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igb: Add device support for flashless SKU of i210 device
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
82bbcdeb
JP		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
9d5c8243 34#include <linux/types.h>
2d064c06 35#include <linux/if_ether.h>
441fc6fd 36#include <linux/i2c.h>
9d5c8243
AK		 37
38#include "e1000_mac.h"
39#include "e1000_82575.h"
f96a8a0b 40#include "e1000_i210.h"
9d5c8243
AK		 41
42static s32 igb_get_invariants_82575(struct e1000_hw *);
43static s32 igb_acquire_phy_82575(struct e1000_hw *);
44static void igb_release_phy_82575(struct e1000_hw *);
45static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46static void igb_release_nvm_82575(struct e1000_hw *);
47static s32 igb_check_for_link_82575(struct e1000_hw *);
48static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49static s32 igb_init_hw_82575(struct e1000_hw *);
50static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 52static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 54static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 55static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243 56static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
da02cde1
CW		 57static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
9d5c8243 59static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 60static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 61static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 64static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
65 u16 *);
66static s32 igb_get_phy_id_82575(struct e1000_hw *);
67static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68static bool igb_sgmii_active_82575(struct e1000_hw *);
69static s32 igb_reset_init_script_82575(struct e1000_hw *);
70static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 71static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
99870a73 72static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
4322e561
CW		 73static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
4322e561
CW		 75static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
bb2ac47b
AD		 77static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
79 35, 70, 140 };
80#define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
82
4085f746
NN		 83/**
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
86 *
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
89 **/
90static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
91{
92 u32 reg = 0;
93 bool ext_mdio = false;
94
95 switch (hw->mac.type) {
96 case e1000_82575:
97 case e1000_82576:
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
100 break;
101 case e1000_82580:
102 case e1000_i350:
ceb5f13b 103 case e1000_i354:
f96a8a0b
CW		 104 case e1000_i210:
105 case e1000_i211:
4085f746
NN		 106 reg = rd32(E1000_MDICNFG);
107 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
108 break;
109 default:
110 break;
111 }
112 return ext_mdio;
113}
114
73bfcd9a
AA		 115/**
116 * igb_init_phy_params_82575 - Init PHY func ptrs.
117 * @hw: pointer to the HW structure
118 **/
119static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
120{
121 struct e1000_phy_info *phy = &hw->phy;
122 s32 ret_val = 0;
123 u32 ctrl_ext;
124
125 if (hw->phy.media_type != e1000_media_type_copper) {
126 phy->type = e1000_phy_none;
127 goto out;
128 }
129
130 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
131 phy->reset_delay_us = 100;
132
133 ctrl_ext = rd32(E1000_CTRL_EXT);
134
135 if (igb_sgmii_active_82575(hw)) {
136 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
137 ctrl_ext |= E1000_CTRL_I2C_ENA;
138 } else {
139 phy->ops.reset = igb_phy_hw_reset;
140 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
141 }
142
143 wr32(E1000_CTRL_EXT, ctrl_ext);
144 igb_reset_mdicnfg_82580(hw);
145
146 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
147 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
148 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
149 } else {
150 switch (hw->mac.type) {
151 case e1000_82580:
152 case e1000_i350:
ceb5f13b 153 case e1000_i354:
73bfcd9a
AA		 154 phy->ops.read_reg = igb_read_phy_reg_82580;
155 phy->ops.write_reg = igb_write_phy_reg_82580;
156 break;
157 case e1000_i210:
158 case e1000_i211:
159 phy->ops.read_reg = igb_read_phy_reg_gs40g;
160 phy->ops.write_reg = igb_write_phy_reg_gs40g;
161 break;
162 default:
163 phy->ops.read_reg = igb_read_phy_reg_igp;
164 phy->ops.write_reg = igb_write_phy_reg_igp;
165 }
166 }
167
168 /* set lan id */
169 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
170 E1000_STATUS_FUNC_SHIFT;
171
172 /* Set phy->phy_addr and phy->id. */
173 ret_val = igb_get_phy_id_82575(hw);
174 if (ret_val)
175 return ret_val;
176
177 /* Verify phy id and set remaining function pointers */
178 switch (phy->id) {
ceb5f13b 179 case M88E1545_E_PHY_ID:
73bfcd9a
AA		 180 case I347AT4_E_PHY_ID:
181 case M88E1112_E_PHY_ID:
182 case M88E1111_I_PHY_ID:
183 phy->type = e1000_phy_m88;
ceb5f13b 184 phy->ops.check_polarity = igb_check_polarity_m88;
73bfcd9a 185 phy->ops.get_phy_info = igb_get_phy_info_m88;
ceb5f13b 186 if (phy->id != M88E1111_I_PHY_ID)
73bfcd9a
AA		 187 phy->ops.get_cable_length =
188 igb_get_cable_length_m88_gen2;
189 else
190 phy->ops.get_cable_length = igb_get_cable_length_m88;
191 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
192 break;
193 case IGP03E1000_E_PHY_ID:
194 phy->type = e1000_phy_igp_3;
195 phy->ops.get_phy_info = igb_get_phy_info_igp;
196 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
197 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
198 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
199 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
200 break;
201 case I82580_I_PHY_ID:
202 case I350_I_PHY_ID:
203 phy->type = e1000_phy_82580;
204 phy->ops.force_speed_duplex =
205 igb_phy_force_speed_duplex_82580;
206 phy->ops.get_cable_length = igb_get_cable_length_82580;
207 phy->ops.get_phy_info = igb_get_phy_info_82580;
208 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
209 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
210 break;
211 case I210_I_PHY_ID:
212 phy->type = e1000_phy_i210;
213 phy->ops.check_polarity = igb_check_polarity_m88;
214 phy->ops.get_phy_info = igb_get_phy_info_m88;
215 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
216 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
217 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
218 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
219 break;
220 default:
221 ret_val = -E1000_ERR_PHY;
222 goto out;
223 }
224
225out:
226 return ret_val;
227}
228
56d8c27f
AA		 229/**
230 * igb_init_nvm_params_82575 - Init NVM func ptrs.
231 * @hw: pointer to the HW structure
232 **/
c8268921 233static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
56d8c27f
AA		 234{
235 struct e1000_nvm_info *nvm = &hw->nvm;
236 u32 eecd = rd32(E1000_EECD);
237 u16 size;
238
239 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
240 E1000_EECD_SIZE_EX_SHIFT);
5a823d8c 241
56d8c27f
AA		 242 /* Added to a constant, "size" becomes the left-shift value
243 * for setting word_size.
244 */
245 size += NVM_WORD_SIZE_BASE_SHIFT;
246
247 /* Just in case size is out of range, cap it to the largest
248 * EEPROM size supported
249 */
250 if (size > 15)
251 size = 15;
252
253 nvm->word_size = 1 << size;
5a823d8c
CW		 254 nvm->opcode_bits = 8;
255 nvm->delay_usec = 1;
56d8c27f 256
5a823d8c
CW		 257 switch (nvm->override) {
258 case e1000_nvm_override_spi_large:
259 nvm->page_size = 32;
260 nvm->address_bits = 16;
261 break;
262 case e1000_nvm_override_spi_small:
263 nvm->page_size = 8;
264 nvm->address_bits = 8;
265 break;
266 default:
267 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
268 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
269 16 : 8;
270 break;
56d8c27f 271 }
5a823d8c
CW		 272 if (nvm->word_size == (1 << 15))
273 nvm->page_size = 128;
274
275 nvm->type = e1000_nvm_eeprom_spi;
56d8c27f
AA		 276
277 /* NVM Function Pointers */
5a823d8c
CW		 278 nvm->ops.acquire = igb_acquire_nvm_82575;
279 nvm->ops.release = igb_release_nvm_82575;
280 nvm->ops.write = igb_write_nvm_spi;
281 nvm->ops.validate = igb_validate_nvm_checksum;
282 nvm->ops.update = igb_update_nvm_checksum;
283 if (nvm->word_size < (1 << 15))
284 nvm->ops.read = igb_read_nvm_eerd;
285 else
286 nvm->ops.read = igb_read_nvm_spi;
287
288 /* override generic family function pointers for specific descendants */
56d8c27f
AA		 289 switch (hw->mac.type) {
290 case e1000_82580:
291 nvm->ops.validate = igb_validate_nvm_checksum_82580;
292 nvm->ops.update = igb_update_nvm_checksum_82580;
56d8c27f 293 break;
ceb5f13b 294 case e1000_i354:
56d8c27f
AA		 295 case e1000_i350:
296 nvm->ops.validate = igb_validate_nvm_checksum_i350;
297 nvm->ops.update = igb_update_nvm_checksum_i350;
56d8c27f
AA		 298 break;
299 default:
56d8c27f
AA		 300 break;
301 }
302
303 return 0;
304}
305
a1bf1f44
AA		 306/**
307 * igb_init_mac_params_82575 - Init MAC func ptrs.
308 * @hw: pointer to the HW structure
309 **/
310static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
311{
312 struct e1000_mac_info *mac = &hw->mac;
313 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
314
315 /* Set mta register count */
316 mac->mta_reg_count = 128;
317 /* Set rar entry count */
318 switch (mac->type) {
319 case e1000_82576:
320 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
321 break;
322 case e1000_82580:
323 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
324 break;
325 case e1000_i350:
ceb5f13b 326 case e1000_i354:
a1bf1f44
AA		 327 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
328 break;
329 default:
330 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
331 break;
332 }
333 /* reset */
334 if (mac->type >= e1000_82580)
335 mac->ops.reset_hw = igb_reset_hw_82580;
336 else
337 mac->ops.reset_hw = igb_reset_hw_82575;
338
339 if (mac->type >= e1000_i210) {
340 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
341 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
342
343 } else {
344 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
345 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
346 }
347
348 /* Set if part includes ASF firmware */
349 mac->asf_firmware_present = true;
350 /* Set if manageability features are enabled. */
351 mac->arc_subsystem_valid =
352 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
353 ? true : false;
354 /* enable EEE on i350 parts and later parts */
355 if (mac->type >= e1000_i350)
356 dev_spec->eee_disable = false;
357 else
358 dev_spec->eee_disable = true;
d44e7a9a
MV		 359 /* Allow a single clear of the SW semaphore on I210 and newer */
360 if (mac->type >= e1000_i210)
361 dev_spec->clear_semaphore_once = true;
a1bf1f44
AA		 362 /* physical interface link setup */
363 mac->ops.setup_physical_interface =
364 (hw->phy.media_type == e1000_media_type_copper)
365 ? igb_setup_copper_link_82575
366 : igb_setup_serdes_link_82575;
367
368 return 0;
369}
370
641ac5c0
AA		 371/**
372 * igb_set_sfp_media_type_82575 - derives SFP module media type.
373 * @hw: pointer to the HW structure
374 *
375 * The media type is chosen based on SFP module.
376 * compatibility flags retrieved from SFP ID EEPROM.
377 **/
378static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
379{
380 s32 ret_val = E1000_ERR_CONFIG;
381 u32 ctrl_ext = 0;
382 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
383 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
384 u8 tranceiver_type = 0;
385 s32 timeout = 3;
386
387 /* Turn I2C interface ON and power on sfp cage */
388 ctrl_ext = rd32(E1000_CTRL_EXT);
389 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
390 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
391
392 wrfl();
393
394 /* Read SFP module data */
395 while (timeout) {
396 ret_val = igb_read_sfp_data_byte(hw,
397 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
398 &tranceiver_type);
399 if (ret_val == 0)
400 break;
401 msleep(100);
402 timeout--;
403 }
404 if (ret_val != 0)
405 goto out;
406
407 ret_val = igb_read_sfp_data_byte(hw,
408 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
409 (u8 *)eth_flags);
410 if (ret_val != 0)
411 goto out;
412
413 /* Check if there is some SFP module plugged and powered */
414 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
415 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
416 dev_spec->module_plugged = true;
417 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
418 hw->phy.media_type = e1000_media_type_internal_serdes;
419 } else if (eth_flags->e100_base_fx) {
420 dev_spec->sgmii_active = true;
421 hw->phy.media_type = e1000_media_type_internal_serdes;
422 } else if (eth_flags->e1000_base_t) {
423 dev_spec->sgmii_active = true;
424 hw->phy.media_type = e1000_media_type_copper;
425 } else {
426 hw->phy.media_type = e1000_media_type_unknown;
427 hw_dbg("PHY module has not been recognized\n");
428 goto out;
429 }
430 } else {
431 hw->phy.media_type = e1000_media_type_unknown;
432 }
433 ret_val = 0;
434out:
435 /* Restore I2C interface setting */
436 wr32(E1000_CTRL_EXT, ctrl_ext);
437 return ret_val;
438}
439
9d5c8243
AK		 440static s32 igb_get_invariants_82575(struct e1000_hw *hw)
441{
9d5c8243 442 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 443 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243 444 s32 ret_val;
9d5c8243 445 u32 ctrl_ext = 0;
641ac5c0 446 u32 link_mode = 0;
9d5c8243
AK		 447
448 switch (hw->device_id) {
449 case E1000_DEV_ID_82575EB_COPPER:
450 case E1000_DEV_ID_82575EB_FIBER_SERDES:
451 case E1000_DEV_ID_82575GB_QUAD_COPPER:
452 mac->type = e1000_82575;
453 break;
2d064c06 454 case E1000_DEV_ID_82576:
9eb2341d 455 case E1000_DEV_ID_82576_NS:
747d49ba 456 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 457 case E1000_DEV_ID_82576_FIBER:
458 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 459 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 460 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 461 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 462 mac->type = e1000_82576;
463 break;
bb2ac47b
AD		 464 case E1000_DEV_ID_82580_COPPER:
465 case E1000_DEV_ID_82580_FIBER:
6493d24f 466 case E1000_DEV_ID_82580_QUAD_FIBER:
bb2ac47b
AD		 467 case E1000_DEV_ID_82580_SERDES:
468 case E1000_DEV_ID_82580_SGMII:
469 case E1000_DEV_ID_82580_COPPER_DUAL:
308fb39a
JG		 470 case E1000_DEV_ID_DH89XXCC_SGMII:
471 case E1000_DEV_ID_DH89XXCC_SERDES:
1b5dda33
GJ		 472 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
473 case E1000_DEV_ID_DH89XXCC_SFP:
bb2ac47b
AD		 474 mac->type = e1000_82580;
475 break;
d2ba2ed8
AD		 476 case E1000_DEV_ID_I350_COPPER:
477 case E1000_DEV_ID_I350_FIBER:
478 case E1000_DEV_ID_I350_SERDES:
479 case E1000_DEV_ID_I350_SGMII:
480 mac->type = e1000_i350;
481 break;
f96a8a0b 482 case E1000_DEV_ID_I210_COPPER:
f96a8a0b
CW		 483 case E1000_DEV_ID_I210_FIBER:
484 case E1000_DEV_ID_I210_SERDES:
485 case E1000_DEV_ID_I210_SGMII:
53b87ce3
CW		 486 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
487 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
f96a8a0b
CW		 488 mac->type = e1000_i210;
489 break;
490 case E1000_DEV_ID_I211_COPPER:
491 mac->type = e1000_i211;
492 break;
ceb5f13b
CW		 493 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
494 case E1000_DEV_ID_I354_SGMII:
495 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
496 mac->type = e1000_i354;
497 break;
9d5c8243
AK		 498 default:
499 return -E1000_ERR_MAC_INIT;
500 break;
501 }
502
9d5c8243 503 /* Set media type */
b980ac18 504 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
9d5c8243
AK		 505 * based on the EEPROM. We cannot rely upon device ID. There
506 * is no distinguishable difference between fiber and internal
507 * SerDes mode on the 82575. There can be an external PHY attached
508 * on the SGMII interface. For this, we'll set sgmii_active to true.
509 */
a6053d76 510 hw->phy.media_type = e1000_media_type_copper;
9d5c8243 511 dev_spec->sgmii_active = false;
641ac5c0 512 dev_spec->module_plugged = false;
9d5c8243
AK		 513
514 ctrl_ext = rd32(E1000_CTRL_EXT);
641ac5c0
AA		 515
516 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
517 switch (link_mode) {
bb2ac47b 518 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26 519 hw->phy.media_type = e1000_media_type_internal_serdes;
641ac5c0
AA		 520 break;
521 case E1000_CTRL_EXT_LINK_MODE_SGMII:
522 /* Get phy control interface type set (MDIO vs. I2C)*/
523 if (igb_sgmii_uses_mdio_82575(hw)) {
524 hw->phy.media_type = e1000_media_type_copper;
525 dev_spec->sgmii_active = true;
526 break;
527 }
528 /* fall through for I2C based SGMII */
529 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
530 /* read media type from SFP EEPROM */
531 ret_val = igb_set_sfp_media_type_82575(hw);
532 if ((ret_val != 0) ||
533 (hw->phy.media_type == e1000_media_type_unknown)) {
534 /* If media type was not identified then return media
535 * type defined by the CTRL_EXT settings.
536 */
537 hw->phy.media_type = e1000_media_type_internal_serdes;
538
539 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
540 hw->phy.media_type = e1000_media_type_copper;
541 dev_spec->sgmii_active = true;
542 }
543
544 break;
545 }
546
547 /* do not change link mode for 100BaseFX */
548 if (dev_spec->eth_flags.e100_base_fx)
549 break;
550
551 /* change current link mode setting */
552 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
553
554 if (hw->phy.media_type == e1000_media_type_copper)
555 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
556 else
557 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
558
559 wr32(E1000_CTRL_EXT, ctrl_ext);
560
2fb02a26
AD		 561 break;
562 default:
2fb02a26 563 break;
9d5c8243 564 }
2fb02a26 565
a6053d76
AA		 566 /* mac initialization and operations */
567 ret_val = igb_init_mac_params_82575(hw);
568 if (ret_val)
569 goto out;
9d5c8243
AK		 570
571 /* NVM initialization */
a6053d76 572 ret_val = igb_init_nvm_params_82575(hw);
5a823d8c
CW		 573 switch (hw->mac.type) {
574 case e1000_i210:
575 case e1000_i211:
576 ret_val = igb_init_nvm_params_i210(hw);
577 break;
578 default:
579 break;
580 }
581
a6053d76
AA		 582 if (ret_val)
583 goto out;
9d5c8243 584
6b78bb1d
CW		 585 /* if part supports SR-IOV then initialize mailbox parameters */
586 switch (mac->type) {
587 case e1000_82576:
588 case e1000_i350:
a0c98605 589 igb_init_mbx_params_pf(hw);
6b78bb1d
CW		 590 break;
591 default:
592 break;
593 }
a0c98605 594
9d5c8243 595 /* setup PHY parameters */
a6053d76 596 ret_val = igb_init_phy_params_82575(hw);
19e588e7 597
a6053d76
AA		 598out:
599 return ret_val;
9d5c8243
AK		 600}
601
602/**
733596be 603 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 604 * @hw: pointer to the HW structure
605 *
606 * Acquire access rights to the correct PHY. This is a
607 * function pointer entry point called by the api module.
608 **/
609static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
610{
008c3422 611 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 612
008c3422
AD		 613 if (hw->bus.func == E1000_FUNC_1)
614 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 615 else if (hw->bus.func == E1000_FUNC_2)
616 mask = E1000_SWFW_PHY2_SM;
617 else if (hw->bus.func == E1000_FUNC_3)
618 mask = E1000_SWFW_PHY3_SM;
9d5c8243 619
f96a8a0b 620 return hw->mac.ops.acquire_swfw_sync(hw, mask);
9d5c8243
AK		 621}
622
623/**
733596be 624 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 625 * @hw: pointer to the HW structure
626 *
627 * A wrapper to release access rights to the correct PHY. This is a
628 * function pointer entry point called by the api module.
629 **/
630static void igb_release_phy_82575(struct e1000_hw *hw)
631{
008c3422
AD		 632 u16 mask = E1000_SWFW_PHY0_SM;
633
634 if (hw->bus.func == E1000_FUNC_1)
635 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 636 else if (hw->bus.func == E1000_FUNC_2)
637 mask = E1000_SWFW_PHY2_SM;
638 else if (hw->bus.func == E1000_FUNC_3)
639 mask = E1000_SWFW_PHY3_SM;
9d5c8243 640
f96a8a0b 641 hw->mac.ops.release_swfw_sync(hw, mask);
9d5c8243
AK		 642}
643
644/**
733596be 645 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 646 * @hw: pointer to the HW structure
647 * @offset: register offset to be read
648 * @data: pointer to the read data
649 *
650 * Reads the PHY register at offset using the serial gigabit media independent
651 * interface and stores the retrieved information in data.
652 **/
653static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
654 u16 *data)
655{
bf6f7a92 656 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 657
658 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 659 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 660 goto out;
9d5c8243
AK		 661 }
662
bf6f7a92
AD		 663 ret_val = hw->phy.ops.acquire(hw);
664 if (ret_val)
665 goto out;
9d5c8243 666
bf6f7a92 667 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 668
bf6f7a92
AD		 669 hw->phy.ops.release(hw);
670
671out:
672 return ret_val;
9d5c8243
AK		 673}
674
675/**
733596be 676 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 677 * @hw: pointer to the HW structure
678 * @offset: register offset to write to
679 * @data: data to write at register offset
680 *
681 * Writes the data to PHY register at the offset using the serial gigabit
682 * media independent interface.
683 **/
684static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
685 u16 data)
686{
bf6f7a92
AD		 687 s32 ret_val = -E1000_ERR_PARAM;
688
9d5c8243
AK		 689
690 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 691 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 692 goto out;
9d5c8243
AK		 693 }
694
bf6f7a92
AD		 695 ret_val = hw->phy.ops.acquire(hw);
696 if (ret_val)
697 goto out;
9d5c8243 698
bf6f7a92 699 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 700
bf6f7a92
AD		 701 hw->phy.ops.release(hw);
702
703out:
704 return ret_val;
9d5c8243
AK		 705}
706
707/**
733596be 708 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 709 * @hw: pointer to the HW structure
710 *
652fff32 711 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 712 * sgmi interface.
713 **/
714static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
715{
716 struct e1000_phy_info *phy = &hw->phy;
717 s32 ret_val = 0;
718 u16 phy_id;
2fb02a26 719 u32 ctrl_ext;
4085f746 720 u32 mdic;
9d5c8243 721
b980ac18 722 /* For SGMII PHYs, we try the list of possible addresses until
9d5c8243
AK		 723 * we find one that works. For non-SGMII PHYs
724 * (e.g. integrated copper PHYs), an address of 1 should
725 * work. The result of this function should mean phy->phy_addr
726 * and phy->id are set correctly.
727 */
728 if (!(igb_sgmii_active_82575(hw))) {
729 phy->addr = 1;
730 ret_val = igb_get_phy_id(hw);
731 goto out;
732 }
733
4085f746
NN		 734 if (igb_sgmii_uses_mdio_82575(hw)) {
735 switch (hw->mac.type) {
736 case e1000_82575:
737 case e1000_82576:
738 mdic = rd32(E1000_MDIC);
739 mdic &= E1000_MDIC_PHY_MASK;
740 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
741 break;
742 case e1000_82580:
743 case e1000_i350:
ceb5f13b 744 case e1000_i354:
f96a8a0b
CW		 745 case e1000_i210:
746 case e1000_i211:
4085f746
NN		 747 mdic = rd32(E1000_MDICNFG);
748 mdic &= E1000_MDICNFG_PHY_MASK;
749 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
750 break;
751 default:
752 ret_val = -E1000_ERR_PHY;
753 goto out;
754 break;
755 }
756 ret_val = igb_get_phy_id(hw);
757 goto out;
758 }
759
2fb02a26
AD		 760 /* Power on sgmii phy if it is disabled */
761 ctrl_ext = rd32(E1000_CTRL_EXT);
762 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
763 wrfl();
764 msleep(300);
765
b980ac18 766 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
9d5c8243
AK		 767 * Therefore, we need to test 1-7
768 */
769 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
770 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
771 if (ret_val == 0) {
652fff32
AK		 772 hw_dbg("Vendor ID 0x%08X read at address %u\n",
773 phy_id, phy->addr);
b980ac18 774 /* At the time of this writing, The M88 part is
9d5c8243
AK		 775 * the only supported SGMII PHY product.
776 */
777 if (phy_id == M88_VENDOR)
778 break;
779 } else {
652fff32 780 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 781 }
782 }
783
784 /* A valid PHY type couldn't be found. */
785 if (phy->addr == 8) {
786 phy->addr = 0;
787 ret_val = -E1000_ERR_PHY;
788 goto out;
2fb02a26
AD		 789 } else {
790 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 791 }
792
2fb02a26
AD		 793 /* restore previous sfp cage power state */
794 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 795
796out:
797 return ret_val;
798}
799
800/**
733596be 801 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 802 * @hw: pointer to the HW structure
803 *
804 * Resets the PHY using the serial gigabit media independent interface.
805 **/
806static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
807{
808 s32 ret_val;
809
b980ac18 810 /* This isn't a true "hard" reset, but is the only reset
9d5c8243
AK		 811 * available to us at this time.
812 */
813
652fff32 814 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243 815
b980ac18 816 /* SFP documentation requires the following to configure the SPF module
9d5c8243
AK		 817 * to work on SGMII. No further documentation is given.
818 */
a8d2a0c2 819 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 820 if (ret_val)
821 goto out;
822
823 ret_val = igb_phy_sw_reset(hw);
824
825out:
826 return ret_val;
827}
828
829/**
733596be 830 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 831 * @hw: pointer to the HW structure
832 * @active: true to enable LPLU, false to disable
833 *
834 * Sets the LPLU D0 state according to the active flag. When
835 * activating LPLU this function also disables smart speed
836 * and vice versa. LPLU will not be activated unless the
837 * device autonegotiation advertisement meets standards of
838 * either 10 or 10/100 or 10/100/1000 at all duplexes.
839 * This is a function pointer entry point only called by
840 * PHY setup routines.
841 **/
842static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
843{
844 struct e1000_phy_info *phy = &hw->phy;
845 s32 ret_val;
846 u16 data;
847
a8d2a0c2 848 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 849 if (ret_val)
850 goto out;
851
852 if (active) {
853 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 854 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 855 data);
9d5c8243
AK		 856 if (ret_val)
857 goto out;
858
859 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 860 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 861 &data);
9d5c8243 862 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 863 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 864 data);
9d5c8243
AK		 865 if (ret_val)
866 goto out;
867 } else {
868 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 869 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 870 data);
b980ac18 871 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
9d5c8243
AK		 872 * during Dx states where the power conservation is most
873 * important. During driver activity we should enable
874 * SmartSpeed, so performance is maintained.
875 */
876 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 877 ret_val = phy->ops.read_reg(hw,
652fff32 878 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 879 if (ret_val)
880 goto out;
881
882 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 883 ret_val = phy->ops.write_reg(hw,
652fff32 884 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 885 if (ret_val)
886 goto out;
887 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 888 ret_val = phy->ops.read_reg(hw,
652fff32 889 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 890 if (ret_val)
891 goto out;
892
893 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 894 ret_val = phy->ops.write_reg(hw,
652fff32 895 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 896 if (ret_val)
897 goto out;
898 }
899 }
900
901out:
902 return ret_val;
903}
904
da02cde1
CW		 905/**
906 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
907 * @hw: pointer to the HW structure
908 * @active: true to enable LPLU, false to disable
909 *
910 * Sets the LPLU D0 state according to the active flag. When
911 * activating LPLU this function also disables smart speed
912 * and vice versa. LPLU will not be activated unless the
913 * device autonegotiation advertisement meets standards of
914 * either 10 or 10/100 or 10/100/1000 at all duplexes.
915 * This is a function pointer entry point only called by
916 * PHY setup routines.
917 **/
918static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
919{
920 struct e1000_phy_info *phy = &hw->phy;
921 s32 ret_val = 0;
922 u16 data;
923
924 data = rd32(E1000_82580_PHY_POWER_MGMT);
925
926 if (active) {
927 data |= E1000_82580_PM_D0_LPLU;
928
929 /* When LPLU is enabled, we should disable SmartSpeed */
930 data &= ~E1000_82580_PM_SPD;
931 } else {
932 data &= ~E1000_82580_PM_D0_LPLU;
933
b980ac18 934 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
da02cde1
CW		 935 * during Dx states where the power conservation is most
936 * important. During driver activity we should enable
937 * SmartSpeed, so performance is maintained.
938 */
939 if (phy->smart_speed == e1000_smart_speed_on)
940 data |= E1000_82580_PM_SPD;
941 else if (phy->smart_speed == e1000_smart_speed_off)
942 data &= ~E1000_82580_PM_SPD; }
943
944 wr32(E1000_82580_PHY_POWER_MGMT, data);
945 return ret_val;
946}
947
948/**
949 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
950 * @hw: pointer to the HW structure
951 * @active: boolean used to enable/disable lplu
952 *
953 * Success returns 0, Failure returns 1
954 *
955 * The low power link up (lplu) state is set to the power management level D3
956 * and SmartSpeed is disabled when active is true, else clear lplu for D3
957 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
958 * is used during Dx states where the power conservation is most important.
959 * During driver activity, SmartSpeed should be enabled so performance is
960 * maintained.
961 **/
c8268921 962static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
da02cde1
CW		 963{
964 struct e1000_phy_info *phy = &hw->phy;
965 s32 ret_val = 0;
966 u16 data;
967
968 data = rd32(E1000_82580_PHY_POWER_MGMT);
969
970 if (!active) {
971 data &= ~E1000_82580_PM_D3_LPLU;
b980ac18 972 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
da02cde1
CW		 973 * during Dx states where the power conservation is most
974 * important. During driver activity we should enable
975 * SmartSpeed, so performance is maintained.
976 */
977 if (phy->smart_speed == e1000_smart_speed_on)
978 data |= E1000_82580_PM_SPD;
979 else if (phy->smart_speed == e1000_smart_speed_off)
980 data &= ~E1000_82580_PM_SPD;
981 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
982 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
983 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
984 data |= E1000_82580_PM_D3_LPLU;
985 /* When LPLU is enabled, we should disable SmartSpeed */
986 data &= ~E1000_82580_PM_SPD;
987 }
988
989 wr32(E1000_82580_PHY_POWER_MGMT, data);
990 return ret_val;
991}
992
9d5c8243 993/**
733596be 994 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 995 * @hw: pointer to the HW structure
996 *
652fff32 997 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 998 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
999 * Return successful if access grant bit set, else clear the request for
1000 * EEPROM access and return -E1000_ERR_NVM (-1).
1001 **/
1002static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1003{
1004 s32 ret_val;
1005
f96a8a0b 1006 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1007 if (ret_val)
1008 goto out;
1009
1010 ret_val = igb_acquire_nvm(hw);
1011
1012 if (ret_val)
f96a8a0b 1013 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1014
1015out:
1016 return ret_val;
1017}
1018
1019/**
733596be 1020 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 1021 * @hw: pointer to the HW structure
1022 *
1023 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1024 * then release the semaphores acquired.
1025 **/
1026static void igb_release_nvm_82575(struct e1000_hw *hw)
1027{
1028 igb_release_nvm(hw);
f96a8a0b 1029 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1030}
1031
1032/**
733596be 1033 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 1034 * @hw: pointer to the HW structure
1035 * @mask: specifies which semaphore to acquire
1036 *
1037 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1038 * will also specify which port we're acquiring the lock for.
1039 **/
1040static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1041{
1042 u32 swfw_sync;
1043 u32 swmask = mask;
1044 u32 fwmask = mask << 16;
1045 s32 ret_val = 0;
1046 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1047
1048 while (i < timeout) {
1049 if (igb_get_hw_semaphore(hw)) {
1050 ret_val = -E1000_ERR_SWFW_SYNC;
1051 goto out;
1052 }
1053
1054 swfw_sync = rd32(E1000_SW_FW_SYNC);
1055 if (!(swfw_sync & (fwmask | swmask)))
1056 break;
1057
b980ac18 1058 /* Firmware currently using resource (fwmask)
9d5c8243
AK		 1059 * or other software thread using resource (swmask)
1060 */
1061 igb_put_hw_semaphore(hw);
1062 mdelay(5);
1063 i++;
1064 }
1065
1066 if (i == timeout) {
652fff32 1067 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 1068 ret_val = -E1000_ERR_SWFW_SYNC;
1069 goto out;
1070 }
1071
1072 swfw_sync |= swmask;
1073 wr32(E1000_SW_FW_SYNC, swfw_sync);
1074
1075 igb_put_hw_semaphore(hw);
1076
1077out:
1078 return ret_val;
1079}
1080
1081/**
733596be 1082 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 1083 * @hw: pointer to the HW structure
1084 * @mask: specifies which semaphore to acquire
1085 *
1086 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1087 * will also specify which port we're releasing the lock for.
1088 **/
1089static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1090{
1091 u32 swfw_sync;
1092
1093 while (igb_get_hw_semaphore(hw) != 0);
1094 /* Empty */
1095
1096 swfw_sync = rd32(E1000_SW_FW_SYNC);
1097 swfw_sync &= ~mask;
1098 wr32(E1000_SW_FW_SYNC, swfw_sync);
1099
1100 igb_put_hw_semaphore(hw);
1101}
1102
1103/**
733596be 1104 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 1105 * @hw: pointer to the HW structure
1106 *
1107 * Read the management control register for the config done bit for
1108 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1109 * to read the config done bit, so an error is *ONLY* logged and returns
1110 * 0. If we were to return with error, EEPROM-less silicon
1111 * would not be able to be reset or change link.
1112 **/
1113static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1114{
1115 s32 timeout = PHY_CFG_TIMEOUT;
1116 s32 ret_val = 0;
1117 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1118
1119 if (hw->bus.func == 1)
1120 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 1121 else if (hw->bus.func == E1000_FUNC_2)
1122 mask = E1000_NVM_CFG_DONE_PORT_2;
1123 else if (hw->bus.func == E1000_FUNC_3)
1124 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 1125
1126 while (timeout) {
1127 if (rd32(E1000_EEMNGCTL) & mask)
1128 break;
1129 msleep(1);
1130 timeout--;
1131 }
1132 if (!timeout)
652fff32 1133 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 1134
1135 /* If EEPROM is not marked present, init the PHY manually */
1136 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1137 (hw->phy.type == e1000_phy_igp_3))
1138 igb_phy_init_script_igp3(hw);
1139
1140 return ret_val;
1141}
1142
1143/**
733596be 1144 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 1145 * @hw: pointer to the HW structure
1146 *
1147 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1148 * use the generic interface for determining link.
1149 **/
1150static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1151{
1152 s32 ret_val;
1153 u16 speed, duplex;
1154
70d92f86 1155 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 1156 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 1157 &duplex);
b980ac18 1158 /* Use this flag to determine if link needs to be checked or
5d0932a5
AD		 1159 * not. If we have link clear the flag so that we do not
1160 * continue to check for link.
1161 */
1162 hw->mac.get_link_status = !hw->mac.serdes_has_link;
daf56e40
CW		 1163
1164 /* Configure Flow Control now that Auto-Neg has completed.
1165 * First, we need to restore the desired flow control
1166 * settings because we may have had to re-autoneg with a
1167 * different link partner.
1168 */
1169 ret_val = igb_config_fc_after_link_up(hw);
1170 if (ret_val)
1171 hw_dbg("Error configuring flow control\n");
5d0932a5 1172 } else {
9d5c8243 1173 ret_val = igb_check_for_copper_link(hw);
5d0932a5 1174 }
9d5c8243
AK		 1175
1176 return ret_val;
1177}
70d92f86 1178
88a268c1
NN		 1179/**
1180 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1181 * @hw: pointer to the HW structure
1182 **/
1183void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1184{
1185 u32 reg;
1186
1187
1188 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1189 !igb_sgmii_active_82575(hw))
1190 return;
1191
1192 /* Enable PCS to turn on link */
1193 reg = rd32(E1000_PCS_CFG0);
1194 reg |= E1000_PCS_CFG_PCS_EN;
1195 wr32(E1000_PCS_CFG0, reg);
1196
1197 /* Power up the laser */
1198 reg = rd32(E1000_CTRL_EXT);
1199 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1200 wr32(E1000_CTRL_EXT, reg);
1201
1202 /* flush the write to verify completion */
1203 wrfl();
1204 msleep(1);
1205}
1206
9d5c8243 1207/**
733596be 1208 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 1209 * @hw: pointer to the HW structure
1210 * @speed: stores the current speed
1211 * @duplex: stores the current duplex
1212 *
652fff32 1213 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 1214 * duplex, then store the values in the pointers provided.
1215 **/
1216static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1217 u16 *duplex)
1218{
1219 struct e1000_mac_info *mac = &hw->mac;
1220 u32 pcs;
1221
1222 /* Set up defaults for the return values of this function */
1223 mac->serdes_has_link = false;
1224 *speed = 0;
1225 *duplex = 0;
1226
b980ac18 1227 /* Read the PCS Status register for link state. For non-copper mode,
9d5c8243
AK		 1228 * the status register is not accurate. The PCS status register is
1229 * used instead.
1230 */
1231 pcs = rd32(E1000_PCS_LSTAT);
1232
b980ac18 1233 /* The link up bit determines when link is up on autoneg. The sync ok
9d5c8243
AK		 1234 * gets set once both sides sync up and agree upon link. Stable link
1235 * can be determined by checking for both link up and link sync ok
1236 */
1237 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1238 mac->serdes_has_link = true;
1239
1240 /* Detect and store PCS speed */
1241 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1242 *speed = SPEED_1000;
1243 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1244 *speed = SPEED_100;
1245 } else {
1246 *speed = SPEED_10;
1247 }
1248
1249 /* Detect and store PCS duplex */
1250 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1251 *duplex = FULL_DUPLEX;
1252 } else {
1253 *duplex = HALF_DUPLEX;
1254 }
1255 }
1256
1257 return 0;
1258}
1259
2d064c06 1260/**
2fb02a26 1261 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 1262 * @hw: pointer to the HW structure
9d5c8243 1263 *
2d064c06
AD		 1264 * In the case of fiber serdes, shut down optics and PCS on driver unload
1265 * when management pass thru is not enabled.
9d5c8243 1266 **/
2fb02a26 1267void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1268{
2d064c06
AD		 1269 u32 reg;
1270
53c992fa 1271 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 1272 igb_sgmii_active_82575(hw))
2d064c06
AD		 1273 return;
1274
53c992fa 1275 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 1276 /* Disable PCS to turn off link */
1277 reg = rd32(E1000_PCS_CFG0);
1278 reg &= ~E1000_PCS_CFG_PCS_EN;
1279 wr32(E1000_PCS_CFG0, reg);
1280
1281 /* shutdown the laser */
1282 reg = rd32(E1000_CTRL_EXT);
2fb02a26 1283 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 1284 wr32(E1000_CTRL_EXT, reg);
1285
1286 /* flush the write to verify completion */
1287 wrfl();
1288 msleep(1);
1289 }
9d5c8243
AK		 1290}
1291
1292/**
733596be 1293 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 1294 * @hw: pointer to the HW structure
1295 *
1296 * This resets the hardware into a known state. This is a
1297 * function pointer entry point called by the api module.
1298 **/
1299static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1300{
e5c3370f 1301 u32 ctrl;
9d5c8243
AK		 1302 s32 ret_val;
1303
b980ac18 1304 /* Prevent the PCI-E bus from sticking if there is no TLP connection
9d5c8243
AK		 1305 * on the last TLP read/write transaction when MAC is reset.
1306 */
1307 ret_val = igb_disable_pcie_master(hw);
1308 if (ret_val)
652fff32 1309 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 1310
009bc06e
AD		 1311 /* set the completion timeout for interface */
1312 ret_val = igb_set_pcie_completion_timeout(hw);
1313 if (ret_val) {
1314 hw_dbg("PCI-E Set completion timeout has failed.\n");
1315 }
1316
652fff32 1317 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 1318 wr32(E1000_IMC, 0xffffffff);
1319
1320 wr32(E1000_RCTL, 0);
1321 wr32(E1000_TCTL, E1000_TCTL_PSP);
1322 wrfl();
1323
1324 msleep(10);
1325
1326 ctrl = rd32(E1000_CTRL);
1327
652fff32 1328 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 1329 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1330
1331 ret_val = igb_get_auto_rd_done(hw);
1332 if (ret_val) {
b980ac18 1333 /* When auto config read does not complete, do not
9d5c8243
AK		 1334 * return with an error. This can happen in situations
1335 * where there is no eeprom and prevents getting link.
1336 */
652fff32 1337 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 1338 }
1339
1340 /* If EEPROM is not present, run manual init scripts */
1341 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1342 igb_reset_init_script_82575(hw);
1343
1344 /* Clear any pending interrupt events. */
1345 wr32(E1000_IMC, 0xffffffff);
e5c3370f 1346 rd32(E1000_ICR);
9d5c8243 1347
5ac16659
AD		 1348 /* Install any alternate MAC address into RAR0 */
1349 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 1350
1351 return ret_val;
1352}
1353
1354/**
733596be 1355 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 1356 * @hw: pointer to the HW structure
1357 *
1358 * This inits the hardware readying it for operation.
1359 **/
1360static s32 igb_init_hw_82575(struct e1000_hw *hw)
1361{
1362 struct e1000_mac_info *mac = &hw->mac;
1363 s32 ret_val;
1364 u16 i, rar_count = mac->rar_entry_count;
1365
1366 /* Initialize identification LED */
1367 ret_val = igb_id_led_init(hw);
1368 if (ret_val) {
652fff32 1369 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 1370 /* This is not fatal and we should not stop init due to this */
1371 }
1372
1373 /* Disabling VLAN filtering */
652fff32 1374 hw_dbg("Initializing the IEEE VLAN\n");
ceb5f13b 1375 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1128c756
CW		 1376 igb_clear_vfta_i350(hw);
1377 else
1378 igb_clear_vfta(hw);
9d5c8243
AK		 1379
1380 /* Setup the receive address */
5ac16659
AD		 1381 igb_init_rx_addrs(hw, rar_count);
1382
9d5c8243 1383 /* Zero out the Multicast HASH table */
652fff32 1384 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1385 for (i = 0; i < mac->mta_reg_count; i++)
1386 array_wr32(E1000_MTA, i, 0);
1387
68d480c4
AD		 1388 /* Zero out the Unicast HASH table */
1389 hw_dbg("Zeroing the UTA\n");
1390 for (i = 0; i < mac->uta_reg_count; i++)
1391 array_wr32(E1000_UTA, i, 0);
1392
9d5c8243
AK		 1393 /* Setup link and flow control */
1394 ret_val = igb_setup_link(hw);
1395
b980ac18 1396 /* Clear all of the statistics registers (clear on read). It is
9d5c8243
AK		 1397 * important that we do this after we have tried to establish link
1398 * because the symbol error count will increment wildly if there
1399 * is no link.
1400 */
1401 igb_clear_hw_cntrs_82575(hw);
9d5c8243
AK		 1402 return ret_val;
1403}
1404
1405/**
733596be 1406 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1407 * @hw: pointer to the HW structure
1408 *
1409 * Configures the link for auto-neg or forced speed and duplex. Then we check
1410 * for link, once link is established calls to configure collision distance
1411 * and flow control are called.
1412 **/
1413static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1414{
12645a19 1415 u32 ctrl;
9d5c8243 1416 s32 ret_val;
867eb39e 1417 u32 phpm_reg;
9d5c8243
AK		 1418
1419 ctrl = rd32(E1000_CTRL);
1420 ctrl |= E1000_CTRL_SLU;
1421 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1422 wr32(E1000_CTRL, ctrl);
1423
867eb39e
CW		 1424 /* Clear Go Link Disconnect bit */
1425 if (hw->mac.type >= e1000_82580) {
1426 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1427 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1428 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1429 }
1430
2fb02a26
AD		 1431 ret_val = igb_setup_serdes_link_82575(hw);
1432 if (ret_val)
1433 goto out;
1434
1435 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1436 /* allow time for SFP cage time to power up phy */
1437 msleep(300);
1438
2fb02a26
AD		 1439 ret_val = hw->phy.ops.reset(hw);
1440 if (ret_val) {
1441 hw_dbg("Error resetting the PHY.\n");
1442 goto out;
1443 }
1444 }
9d5c8243 1445 switch (hw->phy.type) {
f96a8a0b 1446 case e1000_phy_i210:
9d5c8243 1447 case e1000_phy_m88:
ed65bdd8
CW		 1448 switch (hw->phy.id) {
1449 case I347AT4_E_PHY_ID:
1450 case M88E1112_E_PHY_ID:
ceb5f13b 1451 case M88E1545_E_PHY_ID:
ed65bdd8 1452 case I210_I_PHY_ID:
308fb39a 1453 ret_val = igb_copper_link_setup_m88_gen2(hw);
ed65bdd8
CW		 1454 break;
1455 default:
308fb39a 1456 ret_val = igb_copper_link_setup_m88(hw);
ed65bdd8
CW		 1457 break;
1458 }
9d5c8243
AK		 1459 break;
1460 case e1000_phy_igp_3:
1461 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1462 break;
bb2ac47b
AD		 1463 case e1000_phy_82580:
1464 ret_val = igb_copper_link_setup_82580(hw);
1465 break;
9d5c8243
AK		 1466 default:
1467 ret_val = -E1000_ERR_PHY;
1468 break;
1469 }
1470
1471 if (ret_val)
1472 goto out;
1473
81fadd81 1474 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1475out:
1476 return ret_val;
1477}
1478
1479/**
70d92f86 1480 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1481 * @hw: pointer to the HW structure
1482 *
70d92f86
AD		 1483 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1484 * used on copper connections where the serialized gigabit media independent
1485 * interface (sgmii), or serdes fiber is being used. Configures the link
1486 * for auto-negotiation or forces speed/duplex.
9d5c8243 1487 **/
2fb02a26 1488static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1489{
daf56e40 1490 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
bb2ac47b 1491 bool pcs_autoneg;
2c670b5b
CW		 1492 s32 ret_val = E1000_SUCCESS;
1493 u16 data;
2fb02a26
AD		 1494
1495 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1496 !igb_sgmii_active_82575(hw))
2c670b5b
CW		 1497 return ret_val;
1498
9d5c8243 1499
b980ac18 1500 /* On the 82575, SerDes loopback mode persists until it is
9d5c8243
AK		 1501 * explicitly turned off or a power cycle is performed. A read to
1502 * the register does not indicate its status. Therefore, we ensure
1503 * loopback mode is disabled during initialization.
1504 */
1505 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1506
e00bf607 1507 /* power on the sfp cage if present and turn on I2C */
bb2ac47b
AD		 1508 ctrl_ext = rd32(E1000_CTRL_EXT);
1509 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
e00bf607 1510 ctrl_ext |= E1000_CTRL_I2C_ENA;
bb2ac47b 1511 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1512
1513 ctrl_reg = rd32(E1000_CTRL);
1514 ctrl_reg |= E1000_CTRL_SLU;
1515
1516 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1517 /* set both sw defined pins */
1518 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1519
1520 /* Set switch control to serdes energy detect */
1521 reg = rd32(E1000_CONNSW);
1522 reg |= E1000_CONNSW_ENRGSRC;
1523 wr32(E1000_CONNSW, reg);
1524 }
1525
1526 reg = rd32(E1000_PCS_LCTL);
1527
bb2ac47b
AD		 1528 /* default pcs_autoneg to the same setting as mac autoneg */
1529 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1530
bb2ac47b
AD		 1531 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1532 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1533 /* sgmii mode lets the phy handle forcing speed/duplex */
1534 pcs_autoneg = true;
1535 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1536 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1537 break;
1538 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1539 /* disable PCS autoneg and support parallel detect only */
1540 pcs_autoneg = false;
1541 default:
2c670b5b
CW		 1542 if (hw->mac.type == e1000_82575 ||
1543 hw->mac.type == e1000_82576) {
1544 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1545 if (ret_val) {
1546 printk(KERN_DEBUG "NVM Read Error\n\n");
1547 return ret_val;
1548 }
1549
1550 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1551 pcs_autoneg = false;
1552 }
1553
b980ac18 1554 /* non-SGMII modes only supports a speed of 1000/Full for the
bb2ac47b
AD		 1555 * link so it is best to just force the MAC and let the pcs
1556 * link either autoneg or be forced to 1000/Full
1557 */
2fb02a26
AD		 1558 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1559 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1560
1561 /* set speed of 1000/Full if speed/duplex is forced */
1562 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1563 break;
921aa749
AD		 1564 }
1565
2fb02a26 1566 wr32(E1000_CTRL, ctrl_reg);
9d5c8243 1567
b980ac18 1568 /* New SerDes mode allows for forcing speed or autonegotiating speed
9d5c8243
AK		 1569 * at 1gb. Autoneg should be default set by most drivers. This is the
1570 * mode that will be compatible with older link partners and switches.
1571 * However, both are supported by the hardware and some drivers/tools.
1572 */
9d5c8243
AK		 1573 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1574 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1575
bb2ac47b 1576 if (pcs_autoneg) {
9d5c8243 1577 /* Set PCS register for autoneg */
bb2ac47b 1578 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1579 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
daf56e40
CW		 1580
1581 /* Disable force flow control for autoneg */
1582 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1583
1584 /* Configure flow control advertisement for autoneg */
1585 anadv_reg = rd32(E1000_PCS_ANADV);
1586 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1587 switch (hw->fc.requested_mode) {
1588 case e1000_fc_full:
1589 case e1000_fc_rx_pause:
1590 anadv_reg |= E1000_TXCW_ASM_DIR;
1591 anadv_reg |= E1000_TXCW_PAUSE;
1592 break;
1593 case e1000_fc_tx_pause:
1594 anadv_reg |= E1000_TXCW_ASM_DIR;
1595 break;
1596 default:
1597 break;
1598 }
1599 wr32(E1000_PCS_ANADV, anadv_reg);
1600
bb2ac47b 1601 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1602 } else {
bb2ac47b 1603 /* Set PCS register for forced link */
d68caec6 1604 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b 1605
daf56e40
CW		 1606 /* Force flow control for forced link */
1607 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1608
bb2ac47b 1609 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1610 }
726c09e7 1611
9d5c8243
AK		 1612 wr32(E1000_PCS_LCTL, reg);
1613
daf56e40 1614 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
2fb02a26 1615 igb_force_mac_fc(hw);
9d5c8243 1616
2c670b5b 1617 return ret_val;
9d5c8243
AK		 1618}
1619
1620/**
733596be 1621 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1622 * @hw: pointer to the HW structure
1623 *
1624 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1625 * which can be enabled for use in the embedded applications. Simply
1626 * return the current state of the sgmii interface.
1627 **/
1628static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1629{
c1889bfe 1630 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1631 return dev_spec->sgmii_active;
9d5c8243
AK		 1632}
1633
1634/**
733596be 1635 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1636 * @hw: pointer to the HW structure
1637 *
1638 * Inits recommended HW defaults after a reset when there is no EEPROM
1639 * detected. This is only for the 82575.
1640 **/
1641static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1642{
1643 if (hw->mac.type == e1000_82575) {
652fff32 1644 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1645 /* SerDes configuration via SERDESCTRL */
1646 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1647 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1648 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1649 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1650
1651 /* CCM configuration via CCMCTL register */
1652 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1653 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1654
1655 /* PCIe lanes configuration */
1656 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1657 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1658 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1659 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1660
1661 /* PCIe PLL Configuration */
1662 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1663 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1664 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1665 }
1666
1667 return 0;
1668}
1669
1670/**
733596be 1671 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1672 * @hw: pointer to the HW structure
1673 **/
1674static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1675{
1676 s32 ret_val = 0;
1677
b980ac18 1678 /* If there's an alternate MAC address place it in RAR0
22896639
AD		 1679 * so that it will override the Si installed default perm
1680 * address.
1681 */
1682 ret_val = igb_check_alt_mac_addr(hw);
1683 if (ret_val)
1684 goto out;
1685
1686 ret_val = igb_read_mac_addr(hw);
9d5c8243 1687
22896639 1688out:
9d5c8243
AK		 1689 return ret_val;
1690}
1691
88a268c1
NN		 1692/**
1693 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1694 * @hw: pointer to the HW structure
1695 *
1696 * In the case of a PHY power down to save power, or to turn off link during a
1697 * driver unload, or wake on lan is not enabled, remove the link.
1698 **/
1699void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1700{
1701 /* If the management interface is not enabled, then power down */
1702 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1703 igb_power_down_phy_copper(hw);
88a268c1
NN		 1704}
1705
9d5c8243 1706/**
733596be 1707 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1708 * @hw: pointer to the HW structure
1709 *
1710 * Clears the hardware counters by reading the counter registers.
1711 **/
1712static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1713{
9d5c8243
AK		 1714 igb_clear_hw_cntrs_base(hw);
1715
cc9073bb
AD		 1716 rd32(E1000_PRC64);
1717 rd32(E1000_PRC127);
1718 rd32(E1000_PRC255);
1719 rd32(E1000_PRC511);
1720 rd32(E1000_PRC1023);
1721 rd32(E1000_PRC1522);
1722 rd32(E1000_PTC64);
1723 rd32(E1000_PTC127);
1724 rd32(E1000_PTC255);
1725 rd32(E1000_PTC511);
1726 rd32(E1000_PTC1023);
1727 rd32(E1000_PTC1522);
1728
1729 rd32(E1000_ALGNERRC);
1730 rd32(E1000_RXERRC);
1731 rd32(E1000_TNCRS);
1732 rd32(E1000_CEXTERR);
1733 rd32(E1000_TSCTC);
1734 rd32(E1000_TSCTFC);
1735
1736 rd32(E1000_MGTPRC);
1737 rd32(E1000_MGTPDC);
1738 rd32(E1000_MGTPTC);
1739
1740 rd32(E1000_IAC);
1741 rd32(E1000_ICRXOC);
1742
1743 rd32(E1000_ICRXPTC);
1744 rd32(E1000_ICRXATC);
1745 rd32(E1000_ICTXPTC);
1746 rd32(E1000_ICTXATC);
1747 rd32(E1000_ICTXQEC);
1748 rd32(E1000_ICTXQMTC);
1749 rd32(E1000_ICRXDMTC);
1750
1751 rd32(E1000_CBTMPC);
1752 rd32(E1000_HTDPMC);
1753 rd32(E1000_CBRMPC);
1754 rd32(E1000_RPTHC);
1755 rd32(E1000_HGPTC);
1756 rd32(E1000_HTCBDPC);
1757 rd32(E1000_HGORCL);
1758 rd32(E1000_HGORCH);
1759 rd32(E1000_HGOTCL);
1760 rd32(E1000_HGOTCH);
1761 rd32(E1000_LENERRS);
9d5c8243
AK		 1762
1763 /* This register should not be read in copper configurations */
2fb02a26
AD		 1764 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1765 igb_sgmii_active_82575(hw))
cc9073bb 1766 rd32(E1000_SCVPC);
9d5c8243
AK		 1767}
1768
662d7205
AD		 1769/**
1770 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1771 * @hw: pointer to the HW structure
1772 *
1773 * After rx enable if managability is enabled then there is likely some
1774 * bad data at the start of the fifo and possibly in the DMA fifo. This
1775 * function clears the fifos and flushes any packets that came in as rx was
1776 * being enabled.
1777 **/
1778void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1779{
1780 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1781 int i, ms_wait;
1782
1783 if (hw->mac.type != e1000_82575 ||
1784 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1785 return;
1786
1787 /* Disable all RX queues */
1788 for (i = 0; i < 4; i++) {
1789 rxdctl[i] = rd32(E1000_RXDCTL(i));
1790 wr32(E1000_RXDCTL(i),
1791 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1792 }
1793 /* Poll all queues to verify they have shut down */
1794 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1795 msleep(1);
1796 rx_enabled = 0;
1797 for (i = 0; i < 4; i++)
1798 rx_enabled |= rd32(E1000_RXDCTL(i));
1799 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1800 break;
1801 }
1802
1803 if (ms_wait == 10)
1804 hw_dbg("Queue disable timed out after 10ms\n");
1805
1806 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1807 * incoming packets are rejected. Set enable and wait 2ms so that
1808 * any packet that was coming in as RCTL.EN was set is flushed
1809 */
1810 rfctl = rd32(E1000_RFCTL);
1811 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1812
1813 rlpml = rd32(E1000_RLPML);
1814 wr32(E1000_RLPML, 0);
1815
1816 rctl = rd32(E1000_RCTL);
1817 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1818 temp_rctl |= E1000_RCTL_LPE;
1819
1820 wr32(E1000_RCTL, temp_rctl);
1821 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1822 wrfl();
1823 msleep(2);
1824
1825 /* Enable RX queues that were previously enabled and restore our
1826 * previous state
1827 */
1828 for (i = 0; i < 4; i++)
1829 wr32(E1000_RXDCTL(i), rxdctl[i]);
1830 wr32(E1000_RCTL, rctl);
1831 wrfl();
1832
1833 wr32(E1000_RLPML, rlpml);
1834 wr32(E1000_RFCTL, rfctl);
1835
1836 /* Flush receive errors generated by workaround */
1837 rd32(E1000_ROC);
1838 rd32(E1000_RNBC);
1839 rd32(E1000_MPC);
1840}
1841
009bc06e
AD		 1842/**
1843 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1844 * @hw: pointer to the HW structure
1845 *
1846 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1847 * however the hardware default for these parts is 500us to 1ms which is less
1848 * than the 10ms recommended by the pci-e spec. To address this we need to
1849 * increase the value to either 10ms to 200ms for capability version 1 config,
1850 * or 16ms to 55ms for version 2.
1851 **/
1852static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1853{
1854 u32 gcr = rd32(E1000_GCR);
1855 s32 ret_val = 0;
1856 u16 pcie_devctl2;
1857
1858 /* only take action if timeout value is defaulted to 0 */
1859 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1860 goto out;
1861
b980ac18 1862 /* if capabilities version is type 1 we can write the
009bc06e
AD		 1863 * timeout of 10ms to 200ms through the GCR register
1864 */
1865 if (!(gcr & E1000_GCR_CAP_VER2)) {
1866 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1867 goto out;
1868 }
1869
b980ac18 1870 /* for version 2 capabilities we need to write the config space
009bc06e
AD		 1871 * directly in order to set the completion timeout value for
1872 * 16ms to 55ms
1873 */
1874 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1875 &pcie_devctl2);
1876 if (ret_val)
1877 goto out;
1878
1879 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1880
1881 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1882 &pcie_devctl2);
1883out:
1884 /* disable completion timeout resend */
1885 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1886
1887 wr32(E1000_GCR, gcr);
1888 return ret_val;
1889}
1890
13800469
GR		 1891/**
1892 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1893 * @hw: pointer to the hardware struct
1894 * @enable: state to enter, either enabled or disabled
1895 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1896 *
1897 * enables/disables L2 switch anti-spoofing functionality.
1898 **/
1899void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1900{
22c12752 1901 u32 reg_val, reg_offset;
13800469
GR		 1902
1903 switch (hw->mac.type) {
1904 case e1000_82576:
22c12752
LL		 1905 reg_offset = E1000_DTXSWC;
1906 break;
13800469 1907 case e1000_i350:
ceb5f13b 1908 case e1000_i354:
22c12752 1909 reg_offset = E1000_TXSWC;
13800469
GR		 1910 break;
1911 default:
22c12752
LL		 1912 return;
1913 }
1914
1915 reg_val = rd32(reg_offset);
1916 if (enable) {
1917 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1918 E1000_DTXSWC_VLAN_SPOOF_MASK);
1919 /* The PF can spoof - it has to in order to
1920 * support emulation mode NICs
1921 */
1922 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1923 } else {
1924 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1925 E1000_DTXSWC_VLAN_SPOOF_MASK);
13800469 1926 }
22c12752 1927 wr32(reg_offset, reg_val);
13800469
GR		 1928}
1929
4ae196df
AD		 1930/**
1931 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1932 * @hw: pointer to the hardware struct
1933 * @enable: state to enter, either enabled or disabled
1934 *
1935 * enables/disables L2 switch loopback functionality.
1936 **/
1937void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1938{
ca2e3e7e
AA		 1939 u32 dtxswc;
1940
1941 switch (hw->mac.type) {
1942 case e1000_82576:
1943 dtxswc = rd32(E1000_DTXSWC);
1944 if (enable)
1945 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1946 else
1947 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1948 wr32(E1000_DTXSWC, dtxswc);
1949 break;
ceb5f13b 1950 case e1000_i354:
ca2e3e7e
AA		 1951 case e1000_i350:
1952 dtxswc = rd32(E1000_TXSWC);
1953 if (enable)
1954 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1955 else
1956 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1957 wr32(E1000_TXSWC, dtxswc);
1958 break;
1959 default:
1960 /* Currently no other hardware supports loopback */
1961 break;
1962 }
4ae196df 1963
4ae196df
AD		 1964}
1965
1966/**
1967 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1968 * @hw: pointer to the hardware struct
1969 * @enable: state to enter, either enabled or disabled
1970 *
1971 * enables/disables replication of packets across multiple pools.
1972 **/
1973void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1974{
1975 u32 vt_ctl = rd32(E1000_VT_CTL);
1976
1977 if (enable)
1978 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1979 else
1980 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1981
1982 wr32(E1000_VT_CTL, vt_ctl);
1983}
1984
bb2ac47b
AD		 1985/**
1986 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1987 * @hw: pointer to the HW structure
1988 * @offset: register offset to be read
1989 * @data: pointer to the read data
1990 *
1991 * Reads the MDI control register in the PHY at offset and stores the
1992 * information read to data.
1993 **/
1994static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1995{
bb2ac47b
AD		 1996 s32 ret_val;
1997
bb2ac47b
AD		 1998 ret_val = hw->phy.ops.acquire(hw);
1999 if (ret_val)
2000 goto out;
2001
bb2ac47b
AD		 2002 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2003
2004 hw->phy.ops.release(hw);
2005
2006out:
2007 return ret_val;
2008}
2009
2010/**
2011 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2012 * @hw: pointer to the HW structure
2013 * @offset: register offset to write to
2014 * @data: data to write to register at offset
2015 *
2016 * Writes data to MDI control register in the PHY at offset.
2017 **/
2018static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2019{
bb2ac47b
AD		 2020 s32 ret_val;
2021
2022
2023 ret_val = hw->phy.ops.acquire(hw);
2024 if (ret_val)
2025 goto out;
2026
bb2ac47b
AD		 2027 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2028
2029 hw->phy.ops.release(hw);
2030
2031out:
2032 return ret_val;
2033}
2034
08451e25
NN		 2035/**
2036 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2037 * @hw: pointer to the HW structure
2038 *
2039 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2040 * the values found in the EEPROM. This addresses an issue in which these
2041 * bits are not restored from EEPROM after reset.
2042 **/
2043static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2044{
2045 s32 ret_val = 0;
2046 u32 mdicnfg;
1b5dda33 2047 u16 nvm_data = 0;
08451e25
NN		 2048
2049 if (hw->mac.type != e1000_82580)
2050 goto out;
2051 if (!igb_sgmii_active_82575(hw))
2052 goto out;
2053
2054 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2055 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2056 &nvm_data);
2057 if (ret_val) {
2058 hw_dbg("NVM Read Error\n");
2059 goto out;
2060 }
2061
2062 mdicnfg = rd32(E1000_MDICNFG);
2063 if (nvm_data & NVM_WORD24_EXT_MDIO)
2064 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2065 if (nvm_data & NVM_WORD24_COM_MDIO)
2066 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2067 wr32(E1000_MDICNFG, mdicnfg);
2068out:
2069 return ret_val;
2070}
2071
bb2ac47b
AD		 2072/**
2073 * igb_reset_hw_82580 - Reset hardware
2074 * @hw: pointer to the HW structure
2075 *
2076 * This resets function or entire device (all ports, etc.)
2077 * to a known state.
2078 **/
2079static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2080{
2081 s32 ret_val = 0;
2082 /* BH SW mailbox bit in SW_FW_SYNC */
2083 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
e5c3370f 2084 u32 ctrl;
bb2ac47b
AD		 2085 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2086
bb2ac47b
AD		 2087 hw->dev_spec._82575.global_device_reset = false;
2088
a0483e2e
CW		 2089 /* due to hw errata, global device reset doesn't always
2090 * work on 82580
2091 */
2092 if (hw->mac.type == e1000_82580)
2093 global_device_reset = false;
2094
bb2ac47b
AD		 2095 /* Get current control state. */
2096 ctrl = rd32(E1000_CTRL);
2097
b980ac18 2098 /* Prevent the PCI-E bus from sticking if there is no TLP connection
bb2ac47b
AD		 2099 * on the last TLP read/write transaction when MAC is reset.
2100 */
2101 ret_val = igb_disable_pcie_master(hw);
2102 if (ret_val)
2103 hw_dbg("PCI-E Master disable polling has failed.\n");
2104
2105 hw_dbg("Masking off all interrupts\n");
2106 wr32(E1000_IMC, 0xffffffff);
2107 wr32(E1000_RCTL, 0);
2108 wr32(E1000_TCTL, E1000_TCTL_PSP);
2109 wrfl();
2110
2111 msleep(10);
2112
2113 /* Determine whether or not a global dev reset is requested */
2114 if (global_device_reset &&
f96a8a0b 2115 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
bb2ac47b
AD		 2116 global_device_reset = false;
2117
2118 if (global_device_reset &&
2119 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2120 ctrl |= E1000_CTRL_DEV_RST;
2121 else
2122 ctrl |= E1000_CTRL_RST;
2123
2124 wr32(E1000_CTRL, ctrl);
064b4330 2125 wrfl();
bb2ac47b
AD		 2126
2127 /* Add delay to insure DEV_RST has time to complete */
2128 if (global_device_reset)
2129 msleep(5);
2130
2131 ret_val = igb_get_auto_rd_done(hw);
2132 if (ret_val) {
b980ac18 2133 /* When auto config read does not complete, do not
bb2ac47b
AD		 2134 * return with an error. This can happen in situations
2135 * where there is no eeprom and prevents getting link.
2136 */
2137 hw_dbg("Auto Read Done did not complete\n");
2138 }
2139
bb2ac47b
AD		 2140 /* clear global device reset status bit */
2141 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2142
2143 /* Clear any pending interrupt events. */
2144 wr32(E1000_IMC, 0xffffffff);
e5c3370f 2145 rd32(E1000_ICR);
bb2ac47b 2146
08451e25
NN		 2147 ret_val = igb_reset_mdicnfg_82580(hw);
2148 if (ret_val)
2149 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2150
bb2ac47b
AD		 2151 /* Install any alternate MAC address into RAR0 */
2152 ret_val = igb_check_alt_mac_addr(hw);
2153
2154 /* Release semaphore */
2155 if (global_device_reset)
f96a8a0b 2156 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
bb2ac47b
AD		 2157
2158 return ret_val;
2159}
2160
2161/**
2162 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2163 * @data: data received by reading RXPBS register
2164 *
2165 * The 82580 uses a table based approach for packet buffer allocation sizes.
2166 * This function converts the retrieved value into the correct table value
2167 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2168 * 0x0 36 72 144 1 2 4 8 16
2169 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2170 */
2171u16 igb_rxpbs_adjust_82580(u32 data)
2172{
2173 u16 ret_val = 0;
2174
2175 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2176 ret_val = e1000_82580_rxpbs_table[data];
2177
2178 return ret_val;
2179}
2180
4322e561
CW		 2181/**
2182 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2183 * checksum
2184 * @hw: pointer to the HW structure
2185 * @offset: offset in words of the checksum protected region
2186 *
2187 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2188 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2189 **/
bed45a6e
ET		 2190static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2191 u16 offset)
4322e561
CW		 2192{
2193 s32 ret_val = 0;
2194 u16 checksum = 0;
2195 u16 i, nvm_data;
2196
2197 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2198 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2199 if (ret_val) {
2200 hw_dbg("NVM Read Error\n");
2201 goto out;
2202 }
2203 checksum += nvm_data;
2204 }
2205
2206 if (checksum != (u16) NVM_SUM) {
2207 hw_dbg("NVM Checksum Invalid\n");
2208 ret_val = -E1000_ERR_NVM;
2209 goto out;
2210 }
2211
2212out:
2213 return ret_val;
2214}
2215
2216/**
2217 * igb_update_nvm_checksum_with_offset - Update EEPROM
2218 * checksum
2219 * @hw: pointer to the HW structure
2220 * @offset: offset in words of the checksum protected region
2221 *
2222 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2223 * up to the checksum. Then calculates the EEPROM checksum and writes the
2224 * value to the EEPROM.
2225 **/
bed45a6e 2226static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
4322e561
CW		 2227{
2228 s32 ret_val;
2229 u16 checksum = 0;
2230 u16 i, nvm_data;
2231
2232 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2233 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2234 if (ret_val) {
2235 hw_dbg("NVM Read Error while updating checksum.\n");
2236 goto out;
2237 }
2238 checksum += nvm_data;
2239 }
2240 checksum = (u16) NVM_SUM - checksum;
2241 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2242 &checksum);
2243 if (ret_val)
2244 hw_dbg("NVM Write Error while updating checksum.\n");
2245
2246out:
2247 return ret_val;
2248}
2249
2250/**
2251 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2252 * @hw: pointer to the HW structure
2253 *
2254 * Calculates the EEPROM section checksum by reading/adding each word of
2255 * the EEPROM and then verifies that the sum of the EEPROM is
2256 * equal to 0xBABA.
2257 **/
2258static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2259{
2260 s32 ret_val = 0;
2261 u16 eeprom_regions_count = 1;
2262 u16 j, nvm_data;
2263 u16 nvm_offset;
2264
2265 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2266 if (ret_val) {
2267 hw_dbg("NVM Read Error\n");
2268 goto out;
2269 }
2270
2271 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
34a0326e 2272 /* if checksums compatibility bit is set validate checksums
b980ac18
JK		 2273 * for all 4 ports.
2274 */
4322e561
CW		 2275 eeprom_regions_count = 4;
2276 }
2277
2278 for (j = 0; j < eeprom_regions_count; j++) {
2279 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2280 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2281 nvm_offset);
2282 if (ret_val != 0)
2283 goto out;
2284 }
2285
2286out:
2287 return ret_val;
2288}
2289
2290/**
2291 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2292 * @hw: pointer to the HW structure
2293 *
2294 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2295 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2296 * checksum and writes the value to the EEPROM.
2297 **/
2298static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2299{
2300 s32 ret_val;
2301 u16 j, nvm_data;
2302 u16 nvm_offset;
2303
2304 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2305 if (ret_val) {
2306 hw_dbg("NVM Read Error while updating checksum"
2307 " compatibility bit.\n");
2308 goto out;
2309 }
2310
2311 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2312 /* set compatibility bit to validate checksums appropriately */
2313 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2314 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2315 &nvm_data);
2316 if (ret_val) {
2317 hw_dbg("NVM Write Error while updating checksum"
2318 " compatibility bit.\n");
2319 goto out;
2320 }
2321 }
2322
2323 for (j = 0; j < 4; j++) {
2324 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2325 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2326 if (ret_val)
2327 goto out;
2328 }
2329
2330out:
2331 return ret_val;
2332}
2333
2334/**
2335 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2336 * @hw: pointer to the HW structure
2337 *
2338 * Calculates the EEPROM section checksum by reading/adding each word of
2339 * the EEPROM and then verifies that the sum of the EEPROM is
2340 * equal to 0xBABA.
2341 **/
2342static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2343{
2344 s32 ret_val = 0;
2345 u16 j;
2346 u16 nvm_offset;
2347
2348 for (j = 0; j < 4; j++) {
2349 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2350 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2351 nvm_offset);
2352 if (ret_val != 0)
2353 goto out;
2354 }
2355
2356out:
2357 return ret_val;
2358}
2359
2360/**
2361 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2362 * @hw: pointer to the HW structure
2363 *
2364 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2365 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2366 * checksum and writes the value to the EEPROM.
2367 **/
2368static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2369{
2370 s32 ret_val = 0;
2371 u16 j;
2372 u16 nvm_offset;
2373
2374 for (j = 0; j < 4; j++) {
2375 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2376 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2377 if (ret_val != 0)
2378 goto out;
2379 }
2380
2381out:
2382 return ret_val;
2383}
34a0326e 2384
87371b9d
MV		 2385/**
2386 * __igb_access_emi_reg - Read/write EMI register
2387 * @hw: pointer to the HW structure
2388 * @addr: EMI address to program
2389 * @data: pointer to value to read/write from/to the EMI address
2390 * @read: boolean flag to indicate read or write
2391 **/
2392static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2393 u16 *data, bool read)
2394{
2395 s32 ret_val = E1000_SUCCESS;
2396
2397 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2398 if (ret_val)
2399 return ret_val;
2400
2401 if (read)
2402 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2403 else
2404 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2405
2406 return ret_val;
2407}
2408
2409/**
2410 * igb_read_emi_reg - Read Extended Management Interface register
2411 * @hw: pointer to the HW structure
2412 * @addr: EMI address to program
2413 * @data: value to be read from the EMI address
2414 **/
2415s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2416{
2417 return __igb_access_emi_reg(hw, addr, data, true);
2418}
2419
09b068d4
CW		 2420/**
2421 * igb_set_eee_i350 - Enable/disable EEE support
2422 * @hw: pointer to the HW structure
2423 *
2424 * Enable/disable EEE based on setting in dev_spec structure.
2425 *
2426 **/
2427s32 igb_set_eee_i350(struct e1000_hw *hw)
2428{
2429 s32 ret_val = 0;
e5461112 2430 u32 ipcnfg, eeer;
09b068d4 2431
e5461112
AA		 2432 if ((hw->mac.type < e1000_i350) ||
2433 (hw->phy.media_type != e1000_media_type_copper))
09b068d4
CW		 2434 goto out;
2435 ipcnfg = rd32(E1000_IPCNFG);
2436 eeer = rd32(E1000_EEER);
2437
2438 /* enable or disable per user setting */
2439 if (!(hw->dev_spec._82575.eee_disable)) {
40b20122
CW		 2440 u32 eee_su = rd32(E1000_EEE_SU);
2441
2442 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2443 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
09b068d4
CW		 2444 E1000_EEER_LPI_FC);
2445
40b20122
CW		 2446 /* This bit should not be set in normal operation. */
2447 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2448 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2449
09b068d4
CW		 2450 } else {
2451 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2452 E1000_IPCNFG_EEE_100M_AN);
2453 eeer &= ~(E1000_EEER_TX_LPI_EN |
2454 E1000_EEER_RX_LPI_EN |
2455 E1000_EEER_LPI_FC);
2456 }
2457 wr32(E1000_IPCNFG, ipcnfg);
2458 wr32(E1000_EEER, eeer);
e5461112
AA		 2459 rd32(E1000_IPCNFG);
2460 rd32(E1000_EEER);
09b068d4
CW		 2461out:
2462
2463 return ret_val;
2464}
4322e561 2465
ceb5f13b
CW		 2466/**
2467 * igb_set_eee_i354 - Enable/disable EEE support
2468 * @hw: pointer to the HW structure
2469 *
2470 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2471 *
2472 **/
2473s32 igb_set_eee_i354(struct e1000_hw *hw)
2474{
2475 struct e1000_phy_info *phy = &hw->phy;
2476 s32 ret_val = 0;
2477 u16 phy_data;
2478
2479 if ((hw->phy.media_type != e1000_media_type_copper) ||
2480 (phy->id != M88E1545_E_PHY_ID))
2481 goto out;
2482
2483 if (!hw->dev_spec._82575.eee_disable) {
2484 /* Switch to PHY page 18. */
2485 ret_val = phy->ops.write_reg(hw, E1000_M88E1545_PAGE_ADDR, 18);
2486 if (ret_val)
2487 goto out;
2488
2489 ret_val = phy->ops.read_reg(hw, E1000_M88E1545_EEE_CTRL_1,
2490 &phy_data);
2491 if (ret_val)
2492 goto out;
2493
2494 phy_data |= E1000_M88E1545_EEE_CTRL_1_MS;
2495 ret_val = phy->ops.write_reg(hw, E1000_M88E1545_EEE_CTRL_1,
2496 phy_data);
2497 if (ret_val)
2498 goto out;
2499
2500 /* Return the PHY to page 0. */
2501 ret_val = phy->ops.write_reg(hw, E1000_M88E1545_PAGE_ADDR, 0);
2502 if (ret_val)
2503 goto out;
2504
2505 /* Turn on EEE advertisement. */
2506 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2507 E1000_EEE_ADV_DEV_I354,
2508 &phy_data);
2509 if (ret_val)
2510 goto out;
2511
2512 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2513 E1000_EEE_ADV_1000_SUPPORTED;
2514 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2515 E1000_EEE_ADV_DEV_I354,
2516 phy_data);
2517 } else {
2518 /* Turn off EEE advertisement. */
2519 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2520 E1000_EEE_ADV_DEV_I354,
2521 &phy_data);
2522 if (ret_val)
2523 goto out;
2524
2525 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2526 E1000_EEE_ADV_1000_SUPPORTED);
2527 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2528 E1000_EEE_ADV_DEV_I354,
2529 phy_data);
2530 }
2531
2532out:
2533 return ret_val;
2534}
2535
2536/**
2537 * igb_get_eee_status_i354 - Get EEE status
2538 * @hw: pointer to the HW structure
2539 * @status: EEE status
2540 *
2541 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2542 * been received.
2543 **/
2544s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2545{
2546 struct e1000_phy_info *phy = &hw->phy;
2547 s32 ret_val = 0;
2548 u16 phy_data;
2549
2550 /* Check if EEE is supported on this device. */
2551 if ((hw->phy.media_type != e1000_media_type_copper) ||
2552 (phy->id != M88E1545_E_PHY_ID))
2553 goto out;
2554
2555 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2556 E1000_PCS_STATUS_DEV_I354,
2557 &phy_data);
2558 if (ret_val)
2559 goto out;
2560
2561 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2562 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2563
2564out:
2565 return ret_val;
2566}
2567
e428893b
CW		 2568static const u8 e1000_emc_temp_data[4] = {
2569 E1000_EMC_INTERNAL_DATA,
2570 E1000_EMC_DIODE1_DATA,
2571 E1000_EMC_DIODE2_DATA,
2572 E1000_EMC_DIODE3_DATA
2573};
2574static const u8 e1000_emc_therm_limit[4] = {
2575 E1000_EMC_INTERNAL_THERM_LIMIT,
2576 E1000_EMC_DIODE1_THERM_LIMIT,
2577 E1000_EMC_DIODE2_THERM_LIMIT,
2578 E1000_EMC_DIODE3_THERM_LIMIT
2579};
2580
b980ac18
JK		 2581/**
2582 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
e428893b
CW		 2583 * @hw: pointer to hardware structure
2584 *
2585 * Updates the temperatures in mac.thermal_sensor_data
b980ac18 2586 **/
e428893b
CW		 2587s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2588{
2589 s32 status = E1000_SUCCESS;
2590 u16 ets_offset;
2591 u16 ets_cfg;
2592 u16 ets_sensor;
2593 u8 num_sensors;
2594 u8 sensor_index;
2595 u8 sensor_location;
2596 u8 i;
2597 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2598
2599 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2600 return E1000_NOT_IMPLEMENTED;
2601
2602 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2603
2604 /* Return the internal sensor only if ETS is unsupported */
2605 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2606 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2607 return status;
2608
2609 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2610 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2611 != NVM_ETS_TYPE_EMC)
2612 return E1000_NOT_IMPLEMENTED;
2613
2614 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2615 if (num_sensors > E1000_MAX_SENSORS)
2616 num_sensors = E1000_MAX_SENSORS;
2617
2618 for (i = 1; i < num_sensors; i++) {
2619 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2620 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2621 NVM_ETS_DATA_INDEX_SHIFT);
2622 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2623 NVM_ETS_DATA_LOC_SHIFT);
2624
2625 if (sensor_location != 0)
2626 hw->phy.ops.read_i2c_byte(hw,
2627 e1000_emc_temp_data[sensor_index],
2628 E1000_I2C_THERMAL_SENSOR_ADDR,
2629 &data->sensor[i].temp);
2630 }
2631 return status;
2632}
2633
b980ac18
JK		 2634/**
2635 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
e428893b
CW		 2636 * @hw: pointer to hardware structure
2637 *
2638 * Sets the thermal sensor thresholds according to the NVM map
2639 * and save off the threshold and location values into mac.thermal_sensor_data
b980ac18 2640 **/
e428893b
CW		 2641s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2642{
2643 s32 status = E1000_SUCCESS;
2644 u16 ets_offset;
2645 u16 ets_cfg;
2646 u16 ets_sensor;
2647 u8 low_thresh_delta;
2648 u8 num_sensors;
2649 u8 sensor_index;
2650 u8 sensor_location;
2651 u8 therm_limit;
2652 u8 i;
2653 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2654
2655 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2656 return E1000_NOT_IMPLEMENTED;
2657
2658 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2659
2660 data->sensor[0].location = 0x1;
2661 data->sensor[0].caution_thresh =
2662 (rd32(E1000_THHIGHTC) & 0xFF);
2663 data->sensor[0].max_op_thresh =
2664 (rd32(E1000_THLOWTC) & 0xFF);
2665
2666 /* Return the internal sensor only if ETS is unsupported */
2667 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2668 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2669 return status;
2670
2671 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2672 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2673 != NVM_ETS_TYPE_EMC)
2674 return E1000_NOT_IMPLEMENTED;
2675
2676 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2677 NVM_ETS_LTHRES_DELTA_SHIFT);
2678 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2679
2680 for (i = 1; i <= num_sensors; i++) {
2681 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2682 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2683 NVM_ETS_DATA_INDEX_SHIFT);
2684 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2685 NVM_ETS_DATA_LOC_SHIFT);
2686 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2687
2688 hw->phy.ops.write_i2c_byte(hw,
2689 e1000_emc_therm_limit[sensor_index],
2690 E1000_I2C_THERMAL_SENSOR_ADDR,
2691 therm_limit);
2692
2693 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2694 data->sensor[i].location = sensor_location;
2695 data->sensor[i].caution_thresh = therm_limit;
2696 data->sensor[i].max_op_thresh = therm_limit -
2697 low_thresh_delta;
2698 }
2699 }
2700 return status;
2701}
2702
9d5c8243 2703static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 2704 .init_hw = igb_init_hw_82575,
2705 .check_for_link = igb_check_for_link_82575,
2d064c06 2706 .rar_set = igb_rar_set,
9d5c8243
AK		 2707 .read_mac_addr = igb_read_mac_addr_82575,
2708 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
e428893b
CW		 2709#ifdef CONFIG_IGB_HWMON
2710 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2711 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2712#endif
9d5c8243
AK		 2713};
2714
2715static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 2716 .acquire = igb_acquire_phy_82575,
9d5c8243 2717 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 2718 .release = igb_release_phy_82575,
441fc6fd
CW		 2719 .write_i2c_byte = igb_write_i2c_byte,
2720 .read_i2c_byte = igb_read_i2c_byte,
9d5c8243
AK		 2721};
2722
2723static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 2724 .acquire = igb_acquire_nvm_82575,
2725 .read = igb_read_nvm_eerd,
2726 .release = igb_release_nvm_82575,
2727 .write = igb_write_nvm_spi,
9d5c8243
AK		 2728};
2729
2730const struct e1000_info e1000_82575_info = {
2731 .get_invariants = igb_get_invariants_82575,
2732 .mac_ops = &e1000_mac_ops_82575,
2733 .phy_ops = &e1000_phy_ops_82575,
2734 .nvm_ops = &e1000_nvm_ops_82575,
2735};
2736
Linux kernel - Deliverables
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