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igb: Initialize NVM function pointers
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
82bbcdeb
JP		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
9d5c8243 34#include <linux/types.h>
2d064c06 35#include <linux/if_ether.h>
441fc6fd 36#include <linux/i2c.h>
9d5c8243
AK		 37
38#include "e1000_mac.h"
39#include "e1000_82575.h"
f96a8a0b 40#include "e1000_i210.h"
9d5c8243
AK		 41
42static s32 igb_get_invariants_82575(struct e1000_hw *);
43static s32 igb_acquire_phy_82575(struct e1000_hw *);
44static void igb_release_phy_82575(struct e1000_hw *);
45static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46static void igb_release_nvm_82575(struct e1000_hw *);
47static s32 igb_check_for_link_82575(struct e1000_hw *);
48static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49static s32 igb_init_hw_82575(struct e1000_hw *);
50static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 52static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 54static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 55static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243 56static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
da02cde1
CW		 57static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
9d5c8243 59static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 60static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 61static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 64static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
65 u16 *);
66static s32 igb_get_phy_id_82575(struct e1000_hw *);
67static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68static bool igb_sgmii_active_82575(struct e1000_hw *);
69static s32 igb_reset_init_script_82575(struct e1000_hw *);
70static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 71static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
99870a73 72static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
4322e561
CW		 73static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
4322e561
CW		 75static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
bb2ac47b
AD		 77static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
79 35, 70, 140 };
80#define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
82
4085f746
NN		 83/**
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
86 *
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
89 **/
90static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
91{
92 u32 reg = 0;
93 bool ext_mdio = false;
94
95 switch (hw->mac.type) {
96 case e1000_82575:
97 case e1000_82576:
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
100 break;
101 case e1000_82580:
102 case e1000_i350:
f96a8a0b
CW		 103 case e1000_i210:
104 case e1000_i211:
4085f746
NN		 105 reg = rd32(E1000_MDICNFG);
106 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
107 break;
108 default:
109 break;
110 }
111 return ext_mdio;
112}
113
73bfcd9a
AA		 114/**
115 * igb_init_phy_params_82575 - Init PHY func ptrs.
116 * @hw: pointer to the HW structure
117 **/
118static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
119{
120 struct e1000_phy_info *phy = &hw->phy;
121 s32 ret_val = 0;
122 u32 ctrl_ext;
123
124 if (hw->phy.media_type != e1000_media_type_copper) {
125 phy->type = e1000_phy_none;
126 goto out;
127 }
128
129 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
130 phy->reset_delay_us = 100;
131
132 ctrl_ext = rd32(E1000_CTRL_EXT);
133
134 if (igb_sgmii_active_82575(hw)) {
135 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
136 ctrl_ext |= E1000_CTRL_I2C_ENA;
137 } else {
138 phy->ops.reset = igb_phy_hw_reset;
139 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
140 }
141
142 wr32(E1000_CTRL_EXT, ctrl_ext);
143 igb_reset_mdicnfg_82580(hw);
144
145 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
146 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
147 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
148 } else {
149 switch (hw->mac.type) {
150 case e1000_82580:
151 case e1000_i350:
152 phy->ops.read_reg = igb_read_phy_reg_82580;
153 phy->ops.write_reg = igb_write_phy_reg_82580;
154 break;
155 case e1000_i210:
156 case e1000_i211:
157 phy->ops.read_reg = igb_read_phy_reg_gs40g;
158 phy->ops.write_reg = igb_write_phy_reg_gs40g;
159 break;
160 default:
161 phy->ops.read_reg = igb_read_phy_reg_igp;
162 phy->ops.write_reg = igb_write_phy_reg_igp;
163 }
164 }
165
166 /* set lan id */
167 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
168 E1000_STATUS_FUNC_SHIFT;
169
170 /* Set phy->phy_addr and phy->id. */
171 ret_val = igb_get_phy_id_82575(hw);
172 if (ret_val)
173 return ret_val;
174
175 /* Verify phy id and set remaining function pointers */
176 switch (phy->id) {
177 case I347AT4_E_PHY_ID:
178 case M88E1112_E_PHY_ID:
179 case M88E1111_I_PHY_ID:
180 phy->type = e1000_phy_m88;
181 phy->ops.get_phy_info = igb_get_phy_info_m88;
182 if (phy->id == I347AT4_E_PHY_ID ||
183 phy->id == M88E1112_E_PHY_ID)
184 phy->ops.get_cable_length =
185 igb_get_cable_length_m88_gen2;
186 else
187 phy->ops.get_cable_length = igb_get_cable_length_m88;
188 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
189 break;
190 case IGP03E1000_E_PHY_ID:
191 phy->type = e1000_phy_igp_3;
192 phy->ops.get_phy_info = igb_get_phy_info_igp;
193 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
194 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
195 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
196 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
197 break;
198 case I82580_I_PHY_ID:
199 case I350_I_PHY_ID:
200 phy->type = e1000_phy_82580;
201 phy->ops.force_speed_duplex =
202 igb_phy_force_speed_duplex_82580;
203 phy->ops.get_cable_length = igb_get_cable_length_82580;
204 phy->ops.get_phy_info = igb_get_phy_info_82580;
205 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
206 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
207 break;
208 case I210_I_PHY_ID:
209 phy->type = e1000_phy_i210;
210 phy->ops.check_polarity = igb_check_polarity_m88;
211 phy->ops.get_phy_info = igb_get_phy_info_m88;
212 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
213 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
214 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
215 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
216 break;
217 default:
218 ret_val = -E1000_ERR_PHY;
219 goto out;
220 }
221
222out:
223 return ret_val;
224}
225
56d8c27f
AA		 226/**
227 * igb_init_nvm_params_82575 - Init NVM func ptrs.
228 * @hw: pointer to the HW structure
229 **/
230s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
231{
232 struct e1000_nvm_info *nvm = &hw->nvm;
233 u32 eecd = rd32(E1000_EECD);
234 u16 size;
235
236 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
237 E1000_EECD_SIZE_EX_SHIFT);
238 /* Added to a constant, "size" becomes the left-shift value
239 * for setting word_size.
240 */
241 size += NVM_WORD_SIZE_BASE_SHIFT;
242
243 /* Just in case size is out of range, cap it to the largest
244 * EEPROM size supported
245 */
246 if (size > 15)
247 size = 15;
248
249 nvm->word_size = 1 << size;
250 if (hw->mac.type < e1000_i210) {
251 nvm->opcode_bits = 8;
252 nvm->delay_usec = 1;
253
254 switch (nvm->override) {
255 case e1000_nvm_override_spi_large:
256 nvm->page_size = 32;
257 nvm->address_bits = 16;
258 break;
259 case e1000_nvm_override_spi_small:
260 nvm->page_size = 8;
261 nvm->address_bits = 8;
262 break;
263 default:
264 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
265 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
266 16 : 8;
267 break;
268 }
269 if (nvm->word_size == (1 << 15))
270 nvm->page_size = 128;
271
272 nvm->type = e1000_nvm_eeprom_spi;
273 } else {
274 nvm->type = e1000_nvm_flash_hw;
275 }
276
277 /* NVM Function Pointers */
278 switch (hw->mac.type) {
279 case e1000_82580:
280 nvm->ops.validate = igb_validate_nvm_checksum_82580;
281 nvm->ops.update = igb_update_nvm_checksum_82580;
282 nvm->ops.acquire = igb_acquire_nvm_82575;
283 nvm->ops.release = igb_release_nvm_82575;
284 if (nvm->word_size < (1 << 15))
285 nvm->ops.read = igb_read_nvm_eerd;
286 else
287 nvm->ops.read = igb_read_nvm_spi;
288 nvm->ops.write = igb_write_nvm_spi;
289 break;
290 case e1000_i350:
291 nvm->ops.validate = igb_validate_nvm_checksum_i350;
292 nvm->ops.update = igb_update_nvm_checksum_i350;
293 nvm->ops.acquire = igb_acquire_nvm_82575;
294 nvm->ops.release = igb_release_nvm_82575;
295 if (nvm->word_size < (1 << 15))
296 nvm->ops.read = igb_read_nvm_eerd;
297 else
298 nvm->ops.read = igb_read_nvm_spi;
299 nvm->ops.write = igb_write_nvm_spi;
300 break;
301 case e1000_i210:
302 nvm->ops.validate = igb_validate_nvm_checksum_i210;
303 nvm->ops.update = igb_update_nvm_checksum_i210;
304 nvm->ops.acquire = igb_acquire_nvm_i210;
305 nvm->ops.release = igb_release_nvm_i210;
306 nvm->ops.read = igb_read_nvm_srrd_i210;
307 nvm->ops.write = igb_write_nvm_srwr_i210;
308 nvm->ops.valid_led_default = igb_valid_led_default_i210;
309 break;
310 case e1000_i211:
311 nvm->ops.acquire = igb_acquire_nvm_i210;
312 nvm->ops.release = igb_release_nvm_i210;
313 nvm->ops.read = igb_read_nvm_i211;
314 nvm->ops.valid_led_default = igb_valid_led_default_i210;
315 nvm->ops.validate = NULL;
316 nvm->ops.update = NULL;
317 nvm->ops.write = NULL;
318 break;
319 default:
320 nvm->ops.validate = igb_validate_nvm_checksum;
321 nvm->ops.update = igb_update_nvm_checksum;
322 nvm->ops.acquire = igb_acquire_nvm_82575;
323 nvm->ops.release = igb_release_nvm_82575;
324 if (nvm->word_size < (1 << 15))
325 nvm->ops.read = igb_read_nvm_eerd;
326 else
327 nvm->ops.read = igb_read_nvm_spi;
328 nvm->ops.write = igb_write_nvm_spi;
329 break;
330 }
331
332 return 0;
333}
334
9d5c8243
AK		 335static s32 igb_get_invariants_82575(struct e1000_hw *hw)
336{
337 struct e1000_phy_info *phy = &hw->phy;
338 struct e1000_nvm_info *nvm = &hw->nvm;
339 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 340 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243
AK		 341 u32 eecd;
342 s32 ret_val;
343 u16 size;
344 u32 ctrl_ext = 0;
345
346 switch (hw->device_id) {
347 case E1000_DEV_ID_82575EB_COPPER:
348 case E1000_DEV_ID_82575EB_FIBER_SERDES:
349 case E1000_DEV_ID_82575GB_QUAD_COPPER:
350 mac->type = e1000_82575;
351 break;
2d064c06 352 case E1000_DEV_ID_82576:
9eb2341d 353 case E1000_DEV_ID_82576_NS:
747d49ba 354 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 355 case E1000_DEV_ID_82576_FIBER:
356 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 357 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 358 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 359 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 360 mac->type = e1000_82576;
361 break;
bb2ac47b
AD		 362 case E1000_DEV_ID_82580_COPPER:
363 case E1000_DEV_ID_82580_FIBER:
6493d24f 364 case E1000_DEV_ID_82580_QUAD_FIBER:
bb2ac47b
AD		 365 case E1000_DEV_ID_82580_SERDES:
366 case E1000_DEV_ID_82580_SGMII:
367 case E1000_DEV_ID_82580_COPPER_DUAL:
308fb39a
JG		 368 case E1000_DEV_ID_DH89XXCC_SGMII:
369 case E1000_DEV_ID_DH89XXCC_SERDES:
1b5dda33
GJ		 370 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
371 case E1000_DEV_ID_DH89XXCC_SFP:
bb2ac47b
AD		 372 mac->type = e1000_82580;
373 break;
d2ba2ed8
AD		 374 case E1000_DEV_ID_I350_COPPER:
375 case E1000_DEV_ID_I350_FIBER:
376 case E1000_DEV_ID_I350_SERDES:
377 case E1000_DEV_ID_I350_SGMII:
378 mac->type = e1000_i350;
379 break;
f96a8a0b
CW		 380 case E1000_DEV_ID_I210_COPPER:
381 case E1000_DEV_ID_I210_COPPER_OEM1:
382 case E1000_DEV_ID_I210_COPPER_IT:
383 case E1000_DEV_ID_I210_FIBER:
384 case E1000_DEV_ID_I210_SERDES:
385 case E1000_DEV_ID_I210_SGMII:
386 mac->type = e1000_i210;
387 break;
388 case E1000_DEV_ID_I211_COPPER:
389 mac->type = e1000_i211;
390 break;
9d5c8243
AK		 391 default:
392 return -E1000_ERR_MAC_INIT;
393 break;
394 }
395
9d5c8243
AK		 396 /* Set media type */
397 /*
398 * The 82575 uses bits 22:23 for link mode. The mode can be changed
399 * based on the EEPROM. We cannot rely upon device ID. There
400 * is no distinguishable difference between fiber and internal
401 * SerDes mode on the 82575. There can be an external PHY attached
402 * on the SGMII interface. For this, we'll set sgmii_active to true.
403 */
404 phy->media_type = e1000_media_type_copper;
405 dev_spec->sgmii_active = false;
406
407 ctrl_ext = rd32(E1000_CTRL_EXT);
2fb02a26
AD		 408 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
409 case E1000_CTRL_EXT_LINK_MODE_SGMII:
9d5c8243 410 dev_spec->sgmii_active = true;
2fb02a26 411 break;
bb2ac47b 412 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26
AD		 413 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
414 hw->phy.media_type = e1000_media_type_internal_serdes;
2fb02a26
AD		 415 break;
416 default:
2fb02a26 417 break;
9d5c8243 418 }
2fb02a26 419
9d5c8243
AK		 420 /* Set mta register count */
421 mac->mta_reg_count = 128;
422 /* Set rar entry count */
f96a8a0b
CW		 423 switch (mac->type) {
424 case e1000_82576:
2d064c06 425 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
f96a8a0b
CW		 426 break;
427 case e1000_82580:
bb2ac47b 428 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
f96a8a0b
CW		 429 break;
430 case e1000_i350:
d2ba2ed8 431 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
f96a8a0b
CW		 432 break;
433 default:
434 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
435 break;
436 }
bb2ac47b 437 /* reset */
d2ba2ed8 438 if (mac->type >= e1000_82580)
bb2ac47b
AD		 439 mac->ops.reset_hw = igb_reset_hw_82580;
440 else
441 mac->ops.reset_hw = igb_reset_hw_82575;
f96a8a0b
CW		 442
443 if (mac->type >= e1000_i210) {
444 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
445 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
446 } else {
447 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
448 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
449 }
450
9d5c8243
AK		 451 /* Set if part includes ASF firmware */
452 mac->asf_firmware_present = true;
453 /* Set if manageability features are enabled. */
454 mac->arc_subsystem_valid =
455 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
456 ? true : false;
f96a8a0b
CW		 457 /* enable EEE on i350 parts and later parts */
458 if (mac->type >= e1000_i350)
09b068d4
CW		 459 dev_spec->eee_disable = false;
460 else
461 dev_spec->eee_disable = true;
9d5c8243
AK		 462 /* physical interface link setup */
463 mac->ops.setup_physical_interface =
464 (hw->phy.media_type == e1000_media_type_copper)
465 ? igb_setup_copper_link_82575
2fb02a26 466 : igb_setup_serdes_link_82575;
9d5c8243
AK		 467
468 /* NVM initialization */
469 eecd = rd32(E1000_EECD);
9d5c8243
AK		 470 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
471 E1000_EECD_SIZE_EX_SHIFT);
472
473 /*
474 * Added to a constant, "size" becomes the left-shift value
475 * for setting word_size.
476 */
477 size += NVM_WORD_SIZE_BASE_SHIFT;
5c3cad75 478
925b11f7
CW		 479 /*
480 * Check for invalid size
481 */
482 if ((hw->mac.type == e1000_82576) && (size > 15)) {
483 pr_notice("The NVM size is not valid, defaulting to 32K\n");
484 size = 15;
485 }
486
f96a8a0b
CW		 487 nvm->word_size = 1 << size;
488 if (hw->mac.type < e1000_i210) {
489 nvm->opcode_bits = 8;
490 nvm->delay_usec = 1;
491 switch (nvm->override) {
492 case e1000_nvm_override_spi_large:
493 nvm->page_size = 32;
494 nvm->address_bits = 16;
495 break;
496 case e1000_nvm_override_spi_small:
497 nvm->page_size = 8;
498 nvm->address_bits = 8;
499 break;
500 default:
501 nvm->page_size = eecd
502 & E1000_EECD_ADDR_BITS ? 32 : 8;
503 nvm->address_bits = eecd
504 & E1000_EECD_ADDR_BITS ? 16 : 8;
505 break;
506 }
507 if (nvm->word_size == (1 << 15))
508 nvm->page_size = 128;
509
510 nvm->type = e1000_nvm_eeprom_spi;
511 } else
512 nvm->type = e1000_nvm_flash_hw;
513
4322e561 514 /* NVM Function Pointers */
4322e561
CW		 515 switch (hw->mac.type) {
516 case e1000_82580:
517 nvm->ops.validate = igb_validate_nvm_checksum_82580;
518 nvm->ops.update = igb_update_nvm_checksum_82580;
f96a8a0b
CW		 519 nvm->ops.acquire = igb_acquire_nvm_82575;
520 nvm->ops.release = igb_release_nvm_82575;
521 if (nvm->word_size < (1 << 15))
522 nvm->ops.read = igb_read_nvm_eerd;
523 else
524 nvm->ops.read = igb_read_nvm_spi;
525 nvm->ops.write = igb_write_nvm_spi;
4322e561
CW		 526 break;
527 case e1000_i350:
528 nvm->ops.validate = igb_validate_nvm_checksum_i350;
529 nvm->ops.update = igb_update_nvm_checksum_i350;
f96a8a0b
CW		 530 nvm->ops.acquire = igb_acquire_nvm_82575;
531 nvm->ops.release = igb_release_nvm_82575;
532 if (nvm->word_size < (1 << 15))
533 nvm->ops.read = igb_read_nvm_eerd;
534 else
535 nvm->ops.read = igb_read_nvm_spi;
536 nvm->ops.write = igb_write_nvm_spi;
537 break;
538 case e1000_i210:
539 nvm->ops.validate = igb_validate_nvm_checksum_i210;
540 nvm->ops.update = igb_update_nvm_checksum_i210;
541 nvm->ops.acquire = igb_acquire_nvm_i210;
542 nvm->ops.release = igb_release_nvm_i210;
543 nvm->ops.read = igb_read_nvm_srrd_i210;
ede4126e 544 nvm->ops.write = igb_write_nvm_srwr_i210;
f96a8a0b
CW		 545 nvm->ops.valid_led_default = igb_valid_led_default_i210;
546 break;
547 case e1000_i211:
548 nvm->ops.acquire = igb_acquire_nvm_i210;
549 nvm->ops.release = igb_release_nvm_i210;
550 nvm->ops.read = igb_read_nvm_i211;
551 nvm->ops.valid_led_default = igb_valid_led_default_i210;
552 nvm->ops.validate = NULL;
553 nvm->ops.update = NULL;
554 nvm->ops.write = NULL;
4322e561
CW		 555 break;
556 default:
557 nvm->ops.validate = igb_validate_nvm_checksum;
558 nvm->ops.update = igb_update_nvm_checksum;
f96a8a0b
CW		 559 nvm->ops.acquire = igb_acquire_nvm_82575;
560 nvm->ops.release = igb_release_nvm_82575;
561 if (nvm->word_size < (1 << 15))
562 nvm->ops.read = igb_read_nvm_eerd;
563 else
564 nvm->ops.read = igb_read_nvm_spi;
565 nvm->ops.write = igb_write_nvm_spi;
566 break;
4322e561 567 }
9d5c8243 568
6b78bb1d
CW		 569 /* if part supports SR-IOV then initialize mailbox parameters */
570 switch (mac->type) {
571 case e1000_82576:
572 case e1000_i350:
a0c98605 573 igb_init_mbx_params_pf(hw);
6b78bb1d
CW		 574 break;
575 default:
576 break;
577 }
a0c98605 578
9d5c8243
AK		 579 /* setup PHY parameters */
580 if (phy->media_type != e1000_media_type_copper) {
581 phy->type = e1000_phy_none;
582 return 0;
583 }
584
585 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
586 phy->reset_delay_us = 100;
587
99870a73
AD		 588 ctrl_ext = rd32(E1000_CTRL_EXT);
589
9d5c8243 590 /* PHY function pointers */
99870a73 591 if (igb_sgmii_active_82575(hw)) {
4085f746 592 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
99870a73
AD		 593 ctrl_ext |= E1000_CTRL_I2C_ENA;
594 } else {
4085f746 595 phy->ops.reset = igb_phy_hw_reset;
99870a73
AD		 596 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
597 }
598
599 wr32(E1000_CTRL_EXT, ctrl_ext);
600 igb_reset_mdicnfg_82580(hw);
4085f746
NN		 601
602 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
603 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
604 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
f96a8a0b
CW		 605 } else if ((hw->mac.type == e1000_82580)
606 || (hw->mac.type == e1000_i350)) {
4085f746
NN		 607 phy->ops.read_reg = igb_read_phy_reg_82580;
608 phy->ops.write_reg = igb_write_phy_reg_82580;
f96a8a0b
CW		 609 } else if (hw->phy.type >= e1000_phy_i210) {
610 phy->ops.read_reg = igb_read_phy_reg_gs40g;
611 phy->ops.write_reg = igb_write_phy_reg_gs40g;
9d5c8243 612 } else {
4085f746
NN		 613 phy->ops.read_reg = igb_read_phy_reg_igp;
614 phy->ops.write_reg = igb_write_phy_reg_igp;
9d5c8243
AK		 615 }
616
19e588e7
AD		 617 /* set lan id */
618 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
619 E1000_STATUS_FUNC_SHIFT;
620
9d5c8243
AK		 621 /* Set phy->phy_addr and phy->id. */
622 ret_val = igb_get_phy_id_82575(hw);
623 if (ret_val)
624 return ret_val;
625
626 /* Verify phy id and set remaining function pointers */
627 switch (phy->id) {
308fb39a
JG		 628 case I347AT4_E_PHY_ID:
629 case M88E1112_E_PHY_ID:
9d5c8243
AK		 630 case M88E1111_I_PHY_ID:
631 phy->type = e1000_phy_m88;
632 phy->ops.get_phy_info = igb_get_phy_info_m88;
308fb39a
JG		 633
634 if (phy->id == I347AT4_E_PHY_ID ||
635 phy->id == M88E1112_E_PHY_ID)
636 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
637 else
638 phy->ops.get_cable_length = igb_get_cable_length_m88;
639
f96a8a0b
CW		 640 if (phy->id == I210_I_PHY_ID) {
641 phy->ops.get_cable_length =
642 igb_get_cable_length_m88_gen2;
643 phy->ops.set_d0_lplu_state =
644 igb_set_d0_lplu_state_82580;
645 phy->ops.set_d3_lplu_state =
646 igb_set_d3_lplu_state_82580;
647 }
9d5c8243
AK		 648 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
649 break;
650 case IGP03E1000_E_PHY_ID:
651 phy->type = e1000_phy_igp_3;
652 phy->ops.get_phy_info = igb_get_phy_info_igp;
653 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
654 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
655 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
656 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
657 break;
bb2ac47b 658 case I82580_I_PHY_ID:
d2ba2ed8 659 case I350_I_PHY_ID:
bb2ac47b
AD		 660 phy->type = e1000_phy_82580;
661 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
662 phy->ops.get_cable_length = igb_get_cable_length_82580;
663 phy->ops.get_phy_info = igb_get_phy_info_82580;
da02cde1
CW		 664 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
665 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
bb2ac47b 666 break;
f96a8a0b
CW		 667 case I210_I_PHY_ID:
668 phy->type = e1000_phy_i210;
669 phy->ops.get_phy_info = igb_get_phy_info_m88;
670 phy->ops.check_polarity = igb_check_polarity_m88;
671 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
672 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
673 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
674 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
675 break;
9d5c8243
AK		 676 default:
677 return -E1000_ERR_PHY;
678 }
679
680 return 0;
681}
682
683/**
733596be 684 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 685 * @hw: pointer to the HW structure
686 *
687 * Acquire access rights to the correct PHY. This is a
688 * function pointer entry point called by the api module.
689 **/
690static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
691{
008c3422 692 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 693
008c3422
AD		 694 if (hw->bus.func == E1000_FUNC_1)
695 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 696 else if (hw->bus.func == E1000_FUNC_2)
697 mask = E1000_SWFW_PHY2_SM;
698 else if (hw->bus.func == E1000_FUNC_3)
699 mask = E1000_SWFW_PHY3_SM;
9d5c8243 700
f96a8a0b 701 return hw->mac.ops.acquire_swfw_sync(hw, mask);
9d5c8243
AK		 702}
703
704/**
733596be 705 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 706 * @hw: pointer to the HW structure
707 *
708 * A wrapper to release access rights to the correct PHY. This is a
709 * function pointer entry point called by the api module.
710 **/
711static void igb_release_phy_82575(struct e1000_hw *hw)
712{
008c3422
AD		 713 u16 mask = E1000_SWFW_PHY0_SM;
714
715 if (hw->bus.func == E1000_FUNC_1)
716 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 717 else if (hw->bus.func == E1000_FUNC_2)
718 mask = E1000_SWFW_PHY2_SM;
719 else if (hw->bus.func == E1000_FUNC_3)
720 mask = E1000_SWFW_PHY3_SM;
9d5c8243 721
f96a8a0b 722 hw->mac.ops.release_swfw_sync(hw, mask);
9d5c8243
AK		 723}
724
725/**
733596be 726 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 727 * @hw: pointer to the HW structure
728 * @offset: register offset to be read
729 * @data: pointer to the read data
730 *
731 * Reads the PHY register at offset using the serial gigabit media independent
732 * interface and stores the retrieved information in data.
733 **/
734static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
735 u16 *data)
736{
bf6f7a92 737 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 738
739 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 740 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 741 goto out;
9d5c8243
AK		 742 }
743
bf6f7a92
AD		 744 ret_val = hw->phy.ops.acquire(hw);
745 if (ret_val)
746 goto out;
9d5c8243 747
bf6f7a92 748 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 749
bf6f7a92
AD		 750 hw->phy.ops.release(hw);
751
752out:
753 return ret_val;
9d5c8243
AK		 754}
755
756/**
733596be 757 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 758 * @hw: pointer to the HW structure
759 * @offset: register offset to write to
760 * @data: data to write at register offset
761 *
762 * Writes the data to PHY register at the offset using the serial gigabit
763 * media independent interface.
764 **/
765static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
766 u16 data)
767{
bf6f7a92
AD		 768 s32 ret_val = -E1000_ERR_PARAM;
769
9d5c8243
AK		 770
771 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 772 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 773 goto out;
9d5c8243
AK		 774 }
775
bf6f7a92
AD		 776 ret_val = hw->phy.ops.acquire(hw);
777 if (ret_val)
778 goto out;
9d5c8243 779
bf6f7a92 780 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 781
bf6f7a92
AD		 782 hw->phy.ops.release(hw);
783
784out:
785 return ret_val;
9d5c8243
AK		 786}
787
788/**
733596be 789 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 790 * @hw: pointer to the HW structure
791 *
652fff32 792 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 793 * sgmi interface.
794 **/
795static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
796{
797 struct e1000_phy_info *phy = &hw->phy;
798 s32 ret_val = 0;
799 u16 phy_id;
2fb02a26 800 u32 ctrl_ext;
4085f746 801 u32 mdic;
9d5c8243
AK		 802
803 /*
804 * For SGMII PHYs, we try the list of possible addresses until
805 * we find one that works. For non-SGMII PHYs
806 * (e.g. integrated copper PHYs), an address of 1 should
807 * work. The result of this function should mean phy->phy_addr
808 * and phy->id are set correctly.
809 */
810 if (!(igb_sgmii_active_82575(hw))) {
811 phy->addr = 1;
812 ret_val = igb_get_phy_id(hw);
813 goto out;
814 }
815
4085f746
NN		 816 if (igb_sgmii_uses_mdio_82575(hw)) {
817 switch (hw->mac.type) {
818 case e1000_82575:
819 case e1000_82576:
820 mdic = rd32(E1000_MDIC);
821 mdic &= E1000_MDIC_PHY_MASK;
822 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
823 break;
824 case e1000_82580:
825 case e1000_i350:
f96a8a0b
CW		 826 case e1000_i210:
827 case e1000_i211:
4085f746
NN		 828 mdic = rd32(E1000_MDICNFG);
829 mdic &= E1000_MDICNFG_PHY_MASK;
830 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
831 break;
832 default:
833 ret_val = -E1000_ERR_PHY;
834 goto out;
835 break;
836 }
837 ret_val = igb_get_phy_id(hw);
838 goto out;
839 }
840
2fb02a26
AD		 841 /* Power on sgmii phy if it is disabled */
842 ctrl_ext = rd32(E1000_CTRL_EXT);
843 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
844 wrfl();
845 msleep(300);
846
9d5c8243
AK		 847 /*
848 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
849 * Therefore, we need to test 1-7
850 */
851 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
852 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
853 if (ret_val == 0) {
652fff32
AK		 854 hw_dbg("Vendor ID 0x%08X read at address %u\n",
855 phy_id, phy->addr);
9d5c8243
AK		 856 /*
857 * At the time of this writing, The M88 part is
858 * the only supported SGMII PHY product.
859 */
860 if (phy_id == M88_VENDOR)
861 break;
862 } else {
652fff32 863 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 864 }
865 }
866
867 /* A valid PHY type couldn't be found. */
868 if (phy->addr == 8) {
869 phy->addr = 0;
870 ret_val = -E1000_ERR_PHY;
871 goto out;
2fb02a26
AD		 872 } else {
873 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 874 }
875
2fb02a26
AD		 876 /* restore previous sfp cage power state */
877 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 878
879out:
880 return ret_val;
881}
882
883/**
733596be 884 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 885 * @hw: pointer to the HW structure
886 *
887 * Resets the PHY using the serial gigabit media independent interface.
888 **/
889static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
890{
891 s32 ret_val;
892
893 /*
894 * This isn't a true "hard" reset, but is the only reset
895 * available to us at this time.
896 */
897
652fff32 898 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243
AK		 899
900 /*
901 * SFP documentation requires the following to configure the SPF module
902 * to work on SGMII. No further documentation is given.
903 */
a8d2a0c2 904 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 905 if (ret_val)
906 goto out;
907
908 ret_val = igb_phy_sw_reset(hw);
909
910out:
911 return ret_val;
912}
913
914/**
733596be 915 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 916 * @hw: pointer to the HW structure
917 * @active: true to enable LPLU, false to disable
918 *
919 * Sets the LPLU D0 state according to the active flag. When
920 * activating LPLU this function also disables smart speed
921 * and vice versa. LPLU will not be activated unless the
922 * device autonegotiation advertisement meets standards of
923 * either 10 or 10/100 or 10/100/1000 at all duplexes.
924 * This is a function pointer entry point only called by
925 * PHY setup routines.
926 **/
927static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
928{
929 struct e1000_phy_info *phy = &hw->phy;
930 s32 ret_val;
931 u16 data;
932
a8d2a0c2 933 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 934 if (ret_val)
935 goto out;
936
937 if (active) {
938 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 939 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 940 data);
9d5c8243
AK		 941 if (ret_val)
942 goto out;
943
944 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 945 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 946 &data);
9d5c8243 947 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 948 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 949 data);
9d5c8243
AK		 950 if (ret_val)
951 goto out;
952 } else {
953 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 954 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 955 data);
9d5c8243
AK		 956 /*
957 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
958 * during Dx states where the power conservation is most
959 * important. During driver activity we should enable
960 * SmartSpeed, so performance is maintained.
961 */
962 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 963 ret_val = phy->ops.read_reg(hw,
652fff32 964 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 965 if (ret_val)
966 goto out;
967
968 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 969 ret_val = phy->ops.write_reg(hw,
652fff32 970 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 971 if (ret_val)
972 goto out;
973 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 974 ret_val = phy->ops.read_reg(hw,
652fff32 975 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 976 if (ret_val)
977 goto out;
978
979 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 980 ret_val = phy->ops.write_reg(hw,
652fff32 981 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 982 if (ret_val)
983 goto out;
984 }
985 }
986
987out:
988 return ret_val;
989}
990
da02cde1
CW		 991/**
992 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
993 * @hw: pointer to the HW structure
994 * @active: true to enable LPLU, false to disable
995 *
996 * Sets the LPLU D0 state according to the active flag. When
997 * activating LPLU this function also disables smart speed
998 * and vice versa. LPLU will not be activated unless the
999 * device autonegotiation advertisement meets standards of
1000 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1001 * This is a function pointer entry point only called by
1002 * PHY setup routines.
1003 **/
1004static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1005{
1006 struct e1000_phy_info *phy = &hw->phy;
1007 s32 ret_val = 0;
1008 u16 data;
1009
1010 data = rd32(E1000_82580_PHY_POWER_MGMT);
1011
1012 if (active) {
1013 data |= E1000_82580_PM_D0_LPLU;
1014
1015 /* When LPLU is enabled, we should disable SmartSpeed */
1016 data &= ~E1000_82580_PM_SPD;
1017 } else {
1018 data &= ~E1000_82580_PM_D0_LPLU;
1019
1020 /*
1021 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1022 * during Dx states where the power conservation is most
1023 * important. During driver activity we should enable
1024 * SmartSpeed, so performance is maintained.
1025 */
1026 if (phy->smart_speed == e1000_smart_speed_on)
1027 data |= E1000_82580_PM_SPD;
1028 else if (phy->smart_speed == e1000_smart_speed_off)
1029 data &= ~E1000_82580_PM_SPD; }
1030
1031 wr32(E1000_82580_PHY_POWER_MGMT, data);
1032 return ret_val;
1033}
1034
1035/**
1036 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1037 * @hw: pointer to the HW structure
1038 * @active: boolean used to enable/disable lplu
1039 *
1040 * Success returns 0, Failure returns 1
1041 *
1042 * The low power link up (lplu) state is set to the power management level D3
1043 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1044 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1045 * is used during Dx states where the power conservation is most important.
1046 * During driver activity, SmartSpeed should be enabled so performance is
1047 * maintained.
1048 **/
1049s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1050{
1051 struct e1000_phy_info *phy = &hw->phy;
1052 s32 ret_val = 0;
1053 u16 data;
1054
1055 data = rd32(E1000_82580_PHY_POWER_MGMT);
1056
1057 if (!active) {
1058 data &= ~E1000_82580_PM_D3_LPLU;
1059 /*
1060 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1061 * during Dx states where the power conservation is most
1062 * important. During driver activity we should enable
1063 * SmartSpeed, so performance is maintained.
1064 */
1065 if (phy->smart_speed == e1000_smart_speed_on)
1066 data |= E1000_82580_PM_SPD;
1067 else if (phy->smart_speed == e1000_smart_speed_off)
1068 data &= ~E1000_82580_PM_SPD;
1069 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1070 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1071 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1072 data |= E1000_82580_PM_D3_LPLU;
1073 /* When LPLU is enabled, we should disable SmartSpeed */
1074 data &= ~E1000_82580_PM_SPD;
1075 }
1076
1077 wr32(E1000_82580_PHY_POWER_MGMT, data);
1078 return ret_val;
1079}
1080
9d5c8243 1081/**
733596be 1082 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 1083 * @hw: pointer to the HW structure
1084 *
652fff32 1085 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 1086 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1087 * Return successful if access grant bit set, else clear the request for
1088 * EEPROM access and return -E1000_ERR_NVM (-1).
1089 **/
1090static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1091{
1092 s32 ret_val;
1093
f96a8a0b 1094 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1095 if (ret_val)
1096 goto out;
1097
1098 ret_val = igb_acquire_nvm(hw);
1099
1100 if (ret_val)
f96a8a0b 1101 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1102
1103out:
1104 return ret_val;
1105}
1106
1107/**
733596be 1108 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 1109 * @hw: pointer to the HW structure
1110 *
1111 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1112 * then release the semaphores acquired.
1113 **/
1114static void igb_release_nvm_82575(struct e1000_hw *hw)
1115{
1116 igb_release_nvm(hw);
f96a8a0b 1117 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1118}
1119
1120/**
733596be 1121 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 1122 * @hw: pointer to the HW structure
1123 * @mask: specifies which semaphore to acquire
1124 *
1125 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1126 * will also specify which port we're acquiring the lock for.
1127 **/
1128static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1129{
1130 u32 swfw_sync;
1131 u32 swmask = mask;
1132 u32 fwmask = mask << 16;
1133 s32 ret_val = 0;
1134 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1135
1136 while (i < timeout) {
1137 if (igb_get_hw_semaphore(hw)) {
1138 ret_val = -E1000_ERR_SWFW_SYNC;
1139 goto out;
1140 }
1141
1142 swfw_sync = rd32(E1000_SW_FW_SYNC);
1143 if (!(swfw_sync & (fwmask | swmask)))
1144 break;
1145
1146 /*
1147 * Firmware currently using resource (fwmask)
1148 * or other software thread using resource (swmask)
1149 */
1150 igb_put_hw_semaphore(hw);
1151 mdelay(5);
1152 i++;
1153 }
1154
1155 if (i == timeout) {
652fff32 1156 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 1157 ret_val = -E1000_ERR_SWFW_SYNC;
1158 goto out;
1159 }
1160
1161 swfw_sync |= swmask;
1162 wr32(E1000_SW_FW_SYNC, swfw_sync);
1163
1164 igb_put_hw_semaphore(hw);
1165
1166out:
1167 return ret_val;
1168}
1169
1170/**
733596be 1171 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 1172 * @hw: pointer to the HW structure
1173 * @mask: specifies which semaphore to acquire
1174 *
1175 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1176 * will also specify which port we're releasing the lock for.
1177 **/
1178static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1179{
1180 u32 swfw_sync;
1181
1182 while (igb_get_hw_semaphore(hw) != 0);
1183 /* Empty */
1184
1185 swfw_sync = rd32(E1000_SW_FW_SYNC);
1186 swfw_sync &= ~mask;
1187 wr32(E1000_SW_FW_SYNC, swfw_sync);
1188
1189 igb_put_hw_semaphore(hw);
1190}
1191
1192/**
733596be 1193 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 1194 * @hw: pointer to the HW structure
1195 *
1196 * Read the management control register for the config done bit for
1197 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1198 * to read the config done bit, so an error is *ONLY* logged and returns
1199 * 0. If we were to return with error, EEPROM-less silicon
1200 * would not be able to be reset or change link.
1201 **/
1202static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1203{
1204 s32 timeout = PHY_CFG_TIMEOUT;
1205 s32 ret_val = 0;
1206 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1207
1208 if (hw->bus.func == 1)
1209 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 1210 else if (hw->bus.func == E1000_FUNC_2)
1211 mask = E1000_NVM_CFG_DONE_PORT_2;
1212 else if (hw->bus.func == E1000_FUNC_3)
1213 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 1214
1215 while (timeout) {
1216 if (rd32(E1000_EEMNGCTL) & mask)
1217 break;
1218 msleep(1);
1219 timeout--;
1220 }
1221 if (!timeout)
652fff32 1222 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 1223
1224 /* If EEPROM is not marked present, init the PHY manually */
1225 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1226 (hw->phy.type == e1000_phy_igp_3))
1227 igb_phy_init_script_igp3(hw);
1228
1229 return ret_val;
1230}
1231
1232/**
733596be 1233 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 1234 * @hw: pointer to the HW structure
1235 *
1236 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1237 * use the generic interface for determining link.
1238 **/
1239static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1240{
1241 s32 ret_val;
1242 u16 speed, duplex;
1243
70d92f86 1244 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 1245 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 1246 &duplex);
5d0932a5
AD		 1247 /*
1248 * Use this flag to determine if link needs to be checked or
1249 * not. If we have link clear the flag so that we do not
1250 * continue to check for link.
1251 */
1252 hw->mac.get_link_status = !hw->mac.serdes_has_link;
daf56e40
CW		 1253
1254 /* Configure Flow Control now that Auto-Neg has completed.
1255 * First, we need to restore the desired flow control
1256 * settings because we may have had to re-autoneg with a
1257 * different link partner.
1258 */
1259 ret_val = igb_config_fc_after_link_up(hw);
1260 if (ret_val)
1261 hw_dbg("Error configuring flow control\n");
5d0932a5 1262 } else {
9d5c8243 1263 ret_val = igb_check_for_copper_link(hw);
5d0932a5 1264 }
9d5c8243
AK		 1265
1266 return ret_val;
1267}
70d92f86 1268
88a268c1
NN		 1269/**
1270 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1271 * @hw: pointer to the HW structure
1272 **/
1273void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1274{
1275 u32 reg;
1276
1277
1278 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1279 !igb_sgmii_active_82575(hw))
1280 return;
1281
1282 /* Enable PCS to turn on link */
1283 reg = rd32(E1000_PCS_CFG0);
1284 reg |= E1000_PCS_CFG_PCS_EN;
1285 wr32(E1000_PCS_CFG0, reg);
1286
1287 /* Power up the laser */
1288 reg = rd32(E1000_CTRL_EXT);
1289 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1290 wr32(E1000_CTRL_EXT, reg);
1291
1292 /* flush the write to verify completion */
1293 wrfl();
1294 msleep(1);
1295}
1296
9d5c8243 1297/**
733596be 1298 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 1299 * @hw: pointer to the HW structure
1300 * @speed: stores the current speed
1301 * @duplex: stores the current duplex
1302 *
652fff32 1303 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 1304 * duplex, then store the values in the pointers provided.
1305 **/
1306static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1307 u16 *duplex)
1308{
1309 struct e1000_mac_info *mac = &hw->mac;
1310 u32 pcs;
1311
1312 /* Set up defaults for the return values of this function */
1313 mac->serdes_has_link = false;
1314 *speed = 0;
1315 *duplex = 0;
1316
1317 /*
1318 * Read the PCS Status register for link state. For non-copper mode,
1319 * the status register is not accurate. The PCS status register is
1320 * used instead.
1321 */
1322 pcs = rd32(E1000_PCS_LSTAT);
1323
1324 /*
1325 * The link up bit determines when link is up on autoneg. The sync ok
1326 * gets set once both sides sync up and agree upon link. Stable link
1327 * can be determined by checking for both link up and link sync ok
1328 */
1329 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1330 mac->serdes_has_link = true;
1331
1332 /* Detect and store PCS speed */
1333 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1334 *speed = SPEED_1000;
1335 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1336 *speed = SPEED_100;
1337 } else {
1338 *speed = SPEED_10;
1339 }
1340
1341 /* Detect and store PCS duplex */
1342 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1343 *duplex = FULL_DUPLEX;
1344 } else {
1345 *duplex = HALF_DUPLEX;
1346 }
1347 }
1348
1349 return 0;
1350}
1351
2d064c06 1352/**
2fb02a26 1353 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 1354 * @hw: pointer to the HW structure
9d5c8243 1355 *
2d064c06
AD		 1356 * In the case of fiber serdes, shut down optics and PCS on driver unload
1357 * when management pass thru is not enabled.
9d5c8243 1358 **/
2fb02a26 1359void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1360{
2d064c06
AD		 1361 u32 reg;
1362
53c992fa 1363 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 1364 igb_sgmii_active_82575(hw))
2d064c06
AD		 1365 return;
1366
53c992fa 1367 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 1368 /* Disable PCS to turn off link */
1369 reg = rd32(E1000_PCS_CFG0);
1370 reg &= ~E1000_PCS_CFG_PCS_EN;
1371 wr32(E1000_PCS_CFG0, reg);
1372
1373 /* shutdown the laser */
1374 reg = rd32(E1000_CTRL_EXT);
2fb02a26 1375 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 1376 wr32(E1000_CTRL_EXT, reg);
1377
1378 /* flush the write to verify completion */
1379 wrfl();
1380 msleep(1);
1381 }
9d5c8243
AK		 1382}
1383
1384/**
733596be 1385 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 1386 * @hw: pointer to the HW structure
1387 *
1388 * This resets the hardware into a known state. This is a
1389 * function pointer entry point called by the api module.
1390 **/
1391static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1392{
1393 u32 ctrl, icr;
1394 s32 ret_val;
1395
1396 /*
1397 * Prevent the PCI-E bus from sticking if there is no TLP connection
1398 * on the last TLP read/write transaction when MAC is reset.
1399 */
1400 ret_val = igb_disable_pcie_master(hw);
1401 if (ret_val)
652fff32 1402 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 1403
009bc06e
AD		 1404 /* set the completion timeout for interface */
1405 ret_val = igb_set_pcie_completion_timeout(hw);
1406 if (ret_val) {
1407 hw_dbg("PCI-E Set completion timeout has failed.\n");
1408 }
1409
652fff32 1410 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 1411 wr32(E1000_IMC, 0xffffffff);
1412
1413 wr32(E1000_RCTL, 0);
1414 wr32(E1000_TCTL, E1000_TCTL_PSP);
1415 wrfl();
1416
1417 msleep(10);
1418
1419 ctrl = rd32(E1000_CTRL);
1420
652fff32 1421 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 1422 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1423
1424 ret_val = igb_get_auto_rd_done(hw);
1425 if (ret_val) {
1426 /*
1427 * When auto config read does not complete, do not
1428 * return with an error. This can happen in situations
1429 * where there is no eeprom and prevents getting link.
1430 */
652fff32 1431 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 1432 }
1433
1434 /* If EEPROM is not present, run manual init scripts */
1435 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1436 igb_reset_init_script_82575(hw);
1437
1438 /* Clear any pending interrupt events. */
1439 wr32(E1000_IMC, 0xffffffff);
1440 icr = rd32(E1000_ICR);
1441
5ac16659
AD		 1442 /* Install any alternate MAC address into RAR0 */
1443 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 1444
1445 return ret_val;
1446}
1447
1448/**
733596be 1449 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 1450 * @hw: pointer to the HW structure
1451 *
1452 * This inits the hardware readying it for operation.
1453 **/
1454static s32 igb_init_hw_82575(struct e1000_hw *hw)
1455{
1456 struct e1000_mac_info *mac = &hw->mac;
1457 s32 ret_val;
1458 u16 i, rar_count = mac->rar_entry_count;
1459
1460 /* Initialize identification LED */
1461 ret_val = igb_id_led_init(hw);
1462 if (ret_val) {
652fff32 1463 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 1464 /* This is not fatal and we should not stop init due to this */
1465 }
1466
1467 /* Disabling VLAN filtering */
652fff32 1468 hw_dbg("Initializing the IEEE VLAN\n");
1128c756
CW		 1469 if (hw->mac.type == e1000_i350)
1470 igb_clear_vfta_i350(hw);
1471 else
1472 igb_clear_vfta(hw);
9d5c8243
AK		 1473
1474 /* Setup the receive address */
5ac16659
AD		 1475 igb_init_rx_addrs(hw, rar_count);
1476
9d5c8243 1477 /* Zero out the Multicast HASH table */
652fff32 1478 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1479 for (i = 0; i < mac->mta_reg_count; i++)
1480 array_wr32(E1000_MTA, i, 0);
1481
68d480c4
AD		 1482 /* Zero out the Unicast HASH table */
1483 hw_dbg("Zeroing the UTA\n");
1484 for (i = 0; i < mac->uta_reg_count; i++)
1485 array_wr32(E1000_UTA, i, 0);
1486
9d5c8243
AK		 1487 /* Setup link and flow control */
1488 ret_val = igb_setup_link(hw);
1489
1490 /*
1491 * Clear all of the statistics registers (clear on read). It is
1492 * important that we do this after we have tried to establish link
1493 * because the symbol error count will increment wildly if there
1494 * is no link.
1495 */
1496 igb_clear_hw_cntrs_82575(hw);
9d5c8243
AK		 1497 return ret_val;
1498}
1499
1500/**
733596be 1501 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1502 * @hw: pointer to the HW structure
1503 *
1504 * Configures the link for auto-neg or forced speed and duplex. Then we check
1505 * for link, once link is established calls to configure collision distance
1506 * and flow control are called.
1507 **/
1508static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1509{
12645a19 1510 u32 ctrl;
9d5c8243 1511 s32 ret_val;
867eb39e 1512 u32 phpm_reg;
9d5c8243
AK		 1513
1514 ctrl = rd32(E1000_CTRL);
1515 ctrl |= E1000_CTRL_SLU;
1516 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1517 wr32(E1000_CTRL, ctrl);
1518
867eb39e
CW		 1519 /* Clear Go Link Disconnect bit */
1520 if (hw->mac.type >= e1000_82580) {
1521 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1522 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1523 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1524 }
1525
2fb02a26
AD		 1526 ret_val = igb_setup_serdes_link_82575(hw);
1527 if (ret_val)
1528 goto out;
1529
1530 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1531 /* allow time for SFP cage time to power up phy */
1532 msleep(300);
1533
2fb02a26
AD		 1534 ret_val = hw->phy.ops.reset(hw);
1535 if (ret_val) {
1536 hw_dbg("Error resetting the PHY.\n");
1537 goto out;
1538 }
1539 }
9d5c8243 1540 switch (hw->phy.type) {
f96a8a0b 1541 case e1000_phy_i210:
9d5c8243 1542 case e1000_phy_m88:
308fb39a
JG		 1543 if (hw->phy.id == I347AT4_E_PHY_ID ||
1544 hw->phy.id == M88E1112_E_PHY_ID)
1545 ret_val = igb_copper_link_setup_m88_gen2(hw);
1546 else
1547 ret_val = igb_copper_link_setup_m88(hw);
9d5c8243
AK		 1548 break;
1549 case e1000_phy_igp_3:
1550 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1551 break;
bb2ac47b
AD		 1552 case e1000_phy_82580:
1553 ret_val = igb_copper_link_setup_82580(hw);
1554 break;
9d5c8243
AK		 1555 default:
1556 ret_val = -E1000_ERR_PHY;
1557 break;
1558 }
1559
1560 if (ret_val)
1561 goto out;
1562
81fadd81 1563 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1564out:
1565 return ret_val;
1566}
1567
1568/**
70d92f86 1569 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1570 * @hw: pointer to the HW structure
1571 *
70d92f86
AD		 1572 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1573 * used on copper connections where the serialized gigabit media independent
1574 * interface (sgmii), or serdes fiber is being used. Configures the link
1575 * for auto-negotiation or forces speed/duplex.
9d5c8243 1576 **/
2fb02a26 1577static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1578{
daf56e40 1579 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
bb2ac47b 1580 bool pcs_autoneg;
2c670b5b
CW		 1581 s32 ret_val = E1000_SUCCESS;
1582 u16 data;
2fb02a26
AD		 1583
1584 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1585 !igb_sgmii_active_82575(hw))
2c670b5b
CW		 1586 return ret_val;
1587
9d5c8243
AK		 1588
1589 /*
1590 * On the 82575, SerDes loopback mode persists until it is
1591 * explicitly turned off or a power cycle is performed. A read to
1592 * the register does not indicate its status. Therefore, we ensure
1593 * loopback mode is disabled during initialization.
1594 */
1595 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1596
2fb02a26 1597 /* power on the sfp cage if present */
bb2ac47b
AD		 1598 ctrl_ext = rd32(E1000_CTRL_EXT);
1599 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1600 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1601
1602 ctrl_reg = rd32(E1000_CTRL);
1603 ctrl_reg |= E1000_CTRL_SLU;
1604
1605 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1606 /* set both sw defined pins */
1607 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1608
1609 /* Set switch control to serdes energy detect */
1610 reg = rd32(E1000_CONNSW);
1611 reg |= E1000_CONNSW_ENRGSRC;
1612 wr32(E1000_CONNSW, reg);
1613 }
1614
1615 reg = rd32(E1000_PCS_LCTL);
1616
bb2ac47b
AD		 1617 /* default pcs_autoneg to the same setting as mac autoneg */
1618 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1619
bb2ac47b
AD		 1620 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1621 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1622 /* sgmii mode lets the phy handle forcing speed/duplex */
1623 pcs_autoneg = true;
1624 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1625 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1626 break;
1627 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1628 /* disable PCS autoneg and support parallel detect only */
1629 pcs_autoneg = false;
1630 default:
2c670b5b
CW		 1631 if (hw->mac.type == e1000_82575 ||
1632 hw->mac.type == e1000_82576) {
1633 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1634 if (ret_val) {
1635 printk(KERN_DEBUG "NVM Read Error\n\n");
1636 return ret_val;
1637 }
1638
1639 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1640 pcs_autoneg = false;
1641 }
1642
bb2ac47b
AD		 1643 /*
1644 * non-SGMII modes only supports a speed of 1000/Full for the
1645 * link so it is best to just force the MAC and let the pcs
1646 * link either autoneg or be forced to 1000/Full
1647 */
2fb02a26
AD		 1648 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1649 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1650
1651 /* set speed of 1000/Full if speed/duplex is forced */
1652 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1653 break;
921aa749
AD		 1654 }
1655
2fb02a26 1656 wr32(E1000_CTRL, ctrl_reg);
9d5c8243
AK		 1657
1658 /*
1659 * New SerDes mode allows for forcing speed or autonegotiating speed
1660 * at 1gb. Autoneg should be default set by most drivers. This is the
1661 * mode that will be compatible with older link partners and switches.
1662 * However, both are supported by the hardware and some drivers/tools.
1663 */
9d5c8243
AK		 1664 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1665 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1666
bb2ac47b 1667 if (pcs_autoneg) {
9d5c8243 1668 /* Set PCS register for autoneg */
bb2ac47b 1669 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1670 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
daf56e40
CW		 1671
1672 /* Disable force flow control for autoneg */
1673 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1674
1675 /* Configure flow control advertisement for autoneg */
1676 anadv_reg = rd32(E1000_PCS_ANADV);
1677 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1678 switch (hw->fc.requested_mode) {
1679 case e1000_fc_full:
1680 case e1000_fc_rx_pause:
1681 anadv_reg |= E1000_TXCW_ASM_DIR;
1682 anadv_reg |= E1000_TXCW_PAUSE;
1683 break;
1684 case e1000_fc_tx_pause:
1685 anadv_reg |= E1000_TXCW_ASM_DIR;
1686 break;
1687 default:
1688 break;
1689 }
1690 wr32(E1000_PCS_ANADV, anadv_reg);
1691
bb2ac47b 1692 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1693 } else {
bb2ac47b 1694 /* Set PCS register for forced link */
d68caec6 1695 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b 1696
daf56e40
CW		 1697 /* Force flow control for forced link */
1698 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1699
bb2ac47b 1700 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1701 }
726c09e7 1702
9d5c8243
AK		 1703 wr32(E1000_PCS_LCTL, reg);
1704
daf56e40 1705 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
2fb02a26 1706 igb_force_mac_fc(hw);
9d5c8243 1707
2c670b5b 1708 return ret_val;
9d5c8243
AK		 1709}
1710
1711/**
733596be 1712 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1713 * @hw: pointer to the HW structure
1714 *
1715 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1716 * which can be enabled for use in the embedded applications. Simply
1717 * return the current state of the sgmii interface.
1718 **/
1719static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1720{
c1889bfe 1721 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1722 return dev_spec->sgmii_active;
9d5c8243
AK		 1723}
1724
1725/**
733596be 1726 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1727 * @hw: pointer to the HW structure
1728 *
1729 * Inits recommended HW defaults after a reset when there is no EEPROM
1730 * detected. This is only for the 82575.
1731 **/
1732static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1733{
1734 if (hw->mac.type == e1000_82575) {
652fff32 1735 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1736 /* SerDes configuration via SERDESCTRL */
1737 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1738 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1739 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1740 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1741
1742 /* CCM configuration via CCMCTL register */
1743 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1744 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1745
1746 /* PCIe lanes configuration */
1747 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1748 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1749 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1750 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1751
1752 /* PCIe PLL Configuration */
1753 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1754 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1755 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1756 }
1757
1758 return 0;
1759}
1760
1761/**
733596be 1762 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1763 * @hw: pointer to the HW structure
1764 **/
1765static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1766{
1767 s32 ret_val = 0;
1768
22896639
AD		 1769 /*
1770 * If there's an alternate MAC address place it in RAR0
1771 * so that it will override the Si installed default perm
1772 * address.
1773 */
1774 ret_val = igb_check_alt_mac_addr(hw);
1775 if (ret_val)
1776 goto out;
1777
1778 ret_val = igb_read_mac_addr(hw);
9d5c8243 1779
22896639 1780out:
9d5c8243
AK		 1781 return ret_val;
1782}
1783
88a268c1
NN		 1784/**
1785 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1786 * @hw: pointer to the HW structure
1787 *
1788 * In the case of a PHY power down to save power, or to turn off link during a
1789 * driver unload, or wake on lan is not enabled, remove the link.
1790 **/
1791void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1792{
1793 /* If the management interface is not enabled, then power down */
1794 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1795 igb_power_down_phy_copper(hw);
88a268c1
NN		 1796}
1797
9d5c8243 1798/**
733596be 1799 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1800 * @hw: pointer to the HW structure
1801 *
1802 * Clears the hardware counters by reading the counter registers.
1803 **/
1804static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1805{
9d5c8243
AK		 1806 igb_clear_hw_cntrs_base(hw);
1807
cc9073bb
AD		 1808 rd32(E1000_PRC64);
1809 rd32(E1000_PRC127);
1810 rd32(E1000_PRC255);
1811 rd32(E1000_PRC511);
1812 rd32(E1000_PRC1023);
1813 rd32(E1000_PRC1522);
1814 rd32(E1000_PTC64);
1815 rd32(E1000_PTC127);
1816 rd32(E1000_PTC255);
1817 rd32(E1000_PTC511);
1818 rd32(E1000_PTC1023);
1819 rd32(E1000_PTC1522);
1820
1821 rd32(E1000_ALGNERRC);
1822 rd32(E1000_RXERRC);
1823 rd32(E1000_TNCRS);
1824 rd32(E1000_CEXTERR);
1825 rd32(E1000_TSCTC);
1826 rd32(E1000_TSCTFC);
1827
1828 rd32(E1000_MGTPRC);
1829 rd32(E1000_MGTPDC);
1830 rd32(E1000_MGTPTC);
1831
1832 rd32(E1000_IAC);
1833 rd32(E1000_ICRXOC);
1834
1835 rd32(E1000_ICRXPTC);
1836 rd32(E1000_ICRXATC);
1837 rd32(E1000_ICTXPTC);
1838 rd32(E1000_ICTXATC);
1839 rd32(E1000_ICTXQEC);
1840 rd32(E1000_ICTXQMTC);
1841 rd32(E1000_ICRXDMTC);
1842
1843 rd32(E1000_CBTMPC);
1844 rd32(E1000_HTDPMC);
1845 rd32(E1000_CBRMPC);
1846 rd32(E1000_RPTHC);
1847 rd32(E1000_HGPTC);
1848 rd32(E1000_HTCBDPC);
1849 rd32(E1000_HGORCL);
1850 rd32(E1000_HGORCH);
1851 rd32(E1000_HGOTCL);
1852 rd32(E1000_HGOTCH);
1853 rd32(E1000_LENERRS);
9d5c8243
AK		 1854
1855 /* This register should not be read in copper configurations */
2fb02a26
AD		 1856 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1857 igb_sgmii_active_82575(hw))
cc9073bb 1858 rd32(E1000_SCVPC);
9d5c8243
AK		 1859}
1860
662d7205
AD		 1861/**
1862 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1863 * @hw: pointer to the HW structure
1864 *
1865 * After rx enable if managability is enabled then there is likely some
1866 * bad data at the start of the fifo and possibly in the DMA fifo. This
1867 * function clears the fifos and flushes any packets that came in as rx was
1868 * being enabled.
1869 **/
1870void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1871{
1872 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1873 int i, ms_wait;
1874
1875 if (hw->mac.type != e1000_82575 ||
1876 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1877 return;
1878
1879 /* Disable all RX queues */
1880 for (i = 0; i < 4; i++) {
1881 rxdctl[i] = rd32(E1000_RXDCTL(i));
1882 wr32(E1000_RXDCTL(i),
1883 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1884 }
1885 /* Poll all queues to verify they have shut down */
1886 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1887 msleep(1);
1888 rx_enabled = 0;
1889 for (i = 0; i < 4; i++)
1890 rx_enabled |= rd32(E1000_RXDCTL(i));
1891 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1892 break;
1893 }
1894
1895 if (ms_wait == 10)
1896 hw_dbg("Queue disable timed out after 10ms\n");
1897
1898 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1899 * incoming packets are rejected. Set enable and wait 2ms so that
1900 * any packet that was coming in as RCTL.EN was set is flushed
1901 */
1902 rfctl = rd32(E1000_RFCTL);
1903 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1904
1905 rlpml = rd32(E1000_RLPML);
1906 wr32(E1000_RLPML, 0);
1907
1908 rctl = rd32(E1000_RCTL);
1909 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1910 temp_rctl |= E1000_RCTL_LPE;
1911
1912 wr32(E1000_RCTL, temp_rctl);
1913 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1914 wrfl();
1915 msleep(2);
1916
1917 /* Enable RX queues that were previously enabled and restore our
1918 * previous state
1919 */
1920 for (i = 0; i < 4; i++)
1921 wr32(E1000_RXDCTL(i), rxdctl[i]);
1922 wr32(E1000_RCTL, rctl);
1923 wrfl();
1924
1925 wr32(E1000_RLPML, rlpml);
1926 wr32(E1000_RFCTL, rfctl);
1927
1928 /* Flush receive errors generated by workaround */
1929 rd32(E1000_ROC);
1930 rd32(E1000_RNBC);
1931 rd32(E1000_MPC);
1932}
1933
009bc06e
AD		 1934/**
1935 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1936 * @hw: pointer to the HW structure
1937 *
1938 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1939 * however the hardware default for these parts is 500us to 1ms which is less
1940 * than the 10ms recommended by the pci-e spec. To address this we need to
1941 * increase the value to either 10ms to 200ms for capability version 1 config,
1942 * or 16ms to 55ms for version 2.
1943 **/
1944static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1945{
1946 u32 gcr = rd32(E1000_GCR);
1947 s32 ret_val = 0;
1948 u16 pcie_devctl2;
1949
1950 /* only take action if timeout value is defaulted to 0 */
1951 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1952 goto out;
1953
1954 /*
1955 * if capababilities version is type 1 we can write the
1956 * timeout of 10ms to 200ms through the GCR register
1957 */
1958 if (!(gcr & E1000_GCR_CAP_VER2)) {
1959 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1960 goto out;
1961 }
1962
1963 /*
1964 * for version 2 capabilities we need to write the config space
1965 * directly in order to set the completion timeout value for
1966 * 16ms to 55ms
1967 */
1968 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1969 &pcie_devctl2);
1970 if (ret_val)
1971 goto out;
1972
1973 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1974
1975 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1976 &pcie_devctl2);
1977out:
1978 /* disable completion timeout resend */
1979 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1980
1981 wr32(E1000_GCR, gcr);
1982 return ret_val;
1983}
1984
13800469
GR		 1985/**
1986 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1987 * @hw: pointer to the hardware struct
1988 * @enable: state to enter, either enabled or disabled
1989 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1990 *
1991 * enables/disables L2 switch anti-spoofing functionality.
1992 **/
1993void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1994{
1995 u32 dtxswc;
1996
1997 switch (hw->mac.type) {
1998 case e1000_82576:
1999 case e1000_i350:
2000 dtxswc = rd32(E1000_DTXSWC);
2001 if (enable) {
2002 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2003 E1000_DTXSWC_VLAN_SPOOF_MASK);
2004 /* The PF can spoof - it has to in order to
2005 * support emulation mode NICs */
2006 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2007 } else {
2008 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2009 E1000_DTXSWC_VLAN_SPOOF_MASK);
2010 }
2011 wr32(E1000_DTXSWC, dtxswc);
2012 break;
2013 default:
2014 break;
2015 }
2016}
2017
4ae196df
AD		 2018/**
2019 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2020 * @hw: pointer to the hardware struct
2021 * @enable: state to enter, either enabled or disabled
2022 *
2023 * enables/disables L2 switch loopback functionality.
2024 **/
2025void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2026{
ca2e3e7e
AA		 2027 u32 dtxswc;
2028
2029 switch (hw->mac.type) {
2030 case e1000_82576:
2031 dtxswc = rd32(E1000_DTXSWC);
2032 if (enable)
2033 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2034 else
2035 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2036 wr32(E1000_DTXSWC, dtxswc);
2037 break;
2038 case e1000_i350:
2039 dtxswc = rd32(E1000_TXSWC);
2040 if (enable)
2041 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2042 else
2043 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2044 wr32(E1000_TXSWC, dtxswc);
2045 break;
2046 default:
2047 /* Currently no other hardware supports loopback */
2048 break;
2049 }
4ae196df 2050
4ae196df 2051
4ae196df
AD		 2052}
2053
2054/**
2055 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2056 * @hw: pointer to the hardware struct
2057 * @enable: state to enter, either enabled or disabled
2058 *
2059 * enables/disables replication of packets across multiple pools.
2060 **/
2061void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2062{
2063 u32 vt_ctl = rd32(E1000_VT_CTL);
2064
2065 if (enable)
2066 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2067 else
2068 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2069
2070 wr32(E1000_VT_CTL, vt_ctl);
2071}
2072
bb2ac47b
AD		 2073/**
2074 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2075 * @hw: pointer to the HW structure
2076 * @offset: register offset to be read
2077 * @data: pointer to the read data
2078 *
2079 * Reads the MDI control register in the PHY at offset and stores the
2080 * information read to data.
2081 **/
2082static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2083{
bb2ac47b
AD		 2084 s32 ret_val;
2085
2086
2087 ret_val = hw->phy.ops.acquire(hw);
2088 if (ret_val)
2089 goto out;
2090
bb2ac47b
AD		 2091 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2092
2093 hw->phy.ops.release(hw);
2094
2095out:
2096 return ret_val;
2097}
2098
2099/**
2100 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2101 * @hw: pointer to the HW structure
2102 * @offset: register offset to write to
2103 * @data: data to write to register at offset
2104 *
2105 * Writes data to MDI control register in the PHY at offset.
2106 **/
2107static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2108{
bb2ac47b
AD		 2109 s32 ret_val;
2110
2111
2112 ret_val = hw->phy.ops.acquire(hw);
2113 if (ret_val)
2114 goto out;
2115
bb2ac47b
AD		 2116 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2117
2118 hw->phy.ops.release(hw);
2119
2120out:
2121 return ret_val;
2122}
2123
08451e25
NN		 2124/**
2125 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2126 * @hw: pointer to the HW structure
2127 *
2128 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2129 * the values found in the EEPROM. This addresses an issue in which these
2130 * bits are not restored from EEPROM after reset.
2131 **/
2132static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2133{
2134 s32 ret_val = 0;
2135 u32 mdicnfg;
1b5dda33 2136 u16 nvm_data = 0;
08451e25
NN		 2137
2138 if (hw->mac.type != e1000_82580)
2139 goto out;
2140 if (!igb_sgmii_active_82575(hw))
2141 goto out;
2142
2143 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2144 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2145 &nvm_data);
2146 if (ret_val) {
2147 hw_dbg("NVM Read Error\n");
2148 goto out;
2149 }
2150
2151 mdicnfg = rd32(E1000_MDICNFG);
2152 if (nvm_data & NVM_WORD24_EXT_MDIO)
2153 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2154 if (nvm_data & NVM_WORD24_COM_MDIO)
2155 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2156 wr32(E1000_MDICNFG, mdicnfg);
2157out:
2158 return ret_val;
2159}
2160
bb2ac47b
AD		 2161/**
2162 * igb_reset_hw_82580 - Reset hardware
2163 * @hw: pointer to the HW structure
2164 *
2165 * This resets function or entire device (all ports, etc.)
2166 * to a known state.
2167 **/
2168static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2169{
2170 s32 ret_val = 0;
2171 /* BH SW mailbox bit in SW_FW_SYNC */
2172 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2173 u32 ctrl, icr;
2174 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2175
2176
2177 hw->dev_spec._82575.global_device_reset = false;
2178
a0483e2e
CW		 2179 /* due to hw errata, global device reset doesn't always
2180 * work on 82580
2181 */
2182 if (hw->mac.type == e1000_82580)
2183 global_device_reset = false;
2184
bb2ac47b
AD		 2185 /* Get current control state. */
2186 ctrl = rd32(E1000_CTRL);
2187
2188 /*
2189 * Prevent the PCI-E bus from sticking if there is no TLP connection
2190 * on the last TLP read/write transaction when MAC is reset.
2191 */
2192 ret_val = igb_disable_pcie_master(hw);
2193 if (ret_val)
2194 hw_dbg("PCI-E Master disable polling has failed.\n");
2195
2196 hw_dbg("Masking off all interrupts\n");
2197 wr32(E1000_IMC, 0xffffffff);
2198 wr32(E1000_RCTL, 0);
2199 wr32(E1000_TCTL, E1000_TCTL_PSP);
2200 wrfl();
2201
2202 msleep(10);
2203
2204 /* Determine whether or not a global dev reset is requested */
2205 if (global_device_reset &&
f96a8a0b 2206 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
bb2ac47b
AD		 2207 global_device_reset = false;
2208
2209 if (global_device_reset &&
2210 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2211 ctrl |= E1000_CTRL_DEV_RST;
2212 else
2213 ctrl |= E1000_CTRL_RST;
2214
2215 wr32(E1000_CTRL, ctrl);
064b4330 2216 wrfl();
bb2ac47b
AD		 2217
2218 /* Add delay to insure DEV_RST has time to complete */
2219 if (global_device_reset)
2220 msleep(5);
2221
2222 ret_val = igb_get_auto_rd_done(hw);
2223 if (ret_val) {
2224 /*
2225 * When auto config read does not complete, do not
2226 * return with an error. This can happen in situations
2227 * where there is no eeprom and prevents getting link.
2228 */
2229 hw_dbg("Auto Read Done did not complete\n");
2230 }
2231
2232 /* If EEPROM is not present, run manual init scripts */
2233 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
2234 igb_reset_init_script_82575(hw);
2235
2236 /* clear global device reset status bit */
2237 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2238
2239 /* Clear any pending interrupt events. */
2240 wr32(E1000_IMC, 0xffffffff);
2241 icr = rd32(E1000_ICR);
2242
08451e25
NN		 2243 ret_val = igb_reset_mdicnfg_82580(hw);
2244 if (ret_val)
2245 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2246
bb2ac47b
AD		 2247 /* Install any alternate MAC address into RAR0 */
2248 ret_val = igb_check_alt_mac_addr(hw);
2249
2250 /* Release semaphore */
2251 if (global_device_reset)
f96a8a0b 2252 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
bb2ac47b
AD		 2253
2254 return ret_val;
2255}
2256
2257/**
2258 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2259 * @data: data received by reading RXPBS register
2260 *
2261 * The 82580 uses a table based approach for packet buffer allocation sizes.
2262 * This function converts the retrieved value into the correct table value
2263 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2264 * 0x0 36 72 144 1 2 4 8 16
2265 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2266 */
2267u16 igb_rxpbs_adjust_82580(u32 data)
2268{
2269 u16 ret_val = 0;
2270
2271 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2272 ret_val = e1000_82580_rxpbs_table[data];
2273
2274 return ret_val;
2275}
2276
4322e561
CW		 2277/**
2278 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2279 * checksum
2280 * @hw: pointer to the HW structure
2281 * @offset: offset in words of the checksum protected region
2282 *
2283 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2284 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2285 **/
bed45a6e
ET		 2286static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2287 u16 offset)
4322e561
CW		 2288{
2289 s32 ret_val = 0;
2290 u16 checksum = 0;
2291 u16 i, nvm_data;
2292
2293 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2294 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2295 if (ret_val) {
2296 hw_dbg("NVM Read Error\n");
2297 goto out;
2298 }
2299 checksum += nvm_data;
2300 }
2301
2302 if (checksum != (u16) NVM_SUM) {
2303 hw_dbg("NVM Checksum Invalid\n");
2304 ret_val = -E1000_ERR_NVM;
2305 goto out;
2306 }
2307
2308out:
2309 return ret_val;
2310}
2311
2312/**
2313 * igb_update_nvm_checksum_with_offset - Update EEPROM
2314 * checksum
2315 * @hw: pointer to the HW structure
2316 * @offset: offset in words of the checksum protected region
2317 *
2318 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2319 * up to the checksum. Then calculates the EEPROM checksum and writes the
2320 * value to the EEPROM.
2321 **/
bed45a6e 2322static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
4322e561
CW		 2323{
2324 s32 ret_val;
2325 u16 checksum = 0;
2326 u16 i, nvm_data;
2327
2328 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2329 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2330 if (ret_val) {
2331 hw_dbg("NVM Read Error while updating checksum.\n");
2332 goto out;
2333 }
2334 checksum += nvm_data;
2335 }
2336 checksum = (u16) NVM_SUM - checksum;
2337 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2338 &checksum);
2339 if (ret_val)
2340 hw_dbg("NVM Write Error while updating checksum.\n");
2341
2342out:
2343 return ret_val;
2344}
2345
2346/**
2347 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2348 * @hw: pointer to the HW structure
2349 *
2350 * Calculates the EEPROM section checksum by reading/adding each word of
2351 * the EEPROM and then verifies that the sum of the EEPROM is
2352 * equal to 0xBABA.
2353 **/
2354static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2355{
2356 s32 ret_val = 0;
2357 u16 eeprom_regions_count = 1;
2358 u16 j, nvm_data;
2359 u16 nvm_offset;
2360
2361 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2362 if (ret_val) {
2363 hw_dbg("NVM Read Error\n");
2364 goto out;
2365 }
2366
2367 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
34a0326e 2368 /* if checksums compatibility bit is set validate checksums
4322e561
CW		 2369 * for all 4 ports. */
2370 eeprom_regions_count = 4;
2371 }
2372
2373 for (j = 0; j < eeprom_regions_count; j++) {
2374 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2375 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2376 nvm_offset);
2377 if (ret_val != 0)
2378 goto out;
2379 }
2380
2381out:
2382 return ret_val;
2383}
2384
2385/**
2386 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2387 * @hw: pointer to the HW structure
2388 *
2389 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2390 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2391 * checksum and writes the value to the EEPROM.
2392 **/
2393static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2394{
2395 s32 ret_val;
2396 u16 j, nvm_data;
2397 u16 nvm_offset;
2398
2399 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2400 if (ret_val) {
2401 hw_dbg("NVM Read Error while updating checksum"
2402 " compatibility bit.\n");
2403 goto out;
2404 }
2405
2406 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2407 /* set compatibility bit to validate checksums appropriately */
2408 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2409 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2410 &nvm_data);
2411 if (ret_val) {
2412 hw_dbg("NVM Write Error while updating checksum"
2413 " compatibility bit.\n");
2414 goto out;
2415 }
2416 }
2417
2418 for (j = 0; j < 4; j++) {
2419 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2420 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2421 if (ret_val)
2422 goto out;
2423 }
2424
2425out:
2426 return ret_val;
2427}
2428
2429/**
2430 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2431 * @hw: pointer to the HW structure
2432 *
2433 * Calculates the EEPROM section checksum by reading/adding each word of
2434 * the EEPROM and then verifies that the sum of the EEPROM is
2435 * equal to 0xBABA.
2436 **/
2437static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2438{
2439 s32 ret_val = 0;
2440 u16 j;
2441 u16 nvm_offset;
2442
2443 for (j = 0; j < 4; j++) {
2444 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2445 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2446 nvm_offset);
2447 if (ret_val != 0)
2448 goto out;
2449 }
2450
2451out:
2452 return ret_val;
2453}
2454
2455/**
2456 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2457 * @hw: pointer to the HW structure
2458 *
2459 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2460 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2461 * checksum and writes the value to the EEPROM.
2462 **/
2463static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2464{
2465 s32 ret_val = 0;
2466 u16 j;
2467 u16 nvm_offset;
2468
2469 for (j = 0; j < 4; j++) {
2470 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2471 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2472 if (ret_val != 0)
2473 goto out;
2474 }
2475
2476out:
2477 return ret_val;
2478}
34a0326e 2479
09b068d4
CW		 2480/**
2481 * igb_set_eee_i350 - Enable/disable EEE support
2482 * @hw: pointer to the HW structure
2483 *
2484 * Enable/disable EEE based on setting in dev_spec structure.
2485 *
2486 **/
2487s32 igb_set_eee_i350(struct e1000_hw *hw)
2488{
2489 s32 ret_val = 0;
e5461112 2490 u32 ipcnfg, eeer;
09b068d4 2491
e5461112
AA		 2492 if ((hw->mac.type < e1000_i350) ||
2493 (hw->phy.media_type != e1000_media_type_copper))
09b068d4
CW		 2494 goto out;
2495 ipcnfg = rd32(E1000_IPCNFG);
2496 eeer = rd32(E1000_EEER);
2497
2498 /* enable or disable per user setting */
2499 if (!(hw->dev_spec._82575.eee_disable)) {
40b20122
CW		 2500 u32 eee_su = rd32(E1000_EEE_SU);
2501
2502 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2503 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
09b068d4
CW		 2504 E1000_EEER_LPI_FC);
2505
40b20122
CW		 2506 /* This bit should not be set in normal operation. */
2507 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2508 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2509
e5461112 2510
09b068d4
CW		 2511 } else {
2512 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2513 E1000_IPCNFG_EEE_100M_AN);
2514 eeer &= ~(E1000_EEER_TX_LPI_EN |
2515 E1000_EEER_RX_LPI_EN |
2516 E1000_EEER_LPI_FC);
2517 }
2518 wr32(E1000_IPCNFG, ipcnfg);
2519 wr32(E1000_EEER, eeer);
e5461112
AA		 2520 rd32(E1000_IPCNFG);
2521 rd32(E1000_EEER);
09b068d4
CW		 2522out:
2523
2524 return ret_val;
2525}
4322e561 2526
e428893b
CW		 2527static const u8 e1000_emc_temp_data[4] = {
2528 E1000_EMC_INTERNAL_DATA,
2529 E1000_EMC_DIODE1_DATA,
2530 E1000_EMC_DIODE2_DATA,
2531 E1000_EMC_DIODE3_DATA
2532};
2533static const u8 e1000_emc_therm_limit[4] = {
2534 E1000_EMC_INTERNAL_THERM_LIMIT,
2535 E1000_EMC_DIODE1_THERM_LIMIT,
2536 E1000_EMC_DIODE2_THERM_LIMIT,
2537 E1000_EMC_DIODE3_THERM_LIMIT
2538};
2539
2540/* igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2541 * @hw: pointer to hardware structure
2542 *
2543 * Updates the temperatures in mac.thermal_sensor_data
2544 */
2545s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2546{
2547 s32 status = E1000_SUCCESS;
2548 u16 ets_offset;
2549 u16 ets_cfg;
2550 u16 ets_sensor;
2551 u8 num_sensors;
2552 u8 sensor_index;
2553 u8 sensor_location;
2554 u8 i;
2555 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2556
2557 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2558 return E1000_NOT_IMPLEMENTED;
2559
2560 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2561
2562 /* Return the internal sensor only if ETS is unsupported */
2563 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2564 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2565 return status;
2566
2567 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2568 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2569 != NVM_ETS_TYPE_EMC)
2570 return E1000_NOT_IMPLEMENTED;
2571
2572 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2573 if (num_sensors > E1000_MAX_SENSORS)
2574 num_sensors = E1000_MAX_SENSORS;
2575
2576 for (i = 1; i < num_sensors; i++) {
2577 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2578 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2579 NVM_ETS_DATA_INDEX_SHIFT);
2580 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2581 NVM_ETS_DATA_LOC_SHIFT);
2582
2583 if (sensor_location != 0)
2584 hw->phy.ops.read_i2c_byte(hw,
2585 e1000_emc_temp_data[sensor_index],
2586 E1000_I2C_THERMAL_SENSOR_ADDR,
2587 &data->sensor[i].temp);
2588 }
2589 return status;
2590}
2591
2592/* igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2593 * @hw: pointer to hardware structure
2594 *
2595 * Sets the thermal sensor thresholds according to the NVM map
2596 * and save off the threshold and location values into mac.thermal_sensor_data
2597 */
2598s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2599{
2600 s32 status = E1000_SUCCESS;
2601 u16 ets_offset;
2602 u16 ets_cfg;
2603 u16 ets_sensor;
2604 u8 low_thresh_delta;
2605 u8 num_sensors;
2606 u8 sensor_index;
2607 u8 sensor_location;
2608 u8 therm_limit;
2609 u8 i;
2610 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2611
2612 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2613 return E1000_NOT_IMPLEMENTED;
2614
2615 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2616
2617 data->sensor[0].location = 0x1;
2618 data->sensor[0].caution_thresh =
2619 (rd32(E1000_THHIGHTC) & 0xFF);
2620 data->sensor[0].max_op_thresh =
2621 (rd32(E1000_THLOWTC) & 0xFF);
2622
2623 /* Return the internal sensor only if ETS is unsupported */
2624 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2625 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2626 return status;
2627
2628 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2629 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2630 != NVM_ETS_TYPE_EMC)
2631 return E1000_NOT_IMPLEMENTED;
2632
2633 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2634 NVM_ETS_LTHRES_DELTA_SHIFT);
2635 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2636
2637 for (i = 1; i <= num_sensors; i++) {
2638 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2639 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2640 NVM_ETS_DATA_INDEX_SHIFT);
2641 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2642 NVM_ETS_DATA_LOC_SHIFT);
2643 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2644
2645 hw->phy.ops.write_i2c_byte(hw,
2646 e1000_emc_therm_limit[sensor_index],
2647 E1000_I2C_THERMAL_SENSOR_ADDR,
2648 therm_limit);
2649
2650 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2651 data->sensor[i].location = sensor_location;
2652 data->sensor[i].caution_thresh = therm_limit;
2653 data->sensor[i].max_op_thresh = therm_limit -
2654 low_thresh_delta;
2655 }
2656 }
2657 return status;
2658}
2659
9d5c8243 2660static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 2661 .init_hw = igb_init_hw_82575,
2662 .check_for_link = igb_check_for_link_82575,
2d064c06 2663 .rar_set = igb_rar_set,
9d5c8243
AK		 2664 .read_mac_addr = igb_read_mac_addr_82575,
2665 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
e428893b
CW		 2666#ifdef CONFIG_IGB_HWMON
2667 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2668 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2669#endif
9d5c8243
AK		 2670};
2671
2672static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 2673 .acquire = igb_acquire_phy_82575,
9d5c8243 2674 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 2675 .release = igb_release_phy_82575,
441fc6fd
CW		 2676 .write_i2c_byte = igb_write_i2c_byte,
2677 .read_i2c_byte = igb_read_i2c_byte,
9d5c8243
AK		 2678};
2679
2680static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 2681 .acquire = igb_acquire_nvm_82575,
2682 .read = igb_read_nvm_eerd,
2683 .release = igb_release_nvm_82575,
2684 .write = igb_write_nvm_spi,
9d5c8243
AK		 2685};
2686
2687const struct e1000_info e1000_82575_info = {
2688 .get_invariants = igb_get_invariants_82575,
2689 .mac_ops = &e1000_mac_ops_82575,
2690 .phy_ops = &e1000_phy_ops_82575,
2691 .nvm_ops = &e1000_nvm_ops_82575,
2692};
2693
Linux kernel - Deliverables
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