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igb: Refactor of init_nvm_params
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
82bbcdeb
JP		 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
9d5c8243 34#include <linux/types.h>
2d064c06 35#include <linux/if_ether.h>
441fc6fd 36#include <linux/i2c.h>
9d5c8243
AK		 37
38#include "e1000_mac.h"
39#include "e1000_82575.h"
f96a8a0b 40#include "e1000_i210.h"
9d5c8243
AK		 41
42static s32 igb_get_invariants_82575(struct e1000_hw *);
43static s32 igb_acquire_phy_82575(struct e1000_hw *);
44static void igb_release_phy_82575(struct e1000_hw *);
45static s32 igb_acquire_nvm_82575(struct e1000_hw *);
46static void igb_release_nvm_82575(struct e1000_hw *);
47static s32 igb_check_for_link_82575(struct e1000_hw *);
48static s32 igb_get_cfg_done_82575(struct e1000_hw *);
49static s32 igb_init_hw_82575(struct e1000_hw *);
50static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
51static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 52static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
53static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 54static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 55static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243 56static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
da02cde1
CW		 57static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
58static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
9d5c8243 59static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 60static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 61static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
62static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
63static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 64static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
65 u16 *);
66static s32 igb_get_phy_id_82575(struct e1000_hw *);
67static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
68static bool igb_sgmii_active_82575(struct e1000_hw *);
69static s32 igb_reset_init_script_82575(struct e1000_hw *);
70static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 71static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
99870a73 72static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
4322e561
CW		 73static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
74static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
4322e561
CW		 75static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
76static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
bb2ac47b
AD		 77static const u16 e1000_82580_rxpbs_table[] =
78 { 36, 72, 144, 1, 2, 4, 8, 16,
79 35, 70, 140 };
80#define E1000_82580_RXPBS_TABLE_SIZE \
81 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
82
4085f746
NN		 83/**
84 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
85 * @hw: pointer to the HW structure
86 *
87 * Called to determine if the I2C pins are being used for I2C or as an
88 * external MDIO interface since the two options are mutually exclusive.
89 **/
90static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
91{
92 u32 reg = 0;
93 bool ext_mdio = false;
94
95 switch (hw->mac.type) {
96 case e1000_82575:
97 case e1000_82576:
98 reg = rd32(E1000_MDIC);
99 ext_mdio = !!(reg & E1000_MDIC_DEST);
100 break;
101 case e1000_82580:
102 case e1000_i350:
ceb5f13b 103 case e1000_i354:
f96a8a0b
CW		 104 case e1000_i210:
105 case e1000_i211:
4085f746
NN		 106 reg = rd32(E1000_MDICNFG);
107 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
108 break;
109 default:
110 break;
111 }
112 return ext_mdio;
113}
114
73bfcd9a
AA		 115/**
116 * igb_init_phy_params_82575 - Init PHY func ptrs.
117 * @hw: pointer to the HW structure
118 **/
119static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
120{
121 struct e1000_phy_info *phy = &hw->phy;
122 s32 ret_val = 0;
123 u32 ctrl_ext;
124
125 if (hw->phy.media_type != e1000_media_type_copper) {
126 phy->type = e1000_phy_none;
127 goto out;
128 }
129
130 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
131 phy->reset_delay_us = 100;
132
133 ctrl_ext = rd32(E1000_CTRL_EXT);
134
135 if (igb_sgmii_active_82575(hw)) {
136 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
137 ctrl_ext |= E1000_CTRL_I2C_ENA;
138 } else {
139 phy->ops.reset = igb_phy_hw_reset;
140 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
141 }
142
143 wr32(E1000_CTRL_EXT, ctrl_ext);
144 igb_reset_mdicnfg_82580(hw);
145
146 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
147 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
148 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
149 } else {
150 switch (hw->mac.type) {
151 case e1000_82580:
152 case e1000_i350:
ceb5f13b 153 case e1000_i354:
73bfcd9a
AA		 154 phy->ops.read_reg = igb_read_phy_reg_82580;
155 phy->ops.write_reg = igb_write_phy_reg_82580;
156 break;
157 case e1000_i210:
158 case e1000_i211:
159 phy->ops.read_reg = igb_read_phy_reg_gs40g;
160 phy->ops.write_reg = igb_write_phy_reg_gs40g;
161 break;
162 default:
163 phy->ops.read_reg = igb_read_phy_reg_igp;
164 phy->ops.write_reg = igb_write_phy_reg_igp;
165 }
166 }
167
168 /* set lan id */
169 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
170 E1000_STATUS_FUNC_SHIFT;
171
172 /* Set phy->phy_addr and phy->id. */
173 ret_val = igb_get_phy_id_82575(hw);
174 if (ret_val)
175 return ret_val;
176
177 /* Verify phy id and set remaining function pointers */
178 switch (phy->id) {
ceb5f13b 179 case M88E1545_E_PHY_ID:
73bfcd9a
AA		 180 case I347AT4_E_PHY_ID:
181 case M88E1112_E_PHY_ID:
182 case M88E1111_I_PHY_ID:
183 phy->type = e1000_phy_m88;
ceb5f13b 184 phy->ops.check_polarity = igb_check_polarity_m88;
73bfcd9a 185 phy->ops.get_phy_info = igb_get_phy_info_m88;
ceb5f13b 186 if (phy->id != M88E1111_I_PHY_ID)
73bfcd9a
AA		 187 phy->ops.get_cable_length =
188 igb_get_cable_length_m88_gen2;
189 else
190 phy->ops.get_cable_length = igb_get_cable_length_m88;
191 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
192 break;
193 case IGP03E1000_E_PHY_ID:
194 phy->type = e1000_phy_igp_3;
195 phy->ops.get_phy_info = igb_get_phy_info_igp;
196 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
197 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
198 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
199 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
200 break;
201 case I82580_I_PHY_ID:
202 case I350_I_PHY_ID:
203 phy->type = e1000_phy_82580;
204 phy->ops.force_speed_duplex =
205 igb_phy_force_speed_duplex_82580;
206 phy->ops.get_cable_length = igb_get_cable_length_82580;
207 phy->ops.get_phy_info = igb_get_phy_info_82580;
208 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
209 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
210 break;
211 case I210_I_PHY_ID:
212 phy->type = e1000_phy_i210;
213 phy->ops.check_polarity = igb_check_polarity_m88;
214 phy->ops.get_phy_info = igb_get_phy_info_m88;
215 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
216 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
217 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
218 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
219 break;
220 default:
221 ret_val = -E1000_ERR_PHY;
222 goto out;
223 }
224
225out:
226 return ret_val;
227}
228
56d8c27f
AA		 229/**
230 * igb_init_nvm_params_82575 - Init NVM func ptrs.
231 * @hw: pointer to the HW structure
232 **/
c8268921 233static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
56d8c27f
AA		 234{
235 struct e1000_nvm_info *nvm = &hw->nvm;
236 u32 eecd = rd32(E1000_EECD);
237 u16 size;
238
239 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
240 E1000_EECD_SIZE_EX_SHIFT);
5a823d8c 241
56d8c27f
AA		 242 /* Added to a constant, "size" becomes the left-shift value
243 * for setting word_size.
244 */
245 size += NVM_WORD_SIZE_BASE_SHIFT;
246
247 /* Just in case size is out of range, cap it to the largest
248 * EEPROM size supported
249 */
250 if (size > 15)
251 size = 15;
252
253 nvm->word_size = 1 << size;
5a823d8c
CW		 254 nvm->opcode_bits = 8;
255 nvm->delay_usec = 1;
56d8c27f 256
5a823d8c
CW		 257 switch (nvm->override) {
258 case e1000_nvm_override_spi_large:
259 nvm->page_size = 32;
260 nvm->address_bits = 16;
261 break;
262 case e1000_nvm_override_spi_small:
263 nvm->page_size = 8;
264 nvm->address_bits = 8;
265 break;
266 default:
267 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
268 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
269 16 : 8;
270 break;
56d8c27f 271 }
5a823d8c
CW		 272 if (nvm->word_size == (1 << 15))
273 nvm->page_size = 128;
274
275 nvm->type = e1000_nvm_eeprom_spi;
56d8c27f
AA		 276
277 /* NVM Function Pointers */
5a823d8c
CW		 278 nvm->ops.acquire = igb_acquire_nvm_82575;
279 nvm->ops.release = igb_release_nvm_82575;
280 nvm->ops.write = igb_write_nvm_spi;
281 nvm->ops.validate = igb_validate_nvm_checksum;
282 nvm->ops.update = igb_update_nvm_checksum;
283 if (nvm->word_size < (1 << 15))
284 nvm->ops.read = igb_read_nvm_eerd;
285 else
286 nvm->ops.read = igb_read_nvm_spi;
287
288 /* override generic family function pointers for specific descendants */
56d8c27f
AA		 289 switch (hw->mac.type) {
290 case e1000_82580:
291 nvm->ops.validate = igb_validate_nvm_checksum_82580;
292 nvm->ops.update = igb_update_nvm_checksum_82580;
56d8c27f 293 break;
ceb5f13b 294 case e1000_i354:
56d8c27f
AA		 295 case e1000_i350:
296 nvm->ops.validate = igb_validate_nvm_checksum_i350;
297 nvm->ops.update = igb_update_nvm_checksum_i350;
56d8c27f
AA		 298 break;
299 default:
56d8c27f
AA		 300 break;
301 }
302
303 return 0;
304}
305
a1bf1f44
AA		 306/**
307 * igb_init_mac_params_82575 - Init MAC func ptrs.
308 * @hw: pointer to the HW structure
309 **/
310static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
311{
312 struct e1000_mac_info *mac = &hw->mac;
313 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
314
315 /* Set mta register count */
316 mac->mta_reg_count = 128;
317 /* Set rar entry count */
318 switch (mac->type) {
319 case e1000_82576:
320 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
321 break;
322 case e1000_82580:
323 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
324 break;
325 case e1000_i350:
ceb5f13b 326 case e1000_i354:
a1bf1f44
AA		 327 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
328 break;
329 default:
330 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
331 break;
332 }
333 /* reset */
334 if (mac->type >= e1000_82580)
335 mac->ops.reset_hw = igb_reset_hw_82580;
336 else
337 mac->ops.reset_hw = igb_reset_hw_82575;
338
339 if (mac->type >= e1000_i210) {
340 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
341 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
342
343 } else {
344 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
345 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
346 }
347
348 /* Set if part includes ASF firmware */
349 mac->asf_firmware_present = true;
350 /* Set if manageability features are enabled. */
351 mac->arc_subsystem_valid =
352 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
353 ? true : false;
354 /* enable EEE on i350 parts and later parts */
355 if (mac->type >= e1000_i350)
356 dev_spec->eee_disable = false;
357 else
358 dev_spec->eee_disable = true;
d44e7a9a
MV		 359 /* Allow a single clear of the SW semaphore on I210 and newer */
360 if (mac->type >= e1000_i210)
361 dev_spec->clear_semaphore_once = true;
a1bf1f44
AA		 362 /* physical interface link setup */
363 mac->ops.setup_physical_interface =
364 (hw->phy.media_type == e1000_media_type_copper)
365 ? igb_setup_copper_link_82575
366 : igb_setup_serdes_link_82575;
367
368 return 0;
369}
370
641ac5c0
AA		 371/**
372 * igb_set_sfp_media_type_82575 - derives SFP module media type.
373 * @hw: pointer to the HW structure
374 *
375 * The media type is chosen based on SFP module.
376 * compatibility flags retrieved from SFP ID EEPROM.
377 **/
378static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
379{
380 s32 ret_val = E1000_ERR_CONFIG;
381 u32 ctrl_ext = 0;
382 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
383 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
384 u8 tranceiver_type = 0;
385 s32 timeout = 3;
386
387 /* Turn I2C interface ON and power on sfp cage */
388 ctrl_ext = rd32(E1000_CTRL_EXT);
389 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
390 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
391
392 wrfl();
393
394 /* Read SFP module data */
395 while (timeout) {
396 ret_val = igb_read_sfp_data_byte(hw,
397 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
398 &tranceiver_type);
399 if (ret_val == 0)
400 break;
401 msleep(100);
402 timeout--;
403 }
404 if (ret_val != 0)
405 goto out;
406
407 ret_val = igb_read_sfp_data_byte(hw,
408 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
409 (u8 *)eth_flags);
410 if (ret_val != 0)
411 goto out;
412
413 /* Check if there is some SFP module plugged and powered */
414 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
415 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
416 dev_spec->module_plugged = true;
417 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
418 hw->phy.media_type = e1000_media_type_internal_serdes;
419 } else if (eth_flags->e100_base_fx) {
420 dev_spec->sgmii_active = true;
421 hw->phy.media_type = e1000_media_type_internal_serdes;
422 } else if (eth_flags->e1000_base_t) {
423 dev_spec->sgmii_active = true;
424 hw->phy.media_type = e1000_media_type_copper;
425 } else {
426 hw->phy.media_type = e1000_media_type_unknown;
427 hw_dbg("PHY module has not been recognized\n");
428 goto out;
429 }
430 } else {
431 hw->phy.media_type = e1000_media_type_unknown;
432 }
433 ret_val = 0;
434out:
435 /* Restore I2C interface setting */
436 wr32(E1000_CTRL_EXT, ctrl_ext);
437 return ret_val;
438}
439
9d5c8243
AK		 440static s32 igb_get_invariants_82575(struct e1000_hw *hw)
441{
9d5c8243 442 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 443 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243 444 s32 ret_val;
9d5c8243 445 u32 ctrl_ext = 0;
641ac5c0 446 u32 link_mode = 0;
9d5c8243
AK		 447
448 switch (hw->device_id) {
449 case E1000_DEV_ID_82575EB_COPPER:
450 case E1000_DEV_ID_82575EB_FIBER_SERDES:
451 case E1000_DEV_ID_82575GB_QUAD_COPPER:
452 mac->type = e1000_82575;
453 break;
2d064c06 454 case E1000_DEV_ID_82576:
9eb2341d 455 case E1000_DEV_ID_82576_NS:
747d49ba 456 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 457 case E1000_DEV_ID_82576_FIBER:
458 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 459 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 460 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 461 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 462 mac->type = e1000_82576;
463 break;
bb2ac47b
AD		 464 case E1000_DEV_ID_82580_COPPER:
465 case E1000_DEV_ID_82580_FIBER:
6493d24f 466 case E1000_DEV_ID_82580_QUAD_FIBER:
bb2ac47b
AD		 467 case E1000_DEV_ID_82580_SERDES:
468 case E1000_DEV_ID_82580_SGMII:
469 case E1000_DEV_ID_82580_COPPER_DUAL:
308fb39a
JG		 470 case E1000_DEV_ID_DH89XXCC_SGMII:
471 case E1000_DEV_ID_DH89XXCC_SERDES:
1b5dda33
GJ		 472 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
473 case E1000_DEV_ID_DH89XXCC_SFP:
bb2ac47b
AD		 474 mac->type = e1000_82580;
475 break;
d2ba2ed8
AD		 476 case E1000_DEV_ID_I350_COPPER:
477 case E1000_DEV_ID_I350_FIBER:
478 case E1000_DEV_ID_I350_SERDES:
479 case E1000_DEV_ID_I350_SGMII:
480 mac->type = e1000_i350;
481 break;
f96a8a0b 482 case E1000_DEV_ID_I210_COPPER:
f96a8a0b
CW		 483 case E1000_DEV_ID_I210_FIBER:
484 case E1000_DEV_ID_I210_SERDES:
485 case E1000_DEV_ID_I210_SGMII:
486 mac->type = e1000_i210;
487 break;
488 case E1000_DEV_ID_I211_COPPER:
489 mac->type = e1000_i211;
490 break;
ceb5f13b
CW		 491 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
492 case E1000_DEV_ID_I354_SGMII:
493 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
494 mac->type = e1000_i354;
495 break;
9d5c8243
AK		 496 default:
497 return -E1000_ERR_MAC_INIT;
498 break;
499 }
500
9d5c8243 501 /* Set media type */
b980ac18 502 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
9d5c8243
AK		 503 * based on the EEPROM. We cannot rely upon device ID. There
504 * is no distinguishable difference between fiber and internal
505 * SerDes mode on the 82575. There can be an external PHY attached
506 * on the SGMII interface. For this, we'll set sgmii_active to true.
507 */
a6053d76 508 hw->phy.media_type = e1000_media_type_copper;
9d5c8243 509 dev_spec->sgmii_active = false;
641ac5c0 510 dev_spec->module_plugged = false;
9d5c8243
AK		 511
512 ctrl_ext = rd32(E1000_CTRL_EXT);
641ac5c0
AA		 513
514 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
515 switch (link_mode) {
bb2ac47b 516 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26 517 hw->phy.media_type = e1000_media_type_internal_serdes;
641ac5c0
AA		 518 break;
519 case E1000_CTRL_EXT_LINK_MODE_SGMII:
520 /* Get phy control interface type set (MDIO vs. I2C)*/
521 if (igb_sgmii_uses_mdio_82575(hw)) {
522 hw->phy.media_type = e1000_media_type_copper;
523 dev_spec->sgmii_active = true;
524 break;
525 }
526 /* fall through for I2C based SGMII */
527 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
528 /* read media type from SFP EEPROM */
529 ret_val = igb_set_sfp_media_type_82575(hw);
530 if ((ret_val != 0) ||
531 (hw->phy.media_type == e1000_media_type_unknown)) {
532 /* If media type was not identified then return media
533 * type defined by the CTRL_EXT settings.
534 */
535 hw->phy.media_type = e1000_media_type_internal_serdes;
536
537 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
538 hw->phy.media_type = e1000_media_type_copper;
539 dev_spec->sgmii_active = true;
540 }
541
542 break;
543 }
544
545 /* do not change link mode for 100BaseFX */
546 if (dev_spec->eth_flags.e100_base_fx)
547 break;
548
549 /* change current link mode setting */
550 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
551
552 if (hw->phy.media_type == e1000_media_type_copper)
553 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
554 else
555 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
556
557 wr32(E1000_CTRL_EXT, ctrl_ext);
558
2fb02a26
AD		 559 break;
560 default:
2fb02a26 561 break;
9d5c8243 562 }
2fb02a26 563
a6053d76
AA		 564 /* mac initialization and operations */
565 ret_val = igb_init_mac_params_82575(hw);
566 if (ret_val)
567 goto out;
9d5c8243
AK		 568
569 /* NVM initialization */
a6053d76 570 ret_val = igb_init_nvm_params_82575(hw);
5a823d8c
CW		 571 switch (hw->mac.type) {
572 case e1000_i210:
573 case e1000_i211:
574 ret_val = igb_init_nvm_params_i210(hw);
575 break;
576 default:
577 break;
578 }
579
a6053d76
AA		 580 if (ret_val)
581 goto out;
9d5c8243 582
6b78bb1d
CW		 583 /* if part supports SR-IOV then initialize mailbox parameters */
584 switch (mac->type) {
585 case e1000_82576:
586 case e1000_i350:
a0c98605 587 igb_init_mbx_params_pf(hw);
6b78bb1d
CW		 588 break;
589 default:
590 break;
591 }
a0c98605 592
9d5c8243 593 /* setup PHY parameters */
a6053d76 594 ret_val = igb_init_phy_params_82575(hw);
19e588e7 595
a6053d76
AA		 596out:
597 return ret_val;
9d5c8243
AK		 598}
599
600/**
733596be 601 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 602 * @hw: pointer to the HW structure
603 *
604 * Acquire access rights to the correct PHY. This is a
605 * function pointer entry point called by the api module.
606 **/
607static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
608{
008c3422 609 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 610
008c3422
AD		 611 if (hw->bus.func == E1000_FUNC_1)
612 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 613 else if (hw->bus.func == E1000_FUNC_2)
614 mask = E1000_SWFW_PHY2_SM;
615 else if (hw->bus.func == E1000_FUNC_3)
616 mask = E1000_SWFW_PHY3_SM;
9d5c8243 617
f96a8a0b 618 return hw->mac.ops.acquire_swfw_sync(hw, mask);
9d5c8243
AK		 619}
620
621/**
733596be 622 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 623 * @hw: pointer to the HW structure
624 *
625 * A wrapper to release access rights to the correct PHY. This is a
626 * function pointer entry point called by the api module.
627 **/
628static void igb_release_phy_82575(struct e1000_hw *hw)
629{
008c3422
AD		 630 u16 mask = E1000_SWFW_PHY0_SM;
631
632 if (hw->bus.func == E1000_FUNC_1)
633 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 634 else if (hw->bus.func == E1000_FUNC_2)
635 mask = E1000_SWFW_PHY2_SM;
636 else if (hw->bus.func == E1000_FUNC_3)
637 mask = E1000_SWFW_PHY3_SM;
9d5c8243 638
f96a8a0b 639 hw->mac.ops.release_swfw_sync(hw, mask);
9d5c8243
AK		 640}
641
642/**
733596be 643 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 644 * @hw: pointer to the HW structure
645 * @offset: register offset to be read
646 * @data: pointer to the read data
647 *
648 * Reads the PHY register at offset using the serial gigabit media independent
649 * interface and stores the retrieved information in data.
650 **/
651static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
652 u16 *data)
653{
bf6f7a92 654 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 655
656 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 657 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 658 goto out;
9d5c8243
AK		 659 }
660
bf6f7a92
AD		 661 ret_val = hw->phy.ops.acquire(hw);
662 if (ret_val)
663 goto out;
9d5c8243 664
bf6f7a92 665 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 666
bf6f7a92
AD		 667 hw->phy.ops.release(hw);
668
669out:
670 return ret_val;
9d5c8243
AK		 671}
672
673/**
733596be 674 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 675 * @hw: pointer to the HW structure
676 * @offset: register offset to write to
677 * @data: data to write at register offset
678 *
679 * Writes the data to PHY register at the offset using the serial gigabit
680 * media independent interface.
681 **/
682static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
683 u16 data)
684{
bf6f7a92
AD		 685 s32 ret_val = -E1000_ERR_PARAM;
686
9d5c8243
AK		 687
688 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 689 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 690 goto out;
9d5c8243
AK		 691 }
692
bf6f7a92
AD		 693 ret_val = hw->phy.ops.acquire(hw);
694 if (ret_val)
695 goto out;
9d5c8243 696
bf6f7a92 697 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 698
bf6f7a92
AD		 699 hw->phy.ops.release(hw);
700
701out:
702 return ret_val;
9d5c8243
AK		 703}
704
705/**
733596be 706 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 707 * @hw: pointer to the HW structure
708 *
652fff32 709 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 710 * sgmi interface.
711 **/
712static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
713{
714 struct e1000_phy_info *phy = &hw->phy;
715 s32 ret_val = 0;
716 u16 phy_id;
2fb02a26 717 u32 ctrl_ext;
4085f746 718 u32 mdic;
9d5c8243 719
b980ac18 720 /* For SGMII PHYs, we try the list of possible addresses until
9d5c8243
AK		 721 * we find one that works. For non-SGMII PHYs
722 * (e.g. integrated copper PHYs), an address of 1 should
723 * work. The result of this function should mean phy->phy_addr
724 * and phy->id are set correctly.
725 */
726 if (!(igb_sgmii_active_82575(hw))) {
727 phy->addr = 1;
728 ret_val = igb_get_phy_id(hw);
729 goto out;
730 }
731
4085f746
NN		 732 if (igb_sgmii_uses_mdio_82575(hw)) {
733 switch (hw->mac.type) {
734 case e1000_82575:
735 case e1000_82576:
736 mdic = rd32(E1000_MDIC);
737 mdic &= E1000_MDIC_PHY_MASK;
738 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
739 break;
740 case e1000_82580:
741 case e1000_i350:
ceb5f13b 742 case e1000_i354:
f96a8a0b
CW		 743 case e1000_i210:
744 case e1000_i211:
4085f746
NN		 745 mdic = rd32(E1000_MDICNFG);
746 mdic &= E1000_MDICNFG_PHY_MASK;
747 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
748 break;
749 default:
750 ret_val = -E1000_ERR_PHY;
751 goto out;
752 break;
753 }
754 ret_val = igb_get_phy_id(hw);
755 goto out;
756 }
757
2fb02a26
AD		 758 /* Power on sgmii phy if it is disabled */
759 ctrl_ext = rd32(E1000_CTRL_EXT);
760 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
761 wrfl();
762 msleep(300);
763
b980ac18 764 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
9d5c8243
AK		 765 * Therefore, we need to test 1-7
766 */
767 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
768 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
769 if (ret_val == 0) {
652fff32
AK		 770 hw_dbg("Vendor ID 0x%08X read at address %u\n",
771 phy_id, phy->addr);
b980ac18 772 /* At the time of this writing, The M88 part is
9d5c8243
AK		 773 * the only supported SGMII PHY product.
774 */
775 if (phy_id == M88_VENDOR)
776 break;
777 } else {
652fff32 778 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 779 }
780 }
781
782 /* A valid PHY type couldn't be found. */
783 if (phy->addr == 8) {
784 phy->addr = 0;
785 ret_val = -E1000_ERR_PHY;
786 goto out;
2fb02a26
AD		 787 } else {
788 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 789 }
790
2fb02a26
AD		 791 /* restore previous sfp cage power state */
792 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 793
794out:
795 return ret_val;
796}
797
798/**
733596be 799 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 800 * @hw: pointer to the HW structure
801 *
802 * Resets the PHY using the serial gigabit media independent interface.
803 **/
804static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
805{
806 s32 ret_val;
807
b980ac18 808 /* This isn't a true "hard" reset, but is the only reset
9d5c8243
AK		 809 * available to us at this time.
810 */
811
652fff32 812 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243 813
b980ac18 814 /* SFP documentation requires the following to configure the SPF module
9d5c8243
AK		 815 * to work on SGMII. No further documentation is given.
816 */
a8d2a0c2 817 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 818 if (ret_val)
819 goto out;
820
821 ret_val = igb_phy_sw_reset(hw);
822
823out:
824 return ret_val;
825}
826
827/**
733596be 828 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 829 * @hw: pointer to the HW structure
830 * @active: true to enable LPLU, false to disable
831 *
832 * Sets the LPLU D0 state according to the active flag. When
833 * activating LPLU this function also disables smart speed
834 * and vice versa. LPLU will not be activated unless the
835 * device autonegotiation advertisement meets standards of
836 * either 10 or 10/100 or 10/100/1000 at all duplexes.
837 * This is a function pointer entry point only called by
838 * PHY setup routines.
839 **/
840static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
841{
842 struct e1000_phy_info *phy = &hw->phy;
843 s32 ret_val;
844 u16 data;
845
a8d2a0c2 846 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 847 if (ret_val)
848 goto out;
849
850 if (active) {
851 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 852 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 853 data);
9d5c8243
AK		 854 if (ret_val)
855 goto out;
856
857 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 858 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 859 &data);
9d5c8243 860 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 861 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 862 data);
9d5c8243
AK		 863 if (ret_val)
864 goto out;
865 } else {
866 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 867 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 868 data);
b980ac18 869 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
9d5c8243
AK		 870 * during Dx states where the power conservation is most
871 * important. During driver activity we should enable
872 * SmartSpeed, so performance is maintained.
873 */
874 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 875 ret_val = phy->ops.read_reg(hw,
652fff32 876 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 877 if (ret_val)
878 goto out;
879
880 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 881 ret_val = phy->ops.write_reg(hw,
652fff32 882 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 883 if (ret_val)
884 goto out;
885 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 886 ret_val = phy->ops.read_reg(hw,
652fff32 887 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 888 if (ret_val)
889 goto out;
890
891 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 892 ret_val = phy->ops.write_reg(hw,
652fff32 893 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 894 if (ret_val)
895 goto out;
896 }
897 }
898
899out:
900 return ret_val;
901}
902
da02cde1
CW		 903/**
904 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
905 * @hw: pointer to the HW structure
906 * @active: true to enable LPLU, false to disable
907 *
908 * Sets the LPLU D0 state according to the active flag. When
909 * activating LPLU this function also disables smart speed
910 * and vice versa. LPLU will not be activated unless the
911 * device autonegotiation advertisement meets standards of
912 * either 10 or 10/100 or 10/100/1000 at all duplexes.
913 * This is a function pointer entry point only called by
914 * PHY setup routines.
915 **/
916static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
917{
918 struct e1000_phy_info *phy = &hw->phy;
919 s32 ret_val = 0;
920 u16 data;
921
922 data = rd32(E1000_82580_PHY_POWER_MGMT);
923
924 if (active) {
925 data |= E1000_82580_PM_D0_LPLU;
926
927 /* When LPLU is enabled, we should disable SmartSpeed */
928 data &= ~E1000_82580_PM_SPD;
929 } else {
930 data &= ~E1000_82580_PM_D0_LPLU;
931
b980ac18 932 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
da02cde1
CW		 933 * during Dx states where the power conservation is most
934 * important. During driver activity we should enable
935 * SmartSpeed, so performance is maintained.
936 */
937 if (phy->smart_speed == e1000_smart_speed_on)
938 data |= E1000_82580_PM_SPD;
939 else if (phy->smart_speed == e1000_smart_speed_off)
940 data &= ~E1000_82580_PM_SPD; }
941
942 wr32(E1000_82580_PHY_POWER_MGMT, data);
943 return ret_val;
944}
945
946/**
947 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
948 * @hw: pointer to the HW structure
949 * @active: boolean used to enable/disable lplu
950 *
951 * Success returns 0, Failure returns 1
952 *
953 * The low power link up (lplu) state is set to the power management level D3
954 * and SmartSpeed is disabled when active is true, else clear lplu for D3
955 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
956 * is used during Dx states where the power conservation is most important.
957 * During driver activity, SmartSpeed should be enabled so performance is
958 * maintained.
959 **/
c8268921 960static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
da02cde1
CW		 961{
962 struct e1000_phy_info *phy = &hw->phy;
963 s32 ret_val = 0;
964 u16 data;
965
966 data = rd32(E1000_82580_PHY_POWER_MGMT);
967
968 if (!active) {
969 data &= ~E1000_82580_PM_D3_LPLU;
b980ac18 970 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
da02cde1
CW		 971 * during Dx states where the power conservation is most
972 * important. During driver activity we should enable
973 * SmartSpeed, so performance is maintained.
974 */
975 if (phy->smart_speed == e1000_smart_speed_on)
976 data |= E1000_82580_PM_SPD;
977 else if (phy->smart_speed == e1000_smart_speed_off)
978 data &= ~E1000_82580_PM_SPD;
979 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
980 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
981 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
982 data |= E1000_82580_PM_D3_LPLU;
983 /* When LPLU is enabled, we should disable SmartSpeed */
984 data &= ~E1000_82580_PM_SPD;
985 }
986
987 wr32(E1000_82580_PHY_POWER_MGMT, data);
988 return ret_val;
989}
990
9d5c8243 991/**
733596be 992 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 993 * @hw: pointer to the HW structure
994 *
652fff32 995 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 996 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
997 * Return successful if access grant bit set, else clear the request for
998 * EEPROM access and return -E1000_ERR_NVM (-1).
999 **/
1000static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1001{
1002 s32 ret_val;
1003
f96a8a0b 1004 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1005 if (ret_val)
1006 goto out;
1007
1008 ret_val = igb_acquire_nvm(hw);
1009
1010 if (ret_val)
f96a8a0b 1011 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1012
1013out:
1014 return ret_val;
1015}
1016
1017/**
733596be 1018 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 1019 * @hw: pointer to the HW structure
1020 *
1021 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1022 * then release the semaphores acquired.
1023 **/
1024static void igb_release_nvm_82575(struct e1000_hw *hw)
1025{
1026 igb_release_nvm(hw);
f96a8a0b 1027 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1028}
1029
1030/**
733596be 1031 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 1032 * @hw: pointer to the HW structure
1033 * @mask: specifies which semaphore to acquire
1034 *
1035 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1036 * will also specify which port we're acquiring the lock for.
1037 **/
1038static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1039{
1040 u32 swfw_sync;
1041 u32 swmask = mask;
1042 u32 fwmask = mask << 16;
1043 s32 ret_val = 0;
1044 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1045
1046 while (i < timeout) {
1047 if (igb_get_hw_semaphore(hw)) {
1048 ret_val = -E1000_ERR_SWFW_SYNC;
1049 goto out;
1050 }
1051
1052 swfw_sync = rd32(E1000_SW_FW_SYNC);
1053 if (!(swfw_sync & (fwmask | swmask)))
1054 break;
1055
b980ac18 1056 /* Firmware currently using resource (fwmask)
9d5c8243
AK		 1057 * or other software thread using resource (swmask)
1058 */
1059 igb_put_hw_semaphore(hw);
1060 mdelay(5);
1061 i++;
1062 }
1063
1064 if (i == timeout) {
652fff32 1065 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 1066 ret_val = -E1000_ERR_SWFW_SYNC;
1067 goto out;
1068 }
1069
1070 swfw_sync |= swmask;
1071 wr32(E1000_SW_FW_SYNC, swfw_sync);
1072
1073 igb_put_hw_semaphore(hw);
1074
1075out:
1076 return ret_val;
1077}
1078
1079/**
733596be 1080 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 1081 * @hw: pointer to the HW structure
1082 * @mask: specifies which semaphore to acquire
1083 *
1084 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1085 * will also specify which port we're releasing the lock for.
1086 **/
1087static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1088{
1089 u32 swfw_sync;
1090
1091 while (igb_get_hw_semaphore(hw) != 0);
1092 /* Empty */
1093
1094 swfw_sync = rd32(E1000_SW_FW_SYNC);
1095 swfw_sync &= ~mask;
1096 wr32(E1000_SW_FW_SYNC, swfw_sync);
1097
1098 igb_put_hw_semaphore(hw);
1099}
1100
1101/**
733596be 1102 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 1103 * @hw: pointer to the HW structure
1104 *
1105 * Read the management control register for the config done bit for
1106 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1107 * to read the config done bit, so an error is *ONLY* logged and returns
1108 * 0. If we were to return with error, EEPROM-less silicon
1109 * would not be able to be reset or change link.
1110 **/
1111static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1112{
1113 s32 timeout = PHY_CFG_TIMEOUT;
1114 s32 ret_val = 0;
1115 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1116
1117 if (hw->bus.func == 1)
1118 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 1119 else if (hw->bus.func == E1000_FUNC_2)
1120 mask = E1000_NVM_CFG_DONE_PORT_2;
1121 else if (hw->bus.func == E1000_FUNC_3)
1122 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 1123
1124 while (timeout) {
1125 if (rd32(E1000_EEMNGCTL) & mask)
1126 break;
1127 msleep(1);
1128 timeout--;
1129 }
1130 if (!timeout)
652fff32 1131 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 1132
1133 /* If EEPROM is not marked present, init the PHY manually */
1134 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1135 (hw->phy.type == e1000_phy_igp_3))
1136 igb_phy_init_script_igp3(hw);
1137
1138 return ret_val;
1139}
1140
1141/**
733596be 1142 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 1143 * @hw: pointer to the HW structure
1144 *
1145 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1146 * use the generic interface for determining link.
1147 **/
1148static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1149{
1150 s32 ret_val;
1151 u16 speed, duplex;
1152
70d92f86 1153 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 1154 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 1155 &duplex);
b980ac18 1156 /* Use this flag to determine if link needs to be checked or
5d0932a5
AD		 1157 * not. If we have link clear the flag so that we do not
1158 * continue to check for link.
1159 */
1160 hw->mac.get_link_status = !hw->mac.serdes_has_link;
daf56e40
CW		 1161
1162 /* Configure Flow Control now that Auto-Neg has completed.
1163 * First, we need to restore the desired flow control
1164 * settings because we may have had to re-autoneg with a
1165 * different link partner.
1166 */
1167 ret_val = igb_config_fc_after_link_up(hw);
1168 if (ret_val)
1169 hw_dbg("Error configuring flow control\n");
5d0932a5 1170 } else {
9d5c8243 1171 ret_val = igb_check_for_copper_link(hw);
5d0932a5 1172 }
9d5c8243
AK		 1173
1174 return ret_val;
1175}
70d92f86 1176
88a268c1
NN		 1177/**
1178 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1179 * @hw: pointer to the HW structure
1180 **/
1181void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1182{
1183 u32 reg;
1184
1185
1186 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1187 !igb_sgmii_active_82575(hw))
1188 return;
1189
1190 /* Enable PCS to turn on link */
1191 reg = rd32(E1000_PCS_CFG0);
1192 reg |= E1000_PCS_CFG_PCS_EN;
1193 wr32(E1000_PCS_CFG0, reg);
1194
1195 /* Power up the laser */
1196 reg = rd32(E1000_CTRL_EXT);
1197 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1198 wr32(E1000_CTRL_EXT, reg);
1199
1200 /* flush the write to verify completion */
1201 wrfl();
1202 msleep(1);
1203}
1204
9d5c8243 1205/**
733596be 1206 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 1207 * @hw: pointer to the HW structure
1208 * @speed: stores the current speed
1209 * @duplex: stores the current duplex
1210 *
652fff32 1211 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 1212 * duplex, then store the values in the pointers provided.
1213 **/
1214static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1215 u16 *duplex)
1216{
1217 struct e1000_mac_info *mac = &hw->mac;
1218 u32 pcs;
1219
1220 /* Set up defaults for the return values of this function */
1221 mac->serdes_has_link = false;
1222 *speed = 0;
1223 *duplex = 0;
1224
b980ac18 1225 /* Read the PCS Status register for link state. For non-copper mode,
9d5c8243
AK		 1226 * the status register is not accurate. The PCS status register is
1227 * used instead.
1228 */
1229 pcs = rd32(E1000_PCS_LSTAT);
1230
b980ac18 1231 /* The link up bit determines when link is up on autoneg. The sync ok
9d5c8243
AK		 1232 * gets set once both sides sync up and agree upon link. Stable link
1233 * can be determined by checking for both link up and link sync ok
1234 */
1235 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1236 mac->serdes_has_link = true;
1237
1238 /* Detect and store PCS speed */
1239 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
1240 *speed = SPEED_1000;
1241 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
1242 *speed = SPEED_100;
1243 } else {
1244 *speed = SPEED_10;
1245 }
1246
1247 /* Detect and store PCS duplex */
1248 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
1249 *duplex = FULL_DUPLEX;
1250 } else {
1251 *duplex = HALF_DUPLEX;
1252 }
1253 }
1254
1255 return 0;
1256}
1257
2d064c06 1258/**
2fb02a26 1259 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 1260 * @hw: pointer to the HW structure
9d5c8243 1261 *
2d064c06
AD		 1262 * In the case of fiber serdes, shut down optics and PCS on driver unload
1263 * when management pass thru is not enabled.
9d5c8243 1264 **/
2fb02a26 1265void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1266{
2d064c06
AD		 1267 u32 reg;
1268
53c992fa 1269 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 1270 igb_sgmii_active_82575(hw))
2d064c06
AD		 1271 return;
1272
53c992fa 1273 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 1274 /* Disable PCS to turn off link */
1275 reg = rd32(E1000_PCS_CFG0);
1276 reg &= ~E1000_PCS_CFG_PCS_EN;
1277 wr32(E1000_PCS_CFG0, reg);
1278
1279 /* shutdown the laser */
1280 reg = rd32(E1000_CTRL_EXT);
2fb02a26 1281 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 1282 wr32(E1000_CTRL_EXT, reg);
1283
1284 /* flush the write to verify completion */
1285 wrfl();
1286 msleep(1);
1287 }
9d5c8243
AK		 1288}
1289
1290/**
733596be 1291 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 1292 * @hw: pointer to the HW structure
1293 *
1294 * This resets the hardware into a known state. This is a
1295 * function pointer entry point called by the api module.
1296 **/
1297static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1298{
e5c3370f 1299 u32 ctrl;
9d5c8243
AK		 1300 s32 ret_val;
1301
b980ac18 1302 /* Prevent the PCI-E bus from sticking if there is no TLP connection
9d5c8243
AK		 1303 * on the last TLP read/write transaction when MAC is reset.
1304 */
1305 ret_val = igb_disable_pcie_master(hw);
1306 if (ret_val)
652fff32 1307 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 1308
009bc06e
AD		 1309 /* set the completion timeout for interface */
1310 ret_val = igb_set_pcie_completion_timeout(hw);
1311 if (ret_val) {
1312 hw_dbg("PCI-E Set completion timeout has failed.\n");
1313 }
1314
652fff32 1315 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 1316 wr32(E1000_IMC, 0xffffffff);
1317
1318 wr32(E1000_RCTL, 0);
1319 wr32(E1000_TCTL, E1000_TCTL_PSP);
1320 wrfl();
1321
1322 msleep(10);
1323
1324 ctrl = rd32(E1000_CTRL);
1325
652fff32 1326 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 1327 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1328
1329 ret_val = igb_get_auto_rd_done(hw);
1330 if (ret_val) {
b980ac18 1331 /* When auto config read does not complete, do not
9d5c8243
AK		 1332 * return with an error. This can happen in situations
1333 * where there is no eeprom and prevents getting link.
1334 */
652fff32 1335 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 1336 }
1337
1338 /* If EEPROM is not present, run manual init scripts */
1339 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1340 igb_reset_init_script_82575(hw);
1341
1342 /* Clear any pending interrupt events. */
1343 wr32(E1000_IMC, 0xffffffff);
e5c3370f 1344 rd32(E1000_ICR);
9d5c8243 1345
5ac16659
AD		 1346 /* Install any alternate MAC address into RAR0 */
1347 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 1348
1349 return ret_val;
1350}
1351
1352/**
733596be 1353 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 1354 * @hw: pointer to the HW structure
1355 *
1356 * This inits the hardware readying it for operation.
1357 **/
1358static s32 igb_init_hw_82575(struct e1000_hw *hw)
1359{
1360 struct e1000_mac_info *mac = &hw->mac;
1361 s32 ret_val;
1362 u16 i, rar_count = mac->rar_entry_count;
1363
1364 /* Initialize identification LED */
1365 ret_val = igb_id_led_init(hw);
1366 if (ret_val) {
652fff32 1367 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 1368 /* This is not fatal and we should not stop init due to this */
1369 }
1370
1371 /* Disabling VLAN filtering */
652fff32 1372 hw_dbg("Initializing the IEEE VLAN\n");
ceb5f13b 1373 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1128c756
CW		 1374 igb_clear_vfta_i350(hw);
1375 else
1376 igb_clear_vfta(hw);
9d5c8243
AK		 1377
1378 /* Setup the receive address */
5ac16659
AD		 1379 igb_init_rx_addrs(hw, rar_count);
1380
9d5c8243 1381 /* Zero out the Multicast HASH table */
652fff32 1382 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1383 for (i = 0; i < mac->mta_reg_count; i++)
1384 array_wr32(E1000_MTA, i, 0);
1385
68d480c4
AD		 1386 /* Zero out the Unicast HASH table */
1387 hw_dbg("Zeroing the UTA\n");
1388 for (i = 0; i < mac->uta_reg_count; i++)
1389 array_wr32(E1000_UTA, i, 0);
1390
9d5c8243
AK		 1391 /* Setup link and flow control */
1392 ret_val = igb_setup_link(hw);
1393
b980ac18 1394 /* Clear all of the statistics registers (clear on read). It is
9d5c8243
AK		 1395 * important that we do this after we have tried to establish link
1396 * because the symbol error count will increment wildly if there
1397 * is no link.
1398 */
1399 igb_clear_hw_cntrs_82575(hw);
9d5c8243
AK		 1400 return ret_val;
1401}
1402
1403/**
733596be 1404 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1405 * @hw: pointer to the HW structure
1406 *
1407 * Configures the link for auto-neg or forced speed and duplex. Then we check
1408 * for link, once link is established calls to configure collision distance
1409 * and flow control are called.
1410 **/
1411static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1412{
12645a19 1413 u32 ctrl;
9d5c8243 1414 s32 ret_val;
867eb39e 1415 u32 phpm_reg;
9d5c8243
AK		 1416
1417 ctrl = rd32(E1000_CTRL);
1418 ctrl |= E1000_CTRL_SLU;
1419 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1420 wr32(E1000_CTRL, ctrl);
1421
867eb39e
CW		 1422 /* Clear Go Link Disconnect bit */
1423 if (hw->mac.type >= e1000_82580) {
1424 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1425 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1426 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1427 }
1428
2fb02a26
AD		 1429 ret_val = igb_setup_serdes_link_82575(hw);
1430 if (ret_val)
1431 goto out;
1432
1433 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1434 /* allow time for SFP cage time to power up phy */
1435 msleep(300);
1436
2fb02a26
AD		 1437 ret_val = hw->phy.ops.reset(hw);
1438 if (ret_val) {
1439 hw_dbg("Error resetting the PHY.\n");
1440 goto out;
1441 }
1442 }
9d5c8243 1443 switch (hw->phy.type) {
f96a8a0b 1444 case e1000_phy_i210:
9d5c8243 1445 case e1000_phy_m88:
ed65bdd8
CW		 1446 switch (hw->phy.id) {
1447 case I347AT4_E_PHY_ID:
1448 case M88E1112_E_PHY_ID:
ceb5f13b 1449 case M88E1545_E_PHY_ID:
ed65bdd8 1450 case I210_I_PHY_ID:
308fb39a 1451 ret_val = igb_copper_link_setup_m88_gen2(hw);
ed65bdd8
CW		 1452 break;
1453 default:
308fb39a 1454 ret_val = igb_copper_link_setup_m88(hw);
ed65bdd8
CW		 1455 break;
1456 }
9d5c8243
AK		 1457 break;
1458 case e1000_phy_igp_3:
1459 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1460 break;
bb2ac47b
AD		 1461 case e1000_phy_82580:
1462 ret_val = igb_copper_link_setup_82580(hw);
1463 break;
9d5c8243
AK		 1464 default:
1465 ret_val = -E1000_ERR_PHY;
1466 break;
1467 }
1468
1469 if (ret_val)
1470 goto out;
1471
81fadd81 1472 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1473out:
1474 return ret_val;
1475}
1476
1477/**
70d92f86 1478 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1479 * @hw: pointer to the HW structure
1480 *
70d92f86
AD		 1481 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1482 * used on copper connections where the serialized gigabit media independent
1483 * interface (sgmii), or serdes fiber is being used. Configures the link
1484 * for auto-negotiation or forces speed/duplex.
9d5c8243 1485 **/
2fb02a26 1486static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1487{
daf56e40 1488 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
bb2ac47b 1489 bool pcs_autoneg;
2c670b5b
CW		 1490 s32 ret_val = E1000_SUCCESS;
1491 u16 data;
2fb02a26
AD		 1492
1493 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1494 !igb_sgmii_active_82575(hw))
2c670b5b
CW		 1495 return ret_val;
1496
9d5c8243 1497
b980ac18 1498 /* On the 82575, SerDes loopback mode persists until it is
9d5c8243
AK		 1499 * explicitly turned off or a power cycle is performed. A read to
1500 * the register does not indicate its status. Therefore, we ensure
1501 * loopback mode is disabled during initialization.
1502 */
1503 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1504
e00bf607 1505 /* power on the sfp cage if present and turn on I2C */
bb2ac47b
AD		 1506 ctrl_ext = rd32(E1000_CTRL_EXT);
1507 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
e00bf607 1508 ctrl_ext |= E1000_CTRL_I2C_ENA;
bb2ac47b 1509 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1510
1511 ctrl_reg = rd32(E1000_CTRL);
1512 ctrl_reg |= E1000_CTRL_SLU;
1513
1514 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1515 /* set both sw defined pins */
1516 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1517
1518 /* Set switch control to serdes energy detect */
1519 reg = rd32(E1000_CONNSW);
1520 reg |= E1000_CONNSW_ENRGSRC;
1521 wr32(E1000_CONNSW, reg);
1522 }
1523
1524 reg = rd32(E1000_PCS_LCTL);
1525
bb2ac47b
AD		 1526 /* default pcs_autoneg to the same setting as mac autoneg */
1527 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1528
bb2ac47b
AD		 1529 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1530 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1531 /* sgmii mode lets the phy handle forcing speed/duplex */
1532 pcs_autoneg = true;
1533 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1534 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1535 break;
1536 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1537 /* disable PCS autoneg and support parallel detect only */
1538 pcs_autoneg = false;
1539 default:
2c670b5b
CW		 1540 if (hw->mac.type == e1000_82575 ||
1541 hw->mac.type == e1000_82576) {
1542 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1543 if (ret_val) {
1544 printk(KERN_DEBUG "NVM Read Error\n\n");
1545 return ret_val;
1546 }
1547
1548 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1549 pcs_autoneg = false;
1550 }
1551
b980ac18 1552 /* non-SGMII modes only supports a speed of 1000/Full for the
bb2ac47b
AD		 1553 * link so it is best to just force the MAC and let the pcs
1554 * link either autoneg or be forced to 1000/Full
1555 */
2fb02a26
AD		 1556 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1557 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1558
1559 /* set speed of 1000/Full if speed/duplex is forced */
1560 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1561 break;
921aa749
AD		 1562 }
1563
2fb02a26 1564 wr32(E1000_CTRL, ctrl_reg);
9d5c8243 1565
b980ac18 1566 /* New SerDes mode allows for forcing speed or autonegotiating speed
9d5c8243
AK		 1567 * at 1gb. Autoneg should be default set by most drivers. This is the
1568 * mode that will be compatible with older link partners and switches.
1569 * However, both are supported by the hardware and some drivers/tools.
1570 */
9d5c8243
AK		 1571 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1572 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1573
bb2ac47b 1574 if (pcs_autoneg) {
9d5c8243 1575 /* Set PCS register for autoneg */
bb2ac47b 1576 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1577 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
daf56e40
CW		 1578
1579 /* Disable force flow control for autoneg */
1580 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1581
1582 /* Configure flow control advertisement for autoneg */
1583 anadv_reg = rd32(E1000_PCS_ANADV);
1584 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1585 switch (hw->fc.requested_mode) {
1586 case e1000_fc_full:
1587 case e1000_fc_rx_pause:
1588 anadv_reg |= E1000_TXCW_ASM_DIR;
1589 anadv_reg |= E1000_TXCW_PAUSE;
1590 break;
1591 case e1000_fc_tx_pause:
1592 anadv_reg |= E1000_TXCW_ASM_DIR;
1593 break;
1594 default:
1595 break;
1596 }
1597 wr32(E1000_PCS_ANADV, anadv_reg);
1598
bb2ac47b 1599 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1600 } else {
bb2ac47b 1601 /* Set PCS register for forced link */
d68caec6 1602 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b 1603
daf56e40
CW		 1604 /* Force flow control for forced link */
1605 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1606
bb2ac47b 1607 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1608 }
726c09e7 1609
9d5c8243
AK		 1610 wr32(E1000_PCS_LCTL, reg);
1611
daf56e40 1612 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
2fb02a26 1613 igb_force_mac_fc(hw);
9d5c8243 1614
2c670b5b 1615 return ret_val;
9d5c8243
AK		 1616}
1617
1618/**
733596be 1619 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1620 * @hw: pointer to the HW structure
1621 *
1622 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1623 * which can be enabled for use in the embedded applications. Simply
1624 * return the current state of the sgmii interface.
1625 **/
1626static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1627{
c1889bfe 1628 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1629 return dev_spec->sgmii_active;
9d5c8243
AK		 1630}
1631
1632/**
733596be 1633 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1634 * @hw: pointer to the HW structure
1635 *
1636 * Inits recommended HW defaults after a reset when there is no EEPROM
1637 * detected. This is only for the 82575.
1638 **/
1639static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1640{
1641 if (hw->mac.type == e1000_82575) {
652fff32 1642 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1643 /* SerDes configuration via SERDESCTRL */
1644 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1645 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1646 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1647 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1648
1649 /* CCM configuration via CCMCTL register */
1650 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1651 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1652
1653 /* PCIe lanes configuration */
1654 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1655 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1656 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1657 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1658
1659 /* PCIe PLL Configuration */
1660 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1661 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1662 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1663 }
1664
1665 return 0;
1666}
1667
1668/**
733596be 1669 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1670 * @hw: pointer to the HW structure
1671 **/
1672static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1673{
1674 s32 ret_val = 0;
1675
b980ac18 1676 /* If there's an alternate MAC address place it in RAR0
22896639
AD		 1677 * so that it will override the Si installed default perm
1678 * address.
1679 */
1680 ret_val = igb_check_alt_mac_addr(hw);
1681 if (ret_val)
1682 goto out;
1683
1684 ret_val = igb_read_mac_addr(hw);
9d5c8243 1685
22896639 1686out:
9d5c8243
AK		 1687 return ret_val;
1688}
1689
88a268c1
NN		 1690/**
1691 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1692 * @hw: pointer to the HW structure
1693 *
1694 * In the case of a PHY power down to save power, or to turn off link during a
1695 * driver unload, or wake on lan is not enabled, remove the link.
1696 **/
1697void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1698{
1699 /* If the management interface is not enabled, then power down */
1700 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1701 igb_power_down_phy_copper(hw);
88a268c1
NN		 1702}
1703
9d5c8243 1704/**
733596be 1705 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1706 * @hw: pointer to the HW structure
1707 *
1708 * Clears the hardware counters by reading the counter registers.
1709 **/
1710static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1711{
9d5c8243
AK		 1712 igb_clear_hw_cntrs_base(hw);
1713
cc9073bb
AD		 1714 rd32(E1000_PRC64);
1715 rd32(E1000_PRC127);
1716 rd32(E1000_PRC255);
1717 rd32(E1000_PRC511);
1718 rd32(E1000_PRC1023);
1719 rd32(E1000_PRC1522);
1720 rd32(E1000_PTC64);
1721 rd32(E1000_PTC127);
1722 rd32(E1000_PTC255);
1723 rd32(E1000_PTC511);
1724 rd32(E1000_PTC1023);
1725 rd32(E1000_PTC1522);
1726
1727 rd32(E1000_ALGNERRC);
1728 rd32(E1000_RXERRC);
1729 rd32(E1000_TNCRS);
1730 rd32(E1000_CEXTERR);
1731 rd32(E1000_TSCTC);
1732 rd32(E1000_TSCTFC);
1733
1734 rd32(E1000_MGTPRC);
1735 rd32(E1000_MGTPDC);
1736 rd32(E1000_MGTPTC);
1737
1738 rd32(E1000_IAC);
1739 rd32(E1000_ICRXOC);
1740
1741 rd32(E1000_ICRXPTC);
1742 rd32(E1000_ICRXATC);
1743 rd32(E1000_ICTXPTC);
1744 rd32(E1000_ICTXATC);
1745 rd32(E1000_ICTXQEC);
1746 rd32(E1000_ICTXQMTC);
1747 rd32(E1000_ICRXDMTC);
1748
1749 rd32(E1000_CBTMPC);
1750 rd32(E1000_HTDPMC);
1751 rd32(E1000_CBRMPC);
1752 rd32(E1000_RPTHC);
1753 rd32(E1000_HGPTC);
1754 rd32(E1000_HTCBDPC);
1755 rd32(E1000_HGORCL);
1756 rd32(E1000_HGORCH);
1757 rd32(E1000_HGOTCL);
1758 rd32(E1000_HGOTCH);
1759 rd32(E1000_LENERRS);
9d5c8243
AK		 1760
1761 /* This register should not be read in copper configurations */
2fb02a26
AD		 1762 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1763 igb_sgmii_active_82575(hw))
cc9073bb 1764 rd32(E1000_SCVPC);
9d5c8243
AK		 1765}
1766
662d7205
AD		 1767/**
1768 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1769 * @hw: pointer to the HW structure
1770 *
1771 * After rx enable if managability is enabled then there is likely some
1772 * bad data at the start of the fifo and possibly in the DMA fifo. This
1773 * function clears the fifos and flushes any packets that came in as rx was
1774 * being enabled.
1775 **/
1776void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1777{
1778 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1779 int i, ms_wait;
1780
1781 if (hw->mac.type != e1000_82575 ||
1782 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1783 return;
1784
1785 /* Disable all RX queues */
1786 for (i = 0; i < 4; i++) {
1787 rxdctl[i] = rd32(E1000_RXDCTL(i));
1788 wr32(E1000_RXDCTL(i),
1789 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1790 }
1791 /* Poll all queues to verify they have shut down */
1792 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1793 msleep(1);
1794 rx_enabled = 0;
1795 for (i = 0; i < 4; i++)
1796 rx_enabled |= rd32(E1000_RXDCTL(i));
1797 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1798 break;
1799 }
1800
1801 if (ms_wait == 10)
1802 hw_dbg("Queue disable timed out after 10ms\n");
1803
1804 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1805 * incoming packets are rejected. Set enable and wait 2ms so that
1806 * any packet that was coming in as RCTL.EN was set is flushed
1807 */
1808 rfctl = rd32(E1000_RFCTL);
1809 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1810
1811 rlpml = rd32(E1000_RLPML);
1812 wr32(E1000_RLPML, 0);
1813
1814 rctl = rd32(E1000_RCTL);
1815 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1816 temp_rctl |= E1000_RCTL_LPE;
1817
1818 wr32(E1000_RCTL, temp_rctl);
1819 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1820 wrfl();
1821 msleep(2);
1822
1823 /* Enable RX queues that were previously enabled and restore our
1824 * previous state
1825 */
1826 for (i = 0; i < 4; i++)
1827 wr32(E1000_RXDCTL(i), rxdctl[i]);
1828 wr32(E1000_RCTL, rctl);
1829 wrfl();
1830
1831 wr32(E1000_RLPML, rlpml);
1832 wr32(E1000_RFCTL, rfctl);
1833
1834 /* Flush receive errors generated by workaround */
1835 rd32(E1000_ROC);
1836 rd32(E1000_RNBC);
1837 rd32(E1000_MPC);
1838}
1839
009bc06e
AD		 1840/**
1841 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1842 * @hw: pointer to the HW structure
1843 *
1844 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1845 * however the hardware default for these parts is 500us to 1ms which is less
1846 * than the 10ms recommended by the pci-e spec. To address this we need to
1847 * increase the value to either 10ms to 200ms for capability version 1 config,
1848 * or 16ms to 55ms for version 2.
1849 **/
1850static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1851{
1852 u32 gcr = rd32(E1000_GCR);
1853 s32 ret_val = 0;
1854 u16 pcie_devctl2;
1855
1856 /* only take action if timeout value is defaulted to 0 */
1857 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1858 goto out;
1859
b980ac18 1860 /* if capabilities version is type 1 we can write the
009bc06e
AD		 1861 * timeout of 10ms to 200ms through the GCR register
1862 */
1863 if (!(gcr & E1000_GCR_CAP_VER2)) {
1864 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1865 goto out;
1866 }
1867
b980ac18 1868 /* for version 2 capabilities we need to write the config space
009bc06e
AD		 1869 * directly in order to set the completion timeout value for
1870 * 16ms to 55ms
1871 */
1872 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1873 &pcie_devctl2);
1874 if (ret_val)
1875 goto out;
1876
1877 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1878
1879 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1880 &pcie_devctl2);
1881out:
1882 /* disable completion timeout resend */
1883 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1884
1885 wr32(E1000_GCR, gcr);
1886 return ret_val;
1887}
1888
13800469
GR		 1889/**
1890 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1891 * @hw: pointer to the hardware struct
1892 * @enable: state to enter, either enabled or disabled
1893 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1894 *
1895 * enables/disables L2 switch anti-spoofing functionality.
1896 **/
1897void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1898{
22c12752 1899 u32 reg_val, reg_offset;
13800469
GR		 1900
1901 switch (hw->mac.type) {
1902 case e1000_82576:
22c12752
LL		 1903 reg_offset = E1000_DTXSWC;
1904 break;
13800469 1905 case e1000_i350:
ceb5f13b 1906 case e1000_i354:
22c12752 1907 reg_offset = E1000_TXSWC;
13800469
GR		 1908 break;
1909 default:
22c12752
LL		 1910 return;
1911 }
1912
1913 reg_val = rd32(reg_offset);
1914 if (enable) {
1915 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1916 E1000_DTXSWC_VLAN_SPOOF_MASK);
1917 /* The PF can spoof - it has to in order to
1918 * support emulation mode NICs
1919 */
1920 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1921 } else {
1922 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1923 E1000_DTXSWC_VLAN_SPOOF_MASK);
13800469 1924 }
22c12752 1925 wr32(reg_offset, reg_val);
13800469
GR		 1926}
1927
4ae196df
AD		 1928/**
1929 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1930 * @hw: pointer to the hardware struct
1931 * @enable: state to enter, either enabled or disabled
1932 *
1933 * enables/disables L2 switch loopback functionality.
1934 **/
1935void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1936{
ca2e3e7e
AA		 1937 u32 dtxswc;
1938
1939 switch (hw->mac.type) {
1940 case e1000_82576:
1941 dtxswc = rd32(E1000_DTXSWC);
1942 if (enable)
1943 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1944 else
1945 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1946 wr32(E1000_DTXSWC, dtxswc);
1947 break;
ceb5f13b 1948 case e1000_i354:
ca2e3e7e
AA		 1949 case e1000_i350:
1950 dtxswc = rd32(E1000_TXSWC);
1951 if (enable)
1952 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1953 else
1954 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1955 wr32(E1000_TXSWC, dtxswc);
1956 break;
1957 default:
1958 /* Currently no other hardware supports loopback */
1959 break;
1960 }
4ae196df 1961
4ae196df
AD		 1962}
1963
1964/**
1965 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1966 * @hw: pointer to the hardware struct
1967 * @enable: state to enter, either enabled or disabled
1968 *
1969 * enables/disables replication of packets across multiple pools.
1970 **/
1971void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1972{
1973 u32 vt_ctl = rd32(E1000_VT_CTL);
1974
1975 if (enable)
1976 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1977 else
1978 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1979
1980 wr32(E1000_VT_CTL, vt_ctl);
1981}
1982
bb2ac47b
AD		 1983/**
1984 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1985 * @hw: pointer to the HW structure
1986 * @offset: register offset to be read
1987 * @data: pointer to the read data
1988 *
1989 * Reads the MDI control register in the PHY at offset and stores the
1990 * information read to data.
1991 **/
1992static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1993{
bb2ac47b
AD		 1994 s32 ret_val;
1995
bb2ac47b
AD		 1996 ret_val = hw->phy.ops.acquire(hw);
1997 if (ret_val)
1998 goto out;
1999
bb2ac47b
AD		 2000 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2001
2002 hw->phy.ops.release(hw);
2003
2004out:
2005 return ret_val;
2006}
2007
2008/**
2009 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2010 * @hw: pointer to the HW structure
2011 * @offset: register offset to write to
2012 * @data: data to write to register at offset
2013 *
2014 * Writes data to MDI control register in the PHY at offset.
2015 **/
2016static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2017{
bb2ac47b
AD		 2018 s32 ret_val;
2019
2020
2021 ret_val = hw->phy.ops.acquire(hw);
2022 if (ret_val)
2023 goto out;
2024
bb2ac47b
AD		 2025 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2026
2027 hw->phy.ops.release(hw);
2028
2029out:
2030 return ret_val;
2031}
2032
08451e25
NN		 2033/**
2034 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2035 * @hw: pointer to the HW structure
2036 *
2037 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2038 * the values found in the EEPROM. This addresses an issue in which these
2039 * bits are not restored from EEPROM after reset.
2040 **/
2041static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2042{
2043 s32 ret_val = 0;
2044 u32 mdicnfg;
1b5dda33 2045 u16 nvm_data = 0;
08451e25
NN		 2046
2047 if (hw->mac.type != e1000_82580)
2048 goto out;
2049 if (!igb_sgmii_active_82575(hw))
2050 goto out;
2051
2052 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2053 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2054 &nvm_data);
2055 if (ret_val) {
2056 hw_dbg("NVM Read Error\n");
2057 goto out;
2058 }
2059
2060 mdicnfg = rd32(E1000_MDICNFG);
2061 if (nvm_data & NVM_WORD24_EXT_MDIO)
2062 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2063 if (nvm_data & NVM_WORD24_COM_MDIO)
2064 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2065 wr32(E1000_MDICNFG, mdicnfg);
2066out:
2067 return ret_val;
2068}
2069
bb2ac47b
AD		 2070/**
2071 * igb_reset_hw_82580 - Reset hardware
2072 * @hw: pointer to the HW structure
2073 *
2074 * This resets function or entire device (all ports, etc.)
2075 * to a known state.
2076 **/
2077static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2078{
2079 s32 ret_val = 0;
2080 /* BH SW mailbox bit in SW_FW_SYNC */
2081 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
e5c3370f 2082 u32 ctrl;
bb2ac47b
AD		 2083 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2084
bb2ac47b
AD		 2085 hw->dev_spec._82575.global_device_reset = false;
2086
a0483e2e
CW		 2087 /* due to hw errata, global device reset doesn't always
2088 * work on 82580
2089 */
2090 if (hw->mac.type == e1000_82580)
2091 global_device_reset = false;
2092
bb2ac47b
AD		 2093 /* Get current control state. */
2094 ctrl = rd32(E1000_CTRL);
2095
b980ac18 2096 /* Prevent the PCI-E bus from sticking if there is no TLP connection
bb2ac47b
AD		 2097 * on the last TLP read/write transaction when MAC is reset.
2098 */
2099 ret_val = igb_disable_pcie_master(hw);
2100 if (ret_val)
2101 hw_dbg("PCI-E Master disable polling has failed.\n");
2102
2103 hw_dbg("Masking off all interrupts\n");
2104 wr32(E1000_IMC, 0xffffffff);
2105 wr32(E1000_RCTL, 0);
2106 wr32(E1000_TCTL, E1000_TCTL_PSP);
2107 wrfl();
2108
2109 msleep(10);
2110
2111 /* Determine whether or not a global dev reset is requested */
2112 if (global_device_reset &&
f96a8a0b 2113 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
bb2ac47b
AD		 2114 global_device_reset = false;
2115
2116 if (global_device_reset &&
2117 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2118 ctrl |= E1000_CTRL_DEV_RST;
2119 else
2120 ctrl |= E1000_CTRL_RST;
2121
2122 wr32(E1000_CTRL, ctrl);
064b4330 2123 wrfl();
bb2ac47b
AD		 2124
2125 /* Add delay to insure DEV_RST has time to complete */
2126 if (global_device_reset)
2127 msleep(5);
2128
2129 ret_val = igb_get_auto_rd_done(hw);
2130 if (ret_val) {
b980ac18 2131 /* When auto config read does not complete, do not
bb2ac47b
AD		 2132 * return with an error. This can happen in situations
2133 * where there is no eeprom and prevents getting link.
2134 */
2135 hw_dbg("Auto Read Done did not complete\n");
2136 }
2137
bb2ac47b
AD		 2138 /* clear global device reset status bit */
2139 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2140
2141 /* Clear any pending interrupt events. */
2142 wr32(E1000_IMC, 0xffffffff);
e5c3370f 2143 rd32(E1000_ICR);
bb2ac47b 2144
08451e25
NN		 2145 ret_val = igb_reset_mdicnfg_82580(hw);
2146 if (ret_val)
2147 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2148
bb2ac47b
AD		 2149 /* Install any alternate MAC address into RAR0 */
2150 ret_val = igb_check_alt_mac_addr(hw);
2151
2152 /* Release semaphore */
2153 if (global_device_reset)
f96a8a0b 2154 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
bb2ac47b
AD		 2155
2156 return ret_val;
2157}
2158
2159/**
2160 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2161 * @data: data received by reading RXPBS register
2162 *
2163 * The 82580 uses a table based approach for packet buffer allocation sizes.
2164 * This function converts the retrieved value into the correct table value
2165 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2166 * 0x0 36 72 144 1 2 4 8 16
2167 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2168 */
2169u16 igb_rxpbs_adjust_82580(u32 data)
2170{
2171 u16 ret_val = 0;
2172
2173 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2174 ret_val = e1000_82580_rxpbs_table[data];
2175
2176 return ret_val;
2177}
2178
4322e561
CW		 2179/**
2180 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2181 * checksum
2182 * @hw: pointer to the HW structure
2183 * @offset: offset in words of the checksum protected region
2184 *
2185 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2186 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2187 **/
bed45a6e
ET		 2188static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2189 u16 offset)
4322e561
CW		 2190{
2191 s32 ret_val = 0;
2192 u16 checksum = 0;
2193 u16 i, nvm_data;
2194
2195 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2196 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2197 if (ret_val) {
2198 hw_dbg("NVM Read Error\n");
2199 goto out;
2200 }
2201 checksum += nvm_data;
2202 }
2203
2204 if (checksum != (u16) NVM_SUM) {
2205 hw_dbg("NVM Checksum Invalid\n");
2206 ret_val = -E1000_ERR_NVM;
2207 goto out;
2208 }
2209
2210out:
2211 return ret_val;
2212}
2213
2214/**
2215 * igb_update_nvm_checksum_with_offset - Update EEPROM
2216 * checksum
2217 * @hw: pointer to the HW structure
2218 * @offset: offset in words of the checksum protected region
2219 *
2220 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2221 * up to the checksum. Then calculates the EEPROM checksum and writes the
2222 * value to the EEPROM.
2223 **/
bed45a6e 2224static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
4322e561
CW		 2225{
2226 s32 ret_val;
2227 u16 checksum = 0;
2228 u16 i, nvm_data;
2229
2230 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2231 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2232 if (ret_val) {
2233 hw_dbg("NVM Read Error while updating checksum.\n");
2234 goto out;
2235 }
2236 checksum += nvm_data;
2237 }
2238 checksum = (u16) NVM_SUM - checksum;
2239 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2240 &checksum);
2241 if (ret_val)
2242 hw_dbg("NVM Write Error while updating checksum.\n");
2243
2244out:
2245 return ret_val;
2246}
2247
2248/**
2249 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2250 * @hw: pointer to the HW structure
2251 *
2252 * Calculates the EEPROM section checksum by reading/adding each word of
2253 * the EEPROM and then verifies that the sum of the EEPROM is
2254 * equal to 0xBABA.
2255 **/
2256static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2257{
2258 s32 ret_val = 0;
2259 u16 eeprom_regions_count = 1;
2260 u16 j, nvm_data;
2261 u16 nvm_offset;
2262
2263 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2264 if (ret_val) {
2265 hw_dbg("NVM Read Error\n");
2266 goto out;
2267 }
2268
2269 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
34a0326e 2270 /* if checksums compatibility bit is set validate checksums
b980ac18
JK		 2271 * for all 4 ports.
2272 */
4322e561
CW		 2273 eeprom_regions_count = 4;
2274 }
2275
2276 for (j = 0; j < eeprom_regions_count; j++) {
2277 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2278 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2279 nvm_offset);
2280 if (ret_val != 0)
2281 goto out;
2282 }
2283
2284out:
2285 return ret_val;
2286}
2287
2288/**
2289 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2290 * @hw: pointer to the HW structure
2291 *
2292 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2293 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2294 * checksum and writes the value to the EEPROM.
2295 **/
2296static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2297{
2298 s32 ret_val;
2299 u16 j, nvm_data;
2300 u16 nvm_offset;
2301
2302 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2303 if (ret_val) {
2304 hw_dbg("NVM Read Error while updating checksum"
2305 " compatibility bit.\n");
2306 goto out;
2307 }
2308
2309 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2310 /* set compatibility bit to validate checksums appropriately */
2311 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2312 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2313 &nvm_data);
2314 if (ret_val) {
2315 hw_dbg("NVM Write Error while updating checksum"
2316 " compatibility bit.\n");
2317 goto out;
2318 }
2319 }
2320
2321 for (j = 0; j < 4; j++) {
2322 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2323 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2324 if (ret_val)
2325 goto out;
2326 }
2327
2328out:
2329 return ret_val;
2330}
2331
2332/**
2333 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2334 * @hw: pointer to the HW structure
2335 *
2336 * Calculates the EEPROM section checksum by reading/adding each word of
2337 * the EEPROM and then verifies that the sum of the EEPROM is
2338 * equal to 0xBABA.
2339 **/
2340static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2341{
2342 s32 ret_val = 0;
2343 u16 j;
2344 u16 nvm_offset;
2345
2346 for (j = 0; j < 4; j++) {
2347 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2348 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2349 nvm_offset);
2350 if (ret_val != 0)
2351 goto out;
2352 }
2353
2354out:
2355 return ret_val;
2356}
2357
2358/**
2359 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2360 * @hw: pointer to the HW structure
2361 *
2362 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2363 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2364 * checksum and writes the value to the EEPROM.
2365 **/
2366static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2367{
2368 s32 ret_val = 0;
2369 u16 j;
2370 u16 nvm_offset;
2371
2372 for (j = 0; j < 4; j++) {
2373 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2374 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2375 if (ret_val != 0)
2376 goto out;
2377 }
2378
2379out:
2380 return ret_val;
2381}
34a0326e 2382
87371b9d
MV		 2383/**
2384 * __igb_access_emi_reg - Read/write EMI register
2385 * @hw: pointer to the HW structure
2386 * @addr: EMI address to program
2387 * @data: pointer to value to read/write from/to the EMI address
2388 * @read: boolean flag to indicate read or write
2389 **/
2390static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2391 u16 *data, bool read)
2392{
2393 s32 ret_val = E1000_SUCCESS;
2394
2395 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2396 if (ret_val)
2397 return ret_val;
2398
2399 if (read)
2400 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2401 else
2402 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2403
2404 return ret_val;
2405}
2406
2407/**
2408 * igb_read_emi_reg - Read Extended Management Interface register
2409 * @hw: pointer to the HW structure
2410 * @addr: EMI address to program
2411 * @data: value to be read from the EMI address
2412 **/
2413s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2414{
2415 return __igb_access_emi_reg(hw, addr, data, true);
2416}
2417
09b068d4
CW		 2418/**
2419 * igb_set_eee_i350 - Enable/disable EEE support
2420 * @hw: pointer to the HW structure
2421 *
2422 * Enable/disable EEE based on setting in dev_spec structure.
2423 *
2424 **/
2425s32 igb_set_eee_i350(struct e1000_hw *hw)
2426{
2427 s32 ret_val = 0;
e5461112 2428 u32 ipcnfg, eeer;
09b068d4 2429
e5461112
AA		 2430 if ((hw->mac.type < e1000_i350) ||
2431 (hw->phy.media_type != e1000_media_type_copper))
09b068d4
CW		 2432 goto out;
2433 ipcnfg = rd32(E1000_IPCNFG);
2434 eeer = rd32(E1000_EEER);
2435
2436 /* enable or disable per user setting */
2437 if (!(hw->dev_spec._82575.eee_disable)) {
40b20122
CW		 2438 u32 eee_su = rd32(E1000_EEE_SU);
2439
2440 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2441 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
09b068d4
CW		 2442 E1000_EEER_LPI_FC);
2443
40b20122
CW		 2444 /* This bit should not be set in normal operation. */
2445 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2446 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2447
09b068d4
CW		 2448 } else {
2449 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2450 E1000_IPCNFG_EEE_100M_AN);
2451 eeer &= ~(E1000_EEER_TX_LPI_EN |
2452 E1000_EEER_RX_LPI_EN |
2453 E1000_EEER_LPI_FC);
2454 }
2455 wr32(E1000_IPCNFG, ipcnfg);
2456 wr32(E1000_EEER, eeer);
e5461112
AA		 2457 rd32(E1000_IPCNFG);
2458 rd32(E1000_EEER);
09b068d4
CW		 2459out:
2460
2461 return ret_val;
2462}
4322e561 2463
ceb5f13b
CW		 2464/**
2465 * igb_set_eee_i354 - Enable/disable EEE support
2466 * @hw: pointer to the HW structure
2467 *
2468 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2469 *
2470 **/
2471s32 igb_set_eee_i354(struct e1000_hw *hw)
2472{
2473 struct e1000_phy_info *phy = &hw->phy;
2474 s32 ret_val = 0;
2475 u16 phy_data;
2476
2477 if ((hw->phy.media_type != e1000_media_type_copper) ||
2478 (phy->id != M88E1545_E_PHY_ID))
2479 goto out;
2480
2481 if (!hw->dev_spec._82575.eee_disable) {
2482 /* Switch to PHY page 18. */
2483 ret_val = phy->ops.write_reg(hw, E1000_M88E1545_PAGE_ADDR, 18);
2484 if (ret_val)
2485 goto out;
2486
2487 ret_val = phy->ops.read_reg(hw, E1000_M88E1545_EEE_CTRL_1,
2488 &phy_data);
2489 if (ret_val)
2490 goto out;
2491
2492 phy_data |= E1000_M88E1545_EEE_CTRL_1_MS;
2493 ret_val = phy->ops.write_reg(hw, E1000_M88E1545_EEE_CTRL_1,
2494 phy_data);
2495 if (ret_val)
2496 goto out;
2497
2498 /* Return the PHY to page 0. */
2499 ret_val = phy->ops.write_reg(hw, E1000_M88E1545_PAGE_ADDR, 0);
2500 if (ret_val)
2501 goto out;
2502
2503 /* Turn on EEE advertisement. */
2504 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2505 E1000_EEE_ADV_DEV_I354,
2506 &phy_data);
2507 if (ret_val)
2508 goto out;
2509
2510 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2511 E1000_EEE_ADV_1000_SUPPORTED;
2512 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2513 E1000_EEE_ADV_DEV_I354,
2514 phy_data);
2515 } else {
2516 /* Turn off EEE advertisement. */
2517 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2518 E1000_EEE_ADV_DEV_I354,
2519 &phy_data);
2520 if (ret_val)
2521 goto out;
2522
2523 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2524 E1000_EEE_ADV_1000_SUPPORTED);
2525 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2526 E1000_EEE_ADV_DEV_I354,
2527 phy_data);
2528 }
2529
2530out:
2531 return ret_val;
2532}
2533
2534/**
2535 * igb_get_eee_status_i354 - Get EEE status
2536 * @hw: pointer to the HW structure
2537 * @status: EEE status
2538 *
2539 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2540 * been received.
2541 **/
2542s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2543{
2544 struct e1000_phy_info *phy = &hw->phy;
2545 s32 ret_val = 0;
2546 u16 phy_data;
2547
2548 /* Check if EEE is supported on this device. */
2549 if ((hw->phy.media_type != e1000_media_type_copper) ||
2550 (phy->id != M88E1545_E_PHY_ID))
2551 goto out;
2552
2553 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2554 E1000_PCS_STATUS_DEV_I354,
2555 &phy_data);
2556 if (ret_val)
2557 goto out;
2558
2559 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2560 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2561
2562out:
2563 return ret_val;
2564}
2565
e428893b
CW		 2566static const u8 e1000_emc_temp_data[4] = {
2567 E1000_EMC_INTERNAL_DATA,
2568 E1000_EMC_DIODE1_DATA,
2569 E1000_EMC_DIODE2_DATA,
2570 E1000_EMC_DIODE3_DATA
2571};
2572static const u8 e1000_emc_therm_limit[4] = {
2573 E1000_EMC_INTERNAL_THERM_LIMIT,
2574 E1000_EMC_DIODE1_THERM_LIMIT,
2575 E1000_EMC_DIODE2_THERM_LIMIT,
2576 E1000_EMC_DIODE3_THERM_LIMIT
2577};
2578
b980ac18
JK		 2579/**
2580 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
e428893b
CW		 2581 * @hw: pointer to hardware structure
2582 *
2583 * Updates the temperatures in mac.thermal_sensor_data
b980ac18 2584 **/
e428893b
CW		 2585s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2586{
2587 s32 status = E1000_SUCCESS;
2588 u16 ets_offset;
2589 u16 ets_cfg;
2590 u16 ets_sensor;
2591 u8 num_sensors;
2592 u8 sensor_index;
2593 u8 sensor_location;
2594 u8 i;
2595 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2596
2597 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2598 return E1000_NOT_IMPLEMENTED;
2599
2600 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2601
2602 /* Return the internal sensor only if ETS is unsupported */
2603 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2604 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2605 return status;
2606
2607 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2608 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2609 != NVM_ETS_TYPE_EMC)
2610 return E1000_NOT_IMPLEMENTED;
2611
2612 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2613 if (num_sensors > E1000_MAX_SENSORS)
2614 num_sensors = E1000_MAX_SENSORS;
2615
2616 for (i = 1; i < num_sensors; i++) {
2617 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2618 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2619 NVM_ETS_DATA_INDEX_SHIFT);
2620 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2621 NVM_ETS_DATA_LOC_SHIFT);
2622
2623 if (sensor_location != 0)
2624 hw->phy.ops.read_i2c_byte(hw,
2625 e1000_emc_temp_data[sensor_index],
2626 E1000_I2C_THERMAL_SENSOR_ADDR,
2627 &data->sensor[i].temp);
2628 }
2629 return status;
2630}
2631
b980ac18
JK		 2632/**
2633 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
e428893b
CW		 2634 * @hw: pointer to hardware structure
2635 *
2636 * Sets the thermal sensor thresholds according to the NVM map
2637 * and save off the threshold and location values into mac.thermal_sensor_data
b980ac18 2638 **/
e428893b
CW		 2639s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2640{
2641 s32 status = E1000_SUCCESS;
2642 u16 ets_offset;
2643 u16 ets_cfg;
2644 u16 ets_sensor;
2645 u8 low_thresh_delta;
2646 u8 num_sensors;
2647 u8 sensor_index;
2648 u8 sensor_location;
2649 u8 therm_limit;
2650 u8 i;
2651 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2652
2653 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2654 return E1000_NOT_IMPLEMENTED;
2655
2656 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2657
2658 data->sensor[0].location = 0x1;
2659 data->sensor[0].caution_thresh =
2660 (rd32(E1000_THHIGHTC) & 0xFF);
2661 data->sensor[0].max_op_thresh =
2662 (rd32(E1000_THLOWTC) & 0xFF);
2663
2664 /* Return the internal sensor only if ETS is unsupported */
2665 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2666 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2667 return status;
2668
2669 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2670 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2671 != NVM_ETS_TYPE_EMC)
2672 return E1000_NOT_IMPLEMENTED;
2673
2674 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2675 NVM_ETS_LTHRES_DELTA_SHIFT);
2676 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2677
2678 for (i = 1; i <= num_sensors; i++) {
2679 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2680 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2681 NVM_ETS_DATA_INDEX_SHIFT);
2682 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2683 NVM_ETS_DATA_LOC_SHIFT);
2684 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2685
2686 hw->phy.ops.write_i2c_byte(hw,
2687 e1000_emc_therm_limit[sensor_index],
2688 E1000_I2C_THERMAL_SENSOR_ADDR,
2689 therm_limit);
2690
2691 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2692 data->sensor[i].location = sensor_location;
2693 data->sensor[i].caution_thresh = therm_limit;
2694 data->sensor[i].max_op_thresh = therm_limit -
2695 low_thresh_delta;
2696 }
2697 }
2698 return status;
2699}
2700
9d5c8243 2701static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 2702 .init_hw = igb_init_hw_82575,
2703 .check_for_link = igb_check_for_link_82575,
2d064c06 2704 .rar_set = igb_rar_set,
9d5c8243
AK		 2705 .read_mac_addr = igb_read_mac_addr_82575,
2706 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
e428893b
CW		 2707#ifdef CONFIG_IGB_HWMON
2708 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2709 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2710#endif
9d5c8243
AK		 2711};
2712
2713static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 2714 .acquire = igb_acquire_phy_82575,
9d5c8243 2715 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 2716 .release = igb_release_phy_82575,
441fc6fd
CW		 2717 .write_i2c_byte = igb_write_i2c_byte,
2718 .read_i2c_byte = igb_read_i2c_byte,
9d5c8243
AK		 2719};
2720
2721static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 2722 .acquire = igb_acquire_nvm_82575,
2723 .read = igb_read_nvm_eerd,
2724 .release = igb_release_nvm_82575,
2725 .write = igb_write_nvm_spi,
9d5c8243
AK		 2726};
2727
2728const struct e1000_info e1000_82575_info = {
2729 .get_invariants = igb_get_invariants_82575,
2730 .mac_ops = &e1000_mac_ops_82575,
2731 .phy_ops = &e1000_phy_ops_82575,
2732 .nvm_ops = &e1000_nvm_ops_82575,
2733};
2734
Linux kernel - Deliverables
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