projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: Move DMA Coalescing init code to separate function.
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4297f99b 4 Copyright(c) 2007-2011 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* e1000_82575
29 * e1000_82576
30 */
31
32#include <linux/types.h>
2d064c06 33#include <linux/if_ether.h>
9d5c8243
AK		 34
35#include "e1000_mac.h"
36#include "e1000_82575.h"
37
38static s32 igb_get_invariants_82575(struct e1000_hw *);
39static s32 igb_acquire_phy_82575(struct e1000_hw *);
40static void igb_release_phy_82575(struct e1000_hw *);
41static s32 igb_acquire_nvm_82575(struct e1000_hw *);
42static void igb_release_nvm_82575(struct e1000_hw *);
43static s32 igb_check_for_link_82575(struct e1000_hw *);
44static s32 igb_get_cfg_done_82575(struct e1000_hw *);
45static s32 igb_init_hw_82575(struct e1000_hw *);
46static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
47static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 48static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
49static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 50static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 51static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243
AK		 52static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
53static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 54static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 55static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
56static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
57static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 58static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
59 u16 *);
60static s32 igb_get_phy_id_82575(struct e1000_hw *);
61static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
62static bool igb_sgmii_active_82575(struct e1000_hw *);
63static s32 igb_reset_init_script_82575(struct e1000_hw *);
64static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 65static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
99870a73 66static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
4322e561
CW		 67static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
68static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
4322e561
CW		 69static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
70static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
bb2ac47b
AD		 71static const u16 e1000_82580_rxpbs_table[] =
72 { 36, 72, 144, 1, 2, 4, 8, 16,
73 35, 70, 140 };
74#define E1000_82580_RXPBS_TABLE_SIZE \
75 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
76
4085f746
NN		 77/**
78 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
79 * @hw: pointer to the HW structure
80 *
81 * Called to determine if the I2C pins are being used for I2C or as an
82 * external MDIO interface since the two options are mutually exclusive.
83 **/
84static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
85{
86 u32 reg = 0;
87 bool ext_mdio = false;
88
89 switch (hw->mac.type) {
90 case e1000_82575:
91 case e1000_82576:
92 reg = rd32(E1000_MDIC);
93 ext_mdio = !!(reg & E1000_MDIC_DEST);
94 break;
95 case e1000_82580:
96 case e1000_i350:
97 reg = rd32(E1000_MDICNFG);
98 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
99 break;
100 default:
101 break;
102 }
103 return ext_mdio;
104}
105
9d5c8243
AK		 106static s32 igb_get_invariants_82575(struct e1000_hw *hw)
107{
108 struct e1000_phy_info *phy = &hw->phy;
109 struct e1000_nvm_info *nvm = &hw->nvm;
110 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 111 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243
AK		 112 u32 eecd;
113 s32 ret_val;
114 u16 size;
115 u32 ctrl_ext = 0;
116
117 switch (hw->device_id) {
118 case E1000_DEV_ID_82575EB_COPPER:
119 case E1000_DEV_ID_82575EB_FIBER_SERDES:
120 case E1000_DEV_ID_82575GB_QUAD_COPPER:
121 mac->type = e1000_82575;
122 break;
2d064c06 123 case E1000_DEV_ID_82576:
9eb2341d 124 case E1000_DEV_ID_82576_NS:
747d49ba 125 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 126 case E1000_DEV_ID_82576_FIBER:
127 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 128 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 129 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 130 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 131 mac->type = e1000_82576;
132 break;
bb2ac47b
AD		 133 case E1000_DEV_ID_82580_COPPER:
134 case E1000_DEV_ID_82580_FIBER:
6493d24f 135 case E1000_DEV_ID_82580_QUAD_FIBER:
bb2ac47b
AD		 136 case E1000_DEV_ID_82580_SERDES:
137 case E1000_DEV_ID_82580_SGMII:
138 case E1000_DEV_ID_82580_COPPER_DUAL:
308fb39a
JG		 139 case E1000_DEV_ID_DH89XXCC_SGMII:
140 case E1000_DEV_ID_DH89XXCC_SERDES:
1b5dda33
GJ		 141 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
142 case E1000_DEV_ID_DH89XXCC_SFP:
bb2ac47b
AD		 143 mac->type = e1000_82580;
144 break;
d2ba2ed8
AD		 145 case E1000_DEV_ID_I350_COPPER:
146 case E1000_DEV_ID_I350_FIBER:
147 case E1000_DEV_ID_I350_SERDES:
148 case E1000_DEV_ID_I350_SGMII:
149 mac->type = e1000_i350;
150 break;
9d5c8243
AK		 151 default:
152 return -E1000_ERR_MAC_INIT;
153 break;
154 }
155
9d5c8243
AK		 156 /* Set media type */
157 /*
158 * The 82575 uses bits 22:23 for link mode. The mode can be changed
159 * based on the EEPROM. We cannot rely upon device ID. There
160 * is no distinguishable difference between fiber and internal
161 * SerDes mode on the 82575. There can be an external PHY attached
162 * on the SGMII interface. For this, we'll set sgmii_active to true.
163 */
164 phy->media_type = e1000_media_type_copper;
165 dev_spec->sgmii_active = false;
166
167 ctrl_ext = rd32(E1000_CTRL_EXT);
2fb02a26
AD		 168 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
169 case E1000_CTRL_EXT_LINK_MODE_SGMII:
9d5c8243 170 dev_spec->sgmii_active = true;
2fb02a26 171 break;
bb2ac47b 172 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26
AD		 173 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
174 hw->phy.media_type = e1000_media_type_internal_serdes;
2fb02a26
AD		 175 break;
176 default:
2fb02a26 177 break;
9d5c8243 178 }
2fb02a26 179
9d5c8243
AK		 180 /* Set mta register count */
181 mac->mta_reg_count = 128;
182 /* Set rar entry count */
183 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
2d064c06
AD		 184 if (mac->type == e1000_82576)
185 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
bb2ac47b
AD		 186 if (mac->type == e1000_82580)
187 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
d2ba2ed8
AD		 188 if (mac->type == e1000_i350)
189 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
bb2ac47b 190 /* reset */
d2ba2ed8 191 if (mac->type >= e1000_82580)
bb2ac47b
AD		 192 mac->ops.reset_hw = igb_reset_hw_82580;
193 else
194 mac->ops.reset_hw = igb_reset_hw_82575;
9d5c8243
AK		 195 /* Set if part includes ASF firmware */
196 mac->asf_firmware_present = true;
197 /* Set if manageability features are enabled. */
198 mac->arc_subsystem_valid =
199 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
200 ? true : false;
09b068d4
CW		 201 /* enable EEE on i350 parts */
202 if (mac->type == e1000_i350)
203 dev_spec->eee_disable = false;
204 else
205 dev_spec->eee_disable = true;
9d5c8243
AK		 206 /* physical interface link setup */
207 mac->ops.setup_physical_interface =
208 (hw->phy.media_type == e1000_media_type_copper)
209 ? igb_setup_copper_link_82575
2fb02a26 210 : igb_setup_serdes_link_82575;
9d5c8243
AK		 211
212 /* NVM initialization */
213 eecd = rd32(E1000_EECD);
214
215 nvm->opcode_bits = 8;
216 nvm->delay_usec = 1;
217 switch (nvm->override) {
218 case e1000_nvm_override_spi_large:
219 nvm->page_size = 32;
220 nvm->address_bits = 16;
221 break;
222 case e1000_nvm_override_spi_small:
223 nvm->page_size = 8;
224 nvm->address_bits = 8;
225 break;
226 default:
227 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
228 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
229 break;
230 }
231
232 nvm->type = e1000_nvm_eeprom_spi;
233
234 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
235 E1000_EECD_SIZE_EX_SHIFT);
236
237 /*
238 * Added to a constant, "size" becomes the left-shift value
239 * for setting word_size.
240 */
241 size += NVM_WORD_SIZE_BASE_SHIFT;
5c3cad75 242
f6b1bfd1
CW		 243 /*
244 * Check for invalid size
245 */
246 if ((hw->mac.type == e1000_82576) && (size > 15)) {
247 printk("igb: The NVM size is not valid, "
248 "defaulting to 32K.\n");
249 size = 15;
250 }
9d5c8243 251 nvm->word_size = 1 << size;
4322e561
CW		 252 if (nvm->word_size == (1 << 15))
253 nvm->page_size = 128;
254
255 /* NVM Function Pointers */
256 nvm->ops.acquire = igb_acquire_nvm_82575;
257 if (nvm->word_size < (1 << 15))
258 nvm->ops.read = igb_read_nvm_eerd;
259 else
260 nvm->ops.read = igb_read_nvm_spi;
261
262 nvm->ops.release = igb_release_nvm_82575;
263 switch (hw->mac.type) {
264 case e1000_82580:
265 nvm->ops.validate = igb_validate_nvm_checksum_82580;
266 nvm->ops.update = igb_update_nvm_checksum_82580;
267 break;
268 case e1000_i350:
269 nvm->ops.validate = igb_validate_nvm_checksum_i350;
270 nvm->ops.update = igb_update_nvm_checksum_i350;
271 break;
272 default:
273 nvm->ops.validate = igb_validate_nvm_checksum;
274 nvm->ops.update = igb_update_nvm_checksum;
275 }
276 nvm->ops.write = igb_write_nvm_spi;
9d5c8243 277
6b78bb1d
CW		 278 /* if part supports SR-IOV then initialize mailbox parameters */
279 switch (mac->type) {
280 case e1000_82576:
281 case e1000_i350:
a0c98605 282 igb_init_mbx_params_pf(hw);
6b78bb1d
CW		 283 break;
284 default:
285 break;
286 }
a0c98605 287
9d5c8243
AK		 288 /* setup PHY parameters */
289 if (phy->media_type != e1000_media_type_copper) {
290 phy->type = e1000_phy_none;
291 return 0;
292 }
293
294 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
295 phy->reset_delay_us = 100;
296
99870a73
AD		 297 ctrl_ext = rd32(E1000_CTRL_EXT);
298
9d5c8243 299 /* PHY function pointers */
99870a73 300 if (igb_sgmii_active_82575(hw)) {
4085f746 301 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
99870a73
AD		 302 ctrl_ext |= E1000_CTRL_I2C_ENA;
303 } else {
4085f746 304 phy->ops.reset = igb_phy_hw_reset;
99870a73
AD		 305 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
306 }
307
308 wr32(E1000_CTRL_EXT, ctrl_ext);
309 igb_reset_mdicnfg_82580(hw);
4085f746
NN		 310
311 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
312 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
313 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
d2ba2ed8 314 } else if (hw->mac.type >= e1000_82580) {
4085f746
NN		 315 phy->ops.read_reg = igb_read_phy_reg_82580;
316 phy->ops.write_reg = igb_write_phy_reg_82580;
9d5c8243 317 } else {
4085f746
NN		 318 phy->ops.read_reg = igb_read_phy_reg_igp;
319 phy->ops.write_reg = igb_write_phy_reg_igp;
9d5c8243
AK		 320 }
321
19e588e7
AD		 322 /* set lan id */
323 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
324 E1000_STATUS_FUNC_SHIFT;
325
9d5c8243
AK		 326 /* Set phy->phy_addr and phy->id. */
327 ret_val = igb_get_phy_id_82575(hw);
328 if (ret_val)
329 return ret_val;
330
331 /* Verify phy id and set remaining function pointers */
332 switch (phy->id) {
308fb39a
JG		 333 case I347AT4_E_PHY_ID:
334 case M88E1112_E_PHY_ID:
9d5c8243
AK		 335 case M88E1111_I_PHY_ID:
336 phy->type = e1000_phy_m88;
337 phy->ops.get_phy_info = igb_get_phy_info_m88;
308fb39a
JG		 338
339 if (phy->id == I347AT4_E_PHY_ID ||
340 phy->id == M88E1112_E_PHY_ID)
341 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
342 else
343 phy->ops.get_cable_length = igb_get_cable_length_m88;
344
9d5c8243
AK		 345 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
346 break;
347 case IGP03E1000_E_PHY_ID:
348 phy->type = e1000_phy_igp_3;
349 phy->ops.get_phy_info = igb_get_phy_info_igp;
350 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
351 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
352 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
353 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
354 break;
bb2ac47b 355 case I82580_I_PHY_ID:
d2ba2ed8 356 case I350_I_PHY_ID:
bb2ac47b
AD		 357 phy->type = e1000_phy_82580;
358 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580;
359 phy->ops.get_cable_length = igb_get_cable_length_82580;
360 phy->ops.get_phy_info = igb_get_phy_info_82580;
361 break;
9d5c8243
AK		 362 default:
363 return -E1000_ERR_PHY;
364 }
365
366 return 0;
367}
368
369/**
733596be 370 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 371 * @hw: pointer to the HW structure
372 *
373 * Acquire access rights to the correct PHY. This is a
374 * function pointer entry point called by the api module.
375 **/
376static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
377{
008c3422 378 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 379
008c3422
AD		 380 if (hw->bus.func == E1000_FUNC_1)
381 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 382 else if (hw->bus.func == E1000_FUNC_2)
383 mask = E1000_SWFW_PHY2_SM;
384 else if (hw->bus.func == E1000_FUNC_3)
385 mask = E1000_SWFW_PHY3_SM;
9d5c8243
AK		 386
387 return igb_acquire_swfw_sync_82575(hw, mask);
388}
389
390/**
733596be 391 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 392 * @hw: pointer to the HW structure
393 *
394 * A wrapper to release access rights to the correct PHY. This is a
395 * function pointer entry point called by the api module.
396 **/
397static void igb_release_phy_82575(struct e1000_hw *hw)
398{
008c3422
AD		 399 u16 mask = E1000_SWFW_PHY0_SM;
400
401 if (hw->bus.func == E1000_FUNC_1)
402 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 403 else if (hw->bus.func == E1000_FUNC_2)
404 mask = E1000_SWFW_PHY2_SM;
405 else if (hw->bus.func == E1000_FUNC_3)
406 mask = E1000_SWFW_PHY3_SM;
9d5c8243 407
9d5c8243
AK		 408 igb_release_swfw_sync_82575(hw, mask);
409}
410
411/**
733596be 412 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 413 * @hw: pointer to the HW structure
414 * @offset: register offset to be read
415 * @data: pointer to the read data
416 *
417 * Reads the PHY register at offset using the serial gigabit media independent
418 * interface and stores the retrieved information in data.
419 **/
420static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
421 u16 *data)
422{
bf6f7a92 423 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 424
425 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 426 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 427 goto out;
9d5c8243
AK		 428 }
429
bf6f7a92
AD		 430 ret_val = hw->phy.ops.acquire(hw);
431 if (ret_val)
432 goto out;
9d5c8243 433
bf6f7a92 434 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 435
bf6f7a92
AD		 436 hw->phy.ops.release(hw);
437
438out:
439 return ret_val;
9d5c8243
AK		 440}
441
442/**
733596be 443 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 444 * @hw: pointer to the HW structure
445 * @offset: register offset to write to
446 * @data: data to write at register offset
447 *
448 * Writes the data to PHY register at the offset using the serial gigabit
449 * media independent interface.
450 **/
451static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
452 u16 data)
453{
bf6f7a92
AD		 454 s32 ret_val = -E1000_ERR_PARAM;
455
9d5c8243
AK		 456
457 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 458 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 459 goto out;
9d5c8243
AK		 460 }
461
bf6f7a92
AD		 462 ret_val = hw->phy.ops.acquire(hw);
463 if (ret_val)
464 goto out;
9d5c8243 465
bf6f7a92 466 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 467
bf6f7a92
AD		 468 hw->phy.ops.release(hw);
469
470out:
471 return ret_val;
9d5c8243
AK		 472}
473
474/**
733596be 475 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 476 * @hw: pointer to the HW structure
477 *
652fff32 478 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 479 * sgmi interface.
480 **/
481static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
482{
483 struct e1000_phy_info *phy = &hw->phy;
484 s32 ret_val = 0;
485 u16 phy_id;
2fb02a26 486 u32 ctrl_ext;
4085f746 487 u32 mdic;
9d5c8243
AK		 488
489 /*
490 * For SGMII PHYs, we try the list of possible addresses until
491 * we find one that works. For non-SGMII PHYs
492 * (e.g. integrated copper PHYs), an address of 1 should
493 * work. The result of this function should mean phy->phy_addr
494 * and phy->id are set correctly.
495 */
496 if (!(igb_sgmii_active_82575(hw))) {
497 phy->addr = 1;
498 ret_val = igb_get_phy_id(hw);
499 goto out;
500 }
501
4085f746
NN		 502 if (igb_sgmii_uses_mdio_82575(hw)) {
503 switch (hw->mac.type) {
504 case e1000_82575:
505 case e1000_82576:
506 mdic = rd32(E1000_MDIC);
507 mdic &= E1000_MDIC_PHY_MASK;
508 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
509 break;
510 case e1000_82580:
511 case e1000_i350:
512 mdic = rd32(E1000_MDICNFG);
513 mdic &= E1000_MDICNFG_PHY_MASK;
514 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
515 break;
516 default:
517 ret_val = -E1000_ERR_PHY;
518 goto out;
519 break;
520 }
521 ret_val = igb_get_phy_id(hw);
522 goto out;
523 }
524
2fb02a26
AD		 525 /* Power on sgmii phy if it is disabled */
526 ctrl_ext = rd32(E1000_CTRL_EXT);
527 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
528 wrfl();
529 msleep(300);
530
9d5c8243
AK		 531 /*
532 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
533 * Therefore, we need to test 1-7
534 */
535 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
536 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
537 if (ret_val == 0) {
652fff32
AK		 538 hw_dbg("Vendor ID 0x%08X read at address %u\n",
539 phy_id, phy->addr);
9d5c8243
AK		 540 /*
541 * At the time of this writing, The M88 part is
542 * the only supported SGMII PHY product.
543 */
544 if (phy_id == M88_VENDOR)
545 break;
546 } else {
652fff32 547 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 548 }
549 }
550
551 /* A valid PHY type couldn't be found. */
552 if (phy->addr == 8) {
553 phy->addr = 0;
554 ret_val = -E1000_ERR_PHY;
555 goto out;
2fb02a26
AD		 556 } else {
557 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 558 }
559
2fb02a26
AD		 560 /* restore previous sfp cage power state */
561 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 562
563out:
564 return ret_val;
565}
566
567/**
733596be 568 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 569 * @hw: pointer to the HW structure
570 *
571 * Resets the PHY using the serial gigabit media independent interface.
572 **/
573static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
574{
575 s32 ret_val;
576
577 /*
578 * This isn't a true "hard" reset, but is the only reset
579 * available to us at this time.
580 */
581
652fff32 582 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243
AK		 583
584 /*
585 * SFP documentation requires the following to configure the SPF module
586 * to work on SGMII. No further documentation is given.
587 */
a8d2a0c2 588 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 589 if (ret_val)
590 goto out;
591
592 ret_val = igb_phy_sw_reset(hw);
593
594out:
595 return ret_val;
596}
597
598/**
733596be 599 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 600 * @hw: pointer to the HW structure
601 * @active: true to enable LPLU, false to disable
602 *
603 * Sets the LPLU D0 state according to the active flag. When
604 * activating LPLU this function also disables smart speed
605 * and vice versa. LPLU will not be activated unless the
606 * device autonegotiation advertisement meets standards of
607 * either 10 or 10/100 or 10/100/1000 at all duplexes.
608 * This is a function pointer entry point only called by
609 * PHY setup routines.
610 **/
611static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
612{
613 struct e1000_phy_info *phy = &hw->phy;
614 s32 ret_val;
615 u16 data;
616
a8d2a0c2 617 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 618 if (ret_val)
619 goto out;
620
621 if (active) {
622 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 623 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 624 data);
9d5c8243
AK		 625 if (ret_val)
626 goto out;
627
628 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 629 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 630 &data);
9d5c8243 631 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 632 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 633 data);
9d5c8243
AK		 634 if (ret_val)
635 goto out;
636 } else {
637 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 638 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 639 data);
9d5c8243
AK		 640 /*
641 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
642 * during Dx states where the power conservation is most
643 * important. During driver activity we should enable
644 * SmartSpeed, so performance is maintained.
645 */
646 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 647 ret_val = phy->ops.read_reg(hw,
652fff32 648 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 649 if (ret_val)
650 goto out;
651
652 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 653 ret_val = phy->ops.write_reg(hw,
652fff32 654 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 655 if (ret_val)
656 goto out;
657 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 658 ret_val = phy->ops.read_reg(hw,
652fff32 659 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 660 if (ret_val)
661 goto out;
662
663 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 664 ret_val = phy->ops.write_reg(hw,
652fff32 665 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 666 if (ret_val)
667 goto out;
668 }
669 }
670
671out:
672 return ret_val;
673}
674
675/**
733596be 676 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 677 * @hw: pointer to the HW structure
678 *
652fff32 679 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 680 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
681 * Return successful if access grant bit set, else clear the request for
682 * EEPROM access and return -E1000_ERR_NVM (-1).
683 **/
684static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
685{
686 s32 ret_val;
687
688 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
689 if (ret_val)
690 goto out;
691
692 ret_val = igb_acquire_nvm(hw);
693
694 if (ret_val)
695 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
696
697out:
698 return ret_val;
699}
700
701/**
733596be 702 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 703 * @hw: pointer to the HW structure
704 *
705 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
706 * then release the semaphores acquired.
707 **/
708static void igb_release_nvm_82575(struct e1000_hw *hw)
709{
710 igb_release_nvm(hw);
711 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
712}
713
714/**
733596be 715 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 716 * @hw: pointer to the HW structure
717 * @mask: specifies which semaphore to acquire
718 *
719 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
720 * will also specify which port we're acquiring the lock for.
721 **/
722static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
723{
724 u32 swfw_sync;
725 u32 swmask = mask;
726 u32 fwmask = mask << 16;
727 s32 ret_val = 0;
728 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
729
730 while (i < timeout) {
731 if (igb_get_hw_semaphore(hw)) {
732 ret_val = -E1000_ERR_SWFW_SYNC;
733 goto out;
734 }
735
736 swfw_sync = rd32(E1000_SW_FW_SYNC);
737 if (!(swfw_sync & (fwmask | swmask)))
738 break;
739
740 /*
741 * Firmware currently using resource (fwmask)
742 * or other software thread using resource (swmask)
743 */
744 igb_put_hw_semaphore(hw);
745 mdelay(5);
746 i++;
747 }
748
749 if (i == timeout) {
652fff32 750 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 751 ret_val = -E1000_ERR_SWFW_SYNC;
752 goto out;
753 }
754
755 swfw_sync |= swmask;
756 wr32(E1000_SW_FW_SYNC, swfw_sync);
757
758 igb_put_hw_semaphore(hw);
759
760out:
761 return ret_val;
762}
763
764/**
733596be 765 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 766 * @hw: pointer to the HW structure
767 * @mask: specifies which semaphore to acquire
768 *
769 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
770 * will also specify which port we're releasing the lock for.
771 **/
772static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
773{
774 u32 swfw_sync;
775
776 while (igb_get_hw_semaphore(hw) != 0);
777 /* Empty */
778
779 swfw_sync = rd32(E1000_SW_FW_SYNC);
780 swfw_sync &= ~mask;
781 wr32(E1000_SW_FW_SYNC, swfw_sync);
782
783 igb_put_hw_semaphore(hw);
784}
785
786/**
733596be 787 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 788 * @hw: pointer to the HW structure
789 *
790 * Read the management control register for the config done bit for
791 * completion status. NOTE: silicon which is EEPROM-less will fail trying
792 * to read the config done bit, so an error is *ONLY* logged and returns
793 * 0. If we were to return with error, EEPROM-less silicon
794 * would not be able to be reset or change link.
795 **/
796static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
797{
798 s32 timeout = PHY_CFG_TIMEOUT;
799 s32 ret_val = 0;
800 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
801
802 if (hw->bus.func == 1)
803 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 804 else if (hw->bus.func == E1000_FUNC_2)
805 mask = E1000_NVM_CFG_DONE_PORT_2;
806 else if (hw->bus.func == E1000_FUNC_3)
807 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 808
809 while (timeout) {
810 if (rd32(E1000_EEMNGCTL) & mask)
811 break;
812 msleep(1);
813 timeout--;
814 }
815 if (!timeout)
652fff32 816 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 817
818 /* If EEPROM is not marked present, init the PHY manually */
819 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
820 (hw->phy.type == e1000_phy_igp_3))
821 igb_phy_init_script_igp3(hw);
822
823 return ret_val;
824}
825
826/**
733596be 827 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 828 * @hw: pointer to the HW structure
829 *
830 * If sgmii is enabled, then use the pcs register to determine link, otherwise
831 * use the generic interface for determining link.
832 **/
833static s32 igb_check_for_link_82575(struct e1000_hw *hw)
834{
835 s32 ret_val;
836 u16 speed, duplex;
837
70d92f86 838 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 839 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 840 &duplex);
5d0932a5
AD		 841 /*
842 * Use this flag to determine if link needs to be checked or
843 * not. If we have link clear the flag so that we do not
844 * continue to check for link.
845 */
846 hw->mac.get_link_status = !hw->mac.serdes_has_link;
847 } else {
9d5c8243 848 ret_val = igb_check_for_copper_link(hw);
5d0932a5 849 }
9d5c8243
AK		 850
851 return ret_val;
852}
70d92f86 853
88a268c1
NN		 854/**
855 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
856 * @hw: pointer to the HW structure
857 **/
858void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
859{
860 u32 reg;
861
862
863 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
864 !igb_sgmii_active_82575(hw))
865 return;
866
867 /* Enable PCS to turn on link */
868 reg = rd32(E1000_PCS_CFG0);
869 reg |= E1000_PCS_CFG_PCS_EN;
870 wr32(E1000_PCS_CFG0, reg);
871
872 /* Power up the laser */
873 reg = rd32(E1000_CTRL_EXT);
874 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
875 wr32(E1000_CTRL_EXT, reg);
876
877 /* flush the write to verify completion */
878 wrfl();
879 msleep(1);
880}
881
9d5c8243 882/**
733596be 883 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 884 * @hw: pointer to the HW structure
885 * @speed: stores the current speed
886 * @duplex: stores the current duplex
887 *
652fff32 888 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 889 * duplex, then store the values in the pointers provided.
890 **/
891static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
892 u16 *duplex)
893{
894 struct e1000_mac_info *mac = &hw->mac;
895 u32 pcs;
896
897 /* Set up defaults for the return values of this function */
898 mac->serdes_has_link = false;
899 *speed = 0;
900 *duplex = 0;
901
902 /*
903 * Read the PCS Status register for link state. For non-copper mode,
904 * the status register is not accurate. The PCS status register is
905 * used instead.
906 */
907 pcs = rd32(E1000_PCS_LSTAT);
908
909 /*
910 * The link up bit determines when link is up on autoneg. The sync ok
911 * gets set once both sides sync up and agree upon link. Stable link
912 * can be determined by checking for both link up and link sync ok
913 */
914 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
915 mac->serdes_has_link = true;
916
917 /* Detect and store PCS speed */
918 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
919 *speed = SPEED_1000;
920 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
921 *speed = SPEED_100;
922 } else {
923 *speed = SPEED_10;
924 }
925
926 /* Detect and store PCS duplex */
927 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
928 *duplex = FULL_DUPLEX;
929 } else {
930 *duplex = HALF_DUPLEX;
931 }
932 }
933
934 return 0;
935}
936
2d064c06 937/**
2fb02a26 938 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 939 * @hw: pointer to the HW structure
9d5c8243 940 *
2d064c06
AD		 941 * In the case of fiber serdes, shut down optics and PCS on driver unload
942 * when management pass thru is not enabled.
9d5c8243 943 **/
2fb02a26 944void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 945{
2d064c06
AD		 946 u32 reg;
947
53c992fa 948 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 949 igb_sgmii_active_82575(hw))
2d064c06
AD		 950 return;
951
53c992fa 952 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 953 /* Disable PCS to turn off link */
954 reg = rd32(E1000_PCS_CFG0);
955 reg &= ~E1000_PCS_CFG_PCS_EN;
956 wr32(E1000_PCS_CFG0, reg);
957
958 /* shutdown the laser */
959 reg = rd32(E1000_CTRL_EXT);
2fb02a26 960 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 961 wr32(E1000_CTRL_EXT, reg);
962
963 /* flush the write to verify completion */
964 wrfl();
965 msleep(1);
966 }
9d5c8243
AK		 967}
968
969/**
733596be 970 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 971 * @hw: pointer to the HW structure
972 *
973 * This resets the hardware into a known state. This is a
974 * function pointer entry point called by the api module.
975 **/
976static s32 igb_reset_hw_82575(struct e1000_hw *hw)
977{
978 u32 ctrl, icr;
979 s32 ret_val;
980
981 /*
982 * Prevent the PCI-E bus from sticking if there is no TLP connection
983 * on the last TLP read/write transaction when MAC is reset.
984 */
985 ret_val = igb_disable_pcie_master(hw);
986 if (ret_val)
652fff32 987 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 988
009bc06e
AD		 989 /* set the completion timeout for interface */
990 ret_val = igb_set_pcie_completion_timeout(hw);
991 if (ret_val) {
992 hw_dbg("PCI-E Set completion timeout has failed.\n");
993 }
994
652fff32 995 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 996 wr32(E1000_IMC, 0xffffffff);
997
998 wr32(E1000_RCTL, 0);
999 wr32(E1000_TCTL, E1000_TCTL_PSP);
1000 wrfl();
1001
1002 msleep(10);
1003
1004 ctrl = rd32(E1000_CTRL);
1005
652fff32 1006 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 1007 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1008
1009 ret_val = igb_get_auto_rd_done(hw);
1010 if (ret_val) {
1011 /*
1012 * When auto config read does not complete, do not
1013 * return with an error. This can happen in situations
1014 * where there is no eeprom and prevents getting link.
1015 */
652fff32 1016 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 1017 }
1018
1019 /* If EEPROM is not present, run manual init scripts */
1020 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1021 igb_reset_init_script_82575(hw);
1022
1023 /* Clear any pending interrupt events. */
1024 wr32(E1000_IMC, 0xffffffff);
1025 icr = rd32(E1000_ICR);
1026
5ac16659
AD		 1027 /* Install any alternate MAC address into RAR0 */
1028 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 1029
1030 return ret_val;
1031}
1032
1033/**
733596be 1034 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 1035 * @hw: pointer to the HW structure
1036 *
1037 * This inits the hardware readying it for operation.
1038 **/
1039static s32 igb_init_hw_82575(struct e1000_hw *hw)
1040{
1041 struct e1000_mac_info *mac = &hw->mac;
1042 s32 ret_val;
1043 u16 i, rar_count = mac->rar_entry_count;
1044
1045 /* Initialize identification LED */
1046 ret_val = igb_id_led_init(hw);
1047 if (ret_val) {
652fff32 1048 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 1049 /* This is not fatal and we should not stop init due to this */
1050 }
1051
1052 /* Disabling VLAN filtering */
652fff32 1053 hw_dbg("Initializing the IEEE VLAN\n");
9d5c8243
AK		 1054 igb_clear_vfta(hw);
1055
1056 /* Setup the receive address */
5ac16659
AD		 1057 igb_init_rx_addrs(hw, rar_count);
1058
9d5c8243 1059 /* Zero out the Multicast HASH table */
652fff32 1060 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1061 for (i = 0; i < mac->mta_reg_count; i++)
1062 array_wr32(E1000_MTA, i, 0);
1063
68d480c4
AD		 1064 /* Zero out the Unicast HASH table */
1065 hw_dbg("Zeroing the UTA\n");
1066 for (i = 0; i < mac->uta_reg_count; i++)
1067 array_wr32(E1000_UTA, i, 0);
1068
9d5c8243
AK		 1069 /* Setup link and flow control */
1070 ret_val = igb_setup_link(hw);
1071
1072 /*
1073 * Clear all of the statistics registers (clear on read). It is
1074 * important that we do this after we have tried to establish link
1075 * because the symbol error count will increment wildly if there
1076 * is no link.
1077 */
1078 igb_clear_hw_cntrs_82575(hw);
1079
1080 return ret_val;
1081}
1082
1083/**
733596be 1084 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1085 * @hw: pointer to the HW structure
1086 *
1087 * Configures the link for auto-neg or forced speed and duplex. Then we check
1088 * for link, once link is established calls to configure collision distance
1089 * and flow control are called.
1090 **/
1091static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1092{
12645a19 1093 u32 ctrl;
9d5c8243 1094 s32 ret_val;
9d5c8243
AK		 1095
1096 ctrl = rd32(E1000_CTRL);
1097 ctrl |= E1000_CTRL_SLU;
1098 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1099 wr32(E1000_CTRL, ctrl);
1100
2fb02a26
AD		 1101 ret_val = igb_setup_serdes_link_82575(hw);
1102 if (ret_val)
1103 goto out;
1104
1105 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1106 /* allow time for SFP cage time to power up phy */
1107 msleep(300);
1108
2fb02a26
AD		 1109 ret_val = hw->phy.ops.reset(hw);
1110 if (ret_val) {
1111 hw_dbg("Error resetting the PHY.\n");
1112 goto out;
1113 }
1114 }
9d5c8243
AK		 1115 switch (hw->phy.type) {
1116 case e1000_phy_m88:
308fb39a
JG		 1117 if (hw->phy.id == I347AT4_E_PHY_ID ||
1118 hw->phy.id == M88E1112_E_PHY_ID)
1119 ret_val = igb_copper_link_setup_m88_gen2(hw);
1120 else
1121 ret_val = igb_copper_link_setup_m88(hw);
9d5c8243
AK		 1122 break;
1123 case e1000_phy_igp_3:
1124 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1125 break;
bb2ac47b
AD		 1126 case e1000_phy_82580:
1127 ret_val = igb_copper_link_setup_82580(hw);
1128 break;
9d5c8243
AK		 1129 default:
1130 ret_val = -E1000_ERR_PHY;
1131 break;
1132 }
1133
1134 if (ret_val)
1135 goto out;
1136
81fadd81 1137 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1138out:
1139 return ret_val;
1140}
1141
1142/**
70d92f86 1143 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1144 * @hw: pointer to the HW structure
1145 *
70d92f86
AD		 1146 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1147 * used on copper connections where the serialized gigabit media independent
1148 * interface (sgmii), or serdes fiber is being used. Configures the link
1149 * for auto-negotiation or forces speed/duplex.
9d5c8243 1150 **/
2fb02a26 1151static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1152{
bb2ac47b
AD		 1153 u32 ctrl_ext, ctrl_reg, reg;
1154 bool pcs_autoneg;
2c670b5b
CW		 1155 s32 ret_val = E1000_SUCCESS;
1156 u16 data;
2fb02a26
AD		 1157
1158 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1159 !igb_sgmii_active_82575(hw))
2c670b5b
CW		 1160 return ret_val;
1161
9d5c8243
AK		 1162
1163 /*
1164 * On the 82575, SerDes loopback mode persists until it is
1165 * explicitly turned off or a power cycle is performed. A read to
1166 * the register does not indicate its status. Therefore, we ensure
1167 * loopback mode is disabled during initialization.
1168 */
1169 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1170
2fb02a26 1171 /* power on the sfp cage if present */
bb2ac47b
AD		 1172 ctrl_ext = rd32(E1000_CTRL_EXT);
1173 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1174 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1175
1176 ctrl_reg = rd32(E1000_CTRL);
1177 ctrl_reg |= E1000_CTRL_SLU;
1178
1179 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1180 /* set both sw defined pins */
1181 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1182
1183 /* Set switch control to serdes energy detect */
1184 reg = rd32(E1000_CONNSW);
1185 reg |= E1000_CONNSW_ENRGSRC;
1186 wr32(E1000_CONNSW, reg);
1187 }
1188
1189 reg = rd32(E1000_PCS_LCTL);
1190
bb2ac47b
AD		 1191 /* default pcs_autoneg to the same setting as mac autoneg */
1192 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1193
bb2ac47b
AD		 1194 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1195 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1196 /* sgmii mode lets the phy handle forcing speed/duplex */
1197 pcs_autoneg = true;
1198 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1199 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1200 break;
1201 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1202 /* disable PCS autoneg and support parallel detect only */
1203 pcs_autoneg = false;
1204 default:
2c670b5b
CW		 1205 if (hw->mac.type == e1000_82575 ||
1206 hw->mac.type == e1000_82576) {
1207 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1208 if (ret_val) {
1209 printk(KERN_DEBUG "NVM Read Error\n\n");
1210 return ret_val;
1211 }
1212
1213 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1214 pcs_autoneg = false;
1215 }
1216
bb2ac47b
AD		 1217 /*
1218 * non-SGMII modes only supports a speed of 1000/Full for the
1219 * link so it is best to just force the MAC and let the pcs
1220 * link either autoneg or be forced to 1000/Full
1221 */
2fb02a26
AD		 1222 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1223 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1224
1225 /* set speed of 1000/Full if speed/duplex is forced */
1226 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1227 break;
921aa749
AD		 1228 }
1229
2fb02a26 1230 wr32(E1000_CTRL, ctrl_reg);
9d5c8243
AK		 1231
1232 /*
1233 * New SerDes mode allows for forcing speed or autonegotiating speed
1234 * at 1gb. Autoneg should be default set by most drivers. This is the
1235 * mode that will be compatible with older link partners and switches.
1236 * However, both are supported by the hardware and some drivers/tools.
1237 */
9d5c8243
AK		 1238 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1239 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1240
2fb02a26
AD		 1241 /*
1242 * We force flow control to prevent the CTRL register values from being
1243 * overwritten by the autonegotiated flow control values
1244 */
1245 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1246
bb2ac47b 1247 if (pcs_autoneg) {
9d5c8243 1248 /* Set PCS register for autoneg */
bb2ac47b 1249 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1250 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
bb2ac47b 1251 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1252 } else {
bb2ac47b 1253 /* Set PCS register for forced link */
d68caec6 1254 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b
AD		 1255
1256 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1257 }
726c09e7 1258
9d5c8243
AK		 1259 wr32(E1000_PCS_LCTL, reg);
1260
2fb02a26
AD		 1261 if (!igb_sgmii_active_82575(hw))
1262 igb_force_mac_fc(hw);
9d5c8243 1263
2c670b5b 1264 return ret_val;
9d5c8243
AK		 1265}
1266
1267/**
733596be 1268 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1269 * @hw: pointer to the HW structure
1270 *
1271 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1272 * which can be enabled for use in the embedded applications. Simply
1273 * return the current state of the sgmii interface.
1274 **/
1275static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1276{
c1889bfe 1277 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1278 return dev_spec->sgmii_active;
9d5c8243
AK		 1279}
1280
1281/**
733596be 1282 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1283 * @hw: pointer to the HW structure
1284 *
1285 * Inits recommended HW defaults after a reset when there is no EEPROM
1286 * detected. This is only for the 82575.
1287 **/
1288static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1289{
1290 if (hw->mac.type == e1000_82575) {
652fff32 1291 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1292 /* SerDes configuration via SERDESCTRL */
1293 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1294 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1295 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1296 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1297
1298 /* CCM configuration via CCMCTL register */
1299 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1300 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1301
1302 /* PCIe lanes configuration */
1303 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1304 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1305 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1306 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1307
1308 /* PCIe PLL Configuration */
1309 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1310 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1311 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1312 }
1313
1314 return 0;
1315}
1316
1317/**
733596be 1318 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1319 * @hw: pointer to the HW structure
1320 **/
1321static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1322{
1323 s32 ret_val = 0;
1324
22896639
AD		 1325 /*
1326 * If there's an alternate MAC address place it in RAR0
1327 * so that it will override the Si installed default perm
1328 * address.
1329 */
1330 ret_val = igb_check_alt_mac_addr(hw);
1331 if (ret_val)
1332 goto out;
1333
1334 ret_val = igb_read_mac_addr(hw);
9d5c8243 1335
22896639 1336out:
9d5c8243
AK		 1337 return ret_val;
1338}
1339
88a268c1
NN		 1340/**
1341 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1342 * @hw: pointer to the HW structure
1343 *
1344 * In the case of a PHY power down to save power, or to turn off link during a
1345 * driver unload, or wake on lan is not enabled, remove the link.
1346 **/
1347void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1348{
1349 /* If the management interface is not enabled, then power down */
1350 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1351 igb_power_down_phy_copper(hw);
88a268c1
NN		 1352}
1353
9d5c8243 1354/**
733596be 1355 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1356 * @hw: pointer to the HW structure
1357 *
1358 * Clears the hardware counters by reading the counter registers.
1359 **/
1360static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1361{
9d5c8243
AK		 1362 igb_clear_hw_cntrs_base(hw);
1363
cc9073bb
AD		 1364 rd32(E1000_PRC64);
1365 rd32(E1000_PRC127);
1366 rd32(E1000_PRC255);
1367 rd32(E1000_PRC511);
1368 rd32(E1000_PRC1023);
1369 rd32(E1000_PRC1522);
1370 rd32(E1000_PTC64);
1371 rd32(E1000_PTC127);
1372 rd32(E1000_PTC255);
1373 rd32(E1000_PTC511);
1374 rd32(E1000_PTC1023);
1375 rd32(E1000_PTC1522);
1376
1377 rd32(E1000_ALGNERRC);
1378 rd32(E1000_RXERRC);
1379 rd32(E1000_TNCRS);
1380 rd32(E1000_CEXTERR);
1381 rd32(E1000_TSCTC);
1382 rd32(E1000_TSCTFC);
1383
1384 rd32(E1000_MGTPRC);
1385 rd32(E1000_MGTPDC);
1386 rd32(E1000_MGTPTC);
1387
1388 rd32(E1000_IAC);
1389 rd32(E1000_ICRXOC);
1390
1391 rd32(E1000_ICRXPTC);
1392 rd32(E1000_ICRXATC);
1393 rd32(E1000_ICTXPTC);
1394 rd32(E1000_ICTXATC);
1395 rd32(E1000_ICTXQEC);
1396 rd32(E1000_ICTXQMTC);
1397 rd32(E1000_ICRXDMTC);
1398
1399 rd32(E1000_CBTMPC);
1400 rd32(E1000_HTDPMC);
1401 rd32(E1000_CBRMPC);
1402 rd32(E1000_RPTHC);
1403 rd32(E1000_HGPTC);
1404 rd32(E1000_HTCBDPC);
1405 rd32(E1000_HGORCL);
1406 rd32(E1000_HGORCH);
1407 rd32(E1000_HGOTCL);
1408 rd32(E1000_HGOTCH);
1409 rd32(E1000_LENERRS);
9d5c8243
AK		 1410
1411 /* This register should not be read in copper configurations */
2fb02a26
AD		 1412 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1413 igb_sgmii_active_82575(hw))
cc9073bb 1414 rd32(E1000_SCVPC);
9d5c8243
AK		 1415}
1416
662d7205
AD		 1417/**
1418 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1419 * @hw: pointer to the HW structure
1420 *
1421 * After rx enable if managability is enabled then there is likely some
1422 * bad data at the start of the fifo and possibly in the DMA fifo. This
1423 * function clears the fifos and flushes any packets that came in as rx was
1424 * being enabled.
1425 **/
1426void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1427{
1428 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1429 int i, ms_wait;
1430
1431 if (hw->mac.type != e1000_82575 ||
1432 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1433 return;
1434
1435 /* Disable all RX queues */
1436 for (i = 0; i < 4; i++) {
1437 rxdctl[i] = rd32(E1000_RXDCTL(i));
1438 wr32(E1000_RXDCTL(i),
1439 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1440 }
1441 /* Poll all queues to verify they have shut down */
1442 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1443 msleep(1);
1444 rx_enabled = 0;
1445 for (i = 0; i < 4; i++)
1446 rx_enabled |= rd32(E1000_RXDCTL(i));
1447 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1448 break;
1449 }
1450
1451 if (ms_wait == 10)
1452 hw_dbg("Queue disable timed out after 10ms\n");
1453
1454 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1455 * incoming packets are rejected. Set enable and wait 2ms so that
1456 * any packet that was coming in as RCTL.EN was set is flushed
1457 */
1458 rfctl = rd32(E1000_RFCTL);
1459 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1460
1461 rlpml = rd32(E1000_RLPML);
1462 wr32(E1000_RLPML, 0);
1463
1464 rctl = rd32(E1000_RCTL);
1465 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1466 temp_rctl |= E1000_RCTL_LPE;
1467
1468 wr32(E1000_RCTL, temp_rctl);
1469 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1470 wrfl();
1471 msleep(2);
1472
1473 /* Enable RX queues that were previously enabled and restore our
1474 * previous state
1475 */
1476 for (i = 0; i < 4; i++)
1477 wr32(E1000_RXDCTL(i), rxdctl[i]);
1478 wr32(E1000_RCTL, rctl);
1479 wrfl();
1480
1481 wr32(E1000_RLPML, rlpml);
1482 wr32(E1000_RFCTL, rfctl);
1483
1484 /* Flush receive errors generated by workaround */
1485 rd32(E1000_ROC);
1486 rd32(E1000_RNBC);
1487 rd32(E1000_MPC);
1488}
1489
009bc06e
AD		 1490/**
1491 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1492 * @hw: pointer to the HW structure
1493 *
1494 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1495 * however the hardware default for these parts is 500us to 1ms which is less
1496 * than the 10ms recommended by the pci-e spec. To address this we need to
1497 * increase the value to either 10ms to 200ms for capability version 1 config,
1498 * or 16ms to 55ms for version 2.
1499 **/
1500static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1501{
1502 u32 gcr = rd32(E1000_GCR);
1503 s32 ret_val = 0;
1504 u16 pcie_devctl2;
1505
1506 /* only take action if timeout value is defaulted to 0 */
1507 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1508 goto out;
1509
1510 /*
1511 * if capababilities version is type 1 we can write the
1512 * timeout of 10ms to 200ms through the GCR register
1513 */
1514 if (!(gcr & E1000_GCR_CAP_VER2)) {
1515 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1516 goto out;
1517 }
1518
1519 /*
1520 * for version 2 capabilities we need to write the config space
1521 * directly in order to set the completion timeout value for
1522 * 16ms to 55ms
1523 */
1524 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1525 &pcie_devctl2);
1526 if (ret_val)
1527 goto out;
1528
1529 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1530
1531 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1532 &pcie_devctl2);
1533out:
1534 /* disable completion timeout resend */
1535 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1536
1537 wr32(E1000_GCR, gcr);
1538 return ret_val;
1539}
1540
13800469
GR		 1541/**
1542 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1543 * @hw: pointer to the hardware struct
1544 * @enable: state to enter, either enabled or disabled
1545 * @pf: Physical Function pool - do not set anti-spoofing for the PF
1546 *
1547 * enables/disables L2 switch anti-spoofing functionality.
1548 **/
1549void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1550{
1551 u32 dtxswc;
1552
1553 switch (hw->mac.type) {
1554 case e1000_82576:
1555 case e1000_i350:
1556 dtxswc = rd32(E1000_DTXSWC);
1557 if (enable) {
1558 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1559 E1000_DTXSWC_VLAN_SPOOF_MASK);
1560 /* The PF can spoof - it has to in order to
1561 * support emulation mode NICs */
1562 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1563 } else {
1564 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1565 E1000_DTXSWC_VLAN_SPOOF_MASK);
1566 }
1567 wr32(E1000_DTXSWC, dtxswc);
1568 break;
1569 default:
1570 break;
1571 }
1572}
1573
4ae196df
AD		 1574/**
1575 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1576 * @hw: pointer to the hardware struct
1577 * @enable: state to enter, either enabled or disabled
1578 *
1579 * enables/disables L2 switch loopback functionality.
1580 **/
1581void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1582{
ca2e3e7e
AA		 1583 u32 dtxswc;
1584
1585 switch (hw->mac.type) {
1586 case e1000_82576:
1587 dtxswc = rd32(E1000_DTXSWC);
1588 if (enable)
1589 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1590 else
1591 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1592 wr32(E1000_DTXSWC, dtxswc);
1593 break;
1594 case e1000_i350:
1595 dtxswc = rd32(E1000_TXSWC);
1596 if (enable)
1597 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1598 else
1599 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1600 wr32(E1000_TXSWC, dtxswc);
1601 break;
1602 default:
1603 /* Currently no other hardware supports loopback */
1604 break;
1605 }
4ae196df 1606
4ae196df 1607
4ae196df
AD		 1608}
1609
1610/**
1611 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1612 * @hw: pointer to the hardware struct
1613 * @enable: state to enter, either enabled or disabled
1614 *
1615 * enables/disables replication of packets across multiple pools.
1616 **/
1617void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1618{
1619 u32 vt_ctl = rd32(E1000_VT_CTL);
1620
1621 if (enable)
1622 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1623 else
1624 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1625
1626 wr32(E1000_VT_CTL, vt_ctl);
1627}
1628
bb2ac47b
AD		 1629/**
1630 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1631 * @hw: pointer to the HW structure
1632 * @offset: register offset to be read
1633 * @data: pointer to the read data
1634 *
1635 * Reads the MDI control register in the PHY at offset and stores the
1636 * information read to data.
1637 **/
1638static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1639{
bb2ac47b
AD		 1640 s32 ret_val;
1641
1642
1643 ret_val = hw->phy.ops.acquire(hw);
1644 if (ret_val)
1645 goto out;
1646
bb2ac47b
AD		 1647 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
1648
1649 hw->phy.ops.release(hw);
1650
1651out:
1652 return ret_val;
1653}
1654
1655/**
1656 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1657 * @hw: pointer to the HW structure
1658 * @offset: register offset to write to
1659 * @data: data to write to register at offset
1660 *
1661 * Writes data to MDI control register in the PHY at offset.
1662 **/
1663static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1664{
bb2ac47b
AD		 1665 s32 ret_val;
1666
1667
1668 ret_val = hw->phy.ops.acquire(hw);
1669 if (ret_val)
1670 goto out;
1671
bb2ac47b
AD		 1672 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
1673
1674 hw->phy.ops.release(hw);
1675
1676out:
1677 return ret_val;
1678}
1679
08451e25
NN		 1680/**
1681 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
1682 * @hw: pointer to the HW structure
1683 *
1684 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
1685 * the values found in the EEPROM. This addresses an issue in which these
1686 * bits are not restored from EEPROM after reset.
1687 **/
1688static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
1689{
1690 s32 ret_val = 0;
1691 u32 mdicnfg;
1b5dda33 1692 u16 nvm_data = 0;
08451e25
NN		 1693
1694 if (hw->mac.type != e1000_82580)
1695 goto out;
1696 if (!igb_sgmii_active_82575(hw))
1697 goto out;
1698
1699 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
1700 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
1701 &nvm_data);
1702 if (ret_val) {
1703 hw_dbg("NVM Read Error\n");
1704 goto out;
1705 }
1706
1707 mdicnfg = rd32(E1000_MDICNFG);
1708 if (nvm_data & NVM_WORD24_EXT_MDIO)
1709 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
1710 if (nvm_data & NVM_WORD24_COM_MDIO)
1711 mdicnfg |= E1000_MDICNFG_COM_MDIO;
1712 wr32(E1000_MDICNFG, mdicnfg);
1713out:
1714 return ret_val;
1715}
1716
bb2ac47b
AD		 1717/**
1718 * igb_reset_hw_82580 - Reset hardware
1719 * @hw: pointer to the HW structure
1720 *
1721 * This resets function or entire device (all ports, etc.)
1722 * to a known state.
1723 **/
1724static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1725{
1726 s32 ret_val = 0;
1727 /* BH SW mailbox bit in SW_FW_SYNC */
1728 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1729 u32 ctrl, icr;
1730 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1731
1732
1733 hw->dev_spec._82575.global_device_reset = false;
1734
1735 /* Get current control state. */
1736 ctrl = rd32(E1000_CTRL);
1737
1738 /*
1739 * Prevent the PCI-E bus from sticking if there is no TLP connection
1740 * on the last TLP read/write transaction when MAC is reset.
1741 */
1742 ret_val = igb_disable_pcie_master(hw);
1743 if (ret_val)
1744 hw_dbg("PCI-E Master disable polling has failed.\n");
1745
1746 hw_dbg("Masking off all interrupts\n");
1747 wr32(E1000_IMC, 0xffffffff);
1748 wr32(E1000_RCTL, 0);
1749 wr32(E1000_TCTL, E1000_TCTL_PSP);
1750 wrfl();
1751
1752 msleep(10);
1753
1754 /* Determine whether or not a global dev reset is requested */
1755 if (global_device_reset &&
1756 igb_acquire_swfw_sync_82575(hw, swmbsw_mask))
1757 global_device_reset = false;
1758
1759 if (global_device_reset &&
1760 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1761 ctrl |= E1000_CTRL_DEV_RST;
1762 else
1763 ctrl |= E1000_CTRL_RST;
1764
1765 wr32(E1000_CTRL, ctrl);
064b4330 1766 wrfl();
bb2ac47b
AD		 1767
1768 /* Add delay to insure DEV_RST has time to complete */
1769 if (global_device_reset)
1770 msleep(5);
1771
1772 ret_val = igb_get_auto_rd_done(hw);
1773 if (ret_val) {
1774 /*
1775 * When auto config read does not complete, do not
1776 * return with an error. This can happen in situations
1777 * where there is no eeprom and prevents getting link.
1778 */
1779 hw_dbg("Auto Read Done did not complete\n");
1780 }
1781
1782 /* If EEPROM is not present, run manual init scripts */
1783 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1784 igb_reset_init_script_82575(hw);
1785
1786 /* clear global device reset status bit */
1787 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
1788
1789 /* Clear any pending interrupt events. */
1790 wr32(E1000_IMC, 0xffffffff);
1791 icr = rd32(E1000_ICR);
1792
08451e25
NN		 1793 ret_val = igb_reset_mdicnfg_82580(hw);
1794 if (ret_val)
1795 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
1796
bb2ac47b
AD		 1797 /* Install any alternate MAC address into RAR0 */
1798 ret_val = igb_check_alt_mac_addr(hw);
1799
1800 /* Release semaphore */
1801 if (global_device_reset)
1802 igb_release_swfw_sync_82575(hw, swmbsw_mask);
1803
1804 return ret_val;
1805}
1806
1807/**
1808 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1809 * @data: data received by reading RXPBS register
1810 *
1811 * The 82580 uses a table based approach for packet buffer allocation sizes.
1812 * This function converts the retrieved value into the correct table value
1813 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1814 * 0x0 36 72 144 1 2 4 8 16
1815 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1816 */
1817u16 igb_rxpbs_adjust_82580(u32 data)
1818{
1819 u16 ret_val = 0;
1820
1821 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1822 ret_val = e1000_82580_rxpbs_table[data];
1823
1824 return ret_val;
1825}
1826
4322e561
CW		 1827/**
1828 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
1829 * checksum
1830 * @hw: pointer to the HW structure
1831 * @offset: offset in words of the checksum protected region
1832 *
1833 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1834 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1835 **/
bed45a6e
ET		 1836static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
1837 u16 offset)
4322e561
CW		 1838{
1839 s32 ret_val = 0;
1840 u16 checksum = 0;
1841 u16 i, nvm_data;
1842
1843 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
1844 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1845 if (ret_val) {
1846 hw_dbg("NVM Read Error\n");
1847 goto out;
1848 }
1849 checksum += nvm_data;
1850 }
1851
1852 if (checksum != (u16) NVM_SUM) {
1853 hw_dbg("NVM Checksum Invalid\n");
1854 ret_val = -E1000_ERR_NVM;
1855 goto out;
1856 }
1857
1858out:
1859 return ret_val;
1860}
1861
1862/**
1863 * igb_update_nvm_checksum_with_offset - Update EEPROM
1864 * checksum
1865 * @hw: pointer to the HW structure
1866 * @offset: offset in words of the checksum protected region
1867 *
1868 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1869 * up to the checksum. Then calculates the EEPROM checksum and writes the
1870 * value to the EEPROM.
1871 **/
bed45a6e 1872static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
4322e561
CW		 1873{
1874 s32 ret_val;
1875 u16 checksum = 0;
1876 u16 i, nvm_data;
1877
1878 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
1879 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1880 if (ret_val) {
1881 hw_dbg("NVM Read Error while updating checksum.\n");
1882 goto out;
1883 }
1884 checksum += nvm_data;
1885 }
1886 checksum = (u16) NVM_SUM - checksum;
1887 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
1888 &checksum);
1889 if (ret_val)
1890 hw_dbg("NVM Write Error while updating checksum.\n");
1891
1892out:
1893 return ret_val;
1894}
1895
1896/**
1897 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
1898 * @hw: pointer to the HW structure
1899 *
1900 * Calculates the EEPROM section checksum by reading/adding each word of
1901 * the EEPROM and then verifies that the sum of the EEPROM is
1902 * equal to 0xBABA.
1903 **/
1904static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
1905{
1906 s32 ret_val = 0;
1907 u16 eeprom_regions_count = 1;
1908 u16 j, nvm_data;
1909 u16 nvm_offset;
1910
1911 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
1912 if (ret_val) {
1913 hw_dbg("NVM Read Error\n");
1914 goto out;
1915 }
1916
1917 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
34a0326e 1918 /* if checksums compatibility bit is set validate checksums
4322e561
CW		 1919 * for all 4 ports. */
1920 eeprom_regions_count = 4;
1921 }
1922
1923 for (j = 0; j < eeprom_regions_count; j++) {
1924 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1925 ret_val = igb_validate_nvm_checksum_with_offset(hw,
1926 nvm_offset);
1927 if (ret_val != 0)
1928 goto out;
1929 }
1930
1931out:
1932 return ret_val;
1933}
1934
1935/**
1936 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
1937 * @hw: pointer to the HW structure
1938 *
1939 * Updates the EEPROM section checksums for all 4 ports by reading/adding
1940 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
1941 * checksum and writes the value to the EEPROM.
1942 **/
1943static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
1944{
1945 s32 ret_val;
1946 u16 j, nvm_data;
1947 u16 nvm_offset;
1948
1949 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
1950 if (ret_val) {
1951 hw_dbg("NVM Read Error while updating checksum"
1952 " compatibility bit.\n");
1953 goto out;
1954 }
1955
1956 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
1957 /* set compatibility bit to validate checksums appropriately */
1958 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
1959 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
1960 &nvm_data);
1961 if (ret_val) {
1962 hw_dbg("NVM Write Error while updating checksum"
1963 " compatibility bit.\n");
1964 goto out;
1965 }
1966 }
1967
1968 for (j = 0; j < 4; j++) {
1969 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1970 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
1971 if (ret_val)
1972 goto out;
1973 }
1974
1975out:
1976 return ret_val;
1977}
1978
1979/**
1980 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
1981 * @hw: pointer to the HW structure
1982 *
1983 * Calculates the EEPROM section checksum by reading/adding each word of
1984 * the EEPROM and then verifies that the sum of the EEPROM is
1985 * equal to 0xBABA.
1986 **/
1987static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
1988{
1989 s32 ret_val = 0;
1990 u16 j;
1991 u16 nvm_offset;
1992
1993 for (j = 0; j < 4; j++) {
1994 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
1995 ret_val = igb_validate_nvm_checksum_with_offset(hw,
1996 nvm_offset);
1997 if (ret_val != 0)
1998 goto out;
1999 }
2000
2001out:
2002 return ret_val;
2003}
2004
2005/**
2006 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2007 * @hw: pointer to the HW structure
2008 *
2009 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2010 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2011 * checksum and writes the value to the EEPROM.
2012 **/
2013static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2014{
2015 s32 ret_val = 0;
2016 u16 j;
2017 u16 nvm_offset;
2018
2019 for (j = 0; j < 4; j++) {
2020 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2021 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2022 if (ret_val != 0)
2023 goto out;
2024 }
2025
2026out:
2027 return ret_val;
2028}
34a0326e 2029
09b068d4
CW		 2030/**
2031 * igb_set_eee_i350 - Enable/disable EEE support
2032 * @hw: pointer to the HW structure
2033 *
2034 * Enable/disable EEE based on setting in dev_spec structure.
2035 *
2036 **/
2037s32 igb_set_eee_i350(struct e1000_hw *hw)
2038{
2039 s32 ret_val = 0;
2040 u32 ipcnfg, eeer, ctrl_ext;
2041
2042 ctrl_ext = rd32(E1000_CTRL_EXT);
2043 if ((hw->mac.type != e1000_i350) ||
2044 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
2045 goto out;
2046 ipcnfg = rd32(E1000_IPCNFG);
2047 eeer = rd32(E1000_EEER);
2048
2049 /* enable or disable per user setting */
2050 if (!(hw->dev_spec._82575.eee_disable)) {
2051 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
2052 E1000_IPCNFG_EEE_100M_AN);
2053 eeer |= (E1000_EEER_TX_LPI_EN |
2054 E1000_EEER_RX_LPI_EN |
2055 E1000_EEER_LPI_FC);
2056
2057 } else {
2058 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2059 E1000_IPCNFG_EEE_100M_AN);
2060 eeer &= ~(E1000_EEER_TX_LPI_EN |
2061 E1000_EEER_RX_LPI_EN |
2062 E1000_EEER_LPI_FC);
2063 }
2064 wr32(E1000_IPCNFG, ipcnfg);
2065 wr32(E1000_EEER, eeer);
2066out:
2067
2068 return ret_val;
2069}
4322e561 2070
9d5c8243 2071static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 2072 .init_hw = igb_init_hw_82575,
2073 .check_for_link = igb_check_for_link_82575,
2d064c06 2074 .rar_set = igb_rar_set,
9d5c8243
AK		 2075 .read_mac_addr = igb_read_mac_addr_82575,
2076 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
2077};
2078
2079static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 2080 .acquire = igb_acquire_phy_82575,
9d5c8243 2081 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 2082 .release = igb_release_phy_82575,
9d5c8243
AK		 2083};
2084
2085static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 2086 .acquire = igb_acquire_nvm_82575,
2087 .read = igb_read_nvm_eerd,
2088 .release = igb_release_nvm_82575,
2089 .write = igb_write_nvm_spi,
9d5c8243
AK		 2090};
2091
2092const struct e1000_info e1000_82575_info = {
2093 .get_invariants = igb_get_invariants_82575,
2094 .mac_ops = &e1000_mac_ops_82575,
2095 .phy_ops = &e1000_phy_ops_82575,
2096 .nvm_ops = &e1000_nvm_ops_82575,
2097};
2098
Linux kernel - Deliverables
This page took 0.595261 seconds and 5 git commands to generate.