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igb: Cleanups for messaging
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
74cfb2e1 4 Copyright(c) 2007-2014 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
74cfb2e1 16 this program; if not, see <http://www.gnu.org/licenses/>.
9d5c8243
AK		 17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
27/* e1000_82575
28 * e1000_82576
29 */
30
82bbcdeb
JP		 31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
9d5c8243 33#include <linux/types.h>
2d064c06 34#include <linux/if_ether.h>
441fc6fd 35#include <linux/i2c.h>
9d5c8243
AK		 36
37#include "e1000_mac.h"
38#include "e1000_82575.h"
f96a8a0b 39#include "e1000_i210.h"
9d5c8243
AK		 40
41static s32 igb_get_invariants_82575(struct e1000_hw *);
42static s32 igb_acquire_phy_82575(struct e1000_hw *);
43static void igb_release_phy_82575(struct e1000_hw *);
44static s32 igb_acquire_nvm_82575(struct e1000_hw *);
45static void igb_release_nvm_82575(struct e1000_hw *);
46static s32 igb_check_for_link_82575(struct e1000_hw *);
47static s32 igb_get_cfg_done_82575(struct e1000_hw *);
48static s32 igb_init_hw_82575(struct e1000_hw *);
49static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
50static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
bb2ac47b
AD		 51static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
52static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
9d5c8243 53static s32 igb_reset_hw_82575(struct e1000_hw *);
bb2ac47b 54static s32 igb_reset_hw_82580(struct e1000_hw *);
9d5c8243 55static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
da02cde1
CW		 56static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
57static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
9d5c8243 58static s32 igb_setup_copper_link_82575(struct e1000_hw *);
2fb02a26 59static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
9d5c8243
AK		 60static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
61static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
62static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
9d5c8243
AK		 63static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
64 u16 *);
65static s32 igb_get_phy_id_82575(struct e1000_hw *);
66static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
67static bool igb_sgmii_active_82575(struct e1000_hw *);
68static s32 igb_reset_init_script_82575(struct e1000_hw *);
69static s32 igb_read_mac_addr_82575(struct e1000_hw *);
009bc06e 70static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
99870a73 71static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
4322e561
CW		 72static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
73static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
4322e561
CW		 74static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
75static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
bb2ac47b
AD		 76static const u16 e1000_82580_rxpbs_table[] =
77 { 36, 72, 144, 1, 2, 4, 8, 16,
78 35, 70, 140 };
bb2ac47b 79
4085f746
NN		 80/**
81 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
82 * @hw: pointer to the HW structure
83 *
84 * Called to determine if the I2C pins are being used for I2C or as an
85 * external MDIO interface since the two options are mutually exclusive.
86 **/
87static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
88{
89 u32 reg = 0;
90 bool ext_mdio = false;
91
92 switch (hw->mac.type) {
93 case e1000_82575:
94 case e1000_82576:
95 reg = rd32(E1000_MDIC);
96 ext_mdio = !!(reg & E1000_MDIC_DEST);
97 break;
98 case e1000_82580:
99 case e1000_i350:
ceb5f13b 100 case e1000_i354:
f96a8a0b
CW		 101 case e1000_i210:
102 case e1000_i211:
4085f746
NN		 103 reg = rd32(E1000_MDICNFG);
104 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
105 break;
106 default:
107 break;
108 }
109 return ext_mdio;
110}
111
2bdfc4e2
CW		 112/**
113 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
114 * @hw: pointer to the HW structure
115 *
116 * Poll the M88E1112 interfaces to see which interface achieved link.
117 */
118static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
119{
120 struct e1000_phy_info *phy = &hw->phy;
121 s32 ret_val;
122 u16 data;
123 u8 port = 0;
124
125 /* Check the copper medium. */
126 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
127 if (ret_val)
128 return ret_val;
129
130 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
131 if (ret_val)
132 return ret_val;
133
134 if (data & E1000_M88E1112_STATUS_LINK)
135 port = E1000_MEDIA_PORT_COPPER;
136
137 /* Check the other medium. */
138 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
139 if (ret_val)
140 return ret_val;
141
142 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
143 if (ret_val)
144 return ret_val;
145
146 /* reset page to 0 */
147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
148 if (ret_val)
149 return ret_val;
150
151 if (data & E1000_M88E1112_STATUS_LINK)
152 port = E1000_MEDIA_PORT_OTHER;
153
154 /* Determine if a swap needs to happen. */
155 if (port && (hw->dev_spec._82575.media_port != port)) {
156 hw->dev_spec._82575.media_port = port;
157 hw->dev_spec._82575.media_changed = true;
158 } else {
159 ret_val = igb_check_for_link_82575(hw);
160 }
161
162 return E1000_SUCCESS;
163}
164
73bfcd9a
AA		 165/**
166 * igb_init_phy_params_82575 - Init PHY func ptrs.
167 * @hw: pointer to the HW structure
168 **/
169static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
170{
171 struct e1000_phy_info *phy = &hw->phy;
172 s32 ret_val = 0;
173 u32 ctrl_ext;
174
175 if (hw->phy.media_type != e1000_media_type_copper) {
176 phy->type = e1000_phy_none;
177 goto out;
178 }
179
180 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
181 phy->reset_delay_us = 100;
182
183 ctrl_ext = rd32(E1000_CTRL_EXT);
184
185 if (igb_sgmii_active_82575(hw)) {
186 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
187 ctrl_ext |= E1000_CTRL_I2C_ENA;
188 } else {
189 phy->ops.reset = igb_phy_hw_reset;
190 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
191 }
192
193 wr32(E1000_CTRL_EXT, ctrl_ext);
194 igb_reset_mdicnfg_82580(hw);
195
196 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
197 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
198 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
199 } else {
200 switch (hw->mac.type) {
201 case e1000_82580:
202 case e1000_i350:
ceb5f13b 203 case e1000_i354:
73bfcd9a
AA		 204 phy->ops.read_reg = igb_read_phy_reg_82580;
205 phy->ops.write_reg = igb_write_phy_reg_82580;
206 break;
207 case e1000_i210:
208 case e1000_i211:
209 phy->ops.read_reg = igb_read_phy_reg_gs40g;
210 phy->ops.write_reg = igb_write_phy_reg_gs40g;
211 break;
212 default:
213 phy->ops.read_reg = igb_read_phy_reg_igp;
214 phy->ops.write_reg = igb_write_phy_reg_igp;
215 }
216 }
217
218 /* set lan id */
219 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
220 E1000_STATUS_FUNC_SHIFT;
221
222 /* Set phy->phy_addr and phy->id. */
223 ret_val = igb_get_phy_id_82575(hw);
224 if (ret_val)
225 return ret_val;
226
227 /* Verify phy id and set remaining function pointers */
228 switch (phy->id) {
99af4729 229 case M88E1543_E_PHY_ID:
73bfcd9a
AA		 230 case I347AT4_E_PHY_ID:
231 case M88E1112_E_PHY_ID:
232 case M88E1111_I_PHY_ID:
233 phy->type = e1000_phy_m88;
ceb5f13b 234 phy->ops.check_polarity = igb_check_polarity_m88;
73bfcd9a 235 phy->ops.get_phy_info = igb_get_phy_info_m88;
ceb5f13b 236 if (phy->id != M88E1111_I_PHY_ID)
73bfcd9a
AA		 237 phy->ops.get_cable_length =
238 igb_get_cable_length_m88_gen2;
239 else
240 phy->ops.get_cable_length = igb_get_cable_length_m88;
241 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
2bdfc4e2
CW		 242 /* Check if this PHY is confgured for media swap. */
243 if (phy->id == M88E1112_E_PHY_ID) {
244 u16 data;
245
246 ret_val = phy->ops.write_reg(hw,
247 E1000_M88E1112_PAGE_ADDR,
248 2);
249 if (ret_val)
250 goto out;
251
252 ret_val = phy->ops.read_reg(hw,
253 E1000_M88E1112_MAC_CTRL_1,
254 &data);
255 if (ret_val)
256 goto out;
257
258 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
259 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
260 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
261 data == E1000_M88E1112_AUTO_COPPER_BASEX)
262 hw->mac.ops.check_for_link =
263 igb_check_for_link_media_swap;
264 }
73bfcd9a
AA		 265 break;
266 case IGP03E1000_E_PHY_ID:
267 phy->type = e1000_phy_igp_3;
268 phy->ops.get_phy_info = igb_get_phy_info_igp;
269 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
270 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
271 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
272 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
273 break;
274 case I82580_I_PHY_ID:
275 case I350_I_PHY_ID:
276 phy->type = e1000_phy_82580;
277 phy->ops.force_speed_duplex =
278 igb_phy_force_speed_duplex_82580;
279 phy->ops.get_cable_length = igb_get_cable_length_82580;
280 phy->ops.get_phy_info = igb_get_phy_info_82580;
281 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
282 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
283 break;
284 case I210_I_PHY_ID:
285 phy->type = e1000_phy_i210;
286 phy->ops.check_polarity = igb_check_polarity_m88;
287 phy->ops.get_phy_info = igb_get_phy_info_m88;
288 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
289 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
290 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
291 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
292 break;
293 default:
294 ret_val = -E1000_ERR_PHY;
295 goto out;
296 }
297
298out:
299 return ret_val;
300}
301
56d8c27f
AA		 302/**
303 * igb_init_nvm_params_82575 - Init NVM func ptrs.
304 * @hw: pointer to the HW structure
305 **/
c8268921 306static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
56d8c27f
AA		 307{
308 struct e1000_nvm_info *nvm = &hw->nvm;
309 u32 eecd = rd32(E1000_EECD);
310 u16 size;
311
312 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
313 E1000_EECD_SIZE_EX_SHIFT);
5a823d8c 314
56d8c27f
AA		 315 /* Added to a constant, "size" becomes the left-shift value
316 * for setting word_size.
317 */
318 size += NVM_WORD_SIZE_BASE_SHIFT;
319
320 /* Just in case size is out of range, cap it to the largest
321 * EEPROM size supported
322 */
323 if (size > 15)
324 size = 15;
325
326 nvm->word_size = 1 << size;
5a823d8c
CW		 327 nvm->opcode_bits = 8;
328 nvm->delay_usec = 1;
56d8c27f 329
5a823d8c
CW		 330 switch (nvm->override) {
331 case e1000_nvm_override_spi_large:
332 nvm->page_size = 32;
333 nvm->address_bits = 16;
334 break;
335 case e1000_nvm_override_spi_small:
336 nvm->page_size = 8;
337 nvm->address_bits = 8;
338 break;
339 default:
340 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
341 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
342 16 : 8;
343 break;
56d8c27f 344 }
5a823d8c
CW		 345 if (nvm->word_size == (1 << 15))
346 nvm->page_size = 128;
347
348 nvm->type = e1000_nvm_eeprom_spi;
56d8c27f
AA		 349
350 /* NVM Function Pointers */
5a823d8c
CW		 351 nvm->ops.acquire = igb_acquire_nvm_82575;
352 nvm->ops.release = igb_release_nvm_82575;
353 nvm->ops.write = igb_write_nvm_spi;
354 nvm->ops.validate = igb_validate_nvm_checksum;
355 nvm->ops.update = igb_update_nvm_checksum;
356 if (nvm->word_size < (1 << 15))
357 nvm->ops.read = igb_read_nvm_eerd;
358 else
359 nvm->ops.read = igb_read_nvm_spi;
360
361 /* override generic family function pointers for specific descendants */
56d8c27f
AA		 362 switch (hw->mac.type) {
363 case e1000_82580:
364 nvm->ops.validate = igb_validate_nvm_checksum_82580;
365 nvm->ops.update = igb_update_nvm_checksum_82580;
56d8c27f 366 break;
ceb5f13b 367 case e1000_i354:
56d8c27f
AA		 368 case e1000_i350:
369 nvm->ops.validate = igb_validate_nvm_checksum_i350;
370 nvm->ops.update = igb_update_nvm_checksum_i350;
56d8c27f
AA		 371 break;
372 default:
56d8c27f
AA		 373 break;
374 }
375
376 return 0;
377}
378
a1bf1f44
AA		 379/**
380 * igb_init_mac_params_82575 - Init MAC func ptrs.
381 * @hw: pointer to the HW structure
382 **/
383static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
384{
385 struct e1000_mac_info *mac = &hw->mac;
386 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
387
388 /* Set mta register count */
389 mac->mta_reg_count = 128;
390 /* Set rar entry count */
391 switch (mac->type) {
392 case e1000_82576:
393 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
394 break;
395 case e1000_82580:
396 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
397 break;
398 case e1000_i350:
ceb5f13b 399 case e1000_i354:
a1bf1f44
AA		 400 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
401 break;
402 default:
403 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
404 break;
405 }
406 /* reset */
407 if (mac->type >= e1000_82580)
408 mac->ops.reset_hw = igb_reset_hw_82580;
409 else
410 mac->ops.reset_hw = igb_reset_hw_82575;
411
412 if (mac->type >= e1000_i210) {
413 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
414 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
415
416 } else {
417 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
418 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
419 }
420
421 /* Set if part includes ASF firmware */
422 mac->asf_firmware_present = true;
423 /* Set if manageability features are enabled. */
424 mac->arc_subsystem_valid =
425 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
426 ? true : false;
427 /* enable EEE on i350 parts and later parts */
428 if (mac->type >= e1000_i350)
429 dev_spec->eee_disable = false;
430 else
431 dev_spec->eee_disable = true;
d44e7a9a
MV		 432 /* Allow a single clear of the SW semaphore on I210 and newer */
433 if (mac->type >= e1000_i210)
434 dev_spec->clear_semaphore_once = true;
a1bf1f44
AA		 435 /* physical interface link setup */
436 mac->ops.setup_physical_interface =
437 (hw->phy.media_type == e1000_media_type_copper)
438 ? igb_setup_copper_link_82575
439 : igb_setup_serdes_link_82575;
440
56cec249
CW		 441 if (mac->type == e1000_82580) {
442 switch (hw->device_id) {
443 /* feature not supported on these id's */
444 case E1000_DEV_ID_DH89XXCC_SGMII:
445 case E1000_DEV_ID_DH89XXCC_SERDES:
446 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
447 case E1000_DEV_ID_DH89XXCC_SFP:
448 break;
449 default:
450 hw->dev_spec._82575.mas_capable = true;
451 break;
452 }
453 }
a1bf1f44
AA		 454 return 0;
455}
456
641ac5c0
AA		 457/**
458 * igb_set_sfp_media_type_82575 - derives SFP module media type.
459 * @hw: pointer to the HW structure
460 *
461 * The media type is chosen based on SFP module.
462 * compatibility flags retrieved from SFP ID EEPROM.
463 **/
464static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
465{
466 s32 ret_val = E1000_ERR_CONFIG;
467 u32 ctrl_ext = 0;
468 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
469 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
470 u8 tranceiver_type = 0;
471 s32 timeout = 3;
472
473 /* Turn I2C interface ON and power on sfp cage */
474 ctrl_ext = rd32(E1000_CTRL_EXT);
475 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
476 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
477
478 wrfl();
479
480 /* Read SFP module data */
481 while (timeout) {
482 ret_val = igb_read_sfp_data_byte(hw,
483 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
484 &tranceiver_type);
485 if (ret_val == 0)
486 break;
487 msleep(100);
488 timeout--;
489 }
490 if (ret_val != 0)
491 goto out;
492
493 ret_val = igb_read_sfp_data_byte(hw,
494 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
495 (u8 *)eth_flags);
496 if (ret_val != 0)
497 goto out;
498
499 /* Check if there is some SFP module plugged and powered */
500 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
501 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
502 dev_spec->module_plugged = true;
503 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
504 hw->phy.media_type = e1000_media_type_internal_serdes;
505 } else if (eth_flags->e100_base_fx) {
506 dev_spec->sgmii_active = true;
507 hw->phy.media_type = e1000_media_type_internal_serdes;
508 } else if (eth_flags->e1000_base_t) {
509 dev_spec->sgmii_active = true;
510 hw->phy.media_type = e1000_media_type_copper;
511 } else {
512 hw->phy.media_type = e1000_media_type_unknown;
513 hw_dbg("PHY module has not been recognized\n");
514 goto out;
515 }
516 } else {
517 hw->phy.media_type = e1000_media_type_unknown;
518 }
519 ret_val = 0;
520out:
521 /* Restore I2C interface setting */
522 wr32(E1000_CTRL_EXT, ctrl_ext);
523 return ret_val;
524}
525
9d5c8243
AK		 526static s32 igb_get_invariants_82575(struct e1000_hw *hw)
527{
9d5c8243 528 struct e1000_mac_info *mac = &hw->mac;
c1889bfe 529 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
9d5c8243 530 s32 ret_val;
9d5c8243 531 u32 ctrl_ext = 0;
641ac5c0 532 u32 link_mode = 0;
9d5c8243
AK		 533
534 switch (hw->device_id) {
535 case E1000_DEV_ID_82575EB_COPPER:
536 case E1000_DEV_ID_82575EB_FIBER_SERDES:
537 case E1000_DEV_ID_82575GB_QUAD_COPPER:
538 mac->type = e1000_82575;
539 break;
2d064c06 540 case E1000_DEV_ID_82576:
9eb2341d 541 case E1000_DEV_ID_82576_NS:
747d49ba 542 case E1000_DEV_ID_82576_NS_SERDES:
2d064c06
AD		 543 case E1000_DEV_ID_82576_FIBER:
544 case E1000_DEV_ID_82576_SERDES:
c8ea5ea9 545 case E1000_DEV_ID_82576_QUAD_COPPER:
b894fa26 546 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
4703bf73 547 case E1000_DEV_ID_82576_SERDES_QUAD:
2d064c06
AD		 548 mac->type = e1000_82576;
549 break;
bb2ac47b
AD		 550 case E1000_DEV_ID_82580_COPPER:
551 case E1000_DEV_ID_82580_FIBER:
6493d24f 552 case E1000_DEV_ID_82580_QUAD_FIBER:
bb2ac47b
AD		 553 case E1000_DEV_ID_82580_SERDES:
554 case E1000_DEV_ID_82580_SGMII:
555 case E1000_DEV_ID_82580_COPPER_DUAL:
308fb39a
JG		 556 case E1000_DEV_ID_DH89XXCC_SGMII:
557 case E1000_DEV_ID_DH89XXCC_SERDES:
1b5dda33
GJ		 558 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
559 case E1000_DEV_ID_DH89XXCC_SFP:
bb2ac47b
AD		 560 mac->type = e1000_82580;
561 break;
d2ba2ed8
AD		 562 case E1000_DEV_ID_I350_COPPER:
563 case E1000_DEV_ID_I350_FIBER:
564 case E1000_DEV_ID_I350_SERDES:
565 case E1000_DEV_ID_I350_SGMII:
566 mac->type = e1000_i350;
567 break;
f96a8a0b 568 case E1000_DEV_ID_I210_COPPER:
f96a8a0b
CW		 569 case E1000_DEV_ID_I210_FIBER:
570 case E1000_DEV_ID_I210_SERDES:
571 case E1000_DEV_ID_I210_SGMII:
53b87ce3
CW		 572 case E1000_DEV_ID_I210_COPPER_FLASHLESS:
573 case E1000_DEV_ID_I210_SERDES_FLASHLESS:
f96a8a0b
CW		 574 mac->type = e1000_i210;
575 break;
576 case E1000_DEV_ID_I211_COPPER:
577 mac->type = e1000_i211;
578 break;
ceb5f13b
CW		 579 case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
580 case E1000_DEV_ID_I354_SGMII:
581 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
582 mac->type = e1000_i354;
583 break;
9d5c8243
AK		 584 default:
585 return -E1000_ERR_MAC_INIT;
586 break;
587 }
588
9d5c8243 589 /* Set media type */
b980ac18 590 /* The 82575 uses bits 22:23 for link mode. The mode can be changed
9d5c8243
AK		 591 * based on the EEPROM. We cannot rely upon device ID. There
592 * is no distinguishable difference between fiber and internal
593 * SerDes mode on the 82575. There can be an external PHY attached
594 * on the SGMII interface. For this, we'll set sgmii_active to true.
595 */
a6053d76 596 hw->phy.media_type = e1000_media_type_copper;
9d5c8243 597 dev_spec->sgmii_active = false;
641ac5c0 598 dev_spec->module_plugged = false;
9d5c8243
AK		 599
600 ctrl_ext = rd32(E1000_CTRL_EXT);
641ac5c0
AA		 601
602 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
603 switch (link_mode) {
bb2ac47b 604 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
2fb02a26 605 hw->phy.media_type = e1000_media_type_internal_serdes;
641ac5c0
AA		 606 break;
607 case E1000_CTRL_EXT_LINK_MODE_SGMII:
608 /* Get phy control interface type set (MDIO vs. I2C)*/
609 if (igb_sgmii_uses_mdio_82575(hw)) {
610 hw->phy.media_type = e1000_media_type_copper;
611 dev_spec->sgmii_active = true;
612 break;
613 }
614 /* fall through for I2C based SGMII */
615 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
616 /* read media type from SFP EEPROM */
617 ret_val = igb_set_sfp_media_type_82575(hw);
618 if ((ret_val != 0) ||
619 (hw->phy.media_type == e1000_media_type_unknown)) {
620 /* If media type was not identified then return media
621 * type defined by the CTRL_EXT settings.
622 */
623 hw->phy.media_type = e1000_media_type_internal_serdes;
624
625 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
626 hw->phy.media_type = e1000_media_type_copper;
627 dev_spec->sgmii_active = true;
628 }
629
630 break;
631 }
632
633 /* do not change link mode for 100BaseFX */
634 if (dev_spec->eth_flags.e100_base_fx)
635 break;
636
637 /* change current link mode setting */
638 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
639
640 if (hw->phy.media_type == e1000_media_type_copper)
641 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
642 else
643 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
644
645 wr32(E1000_CTRL_EXT, ctrl_ext);
646
2fb02a26
AD		 647 break;
648 default:
2fb02a26 649 break;
9d5c8243 650 }
2fb02a26 651
a6053d76
AA		 652 /* mac initialization and operations */
653 ret_val = igb_init_mac_params_82575(hw);
654 if (ret_val)
655 goto out;
9d5c8243
AK		 656
657 /* NVM initialization */
a6053d76 658 ret_val = igb_init_nvm_params_82575(hw);
5a823d8c
CW		 659 switch (hw->mac.type) {
660 case e1000_i210:
661 case e1000_i211:
662 ret_val = igb_init_nvm_params_i210(hw);
663 break;
664 default:
665 break;
666 }
667
a6053d76
AA		 668 if (ret_val)
669 goto out;
9d5c8243 670
6b78bb1d
CW		 671 /* if part supports SR-IOV then initialize mailbox parameters */
672 switch (mac->type) {
673 case e1000_82576:
674 case e1000_i350:
a0c98605 675 igb_init_mbx_params_pf(hw);
6b78bb1d
CW		 676 break;
677 default:
678 break;
679 }
a0c98605 680
9d5c8243 681 /* setup PHY parameters */
a6053d76 682 ret_val = igb_init_phy_params_82575(hw);
19e588e7 683
a6053d76
AA		 684out:
685 return ret_val;
9d5c8243
AK		 686}
687
688/**
733596be 689 * igb_acquire_phy_82575 - Acquire rights to access PHY
9d5c8243
AK		 690 * @hw: pointer to the HW structure
691 *
692 * Acquire access rights to the correct PHY. This is a
693 * function pointer entry point called by the api module.
694 **/
695static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
696{
008c3422 697 u16 mask = E1000_SWFW_PHY0_SM;
9d5c8243 698
008c3422
AD		 699 if (hw->bus.func == E1000_FUNC_1)
700 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 701 else if (hw->bus.func == E1000_FUNC_2)
702 mask = E1000_SWFW_PHY2_SM;
703 else if (hw->bus.func == E1000_FUNC_3)
704 mask = E1000_SWFW_PHY3_SM;
9d5c8243 705
f96a8a0b 706 return hw->mac.ops.acquire_swfw_sync(hw, mask);
9d5c8243
AK		 707}
708
709/**
733596be 710 * igb_release_phy_82575 - Release rights to access PHY
9d5c8243
AK		 711 * @hw: pointer to the HW structure
712 *
713 * A wrapper to release access rights to the correct PHY. This is a
714 * function pointer entry point called by the api module.
715 **/
716static void igb_release_phy_82575(struct e1000_hw *hw)
717{
008c3422
AD		 718 u16 mask = E1000_SWFW_PHY0_SM;
719
720 if (hw->bus.func == E1000_FUNC_1)
721 mask = E1000_SWFW_PHY1_SM;
ede3ef0d
NN		 722 else if (hw->bus.func == E1000_FUNC_2)
723 mask = E1000_SWFW_PHY2_SM;
724 else if (hw->bus.func == E1000_FUNC_3)
725 mask = E1000_SWFW_PHY3_SM;
9d5c8243 726
f96a8a0b 727 hw->mac.ops.release_swfw_sync(hw, mask);
9d5c8243
AK		 728}
729
730/**
733596be 731 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
9d5c8243
AK		 732 * @hw: pointer to the HW structure
733 * @offset: register offset to be read
734 * @data: pointer to the read data
735 *
736 * Reads the PHY register at offset using the serial gigabit media independent
737 * interface and stores the retrieved information in data.
738 **/
739static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
740 u16 *data)
741{
bf6f7a92 742 s32 ret_val = -E1000_ERR_PARAM;
9d5c8243
AK		 743
744 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 745 hw_dbg("PHY Address %u is out of range\n", offset);
bf6f7a92 746 goto out;
9d5c8243
AK		 747 }
748
bf6f7a92
AD		 749 ret_val = hw->phy.ops.acquire(hw);
750 if (ret_val)
751 goto out;
9d5c8243 752
bf6f7a92 753 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
9d5c8243 754
bf6f7a92
AD		 755 hw->phy.ops.release(hw);
756
757out:
758 return ret_val;
9d5c8243
AK		 759}
760
761/**
733596be 762 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
9d5c8243
AK		 763 * @hw: pointer to the HW structure
764 * @offset: register offset to write to
765 * @data: data to write at register offset
766 *
767 * Writes the data to PHY register at the offset using the serial gigabit
768 * media independent interface.
769 **/
770static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
771 u16 data)
772{
bf6f7a92
AD		 773 s32 ret_val = -E1000_ERR_PARAM;
774
9d5c8243
AK		 775
776 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
652fff32 777 hw_dbg("PHY Address %d is out of range\n", offset);
bf6f7a92 778 goto out;
9d5c8243
AK		 779 }
780
bf6f7a92
AD		 781 ret_val = hw->phy.ops.acquire(hw);
782 if (ret_val)
783 goto out;
9d5c8243 784
bf6f7a92 785 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
9d5c8243 786
bf6f7a92
AD		 787 hw->phy.ops.release(hw);
788
789out:
790 return ret_val;
9d5c8243
AK		 791}
792
793/**
733596be 794 * igb_get_phy_id_82575 - Retrieve PHY addr and id
9d5c8243
AK		 795 * @hw: pointer to the HW structure
796 *
652fff32 797 * Retrieves the PHY address and ID for both PHY's which do and do not use
9d5c8243
AK		 798 * sgmi interface.
799 **/
800static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
801{
802 struct e1000_phy_info *phy = &hw->phy;
803 s32 ret_val = 0;
804 u16 phy_id;
2fb02a26 805 u32 ctrl_ext;
4085f746 806 u32 mdic;
9d5c8243 807
bb1d18d1
CW		 808 /* Extra read required for some PHY's on i354 */
809 if (hw->mac.type == e1000_i354)
810 igb_get_phy_id(hw);
811
b980ac18 812 /* For SGMII PHYs, we try the list of possible addresses until
9d5c8243
AK		 813 * we find one that works. For non-SGMII PHYs
814 * (e.g. integrated copper PHYs), an address of 1 should
815 * work. The result of this function should mean phy->phy_addr
816 * and phy->id are set correctly.
817 */
818 if (!(igb_sgmii_active_82575(hw))) {
819 phy->addr = 1;
820 ret_val = igb_get_phy_id(hw);
821 goto out;
822 }
823
4085f746
NN		 824 if (igb_sgmii_uses_mdio_82575(hw)) {
825 switch (hw->mac.type) {
826 case e1000_82575:
827 case e1000_82576:
828 mdic = rd32(E1000_MDIC);
829 mdic &= E1000_MDIC_PHY_MASK;
830 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
831 break;
832 case e1000_82580:
833 case e1000_i350:
ceb5f13b 834 case e1000_i354:
f96a8a0b
CW		 835 case e1000_i210:
836 case e1000_i211:
4085f746
NN		 837 mdic = rd32(E1000_MDICNFG);
838 mdic &= E1000_MDICNFG_PHY_MASK;
839 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
840 break;
841 default:
842 ret_val = -E1000_ERR_PHY;
843 goto out;
844 break;
845 }
846 ret_val = igb_get_phy_id(hw);
847 goto out;
848 }
849
2fb02a26
AD		 850 /* Power on sgmii phy if it is disabled */
851 ctrl_ext = rd32(E1000_CTRL_EXT);
852 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
853 wrfl();
854 msleep(300);
855
b980ac18 856 /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
9d5c8243
AK		 857 * Therefore, we need to test 1-7
858 */
859 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
860 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
861 if (ret_val == 0) {
652fff32
AK		 862 hw_dbg("Vendor ID 0x%08X read at address %u\n",
863 phy_id, phy->addr);
b980ac18 864 /* At the time of this writing, The M88 part is
9d5c8243
AK		 865 * the only supported SGMII PHY product.
866 */
867 if (phy_id == M88_VENDOR)
868 break;
869 } else {
652fff32 870 hw_dbg("PHY address %u was unreadable\n", phy->addr);
9d5c8243
AK		 871 }
872 }
873
874 /* A valid PHY type couldn't be found. */
875 if (phy->addr == 8) {
876 phy->addr = 0;
877 ret_val = -E1000_ERR_PHY;
878 goto out;
2fb02a26
AD		 879 } else {
880 ret_val = igb_get_phy_id(hw);
9d5c8243
AK		 881 }
882
2fb02a26
AD		 883 /* restore previous sfp cage power state */
884 wr32(E1000_CTRL_EXT, ctrl_ext);
9d5c8243
AK		 885
886out:
887 return ret_val;
888}
889
890/**
733596be 891 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
9d5c8243
AK		 892 * @hw: pointer to the HW structure
893 *
894 * Resets the PHY using the serial gigabit media independent interface.
895 **/
896static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
897{
898 s32 ret_val;
899
b980ac18 900 /* This isn't a true "hard" reset, but is the only reset
9d5c8243
AK		 901 * available to us at this time.
902 */
903
652fff32 904 hw_dbg("Soft resetting SGMII attached PHY...\n");
9d5c8243 905
b980ac18 906 /* SFP documentation requires the following to configure the SPF module
9d5c8243
AK		 907 * to work on SGMII. No further documentation is given.
908 */
a8d2a0c2 909 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
9d5c8243
AK		 910 if (ret_val)
911 goto out;
912
913 ret_val = igb_phy_sw_reset(hw);
914
915out:
916 return ret_val;
917}
918
919/**
733596be 920 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
9d5c8243
AK		 921 * @hw: pointer to the HW structure
922 * @active: true to enable LPLU, false to disable
923 *
924 * Sets the LPLU D0 state according to the active flag. When
925 * activating LPLU this function also disables smart speed
926 * and vice versa. LPLU will not be activated unless the
927 * device autonegotiation advertisement meets standards of
928 * either 10 or 10/100 or 10/100/1000 at all duplexes.
929 * This is a function pointer entry point only called by
930 * PHY setup routines.
931 **/
932static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
933{
934 struct e1000_phy_info *phy = &hw->phy;
935 s32 ret_val;
936 u16 data;
937
a8d2a0c2 938 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
9d5c8243
AK		 939 if (ret_val)
940 goto out;
941
942 if (active) {
943 data |= IGP02E1000_PM_D0_LPLU;
a8d2a0c2 944 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 945 data);
9d5c8243
AK		 946 if (ret_val)
947 goto out;
948
949 /* When LPLU is enabled, we should disable SmartSpeed */
a8d2a0c2 950 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 951 &data);
9d5c8243 952 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 953 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
652fff32 954 data);
9d5c8243
AK		 955 if (ret_val)
956 goto out;
957 } else {
958 data &= ~IGP02E1000_PM_D0_LPLU;
a8d2a0c2 959 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
652fff32 960 data);
b980ac18 961 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
9d5c8243
AK		 962 * during Dx states where the power conservation is most
963 * important. During driver activity we should enable
964 * SmartSpeed, so performance is maintained.
965 */
966 if (phy->smart_speed == e1000_smart_speed_on) {
a8d2a0c2 967 ret_val = phy->ops.read_reg(hw,
652fff32 968 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 969 if (ret_val)
970 goto out;
971
972 data |= IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 973 ret_val = phy->ops.write_reg(hw,
652fff32 974 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 975 if (ret_val)
976 goto out;
977 } else if (phy->smart_speed == e1000_smart_speed_off) {
a8d2a0c2 978 ret_val = phy->ops.read_reg(hw,
652fff32 979 IGP01E1000_PHY_PORT_CONFIG, &data);
9d5c8243
AK		 980 if (ret_val)
981 goto out;
982
983 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
a8d2a0c2 984 ret_val = phy->ops.write_reg(hw,
652fff32 985 IGP01E1000_PHY_PORT_CONFIG, data);
9d5c8243
AK		 986 if (ret_val)
987 goto out;
988 }
989 }
990
991out:
992 return ret_val;
993}
994
da02cde1
CW		 995/**
996 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
997 * @hw: pointer to the HW structure
998 * @active: true to enable LPLU, false to disable
999 *
1000 * Sets the LPLU D0 state according to the active flag. When
1001 * activating LPLU this function also disables smart speed
1002 * and vice versa. LPLU will not be activated unless the
1003 * device autonegotiation advertisement meets standards of
1004 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1005 * This is a function pointer entry point only called by
1006 * PHY setup routines.
1007 **/
1008static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1009{
1010 struct e1000_phy_info *phy = &hw->phy;
1011 s32 ret_val = 0;
1012 u16 data;
1013
1014 data = rd32(E1000_82580_PHY_POWER_MGMT);
1015
1016 if (active) {
1017 data |= E1000_82580_PM_D0_LPLU;
1018
1019 /* When LPLU is enabled, we should disable SmartSpeed */
1020 data &= ~E1000_82580_PM_SPD;
1021 } else {
1022 data &= ~E1000_82580_PM_D0_LPLU;
1023
b980ac18 1024 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
da02cde1
CW		 1025 * during Dx states where the power conservation is most
1026 * important. During driver activity we should enable
1027 * SmartSpeed, so performance is maintained.
1028 */
1029 if (phy->smart_speed == e1000_smart_speed_on)
1030 data |= E1000_82580_PM_SPD;
1031 else if (phy->smart_speed == e1000_smart_speed_off)
1032 data &= ~E1000_82580_PM_SPD; }
1033
1034 wr32(E1000_82580_PHY_POWER_MGMT, data);
1035 return ret_val;
1036}
1037
1038/**
1039 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1040 * @hw: pointer to the HW structure
1041 * @active: boolean used to enable/disable lplu
1042 *
1043 * Success returns 0, Failure returns 1
1044 *
1045 * The low power link up (lplu) state is set to the power management level D3
1046 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1047 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1048 * is used during Dx states where the power conservation is most important.
1049 * During driver activity, SmartSpeed should be enabled so performance is
1050 * maintained.
1051 **/
c8268921 1052static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
da02cde1
CW		 1053{
1054 struct e1000_phy_info *phy = &hw->phy;
1055 s32 ret_val = 0;
1056 u16 data;
1057
1058 data = rd32(E1000_82580_PHY_POWER_MGMT);
1059
1060 if (!active) {
1061 data &= ~E1000_82580_PM_D3_LPLU;
b980ac18 1062 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
da02cde1
CW		 1063 * during Dx states where the power conservation is most
1064 * important. During driver activity we should enable
1065 * SmartSpeed, so performance is maintained.
1066 */
1067 if (phy->smart_speed == e1000_smart_speed_on)
1068 data |= E1000_82580_PM_SPD;
1069 else if (phy->smart_speed == e1000_smart_speed_off)
1070 data &= ~E1000_82580_PM_SPD;
1071 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1072 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1073 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1074 data |= E1000_82580_PM_D3_LPLU;
1075 /* When LPLU is enabled, we should disable SmartSpeed */
1076 data &= ~E1000_82580_PM_SPD;
1077 }
1078
1079 wr32(E1000_82580_PHY_POWER_MGMT, data);
1080 return ret_val;
1081}
1082
9d5c8243 1083/**
733596be 1084 * igb_acquire_nvm_82575 - Request for access to EEPROM
9d5c8243
AK		 1085 * @hw: pointer to the HW structure
1086 *
652fff32 1087 * Acquire the necessary semaphores for exclusive access to the EEPROM.
9d5c8243
AK		 1088 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1089 * Return successful if access grant bit set, else clear the request for
1090 * EEPROM access and return -E1000_ERR_NVM (-1).
1091 **/
1092static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1093{
1094 s32 ret_val;
1095
f96a8a0b 1096 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1097 if (ret_val)
1098 goto out;
1099
1100 ret_val = igb_acquire_nvm(hw);
1101
1102 if (ret_val)
f96a8a0b 1103 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1104
1105out:
1106 return ret_val;
1107}
1108
1109/**
733596be 1110 * igb_release_nvm_82575 - Release exclusive access to EEPROM
9d5c8243
AK		 1111 * @hw: pointer to the HW structure
1112 *
1113 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1114 * then release the semaphores acquired.
1115 **/
1116static void igb_release_nvm_82575(struct e1000_hw *hw)
1117{
1118 igb_release_nvm(hw);
f96a8a0b 1119 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
9d5c8243
AK		 1120}
1121
1122/**
733596be 1123 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
9d5c8243
AK		 1124 * @hw: pointer to the HW structure
1125 * @mask: specifies which semaphore to acquire
1126 *
1127 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1128 * will also specify which port we're acquiring the lock for.
1129 **/
1130static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1131{
1132 u32 swfw_sync;
1133 u32 swmask = mask;
1134 u32 fwmask = mask << 16;
1135 s32 ret_val = 0;
1136 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1137
1138 while (i < timeout) {
1139 if (igb_get_hw_semaphore(hw)) {
1140 ret_val = -E1000_ERR_SWFW_SYNC;
1141 goto out;
1142 }
1143
1144 swfw_sync = rd32(E1000_SW_FW_SYNC);
1145 if (!(swfw_sync & (fwmask | swmask)))
1146 break;
1147
b980ac18 1148 /* Firmware currently using resource (fwmask)
9d5c8243
AK		 1149 * or other software thread using resource (swmask)
1150 */
1151 igb_put_hw_semaphore(hw);
1152 mdelay(5);
1153 i++;
1154 }
1155
1156 if (i == timeout) {
652fff32 1157 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
9d5c8243
AK		 1158 ret_val = -E1000_ERR_SWFW_SYNC;
1159 goto out;
1160 }
1161
1162 swfw_sync |= swmask;
1163 wr32(E1000_SW_FW_SYNC, swfw_sync);
1164
1165 igb_put_hw_semaphore(hw);
1166
1167out:
1168 return ret_val;
1169}
1170
1171/**
733596be 1172 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
9d5c8243
AK		 1173 * @hw: pointer to the HW structure
1174 * @mask: specifies which semaphore to acquire
1175 *
1176 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1177 * will also specify which port we're releasing the lock for.
1178 **/
1179static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1180{
1181 u32 swfw_sync;
1182
1183 while (igb_get_hw_semaphore(hw) != 0);
1184 /* Empty */
1185
1186 swfw_sync = rd32(E1000_SW_FW_SYNC);
1187 swfw_sync &= ~mask;
1188 wr32(E1000_SW_FW_SYNC, swfw_sync);
1189
1190 igb_put_hw_semaphore(hw);
1191}
1192
1193/**
733596be 1194 * igb_get_cfg_done_82575 - Read config done bit
9d5c8243
AK		 1195 * @hw: pointer to the HW structure
1196 *
1197 * Read the management control register for the config done bit for
1198 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1199 * to read the config done bit, so an error is *ONLY* logged and returns
1200 * 0. If we were to return with error, EEPROM-less silicon
1201 * would not be able to be reset or change link.
1202 **/
1203static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1204{
1205 s32 timeout = PHY_CFG_TIMEOUT;
1206 s32 ret_val = 0;
1207 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1208
1209 if (hw->bus.func == 1)
1210 mask = E1000_NVM_CFG_DONE_PORT_1;
bb2ac47b
AD		 1211 else if (hw->bus.func == E1000_FUNC_2)
1212 mask = E1000_NVM_CFG_DONE_PORT_2;
1213 else if (hw->bus.func == E1000_FUNC_3)
1214 mask = E1000_NVM_CFG_DONE_PORT_3;
9d5c8243
AK		 1215
1216 while (timeout) {
1217 if (rd32(E1000_EEMNGCTL) & mask)
1218 break;
1219 msleep(1);
1220 timeout--;
1221 }
1222 if (!timeout)
652fff32 1223 hw_dbg("MNG configuration cycle has not completed.\n");
9d5c8243
AK		 1224
1225 /* If EEPROM is not marked present, init the PHY manually */
1226 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1227 (hw->phy.type == e1000_phy_igp_3))
1228 igb_phy_init_script_igp3(hw);
1229
1230 return ret_val;
1231}
1232
f6878e39
AA		 1233/**
1234 * igb_get_link_up_info_82575 - Get link speed/duplex info
1235 * @hw: pointer to the HW structure
1236 * @speed: stores the current speed
1237 * @duplex: stores the current duplex
1238 *
1239 * This is a wrapper function, if using the serial gigabit media independent
1240 * interface, use PCS to retrieve the link speed and duplex information.
1241 * Otherwise, use the generic function to get the link speed and duplex info.
1242 **/
1243static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1244 u16 *duplex)
1245{
1246 s32 ret_val;
1247
1248 if (hw->phy.media_type != e1000_media_type_copper)
1249 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1250 duplex);
1251 else
1252 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1253 duplex);
1254
1255 return ret_val;
1256}
1257
9d5c8243 1258/**
733596be 1259 * igb_check_for_link_82575 - Check for link
9d5c8243
AK		 1260 * @hw: pointer to the HW structure
1261 *
1262 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1263 * use the generic interface for determining link.
1264 **/
1265static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1266{
1267 s32 ret_val;
1268 u16 speed, duplex;
1269
70d92f86 1270 if (hw->phy.media_type != e1000_media_type_copper) {
9d5c8243 1271 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
2d064c06 1272 &duplex);
b980ac18 1273 /* Use this flag to determine if link needs to be checked or
5d0932a5
AD		 1274 * not. If we have link clear the flag so that we do not
1275 * continue to check for link.
1276 */
1277 hw->mac.get_link_status = !hw->mac.serdes_has_link;
daf56e40
CW		 1278
1279 /* Configure Flow Control now that Auto-Neg has completed.
1280 * First, we need to restore the desired flow control
1281 * settings because we may have had to re-autoneg with a
1282 * different link partner.
1283 */
1284 ret_val = igb_config_fc_after_link_up(hw);
1285 if (ret_val)
1286 hw_dbg("Error configuring flow control\n");
5d0932a5 1287 } else {
9d5c8243 1288 ret_val = igb_check_for_copper_link(hw);
5d0932a5 1289 }
9d5c8243
AK		 1290
1291 return ret_val;
1292}
70d92f86 1293
88a268c1
NN		 1294/**
1295 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1296 * @hw: pointer to the HW structure
1297 **/
1298void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1299{
1300 u32 reg;
1301
1302
1303 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1304 !igb_sgmii_active_82575(hw))
1305 return;
1306
1307 /* Enable PCS to turn on link */
1308 reg = rd32(E1000_PCS_CFG0);
1309 reg |= E1000_PCS_CFG_PCS_EN;
1310 wr32(E1000_PCS_CFG0, reg);
1311
1312 /* Power up the laser */
1313 reg = rd32(E1000_CTRL_EXT);
1314 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1315 wr32(E1000_CTRL_EXT, reg);
1316
1317 /* flush the write to verify completion */
1318 wrfl();
1319 msleep(1);
1320}
1321
9d5c8243 1322/**
733596be 1323 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
9d5c8243
AK		 1324 * @hw: pointer to the HW structure
1325 * @speed: stores the current speed
1326 * @duplex: stores the current duplex
1327 *
652fff32 1328 * Using the physical coding sub-layer (PCS), retrieve the current speed and
9d5c8243
AK		 1329 * duplex, then store the values in the pointers provided.
1330 **/
1331static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1332 u16 *duplex)
1333{
1334 struct e1000_mac_info *mac = &hw->mac;
f1b4d621 1335 u32 pcs, status;
9d5c8243
AK		 1336
1337 /* Set up defaults for the return values of this function */
1338 mac->serdes_has_link = false;
1339 *speed = 0;
1340 *duplex = 0;
1341
b980ac18 1342 /* Read the PCS Status register for link state. For non-copper mode,
9d5c8243
AK		 1343 * the status register is not accurate. The PCS status register is
1344 * used instead.
1345 */
1346 pcs = rd32(E1000_PCS_LSTAT);
1347
b980ac18 1348 /* The link up bit determines when link is up on autoneg. The sync ok
9d5c8243
AK		 1349 * gets set once both sides sync up and agree upon link. Stable link
1350 * can be determined by checking for both link up and link sync ok
1351 */
1352 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1353 mac->serdes_has_link = true;
1354
1355 /* Detect and store PCS speed */
f1b4d621 1356 if (pcs & E1000_PCS_LSTS_SPEED_1000)
9d5c8243 1357 *speed = SPEED_1000;
f1b4d621 1358 else if (pcs & E1000_PCS_LSTS_SPEED_100)
9d5c8243 1359 *speed = SPEED_100;
f1b4d621 1360 else
9d5c8243 1361 *speed = SPEED_10;
9d5c8243
AK		 1362
1363 /* Detect and store PCS duplex */
f1b4d621 1364 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
9d5c8243 1365 *duplex = FULL_DUPLEX;
f1b4d621 1366 else
9d5c8243 1367 *duplex = HALF_DUPLEX;
f1b4d621
AA		 1368
1369 /* Check if it is an I354 2.5Gb backplane connection. */
1370 if (mac->type == e1000_i354) {
1371 status = rd32(E1000_STATUS);
1372 if ((status & E1000_STATUS_2P5_SKU) &&
1373 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1374 *speed = SPEED_2500;
1375 *duplex = FULL_DUPLEX;
1376 hw_dbg("2500 Mbs, ");
1377 hw_dbg("Full Duplex\n");
1378 }
9d5c8243 1379 }
f1b4d621 1380
9d5c8243
AK		 1381 }
1382
1383 return 0;
1384}
1385
2d064c06 1386/**
2fb02a26 1387 * igb_shutdown_serdes_link_82575 - Remove link during power down
9d5c8243 1388 * @hw: pointer to the HW structure
9d5c8243 1389 *
2d064c06
AD		 1390 * In the case of fiber serdes, shut down optics and PCS on driver unload
1391 * when management pass thru is not enabled.
9d5c8243 1392 **/
2fb02a26 1393void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1394{
2d064c06
AD		 1395 u32 reg;
1396
53c992fa 1397 if (hw->phy.media_type != e1000_media_type_internal_serdes &&
2fb02a26 1398 igb_sgmii_active_82575(hw))
2d064c06
AD		 1399 return;
1400
53c992fa 1401 if (!igb_enable_mng_pass_thru(hw)) {
2d064c06
AD		 1402 /* Disable PCS to turn off link */
1403 reg = rd32(E1000_PCS_CFG0);
1404 reg &= ~E1000_PCS_CFG_PCS_EN;
1405 wr32(E1000_PCS_CFG0, reg);
1406
1407 /* shutdown the laser */
1408 reg = rd32(E1000_CTRL_EXT);
2fb02a26 1409 reg |= E1000_CTRL_EXT_SDP3_DATA;
2d064c06
AD		 1410 wr32(E1000_CTRL_EXT, reg);
1411
1412 /* flush the write to verify completion */
1413 wrfl();
1414 msleep(1);
1415 }
9d5c8243
AK		 1416}
1417
1418/**
733596be 1419 * igb_reset_hw_82575 - Reset hardware
9d5c8243
AK		 1420 * @hw: pointer to the HW structure
1421 *
1422 * This resets the hardware into a known state. This is a
1423 * function pointer entry point called by the api module.
1424 **/
1425static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1426{
e5c3370f 1427 u32 ctrl;
9d5c8243
AK		 1428 s32 ret_val;
1429
b980ac18 1430 /* Prevent the PCI-E bus from sticking if there is no TLP connection
9d5c8243
AK		 1431 * on the last TLP read/write transaction when MAC is reset.
1432 */
1433 ret_val = igb_disable_pcie_master(hw);
1434 if (ret_val)
652fff32 1435 hw_dbg("PCI-E Master disable polling has failed.\n");
9d5c8243 1436
009bc06e
AD		 1437 /* set the completion timeout for interface */
1438 ret_val = igb_set_pcie_completion_timeout(hw);
1439 if (ret_val) {
1440 hw_dbg("PCI-E Set completion timeout has failed.\n");
1441 }
1442
652fff32 1443 hw_dbg("Masking off all interrupts\n");
9d5c8243
AK		 1444 wr32(E1000_IMC, 0xffffffff);
1445
1446 wr32(E1000_RCTL, 0);
1447 wr32(E1000_TCTL, E1000_TCTL_PSP);
1448 wrfl();
1449
1450 msleep(10);
1451
1452 ctrl = rd32(E1000_CTRL);
1453
652fff32 1454 hw_dbg("Issuing a global reset to MAC\n");
9d5c8243
AK		 1455 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1456
1457 ret_val = igb_get_auto_rd_done(hw);
1458 if (ret_val) {
b980ac18 1459 /* When auto config read does not complete, do not
9d5c8243
AK		 1460 * return with an error. This can happen in situations
1461 * where there is no eeprom and prevents getting link.
1462 */
652fff32 1463 hw_dbg("Auto Read Done did not complete\n");
9d5c8243
AK		 1464 }
1465
1466 /* If EEPROM is not present, run manual init scripts */
1467 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1468 igb_reset_init_script_82575(hw);
1469
1470 /* Clear any pending interrupt events. */
1471 wr32(E1000_IMC, 0xffffffff);
e5c3370f 1472 rd32(E1000_ICR);
9d5c8243 1473
5ac16659
AD		 1474 /* Install any alternate MAC address into RAR0 */
1475 ret_val = igb_check_alt_mac_addr(hw);
9d5c8243
AK		 1476
1477 return ret_val;
1478}
1479
1480/**
733596be 1481 * igb_init_hw_82575 - Initialize hardware
9d5c8243
AK		 1482 * @hw: pointer to the HW structure
1483 *
1484 * This inits the hardware readying it for operation.
1485 **/
1486static s32 igb_init_hw_82575(struct e1000_hw *hw)
1487{
1488 struct e1000_mac_info *mac = &hw->mac;
1489 s32 ret_val;
1490 u16 i, rar_count = mac->rar_entry_count;
1491
1492 /* Initialize identification LED */
1493 ret_val = igb_id_led_init(hw);
1494 if (ret_val) {
652fff32 1495 hw_dbg("Error initializing identification LED\n");
9d5c8243
AK		 1496 /* This is not fatal and we should not stop init due to this */
1497 }
1498
1499 /* Disabling VLAN filtering */
652fff32 1500 hw_dbg("Initializing the IEEE VLAN\n");
ceb5f13b 1501 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1128c756
CW		 1502 igb_clear_vfta_i350(hw);
1503 else
1504 igb_clear_vfta(hw);
9d5c8243
AK		 1505
1506 /* Setup the receive address */
5ac16659
AD		 1507 igb_init_rx_addrs(hw, rar_count);
1508
9d5c8243 1509 /* Zero out the Multicast HASH table */
652fff32 1510 hw_dbg("Zeroing the MTA\n");
9d5c8243
AK		 1511 for (i = 0; i < mac->mta_reg_count; i++)
1512 array_wr32(E1000_MTA, i, 0);
1513
68d480c4
AD		 1514 /* Zero out the Unicast HASH table */
1515 hw_dbg("Zeroing the UTA\n");
1516 for (i = 0; i < mac->uta_reg_count; i++)
1517 array_wr32(E1000_UTA, i, 0);
1518
9d5c8243
AK		 1519 /* Setup link and flow control */
1520 ret_val = igb_setup_link(hw);
1521
b980ac18 1522 /* Clear all of the statistics registers (clear on read). It is
9d5c8243
AK		 1523 * important that we do this after we have tried to establish link
1524 * because the symbol error count will increment wildly if there
1525 * is no link.
1526 */
1527 igb_clear_hw_cntrs_82575(hw);
9d5c8243
AK		 1528 return ret_val;
1529}
1530
1531/**
733596be 1532 * igb_setup_copper_link_82575 - Configure copper link settings
9d5c8243
AK		 1533 * @hw: pointer to the HW structure
1534 *
1535 * Configures the link for auto-neg or forced speed and duplex. Then we check
1536 * for link, once link is established calls to configure collision distance
1537 * and flow control are called.
1538 **/
1539static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1540{
12645a19 1541 u32 ctrl;
9d5c8243 1542 s32 ret_val;
867eb39e 1543 u32 phpm_reg;
9d5c8243
AK		 1544
1545 ctrl = rd32(E1000_CTRL);
1546 ctrl |= E1000_CTRL_SLU;
1547 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1548 wr32(E1000_CTRL, ctrl);
1549
db476e85
AA		 1550 /* Clear Go Link Disconnect bit on supported devices */
1551 switch (hw->mac.type) {
1552 case e1000_82580:
1553 case e1000_i350:
1554 case e1000_i210:
1555 case e1000_i211:
867eb39e
CW		 1556 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1557 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1558 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
db476e85
AA		 1559 break;
1560 default:
1561 break;
867eb39e
CW		 1562 }
1563
2fb02a26
AD		 1564 ret_val = igb_setup_serdes_link_82575(hw);
1565 if (ret_val)
1566 goto out;
1567
1568 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
bb2ac47b
AD		 1569 /* allow time for SFP cage time to power up phy */
1570 msleep(300);
1571
2fb02a26
AD		 1572 ret_val = hw->phy.ops.reset(hw);
1573 if (ret_val) {
1574 hw_dbg("Error resetting the PHY.\n");
1575 goto out;
1576 }
1577 }
9d5c8243 1578 switch (hw->phy.type) {
f96a8a0b 1579 case e1000_phy_i210:
9d5c8243 1580 case e1000_phy_m88:
ed65bdd8
CW		 1581 switch (hw->phy.id) {
1582 case I347AT4_E_PHY_ID:
1583 case M88E1112_E_PHY_ID:
99af4729 1584 case M88E1543_E_PHY_ID:
ed65bdd8 1585 case I210_I_PHY_ID:
308fb39a 1586 ret_val = igb_copper_link_setup_m88_gen2(hw);
ed65bdd8
CW		 1587 break;
1588 default:
308fb39a 1589 ret_val = igb_copper_link_setup_m88(hw);
ed65bdd8
CW		 1590 break;
1591 }
9d5c8243
AK		 1592 break;
1593 case e1000_phy_igp_3:
1594 ret_val = igb_copper_link_setup_igp(hw);
9d5c8243 1595 break;
bb2ac47b
AD		 1596 case e1000_phy_82580:
1597 ret_val = igb_copper_link_setup_82580(hw);
1598 break;
9d5c8243
AK		 1599 default:
1600 ret_val = -E1000_ERR_PHY;
1601 break;
1602 }
1603
1604 if (ret_val)
1605 goto out;
1606
81fadd81 1607 ret_val = igb_setup_copper_link(hw);
9d5c8243
AK		 1608out:
1609 return ret_val;
1610}
1611
1612/**
70d92f86 1613 * igb_setup_serdes_link_82575 - Setup link for serdes
9d5c8243
AK		 1614 * @hw: pointer to the HW structure
1615 *
70d92f86
AD		 1616 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1617 * used on copper connections where the serialized gigabit media independent
1618 * interface (sgmii), or serdes fiber is being used. Configures the link
1619 * for auto-negotiation or forces speed/duplex.
9d5c8243 1620 **/
2fb02a26 1621static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
9d5c8243 1622{
daf56e40 1623 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
bb2ac47b 1624 bool pcs_autoneg;
2c670b5b
CW		 1625 s32 ret_val = E1000_SUCCESS;
1626 u16 data;
2fb02a26
AD		 1627
1628 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1629 !igb_sgmii_active_82575(hw))
2c670b5b
CW		 1630 return ret_val;
1631
9d5c8243 1632
b980ac18 1633 /* On the 82575, SerDes loopback mode persists until it is
9d5c8243
AK		 1634 * explicitly turned off or a power cycle is performed. A read to
1635 * the register does not indicate its status. Therefore, we ensure
1636 * loopback mode is disabled during initialization.
1637 */
1638 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1639
e00bf607 1640 /* power on the sfp cage if present and turn on I2C */
bb2ac47b
AD		 1641 ctrl_ext = rd32(E1000_CTRL_EXT);
1642 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
e00bf607 1643 ctrl_ext |= E1000_CTRL_I2C_ENA;
bb2ac47b 1644 wr32(E1000_CTRL_EXT, ctrl_ext);
2fb02a26
AD		 1645
1646 ctrl_reg = rd32(E1000_CTRL);
1647 ctrl_reg |= E1000_CTRL_SLU;
1648
1649 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1650 /* set both sw defined pins */
1651 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1652
1653 /* Set switch control to serdes energy detect */
1654 reg = rd32(E1000_CONNSW);
1655 reg |= E1000_CONNSW_ENRGSRC;
1656 wr32(E1000_CONNSW, reg);
1657 }
1658
1659 reg = rd32(E1000_PCS_LCTL);
1660
bb2ac47b
AD		 1661 /* default pcs_autoneg to the same setting as mac autoneg */
1662 pcs_autoneg = hw->mac.autoneg;
2fb02a26 1663
bb2ac47b
AD		 1664 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1665 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1666 /* sgmii mode lets the phy handle forcing speed/duplex */
1667 pcs_autoneg = true;
1668 /* autoneg time out should be disabled for SGMII mode */
2fb02a26 1669 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
bb2ac47b
AD		 1670 break;
1671 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1672 /* disable PCS autoneg and support parallel detect only */
1673 pcs_autoneg = false;
1674 default:
2c670b5b
CW		 1675 if (hw->mac.type == e1000_82575 ||
1676 hw->mac.type == e1000_82576) {
1677 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1678 if (ret_val) {
c75c4edf 1679 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
2c670b5b
CW		 1680 return ret_val;
1681 }
1682
1683 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1684 pcs_autoneg = false;
1685 }
1686
b980ac18 1687 /* non-SGMII modes only supports a speed of 1000/Full for the
bb2ac47b
AD		 1688 * link so it is best to just force the MAC and let the pcs
1689 * link either autoneg or be forced to 1000/Full
1690 */
2fb02a26
AD		 1691 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1692 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
bb2ac47b
AD		 1693
1694 /* set speed of 1000/Full if speed/duplex is forced */
1695 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1696 break;
921aa749
AD		 1697 }
1698
2fb02a26 1699 wr32(E1000_CTRL, ctrl_reg);
9d5c8243 1700
b980ac18 1701 /* New SerDes mode allows for forcing speed or autonegotiating speed
9d5c8243
AK		 1702 * at 1gb. Autoneg should be default set by most drivers. This is the
1703 * mode that will be compatible with older link partners and switches.
1704 * However, both are supported by the hardware and some drivers/tools.
1705 */
9d5c8243
AK		 1706 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1707 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1708
bb2ac47b 1709 if (pcs_autoneg) {
9d5c8243 1710 /* Set PCS register for autoneg */
bb2ac47b 1711 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
70d92f86 1712 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
daf56e40
CW		 1713
1714 /* Disable force flow control for autoneg */
1715 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1716
1717 /* Configure flow control advertisement for autoneg */
1718 anadv_reg = rd32(E1000_PCS_ANADV);
1719 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1720 switch (hw->fc.requested_mode) {
1721 case e1000_fc_full:
1722 case e1000_fc_rx_pause:
1723 anadv_reg |= E1000_TXCW_ASM_DIR;
1724 anadv_reg |= E1000_TXCW_PAUSE;
1725 break;
1726 case e1000_fc_tx_pause:
1727 anadv_reg |= E1000_TXCW_ASM_DIR;
1728 break;
1729 default:
1730 break;
1731 }
1732 wr32(E1000_PCS_ANADV, anadv_reg);
1733
bb2ac47b 1734 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1735 } else {
bb2ac47b 1736 /* Set PCS register for forced link */
d68caec6 1737 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
bb2ac47b 1738
daf56e40
CW		 1739 /* Force flow control for forced link */
1740 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1741
bb2ac47b 1742 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
9d5c8243 1743 }
726c09e7 1744
9d5c8243
AK		 1745 wr32(E1000_PCS_LCTL, reg);
1746
daf56e40 1747 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
2fb02a26 1748 igb_force_mac_fc(hw);
9d5c8243 1749
2c670b5b 1750 return ret_val;
9d5c8243
AK		 1751}
1752
1753/**
733596be 1754 * igb_sgmii_active_82575 - Return sgmii state
9d5c8243
AK		 1755 * @hw: pointer to the HW structure
1756 *
1757 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1758 * which can be enabled for use in the embedded applications. Simply
1759 * return the current state of the sgmii interface.
1760 **/
1761static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1762{
c1889bfe 1763 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
c1889bfe 1764 return dev_spec->sgmii_active;
9d5c8243
AK		 1765}
1766
1767/**
733596be 1768 * igb_reset_init_script_82575 - Inits HW defaults after reset
9d5c8243
AK		 1769 * @hw: pointer to the HW structure
1770 *
1771 * Inits recommended HW defaults after a reset when there is no EEPROM
1772 * detected. This is only for the 82575.
1773 **/
1774static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1775{
1776 if (hw->mac.type == e1000_82575) {
652fff32 1777 hw_dbg("Running reset init script for 82575\n");
9d5c8243
AK		 1778 /* SerDes configuration via SERDESCTRL */
1779 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1780 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1781 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1782 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1783
1784 /* CCM configuration via CCMCTL register */
1785 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1786 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1787
1788 /* PCIe lanes configuration */
1789 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1790 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1791 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1792 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1793
1794 /* PCIe PLL Configuration */
1795 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1796 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1797 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1798 }
1799
1800 return 0;
1801}
1802
1803/**
733596be 1804 * igb_read_mac_addr_82575 - Read device MAC address
9d5c8243
AK		 1805 * @hw: pointer to the HW structure
1806 **/
1807static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1808{
1809 s32 ret_val = 0;
1810
b980ac18 1811 /* If there's an alternate MAC address place it in RAR0
22896639
AD		 1812 * so that it will override the Si installed default perm
1813 * address.
1814 */
1815 ret_val = igb_check_alt_mac_addr(hw);
1816 if (ret_val)
1817 goto out;
1818
1819 ret_val = igb_read_mac_addr(hw);
9d5c8243 1820
22896639 1821out:
9d5c8243
AK		 1822 return ret_val;
1823}
1824
88a268c1
NN		 1825/**
1826 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1827 * @hw: pointer to the HW structure
1828 *
1829 * In the case of a PHY power down to save power, or to turn off link during a
1830 * driver unload, or wake on lan is not enabled, remove the link.
1831 **/
1832void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1833{
1834 /* If the management interface is not enabled, then power down */
1835 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1836 igb_power_down_phy_copper(hw);
88a268c1
NN		 1837}
1838
9d5c8243 1839/**
733596be 1840 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
9d5c8243
AK		 1841 * @hw: pointer to the HW structure
1842 *
1843 * Clears the hardware counters by reading the counter registers.
1844 **/
1845static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1846{
9d5c8243
AK		 1847 igb_clear_hw_cntrs_base(hw);
1848
cc9073bb
AD		 1849 rd32(E1000_PRC64);
1850 rd32(E1000_PRC127);
1851 rd32(E1000_PRC255);
1852 rd32(E1000_PRC511);
1853 rd32(E1000_PRC1023);
1854 rd32(E1000_PRC1522);
1855 rd32(E1000_PTC64);
1856 rd32(E1000_PTC127);
1857 rd32(E1000_PTC255);
1858 rd32(E1000_PTC511);
1859 rd32(E1000_PTC1023);
1860 rd32(E1000_PTC1522);
1861
1862 rd32(E1000_ALGNERRC);
1863 rd32(E1000_RXERRC);
1864 rd32(E1000_TNCRS);
1865 rd32(E1000_CEXTERR);
1866 rd32(E1000_TSCTC);
1867 rd32(E1000_TSCTFC);
1868
1869 rd32(E1000_MGTPRC);
1870 rd32(E1000_MGTPDC);
1871 rd32(E1000_MGTPTC);
1872
1873 rd32(E1000_IAC);
1874 rd32(E1000_ICRXOC);
1875
1876 rd32(E1000_ICRXPTC);
1877 rd32(E1000_ICRXATC);
1878 rd32(E1000_ICTXPTC);
1879 rd32(E1000_ICTXATC);
1880 rd32(E1000_ICTXQEC);
1881 rd32(E1000_ICTXQMTC);
1882 rd32(E1000_ICRXDMTC);
1883
1884 rd32(E1000_CBTMPC);
1885 rd32(E1000_HTDPMC);
1886 rd32(E1000_CBRMPC);
1887 rd32(E1000_RPTHC);
1888 rd32(E1000_HGPTC);
1889 rd32(E1000_HTCBDPC);
1890 rd32(E1000_HGORCL);
1891 rd32(E1000_HGORCH);
1892 rd32(E1000_HGOTCL);
1893 rd32(E1000_HGOTCH);
1894 rd32(E1000_LENERRS);
9d5c8243
AK		 1895
1896 /* This register should not be read in copper configurations */
2fb02a26
AD		 1897 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1898 igb_sgmii_active_82575(hw))
cc9073bb 1899 rd32(E1000_SCVPC);
9d5c8243
AK		 1900}
1901
662d7205
AD		 1902/**
1903 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1904 * @hw: pointer to the HW structure
1905 *
1906 * After rx enable if managability is enabled then there is likely some
1907 * bad data at the start of the fifo and possibly in the DMA fifo. This
1908 * function clears the fifos and flushes any packets that came in as rx was
1909 * being enabled.
1910 **/
1911void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1912{
1913 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1914 int i, ms_wait;
1915
1916 if (hw->mac.type != e1000_82575 ||
1917 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1918 return;
1919
1920 /* Disable all RX queues */
1921 for (i = 0; i < 4; i++) {
1922 rxdctl[i] = rd32(E1000_RXDCTL(i));
1923 wr32(E1000_RXDCTL(i),
1924 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1925 }
1926 /* Poll all queues to verify they have shut down */
1927 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1928 msleep(1);
1929 rx_enabled = 0;
1930 for (i = 0; i < 4; i++)
1931 rx_enabled |= rd32(E1000_RXDCTL(i));
1932 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1933 break;
1934 }
1935
1936 if (ms_wait == 10)
1937 hw_dbg("Queue disable timed out after 10ms\n");
1938
1939 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1940 * incoming packets are rejected. Set enable and wait 2ms so that
1941 * any packet that was coming in as RCTL.EN was set is flushed
1942 */
1943 rfctl = rd32(E1000_RFCTL);
1944 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1945
1946 rlpml = rd32(E1000_RLPML);
1947 wr32(E1000_RLPML, 0);
1948
1949 rctl = rd32(E1000_RCTL);
1950 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1951 temp_rctl |= E1000_RCTL_LPE;
1952
1953 wr32(E1000_RCTL, temp_rctl);
1954 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1955 wrfl();
1956 msleep(2);
1957
1958 /* Enable RX queues that were previously enabled and restore our
1959 * previous state
1960 */
1961 for (i = 0; i < 4; i++)
1962 wr32(E1000_RXDCTL(i), rxdctl[i]);
1963 wr32(E1000_RCTL, rctl);
1964 wrfl();
1965
1966 wr32(E1000_RLPML, rlpml);
1967 wr32(E1000_RFCTL, rfctl);
1968
1969 /* Flush receive errors generated by workaround */
1970 rd32(E1000_ROC);
1971 rd32(E1000_RNBC);
1972 rd32(E1000_MPC);
1973}
1974
009bc06e
AD		 1975/**
1976 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1977 * @hw: pointer to the HW structure
1978 *
1979 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1980 * however the hardware default for these parts is 500us to 1ms which is less
1981 * than the 10ms recommended by the pci-e spec. To address this we need to
1982 * increase the value to either 10ms to 200ms for capability version 1 config,
1983 * or 16ms to 55ms for version 2.
1984 **/
1985static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1986{
1987 u32 gcr = rd32(E1000_GCR);
1988 s32 ret_val = 0;
1989 u16 pcie_devctl2;
1990
1991 /* only take action if timeout value is defaulted to 0 */
1992 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1993 goto out;
1994
b980ac18 1995 /* if capabilities version is type 1 we can write the
009bc06e
AD		 1996 * timeout of 10ms to 200ms through the GCR register
1997 */
1998 if (!(gcr & E1000_GCR_CAP_VER2)) {
1999 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2000 goto out;
2001 }
2002
b980ac18 2003 /* for version 2 capabilities we need to write the config space
009bc06e
AD		 2004 * directly in order to set the completion timeout value for
2005 * 16ms to 55ms
2006 */
2007 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2008 &pcie_devctl2);
2009 if (ret_val)
2010 goto out;
2011
2012 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2013
2014 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2015 &pcie_devctl2);
2016out:
2017 /* disable completion timeout resend */
2018 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2019
2020 wr32(E1000_GCR, gcr);
2021 return ret_val;
2022}
2023
13800469
GR		 2024/**
2025 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2026 * @hw: pointer to the hardware struct
2027 * @enable: state to enter, either enabled or disabled
2028 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2029 *
2030 * enables/disables L2 switch anti-spoofing functionality.
2031 **/
2032void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2033{
22c12752 2034 u32 reg_val, reg_offset;
13800469
GR		 2035
2036 switch (hw->mac.type) {
2037 case e1000_82576:
22c12752
LL		 2038 reg_offset = E1000_DTXSWC;
2039 break;
13800469 2040 case e1000_i350:
ceb5f13b 2041 case e1000_i354:
22c12752 2042 reg_offset = E1000_TXSWC;
13800469
GR		 2043 break;
2044 default:
22c12752
LL		 2045 return;
2046 }
2047
2048 reg_val = rd32(reg_offset);
2049 if (enable) {
2050 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2051 E1000_DTXSWC_VLAN_SPOOF_MASK);
2052 /* The PF can spoof - it has to in order to
2053 * support emulation mode NICs
2054 */
2055 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2056 } else {
2057 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2058 E1000_DTXSWC_VLAN_SPOOF_MASK);
13800469 2059 }
22c12752 2060 wr32(reg_offset, reg_val);
13800469
GR		 2061}
2062
4ae196df
AD		 2063/**
2064 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2065 * @hw: pointer to the hardware struct
2066 * @enable: state to enter, either enabled or disabled
2067 *
2068 * enables/disables L2 switch loopback functionality.
2069 **/
2070void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2071{
ca2e3e7e
AA		 2072 u32 dtxswc;
2073
2074 switch (hw->mac.type) {
2075 case e1000_82576:
2076 dtxswc = rd32(E1000_DTXSWC);
2077 if (enable)
2078 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2079 else
2080 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2081 wr32(E1000_DTXSWC, dtxswc);
2082 break;
ceb5f13b 2083 case e1000_i354:
ca2e3e7e
AA		 2084 case e1000_i350:
2085 dtxswc = rd32(E1000_TXSWC);
2086 if (enable)
2087 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2088 else
2089 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2090 wr32(E1000_TXSWC, dtxswc);
2091 break;
2092 default:
2093 /* Currently no other hardware supports loopback */
2094 break;
2095 }
4ae196df 2096
4ae196df
AD		 2097}
2098
2099/**
2100 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
2101 * @hw: pointer to the hardware struct
2102 * @enable: state to enter, either enabled or disabled
2103 *
2104 * enables/disables replication of packets across multiple pools.
2105 **/
2106void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2107{
2108 u32 vt_ctl = rd32(E1000_VT_CTL);
2109
2110 if (enable)
2111 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2112 else
2113 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2114
2115 wr32(E1000_VT_CTL, vt_ctl);
2116}
2117
bb2ac47b
AD		 2118/**
2119 * igb_read_phy_reg_82580 - Read 82580 MDI control register
2120 * @hw: pointer to the HW structure
2121 * @offset: register offset to be read
2122 * @data: pointer to the read data
2123 *
2124 * Reads the MDI control register in the PHY at offset and stores the
2125 * information read to data.
2126 **/
2127static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2128{
bb2ac47b
AD		 2129 s32 ret_val;
2130
bb2ac47b
AD		 2131 ret_val = hw->phy.ops.acquire(hw);
2132 if (ret_val)
2133 goto out;
2134
bb2ac47b
AD		 2135 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2136
2137 hw->phy.ops.release(hw);
2138
2139out:
2140 return ret_val;
2141}
2142
2143/**
2144 * igb_write_phy_reg_82580 - Write 82580 MDI control register
2145 * @hw: pointer to the HW structure
2146 * @offset: register offset to write to
2147 * @data: data to write to register at offset
2148 *
2149 * Writes data to MDI control register in the PHY at offset.
2150 **/
2151static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2152{
bb2ac47b
AD		 2153 s32 ret_val;
2154
2155
2156 ret_val = hw->phy.ops.acquire(hw);
2157 if (ret_val)
2158 goto out;
2159
bb2ac47b
AD		 2160 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2161
2162 hw->phy.ops.release(hw);
2163
2164out:
2165 return ret_val;
2166}
2167
08451e25
NN		 2168/**
2169 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2170 * @hw: pointer to the HW structure
2171 *
2172 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2173 * the values found in the EEPROM. This addresses an issue in which these
2174 * bits are not restored from EEPROM after reset.
2175 **/
2176static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2177{
2178 s32 ret_val = 0;
2179 u32 mdicnfg;
1b5dda33 2180 u16 nvm_data = 0;
08451e25
NN		 2181
2182 if (hw->mac.type != e1000_82580)
2183 goto out;
2184 if (!igb_sgmii_active_82575(hw))
2185 goto out;
2186
2187 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2188 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2189 &nvm_data);
2190 if (ret_val) {
2191 hw_dbg("NVM Read Error\n");
2192 goto out;
2193 }
2194
2195 mdicnfg = rd32(E1000_MDICNFG);
2196 if (nvm_data & NVM_WORD24_EXT_MDIO)
2197 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2198 if (nvm_data & NVM_WORD24_COM_MDIO)
2199 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2200 wr32(E1000_MDICNFG, mdicnfg);
2201out:
2202 return ret_val;
2203}
2204
bb2ac47b
AD		 2205/**
2206 * igb_reset_hw_82580 - Reset hardware
2207 * @hw: pointer to the HW structure
2208 *
2209 * This resets function or entire device (all ports, etc.)
2210 * to a known state.
2211 **/
2212static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2213{
2214 s32 ret_val = 0;
2215 /* BH SW mailbox bit in SW_FW_SYNC */
2216 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
e5c3370f 2217 u32 ctrl;
bb2ac47b
AD		 2218 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2219
bb2ac47b
AD		 2220 hw->dev_spec._82575.global_device_reset = false;
2221
a0483e2e
CW		 2222 /* due to hw errata, global device reset doesn't always
2223 * work on 82580
2224 */
2225 if (hw->mac.type == e1000_82580)
2226 global_device_reset = false;
2227
bb2ac47b
AD		 2228 /* Get current control state. */
2229 ctrl = rd32(E1000_CTRL);
2230
b980ac18 2231 /* Prevent the PCI-E bus from sticking if there is no TLP connection
bb2ac47b
AD		 2232 * on the last TLP read/write transaction when MAC is reset.
2233 */
2234 ret_val = igb_disable_pcie_master(hw);
2235 if (ret_val)
2236 hw_dbg("PCI-E Master disable polling has failed.\n");
2237
2238 hw_dbg("Masking off all interrupts\n");
2239 wr32(E1000_IMC, 0xffffffff);
2240 wr32(E1000_RCTL, 0);
2241 wr32(E1000_TCTL, E1000_TCTL_PSP);
2242 wrfl();
2243
2244 msleep(10);
2245
2246 /* Determine whether or not a global dev reset is requested */
2247 if (global_device_reset &&
f96a8a0b 2248 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
bb2ac47b
AD		 2249 global_device_reset = false;
2250
2251 if (global_device_reset &&
2252 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2253 ctrl |= E1000_CTRL_DEV_RST;
2254 else
2255 ctrl |= E1000_CTRL_RST;
2256
2257 wr32(E1000_CTRL, ctrl);
064b4330 2258 wrfl();
bb2ac47b
AD		 2259
2260 /* Add delay to insure DEV_RST has time to complete */
2261 if (global_device_reset)
2262 msleep(5);
2263
2264 ret_val = igb_get_auto_rd_done(hw);
2265 if (ret_val) {
b980ac18 2266 /* When auto config read does not complete, do not
bb2ac47b
AD		 2267 * return with an error. This can happen in situations
2268 * where there is no eeprom and prevents getting link.
2269 */
2270 hw_dbg("Auto Read Done did not complete\n");
2271 }
2272
bb2ac47b
AD		 2273 /* clear global device reset status bit */
2274 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2275
2276 /* Clear any pending interrupt events. */
2277 wr32(E1000_IMC, 0xffffffff);
e5c3370f 2278 rd32(E1000_ICR);
bb2ac47b 2279
08451e25
NN		 2280 ret_val = igb_reset_mdicnfg_82580(hw);
2281 if (ret_val)
2282 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2283
bb2ac47b
AD		 2284 /* Install any alternate MAC address into RAR0 */
2285 ret_val = igb_check_alt_mac_addr(hw);
2286
2287 /* Release semaphore */
2288 if (global_device_reset)
f96a8a0b 2289 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
bb2ac47b
AD		 2290
2291 return ret_val;
2292}
2293
2294/**
2295 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2296 * @data: data received by reading RXPBS register
2297 *
2298 * The 82580 uses a table based approach for packet buffer allocation sizes.
2299 * This function converts the retrieved value into the correct table value
2300 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2301 * 0x0 36 72 144 1 2 4 8 16
2302 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2303 */
2304u16 igb_rxpbs_adjust_82580(u32 data)
2305{
2306 u16 ret_val = 0;
2307
72b36727 2308 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
bb2ac47b
AD		 2309 ret_val = e1000_82580_rxpbs_table[data];
2310
2311 return ret_val;
2312}
2313
4322e561
CW		 2314/**
2315 * igb_validate_nvm_checksum_with_offset - Validate EEPROM
2316 * checksum
2317 * @hw: pointer to the HW structure
2318 * @offset: offset in words of the checksum protected region
2319 *
2320 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2321 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2322 **/
bed45a6e
ET		 2323static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2324 u16 offset)
4322e561
CW		 2325{
2326 s32 ret_val = 0;
2327 u16 checksum = 0;
2328 u16 i, nvm_data;
2329
2330 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2331 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2332 if (ret_val) {
2333 hw_dbg("NVM Read Error\n");
2334 goto out;
2335 }
2336 checksum += nvm_data;
2337 }
2338
2339 if (checksum != (u16) NVM_SUM) {
2340 hw_dbg("NVM Checksum Invalid\n");
2341 ret_val = -E1000_ERR_NVM;
2342 goto out;
2343 }
2344
2345out:
2346 return ret_val;
2347}
2348
2349/**
2350 * igb_update_nvm_checksum_with_offset - Update EEPROM
2351 * checksum
2352 * @hw: pointer to the HW structure
2353 * @offset: offset in words of the checksum protected region
2354 *
2355 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2356 * up to the checksum. Then calculates the EEPROM checksum and writes the
2357 * value to the EEPROM.
2358 **/
bed45a6e 2359static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
4322e561
CW		 2360{
2361 s32 ret_val;
2362 u16 checksum = 0;
2363 u16 i, nvm_data;
2364
2365 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2366 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2367 if (ret_val) {
2368 hw_dbg("NVM Read Error while updating checksum.\n");
2369 goto out;
2370 }
2371 checksum += nvm_data;
2372 }
2373 checksum = (u16) NVM_SUM - checksum;
2374 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2375 &checksum);
2376 if (ret_val)
2377 hw_dbg("NVM Write Error while updating checksum.\n");
2378
2379out:
2380 return ret_val;
2381}
2382
2383/**
2384 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2385 * @hw: pointer to the HW structure
2386 *
2387 * Calculates the EEPROM section checksum by reading/adding each word of
2388 * the EEPROM and then verifies that the sum of the EEPROM is
2389 * equal to 0xBABA.
2390 **/
2391static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2392{
2393 s32 ret_val = 0;
2394 u16 eeprom_regions_count = 1;
2395 u16 j, nvm_data;
2396 u16 nvm_offset;
2397
2398 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2399 if (ret_val) {
2400 hw_dbg("NVM Read Error\n");
2401 goto out;
2402 }
2403
2404 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
34a0326e 2405 /* if checksums compatibility bit is set validate checksums
b980ac18
JK		 2406 * for all 4 ports.
2407 */
4322e561
CW		 2408 eeprom_regions_count = 4;
2409 }
2410
2411 for (j = 0; j < eeprom_regions_count; j++) {
2412 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2413 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2414 nvm_offset);
2415 if (ret_val != 0)
2416 goto out;
2417 }
2418
2419out:
2420 return ret_val;
2421}
2422
2423/**
2424 * igb_update_nvm_checksum_82580 - Update EEPROM checksum
2425 * @hw: pointer to the HW structure
2426 *
2427 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2428 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2429 * checksum and writes the value to the EEPROM.
2430 **/
2431static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2432{
2433 s32 ret_val;
2434 u16 j, nvm_data;
2435 u16 nvm_offset;
2436
2437 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2438 if (ret_val) {
c75c4edf 2439 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
4322e561
CW		 2440 goto out;
2441 }
2442
2443 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2444 /* set compatibility bit to validate checksums appropriately */
2445 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2446 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2447 &nvm_data);
2448 if (ret_val) {
c75c4edf 2449 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
4322e561
CW		 2450 goto out;
2451 }
2452 }
2453
2454 for (j = 0; j < 4; j++) {
2455 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2456 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2457 if (ret_val)
2458 goto out;
2459 }
2460
2461out:
2462 return ret_val;
2463}
2464
2465/**
2466 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2467 * @hw: pointer to the HW structure
2468 *
2469 * Calculates the EEPROM section checksum by reading/adding each word of
2470 * the EEPROM and then verifies that the sum of the EEPROM is
2471 * equal to 0xBABA.
2472 **/
2473static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2474{
2475 s32 ret_val = 0;
2476 u16 j;
2477 u16 nvm_offset;
2478
2479 for (j = 0; j < 4; j++) {
2480 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2481 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2482 nvm_offset);
2483 if (ret_val != 0)
2484 goto out;
2485 }
2486
2487out:
2488 return ret_val;
2489}
2490
2491/**
2492 * igb_update_nvm_checksum_i350 - Update EEPROM checksum
2493 * @hw: pointer to the HW structure
2494 *
2495 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2496 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2497 * checksum and writes the value to the EEPROM.
2498 **/
2499static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2500{
2501 s32 ret_val = 0;
2502 u16 j;
2503 u16 nvm_offset;
2504
2505 for (j = 0; j < 4; j++) {
2506 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2507 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2508 if (ret_val != 0)
2509 goto out;
2510 }
2511
2512out:
2513 return ret_val;
2514}
34a0326e 2515
87371b9d
MV		 2516/**
2517 * __igb_access_emi_reg - Read/write EMI register
2518 * @hw: pointer to the HW structure
2519 * @addr: EMI address to program
2520 * @data: pointer to value to read/write from/to the EMI address
2521 * @read: boolean flag to indicate read or write
2522 **/
2523static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2524 u16 *data, bool read)
2525{
2526 s32 ret_val = E1000_SUCCESS;
2527
2528 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2529 if (ret_val)
2530 return ret_val;
2531
2532 if (read)
2533 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2534 else
2535 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2536
2537 return ret_val;
2538}
2539
2540/**
2541 * igb_read_emi_reg - Read Extended Management Interface register
2542 * @hw: pointer to the HW structure
2543 * @addr: EMI address to program
2544 * @data: value to be read from the EMI address
2545 **/
2546s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2547{
2548 return __igb_access_emi_reg(hw, addr, data, true);
2549}
2550
09b068d4
CW		 2551/**
2552 * igb_set_eee_i350 - Enable/disable EEE support
2553 * @hw: pointer to the HW structure
2554 *
2555 * Enable/disable EEE based on setting in dev_spec structure.
2556 *
2557 **/
2558s32 igb_set_eee_i350(struct e1000_hw *hw)
2559{
2560 s32 ret_val = 0;
e5461112 2561 u32 ipcnfg, eeer;
09b068d4 2562
e5461112
AA		 2563 if ((hw->mac.type < e1000_i350) ||
2564 (hw->phy.media_type != e1000_media_type_copper))
09b068d4
CW		 2565 goto out;
2566 ipcnfg = rd32(E1000_IPCNFG);
2567 eeer = rd32(E1000_EEER);
2568
2569 /* enable or disable per user setting */
2570 if (!(hw->dev_spec._82575.eee_disable)) {
40b20122
CW		 2571 u32 eee_su = rd32(E1000_EEE_SU);
2572
2573 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2574 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
09b068d4
CW		 2575 E1000_EEER_LPI_FC);
2576
40b20122
CW		 2577 /* This bit should not be set in normal operation. */
2578 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2579 hw_dbg("LPI Clock Stop Bit should not be set!\n");
2580
09b068d4
CW		 2581 } else {
2582 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2583 E1000_IPCNFG_EEE_100M_AN);
2584 eeer &= ~(E1000_EEER_TX_LPI_EN |
2585 E1000_EEER_RX_LPI_EN |
2586 E1000_EEER_LPI_FC);
2587 }
2588 wr32(E1000_IPCNFG, ipcnfg);
2589 wr32(E1000_EEER, eeer);
e5461112
AA		 2590 rd32(E1000_IPCNFG);
2591 rd32(E1000_EEER);
09b068d4
CW		 2592out:
2593
2594 return ret_val;
2595}
4322e561 2596
ceb5f13b
CW		 2597/**
2598 * igb_set_eee_i354 - Enable/disable EEE support
2599 * @hw: pointer to the HW structure
2600 *
2601 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2602 *
2603 **/
2604s32 igb_set_eee_i354(struct e1000_hw *hw)
2605{
2606 struct e1000_phy_info *phy = &hw->phy;
2607 s32 ret_val = 0;
2608 u16 phy_data;
2609
2610 if ((hw->phy.media_type != e1000_media_type_copper) ||
99af4729 2611 (phy->id != M88E1543_E_PHY_ID))
ceb5f13b
CW		 2612 goto out;
2613
2614 if (!hw->dev_spec._82575.eee_disable) {
2615 /* Switch to PHY page 18. */
99af4729 2616 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
ceb5f13b
CW		 2617 if (ret_val)
2618 goto out;
2619
99af4729 2620 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
ceb5f13b
CW		 2621 &phy_data);
2622 if (ret_val)
2623 goto out;
2624
99af4729
AA		 2625 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2626 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
ceb5f13b
CW		 2627 phy_data);
2628 if (ret_val)
2629 goto out;
2630
2631 /* Return the PHY to page 0. */
99af4729 2632 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
ceb5f13b
CW		 2633 if (ret_val)
2634 goto out;
2635
2636 /* Turn on EEE advertisement. */
2637 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2638 E1000_EEE_ADV_DEV_I354,
2639 &phy_data);
2640 if (ret_val)
2641 goto out;
2642
2643 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2644 E1000_EEE_ADV_1000_SUPPORTED;
2645 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2646 E1000_EEE_ADV_DEV_I354,
2647 phy_data);
2648 } else {
2649 /* Turn off EEE advertisement. */
2650 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2651 E1000_EEE_ADV_DEV_I354,
2652 &phy_data);
2653 if (ret_val)
2654 goto out;
2655
2656 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2657 E1000_EEE_ADV_1000_SUPPORTED);
2658 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2659 E1000_EEE_ADV_DEV_I354,
2660 phy_data);
2661 }
2662
2663out:
2664 return ret_val;
2665}
2666
2667/**
2668 * igb_get_eee_status_i354 - Get EEE status
2669 * @hw: pointer to the HW structure
2670 * @status: EEE status
2671 *
2672 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2673 * been received.
2674 **/
2675s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2676{
2677 struct e1000_phy_info *phy = &hw->phy;
2678 s32 ret_val = 0;
2679 u16 phy_data;
2680
2681 /* Check if EEE is supported on this device. */
2682 if ((hw->phy.media_type != e1000_media_type_copper) ||
99af4729 2683 (phy->id != M88E1543_E_PHY_ID))
ceb5f13b
CW		 2684 goto out;
2685
2686 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2687 E1000_PCS_STATUS_DEV_I354,
2688 &phy_data);
2689 if (ret_val)
2690 goto out;
2691
2692 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2693 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2694
2695out:
2696 return ret_val;
2697}
2698
e428893b
CW		 2699static const u8 e1000_emc_temp_data[4] = {
2700 E1000_EMC_INTERNAL_DATA,
2701 E1000_EMC_DIODE1_DATA,
2702 E1000_EMC_DIODE2_DATA,
2703 E1000_EMC_DIODE3_DATA
2704};
2705static const u8 e1000_emc_therm_limit[4] = {
2706 E1000_EMC_INTERNAL_THERM_LIMIT,
2707 E1000_EMC_DIODE1_THERM_LIMIT,
2708 E1000_EMC_DIODE2_THERM_LIMIT,
2709 E1000_EMC_DIODE3_THERM_LIMIT
2710};
2711
9b143d11 2712#ifdef CONFIG_IGB_HWMON
b980ac18
JK		 2713/**
2714 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
e428893b
CW		 2715 * @hw: pointer to hardware structure
2716 *
2717 * Updates the temperatures in mac.thermal_sensor_data
b980ac18 2718 **/
167f3f71 2719static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
e428893b
CW		 2720{
2721 s32 status = E1000_SUCCESS;
2722 u16 ets_offset;
2723 u16 ets_cfg;
2724 u16 ets_sensor;
2725 u8 num_sensors;
2726 u8 sensor_index;
2727 u8 sensor_location;
2728 u8 i;
2729 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2730
2731 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2732 return E1000_NOT_IMPLEMENTED;
2733
2734 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2735
2736 /* Return the internal sensor only if ETS is unsupported */
2737 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2738 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2739 return status;
2740
2741 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2742 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2743 != NVM_ETS_TYPE_EMC)
2744 return E1000_NOT_IMPLEMENTED;
2745
2746 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2747 if (num_sensors > E1000_MAX_SENSORS)
2748 num_sensors = E1000_MAX_SENSORS;
2749
2750 for (i = 1; i < num_sensors; i++) {
2751 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2752 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2753 NVM_ETS_DATA_INDEX_SHIFT);
2754 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2755 NVM_ETS_DATA_LOC_SHIFT);
2756
2757 if (sensor_location != 0)
2758 hw->phy.ops.read_i2c_byte(hw,
2759 e1000_emc_temp_data[sensor_index],
2760 E1000_I2C_THERMAL_SENSOR_ADDR,
2761 &data->sensor[i].temp);
2762 }
2763 return status;
2764}
2765
b980ac18
JK		 2766/**
2767 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
e428893b
CW		 2768 * @hw: pointer to hardware structure
2769 *
2770 * Sets the thermal sensor thresholds according to the NVM map
2771 * and save off the threshold and location values into mac.thermal_sensor_data
b980ac18 2772 **/
167f3f71 2773static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
e428893b
CW		 2774{
2775 s32 status = E1000_SUCCESS;
2776 u16 ets_offset;
2777 u16 ets_cfg;
2778 u16 ets_sensor;
2779 u8 low_thresh_delta;
2780 u8 num_sensors;
2781 u8 sensor_index;
2782 u8 sensor_location;
2783 u8 therm_limit;
2784 u8 i;
2785 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2786
2787 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2788 return E1000_NOT_IMPLEMENTED;
2789
2790 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2791
2792 data->sensor[0].location = 0x1;
2793 data->sensor[0].caution_thresh =
2794 (rd32(E1000_THHIGHTC) & 0xFF);
2795 data->sensor[0].max_op_thresh =
2796 (rd32(E1000_THLOWTC) & 0xFF);
2797
2798 /* Return the internal sensor only if ETS is unsupported */
2799 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2800 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2801 return status;
2802
2803 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2804 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2805 != NVM_ETS_TYPE_EMC)
2806 return E1000_NOT_IMPLEMENTED;
2807
2808 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2809 NVM_ETS_LTHRES_DELTA_SHIFT);
2810 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2811
2812 for (i = 1; i <= num_sensors; i++) {
2813 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2814 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2815 NVM_ETS_DATA_INDEX_SHIFT);
2816 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2817 NVM_ETS_DATA_LOC_SHIFT);
2818 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2819
2820 hw->phy.ops.write_i2c_byte(hw,
2821 e1000_emc_therm_limit[sensor_index],
2822 E1000_I2C_THERMAL_SENSOR_ADDR,
2823 therm_limit);
2824
2825 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2826 data->sensor[i].location = sensor_location;
2827 data->sensor[i].caution_thresh = therm_limit;
2828 data->sensor[i].max_op_thresh = therm_limit -
2829 low_thresh_delta;
2830 }
2831 }
2832 return status;
2833}
2834
9b143d11 2835#endif
9d5c8243 2836static struct e1000_mac_operations e1000_mac_ops_82575 = {
9d5c8243
AK		 2837 .init_hw = igb_init_hw_82575,
2838 .check_for_link = igb_check_for_link_82575,
2d064c06 2839 .rar_set = igb_rar_set,
9d5c8243 2840 .read_mac_addr = igb_read_mac_addr_82575,
f6878e39 2841 .get_speed_and_duplex = igb_get_link_up_info_82575,
e428893b
CW		 2842#ifdef CONFIG_IGB_HWMON
2843 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2844 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2845#endif
9d5c8243
AK		 2846};
2847
2848static struct e1000_phy_operations e1000_phy_ops_82575 = {
a8d2a0c2 2849 .acquire = igb_acquire_phy_82575,
9d5c8243 2850 .get_cfg_done = igb_get_cfg_done_82575,
a8d2a0c2 2851 .release = igb_release_phy_82575,
441fc6fd
CW		 2852 .write_i2c_byte = igb_write_i2c_byte,
2853 .read_i2c_byte = igb_read_i2c_byte,
9d5c8243
AK		 2854};
2855
2856static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
312c75ae
AD		 2857 .acquire = igb_acquire_nvm_82575,
2858 .read = igb_read_nvm_eerd,
2859 .release = igb_release_nvm_82575,
2860 .write = igb_write_nvm_spi,
9d5c8243
AK		 2861};
2862
2863const struct e1000_info e1000_82575_info = {
2864 .get_invariants = igb_get_invariants_82575,
2865 .mac_ops = &e1000_mac_ops_82575,
2866 .phy_ops = &e1000_phy_ops_82575,
2867 .nvm_ops = &e1000_nvm_ops_82575,
2868};
2869
Linux kernel - Deliverables
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