[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_82575.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2013 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_82575_H_
#define _E1000_82575_H_

extern void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
extern void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
extern void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
extern s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
				u8 dev_addr, u8 *data);
extern s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
				 u8 dev_addr, u8 data);

#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
                                     (ID_LED_DEF1_DEF2 <<  8) | \
                                     (ID_LED_DEF1_DEF2 <<  4) | \
                                     (ID_LED_OFF1_ON2))

#define E1000_RAR_ENTRIES_82575        16
#define E1000_RAR_ENTRIES_82576        24
#define E1000_RAR_ENTRIES_82580        24
#define E1000_RAR_ENTRIES_I350         32

#define E1000_SW_SYNCH_MB              0x00000100
#define E1000_STAT_DEV_RST_SET         0x00100000
#define E1000_CTRL_DEV_RST             0x20000000

/* SRRCTL bit definitions */
#define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
#define E1000_SRRCTL_DROP_EN                            0x80000000
#define E1000_SRRCTL_TIMESTAMP                          0x40000000


#define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
#define E1000_MRQC_ENABLE_VMDQ              0x00000003
#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005
#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000

#define E1000_EICR_TX_QUEUE ( \
    E1000_EICR_TX_QUEUE0 |    \
    E1000_EICR_TX_QUEUE1 |    \
    E1000_EICR_TX_QUEUE2 |    \
    E1000_EICR_TX_QUEUE3)

#define E1000_EICR_RX_QUEUE ( \
    E1000_EICR_RX_QUEUE0 |    \
    E1000_EICR_RX_QUEUE1 |    \
    E1000_EICR_RX_QUEUE2 |    \
    E1000_EICR_RX_QUEUE3)

/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
#define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
#define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */

/* Receive Descriptor - Advanced */
union e1000_adv_rx_desc {
	struct {
		__le64 pkt_addr;             /* Packet buffer address */
		__le64 hdr_addr;             /* Header buffer address */
	} read;
	struct {
		struct {
			struct {
				__le16 pkt_info;   /* RSS type, Packet type */
				__le16 hdr_info;   /* Split Header,
						    * header buffer length */
			} lo_dword;
			union {
				__le32 rss;          /* RSS Hash */
				struct {
					__le16 ip_id;    /* IP id */
					__le16 csum;     /* Packet Checksum */
				} csum_ip;
			} hi_dword;
		} lower;
		struct {
			__le32 status_error;     /* ext status/error */
			__le16 length;           /* Packet length */
			__le16 vlan;             /* VLAN tag */
		} upper;
	} wb;  /* writeback */
};

#define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
#define E1000_RXDADV_HDRBUFLEN_SHIFT     5
#define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
#define E1000_RXDADV_STAT_TSIP           0x08000 /* timestamp in packet */

/* Transmit Descriptor - Advanced */
union e1000_adv_tx_desc {
	struct {
		__le64 buffer_addr;    /* Address of descriptor's data buf */
		__le32 cmd_type_len;
		__le32 olinfo_status;
	} read;
	struct {
		__le64 rsvd;       /* Reserved */
		__le32 nxtseq_seed;
		__le32 status;
	} wb;
};

/* Adv Transmit Descriptor Config Masks */
#define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
#define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
#define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
#define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
#define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
#define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
#define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
#define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
#define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
#define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */

/* Context descriptors */
struct e1000_adv_tx_context_desc {
	__le32 vlan_macip_lens;
	__le32 seqnum_seed;
	__le32 type_tucmd_mlhl;
	__le32 mss_l4len_idx;
};

#define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
#define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
/* IPSec Encrypt Enable for ESP */
#define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
#define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
/* Adv ctxt IPSec SA IDX mask */
/* Adv ctxt IPSec ESP len mask */

/* Additional Transmit Descriptor Control definitions */
#define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
/* Tx Queue Arbitration Priority 0=low, 1=high */

/* Additional Receive Descriptor Control definitions */
#define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */

/* Direct Cache Access (DCA) definitions */
#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
#define E1000_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */

#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */

#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */

/* Additional DCA related definitions, note change in position of CPUID */
#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */

/* ETQF register bit definitions */
#define E1000_ETQF_FILTER_ENABLE   (1 << 26)
#define E1000_ETQF_1588            (1 << 30)

/* FTQF register bit definitions */
#define E1000_FTQF_VF_BP               0x00008000
#define E1000_FTQF_1588_TIME_STAMP     0x08000000
#define E1000_FTQF_MASK                0xF0000000
#define E1000_FTQF_MASK_PROTO_BP       0x10000000
#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000

#define E1000_NVM_APME_82575          0x0400
#define MAX_NUM_VFS                   8

#define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
#define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
#define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */

/* Easy defines for setting default pool, would normally be left a zero */
#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
#define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)

/* Other useful VMD_CTL register defines */
#define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
#define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
#define E1000_VT_CTL_VM_REPL_EN         (1 << 30)

/* Per VM Offload register setup */
#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
#define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
#define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
#define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
#define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
#define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
#define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
#define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
#define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
#define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */

#define E1000_VLVF_ARRAY_SIZE     32
#define E1000_VLVF_VLANID_MASK    0x00000FFF
#define E1000_VLVF_POOLSEL_SHIFT  12
#define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
#define E1000_VLVF_LVLAN          0x00100000
#define E1000_VLVF_VLANID_ENABLE  0x80000000

#define E1000_VMVIR_VLANA_DEFAULT      0x40000000 /* Always use default VLAN */
#define E1000_VMVIR_VLANA_NEVER        0x80000000 /* Never insert VLAN tag */

#define E1000_IOVCTL 0x05BBC
#define E1000_IOVCTL_REUSE_VFQ 0x00000001

#define E1000_RPLOLR_STRVLAN   0x40000000
#define E1000_RPLOLR_STRCRC    0x80000000

#define E1000_DTXCTL_8023LL     0x0004
#define E1000_DTXCTL_VLAN_ADDED 0x0008
#define E1000_DTXCTL_OOS_ENABLE 0x0010
#define E1000_DTXCTL_MDP_EN     0x0020
#define E1000_DTXCTL_SPOOF_INT  0x0040

#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT	(1 << 14)

#define ALL_QUEUES   0xFFFF

/* RX packet buffer size defines */
#define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
u16 igb_rxpbs_adjust_82580(u32 data);
s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data);
s32 igb_set_eee_i350(struct e1000_hw *);
s32 igb_set_eee_i354(struct e1000_hw *);
s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *);
s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw);

#define E1000_I2C_THERMAL_SENSOR_ADDR	0xF8
#define E1000_EMC_INTERNAL_DATA		0x00
#define E1000_EMC_INTERNAL_THERM_LIMIT	0x20
#define E1000_EMC_DIODE1_DATA		0x01
#define E1000_EMC_DIODE1_THERM_LIMIT	0x19
#define E1000_EMC_DIODE2_DATA		0x23
#define E1000_EMC_DIODE2_THERM_LIMIT	0x1A
#define E1000_EMC_DIODE3_DATA		0x2A
#define E1000_EMC_DIODE3_THERM_LIMIT	0x30
#endif
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
4b9ea462	4	Copyright(c) 2007-2013 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _E1000_82575_H_
	29	#define _E1000_82575_H_
	30
2fb02a26	31	extern void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
88a268c1 NN	32	extern void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
88a268c1 NN	33	extern void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
662d7205	34	extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
441fc6fd CW	35	extern s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
	36	u8 dev_addr, u8 *data);
	37	extern s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
	38	u8 dev_addr, u8 data);
662d7205	39
099e1cb7 AD	40	#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) \| \
	41	(ID_LED_DEF1_DEF2 << 8) \| \
	42	(ID_LED_DEF1_DEF2 << 4) \| \
	43	(ID_LED_OFF1_ON2))
	44
d2ba2ed8 AD	45	#define E1000_RAR_ENTRIES_82575 16
	46	#define E1000_RAR_ENTRIES_82576 24
	47	#define E1000_RAR_ENTRIES_82580 24
	48	#define E1000_RAR_ENTRIES_I350 32
bb2ac47b AD	49
	50	#define E1000_SW_SYNCH_MB 0x00000100
	51	#define E1000_STAT_DEV_RST_SET 0x00100000
	52	#define E1000_CTRL_DEV_RST 0x20000000
9d5c8243 AK	53
	54	/* SRRCTL bit definitions */
	55	#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
	56	#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
	57	#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
	58	#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
e1739522	59	#define E1000_SRRCTL_DROP_EN 0x80000000
757b77e2	60	#define E1000_SRRCTL_TIMESTAMP 0x40000000
9d5c8243	61
f96a8a0b	62
9d5c8243	63	#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
e1739522	64	#define E1000_MRQC_ENABLE_VMDQ 0x00000003
9d5c8243	65	#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
f96a8a0b	66	#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
9d5c8243 AK	67	#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
	68	#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
	69
	70	#define E1000_EICR_TX_QUEUE ( \
	71	E1000_EICR_TX_QUEUE0 \| \
	72	E1000_EICR_TX_QUEUE1 \| \
	73	E1000_EICR_TX_QUEUE2 \| \
	74	E1000_EICR_TX_QUEUE3)
	75
	76	#define E1000_EICR_RX_QUEUE ( \
	77	E1000_EICR_RX_QUEUE0 \| \
	78	E1000_EICR_RX_QUEUE1 \| \
	79	E1000_EICR_RX_QUEUE2 \| \
	80	E1000_EICR_RX_QUEUE3)
	81
652fff32	82	/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
c5b9bd5e AD	83	#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
c5b9bd5e AD	84	#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
9d5c8243 AK	85
	86	/* Receive Descriptor - Advanced */
	87	union e1000_adv_rx_desc {
	88	struct {
6d8126f9 AV	89	__le64 pkt_addr; /* Packet buffer address */
6d8126f9 AV	90	__le64 hdr_addr; /* Header buffer address */
9d5c8243 AK	91	} read;
	92	struct {
	93	struct {
	94	struct {
6d8126f9 AV	95	__le16 pkt_info; /* RSS type, Packet type */
	96	__le16 hdr_info; /* Split Header,
	97	* header buffer length */
9d5c8243 AK	98	} lo_dword;
9d5c8243 AK	99	union {
6d8126f9	100	__le32 rss; /* RSS Hash */
9d5c8243	101	struct {
6d8126f9 AV	102	__le16 ip_id; /* IP id */
6d8126f9 AV	103	__le16 csum; /* Packet Checksum */
9d5c8243 AK	104	} csum_ip;
	105	} hi_dword;
	106	} lower;
	107	struct {
6d8126f9 AV	108	__le32 status_error; /* ext status/error */
	109	__le16 length; /* Packet length */
	110	__le16 vlan; /* VLAN tag */
9d5c8243 AK	111	} upper;
	112	} wb; /* writeback */
	113	};
	114
	115	#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
	116	#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
c5b9bd5e	117	#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
757b77e2	118	#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
9d5c8243	119
9d5c8243 AK	120	/* Transmit Descriptor - Advanced */
	121	union e1000_adv_tx_desc {
	122	struct {
6d8126f9 AV	123	__le64 buffer_addr; /* Address of descriptor's data buf */
	124	__le32 cmd_type_len;
	125	__le32 olinfo_status;
9d5c8243 AK	126	} read;
9d5c8243 AK	127	struct {
6d8126f9 AV	128	__le64 rsvd; /* Reserved */
	129	__le32 nxtseq_seed;
	130	__le32 status;
9d5c8243 AK	131	} wb;
	132	};
	133
	134	/* Adv Transmit Descriptor Config Masks */
33af6bcc	135	#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
9d5c8243 AK	136	#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
9d5c8243 AK	137	#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
e032afc8	138	#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
9d5c8243	139	#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
e032afc8	140	#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
9d5c8243 AK	141	#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
	142	#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
	143	#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
	144	#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
	145
	146	/* Context descriptors */
	147	struct e1000_adv_tx_context_desc {
6d8126f9 AV	148	__le32 vlan_macip_lens;
	149	__le32 seqnum_seed;
	150	__le32 type_tucmd_mlhl;
	151	__le32 mss_l4len_idx;
9d5c8243 AK	152	};
	153
	154	#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
	155	#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
	156	#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
b9473560	157	#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
9d5c8243 AK	158	/* IPSec Encrypt Enable for ESP */
	159	#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
	160	#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
	161	/* Adv ctxt IPSec SA IDX mask */
	162	/* Adv ctxt IPSec ESP len mask */
	163
	164	/* Additional Transmit Descriptor Control definitions */
	165	#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
	166	/* Tx Queue Arbitration Priority 0=low, 1=high */
	167
	168	/* Additional Receive Descriptor Control definitions */
	169	#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
	170
	171	/* Direct Cache Access (DCA) definitions */
cbd347ad AD	172	#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
cbd347ad AD	173	#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
9d5c8243	174
fe4506b6 JC	175	#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
	176	#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
	177	#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
	178	#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
6a05004a	179	#define E1000_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
9d5c8243	180
fe4506b6 JC	181	#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
fe4506b6 JC	182	#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
6a05004a	183	#define E1000_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
652fff32	184	#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
6a05004a	185	#define E1000_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
9d5c8243	186
2d064c06 AD	187	/* Additional DCA related definitions, note change in position of CPUID */
	188	#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
	189	#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
	190	#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
	191	#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
fe4506b6	192
c5b9bd5e AD	193	/* ETQF register bit definitions */
	194	#define E1000_ETQF_FILTER_ENABLE (1 << 26)
	195	#define E1000_ETQF_1588 (1 << 30)
	196
	197	/* FTQF register bit definitions */
	198	#define E1000_FTQF_VF_BP 0x00008000
	199	#define E1000_FTQF_1588_TIME_STAMP 0x08000000
	200	#define E1000_FTQF_MASK 0xF0000000
	201	#define E1000_FTQF_MASK_PROTO_BP 0x10000000
	202	#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
	203
70d92f86	204	#define E1000_NVM_APME_82575 0x0400
4ae196df AD	205	#define MAX_NUM_VFS 8
4ae196df AD	206
13800469 GR	207	#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
	208	#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
	209	#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
	210	#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
4ae196df AD	211	#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */
4ae196df AD	212
e1739522 AD	213	/* Easy defines for setting default pool, would normally be left a zero */
	214	#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
	215	#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
	216
	217	/* Other useful VMD_CTL register defines */
	218	#define E1000_VT_CTL_IGNORE_MAC (1 << 28)
	219	#define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29)
	220	#define E1000_VT_CTL_VM_REPL_EN (1 << 30)
	221
	222	/* Per VM Offload register setup */
	223	#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
	224	#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
	225	#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
	226	#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
	227	#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
	228	#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
	229	#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
	230	#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
	231	#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
4ae196df AD	232	#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
	233
	234	#define E1000_VLVF_ARRAY_SIZE 32
	235	#define E1000_VLVF_VLANID_MASK 0x00000FFF
	236	#define E1000_VLVF_POOLSEL_SHIFT 12
	237	#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
	238	#define E1000_VLVF_LVLAN 0x00100000
	239	#define E1000_VLVF_VLANID_ENABLE 0x80000000
	240
8151d294 WM	241	#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
	242	#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
	243
4ae196df AD	244	#define E1000_IOVCTL 0x05BBC
4ae196df AD	245	#define E1000_IOVCTL_REUSE_VFQ 0x00000001
e1739522	246
10d8e907 AD	247	#define E1000_RPLOLR_STRVLAN 0x40000000
	248	#define E1000_RPLOLR_STRCRC 0x80000000
	249
	250	#define E1000_DTXCTL_8023LL 0x0004
	251	#define E1000_DTXCTL_VLAN_ADDED 0x0008
	252	#define E1000_DTXCTL_OOS_ENABLE 0x0010
	253	#define E1000_DTXCTL_MDP_EN 0x0020
	254	#define E1000_DTXCTL_SPOOF_INT 0x0040
	255
2c670b5b CW	256	#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14)
2c670b5b CW	257
e1739522 AD	258	#define ALL_QUEUES 0xFFFF
e1739522 AD	259
d249be54 AD	260	/* RX packet buffer size defines */
d249be54 AD	261	#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
13800469	262	void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
4ae196df AD	263	void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
4ae196df AD	264	void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
bb2ac47b	265	u16 igb_rxpbs_adjust_82580(u32 data);
87371b9d	266	s32 igb_read_emi_reg(struct e1000_hw , u16 addr, u16 data);
09b068d4	267	s32 igb_set_eee_i350(struct e1000_hw *);
ceb5f13b	268	s32 igb_set_eee_i354(struct e1000_hw *);
e428893b CW	269	s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *);
e428893b CW	270	s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw);
e1739522	271
441fc6fd	272	#define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
aca5dae8 CW	273	#define E1000_EMC_INTERNAL_DATA 0x00
	274	#define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
	275	#define E1000_EMC_DIODE1_DATA 0x01
	276	#define E1000_EMC_DIODE1_THERM_LIMIT 0x19
	277	#define E1000_EMC_DIODE2_DATA 0x23
	278	#define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
	279	#define E1000_EMC_DIODE3_DATA 0x2A
	280	#define E1000_EMC_DIODE3_THERM_LIMIT 0x30
9d5c8243	281	#endif