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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
6e861326 | 4 | Copyright(c) 2007-2012 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _E1000_82575_H_ | |
29 | #define _E1000_82575_H_ | |
30 | ||
2fb02a26 | 31 | extern void igb_shutdown_serdes_link_82575(struct e1000_hw *hw); |
88a268c1 NN |
32 | extern void igb_power_up_serdes_link_82575(struct e1000_hw *hw); |
33 | extern void igb_power_down_phy_copper_82575(struct e1000_hw *hw); | |
662d7205 AD |
34 | extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); |
35 | ||
099e1cb7 AD |
36 | #define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ |
37 | (ID_LED_DEF1_DEF2 << 8) | \ | |
38 | (ID_LED_DEF1_DEF2 << 4) | \ | |
39 | (ID_LED_OFF1_ON2)) | |
40 | ||
d2ba2ed8 AD |
41 | #define E1000_RAR_ENTRIES_82575 16 |
42 | #define E1000_RAR_ENTRIES_82576 24 | |
43 | #define E1000_RAR_ENTRIES_82580 24 | |
44 | #define E1000_RAR_ENTRIES_I350 32 | |
bb2ac47b AD |
45 | |
46 | #define E1000_SW_SYNCH_MB 0x00000100 | |
47 | #define E1000_STAT_DEV_RST_SET 0x00100000 | |
48 | #define E1000_CTRL_DEV_RST 0x20000000 | |
9d5c8243 AK |
49 | |
50 | /* SRRCTL bit definitions */ | |
51 | #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ | |
52 | #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ | |
53 | #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 | |
54 | #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 | |
e1739522 | 55 | #define E1000_SRRCTL_DROP_EN 0x80000000 |
757b77e2 | 56 | #define E1000_SRRCTL_TIMESTAMP 0x40000000 |
9d5c8243 | 57 | |
f96a8a0b | 58 | |
9d5c8243 | 59 | #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 |
e1739522 | 60 | #define E1000_MRQC_ENABLE_VMDQ 0x00000003 |
9d5c8243 | 61 | #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 |
f96a8a0b | 62 | #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 |
9d5c8243 AK |
63 | #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 |
64 | #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 | |
65 | ||
66 | #define E1000_EICR_TX_QUEUE ( \ | |
67 | E1000_EICR_TX_QUEUE0 | \ | |
68 | E1000_EICR_TX_QUEUE1 | \ | |
69 | E1000_EICR_TX_QUEUE2 | \ | |
70 | E1000_EICR_TX_QUEUE3) | |
71 | ||
72 | #define E1000_EICR_RX_QUEUE ( \ | |
73 | E1000_EICR_RX_QUEUE0 | \ | |
74 | E1000_EICR_RX_QUEUE1 | \ | |
75 | E1000_EICR_RX_QUEUE2 | \ | |
76 | E1000_EICR_RX_QUEUE3) | |
77 | ||
652fff32 | 78 | /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ |
c5b9bd5e AD |
79 | #define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ |
80 | #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ | |
9d5c8243 AK |
81 | |
82 | /* Receive Descriptor - Advanced */ | |
83 | union e1000_adv_rx_desc { | |
84 | struct { | |
6d8126f9 AV |
85 | __le64 pkt_addr; /* Packet buffer address */ |
86 | __le64 hdr_addr; /* Header buffer address */ | |
9d5c8243 AK |
87 | } read; |
88 | struct { | |
89 | struct { | |
90 | struct { | |
6d8126f9 AV |
91 | __le16 pkt_info; /* RSS type, Packet type */ |
92 | __le16 hdr_info; /* Split Header, | |
93 | * header buffer length */ | |
9d5c8243 AK |
94 | } lo_dword; |
95 | union { | |
6d8126f9 | 96 | __le32 rss; /* RSS Hash */ |
9d5c8243 | 97 | struct { |
6d8126f9 AV |
98 | __le16 ip_id; /* IP id */ |
99 | __le16 csum; /* Packet Checksum */ | |
9d5c8243 AK |
100 | } csum_ip; |
101 | } hi_dword; | |
102 | } lower; | |
103 | struct { | |
6d8126f9 AV |
104 | __le32 status_error; /* ext status/error */ |
105 | __le16 length; /* Packet length */ | |
106 | __le16 vlan; /* VLAN tag */ | |
9d5c8243 AK |
107 | } upper; |
108 | } wb; /* writeback */ | |
109 | }; | |
110 | ||
111 | #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 | |
112 | #define E1000_RXDADV_HDRBUFLEN_SHIFT 5 | |
c5b9bd5e | 113 | #define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */ |
757b77e2 | 114 | #define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */ |
9d5c8243 | 115 | |
9d5c8243 AK |
116 | /* Transmit Descriptor - Advanced */ |
117 | union e1000_adv_tx_desc { | |
118 | struct { | |
6d8126f9 AV |
119 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
120 | __le32 cmd_type_len; | |
121 | __le32 olinfo_status; | |
9d5c8243 AK |
122 | } read; |
123 | struct { | |
6d8126f9 AV |
124 | __le64 rsvd; /* Reserved */ |
125 | __le32 nxtseq_seed; | |
126 | __le32 status; | |
9d5c8243 AK |
127 | } wb; |
128 | }; | |
129 | ||
130 | /* Adv Transmit Descriptor Config Masks */ | |
33af6bcc | 131 | #define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ |
9d5c8243 AK |
132 | #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ |
133 | #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ | |
e032afc8 | 134 | #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ |
9d5c8243 | 135 | #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
e032afc8 | 136 | #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ |
9d5c8243 AK |
137 | #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ |
138 | #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ | |
139 | #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ | |
140 | #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ | |
141 | ||
142 | /* Context descriptors */ | |
143 | struct e1000_adv_tx_context_desc { | |
6d8126f9 AV |
144 | __le32 vlan_macip_lens; |
145 | __le32 seqnum_seed; | |
146 | __le32 type_tucmd_mlhl; | |
147 | __le32 mss_l4len_idx; | |
9d5c8243 AK |
148 | }; |
149 | ||
150 | #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ | |
151 | #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ | |
152 | #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ | |
b9473560 | 153 | #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */ |
9d5c8243 AK |
154 | /* IPSec Encrypt Enable for ESP */ |
155 | #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ | |
156 | #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ | |
157 | /* Adv ctxt IPSec SA IDX mask */ | |
158 | /* Adv ctxt IPSec ESP len mask */ | |
159 | ||
160 | /* Additional Transmit Descriptor Control definitions */ | |
161 | #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ | |
162 | /* Tx Queue Arbitration Priority 0=low, 1=high */ | |
163 | ||
164 | /* Additional Receive Descriptor Control definitions */ | |
165 | #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */ | |
166 | ||
167 | /* Direct Cache Access (DCA) definitions */ | |
cbd347ad AD |
168 | #define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */ |
169 | #define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ | |
9d5c8243 | 170 | |
fe4506b6 JC |
171 | #define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ |
172 | #define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ | |
173 | #define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ | |
174 | #define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ | |
9d5c8243 | 175 | |
fe4506b6 JC |
176 | #define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ |
177 | #define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ | |
652fff32 | 178 | #define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ |
9d5c8243 | 179 | |
2d064c06 AD |
180 | /* Additional DCA related definitions, note change in position of CPUID */ |
181 | #define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */ | |
182 | #define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */ | |
183 | #define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */ | |
184 | #define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */ | |
fe4506b6 | 185 | |
c5b9bd5e AD |
186 | /* ETQF register bit definitions */ |
187 | #define E1000_ETQF_FILTER_ENABLE (1 << 26) | |
188 | #define E1000_ETQF_1588 (1 << 30) | |
189 | ||
190 | /* FTQF register bit definitions */ | |
191 | #define E1000_FTQF_VF_BP 0x00008000 | |
192 | #define E1000_FTQF_1588_TIME_STAMP 0x08000000 | |
193 | #define E1000_FTQF_MASK 0xF0000000 | |
194 | #define E1000_FTQF_MASK_PROTO_BP 0x10000000 | |
195 | #define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 | |
196 | ||
70d92f86 | 197 | #define E1000_NVM_APME_82575 0x0400 |
4ae196df AD |
198 | #define MAX_NUM_VFS 8 |
199 | ||
13800469 GR |
200 | #define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */ |
201 | #define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */ | |
202 | #define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */ | |
203 | #define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8 | |
4ae196df AD |
204 | #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) /* global VF LB enable */ |
205 | ||
e1739522 AD |
206 | /* Easy defines for setting default pool, would normally be left a zero */ |
207 | #define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7 | |
208 | #define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) | |
209 | ||
210 | /* Other useful VMD_CTL register defines */ | |
211 | #define E1000_VT_CTL_IGNORE_MAC (1 << 28) | |
212 | #define E1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) | |
213 | #define E1000_VT_CTL_VM_REPL_EN (1 << 30) | |
214 | ||
215 | /* Per VM Offload register setup */ | |
216 | #define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */ | |
217 | #define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */ | |
218 | #define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */ | |
219 | #define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */ | |
220 | #define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */ | |
221 | #define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */ | |
222 | #define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */ | |
223 | #define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */ | |
224 | #define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */ | |
4ae196df AD |
225 | #define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */ |
226 | ||
227 | #define E1000_VLVF_ARRAY_SIZE 32 | |
228 | #define E1000_VLVF_VLANID_MASK 0x00000FFF | |
229 | #define E1000_VLVF_POOLSEL_SHIFT 12 | |
230 | #define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) | |
231 | #define E1000_VLVF_LVLAN 0x00100000 | |
232 | #define E1000_VLVF_VLANID_ENABLE 0x80000000 | |
233 | ||
8151d294 WM |
234 | #define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ |
235 | #define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ | |
236 | ||
4ae196df AD |
237 | #define E1000_IOVCTL 0x05BBC |
238 | #define E1000_IOVCTL_REUSE_VFQ 0x00000001 | |
e1739522 | 239 | |
10d8e907 AD |
240 | #define E1000_RPLOLR_STRVLAN 0x40000000 |
241 | #define E1000_RPLOLR_STRCRC 0x80000000 | |
242 | ||
243 | #define E1000_DTXCTL_8023LL 0x0004 | |
244 | #define E1000_DTXCTL_VLAN_ADDED 0x0008 | |
245 | #define E1000_DTXCTL_OOS_ENABLE 0x0010 | |
246 | #define E1000_DTXCTL_MDP_EN 0x0020 | |
247 | #define E1000_DTXCTL_SPOOF_INT 0x0040 | |
248 | ||
2c670b5b CW |
249 | #define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT (1 << 14) |
250 | ||
e1739522 AD |
251 | #define ALL_QUEUES 0xFFFF |
252 | ||
d249be54 AD |
253 | /* RX packet buffer size defines */ |
254 | #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F | |
13800469 | 255 | void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int); |
4ae196df AD |
256 | void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool); |
257 | void igb_vmdq_set_replication_pf(struct e1000_hw *, bool); | |
bb2ac47b | 258 | u16 igb_rxpbs_adjust_82580(u32 data); |
09b068d4 | 259 | s32 igb_set_eee_i350(struct e1000_hw *); |
e1739522 | 260 | |
9d5c8243 | 261 | #endif |