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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
4b9ea462 | 4 | Copyright(c) 2007-2013 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _E1000_DEFINES_H_ | |
29 | #define _E1000_DEFINES_H_ | |
30 | ||
31 | /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ | |
32 | #define REQ_TX_DESCRIPTOR_MULTIPLE 8 | |
33 | #define REQ_RX_DESCRIPTOR_MULTIPLE 8 | |
34 | ||
35 | /* Definitions for power management and wakeup registers */ | |
36 | /* Wake Up Control */ | |
37 | #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ | |
38 | ||
39 | /* Wake Up Filter Control */ | |
40 | #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ | |
41 | #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ | |
42 | #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ | |
43 | #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ | |
44 | #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ | |
9d5c8243 AK |
45 | |
46 | /* Extended Device Control */ | |
2fb02a26 | 47 | #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ |
4ae196df AD |
48 | /* Physical Func Reset Done Indication */ |
49 | #define E1000_CTRL_EXT_PFRSTD 0x00004000 | |
9d5c8243 AK |
50 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
51 | #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 | |
bb2ac47b | 52 | #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 |
9d5c8243 | 53 | #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 |
7ef5ed1c | 54 | #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 |
9d5c8243 AK |
55 | #define E1000_CTRL_EXT_EIAME 0x01000000 |
56 | #define E1000_CTRL_EXT_IRCA 0x00000001 | |
57 | /* Interrupt delay cancellation */ | |
58 | /* Driver loaded bit for FW */ | |
59 | #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 | |
60 | /* Interrupt acknowledge Auto-mask */ | |
61 | /* Clear Interrupt timers after IMS clear */ | |
62 | /* packet buffer parity error detection enabled */ | |
63 | /* descriptor FIFO parity error detection enable */ | |
641ac5c0 AA |
64 | #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ |
65 | #define E1000_I2CCMD_REG_ADDR_SHIFT 16 | |
66 | #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 | |
67 | #define E1000_I2CCMD_OPCODE_READ 0x08000000 | |
68 | #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 | |
69 | #define E1000_I2CCMD_READY 0x20000000 | |
70 | #define E1000_I2CCMD_ERROR 0x80000000 | |
71 | #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) | |
72 | #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) | |
73 | #define E1000_MAX_SGMII_PHY_REG_ADDR 255 | |
74 | #define E1000_I2CCMD_PHY_TIMEOUT 200 | |
75 | #define E1000_IVAR_VALID 0x80 | |
76 | #define E1000_GPIE_NSICR 0x00000001 | |
77 | #define E1000_GPIE_MSIX_MODE 0x00000010 | |
78 | #define E1000_GPIE_EIAME 0x40000000 | |
79 | #define E1000_GPIE_PBA 0x80000000 | |
9d5c8243 | 80 | |
652fff32 | 81 | /* Receive Descriptor bit definitions */ |
9d5c8243 AK |
82 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
83 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | |
84 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | |
85 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | |
652fff32 | 86 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
9d5c8243 | 87 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
33af6bcc | 88 | #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ |
9d5c8243 | 89 | |
8be10e91 | 90 | #define E1000_RXDEXT_STATERR_LB 0x00040000 |
9d5c8243 AK |
91 | #define E1000_RXDEXT_STATERR_CE 0x01000000 |
92 | #define E1000_RXDEXT_STATERR_SE 0x02000000 | |
93 | #define E1000_RXDEXT_STATERR_SEQ 0x04000000 | |
94 | #define E1000_RXDEXT_STATERR_CXE 0x10000000 | |
95 | #define E1000_RXDEXT_STATERR_TCPE 0x20000000 | |
96 | #define E1000_RXDEXT_STATERR_IPE 0x40000000 | |
97 | #define E1000_RXDEXT_STATERR_RXE 0x80000000 | |
98 | ||
9d5c8243 AK |
99 | /* Same mask, but for extended and packet split descriptors */ |
100 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ | |
101 | E1000_RXDEXT_STATERR_CE | \ | |
102 | E1000_RXDEXT_STATERR_SE | \ | |
103 | E1000_RXDEXT_STATERR_SEQ | \ | |
104 | E1000_RXDEXT_STATERR_CXE | \ | |
105 | E1000_RXDEXT_STATERR_RXE) | |
106 | ||
107 | #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 | |
108 | #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 | |
109 | #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 | |
110 | #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 | |
111 | #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 | |
112 | ||
113 | ||
114 | /* Management Control */ | |
115 | #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ | |
116 | #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ | |
0a915b95 | 117 | #define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */ |
9d5c8243 AK |
118 | /* Enable Neighbor Discovery Filtering */ |
119 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | |
120 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | |
121 | /* Enable MAC address filtering */ | |
122 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 | |
9d5c8243 AK |
123 | |
124 | /* Receive Control */ | |
125 | #define E1000_RCTL_EN 0x00000002 /* enable */ | |
126 | #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ | |
127 | #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ | |
128 | #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ | |
129 | #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ | |
9d5c8243 AK |
130 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ |
131 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | |
132 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ | |
133 | #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ | |
134 | #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ | |
9d5c8243 AK |
135 | #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ |
136 | #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ | |
9d5c8243 AK |
137 | #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ |
138 | #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ | |
89eaefb6 BG |
139 | #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ |
140 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ | |
9d5c8243 AK |
141 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ |
142 | ||
b980ac18 | 143 | /* Use byte values for the following shift parameters |
9d5c8243 AK |
144 | * Usage: |
145 | * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & | |
146 | * E1000_PSRCTL_BSIZE0_MASK) | | |
147 | * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & | |
148 | * E1000_PSRCTL_BSIZE1_MASK) | | |
149 | * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & | |
150 | * E1000_PSRCTL_BSIZE2_MASK) | | |
151 | * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; | |
152 | * E1000_PSRCTL_BSIZE3_MASK)) | |
153 | * where value0 = [128..16256], default=256 | |
154 | * value1 = [1024..64512], default=4096 | |
155 | * value2 = [0..64512], default=4096 | |
156 | * value3 = [0..64512], default=0 | |
157 | */ | |
158 | ||
159 | #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F | |
160 | #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 | |
161 | #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 | |
162 | #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 | |
163 | ||
164 | #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ | |
165 | #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ | |
166 | #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ | |
167 | #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ | |
168 | ||
169 | /* SWFW_SYNC Definitions */ | |
170 | #define E1000_SWFW_EEP_SM 0x1 | |
171 | #define E1000_SWFW_PHY0_SM 0x2 | |
172 | #define E1000_SWFW_PHY1_SM 0x4 | |
ede3ef0d NN |
173 | #define E1000_SWFW_PHY2_SM 0x20 |
174 | #define E1000_SWFW_PHY3_SM 0x40 | |
9d5c8243 AK |
175 | |
176 | /* FACTPS Definitions */ | |
177 | /* Device Control */ | |
178 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | |
179 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | |
2d064c06 | 180 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ |
9d5c8243 AK |
181 | #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ |
182 | #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ | |
183 | #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ | |
184 | #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ | |
185 | #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ | |
186 | #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ | |
187 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | |
188 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | |
189 | /* Defined polarity of Dock/Undock indication in SDP[0] */ | |
190 | /* Reset both PHY ports, through PHYRST_N pin */ | |
191 | /* enable link status from external LINK_0 and LINK_1 pins */ | |
192 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | |
193 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | |
9d5c8243 | 194 | #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ |
9d5c8243 AK |
195 | #define E1000_CTRL_RST 0x04000000 /* Global reset */ |
196 | #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ | |
197 | #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ | |
198 | #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ | |
199 | #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ | |
200 | /* Initiate an interrupt to manageability engine */ | |
201 | #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ | |
202 | ||
203 | /* Bit definitions for the Management Data IO (MDIO) and Management Data | |
204 | * Clock (MDC) pins in the Device Control Register. | |
205 | */ | |
206 | ||
207 | #define E1000_CONNSW_ENRGSRC 0x4 | |
2d064c06 | 208 | #define E1000_PCS_CFG_PCS_EN 8 |
9d5c8243 AK |
209 | #define E1000_PCS_LCTL_FLV_LINK_UP 1 |
210 | #define E1000_PCS_LCTL_FSV_100 2 | |
211 | #define E1000_PCS_LCTL_FSV_1000 4 | |
212 | #define E1000_PCS_LCTL_FDV_FULL 8 | |
213 | #define E1000_PCS_LCTL_FSD 0x10 | |
214 | #define E1000_PCS_LCTL_FORCE_LINK 0x20 | |
726c09e7 | 215 | #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 |
9d5c8243 AK |
216 | #define E1000_PCS_LCTL_AN_ENABLE 0x10000 |
217 | #define E1000_PCS_LCTL_AN_RESTART 0x20000 | |
218 | #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 | |
2d064c06 | 219 | #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 |
9d5c8243 AK |
220 | |
221 | #define E1000_PCS_LSTS_LINK_OK 1 | |
222 | #define E1000_PCS_LSTS_SPEED_100 2 | |
223 | #define E1000_PCS_LSTS_SPEED_1000 4 | |
224 | #define E1000_PCS_LSTS_DUPLEX_FULL 8 | |
225 | #define E1000_PCS_LSTS_SYNK_OK 0x10 | |
226 | ||
227 | /* Device Status */ | |
228 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ | |
229 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ | |
230 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ | |
231 | #define E1000_STATUS_FUNC_SHIFT 2 | |
232 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ | |
233 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ | |
234 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ | |
235 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ | |
236 | /* Change in Dock/Undock state. Clear on write '0'. */ | |
237 | /* Status of Master requests. */ | |
238 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 | |
239 | /* BMC external code execution disabled */ | |
240 | ||
ceb5f13b CW |
241 | #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ |
242 | #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ | |
9d5c8243 AK |
243 | /* Constants used to intrepret the masked PCI-X bus speed. */ |
244 | ||
245 | #define SPEED_10 10 | |
246 | #define SPEED_100 100 | |
247 | #define SPEED_1000 1000 | |
ceb5f13b | 248 | #define SPEED_2500 2500 |
9d5c8243 AK |
249 | #define HALF_DUPLEX 1 |
250 | #define FULL_DUPLEX 2 | |
251 | ||
252 | ||
253 | #define ADVERTISE_10_HALF 0x0001 | |
254 | #define ADVERTISE_10_FULL 0x0002 | |
255 | #define ADVERTISE_100_HALF 0x0004 | |
256 | #define ADVERTISE_100_FULL 0x0008 | |
257 | #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ | |
258 | #define ADVERTISE_1000_FULL 0x0020 | |
259 | ||
260 | /* 1000/H is not supported, nor spec-compliant. */ | |
261 | #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ | |
262 | ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ | |
263 | ADVERTISE_1000_FULL) | |
264 | #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ | |
265 | ADVERTISE_100_HALF | ADVERTISE_100_FULL) | |
266 | #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) | |
267 | #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) | |
268 | #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ | |
269 | ADVERTISE_1000_FULL) | |
270 | #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) | |
271 | ||
272 | #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX | |
273 | ||
274 | /* LED Control */ | |
cf7ed221 AA |
275 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 |
276 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 | |
277 | #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F | |
278 | #define E1000_LEDCTL_LED0_IVRT 0x00000040 | |
9d5c8243 AK |
279 | |
280 | #define E1000_LEDCTL_MODE_LED_ON 0xE | |
281 | #define E1000_LEDCTL_MODE_LED_OFF 0xF | |
282 | ||
283 | /* Transmit Descriptor bit definitions */ | |
284 | #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ | |
285 | #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ | |
286 | #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ | |
287 | #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ | |
288 | #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ | |
289 | #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ | |
0e014cb1 | 290 | #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ |
9d5c8243 AK |
291 | /* Extended desc bits for Linksec and timesync */ |
292 | ||
293 | /* Transmit Control */ | |
294 | #define E1000_TCTL_EN 0x00000002 /* enable tx */ | |
295 | #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ | |
296 | #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ | |
297 | #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ | |
298 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ | |
299 | ||
831ec0b4 CW |
300 | /* DMA Coalescing register fields */ |
301 | #define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing | |
302 | * Watchdog Timer */ | |
303 | #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive | |
304 | * Threshold */ | |
305 | #define E1000_DMACR_DMACTHR_SHIFT 16 | |
306 | #define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe | |
307 | * transactions */ | |
308 | #define E1000_DMACR_DMAC_LX_SHIFT 28 | |
309 | #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ | |
0c02dd98 MV |
310 | /* DMA Coalescing BMC-to-OS Watchdog Enable */ |
311 | #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 | |
831ec0b4 CW |
312 | |
313 | #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit | |
314 | * Threshold */ | |
315 | ||
316 | #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ | |
317 | ||
318 | #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate | |
319 | * Threshold */ | |
320 | #define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in | |
321 | * current window */ | |
322 | ||
323 | #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic | |
324 | * Current Cnt */ | |
325 | ||
326 | #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold | |
327 | * High val */ | |
328 | #define E1000_FCRTC_RTH_COAL_SHIFT 4 | |
329 | #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */ | |
9d5c8243 | 330 | |
e57b8bdb MV |
331 | /* Timestamp in Rx buffer */ |
332 | #define E1000_RXPBS_CFG_TS_EN 0x80000000 | |
333 | ||
9d5c8243 AK |
334 | /* SerDes Control */ |
335 | #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 | |
336 | ||
337 | /* Receive Checksum Control */ | |
2844f797 | 338 | #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ |
9d5c8243 | 339 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ |
b9473560 | 340 | #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ |
9d5c8243 AK |
341 | #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ |
342 | ||
343 | /* Header split receive */ | |
662d7205 | 344 | #define E1000_RFCTL_LEF 0x00040000 |
9d5c8243 AK |
345 | |
346 | /* Collision related configuration parameters */ | |
347 | #define E1000_COLLISION_THRESHOLD 15 | |
348 | #define E1000_CT_SHIFT 4 | |
349 | #define E1000_COLLISION_DISTANCE 63 | |
350 | #define E1000_COLD_SHIFT 12 | |
351 | ||
352 | /* Ethertype field values */ | |
353 | #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ | |
354 | ||
355 | #define MAX_JUMBO_FRAME_SIZE 0x3F00 | |
356 | ||
9d5c8243 | 357 | /* PBA constants */ |
9d5c8243 | 358 | #define E1000_PBA_34K 0x0022 |
2d064c06 | 359 | #define E1000_PBA_64K 0x0040 /* 64KB */ |
9d5c8243 | 360 | |
9d5c8243 AK |
361 | /* SW Semaphore Register */ |
362 | #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | |
363 | #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | |
364 | ||
365 | /* Interrupt Cause Read */ | |
366 | #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ | |
9d5c8243 AK |
367 | #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ |
368 | #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ | |
369 | #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ | |
9d5c8243 | 370 | #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ |
4ae196df | 371 | #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ |
1f6e8178 | 372 | #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ |
55cac248 | 373 | #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ |
9d5c8243 AK |
374 | /* If this bit asserted, the driver should claim the interrupt */ |
375 | #define E1000_ICR_INT_ASSERTED 0x80000000 | |
9d5c8243 | 376 | /* LAN connected device generates an interrupt */ |
dda0e083 | 377 | #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ |
9d5c8243 AK |
378 | |
379 | /* Extended Interrupt Cause Read */ | |
380 | #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ | |
381 | #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ | |
382 | #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ | |
383 | #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ | |
384 | #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ | |
385 | #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ | |
386 | #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ | |
387 | #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ | |
9d5c8243 AK |
388 | #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ |
389 | /* TCP Timer */ | |
390 | ||
b980ac18 | 391 | /* This defines the bits that are set in the Interrupt Mask |
9d5c8243 AK |
392 | * Set/Read Register. Each bit is documented below: |
393 | * o RXT0 = Receiver Timer Interrupt (ring 0) | |
394 | * o TXDW = Transmit Descriptor Written Back | |
395 | * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) | |
396 | * o RXSEQ = Receive Sequence Error | |
397 | * o LSC = Link Status Change | |
398 | */ | |
399 | #define IMS_ENABLE_MASK ( \ | |
400 | E1000_IMS_RXT0 | \ | |
401 | E1000_IMS_TXDW | \ | |
402 | E1000_IMS_RXDMT0 | \ | |
403 | E1000_IMS_RXSEQ | \ | |
dda0e083 AD |
404 | E1000_IMS_LSC | \ |
405 | E1000_IMS_DOUTSYNC) | |
9d5c8243 AK |
406 | |
407 | /* Interrupt Mask Set */ | |
408 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | |
409 | #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ | |
4ae196df | 410 | #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ |
1f6e8178 | 411 | #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ |
9d5c8243 AK |
412 | #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ |
413 | #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | |
414 | #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ | |
55cac248 | 415 | #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ |
dda0e083 | 416 | #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ |
9d5c8243 AK |
417 | |
418 | /* Extended Interrupt Mask Set */ | |
9d5c8243 AK |
419 | #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ |
420 | ||
421 | /* Interrupt Cause Set */ | |
422 | #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ | |
423 | #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ | |
55cac248 | 424 | #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ |
9d5c8243 AK |
425 | |
426 | /* Extended Interrupt Cause Set */ | |
0ba82994 AD |
427 | /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ |
428 | #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ | |
429 | ||
9d5c8243 AK |
430 | |
431 | /* Transmit Descriptor Control */ | |
432 | /* Enable the counting of descriptors still to be processed. */ | |
433 | ||
434 | /* Flow Control Constants */ | |
435 | #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 | |
436 | #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 | |
437 | #define FLOW_CONTROL_TYPE 0x8808 | |
438 | ||
daf56e40 CW |
439 | /* Transmit Config Word */ |
440 | #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ | |
441 | #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ | |
442 | ||
9d5c8243 AK |
443 | /* 802.1q VLAN Packet Size */ |
444 | #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ | |
445 | #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ | |
446 | ||
447 | /* Receive Address */ | |
b980ac18 | 448 | /* Number of high/low register pairs in the RAR. The RAR (Receive Address |
9d5c8243 AK |
449 | * Registers) holds the directed and multicast addresses that we monitor. |
450 | * Technically, we have 16 spots. However, we reserve one of these spots | |
451 | * (RAR[15]) for our directed address used by controllers with | |
452 | * manageability enabled, allowing us room for 15 multicast addresses. | |
453 | */ | |
454 | #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ | |
40a70b38 AD |
455 | #define E1000_RAL_MAC_ADDR_LEN 4 |
456 | #define E1000_RAH_MAC_ADDR_LEN 2 | |
e1739522 AD |
457 | #define E1000_RAH_POOL_MASK 0x03FC0000 |
458 | #define E1000_RAH_POOL_1 0x00040000 | |
9d5c8243 AK |
459 | |
460 | /* Error Codes */ | |
2c670b5b | 461 | #define E1000_SUCCESS 0 |
9d5c8243 AK |
462 | #define E1000_ERR_NVM 1 |
463 | #define E1000_ERR_PHY 2 | |
464 | #define E1000_ERR_CONFIG 3 | |
465 | #define E1000_ERR_PARAM 4 | |
466 | #define E1000_ERR_MAC_INIT 5 | |
467 | #define E1000_ERR_RESET 9 | |
468 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 | |
9d5c8243 AK |
469 | #define E1000_BLK_PHY_RESET 12 |
470 | #define E1000_ERR_SWFW_SYNC 13 | |
471 | #define E1000_NOT_IMPLEMENTED 14 | |
4ae196df | 472 | #define E1000_ERR_MBX 15 |
9835fd73 CW |
473 | #define E1000_ERR_INVALID_ARGUMENT 16 |
474 | #define E1000_ERR_NO_SPACE 17 | |
475 | #define E1000_ERR_NVM_PBA_SECTION 18 | |
f96a8a0b | 476 | #define E1000_ERR_INVM_VALUE_NOT_FOUND 19 |
441fc6fd | 477 | #define E1000_ERR_I2C 20 |
9d5c8243 AK |
478 | |
479 | /* Loop limit on how long we wait for auto-negotiation to complete */ | |
480 | #define COPPER_LINK_UP_LIMIT 10 | |
481 | #define PHY_AUTO_NEG_LIMIT 45 | |
482 | #define PHY_FORCE_LIMIT 20 | |
483 | /* Number of 100 microseconds we wait for PCI Express master disable */ | |
484 | #define MASTER_DISABLE_TIMEOUT 800 | |
485 | /* Number of milliseconds we wait for PHY configuration done after MAC reset */ | |
486 | #define PHY_CFG_TIMEOUT 100 | |
487 | /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ | |
488 | /* Number of milliseconds for NVM auto read done after MAC reset. */ | |
489 | #define AUTO_READ_DONE_TIMEOUT 10 | |
490 | ||
491 | /* Flow Control */ | |
492 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ | |
493 | ||
c5b9bd5e AD |
494 | #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ |
495 | #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ | |
496 | ||
497 | #define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ | |
498 | #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ | |
499 | #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 | |
500 | #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 | |
501 | #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 | |
502 | #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 | |
503 | #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A | |
504 | #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ | |
505 | ||
506 | #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF | |
507 | #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 | |
508 | #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 | |
509 | #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 | |
510 | #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 | |
511 | #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 | |
512 | ||
513 | #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 | |
514 | #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 | |
515 | #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 | |
516 | #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 | |
517 | #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 | |
518 | #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 | |
519 | #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 | |
520 | #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 | |
521 | #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 | |
522 | #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 | |
523 | #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 | |
524 | ||
525 | #define E1000_TIMINCA_16NS_SHIFT 24 | |
526 | ||
1f6e8178 MV |
527 | #define E1000_TSICR_TXTS 0x00000002 |
528 | #define E1000_TSIM_TXTS 0x00000002 | |
529 | ||
4085f746 NN |
530 | #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ |
531 | #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ | |
532 | #define E1000_MDICNFG_PHY_MASK 0x03E00000 | |
533 | #define E1000_MDICNFG_PHY_SHIFT 21 | |
534 | ||
009bc06e AD |
535 | /* PCI Express Control */ |
536 | #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 | |
537 | #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 | |
538 | #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 | |
539 | #define E1000_GCR_CAP_VER2 0x00040000 | |
540 | ||
a14bc2bb RH |
541 | /* mPHY Address Control and Data Registers */ |
542 | #define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */ | |
543 | #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 | |
544 | #define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */ | |
545 | ||
546 | /* mPHY PCS CLK Register */ | |
547 | #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */ | |
548 | /* mPHY Near End Digital Loopback Override Bit */ | |
549 | #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 | |
550 | ||
daf56e40 CW |
551 | #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 |
552 | #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 | |
553 | ||
9d5c8243 AK |
554 | /* PHY Control Register */ |
555 | #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ | |
556 | #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ | |
88a268c1 | 557 | #define MII_CR_POWER_DOWN 0x0800 /* Power down */ |
9d5c8243 AK |
558 | #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ |
559 | #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ | |
560 | #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ | |
561 | #define MII_CR_SPEED_1000 0x0040 | |
562 | #define MII_CR_SPEED_100 0x2000 | |
563 | #define MII_CR_SPEED_10 0x0000 | |
564 | ||
565 | /* PHY Status Register */ | |
566 | #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ | |
567 | #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ | |
568 | ||
569 | /* Autoneg Advertisement Register */ | |
570 | #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ | |
571 | #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ | |
572 | #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ | |
573 | #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ | |
574 | #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ | |
575 | #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ | |
576 | ||
577 | /* Link Partner Ability Register (Base Page) */ | |
578 | #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ | |
579 | #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ | |
580 | ||
581 | /* Autoneg Expansion Register */ | |
582 | ||
583 | /* 1000BASE-T Control Register */ | |
584 | #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ | |
585 | #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ | |
9d5c8243 AK |
586 | #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ |
587 | /* 0=Configure PHY as Slave */ | |
588 | #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ | |
589 | /* 0=Automatic Master/Slave config */ | |
590 | ||
591 | /* 1000BASE-T Status Register */ | |
592 | #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ | |
593 | #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ | |
594 | ||
595 | ||
596 | /* PHY 1000 MII Register/Bit Definitions */ | |
597 | /* PHY Registers defined by IEEE */ | |
598 | #define PHY_CONTROL 0x00 /* Control Register */ | |
652fff32 | 599 | #define PHY_STATUS 0x01 /* Status Register */ |
9d5c8243 AK |
600 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ |
601 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | |
602 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | |
603 | #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ | |
604 | #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ | |
605 | #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ | |
606 | ||
607 | /* NVM Control */ | |
608 | #define E1000_EECD_SK 0x00000001 /* NVM Clock */ | |
609 | #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ | |
610 | #define E1000_EECD_DI 0x00000004 /* NVM Data In */ | |
611 | #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ | |
612 | #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ | |
613 | #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ | |
614 | #define E1000_EECD_PRES 0x00000100 /* NVM Present */ | |
615 | /* NVM Addressing bits based on type 0=small, 1=large */ | |
616 | #define E1000_EECD_ADDR_BITS 0x00000400 | |
617 | #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ | |
618 | #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ | |
619 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ | |
620 | #define E1000_EECD_SIZE_EX_SHIFT 11 | |
f96a8a0b CW |
621 | #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ |
622 | #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ | |
623 | #define E1000_FLUDONE_ATTEMPTS 20000 | |
624 | #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ | |
625 | #define E1000_I210_FIFO_SEL_RX 0x00 | |
626 | #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) | |
627 | #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) | |
628 | #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 | |
629 | #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 | |
630 | #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ | |
631 | #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ | |
632 | #define E1000_FLUDONE_ATTEMPTS 20000 | |
633 | #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ | |
634 | #define E1000_I210_FIFO_SEL_RX 0x00 | |
635 | #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) | |
636 | #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) | |
637 | #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 | |
638 | #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 | |
639 | ||
9d5c8243 AK |
640 | |
641 | /* Offset to data in NVM read/write registers */ | |
642 | #define E1000_NVM_RW_REG_DATA 16 | |
643 | #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ | |
644 | #define E1000_NVM_RW_REG_START 1 /* Start operation */ | |
645 | #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | |
646 | #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ | |
647 | ||
648 | /* NVM Word Offsets */ | |
2c670b5b CW |
649 | #define NVM_COMPAT 0x0003 |
650 | #define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */ | |
0b1a6f2e | 651 | #define NVM_VERSION 0x0005 |
9d5c8243 | 652 | #define NVM_INIT_CONTROL2_REG 0x000F |
a2cf8b6c | 653 | #define NVM_INIT_CONTROL3_PORT_B 0x0014 |
9d5c8243 AK |
654 | #define NVM_INIT_CONTROL3_PORT_A 0x0024 |
655 | #define NVM_ALT_MAC_ADDR_PTR 0x0037 | |
656 | #define NVM_CHECKSUM_REG 0x003F | |
4322e561 CW |
657 | #define NVM_COMPATIBILITY_REG_3 0x0003 |
658 | #define NVM_COMPATIBILITY_BIT_MASK 0x8000 | |
f96a8a0b CW |
659 | #define NVM_MAC_ADDR 0x0000 |
660 | #define NVM_SUB_DEV_ID 0x000B | |
661 | #define NVM_SUB_VEN_ID 0x000C | |
662 | #define NVM_DEV_ID 0x000D | |
663 | #define NVM_VEN_ID 0x000E | |
664 | #define NVM_INIT_CTRL_2 0x000F | |
665 | #define NVM_INIT_CTRL_4 0x0013 | |
666 | #define NVM_LED_1_CFG 0x001C | |
667 | #define NVM_LED_0_2_CFG 0x001F | |
668 | ||
0b1a6f2e CW |
669 | /* NVM version defines */ |
670 | #define NVM_ETRACK_WORD 0x0042 | |
671 | #define NVM_COMB_VER_OFF 0x0083 | |
672 | #define NVM_COMB_VER_PTR 0x003d | |
673 | #define NVM_MAJOR_MASK 0xF000 | |
674 | #define NVM_MINOR_MASK 0x0FF0 | |
675 | #define NVM_BUILD_MASK 0x000F | |
676 | #define NVM_COMB_VER_MASK 0x00FF | |
677 | #define NVM_MAJOR_SHIFT 12 | |
678 | #define NVM_MINOR_SHIFT 4 | |
679 | #define NVM_COMB_VER_SHFT 8 | |
680 | #define NVM_VER_INVALID 0xFFFF | |
681 | #define NVM_ETRACK_SHIFT 16 | |
aca5dae8 CW |
682 | #define NVM_ETS_CFG 0x003E |
683 | #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0 | |
684 | #define NVM_ETS_LTHRES_DELTA_SHIFT 6 | |
685 | #define NVM_ETS_TYPE_MASK 0x0038 | |
686 | #define NVM_ETS_TYPE_SHIFT 3 | |
687 | #define NVM_ETS_TYPE_EMC 0x000 | |
688 | #define NVM_ETS_NUM_SENSORS_MASK 0x0007 | |
689 | #define NVM_ETS_DATA_LOC_MASK 0x3C00 | |
690 | #define NVM_ETS_DATA_LOC_SHIFT 10 | |
691 | #define NVM_ETS_DATA_INDEX_MASK 0x0300 | |
692 | #define NVM_ETS_DATA_INDEX_SHIFT 8 | |
693 | #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF | |
9d5c8243 | 694 | |
bb2ac47b AD |
695 | #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ |
696 | #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ | |
697 | #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ | |
698 | #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ | |
699 | ||
700 | #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) | |
9d5c8243 | 701 | |
08451e25 NN |
702 | /* Mask bits for fields in Word 0x24 of the NVM */ |
703 | #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ | |
704 | #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ | |
705 | ||
9d5c8243 AK |
706 | /* Mask bits for fields in Word 0x0f of the NVM */ |
707 | #define NVM_WORD0F_PAUSE_MASK 0x3000 | |
708 | #define NVM_WORD0F_ASM_DIR 0x2000 | |
709 | ||
710 | /* Mask bits for fields in Word 0x1a of the NVM */ | |
711 | ||
9835fd73 CW |
712 | /* length of string needed to store part num */ |
713 | #define E1000_PBANUM_LENGTH 11 | |
714 | ||
9d5c8243 AK |
715 | /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ |
716 | #define NVM_SUM 0xBABA | |
717 | ||
718 | #define NVM_PBA_OFFSET_0 8 | |
719 | #define NVM_PBA_OFFSET_1 9 | |
f96a8a0b | 720 | #define NVM_RESERVED_WORD 0xFFFF |
9835fd73 | 721 | #define NVM_PBA_PTR_GUARD 0xFAFA |
9d5c8243 AK |
722 | #define NVM_WORD_SIZE_BASE_SHIFT 6 |
723 | ||
724 | /* NVM Commands - Microwire */ | |
725 | ||
726 | /* NVM Commands - SPI */ | |
727 | #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ | |
728 | #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ | |
4322e561 | 729 | #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ |
9d5c8243 AK |
730 | #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ |
731 | #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ | |
732 | #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ | |
733 | ||
734 | /* SPI NVM Status Register */ | |
735 | #define NVM_STATUS_RDY_SPI 0x01 | |
736 | ||
737 | /* Word definitions for ID LED Settings */ | |
738 | #define ID_LED_RESERVED_0000 0x0000 | |
739 | #define ID_LED_RESERVED_FFFF 0xFFFF | |
740 | #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ | |
741 | (ID_LED_OFF1_OFF2 << 8) | \ | |
742 | (ID_LED_DEF1_DEF2 << 4) | \ | |
743 | (ID_LED_DEF1_DEF2)) | |
744 | #define ID_LED_DEF1_DEF2 0x1 | |
745 | #define ID_LED_DEF1_ON2 0x2 | |
746 | #define ID_LED_DEF1_OFF2 0x3 | |
747 | #define ID_LED_ON1_DEF2 0x4 | |
748 | #define ID_LED_ON1_ON2 0x5 | |
749 | #define ID_LED_ON1_OFF2 0x6 | |
750 | #define ID_LED_OFF1_DEF2 0x7 | |
751 | #define ID_LED_OFF1_ON2 0x8 | |
752 | #define ID_LED_OFF1_OFF2 0x9 | |
753 | ||
754 | #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF | |
755 | #define IGP_ACTIVITY_LED_ENABLE 0x0300 | |
756 | #define IGP_LED3_MODE 0x07000000 | |
757 | ||
758 | /* PCI/PCI-X/PCI-EX Config space */ | |
009bc06e | 759 | #define PCIE_DEVICE_CONTROL2 0x28 |
009bc06e | 760 | #define PCIE_DEVICE_CONTROL2_16ms 0x0005 |
9d5c8243 AK |
761 | |
762 | #define PHY_REVISION_MASK 0xFFFFFFF0 | |
763 | #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ | |
764 | #define MAX_PHY_MULTI_PAGE_REG 0xF | |
765 | ||
766 | /* Bit definitions for valid PHY IDs. */ | |
b980ac18 | 767 | /* I = Integrated |
9d5c8243 AK |
768 | * E = External |
769 | */ | |
770 | #define M88E1111_I_PHY_ID 0x01410CC0 | |
308fb39a JG |
771 | #define M88E1112_E_PHY_ID 0x01410C90 |
772 | #define I347AT4_E_PHY_ID 0x01410DC0 | |
9d5c8243 | 773 | #define IGP03E1000_E_PHY_ID 0x02A80390 |
bb2ac47b | 774 | #define I82580_I_PHY_ID 0x015403A0 |
d2ba2ed8 | 775 | #define I350_I_PHY_ID 0x015403B0 |
9d5c8243 | 776 | #define M88_VENDOR 0x0141 |
f96a8a0b | 777 | #define I210_I_PHY_ID 0x01410C00 |
ceb5f13b | 778 | #define M88E1545_E_PHY_ID 0x01410EA0 |
9d5c8243 AK |
779 | |
780 | /* M88E1000 Specific Registers */ | |
781 | #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ | |
782 | #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ | |
783 | #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ | |
784 | ||
785 | #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ | |
786 | #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ | |
787 | ||
788 | /* M88E1000 PHY Specific Control Register */ | |
789 | #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ | |
790 | /* 1=CLK125 low, 0=CLK125 toggling */ | |
791 | #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ | |
792 | /* Manual MDI configuration */ | |
793 | #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ | |
794 | /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ | |
795 | #define M88E1000_PSCR_AUTO_X_1000T 0x0040 | |
796 | /* Auto crossover enabled all speeds */ | |
797 | #define M88E1000_PSCR_AUTO_X_MODE 0x0060 | |
b980ac18 | 798 | /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold |
652fff32 | 799 | * 0=Normal 10BASE-T Rx Threshold |
9d5c8243 AK |
800 | */ |
801 | /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ | |
802 | #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ | |
803 | ||
804 | /* M88E1000 PHY Specific Status Register */ | |
805 | #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ | |
806 | #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ | |
807 | #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ | |
b980ac18 | 808 | /* 0 = <50M |
9d5c8243 AK |
809 | * 1 = 50-80M |
810 | * 2 = 80-110M | |
811 | * 3 = 110-140M | |
812 | * 4 = >140M | |
813 | */ | |
814 | #define M88E1000_PSSR_CABLE_LENGTH 0x0380 | |
815 | #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ | |
816 | #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ | |
817 | ||
818 | #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 | |
819 | ||
820 | /* M88E1000 Extended PHY Specific Control Register */ | |
b980ac18 | 821 | /* 1 = Lost lock detect enabled. |
9d5c8243 AK |
822 | * Will assert lost lock and bring |
823 | * link down if idle not seen | |
824 | * within 1ms in 1000BASE-T | |
825 | */ | |
b980ac18 | 826 | /* Number of times we will attempt to autonegotiate before downshifting if we |
9d5c8243 AK |
827 | * are the master |
828 | */ | |
829 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 | |
830 | #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 | |
b980ac18 | 831 | /* Number of times we will attempt to autonegotiate before downshifting if we |
9d5c8243 AK |
832 | * are the slave |
833 | */ | |
834 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 | |
835 | #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 | |
836 | #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ | |
837 | ||
308fb39a JG |
838 | /* Intel i347-AT4 Registers */ |
839 | ||
840 | #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ | |
841 | #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ | |
842 | #define I347AT4_PAGE_SELECT 0x16 | |
843 | ||
844 | /* i347-AT4 Extended PHY Specific Control Register */ | |
845 | ||
b980ac18 | 846 | /* Number of times we will attempt to autonegotiate before downshifting if we |
308fb39a JG |
847 | * are the master |
848 | */ | |
849 | #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 | |
850 | #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 | |
851 | #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 | |
852 | #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 | |
853 | #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 | |
854 | #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 | |
855 | #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 | |
856 | #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 | |
857 | #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 | |
858 | #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 | |
859 | ||
860 | /* i347-AT4 PHY Cable Diagnostics Control */ | |
861 | #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ | |
862 | ||
863 | /* Marvell 1112 only registers */ | |
864 | #define M88E1112_VCT_DSP_DISTANCE 0x001A | |
865 | ||
9d5c8243 AK |
866 | /* M88EC018 Rev 2 specific DownShift settings */ |
867 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 | |
868 | #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 | |
869 | ||
870 | /* MDI Control */ | |
4085f746 NN |
871 | #define E1000_MDIC_DATA_MASK 0x0000FFFF |
872 | #define E1000_MDIC_REG_MASK 0x001F0000 | |
9d5c8243 | 873 | #define E1000_MDIC_REG_SHIFT 16 |
4085f746 | 874 | #define E1000_MDIC_PHY_MASK 0x03E00000 |
9d5c8243 AK |
875 | #define E1000_MDIC_PHY_SHIFT 21 |
876 | #define E1000_MDIC_OP_WRITE 0x04000000 | |
877 | #define E1000_MDIC_OP_READ 0x08000000 | |
878 | #define E1000_MDIC_READY 0x10000000 | |
4085f746 | 879 | #define E1000_MDIC_INT_EN 0x20000000 |
9d5c8243 | 880 | #define E1000_MDIC_ERROR 0x40000000 |
4085f746 | 881 | #define E1000_MDIC_DEST 0x80000000 |
9d5c8243 | 882 | |
7ef5ed1c CW |
883 | /* Thermal Sensor */ |
884 | #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ | |
885 | #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */ | |
886 | ||
09b068d4 CW |
887 | /* Energy Efficient Ethernet */ |
888 | #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */ | |
889 | #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */ | |
890 | #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */ | |
891 | #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */ | |
e5461112 | 892 | #define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */ |
09b068d4 | 893 | #define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */ |
e5461112 | 894 | #define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */ |
24a372cd | 895 | #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ |
87371b9d MV |
896 | #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ |
897 | #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ | |
898 | #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ | |
899 | #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ | |
ceb5f13b CW |
900 | #define E1000_M88E1545_PAGE_ADDR 0x16 /* Page Offset Register */ |
901 | #define E1000_M88E1545_EEE_CTRL_1 0x0 | |
902 | #define E1000_M88E1545_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ | |
903 | #define E1000_EEE_ADV_DEV_I354 7 | |
904 | #define E1000_EEE_ADV_ADDR_I354 60 | |
905 | #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ | |
906 | #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ | |
907 | #define E1000_PCS_STATUS_DEV_I354 3 | |
908 | #define E1000_PCS_STATUS_ADDR_I354 1 | |
909 | #define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */ | |
910 | #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 | |
911 | #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 | |
09b068d4 | 912 | |
9d5c8243 AK |
913 | /* SerDes Control */ |
914 | #define E1000_GEN_CTL_READY 0x80000000 | |
915 | #define E1000_GEN_CTL_ADDRESS_SHIFT 8 | |
916 | #define E1000_GEN_POLL_TIMEOUT 640 | |
917 | ||
4ae196df AD |
918 | #define E1000_VFTA_ENTRY_SHIFT 5 |
919 | #define E1000_VFTA_ENTRY_MASK 0x7F | |
920 | #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F | |
921 | ||
55cac248 AD |
922 | /* DMA Coalescing register fields */ |
923 | #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based | |
924 | on DMA coal */ | |
925 | ||
17dc566c LL |
926 | /* Tx Rate-Scheduler Config fields */ |
927 | #define E1000_RTTBCNRC_RS_ENA 0x80000000 | |
928 | #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF | |
929 | #define E1000_RTTBCNRC_RF_INT_SHIFT 14 | |
930 | #define E1000_RTTBCNRC_RF_INT_MASK \ | |
931 | (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) | |
932 | ||
9d5c8243 | 933 | #endif |