[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_hw.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2014 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, see <http://www.gnu.org/licenses/>.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/netdevice.h>

#include "e1000_regs.h"
#include "e1000_defines.h"

struct e1000_hw;

#define E1000_DEV_ID_82576			0x10C9
#define E1000_DEV_ID_82576_FIBER		0x10E6
#define E1000_DEV_ID_82576_SERDES		0x10E7
#define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
#define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
#define E1000_DEV_ID_82576_NS			0x150A
#define E1000_DEV_ID_82576_NS_SERDES		0x1518
#define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
#define E1000_DEV_ID_82575EB_COPPER		0x10A7
#define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
#define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
#define E1000_DEV_ID_82580_COPPER		0x150E
#define E1000_DEV_ID_82580_FIBER		0x150F
#define E1000_DEV_ID_82580_SERDES		0x1510
#define E1000_DEV_ID_82580_SGMII		0x1511
#define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
#define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
#define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
#define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
#define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
#define E1000_DEV_ID_DH89XXCC_SFP		0x0440
#define E1000_DEV_ID_I350_COPPER		0x1521
#define E1000_DEV_ID_I350_FIBER			0x1522
#define E1000_DEV_ID_I350_SERDES		0x1523
#define E1000_DEV_ID_I350_SGMII			0x1524
#define E1000_DEV_ID_I210_COPPER		0x1533
#define E1000_DEV_ID_I210_FIBER			0x1536
#define E1000_DEV_ID_I210_SERDES		0x1537
#define E1000_DEV_ID_I210_SGMII			0x1538
#define E1000_DEV_ID_I210_COPPER_FLASHLESS	0x157B
#define E1000_DEV_ID_I210_SERDES_FLASHLESS	0x157C
#define E1000_DEV_ID_I211_COPPER		0x1539
#define E1000_DEV_ID_I354_BACKPLANE_1GBPS	0x1F40
#define E1000_DEV_ID_I354_SGMII			0x1F41
#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS	0x1F45

#define E1000_REVISION_2 2
#define E1000_REVISION_4 4

#define E1000_FUNC_0     0
#define E1000_FUNC_1     1
#define E1000_FUNC_2     2
#define E1000_FUNC_3     3

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9

enum e1000_mac_type {
	e1000_undefined = 0,
	e1000_82575,
	e1000_82576,
	e1000_82580,
	e1000_i350,
	e1000_i354,
	e1000_i210,
	e1000_i211,
	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
};

enum e1000_media_type {
	e1000_media_type_unknown = 0,
	e1000_media_type_copper = 1,
	e1000_media_type_fiber = 2,
	e1000_media_type_internal_serdes = 3,
	e1000_num_media_types
};

enum e1000_nvm_type {
	e1000_nvm_unknown = 0,
	e1000_nvm_none,
	e1000_nvm_eeprom_spi,
	e1000_nvm_flash_hw,
	e1000_nvm_invm,
	e1000_nvm_flash_sw
};

enum e1000_nvm_override {
	e1000_nvm_override_none = 0,
	e1000_nvm_override_spi_small,
	e1000_nvm_override_spi_large,
};

enum e1000_phy_type {
	e1000_phy_unknown = 0,
	e1000_phy_none,
	e1000_phy_m88,
	e1000_phy_igp,
	e1000_phy_igp_2,
	e1000_phy_gg82563,
	e1000_phy_igp_3,
	e1000_phy_ife,
	e1000_phy_82580,
	e1000_phy_i210,
};

enum e1000_bus_type {
	e1000_bus_type_unknown = 0,
	e1000_bus_type_pci,
	e1000_bus_type_pcix,
	e1000_bus_type_pci_express,
	e1000_bus_type_reserved
};

enum e1000_bus_speed {
	e1000_bus_speed_unknown = 0,
	e1000_bus_speed_33,
	e1000_bus_speed_66,
	e1000_bus_speed_100,
	e1000_bus_speed_120,
	e1000_bus_speed_133,
	e1000_bus_speed_2500,
	e1000_bus_speed_5000,
	e1000_bus_speed_reserved
};

enum e1000_bus_width {
	e1000_bus_width_unknown = 0,
	e1000_bus_width_pcie_x1,
	e1000_bus_width_pcie_x2,
	e1000_bus_width_pcie_x4 = 4,
	e1000_bus_width_pcie_x8 = 8,
	e1000_bus_width_32,
	e1000_bus_width_64,
	e1000_bus_width_reserved
};

enum e1000_1000t_rx_status {
	e1000_1000t_rx_status_not_ok = 0,
	e1000_1000t_rx_status_ok,
	e1000_1000t_rx_status_undefined = 0xFF
};

enum e1000_rev_polarity {
	e1000_rev_polarity_normal = 0,
	e1000_rev_polarity_reversed,
	e1000_rev_polarity_undefined = 0xFF
};

enum e1000_fc_mode {
	e1000_fc_none = 0,
	e1000_fc_rx_pause,
	e1000_fc_tx_pause,
	e1000_fc_full,
	e1000_fc_default = 0xFF
};

/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
	u64 crcerrs;
	u64 algnerrc;
	u64 symerrs;
	u64 rxerrc;
	u64 mpc;
	u64 scc;
	u64 ecol;
	u64 mcc;
	u64 latecol;
	u64 colc;
	u64 dc;
	u64 tncrs;
	u64 sec;
	u64 cexterr;
	u64 rlec;
	u64 xonrxc;
	u64 xontxc;
	u64 xoffrxc;
	u64 xofftxc;
	u64 fcruc;
	u64 prc64;
	u64 prc127;
	u64 prc255;
	u64 prc511;
	u64 prc1023;
	u64 prc1522;
	u64 gprc;
	u64 bprc;
	u64 mprc;
	u64 gptc;
	u64 gorc;
	u64 gotc;
	u64 rnbc;
	u64 ruc;
	u64 rfc;
	u64 roc;
	u64 rjc;
	u64 mgprc;
	u64 mgpdc;
	u64 mgptc;
	u64 tor;
	u64 tot;
	u64 tpr;
	u64 tpt;
	u64 ptc64;
	u64 ptc127;
	u64 ptc255;
	u64 ptc511;
	u64 ptc1023;
	u64 ptc1522;
	u64 mptc;
	u64 bptc;
	u64 tsctc;
	u64 tsctfc;
	u64 iac;
	u64 icrxptc;
	u64 icrxatc;
	u64 ictxptc;
	u64 ictxatc;
	u64 ictxqec;
	u64 ictxqmtc;
	u64 icrxdmtc;
	u64 icrxoc;
	u64 cbtmpc;
	u64 htdpmc;
	u64 cbrdpc;
	u64 cbrmpc;
	u64 rpthc;
	u64 hgptc;
	u64 htcbdpc;
	u64 hgorc;
	u64 hgotc;
	u64 lenerrs;
	u64 scvpc;
	u64 hrmpc;
	u64 doosync;
	u64 o2bgptc;
	u64 o2bspc;
	u64 b2ospc;
	u64 b2ogprc;
};

struct e1000_phy_stats {
	u32 idle_errors;
	u32 receive_errors;
};

struct e1000_host_mng_dhcp_cookie {
	u32 signature;
	u8  status;
	u8  reserved0;
	u16 vlan_id;
	u32 reserved1;
	u16 reserved2;
	u8  reserved3;
	u8  checksum;
};

/* Host Interface "Rev 1" */
struct e1000_host_command_header {
	u8 command_id;
	u8 command_length;
	u8 command_options;
	u8 checksum;
};

#define E1000_HI_MAX_DATA_LENGTH     252
struct e1000_host_command_info {
	struct e1000_host_command_header command_header;
	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
};

/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
	u8  command_id;
	u8  checksum;
	u16 reserved1;
	u16 reserved2;
	u16 command_length;
};

#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
struct e1000_host_mng_command_info {
	struct e1000_host_mng_command_header command_header;
	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
};

#include "e1000_mac.h"
#include "e1000_phy.h"
#include "e1000_nvm.h"
#include "e1000_mbx.h"

struct e1000_mac_operations {
	s32  (*check_for_link)(struct e1000_hw *);
	s32  (*reset_hw)(struct e1000_hw *);
	s32  (*init_hw)(struct e1000_hw *);
	bool (*check_mng_mode)(struct e1000_hw *);
	s32  (*setup_physical_interface)(struct e1000_hw *);
	void (*rar_set)(struct e1000_hw *, u8 *, u32);
	s32  (*read_mac_addr)(struct e1000_hw *);
	s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
	s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
	void (*release_swfw_sync)(struct e1000_hw *, u16);
#ifdef CONFIG_IGB_HWMON
	s32 (*get_thermal_sensor_data)(struct e1000_hw *);
	s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
#endif

};

struct e1000_phy_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*check_polarity)(struct e1000_hw *);
	s32  (*check_reset_block)(struct e1000_hw *);
	s32  (*force_speed_duplex)(struct e1000_hw *);
	s32  (*get_cfg_done)(struct e1000_hw *hw);
	s32  (*get_cable_length)(struct e1000_hw *);
	s32  (*get_phy_info)(struct e1000_hw *);
	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*reset)(struct e1000_hw *);
	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
	s32  (*write_reg)(struct e1000_hw *, u32, u16);
	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
};

struct e1000_nvm_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
	s32  (*update)(struct e1000_hw *);
	s32  (*validate)(struct e1000_hw *);
	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
};

#define E1000_MAX_SENSORS		3

struct e1000_thermal_diode_data {
	u8 location;
	u8 temp;
	u8 caution_thresh;
	u8 max_op_thresh;
};

struct e1000_thermal_sensor_data {
	struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
};

struct e1000_info {
	s32 (*get_invariants)(struct e1000_hw *);
	struct e1000_mac_operations *mac_ops;
	struct e1000_phy_operations *phy_ops;
	struct e1000_nvm_operations *nvm_ops;
};

extern const struct e1000_info e1000_82575_info;

struct e1000_mac_info {
	struct e1000_mac_operations ops;

	u8 addr[6];
	u8 perm_addr[6];

	enum e1000_mac_type type;

	u32 ledctl_default;
	u32 ledctl_mode1;
	u32 ledctl_mode2;
	u32 mc_filter_type;
	u32 txcw;

	u16 mta_reg_count;
	u16 uta_reg_count;

	/* Maximum size of the MTA register table in all supported adapters */
	#define MAX_MTA_REG 128
	u32 mta_shadow[MAX_MTA_REG];
	u16 rar_entry_count;

	u8  forced_speed_duplex;

	bool adaptive_ifs;
	bool arc_subsystem_valid;
	bool asf_firmware_present;
	bool autoneg;
	bool autoneg_failed;
	bool disable_hw_init_bits;
	bool get_link_status;
	bool ifs_params_forced;
	bool in_ifs_mode;
	bool report_tx_early;
	bool serdes_has_link;
	bool tx_pkt_filtering;
	struct e1000_thermal_sensor_data thermal_sensor_data;
};

struct e1000_phy_info {
	struct e1000_phy_operations ops;

	enum e1000_phy_type type;

	enum e1000_1000t_rx_status local_rx;
	enum e1000_1000t_rx_status remote_rx;
	enum e1000_ms_type ms_type;
	enum e1000_ms_type original_ms_type;
	enum e1000_rev_polarity cable_polarity;
	enum e1000_smart_speed smart_speed;

	u32 addr;
	u32 id;
	u32 reset_delay_us; /* in usec */
	u32 revision;

	enum e1000_media_type media_type;

	u16 autoneg_advertised;
	u16 autoneg_mask;
	u16 cable_length;
	u16 max_cable_length;
	u16 min_cable_length;

	u8 mdix;

	bool disable_polarity_correction;
	bool is_mdix;
	bool polarity_correction;
	bool reset_disable;
	bool speed_downgraded;
	bool autoneg_wait_to_complete;
};

struct e1000_nvm_info {
	struct e1000_nvm_operations ops;
	enum e1000_nvm_type type;
	enum e1000_nvm_override override;

	u32 flash_bank_size;
	u32 flash_base_addr;

	u16 word_size;
	u16 delay_usec;
	u16 address_bits;
	u16 opcode_bits;
	u16 page_size;
};

struct e1000_bus_info {
	enum e1000_bus_type type;
	enum e1000_bus_speed speed;
	enum e1000_bus_width width;

	u32 snoop;

	u16 func;
	u16 pci_cmd_word;
};

struct e1000_fc_info {
	u32 high_water;     /* Flow control high-water mark */
	u32 low_water;      /* Flow control low-water mark */
	u16 pause_time;     /* Flow control pause timer */
	bool send_xon;      /* Flow control send XON */
	bool strict_ieee;   /* Strict IEEE mode */
	enum e1000_fc_mode current_mode; /* Type of flow control */
	enum e1000_fc_mode requested_mode;
};

struct e1000_mbx_operations {
	s32 (*init_params)(struct e1000_hw *hw);
	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
	s32 (*check_for_msg)(struct e1000_hw *, u16);
	s32 (*check_for_ack)(struct e1000_hw *, u16);
	s32 (*check_for_rst)(struct e1000_hw *, u16);
};

struct e1000_mbx_stats {
	u32 msgs_tx;
	u32 msgs_rx;

	u32 acks;
	u32 reqs;
	u32 rsts;
};

struct e1000_mbx_info {
	struct e1000_mbx_operations ops;
	struct e1000_mbx_stats stats;
	u32 timeout;
	u32 usec_delay;
	u16 size;
};

struct e1000_dev_spec_82575 {
	bool sgmii_active;
	bool global_device_reset;
	bool eee_disable;
	bool clear_semaphore_once;
	struct e1000_sfp_flags eth_flags;
	bool module_plugged;
	u8 media_port;
	bool media_changed;
	bool mas_capable;
};

struct e1000_hw {
	void *back;

	u8 __iomem *hw_addr;
	u8 __iomem *flash_address;
	unsigned long io_base;

	struct e1000_mac_info  mac;
	struct e1000_fc_info   fc;
	struct e1000_phy_info  phy;
	struct e1000_nvm_info  nvm;
	struct e1000_bus_info  bus;
	struct e1000_mbx_info mbx;
	struct e1000_host_mng_dhcp_cookie mng_cookie;

	union {
		struct e1000_dev_spec_82575	_82575;
	} dev_spec;

	u16 device_id;
	u16 subsystem_vendor_id;
	u16 subsystem_device_id;
	u16 vendor_id;

	u8  revision_id;
};

struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
#define hw_dbg(format, arg...) \
	netdev_dbg(igb_get_hw_dev(hw), format, ##arg)

/* These functions must be implemented by drivers */
s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
#endif /* _E1000_HW_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
74cfb2e1	4	Copyright(c) 2007-2014 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
74cfb2e1	16	this program; if not, see <http://www.gnu.org/licenses/>.
9d5c8243 AK	17
	18	The full GNU General Public License is included in this distribution in
	19	the file called "COPYING".
	20
	21	Contact Information:
	22	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	23	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	24
	25	*******************************************************************************/
	26
	27	#ifndef _E1000_HW_H_
	28	#define _E1000_HW_H_
	29
	30	#include <linux/types.h>
	31	#include <linux/delay.h>
	32	#include <linux/io.h>
c041076a	33	#include <linux/netdevice.h>
9d5c8243	34
9d5c8243 AK	35	#include "e1000_regs.h"
	36	#include "e1000_defines.h"
	37
	38	struct e1000_hw;
	39
b980ac18 JK	40	#define E1000_DEV_ID_82576 0x10C9
	41	#define E1000_DEV_ID_82576_FIBER 0x10E6
	42	#define E1000_DEV_ID_82576_SERDES 0x10E7
	43	#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
	44	#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
	45	#define E1000_DEV_ID_82576_NS 0x150A
	46	#define E1000_DEV_ID_82576_NS_SERDES 0x1518
	47	#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
	48	#define E1000_DEV_ID_82575EB_COPPER 0x10A7
	49	#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
	50	#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
	51	#define E1000_DEV_ID_82580_COPPER 0x150E
	52	#define E1000_DEV_ID_82580_FIBER 0x150F
	53	#define E1000_DEV_ID_82580_SERDES 0x1510
	54	#define E1000_DEV_ID_82580_SGMII 0x1511
	55	#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
	56	#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
	57	#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
	58	#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
	59	#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
	60	#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
	61	#define E1000_DEV_ID_I350_COPPER 0x1521
	62	#define E1000_DEV_ID_I350_FIBER 0x1522
	63	#define E1000_DEV_ID_I350_SERDES 0x1523
	64	#define E1000_DEV_ID_I350_SGMII 0x1524
f96a8a0b	65	#define E1000_DEV_ID_I210_COPPER 0x1533
f96a8a0b CW	66	#define E1000_DEV_ID_I210_FIBER 0x1536
	67	#define E1000_DEV_ID_I210_SERDES 0x1537
	68	#define E1000_DEV_ID_I210_SGMII 0x1538
53b87ce3 CW	69	#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B
53b87ce3 CW	70	#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C
f96a8a0b	71	#define E1000_DEV_ID_I211_COPPER 0x1539
ceb5f13b CW	72	#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
	73	#define E1000_DEV_ID_I354_SGMII 0x1F41
	74	#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
9d5c8243 AK	75
	76	#define E1000_REVISION_2 2
	77	#define E1000_REVISION_4 4
	78
70d92f86	79	#define E1000_FUNC_0 0
9d5c8243	80	#define E1000_FUNC_1 1
bb2ac47b AD	81	#define E1000_FUNC_2 2
bb2ac47b AD	82	#define E1000_FUNC_3 3
9d5c8243	83
bb2ac47b	84	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
22896639	85	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
bb2ac47b AD	86	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
bb2ac47b AD	87	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
22896639	88
9d5c8243 AK	89	enum e1000_mac_type {
	90	e1000_undefined = 0,
	91	e1000_82575,
2d064c06	92	e1000_82576,
bb2ac47b	93	e1000_82580,
d2ba2ed8	94	e1000_i350,
ceb5f13b	95	e1000_i354,
f96a8a0b CW	96	e1000_i210,
f96a8a0b CW	97	e1000_i211,
9d5c8243 AK	98	e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
	99	};
	100
	101	enum e1000_media_type {
	102	e1000_media_type_unknown = 0,
	103	e1000_media_type_copper = 1,
f502ef7d AA	104	e1000_media_type_fiber = 2,
f502ef7d AA	105	e1000_media_type_internal_serdes = 3,
9d5c8243 AK	106	e1000_num_media_types
	107	};
	108
	109	enum e1000_nvm_type {
	110	e1000_nvm_unknown = 0,
	111	e1000_nvm_none,
	112	e1000_nvm_eeprom_spi,
9d5c8243	113	e1000_nvm_flash_hw,
5a823d8c	114	e1000_nvm_invm,
9d5c8243 AK	115	e1000_nvm_flash_sw
	116	};
	117
	118	enum e1000_nvm_override {
	119	e1000_nvm_override_none = 0,
	120	e1000_nvm_override_spi_small,
	121	e1000_nvm_override_spi_large,
9d5c8243 AK	122	};
	123
	124	enum e1000_phy_type {
	125	e1000_phy_unknown = 0,
	126	e1000_phy_none,
	127	e1000_phy_m88,
	128	e1000_phy_igp,
	129	e1000_phy_igp_2,
	130	e1000_phy_gg82563,
	131	e1000_phy_igp_3,
	132	e1000_phy_ife,
2909c3f7	133	e1000_phy_82580,
f96a8a0b	134	e1000_phy_i210,
9d5c8243 AK	135	};
	136
	137	enum e1000_bus_type {
	138	e1000_bus_type_unknown = 0,
	139	e1000_bus_type_pci,
	140	e1000_bus_type_pcix,
	141	e1000_bus_type_pci_express,
	142	e1000_bus_type_reserved
	143	};
	144
	145	enum e1000_bus_speed {
	146	e1000_bus_speed_unknown = 0,
	147	e1000_bus_speed_33,
	148	e1000_bus_speed_66,
	149	e1000_bus_speed_100,
	150	e1000_bus_speed_120,
	151	e1000_bus_speed_133,
	152	e1000_bus_speed_2500,
	153	e1000_bus_speed_5000,
	154	e1000_bus_speed_reserved
	155	};
	156
	157	enum e1000_bus_width {
	158	e1000_bus_width_unknown = 0,
	159	e1000_bus_width_pcie_x1,
	160	e1000_bus_width_pcie_x2,
	161	e1000_bus_width_pcie_x4 = 4,
	162	e1000_bus_width_pcie_x8 = 8,
	163	e1000_bus_width_32,
	164	e1000_bus_width_64,
	165	e1000_bus_width_reserved
	166	};
	167
	168	enum e1000_1000t_rx_status {
	169	e1000_1000t_rx_status_not_ok = 0,
	170	e1000_1000t_rx_status_ok,
	171	e1000_1000t_rx_status_undefined = 0xFF
	172	};
	173
	174	enum e1000_rev_polarity {
	175	e1000_rev_polarity_normal = 0,
	176	e1000_rev_polarity_reversed,
	177	e1000_rev_polarity_undefined = 0xFF
	178	};
	179
0cce119a	180	enum e1000_fc_mode {
9d5c8243 AK	181	e1000_fc_none = 0,
	182	e1000_fc_rx_pause,
	183	e1000_fc_tx_pause,
	184	e1000_fc_full,
	185	e1000_fc_default = 0xFF
	186	};
	187
9d5c8243 AK	188	/* Statistics counters collected by the MAC */
	189	struct e1000_hw_stats {
	190	u64 crcerrs;
	191	u64 algnerrc;
	192	u64 symerrs;
	193	u64 rxerrc;
	194	u64 mpc;
	195	u64 scc;
	196	u64 ecol;
	197	u64 mcc;
	198	u64 latecol;
	199	u64 colc;
	200	u64 dc;
	201	u64 tncrs;
	202	u64 sec;
	203	u64 cexterr;
	204	u64 rlec;
	205	u64 xonrxc;
	206	u64 xontxc;
	207	u64 xoffrxc;
	208	u64 xofftxc;
	209	u64 fcruc;
	210	u64 prc64;
	211	u64 prc127;
	212	u64 prc255;
	213	u64 prc511;
	214	u64 prc1023;
	215	u64 prc1522;
	216	u64 gprc;
	217	u64 bprc;
	218	u64 mprc;
	219	u64 gptc;
	220	u64 gorc;
	221	u64 gotc;
	222	u64 rnbc;
	223	u64 ruc;
	224	u64 rfc;
	225	u64 roc;
	226	u64 rjc;
	227	u64 mgprc;
	228	u64 mgpdc;
	229	u64 mgptc;
	230	u64 tor;
	231	u64 tot;
	232	u64 tpr;
	233	u64 tpt;
	234	u64 ptc64;
	235	u64 ptc127;
	236	u64 ptc255;
	237	u64 ptc511;
	238	u64 ptc1023;
	239	u64 ptc1522;
	240	u64 mptc;
	241	u64 bptc;
	242	u64 tsctc;
	243	u64 tsctfc;
	244	u64 iac;
	245	u64 icrxptc;
	246	u64 icrxatc;
	247	u64 ictxptc;
	248	u64 ictxatc;
	249	u64 ictxqec;
	250	u64 ictxqmtc;
	251	u64 icrxdmtc;
252	u64 icrxoc;
253	u64 cbtmpc;
254	u64 htdpmc;
255	u64 cbrdpc;
256	u64 cbrmpc;
257	u64 rpthc;
258	u64 hgptc;
259	u64 htcbdpc;
260	u64 hgorc;
261	u64 hgotc;
262	u64 lenerrs;
263	u64 scvpc;
264	u64 hrmpc;
dda0e083	265	u64 doosync;
0a915b95 CW	266	u64 o2bgptc;
	267	u64 o2bspc;
	268	u64 b2ospc;
	269	u64 b2ogprc;
9d5c8243 AK	270	};
	271
	272	struct e1000_phy_stats {
	273	u32 idle_errors;
	274	u32 receive_errors;
	275	};
	276
	277	struct e1000_host_mng_dhcp_cookie {
	278	u32 signature;
	279	u8 status;
	280	u8 reserved0;
	281	u16 vlan_id;
	282	u32 reserved1;
	283	u16 reserved2;
	284	u8 reserved3;
	285	u8 checksum;
	286	};
	287
	288	/* Host Interface "Rev 1" */
	289	struct e1000_host_command_header {
	290	u8 command_id;
	291	u8 command_length;
	292	u8 command_options;
	293	u8 checksum;
	294	};
	295
	296	#define E1000_HI_MAX_DATA_LENGTH 252
	297	struct e1000_host_command_info {
	298	struct e1000_host_command_header command_header;
	299	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
	300	};
	301
	302	/* Host Interface "Rev 2" */
	303	struct e1000_host_mng_command_header {
	304	u8 command_id;
	305	u8 checksum;
	306	u16 reserved1;
	307	u16 reserved2;
	308	u16 command_length;
	309	};
	310
	311	#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
	312	struct e1000_host_mng_command_info {
	313	struct e1000_host_mng_command_header command_header;
	314	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
	315	};
	316
	317	#include "e1000_mac.h"
	318	#include "e1000_phy.h"
	319	#include "e1000_nvm.h"
4ae196df	320	#include "e1000_mbx.h"
9d5c8243 AK	321
	322	struct e1000_mac_operations {
	323	s32 (check_for_link)(struct e1000_hw );
	324	s32 (reset_hw)(struct e1000_hw );
	325	s32 (init_hw)(struct e1000_hw );
2d064c06	326	bool (check_mng_mode)(struct e1000_hw );
9d5c8243 AK	327	s32 (setup_physical_interface)(struct e1000_hw );
	328	void (rar_set)(struct e1000_hw , u8 *, u32);
	329	s32 (read_mac_addr)(struct e1000_hw );
	330	s32 (get_speed_and_duplex)(struct e1000_hw , u16 , u16 );
f96a8a0b CW	331	s32 (acquire_swfw_sync)(struct e1000_hw , u16);
f96a8a0b CW	332	void (release_swfw_sync)(struct e1000_hw , u16);
e428893b CW	333	#ifdef CONFIG_IGB_HWMON
	334	s32 (get_thermal_sensor_data)(struct e1000_hw );
	335	s32 (init_thermal_sensor_thresh)(struct e1000_hw );
	336	#endif
f96a8a0b	337
9d5c8243 AK	338	};
	339
	340	struct e1000_phy_operations {
a8d2a0c2	341	s32 (acquire)(struct e1000_hw );
bb2ac47b	342	s32 (check_polarity)(struct e1000_hw );
2d064c06	343	s32 (check_reset_block)(struct e1000_hw );
9d5c8243 AK	344	s32 (force_speed_duplex)(struct e1000_hw );
	345	s32 (get_cfg_done)(struct e1000_hw hw);
	346	s32 (get_cable_length)(struct e1000_hw );
	347	s32 (get_phy_info)(struct e1000_hw );
a8d2a0c2 AD	348	s32 (read_reg)(struct e1000_hw , u32, u16 *);
	349	void (release)(struct e1000_hw );
	350	s32 (reset)(struct e1000_hw );
9d5c8243 AK	351	s32 (set_d0_lplu_state)(struct e1000_hw , bool);
9d5c8243 AK	352	s32 (set_d3_lplu_state)(struct e1000_hw , bool);
a8d2a0c2	353	s32 (write_reg)(struct e1000_hw , u32, u16);
441fc6fd CW	354	s32 (read_i2c_byte)(struct e1000_hw , u8, u8, u8 *);
441fc6fd CW	355	s32 (write_i2c_byte)(struct e1000_hw , u8, u8, u8);
9d5c8243 AK	356	};
	357
	358	struct e1000_nvm_operations {
312c75ae AD	359	s32 (acquire)(struct e1000_hw );
	360	s32 (read)(struct e1000_hw , u16, u16, u16 *);
	361	void (release)(struct e1000_hw );
	362	s32 (write)(struct e1000_hw , u16, u16, u16 *);
4322e561 CW	363	s32 (update)(struct e1000_hw );
4322e561 CW	364	s32 (validate)(struct e1000_hw );
f96a8a0b	365	s32 (valid_led_default)(struct e1000_hw , u16 *);
9d5c8243 AK	366	};
9d5c8243 AK	367
aca5dae8 CW	368	#define E1000_MAX_SENSORS 3
	369
	370	struct e1000_thermal_diode_data {
	371	u8 location;
	372	u8 temp;
	373	u8 caution_thresh;
	374	u8 max_op_thresh;
	375	};
	376
	377	struct e1000_thermal_sensor_data {
	378	struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
	379	};
	380
9d5c8243 AK	381	struct e1000_info {
	382	s32 (get_invariants)(struct e1000_hw );
	383	struct e1000_mac_operations *mac_ops;
	384	struct e1000_phy_operations *phy_ops;
	385	struct e1000_nvm_operations *nvm_ops;
	386	};
	387
	388	extern const struct e1000_info e1000_82575_info;
	389
	390	struct e1000_mac_info {
	391	struct e1000_mac_operations ops;
	392
	393	u8 addr[6];
	394	u8 perm_addr[6];
	395
	396	enum e1000_mac_type type;
	397
9d5c8243 AK	398	u32 ledctl_default;
	399	u32 ledctl_mode1;
	400	u32 ledctl_mode2;
	401	u32 mc_filter_type;
9d5c8243 AK	402	u32 txcw;
9d5c8243 AK	403
9d5c8243	404	u16 mta_reg_count;
68d480c4	405	u16 uta_reg_count;
28fc06f5 AD	406
	407	/* Maximum size of the MTA register table in all supported adapters */
	408	#define MAX_MTA_REG 128
	409	u32 mta_shadow[MAX_MTA_REG];
9d5c8243 AK	410	u16 rar_entry_count;
	411
	412	u8 forced_speed_duplex;
	413
	414	bool adaptive_ifs;
	415	bool arc_subsystem_valid;
	416	bool asf_firmware_present;
	417	bool autoneg;
	418	bool autoneg_failed;
9d5c8243 AK	419	bool disable_hw_init_bits;
	420	bool get_link_status;
	421	bool ifs_params_forced;
	422	bool in_ifs_mode;
	423	bool report_tx_early;
	424	bool serdes_has_link;
	425	bool tx_pkt_filtering;
aca5dae8	426	struct e1000_thermal_sensor_data thermal_sensor_data;
9d5c8243 AK	427	};
	428
	429	struct e1000_phy_info {
	430	struct e1000_phy_operations ops;
	431
	432	enum e1000_phy_type type;
	433
	434	enum e1000_1000t_rx_status local_rx;
	435	enum e1000_1000t_rx_status remote_rx;
	436	enum e1000_ms_type ms_type;
	437	enum e1000_ms_type original_ms_type;
	438	enum e1000_rev_polarity cable_polarity;
	439	enum e1000_smart_speed smart_speed;
	440
	441	u32 addr;
	442	u32 id;
	443	u32 reset_delay_us; /* in usec */
	444	u32 revision;
	445
	446	enum e1000_media_type media_type;
	447
	448	u16 autoneg_advertised;
	449	u16 autoneg_mask;
	450	u16 cable_length;
	451	u16 max_cable_length;
	452	u16 min_cable_length;
	453
	454	u8 mdix;
	455
	456	bool disable_polarity_correction;
	457	bool is_mdix;
	458	bool polarity_correction;
	459	bool reset_disable;
	460	bool speed_downgraded;
	461	bool autoneg_wait_to_complete;
	462	};
	463
	464	struct e1000_nvm_info {
	465	struct e1000_nvm_operations ops;
9d5c8243 AK	466	enum e1000_nvm_type type;
	467	enum e1000_nvm_override override;
	468
	469	u32 flash_bank_size;
	470	u32 flash_base_addr;
	471
	472	u16 word_size;
	473	u16 delay_usec;
	474	u16 address_bits;
	475	u16 opcode_bits;
	476	u16 page_size;
	477	};
	478
	479	struct e1000_bus_info {
	480	enum e1000_bus_type type;
	481	enum e1000_bus_speed speed;
	482	enum e1000_bus_width width;
	483
	484	u32 snoop;
	485
	486	u16 func;
	487	u16 pci_cmd_word;
	488	};
	489
	490	struct e1000_fc_info {
	491	u32 high_water; /* Flow control high-water mark */
	492	u32 low_water; /* Flow control low-water mark */
	493	u16 pause_time; /* Flow control pause timer */
	494	bool send_xon; /* Flow control send XON */
	495	bool strict_ieee; /* Strict IEEE mode */
0cce119a AD	496	enum e1000_fc_mode current_mode; /* Type of flow control */
0cce119a AD	497	enum e1000_fc_mode requested_mode;
9d5c8243 AK	498	};
9d5c8243 AK	499
4ae196df AD	500	struct e1000_mbx_operations {
	501	s32 (init_params)(struct e1000_hw hw);
	502	s32 (read)(struct e1000_hw , u32 *, u16, u16);
	503	s32 (write)(struct e1000_hw , u32 *, u16, u16);
	504	s32 (read_posted)(struct e1000_hw , u32 *, u16, u16);
	505	s32 (write_posted)(struct e1000_hw , u32 *, u16, u16);
	506	s32 (check_for_msg)(struct e1000_hw , u16);
	507	s32 (check_for_ack)(struct e1000_hw , u16);
	508	s32 (check_for_rst)(struct e1000_hw , u16);
	509	};
	510
	511	struct e1000_mbx_stats {
	512	u32 msgs_tx;
	513	u32 msgs_rx;
	514
	515	u32 acks;
	516	u32 reqs;
	517	u32 rsts;
	518	};
	519
	520	struct e1000_mbx_info {
	521	struct e1000_mbx_operations ops;
	522	struct e1000_mbx_stats stats;
	523	u32 timeout;
	524	u32 usec_delay;
	525	u16 size;
	526	};
	527
c1889bfe AD	528	struct e1000_dev_spec_82575 {
c1889bfe AD	529	bool sgmii_active;
bb2ac47b	530	bool global_device_reset;
09b068d4	531	bool eee_disable;
d44e7a9a	532	bool clear_semaphore_once;
641ac5c0 AA	533	struct e1000_sfp_flags eth_flags;
641ac5c0 AA	534	bool module_plugged;
2bdfc4e2 CW	535	u8 media_port;
2bdfc4e2 CW	536	bool media_changed;
56cec249	537	bool mas_capable;
c1889bfe AD	538	};
c1889bfe AD	539
9d5c8243 AK	540	struct e1000_hw {
9d5c8243 AK	541	void *back;
9d5c8243 AK	542
	543	u8 __iomem *hw_addr;
	544	u8 __iomem *flash_address;
	545	unsigned long io_base;
	546
	547	struct e1000_mac_info mac;
	548	struct e1000_fc_info fc;
	549	struct e1000_phy_info phy;
	550	struct e1000_nvm_info nvm;
	551	struct e1000_bus_info bus;
4ae196df	552	struct e1000_mbx_info mbx;
9d5c8243 AK	553	struct e1000_host_mng_dhcp_cookie mng_cookie;
9d5c8243 AK	554
c1889bfe AD	555	union {
	556	struct e1000_dev_spec_82575 _82575;
	557	} dev_spec;
9d5c8243 AK	558
	559	u16 device_id;
	560	u16 subsystem_vendor_id;
	561	u16 subsystem_device_id;
	562	u16 vendor_id;
	563
	564	u8 revision_id;
	565	};
	566
5ccc921a	567	struct net_device igb_get_hw_dev(struct e1000_hw hw);
652fff32	568	#define hw_dbg(format, arg...) \
c041076a AD	569	netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
c041076a AD	570
009bc06e	571	/* These functions must be implemented by drivers */
5ccc921a JP	572	s32 igb_read_pcie_cap_reg(struct e1000_hw hw, u32 reg, u16 value);
5ccc921a JP	573	s32 igb_write_pcie_cap_reg(struct e1000_hw hw, u32 reg, u16 value);
c041076a	574	#endif /* _E1000_HW_H_ */