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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
4b9ea462 | 4 | Copyright(c) 2007-2013 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/if_ether.h> | |
29 | #include <linux/delay.h> | |
30 | ||
31 | #include "e1000_mac.h" | |
32 | #include "e1000_nvm.h" | |
33 | ||
34 | /** | |
733596be | 35 | * igb_raise_eec_clk - Raise EEPROM clock |
9d5c8243 AK |
36 | * @hw: pointer to the HW structure |
37 | * @eecd: pointer to the EEPROM | |
38 | * | |
39 | * Enable/Raise the EEPROM clock bit. | |
40 | **/ | |
41 | static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) | |
42 | { | |
43 | *eecd = *eecd | E1000_EECD_SK; | |
44 | wr32(E1000_EECD, *eecd); | |
45 | wrfl(); | |
46 | udelay(hw->nvm.delay_usec); | |
47 | } | |
48 | ||
49 | /** | |
733596be | 50 | * igb_lower_eec_clk - Lower EEPROM clock |
9d5c8243 AK |
51 | * @hw: pointer to the HW structure |
52 | * @eecd: pointer to the EEPROM | |
53 | * | |
54 | * Clear/Lower the EEPROM clock bit. | |
55 | **/ | |
56 | static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) | |
57 | { | |
58 | *eecd = *eecd & ~E1000_EECD_SK; | |
59 | wr32(E1000_EECD, *eecd); | |
60 | wrfl(); | |
61 | udelay(hw->nvm.delay_usec); | |
62 | } | |
63 | ||
64 | /** | |
733596be | 65 | * igb_shift_out_eec_bits - Shift data bits our to the EEPROM |
9d5c8243 AK |
66 | * @hw: pointer to the HW structure |
67 | * @data: data to send to the EEPROM | |
68 | * @count: number of bits to shift out | |
69 | * | |
70 | * We need to shift 'count' bits out to the EEPROM. So, the value in the | |
71 | * "data" parameter will be shifted out to the EEPROM one bit at a time. | |
72 | * In order to do this, "data" must be broken down into bits. | |
73 | **/ | |
74 | static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) | |
75 | { | |
76 | struct e1000_nvm_info *nvm = &hw->nvm; | |
77 | u32 eecd = rd32(E1000_EECD); | |
78 | u32 mask; | |
79 | ||
80 | mask = 0x01 << (count - 1); | |
285b4167 | 81 | if (nvm->type == e1000_nvm_eeprom_spi) |
9d5c8243 AK |
82 | eecd |= E1000_EECD_DO; |
83 | ||
84 | do { | |
85 | eecd &= ~E1000_EECD_DI; | |
86 | ||
87 | if (data & mask) | |
88 | eecd |= E1000_EECD_DI; | |
89 | ||
90 | wr32(E1000_EECD, eecd); | |
91 | wrfl(); | |
92 | ||
93 | udelay(nvm->delay_usec); | |
94 | ||
95 | igb_raise_eec_clk(hw, &eecd); | |
96 | igb_lower_eec_clk(hw, &eecd); | |
97 | ||
98 | mask >>= 1; | |
99 | } while (mask); | |
100 | ||
101 | eecd &= ~E1000_EECD_DI; | |
102 | wr32(E1000_EECD, eecd); | |
103 | } | |
104 | ||
105 | /** | |
733596be | 106 | * igb_shift_in_eec_bits - Shift data bits in from the EEPROM |
9d5c8243 AK |
107 | * @hw: pointer to the HW structure |
108 | * @count: number of bits to shift in | |
109 | * | |
110 | * In order to read a register from the EEPROM, we need to shift 'count' bits | |
111 | * in from the EEPROM. Bits are "shifted in" by raising the clock input to | |
112 | * the EEPROM (setting the SK bit), and then reading the value of the data out | |
113 | * "DO" bit. During this "shifting in" process the data in "DI" bit should | |
114 | * always be clear. | |
115 | **/ | |
116 | static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count) | |
117 | { | |
118 | u32 eecd; | |
119 | u32 i; | |
120 | u16 data; | |
121 | ||
122 | eecd = rd32(E1000_EECD); | |
123 | ||
124 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); | |
125 | data = 0; | |
126 | ||
127 | for (i = 0; i < count; i++) { | |
128 | data <<= 1; | |
129 | igb_raise_eec_clk(hw, &eecd); | |
130 | ||
131 | eecd = rd32(E1000_EECD); | |
132 | ||
133 | eecd &= ~E1000_EECD_DI; | |
134 | if (eecd & E1000_EECD_DO) | |
135 | data |= 1; | |
136 | ||
137 | igb_lower_eec_clk(hw, &eecd); | |
138 | } | |
139 | ||
140 | return data; | |
141 | } | |
142 | ||
143 | /** | |
733596be | 144 | * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion |
9d5c8243 AK |
145 | * @hw: pointer to the HW structure |
146 | * @ee_reg: EEPROM flag for polling | |
147 | * | |
148 | * Polls the EEPROM status bit for either read or write completion based | |
149 | * upon the value of 'ee_reg'. | |
150 | **/ | |
151 | static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) | |
152 | { | |
153 | u32 attempts = 100000; | |
154 | u32 i, reg = 0; | |
155 | s32 ret_val = -E1000_ERR_NVM; | |
156 | ||
157 | for (i = 0; i < attempts; i++) { | |
158 | if (ee_reg == E1000_NVM_POLL_READ) | |
159 | reg = rd32(E1000_EERD); | |
160 | else | |
161 | reg = rd32(E1000_EEWR); | |
162 | ||
163 | if (reg & E1000_NVM_RW_REG_DONE) { | |
164 | ret_val = 0; | |
165 | break; | |
166 | } | |
167 | ||
168 | udelay(5); | |
169 | } | |
170 | ||
171 | return ret_val; | |
172 | } | |
173 | ||
174 | /** | |
733596be | 175 | * igb_acquire_nvm - Generic request for access to EEPROM |
9d5c8243 AK |
176 | * @hw: pointer to the HW structure |
177 | * | |
178 | * Set the EEPROM access request bit and wait for EEPROM access grant bit. | |
179 | * Return successful if access grant bit set, else clear the request for | |
180 | * EEPROM access and return -E1000_ERR_NVM (-1). | |
181 | **/ | |
182 | s32 igb_acquire_nvm(struct e1000_hw *hw) | |
183 | { | |
184 | u32 eecd = rd32(E1000_EECD); | |
185 | s32 timeout = E1000_NVM_GRANT_ATTEMPTS; | |
186 | s32 ret_val = 0; | |
187 | ||
188 | ||
189 | wr32(E1000_EECD, eecd | E1000_EECD_REQ); | |
190 | eecd = rd32(E1000_EECD); | |
191 | ||
192 | while (timeout) { | |
193 | if (eecd & E1000_EECD_GNT) | |
194 | break; | |
195 | udelay(5); | |
196 | eecd = rd32(E1000_EECD); | |
197 | timeout--; | |
198 | } | |
199 | ||
200 | if (!timeout) { | |
201 | eecd &= ~E1000_EECD_REQ; | |
202 | wr32(E1000_EECD, eecd); | |
652fff32 | 203 | hw_dbg("Could not acquire NVM grant\n"); |
9d5c8243 AK |
204 | ret_val = -E1000_ERR_NVM; |
205 | } | |
206 | ||
207 | return ret_val; | |
208 | } | |
209 | ||
210 | /** | |
733596be | 211 | * igb_standby_nvm - Return EEPROM to standby state |
9d5c8243 AK |
212 | * @hw: pointer to the HW structure |
213 | * | |
214 | * Return the EEPROM to a standby state. | |
215 | **/ | |
216 | static void igb_standby_nvm(struct e1000_hw *hw) | |
217 | { | |
218 | struct e1000_nvm_info *nvm = &hw->nvm; | |
219 | u32 eecd = rd32(E1000_EECD); | |
220 | ||
285b4167 | 221 | if (nvm->type == e1000_nvm_eeprom_spi) { |
9d5c8243 AK |
222 | /* Toggle CS to flush commands */ |
223 | eecd |= E1000_EECD_CS; | |
224 | wr32(E1000_EECD, eecd); | |
225 | wrfl(); | |
226 | udelay(nvm->delay_usec); | |
227 | eecd &= ~E1000_EECD_CS; | |
228 | wr32(E1000_EECD, eecd); | |
229 | wrfl(); | |
230 | udelay(nvm->delay_usec); | |
231 | } | |
232 | } | |
233 | ||
234 | /** | |
235 | * e1000_stop_nvm - Terminate EEPROM command | |
236 | * @hw: pointer to the HW structure | |
237 | * | |
238 | * Terminates the current command by inverting the EEPROM's chip select pin. | |
239 | **/ | |
240 | static void e1000_stop_nvm(struct e1000_hw *hw) | |
241 | { | |
242 | u32 eecd; | |
243 | ||
244 | eecd = rd32(E1000_EECD); | |
245 | if (hw->nvm.type == e1000_nvm_eeprom_spi) { | |
246 | /* Pull CS high */ | |
247 | eecd |= E1000_EECD_CS; | |
248 | igb_lower_eec_clk(hw, &eecd); | |
9d5c8243 AK |
249 | } |
250 | } | |
251 | ||
252 | /** | |
733596be | 253 | * igb_release_nvm - Release exclusive access to EEPROM |
9d5c8243 AK |
254 | * @hw: pointer to the HW structure |
255 | * | |
256 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
257 | **/ | |
258 | void igb_release_nvm(struct e1000_hw *hw) | |
259 | { | |
260 | u32 eecd; | |
261 | ||
262 | e1000_stop_nvm(hw); | |
263 | ||
264 | eecd = rd32(E1000_EECD); | |
265 | eecd &= ~E1000_EECD_REQ; | |
266 | wr32(E1000_EECD, eecd); | |
267 | } | |
268 | ||
269 | /** | |
733596be | 270 | * igb_ready_nvm_eeprom - Prepares EEPROM for read/write |
9d5c8243 AK |
271 | * @hw: pointer to the HW structure |
272 | * | |
273 | * Setups the EEPROM for reading and writing. | |
274 | **/ | |
275 | static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) | |
276 | { | |
277 | struct e1000_nvm_info *nvm = &hw->nvm; | |
278 | u32 eecd = rd32(E1000_EECD); | |
279 | s32 ret_val = 0; | |
280 | u16 timeout = 0; | |
281 | u8 spi_stat_reg; | |
282 | ||
283 | ||
285b4167 | 284 | if (nvm->type == e1000_nvm_eeprom_spi) { |
9d5c8243 AK |
285 | /* Clear SK and CS */ |
286 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); | |
287 | wr32(E1000_EECD, eecd); | |
945a5151 | 288 | wrfl(); |
9d5c8243 AK |
289 | udelay(1); |
290 | timeout = NVM_MAX_RETRY_SPI; | |
291 | ||
b980ac18 | 292 | /* Read "Status Register" repeatedly until the LSB is cleared. |
9d5c8243 AK |
293 | * The EEPROM will signal that the command has been completed |
294 | * by clearing bit 0 of the internal status register. If it's | |
295 | * not cleared within 'timeout', then error out. | |
296 | */ | |
297 | while (timeout) { | |
298 | igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, | |
b980ac18 | 299 | hw->nvm.opcode_bits); |
9d5c8243 AK |
300 | spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8); |
301 | if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) | |
302 | break; | |
303 | ||
304 | udelay(5); | |
305 | igb_standby_nvm(hw); | |
306 | timeout--; | |
307 | } | |
308 | ||
309 | if (!timeout) { | |
652fff32 | 310 | hw_dbg("SPI NVM Status error\n"); |
9d5c8243 AK |
311 | ret_val = -E1000_ERR_NVM; |
312 | goto out; | |
313 | } | |
314 | } | |
315 | ||
316 | out: | |
317 | return ret_val; | |
318 | } | |
319 | ||
4322e561 CW |
320 | /** |
321 | * igb_read_nvm_spi - Read EEPROM's using SPI | |
322 | * @hw: pointer to the HW structure | |
323 | * @offset: offset of word in the EEPROM to read | |
324 | * @words: number of words to read | |
325 | * @data: word read from the EEPROM | |
326 | * | |
327 | * Reads a 16 bit word from the EEPROM. | |
328 | **/ | |
329 | s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
330 | { | |
331 | struct e1000_nvm_info *nvm = &hw->nvm; | |
332 | u32 i = 0; | |
333 | s32 ret_val; | |
334 | u16 word_in; | |
335 | u8 read_opcode = NVM_READ_OPCODE_SPI; | |
336 | ||
b980ac18 | 337 | /* A check for invalid values: offset too large, too many words, |
4322e561 CW |
338 | * and not enough words. |
339 | */ | |
340 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
341 | (words == 0)) { | |
342 | hw_dbg("nvm parameter(s) out of bounds\n"); | |
343 | ret_val = -E1000_ERR_NVM; | |
344 | goto out; | |
345 | } | |
346 | ||
347 | ret_val = nvm->ops.acquire(hw); | |
348 | if (ret_val) | |
349 | goto out; | |
350 | ||
351 | ret_val = igb_ready_nvm_eeprom(hw); | |
352 | if (ret_val) | |
353 | goto release; | |
354 | ||
355 | igb_standby_nvm(hw); | |
356 | ||
357 | if ((nvm->address_bits == 8) && (offset >= 128)) | |
358 | read_opcode |= NVM_A8_OPCODE_SPI; | |
359 | ||
360 | /* Send the READ command (opcode + addr) */ | |
361 | igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); | |
362 | igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); | |
363 | ||
b980ac18 | 364 | /* Read the data. SPI NVMs increment the address with each byte |
4322e561 CW |
365 | * read and will roll over if reading beyond the end. This allows |
366 | * us to read the whole NVM from any offset | |
367 | */ | |
368 | for (i = 0; i < words; i++) { | |
369 | word_in = igb_shift_in_eec_bits(hw, 16); | |
370 | data[i] = (word_in >> 8) | (word_in << 8); | |
371 | } | |
372 | ||
373 | release: | |
374 | nvm->ops.release(hw); | |
375 | ||
376 | out: | |
377 | return ret_val; | |
378 | } | |
379 | ||
9d5c8243 | 380 | /** |
733596be | 381 | * igb_read_nvm_eerd - Reads EEPROM using EERD register |
9d5c8243 AK |
382 | * @hw: pointer to the HW structure |
383 | * @offset: offset of word in the EEPROM to read | |
384 | * @words: number of words to read | |
385 | * @data: word read from the EEPROM | |
386 | * | |
387 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
388 | **/ | |
389 | s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
390 | { | |
391 | struct e1000_nvm_info *nvm = &hw->nvm; | |
392 | u32 i, eerd = 0; | |
393 | s32 ret_val = 0; | |
394 | ||
b980ac18 | 395 | /* A check for invalid values: offset too large, too many words, |
9d5c8243 AK |
396 | * and not enough words. |
397 | */ | |
398 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
399 | (words == 0)) { | |
652fff32 | 400 | hw_dbg("nvm parameter(s) out of bounds\n"); |
9d5c8243 AK |
401 | ret_val = -E1000_ERR_NVM; |
402 | goto out; | |
403 | } | |
404 | ||
405 | for (i = 0; i < words; i++) { | |
406 | eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + | |
b980ac18 | 407 | E1000_NVM_RW_REG_START; |
9d5c8243 AK |
408 | |
409 | wr32(E1000_EERD, eerd); | |
410 | ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); | |
411 | if (ret_val) | |
412 | break; | |
413 | ||
414 | data[i] = (rd32(E1000_EERD) >> | |
4322e561 | 415 | E1000_NVM_RW_REG_DATA); |
9d5c8243 AK |
416 | } |
417 | ||
418 | out: | |
419 | return ret_val; | |
420 | } | |
421 | ||
422 | /** | |
733596be | 423 | * igb_write_nvm_spi - Write to EEPROM using SPI |
9d5c8243 AK |
424 | * @hw: pointer to the HW structure |
425 | * @offset: offset within the EEPROM to be written to | |
426 | * @words: number of words to write | |
427 | * @data: 16 bit word(s) to be written to the EEPROM | |
428 | * | |
429 | * Writes data to EEPROM at offset using SPI interface. | |
430 | * | |
431 | * If e1000_update_nvm_checksum is not called after this function , the | |
432 | * EEPROM will most likley contain an invalid checksum. | |
433 | **/ | |
434 | s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |
435 | { | |
436 | struct e1000_nvm_info *nvm = &hw->nvm; | |
23e0f148 | 437 | s32 ret_val = -E1000_ERR_NVM; |
9d5c8243 AK |
438 | u16 widx = 0; |
439 | ||
b980ac18 | 440 | /* A check for invalid values: offset too large, too many words, |
9d5c8243 AK |
441 | * and not enough words. |
442 | */ | |
443 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || | |
444 | (words == 0)) { | |
652fff32 | 445 | hw_dbg("nvm parameter(s) out of bounds\n"); |
23e0f148 | 446 | return ret_val; |
9d5c8243 AK |
447 | } |
448 | ||
9d5c8243 AK |
449 | while (widx < words) { |
450 | u8 write_opcode = NVM_WRITE_OPCODE_SPI; | |
451 | ||
23e0f148 | 452 | ret_val = nvm->ops.acquire(hw); |
9d5c8243 | 453 | if (ret_val) |
23e0f148 AA |
454 | return ret_val; |
455 | ||
456 | ret_val = igb_ready_nvm_eeprom(hw); | |
457 | if (ret_val) { | |
458 | nvm->ops.release(hw); | |
459 | return ret_val; | |
460 | } | |
9d5c8243 AK |
461 | |
462 | igb_standby_nvm(hw); | |
463 | ||
464 | /* Send the WRITE ENABLE command (8 bit opcode) */ | |
465 | igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, | |
466 | nvm->opcode_bits); | |
467 | ||
468 | igb_standby_nvm(hw); | |
469 | ||
b980ac18 | 470 | /* Some SPI eeproms use the 8th address bit embedded in the |
9d5c8243 AK |
471 | * opcode |
472 | */ | |
473 | if ((nvm->address_bits == 8) && (offset >= 128)) | |
474 | write_opcode |= NVM_A8_OPCODE_SPI; | |
475 | ||
476 | /* Send the Write command (8-bit opcode + addr) */ | |
477 | igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); | |
478 | igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), | |
479 | nvm->address_bits); | |
480 | ||
481 | /* Loop to allow for up to whole page write of eeprom */ | |
482 | while (widx < words) { | |
483 | u16 word_out = data[widx]; | |
484 | word_out = (word_out >> 8) | (word_out << 8); | |
485 | igb_shift_out_eec_bits(hw, word_out, 16); | |
486 | widx++; | |
487 | ||
488 | if ((((offset + widx) * 2) % nvm->page_size) == 0) { | |
489 | igb_standby_nvm(hw); | |
490 | break; | |
491 | } | |
492 | } | |
23e0f148 AA |
493 | usleep_range(1000, 2000); |
494 | nvm->ops.release(hw); | |
9d5c8243 AK |
495 | } |
496 | ||
9d5c8243 AK |
497 | return ret_val; |
498 | } | |
499 | ||
500 | /** | |
9835fd73 | 501 | * igb_read_part_string - Read device part number |
9d5c8243 AK |
502 | * @hw: pointer to the HW structure |
503 | * @part_num: pointer to device part number | |
9835fd73 | 504 | * @part_num_size: size of part number buffer |
9d5c8243 AK |
505 | * |
506 | * Reads the product board assembly (PBA) number from the EEPROM and stores | |
507 | * the value in part_num. | |
508 | **/ | |
9835fd73 | 509 | s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size) |
9d5c8243 | 510 | { |
9835fd73 | 511 | s32 ret_val; |
9d5c8243 | 512 | u16 nvm_data; |
9835fd73 CW |
513 | u16 pointer; |
514 | u16 offset; | |
515 | u16 length; | |
516 | ||
517 | if (part_num == NULL) { | |
518 | hw_dbg("PBA string buffer was null\n"); | |
519 | ret_val = E1000_ERR_INVALID_ARGUMENT; | |
520 | goto out; | |
521 | } | |
9d5c8243 | 522 | |
312c75ae | 523 | ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); |
9d5c8243 | 524 | if (ret_val) { |
652fff32 | 525 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
526 | goto out; |
527 | } | |
9d5c8243 | 528 | |
9835fd73 | 529 | ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer); |
9d5c8243 | 530 | if (ret_val) { |
652fff32 | 531 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
532 | goto out; |
533 | } | |
9835fd73 | 534 | |
b980ac18 | 535 | /* if nvm_data is not ptr guard the PBA must be in legacy format which |
9835fd73 CW |
536 | * means pointer is actually our second data word for the PBA number |
537 | * and we can decode it into an ascii string | |
538 | */ | |
539 | if (nvm_data != NVM_PBA_PTR_GUARD) { | |
540 | hw_dbg("NVM PBA number is not stored as string\n"); | |
541 | ||
542 | /* we will need 11 characters to store the PBA */ | |
543 | if (part_num_size < 11) { | |
544 | hw_dbg("PBA string buffer too small\n"); | |
545 | return E1000_ERR_NO_SPACE; | |
546 | } | |
547 | ||
548 | /* extract hex string from data and pointer */ | |
549 | part_num[0] = (nvm_data >> 12) & 0xF; | |
550 | part_num[1] = (nvm_data >> 8) & 0xF; | |
551 | part_num[2] = (nvm_data >> 4) & 0xF; | |
552 | part_num[3] = nvm_data & 0xF; | |
553 | part_num[4] = (pointer >> 12) & 0xF; | |
554 | part_num[5] = (pointer >> 8) & 0xF; | |
555 | part_num[6] = '-'; | |
556 | part_num[7] = 0; | |
557 | part_num[8] = (pointer >> 4) & 0xF; | |
558 | part_num[9] = pointer & 0xF; | |
559 | ||
560 | /* put a null character on the end of our string */ | |
561 | part_num[10] = '\0'; | |
562 | ||
563 | /* switch all the data but the '-' to hex char */ | |
564 | for (offset = 0; offset < 10; offset++) { | |
565 | if (part_num[offset] < 0xA) | |
566 | part_num[offset] += '0'; | |
567 | else if (part_num[offset] < 0x10) | |
568 | part_num[offset] += 'A' - 0xA; | |
569 | } | |
570 | ||
571 | goto out; | |
572 | } | |
573 | ||
574 | ret_val = hw->nvm.ops.read(hw, pointer, 1, &length); | |
575 | if (ret_val) { | |
576 | hw_dbg("NVM Read Error\n"); | |
577 | goto out; | |
578 | } | |
579 | ||
580 | if (length == 0xFFFF || length == 0) { | |
581 | hw_dbg("NVM PBA number section invalid length\n"); | |
582 | ret_val = E1000_ERR_NVM_PBA_SECTION; | |
583 | goto out; | |
584 | } | |
585 | /* check if part_num buffer is big enough */ | |
586 | if (part_num_size < (((u32)length * 2) - 1)) { | |
587 | hw_dbg("PBA string buffer too small\n"); | |
588 | ret_val = E1000_ERR_NO_SPACE; | |
589 | goto out; | |
590 | } | |
591 | ||
592 | /* trim pba length from start of string */ | |
593 | pointer++; | |
594 | length--; | |
595 | ||
596 | for (offset = 0; offset < length; offset++) { | |
597 | ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data); | |
598 | if (ret_val) { | |
599 | hw_dbg("NVM Read Error\n"); | |
600 | goto out; | |
601 | } | |
602 | part_num[offset * 2] = (u8)(nvm_data >> 8); | |
603 | part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); | |
604 | } | |
605 | part_num[offset * 2] = '\0'; | |
9d5c8243 AK |
606 | |
607 | out: | |
608 | return ret_val; | |
609 | } | |
610 | ||
611 | /** | |
733596be | 612 | * igb_read_mac_addr - Read device MAC address |
9d5c8243 AK |
613 | * @hw: pointer to the HW structure |
614 | * | |
615 | * Reads the device MAC address from the EEPROM and stores the value. | |
616 | * Since devices with two ports use the same EEPROM, we increment the | |
617 | * last bit in the MAC address for the second port. | |
618 | **/ | |
619 | s32 igb_read_mac_addr(struct e1000_hw *hw) | |
620 | { | |
40a70b38 AD |
621 | u32 rar_high; |
622 | u32 rar_low; | |
623 | u16 i; | |
9d5c8243 | 624 | |
40a70b38 AD |
625 | rar_high = rd32(E1000_RAH(0)); |
626 | rar_low = rd32(E1000_RAL(0)); | |
9d5c8243 | 627 | |
40a70b38 AD |
628 | for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) |
629 | hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); | |
630 | ||
631 | for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) | |
632 | hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); | |
9d5c8243 AK |
633 | |
634 | for (i = 0; i < ETH_ALEN; i++) | |
635 | hw->mac.addr[i] = hw->mac.perm_addr[i]; | |
636 | ||
40a70b38 | 637 | return 0; |
9d5c8243 AK |
638 | } |
639 | ||
640 | /** | |
733596be | 641 | * igb_validate_nvm_checksum - Validate EEPROM checksum |
9d5c8243 AK |
642 | * @hw: pointer to the HW structure |
643 | * | |
644 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
645 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
646 | **/ | |
647 | s32 igb_validate_nvm_checksum(struct e1000_hw *hw) | |
648 | { | |
649 | s32 ret_val = 0; | |
650 | u16 checksum = 0; | |
651 | u16 i, nvm_data; | |
652 | ||
653 | for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { | |
312c75ae | 654 | ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); |
9d5c8243 | 655 | if (ret_val) { |
652fff32 | 656 | hw_dbg("NVM Read Error\n"); |
9d5c8243 AK |
657 | goto out; |
658 | } | |
659 | checksum += nvm_data; | |
660 | } | |
661 | ||
662 | if (checksum != (u16) NVM_SUM) { | |
652fff32 | 663 | hw_dbg("NVM Checksum Invalid\n"); |
9d5c8243 AK |
664 | ret_val = -E1000_ERR_NVM; |
665 | goto out; | |
666 | } | |
667 | ||
668 | out: | |
669 | return ret_val; | |
670 | } | |
671 | ||
672 | /** | |
733596be | 673 | * igb_update_nvm_checksum - Update EEPROM checksum |
9d5c8243 AK |
674 | * @hw: pointer to the HW structure |
675 | * | |
676 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
677 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
678 | * value to the EEPROM. | |
679 | **/ | |
680 | s32 igb_update_nvm_checksum(struct e1000_hw *hw) | |
681 | { | |
682 | s32 ret_val; | |
683 | u16 checksum = 0; | |
684 | u16 i, nvm_data; | |
685 | ||
686 | for (i = 0; i < NVM_CHECKSUM_REG; i++) { | |
312c75ae | 687 | ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); |
9d5c8243 | 688 | if (ret_val) { |
652fff32 | 689 | hw_dbg("NVM Read Error while updating checksum.\n"); |
9d5c8243 AK |
690 | goto out; |
691 | } | |
692 | checksum += nvm_data; | |
693 | } | |
694 | checksum = (u16) NVM_SUM - checksum; | |
312c75ae | 695 | ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); |
9d5c8243 | 696 | if (ret_val) |
652fff32 | 697 | hw_dbg("NVM Write Error while updating checksum.\n"); |
9d5c8243 AK |
698 | |
699 | out: | |
700 | return ret_val; | |
701 | } | |
0b1a6f2e CW |
702 | |
703 | /** | |
704 | * igb_get_fw_version - Get firmware version information | |
705 | * @hw: pointer to the HW structure | |
706 | * @fw_vers: pointer to output structure | |
707 | * | |
708 | * unsupported MAC types will return all 0 version structure | |
709 | **/ | |
710 | void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) | |
711 | { | |
712 | u16 eeprom_verh, eeprom_verl, comb_verh, comb_verl, comb_offset; | |
713 | u16 fw_version; | |
714 | ||
715 | memset(fw_vers, 0, sizeof(struct e1000_fw_version)); | |
716 | ||
717 | switch (hw->mac.type) { | |
718 | case e1000_i211: | |
09e77287 | 719 | igb_read_invm_version(hw, fw_vers); |
0b1a6f2e CW |
720 | return; |
721 | case e1000_82575: | |
722 | case e1000_82576: | |
723 | case e1000_82580: | |
ceb5f13b | 724 | case e1000_i354: |
0b1a6f2e CW |
725 | case e1000_i350: |
726 | case e1000_i210: | |
727 | break; | |
728 | default: | |
729 | return; | |
730 | } | |
731 | /* basic eeprom version numbers */ | |
732 | hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); | |
733 | fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; | |
734 | fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK); | |
735 | ||
736 | /* etrack id */ | |
737 | hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); | |
738 | hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); | |
739 | fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | eeprom_verl; | |
740 | ||
741 | switch (hw->mac.type) { | |
742 | case e1000_i210: | |
ceb5f13b | 743 | case e1000_i354: |
0b1a6f2e CW |
744 | case e1000_i350: |
745 | /* find combo image version */ | |
746 | hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); | |
747 | if ((comb_offset != 0x0) && (comb_offset != NVM_VER_INVALID)) { | |
748 | ||
749 | hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset | |
750 | + 1), 1, &comb_verh); | |
751 | hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), | |
752 | 1, &comb_verl); | |
753 | ||
754 | /* get Option Rom version if it exists and is valid */ | |
755 | if ((comb_verh && comb_verl) && | |
756 | ((comb_verh != NVM_VER_INVALID) && | |
757 | (comb_verl != NVM_VER_INVALID))) { | |
758 | ||
759 | fw_vers->or_valid = true; | |
760 | fw_vers->or_major = | |
761 | comb_verl >> NVM_COMB_VER_SHFT; | |
762 | fw_vers->or_build = | |
763 | ((comb_verl << NVM_COMB_VER_SHFT) | |
764 | | (comb_verh >> NVM_COMB_VER_SHFT)); | |
765 | fw_vers->or_patch = | |
766 | comb_verh & NVM_COMB_VER_MASK; | |
767 | } | |
768 | } | |
769 | break; | |
770 | default: | |
771 | break; | |
772 | } | |
773 | return; | |
774 | } |