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e52c0f96 CW |
1 | /* Intel(R) Gigabit Ethernet Linux driver |
2 | * Copyright(c) 2007-2014 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, see <http://www.gnu.org/licenses/>. | |
15 | * | |
16 | * The full GNU General Public License is included in this distribution in | |
17 | * the file called "COPYING". | |
18 | * | |
19 | * Contact Information: | |
20 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
21 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
22 | */ | |
9d5c8243 AK |
23 | |
24 | #include <linux/if_ether.h> | |
25 | #include <linux/delay.h> | |
26 | ||
27 | #include "e1000_mac.h" | |
28 | #include "e1000_phy.h" | |
29 | ||
9d5c8243 AK |
30 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); |
31 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, | |
b980ac18 | 32 | u16 *phy_ctrl); |
9d5c8243 | 33 | static s32 igb_wait_autoneg(struct e1000_hw *hw); |
f96a8a0b | 34 | static s32 igb_set_master_slave_mode(struct e1000_hw *hw); |
9d5c8243 AK |
35 | |
36 | /* Cable length tables */ | |
b980ac18 JK |
37 | static const u16 e1000_m88_cable_length_table[] = { |
38 | 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
2553bb26 | 39 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
b980ac18 JK |
40 | (sizeof(e1000_m88_cable_length_table) / \ |
41 | sizeof(e1000_m88_cable_length_table[0])) | |
42 | ||
43 | static const u16 e1000_igp_2_cable_length_table[] = { | |
44 | 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, | |
45 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, | |
46 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, | |
47 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, | |
48 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, | |
49 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, | |
50 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, | |
51 | 104, 109, 114, 118, 121, 124}; | |
9d5c8243 | 52 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
b980ac18 JK |
53 | (sizeof(e1000_igp_2_cable_length_table) / \ |
54 | sizeof(e1000_igp_2_cable_length_table[0])) | |
9d5c8243 AK |
55 | |
56 | /** | |
733596be | 57 | * igb_check_reset_block - Check if PHY reset is blocked |
9d5c8243 AK |
58 | * @hw: pointer to the HW structure |
59 | * | |
60 | * Read the PHY management control register and check whether a PHY reset | |
61 | * is blocked. If a reset is not blocked return 0, otherwise | |
62 | * return E1000_BLK_PHY_RESET (12). | |
63 | **/ | |
64 | s32 igb_check_reset_block(struct e1000_hw *hw) | |
65 | { | |
66 | u32 manc; | |
67 | ||
68 | manc = rd32(E1000_MANC); | |
69 | ||
b980ac18 | 70 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; |
9d5c8243 AK |
71 | } |
72 | ||
73 | /** | |
733596be | 74 | * igb_get_phy_id - Retrieve the PHY ID and revision |
9d5c8243 AK |
75 | * @hw: pointer to the HW structure |
76 | * | |
77 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
78 | * revision in the hardware structure. | |
79 | **/ | |
80 | s32 igb_get_phy_id(struct e1000_hw *hw) | |
81 | { | |
82 | struct e1000_phy_info *phy = &hw->phy; | |
83 | s32 ret_val = 0; | |
84 | u16 phy_id; | |
85 | ||
a8d2a0c2 | 86 | ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); |
9d5c8243 AK |
87 | if (ret_val) |
88 | goto out; | |
89 | ||
90 | phy->id = (u32)(phy_id << 16); | |
91 | udelay(20); | |
a8d2a0c2 | 92 | ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); |
9d5c8243 AK |
93 | if (ret_val) |
94 | goto out; | |
95 | ||
96 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); | |
97 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
98 | ||
99 | out: | |
100 | return ret_val; | |
101 | } | |
102 | ||
103 | /** | |
733596be | 104 | * igb_phy_reset_dsp - Reset PHY DSP |
9d5c8243 AK |
105 | * @hw: pointer to the HW structure |
106 | * | |
107 | * Reset the digital signal processor. | |
108 | **/ | |
109 | static s32 igb_phy_reset_dsp(struct e1000_hw *hw) | |
110 | { | |
2553bb26 AD |
111 | s32 ret_val = 0; |
112 | ||
113 | if (!(hw->phy.ops.write_reg)) | |
114 | goto out; | |
9d5c8243 | 115 | |
a8d2a0c2 | 116 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); |
9d5c8243 AK |
117 | if (ret_val) |
118 | goto out; | |
119 | ||
a8d2a0c2 | 120 | ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); |
9d5c8243 AK |
121 | |
122 | out: | |
123 | return ret_val; | |
124 | } | |
125 | ||
126 | /** | |
733596be | 127 | * igb_read_phy_reg_mdic - Read MDI control register |
9d5c8243 AK |
128 | * @hw: pointer to the HW structure |
129 | * @offset: register offset to be read | |
130 | * @data: pointer to the read data | |
131 | * | |
132 | * Reads the MDI control regsiter in the PHY at offset and stores the | |
133 | * information read to data. | |
134 | **/ | |
bb2ac47b | 135 | s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
9d5c8243 AK |
136 | { |
137 | struct e1000_phy_info *phy = &hw->phy; | |
138 | u32 i, mdic = 0; | |
139 | s32 ret_val = 0; | |
140 | ||
141 | if (offset > MAX_PHY_REG_ADDRESS) { | |
652fff32 | 142 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
143 | ret_val = -E1000_ERR_PARAM; |
144 | goto out; | |
145 | } | |
146 | ||
b980ac18 | 147 | /* Set up Op-code, Phy Address, and register offset in the MDI |
9d5c8243 AK |
148 | * Control register. The MAC will take care of interfacing with the |
149 | * PHY to retrieve the desired data. | |
150 | */ | |
151 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
152 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
153 | (E1000_MDIC_OP_READ)); | |
154 | ||
155 | wr32(E1000_MDIC, mdic); | |
156 | ||
b980ac18 | 157 | /* Poll the ready bit to see if the MDI read completed |
9d5c8243 AK |
158 | * Increasing the time out as testing showed failures with |
159 | * the lower time out | |
160 | */ | |
161 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
162 | udelay(50); | |
163 | mdic = rd32(E1000_MDIC); | |
164 | if (mdic & E1000_MDIC_READY) | |
165 | break; | |
166 | } | |
167 | if (!(mdic & E1000_MDIC_READY)) { | |
652fff32 | 168 | hw_dbg("MDI Read did not complete\n"); |
9d5c8243 AK |
169 | ret_val = -E1000_ERR_PHY; |
170 | goto out; | |
171 | } | |
172 | if (mdic & E1000_MDIC_ERROR) { | |
652fff32 | 173 | hw_dbg("MDI Error\n"); |
9d5c8243 AK |
174 | ret_val = -E1000_ERR_PHY; |
175 | goto out; | |
176 | } | |
177 | *data = (u16) mdic; | |
178 | ||
179 | out: | |
180 | return ret_val; | |
181 | } | |
182 | ||
183 | /** | |
733596be | 184 | * igb_write_phy_reg_mdic - Write MDI control register |
9d5c8243 AK |
185 | * @hw: pointer to the HW structure |
186 | * @offset: register offset to write to | |
187 | * @data: data to write to register at offset | |
188 | * | |
189 | * Writes data to MDI control register in the PHY at offset. | |
190 | **/ | |
bb2ac47b | 191 | s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
9d5c8243 AK |
192 | { |
193 | struct e1000_phy_info *phy = &hw->phy; | |
194 | u32 i, mdic = 0; | |
195 | s32 ret_val = 0; | |
196 | ||
197 | if (offset > MAX_PHY_REG_ADDRESS) { | |
652fff32 | 198 | hw_dbg("PHY Address %d is out of range\n", offset); |
9d5c8243 AK |
199 | ret_val = -E1000_ERR_PARAM; |
200 | goto out; | |
201 | } | |
202 | ||
b980ac18 | 203 | /* Set up Op-code, Phy Address, and register offset in the MDI |
9d5c8243 AK |
204 | * Control register. The MAC will take care of interfacing with the |
205 | * PHY to retrieve the desired data. | |
206 | */ | |
207 | mdic = (((u32)data) | | |
208 | (offset << E1000_MDIC_REG_SHIFT) | | |
209 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
210 | (E1000_MDIC_OP_WRITE)); | |
211 | ||
212 | wr32(E1000_MDIC, mdic); | |
213 | ||
b980ac18 | 214 | /* Poll the ready bit to see if the MDI read completed |
9d5c8243 AK |
215 | * Increasing the time out as testing showed failures with |
216 | * the lower time out | |
217 | */ | |
218 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
219 | udelay(50); | |
220 | mdic = rd32(E1000_MDIC); | |
221 | if (mdic & E1000_MDIC_READY) | |
222 | break; | |
223 | } | |
224 | if (!(mdic & E1000_MDIC_READY)) { | |
652fff32 | 225 | hw_dbg("MDI Write did not complete\n"); |
9d5c8243 AK |
226 | ret_val = -E1000_ERR_PHY; |
227 | goto out; | |
228 | } | |
229 | if (mdic & E1000_MDIC_ERROR) { | |
652fff32 | 230 | hw_dbg("MDI Error\n"); |
9d5c8243 AK |
231 | ret_val = -E1000_ERR_PHY; |
232 | goto out; | |
233 | } | |
234 | ||
235 | out: | |
236 | return ret_val; | |
237 | } | |
238 | ||
bf6f7a92 AD |
239 | /** |
240 | * igb_read_phy_reg_i2c - Read PHY register using i2c | |
241 | * @hw: pointer to the HW structure | |
242 | * @offset: register offset to be read | |
243 | * @data: pointer to the read data | |
244 | * | |
245 | * Reads the PHY register at offset using the i2c interface and stores the | |
246 | * retrieved information in data. | |
247 | **/ | |
248 | s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) | |
249 | { | |
250 | struct e1000_phy_info *phy = &hw->phy; | |
251 | u32 i, i2ccmd = 0; | |
252 | ||
b980ac18 | 253 | /* Set up Op-code, Phy Address, and register address in the I2CCMD |
bf6f7a92 AD |
254 | * register. The MAC will take care of interfacing with the |
255 | * PHY to retrieve the desired data. | |
256 | */ | |
257 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
b980ac18 JK |
258 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | |
259 | (E1000_I2CCMD_OPCODE_READ)); | |
bf6f7a92 AD |
260 | |
261 | wr32(E1000_I2CCMD, i2ccmd); | |
262 | ||
263 | /* Poll the ready bit to see if the I2C read completed */ | |
264 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
265 | udelay(50); | |
266 | i2ccmd = rd32(E1000_I2CCMD); | |
267 | if (i2ccmd & E1000_I2CCMD_READY) | |
268 | break; | |
269 | } | |
270 | if (!(i2ccmd & E1000_I2CCMD_READY)) { | |
271 | hw_dbg("I2CCMD Read did not complete\n"); | |
272 | return -E1000_ERR_PHY; | |
273 | } | |
274 | if (i2ccmd & E1000_I2CCMD_ERROR) { | |
275 | hw_dbg("I2CCMD Error bit set\n"); | |
276 | return -E1000_ERR_PHY; | |
277 | } | |
278 | ||
279 | /* Need to byte-swap the 16-bit value. */ | |
280 | *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
285 | /** | |
286 | * igb_write_phy_reg_i2c - Write PHY register using i2c | |
287 | * @hw: pointer to the HW structure | |
288 | * @offset: register offset to write to | |
289 | * @data: data to write at register offset | |
290 | * | |
291 | * Writes the data to PHY register at the offset using the i2c interface. | |
292 | **/ | |
293 | s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) | |
294 | { | |
295 | struct e1000_phy_info *phy = &hw->phy; | |
296 | u32 i, i2ccmd = 0; | |
297 | u16 phy_data_swapped; | |
298 | ||
76d06521 AA |
299 | /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ |
300 | if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { | |
301 | hw_dbg("PHY I2C Address %d is out of range.\n", | |
302 | hw->phy.addr); | |
303 | return -E1000_ERR_CONFIG; | |
304 | } | |
bf6f7a92 AD |
305 | |
306 | /* Swap the data bytes for the I2C interface */ | |
307 | phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); | |
308 | ||
b980ac18 | 309 | /* Set up Op-code, Phy Address, and register address in the I2CCMD |
bf6f7a92 AD |
310 | * register. The MAC will take care of interfacing with the |
311 | * PHY to retrieve the desired data. | |
312 | */ | |
313 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
b980ac18 JK |
314 | (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | |
315 | E1000_I2CCMD_OPCODE_WRITE | | |
316 | phy_data_swapped); | |
bf6f7a92 AD |
317 | |
318 | wr32(E1000_I2CCMD, i2ccmd); | |
319 | ||
320 | /* Poll the ready bit to see if the I2C read completed */ | |
321 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
322 | udelay(50); | |
323 | i2ccmd = rd32(E1000_I2CCMD); | |
324 | if (i2ccmd & E1000_I2CCMD_READY) | |
325 | break; | |
326 | } | |
327 | if (!(i2ccmd & E1000_I2CCMD_READY)) { | |
328 | hw_dbg("I2CCMD Write did not complete\n"); | |
329 | return -E1000_ERR_PHY; | |
330 | } | |
331 | if (i2ccmd & E1000_I2CCMD_ERROR) { | |
332 | hw_dbg("I2CCMD Error bit set\n"); | |
333 | return -E1000_ERR_PHY; | |
334 | } | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
641ac5c0 AA |
339 | /** |
340 | * igb_read_sfp_data_byte - Reads SFP module data. | |
341 | * @hw: pointer to the HW structure | |
342 | * @offset: byte location offset to be read | |
343 | * @data: read data buffer pointer | |
344 | * | |
345 | * Reads one byte from SFP module data stored | |
346 | * in SFP resided EEPROM memory or SFP diagnostic area. | |
347 | * Function should be called with | |
348 | * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access | |
349 | * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters | |
350 | * access | |
351 | **/ | |
352 | s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) | |
353 | { | |
354 | u32 i = 0; | |
355 | u32 i2ccmd = 0; | |
356 | u32 data_local = 0; | |
357 | ||
358 | if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { | |
359 | hw_dbg("I2CCMD command address exceeds upper limit\n"); | |
360 | return -E1000_ERR_PHY; | |
361 | } | |
362 | ||
363 | /* Set up Op-code, EEPROM Address,in the I2CCMD | |
364 | * register. The MAC will take care of interfacing with the | |
365 | * EEPROM to retrieve the desired data. | |
366 | */ | |
367 | i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | | |
368 | E1000_I2CCMD_OPCODE_READ); | |
369 | ||
370 | wr32(E1000_I2CCMD, i2ccmd); | |
371 | ||
372 | /* Poll the ready bit to see if the I2C read completed */ | |
373 | for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { | |
374 | udelay(50); | |
375 | data_local = rd32(E1000_I2CCMD); | |
376 | if (data_local & E1000_I2CCMD_READY) | |
377 | break; | |
378 | } | |
379 | if (!(data_local & E1000_I2CCMD_READY)) { | |
380 | hw_dbg("I2CCMD Read did not complete\n"); | |
381 | return -E1000_ERR_PHY; | |
382 | } | |
383 | if (data_local & E1000_I2CCMD_ERROR) { | |
384 | hw_dbg("I2CCMD Error bit set\n"); | |
385 | return -E1000_ERR_PHY; | |
386 | } | |
387 | *data = (u8) data_local & 0xFF; | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
9d5c8243 | 392 | /** |
733596be | 393 | * igb_read_phy_reg_igp - Read igp PHY register |
9d5c8243 AK |
394 | * @hw: pointer to the HW structure |
395 | * @offset: register offset to be read | |
396 | * @data: pointer to the read data | |
397 | * | |
398 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
399 | * and storing the retrieved information in data. Release any acquired | |
400 | * semaphores before exiting. | |
401 | **/ | |
402 | s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
403 | { | |
a8d2a0c2 AD |
404 | s32 ret_val = 0; |
405 | ||
406 | if (!(hw->phy.ops.acquire)) | |
407 | goto out; | |
9d5c8243 | 408 | |
a8d2a0c2 | 409 | ret_val = hw->phy.ops.acquire(hw); |
9d5c8243 AK |
410 | if (ret_val) |
411 | goto out; | |
412 | ||
413 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
414 | ret_val = igb_write_phy_reg_mdic(hw, | |
b980ac18 JK |
415 | IGP01E1000_PHY_PAGE_SELECT, |
416 | (u16)offset); | |
9d5c8243 | 417 | if (ret_val) { |
a8d2a0c2 | 418 | hw->phy.ops.release(hw); |
9d5c8243 AK |
419 | goto out; |
420 | } | |
421 | } | |
422 | ||
a8d2a0c2 AD |
423 | ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
424 | data); | |
9d5c8243 | 425 | |
a8d2a0c2 | 426 | hw->phy.ops.release(hw); |
9d5c8243 AK |
427 | |
428 | out: | |
429 | return ret_val; | |
430 | } | |
431 | ||
432 | /** | |
733596be | 433 | * igb_write_phy_reg_igp - Write igp PHY register |
9d5c8243 AK |
434 | * @hw: pointer to the HW structure |
435 | * @offset: register offset to write to | |
436 | * @data: data to write at register offset | |
437 | * | |
438 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
439 | * at the offset. Release any acquired semaphores before exiting. | |
440 | **/ | |
441 | s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
442 | { | |
a8d2a0c2 | 443 | s32 ret_val = 0; |
9d5c8243 | 444 | |
a8d2a0c2 AD |
445 | if (!(hw->phy.ops.acquire)) |
446 | goto out; | |
447 | ||
448 | ret_val = hw->phy.ops.acquire(hw); | |
9d5c8243 AK |
449 | if (ret_val) |
450 | goto out; | |
451 | ||
452 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
453 | ret_val = igb_write_phy_reg_mdic(hw, | |
b980ac18 JK |
454 | IGP01E1000_PHY_PAGE_SELECT, |
455 | (u16)offset); | |
9d5c8243 | 456 | if (ret_val) { |
a8d2a0c2 | 457 | hw->phy.ops.release(hw); |
9d5c8243 AK |
458 | goto out; |
459 | } | |
460 | } | |
461 | ||
a8d2a0c2 | 462 | ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
b980ac18 | 463 | data); |
9d5c8243 | 464 | |
a8d2a0c2 | 465 | hw->phy.ops.release(hw); |
9d5c8243 AK |
466 | |
467 | out: | |
468 | return ret_val; | |
469 | } | |
470 | ||
2909c3f7 AD |
471 | /** |
472 | * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link | |
473 | * @hw: pointer to the HW structure | |
474 | * | |
475 | * Sets up Carrier-sense on Transmit and downshift values. | |
476 | **/ | |
477 | s32 igb_copper_link_setup_82580(struct e1000_hw *hw) | |
478 | { | |
479 | struct e1000_phy_info *phy = &hw->phy; | |
480 | s32 ret_val; | |
481 | u16 phy_data; | |
482 | ||
2909c3f7 AD |
483 | if (phy->reset_disable) { |
484 | ret_val = 0; | |
485 | goto out; | |
486 | } | |
487 | ||
488 | if (phy->type == e1000_phy_82580) { | |
489 | ret_val = hw->phy.ops.reset(hw); | |
490 | if (ret_val) { | |
491 | hw_dbg("Error resetting the PHY.\n"); | |
492 | goto out; | |
493 | } | |
494 | } | |
495 | ||
496 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
497 | ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); | |
498 | if (ret_val) | |
499 | goto out; | |
500 | ||
501 | phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; | |
502 | ||
503 | /* Enable downshift */ | |
504 | phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; | |
505 | ||
506 | ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); | |
1b556783 JB |
507 | if (ret_val) |
508 | goto out; | |
509 | ||
510 | /* Set MDI/MDIX mode */ | |
511 | ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); | |
512 | if (ret_val) | |
513 | goto out; | |
514 | phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; | |
b980ac18 | 515 | /* Options: |
1b556783 JB |
516 | * 0 - Auto (default) |
517 | * 1 - MDI mode | |
518 | * 2 - MDI-X mode | |
519 | */ | |
520 | switch (hw->phy.mdix) { | |
521 | case 1: | |
522 | break; | |
523 | case 2: | |
524 | phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; | |
525 | break; | |
526 | case 0: | |
527 | default: | |
528 | phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; | |
529 | break; | |
530 | } | |
531 | ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); | |
2909c3f7 AD |
532 | |
533 | out: | |
534 | return ret_val; | |
535 | } | |
536 | ||
9d5c8243 | 537 | /** |
733596be | 538 | * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link |
9d5c8243 AK |
539 | * @hw: pointer to the HW structure |
540 | * | |
541 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
542 | * and downshift values are set also. | |
543 | **/ | |
544 | s32 igb_copper_link_setup_m88(struct e1000_hw *hw) | |
545 | { | |
546 | struct e1000_phy_info *phy = &hw->phy; | |
547 | s32 ret_val; | |
548 | u16 phy_data; | |
549 | ||
550 | if (phy->reset_disable) { | |
551 | ret_val = 0; | |
552 | goto out; | |
553 | } | |
554 | ||
555 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
a8d2a0c2 | 556 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
557 | if (ret_val) |
558 | goto out; | |
559 | ||
560 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
561 | ||
b980ac18 | 562 | /* Options: |
9d5c8243 AK |
563 | * MDI/MDI-X = 0 (default) |
564 | * 0 - Auto for all speeds | |
565 | * 1 - MDI mode | |
566 | * 2 - MDI-X mode | |
567 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
568 | */ | |
569 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
570 | ||
571 | switch (phy->mdix) { | |
572 | case 1: | |
573 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
574 | break; | |
575 | case 2: | |
576 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
577 | break; | |
578 | case 3: | |
579 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
580 | break; | |
581 | case 0: | |
582 | default: | |
583 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
584 | break; | |
585 | } | |
586 | ||
b980ac18 | 587 | /* Options: |
9d5c8243 AK |
588 | * disable_polarity_correction = 0 (default) |
589 | * Automatic Correction for Reversed Cable Polarity | |
590 | * 0 - Disabled | |
591 | * 1 - Enabled | |
592 | */ | |
593 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
594 | if (phy->disable_polarity_correction == 1) | |
595 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
596 | ||
a8d2a0c2 | 597 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
598 | if (ret_val) |
599 | goto out; | |
600 | ||
601 | if (phy->revision < E1000_REVISION_4) { | |
b980ac18 | 602 | /* Force TX_CLK in the Extended PHY Specific Control Register |
9d5c8243 AK |
603 | * to 25MHz clock. |
604 | */ | |
a8d2a0c2 | 605 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
b980ac18 | 606 | &phy_data); |
9d5c8243 AK |
607 | if (ret_val) |
608 | goto out; | |
609 | ||
610 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
611 | ||
612 | if ((phy->revision == E1000_REVISION_2) && | |
613 | (phy->id == M88E1111_I_PHY_ID)) { | |
614 | /* 82573L PHY - set the downshift counter to 5x. */ | |
615 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
616 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
617 | } else { | |
618 | /* Configure Master and Slave downshift values */ | |
619 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
620 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
621 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
622 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
623 | } | |
a8d2a0c2 | 624 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
9d5c8243 AK |
625 | phy_data); |
626 | if (ret_val) | |
627 | goto out; | |
628 | } | |
629 | ||
630 | /* Commit the changes. */ | |
631 | ret_val = igb_phy_sw_reset(hw); | |
632 | if (ret_val) { | |
652fff32 | 633 | hw_dbg("Error committing the PHY changes\n"); |
9d5c8243 AK |
634 | goto out; |
635 | } | |
636 | ||
637 | out: | |
638 | return ret_val; | |
639 | } | |
640 | ||
308fb39a JG |
641 | /** |
642 | * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link | |
643 | * @hw: pointer to the HW structure | |
644 | * | |
645 | * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. | |
646 | * Also enables and sets the downshift parameters. | |
647 | **/ | |
648 | s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) | |
649 | { | |
650 | struct e1000_phy_info *phy = &hw->phy; | |
651 | s32 ret_val; | |
652 | u16 phy_data; | |
653 | ||
dfc70755 AA |
654 | if (phy->reset_disable) |
655 | return 0; | |
308fb39a JG |
656 | |
657 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ | |
658 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
659 | if (ret_val) | |
dfc70755 | 660 | return ret_val; |
308fb39a | 661 | |
b980ac18 | 662 | /* Options: |
308fb39a JG |
663 | * MDI/MDI-X = 0 (default) |
664 | * 0 - Auto for all speeds | |
665 | * 1 - MDI mode | |
666 | * 2 - MDI-X mode | |
667 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
668 | */ | |
669 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
670 | ||
671 | switch (phy->mdix) { | |
672 | case 1: | |
673 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
674 | break; | |
675 | case 2: | |
676 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
677 | break; | |
678 | case 3: | |
679 | /* M88E1112 does not support this mode) */ | |
680 | if (phy->id != M88E1112_E_PHY_ID) { | |
681 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
682 | break; | |
683 | } | |
684 | case 0: | |
685 | default: | |
686 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
687 | break; | |
688 | } | |
689 | ||
b980ac18 | 690 | /* Options: |
308fb39a JG |
691 | * disable_polarity_correction = 0 (default) |
692 | * Automatic Correction for Reversed Cable Polarity | |
693 | * 0 - Disabled | |
694 | * 1 - Enabled | |
695 | */ | |
696 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
697 | if (phy->disable_polarity_correction == 1) | |
698 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
699 | ||
700 | /* Enable downshift and setting it to X6 */ | |
dfc70755 AA |
701 | if (phy->id == M88E1543_E_PHY_ID) { |
702 | phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; | |
703 | ret_val = | |
704 | phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
705 | if (ret_val) | |
706 | return ret_val; | |
707 | ||
708 | ret_val = igb_phy_sw_reset(hw); | |
709 | if (ret_val) { | |
710 | hw_dbg("Error committing the PHY changes\n"); | |
711 | return ret_val; | |
712 | } | |
713 | } | |
714 | ||
308fb39a JG |
715 | phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; |
716 | phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; | |
717 | phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; | |
718 | ||
719 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
720 | if (ret_val) | |
dfc70755 | 721 | return ret_val; |
308fb39a JG |
722 | |
723 | /* Commit the changes. */ | |
724 | ret_val = igb_phy_sw_reset(hw); | |
725 | if (ret_val) { | |
726 | hw_dbg("Error committing the PHY changes\n"); | |
dfc70755 | 727 | return ret_val; |
308fb39a | 728 | } |
d1c17d80 CW |
729 | ret_val = igb_set_master_slave_mode(hw); |
730 | if (ret_val) | |
731 | return ret_val; | |
308fb39a | 732 | |
dfc70755 | 733 | return 0; |
308fb39a JG |
734 | } |
735 | ||
9d5c8243 | 736 | /** |
733596be | 737 | * igb_copper_link_setup_igp - Setup igp PHY's for copper link |
9d5c8243 AK |
738 | * @hw: pointer to the HW structure |
739 | * | |
740 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
741 | * igp PHY's. | |
742 | **/ | |
743 | s32 igb_copper_link_setup_igp(struct e1000_hw *hw) | |
744 | { | |
745 | struct e1000_phy_info *phy = &hw->phy; | |
746 | s32 ret_val; | |
747 | u16 data; | |
748 | ||
749 | if (phy->reset_disable) { | |
750 | ret_val = 0; | |
751 | goto out; | |
752 | } | |
753 | ||
a8d2a0c2 | 754 | ret_val = phy->ops.reset(hw); |
9d5c8243 | 755 | if (ret_val) { |
652fff32 | 756 | hw_dbg("Error resetting the PHY.\n"); |
9d5c8243 AK |
757 | goto out; |
758 | } | |
759 | ||
b980ac18 | 760 | /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
a6a60569 AD |
761 | * timeout issues when LFS is enabled. |
762 | */ | |
763 | msleep(100); | |
9d5c8243 | 764 | |
b980ac18 | 765 | /* The NVM settings will configure LPLU in D3 for |
9d5c8243 AK |
766 | * non-IGP1 PHYs. |
767 | */ | |
768 | if (phy->type == e1000_phy_igp) { | |
769 | /* disable lplu d3 during driver init */ | |
a8d2a0c2 AD |
770 | if (phy->ops.set_d3_lplu_state) |
771 | ret_val = phy->ops.set_d3_lplu_state(hw, false); | |
9d5c8243 | 772 | if (ret_val) { |
652fff32 | 773 | hw_dbg("Error Disabling LPLU D3\n"); |
9d5c8243 AK |
774 | goto out; |
775 | } | |
776 | } | |
777 | ||
778 | /* disable lplu d0 during driver init */ | |
a8d2a0c2 | 779 | ret_val = phy->ops.set_d0_lplu_state(hw, false); |
9d5c8243 | 780 | if (ret_val) { |
652fff32 | 781 | hw_dbg("Error Disabling LPLU D0\n"); |
9d5c8243 AK |
782 | goto out; |
783 | } | |
784 | /* Configure mdi-mdix settings */ | |
a8d2a0c2 | 785 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); |
9d5c8243 AK |
786 | if (ret_val) |
787 | goto out; | |
788 | ||
789 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
790 | ||
791 | switch (phy->mdix) { | |
792 | case 1: | |
793 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
794 | break; | |
795 | case 2: | |
796 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
797 | break; | |
798 | case 0: | |
799 | default: | |
800 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
801 | break; | |
802 | } | |
a8d2a0c2 | 803 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); |
9d5c8243 AK |
804 | if (ret_val) |
805 | goto out; | |
806 | ||
807 | /* set auto-master slave resolution settings */ | |
808 | if (hw->mac.autoneg) { | |
b980ac18 | 809 | /* when autonegotiation advertisement is only 1000Mbps then we |
9d5c8243 AK |
810 | * should disable SmartSpeed and enable Auto MasterSlave |
811 | * resolution as hardware default. | |
812 | */ | |
813 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { | |
814 | /* Disable SmartSpeed */ | |
a8d2a0c2 AD |
815 | ret_val = phy->ops.read_reg(hw, |
816 | IGP01E1000_PHY_PORT_CONFIG, | |
817 | &data); | |
9d5c8243 AK |
818 | if (ret_val) |
819 | goto out; | |
820 | ||
821 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 822 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
823 | IGP01E1000_PHY_PORT_CONFIG, |
824 | data); | |
825 | if (ret_val) | |
826 | goto out; | |
827 | ||
828 | /* Set auto Master/Slave resolution process */ | |
a8d2a0c2 | 829 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
9d5c8243 AK |
830 | if (ret_val) |
831 | goto out; | |
832 | ||
833 | data &= ~CR_1000T_MS_ENABLE; | |
a8d2a0c2 | 834 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
9d5c8243 AK |
835 | if (ret_val) |
836 | goto out; | |
837 | } | |
838 | ||
a8d2a0c2 | 839 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); |
9d5c8243 AK |
840 | if (ret_val) |
841 | goto out; | |
842 | ||
843 | /* load defaults for future use */ | |
844 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? | |
845 | ((data & CR_1000T_MS_VALUE) ? | |
846 | e1000_ms_force_master : | |
847 | e1000_ms_force_slave) : | |
848 | e1000_ms_auto; | |
849 | ||
850 | switch (phy->ms_type) { | |
851 | case e1000_ms_force_master: | |
852 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
853 | break; | |
854 | case e1000_ms_force_slave: | |
855 | data |= CR_1000T_MS_ENABLE; | |
856 | data &= ~(CR_1000T_MS_VALUE); | |
857 | break; | |
858 | case e1000_ms_auto: | |
859 | data &= ~CR_1000T_MS_ENABLE; | |
860 | default: | |
861 | break; | |
862 | } | |
a8d2a0c2 | 863 | ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); |
9d5c8243 AK |
864 | if (ret_val) |
865 | goto out; | |
866 | } | |
867 | ||
868 | out: | |
869 | return ret_val; | |
870 | } | |
871 | ||
872 | /** | |
733596be | 873 | * igb_copper_link_autoneg - Setup/Enable autoneg for copper link |
9d5c8243 AK |
874 | * @hw: pointer to the HW structure |
875 | * | |
876 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
877 | * configure to advertise the full capability. Setup the PHY to autoneg | |
878 | * and restart the negotiation process between the link partner. If | |
879 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. | |
880 | **/ | |
81fadd81 | 881 | static s32 igb_copper_link_autoneg(struct e1000_hw *hw) |
9d5c8243 AK |
882 | { |
883 | struct e1000_phy_info *phy = &hw->phy; | |
884 | s32 ret_val; | |
885 | u16 phy_ctrl; | |
886 | ||
b980ac18 | 887 | /* Perform some bounds checking on the autoneg advertisement |
9d5c8243 AK |
888 | * parameter. |
889 | */ | |
890 | phy->autoneg_advertised &= phy->autoneg_mask; | |
891 | ||
b980ac18 | 892 | /* If autoneg_advertised is zero, we assume it was not defaulted |
9d5c8243 AK |
893 | * by the calling code so we set to advertise full capability. |
894 | */ | |
895 | if (phy->autoneg_advertised == 0) | |
896 | phy->autoneg_advertised = phy->autoneg_mask; | |
897 | ||
652fff32 | 898 | hw_dbg("Reconfiguring auto-neg advertisement params\n"); |
9d5c8243 AK |
899 | ret_val = igb_phy_setup_autoneg(hw); |
900 | if (ret_val) { | |
652fff32 | 901 | hw_dbg("Error Setting up Auto-Negotiation\n"); |
9d5c8243 AK |
902 | goto out; |
903 | } | |
652fff32 | 904 | hw_dbg("Restarting Auto-Neg\n"); |
9d5c8243 | 905 | |
b980ac18 | 906 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
9d5c8243 AK |
907 | * the Auto Neg Restart bit in the PHY control register. |
908 | */ | |
a8d2a0c2 | 909 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
9d5c8243 AK |
910 | if (ret_val) |
911 | goto out; | |
912 | ||
913 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | |
a8d2a0c2 | 914 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
9d5c8243 AK |
915 | if (ret_val) |
916 | goto out; | |
917 | ||
b980ac18 | 918 | /* Does the user want to wait for Auto-Neg to complete here, or |
9d5c8243 AK |
919 | * check at a later time (for example, callback routine). |
920 | */ | |
921 | if (phy->autoneg_wait_to_complete) { | |
922 | ret_val = igb_wait_autoneg(hw); | |
923 | if (ret_val) { | |
c75c4edf | 924 | hw_dbg("Error while waiting for autoneg to complete\n"); |
9d5c8243 AK |
925 | goto out; |
926 | } | |
927 | } | |
928 | ||
929 | hw->mac.get_link_status = true; | |
930 | ||
931 | out: | |
932 | return ret_val; | |
933 | } | |
934 | ||
935 | /** | |
733596be | 936 | * igb_phy_setup_autoneg - Configure PHY for auto-negotiation |
9d5c8243 AK |
937 | * @hw: pointer to the HW structure |
938 | * | |
939 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
940 | * register and if the PHY is already setup for auto-negotiation, then | |
941 | * return successful. Otherwise, setup advertisement and flow control to | |
942 | * the appropriate values for the wanted auto-negotiation. | |
943 | **/ | |
944 | static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) | |
945 | { | |
946 | struct e1000_phy_info *phy = &hw->phy; | |
947 | s32 ret_val; | |
948 | u16 mii_autoneg_adv_reg; | |
949 | u16 mii_1000t_ctrl_reg = 0; | |
950 | ||
951 | phy->autoneg_advertised &= phy->autoneg_mask; | |
952 | ||
953 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
a8d2a0c2 | 954 | ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
9d5c8243 AK |
955 | if (ret_val) |
956 | goto out; | |
957 | ||
958 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
959 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
a8d2a0c2 | 960 | ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, |
9d5c8243 AK |
961 | &mii_1000t_ctrl_reg); |
962 | if (ret_val) | |
963 | goto out; | |
964 | } | |
965 | ||
b980ac18 | 966 | /* Need to parse both autoneg_advertised and fc and set up |
9d5c8243 AK |
967 | * the appropriate PHY registers. First we will parse for |
968 | * autoneg_advertised software override. Since we can advertise | |
969 | * a plethora of combinations, we need to check each bit | |
970 | * individually. | |
971 | */ | |
972 | ||
b980ac18 | 973 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
9d5c8243 AK |
974 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
975 | * the 1000Base-T Control Register (Address 9). | |
976 | */ | |
977 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | | |
978 | NWAY_AR_100TX_HD_CAPS | | |
979 | NWAY_AR_10T_FD_CAPS | | |
980 | NWAY_AR_10T_HD_CAPS); | |
981 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); | |
982 | ||
652fff32 | 983 | hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
9d5c8243 AK |
984 | |
985 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
986 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
652fff32 | 987 | hw_dbg("Advertise 10mb Half duplex\n"); |
9d5c8243 AK |
988 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
989 | } | |
990 | ||
991 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
992 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
652fff32 | 993 | hw_dbg("Advertise 10mb Full duplex\n"); |
9d5c8243 AK |
994 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
995 | } | |
996 | ||
997 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
998 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
652fff32 | 999 | hw_dbg("Advertise 100mb Half duplex\n"); |
9d5c8243 AK |
1000 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
1001 | } | |
1002 | ||
1003 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
1004 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
652fff32 | 1005 | hw_dbg("Advertise 100mb Full duplex\n"); |
9d5c8243 AK |
1006 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
1007 | } | |
1008 | ||
1009 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
1010 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
652fff32 | 1011 | hw_dbg("Advertise 1000mb Half duplex request denied!\n"); |
9d5c8243 AK |
1012 | |
1013 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
1014 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
652fff32 | 1015 | hw_dbg("Advertise 1000mb Full duplex\n"); |
9d5c8243 AK |
1016 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
1017 | } | |
1018 | ||
b980ac18 | 1019 | /* Check for a software override of the flow control settings, and |
9d5c8243 AK |
1020 | * setup the PHY advertisement registers accordingly. If |
1021 | * auto-negotiation is enabled, then software will have to set the | |
1022 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
1023 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- | |
1024 | * negotiation. | |
1025 | * | |
1026 | * The possible values of the "fc" parameter are: | |
1027 | * 0: Flow control is completely disabled | |
1028 | * 1: Rx flow control is enabled (we can receive pause frames | |
1029 | * but not send pause frames). | |
1030 | * 2: Tx flow control is enabled (we can send pause frames | |
1031 | * but we do not support receiving pause frames). | |
1032 | * 3: Both Rx and TX flow control (symmetric) are enabled. | |
1033 | * other: No software override. The flow control configuration | |
1034 | * in the EEPROM is used. | |
1035 | */ | |
0cce119a | 1036 | switch (hw->fc.current_mode) { |
9d5c8243 | 1037 | case e1000_fc_none: |
b980ac18 | 1038 | /* Flow control (RX & TX) is completely disabled by a |
9d5c8243 AK |
1039 | * software over-ride. |
1040 | */ | |
1041 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1042 | break; | |
1043 | case e1000_fc_rx_pause: | |
b980ac18 | 1044 | /* RX Flow control is enabled, and TX Flow control is |
9d5c8243 AK |
1045 | * disabled, by a software over-ride. |
1046 | * | |
1047 | * Since there really isn't a way to advertise that we are | |
1048 | * capable of RX Pause ONLY, we will advertise that we | |
1049 | * support both symmetric and asymmetric RX PAUSE. Later | |
1050 | * (in e1000_config_fc_after_link_up) we will disable the | |
1051 | * hw's ability to send PAUSE frames. | |
1052 | */ | |
1053 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1054 | break; | |
1055 | case e1000_fc_tx_pause: | |
b980ac18 | 1056 | /* TX Flow control is enabled, and RX Flow control is |
9d5c8243 AK |
1057 | * disabled, by a software over-ride. |
1058 | */ | |
1059 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
1060 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
1061 | break; | |
1062 | case e1000_fc_full: | |
b980ac18 | 1063 | /* Flow control (both RX and TX) is enabled by a software |
9d5c8243 AK |
1064 | * over-ride. |
1065 | */ | |
1066 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1067 | break; | |
1068 | default: | |
652fff32 | 1069 | hw_dbg("Flow control param set incorrectly\n"); |
9d5c8243 AK |
1070 | ret_val = -E1000_ERR_CONFIG; |
1071 | goto out; | |
1072 | } | |
1073 | ||
a8d2a0c2 | 1074 | ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
9d5c8243 AK |
1075 | if (ret_val) |
1076 | goto out; | |
1077 | ||
652fff32 | 1078 | hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
9d5c8243 AK |
1079 | |
1080 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
a8d2a0c2 AD |
1081 | ret_val = phy->ops.write_reg(hw, |
1082 | PHY_1000T_CTRL, | |
1083 | mii_1000t_ctrl_reg); | |
9d5c8243 AK |
1084 | if (ret_val) |
1085 | goto out; | |
1086 | } | |
1087 | ||
1088 | out: | |
1089 | return ret_val; | |
1090 | } | |
1091 | ||
81fadd81 AD |
1092 | /** |
1093 | * igb_setup_copper_link - Configure copper link settings | |
1094 | * @hw: pointer to the HW structure | |
1095 | * | |
1096 | * Calls the appropriate function to configure the link for auto-neg or forced | |
1097 | * speed and duplex. Then we check for link, once link is established calls | |
1098 | * to configure collision distance and flow control are called. If link is | |
1099 | * not established, we return -E1000_ERR_PHY (-2). | |
1100 | **/ | |
1101 | s32 igb_setup_copper_link(struct e1000_hw *hw) | |
1102 | { | |
1103 | s32 ret_val; | |
1104 | bool link; | |
1105 | ||
81fadd81 | 1106 | if (hw->mac.autoneg) { |
b980ac18 | 1107 | /* Setup autoneg and flow control advertisement and perform |
81fadd81 AD |
1108 | * autonegotiation. |
1109 | */ | |
1110 | ret_val = igb_copper_link_autoneg(hw); | |
1111 | if (ret_val) | |
1112 | goto out; | |
1113 | } else { | |
b980ac18 | 1114 | /* PHY will be set to 10H, 10F, 100H or 100F |
81fadd81 AD |
1115 | * depending on user settings. |
1116 | */ | |
1117 | hw_dbg("Forcing Speed and Duplex\n"); | |
1118 | ret_val = hw->phy.ops.force_speed_duplex(hw); | |
1119 | if (ret_val) { | |
1120 | hw_dbg("Error Forcing Speed and Duplex\n"); | |
1121 | goto out; | |
1122 | } | |
1123 | } | |
1124 | ||
b980ac18 | 1125 | /* Check link status. Wait up to 100 microseconds for link to become |
81fadd81 AD |
1126 | * valid. |
1127 | */ | |
b980ac18 | 1128 | ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); |
81fadd81 AD |
1129 | if (ret_val) |
1130 | goto out; | |
1131 | ||
1132 | if (link) { | |
1133 | hw_dbg("Valid link established!!!\n"); | |
1134 | igb_config_collision_dist(hw); | |
1135 | ret_val = igb_config_fc_after_link_up(hw); | |
1136 | } else { | |
1137 | hw_dbg("Unable to establish link!!!\n"); | |
1138 | } | |
1139 | ||
1140 | out: | |
1141 | return ret_val; | |
1142 | } | |
1143 | ||
9d5c8243 | 1144 | /** |
733596be | 1145 | * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY |
9d5c8243 AK |
1146 | * @hw: pointer to the HW structure |
1147 | * | |
1148 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1149 | * auto-crossover to force MDI manually. Waits for link and returns | |
1150 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
1151 | **/ | |
1152 | s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
1153 | { | |
1154 | struct e1000_phy_info *phy = &hw->phy; | |
1155 | s32 ret_val; | |
1156 | u16 phy_data; | |
1157 | bool link; | |
1158 | ||
a8d2a0c2 | 1159 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
9d5c8243 AK |
1160 | if (ret_val) |
1161 | goto out; | |
1162 | ||
1163 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
1164 | ||
a8d2a0c2 | 1165 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
9d5c8243 AK |
1166 | if (ret_val) |
1167 | goto out; | |
1168 | ||
b980ac18 | 1169 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
9d5c8243 AK |
1170 | * forced whenever speed and duplex are forced. |
1171 | */ | |
a8d2a0c2 | 1172 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
9d5c8243 AK |
1173 | if (ret_val) |
1174 | goto out; | |
1175 | ||
1176 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1177 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1178 | ||
a8d2a0c2 | 1179 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
9d5c8243 AK |
1180 | if (ret_val) |
1181 | goto out; | |
1182 | ||
652fff32 | 1183 | hw_dbg("IGP PSCR: %X\n", phy_data); |
9d5c8243 AK |
1184 | |
1185 | udelay(1); | |
1186 | ||
1187 | if (phy->autoneg_wait_to_complete) { | |
652fff32 | 1188 | hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
9d5c8243 | 1189 | |
dc3d226f | 1190 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); |
9d5c8243 AK |
1191 | if (ret_val) |
1192 | goto out; | |
1193 | ||
1194 | if (!link) | |
652fff32 | 1195 | hw_dbg("Link taking longer than expected.\n"); |
9d5c8243 AK |
1196 | |
1197 | /* Try once more */ | |
dc3d226f | 1198 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); |
9d5c8243 AK |
1199 | if (ret_val) |
1200 | goto out; | |
1201 | } | |
1202 | ||
1203 | out: | |
1204 | return ret_val; | |
1205 | } | |
1206 | ||
1207 | /** | |
733596be | 1208 | * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY |
9d5c8243 AK |
1209 | * @hw: pointer to the HW structure |
1210 | * | |
1211 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1212 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
1213 | * changes. If time expires while waiting for link up, we reset the DSP. | |
1214 | * After reset, TX_CLK and CRS on TX must be set. Return successful upon | |
1215 | * successful completion, else return corresponding error code. | |
1216 | **/ | |
1217 | s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
1218 | { | |
1219 | struct e1000_phy_info *phy = &hw->phy; | |
1220 | s32 ret_val; | |
1221 | u16 phy_data; | |
1222 | bool link; | |
1223 | ||
9f0b8516 MV |
1224 | /* I210 and I211 devices support Auto-Crossover in forced operation. */ |
1225 | if (phy->type != e1000_phy_i210) { | |
b980ac18 | 1226 | /* Clear Auto-Crossover to force MDI manually. M88E1000 |
9f0b8516 MV |
1227 | * requires MDI forced whenever speed and duplex are forced. |
1228 | */ | |
1229 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, | |
1230 | &phy_data); | |
1231 | if (ret_val) | |
1232 | goto out; | |
9d5c8243 | 1233 | |
9f0b8516 MV |
1234 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
1235 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, | |
1236 | phy_data); | |
1237 | if (ret_val) | |
1238 | goto out; | |
9d5c8243 | 1239 | |
9f0b8516 MV |
1240 | hw_dbg("M88E1000 PSCR: %X\n", phy_data); |
1241 | } | |
9d5c8243 | 1242 | |
a8d2a0c2 | 1243 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
9d5c8243 AK |
1244 | if (ret_val) |
1245 | goto out; | |
1246 | ||
1247 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
1248 | ||
a8d2a0c2 | 1249 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
9d5c8243 AK |
1250 | if (ret_val) |
1251 | goto out; | |
1252 | ||
2553bb26 AD |
1253 | /* Reset the phy to commit changes. */ |
1254 | ret_val = igb_phy_sw_reset(hw); | |
1255 | if (ret_val) | |
1256 | goto out; | |
9d5c8243 AK |
1257 | |
1258 | if (phy->autoneg_wait_to_complete) { | |
652fff32 | 1259 | hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
9d5c8243 | 1260 | |
2553bb26 | 1261 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
9d5c8243 AK |
1262 | if (ret_val) |
1263 | goto out; | |
1264 | ||
1265 | if (!link) { | |
f96a8a0b CW |
1266 | bool reset_dsp = true; |
1267 | ||
1268 | switch (hw->phy.id) { | |
1269 | case I347AT4_E_PHY_ID: | |
1270 | case M88E1112_E_PHY_ID: | |
1271 | case I210_I_PHY_ID: | |
1272 | reset_dsp = false; | |
1273 | break; | |
1274 | default: | |
1275 | if (hw->phy.type != e1000_phy_m88) | |
1276 | reset_dsp = false; | |
1277 | break; | |
1278 | } | |
1279 | if (!reset_dsp) | |
308fb39a | 1280 | hw_dbg("Link taking longer than expected.\n"); |
f96a8a0b | 1281 | else { |
b980ac18 | 1282 | /* We didn't get link. |
308fb39a JG |
1283 | * Reset the DSP and cross our fingers. |
1284 | */ | |
1285 | ret_val = phy->ops.write_reg(hw, | |
b980ac18 JK |
1286 | M88E1000_PHY_PAGE_SELECT, |
1287 | 0x001d); | |
308fb39a JG |
1288 | if (ret_val) |
1289 | goto out; | |
1290 | ret_val = igb_phy_reset_dsp(hw); | |
1291 | if (ret_val) | |
1292 | goto out; | |
1293 | } | |
9d5c8243 AK |
1294 | } |
1295 | ||
1296 | /* Try once more */ | |
1297 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, | |
2553bb26 | 1298 | 100000, &link); |
9d5c8243 AK |
1299 | if (ret_val) |
1300 | goto out; | |
1301 | } | |
1302 | ||
308fb39a JG |
1303 | if (hw->phy.type != e1000_phy_m88 || |
1304 | hw->phy.id == I347AT4_E_PHY_ID || | |
f96a8a0b CW |
1305 | hw->phy.id == M88E1112_E_PHY_ID || |
1306 | hw->phy.id == I210_I_PHY_ID) | |
308fb39a JG |
1307 | goto out; |
1308 | ||
a8d2a0c2 | 1309 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1310 | if (ret_val) |
1311 | goto out; | |
1312 | ||
b980ac18 | 1313 | /* Resetting the phy means we need to re-force TX_CLK in the |
9d5c8243 AK |
1314 | * Extended PHY Specific Control Register to 25MHz clock from |
1315 | * the reset value of 2.5MHz. | |
1316 | */ | |
1317 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
a8d2a0c2 | 1318 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
1319 | if (ret_val) |
1320 | goto out; | |
1321 | ||
b980ac18 | 1322 | /* In addition, we must re-enable CRS on Tx for both half and full |
9d5c8243 AK |
1323 | * duplex. |
1324 | */ | |
a8d2a0c2 | 1325 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1326 | if (ret_val) |
1327 | goto out; | |
1328 | ||
1329 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
a8d2a0c2 | 1330 | ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
9d5c8243 AK |
1331 | |
1332 | out: | |
1333 | return ret_val; | |
1334 | } | |
1335 | ||
1336 | /** | |
733596be | 1337 | * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex |
9d5c8243 AK |
1338 | * @hw: pointer to the HW structure |
1339 | * @phy_ctrl: pointer to current value of PHY_CONTROL | |
1340 | * | |
1341 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
1342 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
1343 | * disable auto-negotiation, configure duplex, configure speed, configure | |
1344 | * the collision distance, write configuration to CTRL register. The | |
1345 | * caller must write to the PHY_CONTROL register for these settings to | |
1346 | * take affect. | |
1347 | **/ | |
1348 | static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, | |
b980ac18 | 1349 | u16 *phy_ctrl) |
9d5c8243 AK |
1350 | { |
1351 | struct e1000_mac_info *mac = &hw->mac; | |
1352 | u32 ctrl; | |
1353 | ||
1354 | /* Turn off flow control when forcing speed/duplex */ | |
0cce119a | 1355 | hw->fc.current_mode = e1000_fc_none; |
9d5c8243 AK |
1356 | |
1357 | /* Force speed/duplex on the mac */ | |
1358 | ctrl = rd32(E1000_CTRL); | |
1359 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1360 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1361 | ||
1362 | /* Disable Auto Speed Detection */ | |
1363 | ctrl &= ~E1000_CTRL_ASDE; | |
1364 | ||
1365 | /* Disable autoneg on the phy */ | |
1366 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; | |
1367 | ||
1368 | /* Forcing Full or Half Duplex? */ | |
1369 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1370 | ctrl &= ~E1000_CTRL_FD; | |
1371 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; | |
652fff32 | 1372 | hw_dbg("Half Duplex\n"); |
9d5c8243 AK |
1373 | } else { |
1374 | ctrl |= E1000_CTRL_FD; | |
1375 | *phy_ctrl |= MII_CR_FULL_DUPLEX; | |
652fff32 | 1376 | hw_dbg("Full Duplex\n"); |
9d5c8243 AK |
1377 | } |
1378 | ||
1379 | /* Forcing 10mb or 100mb? */ | |
1380 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1381 | ctrl |= E1000_CTRL_SPD_100; | |
1382 | *phy_ctrl |= MII_CR_SPEED_100; | |
1383 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
652fff32 | 1384 | hw_dbg("Forcing 100mb\n"); |
9d5c8243 AK |
1385 | } else { |
1386 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1387 | *phy_ctrl |= MII_CR_SPEED_10; | |
1388 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
652fff32 | 1389 | hw_dbg("Forcing 10mb\n"); |
9d5c8243 AK |
1390 | } |
1391 | ||
1392 | igb_config_collision_dist(hw); | |
1393 | ||
1394 | wr32(E1000_CTRL, ctrl); | |
1395 | } | |
1396 | ||
1397 | /** | |
733596be | 1398 | * igb_set_d3_lplu_state - Sets low power link up state for D3 |
9d5c8243 AK |
1399 | * @hw: pointer to the HW structure |
1400 | * @active: boolean used to enable/disable lplu | |
1401 | * | |
1402 | * Success returns 0, Failure returns 1 | |
1403 | * | |
1404 | * The low power link up (lplu) state is set to the power management level D3 | |
1405 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1406 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1407 | * is used during Dx states where the power conservation is most important. | |
1408 | * During driver activity, SmartSpeed should be enabled so performance is | |
1409 | * maintained. | |
1410 | **/ | |
1411 | s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1412 | { | |
1413 | struct e1000_phy_info *phy = &hw->phy; | |
2553bb26 | 1414 | s32 ret_val = 0; |
9d5c8243 AK |
1415 | u16 data; |
1416 | ||
2553bb26 AD |
1417 | if (!(hw->phy.ops.read_reg)) |
1418 | goto out; | |
1419 | ||
a8d2a0c2 | 1420 | ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); |
9d5c8243 AK |
1421 | if (ret_val) |
1422 | goto out; | |
1423 | ||
1424 | if (!active) { | |
1425 | data &= ~IGP02E1000_PM_D3_LPLU; | |
a8d2a0c2 | 1426 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
9d5c8243 AK |
1427 | data); |
1428 | if (ret_val) | |
1429 | goto out; | |
b980ac18 | 1430 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
9d5c8243 AK |
1431 | * during Dx states where the power conservation is most |
1432 | * important. During driver activity we should enable | |
1433 | * SmartSpeed, so performance is maintained. | |
1434 | */ | |
1435 | if (phy->smart_speed == e1000_smart_speed_on) { | |
a8d2a0c2 | 1436 | ret_val = phy->ops.read_reg(hw, |
9d5c8243 AK |
1437 | IGP01E1000_PHY_PORT_CONFIG, |
1438 | &data); | |
1439 | if (ret_val) | |
1440 | goto out; | |
1441 | ||
1442 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1443 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
1444 | IGP01E1000_PHY_PORT_CONFIG, |
1445 | data); | |
1446 | if (ret_val) | |
1447 | goto out; | |
1448 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
a8d2a0c2 | 1449 | ret_val = phy->ops.read_reg(hw, |
9d5c8243 AK |
1450 | IGP01E1000_PHY_PORT_CONFIG, |
1451 | &data); | |
1452 | if (ret_val) | |
1453 | goto out; | |
1454 | ||
1455 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1456 | ret_val = phy->ops.write_reg(hw, |
9d5c8243 AK |
1457 | IGP01E1000_PHY_PORT_CONFIG, |
1458 | data); | |
1459 | if (ret_val) | |
1460 | goto out; | |
1461 | } | |
1462 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1463 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1464 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1465 | data |= IGP02E1000_PM_D3_LPLU; | |
a8d2a0c2 | 1466 | ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
9d5c8243 AK |
1467 | data); |
1468 | if (ret_val) | |
1469 | goto out; | |
1470 | ||
1471 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
a8d2a0c2 | 1472 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
b980ac18 | 1473 | &data); |
9d5c8243 AK |
1474 | if (ret_val) |
1475 | goto out; | |
1476 | ||
1477 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
a8d2a0c2 | 1478 | ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
b980ac18 | 1479 | data); |
9d5c8243 AK |
1480 | } |
1481 | ||
1482 | out: | |
1483 | return ret_val; | |
1484 | } | |
1485 | ||
1486 | /** | |
25985edc | 1487 | * igb_check_downshift - Checks whether a downshift in speed occurred |
9d5c8243 AK |
1488 | * @hw: pointer to the HW structure |
1489 | * | |
1490 | * Success returns 0, Failure returns 1 | |
1491 | * | |
1492 | * A downshift is detected by querying the PHY link health. | |
1493 | **/ | |
1494 | s32 igb_check_downshift(struct e1000_hw *hw) | |
1495 | { | |
1496 | struct e1000_phy_info *phy = &hw->phy; | |
1497 | s32 ret_val; | |
1498 | u16 phy_data, offset, mask; | |
1499 | ||
1500 | switch (phy->type) { | |
f96a8a0b | 1501 | case e1000_phy_i210: |
9d5c8243 AK |
1502 | case e1000_phy_m88: |
1503 | case e1000_phy_gg82563: | |
1504 | offset = M88E1000_PHY_SPEC_STATUS; | |
1505 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1506 | break; | |
1507 | case e1000_phy_igp_2: | |
1508 | case e1000_phy_igp: | |
1509 | case e1000_phy_igp_3: | |
1510 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1511 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1512 | break; | |
1513 | default: | |
1514 | /* speed downshift not supported */ | |
1515 | phy->speed_downgraded = false; | |
1516 | ret_val = 0; | |
1517 | goto out; | |
1518 | } | |
1519 | ||
a8d2a0c2 | 1520 | ret_val = phy->ops.read_reg(hw, offset, &phy_data); |
9d5c8243 AK |
1521 | |
1522 | if (!ret_val) | |
1523 | phy->speed_downgraded = (phy_data & mask) ? true : false; | |
1524 | ||
1525 | out: | |
1526 | return ret_val; | |
1527 | } | |
1528 | ||
1529 | /** | |
733596be | 1530 | * igb_check_polarity_m88 - Checks the polarity. |
9d5c8243 AK |
1531 | * @hw: pointer to the HW structure |
1532 | * | |
1533 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1534 | * | |
1535 | * Polarity is determined based on the PHY specific status register. | |
1536 | **/ | |
f96a8a0b | 1537 | s32 igb_check_polarity_m88(struct e1000_hw *hw) |
9d5c8243 AK |
1538 | { |
1539 | struct e1000_phy_info *phy = &hw->phy; | |
1540 | s32 ret_val; | |
1541 | u16 data; | |
1542 | ||
a8d2a0c2 | 1543 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); |
9d5c8243 AK |
1544 | |
1545 | if (!ret_val) | |
1546 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1547 | ? e1000_rev_polarity_reversed | |
1548 | : e1000_rev_polarity_normal; | |
1549 | ||
1550 | return ret_val; | |
1551 | } | |
1552 | ||
1553 | /** | |
733596be | 1554 | * igb_check_polarity_igp - Checks the polarity. |
9d5c8243 AK |
1555 | * @hw: pointer to the HW structure |
1556 | * | |
1557 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1558 | * | |
1559 | * Polarity is determined based on the PHY port status register, and the | |
1560 | * current speed (since there is no polarity at 100Mbps). | |
1561 | **/ | |
1562 | static s32 igb_check_polarity_igp(struct e1000_hw *hw) | |
1563 | { | |
1564 | struct e1000_phy_info *phy = &hw->phy; | |
1565 | s32 ret_val; | |
1566 | u16 data, offset, mask; | |
1567 | ||
b980ac18 | 1568 | /* Polarity is determined based on the speed of |
9d5c8243 AK |
1569 | * our connection. |
1570 | */ | |
a8d2a0c2 | 1571 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
9d5c8243 AK |
1572 | if (ret_val) |
1573 | goto out; | |
1574 | ||
1575 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1576 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1577 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1578 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1579 | } else { | |
b980ac18 | 1580 | /* This really only applies to 10Mbps since |
9d5c8243 AK |
1581 | * there is no polarity for 100Mbps (always 0). |
1582 | */ | |
1583 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1584 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1585 | } | |
1586 | ||
a8d2a0c2 | 1587 | ret_val = phy->ops.read_reg(hw, offset, &data); |
9d5c8243 AK |
1588 | |
1589 | if (!ret_val) | |
1590 | phy->cable_polarity = (data & mask) | |
1591 | ? e1000_rev_polarity_reversed | |
1592 | : e1000_rev_polarity_normal; | |
1593 | ||
1594 | out: | |
1595 | return ret_val; | |
1596 | } | |
1597 | ||
1598 | /** | |
b980ac18 | 1599 | * igb_wait_autoneg - Wait for auto-neg completion |
9d5c8243 AK |
1600 | * @hw: pointer to the HW structure |
1601 | * | |
1602 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1603 | * limit to expire, which ever happens first. | |
1604 | **/ | |
1605 | static s32 igb_wait_autoneg(struct e1000_hw *hw) | |
1606 | { | |
1607 | s32 ret_val = 0; | |
1608 | u16 i, phy_status; | |
1609 | ||
1610 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1611 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
a8d2a0c2 | 1612 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1613 | if (ret_val) |
1614 | break; | |
a8d2a0c2 | 1615 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1616 | if (ret_val) |
1617 | break; | |
1618 | if (phy_status & MII_SR_AUTONEG_COMPLETE) | |
1619 | break; | |
1620 | msleep(100); | |
1621 | } | |
1622 | ||
b980ac18 | 1623 | /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation |
9d5c8243 AK |
1624 | * has completed. |
1625 | */ | |
1626 | return ret_val; | |
1627 | } | |
1628 | ||
1629 | /** | |
733596be | 1630 | * igb_phy_has_link - Polls PHY for link |
9d5c8243 AK |
1631 | * @hw: pointer to the HW structure |
1632 | * @iterations: number of times to poll for link | |
1633 | * @usec_interval: delay between polling attempts | |
1634 | * @success: pointer to whether polling was successful or not | |
1635 | * | |
1636 | * Polls the PHY status register for link, 'iterations' number of times. | |
1637 | **/ | |
1638 | s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, | |
b980ac18 | 1639 | u32 usec_interval, bool *success) |
9d5c8243 AK |
1640 | { |
1641 | s32 ret_val = 0; | |
1642 | u16 i, phy_status; | |
1643 | ||
1644 | for (i = 0; i < iterations; i++) { | |
b980ac18 | 1645 | /* Some PHYs require the PHY_STATUS register to be read |
9d5c8243 AK |
1646 | * twice due to the link bit being sticky. No harm doing |
1647 | * it across the board. | |
1648 | */ | |
a8d2a0c2 | 1649 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
dc3d226f | 1650 | if (ret_val && usec_interval > 0) { |
b980ac18 | 1651 | /* If the first read fails, another entity may have |
ab576389 AD |
1652 | * ownership of the resources, wait and try again to |
1653 | * see if they have relinquished the resources yet. | |
1654 | */ | |
df29df92 CW |
1655 | if (usec_interval >= 1000) |
1656 | mdelay(usec_interval/1000); | |
1657 | else | |
1658 | udelay(usec_interval); | |
ab576389 | 1659 | } |
a8d2a0c2 | 1660 | ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); |
9d5c8243 AK |
1661 | if (ret_val) |
1662 | break; | |
1663 | if (phy_status & MII_SR_LINK_STATUS) | |
1664 | break; | |
1665 | if (usec_interval >= 1000) | |
1666 | mdelay(usec_interval/1000); | |
1667 | else | |
1668 | udelay(usec_interval); | |
1669 | } | |
1670 | ||
1671 | *success = (i < iterations) ? true : false; | |
1672 | ||
1673 | return ret_val; | |
1674 | } | |
1675 | ||
1676 | /** | |
733596be | 1677 | * igb_get_cable_length_m88 - Determine cable length for m88 PHY |
9d5c8243 AK |
1678 | * @hw: pointer to the HW structure |
1679 | * | |
1680 | * Reads the PHY specific status register to retrieve the cable length | |
1681 | * information. The cable length is determined by averaging the minimum and | |
1682 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1683 | * possible cable length values, which are: | |
1684 | * Register Value Cable Length | |
1685 | * 0 < 50 meters | |
1686 | * 1 50 - 80 meters | |
1687 | * 2 80 - 110 meters | |
1688 | * 3 110 - 140 meters | |
1689 | * 4 > 140 meters | |
1690 | **/ | |
1691 | s32 igb_get_cable_length_m88(struct e1000_hw *hw) | |
1692 | { | |
1693 | struct e1000_phy_info *phy = &hw->phy; | |
1694 | s32 ret_val; | |
1695 | u16 phy_data, index; | |
1696 | ||
a8d2a0c2 | 1697 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
9d5c8243 AK |
1698 | if (ret_val) |
1699 | goto out; | |
1700 | ||
1701 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
1702 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
2553bb26 AD |
1703 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { |
1704 | ret_val = -E1000_ERR_PHY; | |
1705 | goto out; | |
1706 | } | |
1707 | ||
9d5c8243 | 1708 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
2553bb26 | 1709 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
9d5c8243 AK |
1710 | |
1711 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1712 | ||
1713 | out: | |
1714 | return ret_val; | |
1715 | } | |
1716 | ||
308fb39a JG |
1717 | s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) |
1718 | { | |
1719 | struct e1000_phy_info *phy = &hw->phy; | |
1720 | s32 ret_val; | |
1721 | u16 phy_data, phy_data2, index, default_page, is_cm; | |
1722 | ||
1723 | switch (hw->phy.id) { | |
f96a8a0b | 1724 | case I210_I_PHY_ID: |
59f30104 CW |
1725 | /* Get cable length from PHY Cable Diagnostics Control Reg */ |
1726 | ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + | |
1727 | (I347AT4_PCDL + phy->addr), | |
1728 | &phy_data); | |
1729 | if (ret_val) | |
1730 | return ret_val; | |
1731 | ||
1732 | /* Check if the unit of cable length is meters or cm */ | |
1733 | ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + | |
1734 | I347AT4_PCDC, &phy_data2); | |
1735 | if (ret_val) | |
1736 | return ret_val; | |
1737 | ||
1738 | is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); | |
1739 | ||
1740 | /* Populate the phy structure with cable length in meters */ | |
1741 | phy->min_cable_length = phy_data / (is_cm ? 100 : 1); | |
1742 | phy->max_cable_length = phy_data / (is_cm ? 100 : 1); | |
1743 | phy->cable_length = phy_data / (is_cm ? 100 : 1); | |
1744 | break; | |
99af4729 | 1745 | case M88E1543_E_PHY_ID: |
308fb39a JG |
1746 | case I347AT4_E_PHY_ID: |
1747 | /* Remember the original page select and set it to 7 */ | |
1748 | ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, | |
1749 | &default_page); | |
1750 | if (ret_val) | |
1751 | goto out; | |
1752 | ||
1753 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); | |
1754 | if (ret_val) | |
1755 | goto out; | |
1756 | ||
1757 | /* Get cable length from PHY Cable Diagnostics Control Reg */ | |
1758 | ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), | |
1759 | &phy_data); | |
1760 | if (ret_val) | |
1761 | goto out; | |
1762 | ||
1763 | /* Check if the unit of cable length is meters or cm */ | |
1764 | ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); | |
1765 | if (ret_val) | |
1766 | goto out; | |
1767 | ||
d5a0e364 | 1768 | is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); |
308fb39a JG |
1769 | |
1770 | /* Populate the phy structure with cable length in meters */ | |
1771 | phy->min_cable_length = phy_data / (is_cm ? 100 : 1); | |
1772 | phy->max_cable_length = phy_data / (is_cm ? 100 : 1); | |
1773 | phy->cable_length = phy_data / (is_cm ? 100 : 1); | |
1774 | ||
1775 | /* Reset the page selec to its original value */ | |
1776 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, | |
1777 | default_page); | |
1778 | if (ret_val) | |
1779 | goto out; | |
1780 | break; | |
1781 | case M88E1112_E_PHY_ID: | |
1782 | /* Remember the original page select and set it to 5 */ | |
1783 | ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, | |
1784 | &default_page); | |
1785 | if (ret_val) | |
1786 | goto out; | |
1787 | ||
1788 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); | |
1789 | if (ret_val) | |
1790 | goto out; | |
1791 | ||
1792 | ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, | |
1793 | &phy_data); | |
1794 | if (ret_val) | |
1795 | goto out; | |
1796 | ||
1797 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
1798 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; | |
1799 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { | |
1800 | ret_val = -E1000_ERR_PHY; | |
1801 | goto out; | |
1802 | } | |
1803 | ||
1804 | phy->min_cable_length = e1000_m88_cable_length_table[index]; | |
1805 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; | |
1806 | ||
1807 | phy->cable_length = (phy->min_cable_length + | |
1808 | phy->max_cable_length) / 2; | |
1809 | ||
1810 | /* Reset the page select to its original value */ | |
1811 | ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, | |
1812 | default_page); | |
1813 | if (ret_val) | |
1814 | goto out; | |
1815 | ||
1816 | break; | |
1817 | default: | |
1818 | ret_val = -E1000_ERR_PHY; | |
1819 | goto out; | |
1820 | } | |
1821 | ||
1822 | out: | |
1823 | return ret_val; | |
1824 | } | |
1825 | ||
9d5c8243 | 1826 | /** |
733596be | 1827 | * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY |
9d5c8243 AK |
1828 | * @hw: pointer to the HW structure |
1829 | * | |
1830 | * The automatic gain control (agc) normalizes the amplitude of the | |
1831 | * received signal, adjusting for the attenuation produced by the | |
a8d2a0c2 AD |
1832 | * cable. By reading the AGC registers, which represent the |
1833 | * combination of coarse and fine gain value, the value can be put | |
9d5c8243 AK |
1834 | * into a lookup table to obtain the approximate cable length |
1835 | * for each channel. | |
1836 | **/ | |
1837 | s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) | |
1838 | { | |
1839 | struct e1000_phy_info *phy = &hw->phy; | |
1840 | s32 ret_val = 0; | |
1841 | u16 phy_data, i, agc_value = 0; | |
1842 | u16 cur_agc_index, max_agc_index = 0; | |
1843 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
66744500 | 1844 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
b980ac18 JK |
1845 | IGP02E1000_PHY_AGC_A, |
1846 | IGP02E1000_PHY_AGC_B, | |
1847 | IGP02E1000_PHY_AGC_C, | |
1848 | IGP02E1000_PHY_AGC_D | |
66744500 | 1849 | }; |
9d5c8243 AK |
1850 | |
1851 | /* Read the AGC registers for all channels */ | |
1852 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
a8d2a0c2 | 1853 | ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); |
9d5c8243 AK |
1854 | if (ret_val) |
1855 | goto out; | |
1856 | ||
b980ac18 | 1857 | /* Getting bits 15:9, which represent the combination of |
a8d2a0c2 | 1858 | * coarse and fine gain values. The result is a number |
9d5c8243 AK |
1859 | * that can be put into the lookup table to obtain the |
1860 | * approximate cable length. | |
1861 | */ | |
1862 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & | |
1863 | IGP02E1000_AGC_LENGTH_MASK; | |
1864 | ||
1865 | /* Array index bound check. */ | |
1866 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1867 | (cur_agc_index == 0)) { | |
1868 | ret_val = -E1000_ERR_PHY; | |
1869 | goto out; | |
1870 | } | |
1871 | ||
1872 | /* Remove min & max AGC values from calculation. */ | |
1873 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1874 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1875 | min_agc_index = cur_agc_index; | |
1876 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1877 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1878 | max_agc_index = cur_agc_index; | |
1879 | ||
1880 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1881 | } | |
1882 | ||
1883 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1884 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1885 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1886 | ||
1887 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1888 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1889 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1890 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1891 | ||
1892 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1893 | ||
1894 | out: | |
1895 | return ret_val; | |
1896 | } | |
1897 | ||
1898 | /** | |
733596be | 1899 | * igb_get_phy_info_m88 - Retrieve PHY information |
9d5c8243 AK |
1900 | * @hw: pointer to the HW structure |
1901 | * | |
1902 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1903 | * to verify that link is up. Read the PHY special control register to | |
1904 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1905 | * special status register to determine MDI/MDIx and current speed. If | |
1906 | * speed is 1000, then determine cable length, local and remote receiver. | |
1907 | **/ | |
1908 | s32 igb_get_phy_info_m88(struct e1000_hw *hw) | |
1909 | { | |
1910 | struct e1000_phy_info *phy = &hw->phy; | |
1911 | s32 ret_val; | |
1912 | u16 phy_data; | |
1913 | bool link; | |
1914 | ||
a8d2a0c2 | 1915 | if (phy->media_type != e1000_media_type_copper) { |
652fff32 | 1916 | hw_dbg("Phy info is only valid for copper media\n"); |
9d5c8243 AK |
1917 | ret_val = -E1000_ERR_CONFIG; |
1918 | goto out; | |
1919 | } | |
1920 | ||
1921 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
1922 | if (ret_val) | |
1923 | goto out; | |
1924 | ||
1925 | if (!link) { | |
652fff32 | 1926 | hw_dbg("Phy info is only valid if link is up\n"); |
9d5c8243 AK |
1927 | ret_val = -E1000_ERR_CONFIG; |
1928 | goto out; | |
1929 | } | |
1930 | ||
a8d2a0c2 | 1931 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
9d5c8243 AK |
1932 | if (ret_val) |
1933 | goto out; | |
1934 | ||
1935 | phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) | |
a8d2a0c2 | 1936 | ? true : false; |
9d5c8243 AK |
1937 | |
1938 | ret_val = igb_check_polarity_m88(hw); | |
1939 | if (ret_val) | |
1940 | goto out; | |
1941 | ||
a8d2a0c2 | 1942 | ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
9d5c8243 AK |
1943 | if (ret_val) |
1944 | goto out; | |
1945 | ||
1946 | phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; | |
1947 | ||
1948 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
a8d2a0c2 | 1949 | ret_val = phy->ops.get_cable_length(hw); |
9d5c8243 AK |
1950 | if (ret_val) |
1951 | goto out; | |
1952 | ||
a8d2a0c2 | 1953 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); |
9d5c8243 AK |
1954 | if (ret_val) |
1955 | goto out; | |
1956 | ||
1957 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) | |
1958 | ? e1000_1000t_rx_status_ok | |
1959 | : e1000_1000t_rx_status_not_ok; | |
1960 | ||
1961 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) | |
1962 | ? e1000_1000t_rx_status_ok | |
1963 | : e1000_1000t_rx_status_not_ok; | |
1964 | } else { | |
1965 | /* Set values to "undefined" */ | |
1966 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1967 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1968 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1969 | } | |
1970 | ||
1971 | out: | |
1972 | return ret_val; | |
1973 | } | |
1974 | ||
1975 | /** | |
733596be | 1976 | * igb_get_phy_info_igp - Retrieve igp PHY information |
9d5c8243 AK |
1977 | * @hw: pointer to the HW structure |
1978 | * | |
1979 | * Read PHY status to determine if link is up. If link is up, then | |
1980 | * set/determine 10base-T extended distance and polarity correction. Read | |
1981 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1982 | * determine on the cable length, local and remote receiver. | |
1983 | **/ | |
1984 | s32 igb_get_phy_info_igp(struct e1000_hw *hw) | |
1985 | { | |
1986 | struct e1000_phy_info *phy = &hw->phy; | |
1987 | s32 ret_val; | |
1988 | u16 data; | |
1989 | bool link; | |
1990 | ||
1991 | ret_val = igb_phy_has_link(hw, 1, 0, &link); | |
1992 | if (ret_val) | |
1993 | goto out; | |
1994 | ||
1995 | if (!link) { | |
652fff32 | 1996 | hw_dbg("Phy info is only valid if link is up\n"); |
9d5c8243 AK |
1997 | ret_val = -E1000_ERR_CONFIG; |
1998 | goto out; | |
1999 | } | |
2000 | ||
2001 | phy->polarity_correction = true; | |
2002 | ||
2003 | ret_val = igb_check_polarity_igp(hw); | |
2004 | if (ret_val) | |
2005 | goto out; | |
2006 | ||
a8d2a0c2 | 2007 | ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
9d5c8243 AK |
2008 | if (ret_val) |
2009 | goto out; | |
2010 | ||
2011 | phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; | |
2012 | ||
2013 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
2014 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
a8d2a0c2 | 2015 | ret_val = phy->ops.get_cable_length(hw); |
9d5c8243 AK |
2016 | if (ret_val) |
2017 | goto out; | |
2018 | ||
a8d2a0c2 | 2019 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
9d5c8243 AK |
2020 | if (ret_val) |
2021 | goto out; | |
2022 | ||
2023 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
2024 | ? e1000_1000t_rx_status_ok | |
2025 | : e1000_1000t_rx_status_not_ok; | |
2026 | ||
2027 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
2028 | ? e1000_1000t_rx_status_ok | |
2029 | : e1000_1000t_rx_status_not_ok; | |
2030 | } else { | |
2031 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2032 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2033 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2034 | } | |
2035 | ||
2036 | out: | |
2037 | return ret_val; | |
2038 | } | |
2039 | ||
2040 | /** | |
733596be | 2041 | * igb_phy_sw_reset - PHY software reset |
9d5c8243 AK |
2042 | * @hw: pointer to the HW structure |
2043 | * | |
2044 | * Does a software reset of the PHY by reading the PHY control register and | |
2045 | * setting/write the control register reset bit to the PHY. | |
2046 | **/ | |
2047 | s32 igb_phy_sw_reset(struct e1000_hw *hw) | |
2048 | { | |
d314737a | 2049 | s32 ret_val = 0; |
9d5c8243 AK |
2050 | u16 phy_ctrl; |
2051 | ||
d314737a AD |
2052 | if (!(hw->phy.ops.read_reg)) |
2053 | goto out; | |
2054 | ||
a8d2a0c2 | 2055 | ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); |
9d5c8243 AK |
2056 | if (ret_val) |
2057 | goto out; | |
2058 | ||
2059 | phy_ctrl |= MII_CR_RESET; | |
a8d2a0c2 | 2060 | ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); |
9d5c8243 AK |
2061 | if (ret_val) |
2062 | goto out; | |
2063 | ||
2064 | udelay(1); | |
2065 | ||
2066 | out: | |
2067 | return ret_val; | |
2068 | } | |
2069 | ||
2070 | /** | |
733596be | 2071 | * igb_phy_hw_reset - PHY hardware reset |
9d5c8243 AK |
2072 | * @hw: pointer to the HW structure |
2073 | * | |
2074 | * Verify the reset block is not blocking us from resetting. Acquire | |
2075 | * semaphore (if necessary) and read/set/write the device control reset | |
2076 | * bit in the PHY. Wait the appropriate delay time for the device to | |
83a35e36 | 2077 | * reset and release the semaphore (if necessary). |
9d5c8243 AK |
2078 | **/ |
2079 | s32 igb_phy_hw_reset(struct e1000_hw *hw) | |
2080 | { | |
2081 | struct e1000_phy_info *phy = &hw->phy; | |
2082 | s32 ret_val; | |
2083 | u32 ctrl; | |
2084 | ||
2085 | ret_val = igb_check_reset_block(hw); | |
2086 | if (ret_val) { | |
2087 | ret_val = 0; | |
2088 | goto out; | |
2089 | } | |
2090 | ||
a8d2a0c2 | 2091 | ret_val = phy->ops.acquire(hw); |
9d5c8243 AK |
2092 | if (ret_val) |
2093 | goto out; | |
2094 | ||
2095 | ctrl = rd32(E1000_CTRL); | |
2096 | wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); | |
2097 | wrfl(); | |
2098 | ||
2099 | udelay(phy->reset_delay_us); | |
2100 | ||
2101 | wr32(E1000_CTRL, ctrl); | |
2102 | wrfl(); | |
2103 | ||
2104 | udelay(150); | |
2105 | ||
a8d2a0c2 | 2106 | phy->ops.release(hw); |
9d5c8243 | 2107 | |
a8d2a0c2 | 2108 | ret_val = phy->ops.get_cfg_done(hw); |
9d5c8243 AK |
2109 | |
2110 | out: | |
2111 | return ret_val; | |
2112 | } | |
2113 | ||
9d5c8243 | 2114 | /** |
733596be | 2115 | * igb_phy_init_script_igp3 - Inits the IGP3 PHY |
9d5c8243 AK |
2116 | * @hw: pointer to the HW structure |
2117 | * | |
2118 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
2119 | **/ | |
2120 | s32 igb_phy_init_script_igp3(struct e1000_hw *hw) | |
2121 | { | |
652fff32 | 2122 | hw_dbg("Running IGP 3 PHY init script\n"); |
9d5c8243 AK |
2123 | |
2124 | /* PHY init IGP 3 */ | |
2125 | /* Enable rise/fall, 10-mode work in class-A */ | |
a8d2a0c2 | 2126 | hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); |
9d5c8243 | 2127 | /* Remove all caps from Replica path filter */ |
a8d2a0c2 | 2128 | hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); |
9d5c8243 | 2129 | /* Bias trimming for ADC, AFE and Driver (Default) */ |
a8d2a0c2 | 2130 | hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); |
9d5c8243 | 2131 | /* Increase Hybrid poly bias */ |
a8d2a0c2 | 2132 | hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); |
9d5c8243 | 2133 | /* Add 4% to TX amplitude in Giga mode */ |
a8d2a0c2 | 2134 | hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); |
9d5c8243 | 2135 | /* Disable trimming (TTT) */ |
a8d2a0c2 | 2136 | hw->phy.ops.write_reg(hw, 0x2011, 0x0000); |
9d5c8243 | 2137 | /* Poly DC correction to 94.6% + 2% for all channels */ |
a8d2a0c2 | 2138 | hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); |
9d5c8243 | 2139 | /* ABS DC correction to 95.9% */ |
a8d2a0c2 | 2140 | hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); |
9d5c8243 | 2141 | /* BG temp curve trim */ |
a8d2a0c2 | 2142 | hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); |
9d5c8243 | 2143 | /* Increasing ADC OPAMP stage 1 currents to max */ |
a8d2a0c2 | 2144 | hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); |
9d5c8243 | 2145 | /* Force 1000 ( required for enabling PHY regs configuration) */ |
a8d2a0c2 | 2146 | hw->phy.ops.write_reg(hw, 0x0000, 0x0140); |
9d5c8243 | 2147 | /* Set upd_freq to 6 */ |
a8d2a0c2 | 2148 | hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); |
9d5c8243 | 2149 | /* Disable NPDFE */ |
a8d2a0c2 | 2150 | hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); |
9d5c8243 | 2151 | /* Disable adaptive fixed FFE (Default) */ |
a8d2a0c2 | 2152 | hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); |
9d5c8243 | 2153 | /* Enable FFE hysteresis */ |
a8d2a0c2 | 2154 | hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); |
9d5c8243 | 2155 | /* Fixed FFE for short cable lengths */ |
a8d2a0c2 | 2156 | hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); |
9d5c8243 | 2157 | /* Fixed FFE for medium cable lengths */ |
a8d2a0c2 | 2158 | hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); |
9d5c8243 | 2159 | /* Fixed FFE for long cable lengths */ |
a8d2a0c2 | 2160 | hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); |
9d5c8243 | 2161 | /* Enable Adaptive Clip Threshold */ |
a8d2a0c2 | 2162 | hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); |
9d5c8243 | 2163 | /* AHT reset limit to 1 */ |
a8d2a0c2 | 2164 | hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); |
9d5c8243 | 2165 | /* Set AHT master delay to 127 msec */ |
a8d2a0c2 | 2166 | hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); |
9d5c8243 | 2167 | /* Set scan bits for AHT */ |
a8d2a0c2 | 2168 | hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); |
9d5c8243 | 2169 | /* Set AHT Preset bits */ |
a8d2a0c2 | 2170 | hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); |
9d5c8243 | 2171 | /* Change integ_factor of channel A to 3 */ |
a8d2a0c2 | 2172 | hw->phy.ops.write_reg(hw, 0x1895, 0x0003); |
9d5c8243 | 2173 | /* Change prop_factor of channels BCD to 8 */ |
a8d2a0c2 | 2174 | hw->phy.ops.write_reg(hw, 0x1796, 0x0008); |
9d5c8243 | 2175 | /* Change cg_icount + enable integbp for channels BCD */ |
a8d2a0c2 | 2176 | hw->phy.ops.write_reg(hw, 0x1798, 0xD008); |
b980ac18 | 2177 | /* Change cg_icount + enable integbp + change prop_factor_master |
9d5c8243 AK |
2178 | * to 8 for channel A |
2179 | */ | |
a8d2a0c2 | 2180 | hw->phy.ops.write_reg(hw, 0x1898, 0xD918); |
9d5c8243 | 2181 | /* Disable AHT in Slave mode on channel A */ |
a8d2a0c2 | 2182 | hw->phy.ops.write_reg(hw, 0x187A, 0x0800); |
b980ac18 | 2183 | /* Enable LPLU and disable AN to 1000 in non-D0a states, |
9d5c8243 AK |
2184 | * Enable SPD+B2B |
2185 | */ | |
a8d2a0c2 | 2186 | hw->phy.ops.write_reg(hw, 0x0019, 0x008D); |
9d5c8243 | 2187 | /* Enable restart AN on an1000_dis change */ |
a8d2a0c2 | 2188 | hw->phy.ops.write_reg(hw, 0x001B, 0x2080); |
9d5c8243 | 2189 | /* Enable wh_fifo read clock in 10/100 modes */ |
a8d2a0c2 | 2190 | hw->phy.ops.write_reg(hw, 0x0014, 0x0045); |
9d5c8243 | 2191 | /* Restart AN, Speed selection is 1000 */ |
a8d2a0c2 | 2192 | hw->phy.ops.write_reg(hw, 0x0000, 0x1340); |
9d5c8243 AK |
2193 | |
2194 | return 0; | |
2195 | } | |
2196 | ||
88a268c1 NN |
2197 | /** |
2198 | * igb_power_up_phy_copper - Restore copper link in case of PHY power down | |
2199 | * @hw: pointer to the HW structure | |
2200 | * | |
2201 | * In the case of a PHY power down to save power, or to turn off link during a | |
2202 | * driver unload, restore the link to previous settings. | |
2203 | **/ | |
2204 | void igb_power_up_phy_copper(struct e1000_hw *hw) | |
2205 | { | |
2206 | u16 mii_reg = 0; | |
f96a8a0b | 2207 | u16 power_reg = 0; |
88a268c1 NN |
2208 | |
2209 | /* The PHY will retain its settings across a power down/up cycle */ | |
2210 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); | |
2211 | mii_reg &= ~MII_CR_POWER_DOWN; | |
f96a8a0b CW |
2212 | if (hw->phy.type == e1000_phy_i210) { |
2213 | hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); | |
2214 | power_reg &= ~GS40G_CS_POWER_DOWN; | |
2215 | hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); | |
2216 | } | |
88a268c1 NN |
2217 | hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); |
2218 | } | |
2219 | ||
2220 | /** | |
2221 | * igb_power_down_phy_copper - Power down copper PHY | |
2222 | * @hw: pointer to the HW structure | |
2223 | * | |
2224 | * Power down PHY to save power when interface is down and wake on lan | |
2225 | * is not enabled. | |
2226 | **/ | |
2227 | void igb_power_down_phy_copper(struct e1000_hw *hw) | |
2228 | { | |
2229 | u16 mii_reg = 0; | |
f96a8a0b | 2230 | u16 power_reg = 0; |
88a268c1 NN |
2231 | |
2232 | /* The PHY will retain its settings across a power down/up cycle */ | |
2233 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); | |
2234 | mii_reg |= MII_CR_POWER_DOWN; | |
f96a8a0b CW |
2235 | |
2236 | /* i210 Phy requires an additional bit for power up/down */ | |
2237 | if (hw->phy.type == e1000_phy_i210) { | |
2238 | hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); | |
2239 | power_reg |= GS40G_CS_POWER_DOWN; | |
2240 | hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); | |
2241 | } | |
88a268c1 | 2242 | hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); |
0d451e79 | 2243 | usleep_range(1000, 2000); |
88a268c1 NN |
2244 | } |
2245 | ||
2909c3f7 AD |
2246 | /** |
2247 | * igb_check_polarity_82580 - Checks the polarity. | |
2248 | * @hw: pointer to the HW structure | |
2249 | * | |
2250 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
2251 | * | |
2252 | * Polarity is determined based on the PHY specific status register. | |
2253 | **/ | |
bb2ac47b | 2254 | static s32 igb_check_polarity_82580(struct e1000_hw *hw) |
2909c3f7 AD |
2255 | { |
2256 | struct e1000_phy_info *phy = &hw->phy; | |
2257 | s32 ret_val; | |
2258 | u16 data; | |
2259 | ||
2260 | ||
2261 | ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); | |
2262 | ||
2263 | if (!ret_val) | |
2264 | phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) | |
b980ac18 JK |
2265 | ? e1000_rev_polarity_reversed |
2266 | : e1000_rev_polarity_normal; | |
2909c3f7 AD |
2267 | |
2268 | return ret_val; | |
2269 | } | |
2270 | ||
2271 | /** | |
2272 | * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY | |
2273 | * @hw: pointer to the HW structure | |
2274 | * | |
2275 | * Calls the PHY setup function to force speed and duplex. Clears the | |
2276 | * auto-crossover to force MDI manually. Waits for link and returns | |
2277 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
2278 | **/ | |
2279 | s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) | |
2280 | { | |
2281 | struct e1000_phy_info *phy = &hw->phy; | |
2282 | s32 ret_val; | |
2283 | u16 phy_data; | |
2284 | bool link; | |
2285 | ||
2909c3f7 AD |
2286 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
2287 | if (ret_val) | |
2288 | goto out; | |
2289 | ||
2290 | igb_phy_force_speed_duplex_setup(hw, &phy_data); | |
2291 | ||
2292 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); | |
2293 | if (ret_val) | |
2294 | goto out; | |
2295 | ||
b980ac18 | 2296 | /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI |
2909c3f7 AD |
2297 | * forced whenever speed and duplex are forced. |
2298 | */ | |
2299 | ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); | |
2300 | if (ret_val) | |
2301 | goto out; | |
2302 | ||
1b556783 | 2303 | phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; |
2909c3f7 AD |
2304 | |
2305 | ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); | |
2306 | if (ret_val) | |
2307 | goto out; | |
2308 | ||
2309 | hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); | |
2310 | ||
2311 | udelay(1); | |
2312 | ||
2313 | if (phy->autoneg_wait_to_complete) { | |
2314 | hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); | |
2315 | ||
b980ac18 | 2316 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
2909c3f7 AD |
2317 | if (ret_val) |
2318 | goto out; | |
2319 | ||
2320 | if (!link) | |
2321 | hw_dbg("Link taking longer than expected.\n"); | |
2322 | ||
2323 | /* Try once more */ | |
b980ac18 | 2324 | ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); |
2909c3f7 AD |
2325 | if (ret_val) |
2326 | goto out; | |
2327 | } | |
2328 | ||
2329 | out: | |
2330 | return ret_val; | |
2331 | } | |
2332 | ||
2333 | /** | |
2334 | * igb_get_phy_info_82580 - Retrieve I82580 PHY information | |
2335 | * @hw: pointer to the HW structure | |
2336 | * | |
2337 | * Read PHY status to determine if link is up. If link is up, then | |
2338 | * set/determine 10base-T extended distance and polarity correction. Read | |
2339 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
2340 | * determine on the cable length, local and remote receiver. | |
2341 | **/ | |
2342 | s32 igb_get_phy_info_82580(struct e1000_hw *hw) | |
2343 | { | |
2344 | struct e1000_phy_info *phy = &hw->phy; | |
2345 | s32 ret_val; | |
2346 | u16 data; | |
2347 | bool link; | |
2348 | ||
2909c3f7 AD |
2349 | ret_val = igb_phy_has_link(hw, 1, 0, &link); |
2350 | if (ret_val) | |
2351 | goto out; | |
2352 | ||
2353 | if (!link) { | |
2354 | hw_dbg("Phy info is only valid if link is up\n"); | |
2355 | ret_val = -E1000_ERR_CONFIG; | |
2356 | goto out; | |
2357 | } | |
2358 | ||
2359 | phy->polarity_correction = true; | |
2360 | ||
2361 | ret_val = igb_check_polarity_82580(hw); | |
2362 | if (ret_val) | |
2363 | goto out; | |
2364 | ||
2365 | ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); | |
2366 | if (ret_val) | |
2367 | goto out; | |
2368 | ||
2369 | phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; | |
2370 | ||
2371 | if ((data & I82580_PHY_STATUS2_SPEED_MASK) == | |
2372 | I82580_PHY_STATUS2_SPEED_1000MBPS) { | |
2373 | ret_val = hw->phy.ops.get_cable_length(hw); | |
2374 | if (ret_val) | |
2375 | goto out; | |
2376 | ||
2377 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); | |
2378 | if (ret_val) | |
2379 | goto out; | |
2380 | ||
2381 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
b980ac18 JK |
2382 | ? e1000_1000t_rx_status_ok |
2383 | : e1000_1000t_rx_status_not_ok; | |
2909c3f7 AD |
2384 | |
2385 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
b980ac18 JK |
2386 | ? e1000_1000t_rx_status_ok |
2387 | : e1000_1000t_rx_status_not_ok; | |
2909c3f7 AD |
2388 | } else { |
2389 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2390 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2391 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2392 | } | |
2393 | ||
2394 | out: | |
2395 | return ret_val; | |
2396 | } | |
2397 | ||
2398 | /** | |
2399 | * igb_get_cable_length_82580 - Determine cable length for 82580 PHY | |
2400 | * @hw: pointer to the HW structure | |
2401 | * | |
2402 | * Reads the diagnostic status register and verifies result is valid before | |
2403 | * placing it in the phy_cable_length field. | |
2404 | **/ | |
2405 | s32 igb_get_cable_length_82580(struct e1000_hw *hw) | |
2406 | { | |
2407 | struct e1000_phy_info *phy = &hw->phy; | |
2408 | s32 ret_val; | |
2409 | u16 phy_data, length; | |
2410 | ||
2909c3f7 AD |
2411 | ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); |
2412 | if (ret_val) | |
2413 | goto out; | |
2414 | ||
2415 | length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> | |
b980ac18 | 2416 | I82580_DSTATUS_CABLE_LENGTH_SHIFT; |
2909c3f7 AD |
2417 | |
2418 | if (length == E1000_CABLE_LENGTH_UNDEFINED) | |
2419 | ret_val = -E1000_ERR_PHY; | |
2420 | ||
2421 | phy->cable_length = length; | |
2422 | ||
2423 | out: | |
2424 | return ret_val; | |
2425 | } | |
f96a8a0b CW |
2426 | |
2427 | /** | |
2428 | * igb_write_phy_reg_gs40g - Write GS40G PHY register | |
2429 | * @hw: pointer to the HW structure | |
2430 | * @offset: lower half is register offset to write to | |
2431 | * upper half is page to use. | |
2432 | * @data: data to write at register offset | |
2433 | * | |
2434 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2435 | * at the offset. Release any acquired semaphores before exiting. | |
2436 | **/ | |
2437 | s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) | |
2438 | { | |
2439 | s32 ret_val; | |
2440 | u16 page = offset >> GS40G_PAGE_SHIFT; | |
2441 | ||
2442 | offset = offset & GS40G_OFFSET_MASK; | |
2443 | ret_val = hw->phy.ops.acquire(hw); | |
2444 | if (ret_val) | |
2445 | return ret_val; | |
2446 | ||
2447 | ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); | |
2448 | if (ret_val) | |
2449 | goto release; | |
2450 | ret_val = igb_write_phy_reg_mdic(hw, offset, data); | |
2451 | ||
2452 | release: | |
2453 | hw->phy.ops.release(hw); | |
2454 | return ret_val; | |
2455 | } | |
2456 | ||
2457 | /** | |
2458 | * igb_read_phy_reg_gs40g - Read GS40G PHY register | |
2459 | * @hw: pointer to the HW structure | |
2460 | * @offset: lower half is register offset to read to | |
2461 | * upper half is page to use. | |
2462 | * @data: data to read at register offset | |
2463 | * | |
2464 | * Acquires semaphore, if necessary, then reads the data in the PHY register | |
2465 | * at the offset. Release any acquired semaphores before exiting. | |
2466 | **/ | |
2467 | s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) | |
2468 | { | |
2469 | s32 ret_val; | |
2470 | u16 page = offset >> GS40G_PAGE_SHIFT; | |
2471 | ||
2472 | offset = offset & GS40G_OFFSET_MASK; | |
2473 | ret_val = hw->phy.ops.acquire(hw); | |
2474 | if (ret_val) | |
2475 | return ret_val; | |
2476 | ||
2477 | ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); | |
2478 | if (ret_val) | |
2479 | goto release; | |
2480 | ret_val = igb_read_phy_reg_mdic(hw, offset, data); | |
2481 | ||
2482 | release: | |
2483 | hw->phy.ops.release(hw); | |
2484 | return ret_val; | |
2485 | } | |
2486 | ||
2487 | /** | |
2488 | * igb_set_master_slave_mode - Setup PHY for Master/slave mode | |
2489 | * @hw: pointer to the HW structure | |
2490 | * | |
2491 | * Sets up Master/slave mode | |
2492 | **/ | |
2493 | static s32 igb_set_master_slave_mode(struct e1000_hw *hw) | |
2494 | { | |
2495 | s32 ret_val; | |
2496 | u16 phy_data; | |
2497 | ||
2498 | /* Resolve Master/Slave mode */ | |
2499 | ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); | |
2500 | if (ret_val) | |
2501 | return ret_val; | |
2502 | ||
2503 | /* load defaults for future use */ | |
2504 | hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? | |
2505 | ((phy_data & CR_1000T_MS_VALUE) ? | |
2506 | e1000_ms_force_master : | |
2507 | e1000_ms_force_slave) : e1000_ms_auto; | |
2508 | ||
2509 | switch (hw->phy.ms_type) { | |
2510 | case e1000_ms_force_master: | |
2511 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
2512 | break; | |
2513 | case e1000_ms_force_slave: | |
2514 | phy_data |= CR_1000T_MS_ENABLE; | |
2515 | phy_data &= ~(CR_1000T_MS_VALUE); | |
2516 | break; | |
2517 | case e1000_ms_auto: | |
2518 | phy_data &= ~CR_1000T_MS_ENABLE; | |
2519 | /* fall-through */ | |
2520 | default: | |
2521 | break; | |
2522 | } | |
2523 | ||
2524 | return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); | |
2525 | } |