[deliverable/linux.git] / drivers / net / ethernet / intel / igb / e1000_phy.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2014 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, see <http://www.gnu.org/licenses/>.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_PHY_H_
#define _E1000_PHY_H_

enum e1000_ms_type {
	e1000_ms_hw_default = 0,
	e1000_ms_force_master,
	e1000_ms_force_slave,
	e1000_ms_auto
};

enum e1000_smart_speed {
	e1000_smart_speed_default = 0,
	e1000_smart_speed_on,
	e1000_smart_speed_off
};

s32  igb_check_downshift(struct e1000_hw *hw);
s32  igb_check_reset_block(struct e1000_hw *hw);
s32  igb_copper_link_setup_igp(struct e1000_hw *hw);
s32  igb_copper_link_setup_m88(struct e1000_hw *hw);
s32  igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);
s32  igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
s32  igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
s32  igb_get_cable_length_m88(struct e1000_hw *hw);
s32  igb_get_cable_length_m88_gen2(struct e1000_hw *hw);
s32  igb_get_cable_length_igp_2(struct e1000_hw *hw);
s32  igb_get_phy_id(struct e1000_hw *hw);
s32  igb_get_phy_info_igp(struct e1000_hw *hw);
s32  igb_get_phy_info_m88(struct e1000_hw *hw);
s32  igb_phy_sw_reset(struct e1000_hw *hw);
s32  igb_phy_hw_reset(struct e1000_hw *hw);
s32  igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
s32  igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
s32  igb_setup_copper_link(struct e1000_hw *hw);
s32  igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
s32  igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
				u32 usec_interval, bool *success);
void igb_power_up_phy_copper(struct e1000_hw *hw);
void igb_power_down_phy_copper(struct e1000_hw *hw);
s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
s32  igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
s32  igb_copper_link_setup_82580(struct e1000_hw *hw);
s32  igb_get_phy_info_82580(struct e1000_hw *hw);
s32  igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
s32  igb_get_cable_length_82580(struct e1000_hw *hw);
s32  igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
s32  igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
s32  igb_check_polarity_m88(struct e1000_hw *hw);

/* IGP01E1000 Specific Registers */
#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
#define IGP01E1000_PHY_POLARITY_MASK      0x0078
#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
#define IGP01E1000_PSCFR_SMART_SPEED      0x0080

#define I82580_ADDR_REG                   16
#define I82580_CFG_REG                    22
#define I82580_CFG_ASSERT_CRS_ON_TX       (1 << 15)
#define I82580_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
#define I82580_CTRL_REG                   23
#define I82580_CTRL_DOWNSHIFT_MASK        (7 << 10)

/* 82580 specific PHY registers */
#define I82580_PHY_CTRL_2            18
#define I82580_PHY_LBK_CTRL          19
#define I82580_PHY_STATUS_2          26
#define I82580_PHY_DIAG_STATUS       31

/* I82580 PHY Status 2 */
#define I82580_PHY_STATUS2_REV_POLARITY   0x0400
#define I82580_PHY_STATUS2_MDIX           0x0800
#define I82580_PHY_STATUS2_SPEED_MASK     0x0300
#define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200
#define I82580_PHY_STATUS2_SPEED_100MBPS  0x0100

/* I82580 PHY Control 2 */
#define I82580_PHY_CTRL2_MANUAL_MDIX      0x0200
#define I82580_PHY_CTRL2_AUTO_MDI_MDIX    0x0400
#define I82580_PHY_CTRL2_MDIX_CFG_MASK    0x0600

/* I82580 PHY Diagnostics Status */
#define I82580_DSTATUS_CABLE_LENGTH       0x03FC
#define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2

/* 82580 PHY Power Management */
#define E1000_82580_PHY_POWER_MGMT	0xE14
#define E1000_82580_PM_SPD		0x0001 /* Smart Power Down */
#define E1000_82580_PM_D0_LPLU		0x0002 /* For D0a states */
#define E1000_82580_PM_D3_LPLU		0x0004 /* For all other states */
#define E1000_82580_PM_GO_LINKD		0x0020 /* Go Link Disconnect */

/* Enable flexible speed on link-up */
#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
#define IGP01E1000_PSSR_MDIX              0x0800
#define IGP01E1000_PSSR_SPEED_MASK        0xC000
#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
#define IGP02E1000_PHY_CHANNEL_NUM        4
#define IGP02E1000_PHY_AGC_A              0x11B1
#define IGP02E1000_PHY_AGC_B              0x12B1
#define IGP02E1000_PHY_AGC_C              0x14B1
#define IGP02E1000_PHY_AGC_D              0x18B1
#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
#define IGP02E1000_AGC_LENGTH_MASK        0x7F
#define IGP02E1000_AGC_RANGE              15

#define E1000_CABLE_LENGTH_UNDEFINED      0xFF

/* GS40G - I210 PHY defines */
#define GS40G_PAGE_SELECT		0x16
#define GS40G_PAGE_SHIFT		16
#define GS40G_OFFSET_MASK		0xFFFF
#define GS40G_PAGE_2			0x20000
#define GS40G_MAC_REG2			0x15
#define GS40G_MAC_LB			0x4140
#define GS40G_MAC_SPEED_1G		0X0006
#define GS40G_COPPER_SPEC		0x0010
#define GS40G_CS_POWER_DOWN		0x0002
#define GS40G_LINE_LB			0x4000

/* SFP modules ID memory locations */
#define E1000_SFF_IDENTIFIER_OFFSET	0x00
#define E1000_SFF_IDENTIFIER_SFF	0x02
#define E1000_SFF_IDENTIFIER_SFP	0x03

#define E1000_SFF_ETH_FLAGS_OFFSET	0x06
/* Flags for SFP modules compatible with ETH up to 1Gb */
struct e1000_sfp_flags {
	u8 e1000_base_sx:1;
	u8 e1000_base_lx:1;
	u8 e1000_base_cx:1;
	u8 e1000_base_t:1;
	u8 e100_base_lx:1;
	u8 e100_base_fx:1;
	u8 e10_base_bx10:1;
	u8 e10_base_px:1;
};

#endif
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
74cfb2e1	4	Copyright(c) 2007-2014 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
74cfb2e1	16	this program; if not, see <http://www.gnu.org/licenses/>.
9d5c8243 AK	17
	18	The full GNU General Public License is included in this distribution in
	19	the file called "COPYING".
	20
	21	Contact Information:
	22	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	23	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	24
	25	*******************************************************************************/
	26
	27	#ifndef _E1000_PHY_H_
	28	#define _E1000_PHY_H_
	29
	30	enum e1000_ms_type {
	31	e1000_ms_hw_default = 0,
	32	e1000_ms_force_master,
	33	e1000_ms_force_slave,
	34	e1000_ms_auto
	35	};
	36
	37	enum e1000_smart_speed {
	38	e1000_smart_speed_default = 0,
	39	e1000_smart_speed_on,
	40	e1000_smart_speed_off
	41	};
	42
	43	s32 igb_check_downshift(struct e1000_hw *hw);
	44	s32 igb_check_reset_block(struct e1000_hw *hw);
9d5c8243 AK	45	s32 igb_copper_link_setup_igp(struct e1000_hw *hw);
9d5c8243 AK	46	s32 igb_copper_link_setup_m88(struct e1000_hw *hw);
308fb39a	47	s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);
9d5c8243 AK	48	s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
	49	s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
	50	s32 igb_get_cable_length_m88(struct e1000_hw *hw);
308fb39a	51	s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw);
9d5c8243 AK	52	s32 igb_get_cable_length_igp_2(struct e1000_hw *hw);
	53	s32 igb_get_phy_id(struct e1000_hw *hw);
	54	s32 igb_get_phy_info_igp(struct e1000_hw *hw);
	55	s32 igb_get_phy_info_m88(struct e1000_hw *hw);
	56	s32 igb_phy_sw_reset(struct e1000_hw *hw);
	57	s32 igb_phy_hw_reset(struct e1000_hw *hw);
	58	s32 igb_read_phy_reg_igp(struct e1000_hw hw, u32 offset, u16 data);
	59	s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
81fadd81	60	s32 igb_setup_copper_link(struct e1000_hw *hw);
9d5c8243 AK	61	s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
	62	s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
	63	u32 usec_interval, bool *success);
88a268c1 NN	64	void igb_power_up_phy_copper(struct e1000_hw *hw);
88a268c1 NN	65	void igb_power_down_phy_copper(struct e1000_hw *hw);
9d5c8243	66	s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
bb2ac47b AD	67	s32 igb_read_phy_reg_mdic(struct e1000_hw hw, u32 offset, u16 data);
bb2ac47b AD	68	s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
bf6f7a92 AD	69	s32 igb_read_phy_reg_i2c(struct e1000_hw hw, u32 offset, u16 data);
bf6f7a92 AD	70	s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
641ac5c0	71	s32 igb_read_sfp_data_byte(struct e1000_hw hw, u16 offset, u8 data);
2909c3f7	72	s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
2909c3f7 AD	73	s32 igb_get_phy_info_82580(struct e1000_hw *hw);
	74	s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
	75	s32 igb_get_cable_length_82580(struct e1000_hw *hw);
f96a8a0b CW	76	s32 igb_read_phy_reg_gs40g(struct e1000_hw hw, u32 offset, u16 data);
	77	s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
	78	s32 igb_check_polarity_m88(struct e1000_hw *hw);
9d5c8243 AK	79
	80	/* IGP01E1000 Specific Registers */
	81	#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
	82	#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
	83	#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
	84	#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
	85	#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
	86	#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
	87	#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
	88	#define IGP01E1000_PHY_POLARITY_MASK 0x0078
	89	#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
	90	#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
	91	#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
	92
2909c3f7 AD	93	#define I82580_ADDR_REG 16
	94	#define I82580_CFG_REG 22
	95	#define I82580_CFG_ASSERT_CRS_ON_TX (1 << 15)
	96	#define I82580_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
	97	#define I82580_CTRL_REG 23
	98	#define I82580_CTRL_DOWNSHIFT_MASK (7 << 10)
	99
	100	/* 82580 specific PHY registers */
	101	#define I82580_PHY_CTRL_2 18
	102	#define I82580_PHY_LBK_CTRL 19
	103	#define I82580_PHY_STATUS_2 26
	104	#define I82580_PHY_DIAG_STATUS 31
	105
	106	/* I82580 PHY Status 2 */
	107	#define I82580_PHY_STATUS2_REV_POLARITY 0x0400
	108	#define I82580_PHY_STATUS2_MDIX 0x0800
	109	#define I82580_PHY_STATUS2_SPEED_MASK 0x0300
	110	#define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200
	111	#define I82580_PHY_STATUS2_SPEED_100MBPS 0x0100
	112
	113	/* I82580 PHY Control 2 */
1b556783 JB	114	#define I82580_PHY_CTRL2_MANUAL_MDIX 0x0200
	115	#define I82580_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
	116	#define I82580_PHY_CTRL2_MDIX_CFG_MASK 0x0600
2909c3f7 AD	117
	118	/* I82580 PHY Diagnostics Status */
	119	#define I82580_DSTATUS_CABLE_LENGTH 0x03FC
	120	#define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2
da02cde1 CW	121
	122	/* 82580 PHY Power Management */
	123	#define E1000_82580_PHY_POWER_MGMT 0xE14
	124	#define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */
	125	#define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */
	126	#define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */
867eb39e	127	#define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */
da02cde1	128
9d5c8243 AK	129	/* Enable flexible speed on link-up */
	130	#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
	131	#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
	132	#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
	133	#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
cbe7a81a	134	#define IGP01E1000_PSSR_MDIX 0x0800
9d5c8243 AK	135	#define IGP01E1000_PSSR_SPEED_MASK 0xC000
	136	#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
	137	#define IGP02E1000_PHY_CHANNEL_NUM 4
	138	#define IGP02E1000_PHY_AGC_A 0x11B1
	139	#define IGP02E1000_PHY_AGC_B 0x12B1
	140	#define IGP02E1000_PHY_AGC_C 0x14B1
	141	#define IGP02E1000_PHY_AGC_D 0x18B1
	142	#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
	143	#define IGP02E1000_AGC_LENGTH_MASK 0x7F
	144	#define IGP02E1000_AGC_RANGE 15
	145
	146	#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
	147
f96a8a0b CW	148	/* GS40G - I210 PHY defines */
	149	#define GS40G_PAGE_SELECT 0x16
	150	#define GS40G_PAGE_SHIFT 16
	151	#define GS40G_OFFSET_MASK 0xFFFF
	152	#define GS40G_PAGE_2 0x20000
	153	#define GS40G_MAC_REG2 0x15
	154	#define GS40G_MAC_LB 0x4140
	155	#define GS40G_MAC_SPEED_1G 0X0006
	156	#define GS40G_COPPER_SPEC 0x0010
	157	#define GS40G_CS_POWER_DOWN 0x0002
	158	#define GS40G_LINE_LB 0x4000
	159
641ac5c0 AA	160	/* SFP modules ID memory locations */
	161	#define E1000_SFF_IDENTIFIER_OFFSET 0x00
	162	#define E1000_SFF_IDENTIFIER_SFF 0x02
	163	#define E1000_SFF_IDENTIFIER_SFP 0x03
	164
	165	#define E1000_SFF_ETH_FLAGS_OFFSET 0x06
	166	/* Flags for SFP modules compatible with ETH up to 1Gb */
	167	struct e1000_sfp_flags {
	168	u8 e1000_base_sx:1;
	169	u8 e1000_base_lx:1;
	170	u8 e1000_base_cx:1;
	171	u8 e1000_base_t:1;
	172	u8 e100_base_lx:1;
	173	u8 e100_base_fx:1;
	174	u8 e10_base_bx10:1;
	175	u8 e10_base_px:1;
	176	};
	177
9d5c8243	178	#endif