[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2013 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>

struct igb_adapter;

#define E1000_PCS_CFG_IGN_SD	1

/* Interrupt defines */
#define IGB_START_ITR		648 /* ~6000 ints/sec */
#define IGB_4K_ITR		980
#define IGB_20K_ITR		196
#define IGB_70K_ITR		56

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD		256
#define IGB_DEFAULT_TX_WORK	128
#define IGB_MIN_TXD		80
#define IGB_MAX_TXD		4096

#define IGB_DEFAULT_RXD		256
#define IGB_MIN_RXD		80
#define IGB_MAX_RXD		4096

#define IGB_DEFAULT_ITR		3 /* dynamic */
#define IGB_MAX_ITR_USECS	10000
#define IGB_MIN_ITR_USECS	10
#define NON_Q_VECTORS		1
#define MAX_Q_VECTORS		8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES	8
#define IGB_MAX_RX_QUEUES_82575	4
#define IGB_MAX_RX_QUEUES_I211	2
#define IGB_MAX_TX_QUEUES	8
#define IGB_MAX_VF_MC_ENTRIES	30
#define IGB_MAX_VF_FUNCTIONS	8
#define IGB_MAX_VFTA_ENTRIES	128
#define IGB_82576_VF_DEV_ID	0x10CA
#define IGB_I350_VF_DEV_ID	0x1520

/* NVM version defines */
#define IGB_MAJOR_MASK		0xF000
#define IGB_MINOR_MASK		0x0FF0
#define IGB_BUILD_MASK		0x000F
#define IGB_COMB_VER_MASK	0x00FF
#define IGB_MAJOR_SHIFT		12
#define IGB_MINOR_SHIFT		4
#define IGB_COMB_VER_SHFT	8
#define IGB_NVM_VER_INVALID	0xFFFF
#define IGB_ETRACK_SHIFT	16
#define NVM_ETRACK_WORD		0x0042
#define NVM_COMB_VER_OFF	0x0083
#define NVM_COMB_VER_PTR	0x003d

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	u32 flags;
	unsigned long last_nack;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
	u16 tx_rate;
	bool spoofchk_enabled;
};

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH	((hw->mac.type == e1000_i354) ? 12 : 8)
#define IGB_RX_HTHRESH	8
#define IGB_TX_PTHRESH	((hw->mac.type == e1000_i354) ? 20 : 8)
#define IGB_TX_HTHRESH	1
#define IGB_RX_WTHRESH	((hw->mac.type == e1000_82576 && \
			  adapter->msix_entries) ? 1 : 4)
#define IGB_TX_WTHRESH	((hw->mac.type == e1000_82576 && \
			  adapter->msix_entries) ? 1 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_256	256
#define IGB_RXBUFFER_2048	2048
#define IGB_RX_HDR_LEN		IGB_RXBUFFER_256
#define IGB_RX_BUFSZ		IGB_RXBUFFER_2048

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16 /* Must be power of 2 */

#define AUTO_ALL_MODES		0
#define IGB_EEPROM_APME		0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE	-1

enum igb_tx_flags {
	/* cmd_type flags */
	IGB_TX_FLAGS_VLAN	= 0x01,
	IGB_TX_FLAGS_TSO	= 0x02,
	IGB_TX_FLAGS_TSTAMP	= 0x04,

	/* olinfo flags */
	IGB_TX_FLAGS_IPV4	= 0x10,
	IGB_TX_FLAGS_CSUM	= 0x20,
};

/* VLAN info */
#define IGB_TX_FLAGS_VLAN_MASK	0xffff0000
#define IGB_TX_FLAGS_VLAN_SHIFT	16

/* The largest size we can write to the descriptor is 65535.  In order to
 * maintain a power of two alignment we have to limit ourselves to 32K.
 */
#define IGB_MAX_TXD_PWR	15
#define IGB_MAX_DATA_PER_TXD	(1 << IGB_MAX_TXD_PWR)

/* Tx Descriptors needed, worst case */
#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
#define DESC_NEEDED (MAX_SKB_FRAGS + 4)

/* EEPROM byte offsets */
#define IGB_SFF_8472_SWAP		0x5C
#define IGB_SFF_8472_COMP		0x5E

/* Bitmasks */
#define IGB_SFF_ADDRESSING_MODE		0x4
#define IGB_SFF_8472_UNSUP		0x00

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer
 */
struct igb_tx_buffer {
	union e1000_adv_tx_desc *next_to_watch;
	unsigned long time_stamp;
	struct sk_buff *skb;
	unsigned int bytecount;
	u16 gso_segs;
	__be16 protocol;
	DEFINE_DMA_UNMAP_ADDR(dma);
	DEFINE_DMA_UNMAP_LEN(len);
	u32 tx_flags;
};

struct igb_rx_buffer {
	dma_addr_t dma;
	struct page *page;
	unsigned int page_offset;
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 restart_queue2;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_ring_container {
	struct igb_ring *ring;		/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u16 work_limit;			/* total work allowed per interrupt */
	u8 count;			/* total number of rings in vector */
	u8 itr;				/* current ITR setting for ring */
};

struct igb_ring {
	struct igb_q_vector *q_vector;	/* backlink to q_vector */
	struct net_device *netdev;	/* back pointer to net_device */
	struct device *dev;		/* device pointer for dma mapping */
	union {				/* array of buffer info structs */
		struct igb_tx_buffer *tx_buffer_info;
		struct igb_rx_buffer *rx_buffer_info;
	};
	unsigned long last_rx_timestamp;
	void *desc;			/* descriptor ring memory */
	unsigned long flags;		/* ring specific flags */
	void __iomem *tail;		/* pointer to ring tail register */
	dma_addr_t dma;			/* phys address of the ring */
	unsigned int  size;		/* length of desc. ring in bytes */

	u16 count;			/* number of desc. in the ring */
	u8 queue_index;			/* logical index of the ring*/
	u8 reg_idx;			/* physical index of the ring */

	/* everything past this point are written often */
	u16 next_to_clean;
	u16 next_to_use;
	u16 next_to_alloc;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			struct u64_stats_sync tx_syncp;
			struct u64_stats_sync tx_syncp2;
		};
		/* RX */
		struct {
			struct sk_buff *skb;
			struct igb_rx_queue_stats rx_stats;
			struct u64_stats_sync rx_syncp;
		};
	};
} ____cacheline_internodealigned_in_smp;

struct igb_q_vector {
	struct igb_adapter *adapter;	/* backlink */
	int cpu;			/* CPU for DCA */
	u32 eims_value;			/* EIMS mask value */

	u16 itr_val;
	u8 set_itr;
	void __iomem *itr_register;

	struct igb_ring_container rx, tx;

	struct napi_struct napi;
	struct rcu_head rcu;	/* to avoid race with update stats on free */
	char name[IFNAMSIZ + 9];

	/* for dynamic allocation of rings associated with this q_vector */
	struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
};

enum e1000_ring_flags_t {
	IGB_RING_FLAG_RX_SCTP_CSUM,
	IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
	IGB_RING_FLAG_TX_CTX_IDX,
	IGB_RING_FLAG_TX_DETECT_HANG
};

#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)

#define IGB_RX_DESC(R, i)	\
	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
#define IGB_TX_DESC(R, i)	\
	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
#define IGB_TX_CTXTDESC(R, i)	\
	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))

/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
				      const u32 stat_err_bits)
{
	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
}

/* igb_desc_unused - calculate if we have unused descriptors */
static inline int igb_desc_unused(struct igb_ring *ring)
{
	if (ring->next_to_clean > ring->next_to_use)
		return ring->next_to_clean - ring->next_to_use - 1;

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
}

#ifdef CONFIG_IGB_HWMON

#define IGB_HWMON_TYPE_LOC	0
#define IGB_HWMON_TYPE_TEMP	1
#define IGB_HWMON_TYPE_CAUTION	2
#define IGB_HWMON_TYPE_MAX	3

struct hwmon_attr {
	struct device_attribute dev_attr;
	struct e1000_hw *hw;
	struct e1000_thermal_diode_data *sensor;
	char name[12];
	};

struct hwmon_buff {
	struct device *device;
	struct hwmon_attr *hwmon_list;
	unsigned int n_hwmon;
	};
#endif

/* board specific private data structure */
struct igb_adapter {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

	struct net_device *netdev;

	unsigned long state;
	unsigned int flags;

	unsigned int num_q_vectors;
	struct msix_entry *msix_entries;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	/* TX */
	u16 tx_work_limit;
	u32 tx_timeout_count;
	int num_tx_queues;
	struct igb_ring *tx_ring[16];

	/* RX */
	int num_rx_queues;
	struct igb_ring *rx_ring[16];

	u32 max_frame_size;
	u32 min_frame_size;

	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;

	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* OS defined structs */
	struct pci_dev *pdev;

	spinlock_t stats64_lock;
	struct rtnl_link_stats64 stats64;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	u16 tx_ring_count;
	u16 rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
	int vf_rate_link_speed;
	u32 rss_queues;
	u32 wvbr;
	u32 *shadow_vfta;

	struct ptp_clock *ptp_clock;
	struct ptp_clock_info ptp_caps;
	struct delayed_work ptp_overflow_work;
	struct work_struct ptp_tx_work;
	struct sk_buff *ptp_tx_skb;
	unsigned long ptp_tx_start;
	unsigned long last_rx_ptp_check;
	spinlock_t tmreg_lock;
	struct cyclecounter cc;
	struct timecounter tc;
	u32 tx_hwtstamp_timeouts;
	u32 rx_hwtstamp_cleared;

	char fw_version[32];
#ifdef CONFIG_IGB_HWMON
	struct hwmon_buff igb_hwmon_buff;
	bool ets;
#endif
	struct i2c_algo_bit_data i2c_algo;
	struct i2c_adapter i2c_adap;
	struct i2c_client *i2c_client;
};

#define IGB_FLAG_HAS_MSI		(1 << 0)
#define IGB_FLAG_DCA_ENABLED		(1 << 1)
#define IGB_FLAG_QUAD_PORT_A		(1 << 2)
#define IGB_FLAG_QUEUE_PAIRS		(1 << 3)
#define IGB_FLAG_DMAC			(1 << 4)
#define IGB_FLAG_PTP			(1 << 5)
#define IGB_FLAG_RSS_FIELD_IPV4_UDP	(1 << 6)
#define IGB_FLAG_RSS_FIELD_IPV6_UDP	(1 << 7)
#define IGB_FLAG_WOL_SUPPORTED		(1 << 8)

/* DMA Coalescing defines */
#define IGB_MIN_TXPBSIZE	20408
#define IGB_TX_BUF_4096		4096
#define IGB_DMCTLX_DCFLUSH_DIS	0x80000000  /* Disable DMA Coal Flush */

#define IGB_82576_TSYNC_SHIFT	19
#define IGB_TS_HDR_LEN		16
enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_setup_tctl(struct igb_adapter *);
extern void igb_setup_rctl(struct igb_adapter *);
extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
					   struct igb_tx_buffer *);
extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
extern bool igb_has_link(struct igb_adapter *adapter);
extern void igb_set_ethtool_ops(struct net_device *);
extern void igb_power_up_link(struct igb_adapter *);
extern void igb_set_fw_version(struct igb_adapter *);
extern void igb_ptp_init(struct igb_adapter *adapter);
extern void igb_ptp_stop(struct igb_adapter *adapter);
extern void igb_ptp_reset(struct igb_adapter *adapter);
extern void igb_ptp_tx_work(struct work_struct *work);
extern void igb_ptp_rx_hang(struct igb_adapter *adapter);
extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
				struct sk_buff *skb);
extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
				unsigned char *va,
				struct sk_buff *skb);
static inline void igb_ptp_rx_hwtstamp(struct igb_ring *rx_ring,
				       union e1000_adv_rx_desc *rx_desc,
				       struct sk_buff *skb)
{
	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
	    !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
		igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);

	/* Update the last_rx_timestamp timer in order to enable watchdog check
	 * for error case of latched timestamp on a dropped packet.
	 */
	rx_ring->last_rx_timestamp = jiffies;
}

extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
				  struct ifreq *ifr, int cmd);
#ifdef CONFIG_IGB_HWMON
extern void igb_sysfs_exit(struct igb_adapter *adapter);
extern int igb_sysfs_init(struct igb_adapter *adapter);
#endif
static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
{
	return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
4b9ea462	4	Copyright(c) 2007-2013 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc	38	#include <linux/net_tstamp.h>
d339b133	39	#include <linux/ptp_clock_kernel.h>
b2cb09b1 JP	40	#include <linux/bitops.h>
b2cb09b1 JP	41	#include <linux/if_vlan.h>
441fc6fd CW	42	#include <linux/i2c.h>
441fc6fd CW	43	#include <linux/i2c-algo-bit.h>
38c845c7	44
9d5c8243 AK	45	struct igb_adapter;
9d5c8243 AK	46
b980ac18	47	#define E1000_PCS_CFG_IGN_SD 1
3860a0bf	48
0ba82994	49	/* Interrupt defines */
b980ac18 JK	50	#define IGB_START_ITR 648 /* ~6000 ints/sec */
	51	#define IGB_4K_ITR 980
	52	#define IGB_20K_ITR 196
	53	#define IGB_70K_ITR 56
9d5c8243	54
9d5c8243	55	/* TX/RX descriptor defines */
b980ac18 JK	56	#define IGB_DEFAULT_TXD 256
	57	#define IGB_DEFAULT_TX_WORK 128
	58	#define IGB_MIN_TXD 80
	59	#define IGB_MAX_TXD 4096
9d5c8243	60
b980ac18 JK	61	#define IGB_DEFAULT_RXD 256
	62	#define IGB_MIN_RXD 80
	63	#define IGB_MAX_RXD 4096
9d5c8243	64
b980ac18 JK	65	#define IGB_DEFAULT_ITR 3 /* dynamic */
	66	#define IGB_MAX_ITR_USECS 10000
	67	#define IGB_MIN_ITR_USECS 10
	68	#define NON_Q_VECTORS 1
	69	#define MAX_Q_VECTORS 8
9d5c8243 AK	70
9d5c8243 AK	71	/* Transmit and receive queues */
b980ac18 JK	72	#define IGB_MAX_RX_QUEUES 8
	73	#define IGB_MAX_RX_QUEUES_82575 4
	74	#define IGB_MAX_RX_QUEUES_I211 2
	75	#define IGB_MAX_TX_QUEUES 8
	76	#define IGB_MAX_VF_MC_ENTRIES 30
	77	#define IGB_MAX_VF_FUNCTIONS 8
	78	#define IGB_MAX_VFTA_ENTRIES 128
	79	#define IGB_82576_VF_DEV_ID 0x10CA
	80	#define IGB_I350_VF_DEV_ID 0x1520
4ae196df	81
d67974f0	82	/* NVM version defines */
b980ac18 JK	83	#define IGB_MAJOR_MASK 0xF000
	84	#define IGB_MINOR_MASK 0x0FF0
	85	#define IGB_BUILD_MASK 0x000F
	86	#define IGB_COMB_VER_MASK 0x00FF
	87	#define IGB_MAJOR_SHIFT 12
	88	#define IGB_MINOR_SHIFT 4
	89	#define IGB_COMB_VER_SHFT 8
	90	#define IGB_NVM_VER_INVALID 0xFFFF
	91	#define IGB_ETRACK_SHIFT 16
	92	#define NVM_ETRACK_WORD 0x0042
	93	#define NVM_COMB_VER_OFF 0x0083
	94	#define NVM_COMB_VER_PTR 0x003d
d67974f0	95
4ae196df AD	96	struct vf_data_storage {
	97	unsigned char vf_mac_addresses[ETH_ALEN];
	98	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	99	u16 num_vf_mc_hashes;
ae641bdc	100	u16 vlans_enabled;
f2ca0dbe AD	101	u32 flags;
f2ca0dbe AD	102	unsigned long last_nack;
8151d294 WM	103	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
8151d294 WM	104	u16 pf_qos;
17dc566c	105	u16 tx_rate;
70ea4783	106	bool spoofchk_enabled;
4ae196df AD	107	};
4ae196df AD	108
f2ca0dbe	109	#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
7d5753f0 AD	110	#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
7d5753f0 AD	111	#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
8151d294	112	#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
f2ca0dbe	113
9d5c8243 AK	114	/* RX descriptor control thresholds.
	115	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	116	* descriptors available in its onboard memory.
	117	* Setting this to 0 disables RX descriptor prefetch.
	118	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	119	* available in host memory.
	120	* If PTHRESH is 0, this should also be 0.
	121	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	122	* descriptors until either it has this many to write back, or the
	123	* ITR timer expires.
	124	*/
ceb5f13b	125	#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
b980ac18	126	#define IGB_RX_HTHRESH 8
ceb5f13b	127	#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
b980ac18 JK	128	#define IGB_TX_HTHRESH 1
	129	#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
	130	adapter->msix_entries) ? 1 : 4)
	131	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
	132	adapter->msix_entries) ? 1 : 16)
9d5c8243 AK	133
	134	/* this is the size past which hardware will drop packets when setting LPE=0 */
	135	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	136
	137	/* Supported Rx Buffer Sizes */
de78d1f9 AD	138	#define IGB_RXBUFFER_256 256
	139	#define IGB_RXBUFFER_2048 2048
	140	#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
	141	#define IGB_RX_BUFSZ IGB_RXBUFFER_2048
9d5c8243	142
9d5c8243	143	/* How many Rx Buffers do we bundle into one write to the hardware ? */
b980ac18	144	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
9d5c8243	145
b980ac18 JK	146	#define AUTO_ALL_MODES 0
b980ac18 JK	147	#define IGB_EEPROM_APME 0x0400
9d5c8243 AK	148
	149	#ifndef IGB_MASTER_SLAVE
	150	/* Switch to override PHY master/slave setting */
	151	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	152	#endif
	153
b980ac18	154	#define IGB_MNG_VLAN_NONE -1
9d5c8243	155
1d9daf45 AD	156	enum igb_tx_flags {
	157	/* cmd_type flags */
	158	IGB_TX_FLAGS_VLAN = 0x01,
	159	IGB_TX_FLAGS_TSO = 0x02,
	160	IGB_TX_FLAGS_TSTAMP = 0x04,
	161
	162	/* olinfo flags */
	163	IGB_TX_FLAGS_IPV4 = 0x10,
	164	IGB_TX_FLAGS_CSUM = 0x20,
	165	};
	166
	167	/* VLAN info */
b980ac18	168	#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2bbfebe2 AD	169	#define IGB_TX_FLAGS_VLAN_SHIFT 16
2bbfebe2 AD	170
b980ac18	171	/* The largest size we can write to the descriptor is 65535. In order to
21ba6fe1 AD	172	* maintain a power of two alignment we have to limit ourselves to 32K.
	173	*/
	174	#define IGB_MAX_TXD_PWR 15
	175	#define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR)
	176
	177	/* Tx Descriptors needed, worst case */
	178	#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
	179	#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
	180
f69aa390 AA	181	/* EEPROM byte offsets */
	182	#define IGB_SFF_8472_SWAP 0x5C
	183	#define IGB_SFF_8472_COMP 0x5E
	184
	185	/* Bitmasks */
	186	#define IGB_SFF_ADDRESSING_MODE 0x4
	187	#define IGB_SFF_8472_UNSUP 0x00
	188
9d5c8243	189	/* wrapper around a pointer to a socket buffer,
b980ac18 JK	190	* so a DMA handle can be stored along with the buffer
b980ac18 JK	191	*/
06034649	192	struct igb_tx_buffer {
8542db05	193	union e1000_adv_tx_desc *next_to_watch;
06034649	194	unsigned long time_stamp;
06034649 AD	195	struct sk_buff *skb;
	196	unsigned int bytecount;
	197	u16 gso_segs;
7af40ad9	198	__be16 protocol;
c9f14bf3 AD	199	DEFINE_DMA_UNMAP_ADDR(dma);
c9f14bf3 AD	200	DEFINE_DMA_UNMAP_LEN(len);
ebe42d16	201	u32 tx_flags;
06034649 AD	202	};
	203
	204	struct igb_rx_buffer {
9d5c8243	205	dma_addr_t dma;
06034649	206	struct page *page;
1a1c225b	207	unsigned int page_offset;
9d5c8243 AK	208	};
9d5c8243 AK	209
8c0ab70a	210	struct igb_tx_queue_stats {
9d5c8243 AK	211	u64 packets;
9d5c8243 AK	212	u64 bytes;
04a5fcaa	213	u64 restart_queue;
12dcd86b	214	u64 restart_queue2;
9d5c8243 AK	215	};
9d5c8243 AK	216
8c0ab70a JDB	217	struct igb_rx_queue_stats {
	218	u64 packets;
	219	u64 bytes;
	220	u64 drops;
04a5fcaa AD	221	u64 csum_err;
04a5fcaa AD	222	u64 alloc_failed;
8c0ab70a JDB	223	};
8c0ab70a JDB	224
0ba82994 AD	225	struct igb_ring_container {
	226	struct igb_ring ring; / pointer to linked list of rings */
	227	unsigned int total_bytes; /* total bytes processed this int */
	228	unsigned int total_packets; /* total packets processed this int */
	229	u16 work_limit; /* total work allowed per interrupt */
	230	u8 count; /* total number of rings in vector */
	231	u8 itr; /* current ITR setting for ring */
	232	};
	233
047e0030	234	struct igb_ring {
238ac817 AD	235	struct igb_q_vector q_vector; / backlink to q_vector */
	236	struct net_device netdev; / back pointer to net_device */
	237	struct device dev; / device pointer for dma mapping */
06034649 AD	238	union { /* array of buffer info structs */
	239	struct igb_tx_buffer *tx_buffer_info;
	240	struct igb_rx_buffer *rx_buffer_info;
	241	};
fc580751	242	unsigned long last_rx_timestamp;
238ac817 AD	243	void desc; / descriptor ring memory */
	244	unsigned long flags; /* ring specific flags */
	245	void __iomem tail; / pointer to ring tail register */
5536d210 AD	246	dma_addr_t dma; /* phys address of the ring */
5536d210 AD	247	unsigned int size; /* length of desc. ring in bytes */
238ac817 AD	248
	249	u16 count; /* number of desc. in the ring */
	250	u8 queue_index; /* logical index of the ring*/
	251	u8 reg_idx; /* physical index of the ring */
238ac817 AD	252
238ac817 AD	253	/* everything past this point are written often */
5536d210	254	u16 next_to_clean;
9d5c8243	255	u16 next_to_use;
cbc8e55f	256	u16 next_to_alloc;
9d5c8243	257
9d5c8243 AK	258	union {
	259	/* TX */
	260	struct {
8c0ab70a	261	struct igb_tx_queue_stats tx_stats;
12dcd86b ED	262	struct u64_stats_sync tx_syncp;
12dcd86b ED	263	struct u64_stats_sync tx_syncp2;
9d5c8243 AK	264	};
	265	/* RX */
	266	struct {
1a1c225b	267	struct sk_buff *skb;
8c0ab70a	268	struct igb_rx_queue_stats rx_stats;
12dcd86b	269	struct u64_stats_sync rx_syncp;
9d5c8243 AK	270	};
9d5c8243 AK	271	};
5536d210 AD	272	} ____cacheline_internodealigned_in_smp;
	273
	274	struct igb_q_vector {
	275	struct igb_adapter adapter; / backlink */
	276	int cpu; /* CPU for DCA */
	277	u32 eims_value; /* EIMS mask value */
	278
	279	u16 itr_val;
	280	u8 set_itr;
	281	void __iomem *itr_register;
	282
	283	struct igb_ring_container rx, tx;
	284
	285	struct napi_struct napi;
	286	struct rcu_head rcu; /* to avoid race with update stats on free */
	287	char name[IFNAMSIZ + 9];
	288
	289	/* for dynamic allocation of rings associated with this q_vector */
	290	struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
9d5c8243 AK	291	};
9d5c8243 AK	292
866cff06	293	enum e1000_ring_flags_t {
866cff06	294	IGB_RING_FLAG_RX_SCTP_CSUM,
8be10e91	295	IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
866cff06 AD	296	IGB_RING_FLAG_TX_CTX_IDX,
	297	IGB_RING_FLAG_TX_DETECT_HANG
	298	};
85ad76b2	299
e032afc8	300	#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP \| E1000_ADVTXD_DCMD_RS)
85ad76b2	301
b980ac18	302	#define IGB_RX_DESC(R, i) \
60136906	303	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
b980ac18	304	#define IGB_TX_DESC(R, i) \
60136906	305	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
b980ac18	306	#define IGB_TX_CTXTDESC(R, i) \
60136906	307	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
9d5c8243	308
3ceb90fd AD	309	/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
	310	static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
	311	const u32 stat_err_bits)
	312	{
	313	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
	314	}
	315
d7ee5b3a AD	316	/* igb_desc_unused - calculate if we have unused descriptors */
	317	static inline int igb_desc_unused(struct igb_ring *ring)
	318	{
	319	if (ring->next_to_clean > ring->next_to_use)
	320	return ring->next_to_clean - ring->next_to_use - 1;
	321
	322	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
	323	}
	324
e428893b CW	325	#ifdef CONFIG_IGB_HWMON
	326
	327	#define IGB_HWMON_TYPE_LOC 0
	328	#define IGB_HWMON_TYPE_TEMP 1
	329	#define IGB_HWMON_TYPE_CAUTION 2
	330	#define IGB_HWMON_TYPE_MAX 3
	331
	332	struct hwmon_attr {
	333	struct device_attribute dev_attr;
	334	struct e1000_hw *hw;
	335	struct e1000_thermal_diode_data *sensor;
	336	char name[12];
	337	};
	338
	339	struct hwmon_buff {
	340	struct device *device;
	341	struct hwmon_attr *hwmon_list;
	342	unsigned int n_hwmon;
	343	};
	344	#endif
	345
9d5c8243	346	/* board specific private data structure */
9d5c8243	347	struct igb_adapter {
b2cb09b1	348	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
238ac817 AD	349
	350	struct net_device *netdev;
	351
	352	unsigned long state;
	353	unsigned int flags;
	354
	355	unsigned int num_q_vectors;
	356	struct msix_entry *msix_entries;
2e5655e7	357
9d5c8243	358	/* Interrupt Throttle Rate */
4fc82adf AD	359	u32 rx_itr_setting;
4fc82adf AD	360	u32 tx_itr_setting;
9d5c8243 AK	361	u16 tx_itr;
9d5c8243 AK	362	u16 rx_itr;
9d5c8243	363
9d5c8243	364	/* TX */
13fde97a	365	u16 tx_work_limit;
9d5c8243	366	u32 tx_timeout_count;
238ac817 AD	367	int num_tx_queues;
238ac817 AD	368	struct igb_ring *tx_ring[16];
9d5c8243 AK	369
9d5c8243 AK	370	/* RX */
9d5c8243	371	int num_rx_queues;
238ac817	372	struct igb_ring *rx_ring[16];
9d5c8243	373
9d5c8243 AK	374	u32 max_frame_size;
	375	u32 min_frame_size;
	376
238ac817 AD	377	struct timer_list watchdog_timer;
	378	struct timer_list phy_info_timer;
	379
	380	u16 mng_vlan_id;
	381	u32 bd_number;
	382	u32 wol;
	383	u32 en_mng_pt;
	384	u16 link_speed;
	385	u16 link_duplex;
	386
	387	struct work_struct reset_task;
	388	struct work_struct watchdog_task;
	389	bool fc_autoneg;
	390	u8 tx_timeout_factor;
	391	struct timer_list blink_timer;
	392	unsigned long led_status;
	393
9d5c8243	394	/* OS defined structs */
9d5c8243	395	struct pci_dev *pdev;
9d5c8243	396
12dcd86b ED	397	spinlock_t stats64_lock;
	398	struct rtnl_link_stats64 stats64;
	399
9d5c8243 AK	400	/* structs defined in e1000_hw.h */
	401	struct e1000_hw hw;
	402	struct e1000_hw_stats stats;
	403	struct e1000_phy_info phy_info;
	404	struct e1000_phy_stats phy_stats;
	405
	406	u32 test_icr;
	407	struct igb_ring test_tx_ring;
	408	struct igb_ring test_rx_ring;
	409
	410	int msg_enable;
047e0030	411
047e0030	412	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243	413	u32 eims_enable_mask;
844290e5	414	u32 eims_other;
9d5c8243 AK	415
9d5c8243 AK	416	/* to not mess up cache alignment, always add to the bottom */
2e5655e7 AD	417	u16 tx_ring_count;
2e5655e7 AD	418	u16 rx_ring_count;
1bfaf07b	419	unsigned int vfs_allocated_count;
4ae196df	420	struct vf_data_storage *vf_data;
17dc566c	421	int vf_rate_link_speed;
a99955fc	422	u32 rss_queues;
13800469	423	u32 wvbr;
1128c756	424	u32 *shadow_vfta;
d339b133 RC	425
d339b133 RC	426	struct ptp_clock *ptp_clock;
a79f4f88 MV	427	struct ptp_clock_info ptp_caps;
a79f4f88 MV	428	struct delayed_work ptp_overflow_work;
1f6e8178 MV	429	struct work_struct ptp_tx_work;
1f6e8178 MV	430	struct sk_buff *ptp_tx_skb;
428f1f71	431	unsigned long ptp_tx_start;
fc580751	432	unsigned long last_rx_ptp_check;
d339b133 RC	433	spinlock_t tmreg_lock;
	434	struct cyclecounter cc;
	435	struct timecounter tc;
428f1f71	436	u32 tx_hwtstamp_timeouts;
fc580751	437	u32 rx_hwtstamp_cleared;
3c89f6d0	438
d67974f0	439	char fw_version[32];
e428893b CW	440	#ifdef CONFIG_IGB_HWMON
	441	struct hwmon_buff igb_hwmon_buff;
	442	bool ets;
	443	#endif
441fc6fd CW	444	struct i2c_algo_bit_data i2c_algo;
441fc6fd CW	445	struct i2c_adapter i2c_adap;
603e86fa	446	struct i2c_client *i2c_client;
9d5c8243 AK	447	};
9d5c8243 AK	448
039454a8 AA	449	#define IGB_FLAG_HAS_MSI (1 << 0)
	450	#define IGB_FLAG_DCA_ENABLED (1 << 1)
	451	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
	452	#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
	453	#define IGB_FLAG_DMAC (1 << 4)
	454	#define IGB_FLAG_PTP (1 << 5)
	455	#define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
	456	#define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
63d4a8f9	457	#define IGB_FLAG_WOL_SUPPORTED (1 << 8)
831ec0b4 CW	458
831ec0b4 CW	459	/* DMA Coalescing defines */
b980ac18 JK	460	#define IGB_MIN_TXPBSIZE 20408
	461	#define IGB_TX_BUF_4096 4096
	462	#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
7dfc16fa	463
b980ac18 JK	464	#define IGB_82576_TSYNC_SHIFT 19
b980ac18 JK	465	#define IGB_TS_HDR_LEN 16
9d5c8243 AK	466	enum e1000_state_t {
	467	__IGB_TESTING,
	468	__IGB_RESETTING,
	469	__IGB_DOWN
	470	};
	471
	472	enum igb_boards {
	473	board_82575,
	474	};
	475
	476	extern char igb_driver_name[];
	477	extern char igb_driver_version[];
	478
9d5c8243 AK	479	extern int igb_up(struct igb_adapter *);
	480	extern void igb_down(struct igb_adapter *);
	481	extern void igb_reinit_locked(struct igb_adapter *);
	482	extern void igb_reset(struct igb_adapter *);
14ad2513	483	extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
80785298 AD	484	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	485	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	486	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	487	extern void igb_free_rx_resources(struct igb_ring *);
d7ee5b3a AD	488	extern void igb_configure_tx_ring(struct igb_adapter , struct igb_ring );
	489	extern void igb_configure_rx_ring(struct igb_adapter , struct igb_ring );
	490	extern void igb_setup_tctl(struct igb_adapter *);
	491	extern void igb_setup_rctl(struct igb_adapter *);
cd392f5c	492	extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff , struct igb_ring );
b1a436c3	493	extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
06034649	494	struct igb_tx_buffer *);
cd392f5c	495	extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
12dcd86b	496	extern void igb_update_stats(struct igb_adapter , struct rtnl_link_stats64 );
3145535a	497	extern bool igb_has_link(struct igb_adapter *adapter);
9d5c8243	498	extern void igb_set_ethtool_ops(struct net_device *);
88a268c1	499	extern void igb_power_up_link(struct igb_adapter *);
d67974f0	500	extern void igb_set_fw_version(struct igb_adapter *);
7ebae817	501	extern void igb_ptp_init(struct igb_adapter *adapter);
a79f4f88	502	extern void igb_ptp_stop(struct igb_adapter *adapter);
1f6e8178 MV	503	extern void igb_ptp_reset(struct igb_adapter *adapter);
1f6e8178 MV	504	extern void igb_ptp_tx_work(struct work_struct *work);
fc580751	505	extern void igb_ptp_rx_hang(struct igb_adapter *adapter);
1f6e8178	506	extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
b534550a	507	extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
a79f4f88	508	struct sk_buff *skb);
b534550a AD	509	extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
	510	unsigned char *va,
	511	struct sk_buff *skb);
20a48412	512	static inline void igb_ptp_rx_hwtstamp(struct igb_ring *rx_ring,
b534550a AD	513	union e1000_adv_rx_desc *rx_desc,
	514	struct sk_buff *skb)
	515	{
1a1c225b AD	516	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
1a1c225b AD	517	!igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
20a48412 MV	518	igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
	519
	520	/* Update the last_rx_timestamp timer in order to enable watchdog check
	521	* for error case of latched timestamp on a dropped packet.
	522	*/
	523	rx_ring->last_rx_timestamp = jiffies;
b534550a	524	}
1a1c225b	525
a79f4f88 MV	526	extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
a79f4f88 MV	527	struct ifreq *ifr, int cmd);
e428893b CW	528	#ifdef CONFIG_IGB_HWMON
	529	extern void igb_sysfs_exit(struct igb_adapter *adapter);
	530	extern int igb_sysfs_init(struct igb_adapter *adapter);
	531	#endif
f5f4cf08 AD	532	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	533	{
a8d2a0c2 AD	534	if (hw->phy.ops.reset)
a8d2a0c2 AD	535	return hw->phy.ops.reset(hw);
f5f4cf08 AD	536
	537	return 0;
	538	}
	539
	540	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	541	{
a8d2a0c2 AD	542	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	543	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	544
	545	return 0;
	546	}
	547
	548	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	549	{
a8d2a0c2 AD	550	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	551	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	552
	553	return 0;
	554	}
	555
	556	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	557	{
	558	if (hw->phy.ops.get_phy_info)
	559	return hw->phy.ops.get_phy_info(hw);
	560
	561	return 0;
	562	}
	563
bdbc0631 ED	564	static inline struct netdev_queue txring_txq(const struct igb_ring tx_ring)
	565	{
	566	return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
	567	}
	568
9d5c8243	569	#endif /* _IGB_H_ */