[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2011 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>

struct igb_adapter;

/* Interrupt defines */
#define IGB_START_ITR                    648 /* ~6000 ints/sec */
#define IGB_4K_ITR                       980
#define IGB_20K_ITR                      196
#define IGB_70K_ITR                       56

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_DEFAULT_TX_WORK		 128
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
                                           (hw->mac.type > e1000_82575 ? 8 : 4))
#define IGB_MAX_TX_QUEUES                  16

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	u32 flags;
	unsigned long last_nack;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
	u16 tx_rate;
};

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                     8
#define IGB_RX_HTHRESH                     8
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 4)
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_512   512
#define IGB_RXBUFFER_16384 16384
#define IGB_RX_HDR_LEN     IGB_RXBUFFER_512

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

#define IGB_TX_FLAGS_CSUM		0x00000001
#define IGB_TX_FLAGS_VLAN		0x00000002
#define IGB_TX_FLAGS_TSO		0x00000004
#define IGB_TX_FLAGS_IPV4		0x00000008
#define IGB_TX_FLAGS_TSTAMP		0x00000010
#define IGB_TX_FLAGS_VLAN_MASK		0xffff0000
#define IGB_TX_FLAGS_VLAN_SHIFT	16

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_tx_buffer {
	union e1000_adv_tx_desc *next_to_watch;
	unsigned long time_stamp;
	struct sk_buff *skb;
	unsigned int bytecount;
	u16 gso_segs;
	__be16 protocol;
	dma_addr_t dma;
	u32 length;
	u32 tx_flags;
};

struct igb_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	u32 page_offset;
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 restart_queue2;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_ring_container {
	struct igb_ring *ring;		/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u16 work_limit;			/* total work allowed per interrupt */
	u8 count;			/* total number of rings in vector */
	u8 itr;				/* current ITR setting for ring */
};

struct igb_q_vector {
	struct igb_adapter *adapter;	/* backlink */
	int cpu;			/* CPU for DCA */
	u32 eims_value;			/* EIMS mask value */

	struct igb_ring_container rx, tx;

	struct napi_struct napi;
	int numa_node;

	u16 itr_val;
	u8 set_itr;
	void __iomem *itr_register;

	char name[IFNAMSIZ + 9];
};

struct igb_ring {
	struct igb_q_vector *q_vector;	/* backlink to q_vector */
	struct net_device *netdev;	/* back pointer to net_device */
	struct device *dev;		/* device pointer for dma mapping */
	union {				/* array of buffer info structs */
		struct igb_tx_buffer *tx_buffer_info;
		struct igb_rx_buffer *rx_buffer_info;
	};
	void *desc;			/* descriptor ring memory */
	unsigned long flags;		/* ring specific flags */
	void __iomem *tail;		/* pointer to ring tail register */

	u16 count;			/* number of desc. in the ring */
	u8 queue_index;			/* logical index of the ring*/
	u8 reg_idx;			/* physical index of the ring */
	u32 size;			/* length of desc. ring in bytes */

	/* everything past this point are written often */
	u16 next_to_clean ____cacheline_aligned_in_smp;
	u16 next_to_use;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			struct u64_stats_sync tx_syncp;
			struct u64_stats_sync tx_syncp2;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			struct u64_stats_sync rx_syncp;
		};
	};
	/* Items past this point are only used during ring alloc / free */
	dma_addr_t dma;                /* phys address of the ring */
	int numa_node;                  /* node to alloc ring memory on */
};

enum e1000_ring_flags_t {
	IGB_RING_FLAG_RX_SCTP_CSUM,
	IGB_RING_FLAG_TX_CTX_IDX,
	IGB_RING_FLAG_TX_DETECT_HANG
};

#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)

#define IGB_RX_DESC(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
#define IGB_TX_DESC(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
#define IGB_TX_CTXTDESC(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))

/* igb_desc_unused - calculate if we have unused descriptors */
static inline int igb_desc_unused(struct igb_ring *ring)
{
	if (ring->next_to_clean > ring->next_to_use)
		return ring->next_to_clean - ring->next_to_use - 1;

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
}

/* board specific private data structure */
struct igb_adapter {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

	struct net_device *netdev;

	unsigned long state;
	unsigned int flags;

	unsigned int num_q_vectors;
	struct msix_entry *msix_entries;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	/* TX */
	u16 tx_work_limit;
	u32 tx_timeout_count;
	int num_tx_queues;
	struct igb_ring *tx_ring[16];

	/* RX */
	int num_rx_queues;
	struct igb_ring *rx_ring[16];

	u32 max_frame_size;
	u32 min_frame_size;

	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;

	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* OS defined structs */
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	spinlock_t stats64_lock;
	struct rtnl_link_stats64 stats64;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	u32 eeprom_wol;

	u16 tx_ring_count;
	u16 rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
	int vf_rate_link_speed;
	u32 rss_queues;
	u32 wvbr;
	int node;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
#define IGB_FLAG_DMAC              (1 << 4)

/* DMA Coalescing defines */
#define IGB_MIN_TXPBSIZE           20408
#define IGB_TX_BUF_4096            4096
#define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */

#define IGB_82576_TSYNC_SHIFT 19
#define IGB_82580_TSYNC_SHIFT 24
#define IGB_TS_HDR_LEN        16
enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_setup_tctl(struct igb_adapter *);
extern void igb_setup_rctl(struct igb_adapter *);
extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
					   struct igb_tx_buffer *);
extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
extern bool igb_has_link(struct igb_adapter *adapter);
extern void igb_set_ethtool_ops(struct net_device *);
extern void igb_power_up_link(struct igb_adapter *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
4297f99b	4	Copyright(c) 2007-2011 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
b2cb09b1 JP	40	#include <linux/bitops.h>
b2cb09b1 JP	41	#include <linux/if_vlan.h>
38c845c7	42
9d5c8243 AK	43	struct igb_adapter;
9d5c8243 AK	44
0ba82994 AD	45	/* Interrupt defines */
	46	#define IGB_START_ITR 648 /* ~6000 ints/sec */
	47	#define IGB_4K_ITR 980
	48	#define IGB_20K_ITR 196
	49	#define IGB_70K_ITR 56
9d5c8243	50
9d5c8243 AK	51	/* TX/RX descriptor defines */
9d5c8243 AK	52	#define IGB_DEFAULT_TXD 256
13fde97a	53	#define IGB_DEFAULT_TX_WORK 128
9d5c8243 AK	54	#define IGB_MIN_TXD 80
	55	#define IGB_MAX_TXD 4096
	56
	57	#define IGB_DEFAULT_RXD 256
	58	#define IGB_MIN_RXD 80
	59	#define IGB_MAX_RXD 4096
	60
	61	#define IGB_DEFAULT_ITR 3 /* dynamic */
	62	#define IGB_MAX_ITR_USECS 10000
	63	#define IGB_MIN_ITR_USECS 10
047e0030 AD	64	#define NON_Q_VECTORS 1
047e0030 AD	65	#define MAX_Q_VECTORS 8
9d5c8243 AK	66
9d5c8243 AK	67	/* Transmit and receive queues */
a99955fc AD	68	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
a99955fc AD	69	(hw->mac.type > e1000_82575 ? 8 : 4))
1cc3bd87	70	#define IGB_MAX_TX_QUEUES 16
9d5c8243	71
4ae196df AD	72	#define IGB_MAX_VF_MC_ENTRIES 30
	73	#define IGB_MAX_VF_FUNCTIONS 8
	74	#define IGB_MAX_VFTA_ENTRIES 128
	75
	76	struct vf_data_storage {
	77	unsigned char vf_mac_addresses[ETH_ALEN];
	78	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	79	u16 num_vf_mc_hashes;
ae641bdc	80	u16 vlans_enabled;
f2ca0dbe AD	81	u32 flags;
f2ca0dbe AD	82	unsigned long last_nack;
8151d294 WM	83	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
8151d294 WM	84	u16 pf_qos;
17dc566c	85	u16 tx_rate;
4ae196df AD	86	};
4ae196df AD	87
f2ca0dbe	88	#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
7d5753f0 AD	89	#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
7d5753f0 AD	90	#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
8151d294	91	#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
f2ca0dbe	92
9d5c8243 AK	93	/* RX descriptor control thresholds.
	94	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	95	* descriptors available in its onboard memory.
	96	* Setting this to 0 disables RX descriptor prefetch.
	97	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	98	* available in host memory.
	99	* If PTHRESH is 0, this should also be 0.
	100	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	101	* descriptors until either it has this many to write back, or the
	102	* ITR timer expires.
	103	*/
58fd62f5	104	#define IGB_RX_PTHRESH 8
9d5c8243	105	#define IGB_RX_HTHRESH 8
85b430b4 AD	106	#define IGB_TX_PTHRESH 8
85b430b4 AD	107	#define IGB_TX_HTHRESH 1
a74420e0 AD	108	#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0 AD	109	adapter->msix_entries) ? 1 : 4)
85b430b4	110	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0	111	adapter->msix_entries) ? 1 : 16)
9d5c8243 AK	112
	113	/* this is the size past which hardware will drop packets when setting LPE=0 */
	114	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	115
	116	/* Supported Rx Buffer Sizes */
44390ca6	117	#define IGB_RXBUFFER_512 512
9d5c8243	118	#define IGB_RXBUFFER_16384 16384
44390ca6	119	#define IGB_RX_HDR_LEN IGB_RXBUFFER_512
9d5c8243	120
9d5c8243 AK	121	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	122	#define IGB_TX_QUEUE_WAKE 16
	123	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	124	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	125
	126	#define AUTO_ALL_MODES 0
	127	#define IGB_EEPROM_APME 0x0400
	128
	129	#ifndef IGB_MASTER_SLAVE
	130	/* Switch to override PHY master/slave setting */
	131	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	132	#endif
	133
	134	#define IGB_MNG_VLAN_NONE -1
	135
2bbfebe2 AD	136	#define IGB_TX_FLAGS_CSUM 0x00000001
	137	#define IGB_TX_FLAGS_VLAN 0x00000002
	138	#define IGB_TX_FLAGS_TSO 0x00000004
	139	#define IGB_TX_FLAGS_IPV4 0x00000008
	140	#define IGB_TX_FLAGS_TSTAMP 0x00000010
2bbfebe2 AD	141	#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
	142	#define IGB_TX_FLAGS_VLAN_SHIFT 16
	143
9d5c8243 AK	144	/* wrapper around a pointer to a socket buffer,
9d5c8243 AK	145	* so a DMA handle can be stored along with the buffer */
06034649	146	struct igb_tx_buffer {
8542db05	147	union e1000_adv_tx_desc *next_to_watch;
06034649	148	unsigned long time_stamp;
06034649 AD	149	struct sk_buff *skb;
	150	unsigned int bytecount;
	151	u16 gso_segs;
7af40ad9	152	__be16 protocol;
ebe42d16 AD	153	dma_addr_t dma;
	154	u32 length;
	155	u32 tx_flags;
06034649 AD	156	};
	157
	158	struct igb_rx_buffer {
9d5c8243 AK	159	struct sk_buff *skb;
9d5c8243 AK	160	dma_addr_t dma;
06034649 AD	161	struct page *page;
	162	dma_addr_t page_dma;
	163	u32 page_offset;
9d5c8243 AK	164	};
9d5c8243 AK	165
8c0ab70a	166	struct igb_tx_queue_stats {
9d5c8243 AK	167	u64 packets;
9d5c8243 AK	168	u64 bytes;
04a5fcaa	169	u64 restart_queue;
12dcd86b	170	u64 restart_queue2;
9d5c8243 AK	171	};
9d5c8243 AK	172
8c0ab70a JDB	173	struct igb_rx_queue_stats {
	174	u64 packets;
	175	u64 bytes;
	176	u64 drops;
04a5fcaa AD	177	u64 csum_err;
04a5fcaa AD	178	u64 alloc_failed;
8c0ab70a JDB	179	};
8c0ab70a JDB	180
0ba82994 AD	181	struct igb_ring_container {
	182	struct igb_ring ring; / pointer to linked list of rings */
	183	unsigned int total_bytes; /* total bytes processed this int */
	184	unsigned int total_packets; /* total packets processed this int */
	185	u16 work_limit; /* total work allowed per interrupt */
	186	u8 count; /* total number of rings in vector */
	187	u8 itr; /* current ITR setting for ring */
	188	};
	189
047e0030	190	struct igb_q_vector {
0ba82994 AD	191	struct igb_adapter adapter; / backlink */
	192	int cpu; /* CPU for DCA */
	193	u32 eims_value; /* EIMS mask value */
047e0030	194
0ba82994	195	struct igb_ring_container rx, tx;
047e0030	196
0ba82994	197	struct napi_struct napi;
81c2fc22 AD	198	int numa_node;
81c2fc22 AD	199
047e0030 AD	200	u16 itr_val;
047e0030 AD	201	u8 set_itr;
047e0030 AD	202	void __iomem *itr_register;
	203
	204	char name[IFNAMSIZ + 9];
	205	};
	206
	207	struct igb_ring {
238ac817 AD	208	struct igb_q_vector q_vector; / backlink to q_vector */
	209	struct net_device netdev; / back pointer to net_device */
	210	struct device dev; / device pointer for dma mapping */
06034649 AD	211	union { /* array of buffer info structs */
	212	struct igb_tx_buffer *tx_buffer_info;
	213	struct igb_rx_buffer *rx_buffer_info;
	214	};
238ac817 AD	215	void desc; / descriptor ring memory */
	216	unsigned long flags; /* ring specific flags */
	217	void __iomem tail; / pointer to ring tail register */
	218
	219	u16 count; /* number of desc. in the ring */
	220	u8 queue_index; /* logical index of the ring*/
	221	u8 reg_idx; /* physical index of the ring */
	222	u32 size; /* length of desc. ring in bytes */
	223
	224	/* everything past this point are written often */
	225	u16 next_to_clean ____cacheline_aligned_in_smp;
9d5c8243	226	u16 next_to_use;
9d5c8243	227
9d5c8243 AK	228	union {
	229	/* TX */
	230	struct {
8c0ab70a	231	struct igb_tx_queue_stats tx_stats;
12dcd86b ED	232	struct u64_stats_sync tx_syncp;
12dcd86b ED	233	struct u64_stats_sync tx_syncp2;
9d5c8243 AK	234	bool detect_tx_hung;
	235	};
	236	/* RX */
	237	struct {
8c0ab70a	238	struct igb_rx_queue_stats rx_stats;
12dcd86b	239	struct u64_stats_sync rx_syncp;
9d5c8243 AK	240	};
9d5c8243 AK	241	};
238ac817 AD	242	/* Items past this point are only used during ring alloc / free */
238ac817 AD	243	dma_addr_t dma; /* phys address of the ring */
81c2fc22	244	int numa_node; /* node to alloc ring memory on */
9d5c8243 AK	245	};
9d5c8243 AK	246
866cff06	247	enum e1000_ring_flags_t {
866cff06 AD	248	IGB_RING_FLAG_RX_SCTP_CSUM,
	249	IGB_RING_FLAG_TX_CTX_IDX,
	250	IGB_RING_FLAG_TX_DETECT_HANG
	251	};
85ad76b2	252
e032afc8	253	#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP \| E1000_ADVTXD_DCMD_RS)
85ad76b2	254
60136906 AD	255	#define IGB_RX_DESC(R, i) \
	256	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
	257	#define IGB_TX_DESC(R, i) \
	258	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
	259	#define IGB_TX_CTXTDESC(R, i) \
	260	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
9d5c8243	261
d7ee5b3a AD	262	/* igb_desc_unused - calculate if we have unused descriptors */
	263	static inline int igb_desc_unused(struct igb_ring *ring)
	264	{
	265	if (ring->next_to_clean > ring->next_to_use)
	266	return ring->next_to_clean - ring->next_to_use - 1;
	267
	268	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
	269	}
	270
9d5c8243	271	/* board specific private data structure */
9d5c8243	272	struct igb_adapter {
b2cb09b1	273	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
238ac817 AD	274
	275	struct net_device *netdev;
	276
	277	unsigned long state;
	278	unsigned int flags;
	279
	280	unsigned int num_q_vectors;
	281	struct msix_entry *msix_entries;
2e5655e7	282
9d5c8243	283	/* Interrupt Throttle Rate */
4fc82adf AD	284	u32 rx_itr_setting;
4fc82adf AD	285	u32 tx_itr_setting;
9d5c8243 AK	286	u16 tx_itr;
9d5c8243 AK	287	u16 rx_itr;
9d5c8243	288
9d5c8243	289	/* TX */
13fde97a	290	u16 tx_work_limit;
9d5c8243	291	u32 tx_timeout_count;
238ac817 AD	292	int num_tx_queues;
238ac817 AD	293	struct igb_ring *tx_ring[16];
9d5c8243 AK	294
9d5c8243 AK	295	/* RX */
9d5c8243	296	int num_rx_queues;
238ac817	297	struct igb_ring *rx_ring[16];
9d5c8243	298
9d5c8243 AK	299	u32 max_frame_size;
	300	u32 min_frame_size;
	301
238ac817 AD	302	struct timer_list watchdog_timer;
	303	struct timer_list phy_info_timer;
	304
	305	u16 mng_vlan_id;
	306	u32 bd_number;
	307	u32 wol;
	308	u32 en_mng_pt;
	309	u16 link_speed;
	310	u16 link_duplex;
	311
	312	struct work_struct reset_task;
	313	struct work_struct watchdog_task;
	314	bool fc_autoneg;
	315	u8 tx_timeout_factor;
	316	struct timer_list blink_timer;
	317	unsigned long led_status;
	318
9d5c8243	319	/* OS defined structs */
9d5c8243	320	struct pci_dev *pdev;
38c845c7 PO	321	struct cyclecounter cycles;
38c845c7 PO	322	struct timecounter clock;
33af6bcc PO	323	struct timecompare compare;
33af6bcc PO	324	struct hwtstamp_config hwtstamp_config;
9d5c8243	325
12dcd86b ED	326	spinlock_t stats64_lock;
	327	struct rtnl_link_stats64 stats64;
	328
9d5c8243 AK	329	/* structs defined in e1000_hw.h */
	330	struct e1000_hw hw;
	331	struct e1000_hw_stats stats;
	332	struct e1000_phy_info phy_info;
	333	struct e1000_phy_stats phy_stats;
	334
	335	u32 test_icr;
	336	struct igb_ring test_tx_ring;
	337	struct igb_ring test_rx_ring;
	338
	339	int msg_enable;
047e0030	340
047e0030	341	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243	342	u32 eims_enable_mask;
844290e5	343	u32 eims_other;
9d5c8243 AK	344
9d5c8243 AK	345	/* to not mess up cache alignment, always add to the bottom */
9d5c8243	346	u32 eeprom_wol;
42bfd33a	347
2e5655e7 AD	348	u16 tx_ring_count;
2e5655e7 AD	349	u16 rx_ring_count;
1bfaf07b	350	unsigned int vfs_allocated_count;
4ae196df	351	struct vf_data_storage *vf_data;
17dc566c	352	int vf_rate_link_speed;
a99955fc	353	u32 rss_queues;
13800469	354	u32 wvbr;
81c2fc22	355	int node;
9d5c8243 AK	356	};
9d5c8243 AK	357
7dfc16fa	358	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	359	#define IGB_FLAG_DCA_ENABLED (1 << 1)
cbd347ad AD	360	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
4fc82adf	361	#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
831ec0b4 CW	362	#define IGB_FLAG_DMAC (1 << 4)
	363
	364	/* DMA Coalescing defines */
	365	#define IGB_MIN_TXPBSIZE 20408
	366	#define IGB_TX_BUF_4096 4096
	367	#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
7dfc16fa	368
c5b9bd5e	369	#define IGB_82576_TSYNC_SHIFT 19
55cac248	370	#define IGB_82580_TSYNC_SHIFT 24
757b77e2	371	#define IGB_TS_HDR_LEN 16
9d5c8243 AK	372	enum e1000_state_t {
	373	__IGB_TESTING,
	374	__IGB_RESETTING,
	375	__IGB_DOWN
	376	};
	377
	378	enum igb_boards {
	379	board_82575,
	380	};
	381
	382	extern char igb_driver_name[];
	383	extern char igb_driver_version[];
	384
9d5c8243 AK	385	extern int igb_up(struct igb_adapter *);
	386	extern void igb_down(struct igb_adapter *);
	387	extern void igb_reinit_locked(struct igb_adapter *);
	388	extern void igb_reset(struct igb_adapter *);
14ad2513	389	extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
80785298 AD	390	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	391	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	392	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	393	extern void igb_free_rx_resources(struct igb_ring *);
d7ee5b3a AD	394	extern void igb_configure_tx_ring(struct igb_adapter , struct igb_ring );
	395	extern void igb_configure_rx_ring(struct igb_adapter , struct igb_ring );
	396	extern void igb_setup_tctl(struct igb_adapter *);
	397	extern void igb_setup_rctl(struct igb_adapter *);
cd392f5c	398	extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff , struct igb_ring );
b1a436c3	399	extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
06034649	400	struct igb_tx_buffer *);
cd392f5c	401	extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
12dcd86b	402	extern void igb_update_stats(struct igb_adapter , struct rtnl_link_stats64 );
3145535a	403	extern bool igb_has_link(struct igb_adapter *adapter);
9d5c8243	404	extern void igb_set_ethtool_ops(struct net_device *);
88a268c1	405	extern void igb_power_up_link(struct igb_adapter *);
9d5c8243	406
f5f4cf08 AD	407	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	408	{
a8d2a0c2 AD	409	if (hw->phy.ops.reset)
a8d2a0c2 AD	410	return hw->phy.ops.reset(hw);
f5f4cf08 AD	411
	412	return 0;
	413	}
	414
	415	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	416	{
a8d2a0c2 AD	417	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	418	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	419
	420	return 0;
	421	}
	422
	423	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	424	{
a8d2a0c2 AD	425	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	426	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	427
	428	return 0;
	429	}
	430
	431	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	432	{
	433	if (hw->phy.ops.get_phy_info)
	434	return hw->phy.ops.get_phy_info(hw);
	435
	436	return 0;
	437	}
	438
9d5c8243	439	#endif /* _IGB_H_ */