[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2012 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>

struct igb_adapter;

#define E1000_PCS_CFG_IGN_SD               1

/* Interrupt defines */
#define IGB_START_ITR                    648 /* ~6000 ints/sec */
#define IGB_4K_ITR                       980
#define IGB_20K_ITR                      196
#define IGB_70K_ITR                       56

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_DEFAULT_TX_WORK		 128
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  8
#define IGB_MAX_RX_QUEUES_82575            4
#define IGB_MAX_RX_QUEUES_I211             2
#define IGB_MAX_TX_QUEUES                  8
#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128
#define IGB_82576_VF_DEV_ID                0x10CA
#define IGB_I350_VF_DEV_ID                 0x1520

/* NVM version defines */
#define IGB_MAJOR_MASK			0xF000
#define IGB_MINOR_MASK			0x0FF0
#define IGB_BUILD_MASK			0x000F
#define IGB_COMB_VER_MASK		0x00FF
#define IGB_MAJOR_SHIFT			12
#define IGB_MINOR_SHIFT			4
#define IGB_COMB_VER_SHFT		8
#define IGB_NVM_VER_INVALID		0xFFFF
#define IGB_ETRACK_SHIFT		16
#define NVM_ETRACK_WORD			0x0042
#define NVM_COMB_VER_OFF		0x0083
#define NVM_COMB_VER_PTR		0x003d

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	u32 flags;
	unsigned long last_nack;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
	u16 tx_rate;
};

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                     8
#define IGB_RX_HTHRESH                     8
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 4)
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_256	256
#define IGB_RXBUFFER_2048	2048
#define IGB_RX_HDR_LEN		IGB_RXBUFFER_256
#define IGB_RX_BUFSZ		IGB_RXBUFFER_2048

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

enum igb_tx_flags {
	/* cmd_type flags */
	IGB_TX_FLAGS_VLAN	= 0x01,
	IGB_TX_FLAGS_TSO	= 0x02,
	IGB_TX_FLAGS_TSTAMP	= 0x04,

	/* olinfo flags */
	IGB_TX_FLAGS_IPV4	= 0x10,
	IGB_TX_FLAGS_CSUM	= 0x20,
};

/* VLAN info */
#define IGB_TX_FLAGS_VLAN_MASK		0xffff0000
#define IGB_TX_FLAGS_VLAN_SHIFT	16

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_tx_buffer {
	union e1000_adv_tx_desc *next_to_watch;
	unsigned long time_stamp;
	struct sk_buff *skb;
	unsigned int bytecount;
	u16 gso_segs;
	__be16 protocol;
	DEFINE_DMA_UNMAP_ADDR(dma);
	DEFINE_DMA_UNMAP_LEN(len);
	u32 tx_flags;
};

struct igb_rx_buffer {
	dma_addr_t dma;
	struct page *page;
	unsigned int page_offset;
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 restart_queue2;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_ring_container {
	struct igb_ring *ring;		/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u16 work_limit;			/* total work allowed per interrupt */
	u8 count;			/* total number of rings in vector */
	u8 itr;				/* current ITR setting for ring */
};

struct igb_ring {
	struct igb_q_vector *q_vector;	/* backlink to q_vector */
	struct net_device *netdev;	/* back pointer to net_device */
	struct device *dev;		/* device pointer for dma mapping */
	union {				/* array of buffer info structs */
		struct igb_tx_buffer *tx_buffer_info;
		struct igb_rx_buffer *rx_buffer_info;
	};
	void *desc;			/* descriptor ring memory */
	unsigned long flags;		/* ring specific flags */
	void __iomem *tail;		/* pointer to ring tail register */
	dma_addr_t dma;			/* phys address of the ring */
	unsigned int  size;		/* length of desc. ring in bytes */

	u16 count;			/* number of desc. in the ring */
	u8 queue_index;			/* logical index of the ring*/
	u8 reg_idx;			/* physical index of the ring */

	/* everything past this point are written often */
	u16 next_to_clean;
	u16 next_to_use;
	u16 next_to_alloc;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			struct u64_stats_sync tx_syncp;
			struct u64_stats_sync tx_syncp2;
		};
		/* RX */
		struct {
			struct sk_buff *skb;
			struct igb_rx_queue_stats rx_stats;
			struct u64_stats_sync rx_syncp;
		};
	};
} ____cacheline_internodealigned_in_smp;

struct igb_q_vector {
	struct igb_adapter *adapter;	/* backlink */
	int cpu;			/* CPU for DCA */
	u32 eims_value;			/* EIMS mask value */

	u16 itr_val;
	u8 set_itr;
	void __iomem *itr_register;

	struct igb_ring_container rx, tx;

	struct napi_struct napi;
	struct rcu_head rcu;	/* to avoid race with update stats on free */
	char name[IFNAMSIZ + 9];

	/* for dynamic allocation of rings associated with this q_vector */
	struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
};

enum e1000_ring_flags_t {
	IGB_RING_FLAG_RX_SCTP_CSUM,
	IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
	IGB_RING_FLAG_TX_CTX_IDX,
	IGB_RING_FLAG_TX_DETECT_HANG
};

#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)

#define IGB_RX_DESC(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
#define IGB_TX_DESC(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
#define IGB_TX_CTXTDESC(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))

/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
				      const u32 stat_err_bits)
{
	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
}

/* igb_desc_unused - calculate if we have unused descriptors */
static inline int igb_desc_unused(struct igb_ring *ring)
{
	if (ring->next_to_clean > ring->next_to_use)
		return ring->next_to_clean - ring->next_to_use - 1;

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
}

/* board specific private data structure */
struct igb_adapter {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

	struct net_device *netdev;

	unsigned long state;
	unsigned int flags;

	unsigned int num_q_vectors;
	struct msix_entry *msix_entries;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	/* TX */
	u16 tx_work_limit;
	u32 tx_timeout_count;
	int num_tx_queues;
	struct igb_ring *tx_ring[16];

	/* RX */
	int num_rx_queues;
	struct igb_ring *rx_ring[16];

	u32 max_frame_size;
	u32 min_frame_size;

	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;

	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* OS defined structs */
	struct pci_dev *pdev;

	spinlock_t stats64_lock;
	struct rtnl_link_stats64 stats64;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	u16 tx_ring_count;
	u16 rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
	int vf_rate_link_speed;
	u32 rss_queues;
	u32 wvbr;
	u32 *shadow_vfta;

	struct ptp_clock *ptp_clock;
	struct ptp_clock_info ptp_caps;
	struct delayed_work ptp_overflow_work;
	struct work_struct ptp_tx_work;
	struct sk_buff *ptp_tx_skb;
	spinlock_t tmreg_lock;
	struct cyclecounter cc;
	struct timecounter tc;

	char fw_version[32];
};

#define IGB_FLAG_HAS_MSI		(1 << 0)
#define IGB_FLAG_DCA_ENABLED		(1 << 1)
#define IGB_FLAG_QUAD_PORT_A		(1 << 2)
#define IGB_FLAG_QUEUE_PAIRS		(1 << 3)
#define IGB_FLAG_DMAC			(1 << 4)
#define IGB_FLAG_PTP			(1 << 5)
#define IGB_FLAG_RSS_FIELD_IPV4_UDP	(1 << 6)
#define IGB_FLAG_RSS_FIELD_IPV6_UDP	(1 << 7)
#define IGB_FLAG_WOL_SUPPORTED		(1 << 8)

/* DMA Coalescing defines */
#define IGB_MIN_TXPBSIZE           20408
#define IGB_TX_BUF_4096            4096
#define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */

#define IGB_82576_TSYNC_SHIFT 19
#define IGB_TS_HDR_LEN        16
enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_setup_tctl(struct igb_adapter *);
extern void igb_setup_rctl(struct igb_adapter *);
extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
					   struct igb_tx_buffer *);
extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
extern bool igb_has_link(struct igb_adapter *adapter);
extern void igb_set_ethtool_ops(struct net_device *);
extern void igb_power_up_link(struct igb_adapter *);
extern void igb_set_fw_version(struct igb_adapter *);
extern void igb_ptp_init(struct igb_adapter *adapter);
extern void igb_ptp_stop(struct igb_adapter *adapter);
extern void igb_ptp_reset(struct igb_adapter *adapter);
extern void igb_ptp_tx_work(struct work_struct *work);
extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
				struct sk_buff *skb);
extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
				unsigned char *va,
				struct sk_buff *skb);
static inline void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector,
				       union e1000_adv_rx_desc *rx_desc,
				       struct sk_buff *skb)
{
	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
	    !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
		igb_ptp_rx_rgtstamp(q_vector, skb);
}

extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
				  struct ifreq *ifr, int cmd);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
{
	return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
6e861326	4	Copyright(c) 2007-2012 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc	38	#include <linux/net_tstamp.h>
d339b133	39	#include <linux/ptp_clock_kernel.h>
b2cb09b1 JP	40	#include <linux/bitops.h>
b2cb09b1 JP	41	#include <linux/if_vlan.h>
38c845c7	42
9d5c8243 AK	43	struct igb_adapter;
9d5c8243 AK	44
3860a0bf CW	45	#define E1000_PCS_CFG_IGN_SD 1
3860a0bf CW	46
0ba82994 AD	47	/* Interrupt defines */
	48	#define IGB_START_ITR 648 /* ~6000 ints/sec */
	49	#define IGB_4K_ITR 980
	50	#define IGB_20K_ITR 196
	51	#define IGB_70K_ITR 56
9d5c8243	52
9d5c8243 AK	53	/* TX/RX descriptor defines */
9d5c8243 AK	54	#define IGB_DEFAULT_TXD 256
13fde97a	55	#define IGB_DEFAULT_TX_WORK 128
9d5c8243 AK	56	#define IGB_MIN_TXD 80
	57	#define IGB_MAX_TXD 4096
	58
	59	#define IGB_DEFAULT_RXD 256
	60	#define IGB_MIN_RXD 80
	61	#define IGB_MAX_RXD 4096
	62
	63	#define IGB_DEFAULT_ITR 3 /* dynamic */
	64	#define IGB_MAX_ITR_USECS 10000
	65	#define IGB_MIN_ITR_USECS 10
047e0030 AD	66	#define NON_Q_VECTORS 1
047e0030 AD	67	#define MAX_Q_VECTORS 8
9d5c8243 AK	68
9d5c8243 AK	69	/* Transmit and receive queues */
374a542d MV	70	#define IGB_MAX_RX_QUEUES 8
374a542d MV	71	#define IGB_MAX_RX_QUEUES_82575 4
f96a8a0b	72	#define IGB_MAX_RX_QUEUES_I211 2
374a542d	73	#define IGB_MAX_TX_QUEUES 8
4ae196df AD	74	#define IGB_MAX_VF_MC_ENTRIES 30
	75	#define IGB_MAX_VF_FUNCTIONS 8
	76	#define IGB_MAX_VFTA_ENTRIES 128
0224d663 GR	77	#define IGB_82576_VF_DEV_ID 0x10CA
0224d663 GR	78	#define IGB_I350_VF_DEV_ID 0x1520
4ae196df	79
d67974f0 CW	80	/* NVM version defines */
	81	#define IGB_MAJOR_MASK 0xF000
	82	#define IGB_MINOR_MASK 0x0FF0
	83	#define IGB_BUILD_MASK 0x000F
	84	#define IGB_COMB_VER_MASK 0x00FF
	85	#define IGB_MAJOR_SHIFT 12
	86	#define IGB_MINOR_SHIFT 4
	87	#define IGB_COMB_VER_SHFT 8
	88	#define IGB_NVM_VER_INVALID 0xFFFF
	89	#define IGB_ETRACK_SHIFT 16
	90	#define NVM_ETRACK_WORD 0x0042
	91	#define NVM_COMB_VER_OFF 0x0083
	92	#define NVM_COMB_VER_PTR 0x003d
	93
4ae196df AD	94	struct vf_data_storage {
	95	unsigned char vf_mac_addresses[ETH_ALEN];
	96	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	97	u16 num_vf_mc_hashes;
ae641bdc	98	u16 vlans_enabled;
f2ca0dbe AD	99	u32 flags;
f2ca0dbe AD	100	unsigned long last_nack;
8151d294 WM	101	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
8151d294 WM	102	u16 pf_qos;
17dc566c	103	u16 tx_rate;
4ae196df AD	104	};
4ae196df AD	105
f2ca0dbe	106	#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
7d5753f0 AD	107	#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
7d5753f0 AD	108	#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
8151d294	109	#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
f2ca0dbe	110
9d5c8243 AK	111	/* RX descriptor control thresholds.
	112	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	113	* descriptors available in its onboard memory.
	114	* Setting this to 0 disables RX descriptor prefetch.
	115	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	116	* available in host memory.
	117	* If PTHRESH is 0, this should also be 0.
	118	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	119	* descriptors until either it has this many to write back, or the
	120	* ITR timer expires.
	121	*/
58fd62f5	122	#define IGB_RX_PTHRESH 8
9d5c8243	123	#define IGB_RX_HTHRESH 8
85b430b4 AD	124	#define IGB_TX_PTHRESH 8
85b430b4 AD	125	#define IGB_TX_HTHRESH 1
a74420e0 AD	126	#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0 AD	127	adapter->msix_entries) ? 1 : 4)
85b430b4	128	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0	129	adapter->msix_entries) ? 1 : 16)
9d5c8243 AK	130
	131	/* this is the size past which hardware will drop packets when setting LPE=0 */
	132	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	133
	134	/* Supported Rx Buffer Sizes */
de78d1f9 AD	135	#define IGB_RXBUFFER_256 256
	136	#define IGB_RXBUFFER_2048 2048
	137	#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
	138	#define IGB_RX_BUFSZ IGB_RXBUFFER_2048
9d5c8243	139
9d5c8243 AK	140	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	141	#define IGB_TX_QUEUE_WAKE 16
	142	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	143	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	144
	145	#define AUTO_ALL_MODES 0
	146	#define IGB_EEPROM_APME 0x0400
	147
	148	#ifndef IGB_MASTER_SLAVE
	149	/* Switch to override PHY master/slave setting */
	150	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	151	#endif
	152
	153	#define IGB_MNG_VLAN_NONE -1
	154
1d9daf45 AD	155	enum igb_tx_flags {
	156	/* cmd_type flags */
	157	IGB_TX_FLAGS_VLAN = 0x01,
	158	IGB_TX_FLAGS_TSO = 0x02,
	159	IGB_TX_FLAGS_TSTAMP = 0x04,
	160
	161	/* olinfo flags */
	162	IGB_TX_FLAGS_IPV4 = 0x10,
	163	IGB_TX_FLAGS_CSUM = 0x20,
	164	};
	165
	166	/* VLAN info */
2bbfebe2 AD	167	#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
	168	#define IGB_TX_FLAGS_VLAN_SHIFT 16
	169
9d5c8243 AK	170	/* wrapper around a pointer to a socket buffer,
9d5c8243 AK	171	* so a DMA handle can be stored along with the buffer */
06034649	172	struct igb_tx_buffer {
8542db05	173	union e1000_adv_tx_desc *next_to_watch;
06034649	174	unsigned long time_stamp;
06034649 AD	175	struct sk_buff *skb;
	176	unsigned int bytecount;
	177	u16 gso_segs;
7af40ad9	178	__be16 protocol;
c9f14bf3 AD	179	DEFINE_DMA_UNMAP_ADDR(dma);
c9f14bf3 AD	180	DEFINE_DMA_UNMAP_LEN(len);
ebe42d16	181	u32 tx_flags;
06034649 AD	182	};
	183
	184	struct igb_rx_buffer {
9d5c8243	185	dma_addr_t dma;
06034649	186	struct page *page;
1a1c225b	187	unsigned int page_offset;
9d5c8243 AK	188	};
9d5c8243 AK	189
8c0ab70a	190	struct igb_tx_queue_stats {
9d5c8243 AK	191	u64 packets;
9d5c8243 AK	192	u64 bytes;
04a5fcaa	193	u64 restart_queue;
12dcd86b	194	u64 restart_queue2;
9d5c8243 AK	195	};
9d5c8243 AK	196
8c0ab70a JDB	197	struct igb_rx_queue_stats {
	198	u64 packets;
	199	u64 bytes;
	200	u64 drops;
04a5fcaa AD	201	u64 csum_err;
04a5fcaa AD	202	u64 alloc_failed;
8c0ab70a JDB	203	};
8c0ab70a JDB	204
0ba82994 AD	205	struct igb_ring_container {
	206	struct igb_ring ring; / pointer to linked list of rings */
	207	unsigned int total_bytes; /* total bytes processed this int */
	208	unsigned int total_packets; /* total packets processed this int */
	209	u16 work_limit; /* total work allowed per interrupt */
	210	u8 count; /* total number of rings in vector */
	211	u8 itr; /* current ITR setting for ring */
	212	};
	213
047e0030	214	struct igb_ring {
238ac817 AD	215	struct igb_q_vector q_vector; / backlink to q_vector */
	216	struct net_device netdev; / back pointer to net_device */
	217	struct device dev; / device pointer for dma mapping */
06034649 AD	218	union { /* array of buffer info structs */
	219	struct igb_tx_buffer *tx_buffer_info;
	220	struct igb_rx_buffer *rx_buffer_info;
	221	};
238ac817 AD	222	void desc; / descriptor ring memory */
	223	unsigned long flags; /* ring specific flags */
	224	void __iomem tail; / pointer to ring tail register */
5536d210 AD	225	dma_addr_t dma; /* phys address of the ring */
5536d210 AD	226	unsigned int size; /* length of desc. ring in bytes */
238ac817 AD	227
	228	u16 count; /* number of desc. in the ring */
	229	u8 queue_index; /* logical index of the ring*/
	230	u8 reg_idx; /* physical index of the ring */
238ac817 AD	231
238ac817 AD	232	/* everything past this point are written often */
5536d210	233	u16 next_to_clean;
9d5c8243	234	u16 next_to_use;
cbc8e55f	235	u16 next_to_alloc;
9d5c8243	236
9d5c8243 AK	237	union {
	238	/* TX */
	239	struct {
8c0ab70a	240	struct igb_tx_queue_stats tx_stats;
12dcd86b ED	241	struct u64_stats_sync tx_syncp;
12dcd86b ED	242	struct u64_stats_sync tx_syncp2;
9d5c8243 AK	243	};
	244	/* RX */
	245	struct {
1a1c225b	246	struct sk_buff *skb;
8c0ab70a	247	struct igb_rx_queue_stats rx_stats;
12dcd86b	248	struct u64_stats_sync rx_syncp;
9d5c8243 AK	249	};
9d5c8243 AK	250	};
5536d210 AD	251	} ____cacheline_internodealigned_in_smp;
	252
	253	struct igb_q_vector {
	254	struct igb_adapter adapter; / backlink */
	255	int cpu; /* CPU for DCA */
	256	u32 eims_value; /* EIMS mask value */
	257
	258	u16 itr_val;
	259	u8 set_itr;
	260	void __iomem *itr_register;
	261
	262	struct igb_ring_container rx, tx;
	263
	264	struct napi_struct napi;
	265	struct rcu_head rcu; /* to avoid race with update stats on free */
	266	char name[IFNAMSIZ + 9];
	267
	268	/* for dynamic allocation of rings associated with this q_vector */
	269	struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
9d5c8243 AK	270	};
9d5c8243 AK	271
866cff06	272	enum e1000_ring_flags_t {
866cff06	273	IGB_RING_FLAG_RX_SCTP_CSUM,
8be10e91	274	IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
866cff06 AD	275	IGB_RING_FLAG_TX_CTX_IDX,
	276	IGB_RING_FLAG_TX_DETECT_HANG
	277	};
85ad76b2	278
e032afc8	279	#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP \| E1000_ADVTXD_DCMD_RS)
85ad76b2	280
60136906 AD	281	#define IGB_RX_DESC(R, i) \
	282	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
	283	#define IGB_TX_DESC(R, i) \
	284	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
	285	#define IGB_TX_CTXTDESC(R, i) \
	286	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
9d5c8243	287
3ceb90fd AD	288	/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
	289	static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
	290	const u32 stat_err_bits)
	291	{
	292	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
	293	}
	294
d7ee5b3a AD	295	/* igb_desc_unused - calculate if we have unused descriptors */
	296	static inline int igb_desc_unused(struct igb_ring *ring)
	297	{
	298	if (ring->next_to_clean > ring->next_to_use)
	299	return ring->next_to_clean - ring->next_to_use - 1;
	300
	301	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
	302	}
	303
9d5c8243	304	/* board specific private data structure */
9d5c8243	305	struct igb_adapter {
b2cb09b1	306	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
238ac817 AD	307
	308	struct net_device *netdev;
	309
	310	unsigned long state;
	311	unsigned int flags;
	312
	313	unsigned int num_q_vectors;
	314	struct msix_entry *msix_entries;
2e5655e7	315
9d5c8243	316	/* Interrupt Throttle Rate */
4fc82adf AD	317	u32 rx_itr_setting;
4fc82adf AD	318	u32 tx_itr_setting;
9d5c8243 AK	319	u16 tx_itr;
9d5c8243 AK	320	u16 rx_itr;
9d5c8243	321
9d5c8243	322	/* TX */
13fde97a	323	u16 tx_work_limit;
9d5c8243	324	u32 tx_timeout_count;
238ac817 AD	325	int num_tx_queues;
238ac817 AD	326	struct igb_ring *tx_ring[16];
9d5c8243 AK	327
9d5c8243 AK	328	/* RX */
9d5c8243	329	int num_rx_queues;
238ac817	330	struct igb_ring *rx_ring[16];
9d5c8243	331
9d5c8243 AK	332	u32 max_frame_size;
	333	u32 min_frame_size;
	334
238ac817 AD	335	struct timer_list watchdog_timer;
	336	struct timer_list phy_info_timer;
	337
	338	u16 mng_vlan_id;
	339	u32 bd_number;
	340	u32 wol;
	341	u32 en_mng_pt;
	342	u16 link_speed;
	343	u16 link_duplex;
	344
	345	struct work_struct reset_task;
	346	struct work_struct watchdog_task;
	347	bool fc_autoneg;
	348	u8 tx_timeout_factor;
	349	struct timer_list blink_timer;
	350	unsigned long led_status;
	351
9d5c8243	352	/* OS defined structs */
9d5c8243	353	struct pci_dev *pdev;
9d5c8243	354
12dcd86b ED	355	spinlock_t stats64_lock;
	356	struct rtnl_link_stats64 stats64;
	357
9d5c8243 AK	358	/* structs defined in e1000_hw.h */
	359	struct e1000_hw hw;
	360	struct e1000_hw_stats stats;
	361	struct e1000_phy_info phy_info;
	362	struct e1000_phy_stats phy_stats;
	363
	364	u32 test_icr;
	365	struct igb_ring test_tx_ring;
	366	struct igb_ring test_rx_ring;
	367
	368	int msg_enable;
047e0030	369
047e0030	370	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243	371	u32 eims_enable_mask;
844290e5	372	u32 eims_other;
9d5c8243 AK	373
9d5c8243 AK	374	/* to not mess up cache alignment, always add to the bottom */
2e5655e7 AD	375	u16 tx_ring_count;
2e5655e7 AD	376	u16 rx_ring_count;
1bfaf07b	377	unsigned int vfs_allocated_count;
4ae196df	378	struct vf_data_storage *vf_data;
17dc566c	379	int vf_rate_link_speed;
a99955fc	380	u32 rss_queues;
13800469	381	u32 wvbr;
1128c756	382	u32 *shadow_vfta;
d339b133 RC	383
d339b133 RC	384	struct ptp_clock *ptp_clock;
a79f4f88 MV	385	struct ptp_clock_info ptp_caps;
a79f4f88 MV	386	struct delayed_work ptp_overflow_work;
1f6e8178 MV	387	struct work_struct ptp_tx_work;
1f6e8178 MV	388	struct sk_buff *ptp_tx_skb;
d339b133 RC	389	spinlock_t tmreg_lock;
	390	struct cyclecounter cc;
	391	struct timecounter tc;
3c89f6d0	392
d67974f0	393	char fw_version[32];
9d5c8243 AK	394	};
9d5c8243 AK	395
039454a8 AA	396	#define IGB_FLAG_HAS_MSI (1 << 0)
	397	#define IGB_FLAG_DCA_ENABLED (1 << 1)
	398	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
	399	#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
	400	#define IGB_FLAG_DMAC (1 << 4)
	401	#define IGB_FLAG_PTP (1 << 5)
	402	#define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6)
	403	#define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7)
63d4a8f9	404	#define IGB_FLAG_WOL_SUPPORTED (1 << 8)
831ec0b4 CW	405
	406	/* DMA Coalescing defines */
	407	#define IGB_MIN_TXPBSIZE 20408
	408	#define IGB_TX_BUF_4096 4096
	409	#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
7dfc16fa	410
c5b9bd5e	411	#define IGB_82576_TSYNC_SHIFT 19
757b77e2	412	#define IGB_TS_HDR_LEN 16
9d5c8243 AK	413	enum e1000_state_t {
	414	__IGB_TESTING,
	415	__IGB_RESETTING,
	416	__IGB_DOWN
	417	};
	418
	419	enum igb_boards {
	420	board_82575,
	421	};
	422
	423	extern char igb_driver_name[];
	424	extern char igb_driver_version[];
	425
9d5c8243 AK	426	extern int igb_up(struct igb_adapter *);
	427	extern void igb_down(struct igb_adapter *);
	428	extern void igb_reinit_locked(struct igb_adapter *);
	429	extern void igb_reset(struct igb_adapter *);
14ad2513	430	extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
80785298 AD	431	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	432	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	433	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	434	extern void igb_free_rx_resources(struct igb_ring *);
d7ee5b3a AD	435	extern void igb_configure_tx_ring(struct igb_adapter , struct igb_ring );
	436	extern void igb_configure_rx_ring(struct igb_adapter , struct igb_ring );
	437	extern void igb_setup_tctl(struct igb_adapter *);
	438	extern void igb_setup_rctl(struct igb_adapter *);
cd392f5c	439	extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff , struct igb_ring );
b1a436c3	440	extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
06034649	441	struct igb_tx_buffer *);
cd392f5c	442	extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
12dcd86b	443	extern void igb_update_stats(struct igb_adapter , struct rtnl_link_stats64 );
3145535a	444	extern bool igb_has_link(struct igb_adapter *adapter);
9d5c8243	445	extern void igb_set_ethtool_ops(struct net_device *);
88a268c1	446	extern void igb_power_up_link(struct igb_adapter *);
d67974f0	447	extern void igb_set_fw_version(struct igb_adapter *);
7ebae817	448	extern void igb_ptp_init(struct igb_adapter *adapter);
a79f4f88	449	extern void igb_ptp_stop(struct igb_adapter *adapter);
1f6e8178 MV	450	extern void igb_ptp_reset(struct igb_adapter *adapter);
	451	extern void igb_ptp_tx_work(struct work_struct *work);
	452	extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
b534550a	453	extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
a79f4f88	454	struct sk_buff *skb);
b534550a AD	455	extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
	456	unsigned char *va,
	457	struct sk_buff *skb);
	458	static inline void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector,
	459	union e1000_adv_rx_desc *rx_desc,
	460	struct sk_buff *skb)
	461	{
1a1c225b AD	462	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
1a1c225b AD	463	!igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
b534550a	464	igb_ptp_rx_rgtstamp(q_vector, skb);
b534550a	465	}
1a1c225b	466
a79f4f88 MV	467	extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
a79f4f88 MV	468	struct ifreq *ifr, int cmd);
7ebae817	469
f5f4cf08 AD	470	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	471	{
a8d2a0c2 AD	472	if (hw->phy.ops.reset)
a8d2a0c2 AD	473	return hw->phy.ops.reset(hw);
f5f4cf08 AD	474
	475	return 0;
	476	}
	477
	478	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	479	{
a8d2a0c2 AD	480	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	481	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	482
	483	return 0;
	484	}
	485
	486	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	487	{
a8d2a0c2 AD	488	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	489	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	490
	491	return 0;
	492	}
	493
	494	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	495	{
	496	if (hw->phy.ops.get_phy_info)
	497	return hw->phy.ops.get_phy_info(hw);
	498
	499	return 0;
	500	}
	501
bdbc0631 ED	502	static inline struct netdev_queue txring_txq(const struct igb_ring tx_ring)
	503	{
	504	return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
	505	}
	506
9d5c8243	507	#endif /* _IGB_H_ */