Commit | Line | Data |
---|---|---|
9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
6e861326 | 4 | Copyright(c) 2007-2012 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | ||
29 | /* Linux PRO/1000 Ethernet Driver main header file */ | |
30 | ||
31 | #ifndef _IGB_H_ | |
32 | #define _IGB_H_ | |
33 | ||
34 | #include "e1000_mac.h" | |
35 | #include "e1000_82575.h" | |
36 | ||
38c845c7 | 37 | #include <linux/clocksource.h> |
33af6bcc | 38 | #include <linux/net_tstamp.h> |
d339b133 | 39 | #include <linux/ptp_clock_kernel.h> |
b2cb09b1 JP |
40 | #include <linux/bitops.h> |
41 | #include <linux/if_vlan.h> | |
38c845c7 | 42 | |
9d5c8243 AK |
43 | struct igb_adapter; |
44 | ||
0ba82994 AD |
45 | /* Interrupt defines */ |
46 | #define IGB_START_ITR 648 /* ~6000 ints/sec */ | |
47 | #define IGB_4K_ITR 980 | |
48 | #define IGB_20K_ITR 196 | |
49 | #define IGB_70K_ITR 56 | |
9d5c8243 | 50 | |
9d5c8243 AK |
51 | /* TX/RX descriptor defines */ |
52 | #define IGB_DEFAULT_TXD 256 | |
13fde97a | 53 | #define IGB_DEFAULT_TX_WORK 128 |
9d5c8243 AK |
54 | #define IGB_MIN_TXD 80 |
55 | #define IGB_MAX_TXD 4096 | |
56 | ||
57 | #define IGB_DEFAULT_RXD 256 | |
58 | #define IGB_MIN_RXD 80 | |
59 | #define IGB_MAX_RXD 4096 | |
60 | ||
61 | #define IGB_DEFAULT_ITR 3 /* dynamic */ | |
62 | #define IGB_MAX_ITR_USECS 10000 | |
63 | #define IGB_MIN_ITR_USECS 10 | |
047e0030 AD |
64 | #define NON_Q_VECTORS 1 |
65 | #define MAX_Q_VECTORS 8 | |
9d5c8243 AK |
66 | |
67 | /* Transmit and receive queues */ | |
374a542d MV |
68 | #define IGB_MAX_RX_QUEUES 8 |
69 | #define IGB_MAX_RX_QUEUES_82575 4 | |
f96a8a0b | 70 | #define IGB_MAX_RX_QUEUES_I211 2 |
374a542d | 71 | #define IGB_MAX_TX_QUEUES 8 |
4ae196df AD |
72 | #define IGB_MAX_VF_MC_ENTRIES 30 |
73 | #define IGB_MAX_VF_FUNCTIONS 8 | |
74 | #define IGB_MAX_VFTA_ENTRIES 128 | |
0224d663 GR |
75 | #define IGB_82576_VF_DEV_ID 0x10CA |
76 | #define IGB_I350_VF_DEV_ID 0x1520 | |
4ae196df | 77 | |
d67974f0 CW |
78 | /* NVM version defines */ |
79 | #define IGB_MAJOR_MASK 0xF000 | |
80 | #define IGB_MINOR_MASK 0x0FF0 | |
81 | #define IGB_BUILD_MASK 0x000F | |
82 | #define IGB_COMB_VER_MASK 0x00FF | |
83 | #define IGB_MAJOR_SHIFT 12 | |
84 | #define IGB_MINOR_SHIFT 4 | |
85 | #define IGB_COMB_VER_SHFT 8 | |
86 | #define IGB_NVM_VER_INVALID 0xFFFF | |
87 | #define IGB_ETRACK_SHIFT 16 | |
88 | #define NVM_ETRACK_WORD 0x0042 | |
89 | #define NVM_COMB_VER_OFF 0x0083 | |
90 | #define NVM_COMB_VER_PTR 0x003d | |
91 | ||
4ae196df AD |
92 | struct vf_data_storage { |
93 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
94 | u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; | |
95 | u16 num_vf_mc_hashes; | |
ae641bdc | 96 | u16 vlans_enabled; |
f2ca0dbe AD |
97 | u32 flags; |
98 | unsigned long last_nack; | |
8151d294 WM |
99 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
100 | u16 pf_qos; | |
17dc566c | 101 | u16 tx_rate; |
0224d663 | 102 | struct pci_dev *vfdev; |
4ae196df AD |
103 | }; |
104 | ||
f2ca0dbe | 105 | #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ |
7d5753f0 AD |
106 | #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ |
107 | #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ | |
8151d294 | 108 | #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ |
f2ca0dbe | 109 | |
9d5c8243 AK |
110 | /* RX descriptor control thresholds. |
111 | * PTHRESH - MAC will consider prefetch if it has fewer than this number of | |
112 | * descriptors available in its onboard memory. | |
113 | * Setting this to 0 disables RX descriptor prefetch. | |
114 | * HTHRESH - MAC will only prefetch if there are at least this many descriptors | |
115 | * available in host memory. | |
116 | * If PTHRESH is 0, this should also be 0. | |
117 | * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back | |
118 | * descriptors until either it has this many to write back, or the | |
119 | * ITR timer expires. | |
120 | */ | |
58fd62f5 | 121 | #define IGB_RX_PTHRESH 8 |
9d5c8243 | 122 | #define IGB_RX_HTHRESH 8 |
85b430b4 AD |
123 | #define IGB_TX_PTHRESH 8 |
124 | #define IGB_TX_HTHRESH 1 | |
a74420e0 AD |
125 | #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
126 | adapter->msix_entries) ? 1 : 4) | |
85b430b4 | 127 | #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
a74420e0 | 128 | adapter->msix_entries) ? 1 : 16) |
9d5c8243 AK |
129 | |
130 | /* this is the size past which hardware will drop packets when setting LPE=0 */ | |
131 | #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 | |
132 | ||
133 | /* Supported Rx Buffer Sizes */ | |
44390ca6 | 134 | #define IGB_RXBUFFER_512 512 |
9d5c8243 | 135 | #define IGB_RXBUFFER_16384 16384 |
44390ca6 | 136 | #define IGB_RX_HDR_LEN IGB_RXBUFFER_512 |
9d5c8243 | 137 | |
9d5c8243 AK |
138 | /* How many Tx Descriptors do we need to call netif_wake_queue ? */ |
139 | #define IGB_TX_QUEUE_WAKE 16 | |
140 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
141 | #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
142 | ||
143 | #define AUTO_ALL_MODES 0 | |
144 | #define IGB_EEPROM_APME 0x0400 | |
145 | ||
146 | #ifndef IGB_MASTER_SLAVE | |
147 | /* Switch to override PHY master/slave setting */ | |
148 | #define IGB_MASTER_SLAVE e1000_ms_hw_default | |
149 | #endif | |
150 | ||
151 | #define IGB_MNG_VLAN_NONE -1 | |
152 | ||
2bbfebe2 AD |
153 | #define IGB_TX_FLAGS_CSUM 0x00000001 |
154 | #define IGB_TX_FLAGS_VLAN 0x00000002 | |
155 | #define IGB_TX_FLAGS_TSO 0x00000004 | |
156 | #define IGB_TX_FLAGS_IPV4 0x00000008 | |
157 | #define IGB_TX_FLAGS_TSTAMP 0x00000010 | |
2bbfebe2 AD |
158 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 |
159 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 | |
160 | ||
9d5c8243 AK |
161 | /* wrapper around a pointer to a socket buffer, |
162 | * so a DMA handle can be stored along with the buffer */ | |
06034649 | 163 | struct igb_tx_buffer { |
8542db05 | 164 | union e1000_adv_tx_desc *next_to_watch; |
06034649 | 165 | unsigned long time_stamp; |
06034649 AD |
166 | struct sk_buff *skb; |
167 | unsigned int bytecount; | |
168 | u16 gso_segs; | |
7af40ad9 | 169 | __be16 protocol; |
ebe42d16 AD |
170 | dma_addr_t dma; |
171 | u32 length; | |
172 | u32 tx_flags; | |
06034649 AD |
173 | }; |
174 | ||
175 | struct igb_rx_buffer { | |
9d5c8243 AK |
176 | struct sk_buff *skb; |
177 | dma_addr_t dma; | |
06034649 AD |
178 | struct page *page; |
179 | dma_addr_t page_dma; | |
180 | u32 page_offset; | |
9d5c8243 AK |
181 | }; |
182 | ||
8c0ab70a | 183 | struct igb_tx_queue_stats { |
9d5c8243 AK |
184 | u64 packets; |
185 | u64 bytes; | |
04a5fcaa | 186 | u64 restart_queue; |
12dcd86b | 187 | u64 restart_queue2; |
9d5c8243 AK |
188 | }; |
189 | ||
8c0ab70a JDB |
190 | struct igb_rx_queue_stats { |
191 | u64 packets; | |
192 | u64 bytes; | |
193 | u64 drops; | |
04a5fcaa AD |
194 | u64 csum_err; |
195 | u64 alloc_failed; | |
8c0ab70a JDB |
196 | }; |
197 | ||
0ba82994 AD |
198 | struct igb_ring_container { |
199 | struct igb_ring *ring; /* pointer to linked list of rings */ | |
200 | unsigned int total_bytes; /* total bytes processed this int */ | |
201 | unsigned int total_packets; /* total packets processed this int */ | |
202 | u16 work_limit; /* total work allowed per interrupt */ | |
203 | u8 count; /* total number of rings in vector */ | |
204 | u8 itr; /* current ITR setting for ring */ | |
205 | }; | |
206 | ||
047e0030 | 207 | struct igb_q_vector { |
0ba82994 AD |
208 | struct igb_adapter *adapter; /* backlink */ |
209 | int cpu; /* CPU for DCA */ | |
210 | u32 eims_value; /* EIMS mask value */ | |
047e0030 | 211 | |
0ba82994 | 212 | struct igb_ring_container rx, tx; |
047e0030 | 213 | |
0ba82994 | 214 | struct napi_struct napi; |
81c2fc22 AD |
215 | int numa_node; |
216 | ||
047e0030 AD |
217 | u16 itr_val; |
218 | u8 set_itr; | |
047e0030 AD |
219 | void __iomem *itr_register; |
220 | ||
221 | char name[IFNAMSIZ + 9]; | |
222 | }; | |
223 | ||
224 | struct igb_ring { | |
238ac817 AD |
225 | struct igb_q_vector *q_vector; /* backlink to q_vector */ |
226 | struct net_device *netdev; /* back pointer to net_device */ | |
227 | struct device *dev; /* device pointer for dma mapping */ | |
06034649 AD |
228 | union { /* array of buffer info structs */ |
229 | struct igb_tx_buffer *tx_buffer_info; | |
230 | struct igb_rx_buffer *rx_buffer_info; | |
231 | }; | |
238ac817 AD |
232 | void *desc; /* descriptor ring memory */ |
233 | unsigned long flags; /* ring specific flags */ | |
234 | void __iomem *tail; /* pointer to ring tail register */ | |
235 | ||
236 | u16 count; /* number of desc. in the ring */ | |
237 | u8 queue_index; /* logical index of the ring*/ | |
238 | u8 reg_idx; /* physical index of the ring */ | |
239 | u32 size; /* length of desc. ring in bytes */ | |
240 | ||
241 | /* everything past this point are written often */ | |
242 | u16 next_to_clean ____cacheline_aligned_in_smp; | |
9d5c8243 | 243 | u16 next_to_use; |
9d5c8243 | 244 | |
9d5c8243 AK |
245 | union { |
246 | /* TX */ | |
247 | struct { | |
8c0ab70a | 248 | struct igb_tx_queue_stats tx_stats; |
12dcd86b ED |
249 | struct u64_stats_sync tx_syncp; |
250 | struct u64_stats_sync tx_syncp2; | |
9d5c8243 AK |
251 | }; |
252 | /* RX */ | |
253 | struct { | |
8c0ab70a | 254 | struct igb_rx_queue_stats rx_stats; |
12dcd86b | 255 | struct u64_stats_sync rx_syncp; |
9d5c8243 AK |
256 | }; |
257 | }; | |
238ac817 AD |
258 | /* Items past this point are only used during ring alloc / free */ |
259 | dma_addr_t dma; /* phys address of the ring */ | |
81c2fc22 | 260 | int numa_node; /* node to alloc ring memory on */ |
9d5c8243 AK |
261 | }; |
262 | ||
866cff06 | 263 | enum e1000_ring_flags_t { |
866cff06 | 264 | IGB_RING_FLAG_RX_SCTP_CSUM, |
8be10e91 | 265 | IGB_RING_FLAG_RX_LB_VLAN_BSWAP, |
866cff06 AD |
266 | IGB_RING_FLAG_TX_CTX_IDX, |
267 | IGB_RING_FLAG_TX_DETECT_HANG | |
268 | }; | |
85ad76b2 | 269 | |
e032afc8 | 270 | #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) |
85ad76b2 | 271 | |
60136906 AD |
272 | #define IGB_RX_DESC(R, i) \ |
273 | (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) | |
274 | #define IGB_TX_DESC(R, i) \ | |
275 | (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) | |
276 | #define IGB_TX_CTXTDESC(R, i) \ | |
277 | (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) | |
9d5c8243 | 278 | |
3ceb90fd AD |
279 | /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ |
280 | static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, | |
281 | const u32 stat_err_bits) | |
282 | { | |
283 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
284 | } | |
285 | ||
d7ee5b3a AD |
286 | /* igb_desc_unused - calculate if we have unused descriptors */ |
287 | static inline int igb_desc_unused(struct igb_ring *ring) | |
288 | { | |
289 | if (ring->next_to_clean > ring->next_to_use) | |
290 | return ring->next_to_clean - ring->next_to_use - 1; | |
291 | ||
292 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; | |
293 | } | |
294 | ||
9d5c8243 | 295 | /* board specific private data structure */ |
9d5c8243 | 296 | struct igb_adapter { |
b2cb09b1 | 297 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
238ac817 AD |
298 | |
299 | struct net_device *netdev; | |
300 | ||
301 | unsigned long state; | |
302 | unsigned int flags; | |
303 | ||
304 | unsigned int num_q_vectors; | |
305 | struct msix_entry *msix_entries; | |
2e5655e7 | 306 | |
9d5c8243 | 307 | /* Interrupt Throttle Rate */ |
4fc82adf AD |
308 | u32 rx_itr_setting; |
309 | u32 tx_itr_setting; | |
9d5c8243 AK |
310 | u16 tx_itr; |
311 | u16 rx_itr; | |
9d5c8243 | 312 | |
9d5c8243 | 313 | /* TX */ |
13fde97a | 314 | u16 tx_work_limit; |
9d5c8243 | 315 | u32 tx_timeout_count; |
238ac817 AD |
316 | int num_tx_queues; |
317 | struct igb_ring *tx_ring[16]; | |
9d5c8243 AK |
318 | |
319 | /* RX */ | |
9d5c8243 | 320 | int num_rx_queues; |
238ac817 | 321 | struct igb_ring *rx_ring[16]; |
9d5c8243 | 322 | |
9d5c8243 AK |
323 | u32 max_frame_size; |
324 | u32 min_frame_size; | |
325 | ||
238ac817 AD |
326 | struct timer_list watchdog_timer; |
327 | struct timer_list phy_info_timer; | |
328 | ||
329 | u16 mng_vlan_id; | |
330 | u32 bd_number; | |
331 | u32 wol; | |
332 | u32 en_mng_pt; | |
333 | u16 link_speed; | |
334 | u16 link_duplex; | |
335 | ||
336 | struct work_struct reset_task; | |
337 | struct work_struct watchdog_task; | |
338 | bool fc_autoneg; | |
339 | u8 tx_timeout_factor; | |
340 | struct timer_list blink_timer; | |
341 | unsigned long led_status; | |
342 | ||
9d5c8243 | 343 | /* OS defined structs */ |
9d5c8243 | 344 | struct pci_dev *pdev; |
33af6bcc | 345 | struct hwtstamp_config hwtstamp_config; |
9d5c8243 | 346 | |
12dcd86b ED |
347 | spinlock_t stats64_lock; |
348 | struct rtnl_link_stats64 stats64; | |
349 | ||
9d5c8243 AK |
350 | /* structs defined in e1000_hw.h */ |
351 | struct e1000_hw hw; | |
352 | struct e1000_hw_stats stats; | |
353 | struct e1000_phy_info phy_info; | |
354 | struct e1000_phy_stats phy_stats; | |
355 | ||
356 | u32 test_icr; | |
357 | struct igb_ring test_tx_ring; | |
358 | struct igb_ring test_rx_ring; | |
359 | ||
360 | int msg_enable; | |
047e0030 | 361 | |
047e0030 | 362 | struct igb_q_vector *q_vector[MAX_Q_VECTORS]; |
9d5c8243 | 363 | u32 eims_enable_mask; |
844290e5 | 364 | u32 eims_other; |
9d5c8243 AK |
365 | |
366 | /* to not mess up cache alignment, always add to the bottom */ | |
9d5c8243 | 367 | u32 eeprom_wol; |
42bfd33a | 368 | |
2e5655e7 AD |
369 | u16 tx_ring_count; |
370 | u16 rx_ring_count; | |
1bfaf07b | 371 | unsigned int vfs_allocated_count; |
4ae196df | 372 | struct vf_data_storage *vf_data; |
17dc566c | 373 | int vf_rate_link_speed; |
a99955fc | 374 | u32 rss_queues; |
13800469 | 375 | u32 wvbr; |
81c2fc22 | 376 | int node; |
1128c756 | 377 | u32 *shadow_vfta; |
d339b133 RC |
378 | |
379 | struct ptp_clock *ptp_clock; | |
380 | struct ptp_clock_info caps; | |
381 | struct delayed_work overflow_work; | |
382 | spinlock_t tmreg_lock; | |
383 | struct cyclecounter cc; | |
384 | struct timecounter tc; | |
d67974f0 | 385 | char fw_version[32]; |
9d5c8243 AK |
386 | }; |
387 | ||
7dfc16fa | 388 | #define IGB_FLAG_HAS_MSI (1 << 0) |
cbd347ad AD |
389 | #define IGB_FLAG_DCA_ENABLED (1 << 1) |
390 | #define IGB_FLAG_QUAD_PORT_A (1 << 2) | |
4fc82adf | 391 | #define IGB_FLAG_QUEUE_PAIRS (1 << 3) |
831ec0b4 CW |
392 | #define IGB_FLAG_DMAC (1 << 4) |
393 | ||
394 | /* DMA Coalescing defines */ | |
395 | #define IGB_MIN_TXPBSIZE 20408 | |
396 | #define IGB_TX_BUF_4096 4096 | |
397 | #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ | |
7dfc16fa | 398 | |
c5b9bd5e | 399 | #define IGB_82576_TSYNC_SHIFT 19 |
757b77e2 | 400 | #define IGB_TS_HDR_LEN 16 |
9d5c8243 AK |
401 | enum e1000_state_t { |
402 | __IGB_TESTING, | |
403 | __IGB_RESETTING, | |
404 | __IGB_DOWN | |
405 | }; | |
406 | ||
407 | enum igb_boards { | |
408 | board_82575, | |
409 | }; | |
410 | ||
411 | extern char igb_driver_name[]; | |
412 | extern char igb_driver_version[]; | |
413 | ||
9d5c8243 AK |
414 | extern int igb_up(struct igb_adapter *); |
415 | extern void igb_down(struct igb_adapter *); | |
416 | extern void igb_reinit_locked(struct igb_adapter *); | |
417 | extern void igb_reset(struct igb_adapter *); | |
14ad2513 | 418 | extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8); |
80785298 AD |
419 | extern int igb_setup_tx_resources(struct igb_ring *); |
420 | extern int igb_setup_rx_resources(struct igb_ring *); | |
68fd9910 AD |
421 | extern void igb_free_tx_resources(struct igb_ring *); |
422 | extern void igb_free_rx_resources(struct igb_ring *); | |
d7ee5b3a AD |
423 | extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); |
424 | extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); | |
425 | extern void igb_setup_tctl(struct igb_adapter *); | |
426 | extern void igb_setup_rctl(struct igb_adapter *); | |
cd392f5c | 427 | extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); |
b1a436c3 | 428 | extern void igb_unmap_and_free_tx_resource(struct igb_ring *, |
06034649 | 429 | struct igb_tx_buffer *); |
cd392f5c | 430 | extern void igb_alloc_rx_buffers(struct igb_ring *, u16); |
12dcd86b | 431 | extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); |
3145535a | 432 | extern bool igb_has_link(struct igb_adapter *adapter); |
9d5c8243 | 433 | extern void igb_set_ethtool_ops(struct net_device *); |
88a268c1 | 434 | extern void igb_power_up_link(struct igb_adapter *); |
d67974f0 | 435 | extern void igb_set_fw_version(struct igb_adapter *); |
7ebae817 RC |
436 | #ifdef CONFIG_IGB_PTP |
437 | extern void igb_ptp_init(struct igb_adapter *adapter); | |
438 | extern void igb_ptp_remove(struct igb_adapter *adapter); | |
9d5c8243 | 439 | |
7ebae817 RC |
440 | extern void igb_systim_to_hwtstamp(struct igb_adapter *adapter, |
441 | struct skb_shared_hwtstamps *hwtstamps, | |
442 | u64 systim); | |
443 | ||
444 | #endif | |
f5f4cf08 AD |
445 | static inline s32 igb_reset_phy(struct e1000_hw *hw) |
446 | { | |
a8d2a0c2 AD |
447 | if (hw->phy.ops.reset) |
448 | return hw->phy.ops.reset(hw); | |
f5f4cf08 AD |
449 | |
450 | return 0; | |
451 | } | |
452 | ||
453 | static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
454 | { | |
a8d2a0c2 AD |
455 | if (hw->phy.ops.read_reg) |
456 | return hw->phy.ops.read_reg(hw, offset, data); | |
f5f4cf08 AD |
457 | |
458 | return 0; | |
459 | } | |
460 | ||
461 | static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
462 | { | |
a8d2a0c2 AD |
463 | if (hw->phy.ops.write_reg) |
464 | return hw->phy.ops.write_reg(hw, offset, data); | |
f5f4cf08 AD |
465 | |
466 | return 0; | |
467 | } | |
468 | ||
469 | static inline s32 igb_get_phy_info(struct e1000_hw *hw) | |
470 | { | |
471 | if (hw->phy.ops.get_phy_info) | |
472 | return hw->phy.ops.get_phy_info(hw); | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
bdbc0631 ED |
477 | static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) |
478 | { | |
479 | return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); | |
480 | } | |
481 | ||
9d5c8243 | 482 | #endif /* _IGB_H_ */ |