[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2011 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_DEFAULT_TX_WORK		 128
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
                                           (hw->mac.type > e1000_82575 ? 8 : 4))
#define IGB_MAX_TX_QUEUES                  16

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	u32 flags;
	unsigned long last_nack;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
	u16 tx_rate;
};

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                     8
#define IGB_RX_HTHRESH                     8
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 4)
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_512   512
#define IGB_RXBUFFER_16384 16384
#define IGB_RX_HDR_LEN     IGB_RXBUFFER_512

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

#define IGB_TX_FLAGS_CSUM		0x00000001
#define IGB_TX_FLAGS_VLAN		0x00000002
#define IGB_TX_FLAGS_TSO		0x00000004
#define IGB_TX_FLAGS_IPV4		0x00000008
#define IGB_TX_FLAGS_TSTAMP		0x00000010
#define IGB_TX_FLAGS_VLAN_MASK		0xffff0000
#define IGB_TX_FLAGS_VLAN_SHIFT	16

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_tx_buffer {
	union e1000_adv_tx_desc *next_to_watch;
	unsigned long time_stamp;
	struct sk_buff *skb;
	unsigned int bytecount;
	u16 gso_segs;
	__be16 protocol;
	dma_addr_t dma;
	u32 length;
	u32 tx_flags;
};

struct igb_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	u32 page_offset;
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 restart_queue2;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_q_vector {
	struct igb_adapter *adapter; /* backlink */
	struct igb_ring *rx_ring;
	struct igb_ring *tx_ring;
	struct napi_struct napi;

	u32 eims_value;
	u16 cpu;
	u16 tx_work_limit;

	int numa_node;

	u16 itr_val;
	u8 set_itr;
	void __iomem *itr_register;

	char name[IFNAMSIZ + 9];
};

struct igb_ring {
	struct igb_q_vector *q_vector;	/* backlink to q_vector */
	struct net_device *netdev;	/* back pointer to net_device */
	struct device *dev;		/* device pointer for dma mapping */
	union {				/* array of buffer info structs */
		struct igb_tx_buffer *tx_buffer_info;
		struct igb_rx_buffer *rx_buffer_info;
	};
	void *desc;			/* descriptor ring memory */
	unsigned long flags;		/* ring specific flags */
	void __iomem *tail;		/* pointer to ring tail register */

	u16 count;			/* number of desc. in the ring */
	u8 queue_index;			/* logical index of the ring*/
	u8 reg_idx;			/* physical index of the ring */
	u32 size;			/* length of desc. ring in bytes */

	/* everything past this point are written often */
	u16 next_to_clean ____cacheline_aligned_in_smp;
	u16 next_to_use;

	unsigned int total_bytes;
	unsigned int total_packets;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			struct u64_stats_sync tx_syncp;
			struct u64_stats_sync tx_syncp2;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			struct u64_stats_sync rx_syncp;
		};
	};
	/* Items past this point are only used during ring alloc / free */
	dma_addr_t dma;                /* phys address of the ring */
	int numa_node;                  /* node to alloc ring memory on */
};

#define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
#define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */

#define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */

#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)

#define IGB_RX_DESC(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
#define IGB_TX_DESC(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
#define IGB_TX_CTXTDESC(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))

/* igb_desc_unused - calculate if we have unused descriptors */
static inline int igb_desc_unused(struct igb_ring *ring)
{
	if (ring->next_to_clean > ring->next_to_use)
		return ring->next_to_clean - ring->next_to_use - 1;

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
}

/* board specific private data structure */
struct igb_adapter {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

	struct net_device *netdev;

	unsigned long state;
	unsigned int flags;

	unsigned int num_q_vectors;
	struct msix_entry *msix_entries;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	/* TX */
	u16 tx_work_limit;
	u32 tx_timeout_count;
	int num_tx_queues;
	struct igb_ring *tx_ring[16];

	/* RX */
	int num_rx_queues;
	struct igb_ring *rx_ring[16];

	u32 max_frame_size;
	u32 min_frame_size;

	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;

	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* OS defined structs */
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	spinlock_t stats64_lock;
	struct rtnl_link_stats64 stats64;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	u32 eeprom_wol;

	u16 tx_ring_count;
	u16 rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
	int vf_rate_link_speed;
	u32 rss_queues;
	u32 wvbr;
	int node;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
#define IGB_FLAG_DMAC              (1 << 4)

/* DMA Coalescing defines */
#define IGB_MIN_TXPBSIZE           20408
#define IGB_TX_BUF_4096            4096
#define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */

#define IGB_82576_TSYNC_SHIFT 19
#define IGB_82580_TSYNC_SHIFT 24
#define IGB_TS_HDR_LEN        16
enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_setup_tctl(struct igb_adapter *);
extern void igb_setup_rctl(struct igb_adapter *);
extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
					   struct igb_tx_buffer *);
extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
extern bool igb_has_link(struct igb_adapter *adapter);
extern void igb_set_ethtool_ops(struct net_device *);
extern void igb_power_up_link(struct igb_adapter *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
4297f99b	4	Copyright(c) 2007-2011 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
b2cb09b1 JP	40	#include <linux/bitops.h>
b2cb09b1 JP	41	#include <linux/if_vlan.h>
38c845c7	42
9d5c8243 AK	43	struct igb_adapter;
9d5c8243 AK	44
6eb5a7f1 AD	45	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	46	#define IGB_START_ITR 648
9d5c8243	47
9d5c8243 AK	48	/* TX/RX descriptor defines */
9d5c8243 AK	49	#define IGB_DEFAULT_TXD 256
13fde97a	50	#define IGB_DEFAULT_TX_WORK 128
9d5c8243 AK	51	#define IGB_MIN_TXD 80
	52	#define IGB_MAX_TXD 4096
	53
	54	#define IGB_DEFAULT_RXD 256
	55	#define IGB_MIN_RXD 80
	56	#define IGB_MAX_RXD 4096
	57
	58	#define IGB_DEFAULT_ITR 3 /* dynamic */
	59	#define IGB_MAX_ITR_USECS 10000
	60	#define IGB_MIN_ITR_USECS 10
047e0030 AD	61	#define NON_Q_VECTORS 1
047e0030 AD	62	#define MAX_Q_VECTORS 8
9d5c8243 AK	63
9d5c8243 AK	64	/* Transmit and receive queues */
a99955fc AD	65	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
a99955fc AD	66	(hw->mac.type > e1000_82575 ? 8 : 4))
1cc3bd87	67	#define IGB_MAX_TX_QUEUES 16
9d5c8243	68
4ae196df AD	69	#define IGB_MAX_VF_MC_ENTRIES 30
	70	#define IGB_MAX_VF_FUNCTIONS 8
	71	#define IGB_MAX_VFTA_ENTRIES 128
	72
	73	struct vf_data_storage {
	74	unsigned char vf_mac_addresses[ETH_ALEN];
	75	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	76	u16 num_vf_mc_hashes;
ae641bdc	77	u16 vlans_enabled;
f2ca0dbe AD	78	u32 flags;
f2ca0dbe AD	79	unsigned long last_nack;
8151d294 WM	80	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
8151d294 WM	81	u16 pf_qos;
17dc566c	82	u16 tx_rate;
4ae196df AD	83	};
4ae196df AD	84
f2ca0dbe	85	#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
7d5753f0 AD	86	#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
7d5753f0 AD	87	#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
8151d294	88	#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
f2ca0dbe	89
9d5c8243 AK	90	/* RX descriptor control thresholds.
	91	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	92	* descriptors available in its onboard memory.
	93	* Setting this to 0 disables RX descriptor prefetch.
	94	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	95	* available in host memory.
	96	* If PTHRESH is 0, this should also be 0.
	97	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	98	* descriptors until either it has this many to write back, or the
	99	* ITR timer expires.
	100	*/
58fd62f5	101	#define IGB_RX_PTHRESH 8
9d5c8243	102	#define IGB_RX_HTHRESH 8
85b430b4 AD	103	#define IGB_TX_PTHRESH 8
85b430b4 AD	104	#define IGB_TX_HTHRESH 1
a74420e0 AD	105	#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0 AD	106	adapter->msix_entries) ? 1 : 4)
85b430b4	107	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0	108	adapter->msix_entries) ? 1 : 16)
9d5c8243 AK	109
	110	/* this is the size past which hardware will drop packets when setting LPE=0 */
	111	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	112
	113	/* Supported Rx Buffer Sizes */
44390ca6	114	#define IGB_RXBUFFER_512 512
9d5c8243	115	#define IGB_RXBUFFER_16384 16384
44390ca6	116	#define IGB_RX_HDR_LEN IGB_RXBUFFER_512
9d5c8243	117
9d5c8243 AK	118	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	119	#define IGB_TX_QUEUE_WAKE 16
	120	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	121	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	122
	123	#define AUTO_ALL_MODES 0
	124	#define IGB_EEPROM_APME 0x0400
	125
	126	#ifndef IGB_MASTER_SLAVE
	127	/* Switch to override PHY master/slave setting */
	128	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	129	#endif
	130
	131	#define IGB_MNG_VLAN_NONE -1
	132
2bbfebe2 AD	133	#define IGB_TX_FLAGS_CSUM 0x00000001
	134	#define IGB_TX_FLAGS_VLAN 0x00000002
	135	#define IGB_TX_FLAGS_TSO 0x00000004
	136	#define IGB_TX_FLAGS_IPV4 0x00000008
	137	#define IGB_TX_FLAGS_TSTAMP 0x00000010
2bbfebe2 AD	138	#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
	139	#define IGB_TX_FLAGS_VLAN_SHIFT 16
	140
9d5c8243 AK	141	/* wrapper around a pointer to a socket buffer,
9d5c8243 AK	142	* so a DMA handle can be stored along with the buffer */
06034649	143	struct igb_tx_buffer {
8542db05	144	union e1000_adv_tx_desc *next_to_watch;
06034649	145	unsigned long time_stamp;
06034649 AD	146	struct sk_buff *skb;
	147	unsigned int bytecount;
	148	u16 gso_segs;
7af40ad9	149	__be16 protocol;
ebe42d16 AD	150	dma_addr_t dma;
	151	u32 length;
	152	u32 tx_flags;
06034649 AD	153	};
	154
	155	struct igb_rx_buffer {
9d5c8243 AK	156	struct sk_buff *skb;
9d5c8243 AK	157	dma_addr_t dma;
06034649 AD	158	struct page *page;
	159	dma_addr_t page_dma;
	160	u32 page_offset;
9d5c8243 AK	161	};
9d5c8243 AK	162
8c0ab70a	163	struct igb_tx_queue_stats {
9d5c8243 AK	164	u64 packets;
9d5c8243 AK	165	u64 bytes;
04a5fcaa	166	u64 restart_queue;
12dcd86b	167	u64 restart_queue2;
9d5c8243 AK	168	};
9d5c8243 AK	169
8c0ab70a JDB	170	struct igb_rx_queue_stats {
	171	u64 packets;
	172	u64 bytes;
	173	u64 drops;
04a5fcaa AD	174	u64 csum_err;
04a5fcaa AD	175	u64 alloc_failed;
8c0ab70a JDB	176	};
8c0ab70a JDB	177
047e0030	178	struct igb_q_vector {
9d5c8243	179	struct igb_adapter adapter; / backlink */
047e0030 AD	180	struct igb_ring *rx_ring;
	181	struct igb_ring *tx_ring;
	182	struct napi_struct napi;
	183
	184	u32 eims_value;
	185	u16 cpu;
13fde97a	186	u16 tx_work_limit;
047e0030	187
81c2fc22 AD	188	int numa_node;
81c2fc22 AD	189
047e0030 AD	190	u16 itr_val;
047e0030 AD	191	u8 set_itr;
047e0030 AD	192	void __iomem *itr_register;
	193
	194	char name[IFNAMSIZ + 9];
	195	};
	196
	197	struct igb_ring {
238ac817 AD	198	struct igb_q_vector q_vector; / backlink to q_vector */
	199	struct net_device netdev; / back pointer to net_device */
	200	struct device dev; / device pointer for dma mapping */
06034649 AD	201	union { /* array of buffer info structs */
	202	struct igb_tx_buffer *tx_buffer_info;
	203	struct igb_rx_buffer *rx_buffer_info;
	204	};
238ac817 AD	205	void desc; / descriptor ring memory */
	206	unsigned long flags; /* ring specific flags */
	207	void __iomem tail; / pointer to ring tail register */
	208
	209	u16 count; /* number of desc. in the ring */
	210	u8 queue_index; /* logical index of the ring*/
	211	u8 reg_idx; /* physical index of the ring */
	212	u32 size; /* length of desc. ring in bytes */
	213
	214	/* everything past this point are written often */
	215	u16 next_to_clean ____cacheline_aligned_in_smp;
9d5c8243	216	u16 next_to_use;
9d5c8243	217
9d5c8243 AK	218	unsigned int total_bytes;
	219	unsigned int total_packets;
	220
	221	union {
	222	/* TX */
	223	struct {
8c0ab70a	224	struct igb_tx_queue_stats tx_stats;
12dcd86b ED	225	struct u64_stats_sync tx_syncp;
12dcd86b ED	226	struct u64_stats_sync tx_syncp2;
9d5c8243 AK	227	bool detect_tx_hung;
	228	};
	229	/* RX */
	230	struct {
8c0ab70a	231	struct igb_rx_queue_stats rx_stats;
12dcd86b	232	struct u64_stats_sync rx_syncp;
9d5c8243 AK	233	};
9d5c8243 AK	234	};
238ac817 AD	235	/* Items past this point are only used during ring alloc / free */
238ac817 AD	236	dma_addr_t dma; /* phys address of the ring */
81c2fc22	237	int numa_node; /* node to alloc ring memory on */
9d5c8243 AK	238	};
9d5c8243 AK	239
85ad76b2 AD	240	#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
	241	#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
	242
	243	#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
	244
e032afc8	245	#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP \| E1000_ADVTXD_DCMD_RS)
85ad76b2	246
60136906 AD	247	#define IGB_RX_DESC(R, i) \
	248	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
	249	#define IGB_TX_DESC(R, i) \
	250	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
	251	#define IGB_TX_CTXTDESC(R, i) \
	252	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
9d5c8243	253
d7ee5b3a AD	254	/* igb_desc_unused - calculate if we have unused descriptors */
	255	static inline int igb_desc_unused(struct igb_ring *ring)
	256	{
	257	if (ring->next_to_clean > ring->next_to_use)
	258	return ring->next_to_clean - ring->next_to_use - 1;
	259
	260	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
	261	}
	262
9d5c8243	263	/* board specific private data structure */
9d5c8243	264	struct igb_adapter {
b2cb09b1	265	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
238ac817 AD	266
	267	struct net_device *netdev;
	268
	269	unsigned long state;
	270	unsigned int flags;
	271
	272	unsigned int num_q_vectors;
	273	struct msix_entry *msix_entries;
2e5655e7	274
9d5c8243	275	/* Interrupt Throttle Rate */
4fc82adf AD	276	u32 rx_itr_setting;
4fc82adf AD	277	u32 tx_itr_setting;
9d5c8243 AK	278	u16 tx_itr;
9d5c8243 AK	279	u16 rx_itr;
9d5c8243	280
9d5c8243	281	/* TX */
13fde97a	282	u16 tx_work_limit;
9d5c8243	283	u32 tx_timeout_count;
238ac817 AD	284	int num_tx_queues;
238ac817 AD	285	struct igb_ring *tx_ring[16];
9d5c8243 AK	286
9d5c8243 AK	287	/* RX */
9d5c8243	288	int num_rx_queues;
238ac817	289	struct igb_ring *rx_ring[16];
9d5c8243	290
9d5c8243 AK	291	u32 max_frame_size;
	292	u32 min_frame_size;
	293
238ac817 AD	294	struct timer_list watchdog_timer;
	295	struct timer_list phy_info_timer;
	296
	297	u16 mng_vlan_id;
	298	u32 bd_number;
	299	u32 wol;
	300	u32 en_mng_pt;
	301	u16 link_speed;
	302	u16 link_duplex;
	303
	304	struct work_struct reset_task;
	305	struct work_struct watchdog_task;
	306	bool fc_autoneg;
	307	u8 tx_timeout_factor;
	308	struct timer_list blink_timer;
	309	unsigned long led_status;
	310
9d5c8243	311	/* OS defined structs */
9d5c8243	312	struct pci_dev *pdev;
38c845c7 PO	313	struct cyclecounter cycles;
38c845c7 PO	314	struct timecounter clock;
33af6bcc PO	315	struct timecompare compare;
33af6bcc PO	316	struct hwtstamp_config hwtstamp_config;
9d5c8243	317
12dcd86b ED	318	spinlock_t stats64_lock;
	319	struct rtnl_link_stats64 stats64;
	320
9d5c8243 AK	321	/* structs defined in e1000_hw.h */
	322	struct e1000_hw hw;
	323	struct e1000_hw_stats stats;
	324	struct e1000_phy_info phy_info;
	325	struct e1000_phy_stats phy_stats;
	326
	327	u32 test_icr;
	328	struct igb_ring test_tx_ring;
	329	struct igb_ring test_rx_ring;
	330
	331	int msg_enable;
047e0030	332
047e0030	333	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243	334	u32 eims_enable_mask;
844290e5	335	u32 eims_other;
9d5c8243 AK	336
9d5c8243 AK	337	/* to not mess up cache alignment, always add to the bottom */
9d5c8243	338	u32 eeprom_wol;
42bfd33a	339
2e5655e7 AD	340	u16 tx_ring_count;
2e5655e7 AD	341	u16 rx_ring_count;
1bfaf07b	342	unsigned int vfs_allocated_count;
4ae196df	343	struct vf_data_storage *vf_data;
17dc566c	344	int vf_rate_link_speed;
a99955fc	345	u32 rss_queues;
13800469	346	u32 wvbr;
81c2fc22	347	int node;
9d5c8243 AK	348	};
9d5c8243 AK	349
7dfc16fa	350	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	351	#define IGB_FLAG_DCA_ENABLED (1 << 1)
cbd347ad AD	352	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
4fc82adf	353	#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
831ec0b4 CW	354	#define IGB_FLAG_DMAC (1 << 4)
	355
	356	/* DMA Coalescing defines */
	357	#define IGB_MIN_TXPBSIZE 20408
	358	#define IGB_TX_BUF_4096 4096
	359	#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
7dfc16fa	360
c5b9bd5e	361	#define IGB_82576_TSYNC_SHIFT 19
55cac248	362	#define IGB_82580_TSYNC_SHIFT 24
757b77e2	363	#define IGB_TS_HDR_LEN 16
9d5c8243 AK	364	enum e1000_state_t {
	365	__IGB_TESTING,
	366	__IGB_RESETTING,
	367	__IGB_DOWN
	368	};
	369
	370	enum igb_boards {
	371	board_82575,
	372	};
	373
	374	extern char igb_driver_name[];
	375	extern char igb_driver_version[];
	376
9d5c8243 AK	377	extern int igb_up(struct igb_adapter *);
	378	extern void igb_down(struct igb_adapter *);
	379	extern void igb_reinit_locked(struct igb_adapter *);
	380	extern void igb_reset(struct igb_adapter *);
14ad2513	381	extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
80785298 AD	382	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	383	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	384	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	385	extern void igb_free_rx_resources(struct igb_ring *);
d7ee5b3a AD	386	extern void igb_configure_tx_ring(struct igb_adapter , struct igb_ring );
	387	extern void igb_configure_rx_ring(struct igb_adapter , struct igb_ring );
	388	extern void igb_setup_tctl(struct igb_adapter *);
	389	extern void igb_setup_rctl(struct igb_adapter *);
cd392f5c	390	extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff , struct igb_ring );
b1a436c3	391	extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
06034649	392	struct igb_tx_buffer *);
cd392f5c	393	extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
12dcd86b	394	extern void igb_update_stats(struct igb_adapter , struct rtnl_link_stats64 );
3145535a	395	extern bool igb_has_link(struct igb_adapter *adapter);
9d5c8243	396	extern void igb_set_ethtool_ops(struct net_device *);
88a268c1	397	extern void igb_power_up_link(struct igb_adapter *);
9d5c8243	398
f5f4cf08 AD	399	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	400	{
a8d2a0c2 AD	401	if (hw->phy.ops.reset)
a8d2a0c2 AD	402	return hw->phy.ops.reset(hw);
f5f4cf08 AD	403
	404	return 0;
	405	}
	406
	407	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	408	{
a8d2a0c2 AD	409	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	410	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	411
	412	return 0;
	413	}
	414
	415	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	416	{
a8d2a0c2 AD	417	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	418	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	419
	420	return 0;
	421	}
	422
	423	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	424	{
	425	if (hw->phy.ops.get_phy_info)
	426	return hw->phy.ops.get_phy_info(hw);
	427
	428	return 0;
	429	}
	430
9d5c8243	431	#endif /* _IGB_H_ */