Commit | Line | Data |
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e52c0f96 CW |
1 | /* Intel(R) Gigabit Ethernet Linux driver |
2 | * Copyright(c) 2007-2014 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, see <http://www.gnu.org/licenses/>. | |
15 | * | |
16 | * The full GNU General Public License is included in this distribution in | |
17 | * the file called "COPYING". | |
18 | * | |
19 | * Contact Information: | |
20 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
21 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
22 | */ | |
9d5c8243 AK |
23 | |
24 | /* Linux PRO/1000 Ethernet Driver main header file */ | |
25 | ||
26 | #ifndef _IGB_H_ | |
27 | #define _IGB_H_ | |
28 | ||
29 | #include "e1000_mac.h" | |
30 | #include "e1000_82575.h" | |
31 | ||
74d23cc7 | 32 | #include <linux/timecounter.h> |
33af6bcc | 33 | #include <linux/net_tstamp.h> |
d339b133 | 34 | #include <linux/ptp_clock_kernel.h> |
b2cb09b1 JP |
35 | #include <linux/bitops.h> |
36 | #include <linux/if_vlan.h> | |
441fc6fd CW |
37 | #include <linux/i2c.h> |
38 | #include <linux/i2c-algo-bit.h> | |
cd14ef54 | 39 | #include <linux/pci.h> |
f4c01e96 | 40 | #include <linux/mdio.h> |
38c845c7 | 41 | |
9d5c8243 AK |
42 | struct igb_adapter; |
43 | ||
b980ac18 | 44 | #define E1000_PCS_CFG_IGN_SD 1 |
3860a0bf | 45 | |
0ba82994 | 46 | /* Interrupt defines */ |
b980ac18 JK |
47 | #define IGB_START_ITR 648 /* ~6000 ints/sec */ |
48 | #define IGB_4K_ITR 980 | |
49 | #define IGB_20K_ITR 196 | |
50 | #define IGB_70K_ITR 56 | |
9d5c8243 | 51 | |
9d5c8243 | 52 | /* TX/RX descriptor defines */ |
b980ac18 JK |
53 | #define IGB_DEFAULT_TXD 256 |
54 | #define IGB_DEFAULT_TX_WORK 128 | |
55 | #define IGB_MIN_TXD 80 | |
56 | #define IGB_MAX_TXD 4096 | |
9d5c8243 | 57 | |
b980ac18 JK |
58 | #define IGB_DEFAULT_RXD 256 |
59 | #define IGB_MIN_RXD 80 | |
60 | #define IGB_MAX_RXD 4096 | |
9d5c8243 | 61 | |
b980ac18 JK |
62 | #define IGB_DEFAULT_ITR 3 /* dynamic */ |
63 | #define IGB_MAX_ITR_USECS 10000 | |
64 | #define IGB_MIN_ITR_USECS 10 | |
65 | #define NON_Q_VECTORS 1 | |
66 | #define MAX_Q_VECTORS 8 | |
cd14ef54 | 67 | #define MAX_MSIX_ENTRIES 10 |
9d5c8243 AK |
68 | |
69 | /* Transmit and receive queues */ | |
b980ac18 JK |
70 | #define IGB_MAX_RX_QUEUES 8 |
71 | #define IGB_MAX_RX_QUEUES_82575 4 | |
72 | #define IGB_MAX_RX_QUEUES_I211 2 | |
73 | #define IGB_MAX_TX_QUEUES 8 | |
74 | #define IGB_MAX_VF_MC_ENTRIES 30 | |
75 | #define IGB_MAX_VF_FUNCTIONS 8 | |
76 | #define IGB_MAX_VFTA_ENTRIES 128 | |
77 | #define IGB_82576_VF_DEV_ID 0x10CA | |
78 | #define IGB_I350_VF_DEV_ID 0x1520 | |
4ae196df | 79 | |
d67974f0 | 80 | /* NVM version defines */ |
b980ac18 JK |
81 | #define IGB_MAJOR_MASK 0xF000 |
82 | #define IGB_MINOR_MASK 0x0FF0 | |
83 | #define IGB_BUILD_MASK 0x000F | |
84 | #define IGB_COMB_VER_MASK 0x00FF | |
85 | #define IGB_MAJOR_SHIFT 12 | |
86 | #define IGB_MINOR_SHIFT 4 | |
87 | #define IGB_COMB_VER_SHFT 8 | |
88 | #define IGB_NVM_VER_INVALID 0xFFFF | |
89 | #define IGB_ETRACK_SHIFT 16 | |
90 | #define NVM_ETRACK_WORD 0x0042 | |
91 | #define NVM_COMB_VER_OFF 0x0083 | |
92 | #define NVM_COMB_VER_PTR 0x003d | |
d67974f0 | 93 | |
4ae196df AD |
94 | struct vf_data_storage { |
95 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
96 | u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; | |
97 | u16 num_vf_mc_hashes; | |
ae641bdc | 98 | u16 vlans_enabled; |
f2ca0dbe AD |
99 | u32 flags; |
100 | unsigned long last_nack; | |
8151d294 WM |
101 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
102 | u16 pf_qos; | |
17dc566c | 103 | u16 tx_rate; |
70ea4783 | 104 | bool spoofchk_enabled; |
4ae196df AD |
105 | }; |
106 | ||
f2ca0dbe | 107 | #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ |
7d5753f0 AD |
108 | #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ |
109 | #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ | |
8151d294 | 110 | #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ |
f2ca0dbe | 111 | |
9d5c8243 AK |
112 | /* RX descriptor control thresholds. |
113 | * PTHRESH - MAC will consider prefetch if it has fewer than this number of | |
114 | * descriptors available in its onboard memory. | |
115 | * Setting this to 0 disables RX descriptor prefetch. | |
116 | * HTHRESH - MAC will only prefetch if there are at least this many descriptors | |
117 | * available in host memory. | |
118 | * If PTHRESH is 0, this should also be 0. | |
119 | * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back | |
120 | * descriptors until either it has this many to write back, or the | |
121 | * ITR timer expires. | |
122 | */ | |
ceb5f13b | 123 | #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) |
b980ac18 | 124 | #define IGB_RX_HTHRESH 8 |
ceb5f13b | 125 | #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) |
b980ac18 JK |
126 | #define IGB_TX_HTHRESH 1 |
127 | #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ | |
cd14ef54 | 128 | (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4) |
b980ac18 | 129 | #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
cd14ef54 | 130 | (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16) |
9d5c8243 AK |
131 | |
132 | /* this is the size past which hardware will drop packets when setting LPE=0 */ | |
133 | #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 | |
134 | ||
135 | /* Supported Rx Buffer Sizes */ | |
de78d1f9 AD |
136 | #define IGB_RXBUFFER_256 256 |
137 | #define IGB_RXBUFFER_2048 2048 | |
138 | #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 | |
139 | #define IGB_RX_BUFSZ IGB_RXBUFFER_2048 | |
9d5c8243 | 140 | |
9d5c8243 | 141 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
b980ac18 | 142 | #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
9d5c8243 | 143 | |
b980ac18 JK |
144 | #define AUTO_ALL_MODES 0 |
145 | #define IGB_EEPROM_APME 0x0400 | |
9d5c8243 AK |
146 | |
147 | #ifndef IGB_MASTER_SLAVE | |
148 | /* Switch to override PHY master/slave setting */ | |
149 | #define IGB_MASTER_SLAVE e1000_ms_hw_default | |
150 | #endif | |
151 | ||
b980ac18 | 152 | #define IGB_MNG_VLAN_NONE -1 |
9d5c8243 | 153 | |
1d9daf45 AD |
154 | enum igb_tx_flags { |
155 | /* cmd_type flags */ | |
156 | IGB_TX_FLAGS_VLAN = 0x01, | |
157 | IGB_TX_FLAGS_TSO = 0x02, | |
158 | IGB_TX_FLAGS_TSTAMP = 0x04, | |
159 | ||
160 | /* olinfo flags */ | |
161 | IGB_TX_FLAGS_IPV4 = 0x10, | |
162 | IGB_TX_FLAGS_CSUM = 0x20, | |
163 | }; | |
164 | ||
165 | /* VLAN info */ | |
b980ac18 | 166 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 |
2bbfebe2 AD |
167 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 |
168 | ||
b980ac18 | 169 | /* The largest size we can write to the descriptor is 65535. In order to |
21ba6fe1 AD |
170 | * maintain a power of two alignment we have to limit ourselves to 32K. |
171 | */ | |
172 | #define IGB_MAX_TXD_PWR 15 | |
173 | #define IGB_MAX_DATA_PER_TXD (1 << IGB_MAX_TXD_PWR) | |
174 | ||
175 | /* Tx Descriptors needed, worst case */ | |
176 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) | |
177 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) | |
178 | ||
f69aa390 AA |
179 | /* EEPROM byte offsets */ |
180 | #define IGB_SFF_8472_SWAP 0x5C | |
181 | #define IGB_SFF_8472_COMP 0x5E | |
182 | ||
183 | /* Bitmasks */ | |
184 | #define IGB_SFF_ADDRESSING_MODE 0x4 | |
185 | #define IGB_SFF_8472_UNSUP 0x00 | |
186 | ||
9d5c8243 | 187 | /* wrapper around a pointer to a socket buffer, |
b980ac18 JK |
188 | * so a DMA handle can be stored along with the buffer |
189 | */ | |
06034649 | 190 | struct igb_tx_buffer { |
8542db05 | 191 | union e1000_adv_tx_desc *next_to_watch; |
06034649 | 192 | unsigned long time_stamp; |
06034649 AD |
193 | struct sk_buff *skb; |
194 | unsigned int bytecount; | |
195 | u16 gso_segs; | |
7af40ad9 | 196 | __be16 protocol; |
9005df38 | 197 | |
c9f14bf3 AD |
198 | DEFINE_DMA_UNMAP_ADDR(dma); |
199 | DEFINE_DMA_UNMAP_LEN(len); | |
ebe42d16 | 200 | u32 tx_flags; |
06034649 AD |
201 | }; |
202 | ||
203 | struct igb_rx_buffer { | |
9d5c8243 | 204 | dma_addr_t dma; |
06034649 | 205 | struct page *page; |
1a1c225b | 206 | unsigned int page_offset; |
9d5c8243 AK |
207 | }; |
208 | ||
8c0ab70a | 209 | struct igb_tx_queue_stats { |
9d5c8243 AK |
210 | u64 packets; |
211 | u64 bytes; | |
04a5fcaa | 212 | u64 restart_queue; |
12dcd86b | 213 | u64 restart_queue2; |
9d5c8243 AK |
214 | }; |
215 | ||
8c0ab70a JDB |
216 | struct igb_rx_queue_stats { |
217 | u64 packets; | |
218 | u64 bytes; | |
219 | u64 drops; | |
04a5fcaa AD |
220 | u64 csum_err; |
221 | u64 alloc_failed; | |
8c0ab70a JDB |
222 | }; |
223 | ||
0ba82994 AD |
224 | struct igb_ring_container { |
225 | struct igb_ring *ring; /* pointer to linked list of rings */ | |
226 | unsigned int total_bytes; /* total bytes processed this int */ | |
227 | unsigned int total_packets; /* total packets processed this int */ | |
228 | u16 work_limit; /* total work allowed per interrupt */ | |
229 | u8 count; /* total number of rings in vector */ | |
230 | u8 itr; /* current ITR setting for ring */ | |
231 | }; | |
232 | ||
047e0030 | 233 | struct igb_ring { |
238ac817 AD |
234 | struct igb_q_vector *q_vector; /* backlink to q_vector */ |
235 | struct net_device *netdev; /* back pointer to net_device */ | |
236 | struct device *dev; /* device pointer for dma mapping */ | |
06034649 AD |
237 | union { /* array of buffer info structs */ |
238 | struct igb_tx_buffer *tx_buffer_info; | |
239 | struct igb_rx_buffer *rx_buffer_info; | |
240 | }; | |
238ac817 AD |
241 | void *desc; /* descriptor ring memory */ |
242 | unsigned long flags; /* ring specific flags */ | |
243 | void __iomem *tail; /* pointer to ring tail register */ | |
5536d210 AD |
244 | dma_addr_t dma; /* phys address of the ring */ |
245 | unsigned int size; /* length of desc. ring in bytes */ | |
238ac817 AD |
246 | |
247 | u16 count; /* number of desc. in the ring */ | |
248 | u8 queue_index; /* logical index of the ring*/ | |
249 | u8 reg_idx; /* physical index of the ring */ | |
238ac817 AD |
250 | |
251 | /* everything past this point are written often */ | |
5536d210 | 252 | u16 next_to_clean; |
9d5c8243 | 253 | u16 next_to_use; |
cbc8e55f | 254 | u16 next_to_alloc; |
9d5c8243 | 255 | |
9d5c8243 AK |
256 | union { |
257 | /* TX */ | |
258 | struct { | |
8c0ab70a | 259 | struct igb_tx_queue_stats tx_stats; |
12dcd86b ED |
260 | struct u64_stats_sync tx_syncp; |
261 | struct u64_stats_sync tx_syncp2; | |
9d5c8243 AK |
262 | }; |
263 | /* RX */ | |
264 | struct { | |
1a1c225b | 265 | struct sk_buff *skb; |
8c0ab70a | 266 | struct igb_rx_queue_stats rx_stats; |
12dcd86b | 267 | struct u64_stats_sync rx_syncp; |
9d5c8243 AK |
268 | }; |
269 | }; | |
5536d210 AD |
270 | } ____cacheline_internodealigned_in_smp; |
271 | ||
272 | struct igb_q_vector { | |
273 | struct igb_adapter *adapter; /* backlink */ | |
274 | int cpu; /* CPU for DCA */ | |
275 | u32 eims_value; /* EIMS mask value */ | |
276 | ||
277 | u16 itr_val; | |
278 | u8 set_itr; | |
279 | void __iomem *itr_register; | |
280 | ||
281 | struct igb_ring_container rx, tx; | |
282 | ||
283 | struct napi_struct napi; | |
284 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
285 | char name[IFNAMSIZ + 9]; | |
286 | ||
287 | /* for dynamic allocation of rings associated with this q_vector */ | |
288 | struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; | |
9d5c8243 AK |
289 | }; |
290 | ||
866cff06 | 291 | enum e1000_ring_flags_t { |
866cff06 | 292 | IGB_RING_FLAG_RX_SCTP_CSUM, |
8be10e91 | 293 | IGB_RING_FLAG_RX_LB_VLAN_BSWAP, |
866cff06 AD |
294 | IGB_RING_FLAG_TX_CTX_IDX, |
295 | IGB_RING_FLAG_TX_DETECT_HANG | |
296 | }; | |
85ad76b2 | 297 | |
e032afc8 | 298 | #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) |
85ad76b2 | 299 | |
b980ac18 | 300 | #define IGB_RX_DESC(R, i) \ |
60136906 | 301 | (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) |
b980ac18 | 302 | #define IGB_TX_DESC(R, i) \ |
60136906 | 303 | (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) |
b980ac18 | 304 | #define IGB_TX_CTXTDESC(R, i) \ |
60136906 | 305 | (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) |
9d5c8243 | 306 | |
3ceb90fd AD |
307 | /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ |
308 | static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, | |
309 | const u32 stat_err_bits) | |
310 | { | |
311 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
312 | } | |
313 | ||
d7ee5b3a AD |
314 | /* igb_desc_unused - calculate if we have unused descriptors */ |
315 | static inline int igb_desc_unused(struct igb_ring *ring) | |
316 | { | |
317 | if (ring->next_to_clean > ring->next_to_use) | |
318 | return ring->next_to_clean - ring->next_to_use - 1; | |
319 | ||
320 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; | |
321 | } | |
322 | ||
e428893b CW |
323 | #ifdef CONFIG_IGB_HWMON |
324 | ||
325 | #define IGB_HWMON_TYPE_LOC 0 | |
326 | #define IGB_HWMON_TYPE_TEMP 1 | |
327 | #define IGB_HWMON_TYPE_CAUTION 2 | |
328 | #define IGB_HWMON_TYPE_MAX 3 | |
329 | ||
330 | struct hwmon_attr { | |
331 | struct device_attribute dev_attr; | |
332 | struct e1000_hw *hw; | |
333 | struct e1000_thermal_diode_data *sensor; | |
334 | char name[12]; | |
335 | }; | |
336 | ||
337 | struct hwmon_buff { | |
e3670b81 GR |
338 | struct attribute_group group; |
339 | const struct attribute_group *groups[2]; | |
340 | struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1]; | |
341 | struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4]; | |
e428893b CW |
342 | unsigned int n_hwmon; |
343 | }; | |
344 | #endif | |
345 | ||
720db4ff RC |
346 | #define IGB_N_EXTTS 2 |
347 | #define IGB_N_PEROUT 2 | |
348 | #define IGB_N_SDP 4 | |
c342b39e LMV |
349 | #define IGB_RETA_SIZE 128 |
350 | ||
9d5c8243 | 351 | /* board specific private data structure */ |
9d5c8243 | 352 | struct igb_adapter { |
b2cb09b1 | 353 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
238ac817 AD |
354 | |
355 | struct net_device *netdev; | |
356 | ||
357 | unsigned long state; | |
358 | unsigned int flags; | |
359 | ||
360 | unsigned int num_q_vectors; | |
cd14ef54 | 361 | struct msix_entry msix_entries[MAX_MSIX_ENTRIES]; |
2e5655e7 | 362 | |
9d5c8243 | 363 | /* Interrupt Throttle Rate */ |
4fc82adf AD |
364 | u32 rx_itr_setting; |
365 | u32 tx_itr_setting; | |
9d5c8243 AK |
366 | u16 tx_itr; |
367 | u16 rx_itr; | |
9d5c8243 | 368 | |
9d5c8243 | 369 | /* TX */ |
13fde97a | 370 | u16 tx_work_limit; |
9d5c8243 | 371 | u32 tx_timeout_count; |
238ac817 AD |
372 | int num_tx_queues; |
373 | struct igb_ring *tx_ring[16]; | |
9d5c8243 AK |
374 | |
375 | /* RX */ | |
9d5c8243 | 376 | int num_rx_queues; |
238ac817 | 377 | struct igb_ring *rx_ring[16]; |
9d5c8243 | 378 | |
9d5c8243 AK |
379 | u32 max_frame_size; |
380 | u32 min_frame_size; | |
381 | ||
238ac817 AD |
382 | struct timer_list watchdog_timer; |
383 | struct timer_list phy_info_timer; | |
384 | ||
385 | u16 mng_vlan_id; | |
386 | u32 bd_number; | |
387 | u32 wol; | |
388 | u32 en_mng_pt; | |
389 | u16 link_speed; | |
390 | u16 link_duplex; | |
391 | ||
392 | struct work_struct reset_task; | |
393 | struct work_struct watchdog_task; | |
394 | bool fc_autoneg; | |
395 | u8 tx_timeout_factor; | |
396 | struct timer_list blink_timer; | |
397 | unsigned long led_status; | |
398 | ||
9d5c8243 | 399 | /* OS defined structs */ |
9d5c8243 | 400 | struct pci_dev *pdev; |
9d5c8243 | 401 | |
12dcd86b ED |
402 | spinlock_t stats64_lock; |
403 | struct rtnl_link_stats64 stats64; | |
404 | ||
9d5c8243 AK |
405 | /* structs defined in e1000_hw.h */ |
406 | struct e1000_hw hw; | |
407 | struct e1000_hw_stats stats; | |
408 | struct e1000_phy_info phy_info; | |
9d5c8243 AK |
409 | |
410 | u32 test_icr; | |
411 | struct igb_ring test_tx_ring; | |
412 | struct igb_ring test_rx_ring; | |
413 | ||
414 | int msg_enable; | |
047e0030 | 415 | |
047e0030 | 416 | struct igb_q_vector *q_vector[MAX_Q_VECTORS]; |
9d5c8243 | 417 | u32 eims_enable_mask; |
844290e5 | 418 | u32 eims_other; |
9d5c8243 AK |
419 | |
420 | /* to not mess up cache alignment, always add to the bottom */ | |
2e5655e7 AD |
421 | u16 tx_ring_count; |
422 | u16 rx_ring_count; | |
1bfaf07b | 423 | unsigned int vfs_allocated_count; |
4ae196df | 424 | struct vf_data_storage *vf_data; |
17dc566c | 425 | int vf_rate_link_speed; |
a99955fc | 426 | u32 rss_queues; |
13800469 | 427 | u32 wvbr; |
1128c756 | 428 | u32 *shadow_vfta; |
d339b133 RC |
429 | |
430 | struct ptp_clock *ptp_clock; | |
a79f4f88 MV |
431 | struct ptp_clock_info ptp_caps; |
432 | struct delayed_work ptp_overflow_work; | |
1f6e8178 MV |
433 | struct work_struct ptp_tx_work; |
434 | struct sk_buff *ptp_tx_skb; | |
6ab5f7b2 | 435 | struct hwtstamp_config tstamp_config; |
428f1f71 | 436 | unsigned long ptp_tx_start; |
fc580751 | 437 | unsigned long last_rx_ptp_check; |
5499a968 | 438 | unsigned long last_rx_timestamp; |
d339b133 RC |
439 | spinlock_t tmreg_lock; |
440 | struct cyclecounter cc; | |
441 | struct timecounter tc; | |
428f1f71 | 442 | u32 tx_hwtstamp_timeouts; |
fc580751 | 443 | u32 rx_hwtstamp_cleared; |
3c89f6d0 | 444 | |
720db4ff RC |
445 | struct ptp_pin_desc sdp_config[IGB_N_SDP]; |
446 | struct { | |
447 | struct timespec start; | |
448 | struct timespec period; | |
449 | } perout[IGB_N_PEROUT]; | |
450 | ||
d67974f0 | 451 | char fw_version[32]; |
e428893b | 452 | #ifdef CONFIG_IGB_HWMON |
e3670b81 | 453 | struct hwmon_buff *igb_hwmon_buff; |
e428893b CW |
454 | bool ets; |
455 | #endif | |
441fc6fd CW |
456 | struct i2c_algo_bit_data i2c_algo; |
457 | struct i2c_adapter i2c_adap; | |
603e86fa | 458 | struct i2c_client *i2c_client; |
ed12cc9a LMV |
459 | u32 rss_indir_tbl_init; |
460 | u8 rss_indir_tbl[IGB_RETA_SIZE]; | |
aa9b8cc4 AA |
461 | |
462 | unsigned long link_check_timeout; | |
56cec249 CW |
463 | int copper_tries; |
464 | struct e1000_info ei; | |
f4c01e96 | 465 | u16 eee_advert; |
9d5c8243 AK |
466 | }; |
467 | ||
039454a8 AA |
468 | #define IGB_FLAG_HAS_MSI (1 << 0) |
469 | #define IGB_FLAG_DCA_ENABLED (1 << 1) | |
470 | #define IGB_FLAG_QUAD_PORT_A (1 << 2) | |
471 | #define IGB_FLAG_QUEUE_PAIRS (1 << 3) | |
472 | #define IGB_FLAG_DMAC (1 << 4) | |
473 | #define IGB_FLAG_PTP (1 << 5) | |
474 | #define IGB_FLAG_RSS_FIELD_IPV4_UDP (1 << 6) | |
475 | #define IGB_FLAG_RSS_FIELD_IPV6_UDP (1 << 7) | |
63d4a8f9 | 476 | #define IGB_FLAG_WOL_SUPPORTED (1 << 8) |
aa9b8cc4 | 477 | #define IGB_FLAG_NEED_LINK_UPDATE (1 << 9) |
2bdfc4e2 | 478 | #define IGB_FLAG_MEDIA_RESET (1 << 10) |
56cec249 CW |
479 | #define IGB_FLAG_MAS_CAPABLE (1 << 11) |
480 | #define IGB_FLAG_MAS_ENABLE (1 << 12) | |
cd14ef54 | 481 | #define IGB_FLAG_HAS_MSIX (1 << 13) |
f4c01e96 | 482 | #define IGB_FLAG_EEE (1 << 14) |
56cec249 CW |
483 | |
484 | /* Media Auto Sense */ | |
485 | #define IGB_MAS_ENABLE_0 0X0001 | |
486 | #define IGB_MAS_ENABLE_1 0X0002 | |
487 | #define IGB_MAS_ENABLE_2 0X0004 | |
488 | #define IGB_MAS_ENABLE_3 0X0008 | |
831ec0b4 CW |
489 | |
490 | /* DMA Coalescing defines */ | |
b980ac18 JK |
491 | #define IGB_MIN_TXPBSIZE 20408 |
492 | #define IGB_TX_BUF_4096 4096 | |
493 | #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ | |
7dfc16fa | 494 | |
b980ac18 JK |
495 | #define IGB_82576_TSYNC_SHIFT 19 |
496 | #define IGB_TS_HDR_LEN 16 | |
9d5c8243 AK |
497 | enum e1000_state_t { |
498 | __IGB_TESTING, | |
499 | __IGB_RESETTING, | |
ed4420a3 JK |
500 | __IGB_DOWN, |
501 | __IGB_PTP_TX_IN_PROGRESS, | |
9d5c8243 AK |
502 | }; |
503 | ||
504 | enum igb_boards { | |
505 | board_82575, | |
506 | }; | |
507 | ||
508 | extern char igb_driver_name[]; | |
509 | extern char igb_driver_version[]; | |
510 | ||
5ccc921a JP |
511 | int igb_up(struct igb_adapter *); |
512 | void igb_down(struct igb_adapter *); | |
513 | void igb_reinit_locked(struct igb_adapter *); | |
514 | void igb_reset(struct igb_adapter *); | |
907b7835 | 515 | int igb_reinit_queues(struct igb_adapter *); |
5ccc921a JP |
516 | void igb_write_rss_indir_tbl(struct igb_adapter *); |
517 | int igb_set_spd_dplx(struct igb_adapter *, u32, u8); | |
518 | int igb_setup_tx_resources(struct igb_ring *); | |
519 | int igb_setup_rx_resources(struct igb_ring *); | |
520 | void igb_free_tx_resources(struct igb_ring *); | |
521 | void igb_free_rx_resources(struct igb_ring *); | |
522 | void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); | |
523 | void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); | |
524 | void igb_setup_tctl(struct igb_adapter *); | |
525 | void igb_setup_rctl(struct igb_adapter *); | |
526 | netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); | |
527 | void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *); | |
528 | void igb_alloc_rx_buffers(struct igb_ring *, u16); | |
529 | void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); | |
530 | bool igb_has_link(struct igb_adapter *adapter); | |
531 | void igb_set_ethtool_ops(struct net_device *); | |
532 | void igb_power_up_link(struct igb_adapter *); | |
533 | void igb_set_fw_version(struct igb_adapter *); | |
534 | void igb_ptp_init(struct igb_adapter *adapter); | |
535 | void igb_ptp_stop(struct igb_adapter *adapter); | |
536 | void igb_ptp_reset(struct igb_adapter *adapter); | |
5ccc921a | 537 | void igb_ptp_rx_hang(struct igb_adapter *adapter); |
5ccc921a JP |
538 | void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb); |
539 | void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va, | |
540 | struct sk_buff *skb); | |
6ab5f7b2 JK |
541 | int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); |
542 | int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); | |
e428893b | 543 | #ifdef CONFIG_IGB_HWMON |
5ccc921a JP |
544 | void igb_sysfs_exit(struct igb_adapter *adapter); |
545 | int igb_sysfs_init(struct igb_adapter *adapter); | |
e428893b | 546 | #endif |
f5f4cf08 AD |
547 | static inline s32 igb_reset_phy(struct e1000_hw *hw) |
548 | { | |
a8d2a0c2 AD |
549 | if (hw->phy.ops.reset) |
550 | return hw->phy.ops.reset(hw); | |
f5f4cf08 AD |
551 | |
552 | return 0; | |
553 | } | |
554 | ||
555 | static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
556 | { | |
a8d2a0c2 AD |
557 | if (hw->phy.ops.read_reg) |
558 | return hw->phy.ops.read_reg(hw, offset, data); | |
f5f4cf08 AD |
559 | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
564 | { | |
a8d2a0c2 AD |
565 | if (hw->phy.ops.write_reg) |
566 | return hw->phy.ops.write_reg(hw, offset, data); | |
f5f4cf08 AD |
567 | |
568 | return 0; | |
569 | } | |
570 | ||
571 | static inline s32 igb_get_phy_info(struct e1000_hw *hw) | |
572 | { | |
573 | if (hw->phy.ops.get_phy_info) | |
574 | return hw->phy.ops.get_phy_info(hw); | |
575 | ||
576 | return 0; | |
577 | } | |
578 | ||
bdbc0631 ED |
579 | static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) |
580 | { | |
581 | return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); | |
582 | } | |
583 | ||
9d5c8243 | 584 | #endif /* _IGB_H_ */ |