[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2011 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
                                           (hw->mac.type > e1000_82575 ? 8 : 4))
#define IGB_MAX_TX_QUEUES                  16

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	u32 flags;
	unsigned long last_nack;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
	u16 tx_rate;
};

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                     8
#define IGB_RX_HTHRESH                     8
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 4)
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_512   512
#define IGB_RXBUFFER_16384 16384
#define IGB_RX_HDR_LEN     IGB_RXBUFFER_512

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	union {
		/* TX */
		struct {
			unsigned long time_stamp;
			u16 length;
			u16 next_to_watch;
			unsigned int bytecount;
			u16 gso_segs;
			u8 tx_flags;
			u8 mapped_as_page;
		};
		/* RX */
		struct {
			struct page *page;
			dma_addr_t page_dma;
			u16 page_offset;
		};
	};
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 restart_queue2;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_q_vector {
	struct igb_adapter *adapter; /* backlink */
	struct igb_ring *rx_ring;
	struct igb_ring *tx_ring;
	struct napi_struct napi;

	u32 eims_value;
	u16 cpu;

	u16 itr_val;
	u8 set_itr;
	void __iomem *itr_register;

	char name[IFNAMSIZ + 9];
};

struct igb_ring {
	struct igb_q_vector *q_vector;	/* backlink to q_vector */
	struct net_device *netdev;	/* back pointer to net_device */
	struct device *dev;		/* device pointer for dma mapping */
	struct igb_buffer *buffer_info;	/* array of buffer info structs */
	void *desc;			/* descriptor ring memory */
	unsigned long flags;		/* ring specific flags */
	void __iomem *tail;		/* pointer to ring tail register */

	u16 count;			/* number of desc. in the ring */
	u8 queue_index;			/* logical index of the ring*/
	u8 reg_idx;			/* physical index of the ring */
	u32 size;			/* length of desc. ring in bytes */

	/* everything past this point are written often */
	u16 next_to_clean ____cacheline_aligned_in_smp;
	u16 next_to_use;

	unsigned int total_bytes;
	unsigned int total_packets;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			struct u64_stats_sync tx_syncp;
			struct u64_stats_sync tx_syncp2;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			struct u64_stats_sync rx_syncp;
		};
	};
	/* Items past this point are only used during ring alloc / free */
	dma_addr_t dma;                /* phys address of the ring */
};

#define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
#define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */

#define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */

#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS)

#define IGB_RX_DESC(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
#define IGB_TX_DESC(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
#define IGB_TX_CTXTDESC(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))

/* igb_desc_unused - calculate if we have unused descriptors */
static inline int igb_desc_unused(struct igb_ring *ring)
{
	if (ring->next_to_clean > ring->next_to_use)
		return ring->next_to_clean - ring->next_to_use - 1;

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
}

/* board specific private data structure */
struct igb_adapter {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

	struct net_device *netdev;

	unsigned long state;
	unsigned int flags;

	unsigned int num_q_vectors;
	struct msix_entry *msix_entries;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	/* TX */
	u32 tx_timeout_count;
	int num_tx_queues;
	struct igb_ring *tx_ring[16];

	/* RX */
	int num_rx_queues;
	struct igb_ring *rx_ring[16];

	u32 max_frame_size;
	u32 min_frame_size;

	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;

	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* OS defined structs */
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	spinlock_t stats64_lock;
	struct rtnl_link_stats64 stats64;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	u32 eeprom_wol;

	u16 tx_ring_count;
	u16 rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
	int vf_rate_link_speed;
	u32 rss_queues;
	u32 wvbr;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
#define IGB_FLAG_DMAC              (1 << 4)

/* DMA Coalescing defines */
#define IGB_MIN_TXPBSIZE           20408
#define IGB_TX_BUF_4096            4096
#define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */

#define IGB_82576_TSYNC_SHIFT 19
#define IGB_82580_TSYNC_SHIFT 24
#define IGB_TS_HDR_LEN        16
enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_setup_tctl(struct igb_adapter *);
extern void igb_setup_rctl(struct igb_adapter *);
extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
					   struct igb_buffer *);
extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
extern bool igb_has_link(struct igb_adapter *adapter);
extern void igb_set_ethtool_ops(struct net_device *);
extern void igb_power_up_link(struct igb_adapter *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
4297f99b	4	Copyright(c) 2007-2011 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
b2cb09b1 JP	40	#include <linux/bitops.h>
b2cb09b1 JP	41	#include <linux/if_vlan.h>
38c845c7	42
9d5c8243 AK	43	struct igb_adapter;
9d5c8243 AK	44
6eb5a7f1 AD	45	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	46	#define IGB_START_ITR 648
9d5c8243	47
9d5c8243 AK	48	/* TX/RX descriptor defines */
	49	#define IGB_DEFAULT_TXD 256
	50	#define IGB_MIN_TXD 80
	51	#define IGB_MAX_TXD 4096
	52
	53	#define IGB_DEFAULT_RXD 256
	54	#define IGB_MIN_RXD 80
	55	#define IGB_MAX_RXD 4096
	56
	57	#define IGB_DEFAULT_ITR 3 /* dynamic */
	58	#define IGB_MAX_ITR_USECS 10000
	59	#define IGB_MIN_ITR_USECS 10
047e0030 AD	60	#define NON_Q_VECTORS 1
047e0030 AD	61	#define MAX_Q_VECTORS 8
9d5c8243 AK	62
9d5c8243 AK	63	/* Transmit and receive queues */
a99955fc AD	64	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
a99955fc AD	65	(hw->mac.type > e1000_82575 ? 8 : 4))
1cc3bd87	66	#define IGB_MAX_TX_QUEUES 16
9d5c8243	67
4ae196df AD	68	#define IGB_MAX_VF_MC_ENTRIES 30
	69	#define IGB_MAX_VF_FUNCTIONS 8
	70	#define IGB_MAX_VFTA_ENTRIES 128
	71
	72	struct vf_data_storage {
	73	unsigned char vf_mac_addresses[ETH_ALEN];
	74	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	75	u16 num_vf_mc_hashes;
ae641bdc	76	u16 vlans_enabled;
f2ca0dbe AD	77	u32 flags;
f2ca0dbe AD	78	unsigned long last_nack;
8151d294 WM	79	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
8151d294 WM	80	u16 pf_qos;
17dc566c	81	u16 tx_rate;
4ae196df AD	82	};
4ae196df AD	83
f2ca0dbe	84	#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
7d5753f0 AD	85	#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
7d5753f0 AD	86	#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
8151d294	87	#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
f2ca0dbe	88
9d5c8243 AK	89	/* RX descriptor control thresholds.
	90	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	91	* descriptors available in its onboard memory.
	92	* Setting this to 0 disables RX descriptor prefetch.
	93	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	94	* available in host memory.
	95	* If PTHRESH is 0, this should also be 0.
	96	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	97	* descriptors until either it has this many to write back, or the
	98	* ITR timer expires.
	99	*/
58fd62f5	100	#define IGB_RX_PTHRESH 8
9d5c8243	101	#define IGB_RX_HTHRESH 8
85b430b4 AD	102	#define IGB_TX_PTHRESH 8
85b430b4 AD	103	#define IGB_TX_HTHRESH 1
a74420e0 AD	104	#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0 AD	105	adapter->msix_entries) ? 1 : 4)
85b430b4	106	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0	107	adapter->msix_entries) ? 1 : 16)
9d5c8243 AK	108
	109	/* this is the size past which hardware will drop packets when setting LPE=0 */
	110	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	111
	112	/* Supported Rx Buffer Sizes */
44390ca6	113	#define IGB_RXBUFFER_512 512
9d5c8243	114	#define IGB_RXBUFFER_16384 16384
44390ca6	115	#define IGB_RX_HDR_LEN IGB_RXBUFFER_512
9d5c8243	116
9d5c8243 AK	117	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	118	#define IGB_TX_QUEUE_WAKE 16
	119	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	120	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	121
	122	#define AUTO_ALL_MODES 0
	123	#define IGB_EEPROM_APME 0x0400
	124
	125	#ifndef IGB_MASTER_SLAVE
	126	/* Switch to override PHY master/slave setting */
	127	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	128	#endif
	129
	130	#define IGB_MNG_VLAN_NONE -1
	131
	132	/* wrapper around a pointer to a socket buffer,
	133	* so a DMA handle can be stored along with the buffer */
	134	struct igb_buffer {
	135	struct sk_buff *skb;
	136	dma_addr_t dma;
	137	union {
	138	/* TX */
	139	struct {
	140	unsigned long time_stamp;
0e014cb1 AD	141	u16 length;
0e014cb1 AD	142	u16 next_to_watch;
2873957d	143	unsigned int bytecount;
40e90c26	144	u16 gso_segs;
2244d07b	145	u8 tx_flags;
2873957d	146	u8 mapped_as_page;
9d5c8243 AK	147	};
	148	/* RX */
	149	struct {
	150	struct page *page;
6366ad33 AD	151	dma_addr_t page_dma;
6366ad33 AD	152	u16 page_offset;
9d5c8243 AK	153	};
	154	};
	155	};
	156
8c0ab70a	157	struct igb_tx_queue_stats {
9d5c8243 AK	158	u64 packets;
9d5c8243 AK	159	u64 bytes;
04a5fcaa	160	u64 restart_queue;
12dcd86b	161	u64 restart_queue2;
9d5c8243 AK	162	};
9d5c8243 AK	163
8c0ab70a JDB	164	struct igb_rx_queue_stats {
	165	u64 packets;
	166	u64 bytes;
	167	u64 drops;
04a5fcaa AD	168	u64 csum_err;
04a5fcaa AD	169	u64 alloc_failed;
8c0ab70a JDB	170	};
8c0ab70a JDB	171
047e0030	172	struct igb_q_vector {
9d5c8243	173	struct igb_adapter adapter; / backlink */
047e0030 AD	174	struct igb_ring *rx_ring;
	175	struct igb_ring *tx_ring;
	176	struct napi_struct napi;
	177
	178	u32 eims_value;
	179	u16 cpu;
	180
	181	u16 itr_val;
	182	u8 set_itr;
047e0030 AD	183	void __iomem *itr_register;
	184
	185	char name[IFNAMSIZ + 9];
	186	};
	187
	188	struct igb_ring {
238ac817 AD	189	struct igb_q_vector q_vector; / backlink to q_vector */
	190	struct net_device netdev; / back pointer to net_device */
	191	struct device dev; / device pointer for dma mapping */
	192	struct igb_buffer buffer_info; / array of buffer info structs */
	193	void desc; / descriptor ring memory */
	194	unsigned long flags; /* ring specific flags */
	195	void __iomem tail; / pointer to ring tail register */
	196
	197	u16 count; /* number of desc. in the ring */
	198	u8 queue_index; /* logical index of the ring*/
	199	u8 reg_idx; /* physical index of the ring */
	200	u32 size; /* length of desc. ring in bytes */
	201
	202	/* everything past this point are written often */
	203	u16 next_to_clean ____cacheline_aligned_in_smp;
9d5c8243	204	u16 next_to_use;
9d5c8243	205
9d5c8243 AK	206	unsigned int total_bytes;
	207	unsigned int total_packets;
	208
	209	union {
	210	/* TX */
	211	struct {
8c0ab70a	212	struct igb_tx_queue_stats tx_stats;
12dcd86b ED	213	struct u64_stats_sync tx_syncp;
12dcd86b ED	214	struct u64_stats_sync tx_syncp2;
9d5c8243 AK	215	bool detect_tx_hung;
	216	};
	217	/* RX */
	218	struct {
8c0ab70a	219	struct igb_rx_queue_stats rx_stats;
12dcd86b	220	struct u64_stats_sync rx_syncp;
9d5c8243 AK	221	};
9d5c8243 AK	222	};
238ac817 AD	223	/* Items past this point are only used during ring alloc / free */
238ac817 AD	224	dma_addr_t dma; /* phys address of the ring */
9d5c8243 AK	225	};
9d5c8243 AK	226
85ad76b2 AD	227	#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
	228	#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
	229
	230	#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
	231
	232	#define IGB_ADVTXD_DCMD (E1000_TXD_CMD_EOP \| E1000_TXD_CMD_RS)
	233
60136906 AD	234	#define IGB_RX_DESC(R, i) \
	235	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
	236	#define IGB_TX_DESC(R, i) \
	237	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
	238	#define IGB_TX_CTXTDESC(R, i) \
	239	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
9d5c8243	240
d7ee5b3a AD	241	/* igb_desc_unused - calculate if we have unused descriptors */
	242	static inline int igb_desc_unused(struct igb_ring *ring)
	243	{
	244	if (ring->next_to_clean > ring->next_to_use)
	245	return ring->next_to_clean - ring->next_to_use - 1;
	246
	247	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
	248	}
	249
9d5c8243	250	/* board specific private data structure */
9d5c8243	251	struct igb_adapter {
b2cb09b1	252	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
238ac817 AD	253
	254	struct net_device *netdev;
	255
	256	unsigned long state;
	257	unsigned int flags;
	258
	259	unsigned int num_q_vectors;
	260	struct msix_entry *msix_entries;
2e5655e7	261
9d5c8243	262	/* Interrupt Throttle Rate */
4fc82adf AD	263	u32 rx_itr_setting;
4fc82adf AD	264	u32 tx_itr_setting;
9d5c8243 AK	265	u16 tx_itr;
9d5c8243 AK	266	u16 rx_itr;
9d5c8243	267
9d5c8243	268	/* TX */
9d5c8243	269	u32 tx_timeout_count;
238ac817 AD	270	int num_tx_queues;
238ac817 AD	271	struct igb_ring *tx_ring[16];
9d5c8243 AK	272
9d5c8243 AK	273	/* RX */
9d5c8243	274	int num_rx_queues;
238ac817	275	struct igb_ring *rx_ring[16];
9d5c8243	276
9d5c8243 AK	277	u32 max_frame_size;
	278	u32 min_frame_size;
	279
238ac817 AD	280	struct timer_list watchdog_timer;
	281	struct timer_list phy_info_timer;
	282
	283	u16 mng_vlan_id;
	284	u32 bd_number;
	285	u32 wol;
	286	u32 en_mng_pt;
	287	u16 link_speed;
	288	u16 link_duplex;
	289
	290	struct work_struct reset_task;
	291	struct work_struct watchdog_task;
	292	bool fc_autoneg;
	293	u8 tx_timeout_factor;
	294	struct timer_list blink_timer;
	295	unsigned long led_status;
	296
9d5c8243	297	/* OS defined structs */
9d5c8243	298	struct pci_dev *pdev;
38c845c7 PO	299	struct cyclecounter cycles;
38c845c7 PO	300	struct timecounter clock;
33af6bcc PO	301	struct timecompare compare;
33af6bcc PO	302	struct hwtstamp_config hwtstamp_config;
9d5c8243	303
12dcd86b ED	304	spinlock_t stats64_lock;
	305	struct rtnl_link_stats64 stats64;
	306
9d5c8243 AK	307	/* structs defined in e1000_hw.h */
	308	struct e1000_hw hw;
	309	struct e1000_hw_stats stats;
	310	struct e1000_phy_info phy_info;
	311	struct e1000_phy_stats phy_stats;
	312
	313	u32 test_icr;
	314	struct igb_ring test_tx_ring;
	315	struct igb_ring test_rx_ring;
	316
	317	int msg_enable;
047e0030	318
047e0030	319	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243	320	u32 eims_enable_mask;
844290e5	321	u32 eims_other;
9d5c8243 AK	322
9d5c8243 AK	323	/* to not mess up cache alignment, always add to the bottom */
9d5c8243	324	u32 eeprom_wol;
42bfd33a	325
2e5655e7 AD	326	u16 tx_ring_count;
2e5655e7 AD	327	u16 rx_ring_count;
1bfaf07b	328	unsigned int vfs_allocated_count;
4ae196df	329	struct vf_data_storage *vf_data;
17dc566c	330	int vf_rate_link_speed;
a99955fc	331	u32 rss_queues;
13800469	332	u32 wvbr;
9d5c8243 AK	333	};
9d5c8243 AK	334
7dfc16fa	335	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	336	#define IGB_FLAG_DCA_ENABLED (1 << 1)
cbd347ad AD	337	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
4fc82adf	338	#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
831ec0b4 CW	339	#define IGB_FLAG_DMAC (1 << 4)
	340
	341	/* DMA Coalescing defines */
	342	#define IGB_MIN_TXPBSIZE 20408
	343	#define IGB_TX_BUF_4096 4096
	344	#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
7dfc16fa	345
c5b9bd5e	346	#define IGB_82576_TSYNC_SHIFT 19
55cac248	347	#define IGB_82580_TSYNC_SHIFT 24
757b77e2	348	#define IGB_TS_HDR_LEN 16
9d5c8243 AK	349	enum e1000_state_t {
	350	__IGB_TESTING,
	351	__IGB_RESETTING,
	352	__IGB_DOWN
	353	};
	354
	355	enum igb_boards {
	356	board_82575,
	357	};
	358
	359	extern char igb_driver_name[];
	360	extern char igb_driver_version[];
	361
9d5c8243 AK	362	extern int igb_up(struct igb_adapter *);
	363	extern void igb_down(struct igb_adapter *);
	364	extern void igb_reinit_locked(struct igb_adapter *);
	365	extern void igb_reset(struct igb_adapter *);
14ad2513	366	extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
80785298 AD	367	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	368	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	369	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	370	extern void igb_free_rx_resources(struct igb_ring *);
d7ee5b3a AD	371	extern void igb_configure_tx_ring(struct igb_adapter , struct igb_ring );
	372	extern void igb_configure_rx_ring(struct igb_adapter , struct igb_ring );
	373	extern void igb_setup_tctl(struct igb_adapter *);
	374	extern void igb_setup_rctl(struct igb_adapter *);
cd392f5c	375	extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff , struct igb_ring );
b1a436c3 AD	376	extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
b1a436c3 AD	377	struct igb_buffer *);
cd392f5c	378	extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
12dcd86b	379	extern void igb_update_stats(struct igb_adapter , struct rtnl_link_stats64 );
3145535a	380	extern bool igb_has_link(struct igb_adapter *adapter);
9d5c8243	381	extern void igb_set_ethtool_ops(struct net_device *);
88a268c1	382	extern void igb_power_up_link(struct igb_adapter *);
9d5c8243	383
f5f4cf08 AD	384	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	385	{
a8d2a0c2 AD	386	if (hw->phy.ops.reset)
a8d2a0c2 AD	387	return hw->phy.ops.reset(hw);
f5f4cf08 AD	388
	389	return 0;
	390	}
	391
	392	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	393	{
a8d2a0c2 AD	394	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	395	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	396
	397	return 0;
	398	}
	399
	400	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	401	{
a8d2a0c2 AD	402	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	403	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	404
	405	return 0;
	406	}
	407
	408	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	409	{
	410	if (hw->phy.ops.get_phy_info)
	411	return hw->phy.ops.get_phy_info(hw);
	412
	413	return 0;
	414	}
	415
9d5c8243	416	#endif /* _IGB_H_ */