[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb.h

/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
  Copyright(c) 2007-2011 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


/* Linux PRO/1000 Ethernet Driver main header file */

#ifndef _IGB_H_
#define _IGB_H_

#include "e1000_mac.h"
#include "e1000_82575.h"

#include <linux/clocksource.h>
#include <linux/timecompare.h>
#include <linux/net_tstamp.h>
#include <linux/bitops.h>
#include <linux/if_vlan.h>

struct igb_adapter;

/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
#define IGB_START_ITR 648

/* TX/RX descriptor defines */
#define IGB_DEFAULT_TXD                  256
#define IGB_DEFAULT_TX_WORK		 128
#define IGB_MIN_TXD                       80
#define IGB_MAX_TXD                     4096

#define IGB_DEFAULT_RXD                  256
#define IGB_MIN_RXD                       80
#define IGB_MAX_RXD                     4096

#define IGB_DEFAULT_ITR                    3 /* dynamic */
#define IGB_MAX_ITR_USECS              10000
#define IGB_MIN_ITR_USECS                 10
#define NON_Q_VECTORS                      1
#define MAX_Q_VECTORS                      8

/* Transmit and receive queues */
#define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
                                           (hw->mac.type > e1000_82575 ? 8 : 4))
#define IGB_MAX_TX_QUEUES                  16

#define IGB_MAX_VF_MC_ENTRIES              30
#define IGB_MAX_VF_FUNCTIONS               8
#define IGB_MAX_VFTA_ENTRIES               128

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 vlans_enabled;
	u32 flags;
	unsigned long last_nack;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
	u16 tx_rate;
};

#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC     0x00000008 /* PF has set MAC address */

/* RX descriptor control thresholds.
 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
 *           descriptors available in its onboard memory.
 *           Setting this to 0 disables RX descriptor prefetch.
 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
 *           available in host memory.
 *           If PTHRESH is 0, this should also be 0.
 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
 *           descriptors until either it has this many to write back, or the
 *           ITR timer expires.
 */
#define IGB_RX_PTHRESH                     8
#define IGB_RX_HTHRESH                     8
#define IGB_TX_PTHRESH                     8
#define IGB_TX_HTHRESH                     1
#define IGB_RX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 4)
#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
					     adapter->msix_entries) ? 1 : 16)

/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522

/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_512   512
#define IGB_RXBUFFER_16384 16384
#define IGB_RX_HDR_LEN     IGB_RXBUFFER_512

/* How many Tx Descriptors do we need to call netif_wake_queue ? */
#define IGB_TX_QUEUE_WAKE	16
/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define AUTO_ALL_MODES            0
#define IGB_EEPROM_APME         0x0400

#ifndef IGB_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define IGB_MASTER_SLAVE	e1000_ms_hw_default
#endif

#define IGB_MNG_VLAN_NONE -1

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct igb_tx_buffer {
	union e1000_adv_tx_desc *next_to_watch;
	unsigned long time_stamp;
	dma_addr_t dma;
	u32 length;
	u32 tx_flags;
	struct sk_buff *skb;
	unsigned int bytecount;
	u16 gso_segs;
	u8 mapped_as_page;
};

struct igb_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	u32 page_offset;
};

struct igb_tx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 restart_queue;
	u64 restart_queue2;
};

struct igb_rx_queue_stats {
	u64 packets;
	u64 bytes;
	u64 drops;
	u64 csum_err;
	u64 alloc_failed;
};

struct igb_q_vector {
	struct igb_adapter *adapter; /* backlink */
	struct igb_ring *rx_ring;
	struct igb_ring *tx_ring;
	struct napi_struct napi;

	u32 eims_value;
	u16 cpu;
	u16 tx_work_limit;

	u16 itr_val;
	u8 set_itr;
	void __iomem *itr_register;

	char name[IFNAMSIZ + 9];
};

struct igb_ring {
	struct igb_q_vector *q_vector;	/* backlink to q_vector */
	struct net_device *netdev;	/* back pointer to net_device */
	struct device *dev;		/* device pointer for dma mapping */
	union {				/* array of buffer info structs */
		struct igb_tx_buffer *tx_buffer_info;
		struct igb_rx_buffer *rx_buffer_info;
	};
	void *desc;			/* descriptor ring memory */
	unsigned long flags;		/* ring specific flags */
	void __iomem *tail;		/* pointer to ring tail register */

	u16 count;			/* number of desc. in the ring */
	u8 queue_index;			/* logical index of the ring*/
	u8 reg_idx;			/* physical index of the ring */
	u32 size;			/* length of desc. ring in bytes */

	/* everything past this point are written often */
	u16 next_to_clean ____cacheline_aligned_in_smp;
	u16 next_to_use;

	unsigned int total_bytes;
	unsigned int total_packets;

	union {
		/* TX */
		struct {
			struct igb_tx_queue_stats tx_stats;
			struct u64_stats_sync tx_syncp;
			struct u64_stats_sync tx_syncp2;
			bool detect_tx_hung;
		};
		/* RX */
		struct {
			struct igb_rx_queue_stats rx_stats;
			struct u64_stats_sync rx_syncp;
		};
	};
	/* Items past this point are only used during ring alloc / free */
	dma_addr_t dma;                /* phys address of the ring */
};

#define IGB_RING_FLAG_RX_CSUM        0x00000001 /* RX CSUM enabled */
#define IGB_RING_FLAG_RX_SCTP_CSUM   0x00000002 /* SCTP CSUM offload enabled */

#define IGB_RING_FLAG_TX_CTX_IDX     0x00000001 /* HW requires context index */

#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)

#define IGB_RX_DESC(R, i)	    \
	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
#define IGB_TX_DESC(R, i)	    \
	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
#define IGB_TX_CTXTDESC(R, i)	    \
	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))

/* igb_desc_unused - calculate if we have unused descriptors */
static inline int igb_desc_unused(struct igb_ring *ring)
{
	if (ring->next_to_clean > ring->next_to_use)
		return ring->next_to_clean - ring->next_to_use - 1;

	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
}

/* board specific private data structure */
struct igb_adapter {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

	struct net_device *netdev;

	unsigned long state;
	unsigned int flags;

	unsigned int num_q_vectors;
	struct msix_entry *msix_entries;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 tx_itr;
	u16 rx_itr;

	/* TX */
	u16 tx_work_limit;
	u32 tx_timeout_count;
	int num_tx_queues;
	struct igb_ring *tx_ring[16];

	/* RX */
	int num_rx_queues;
	struct igb_ring *rx_ring[16];

	u32 max_frame_size;
	u32 min_frame_size;

	struct timer_list watchdog_timer;
	struct timer_list phy_info_timer;

	u16 mng_vlan_id;
	u32 bd_number;
	u32 wol;
	u32 en_mng_pt;
	u16 link_speed;
	u16 link_duplex;

	struct work_struct reset_task;
	struct work_struct watchdog_task;
	bool fc_autoneg;
	u8  tx_timeout_factor;
	struct timer_list blink_timer;
	unsigned long led_status;

	/* OS defined structs */
	struct pci_dev *pdev;
	struct cyclecounter cycles;
	struct timecounter clock;
	struct timecompare compare;
	struct hwtstamp_config hwtstamp_config;

	spinlock_t stats64_lock;
	struct rtnl_link_stats64 stats64;

	/* structs defined in e1000_hw.h */
	struct e1000_hw hw;
	struct e1000_hw_stats stats;
	struct e1000_phy_info phy_info;
	struct e1000_phy_stats phy_stats;

	u32 test_icr;
	struct igb_ring test_tx_ring;
	struct igb_ring test_rx_ring;

	int msg_enable;

	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
	u32 eims_enable_mask;
	u32 eims_other;

	/* to not mess up cache alignment, always add to the bottom */
	u32 eeprom_wol;

	u16 tx_ring_count;
	u16 rx_ring_count;
	unsigned int vfs_allocated_count;
	struct vf_data_storage *vf_data;
	int vf_rate_link_speed;
	u32 rss_queues;
	u32 wvbr;
};

#define IGB_FLAG_HAS_MSI           (1 << 0)
#define IGB_FLAG_DCA_ENABLED       (1 << 1)
#define IGB_FLAG_QUAD_PORT_A       (1 << 2)
#define IGB_FLAG_QUEUE_PAIRS       (1 << 3)
#define IGB_FLAG_DMAC              (1 << 4)

/* DMA Coalescing defines */
#define IGB_MIN_TXPBSIZE           20408
#define IGB_TX_BUF_4096            4096
#define IGB_DMCTLX_DCFLUSH_DIS     0x80000000  /* Disable DMA Coal Flush */

#define IGB_82576_TSYNC_SHIFT 19
#define IGB_82580_TSYNC_SHIFT 24
#define IGB_TS_HDR_LEN        16
enum e1000_state_t {
	__IGB_TESTING,
	__IGB_RESETTING,
	__IGB_DOWN
};

enum igb_boards {
	board_82575,
};

extern char igb_driver_name[];
extern char igb_driver_version[];

extern int igb_up(struct igb_adapter *);
extern void igb_down(struct igb_adapter *);
extern void igb_reinit_locked(struct igb_adapter *);
extern void igb_reset(struct igb_adapter *);
extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
extern int igb_setup_tx_resources(struct igb_ring *);
extern int igb_setup_rx_resources(struct igb_ring *);
extern void igb_free_tx_resources(struct igb_ring *);
extern void igb_free_rx_resources(struct igb_ring *);
extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
extern void igb_setup_tctl(struct igb_adapter *);
extern void igb_setup_rctl(struct igb_adapter *);
extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
					   struct igb_tx_buffer *);
extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
extern bool igb_has_link(struct igb_adapter *adapter);
extern void igb_set_ethtool_ops(struct net_device *);
extern void igb_power_up_link(struct igb_adapter *);

static inline s32 igb_reset_phy(struct e1000_hw *hw)
{
	if (hw->phy.ops.reset)
		return hw->phy.ops.reset(hw);

	return 0;
}

static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
{
	if (hw->phy.ops.read_reg)
		return hw->phy.ops.read_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
{
	if (hw->phy.ops.write_reg)
		return hw->phy.ops.write_reg(hw, offset, data);

	return 0;
}

static inline s32 igb_get_phy_info(struct e1000_hw *hw)
{
	if (hw->phy.ops.get_phy_info)
		return hw->phy.ops.get_phy_info(hw);

	return 0;
}

#endif /* _IGB_H_ */
Commit	Line	Data
9d5c8243 AK	1	/*******************************************************************************
	2
	3	Intel(R) Gigabit Ethernet Linux driver
4297f99b	4	Copyright(c) 2007-2011 Intel Corporation.
9d5c8243 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28
	29	/* Linux PRO/1000 Ethernet Driver main header file */
	30
	31	#ifndef _IGB_H_
	32	#define _IGB_H_
	33
	34	#include "e1000_mac.h"
	35	#include "e1000_82575.h"
	36
38c845c7	37	#include <linux/clocksource.h>
33af6bcc PO	38	#include <linux/timecompare.h>
33af6bcc PO	39	#include <linux/net_tstamp.h>
b2cb09b1 JP	40	#include <linux/bitops.h>
b2cb09b1 JP	41	#include <linux/if_vlan.h>
38c845c7	42
9d5c8243 AK	43	struct igb_adapter;
9d5c8243 AK	44
6eb5a7f1 AD	45	/* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
6eb5a7f1 AD	46	#define IGB_START_ITR 648
9d5c8243	47
9d5c8243 AK	48	/* TX/RX descriptor defines */
9d5c8243 AK	49	#define IGB_DEFAULT_TXD 256
13fde97a	50	#define IGB_DEFAULT_TX_WORK 128
9d5c8243 AK	51	#define IGB_MIN_TXD 80
	52	#define IGB_MAX_TXD 4096
	53
	54	#define IGB_DEFAULT_RXD 256
	55	#define IGB_MIN_RXD 80
	56	#define IGB_MAX_RXD 4096
	57
	58	#define IGB_DEFAULT_ITR 3 /* dynamic */
	59	#define IGB_MAX_ITR_USECS 10000
	60	#define IGB_MIN_ITR_USECS 10
047e0030 AD	61	#define NON_Q_VECTORS 1
047e0030 AD	62	#define MAX_Q_VECTORS 8
9d5c8243 AK	63
9d5c8243 AK	64	/* Transmit and receive queues */
a99955fc AD	65	#define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
a99955fc AD	66	(hw->mac.type > e1000_82575 ? 8 : 4))
1cc3bd87	67	#define IGB_MAX_TX_QUEUES 16
9d5c8243	68
4ae196df AD	69	#define IGB_MAX_VF_MC_ENTRIES 30
	70	#define IGB_MAX_VF_FUNCTIONS 8
	71	#define IGB_MAX_VFTA_ENTRIES 128
	72
	73	struct vf_data_storage {
	74	unsigned char vf_mac_addresses[ETH_ALEN];
	75	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
	76	u16 num_vf_mc_hashes;
ae641bdc	77	u16 vlans_enabled;
f2ca0dbe AD	78	u32 flags;
f2ca0dbe AD	79	unsigned long last_nack;
8151d294 WM	80	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
8151d294 WM	81	u16 pf_qos;
17dc566c	82	u16 tx_rate;
4ae196df AD	83	};
4ae196df AD	84
f2ca0dbe	85	#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
7d5753f0 AD	86	#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
7d5753f0 AD	87	#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
8151d294	88	#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
f2ca0dbe	89
9d5c8243 AK	90	/* RX descriptor control thresholds.
	91	* PTHRESH - MAC will consider prefetch if it has fewer than this number of
	92	* descriptors available in its onboard memory.
	93	* Setting this to 0 disables RX descriptor prefetch.
	94	* HTHRESH - MAC will only prefetch if there are at least this many descriptors
	95	* available in host memory.
	96	* If PTHRESH is 0, this should also be 0.
	97	* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
	98	* descriptors until either it has this many to write back, or the
	99	* ITR timer expires.
	100	*/
58fd62f5	101	#define IGB_RX_PTHRESH 8
9d5c8243	102	#define IGB_RX_HTHRESH 8
85b430b4 AD	103	#define IGB_TX_PTHRESH 8
85b430b4 AD	104	#define IGB_TX_HTHRESH 1
a74420e0 AD	105	#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0 AD	106	adapter->msix_entries) ? 1 : 4)
85b430b4	107	#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
a74420e0	108	adapter->msix_entries) ? 1 : 16)
9d5c8243 AK	109
	110	/* this is the size past which hardware will drop packets when setting LPE=0 */
	111	#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
	112
	113	/* Supported Rx Buffer Sizes */
44390ca6	114	#define IGB_RXBUFFER_512 512
9d5c8243	115	#define IGB_RXBUFFER_16384 16384
44390ca6	116	#define IGB_RX_HDR_LEN IGB_RXBUFFER_512
9d5c8243	117
9d5c8243 AK	118	/* How many Tx Descriptors do we need to call netif_wake_queue ? */
	119	#define IGB_TX_QUEUE_WAKE 16
	120	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	121	#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	122
	123	#define AUTO_ALL_MODES 0
	124	#define IGB_EEPROM_APME 0x0400
	125
	126	#ifndef IGB_MASTER_SLAVE
	127	/* Switch to override PHY master/slave setting */
	128	#define IGB_MASTER_SLAVE e1000_ms_hw_default
	129	#endif
	130
	131	#define IGB_MNG_VLAN_NONE -1
	132
	133	/* wrapper around a pointer to a socket buffer,
	134	* so a DMA handle can be stored along with the buffer */
06034649	135	struct igb_tx_buffer {
8542db05	136	union e1000_adv_tx_desc *next_to_watch;
06034649 AD	137	unsigned long time_stamp;
	138	dma_addr_t dma;
	139	u32 length;
	140	u32 tx_flags;
	141	struct sk_buff *skb;
	142	unsigned int bytecount;
	143	u16 gso_segs;
	144	u8 mapped_as_page;
	145	};
	146
	147	struct igb_rx_buffer {
9d5c8243 AK	148	struct sk_buff *skb;
9d5c8243 AK	149	dma_addr_t dma;
06034649 AD	150	struct page *page;
	151	dma_addr_t page_dma;
	152	u32 page_offset;
9d5c8243 AK	153	};
9d5c8243 AK	154
8c0ab70a	155	struct igb_tx_queue_stats {
9d5c8243 AK	156	u64 packets;
9d5c8243 AK	157	u64 bytes;
04a5fcaa	158	u64 restart_queue;
12dcd86b	159	u64 restart_queue2;
9d5c8243 AK	160	};
9d5c8243 AK	161
8c0ab70a JDB	162	struct igb_rx_queue_stats {
	163	u64 packets;
	164	u64 bytes;
	165	u64 drops;
04a5fcaa AD	166	u64 csum_err;
04a5fcaa AD	167	u64 alloc_failed;
8c0ab70a JDB	168	};
8c0ab70a JDB	169
047e0030	170	struct igb_q_vector {
9d5c8243	171	struct igb_adapter adapter; / backlink */
047e0030 AD	172	struct igb_ring *rx_ring;
	173	struct igb_ring *tx_ring;
	174	struct napi_struct napi;
	175
	176	u32 eims_value;
	177	u16 cpu;
13fde97a	178	u16 tx_work_limit;
047e0030 AD	179
	180	u16 itr_val;
	181	u8 set_itr;
047e0030 AD	182	void __iomem *itr_register;
	183
	184	char name[IFNAMSIZ + 9];
	185	};
	186
	187	struct igb_ring {
238ac817 AD	188	struct igb_q_vector q_vector; / backlink to q_vector */
	189	struct net_device netdev; / back pointer to net_device */
	190	struct device dev; / device pointer for dma mapping */
06034649 AD	191	union { /* array of buffer info structs */
	192	struct igb_tx_buffer *tx_buffer_info;
	193	struct igb_rx_buffer *rx_buffer_info;
	194	};
238ac817 AD	195	void desc; / descriptor ring memory */
	196	unsigned long flags; /* ring specific flags */
	197	void __iomem tail; / pointer to ring tail register */
	198
	199	u16 count; /* number of desc. in the ring */
	200	u8 queue_index; /* logical index of the ring*/
	201	u8 reg_idx; /* physical index of the ring */
	202	u32 size; /* length of desc. ring in bytes */
	203
	204	/* everything past this point are written often */
	205	u16 next_to_clean ____cacheline_aligned_in_smp;
9d5c8243	206	u16 next_to_use;
9d5c8243	207
9d5c8243 AK	208	unsigned int total_bytes;
	209	unsigned int total_packets;
	210
	211	union {
	212	/* TX */
	213	struct {
8c0ab70a	214	struct igb_tx_queue_stats tx_stats;
12dcd86b ED	215	struct u64_stats_sync tx_syncp;
12dcd86b ED	216	struct u64_stats_sync tx_syncp2;
9d5c8243 AK	217	bool detect_tx_hung;
	218	};
	219	/* RX */
	220	struct {
8c0ab70a	221	struct igb_rx_queue_stats rx_stats;
12dcd86b	222	struct u64_stats_sync rx_syncp;
9d5c8243 AK	223	};
9d5c8243 AK	224	};
238ac817 AD	225	/* Items past this point are only used during ring alloc / free */
238ac817 AD	226	dma_addr_t dma; /* phys address of the ring */
9d5c8243 AK	227	};
9d5c8243 AK	228
85ad76b2 AD	229	#define IGB_RING_FLAG_RX_CSUM 0x00000001 /* RX CSUM enabled */
	230	#define IGB_RING_FLAG_RX_SCTP_CSUM 0x00000002 /* SCTP CSUM offload enabled */
	231
	232	#define IGB_RING_FLAG_TX_CTX_IDX 0x00000001 /* HW requires context index */
	233
e032afc8	234	#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP \| E1000_ADVTXD_DCMD_RS)
85ad76b2	235
60136906 AD	236	#define IGB_RX_DESC(R, i) \
	237	(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
	238	#define IGB_TX_DESC(R, i) \
	239	(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
	240	#define IGB_TX_CTXTDESC(R, i) \
	241	(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
9d5c8243	242
d7ee5b3a AD	243	/* igb_desc_unused - calculate if we have unused descriptors */
	244	static inline int igb_desc_unused(struct igb_ring *ring)
	245	{
	246	if (ring->next_to_clean > ring->next_to_use)
	247	return ring->next_to_clean - ring->next_to_use - 1;
	248
	249	return ring->count + ring->next_to_clean - ring->next_to_use - 1;
	250	}
	251
9d5c8243	252	/* board specific private data structure */
9d5c8243	253	struct igb_adapter {
b2cb09b1	254	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
238ac817 AD	255
	256	struct net_device *netdev;
	257
	258	unsigned long state;
	259	unsigned int flags;
	260
	261	unsigned int num_q_vectors;
	262	struct msix_entry *msix_entries;
2e5655e7	263
9d5c8243	264	/* Interrupt Throttle Rate */
4fc82adf AD	265	u32 rx_itr_setting;
4fc82adf AD	266	u32 tx_itr_setting;
9d5c8243 AK	267	u16 tx_itr;
9d5c8243 AK	268	u16 rx_itr;
9d5c8243	269
9d5c8243	270	/* TX */
13fde97a	271	u16 tx_work_limit;
9d5c8243	272	u32 tx_timeout_count;
238ac817 AD	273	int num_tx_queues;
238ac817 AD	274	struct igb_ring *tx_ring[16];
9d5c8243 AK	275
9d5c8243 AK	276	/* RX */
9d5c8243	277	int num_rx_queues;
238ac817	278	struct igb_ring *rx_ring[16];
9d5c8243	279
9d5c8243 AK	280	u32 max_frame_size;
	281	u32 min_frame_size;
	282
238ac817 AD	283	struct timer_list watchdog_timer;
	284	struct timer_list phy_info_timer;
	285
	286	u16 mng_vlan_id;
	287	u32 bd_number;
	288	u32 wol;
	289	u32 en_mng_pt;
	290	u16 link_speed;
	291	u16 link_duplex;
	292
	293	struct work_struct reset_task;
	294	struct work_struct watchdog_task;
	295	bool fc_autoneg;
	296	u8 tx_timeout_factor;
	297	struct timer_list blink_timer;
	298	unsigned long led_status;
	299
9d5c8243	300	/* OS defined structs */
9d5c8243	301	struct pci_dev *pdev;
38c845c7 PO	302	struct cyclecounter cycles;
38c845c7 PO	303	struct timecounter clock;
33af6bcc PO	304	struct timecompare compare;
33af6bcc PO	305	struct hwtstamp_config hwtstamp_config;
9d5c8243	306
12dcd86b ED	307	spinlock_t stats64_lock;
	308	struct rtnl_link_stats64 stats64;
	309
9d5c8243 AK	310	/* structs defined in e1000_hw.h */
	311	struct e1000_hw hw;
	312	struct e1000_hw_stats stats;
	313	struct e1000_phy_info phy_info;
	314	struct e1000_phy_stats phy_stats;
	315
	316	u32 test_icr;
	317	struct igb_ring test_tx_ring;
	318	struct igb_ring test_rx_ring;
	319
	320	int msg_enable;
047e0030	321
047e0030	322	struct igb_q_vector *q_vector[MAX_Q_VECTORS];
9d5c8243	323	u32 eims_enable_mask;
844290e5	324	u32 eims_other;
9d5c8243 AK	325
9d5c8243 AK	326	/* to not mess up cache alignment, always add to the bottom */
9d5c8243	327	u32 eeprom_wol;
42bfd33a	328
2e5655e7 AD	329	u16 tx_ring_count;
2e5655e7 AD	330	u16 rx_ring_count;
1bfaf07b	331	unsigned int vfs_allocated_count;
4ae196df	332	struct vf_data_storage *vf_data;
17dc566c	333	int vf_rate_link_speed;
a99955fc	334	u32 rss_queues;
13800469	335	u32 wvbr;
9d5c8243 AK	336	};
9d5c8243 AK	337
7dfc16fa	338	#define IGB_FLAG_HAS_MSI (1 << 0)
cbd347ad AD	339	#define IGB_FLAG_DCA_ENABLED (1 << 1)
cbd347ad AD	340	#define IGB_FLAG_QUAD_PORT_A (1 << 2)
4fc82adf	341	#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
831ec0b4 CW	342	#define IGB_FLAG_DMAC (1 << 4)
	343
	344	/* DMA Coalescing defines */
	345	#define IGB_MIN_TXPBSIZE 20408
	346	#define IGB_TX_BUF_4096 4096
	347	#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
7dfc16fa	348
c5b9bd5e	349	#define IGB_82576_TSYNC_SHIFT 19
55cac248	350	#define IGB_82580_TSYNC_SHIFT 24
757b77e2	351	#define IGB_TS_HDR_LEN 16
9d5c8243 AK	352	enum e1000_state_t {
	353	__IGB_TESTING,
	354	__IGB_RESETTING,
	355	__IGB_DOWN
	356	};
	357
	358	enum igb_boards {
	359	board_82575,
	360	};
	361
	362	extern char igb_driver_name[];
	363	extern char igb_driver_version[];
	364
9d5c8243 AK	365	extern int igb_up(struct igb_adapter *);
	366	extern void igb_down(struct igb_adapter *);
	367	extern void igb_reinit_locked(struct igb_adapter *);
	368	extern void igb_reset(struct igb_adapter *);
14ad2513	369	extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
80785298 AD	370	extern int igb_setup_tx_resources(struct igb_ring *);
80785298 AD	371	extern int igb_setup_rx_resources(struct igb_ring *);
68fd9910 AD	372	extern void igb_free_tx_resources(struct igb_ring *);
68fd9910 AD	373	extern void igb_free_rx_resources(struct igb_ring *);
d7ee5b3a AD	374	extern void igb_configure_tx_ring(struct igb_adapter , struct igb_ring );
	375	extern void igb_configure_rx_ring(struct igb_adapter , struct igb_ring );
	376	extern void igb_setup_tctl(struct igb_adapter *);
	377	extern void igb_setup_rctl(struct igb_adapter *);
cd392f5c	378	extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff , struct igb_ring );
b1a436c3	379	extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
06034649	380	struct igb_tx_buffer *);
cd392f5c	381	extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
12dcd86b	382	extern void igb_update_stats(struct igb_adapter , struct rtnl_link_stats64 );
3145535a	383	extern bool igb_has_link(struct igb_adapter *adapter);
9d5c8243	384	extern void igb_set_ethtool_ops(struct net_device *);
88a268c1	385	extern void igb_power_up_link(struct igb_adapter *);
9d5c8243	386
f5f4cf08 AD	387	static inline s32 igb_reset_phy(struct e1000_hw *hw)
f5f4cf08 AD	388	{
a8d2a0c2 AD	389	if (hw->phy.ops.reset)
a8d2a0c2 AD	390	return hw->phy.ops.reset(hw);
f5f4cf08 AD	391
	392	return 0;
	393	}
	394
	395	static inline s32 igb_read_phy_reg(struct e1000_hw hw, u32 offset, u16 data)
	396	{
a8d2a0c2 AD	397	if (hw->phy.ops.read_reg)
a8d2a0c2 AD	398	return hw->phy.ops.read_reg(hw, offset, data);
f5f4cf08 AD	399
	400	return 0;
	401	}
	402
	403	static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
	404	{
a8d2a0c2 AD	405	if (hw->phy.ops.write_reg)
a8d2a0c2 AD	406	return hw->phy.ops.write_reg(hw, offset, data);
f5f4cf08 AD	407
	408	return 0;
	409	}
	410
	411	static inline s32 igb_get_phy_info(struct e1000_hw *hw)
	412	{
	413	if (hw->phy.ops.get_phy_info)
	414	return hw->phy.ops.get_phy_info(hw);
	415
	416	return 0;
	417	}
	418
9d5c8243	419	#endif /* _IGB_H_ */