projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: make local functions static
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4297f99b 4 Copyright(c) 2007-2011 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
d43c36dc 37#include <linux/sched.h>
5a0e3ad6 38#include <linux/slab.h>
749ab2cd 39#include <linux/pm_runtime.h>
9d5c8243
AK		 40
41#include "igb.h"
42
43struct igb_stats {
44 char stat_string[ETH_GSTRING_LEN];
45 int sizeof_stat;
46 int stat_offset;
47};
48
128e45eb
AD		 49#define IGB_STAT(_name, _stat) { \
50 .stat_string = _name, \
51 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
52 .stat_offset = offsetof(struct igb_adapter, _stat) \
53}
9d5c8243 54static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 55 IGB_STAT("rx_packets", stats.gprc),
56 IGB_STAT("tx_packets", stats.gptc),
57 IGB_STAT("rx_bytes", stats.gorc),
58 IGB_STAT("tx_bytes", stats.gotc),
59 IGB_STAT("rx_broadcast", stats.bprc),
60 IGB_STAT("tx_broadcast", stats.bptc),
61 IGB_STAT("rx_multicast", stats.mprc),
62 IGB_STAT("tx_multicast", stats.mptc),
63 IGB_STAT("multicast", stats.mprc),
64 IGB_STAT("collisions", stats.colc),
65 IGB_STAT("rx_crc_errors", stats.crcerrs),
66 IGB_STAT("rx_no_buffer_count", stats.rnbc),
67 IGB_STAT("rx_missed_errors", stats.mpc),
68 IGB_STAT("tx_aborted_errors", stats.ecol),
69 IGB_STAT("tx_carrier_errors", stats.tncrs),
70 IGB_STAT("tx_window_errors", stats.latecol),
71 IGB_STAT("tx_abort_late_coll", stats.latecol),
72 IGB_STAT("tx_deferred_ok", stats.dc),
73 IGB_STAT("tx_single_coll_ok", stats.scc),
74 IGB_STAT("tx_multi_coll_ok", stats.mcc),
75 IGB_STAT("tx_timeout_count", tx_timeout_count),
76 IGB_STAT("rx_long_length_errors", stats.roc),
77 IGB_STAT("rx_short_length_errors", stats.ruc),
78 IGB_STAT("rx_align_errors", stats.algnerrc),
79 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
80 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
81 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
82 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
83 IGB_STAT("tx_flow_control_xon", stats.xontxc),
84 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
85 IGB_STAT("rx_long_byte_count", stats.gorc),
86 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
87 IGB_STAT("tx_smbus", stats.mgptc),
88 IGB_STAT("rx_smbus", stats.mgprc),
89 IGB_STAT("dropped_smbus", stats.mgpdc),
0a915b95
CW		 90 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
91 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
92 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
93 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
128e45eb
AD		 94};
95
96#define IGB_NETDEV_STAT(_net_stat) { \
97 .stat_string = __stringify(_net_stat), \
12dcd86b
ED		 98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
128e45eb
AD		 100}
101static const struct igb_stats igb_gstrings_net_stats[] = {
102 IGB_NETDEV_STAT(rx_errors),
103 IGB_NETDEV_STAT(tx_errors),
104 IGB_NETDEV_STAT(tx_dropped),
105 IGB_NETDEV_STAT(rx_length_errors),
106 IGB_NETDEV_STAT(rx_over_errors),
107 IGB_NETDEV_STAT(rx_frame_errors),
108 IGB_NETDEV_STAT(rx_fifo_errors),
109 IGB_NETDEV_STAT(tx_fifo_errors),
110 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 111};
112
128e45eb
AD		 113#define IGB_GLOBAL_STATS_LEN \
114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
115#define IGB_NETDEV_STATS_LEN \
116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
117#define IGB_RX_QUEUE_STATS_LEN \
118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
12dcd86b
ED		 119
120#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
121
9d5c8243 122#define IGB_QUEUE_STATS_LEN \
317f66bd 123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 124 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 126 IGB_TX_QUEUE_STATS_LEN))
127#define IGB_STATS_LEN \
128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
129
9d5c8243
AK		 130static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
131 "Register test (offline)", "Eeprom test (offline)",
132 "Interrupt test (offline)", "Loopback test (offline)",
133 "Link test (on/offline)"
134};
317f66bd 135#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 136
137static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
138{
139 struct igb_adapter *adapter = netdev_priv(netdev);
140 struct e1000_hw *hw = &adapter->hw;
317f66bd 141 u32 status;
9d5c8243
AK		 142
143 if (hw->phy.media_type == e1000_media_type_copper) {
144
145 ecmd->supported = (SUPPORTED_10baseT_Half |
146 SUPPORTED_10baseT_Full |
147 SUPPORTED_100baseT_Half |
148 SUPPORTED_100baseT_Full |
149 SUPPORTED_1000baseT_Full|
150 SUPPORTED_Autoneg |
151 SUPPORTED_TP);
f83396ad
CW		 152 ecmd->advertising = (ADVERTISED_TP |
153 ADVERTISED_Pause);
9d5c8243
AK		 154
155 if (hw->mac.autoneg == 1) {
156 ecmd->advertising |= ADVERTISED_Autoneg;
157 /* the e1000 autoneg seems to match ethtool nicely */
158 ecmd->advertising |= hw->phy.autoneg_advertised;
159 }
160
161 ecmd->port = PORT_TP;
162 ecmd->phy_address = hw->phy.addr;
163 } else {
164 ecmd->supported = (SUPPORTED_1000baseT_Full |
165 SUPPORTED_FIBRE |
166 SUPPORTED_Autoneg);
167
168 ecmd->advertising = (ADVERTISED_1000baseT_Full |
169 ADVERTISED_FIBRE |
f83396ad
CW		 170 ADVERTISED_Autoneg |
171 ADVERTISED_Pause);
9d5c8243
AK		 172
173 ecmd->port = PORT_FIBRE;
174 }
175
176 ecmd->transceiver = XCVR_INTERNAL;
177
317f66bd 178 status = rd32(E1000_STATUS);
9d5c8243 179
317f66bd 180 if (status & E1000_STATUS_LU) {
9d5c8243 181
317f66bd
AD		 182 if ((status & E1000_STATUS_SPEED_1000) ||
183 hw->phy.media_type != e1000_media_type_copper)
70739497 184 ethtool_cmd_speed_set(ecmd, SPEED_1000);
317f66bd 185 else if (status & E1000_STATUS_SPEED_100)
70739497 186 ethtool_cmd_speed_set(ecmd, SPEED_100);
317f66bd 187 else
70739497 188 ethtool_cmd_speed_set(ecmd, SPEED_10);
9d5c8243 189
317f66bd
AD		 190 if ((status & E1000_STATUS_FD) ||
191 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 192 ecmd->duplex = DUPLEX_FULL;
193 else
194 ecmd->duplex = DUPLEX_HALF;
195 } else {
70739497 196 ethtool_cmd_speed_set(ecmd, -1);
9d5c8243
AK		 197 ecmd->duplex = -1;
198 }
199
dcc3ae9a 200 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
9d5c8243
AK		 201 return 0;
202}
203
204static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
205{
206 struct igb_adapter *adapter = netdev_priv(netdev);
207 struct e1000_hw *hw = &adapter->hw;
208
209 /* When SoL/IDER sessions are active, autoneg/speed/duplex
210 * cannot be changed */
211 if (igb_check_reset_block(hw)) {
212 dev_err(&adapter->pdev->dev, "Cannot change link "
213 "characteristics when SoL/IDER is active.\n");
214 return -EINVAL;
215 }
216
217 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
218 msleep(1);
219
220 if (ecmd->autoneg == AUTONEG_ENABLE) {
221 hw->mac.autoneg = 1;
dcc3ae9a
AD		 222 hw->phy.autoneg_advertised = ecmd->advertising |
223 ADVERTISED_TP |
224 ADVERTISED_Autoneg;
9d5c8243 225 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 226 if (adapter->fc_autoneg)
227 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 228 } else {
25db0338 229 u32 speed = ethtool_cmd_speed(ecmd);
14ad2513 230 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
9d5c8243
AK		 231 clear_bit(__IGB_RESETTING, &adapter->state);
232 return -EINVAL;
233 }
dcc3ae9a 234 }
9d5c8243
AK		 235
236 /* reset the link */
9d5c8243
AK		 237 if (netif_running(adapter->netdev)) {
238 igb_down(adapter);
239 igb_up(adapter);
240 } else
241 igb_reset(adapter);
242
243 clear_bit(__IGB_RESETTING, &adapter->state);
244 return 0;
245}
246
3145535a
NN		 247static u32 igb_get_link(struct net_device *netdev)
248{
249 struct igb_adapter *adapter = netdev_priv(netdev);
250 struct e1000_mac_info *mac = &adapter->hw.mac;
251
252 /*
253 * If the link is not reported up to netdev, interrupts are disabled,
254 * and so the physical link state may have changed since we last
255 * looked. Set get_link_status to make sure that the true link
256 * state is interrogated, rather than pulling a cached and possibly
257 * stale link state from the driver.
258 */
259 if (!netif_carrier_ok(netdev))
260 mac->get_link_status = 1;
261
262 return igb_has_link(adapter);
263}
264
9d5c8243
AK		 265static void igb_get_pauseparam(struct net_device *netdev,
266 struct ethtool_pauseparam *pause)
267{
268 struct igb_adapter *adapter = netdev_priv(netdev);
269 struct e1000_hw *hw = &adapter->hw;
270
271 pause->autoneg =
272 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
273
0cce119a 274 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 275 pause->rx_pause = 1;
0cce119a 276 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 277 pause->tx_pause = 1;
0cce119a 278 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 279 pause->rx_pause = 1;
280 pause->tx_pause = 1;
281 }
282}
283
284static int igb_set_pauseparam(struct net_device *netdev,
285 struct ethtool_pauseparam *pause)
286{
287 struct igb_adapter *adapter = netdev_priv(netdev);
288 struct e1000_hw *hw = &adapter->hw;
289 int retval = 0;
290
291 adapter->fc_autoneg = pause->autoneg;
292
293 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
294 msleep(1);
295
9d5c8243 296 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 297 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 298 if (netif_running(adapter->netdev)) {
299 igb_down(adapter);
300 igb_up(adapter);
317f66bd 301 } else {
9d5c8243 302 igb_reset(adapter);
317f66bd 303 }
0cce119a
AD		 304 } else {
305 if (pause->rx_pause && pause->tx_pause)
306 hw->fc.requested_mode = e1000_fc_full;
307 else if (pause->rx_pause && !pause->tx_pause)
308 hw->fc.requested_mode = e1000_fc_rx_pause;
309 else if (!pause->rx_pause && pause->tx_pause)
310 hw->fc.requested_mode = e1000_fc_tx_pause;
311 else if (!pause->rx_pause && !pause->tx_pause)
312 hw->fc.requested_mode = e1000_fc_none;
313
314 hw->fc.current_mode = hw->fc.requested_mode;
315
dcc3ae9a
AD		 316 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
317 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 318 }
9d5c8243
AK		 319
320 clear_bit(__IGB_RESETTING, &adapter->state);
321 return retval;
322}
323
9d5c8243
AK		 324static u32 igb_get_msglevel(struct net_device *netdev)
325{
326 struct igb_adapter *adapter = netdev_priv(netdev);
327 return adapter->msg_enable;
328}
329
330static void igb_set_msglevel(struct net_device *netdev, u32 data)
331{
332 struct igb_adapter *adapter = netdev_priv(netdev);
333 adapter->msg_enable = data;
334}
335
336static int igb_get_regs_len(struct net_device *netdev)
337{
338#define IGB_REGS_LEN 551
339 return IGB_REGS_LEN * sizeof(u32);
340}
341
342static void igb_get_regs(struct net_device *netdev,
343 struct ethtool_regs *regs, void *p)
344{
345 struct igb_adapter *adapter = netdev_priv(netdev);
346 struct e1000_hw *hw = &adapter->hw;
347 u32 *regs_buff = p;
348 u8 i;
349
350 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
351
352 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
353
354 /* General Registers */
355 regs_buff[0] = rd32(E1000_CTRL);
356 regs_buff[1] = rd32(E1000_STATUS);
357 regs_buff[2] = rd32(E1000_CTRL_EXT);
358 regs_buff[3] = rd32(E1000_MDIC);
359 regs_buff[4] = rd32(E1000_SCTL);
360 regs_buff[5] = rd32(E1000_CONNSW);
361 regs_buff[6] = rd32(E1000_VET);
362 regs_buff[7] = rd32(E1000_LEDCTL);
363 regs_buff[8] = rd32(E1000_PBA);
364 regs_buff[9] = rd32(E1000_PBS);
365 regs_buff[10] = rd32(E1000_FRTIMER);
366 regs_buff[11] = rd32(E1000_TCPTIMER);
367
368 /* NVM Register */
369 regs_buff[12] = rd32(E1000_EECD);
370
371 /* Interrupt */
fe59de38
AD		 372 /* Reading EICS for EICR because they read the
373 * same but EICS does not clear on read */
374 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 375 regs_buff[14] = rd32(E1000_EICS);
376 regs_buff[15] = rd32(E1000_EIMS);
377 regs_buff[16] = rd32(E1000_EIMC);
378 regs_buff[17] = rd32(E1000_EIAC);
379 regs_buff[18] = rd32(E1000_EIAM);
fe59de38
AD		 380 /* Reading ICS for ICR because they read the
381 * same but ICS does not clear on read */
382 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 383 regs_buff[20] = rd32(E1000_ICS);
384 regs_buff[21] = rd32(E1000_IMS);
385 regs_buff[22] = rd32(E1000_IMC);
386 regs_buff[23] = rd32(E1000_IAC);
387 regs_buff[24] = rd32(E1000_IAM);
388 regs_buff[25] = rd32(E1000_IMIRVP);
389
390 /* Flow Control */
391 regs_buff[26] = rd32(E1000_FCAL);
392 regs_buff[27] = rd32(E1000_FCAH);
393 regs_buff[28] = rd32(E1000_FCTTV);
394 regs_buff[29] = rd32(E1000_FCRTL);
395 regs_buff[30] = rd32(E1000_FCRTH);
396 regs_buff[31] = rd32(E1000_FCRTV);
397
398 /* Receive */
399 regs_buff[32] = rd32(E1000_RCTL);
400 regs_buff[33] = rd32(E1000_RXCSUM);
401 regs_buff[34] = rd32(E1000_RLPML);
402 regs_buff[35] = rd32(E1000_RFCTL);
403 regs_buff[36] = rd32(E1000_MRQC);
e1739522 404 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 405
406 /* Transmit */
407 regs_buff[38] = rd32(E1000_TCTL);
408 regs_buff[39] = rd32(E1000_TCTL_EXT);
409 regs_buff[40] = rd32(E1000_TIPG);
410 regs_buff[41] = rd32(E1000_DTXCTL);
411
412 /* Wake Up */
413 regs_buff[42] = rd32(E1000_WUC);
414 regs_buff[43] = rd32(E1000_WUFC);
415 regs_buff[44] = rd32(E1000_WUS);
416 regs_buff[45] = rd32(E1000_IPAV);
417 regs_buff[46] = rd32(E1000_WUPL);
418
419 /* MAC */
420 regs_buff[47] = rd32(E1000_PCS_CFG0);
421 regs_buff[48] = rd32(E1000_PCS_LCTL);
422 regs_buff[49] = rd32(E1000_PCS_LSTAT);
423 regs_buff[50] = rd32(E1000_PCS_ANADV);
424 regs_buff[51] = rd32(E1000_PCS_LPAB);
425 regs_buff[52] = rd32(E1000_PCS_NPTX);
426 regs_buff[53] = rd32(E1000_PCS_LPABNP);
427
428 /* Statistics */
429 regs_buff[54] = adapter->stats.crcerrs;
430 regs_buff[55] = adapter->stats.algnerrc;
431 regs_buff[56] = adapter->stats.symerrs;
432 regs_buff[57] = adapter->stats.rxerrc;
433 regs_buff[58] = adapter->stats.mpc;
434 regs_buff[59] = adapter->stats.scc;
435 regs_buff[60] = adapter->stats.ecol;
436 regs_buff[61] = adapter->stats.mcc;
437 regs_buff[62] = adapter->stats.latecol;
438 regs_buff[63] = adapter->stats.colc;
439 regs_buff[64] = adapter->stats.dc;
440 regs_buff[65] = adapter->stats.tncrs;
441 regs_buff[66] = adapter->stats.sec;
442 regs_buff[67] = adapter->stats.htdpmc;
443 regs_buff[68] = adapter->stats.rlec;
444 regs_buff[69] = adapter->stats.xonrxc;
445 regs_buff[70] = adapter->stats.xontxc;
446 regs_buff[71] = adapter->stats.xoffrxc;
447 regs_buff[72] = adapter->stats.xofftxc;
448 regs_buff[73] = adapter->stats.fcruc;
449 regs_buff[74] = adapter->stats.prc64;
450 regs_buff[75] = adapter->stats.prc127;
451 regs_buff[76] = adapter->stats.prc255;
452 regs_buff[77] = adapter->stats.prc511;
453 regs_buff[78] = adapter->stats.prc1023;
454 regs_buff[79] = adapter->stats.prc1522;
455 regs_buff[80] = adapter->stats.gprc;
456 regs_buff[81] = adapter->stats.bprc;
457 regs_buff[82] = adapter->stats.mprc;
458 regs_buff[83] = adapter->stats.gptc;
459 regs_buff[84] = adapter->stats.gorc;
460 regs_buff[86] = adapter->stats.gotc;
461 regs_buff[88] = adapter->stats.rnbc;
462 regs_buff[89] = adapter->stats.ruc;
463 regs_buff[90] = adapter->stats.rfc;
464 regs_buff[91] = adapter->stats.roc;
465 regs_buff[92] = adapter->stats.rjc;
466 regs_buff[93] = adapter->stats.mgprc;
467 regs_buff[94] = adapter->stats.mgpdc;
468 regs_buff[95] = adapter->stats.mgptc;
469 regs_buff[96] = adapter->stats.tor;
470 regs_buff[98] = adapter->stats.tot;
471 regs_buff[100] = adapter->stats.tpr;
472 regs_buff[101] = adapter->stats.tpt;
473 regs_buff[102] = adapter->stats.ptc64;
474 regs_buff[103] = adapter->stats.ptc127;
475 regs_buff[104] = adapter->stats.ptc255;
476 regs_buff[105] = adapter->stats.ptc511;
477 regs_buff[106] = adapter->stats.ptc1023;
478 regs_buff[107] = adapter->stats.ptc1522;
479 regs_buff[108] = adapter->stats.mptc;
480 regs_buff[109] = adapter->stats.bptc;
481 regs_buff[110] = adapter->stats.tsctc;
482 regs_buff[111] = adapter->stats.iac;
483 regs_buff[112] = adapter->stats.rpthc;
484 regs_buff[113] = adapter->stats.hgptc;
485 regs_buff[114] = adapter->stats.hgorc;
486 regs_buff[116] = adapter->stats.hgotc;
487 regs_buff[118] = adapter->stats.lenerrs;
488 regs_buff[119] = adapter->stats.scvpc;
489 regs_buff[120] = adapter->stats.hrmpc;
490
9d5c8243
AK		 491 for (i = 0; i < 4; i++)
492 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
493 for (i = 0; i < 4; i++)
83ab50a5 494 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 495 for (i = 0; i < 4; i++)
496 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
497 for (i = 0; i < 4; i++)
498 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
499 for (i = 0; i < 4; i++)
500 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
501 for (i = 0; i < 4; i++)
502 regs_buff[141 + i] = rd32(E1000_RDH(i));
503 for (i = 0; i < 4; i++)
504 regs_buff[145 + i] = rd32(E1000_RDT(i));
505 for (i = 0; i < 4; i++)
506 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
507
508 for (i = 0; i < 10; i++)
509 regs_buff[153 + i] = rd32(E1000_EITR(i));
510 for (i = 0; i < 8; i++)
511 regs_buff[163 + i] = rd32(E1000_IMIR(i));
512 for (i = 0; i < 8; i++)
513 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
514 for (i = 0; i < 16; i++)
515 regs_buff[179 + i] = rd32(E1000_RAL(i));
516 for (i = 0; i < 16; i++)
517 regs_buff[195 + i] = rd32(E1000_RAH(i));
518
519 for (i = 0; i < 4; i++)
520 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
521 for (i = 0; i < 4; i++)
522 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
523 for (i = 0; i < 4; i++)
524 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
525 for (i = 0; i < 4; i++)
526 regs_buff[223 + i] = rd32(E1000_TDH(i));
527 for (i = 0; i < 4; i++)
528 regs_buff[227 + i] = rd32(E1000_TDT(i));
529 for (i = 0; i < 4; i++)
530 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
531 for (i = 0; i < 4; i++)
532 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
533 for (i = 0; i < 4; i++)
534 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
535 for (i = 0; i < 4; i++)
536 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
537
538 for (i = 0; i < 4; i++)
539 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
540 for (i = 0; i < 4; i++)
541 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
542 for (i = 0; i < 32; i++)
543 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
544 for (i = 0; i < 128; i++)
545 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
546 for (i = 0; i < 128; i++)
547 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
548 for (i = 0; i < 4; i++)
549 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
550
551 regs_buff[547] = rd32(E1000_TDFH);
552 regs_buff[548] = rd32(E1000_TDFT);
553 regs_buff[549] = rd32(E1000_TDFHS);
554 regs_buff[550] = rd32(E1000_TDFPC);
0a915b95
CW		 555 regs_buff[551] = adapter->stats.o2bgptc;
556 regs_buff[552] = adapter->stats.b2ospc;
557 regs_buff[553] = adapter->stats.o2bspc;
558 regs_buff[554] = adapter->stats.b2ogprc;
9d5c8243
AK		 559}
560
561static int igb_get_eeprom_len(struct net_device *netdev)
562{
563 struct igb_adapter *adapter = netdev_priv(netdev);
564 return adapter->hw.nvm.word_size * 2;
565}
566
567static int igb_get_eeprom(struct net_device *netdev,
568 struct ethtool_eeprom *eeprom, u8 *bytes)
569{
570 struct igb_adapter *adapter = netdev_priv(netdev);
571 struct e1000_hw *hw = &adapter->hw;
572 u16 *eeprom_buff;
573 int first_word, last_word;
574 int ret_val = 0;
575 u16 i;
576
577 if (eeprom->len == 0)
578 return -EINVAL;
579
580 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
581
582 first_word = eeprom->offset >> 1;
583 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
584
585 eeprom_buff = kmalloc(sizeof(u16) *
586 (last_word - first_word + 1), GFP_KERNEL);
587 if (!eeprom_buff)
588 return -ENOMEM;
589
590 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 591 ret_val = hw->nvm.ops.read(hw, first_word,
9d5c8243
AK		 592 last_word - first_word + 1,
593 eeprom_buff);
594 else {
595 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 596 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
9d5c8243
AK		 597 &eeprom_buff[i]);
598 if (ret_val)
599 break;
600 }
601 }
602
603 /* Device's eeprom is always little-endian, word addressable */
604 for (i = 0; i < last_word - first_word + 1; i++)
605 le16_to_cpus(&eeprom_buff[i]);
606
607 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
608 eeprom->len);
609 kfree(eeprom_buff);
610
611 return ret_val;
612}
613
614static int igb_set_eeprom(struct net_device *netdev,
615 struct ethtool_eeprom *eeprom, u8 *bytes)
616{
617 struct igb_adapter *adapter = netdev_priv(netdev);
618 struct e1000_hw *hw = &adapter->hw;
619 u16 *eeprom_buff;
620 void *ptr;
621 int max_len, first_word, last_word, ret_val = 0;
622 u16 i;
623
624 if (eeprom->len == 0)
625 return -EOPNOTSUPP;
626
627 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
628 return -EFAULT;
629
630 max_len = hw->nvm.word_size * 2;
631
632 first_word = eeprom->offset >> 1;
633 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
634 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
635 if (!eeprom_buff)
636 return -ENOMEM;
637
638 ptr = (void *)eeprom_buff;
639
640 if (eeprom->offset & 1) {
641 /* need read/modify/write of first changed EEPROM word */
642 /* only the second byte of the word is being modified */
312c75ae 643 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 644 &eeprom_buff[0]);
645 ptr++;
646 }
647 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
648 /* need read/modify/write of last changed EEPROM word */
649 /* only the first byte of the word is being modified */
312c75ae 650 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 651 &eeprom_buff[last_word - first_word]);
652 }
653
654 /* Device's eeprom is always little-endian, word addressable */
655 for (i = 0; i < last_word - first_word + 1; i++)
656 le16_to_cpus(&eeprom_buff[i]);
657
658 memcpy(ptr, bytes, eeprom->len);
659
660 for (i = 0; i < last_word - first_word + 1; i++)
661 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
662
312c75ae 663 ret_val = hw->nvm.ops.write(hw, first_word,
9d5c8243
AK		 664 last_word - first_word + 1, eeprom_buff);
665
666 /* Update the checksum over the first part of the EEPROM if needed
667 * and flush shadow RAM for 82573 controllers */
668 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
4322e561 669 hw->nvm.ops.update(hw);
9d5c8243
AK		 670
671 kfree(eeprom_buff);
672 return ret_val;
673}
674
675static void igb_get_drvinfo(struct net_device *netdev,
676 struct ethtool_drvinfo *drvinfo)
677{
678 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 679 u16 eeprom_data;
680
612a94d6
RJ		 681 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
682 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
9d5c8243
AK		 683
684 /* EEPROM image version # is reported as firmware version # for
685 * 82575 controllers */
312c75ae 686 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
612a94d6
RJ		 687 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
688 "%d.%d-%d",
9d5c8243
AK		 689 (eeprom_data & 0xF000) >> 12,
690 (eeprom_data & 0x0FF0) >> 4,
691 eeprom_data & 0x000F);
692
612a94d6
RJ		 693 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
694 sizeof(drvinfo->bus_info));
9d5c8243
AK		 695 drvinfo->n_stats = IGB_STATS_LEN;
696 drvinfo->testinfo_len = IGB_TEST_LEN;
697 drvinfo->regdump_len = igb_get_regs_len(netdev);
698 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
699}
700
701static void igb_get_ringparam(struct net_device *netdev,
702 struct ethtool_ringparam *ring)
703{
704 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 705
706 ring->rx_max_pending = IGB_MAX_RXD;
707 ring->tx_max_pending = IGB_MAX_TXD;
68fd9910
AD		 708 ring->rx_pending = adapter->rx_ring_count;
709 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 710}
711
712static int igb_set_ringparam(struct net_device *netdev,
713 struct ethtool_ringparam *ring)
714{
715 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 716 struct igb_ring *temp_ring;
6d9f4fc4 717 int i, err = 0;
0e15439a 718 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 719
720 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
721 return -EINVAL;
722
0e15439a
AD		 723 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
724 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 725 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
726
0e15439a
AD		 727 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
728 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 729 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
730
68fd9910
AD		 731 if ((new_tx_count == adapter->tx_ring_count) &&
732 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 733 /* nothing to do */
734 return 0;
735 }
736
6d9f4fc4
AD		 737 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
738 msleep(1);
739
740 if (!netif_running(adapter->netdev)) {
741 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 742 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 743 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 744 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 745 adapter->tx_ring_count = new_tx_count;
746 adapter->rx_ring_count = new_rx_count;
747 goto clear_reset;
748 }
749
68fd9910
AD		 750 if (adapter->num_tx_queues > adapter->num_rx_queues)
751 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
752 else
753 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
68fd9910 754
6d9f4fc4
AD		 755 if (!temp_ring) {
756 err = -ENOMEM;
757 goto clear_reset;
758 }
9d5c8243 759
6d9f4fc4 760 igb_down(adapter);
9d5c8243
AK		 761
762 /*
763 * We can't just free everything and then setup again,
764 * because the ISRs in MSI-X mode get passed pointers
765 * to the tx and rx ring structs.
766 */
68fd9910 767 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 768 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 769 memcpy(&temp_ring[i], adapter->tx_ring[i],
770 sizeof(struct igb_ring));
771
68fd9910 772 temp_ring[i].count = new_tx_count;
80785298 773 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 774 if (err) {
68fd9910
AD		 775 while (i) {
776 i--;
777 igb_free_tx_resources(&temp_ring[i]);
778 }
9d5c8243
AK		 779 goto err_setup;
780 }
9d5c8243 781 }
68fd9910 782
3025a446
AD		 783 for (i = 0; i < adapter->num_tx_queues; i++) {
784 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 785
3025a446
AD		 786 memcpy(adapter->tx_ring[i], &temp_ring[i],
787 sizeof(struct igb_ring));
788 }
68fd9910
AD		 789
790 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 791 }
792
3025a446 793 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 794 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 795 memcpy(&temp_ring[i], adapter->rx_ring[i],
796 sizeof(struct igb_ring));
797
68fd9910 798 temp_ring[i].count = new_rx_count;
80785298 799 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 800 if (err) {
68fd9910
AD		 801 while (i) {
802 i--;
803 igb_free_rx_resources(&temp_ring[i]);
804 }
9d5c8243
AK		 805 goto err_setup;
806 }
807
9d5c8243 808 }
68fd9910 809
3025a446
AD		 810 for (i = 0; i < adapter->num_rx_queues; i++) {
811 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 812
3025a446
AD		 813 memcpy(adapter->rx_ring[i], &temp_ring[i],
814 sizeof(struct igb_ring));
815 }
68fd9910
AD		 816
817 adapter->rx_ring_count = new_rx_count;
9d5c8243 818 }
9d5c8243 819err_setup:
6d9f4fc4 820 igb_up(adapter);
68fd9910 821 vfree(temp_ring);
6d9f4fc4
AD		 822clear_reset:
823 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 824 return err;
825}
826
827/* ethtool register test data */
828struct igb_reg_test {
829 u16 reg;
2d064c06
AD		 830 u16 reg_offset;
831 u16 array_len;
832 u16 test_type;
9d5c8243
AK		 833 u32 mask;
834 u32 write;
835};
836
837/* In the hardware, registers are laid out either singly, in arrays
838 * spaced 0x100 bytes apart, or in contiguous tables. We assume
839 * most tests take place on arrays or single registers (handled
840 * as a single-element array) and special-case the tables.
841 * Table tests are always pattern tests.
842 *
843 * We also make provision for some required setup steps by specifying
844 * registers to be written without any read-back testing.
845 */
846
847#define PATTERN_TEST 1
848#define SET_READ_TEST 2
849#define WRITE_NO_TEST 3
850#define TABLE32_TEST 4
851#define TABLE64_TEST_LO 5
852#define TABLE64_TEST_HI 6
853
d2ba2ed8
AD		 854/* i350 reg test */
855static struct igb_reg_test reg_test_i350[] = {
856 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
857 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
858 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
859 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
860 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
861 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 862 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 863 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
864 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 865 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 866 /* RDH is read-only for i350, only test RDT. */
867 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
868 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
869 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
870 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
871 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
872 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
873 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 874 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 875 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
876 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 877 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 878 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
879 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
880 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
881 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
882 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
883 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
884 { E1000_RA, 0, 16, TABLE64_TEST_LO,
885 0xFFFFFFFF, 0xFFFFFFFF },
886 { E1000_RA, 0, 16, TABLE64_TEST_HI,
887 0xC3FFFFFF, 0xFFFFFFFF },
888 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
889 0xFFFFFFFF, 0xFFFFFFFF },
890 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
891 0xC3FFFFFF, 0xFFFFFFFF },
892 { E1000_MTA, 0, 128, TABLE32_TEST,
893 0xFFFFFFFF, 0xFFFFFFFF },
894 { 0, 0, 0, 0 }
895};
896
55cac248
AD		 897/* 82580 reg test */
898static struct igb_reg_test reg_test_82580[] = {
899 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
900 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
901 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
902 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
903 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
904 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
905 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
906 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
907 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
908 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
909 /* RDH is read-only for 82580, only test RDT. */
910 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
911 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
912 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
913 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
914 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
915 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
916 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
917 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
918 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
919 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
920 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
921 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
922 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
923 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
924 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
925 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
926 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
927 { E1000_RA, 0, 16, TABLE64_TEST_LO,
928 0xFFFFFFFF, 0xFFFFFFFF },
929 { E1000_RA, 0, 16, TABLE64_TEST_HI,
930 0x83FFFFFF, 0xFFFFFFFF },
931 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
932 0xFFFFFFFF, 0xFFFFFFFF },
933 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
934 0x83FFFFFF, 0xFFFFFFFF },
935 { E1000_MTA, 0, 128, TABLE32_TEST,
936 0xFFFFFFFF, 0xFFFFFFFF },
937 { 0, 0, 0, 0 }
938};
939
2d064c06
AD		 940/* 82576 reg test */
941static struct igb_reg_test reg_test_82576[] = {
942 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
943 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
944 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
945 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
946 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
947 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
948 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 949 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
950 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
951 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
952 /* Enable all RX queues before testing. */
953 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
954 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 955 /* RDH is read-only for 82576, only test RDT. */
956 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 957 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 958 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 959 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 960 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
961 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
962 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
963 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
964 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
965 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 966 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
967 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
968 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 969 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
970 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
971 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
972 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
973 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
974 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
975 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
976 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
977 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
978 { 0, 0, 0, 0 }
979};
980
981/* 82575 register test */
9d5c8243 982static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 983 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
984 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
985 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
986 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
987 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
988 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
989 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 990 /* Enable all four RX queues before testing. */
2d064c06 991 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 992 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 993 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
994 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
995 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
996 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
997 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
998 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
999 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1000 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1001 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1002 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1003 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1004 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1005 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1006 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1007 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1008 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1009 { 0, 0, 0, 0 }
1010};
1011
1012static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1013 int reg, u32 mask, u32 write)
1014{
2753f4ce 1015 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1016 u32 pat, val;
317f66bd 1017 static const u32 _test[] =
9d5c8243
AK		 1018 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1019 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce 1020 wr32(reg, (_test[pat] & write));
93ed8359 1021 val = rd32(reg) & mask;
9d5c8243
AK		 1022 if (val != (_test[pat] & write & mask)) {
1023 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1024 "failed: got 0x%08X expected 0x%08X\n",
1025 reg, val, (_test[pat] & write & mask));
1026 *data = reg;
1027 return 1;
1028 }
1029 }
317f66bd 1030
9d5c8243
AK		 1031 return 0;
1032}
1033
1034static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1035 int reg, u32 mask, u32 write)
1036{
2753f4ce 1037 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1038 u32 val;
2753f4ce
AD		 1039 wr32(reg, write & mask);
1040 val = rd32(reg);
9d5c8243
AK		 1041 if ((write & mask) != (val & mask)) {
1042 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1043 " got 0x%08X expected 0x%08X\n", reg,
1044 (val & mask), (write & mask));
1045 *data = reg;
1046 return 1;
1047 }
317f66bd 1048
9d5c8243
AK		 1049 return 0;
1050}
1051
1052#define REG_PATTERN_TEST(reg, mask, write) \
1053 do { \
1054 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1055 return 1; \
1056 } while (0)
1057
1058#define REG_SET_AND_CHECK(reg, mask, write) \
1059 do { \
1060 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1061 return 1; \
1062 } while (0)
1063
1064static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1065{
1066 struct e1000_hw *hw = &adapter->hw;
1067 struct igb_reg_test *test;
1068 u32 value, before, after;
1069 u32 i, toggle;
1070
2d064c06 1071 switch (adapter->hw.mac.type) {
d2ba2ed8
AD		 1072 case e1000_i350:
1073 test = reg_test_i350;
1074 toggle = 0x7FEFF3FF;
1075 break;
55cac248
AD		 1076 case e1000_82580:
1077 test = reg_test_82580;
1078 toggle = 0x7FEFF3FF;
1079 break;
2d064c06
AD		 1080 case e1000_82576:
1081 test = reg_test_82576;
317f66bd 1082 toggle = 0x7FFFF3FF;
2d064c06
AD		 1083 break;
1084 default:
1085 test = reg_test_82575;
317f66bd 1086 toggle = 0x7FFFF3FF;
2d064c06
AD		 1087 break;
1088 }
9d5c8243
AK		 1089
1090 /* Because the status register is such a special case,
1091 * we handle it separately from the rest of the register
1092 * tests. Some bits are read-only, some toggle, and some
1093 * are writable on newer MACs.
1094 */
1095 before = rd32(E1000_STATUS);
1096 value = (rd32(E1000_STATUS) & toggle);
1097 wr32(E1000_STATUS, toggle);
1098 after = rd32(E1000_STATUS) & toggle;
1099 if (value != after) {
1100 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1101 "got: 0x%08X expected: 0x%08X\n", after, value);
1102 *data = 1;
1103 return 1;
1104 }
1105 /* restore previous status */
1106 wr32(E1000_STATUS, before);
1107
1108 /* Perform the remainder of the register test, looping through
1109 * the test table until we either fail or reach the null entry.
1110 */
1111 while (test->reg) {
1112 for (i = 0; i < test->array_len; i++) {
1113 switch (test->test_type) {
1114 case PATTERN_TEST:
2753f4ce
AD		 1115 REG_PATTERN_TEST(test->reg +
1116 (i * test->reg_offset),
9d5c8243
AK		 1117 test->mask,
1118 test->write);
1119 break;
1120 case SET_READ_TEST:
2753f4ce
AD		 1121 REG_SET_AND_CHECK(test->reg +
1122 (i * test->reg_offset),
9d5c8243
AK		 1123 test->mask,
1124 test->write);
1125 break;
1126 case WRITE_NO_TEST:
1127 writel(test->write,
1128 (adapter->hw.hw_addr + test->reg)
2d064c06 1129 + (i * test->reg_offset));
9d5c8243
AK		 1130 break;
1131 case TABLE32_TEST:
1132 REG_PATTERN_TEST(test->reg + (i * 4),
1133 test->mask,
1134 test->write);
1135 break;
1136 case TABLE64_TEST_LO:
1137 REG_PATTERN_TEST(test->reg + (i * 8),
1138 test->mask,
1139 test->write);
1140 break;
1141 case TABLE64_TEST_HI:
1142 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1143 test->mask,
1144 test->write);
1145 break;
1146 }
1147 }
1148 test++;
1149 }
1150
1151 *data = 0;
1152 return 0;
1153}
1154
1155static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1156{
1157 u16 temp;
1158 u16 checksum = 0;
1159 u16 i;
1160
1161 *data = 0;
1162 /* Read and add up the contents of the EEPROM */
1163 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
317f66bd 1164 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
9d5c8243
AK		 1165 *data = 1;
1166 break;
1167 }
1168 checksum += temp;
1169 }
1170
1171 /* If Checksum is not Correct return error else test passed */
1172 if ((checksum != (u16) NVM_SUM) && !(*data))
1173 *data = 2;
1174
1175 return *data;
1176}
1177
1178static irqreturn_t igb_test_intr(int irq, void *data)
1179{
317f66bd 1180 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1181 struct e1000_hw *hw = &adapter->hw;
1182
1183 adapter->test_icr |= rd32(E1000_ICR);
1184
1185 return IRQ_HANDLED;
1186}
1187
1188static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1189{
1190 struct e1000_hw *hw = &adapter->hw;
1191 struct net_device *netdev = adapter->netdev;
2753f4ce 1192 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1193 u32 irq = adapter->pdev->irq;
1194
1195 *data = 0;
1196
1197 /* Hook up test interrupt handler just for this test */
4eefa8f0
AD		 1198 if (adapter->msix_entries) {
1199 if (request_irq(adapter->msix_entries[0].vector,
a0607fd3 1200 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1201 *data = 1;
1202 return -1;
1203 }
4eefa8f0 1204 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1205 shared_int = false;
4eefa8f0 1206 if (request_irq(irq,
a0607fd3 1207 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1208 *data = 1;
1209 return -1;
1210 }
a0607fd3 1211 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1212 netdev->name, adapter)) {
9d5c8243 1213 shared_int = false;
a0607fd3 1214 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1215 netdev->name, adapter)) {
9d5c8243
AK		 1216 *data = 1;
1217 return -1;
1218 }
1219 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1220 (shared_int ? "shared" : "unshared"));
317f66bd 1221
9d5c8243 1222 /* Disable all the interrupts */
4eefa8f0 1223 wr32(E1000_IMC, ~0);
945a5151 1224 wrfl();
9d5c8243
AK		 1225 msleep(10);
1226
2753f4ce 1227 /* Define all writable bits for ICS */
4eefa8f0 1228 switch (hw->mac.type) {
2753f4ce
AD		 1229 case e1000_82575:
1230 ics_mask = 0x37F47EDD;
1231 break;
1232 case e1000_82576:
1233 ics_mask = 0x77D4FBFD;
1234 break;
55cac248
AD		 1235 case e1000_82580:
1236 ics_mask = 0x77DCFED5;
1237 break;
d2ba2ed8
AD		 1238 case e1000_i350:
1239 ics_mask = 0x77DCFED5;
1240 break;
2753f4ce
AD		 1241 default:
1242 ics_mask = 0x7FFFFFFF;
1243 break;
1244 }
1245
9d5c8243 1246 /* Test each interrupt */
2753f4ce 1247 for (; i < 31; i++) {
9d5c8243
AK		 1248 /* Interrupt to test */
1249 mask = 1 << i;
1250
2753f4ce
AD		 1251 if (!(mask & ics_mask))
1252 continue;
1253
9d5c8243
AK		 1254 if (!shared_int) {
1255 /* Disable the interrupt to be reported in
1256 * the cause register and then force the same
1257 * interrupt and see if one gets posted. If
1258 * an interrupt was posted to the bus, the
1259 * test failed.
1260 */
1261 adapter->test_icr = 0;
2753f4ce
AD		 1262
1263 /* Flush any pending interrupts */
1264 wr32(E1000_ICR, ~0);
1265
1266 wr32(E1000_IMC, mask);
1267 wr32(E1000_ICS, mask);
945a5151 1268 wrfl();
9d5c8243
AK		 1269 msleep(10);
1270
1271 if (adapter->test_icr & mask) {
1272 *data = 3;
1273 break;
1274 }
1275 }
1276
1277 /* Enable the interrupt to be reported in
1278 * the cause register and then force the same
1279 * interrupt and see if one gets posted. If
1280 * an interrupt was not posted to the bus, the
1281 * test failed.
1282 */
1283 adapter->test_icr = 0;
2753f4ce
AD		 1284
1285 /* Flush any pending interrupts */
1286 wr32(E1000_ICR, ~0);
1287
9d5c8243
AK		 1288 wr32(E1000_IMS, mask);
1289 wr32(E1000_ICS, mask);
945a5151 1290 wrfl();
9d5c8243
AK		 1291 msleep(10);
1292
1293 if (!(adapter->test_icr & mask)) {
1294 *data = 4;
1295 break;
1296 }
1297
1298 if (!shared_int) {
1299 /* Disable the other interrupts to be reported in
1300 * the cause register and then force the other
1301 * interrupts and see if any get posted. If
1302 * an interrupt was posted to the bus, the
1303 * test failed.
1304 */
1305 adapter->test_icr = 0;
2753f4ce
AD		 1306
1307 /* Flush any pending interrupts */
1308 wr32(E1000_ICR, ~0);
1309
1310 wr32(E1000_IMC, ~mask);
1311 wr32(E1000_ICS, ~mask);
945a5151 1312 wrfl();
9d5c8243
AK		 1313 msleep(10);
1314
2753f4ce 1315 if (adapter->test_icr & mask) {
9d5c8243
AK		 1316 *data = 5;
1317 break;
1318 }
1319 }
1320 }
1321
1322 /* Disable all the interrupts */
2753f4ce 1323 wr32(E1000_IMC, ~0);
945a5151 1324 wrfl();
9d5c8243
AK		 1325 msleep(10);
1326
1327 /* Unhook test interrupt handler */
4eefa8f0
AD		 1328 if (adapter->msix_entries)
1329 free_irq(adapter->msix_entries[0].vector, adapter);
1330 else
1331 free_irq(irq, adapter);
9d5c8243
AK		 1332
1333 return *data;
1334}
1335
1336static void igb_free_desc_rings(struct igb_adapter *adapter)
1337{
d7ee5b3a
AD		 1338 igb_free_tx_resources(&adapter->test_tx_ring);
1339 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1340}
1341
1342static int igb_setup_desc_rings(struct igb_adapter *adapter)
1343{
9d5c8243
AK		 1344 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1345 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1346 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1347 int ret_val;
9d5c8243
AK		 1348
1349 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a 1350 tx_ring->count = IGB_DEFAULT_TXD;
59d71989 1351 tx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1352 tx_ring->netdev = adapter->netdev;
1353 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1354
d7ee5b3a 1355 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1356 ret_val = 1;
1357 goto err_nomem;
1358 }
1359
d7ee5b3a
AD		 1360 igb_setup_tctl(adapter);
1361 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1362
9d5c8243 1363 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a 1364 rx_ring->count = IGB_DEFAULT_RXD;
59d71989 1365 rx_ring->dev = &adapter->pdev->dev;
d7ee5b3a 1366 rx_ring->netdev = adapter->netdev;
d7ee5b3a
AD		 1367 rx_ring->reg_idx = adapter->vfs_allocated_count;
1368
1369 if (igb_setup_rx_resources(rx_ring)) {
1370 ret_val = 3;
9d5c8243
AK		 1371 goto err_nomem;
1372 }
9d5c8243 1373
d7ee5b3a
AD		 1374 /* set the default queue to queue 0 of PF */
1375 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1376
d7ee5b3a
AD		 1377 /* enable receive ring */
1378 igb_setup_rctl(adapter);
1379 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1380
cd392f5c 1381 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1382
1383 return 0;
1384
1385err_nomem:
1386 igb_free_desc_rings(adapter);
1387 return ret_val;
1388}
1389
1390static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1391{
1392 struct e1000_hw *hw = &adapter->hw;
1393
1394 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1395 igb_write_phy_reg(hw, 29, 0x001F);
1396 igb_write_phy_reg(hw, 30, 0x8FFC);
1397 igb_write_phy_reg(hw, 29, 0x001A);
1398 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1399}
1400
1401static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1402{
1403 struct e1000_hw *hw = &adapter->hw;
1404 u32 ctrl_reg = 0;
9d5c8243
AK		 1405
1406 hw->mac.autoneg = false;
1407
1408 if (hw->phy.type == e1000_phy_m88) {
1409 /* Auto-MDI/MDIX Off */
f5f4cf08 1410 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
9d5c8243 1411 /* reset to update Auto-MDI/MDIX */
f5f4cf08 1412 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
9d5c8243 1413 /* autoneg off */
f5f4cf08 1414 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
55cac248
AD		 1415 } else if (hw->phy.type == e1000_phy_82580) {
1416 /* enable MII loopback */
1417 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
9d5c8243
AK		 1418 }
1419
1420 ctrl_reg = rd32(E1000_CTRL);
1421
1422 /* force 1000, set loopback */
f5f4cf08 1423 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1424
1425 /* Now set up the MAC to the same speed/duplex as the PHY. */
1426 ctrl_reg = rd32(E1000_CTRL);
1427 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1428 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1429 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1430 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1431 E1000_CTRL_FD | /* Force Duplex to FULL */
1432 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1433
cdfa9f64 1434 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1435 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1436
1437 wr32(E1000_CTRL, ctrl_reg);
1438
1439 /* Disable the receiver on the PHY so when a cable is plugged in, the
1440 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1441 */
1442 if (hw->phy.type == e1000_phy_m88)
1443 igb_phy_disable_receiver(adapter);
1444
1445 udelay(500);
1446
1447 return 0;
1448}
1449
1450static int igb_set_phy_loopback(struct igb_adapter *adapter)
1451{
1452 return igb_integrated_phy_loopback(adapter);
1453}
1454
1455static int igb_setup_loopback_test(struct igb_adapter *adapter)
1456{
1457 struct e1000_hw *hw = &adapter->hw;
2d064c06 1458 u32 reg;
9d5c8243 1459
317f66bd
AD		 1460 reg = rd32(E1000_CTRL_EXT);
1461
1462 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1463 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
a14bc2bb
RH		 1464 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1465 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1466 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1467 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1468
1469 /* Enable DH89xxCC MPHY for near end loopback */
1470 reg = rd32(E1000_MPHY_ADDR_CTL);
1471 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1472 E1000_MPHY_PCS_CLK_REG_OFFSET;
1473 wr32(E1000_MPHY_ADDR_CTL, reg);
1474
1475 reg = rd32(E1000_MPHY_DATA);
1476 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1477 wr32(E1000_MPHY_DATA, reg);
1478 }
1479
2d064c06
AD		 1480 reg = rd32(E1000_RCTL);
1481 reg |= E1000_RCTL_LBM_TCVR;
1482 wr32(E1000_RCTL, reg);
1483
1484 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1485
1486 reg = rd32(E1000_CTRL);
1487 reg &= ~(E1000_CTRL_RFCE |
1488 E1000_CTRL_TFCE |
1489 E1000_CTRL_LRST);
1490 reg |= E1000_CTRL_SLU |
2753f4ce 1491 E1000_CTRL_FD;
2d064c06
AD		 1492 wr32(E1000_CTRL, reg);
1493
1494 /* Unset switch control to serdes energy detect */
1495 reg = rd32(E1000_CONNSW);
1496 reg &= ~E1000_CONNSW_ENRGSRC;
1497 wr32(E1000_CONNSW, reg);
1498
1499 /* Set PCS register for forced speed */
1500 reg = rd32(E1000_PCS_LCTL);
1501 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1502 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1503 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1504 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1505 E1000_PCS_LCTL_FSD | /* Force Speed */
1506 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1507 wr32(E1000_PCS_LCTL, reg);
1508
9d5c8243 1509 return 0;
9d5c8243
AK		 1510 }
1511
317f66bd 1512 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1513}
1514
1515static void igb_loopback_cleanup(struct igb_adapter *adapter)
1516{
1517 struct e1000_hw *hw = &adapter->hw;
1518 u32 rctl;
1519 u16 phy_reg;
1520
a14bc2bb
RH		 1521 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1522 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1523 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1524 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1525 u32 reg;
1526
1527 /* Disable near end loopback on DH89xxCC */
1528 reg = rd32(E1000_MPHY_ADDR_CTL);
1529 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1530 E1000_MPHY_PCS_CLK_REG_OFFSET;
1531 wr32(E1000_MPHY_ADDR_CTL, reg);
1532
1533 reg = rd32(E1000_MPHY_DATA);
1534 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1535 wr32(E1000_MPHY_DATA, reg);
1536 }
1537
9d5c8243
AK		 1538 rctl = rd32(E1000_RCTL);
1539 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1540 wr32(E1000_RCTL, rctl);
1541
1542 hw->mac.autoneg = true;
f5f4cf08 1543 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1544 if (phy_reg & MII_CR_LOOPBACK) {
1545 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1546 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1547 igb_phy_sw_reset(hw);
1548 }
1549}
1550
1551static void igb_create_lbtest_frame(struct sk_buff *skb,
1552 unsigned int frame_size)
1553{
1554 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1555 frame_size /= 2;
1556 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1557 memset(&skb->data[frame_size + 10], 0xBE, 1);
1558 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1559}
1560
1561static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1562{
317f66bd
AD		 1563 frame_size /= 2;
1564 if (*(skb->data + 3) == 0xFF) {
1565 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1566 (*(skb->data + frame_size + 12) == 0xAF)) {
9d5c8243 1567 return 0;
317f66bd
AD		 1568 }
1569 }
9d5c8243
AK		 1570 return 13;
1571}
1572
ad93d17e
AD		 1573static int igb_clean_test_rings(struct igb_ring *rx_ring,
1574 struct igb_ring *tx_ring,
1575 unsigned int size)
1576{
1577 union e1000_adv_rx_desc *rx_desc;
06034649
AD		 1578 struct igb_rx_buffer *rx_buffer_info;
1579 struct igb_tx_buffer *tx_buffer_info;
6ad4edfc 1580 u16 rx_ntc, tx_ntc, count = 0;
ad93d17e
AD		 1581
1582 /* initialize next to clean and descriptor values */
1583 rx_ntc = rx_ring->next_to_clean;
1584 tx_ntc = tx_ring->next_to_clean;
60136906 1585 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e 1586
3ceb90fd 1587 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
ad93d17e 1588 /* check rx buffer */
06034649 1589 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
ad93d17e
AD		 1590
1591 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
59d71989 1592 dma_unmap_single(rx_ring->dev,
06034649 1593 rx_buffer_info->dma,
44390ca6 1594 IGB_RX_HDR_LEN,
59d71989 1595 DMA_FROM_DEVICE);
06034649 1596 rx_buffer_info->dma = 0;
ad93d17e
AD		 1597
1598 /* verify contents of skb */
06034649 1599 if (!igb_check_lbtest_frame(rx_buffer_info->skb, size))
ad93d17e
AD		 1600 count++;
1601
1602 /* unmap buffer on tx side */
06034649
AD		 1603 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1604 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
ad93d17e
AD		 1605
1606 /* increment rx/tx next to clean counters */
1607 rx_ntc++;
1608 if (rx_ntc == rx_ring->count)
1609 rx_ntc = 0;
1610 tx_ntc++;
1611 if (tx_ntc == tx_ring->count)
1612 tx_ntc = 0;
1613
1614 /* fetch next descriptor */
60136906 1615 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e
AD		 1616 }
1617
1618 /* re-map buffers to ring, store next to clean values */
cd392f5c 1619 igb_alloc_rx_buffers(rx_ring, count);
ad93d17e
AD		 1620 rx_ring->next_to_clean = rx_ntc;
1621 tx_ring->next_to_clean = tx_ntc;
1622
1623 return count;
1624}
1625
9d5c8243
AK		 1626static int igb_run_loopback_test(struct igb_adapter *adapter)
1627{
9d5c8243
AK		 1628 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1629 struct igb_ring *rx_ring = &adapter->test_rx_ring;
6ad4edfc
AD		 1630 u16 i, j, lc, good_cnt;
1631 int ret_val = 0;
44390ca6 1632 unsigned int size = IGB_RX_HDR_LEN;
ad93d17e
AD		 1633 netdev_tx_t tx_ret_val;
1634 struct sk_buff *skb;
1635
1636 /* allocate test skb */
1637 skb = alloc_skb(size, GFP_KERNEL);
1638 if (!skb)
1639 return 11;
9d5c8243 1640
ad93d17e
AD		 1641 /* place data into test skb */
1642 igb_create_lbtest_frame(skb, size);
1643 skb_put(skb, size);
9d5c8243 1644
317f66bd
AD		 1645 /*
1646 * Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1647 * The idea is to wrap the largest ring a number of times using 64
1648 * send/receive pairs during each loop
1649 */
1650
1651 if (rx_ring->count <= tx_ring->count)
1652 lc = ((tx_ring->count / 64) * 2) + 1;
1653 else
1654 lc = ((rx_ring->count / 64) * 2) + 1;
1655
9d5c8243 1656 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1657 /* reset count of good packets */
9d5c8243 1658 good_cnt = 0;
ad93d17e
AD		 1659
1660 /* place 64 packets on the transmit queue*/
1661 for (i = 0; i < 64; i++) {
1662 skb_get(skb);
cd392f5c 1663 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
ad93d17e 1664 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1665 good_cnt++;
ad93d17e
AD		 1666 }
1667
9d5c8243 1668 if (good_cnt != 64) {
ad93d17e 1669 ret_val = 12;
9d5c8243
AK		 1670 break;
1671 }
ad93d17e
AD		 1672
1673 /* allow 200 milliseconds for packets to go from tx to rx */
1674 msleep(200);
1675
1676 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1677 if (good_cnt != 64) {
1678 ret_val = 13;
9d5c8243
AK		 1679 break;
1680 }
1681 } /* end loop count loop */
ad93d17e
AD		 1682
1683 /* free the original skb */
1684 kfree_skb(skb);
1685
9d5c8243
AK		 1686 return ret_val;
1687}
1688
1689static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1690{
1691 /* PHY loopback cannot be performed if SoL/IDER
1692 * sessions are active */
1693 if (igb_check_reset_block(&adapter->hw)) {
1694 dev_err(&adapter->pdev->dev,
1695 "Cannot do PHY loopback test "
1696 "when SoL/IDER is active.\n");
1697 *data = 0;
1698 goto out;
1699 }
1700 *data = igb_setup_desc_rings(adapter);
1701 if (*data)
1702 goto out;
1703 *data = igb_setup_loopback_test(adapter);
1704 if (*data)
1705 goto err_loopback;
1706 *data = igb_run_loopback_test(adapter);
1707 igb_loopback_cleanup(adapter);
1708
1709err_loopback:
1710 igb_free_desc_rings(adapter);
1711out:
1712 return *data;
1713}
1714
1715static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1716{
1717 struct e1000_hw *hw = &adapter->hw;
1718 *data = 0;
1719 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1720 int i = 0;
1721 hw->mac.serdes_has_link = false;
1722
1723 /* On some blade server designs, link establishment
1724 * could take as long as 2-3 minutes */
1725 do {
1726 hw->mac.ops.check_for_link(&adapter->hw);
1727 if (hw->mac.serdes_has_link)
1728 return *data;
1729 msleep(20);
1730 } while (i++ < 3750);
1731
1732 *data = 1;
1733 } else {
1734 hw->mac.ops.check_for_link(&adapter->hw);
1735 if (hw->mac.autoneg)
1736 msleep(4000);
1737
317f66bd 1738 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1739 *data = 1;
1740 }
1741 return *data;
1742}
1743
1744static void igb_diag_test(struct net_device *netdev,
1745 struct ethtool_test *eth_test, u64 *data)
1746{
1747 struct igb_adapter *adapter = netdev_priv(netdev);
1748 u16 autoneg_advertised;
1749 u8 forced_speed_duplex, autoneg;
1750 bool if_running = netif_running(netdev);
1751
1752 set_bit(__IGB_TESTING, &adapter->state);
1753 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1754 /* Offline tests */
1755
1756 /* save speed, duplex, autoneg settings */
1757 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1758 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1759 autoneg = adapter->hw.mac.autoneg;
1760
1761 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1762
88a268c1
NN		 1763 /* power up link for link test */
1764 igb_power_up_link(adapter);
1765
9d5c8243
AK		 1766 /* Link test performed before hardware reset so autoneg doesn't
1767 * interfere with test result */
1768 if (igb_link_test(adapter, &data[4]))
1769 eth_test->flags |= ETH_TEST_FL_FAILED;
1770
1771 if (if_running)
1772 /* indicate we're in test mode */
1773 dev_close(netdev);
1774 else
1775 igb_reset(adapter);
1776
1777 if (igb_reg_test(adapter, &data[0]))
1778 eth_test->flags |= ETH_TEST_FL_FAILED;
1779
1780 igb_reset(adapter);
1781 if (igb_eeprom_test(adapter, &data[1]))
1782 eth_test->flags |= ETH_TEST_FL_FAILED;
1783
1784 igb_reset(adapter);
1785 if (igb_intr_test(adapter, &data[2]))
1786 eth_test->flags |= ETH_TEST_FL_FAILED;
1787
1788 igb_reset(adapter);
88a268c1
NN		 1789 /* power up link for loopback test */
1790 igb_power_up_link(adapter);
9d5c8243
AK		 1791 if (igb_loopback_test(adapter, &data[3]))
1792 eth_test->flags |= ETH_TEST_FL_FAILED;
1793
1794 /* restore speed, duplex, autoneg settings */
1795 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1796 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1797 adapter->hw.mac.autoneg = autoneg;
1798
1799 /* force this routine to wait until autoneg complete/timeout */
1800 adapter->hw.phy.autoneg_wait_to_complete = true;
1801 igb_reset(adapter);
1802 adapter->hw.phy.autoneg_wait_to_complete = false;
1803
1804 clear_bit(__IGB_TESTING, &adapter->state);
1805 if (if_running)
1806 dev_open(netdev);
1807 } else {
1808 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 1809
1810 /* PHY is powered down when interface is down */
8d420a1b
AD		 1811 if (if_running && igb_link_test(adapter, &data[4]))
1812 eth_test->flags |= ETH_TEST_FL_FAILED;
1813 else
88a268c1 1814 data[4] = 0;
9d5c8243
AK		 1815
1816 /* Online tests aren't run; pass by default */
1817 data[0] = 0;
1818 data[1] = 0;
1819 data[2] = 0;
1820 data[3] = 0;
1821
1822 clear_bit(__IGB_TESTING, &adapter->state);
1823 }
1824 msleep_interruptible(4 * 1000);
1825}
1826
1827static int igb_wol_exclusion(struct igb_adapter *adapter,
1828 struct ethtool_wolinfo *wol)
1829{
1830 struct e1000_hw *hw = &adapter->hw;
1831 int retval = 1; /* fail by default */
1832
1833 switch (hw->device_id) {
1834 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1835 /* WoL not supported */
1836 wol->supported = 0;
1837 break;
1838 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1839 case E1000_DEV_ID_82576_FIBER:
1840 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1841 /* Wake events not supported on port B */
1842 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1843 wol->supported = 0;
1844 break;
1845 }
7dfc16fa
AD		 1846 /* return success for non excluded adapter ports */
1847 retval = 0;
1848 break;
c8ea5ea9 1849 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 1850 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 1851 /* quad port adapters only support WoL on port A */
1852 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1853 wol->supported = 0;
1854 break;
1855 }
1856 /* return success for non excluded adapter ports */
1857 retval = 0;
1858 break;
9d5c8243
AK		 1859 default:
1860 /* dual port cards only support WoL on port A from now on
1861 * unless it was enabled in the eeprom for port B
1862 * so exclude FUNC_1 ports from having WoL enabled */
58b8b042 1863 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
9d5c8243
AK		 1864 !adapter->eeprom_wol) {
1865 wol->supported = 0;
1866 break;
1867 }
1868
1869 retval = 0;
1870 }
1871
1872 return retval;
1873}
1874
1875static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1876{
1877 struct igb_adapter *adapter = netdev_priv(netdev);
1878
1879 wol->supported = WAKE_UCAST | WAKE_MCAST |
22939f06
NN		 1880 WAKE_BCAST | WAKE_MAGIC |
1881 WAKE_PHY;
9d5c8243
AK		 1882 wol->wolopts = 0;
1883
1884 /* this function will set ->supported = 0 and return 1 if wol is not
1885 * supported by this hardware */
e1b86d84
RW		 1886 if (igb_wol_exclusion(adapter, wol) ||
1887 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1888 return;
1889
1890 /* apply any specific unsupported masks here */
1891 switch (adapter->hw.device_id) {
1892 default:
1893 break;
1894 }
1895
1896 if (adapter->wol & E1000_WUFC_EX)
1897 wol->wolopts |= WAKE_UCAST;
1898 if (adapter->wol & E1000_WUFC_MC)
1899 wol->wolopts |= WAKE_MCAST;
1900 if (adapter->wol & E1000_WUFC_BC)
1901 wol->wolopts |= WAKE_BCAST;
1902 if (adapter->wol & E1000_WUFC_MAG)
1903 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 1904 if (adapter->wol & E1000_WUFC_LNKC)
1905 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 1906}
1907
1908static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1909{
1910 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 1911
22939f06 1912 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 1913 return -EOPNOTSUPP;
1914
e1b86d84
RW		 1915 if (igb_wol_exclusion(adapter, wol) ||
1916 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1917 return wol->wolopts ? -EOPNOTSUPP : 0;
1918
9d5c8243
AK		 1919 /* these settings will always override what we currently have */
1920 adapter->wol = 0;
1921
1922 if (wol->wolopts & WAKE_UCAST)
1923 adapter->wol |= E1000_WUFC_EX;
1924 if (wol->wolopts & WAKE_MCAST)
1925 adapter->wol |= E1000_WUFC_MC;
1926 if (wol->wolopts & WAKE_BCAST)
1927 adapter->wol |= E1000_WUFC_BC;
1928 if (wol->wolopts & WAKE_MAGIC)
1929 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 1930 if (wol->wolopts & WAKE_PHY)
1931 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 1932 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1933
9d5c8243
AK		 1934 return 0;
1935}
1936
9d5c8243
AK		 1937/* bit defines for adapter->led_status */
1938#define IGB_LED_ON 0
1939
936db355
JK		 1940static int igb_set_phys_id(struct net_device *netdev,
1941 enum ethtool_phys_id_state state)
9d5c8243
AK		 1942{
1943 struct igb_adapter *adapter = netdev_priv(netdev);
1944 struct e1000_hw *hw = &adapter->hw;
1945
936db355
JK		 1946 switch (state) {
1947 case ETHTOOL_ID_ACTIVE:
1948 igb_blink_led(hw);
1949 return 2;
1950 case ETHTOOL_ID_ON:
1951 igb_blink_led(hw);
1952 break;
1953 case ETHTOOL_ID_OFF:
1954 igb_led_off(hw);
1955 break;
1956 case ETHTOOL_ID_INACTIVE:
1957 igb_led_off(hw);
1958 clear_bit(IGB_LED_ON, &adapter->led_status);
1959 igb_cleanup_led(hw);
1960 break;
1961 }
9d5c8243
AK		 1962
1963 return 0;
1964}
1965
1966static int igb_set_coalesce(struct net_device *netdev,
1967 struct ethtool_coalesce *ec)
1968{
1969 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 1970 int i;
9d5c8243
AK		 1971
1972 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1973 ((ec->rx_coalesce_usecs > 3) &&
1974 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1975 (ec->rx_coalesce_usecs == 2))
1976 return -EINVAL;
1977
4fc82adf
AD		 1978 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1979 ((ec->tx_coalesce_usecs > 3) &&
1980 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1981 (ec->tx_coalesce_usecs == 2))
1982 return -EINVAL;
1983
1984 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
1985 return -EINVAL;
1986
831ec0b4
CW		 1987 /* If ITR is disabled, disable DMAC */
1988 if (ec->rx_coalesce_usecs == 0) {
1989 if (adapter->flags & IGB_FLAG_DMAC)
1990 adapter->flags &= ~IGB_FLAG_DMAC;
1991 }
1992
9d5c8243 1993 /* convert to rate of irq's per second */
4fc82adf
AD		 1994 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
1995 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
1996 else
1997 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
1998
1999 /* convert to rate of irq's per second */
2000 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2001 adapter->tx_itr_setting = adapter->rx_itr_setting;
2002 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2003 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2004 else
2005 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 2006
047e0030
AD		 2007 for (i = 0; i < adapter->num_q_vectors; i++) {
2008 struct igb_q_vector *q_vector = adapter->q_vector[i];
0ba82994
AD		 2009 q_vector->tx.work_limit = adapter->tx_work_limit;
2010 if (q_vector->rx.ring)
4fc82adf
AD		 2011 q_vector->itr_val = adapter->rx_itr_setting;
2012 else
2013 q_vector->itr_val = adapter->tx_itr_setting;
2014 if (q_vector->itr_val && q_vector->itr_val <= 3)
2015 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 2016 q_vector->set_itr = 1;
2017 }
9d5c8243
AK		 2018
2019 return 0;
2020}
2021
2022static int igb_get_coalesce(struct net_device *netdev,
2023 struct ethtool_coalesce *ec)
2024{
2025 struct igb_adapter *adapter = netdev_priv(netdev);
2026
4fc82adf
AD		 2027 if (adapter->rx_itr_setting <= 3)
2028 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 2029 else
4fc82adf
AD		 2030 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2031
2032 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2033 if (adapter->tx_itr_setting <= 3)
2034 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2035 else
2036 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2037 }
9d5c8243
AK		 2038
2039 return 0;
2040}
2041
9d5c8243
AK		 2042static int igb_nway_reset(struct net_device *netdev)
2043{
2044 struct igb_adapter *adapter = netdev_priv(netdev);
2045 if (netif_running(netdev))
2046 igb_reinit_locked(adapter);
2047 return 0;
2048}
2049
2050static int igb_get_sset_count(struct net_device *netdev, int sset)
2051{
2052 switch (sset) {
2053 case ETH_SS_STATS:
2054 return IGB_STATS_LEN;
2055 case ETH_SS_TEST:
2056 return IGB_TEST_LEN;
2057 default:
2058 return -ENOTSUPP;
2059 }
2060}
2061
2062static void igb_get_ethtool_stats(struct net_device *netdev,
2063 struct ethtool_stats *stats, u64 *data)
2064{
2065 struct igb_adapter *adapter = netdev_priv(netdev);
12dcd86b
ED		 2066 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2067 unsigned int start;
2068 struct igb_ring *ring;
2069 int i, j;
128e45eb 2070 char *p;
9d5c8243 2071
12dcd86b
ED		 2072 spin_lock(&adapter->stats64_lock);
2073 igb_update_stats(adapter, net_stats);
317f66bd 2074
9d5c8243 2075 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2076 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2077 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2078 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2079 }
128e45eb
AD		 2080 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2081 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2082 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2083 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2084 }
e21ed353 2085 for (j = 0; j < adapter->num_tx_queues; j++) {
12dcd86b
ED		 2086 u64 restart2;
2087
2088 ring = adapter->tx_ring[j];
2089 do {
2090 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2091 data[i] = ring->tx_stats.packets;
2092 data[i+1] = ring->tx_stats.bytes;
2093 data[i+2] = ring->tx_stats.restart_queue;
2094 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2095 do {
2096 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2097 restart2 = ring->tx_stats.restart_queue2;
2098 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2099 data[i+2] += restart2;
2100
2101 i += IGB_TX_QUEUE_STATS_LEN;
e21ed353 2102 }
9d5c8243 2103 for (j = 0; j < adapter->num_rx_queues; j++) {
12dcd86b
ED		 2104 ring = adapter->rx_ring[j];
2105 do {
2106 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2107 data[i] = ring->rx_stats.packets;
2108 data[i+1] = ring->rx_stats.bytes;
2109 data[i+2] = ring->rx_stats.drops;
2110 data[i+3] = ring->rx_stats.csum_err;
2111 data[i+4] = ring->rx_stats.alloc_failed;
2112 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2113 i += IGB_RX_QUEUE_STATS_LEN;
9d5c8243 2114 }
12dcd86b 2115 spin_unlock(&adapter->stats64_lock);
9d5c8243
AK		 2116}
2117
2118static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2119{
2120 struct igb_adapter *adapter = netdev_priv(netdev);
2121 u8 *p = data;
2122 int i;
2123
2124 switch (stringset) {
2125 case ETH_SS_TEST:
2126 memcpy(data, *igb_gstrings_test,
2127 IGB_TEST_LEN*ETH_GSTRING_LEN);
2128 break;
2129 case ETH_SS_STATS:
2130 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2131 memcpy(p, igb_gstrings_stats[i].stat_string,
2132 ETH_GSTRING_LEN);
2133 p += ETH_GSTRING_LEN;
2134 }
128e45eb
AD		 2135 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2136 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2137 ETH_GSTRING_LEN);
2138 p += ETH_GSTRING_LEN;
2139 }
9d5c8243
AK		 2140 for (i = 0; i < adapter->num_tx_queues; i++) {
2141 sprintf(p, "tx_queue_%u_packets", i);
2142 p += ETH_GSTRING_LEN;
2143 sprintf(p, "tx_queue_%u_bytes", i);
2144 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2145 sprintf(p, "tx_queue_%u_restart", i);
2146 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2147 }
2148 for (i = 0; i < adapter->num_rx_queues; i++) {
2149 sprintf(p, "rx_queue_%u_packets", i);
2150 p += ETH_GSTRING_LEN;
2151 sprintf(p, "rx_queue_%u_bytes", i);
2152 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2153 sprintf(p, "rx_queue_%u_drops", i);
2154 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2155 sprintf(p, "rx_queue_%u_csum_err", i);
2156 p += ETH_GSTRING_LEN;
2157 sprintf(p, "rx_queue_%u_alloc_failed", i);
2158 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2159 }
2160/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2161 break;
2162 }
2163}
2164
749ab2cd
YZ		 2165static int igb_ethtool_begin(struct net_device *netdev)
2166{
2167 struct igb_adapter *adapter = netdev_priv(netdev);
2168 pm_runtime_get_sync(&adapter->pdev->dev);
2169 return 0;
2170}
2171
2172static void igb_ethtool_complete(struct net_device *netdev)
2173{
2174 struct igb_adapter *adapter = netdev_priv(netdev);
2175 pm_runtime_put(&adapter->pdev->dev);
2176}
2177
0fc0b732 2178static const struct ethtool_ops igb_ethtool_ops = {
9d5c8243
AK		 2179 .get_settings = igb_get_settings,
2180 .set_settings = igb_set_settings,
2181 .get_drvinfo = igb_get_drvinfo,
2182 .get_regs_len = igb_get_regs_len,
2183 .get_regs = igb_get_regs,
2184 .get_wol = igb_get_wol,
2185 .set_wol = igb_set_wol,
2186 .get_msglevel = igb_get_msglevel,
2187 .set_msglevel = igb_set_msglevel,
2188 .nway_reset = igb_nway_reset,
3145535a 2189 .get_link = igb_get_link,
9d5c8243
AK		 2190 .get_eeprom_len = igb_get_eeprom_len,
2191 .get_eeprom = igb_get_eeprom,
2192 .set_eeprom = igb_set_eeprom,
2193 .get_ringparam = igb_get_ringparam,
2194 .set_ringparam = igb_set_ringparam,
2195 .get_pauseparam = igb_get_pauseparam,
2196 .set_pauseparam = igb_set_pauseparam,
9d5c8243
AK		 2197 .self_test = igb_diag_test,
2198 .get_strings = igb_get_strings,
936db355 2199 .set_phys_id = igb_set_phys_id,
9d5c8243
AK		 2200 .get_sset_count = igb_get_sset_count,
2201 .get_ethtool_stats = igb_get_ethtool_stats,
2202 .get_coalesce = igb_get_coalesce,
2203 .set_coalesce = igb_set_coalesce,
749ab2cd
YZ		 2204 .begin = igb_ethtool_begin,
2205 .complete = igb_ethtool_complete,
9d5c8243
AK		 2206};
2207
2208void igb_set_ethtool_ops(struct net_device *netdev)
2209{
2210 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2211}
Linux kernel - Deliverables
This page took 0.595286 seconds and 5 git commands to generate.