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igb: Change to use statically allocated array for MSIx entries
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
d43c36dc 37#include <linux/sched.h>
5a0e3ad6 38#include <linux/slab.h>
749ab2cd 39#include <linux/pm_runtime.h>
1a1c225b 40#include <linux/highmem.h>
87371b9d 41#include <linux/mdio.h>
9d5c8243
AK		 42
43#include "igb.h"
44
45struct igb_stats {
46 char stat_string[ETH_GSTRING_LEN];
47 int sizeof_stat;
48 int stat_offset;
49};
50
128e45eb
AD		 51#define IGB_STAT(_name, _stat) { \
52 .stat_string = _name, \
53 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
54 .stat_offset = offsetof(struct igb_adapter, _stat) \
55}
9d5c8243 56static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 57 IGB_STAT("rx_packets", stats.gprc),
58 IGB_STAT("tx_packets", stats.gptc),
59 IGB_STAT("rx_bytes", stats.gorc),
60 IGB_STAT("tx_bytes", stats.gotc),
61 IGB_STAT("rx_broadcast", stats.bprc),
62 IGB_STAT("tx_broadcast", stats.bptc),
63 IGB_STAT("rx_multicast", stats.mprc),
64 IGB_STAT("tx_multicast", stats.mptc),
65 IGB_STAT("multicast", stats.mprc),
66 IGB_STAT("collisions", stats.colc),
67 IGB_STAT("rx_crc_errors", stats.crcerrs),
68 IGB_STAT("rx_no_buffer_count", stats.rnbc),
69 IGB_STAT("rx_missed_errors", stats.mpc),
70 IGB_STAT("tx_aborted_errors", stats.ecol),
71 IGB_STAT("tx_carrier_errors", stats.tncrs),
72 IGB_STAT("tx_window_errors", stats.latecol),
73 IGB_STAT("tx_abort_late_coll", stats.latecol),
74 IGB_STAT("tx_deferred_ok", stats.dc),
75 IGB_STAT("tx_single_coll_ok", stats.scc),
76 IGB_STAT("tx_multi_coll_ok", stats.mcc),
77 IGB_STAT("tx_timeout_count", tx_timeout_count),
78 IGB_STAT("rx_long_length_errors", stats.roc),
79 IGB_STAT("rx_short_length_errors", stats.ruc),
80 IGB_STAT("rx_align_errors", stats.algnerrc),
81 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
82 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
83 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
84 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
85 IGB_STAT("tx_flow_control_xon", stats.xontxc),
86 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
87 IGB_STAT("rx_long_byte_count", stats.gorc),
88 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
89 IGB_STAT("tx_smbus", stats.mgptc),
90 IGB_STAT("rx_smbus", stats.mgprc),
91 IGB_STAT("dropped_smbus", stats.mgpdc),
0a915b95
CW		 92 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
93 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
94 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
95 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
428f1f71 96 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
fc580751 97 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
128e45eb
AD		 98};
99
100#define IGB_NETDEV_STAT(_net_stat) { \
101 .stat_string = __stringify(_net_stat), \
12dcd86b
ED		 102 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
103 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
128e45eb
AD		 104}
105static const struct igb_stats igb_gstrings_net_stats[] = {
106 IGB_NETDEV_STAT(rx_errors),
107 IGB_NETDEV_STAT(tx_errors),
108 IGB_NETDEV_STAT(tx_dropped),
109 IGB_NETDEV_STAT(rx_length_errors),
110 IGB_NETDEV_STAT(rx_over_errors),
111 IGB_NETDEV_STAT(rx_frame_errors),
112 IGB_NETDEV_STAT(rx_fifo_errors),
113 IGB_NETDEV_STAT(tx_fifo_errors),
114 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 115};
116
128e45eb
AD		 117#define IGB_GLOBAL_STATS_LEN \
118 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
119#define IGB_NETDEV_STATS_LEN \
120 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
121#define IGB_RX_QUEUE_STATS_LEN \
122 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
12dcd86b
ED		 123
124#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
125
9d5c8243 126#define IGB_QUEUE_STATS_LEN \
317f66bd 127 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 128 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 129 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 130 IGB_TX_QUEUE_STATS_LEN))
131#define IGB_STATS_LEN \
132 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
133
9d5c8243
AK		 134static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
135 "Register test (offline)", "Eeprom test (offline)",
136 "Interrupt test (offline)", "Loopback test (offline)",
137 "Link test (on/offline)"
138};
317f66bd 139#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 140
141static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
142{
143 struct igb_adapter *adapter = netdev_priv(netdev);
144 struct e1000_hw *hw = &adapter->hw;
641ac5c0
AA		 145 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
146 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
317f66bd 147 u32 status;
9d5c8243 148
01237139 149 status = rd32(E1000_STATUS);
9d5c8243
AK		 150 if (hw->phy.media_type == e1000_media_type_copper) {
151
152 ecmd->supported = (SUPPORTED_10baseT_Half |
153 SUPPORTED_10baseT_Full |
154 SUPPORTED_100baseT_Half |
155 SUPPORTED_100baseT_Full |
156 SUPPORTED_1000baseT_Full|
157 SUPPORTED_Autoneg |
42f3c43b
AA		 158 SUPPORTED_TP |
159 SUPPORTED_Pause);
160 ecmd->advertising = ADVERTISED_TP;
9d5c8243
AK		 161
162 if (hw->mac.autoneg == 1) {
163 ecmd->advertising |= ADVERTISED_Autoneg;
164 /* the e1000 autoneg seems to match ethtool nicely */
165 ecmd->advertising |= hw->phy.autoneg_advertised;
166 }
167
168 ecmd->port = PORT_TP;
169 ecmd->phy_address = hw->phy.addr;
f502ef7d 170 ecmd->transceiver = XCVR_INTERNAL;
9d5c8243 171 } else {
641ac5c0 172 ecmd->supported = (SUPPORTED_FIBRE |
01237139 173 SUPPORTED_1000baseKX_Full |
ceb5f13b
CW		 174 SUPPORTED_Autoneg |
175 SUPPORTED_Pause);
01237139
CW		 176 ecmd->advertising = (ADVERTISED_FIBRE |
177 ADVERTISED_1000baseKX_Full);
178 if (hw->mac.type == e1000_i354) {
179 if ((hw->device_id ==
180 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
181 !(status & E1000_STATUS_2P5_SKU_OVER)) {
182 ecmd->supported |= SUPPORTED_2500baseX_Full;
183 ecmd->supported &=
184 ~SUPPORTED_1000baseKX_Full;
185 ecmd->advertising |= ADVERTISED_2500baseX_Full;
186 ecmd->advertising &=
187 ~ADVERTISED_1000baseKX_Full;
188 }
641ac5c0
AA		 189 }
190 if (eth_flags->e100_base_fx) {
191 ecmd->supported |= SUPPORTED_100baseT_Full;
192 ecmd->advertising |= ADVERTISED_100baseT_Full;
ceb5f13b 193 }
f502ef7d
AA		 194 if (hw->mac.autoneg == 1)
195 ecmd->advertising |= ADVERTISED_Autoneg;
9d5c8243
AK		 196
197 ecmd->port = PORT_FIBRE;
f502ef7d 198 ecmd->transceiver = XCVR_EXTERNAL;
9d5c8243 199 }
373e6978
AA		 200 if (hw->mac.autoneg != 1)
201 ecmd->advertising &= ~(ADVERTISED_Pause |
202 ADVERTISED_Asym_Pause);
203
01237139
CW		 204 switch (hw->fc.requested_mode) {
205 case e1000_fc_full:
373e6978 206 ecmd->advertising |= ADVERTISED_Pause;
01237139
CW		 207 break;
208 case e1000_fc_rx_pause:
373e6978
AA		 209 ecmd->advertising |= (ADVERTISED_Pause |
210 ADVERTISED_Asym_Pause);
01237139
CW		 211 break;
212 case e1000_fc_tx_pause:
373e6978 213 ecmd->advertising |= ADVERTISED_Asym_Pause;
01237139
CW		 214 break;
215 default:
373e6978
AA		 216 ecmd->advertising &= ~(ADVERTISED_Pause |
217 ADVERTISED_Asym_Pause);
01237139 218 }
317f66bd 219 if (status & E1000_STATUS_LU) {
01237139
CW		 220 if ((status & E1000_STATUS_2P5_SKU) &&
221 !(status & E1000_STATUS_2P5_SKU_OVER)) {
222 ecmd->speed = SPEED_2500;
41fcfbea 223 } else if (status & E1000_STATUS_SPEED_1000) {
ceb5f13b 224 ecmd->speed = SPEED_1000;
41fcfbea 225 } else if (status & E1000_STATUS_SPEED_100) {
ceb5f13b 226 ecmd->speed = SPEED_100;
41fcfbea 227 } else {
ceb5f13b 228 ecmd->speed = SPEED_10;
41fcfbea 229 }
317f66bd
AD		 230 if ((status & E1000_STATUS_FD) ||
231 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 232 ecmd->duplex = DUPLEX_FULL;
233 else
234 ecmd->duplex = DUPLEX_HALF;
235 } else {
ceb5f13b 236 ecmd->speed = -1;
9d5c8243
AK		 237 ecmd->duplex = -1;
238 }
f502ef7d
AA		 239 if ((hw->phy.media_type == e1000_media_type_fiber) ||
240 hw->mac.autoneg)
241 ecmd->autoneg = AUTONEG_ENABLE;
242 else
243 ecmd->autoneg = AUTONEG_DISABLE;
8376dad0
JB		 244
245 /* MDI-X => 2; MDI =>1; Invalid =>0 */
246 if (hw->phy.media_type == e1000_media_type_copper)
247 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
248 ETH_TP_MDI;
249 else
250 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
251
252 if (hw->phy.mdix == AUTO_ALL_MODES)
253 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
254 else
255 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
256
9d5c8243
AK		 257 return 0;
258}
259
260static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
261{
262 struct igb_adapter *adapter = netdev_priv(netdev);
263 struct e1000_hw *hw = &adapter->hw;
264
265 /* When SoL/IDER sessions are active, autoneg/speed/duplex
b980ac18
JK		 266 * cannot be changed
267 */
9d5c8243 268 if (igb_check_reset_block(hw)) {
d836200a
JJ		 269 dev_err(&adapter->pdev->dev,
270 "Cannot change link characteristics when SoL/IDER is active.\n");
9d5c8243
AK		 271 return -EINVAL;
272 }
273
b980ac18 274 /* MDI setting is only allowed when autoneg enabled because
8376dad0
JB		 275 * some hardware doesn't allow MDI setting when speed or
276 * duplex is forced.
277 */
278 if (ecmd->eth_tp_mdix_ctrl) {
279 if (hw->phy.media_type != e1000_media_type_copper)
280 return -EOPNOTSUPP;
281
282 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
283 (ecmd->autoneg != AUTONEG_ENABLE)) {
284 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
285 return -EINVAL;
286 }
287 }
288
9d5c8243
AK		 289 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
290 msleep(1);
291
292 if (ecmd->autoneg == AUTONEG_ENABLE) {
293 hw->mac.autoneg = 1;
f502ef7d
AA		 294 if (hw->phy.media_type == e1000_media_type_fiber) {
295 hw->phy.autoneg_advertised = ecmd->advertising |
296 ADVERTISED_FIBRE |
297 ADVERTISED_Autoneg;
ceb5f13b
CW		 298 switch (adapter->link_speed) {
299 case SPEED_2500:
300 hw->phy.autoneg_advertised =
301 ADVERTISED_2500baseX_Full;
302 break;
303 case SPEED_1000:
f502ef7d
AA		 304 hw->phy.autoneg_advertised =
305 ADVERTISED_1000baseT_Full;
ceb5f13b
CW		 306 break;
307 case SPEED_100:
f502ef7d
AA		 308 hw->phy.autoneg_advertised =
309 ADVERTISED_100baseT_Full;
ceb5f13b
CW		 310 break;
311 default:
312 break;
313 }
f502ef7d
AA		 314 } else {
315 hw->phy.autoneg_advertised = ecmd->advertising |
316 ADVERTISED_TP |
317 ADVERTISED_Autoneg;
318 }
9d5c8243 319 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 320 if (adapter->fc_autoneg)
321 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 322 } else {
25db0338 323 u32 speed = ethtool_cmd_speed(ecmd);
8376dad0 324 /* calling this overrides forced MDI setting */
14ad2513 325 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
9d5c8243
AK		 326 clear_bit(__IGB_RESETTING, &adapter->state);
327 return -EINVAL;
328 }
dcc3ae9a 329 }
9d5c8243 330
8376dad0
JB		 331 /* MDI-X => 2; MDI => 1; Auto => 3 */
332 if (ecmd->eth_tp_mdix_ctrl) {
b980ac18 333 /* fix up the value for auto (3 => 0) as zero is mapped
8376dad0
JB		 334 * internally to auto
335 */
336 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
337 hw->phy.mdix = AUTO_ALL_MODES;
338 else
339 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
340 }
341
9d5c8243 342 /* reset the link */
9d5c8243
AK		 343 if (netif_running(adapter->netdev)) {
344 igb_down(adapter);
345 igb_up(adapter);
346 } else
347 igb_reset(adapter);
348
349 clear_bit(__IGB_RESETTING, &adapter->state);
350 return 0;
351}
352
3145535a
NN		 353static u32 igb_get_link(struct net_device *netdev)
354{
355 struct igb_adapter *adapter = netdev_priv(netdev);
356 struct e1000_mac_info *mac = &adapter->hw.mac;
357
b980ac18 358 /* If the link is not reported up to netdev, interrupts are disabled,
3145535a
NN		 359 * and so the physical link state may have changed since we last
360 * looked. Set get_link_status to make sure that the true link
361 * state is interrogated, rather than pulling a cached and possibly
362 * stale link state from the driver.
363 */
364 if (!netif_carrier_ok(netdev))
365 mac->get_link_status = 1;
366
367 return igb_has_link(adapter);
368}
369
9d5c8243
AK		 370static void igb_get_pauseparam(struct net_device *netdev,
371 struct ethtool_pauseparam *pause)
372{
373 struct igb_adapter *adapter = netdev_priv(netdev);
374 struct e1000_hw *hw = &adapter->hw;
375
376 pause->autoneg =
377 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
378
0cce119a 379 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 380 pause->rx_pause = 1;
0cce119a 381 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 382 pause->tx_pause = 1;
0cce119a 383 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 384 pause->rx_pause = 1;
385 pause->tx_pause = 1;
386 }
387}
388
389static int igb_set_pauseparam(struct net_device *netdev,
390 struct ethtool_pauseparam *pause)
391{
392 struct igb_adapter *adapter = netdev_priv(netdev);
393 struct e1000_hw *hw = &adapter->hw;
394 int retval = 0;
395
373e6978
AA		 396 /* 100basefx does not support setting link flow control */
397 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
398 return -EINVAL;
399
9d5c8243
AK		 400 adapter->fc_autoneg = pause->autoneg;
401
402 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
403 msleep(1);
404
9d5c8243 405 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 406 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 407 if (netif_running(adapter->netdev)) {
408 igb_down(adapter);
409 igb_up(adapter);
317f66bd 410 } else {
9d5c8243 411 igb_reset(adapter);
317f66bd 412 }
0cce119a
AD		 413 } else {
414 if (pause->rx_pause && pause->tx_pause)
415 hw->fc.requested_mode = e1000_fc_full;
416 else if (pause->rx_pause && !pause->tx_pause)
417 hw->fc.requested_mode = e1000_fc_rx_pause;
418 else if (!pause->rx_pause && pause->tx_pause)
419 hw->fc.requested_mode = e1000_fc_tx_pause;
420 else if (!pause->rx_pause && !pause->tx_pause)
421 hw->fc.requested_mode = e1000_fc_none;
422
423 hw->fc.current_mode = hw->fc.requested_mode;
424
dcc3ae9a
AD		 425 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
426 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 427 }
9d5c8243
AK		 428
429 clear_bit(__IGB_RESETTING, &adapter->state);
430 return retval;
431}
432
9d5c8243
AK		 433static u32 igb_get_msglevel(struct net_device *netdev)
434{
435 struct igb_adapter *adapter = netdev_priv(netdev);
436 return adapter->msg_enable;
437}
438
439static void igb_set_msglevel(struct net_device *netdev, u32 data)
440{
441 struct igb_adapter *adapter = netdev_priv(netdev);
442 adapter->msg_enable = data;
443}
444
445static int igb_get_regs_len(struct net_device *netdev)
446{
7e3b4ffb 447#define IGB_REGS_LEN 739
9d5c8243
AK		 448 return IGB_REGS_LEN * sizeof(u32);
449}
450
451static void igb_get_regs(struct net_device *netdev,
452 struct ethtool_regs *regs, void *p)
453{
454 struct igb_adapter *adapter = netdev_priv(netdev);
455 struct e1000_hw *hw = &adapter->hw;
456 u32 *regs_buff = p;
457 u8 i;
458
459 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
460
461 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
462
463 /* General Registers */
464 regs_buff[0] = rd32(E1000_CTRL);
465 regs_buff[1] = rd32(E1000_STATUS);
466 regs_buff[2] = rd32(E1000_CTRL_EXT);
467 regs_buff[3] = rd32(E1000_MDIC);
468 regs_buff[4] = rd32(E1000_SCTL);
469 regs_buff[5] = rd32(E1000_CONNSW);
470 regs_buff[6] = rd32(E1000_VET);
471 regs_buff[7] = rd32(E1000_LEDCTL);
472 regs_buff[8] = rd32(E1000_PBA);
473 regs_buff[9] = rd32(E1000_PBS);
474 regs_buff[10] = rd32(E1000_FRTIMER);
475 regs_buff[11] = rd32(E1000_TCPTIMER);
476
477 /* NVM Register */
478 regs_buff[12] = rd32(E1000_EECD);
479
480 /* Interrupt */
fe59de38 481 /* Reading EICS for EICR because they read the
b980ac18
JK		 482 * same but EICS does not clear on read
483 */
fe59de38 484 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 485 regs_buff[14] = rd32(E1000_EICS);
486 regs_buff[15] = rd32(E1000_EIMS);
487 regs_buff[16] = rd32(E1000_EIMC);
488 regs_buff[17] = rd32(E1000_EIAC);
489 regs_buff[18] = rd32(E1000_EIAM);
fe59de38 490 /* Reading ICS for ICR because they read the
b980ac18
JK		 491 * same but ICS does not clear on read
492 */
fe59de38 493 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 494 regs_buff[20] = rd32(E1000_ICS);
495 regs_buff[21] = rd32(E1000_IMS);
496 regs_buff[22] = rd32(E1000_IMC);
497 regs_buff[23] = rd32(E1000_IAC);
498 regs_buff[24] = rd32(E1000_IAM);
499 regs_buff[25] = rd32(E1000_IMIRVP);
500
501 /* Flow Control */
502 regs_buff[26] = rd32(E1000_FCAL);
503 regs_buff[27] = rd32(E1000_FCAH);
504 regs_buff[28] = rd32(E1000_FCTTV);
505 regs_buff[29] = rd32(E1000_FCRTL);
506 regs_buff[30] = rd32(E1000_FCRTH);
507 regs_buff[31] = rd32(E1000_FCRTV);
508
509 /* Receive */
510 regs_buff[32] = rd32(E1000_RCTL);
511 regs_buff[33] = rd32(E1000_RXCSUM);
512 regs_buff[34] = rd32(E1000_RLPML);
513 regs_buff[35] = rd32(E1000_RFCTL);
514 regs_buff[36] = rd32(E1000_MRQC);
e1739522 515 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 516
517 /* Transmit */
518 regs_buff[38] = rd32(E1000_TCTL);
519 regs_buff[39] = rd32(E1000_TCTL_EXT);
520 regs_buff[40] = rd32(E1000_TIPG);
521 regs_buff[41] = rd32(E1000_DTXCTL);
522
523 /* Wake Up */
524 regs_buff[42] = rd32(E1000_WUC);
525 regs_buff[43] = rd32(E1000_WUFC);
526 regs_buff[44] = rd32(E1000_WUS);
527 regs_buff[45] = rd32(E1000_IPAV);
528 regs_buff[46] = rd32(E1000_WUPL);
529
530 /* MAC */
531 regs_buff[47] = rd32(E1000_PCS_CFG0);
532 regs_buff[48] = rd32(E1000_PCS_LCTL);
533 regs_buff[49] = rd32(E1000_PCS_LSTAT);
534 regs_buff[50] = rd32(E1000_PCS_ANADV);
535 regs_buff[51] = rd32(E1000_PCS_LPAB);
536 regs_buff[52] = rd32(E1000_PCS_NPTX);
537 regs_buff[53] = rd32(E1000_PCS_LPABNP);
538
539 /* Statistics */
540 regs_buff[54] = adapter->stats.crcerrs;
541 regs_buff[55] = adapter->stats.algnerrc;
542 regs_buff[56] = adapter->stats.symerrs;
543 regs_buff[57] = adapter->stats.rxerrc;
544 regs_buff[58] = adapter->stats.mpc;
545 regs_buff[59] = adapter->stats.scc;
546 regs_buff[60] = adapter->stats.ecol;
547 regs_buff[61] = adapter->stats.mcc;
548 regs_buff[62] = adapter->stats.latecol;
549 regs_buff[63] = adapter->stats.colc;
550 regs_buff[64] = adapter->stats.dc;
551 regs_buff[65] = adapter->stats.tncrs;
552 regs_buff[66] = adapter->stats.sec;
553 regs_buff[67] = adapter->stats.htdpmc;
554 regs_buff[68] = adapter->stats.rlec;
555 regs_buff[69] = adapter->stats.xonrxc;
556 regs_buff[70] = adapter->stats.xontxc;
557 regs_buff[71] = adapter->stats.xoffrxc;
558 regs_buff[72] = adapter->stats.xofftxc;
559 regs_buff[73] = adapter->stats.fcruc;
560 regs_buff[74] = adapter->stats.prc64;
561 regs_buff[75] = adapter->stats.prc127;
562 regs_buff[76] = adapter->stats.prc255;
563 regs_buff[77] = adapter->stats.prc511;
564 regs_buff[78] = adapter->stats.prc1023;
565 regs_buff[79] = adapter->stats.prc1522;
566 regs_buff[80] = adapter->stats.gprc;
567 regs_buff[81] = adapter->stats.bprc;
568 regs_buff[82] = adapter->stats.mprc;
569 regs_buff[83] = adapter->stats.gptc;
570 regs_buff[84] = adapter->stats.gorc;
571 regs_buff[86] = adapter->stats.gotc;
572 regs_buff[88] = adapter->stats.rnbc;
573 regs_buff[89] = adapter->stats.ruc;
574 regs_buff[90] = adapter->stats.rfc;
575 regs_buff[91] = adapter->stats.roc;
576 regs_buff[92] = adapter->stats.rjc;
577 regs_buff[93] = adapter->stats.mgprc;
578 regs_buff[94] = adapter->stats.mgpdc;
579 regs_buff[95] = adapter->stats.mgptc;
580 regs_buff[96] = adapter->stats.tor;
581 regs_buff[98] = adapter->stats.tot;
582 regs_buff[100] = adapter->stats.tpr;
583 regs_buff[101] = adapter->stats.tpt;
584 regs_buff[102] = adapter->stats.ptc64;
585 regs_buff[103] = adapter->stats.ptc127;
586 regs_buff[104] = adapter->stats.ptc255;
587 regs_buff[105] = adapter->stats.ptc511;
588 regs_buff[106] = adapter->stats.ptc1023;
589 regs_buff[107] = adapter->stats.ptc1522;
590 regs_buff[108] = adapter->stats.mptc;
591 regs_buff[109] = adapter->stats.bptc;
592 regs_buff[110] = adapter->stats.tsctc;
593 regs_buff[111] = adapter->stats.iac;
594 regs_buff[112] = adapter->stats.rpthc;
595 regs_buff[113] = adapter->stats.hgptc;
596 regs_buff[114] = adapter->stats.hgorc;
597 regs_buff[116] = adapter->stats.hgotc;
598 regs_buff[118] = adapter->stats.lenerrs;
599 regs_buff[119] = adapter->stats.scvpc;
600 regs_buff[120] = adapter->stats.hrmpc;
601
9d5c8243
AK		 602 for (i = 0; i < 4; i++)
603 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
604 for (i = 0; i < 4; i++)
83ab50a5 605 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 606 for (i = 0; i < 4; i++)
607 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
608 for (i = 0; i < 4; i++)
609 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
610 for (i = 0; i < 4; i++)
611 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
612 for (i = 0; i < 4; i++)
613 regs_buff[141 + i] = rd32(E1000_RDH(i));
614 for (i = 0; i < 4; i++)
615 regs_buff[145 + i] = rd32(E1000_RDT(i));
616 for (i = 0; i < 4; i++)
617 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
618
619 for (i = 0; i < 10; i++)
620 regs_buff[153 + i] = rd32(E1000_EITR(i));
621 for (i = 0; i < 8; i++)
622 regs_buff[163 + i] = rd32(E1000_IMIR(i));
623 for (i = 0; i < 8; i++)
624 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
625 for (i = 0; i < 16; i++)
626 regs_buff[179 + i] = rd32(E1000_RAL(i));
627 for (i = 0; i < 16; i++)
628 regs_buff[195 + i] = rd32(E1000_RAH(i));
629
630 for (i = 0; i < 4; i++)
631 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
632 for (i = 0; i < 4; i++)
633 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
634 for (i = 0; i < 4; i++)
635 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
636 for (i = 0; i < 4; i++)
637 regs_buff[223 + i] = rd32(E1000_TDH(i));
638 for (i = 0; i < 4; i++)
639 regs_buff[227 + i] = rd32(E1000_TDT(i));
640 for (i = 0; i < 4; i++)
641 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
642 for (i = 0; i < 4; i++)
643 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
644 for (i = 0; i < 4; i++)
645 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
646 for (i = 0; i < 4; i++)
647 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
648
649 for (i = 0; i < 4; i++)
650 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
651 for (i = 0; i < 4; i++)
652 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
653 for (i = 0; i < 32; i++)
654 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
655 for (i = 0; i < 128; i++)
656 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
657 for (i = 0; i < 128; i++)
658 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
659 for (i = 0; i < 4; i++)
660 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
661
662 regs_buff[547] = rd32(E1000_TDFH);
663 regs_buff[548] = rd32(E1000_TDFT);
664 regs_buff[549] = rd32(E1000_TDFHS);
665 regs_buff[550] = rd32(E1000_TDFPC);
f96a8a0b
CW		 666
667 if (hw->mac.type > e1000_82580) {
668 regs_buff[551] = adapter->stats.o2bgptc;
669 regs_buff[552] = adapter->stats.b2ospc;
670 regs_buff[553] = adapter->stats.o2bspc;
671 regs_buff[554] = adapter->stats.b2ogprc;
672 }
7e3b4ffb
KS		 673
674 if (hw->mac.type != e1000_82576)
675 return;
676 for (i = 0; i < 12; i++)
677 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
678 for (i = 0; i < 4; i++)
679 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
680 for (i = 0; i < 12; i++)
681 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
682 for (i = 0; i < 12; i++)
683 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
684 for (i = 0; i < 12; i++)
685 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
686 for (i = 0; i < 12; i++)
687 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
688 for (i = 0; i < 12; i++)
689 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
690 for (i = 0; i < 12; i++)
691 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
692
693 for (i = 0; i < 12; i++)
694 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
695 for (i = 0; i < 12; i++)
696 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
697 for (i = 0; i < 12; i++)
698 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
699 for (i = 0; i < 12; i++)
700 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
701 for (i = 0; i < 12; i++)
702 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
703 for (i = 0; i < 12; i++)
704 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
705 for (i = 0; i < 12; i++)
706 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
707 for (i = 0; i < 12; i++)
708 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
9d5c8243
AK		 709}
710
711static int igb_get_eeprom_len(struct net_device *netdev)
712{
713 struct igb_adapter *adapter = netdev_priv(netdev);
714 return adapter->hw.nvm.word_size * 2;
715}
716
717static int igb_get_eeprom(struct net_device *netdev,
718 struct ethtool_eeprom *eeprom, u8 *bytes)
719{
720 struct igb_adapter *adapter = netdev_priv(netdev);
721 struct e1000_hw *hw = &adapter->hw;
722 u16 *eeprom_buff;
723 int first_word, last_word;
724 int ret_val = 0;
725 u16 i;
726
727 if (eeprom->len == 0)
728 return -EINVAL;
729
730 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
731
732 first_word = eeprom->offset >> 1;
733 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
734
735 eeprom_buff = kmalloc(sizeof(u16) *
736 (last_word - first_word + 1), GFP_KERNEL);
737 if (!eeprom_buff)
738 return -ENOMEM;
739
740 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 741 ret_val = hw->nvm.ops.read(hw, first_word,
b980ac18
JK		 742 last_word - first_word + 1,
743 eeprom_buff);
9d5c8243
AK		 744 else {
745 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 746 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
b980ac18 747 &eeprom_buff[i]);
9d5c8243
AK		 748 if (ret_val)
749 break;
750 }
751 }
752
753 /* Device's eeprom is always little-endian, word addressable */
754 for (i = 0; i < last_word - first_word + 1; i++)
755 le16_to_cpus(&eeprom_buff[i]);
756
757 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
758 eeprom->len);
759 kfree(eeprom_buff);
760
761 return ret_val;
762}
763
764static int igb_set_eeprom(struct net_device *netdev,
765 struct ethtool_eeprom *eeprom, u8 *bytes)
766{
767 struct igb_adapter *adapter = netdev_priv(netdev);
768 struct e1000_hw *hw = &adapter->hw;
769 u16 *eeprom_buff;
770 void *ptr;
771 int max_len, first_word, last_word, ret_val = 0;
772 u16 i;
773
774 if (eeprom->len == 0)
775 return -EOPNOTSUPP;
776
a71fc313
FT		 777 if ((hw->mac.type >= e1000_i210) &&
778 !igb_get_flash_presence_i210(hw)) {
f96a8a0b 779 return -EOPNOTSUPP;
a71fc313 780 }
f96a8a0b 781
9d5c8243
AK		 782 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
783 return -EFAULT;
784
785 max_len = hw->nvm.word_size * 2;
786
787 first_word = eeprom->offset >> 1;
788 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
789 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
790 if (!eeprom_buff)
791 return -ENOMEM;
792
793 ptr = (void *)eeprom_buff;
794
795 if (eeprom->offset & 1) {
b980ac18
JK		 796 /* need read/modify/write of first changed EEPROM word
797 * only the second byte of the word is being modified
798 */
312c75ae 799 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 800 &eeprom_buff[0]);
801 ptr++;
802 }
803 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
b980ac18
JK		 804 /* need read/modify/write of last changed EEPROM word
805 * only the first byte of the word is being modified
806 */
312c75ae 807 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 808 &eeprom_buff[last_word - first_word]);
809 }
810
811 /* Device's eeprom is always little-endian, word addressable */
812 for (i = 0; i < last_word - first_word + 1; i++)
813 le16_to_cpus(&eeprom_buff[i]);
814
815 memcpy(ptr, bytes, eeprom->len);
816
817 for (i = 0; i < last_word - first_word + 1; i++)
818 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
819
312c75ae 820 ret_val = hw->nvm.ops.write(hw, first_word,
b980ac18 821 last_word - first_word + 1, eeprom_buff);
9d5c8243 822
2a0a0f1e
CW		 823 /* Update the checksum if nvm write succeeded */
824 if (ret_val == 0)
4322e561 825 hw->nvm.ops.update(hw);
9d5c8243 826
d67974f0 827 igb_set_fw_version(adapter);
9d5c8243
AK		 828 kfree(eeprom_buff);
829 return ret_val;
830}
831
832static void igb_get_drvinfo(struct net_device *netdev,
833 struct ethtool_drvinfo *drvinfo)
834{
835 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 836
612a94d6
RJ		 837 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
838 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
9d5c8243 839
b980ac18 840 /* EEPROM image version # is reported as firmware version # for
d67974f0
CW		 841 * 82575 controllers
842 */
843 strlcpy(drvinfo->fw_version, adapter->fw_version,
844 sizeof(drvinfo->fw_version));
612a94d6
RJ		 845 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
846 sizeof(drvinfo->bus_info));
9d5c8243
AK		 847 drvinfo->n_stats = IGB_STATS_LEN;
848 drvinfo->testinfo_len = IGB_TEST_LEN;
849 drvinfo->regdump_len = igb_get_regs_len(netdev);
850 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
851}
852
853static void igb_get_ringparam(struct net_device *netdev,
854 struct ethtool_ringparam *ring)
855{
856 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 857
858 ring->rx_max_pending = IGB_MAX_RXD;
859 ring->tx_max_pending = IGB_MAX_TXD;
68fd9910
AD		 860 ring->rx_pending = adapter->rx_ring_count;
861 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 862}
863
864static int igb_set_ringparam(struct net_device *netdev,
865 struct ethtool_ringparam *ring)
866{
867 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 868 struct igb_ring *temp_ring;
6d9f4fc4 869 int i, err = 0;
0e15439a 870 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 871
872 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
873 return -EINVAL;
874
0e15439a
AD		 875 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
876 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 877 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
878
0e15439a
AD		 879 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
880 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 881 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
882
68fd9910
AD		 883 if ((new_tx_count == adapter->tx_ring_count) &&
884 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 885 /* nothing to do */
886 return 0;
887 }
888
6d9f4fc4
AD		 889 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
890 msleep(1);
891
892 if (!netif_running(adapter->netdev)) {
893 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 894 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 895 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 896 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 897 adapter->tx_ring_count = new_tx_count;
898 adapter->rx_ring_count = new_rx_count;
899 goto clear_reset;
900 }
901
68fd9910 902 if (adapter->num_tx_queues > adapter->num_rx_queues)
b980ac18
JK		 903 temp_ring = vmalloc(adapter->num_tx_queues *
904 sizeof(struct igb_ring));
68fd9910 905 else
b980ac18
JK		 906 temp_ring = vmalloc(adapter->num_rx_queues *
907 sizeof(struct igb_ring));
68fd9910 908
6d9f4fc4
AD		 909 if (!temp_ring) {
910 err = -ENOMEM;
911 goto clear_reset;
912 }
9d5c8243 913
6d9f4fc4 914 igb_down(adapter);
9d5c8243 915
b980ac18 916 /* We can't just free everything and then setup again,
9d5c8243 917 * because the ISRs in MSI-X mode get passed pointers
b980ac18 918 * to the Tx and Rx ring structs.
9d5c8243 919 */
68fd9910 920 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 921 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 922 memcpy(&temp_ring[i], adapter->tx_ring[i],
923 sizeof(struct igb_ring));
924
68fd9910 925 temp_ring[i].count = new_tx_count;
80785298 926 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 927 if (err) {
68fd9910
AD		 928 while (i) {
929 i--;
930 igb_free_tx_resources(&temp_ring[i]);
931 }
9d5c8243
AK		 932 goto err_setup;
933 }
9d5c8243 934 }
68fd9910 935
3025a446
AD		 936 for (i = 0; i < adapter->num_tx_queues; i++) {
937 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 938
3025a446
AD		 939 memcpy(adapter->tx_ring[i], &temp_ring[i],
940 sizeof(struct igb_ring));
941 }
68fd9910
AD		 942
943 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 944 }
945
3025a446 946 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 947 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 948 memcpy(&temp_ring[i], adapter->rx_ring[i],
949 sizeof(struct igb_ring));
950
68fd9910 951 temp_ring[i].count = new_rx_count;
80785298 952 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 953 if (err) {
68fd9910
AD		 954 while (i) {
955 i--;
956 igb_free_rx_resources(&temp_ring[i]);
957 }
9d5c8243
AK		 958 goto err_setup;
959 }
960
9d5c8243 961 }
68fd9910 962
3025a446
AD		 963 for (i = 0; i < adapter->num_rx_queues; i++) {
964 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 965
3025a446
AD		 966 memcpy(adapter->rx_ring[i], &temp_ring[i],
967 sizeof(struct igb_ring));
968 }
68fd9910
AD		 969
970 adapter->rx_ring_count = new_rx_count;
9d5c8243 971 }
9d5c8243 972err_setup:
6d9f4fc4 973 igb_up(adapter);
68fd9910 974 vfree(temp_ring);
6d9f4fc4
AD		 975clear_reset:
976 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 977 return err;
978}
979
980/* ethtool register test data */
981struct igb_reg_test {
982 u16 reg;
2d064c06
AD		 983 u16 reg_offset;
984 u16 array_len;
985 u16 test_type;
9d5c8243
AK		 986 u32 mask;
987 u32 write;
988};
989
990/* In the hardware, registers are laid out either singly, in arrays
991 * spaced 0x100 bytes apart, or in contiguous tables. We assume
992 * most tests take place on arrays or single registers (handled
993 * as a single-element array) and special-case the tables.
994 * Table tests are always pattern tests.
995 *
996 * We also make provision for some required setup steps by specifying
997 * registers to be written without any read-back testing.
998 */
999
1000#define PATTERN_TEST 1
1001#define SET_READ_TEST 2
1002#define WRITE_NO_TEST 3
1003#define TABLE32_TEST 4
1004#define TABLE64_TEST_LO 5
1005#define TABLE64_TEST_HI 6
1006
f96a8a0b
CW		 1007/* i210 reg test */
1008static struct igb_reg_test reg_test_i210[] = {
1009 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1010 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1011 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1012 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1013 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1014 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1015 /* RDH is read-only for i210, only test RDT. */
1016 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1017 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1018 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1019 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1020 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1021 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1022 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1023 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1024 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1025 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1026 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1027 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1028 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1029 0xFFFFFFFF, 0xFFFFFFFF },
1030 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1031 0x900FFFFF, 0xFFFFFFFF },
1032 { E1000_MTA, 0, 128, TABLE32_TEST,
1033 0xFFFFFFFF, 0xFFFFFFFF },
1034 { 0, 0, 0, 0, 0 }
1035};
1036
d2ba2ed8
AD		 1037/* i350 reg test */
1038static struct igb_reg_test reg_test_i350[] = {
1039 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1040 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1041 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1042 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1043 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1044 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1045 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1046 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1047 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1048 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1049 /* RDH is read-only for i350, only test RDT. */
1050 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1051 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1052 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1053 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1054 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1055 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1056 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1057 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1058 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1059 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1060 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1061 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1062 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1063 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1064 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1065 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1066 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1067 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1068 0xFFFFFFFF, 0xFFFFFFFF },
1069 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1070 0xC3FFFFFF, 0xFFFFFFFF },
1071 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1072 0xFFFFFFFF, 0xFFFFFFFF },
1073 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1074 0xC3FFFFFF, 0xFFFFFFFF },
1075 { E1000_MTA, 0, 128, TABLE32_TEST,
1076 0xFFFFFFFF, 0xFFFFFFFF },
1077 { 0, 0, 0, 0 }
1078};
1079
55cac248
AD		 1080/* 82580 reg test */
1081static struct igb_reg_test reg_test_82580[] = {
1082 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1083 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1084 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1085 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1086 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1087 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1088 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1089 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1090 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1091 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1092 /* RDH is read-only for 82580, only test RDT. */
1093 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1094 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1095 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1096 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1097 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1098 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1099 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1100 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1101 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1102 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1103 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1104 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1105 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1106 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1107 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1108 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1109 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1110 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1111 0xFFFFFFFF, 0xFFFFFFFF },
1112 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1113 0x83FFFFFF, 0xFFFFFFFF },
1114 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1115 0xFFFFFFFF, 0xFFFFFFFF },
1116 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1117 0x83FFFFFF, 0xFFFFFFFF },
1118 { E1000_MTA, 0, 128, TABLE32_TEST,
1119 0xFFFFFFFF, 0xFFFFFFFF },
1120 { 0, 0, 0, 0 }
1121};
1122
2d064c06
AD		 1123/* 82576 reg test */
1124static struct igb_reg_test reg_test_82576[] = {
1125 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1126 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1127 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1128 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1129 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1130 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1131 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1132 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1133 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1134 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1135 /* Enable all RX queues before testing. */
1136 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1137 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 1138 /* RDH is read-only for 82576, only test RDT. */
1139 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 1140 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 1141 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 1142 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 1143 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1144 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1145 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1146 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1147 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1148 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1149 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1150 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 1152 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1153 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1154 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1155 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1156 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1157 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1158 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1159 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1160 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1161 { 0, 0, 0, 0 }
1162};
1163
1164/* 82575 register test */
9d5c8243 1165static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 1166 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1167 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1168 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1169 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1171 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1172 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 1173 /* Enable all four RX queues before testing. */
2d064c06 1174 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 1175 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 1176 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1177 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1178 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1179 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1180 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1181 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1182 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1183 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1184 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1185 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1186 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1187 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1188 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1189 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1190 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1191 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1192 { 0, 0, 0, 0 }
1193};
1194
1195static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1196 int reg, u32 mask, u32 write)
1197{
2753f4ce 1198 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1199 u32 pat, val;
317f66bd 1200 static const u32 _test[] =
9d5c8243
AK		 1201 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1202 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce 1203 wr32(reg, (_test[pat] & write));
93ed8359 1204 val = rd32(reg) & mask;
9d5c8243 1205 if (val != (_test[pat] & write & mask)) {
d836200a
JJ		 1206 dev_err(&adapter->pdev->dev,
1207 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
9d5c8243
AK		 1208 reg, val, (_test[pat] & write & mask));
1209 *data = reg;
1210 return 1;
1211 }
1212 }
317f66bd 1213
9d5c8243
AK		 1214 return 0;
1215}
1216
1217static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1218 int reg, u32 mask, u32 write)
1219{
2753f4ce 1220 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1221 u32 val;
2753f4ce
AD		 1222 wr32(reg, write & mask);
1223 val = rd32(reg);
9d5c8243 1224 if ((write & mask) != (val & mask)) {
d836200a
JJ		 1225 dev_err(&adapter->pdev->dev,
1226 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg,
9d5c8243
AK		 1227 (val & mask), (write & mask));
1228 *data = reg;
1229 return 1;
1230 }
317f66bd 1231
9d5c8243
AK		 1232 return 0;
1233}
1234
1235#define REG_PATTERN_TEST(reg, mask, write) \
1236 do { \
1237 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1238 return 1; \
1239 } while (0)
1240
1241#define REG_SET_AND_CHECK(reg, mask, write) \
1242 do { \
1243 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1244 return 1; \
1245 } while (0)
1246
1247static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1248{
1249 struct e1000_hw *hw = &adapter->hw;
1250 struct igb_reg_test *test;
1251 u32 value, before, after;
1252 u32 i, toggle;
1253
2d064c06 1254 switch (adapter->hw.mac.type) {
d2ba2ed8 1255 case e1000_i350:
ceb5f13b 1256 case e1000_i354:
d2ba2ed8
AD		 1257 test = reg_test_i350;
1258 toggle = 0x7FEFF3FF;
1259 break;
f96a8a0b
CW		 1260 case e1000_i210:
1261 case e1000_i211:
1262 test = reg_test_i210;
1263 toggle = 0x7FEFF3FF;
1264 break;
55cac248
AD		 1265 case e1000_82580:
1266 test = reg_test_82580;
1267 toggle = 0x7FEFF3FF;
1268 break;
2d064c06
AD		 1269 case e1000_82576:
1270 test = reg_test_82576;
317f66bd 1271 toggle = 0x7FFFF3FF;
2d064c06
AD		 1272 break;
1273 default:
1274 test = reg_test_82575;
317f66bd 1275 toggle = 0x7FFFF3FF;
2d064c06
AD		 1276 break;
1277 }
9d5c8243
AK		 1278
1279 /* Because the status register is such a special case,
1280 * we handle it separately from the rest of the register
1281 * tests. Some bits are read-only, some toggle, and some
1282 * are writable on newer MACs.
1283 */
1284 before = rd32(E1000_STATUS);
1285 value = (rd32(E1000_STATUS) & toggle);
1286 wr32(E1000_STATUS, toggle);
1287 after = rd32(E1000_STATUS) & toggle;
1288 if (value != after) {
d836200a
JJ		 1289 dev_err(&adapter->pdev->dev,
1290 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1291 after, value);
9d5c8243
AK		 1292 *data = 1;
1293 return 1;
1294 }
1295 /* restore previous status */
1296 wr32(E1000_STATUS, before);
1297
1298 /* Perform the remainder of the register test, looping through
1299 * the test table until we either fail or reach the null entry.
1300 */
1301 while (test->reg) {
1302 for (i = 0; i < test->array_len; i++) {
1303 switch (test->test_type) {
1304 case PATTERN_TEST:
2753f4ce
AD		 1305 REG_PATTERN_TEST(test->reg +
1306 (i * test->reg_offset),
9d5c8243
AK		 1307 test->mask,
1308 test->write);
1309 break;
1310 case SET_READ_TEST:
2753f4ce
AD		 1311 REG_SET_AND_CHECK(test->reg +
1312 (i * test->reg_offset),
9d5c8243
AK		 1313 test->mask,
1314 test->write);
1315 break;
1316 case WRITE_NO_TEST:
1317 writel(test->write,
1318 (adapter->hw.hw_addr + test->reg)
2d064c06 1319 + (i * test->reg_offset));
9d5c8243
AK		 1320 break;
1321 case TABLE32_TEST:
1322 REG_PATTERN_TEST(test->reg + (i * 4),
1323 test->mask,
1324 test->write);
1325 break;
1326 case TABLE64_TEST_LO:
1327 REG_PATTERN_TEST(test->reg + (i * 8),
1328 test->mask,
1329 test->write);
1330 break;
1331 case TABLE64_TEST_HI:
1332 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1333 test->mask,
1334 test->write);
1335 break;
1336 }
1337 }
1338 test++;
1339 }
1340
1341 *data = 0;
1342 return 0;
1343}
1344
1345static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1346{
53b87ce3
CW		 1347 struct e1000_hw *hw = &adapter->hw;
1348
9d5c8243 1349 *data = 0;
9d5c8243 1350
53b87ce3
CW		 1351 /* Validate eeprom on all parts but flashless */
1352 switch (hw->mac.type) {
1353 case e1000_i210:
1354 case e1000_i211:
1355 if (igb_get_flash_presence_i210(hw)) {
1356 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1357 *data = 2;
1358 }
1359 break;
1360 default:
f96a8a0b
CW		 1361 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1362 *data = 2;
53b87ce3 1363 break;
f96a8a0b 1364 }
9d5c8243
AK		 1365
1366 return *data;
1367}
1368
1369static irqreturn_t igb_test_intr(int irq, void *data)
1370{
317f66bd 1371 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1372 struct e1000_hw *hw = &adapter->hw;
1373
1374 adapter->test_icr |= rd32(E1000_ICR);
1375
1376 return IRQ_HANDLED;
1377}
1378
1379static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1380{
1381 struct e1000_hw *hw = &adapter->hw;
1382 struct net_device *netdev = adapter->netdev;
2753f4ce 1383 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1384 u32 irq = adapter->pdev->irq;
1385
1386 *data = 0;
1387
1388 /* Hook up test interrupt handler just for this test */
cd14ef54 1389 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
4eefa8f0 1390 if (request_irq(adapter->msix_entries[0].vector,
a0607fd3 1391 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1392 *data = 1;
1393 return -1;
1394 }
4eefa8f0 1395 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1396 shared_int = false;
4eefa8f0 1397 if (request_irq(irq,
a0607fd3 1398 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1399 *data = 1;
1400 return -1;
1401 }
a0607fd3 1402 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1403 netdev->name, adapter)) {
9d5c8243 1404 shared_int = false;
a0607fd3 1405 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1406 netdev->name, adapter)) {
9d5c8243
AK		 1407 *data = 1;
1408 return -1;
1409 }
1410 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1411 (shared_int ? "shared" : "unshared"));
317f66bd 1412
9d5c8243 1413 /* Disable all the interrupts */
4eefa8f0 1414 wr32(E1000_IMC, ~0);
945a5151 1415 wrfl();
9d5c8243
AK		 1416 msleep(10);
1417
2753f4ce 1418 /* Define all writable bits for ICS */
4eefa8f0 1419 switch (hw->mac.type) {
2753f4ce
AD		 1420 case e1000_82575:
1421 ics_mask = 0x37F47EDD;
1422 break;
1423 case e1000_82576:
1424 ics_mask = 0x77D4FBFD;
1425 break;
55cac248
AD		 1426 case e1000_82580:
1427 ics_mask = 0x77DCFED5;
1428 break;
d2ba2ed8 1429 case e1000_i350:
ceb5f13b 1430 case e1000_i354:
f96a8a0b
CW		 1431 case e1000_i210:
1432 case e1000_i211:
d2ba2ed8
AD		 1433 ics_mask = 0x77DCFED5;
1434 break;
2753f4ce
AD		 1435 default:
1436 ics_mask = 0x7FFFFFFF;
1437 break;
1438 }
1439
9d5c8243 1440 /* Test each interrupt */
2753f4ce 1441 for (; i < 31; i++) {
9d5c8243
AK		 1442 /* Interrupt to test */
1443 mask = 1 << i;
1444
2753f4ce
AD		 1445 if (!(mask & ics_mask))
1446 continue;
1447
9d5c8243
AK		 1448 if (!shared_int) {
1449 /* Disable the interrupt to be reported in
1450 * the cause register and then force the same
1451 * interrupt and see if one gets posted. If
1452 * an interrupt was posted to the bus, the
1453 * test failed.
1454 */
1455 adapter->test_icr = 0;
2753f4ce
AD		 1456
1457 /* Flush any pending interrupts */
1458 wr32(E1000_ICR, ~0);
1459
1460 wr32(E1000_IMC, mask);
1461 wr32(E1000_ICS, mask);
945a5151 1462 wrfl();
9d5c8243
AK		 1463 msleep(10);
1464
1465 if (adapter->test_icr & mask) {
1466 *data = 3;
1467 break;
1468 }
1469 }
1470
1471 /* Enable the interrupt to be reported in
1472 * the cause register and then force the same
1473 * interrupt and see if one gets posted. If
1474 * an interrupt was not posted to the bus, the
1475 * test failed.
1476 */
1477 adapter->test_icr = 0;
2753f4ce
AD		 1478
1479 /* Flush any pending interrupts */
1480 wr32(E1000_ICR, ~0);
1481
9d5c8243
AK		 1482 wr32(E1000_IMS, mask);
1483 wr32(E1000_ICS, mask);
945a5151 1484 wrfl();
9d5c8243
AK		 1485 msleep(10);
1486
1487 if (!(adapter->test_icr & mask)) {
1488 *data = 4;
1489 break;
1490 }
1491
1492 if (!shared_int) {
1493 /* Disable the other interrupts to be reported in
1494 * the cause register and then force the other
1495 * interrupts and see if any get posted. If
1496 * an interrupt was posted to the bus, the
1497 * test failed.
1498 */
1499 adapter->test_icr = 0;
2753f4ce
AD		 1500
1501 /* Flush any pending interrupts */
1502 wr32(E1000_ICR, ~0);
1503
1504 wr32(E1000_IMC, ~mask);
1505 wr32(E1000_ICS, ~mask);
945a5151 1506 wrfl();
9d5c8243
AK		 1507 msleep(10);
1508
2753f4ce 1509 if (adapter->test_icr & mask) {
9d5c8243
AK		 1510 *data = 5;
1511 break;
1512 }
1513 }
1514 }
1515
1516 /* Disable all the interrupts */
2753f4ce 1517 wr32(E1000_IMC, ~0);
945a5151 1518 wrfl();
9d5c8243
AK		 1519 msleep(10);
1520
1521 /* Unhook test interrupt handler */
cd14ef54 1522 if (adapter->flags & IGB_FLAG_HAS_MSIX)
4eefa8f0
AD		 1523 free_irq(adapter->msix_entries[0].vector, adapter);
1524 else
1525 free_irq(irq, adapter);
9d5c8243
AK		 1526
1527 return *data;
1528}
1529
1530static void igb_free_desc_rings(struct igb_adapter *adapter)
1531{
d7ee5b3a
AD		 1532 igb_free_tx_resources(&adapter->test_tx_ring);
1533 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1534}
1535
1536static int igb_setup_desc_rings(struct igb_adapter *adapter)
1537{
9d5c8243
AK		 1538 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1539 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1540 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1541 int ret_val;
9d5c8243
AK		 1542
1543 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a 1544 tx_ring->count = IGB_DEFAULT_TXD;
59d71989 1545 tx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1546 tx_ring->netdev = adapter->netdev;
1547 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1548
d7ee5b3a 1549 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1550 ret_val = 1;
1551 goto err_nomem;
1552 }
1553
d7ee5b3a
AD		 1554 igb_setup_tctl(adapter);
1555 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1556
9d5c8243 1557 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a 1558 rx_ring->count = IGB_DEFAULT_RXD;
59d71989 1559 rx_ring->dev = &adapter->pdev->dev;
d7ee5b3a 1560 rx_ring->netdev = adapter->netdev;
d7ee5b3a
AD		 1561 rx_ring->reg_idx = adapter->vfs_allocated_count;
1562
1563 if (igb_setup_rx_resources(rx_ring)) {
1564 ret_val = 3;
9d5c8243
AK		 1565 goto err_nomem;
1566 }
9d5c8243 1567
d7ee5b3a
AD		 1568 /* set the default queue to queue 0 of PF */
1569 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1570
d7ee5b3a
AD		 1571 /* enable receive ring */
1572 igb_setup_rctl(adapter);
1573 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1574
cd392f5c 1575 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1576
1577 return 0;
1578
1579err_nomem:
1580 igb_free_desc_rings(adapter);
1581 return ret_val;
1582}
1583
1584static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587
1588 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1589 igb_write_phy_reg(hw, 29, 0x001F);
1590 igb_write_phy_reg(hw, 30, 0x8FFC);
1591 igb_write_phy_reg(hw, 29, 0x001A);
1592 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1593}
1594
1595static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1596{
1597 struct e1000_hw *hw = &adapter->hw;
1598 u32 ctrl_reg = 0;
9d5c8243
AK		 1599
1600 hw->mac.autoneg = false;
1601
8aa23f0d
CW		 1602 if (hw->phy.type == e1000_phy_m88) {
1603 if (hw->phy.id != I210_I_PHY_ID) {
1604 /* Auto-MDI/MDIX Off */
1605 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1606 /* reset to update Auto-MDI/MDIX */
1607 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1608 /* autoneg off */
1609 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1610 } else {
1611 /* force 1000, set loopback */
1612 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1613 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1614 }
5aa3a449
TF		 1615 } else if (hw->phy.type == e1000_phy_82580) {
1616 /* enable MII loopback */
1617 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
9d5c8243
AK		 1618 }
1619
119b0e03
SA		 1620 /* add small delay to avoid loopback test failure */
1621 msleep(50);
1622
9d5c8243 1623 /* force 1000, set loopback */
f5f4cf08 1624 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1625
1626 /* Now set up the MAC to the same speed/duplex as the PHY. */
1627 ctrl_reg = rd32(E1000_CTRL);
1628 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1629 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1630 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1631 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1632 E1000_CTRL_FD | /* Force Duplex to FULL */
1633 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1634
8aa23f0d 1635 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1636 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1637
1638 wr32(E1000_CTRL, ctrl_reg);
1639
1640 /* Disable the receiver on the PHY so when a cable is plugged in, the
1641 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1642 */
8aa23f0d 1643 if (hw->phy.type == e1000_phy_m88)
9d5c8243
AK		 1644 igb_phy_disable_receiver(adapter);
1645
8aa23f0d 1646 mdelay(500);
9d5c8243
AK		 1647 return 0;
1648}
1649
1650static int igb_set_phy_loopback(struct igb_adapter *adapter)
1651{
1652 return igb_integrated_phy_loopback(adapter);
1653}
1654
1655static int igb_setup_loopback_test(struct igb_adapter *adapter)
1656{
1657 struct e1000_hw *hw = &adapter->hw;
2d064c06 1658 u32 reg;
9d5c8243 1659
317f66bd
AD		 1660 reg = rd32(E1000_CTRL_EXT);
1661
1662 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1663 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
a14bc2bb
RH		 1664 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1665 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1666 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
a4e979a2
FT		 1667 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1668 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
a14bc2bb
RH		 1669
1670 /* Enable DH89xxCC MPHY for near end loopback */
1671 reg = rd32(E1000_MPHY_ADDR_CTL);
1672 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1673 E1000_MPHY_PCS_CLK_REG_OFFSET;
1674 wr32(E1000_MPHY_ADDR_CTL, reg);
1675
1676 reg = rd32(E1000_MPHY_DATA);
1677 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1678 wr32(E1000_MPHY_DATA, reg);
1679 }
1680
2d064c06
AD		 1681 reg = rd32(E1000_RCTL);
1682 reg |= E1000_RCTL_LBM_TCVR;
1683 wr32(E1000_RCTL, reg);
1684
1685 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1686
1687 reg = rd32(E1000_CTRL);
1688 reg &= ~(E1000_CTRL_RFCE |
1689 E1000_CTRL_TFCE |
1690 E1000_CTRL_LRST);
1691 reg |= E1000_CTRL_SLU |
2753f4ce 1692 E1000_CTRL_FD;
2d064c06
AD		 1693 wr32(E1000_CTRL, reg);
1694
1695 /* Unset switch control to serdes energy detect */
1696 reg = rd32(E1000_CONNSW);
1697 reg &= ~E1000_CONNSW_ENRGSRC;
1698 wr32(E1000_CONNSW, reg);
1699
3860a0bf 1700 /* Unset sigdetect for SERDES loopback on
0ba96d3d 1701 * 82580 and newer devices.
3860a0bf 1702 */
0ba96d3d 1703 if (hw->mac.type >= e1000_82580) {
3860a0bf
CW		 1704 reg = rd32(E1000_PCS_CFG0);
1705 reg |= E1000_PCS_CFG_IGN_SD;
1706 wr32(E1000_PCS_CFG0, reg);
3860a0bf
CW		 1707 }
1708
2d064c06
AD		 1709 /* Set PCS register for forced speed */
1710 reg = rd32(E1000_PCS_LCTL);
1711 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1712 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1713 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1714 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1715 E1000_PCS_LCTL_FSD | /* Force Speed */
1716 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1717 wr32(E1000_PCS_LCTL, reg);
1718
9d5c8243 1719 return 0;
9d5c8243
AK		 1720 }
1721
317f66bd 1722 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1723}
1724
1725static void igb_loopback_cleanup(struct igb_adapter *adapter)
1726{
1727 struct e1000_hw *hw = &adapter->hw;
1728 u32 rctl;
1729 u16 phy_reg;
1730
a14bc2bb
RH		 1731 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1732 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1733 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
a4e979a2
FT		 1734 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1735 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
a14bc2bb
RH		 1736 u32 reg;
1737
1738 /* Disable near end loopback on DH89xxCC */
1739 reg = rd32(E1000_MPHY_ADDR_CTL);
1740 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1741 E1000_MPHY_PCS_CLK_REG_OFFSET;
1742 wr32(E1000_MPHY_ADDR_CTL, reg);
1743
1744 reg = rd32(E1000_MPHY_DATA);
1745 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1746 wr32(E1000_MPHY_DATA, reg);
1747 }
1748
9d5c8243
AK		 1749 rctl = rd32(E1000_RCTL);
1750 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1751 wr32(E1000_RCTL, rctl);
1752
1753 hw->mac.autoneg = true;
f5f4cf08 1754 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1755 if (phy_reg & MII_CR_LOOPBACK) {
1756 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1757 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1758 igb_phy_sw_reset(hw);
1759 }
1760}
1761
1762static void igb_create_lbtest_frame(struct sk_buff *skb,
1763 unsigned int frame_size)
1764{
1765 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1766 frame_size /= 2;
1767 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1768 memset(&skb->data[frame_size + 10], 0xBE, 1);
1769 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1770}
1771
1a1c225b
AD		 1772static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1773 unsigned int frame_size)
9d5c8243 1774{
1a1c225b
AD		 1775 unsigned char *data;
1776 bool match = true;
1777
1778 frame_size >>= 1;
1779
cbc8e55f 1780 data = kmap(rx_buffer->page);
1a1c225b
AD		 1781
1782 if (data[3] != 0xFF ||
1783 data[frame_size + 10] != 0xBE ||
1784 data[frame_size + 12] != 0xAF)
1785 match = false;
1786
1787 kunmap(rx_buffer->page);
1788
1789 return match;
9d5c8243
AK		 1790}
1791
ad93d17e 1792static int igb_clean_test_rings(struct igb_ring *rx_ring,
b980ac18
JK		 1793 struct igb_ring *tx_ring,
1794 unsigned int size)
ad93d17e
AD		 1795{
1796 union e1000_adv_rx_desc *rx_desc;
06034649
AD		 1797 struct igb_rx_buffer *rx_buffer_info;
1798 struct igb_tx_buffer *tx_buffer_info;
6ad4edfc 1799 u16 rx_ntc, tx_ntc, count = 0;
ad93d17e
AD		 1800
1801 /* initialize next to clean and descriptor values */
1802 rx_ntc = rx_ring->next_to_clean;
1803 tx_ntc = tx_ring->next_to_clean;
60136906 1804 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e 1805
3ceb90fd 1806 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
b980ac18 1807 /* check Rx buffer */
06034649 1808 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
ad93d17e 1809
cbc8e55f
AD		 1810 /* sync Rx buffer for CPU read */
1811 dma_sync_single_for_cpu(rx_ring->dev,
1812 rx_buffer_info->dma,
de78d1f9 1813 IGB_RX_BUFSZ,
cbc8e55f 1814 DMA_FROM_DEVICE);
ad93d17e
AD		 1815
1816 /* verify contents of skb */
1a1c225b 1817 if (igb_check_lbtest_frame(rx_buffer_info, size))
ad93d17e
AD		 1818 count++;
1819
cbc8e55f
AD		 1820 /* sync Rx buffer for device write */
1821 dma_sync_single_for_device(rx_ring->dev,
1822 rx_buffer_info->dma,
de78d1f9 1823 IGB_RX_BUFSZ,
cbc8e55f
AD		 1824 DMA_FROM_DEVICE);
1825
b980ac18 1826 /* unmap buffer on Tx side */
06034649
AD		 1827 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1828 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
ad93d17e 1829
b980ac18 1830 /* increment Rx/Tx next to clean counters */
ad93d17e
AD		 1831 rx_ntc++;
1832 if (rx_ntc == rx_ring->count)
1833 rx_ntc = 0;
1834 tx_ntc++;
1835 if (tx_ntc == tx_ring->count)
1836 tx_ntc = 0;
1837
1838 /* fetch next descriptor */
60136906 1839 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e
AD		 1840 }
1841
cbc8e55f 1842 netdev_tx_reset_queue(txring_txq(tx_ring));
51a76c30 1843
ad93d17e 1844 /* re-map buffers to ring, store next to clean values */
cd392f5c 1845 igb_alloc_rx_buffers(rx_ring, count);
ad93d17e
AD		 1846 rx_ring->next_to_clean = rx_ntc;
1847 tx_ring->next_to_clean = tx_ntc;
1848
1849 return count;
1850}
1851
9d5c8243
AK		 1852static int igb_run_loopback_test(struct igb_adapter *adapter)
1853{
9d5c8243
AK		 1854 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1855 struct igb_ring *rx_ring = &adapter->test_rx_ring;
6ad4edfc
AD		 1856 u16 i, j, lc, good_cnt;
1857 int ret_val = 0;
44390ca6 1858 unsigned int size = IGB_RX_HDR_LEN;
ad93d17e
AD		 1859 netdev_tx_t tx_ret_val;
1860 struct sk_buff *skb;
1861
1862 /* allocate test skb */
1863 skb = alloc_skb(size, GFP_KERNEL);
1864 if (!skb)
1865 return 11;
9d5c8243 1866
ad93d17e
AD		 1867 /* place data into test skb */
1868 igb_create_lbtest_frame(skb, size);
1869 skb_put(skb, size);
9d5c8243 1870
b980ac18 1871 /* Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1872 * The idea is to wrap the largest ring a number of times using 64
1873 * send/receive pairs during each loop
1874 */
1875
1876 if (rx_ring->count <= tx_ring->count)
1877 lc = ((tx_ring->count / 64) * 2) + 1;
1878 else
1879 lc = ((rx_ring->count / 64) * 2) + 1;
1880
9d5c8243 1881 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1882 /* reset count of good packets */
9d5c8243 1883 good_cnt = 0;
ad93d17e
AD		 1884
1885 /* place 64 packets on the transmit queue*/
1886 for (i = 0; i < 64; i++) {
1887 skb_get(skb);
cd392f5c 1888 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
ad93d17e 1889 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1890 good_cnt++;
ad93d17e
AD		 1891 }
1892
9d5c8243 1893 if (good_cnt != 64) {
ad93d17e 1894 ret_val = 12;
9d5c8243
AK		 1895 break;
1896 }
ad93d17e 1897
b980ac18 1898 /* allow 200 milliseconds for packets to go from Tx to Rx */
ad93d17e
AD		 1899 msleep(200);
1900
1901 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1902 if (good_cnt != 64) {
1903 ret_val = 13;
9d5c8243
AK		 1904 break;
1905 }
1906 } /* end loop count loop */
ad93d17e
AD		 1907
1908 /* free the original skb */
1909 kfree_skb(skb);
1910
9d5c8243
AK		 1911 return ret_val;
1912}
1913
1914static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1915{
1916 /* PHY loopback cannot be performed if SoL/IDER
b980ac18
JK		 1917 * sessions are active
1918 */
9d5c8243
AK		 1919 if (igb_check_reset_block(&adapter->hw)) {
1920 dev_err(&adapter->pdev->dev,
d836200a 1921 "Cannot do PHY loopback test when SoL/IDER is active.\n");
f96a8a0b
CW		 1922 *data = 0;
1923 goto out;
1924 }
ceb5f13b
CW		 1925
1926 if (adapter->hw.mac.type == e1000_i354) {
1927 dev_info(&adapter->pdev->dev,
1928 "Loopback test not supported on i354.\n");
1929 *data = 0;
1930 goto out;
1931 }
9d5c8243
AK		 1932 *data = igb_setup_desc_rings(adapter);
1933 if (*data)
1934 goto out;
1935 *data = igb_setup_loopback_test(adapter);
1936 if (*data)
1937 goto err_loopback;
1938 *data = igb_run_loopback_test(adapter);
1939 igb_loopback_cleanup(adapter);
1940
1941err_loopback:
1942 igb_free_desc_rings(adapter);
1943out:
1944 return *data;
1945}
1946
1947static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1948{
1949 struct e1000_hw *hw = &adapter->hw;
1950 *data = 0;
1951 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1952 int i = 0;
1953 hw->mac.serdes_has_link = false;
1954
1955 /* On some blade server designs, link establishment
b980ac18
JK		 1956 * could take as long as 2-3 minutes
1957 */
9d5c8243
AK		 1958 do {
1959 hw->mac.ops.check_for_link(&adapter->hw);
1960 if (hw->mac.serdes_has_link)
1961 return *data;
1962 msleep(20);
1963 } while (i++ < 3750);
1964
1965 *data = 1;
1966 } else {
1967 hw->mac.ops.check_for_link(&adapter->hw);
1968 if (hw->mac.autoneg)
4507dc9f 1969 msleep(5000);
9d5c8243 1970
317f66bd 1971 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1972 *data = 1;
1973 }
1974 return *data;
1975}
1976
1977static void igb_diag_test(struct net_device *netdev,
1978 struct ethtool_test *eth_test, u64 *data)
1979{
1980 struct igb_adapter *adapter = netdev_priv(netdev);
1981 u16 autoneg_advertised;
1982 u8 forced_speed_duplex, autoneg;
1983 bool if_running = netif_running(netdev);
1984
1985 set_bit(__IGB_TESTING, &adapter->state);
56cec249
CW		 1986
1987 /* can't do offline tests on media switching devices */
1988 if (adapter->hw.dev_spec._82575.mas_capable)
1989 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
9d5c8243
AK		 1990 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1991 /* Offline tests */
1992
1993 /* save speed, duplex, autoneg settings */
1994 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1995 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1996 autoneg = adapter->hw.mac.autoneg;
1997
1998 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1999
88a268c1
NN		 2000 /* power up link for link test */
2001 igb_power_up_link(adapter);
2002
9d5c8243 2003 /* Link test performed before hardware reset so autoneg doesn't
b980ac18
JK		 2004 * interfere with test result
2005 */
9d5c8243
AK		 2006 if (igb_link_test(adapter, &data[4]))
2007 eth_test->flags |= ETH_TEST_FL_FAILED;
2008
2009 if (if_running)
2010 /* indicate we're in test mode */
2011 dev_close(netdev);
2012 else
2013 igb_reset(adapter);
2014
2015 if (igb_reg_test(adapter, &data[0]))
2016 eth_test->flags |= ETH_TEST_FL_FAILED;
2017
2018 igb_reset(adapter);
2019 if (igb_eeprom_test(adapter, &data[1]))
2020 eth_test->flags |= ETH_TEST_FL_FAILED;
2021
2022 igb_reset(adapter);
2023 if (igb_intr_test(adapter, &data[2]))
2024 eth_test->flags |= ETH_TEST_FL_FAILED;
2025
2026 igb_reset(adapter);
88a268c1
NN		 2027 /* power up link for loopback test */
2028 igb_power_up_link(adapter);
9d5c8243
AK		 2029 if (igb_loopback_test(adapter, &data[3]))
2030 eth_test->flags |= ETH_TEST_FL_FAILED;
2031
2032 /* restore speed, duplex, autoneg settings */
2033 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2034 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2035 adapter->hw.mac.autoneg = autoneg;
2036
2037 /* force this routine to wait until autoneg complete/timeout */
2038 adapter->hw.phy.autoneg_wait_to_complete = true;
2039 igb_reset(adapter);
2040 adapter->hw.phy.autoneg_wait_to_complete = false;
2041
2042 clear_bit(__IGB_TESTING, &adapter->state);
2043 if (if_running)
2044 dev_open(netdev);
2045 } else {
2046 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 2047
2048 /* PHY is powered down when interface is down */
8d420a1b
AD		 2049 if (if_running && igb_link_test(adapter, &data[4]))
2050 eth_test->flags |= ETH_TEST_FL_FAILED;
2051 else
88a268c1 2052 data[4] = 0;
9d5c8243
AK		 2053
2054 /* Online tests aren't run; pass by default */
2055 data[0] = 0;
2056 data[1] = 0;
2057 data[2] = 0;
2058 data[3] = 0;
2059
2060 clear_bit(__IGB_TESTING, &adapter->state);
2061 }
2062 msleep_interruptible(4 * 1000);
2063}
2064
9d5c8243
AK		 2065static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2066{
2067 struct igb_adapter *adapter = netdev_priv(netdev);
2068
9d5c8243
AK		 2069 wol->wolopts = 0;
2070
63d4a8f9 2071 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2072 return;
2073
42ce4126
AA		 2074 wol->supported = WAKE_UCAST | WAKE_MCAST |
2075 WAKE_BCAST | WAKE_MAGIC |
2076 WAKE_PHY;
2077
9d5c8243
AK		 2078 /* apply any specific unsupported masks here */
2079 switch (adapter->hw.device_id) {
2080 default:
2081 break;
2082 }
2083
2084 if (adapter->wol & E1000_WUFC_EX)
2085 wol->wolopts |= WAKE_UCAST;
2086 if (adapter->wol & E1000_WUFC_MC)
2087 wol->wolopts |= WAKE_MCAST;
2088 if (adapter->wol & E1000_WUFC_BC)
2089 wol->wolopts |= WAKE_BCAST;
2090 if (adapter->wol & E1000_WUFC_MAG)
2091 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 2092 if (adapter->wol & E1000_WUFC_LNKC)
2093 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 2094}
2095
2096static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2097{
2098 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 2099
22939f06 2100 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 2101 return -EOPNOTSUPP;
2102
63d4a8f9 2103 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2104 return wol->wolopts ? -EOPNOTSUPP : 0;
2105
9d5c8243
AK		 2106 /* these settings will always override what we currently have */
2107 adapter->wol = 0;
2108
2109 if (wol->wolopts & WAKE_UCAST)
2110 adapter->wol |= E1000_WUFC_EX;
2111 if (wol->wolopts & WAKE_MCAST)
2112 adapter->wol |= E1000_WUFC_MC;
2113 if (wol->wolopts & WAKE_BCAST)
2114 adapter->wol |= E1000_WUFC_BC;
2115 if (wol->wolopts & WAKE_MAGIC)
2116 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 2117 if (wol->wolopts & WAKE_PHY)
2118 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 2119 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2120
9d5c8243
AK		 2121 return 0;
2122}
2123
9d5c8243
AK		 2124/* bit defines for adapter->led_status */
2125#define IGB_LED_ON 0
2126
936db355
JK		 2127static int igb_set_phys_id(struct net_device *netdev,
2128 enum ethtool_phys_id_state state)
9d5c8243
AK		 2129{
2130 struct igb_adapter *adapter = netdev_priv(netdev);
2131 struct e1000_hw *hw = &adapter->hw;
2132
936db355
JK		 2133 switch (state) {
2134 case ETHTOOL_ID_ACTIVE:
2135 igb_blink_led(hw);
2136 return 2;
2137 case ETHTOOL_ID_ON:
2138 igb_blink_led(hw);
2139 break;
2140 case ETHTOOL_ID_OFF:
2141 igb_led_off(hw);
2142 break;
2143 case ETHTOOL_ID_INACTIVE:
2144 igb_led_off(hw);
2145 clear_bit(IGB_LED_ON, &adapter->led_status);
2146 igb_cleanup_led(hw);
2147 break;
2148 }
9d5c8243
AK		 2149
2150 return 0;
2151}
2152
2153static int igb_set_coalesce(struct net_device *netdev,
2154 struct ethtool_coalesce *ec)
2155{
2156 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 2157 int i;
9d5c8243
AK		 2158
2159 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2160 ((ec->rx_coalesce_usecs > 3) &&
2161 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2162 (ec->rx_coalesce_usecs == 2))
2163 return -EINVAL;
2164
4fc82adf
AD		 2165 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2166 ((ec->tx_coalesce_usecs > 3) &&
2167 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2168 (ec->tx_coalesce_usecs == 2))
2169 return -EINVAL;
2170
2171 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2172 return -EINVAL;
2173
831ec0b4
CW		 2174 /* If ITR is disabled, disable DMAC */
2175 if (ec->rx_coalesce_usecs == 0) {
2176 if (adapter->flags & IGB_FLAG_DMAC)
2177 adapter->flags &= ~IGB_FLAG_DMAC;
2178 }
2179
9d5c8243 2180 /* convert to rate of irq's per second */
4fc82adf
AD		 2181 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2182 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2183 else
2184 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2185
2186 /* convert to rate of irq's per second */
2187 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2188 adapter->tx_itr_setting = adapter->rx_itr_setting;
2189 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2190 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2191 else
2192 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 2193
047e0030
AD		 2194 for (i = 0; i < adapter->num_q_vectors; i++) {
2195 struct igb_q_vector *q_vector = adapter->q_vector[i];
0ba82994
AD		 2196 q_vector->tx.work_limit = adapter->tx_work_limit;
2197 if (q_vector->rx.ring)
4fc82adf
AD		 2198 q_vector->itr_val = adapter->rx_itr_setting;
2199 else
2200 q_vector->itr_val = adapter->tx_itr_setting;
2201 if (q_vector->itr_val && q_vector->itr_val <= 3)
2202 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 2203 q_vector->set_itr = 1;
2204 }
9d5c8243
AK		 2205
2206 return 0;
2207}
2208
2209static int igb_get_coalesce(struct net_device *netdev,
2210 struct ethtool_coalesce *ec)
2211{
2212 struct igb_adapter *adapter = netdev_priv(netdev);
2213
4fc82adf
AD		 2214 if (adapter->rx_itr_setting <= 3)
2215 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 2216 else
4fc82adf
AD		 2217 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2218
2219 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2220 if (adapter->tx_itr_setting <= 3)
2221 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2222 else
2223 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2224 }
9d5c8243
AK		 2225
2226 return 0;
2227}
2228
9d5c8243
AK		 2229static int igb_nway_reset(struct net_device *netdev)
2230{
2231 struct igb_adapter *adapter = netdev_priv(netdev);
2232 if (netif_running(netdev))
2233 igb_reinit_locked(adapter);
2234 return 0;
2235}
2236
2237static int igb_get_sset_count(struct net_device *netdev, int sset)
2238{
2239 switch (sset) {
2240 case ETH_SS_STATS:
2241 return IGB_STATS_LEN;
2242 case ETH_SS_TEST:
2243 return IGB_TEST_LEN;
2244 default:
2245 return -ENOTSUPP;
2246 }
2247}
2248
2249static void igb_get_ethtool_stats(struct net_device *netdev,
2250 struct ethtool_stats *stats, u64 *data)
2251{
2252 struct igb_adapter *adapter = netdev_priv(netdev);
12dcd86b
ED		 2253 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2254 unsigned int start;
2255 struct igb_ring *ring;
2256 int i, j;
128e45eb 2257 char *p;
9d5c8243 2258
12dcd86b
ED		 2259 spin_lock(&adapter->stats64_lock);
2260 igb_update_stats(adapter, net_stats);
317f66bd 2261
9d5c8243 2262 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2263 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2264 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2265 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2266 }
128e45eb
AD		 2267 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2268 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2269 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2270 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2271 }
e21ed353 2272 for (j = 0; j < adapter->num_tx_queues; j++) {
12dcd86b
ED		 2273 u64 restart2;
2274
2275 ring = adapter->tx_ring[j];
2276 do {
2277 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2278 data[i] = ring->tx_stats.packets;
2279 data[i+1] = ring->tx_stats.bytes;
2280 data[i+2] = ring->tx_stats.restart_queue;
2281 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2282 do {
2283 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2284 restart2 = ring->tx_stats.restart_queue2;
2285 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2286 data[i+2] += restart2;
2287
2288 i += IGB_TX_QUEUE_STATS_LEN;
e21ed353 2289 }
9d5c8243 2290 for (j = 0; j < adapter->num_rx_queues; j++) {
12dcd86b
ED		 2291 ring = adapter->rx_ring[j];
2292 do {
2293 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2294 data[i] = ring->rx_stats.packets;
2295 data[i+1] = ring->rx_stats.bytes;
2296 data[i+2] = ring->rx_stats.drops;
2297 data[i+3] = ring->rx_stats.csum_err;
2298 data[i+4] = ring->rx_stats.alloc_failed;
2299 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2300 i += IGB_RX_QUEUE_STATS_LEN;
9d5c8243 2301 }
12dcd86b 2302 spin_unlock(&adapter->stats64_lock);
9d5c8243
AK		 2303}
2304
2305static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2306{
2307 struct igb_adapter *adapter = netdev_priv(netdev);
2308 u8 *p = data;
2309 int i;
2310
2311 switch (stringset) {
2312 case ETH_SS_TEST:
2313 memcpy(data, *igb_gstrings_test,
2314 IGB_TEST_LEN*ETH_GSTRING_LEN);
2315 break;
2316 case ETH_SS_STATS:
2317 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2318 memcpy(p, igb_gstrings_stats[i].stat_string,
2319 ETH_GSTRING_LEN);
2320 p += ETH_GSTRING_LEN;
2321 }
128e45eb
AD		 2322 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2323 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2324 ETH_GSTRING_LEN);
2325 p += ETH_GSTRING_LEN;
2326 }
9d5c8243
AK		 2327 for (i = 0; i < adapter->num_tx_queues; i++) {
2328 sprintf(p, "tx_queue_%u_packets", i);
2329 p += ETH_GSTRING_LEN;
2330 sprintf(p, "tx_queue_%u_bytes", i);
2331 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2332 sprintf(p, "tx_queue_%u_restart", i);
2333 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2334 }
2335 for (i = 0; i < adapter->num_rx_queues; i++) {
2336 sprintf(p, "rx_queue_%u_packets", i);
2337 p += ETH_GSTRING_LEN;
2338 sprintf(p, "rx_queue_%u_bytes", i);
2339 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2340 sprintf(p, "rx_queue_%u_drops", i);
2341 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2342 sprintf(p, "rx_queue_%u_csum_err", i);
2343 p += ETH_GSTRING_LEN;
2344 sprintf(p, "rx_queue_%u_alloc_failed", i);
2345 p += ETH_GSTRING_LEN;
9d5c8243 2346 }
b980ac18 2347 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
9d5c8243
AK		 2348 break;
2349 }
2350}
2351
a79f4f88 2352static int igb_get_ts_info(struct net_device *dev,
a9188028 2353 struct ethtool_ts_info *info)
cb41145e
CW		 2354{
2355 struct igb_adapter *adapter = netdev_priv(dev);
2356
a9188028 2357 switch (adapter->hw.mac.type) {
b66e2397
MV		 2358 case e1000_82575:
2359 info->so_timestamping =
2360 SOF_TIMESTAMPING_TX_SOFTWARE |
2361 SOF_TIMESTAMPING_RX_SOFTWARE |
2362 SOF_TIMESTAMPING_SOFTWARE;
2363 return 0;
a9188028
MV		 2364 case e1000_82576:
2365 case e1000_82580:
2366 case e1000_i350:
ceb5f13b 2367 case e1000_i354:
a9188028
MV		 2368 case e1000_i210:
2369 case e1000_i211:
2370 info->so_timestamping =
b66e2397
MV		 2371 SOF_TIMESTAMPING_TX_SOFTWARE |
2372 SOF_TIMESTAMPING_RX_SOFTWARE |
2373 SOF_TIMESTAMPING_SOFTWARE |
a9188028
MV		 2374 SOF_TIMESTAMPING_TX_HARDWARE |
2375 SOF_TIMESTAMPING_RX_HARDWARE |
2376 SOF_TIMESTAMPING_RAW_HARDWARE;
cb41145e 2377
a9188028
MV		 2378 if (adapter->ptp_clock)
2379 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2380 else
2381 info->phc_index = -1;
cb41145e 2382
a9188028
MV		 2383 info->tx_types =
2384 (1 << HWTSTAMP_TX_OFF) |
2385 (1 << HWTSTAMP_TX_ON);
cb41145e 2386
a9188028 2387 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
cb41145e 2388
a9188028
MV		 2389 /* 82576 does not support timestamping all packets. */
2390 if (adapter->hw.mac.type >= e1000_82580)
2391 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2392 else
2393 info->rx_filters |=
2394 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2395 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2396 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2397 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2398 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2399 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2400 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2401
2402 return 0;
a9188028
MV		 2403 default:
2404 return -EOPNOTSUPP;
2405 }
2406}
cb41145e 2407
039454a8
AA		 2408static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2409 struct ethtool_rxnfc *cmd)
2410{
2411 cmd->data = 0;
2412
2413 /* Report default options for RSS on igb */
2414 switch (cmd->flow_type) {
2415 case TCP_V4_FLOW:
2416 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2417 case UDP_V4_FLOW:
2418 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2419 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2420 case SCTP_V4_FLOW:
2421 case AH_ESP_V4_FLOW:
2422 case AH_V4_FLOW:
2423 case ESP_V4_FLOW:
2424 case IPV4_FLOW:
2425 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2426 break;
2427 case TCP_V6_FLOW:
2428 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2429 case UDP_V6_FLOW:
2430 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2431 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2432 case SCTP_V6_FLOW:
2433 case AH_ESP_V6_FLOW:
2434 case AH_V6_FLOW:
2435 case ESP_V6_FLOW:
2436 case IPV6_FLOW:
2437 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2438 break;
2439 default:
2440 return -EINVAL;
2441 }
2442
2443 return 0;
2444}
2445
2446static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
b980ac18 2447 u32 *rule_locs)
039454a8
AA		 2448{
2449 struct igb_adapter *adapter = netdev_priv(dev);
2450 int ret = -EOPNOTSUPP;
2451
2452 switch (cmd->cmd) {
2453 case ETHTOOL_GRXRINGS:
2454 cmd->data = adapter->num_rx_queues;
2455 ret = 0;
2456 break;
2457 case ETHTOOL_GRXFH:
2458 ret = igb_get_rss_hash_opts(adapter, cmd);
2459 break;
2460 default:
2461 break;
2462 }
2463
2464 return ret;
2465}
2466
2467#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2468 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2469static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2470 struct ethtool_rxnfc *nfc)
2471{
2472 u32 flags = adapter->flags;
2473
2474 /* RSS does not support anything other than hashing
2475 * to queues on src and dst IPs and ports
2476 */
2477 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2478 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2479 return -EINVAL;
2480
2481 switch (nfc->flow_type) {
2482 case TCP_V4_FLOW:
2483 case TCP_V6_FLOW:
2484 if (!(nfc->data & RXH_IP_SRC) ||
2485 !(nfc->data & RXH_IP_DST) ||
2486 !(nfc->data & RXH_L4_B_0_1) ||
2487 !(nfc->data & RXH_L4_B_2_3))
2488 return -EINVAL;
2489 break;
2490 case UDP_V4_FLOW:
2491 if (!(nfc->data & RXH_IP_SRC) ||
2492 !(nfc->data & RXH_IP_DST))
2493 return -EINVAL;
2494 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2495 case 0:
2496 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2497 break;
2498 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2499 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2500 break;
2501 default:
2502 return -EINVAL;
2503 }
2504 break;
2505 case UDP_V6_FLOW:
2506 if (!(nfc->data & RXH_IP_SRC) ||
2507 !(nfc->data & RXH_IP_DST))
2508 return -EINVAL;
2509 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2510 case 0:
2511 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2512 break;
2513 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2514 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2515 break;
2516 default:
2517 return -EINVAL;
2518 }
2519 break;
2520 case AH_ESP_V4_FLOW:
2521 case AH_V4_FLOW:
2522 case ESP_V4_FLOW:
2523 case SCTP_V4_FLOW:
2524 case AH_ESP_V6_FLOW:
2525 case AH_V6_FLOW:
2526 case ESP_V6_FLOW:
2527 case SCTP_V6_FLOW:
2528 if (!(nfc->data & RXH_IP_SRC) ||
2529 !(nfc->data & RXH_IP_DST) ||
2530 (nfc->data & RXH_L4_B_0_1) ||
2531 (nfc->data & RXH_L4_B_2_3))
2532 return -EINVAL;
2533 break;
2534 default:
2535 return -EINVAL;
2536 }
2537
2538 /* if we changed something we need to update flags */
2539 if (flags != adapter->flags) {
2540 struct e1000_hw *hw = &adapter->hw;
2541 u32 mrqc = rd32(E1000_MRQC);
2542
2543 if ((flags & UDP_RSS_FLAGS) &&
2544 !(adapter->flags & UDP_RSS_FLAGS))
2545 dev_err(&adapter->pdev->dev,
2546 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2547
2548 adapter->flags = flags;
2549
2550 /* Perform hash on these packet types */
2551 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2552 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2553 E1000_MRQC_RSS_FIELD_IPV6 |
2554 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2555
2556 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2557 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2558
2559 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2560 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2561
2562 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2563 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2564
2565 wr32(E1000_MRQC, mrqc);
2566 }
2567
2568 return 0;
2569}
2570
2571static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2572{
2573 struct igb_adapter *adapter = netdev_priv(dev);
2574 int ret = -EOPNOTSUPP;
2575
2576 switch (cmd->cmd) {
2577 case ETHTOOL_SRXFH:
2578 ret = igb_set_rss_hash_opt(adapter, cmd);
2579 break;
2580 default:
2581 break;
2582 }
2583
2584 return ret;
2585}
2586
24a372cd
AA		 2587static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2588{
2589 struct igb_adapter *adapter = netdev_priv(netdev);
2590 struct e1000_hw *hw = &adapter->hw;
87371b9d
MV		 2591 u32 ipcnfg, eeer, ret_val;
2592 u16 phy_data;
24a372cd
AA		 2593
2594 if ((hw->mac.type < e1000_i350) ||
2595 (hw->phy.media_type != e1000_media_type_copper))
2596 return -EOPNOTSUPP;
2597
2598 edata->supported = (SUPPORTED_1000baseT_Full |
2599 SUPPORTED_100baseT_Full);
2600
2601 ipcnfg = rd32(E1000_IPCNFG);
2602 eeer = rd32(E1000_EEER);
2603
2604 /* EEE status on negotiated link */
2605 if (ipcnfg & E1000_IPCNFG_EEE_1G_AN)
2606 edata->advertised = ADVERTISED_1000baseT_Full;
2607
2608 if (ipcnfg & E1000_IPCNFG_EEE_100M_AN)
2609 edata->advertised |= ADVERTISED_100baseT_Full;
2610
87371b9d
MV		 2611 /* EEE Link Partner Advertised */
2612 switch (hw->mac.type) {
2613 case e1000_i350:
2614 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
2615 &phy_data);
2616 if (ret_val)
2617 return -ENODATA;
2618
2619 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2620
2621 break;
2622 case e1000_i210:
2623 case e1000_i211:
2624 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
2625 E1000_EEE_LP_ADV_DEV_I210,
2626 &phy_data);
2627 if (ret_val)
2628 return -ENODATA;
2629
2630 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
2631
2632 break;
2633 default:
2634 break;
2635 }
2636
24a372cd
AA		 2637 if (eeer & E1000_EEER_EEE_NEG)
2638 edata->eee_active = true;
2639
2640 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2641
2642 if (eeer & E1000_EEER_TX_LPI_EN)
2643 edata->tx_lpi_enabled = true;
2644
2645 /* Report correct negotiated EEE status for devices that
2646 * wrongly report EEE at half-duplex
2647 */
2648 if (adapter->link_duplex == HALF_DUPLEX) {
2649 edata->eee_enabled = false;
2650 edata->eee_active = false;
2651 edata->tx_lpi_enabled = false;
2652 edata->advertised &= ~edata->advertised;
2653 }
2654
2655 return 0;
2656}
2657
2658static int igb_set_eee(struct net_device *netdev,
2659 struct ethtool_eee *edata)
2660{
2661 struct igb_adapter *adapter = netdev_priv(netdev);
2662 struct e1000_hw *hw = &adapter->hw;
2663 struct ethtool_eee eee_curr;
2664 s32 ret_val;
2665
2666 if ((hw->mac.type < e1000_i350) ||
2667 (hw->phy.media_type != e1000_media_type_copper))
2668 return -EOPNOTSUPP;
2669
58e4e1f6
AK		 2670 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
2671
24a372cd
AA		 2672 ret_val = igb_get_eee(netdev, &eee_curr);
2673 if (ret_val)
2674 return ret_val;
2675
2676 if (eee_curr.eee_enabled) {
2677 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2678 dev_err(&adapter->pdev->dev,
2679 "Setting EEE tx-lpi is not supported\n");
2680 return -EINVAL;
2681 }
2682
2683 /* Tx LPI timer is not implemented currently */
2684 if (edata->tx_lpi_timer) {
2685 dev_err(&adapter->pdev->dev,
2686 "Setting EEE Tx LPI timer is not supported\n");
2687 return -EINVAL;
2688 }
2689
2690 if (eee_curr.advertised != edata->advertised) {
2691 dev_err(&adapter->pdev->dev,
2692 "Setting EEE Advertisement is not supported\n");
2693 return -EINVAL;
2694 }
2695
2696 } else if (!edata->eee_enabled) {
2697 dev_err(&adapter->pdev->dev,
2698 "Setting EEE options are not supported with EEE disabled\n");
2699 return -EINVAL;
2700 }
2701
2702 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2703 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2704 igb_set_eee_i350(hw);
2705
2706 /* reset link */
8a650aa2
AA		 2707 if (netif_running(netdev))
2708 igb_reinit_locked(adapter);
2709 else
24a372cd
AA		 2710 igb_reset(adapter);
2711 }
2712
2713 return 0;
2714}
2715
f69aa390
AA		 2716static int igb_get_module_info(struct net_device *netdev,
2717 struct ethtool_modinfo *modinfo)
2718{
2719 struct igb_adapter *adapter = netdev_priv(netdev);
2720 struct e1000_hw *hw = &adapter->hw;
2721 u32 status = E1000_SUCCESS;
2722 u16 sff8472_rev, addr_mode;
2723 bool page_swap = false;
2724
2725 if ((hw->phy.media_type == e1000_media_type_copper) ||
2726 (hw->phy.media_type == e1000_media_type_unknown))
2727 return -EOPNOTSUPP;
2728
2729 /* Check whether we support SFF-8472 or not */
2730 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
2731 if (status != E1000_SUCCESS)
2732 return -EIO;
2733
2734 /* addressing mode is not supported */
2735 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
2736 if (status != E1000_SUCCESS)
2737 return -EIO;
2738
2739 /* addressing mode is not supported */
2740 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
2741 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2742 page_swap = true;
2743 }
2744
2745 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
2746 /* We have an SFP, but it does not support SFF-8472 */
2747 modinfo->type = ETH_MODULE_SFF_8079;
2748 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2749 } else {
2750 /* We have an SFP which supports a revision of SFF-8472 */
2751 modinfo->type = ETH_MODULE_SFF_8472;
2752 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2753 }
2754
2755 return 0;
2756}
2757
2758static int igb_get_module_eeprom(struct net_device *netdev,
2759 struct ethtool_eeprom *ee, u8 *data)
2760{
2761 struct igb_adapter *adapter = netdev_priv(netdev);
2762 struct e1000_hw *hw = &adapter->hw;
2763 u32 status = E1000_SUCCESS;
2764 u16 *dataword;
2765 u16 first_word, last_word;
2766 int i = 0;
2767
2768 if (ee->len == 0)
2769 return -EINVAL;
2770
2771 first_word = ee->offset >> 1;
2772 last_word = (ee->offset + ee->len - 1) >> 1;
2773
2774 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
2775 GFP_KERNEL);
2776 if (!dataword)
2777 return -ENOMEM;
2778
2779 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
2780 for (i = 0; i < last_word - first_word + 1; i++) {
2781 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
2782 if (status != E1000_SUCCESS)
2783 /* Error occurred while reading module */
2784 return -EIO;
2785
2786 be16_to_cpus(&dataword[i]);
2787 }
2788
2789 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
2790 kfree(dataword);
2791
2792 return 0;
2793}
2794
a79f4f88
MV		 2795static int igb_ethtool_begin(struct net_device *netdev)
2796{
2797 struct igb_adapter *adapter = netdev_priv(netdev);
2798 pm_runtime_get_sync(&adapter->pdev->dev);
2799 return 0;
2800}
2801
2802static void igb_ethtool_complete(struct net_device *netdev)
2803{
2804 struct igb_adapter *adapter = netdev_priv(netdev);
2805 pm_runtime_put(&adapter->pdev->dev);
2806}
2807
ed12cc9a
LMV		 2808static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
2809{
2810 return IGB_RETA_SIZE;
2811}
2812
2813static int igb_get_rxfh_indir(struct net_device *netdev, u32 *indir)
2814{
2815 struct igb_adapter *adapter = netdev_priv(netdev);
2816 int i;
2817
2818 for (i = 0; i < IGB_RETA_SIZE; i++)
2819 indir[i] = adapter->rss_indir_tbl[i];
2820
2821 return 0;
2822}
2823
2824void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
2825{
2826 struct e1000_hw *hw = &adapter->hw;
2827 u32 reg = E1000_RETA(0);
2828 u32 shift = 0;
2829 int i = 0;
2830
2831 switch (hw->mac.type) {
2832 case e1000_82575:
2833 shift = 6;
2834 break;
2835 case e1000_82576:
2836 /* 82576 supports 2 RSS queues for SR-IOV */
2837 if (adapter->vfs_allocated_count)
2838 shift = 3;
2839 break;
2840 default:
2841 break;
2842 }
2843
2844 while (i < IGB_RETA_SIZE) {
2845 u32 val = 0;
2846 int j;
2847
2848 for (j = 3; j >= 0; j--) {
2849 val <<= 8;
2850 val |= adapter->rss_indir_tbl[i + j];
2851 }
2852
2853 wr32(reg, val << shift);
2854 reg += 4;
2855 i += 4;
2856 }
2857}
2858
2859static int igb_set_rxfh_indir(struct net_device *netdev, const u32 *indir)
2860{
2861 struct igb_adapter *adapter = netdev_priv(netdev);
2862 struct e1000_hw *hw = &adapter->hw;
2863 int i;
2864 u32 num_queues;
2865
2866 num_queues = adapter->rss_queues;
2867
2868 switch (hw->mac.type) {
2869 case e1000_82576:
2870 /* 82576 supports 2 RSS queues for SR-IOV */
2871 if (adapter->vfs_allocated_count)
2872 num_queues = 2;
2873 break;
2874 default:
2875 break;
2876 }
2877
2878 /* Verify user input. */
2879 for (i = 0; i < IGB_RETA_SIZE; i++)
2880 if (indir[i] >= num_queues)
2881 return -EINVAL;
2882
2883
2884 for (i = 0; i < IGB_RETA_SIZE; i++)
2885 adapter->rss_indir_tbl[i] = indir[i];
2886
2887 igb_write_rss_indir_tbl(adapter);
2888
2889 return 0;
2890}
2891
907b7835
LMV		 2892static unsigned int igb_max_channels(struct igb_adapter *adapter)
2893{
2894 struct e1000_hw *hw = &adapter->hw;
2895 unsigned int max_combined = 0;
2896
2897 switch (hw->mac.type) {
2898 case e1000_i211:
2899 max_combined = IGB_MAX_RX_QUEUES_I211;
2900 break;
2901 case e1000_82575:
2902 case e1000_i210:
2903 max_combined = IGB_MAX_RX_QUEUES_82575;
2904 break;
2905 case e1000_i350:
2906 if (!!adapter->vfs_allocated_count) {
2907 max_combined = 1;
2908 break;
2909 }
2910 /* fall through */
2911 case e1000_82576:
2912 if (!!adapter->vfs_allocated_count) {
2913 max_combined = 2;
2914 break;
2915 }
2916 /* fall through */
2917 case e1000_82580:
2918 case e1000_i354:
2919 default:
2920 max_combined = IGB_MAX_RX_QUEUES;
2921 break;
2922 }
2923
2924 return max_combined;
2925}
2926
2927static void igb_get_channels(struct net_device *netdev,
2928 struct ethtool_channels *ch)
2929{
2930 struct igb_adapter *adapter = netdev_priv(netdev);
2931
2932 /* Report maximum channels */
2933 ch->max_combined = igb_max_channels(adapter);
2934
2935 /* Report info for other vector */
cd14ef54 2936 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
907b7835
LMV		 2937 ch->max_other = NON_Q_VECTORS;
2938 ch->other_count = NON_Q_VECTORS;
2939 }
2940
2941 ch->combined_count = adapter->rss_queues;
2942}
2943
2944static int igb_set_channels(struct net_device *netdev,
2945 struct ethtool_channels *ch)
2946{
2947 struct igb_adapter *adapter = netdev_priv(netdev);
2948 unsigned int count = ch->combined_count;
2949
2950 /* Verify they are not requesting separate vectors */
2951 if (!count || ch->rx_count || ch->tx_count)
2952 return -EINVAL;
2953
2954 /* Verify other_count is valid and has not been changed */
2955 if (ch->other_count != NON_Q_VECTORS)
2956 return -EINVAL;
2957
2958 /* Verify the number of channels doesn't exceed hw limits */
2959 if (count > igb_max_channels(adapter))
2960 return -EINVAL;
2961
2962 if (count != adapter->rss_queues) {
2963 adapter->rss_queues = count;
2964
2965 /* Hardware has to reinitialize queues and interrupts to
2966 * match the new configuration.
2967 */
2968 return igb_reinit_queues(adapter);
2969 }
2970
2971 return 0;
2972}
2973
0fc0b732 2974static const struct ethtool_ops igb_ethtool_ops = {
b980ac18
JK		 2975 .get_settings = igb_get_settings,
2976 .set_settings = igb_set_settings,
2977 .get_drvinfo = igb_get_drvinfo,
2978 .get_regs_len = igb_get_regs_len,
2979 .get_regs = igb_get_regs,
2980 .get_wol = igb_get_wol,
2981 .set_wol = igb_set_wol,
2982 .get_msglevel = igb_get_msglevel,
2983 .set_msglevel = igb_set_msglevel,
2984 .nway_reset = igb_nway_reset,
2985 .get_link = igb_get_link,
2986 .get_eeprom_len = igb_get_eeprom_len,
2987 .get_eeprom = igb_get_eeprom,
2988 .set_eeprom = igb_set_eeprom,
2989 .get_ringparam = igb_get_ringparam,
2990 .set_ringparam = igb_set_ringparam,
2991 .get_pauseparam = igb_get_pauseparam,
2992 .set_pauseparam = igb_set_pauseparam,
2993 .self_test = igb_diag_test,
2994 .get_strings = igb_get_strings,
2995 .set_phys_id = igb_set_phys_id,
2996 .get_sset_count = igb_get_sset_count,
2997 .get_ethtool_stats = igb_get_ethtool_stats,
2998 .get_coalesce = igb_get_coalesce,
2999 .set_coalesce = igb_set_coalesce,
3000 .get_ts_info = igb_get_ts_info,
039454a8
AA		 3001 .get_rxnfc = igb_get_rxnfc,
3002 .set_rxnfc = igb_set_rxnfc,
24a372cd
AA		 3003 .get_eee = igb_get_eee,
3004 .set_eee = igb_set_eee,
f69aa390
AA		 3005 .get_module_info = igb_get_module_info,
3006 .get_module_eeprom = igb_get_module_eeprom,
ed12cc9a
LMV		 3007 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
3008 .get_rxfh_indir = igb_get_rxfh_indir,
3009 .set_rxfh_indir = igb_set_rxfh_indir,
907b7835
LMV		 3010 .get_channels = igb_get_channels,
3011 .set_channels = igb_set_channels,
a79f4f88
MV		 3012 .begin = igb_ethtool_begin,
3013 .complete = igb_ethtool_complete,
9d5c8243
AK		 3014};
3015
3016void igb_set_ethtool_ops(struct net_device *netdev)
3017{
3018 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
3019}
Linux kernel - Deliverables
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