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ixgbevf: Fix register defines to correctly handle complex expressions
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4297f99b 4 Copyright(c) 2007-2011 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
d43c36dc 37#include <linux/sched.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39
40#include "igb.h"
41
42struct igb_stats {
43 char stat_string[ETH_GSTRING_LEN];
44 int sizeof_stat;
45 int stat_offset;
46};
47
128e45eb
AD		 48#define IGB_STAT(_name, _stat) { \
49 .stat_string = _name, \
50 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
51 .stat_offset = offsetof(struct igb_adapter, _stat) \
52}
9d5c8243 53static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 54 IGB_STAT("rx_packets", stats.gprc),
55 IGB_STAT("tx_packets", stats.gptc),
56 IGB_STAT("rx_bytes", stats.gorc),
57 IGB_STAT("tx_bytes", stats.gotc),
58 IGB_STAT("rx_broadcast", stats.bprc),
59 IGB_STAT("tx_broadcast", stats.bptc),
60 IGB_STAT("rx_multicast", stats.mprc),
61 IGB_STAT("tx_multicast", stats.mptc),
62 IGB_STAT("multicast", stats.mprc),
63 IGB_STAT("collisions", stats.colc),
64 IGB_STAT("rx_crc_errors", stats.crcerrs),
65 IGB_STAT("rx_no_buffer_count", stats.rnbc),
66 IGB_STAT("rx_missed_errors", stats.mpc),
67 IGB_STAT("tx_aborted_errors", stats.ecol),
68 IGB_STAT("tx_carrier_errors", stats.tncrs),
69 IGB_STAT("tx_window_errors", stats.latecol),
70 IGB_STAT("tx_abort_late_coll", stats.latecol),
71 IGB_STAT("tx_deferred_ok", stats.dc),
72 IGB_STAT("tx_single_coll_ok", stats.scc),
73 IGB_STAT("tx_multi_coll_ok", stats.mcc),
74 IGB_STAT("tx_timeout_count", tx_timeout_count),
75 IGB_STAT("rx_long_length_errors", stats.roc),
76 IGB_STAT("rx_short_length_errors", stats.ruc),
77 IGB_STAT("rx_align_errors", stats.algnerrc),
78 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
79 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
80 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
81 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
82 IGB_STAT("tx_flow_control_xon", stats.xontxc),
83 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
84 IGB_STAT("rx_long_byte_count", stats.gorc),
85 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
86 IGB_STAT("tx_smbus", stats.mgptc),
87 IGB_STAT("rx_smbus", stats.mgprc),
88 IGB_STAT("dropped_smbus", stats.mgpdc),
0a915b95
CW		 89 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
90 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
91 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
92 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
128e45eb
AD		 93};
94
95#define IGB_NETDEV_STAT(_net_stat) { \
96 .stat_string = __stringify(_net_stat), \
12dcd86b
ED		 97 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
98 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
128e45eb
AD		 99}
100static const struct igb_stats igb_gstrings_net_stats[] = {
101 IGB_NETDEV_STAT(rx_errors),
102 IGB_NETDEV_STAT(tx_errors),
103 IGB_NETDEV_STAT(tx_dropped),
104 IGB_NETDEV_STAT(rx_length_errors),
105 IGB_NETDEV_STAT(rx_over_errors),
106 IGB_NETDEV_STAT(rx_frame_errors),
107 IGB_NETDEV_STAT(rx_fifo_errors),
108 IGB_NETDEV_STAT(tx_fifo_errors),
109 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 110};
111
128e45eb
AD		 112#define IGB_GLOBAL_STATS_LEN \
113 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
114#define IGB_NETDEV_STATS_LEN \
115 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
116#define IGB_RX_QUEUE_STATS_LEN \
117 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
12dcd86b
ED		 118
119#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
120
9d5c8243 121#define IGB_QUEUE_STATS_LEN \
317f66bd 122 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 123 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 124 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 125 IGB_TX_QUEUE_STATS_LEN))
126#define IGB_STATS_LEN \
127 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
128
9d5c8243
AK		 129static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
130 "Register test (offline)", "Eeprom test (offline)",
131 "Interrupt test (offline)", "Loopback test (offline)",
132 "Link test (on/offline)"
133};
317f66bd 134#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 135
136static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
137{
138 struct igb_adapter *adapter = netdev_priv(netdev);
139 struct e1000_hw *hw = &adapter->hw;
317f66bd 140 u32 status;
9d5c8243
AK		 141
142 if (hw->phy.media_type == e1000_media_type_copper) {
143
144 ecmd->supported = (SUPPORTED_10baseT_Half |
145 SUPPORTED_10baseT_Full |
146 SUPPORTED_100baseT_Half |
147 SUPPORTED_100baseT_Full |
148 SUPPORTED_1000baseT_Full|
149 SUPPORTED_Autoneg |
150 SUPPORTED_TP);
151 ecmd->advertising = ADVERTISED_TP;
152
153 if (hw->mac.autoneg == 1) {
154 ecmd->advertising |= ADVERTISED_Autoneg;
155 /* the e1000 autoneg seems to match ethtool nicely */
156 ecmd->advertising |= hw->phy.autoneg_advertised;
157 }
158
159 ecmd->port = PORT_TP;
160 ecmd->phy_address = hw->phy.addr;
161 } else {
162 ecmd->supported = (SUPPORTED_1000baseT_Full |
163 SUPPORTED_FIBRE |
164 SUPPORTED_Autoneg);
165
166 ecmd->advertising = (ADVERTISED_1000baseT_Full |
167 ADVERTISED_FIBRE |
168 ADVERTISED_Autoneg);
169
170 ecmd->port = PORT_FIBRE;
171 }
172
173 ecmd->transceiver = XCVR_INTERNAL;
174
317f66bd 175 status = rd32(E1000_STATUS);
9d5c8243 176
317f66bd 177 if (status & E1000_STATUS_LU) {
9d5c8243 178
317f66bd
AD		 179 if ((status & E1000_STATUS_SPEED_1000) ||
180 hw->phy.media_type != e1000_media_type_copper)
70739497 181 ethtool_cmd_speed_set(ecmd, SPEED_1000);
317f66bd 182 else if (status & E1000_STATUS_SPEED_100)
70739497 183 ethtool_cmd_speed_set(ecmd, SPEED_100);
317f66bd 184 else
70739497 185 ethtool_cmd_speed_set(ecmd, SPEED_10);
9d5c8243 186
317f66bd
AD		 187 if ((status & E1000_STATUS_FD) ||
188 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 189 ecmd->duplex = DUPLEX_FULL;
190 else
191 ecmd->duplex = DUPLEX_HALF;
192 } else {
70739497 193 ethtool_cmd_speed_set(ecmd, -1);
9d5c8243
AK		 194 ecmd->duplex = -1;
195 }
196
dcc3ae9a 197 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
9d5c8243
AK		 198 return 0;
199}
200
201static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
202{
203 struct igb_adapter *adapter = netdev_priv(netdev);
204 struct e1000_hw *hw = &adapter->hw;
205
206 /* When SoL/IDER sessions are active, autoneg/speed/duplex
207 * cannot be changed */
208 if (igb_check_reset_block(hw)) {
209 dev_err(&adapter->pdev->dev, "Cannot change link "
210 "characteristics when SoL/IDER is active.\n");
211 return -EINVAL;
212 }
213
214 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
215 msleep(1);
216
217 if (ecmd->autoneg == AUTONEG_ENABLE) {
218 hw->mac.autoneg = 1;
dcc3ae9a
AD		 219 hw->phy.autoneg_advertised = ecmd->advertising |
220 ADVERTISED_TP |
221 ADVERTISED_Autoneg;
9d5c8243 222 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 223 if (adapter->fc_autoneg)
224 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 225 } else {
25db0338 226 u32 speed = ethtool_cmd_speed(ecmd);
14ad2513 227 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
9d5c8243
AK		 228 clear_bit(__IGB_RESETTING, &adapter->state);
229 return -EINVAL;
230 }
dcc3ae9a 231 }
9d5c8243
AK		 232
233 /* reset the link */
9d5c8243
AK		 234 if (netif_running(adapter->netdev)) {
235 igb_down(adapter);
236 igb_up(adapter);
237 } else
238 igb_reset(adapter);
239
240 clear_bit(__IGB_RESETTING, &adapter->state);
241 return 0;
242}
243
3145535a
NN		 244static u32 igb_get_link(struct net_device *netdev)
245{
246 struct igb_adapter *adapter = netdev_priv(netdev);
247 struct e1000_mac_info *mac = &adapter->hw.mac;
248
249 /*
250 * If the link is not reported up to netdev, interrupts are disabled,
251 * and so the physical link state may have changed since we last
252 * looked. Set get_link_status to make sure that the true link
253 * state is interrogated, rather than pulling a cached and possibly
254 * stale link state from the driver.
255 */
256 if (!netif_carrier_ok(netdev))
257 mac->get_link_status = 1;
258
259 return igb_has_link(adapter);
260}
261
9d5c8243
AK		 262static void igb_get_pauseparam(struct net_device *netdev,
263 struct ethtool_pauseparam *pause)
264{
265 struct igb_adapter *adapter = netdev_priv(netdev);
266 struct e1000_hw *hw = &adapter->hw;
267
268 pause->autoneg =
269 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
270
0cce119a 271 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 272 pause->rx_pause = 1;
0cce119a 273 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 274 pause->tx_pause = 1;
0cce119a 275 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 276 pause->rx_pause = 1;
277 pause->tx_pause = 1;
278 }
279}
280
281static int igb_set_pauseparam(struct net_device *netdev,
282 struct ethtool_pauseparam *pause)
283{
284 struct igb_adapter *adapter = netdev_priv(netdev);
285 struct e1000_hw *hw = &adapter->hw;
286 int retval = 0;
287
288 adapter->fc_autoneg = pause->autoneg;
289
290 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
291 msleep(1);
292
9d5c8243 293 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 294 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 295 if (netif_running(adapter->netdev)) {
296 igb_down(adapter);
297 igb_up(adapter);
317f66bd 298 } else {
9d5c8243 299 igb_reset(adapter);
317f66bd 300 }
0cce119a
AD		 301 } else {
302 if (pause->rx_pause && pause->tx_pause)
303 hw->fc.requested_mode = e1000_fc_full;
304 else if (pause->rx_pause && !pause->tx_pause)
305 hw->fc.requested_mode = e1000_fc_rx_pause;
306 else if (!pause->rx_pause && pause->tx_pause)
307 hw->fc.requested_mode = e1000_fc_tx_pause;
308 else if (!pause->rx_pause && !pause->tx_pause)
309 hw->fc.requested_mode = e1000_fc_none;
310
311 hw->fc.current_mode = hw->fc.requested_mode;
312
dcc3ae9a
AD		 313 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
314 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 315 }
9d5c8243
AK		 316
317 clear_bit(__IGB_RESETTING, &adapter->state);
318 return retval;
319}
320
9d5c8243
AK		 321static u32 igb_get_msglevel(struct net_device *netdev)
322{
323 struct igb_adapter *adapter = netdev_priv(netdev);
324 return adapter->msg_enable;
325}
326
327static void igb_set_msglevel(struct net_device *netdev, u32 data)
328{
329 struct igb_adapter *adapter = netdev_priv(netdev);
330 adapter->msg_enable = data;
331}
332
333static int igb_get_regs_len(struct net_device *netdev)
334{
335#define IGB_REGS_LEN 551
336 return IGB_REGS_LEN * sizeof(u32);
337}
338
339static void igb_get_regs(struct net_device *netdev,
340 struct ethtool_regs *regs, void *p)
341{
342 struct igb_adapter *adapter = netdev_priv(netdev);
343 struct e1000_hw *hw = &adapter->hw;
344 u32 *regs_buff = p;
345 u8 i;
346
347 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
348
349 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
350
351 /* General Registers */
352 regs_buff[0] = rd32(E1000_CTRL);
353 regs_buff[1] = rd32(E1000_STATUS);
354 regs_buff[2] = rd32(E1000_CTRL_EXT);
355 regs_buff[3] = rd32(E1000_MDIC);
356 regs_buff[4] = rd32(E1000_SCTL);
357 regs_buff[5] = rd32(E1000_CONNSW);
358 regs_buff[6] = rd32(E1000_VET);
359 regs_buff[7] = rd32(E1000_LEDCTL);
360 regs_buff[8] = rd32(E1000_PBA);
361 regs_buff[9] = rd32(E1000_PBS);
362 regs_buff[10] = rd32(E1000_FRTIMER);
363 regs_buff[11] = rd32(E1000_TCPTIMER);
364
365 /* NVM Register */
366 regs_buff[12] = rd32(E1000_EECD);
367
368 /* Interrupt */
fe59de38
AD		 369 /* Reading EICS for EICR because they read the
370 * same but EICS does not clear on read */
371 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 372 regs_buff[14] = rd32(E1000_EICS);
373 regs_buff[15] = rd32(E1000_EIMS);
374 regs_buff[16] = rd32(E1000_EIMC);
375 regs_buff[17] = rd32(E1000_EIAC);
376 regs_buff[18] = rd32(E1000_EIAM);
fe59de38
AD		 377 /* Reading ICS for ICR because they read the
378 * same but ICS does not clear on read */
379 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 380 regs_buff[20] = rd32(E1000_ICS);
381 regs_buff[21] = rd32(E1000_IMS);
382 regs_buff[22] = rd32(E1000_IMC);
383 regs_buff[23] = rd32(E1000_IAC);
384 regs_buff[24] = rd32(E1000_IAM);
385 regs_buff[25] = rd32(E1000_IMIRVP);
386
387 /* Flow Control */
388 regs_buff[26] = rd32(E1000_FCAL);
389 regs_buff[27] = rd32(E1000_FCAH);
390 regs_buff[28] = rd32(E1000_FCTTV);
391 regs_buff[29] = rd32(E1000_FCRTL);
392 regs_buff[30] = rd32(E1000_FCRTH);
393 regs_buff[31] = rd32(E1000_FCRTV);
394
395 /* Receive */
396 regs_buff[32] = rd32(E1000_RCTL);
397 regs_buff[33] = rd32(E1000_RXCSUM);
398 regs_buff[34] = rd32(E1000_RLPML);
399 regs_buff[35] = rd32(E1000_RFCTL);
400 regs_buff[36] = rd32(E1000_MRQC);
e1739522 401 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 402
403 /* Transmit */
404 regs_buff[38] = rd32(E1000_TCTL);
405 regs_buff[39] = rd32(E1000_TCTL_EXT);
406 regs_buff[40] = rd32(E1000_TIPG);
407 regs_buff[41] = rd32(E1000_DTXCTL);
408
409 /* Wake Up */
410 regs_buff[42] = rd32(E1000_WUC);
411 regs_buff[43] = rd32(E1000_WUFC);
412 regs_buff[44] = rd32(E1000_WUS);
413 regs_buff[45] = rd32(E1000_IPAV);
414 regs_buff[46] = rd32(E1000_WUPL);
415
416 /* MAC */
417 regs_buff[47] = rd32(E1000_PCS_CFG0);
418 regs_buff[48] = rd32(E1000_PCS_LCTL);
419 regs_buff[49] = rd32(E1000_PCS_LSTAT);
420 regs_buff[50] = rd32(E1000_PCS_ANADV);
421 regs_buff[51] = rd32(E1000_PCS_LPAB);
422 regs_buff[52] = rd32(E1000_PCS_NPTX);
423 regs_buff[53] = rd32(E1000_PCS_LPABNP);
424
425 /* Statistics */
426 regs_buff[54] = adapter->stats.crcerrs;
427 regs_buff[55] = adapter->stats.algnerrc;
428 regs_buff[56] = adapter->stats.symerrs;
429 regs_buff[57] = adapter->stats.rxerrc;
430 regs_buff[58] = adapter->stats.mpc;
431 regs_buff[59] = adapter->stats.scc;
432 regs_buff[60] = adapter->stats.ecol;
433 regs_buff[61] = adapter->stats.mcc;
434 regs_buff[62] = adapter->stats.latecol;
435 regs_buff[63] = adapter->stats.colc;
436 regs_buff[64] = adapter->stats.dc;
437 regs_buff[65] = adapter->stats.tncrs;
438 regs_buff[66] = adapter->stats.sec;
439 regs_buff[67] = adapter->stats.htdpmc;
440 regs_buff[68] = adapter->stats.rlec;
441 regs_buff[69] = adapter->stats.xonrxc;
442 regs_buff[70] = adapter->stats.xontxc;
443 regs_buff[71] = adapter->stats.xoffrxc;
444 regs_buff[72] = adapter->stats.xofftxc;
445 regs_buff[73] = adapter->stats.fcruc;
446 regs_buff[74] = adapter->stats.prc64;
447 regs_buff[75] = adapter->stats.prc127;
448 regs_buff[76] = adapter->stats.prc255;
449 regs_buff[77] = adapter->stats.prc511;
450 regs_buff[78] = adapter->stats.prc1023;
451 regs_buff[79] = adapter->stats.prc1522;
452 regs_buff[80] = adapter->stats.gprc;
453 regs_buff[81] = adapter->stats.bprc;
454 regs_buff[82] = adapter->stats.mprc;
455 regs_buff[83] = adapter->stats.gptc;
456 regs_buff[84] = adapter->stats.gorc;
457 regs_buff[86] = adapter->stats.gotc;
458 regs_buff[88] = adapter->stats.rnbc;
459 regs_buff[89] = adapter->stats.ruc;
460 regs_buff[90] = adapter->stats.rfc;
461 regs_buff[91] = adapter->stats.roc;
462 regs_buff[92] = adapter->stats.rjc;
463 regs_buff[93] = adapter->stats.mgprc;
464 regs_buff[94] = adapter->stats.mgpdc;
465 regs_buff[95] = adapter->stats.mgptc;
466 regs_buff[96] = adapter->stats.tor;
467 regs_buff[98] = adapter->stats.tot;
468 regs_buff[100] = adapter->stats.tpr;
469 regs_buff[101] = adapter->stats.tpt;
470 regs_buff[102] = adapter->stats.ptc64;
471 regs_buff[103] = adapter->stats.ptc127;
472 regs_buff[104] = adapter->stats.ptc255;
473 regs_buff[105] = adapter->stats.ptc511;
474 regs_buff[106] = adapter->stats.ptc1023;
475 regs_buff[107] = adapter->stats.ptc1522;
476 regs_buff[108] = adapter->stats.mptc;
477 regs_buff[109] = adapter->stats.bptc;
478 regs_buff[110] = adapter->stats.tsctc;
479 regs_buff[111] = adapter->stats.iac;
480 regs_buff[112] = adapter->stats.rpthc;
481 regs_buff[113] = adapter->stats.hgptc;
482 regs_buff[114] = adapter->stats.hgorc;
483 regs_buff[116] = adapter->stats.hgotc;
484 regs_buff[118] = adapter->stats.lenerrs;
485 regs_buff[119] = adapter->stats.scvpc;
486 regs_buff[120] = adapter->stats.hrmpc;
487
9d5c8243
AK		 488 for (i = 0; i < 4; i++)
489 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
490 for (i = 0; i < 4; i++)
83ab50a5 491 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 492 for (i = 0; i < 4; i++)
493 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
494 for (i = 0; i < 4; i++)
495 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
496 for (i = 0; i < 4; i++)
497 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
498 for (i = 0; i < 4; i++)
499 regs_buff[141 + i] = rd32(E1000_RDH(i));
500 for (i = 0; i < 4; i++)
501 regs_buff[145 + i] = rd32(E1000_RDT(i));
502 for (i = 0; i < 4; i++)
503 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
504
505 for (i = 0; i < 10; i++)
506 regs_buff[153 + i] = rd32(E1000_EITR(i));
507 for (i = 0; i < 8; i++)
508 regs_buff[163 + i] = rd32(E1000_IMIR(i));
509 for (i = 0; i < 8; i++)
510 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
511 for (i = 0; i < 16; i++)
512 regs_buff[179 + i] = rd32(E1000_RAL(i));
513 for (i = 0; i < 16; i++)
514 regs_buff[195 + i] = rd32(E1000_RAH(i));
515
516 for (i = 0; i < 4; i++)
517 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
518 for (i = 0; i < 4; i++)
519 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
520 for (i = 0; i < 4; i++)
521 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
522 for (i = 0; i < 4; i++)
523 regs_buff[223 + i] = rd32(E1000_TDH(i));
524 for (i = 0; i < 4; i++)
525 regs_buff[227 + i] = rd32(E1000_TDT(i));
526 for (i = 0; i < 4; i++)
527 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
528 for (i = 0; i < 4; i++)
529 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
530 for (i = 0; i < 4; i++)
531 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
532 for (i = 0; i < 4; i++)
533 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
534
535 for (i = 0; i < 4; i++)
536 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
537 for (i = 0; i < 4; i++)
538 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
539 for (i = 0; i < 32; i++)
540 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
541 for (i = 0; i < 128; i++)
542 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
543 for (i = 0; i < 128; i++)
544 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
545 for (i = 0; i < 4; i++)
546 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
547
548 regs_buff[547] = rd32(E1000_TDFH);
549 regs_buff[548] = rd32(E1000_TDFT);
550 regs_buff[549] = rd32(E1000_TDFHS);
551 regs_buff[550] = rd32(E1000_TDFPC);
0a915b95
CW		 552 regs_buff[551] = adapter->stats.o2bgptc;
553 regs_buff[552] = adapter->stats.b2ospc;
554 regs_buff[553] = adapter->stats.o2bspc;
555 regs_buff[554] = adapter->stats.b2ogprc;
9d5c8243
AK		 556}
557
558static int igb_get_eeprom_len(struct net_device *netdev)
559{
560 struct igb_adapter *adapter = netdev_priv(netdev);
561 return adapter->hw.nvm.word_size * 2;
562}
563
564static int igb_get_eeprom(struct net_device *netdev,
565 struct ethtool_eeprom *eeprom, u8 *bytes)
566{
567 struct igb_adapter *adapter = netdev_priv(netdev);
568 struct e1000_hw *hw = &adapter->hw;
569 u16 *eeprom_buff;
570 int first_word, last_word;
571 int ret_val = 0;
572 u16 i;
573
574 if (eeprom->len == 0)
575 return -EINVAL;
576
577 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
578
579 first_word = eeprom->offset >> 1;
580 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
581
582 eeprom_buff = kmalloc(sizeof(u16) *
583 (last_word - first_word + 1), GFP_KERNEL);
584 if (!eeprom_buff)
585 return -ENOMEM;
586
587 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 588 ret_val = hw->nvm.ops.read(hw, first_word,
9d5c8243
AK		 589 last_word - first_word + 1,
590 eeprom_buff);
591 else {
592 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 593 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
9d5c8243
AK		 594 &eeprom_buff[i]);
595 if (ret_val)
596 break;
597 }
598 }
599
600 /* Device's eeprom is always little-endian, word addressable */
601 for (i = 0; i < last_word - first_word + 1; i++)
602 le16_to_cpus(&eeprom_buff[i]);
603
604 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
605 eeprom->len);
606 kfree(eeprom_buff);
607
608 return ret_val;
609}
610
611static int igb_set_eeprom(struct net_device *netdev,
612 struct ethtool_eeprom *eeprom, u8 *bytes)
613{
614 struct igb_adapter *adapter = netdev_priv(netdev);
615 struct e1000_hw *hw = &adapter->hw;
616 u16 *eeprom_buff;
617 void *ptr;
618 int max_len, first_word, last_word, ret_val = 0;
619 u16 i;
620
621 if (eeprom->len == 0)
622 return -EOPNOTSUPP;
623
624 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
625 return -EFAULT;
626
627 max_len = hw->nvm.word_size * 2;
628
629 first_word = eeprom->offset >> 1;
630 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
631 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
632 if (!eeprom_buff)
633 return -ENOMEM;
634
635 ptr = (void *)eeprom_buff;
636
637 if (eeprom->offset & 1) {
638 /* need read/modify/write of first changed EEPROM word */
639 /* only the second byte of the word is being modified */
312c75ae 640 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 641 &eeprom_buff[0]);
642 ptr++;
643 }
644 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
645 /* need read/modify/write of last changed EEPROM word */
646 /* only the first byte of the word is being modified */
312c75ae 647 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 648 &eeprom_buff[last_word - first_word]);
649 }
650
651 /* Device's eeprom is always little-endian, word addressable */
652 for (i = 0; i < last_word - first_word + 1; i++)
653 le16_to_cpus(&eeprom_buff[i]);
654
655 memcpy(ptr, bytes, eeprom->len);
656
657 for (i = 0; i < last_word - first_word + 1; i++)
658 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
659
312c75ae 660 ret_val = hw->nvm.ops.write(hw, first_word,
9d5c8243
AK		 661 last_word - first_word + 1, eeprom_buff);
662
663 /* Update the checksum over the first part of the EEPROM if needed
664 * and flush shadow RAM for 82573 controllers */
665 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
4322e561 666 hw->nvm.ops.update(hw);
9d5c8243
AK		 667
668 kfree(eeprom_buff);
669 return ret_val;
670}
671
672static void igb_get_drvinfo(struct net_device *netdev,
673 struct ethtool_drvinfo *drvinfo)
674{
675 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 676 u16 eeprom_data;
677
612a94d6
RJ		 678 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
679 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
9d5c8243
AK		 680
681 /* EEPROM image version # is reported as firmware version # for
682 * 82575 controllers */
312c75ae 683 adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
612a94d6
RJ		 684 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
685 "%d.%d-%d",
9d5c8243
AK		 686 (eeprom_data & 0xF000) >> 12,
687 (eeprom_data & 0x0FF0) >> 4,
688 eeprom_data & 0x000F);
689
612a94d6
RJ		 690 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
691 sizeof(drvinfo->bus_info));
9d5c8243
AK		 692 drvinfo->n_stats = IGB_STATS_LEN;
693 drvinfo->testinfo_len = IGB_TEST_LEN;
694 drvinfo->regdump_len = igb_get_regs_len(netdev);
695 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
696}
697
698static void igb_get_ringparam(struct net_device *netdev,
699 struct ethtool_ringparam *ring)
700{
701 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 702
703 ring->rx_max_pending = IGB_MAX_RXD;
704 ring->tx_max_pending = IGB_MAX_TXD;
68fd9910
AD		 705 ring->rx_pending = adapter->rx_ring_count;
706 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 707}
708
709static int igb_set_ringparam(struct net_device *netdev,
710 struct ethtool_ringparam *ring)
711{
712 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 713 struct igb_ring *temp_ring;
6d9f4fc4 714 int i, err = 0;
0e15439a 715 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 716
717 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
718 return -EINVAL;
719
0e15439a
AD		 720 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
721 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 722 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
723
0e15439a
AD		 724 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
725 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 726 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
727
68fd9910
AD		 728 if ((new_tx_count == adapter->tx_ring_count) &&
729 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 730 /* nothing to do */
731 return 0;
732 }
733
6d9f4fc4
AD		 734 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
735 msleep(1);
736
737 if (!netif_running(adapter->netdev)) {
738 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 739 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 740 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 741 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 742 adapter->tx_ring_count = new_tx_count;
743 adapter->rx_ring_count = new_rx_count;
744 goto clear_reset;
745 }
746
68fd9910
AD		 747 if (adapter->num_tx_queues > adapter->num_rx_queues)
748 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
749 else
750 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
68fd9910 751
6d9f4fc4
AD		 752 if (!temp_ring) {
753 err = -ENOMEM;
754 goto clear_reset;
755 }
9d5c8243 756
6d9f4fc4 757 igb_down(adapter);
9d5c8243
AK		 758
759 /*
760 * We can't just free everything and then setup again,
761 * because the ISRs in MSI-X mode get passed pointers
762 * to the tx and rx ring structs.
763 */
68fd9910 764 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 765 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 766 memcpy(&temp_ring[i], adapter->tx_ring[i],
767 sizeof(struct igb_ring));
768
68fd9910 769 temp_ring[i].count = new_tx_count;
80785298 770 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 771 if (err) {
68fd9910
AD		 772 while (i) {
773 i--;
774 igb_free_tx_resources(&temp_ring[i]);
775 }
9d5c8243
AK		 776 goto err_setup;
777 }
9d5c8243 778 }
68fd9910 779
3025a446
AD		 780 for (i = 0; i < adapter->num_tx_queues; i++) {
781 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 782
3025a446
AD		 783 memcpy(adapter->tx_ring[i], &temp_ring[i],
784 sizeof(struct igb_ring));
785 }
68fd9910
AD		 786
787 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 788 }
789
3025a446 790 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 791 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 792 memcpy(&temp_ring[i], adapter->rx_ring[i],
793 sizeof(struct igb_ring));
794
68fd9910 795 temp_ring[i].count = new_rx_count;
80785298 796 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 797 if (err) {
68fd9910
AD		 798 while (i) {
799 i--;
800 igb_free_rx_resources(&temp_ring[i]);
801 }
9d5c8243
AK		 802 goto err_setup;
803 }
804
9d5c8243 805 }
68fd9910 806
3025a446
AD		 807 for (i = 0; i < adapter->num_rx_queues; i++) {
808 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 809
3025a446
AD		 810 memcpy(adapter->rx_ring[i], &temp_ring[i],
811 sizeof(struct igb_ring));
812 }
68fd9910
AD		 813
814 adapter->rx_ring_count = new_rx_count;
9d5c8243 815 }
9d5c8243 816err_setup:
6d9f4fc4 817 igb_up(adapter);
68fd9910 818 vfree(temp_ring);
6d9f4fc4
AD		 819clear_reset:
820 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 821 return err;
822}
823
824/* ethtool register test data */
825struct igb_reg_test {
826 u16 reg;
2d064c06
AD		 827 u16 reg_offset;
828 u16 array_len;
829 u16 test_type;
9d5c8243
AK		 830 u32 mask;
831 u32 write;
832};
833
834/* In the hardware, registers are laid out either singly, in arrays
835 * spaced 0x100 bytes apart, or in contiguous tables. We assume
836 * most tests take place on arrays or single registers (handled
837 * as a single-element array) and special-case the tables.
838 * Table tests are always pattern tests.
839 *
840 * We also make provision for some required setup steps by specifying
841 * registers to be written without any read-back testing.
842 */
843
844#define PATTERN_TEST 1
845#define SET_READ_TEST 2
846#define WRITE_NO_TEST 3
847#define TABLE32_TEST 4
848#define TABLE64_TEST_LO 5
849#define TABLE64_TEST_HI 6
850
d2ba2ed8
AD		 851/* i350 reg test */
852static struct igb_reg_test reg_test_i350[] = {
853 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
854 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
855 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
856 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
857 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
858 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 859 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 860 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
861 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 862 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 863 /* RDH is read-only for i350, only test RDT. */
864 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
865 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
866 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
867 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
868 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
869 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
870 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 871 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 872 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
873 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 874 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 875 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
876 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
877 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
878 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
879 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
880 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
881 { E1000_RA, 0, 16, TABLE64_TEST_LO,
882 0xFFFFFFFF, 0xFFFFFFFF },
883 { E1000_RA, 0, 16, TABLE64_TEST_HI,
884 0xC3FFFFFF, 0xFFFFFFFF },
885 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
886 0xFFFFFFFF, 0xFFFFFFFF },
887 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
888 0xC3FFFFFF, 0xFFFFFFFF },
889 { E1000_MTA, 0, 128, TABLE32_TEST,
890 0xFFFFFFFF, 0xFFFFFFFF },
891 { 0, 0, 0, 0 }
892};
893
55cac248
AD		 894/* 82580 reg test */
895static struct igb_reg_test reg_test_82580[] = {
896 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
897 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
898 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
899 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
900 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
901 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
902 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
903 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
904 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
905 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
906 /* RDH is read-only for 82580, only test RDT. */
907 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
908 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
909 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
910 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
911 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
912 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
913 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
914 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
915 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
916 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
917 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
918 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
919 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
920 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
921 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
922 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
923 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
924 { E1000_RA, 0, 16, TABLE64_TEST_LO,
925 0xFFFFFFFF, 0xFFFFFFFF },
926 { E1000_RA, 0, 16, TABLE64_TEST_HI,
927 0x83FFFFFF, 0xFFFFFFFF },
928 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
929 0xFFFFFFFF, 0xFFFFFFFF },
930 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
931 0x83FFFFFF, 0xFFFFFFFF },
932 { E1000_MTA, 0, 128, TABLE32_TEST,
933 0xFFFFFFFF, 0xFFFFFFFF },
934 { 0, 0, 0, 0 }
935};
936
2d064c06
AD		 937/* 82576 reg test */
938static struct igb_reg_test reg_test_82576[] = {
939 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
940 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
941 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
942 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
943 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
944 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
945 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 946 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
947 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
948 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
949 /* Enable all RX queues before testing. */
950 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
951 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 952 /* RDH is read-only for 82576, only test RDT. */
953 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 954 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 955 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 956 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 957 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
958 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
959 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
960 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
961 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
962 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 963 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
964 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
965 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 966 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
967 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
968 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
969 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
970 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
971 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
972 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
973 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
974 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
975 { 0, 0, 0, 0 }
976};
977
978/* 82575 register test */
9d5c8243 979static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 980 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
981 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
982 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
983 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
984 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
985 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
986 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 987 /* Enable all four RX queues before testing. */
2d064c06 988 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 989 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 990 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
991 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
992 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
993 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
994 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
995 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
996 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
997 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
998 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
999 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1000 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1001 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1002 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1003 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1004 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1005 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1006 { 0, 0, 0, 0 }
1007};
1008
1009static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1010 int reg, u32 mask, u32 write)
1011{
2753f4ce 1012 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1013 u32 pat, val;
317f66bd 1014 static const u32 _test[] =
9d5c8243
AK		 1015 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1016 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce 1017 wr32(reg, (_test[pat] & write));
93ed8359 1018 val = rd32(reg) & mask;
9d5c8243
AK		 1019 if (val != (_test[pat] & write & mask)) {
1020 dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1021 "failed: got 0x%08X expected 0x%08X\n",
1022 reg, val, (_test[pat] & write & mask));
1023 *data = reg;
1024 return 1;
1025 }
1026 }
317f66bd 1027
9d5c8243
AK		 1028 return 0;
1029}
1030
1031static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1032 int reg, u32 mask, u32 write)
1033{
2753f4ce 1034 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1035 u32 val;
2753f4ce
AD		 1036 wr32(reg, write & mask);
1037 val = rd32(reg);
9d5c8243
AK		 1038 if ((write & mask) != (val & mask)) {
1039 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1040 " got 0x%08X expected 0x%08X\n", reg,
1041 (val & mask), (write & mask));
1042 *data = reg;
1043 return 1;
1044 }
317f66bd 1045
9d5c8243
AK		 1046 return 0;
1047}
1048
1049#define REG_PATTERN_TEST(reg, mask, write) \
1050 do { \
1051 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1052 return 1; \
1053 } while (0)
1054
1055#define REG_SET_AND_CHECK(reg, mask, write) \
1056 do { \
1057 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1058 return 1; \
1059 } while (0)
1060
1061static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1062{
1063 struct e1000_hw *hw = &adapter->hw;
1064 struct igb_reg_test *test;
1065 u32 value, before, after;
1066 u32 i, toggle;
1067
2d064c06 1068 switch (adapter->hw.mac.type) {
d2ba2ed8
AD		 1069 case e1000_i350:
1070 test = reg_test_i350;
1071 toggle = 0x7FEFF3FF;
1072 break;
55cac248
AD		 1073 case e1000_82580:
1074 test = reg_test_82580;
1075 toggle = 0x7FEFF3FF;
1076 break;
2d064c06
AD		 1077 case e1000_82576:
1078 test = reg_test_82576;
317f66bd 1079 toggle = 0x7FFFF3FF;
2d064c06
AD		 1080 break;
1081 default:
1082 test = reg_test_82575;
317f66bd 1083 toggle = 0x7FFFF3FF;
2d064c06
AD		 1084 break;
1085 }
9d5c8243
AK		 1086
1087 /* Because the status register is such a special case,
1088 * we handle it separately from the rest of the register
1089 * tests. Some bits are read-only, some toggle, and some
1090 * are writable on newer MACs.
1091 */
1092 before = rd32(E1000_STATUS);
1093 value = (rd32(E1000_STATUS) & toggle);
1094 wr32(E1000_STATUS, toggle);
1095 after = rd32(E1000_STATUS) & toggle;
1096 if (value != after) {
1097 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1098 "got: 0x%08X expected: 0x%08X\n", after, value);
1099 *data = 1;
1100 return 1;
1101 }
1102 /* restore previous status */
1103 wr32(E1000_STATUS, before);
1104
1105 /* Perform the remainder of the register test, looping through
1106 * the test table until we either fail or reach the null entry.
1107 */
1108 while (test->reg) {
1109 for (i = 0; i < test->array_len; i++) {
1110 switch (test->test_type) {
1111 case PATTERN_TEST:
2753f4ce
AD		 1112 REG_PATTERN_TEST(test->reg +
1113 (i * test->reg_offset),
9d5c8243
AK		 1114 test->mask,
1115 test->write);
1116 break;
1117 case SET_READ_TEST:
2753f4ce
AD		 1118 REG_SET_AND_CHECK(test->reg +
1119 (i * test->reg_offset),
9d5c8243
AK		 1120 test->mask,
1121 test->write);
1122 break;
1123 case WRITE_NO_TEST:
1124 writel(test->write,
1125 (adapter->hw.hw_addr + test->reg)
2d064c06 1126 + (i * test->reg_offset));
9d5c8243
AK		 1127 break;
1128 case TABLE32_TEST:
1129 REG_PATTERN_TEST(test->reg + (i * 4),
1130 test->mask,
1131 test->write);
1132 break;
1133 case TABLE64_TEST_LO:
1134 REG_PATTERN_TEST(test->reg + (i * 8),
1135 test->mask,
1136 test->write);
1137 break;
1138 case TABLE64_TEST_HI:
1139 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1140 test->mask,
1141 test->write);
1142 break;
1143 }
1144 }
1145 test++;
1146 }
1147
1148 *data = 0;
1149 return 0;
1150}
1151
1152static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1153{
1154 u16 temp;
1155 u16 checksum = 0;
1156 u16 i;
1157
1158 *data = 0;
1159 /* Read and add up the contents of the EEPROM */
1160 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
317f66bd 1161 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp)) < 0) {
9d5c8243
AK		 1162 *data = 1;
1163 break;
1164 }
1165 checksum += temp;
1166 }
1167
1168 /* If Checksum is not Correct return error else test passed */
1169 if ((checksum != (u16) NVM_SUM) && !(*data))
1170 *data = 2;
1171
1172 return *data;
1173}
1174
1175static irqreturn_t igb_test_intr(int irq, void *data)
1176{
317f66bd 1177 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1178 struct e1000_hw *hw = &adapter->hw;
1179
1180 adapter->test_icr |= rd32(E1000_ICR);
1181
1182 return IRQ_HANDLED;
1183}
1184
1185static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1186{
1187 struct e1000_hw *hw = &adapter->hw;
1188 struct net_device *netdev = adapter->netdev;
2753f4ce 1189 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1190 u32 irq = adapter->pdev->irq;
1191
1192 *data = 0;
1193
1194 /* Hook up test interrupt handler just for this test */
4eefa8f0
AD		 1195 if (adapter->msix_entries) {
1196 if (request_irq(adapter->msix_entries[0].vector,
a0607fd3 1197 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1198 *data = 1;
1199 return -1;
1200 }
4eefa8f0 1201 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1202 shared_int = false;
4eefa8f0 1203 if (request_irq(irq,
a0607fd3 1204 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1205 *data = 1;
1206 return -1;
1207 }
a0607fd3 1208 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1209 netdev->name, adapter)) {
9d5c8243 1210 shared_int = false;
a0607fd3 1211 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1212 netdev->name, adapter)) {
9d5c8243
AK		 1213 *data = 1;
1214 return -1;
1215 }
1216 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1217 (shared_int ? "shared" : "unshared"));
317f66bd 1218
9d5c8243 1219 /* Disable all the interrupts */
4eefa8f0 1220 wr32(E1000_IMC, ~0);
945a5151 1221 wrfl();
9d5c8243
AK		 1222 msleep(10);
1223
2753f4ce 1224 /* Define all writable bits for ICS */
4eefa8f0 1225 switch (hw->mac.type) {
2753f4ce
AD		 1226 case e1000_82575:
1227 ics_mask = 0x37F47EDD;
1228 break;
1229 case e1000_82576:
1230 ics_mask = 0x77D4FBFD;
1231 break;
55cac248
AD		 1232 case e1000_82580:
1233 ics_mask = 0x77DCFED5;
1234 break;
d2ba2ed8
AD		 1235 case e1000_i350:
1236 ics_mask = 0x77DCFED5;
1237 break;
2753f4ce
AD		 1238 default:
1239 ics_mask = 0x7FFFFFFF;
1240 break;
1241 }
1242
9d5c8243 1243 /* Test each interrupt */
2753f4ce 1244 for (; i < 31; i++) {
9d5c8243
AK		 1245 /* Interrupt to test */
1246 mask = 1 << i;
1247
2753f4ce
AD		 1248 if (!(mask & ics_mask))
1249 continue;
1250
9d5c8243
AK		 1251 if (!shared_int) {
1252 /* Disable the interrupt to be reported in
1253 * the cause register and then force the same
1254 * interrupt and see if one gets posted. If
1255 * an interrupt was posted to the bus, the
1256 * test failed.
1257 */
1258 adapter->test_icr = 0;
2753f4ce
AD		 1259
1260 /* Flush any pending interrupts */
1261 wr32(E1000_ICR, ~0);
1262
1263 wr32(E1000_IMC, mask);
1264 wr32(E1000_ICS, mask);
945a5151 1265 wrfl();
9d5c8243
AK		 1266 msleep(10);
1267
1268 if (adapter->test_icr & mask) {
1269 *data = 3;
1270 break;
1271 }
1272 }
1273
1274 /* Enable the interrupt to be reported in
1275 * the cause register and then force the same
1276 * interrupt and see if one gets posted. If
1277 * an interrupt was not posted to the bus, the
1278 * test failed.
1279 */
1280 adapter->test_icr = 0;
2753f4ce
AD		 1281
1282 /* Flush any pending interrupts */
1283 wr32(E1000_ICR, ~0);
1284
9d5c8243
AK		 1285 wr32(E1000_IMS, mask);
1286 wr32(E1000_ICS, mask);
945a5151 1287 wrfl();
9d5c8243
AK		 1288 msleep(10);
1289
1290 if (!(adapter->test_icr & mask)) {
1291 *data = 4;
1292 break;
1293 }
1294
1295 if (!shared_int) {
1296 /* Disable the other interrupts to be reported in
1297 * the cause register and then force the other
1298 * interrupts and see if any get posted. If
1299 * an interrupt was posted to the bus, the
1300 * test failed.
1301 */
1302 adapter->test_icr = 0;
2753f4ce
AD		 1303
1304 /* Flush any pending interrupts */
1305 wr32(E1000_ICR, ~0);
1306
1307 wr32(E1000_IMC, ~mask);
1308 wr32(E1000_ICS, ~mask);
945a5151 1309 wrfl();
9d5c8243
AK		 1310 msleep(10);
1311
2753f4ce 1312 if (adapter->test_icr & mask) {
9d5c8243
AK		 1313 *data = 5;
1314 break;
1315 }
1316 }
1317 }
1318
1319 /* Disable all the interrupts */
2753f4ce 1320 wr32(E1000_IMC, ~0);
945a5151 1321 wrfl();
9d5c8243
AK		 1322 msleep(10);
1323
1324 /* Unhook test interrupt handler */
4eefa8f0
AD		 1325 if (adapter->msix_entries)
1326 free_irq(adapter->msix_entries[0].vector, adapter);
1327 else
1328 free_irq(irq, adapter);
9d5c8243
AK		 1329
1330 return *data;
1331}
1332
1333static void igb_free_desc_rings(struct igb_adapter *adapter)
1334{
d7ee5b3a
AD		 1335 igb_free_tx_resources(&adapter->test_tx_ring);
1336 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1337}
1338
1339static int igb_setup_desc_rings(struct igb_adapter *adapter)
1340{
9d5c8243
AK		 1341 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1342 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1343 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1344 int ret_val;
9d5c8243
AK		 1345
1346 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a 1347 tx_ring->count = IGB_DEFAULT_TXD;
59d71989 1348 tx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1349 tx_ring->netdev = adapter->netdev;
1350 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1351
d7ee5b3a 1352 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1353 ret_val = 1;
1354 goto err_nomem;
1355 }
1356
d7ee5b3a
AD		 1357 igb_setup_tctl(adapter);
1358 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1359
9d5c8243 1360 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a 1361 rx_ring->count = IGB_DEFAULT_RXD;
59d71989 1362 rx_ring->dev = &adapter->pdev->dev;
d7ee5b3a 1363 rx_ring->netdev = adapter->netdev;
d7ee5b3a
AD		 1364 rx_ring->reg_idx = adapter->vfs_allocated_count;
1365
1366 if (igb_setup_rx_resources(rx_ring)) {
1367 ret_val = 3;
9d5c8243
AK		 1368 goto err_nomem;
1369 }
9d5c8243 1370
d7ee5b3a
AD		 1371 /* set the default queue to queue 0 of PF */
1372 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1373
d7ee5b3a
AD		 1374 /* enable receive ring */
1375 igb_setup_rctl(adapter);
1376 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1377
cd392f5c 1378 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1379
1380 return 0;
1381
1382err_nomem:
1383 igb_free_desc_rings(adapter);
1384 return ret_val;
1385}
1386
1387static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1388{
1389 struct e1000_hw *hw = &adapter->hw;
1390
1391 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1392 igb_write_phy_reg(hw, 29, 0x001F);
1393 igb_write_phy_reg(hw, 30, 0x8FFC);
1394 igb_write_phy_reg(hw, 29, 0x001A);
1395 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1396}
1397
1398static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1399{
1400 struct e1000_hw *hw = &adapter->hw;
1401 u32 ctrl_reg = 0;
9d5c8243
AK		 1402
1403 hw->mac.autoneg = false;
1404
1405 if (hw->phy.type == e1000_phy_m88) {
1406 /* Auto-MDI/MDIX Off */
f5f4cf08 1407 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
9d5c8243 1408 /* reset to update Auto-MDI/MDIX */
f5f4cf08 1409 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
9d5c8243 1410 /* autoneg off */
f5f4cf08 1411 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
55cac248
AD		 1412 } else if (hw->phy.type == e1000_phy_82580) {
1413 /* enable MII loopback */
1414 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
9d5c8243
AK		 1415 }
1416
1417 ctrl_reg = rd32(E1000_CTRL);
1418
1419 /* force 1000, set loopback */
f5f4cf08 1420 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1421
1422 /* Now set up the MAC to the same speed/duplex as the PHY. */
1423 ctrl_reg = rd32(E1000_CTRL);
1424 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1425 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1426 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1427 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1428 E1000_CTRL_FD | /* Force Duplex to FULL */
1429 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1430
cdfa9f64 1431 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1432 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1433
1434 wr32(E1000_CTRL, ctrl_reg);
1435
1436 /* Disable the receiver on the PHY so when a cable is plugged in, the
1437 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1438 */
1439 if (hw->phy.type == e1000_phy_m88)
1440 igb_phy_disable_receiver(adapter);
1441
1442 udelay(500);
1443
1444 return 0;
1445}
1446
1447static int igb_set_phy_loopback(struct igb_adapter *adapter)
1448{
1449 return igb_integrated_phy_loopback(adapter);
1450}
1451
1452static int igb_setup_loopback_test(struct igb_adapter *adapter)
1453{
1454 struct e1000_hw *hw = &adapter->hw;
2d064c06 1455 u32 reg;
9d5c8243 1456
317f66bd
AD		 1457 reg = rd32(E1000_CTRL_EXT);
1458
1459 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1460 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
a14bc2bb
RH		 1461 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1462 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1463 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1464 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1465
1466 /* Enable DH89xxCC MPHY for near end loopback */
1467 reg = rd32(E1000_MPHY_ADDR_CTL);
1468 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1469 E1000_MPHY_PCS_CLK_REG_OFFSET;
1470 wr32(E1000_MPHY_ADDR_CTL, reg);
1471
1472 reg = rd32(E1000_MPHY_DATA);
1473 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1474 wr32(E1000_MPHY_DATA, reg);
1475 }
1476
2d064c06
AD		 1477 reg = rd32(E1000_RCTL);
1478 reg |= E1000_RCTL_LBM_TCVR;
1479 wr32(E1000_RCTL, reg);
1480
1481 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1482
1483 reg = rd32(E1000_CTRL);
1484 reg &= ~(E1000_CTRL_RFCE |
1485 E1000_CTRL_TFCE |
1486 E1000_CTRL_LRST);
1487 reg |= E1000_CTRL_SLU |
2753f4ce 1488 E1000_CTRL_FD;
2d064c06
AD		 1489 wr32(E1000_CTRL, reg);
1490
1491 /* Unset switch control to serdes energy detect */
1492 reg = rd32(E1000_CONNSW);
1493 reg &= ~E1000_CONNSW_ENRGSRC;
1494 wr32(E1000_CONNSW, reg);
1495
1496 /* Set PCS register for forced speed */
1497 reg = rd32(E1000_PCS_LCTL);
1498 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1499 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1500 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1501 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1502 E1000_PCS_LCTL_FSD | /* Force Speed */
1503 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1504 wr32(E1000_PCS_LCTL, reg);
1505
9d5c8243 1506 return 0;
9d5c8243
AK		 1507 }
1508
317f66bd 1509 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1510}
1511
1512static void igb_loopback_cleanup(struct igb_adapter *adapter)
1513{
1514 struct e1000_hw *hw = &adapter->hw;
1515 u32 rctl;
1516 u16 phy_reg;
1517
a14bc2bb
RH		 1518 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1519 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1520 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1521 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1522 u32 reg;
1523
1524 /* Disable near end loopback on DH89xxCC */
1525 reg = rd32(E1000_MPHY_ADDR_CTL);
1526 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1527 E1000_MPHY_PCS_CLK_REG_OFFSET;
1528 wr32(E1000_MPHY_ADDR_CTL, reg);
1529
1530 reg = rd32(E1000_MPHY_DATA);
1531 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1532 wr32(E1000_MPHY_DATA, reg);
1533 }
1534
9d5c8243
AK		 1535 rctl = rd32(E1000_RCTL);
1536 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1537 wr32(E1000_RCTL, rctl);
1538
1539 hw->mac.autoneg = true;
f5f4cf08 1540 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1541 if (phy_reg & MII_CR_LOOPBACK) {
1542 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1543 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1544 igb_phy_sw_reset(hw);
1545 }
1546}
1547
1548static void igb_create_lbtest_frame(struct sk_buff *skb,
1549 unsigned int frame_size)
1550{
1551 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1552 frame_size /= 2;
1553 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1554 memset(&skb->data[frame_size + 10], 0xBE, 1);
1555 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1556}
1557
1558static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1559{
317f66bd
AD		 1560 frame_size /= 2;
1561 if (*(skb->data + 3) == 0xFF) {
1562 if ((*(skb->data + frame_size + 10) == 0xBE) &&
1563 (*(skb->data + frame_size + 12) == 0xAF)) {
9d5c8243 1564 return 0;
317f66bd
AD		 1565 }
1566 }
9d5c8243
AK		 1567 return 13;
1568}
1569
ad93d17e
AD		 1570static int igb_clean_test_rings(struct igb_ring *rx_ring,
1571 struct igb_ring *tx_ring,
1572 unsigned int size)
1573{
1574 union e1000_adv_rx_desc *rx_desc;
06034649
AD		 1575 struct igb_rx_buffer *rx_buffer_info;
1576 struct igb_tx_buffer *tx_buffer_info;
6ad4edfc 1577 u16 rx_ntc, tx_ntc, count = 0;
ad93d17e
AD		 1578
1579 /* initialize next to clean and descriptor values */
1580 rx_ntc = rx_ring->next_to_clean;
1581 tx_ntc = tx_ring->next_to_clean;
60136906 1582 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e 1583
3ceb90fd 1584 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
ad93d17e 1585 /* check rx buffer */
06034649 1586 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
ad93d17e
AD		 1587
1588 /* unmap rx buffer, will be remapped by alloc_rx_buffers */
59d71989 1589 dma_unmap_single(rx_ring->dev,
06034649 1590 rx_buffer_info->dma,
44390ca6 1591 IGB_RX_HDR_LEN,
59d71989 1592 DMA_FROM_DEVICE);
06034649 1593 rx_buffer_info->dma = 0;
ad93d17e
AD		 1594
1595 /* verify contents of skb */
06034649 1596 if (!igb_check_lbtest_frame(rx_buffer_info->skb, size))
ad93d17e
AD		 1597 count++;
1598
1599 /* unmap buffer on tx side */
06034649
AD		 1600 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1601 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
ad93d17e
AD		 1602
1603 /* increment rx/tx next to clean counters */
1604 rx_ntc++;
1605 if (rx_ntc == rx_ring->count)
1606 rx_ntc = 0;
1607 tx_ntc++;
1608 if (tx_ntc == tx_ring->count)
1609 tx_ntc = 0;
1610
1611 /* fetch next descriptor */
60136906 1612 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e
AD		 1613 }
1614
1615 /* re-map buffers to ring, store next to clean values */
cd392f5c 1616 igb_alloc_rx_buffers(rx_ring, count);
ad93d17e
AD		 1617 rx_ring->next_to_clean = rx_ntc;
1618 tx_ring->next_to_clean = tx_ntc;
1619
1620 return count;
1621}
1622
9d5c8243
AK		 1623static int igb_run_loopback_test(struct igb_adapter *adapter)
1624{
9d5c8243
AK		 1625 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1626 struct igb_ring *rx_ring = &adapter->test_rx_ring;
6ad4edfc
AD		 1627 u16 i, j, lc, good_cnt;
1628 int ret_val = 0;
44390ca6 1629 unsigned int size = IGB_RX_HDR_LEN;
ad93d17e
AD		 1630 netdev_tx_t tx_ret_val;
1631 struct sk_buff *skb;
1632
1633 /* allocate test skb */
1634 skb = alloc_skb(size, GFP_KERNEL);
1635 if (!skb)
1636 return 11;
9d5c8243 1637
ad93d17e
AD		 1638 /* place data into test skb */
1639 igb_create_lbtest_frame(skb, size);
1640 skb_put(skb, size);
9d5c8243 1641
317f66bd
AD		 1642 /*
1643 * Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1644 * The idea is to wrap the largest ring a number of times using 64
1645 * send/receive pairs during each loop
1646 */
1647
1648 if (rx_ring->count <= tx_ring->count)
1649 lc = ((tx_ring->count / 64) * 2) + 1;
1650 else
1651 lc = ((rx_ring->count / 64) * 2) + 1;
1652
9d5c8243 1653 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1654 /* reset count of good packets */
9d5c8243 1655 good_cnt = 0;
ad93d17e
AD		 1656
1657 /* place 64 packets on the transmit queue*/
1658 for (i = 0; i < 64; i++) {
1659 skb_get(skb);
cd392f5c 1660 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
ad93d17e 1661 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1662 good_cnt++;
ad93d17e
AD		 1663 }
1664
9d5c8243 1665 if (good_cnt != 64) {
ad93d17e 1666 ret_val = 12;
9d5c8243
AK		 1667 break;
1668 }
ad93d17e
AD		 1669
1670 /* allow 200 milliseconds for packets to go from tx to rx */
1671 msleep(200);
1672
1673 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1674 if (good_cnt != 64) {
1675 ret_val = 13;
9d5c8243
AK		 1676 break;
1677 }
1678 } /* end loop count loop */
ad93d17e
AD		 1679
1680 /* free the original skb */
1681 kfree_skb(skb);
1682
9d5c8243
AK		 1683 return ret_val;
1684}
1685
1686static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1687{
1688 /* PHY loopback cannot be performed if SoL/IDER
1689 * sessions are active */
1690 if (igb_check_reset_block(&adapter->hw)) {
1691 dev_err(&adapter->pdev->dev,
1692 "Cannot do PHY loopback test "
1693 "when SoL/IDER is active.\n");
1694 *data = 0;
1695 goto out;
1696 }
1697 *data = igb_setup_desc_rings(adapter);
1698 if (*data)
1699 goto out;
1700 *data = igb_setup_loopback_test(adapter);
1701 if (*data)
1702 goto err_loopback;
1703 *data = igb_run_loopback_test(adapter);
1704 igb_loopback_cleanup(adapter);
1705
1706err_loopback:
1707 igb_free_desc_rings(adapter);
1708out:
1709 return *data;
1710}
1711
1712static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1713{
1714 struct e1000_hw *hw = &adapter->hw;
1715 *data = 0;
1716 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1717 int i = 0;
1718 hw->mac.serdes_has_link = false;
1719
1720 /* On some blade server designs, link establishment
1721 * could take as long as 2-3 minutes */
1722 do {
1723 hw->mac.ops.check_for_link(&adapter->hw);
1724 if (hw->mac.serdes_has_link)
1725 return *data;
1726 msleep(20);
1727 } while (i++ < 3750);
1728
1729 *data = 1;
1730 } else {
1731 hw->mac.ops.check_for_link(&adapter->hw);
1732 if (hw->mac.autoneg)
1733 msleep(4000);
1734
317f66bd 1735 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1736 *data = 1;
1737 }
1738 return *data;
1739}
1740
1741static void igb_diag_test(struct net_device *netdev,
1742 struct ethtool_test *eth_test, u64 *data)
1743{
1744 struct igb_adapter *adapter = netdev_priv(netdev);
1745 u16 autoneg_advertised;
1746 u8 forced_speed_duplex, autoneg;
1747 bool if_running = netif_running(netdev);
1748
1749 set_bit(__IGB_TESTING, &adapter->state);
1750 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1751 /* Offline tests */
1752
1753 /* save speed, duplex, autoneg settings */
1754 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1755 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1756 autoneg = adapter->hw.mac.autoneg;
1757
1758 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1759
88a268c1
NN		 1760 /* power up link for link test */
1761 igb_power_up_link(adapter);
1762
9d5c8243
AK		 1763 /* Link test performed before hardware reset so autoneg doesn't
1764 * interfere with test result */
1765 if (igb_link_test(adapter, &data[4]))
1766 eth_test->flags |= ETH_TEST_FL_FAILED;
1767
1768 if (if_running)
1769 /* indicate we're in test mode */
1770 dev_close(netdev);
1771 else
1772 igb_reset(adapter);
1773
1774 if (igb_reg_test(adapter, &data[0]))
1775 eth_test->flags |= ETH_TEST_FL_FAILED;
1776
1777 igb_reset(adapter);
1778 if (igb_eeprom_test(adapter, &data[1]))
1779 eth_test->flags |= ETH_TEST_FL_FAILED;
1780
1781 igb_reset(adapter);
1782 if (igb_intr_test(adapter, &data[2]))
1783 eth_test->flags |= ETH_TEST_FL_FAILED;
1784
1785 igb_reset(adapter);
88a268c1
NN		 1786 /* power up link for loopback test */
1787 igb_power_up_link(adapter);
9d5c8243
AK		 1788 if (igb_loopback_test(adapter, &data[3]))
1789 eth_test->flags |= ETH_TEST_FL_FAILED;
1790
1791 /* restore speed, duplex, autoneg settings */
1792 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1793 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1794 adapter->hw.mac.autoneg = autoneg;
1795
1796 /* force this routine to wait until autoneg complete/timeout */
1797 adapter->hw.phy.autoneg_wait_to_complete = true;
1798 igb_reset(adapter);
1799 adapter->hw.phy.autoneg_wait_to_complete = false;
1800
1801 clear_bit(__IGB_TESTING, &adapter->state);
1802 if (if_running)
1803 dev_open(netdev);
1804 } else {
1805 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 1806
1807 /* PHY is powered down when interface is down */
8d420a1b
AD		 1808 if (if_running && igb_link_test(adapter, &data[4]))
1809 eth_test->flags |= ETH_TEST_FL_FAILED;
1810 else
88a268c1 1811 data[4] = 0;
9d5c8243
AK		 1812
1813 /* Online tests aren't run; pass by default */
1814 data[0] = 0;
1815 data[1] = 0;
1816 data[2] = 0;
1817 data[3] = 0;
1818
1819 clear_bit(__IGB_TESTING, &adapter->state);
1820 }
1821 msleep_interruptible(4 * 1000);
1822}
1823
1824static int igb_wol_exclusion(struct igb_adapter *adapter,
1825 struct ethtool_wolinfo *wol)
1826{
1827 struct e1000_hw *hw = &adapter->hw;
1828 int retval = 1; /* fail by default */
1829
1830 switch (hw->device_id) {
1831 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1832 /* WoL not supported */
1833 wol->supported = 0;
1834 break;
1835 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 1836 case E1000_DEV_ID_82576_FIBER:
1837 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 1838 /* Wake events not supported on port B */
1839 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1840 wol->supported = 0;
1841 break;
1842 }
7dfc16fa
AD		 1843 /* return success for non excluded adapter ports */
1844 retval = 0;
1845 break;
c8ea5ea9 1846 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 1847 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 1848 /* quad port adapters only support WoL on port A */
1849 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1850 wol->supported = 0;
1851 break;
1852 }
1853 /* return success for non excluded adapter ports */
1854 retval = 0;
1855 break;
9d5c8243
AK		 1856 default:
1857 /* dual port cards only support WoL on port A from now on
1858 * unless it was enabled in the eeprom for port B
1859 * so exclude FUNC_1 ports from having WoL enabled */
58b8b042 1860 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
9d5c8243
AK		 1861 !adapter->eeprom_wol) {
1862 wol->supported = 0;
1863 break;
1864 }
1865
1866 retval = 0;
1867 }
1868
1869 return retval;
1870}
1871
1872static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1873{
1874 struct igb_adapter *adapter = netdev_priv(netdev);
1875
1876 wol->supported = WAKE_UCAST | WAKE_MCAST |
22939f06
NN		 1877 WAKE_BCAST | WAKE_MAGIC |
1878 WAKE_PHY;
9d5c8243
AK		 1879 wol->wolopts = 0;
1880
1881 /* this function will set ->supported = 0 and return 1 if wol is not
1882 * supported by this hardware */
e1b86d84
RW		 1883 if (igb_wol_exclusion(adapter, wol) ||
1884 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1885 return;
1886
1887 /* apply any specific unsupported masks here */
1888 switch (adapter->hw.device_id) {
1889 default:
1890 break;
1891 }
1892
1893 if (adapter->wol & E1000_WUFC_EX)
1894 wol->wolopts |= WAKE_UCAST;
1895 if (adapter->wol & E1000_WUFC_MC)
1896 wol->wolopts |= WAKE_MCAST;
1897 if (adapter->wol & E1000_WUFC_BC)
1898 wol->wolopts |= WAKE_BCAST;
1899 if (adapter->wol & E1000_WUFC_MAG)
1900 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 1901 if (adapter->wol & E1000_WUFC_LNKC)
1902 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 1903}
1904
1905static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1906{
1907 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 1908
22939f06 1909 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 1910 return -EOPNOTSUPP;
1911
e1b86d84
RW		 1912 if (igb_wol_exclusion(adapter, wol) ||
1913 !device_can_wakeup(&adapter->pdev->dev))
9d5c8243
AK		 1914 return wol->wolopts ? -EOPNOTSUPP : 0;
1915
9d5c8243
AK		 1916 /* these settings will always override what we currently have */
1917 adapter->wol = 0;
1918
1919 if (wol->wolopts & WAKE_UCAST)
1920 adapter->wol |= E1000_WUFC_EX;
1921 if (wol->wolopts & WAKE_MCAST)
1922 adapter->wol |= E1000_WUFC_MC;
1923 if (wol->wolopts & WAKE_BCAST)
1924 adapter->wol |= E1000_WUFC_BC;
1925 if (wol->wolopts & WAKE_MAGIC)
1926 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 1927 if (wol->wolopts & WAKE_PHY)
1928 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 1929 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1930
9d5c8243
AK		 1931 return 0;
1932}
1933
9d5c8243
AK		 1934/* bit defines for adapter->led_status */
1935#define IGB_LED_ON 0
1936
936db355
JK		 1937static int igb_set_phys_id(struct net_device *netdev,
1938 enum ethtool_phys_id_state state)
9d5c8243
AK		 1939{
1940 struct igb_adapter *adapter = netdev_priv(netdev);
1941 struct e1000_hw *hw = &adapter->hw;
1942
936db355
JK		 1943 switch (state) {
1944 case ETHTOOL_ID_ACTIVE:
1945 igb_blink_led(hw);
1946 return 2;
1947 case ETHTOOL_ID_ON:
1948 igb_blink_led(hw);
1949 break;
1950 case ETHTOOL_ID_OFF:
1951 igb_led_off(hw);
1952 break;
1953 case ETHTOOL_ID_INACTIVE:
1954 igb_led_off(hw);
1955 clear_bit(IGB_LED_ON, &adapter->led_status);
1956 igb_cleanup_led(hw);
1957 break;
1958 }
9d5c8243
AK		 1959
1960 return 0;
1961}
1962
1963static int igb_set_coalesce(struct net_device *netdev,
1964 struct ethtool_coalesce *ec)
1965{
1966 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 1967 int i;
9d5c8243
AK		 1968
1969 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1970 ((ec->rx_coalesce_usecs > 3) &&
1971 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1972 (ec->rx_coalesce_usecs == 2))
1973 return -EINVAL;
1974
4fc82adf
AD		 1975 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1976 ((ec->tx_coalesce_usecs > 3) &&
1977 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1978 (ec->tx_coalesce_usecs == 2))
1979 return -EINVAL;
1980
1981 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
1982 return -EINVAL;
1983
831ec0b4
CW		 1984 /* If ITR is disabled, disable DMAC */
1985 if (ec->rx_coalesce_usecs == 0) {
1986 if (adapter->flags & IGB_FLAG_DMAC)
1987 adapter->flags &= ~IGB_FLAG_DMAC;
1988 }
1989
9d5c8243 1990 /* convert to rate of irq's per second */
4fc82adf
AD		 1991 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
1992 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
1993 else
1994 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
1995
1996 /* convert to rate of irq's per second */
1997 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
1998 adapter->tx_itr_setting = adapter->rx_itr_setting;
1999 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2000 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2001 else
2002 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 2003
047e0030
AD		 2004 for (i = 0; i < adapter->num_q_vectors; i++) {
2005 struct igb_q_vector *q_vector = adapter->q_vector[i];
0ba82994
AD		 2006 q_vector->tx.work_limit = adapter->tx_work_limit;
2007 if (q_vector->rx.ring)
4fc82adf
AD		 2008 q_vector->itr_val = adapter->rx_itr_setting;
2009 else
2010 q_vector->itr_val = adapter->tx_itr_setting;
2011 if (q_vector->itr_val && q_vector->itr_val <= 3)
2012 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 2013 q_vector->set_itr = 1;
2014 }
9d5c8243
AK		 2015
2016 return 0;
2017}
2018
2019static int igb_get_coalesce(struct net_device *netdev,
2020 struct ethtool_coalesce *ec)
2021{
2022 struct igb_adapter *adapter = netdev_priv(netdev);
2023
4fc82adf
AD		 2024 if (adapter->rx_itr_setting <= 3)
2025 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 2026 else
4fc82adf
AD		 2027 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2028
2029 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2030 if (adapter->tx_itr_setting <= 3)
2031 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2032 else
2033 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2034 }
9d5c8243
AK		 2035
2036 return 0;
2037}
2038
9d5c8243
AK		 2039static int igb_nway_reset(struct net_device *netdev)
2040{
2041 struct igb_adapter *adapter = netdev_priv(netdev);
2042 if (netif_running(netdev))
2043 igb_reinit_locked(adapter);
2044 return 0;
2045}
2046
2047static int igb_get_sset_count(struct net_device *netdev, int sset)
2048{
2049 switch (sset) {
2050 case ETH_SS_STATS:
2051 return IGB_STATS_LEN;
2052 case ETH_SS_TEST:
2053 return IGB_TEST_LEN;
2054 default:
2055 return -ENOTSUPP;
2056 }
2057}
2058
2059static void igb_get_ethtool_stats(struct net_device *netdev,
2060 struct ethtool_stats *stats, u64 *data)
2061{
2062 struct igb_adapter *adapter = netdev_priv(netdev);
12dcd86b
ED		 2063 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2064 unsigned int start;
2065 struct igb_ring *ring;
2066 int i, j;
128e45eb 2067 char *p;
9d5c8243 2068
12dcd86b
ED		 2069 spin_lock(&adapter->stats64_lock);
2070 igb_update_stats(adapter, net_stats);
317f66bd 2071
9d5c8243 2072 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2073 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2074 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2075 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2076 }
128e45eb
AD		 2077 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2078 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2079 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2080 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2081 }
e21ed353 2082 for (j = 0; j < adapter->num_tx_queues; j++) {
12dcd86b
ED		 2083 u64 restart2;
2084
2085 ring = adapter->tx_ring[j];
2086 do {
2087 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2088 data[i] = ring->tx_stats.packets;
2089 data[i+1] = ring->tx_stats.bytes;
2090 data[i+2] = ring->tx_stats.restart_queue;
2091 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2092 do {
2093 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2094 restart2 = ring->tx_stats.restart_queue2;
2095 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2096 data[i+2] += restart2;
2097
2098 i += IGB_TX_QUEUE_STATS_LEN;
e21ed353 2099 }
9d5c8243 2100 for (j = 0; j < adapter->num_rx_queues; j++) {
12dcd86b
ED		 2101 ring = adapter->rx_ring[j];
2102 do {
2103 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2104 data[i] = ring->rx_stats.packets;
2105 data[i+1] = ring->rx_stats.bytes;
2106 data[i+2] = ring->rx_stats.drops;
2107 data[i+3] = ring->rx_stats.csum_err;
2108 data[i+4] = ring->rx_stats.alloc_failed;
2109 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2110 i += IGB_RX_QUEUE_STATS_LEN;
9d5c8243 2111 }
12dcd86b 2112 spin_unlock(&adapter->stats64_lock);
9d5c8243
AK		 2113}
2114
2115static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2116{
2117 struct igb_adapter *adapter = netdev_priv(netdev);
2118 u8 *p = data;
2119 int i;
2120
2121 switch (stringset) {
2122 case ETH_SS_TEST:
2123 memcpy(data, *igb_gstrings_test,
2124 IGB_TEST_LEN*ETH_GSTRING_LEN);
2125 break;
2126 case ETH_SS_STATS:
2127 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2128 memcpy(p, igb_gstrings_stats[i].stat_string,
2129 ETH_GSTRING_LEN);
2130 p += ETH_GSTRING_LEN;
2131 }
128e45eb
AD		 2132 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2133 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2134 ETH_GSTRING_LEN);
2135 p += ETH_GSTRING_LEN;
2136 }
9d5c8243
AK		 2137 for (i = 0; i < adapter->num_tx_queues; i++) {
2138 sprintf(p, "tx_queue_%u_packets", i);
2139 p += ETH_GSTRING_LEN;
2140 sprintf(p, "tx_queue_%u_bytes", i);
2141 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2142 sprintf(p, "tx_queue_%u_restart", i);
2143 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2144 }
2145 for (i = 0; i < adapter->num_rx_queues; i++) {
2146 sprintf(p, "rx_queue_%u_packets", i);
2147 p += ETH_GSTRING_LEN;
2148 sprintf(p, "rx_queue_%u_bytes", i);
2149 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2150 sprintf(p, "rx_queue_%u_drops", i);
2151 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2152 sprintf(p, "rx_queue_%u_csum_err", i);
2153 p += ETH_GSTRING_LEN;
2154 sprintf(p, "rx_queue_%u_alloc_failed", i);
2155 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2156 }
2157/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2158 break;
2159 }
2160}
2161
0fc0b732 2162static const struct ethtool_ops igb_ethtool_ops = {
9d5c8243
AK		 2163 .get_settings = igb_get_settings,
2164 .set_settings = igb_set_settings,
2165 .get_drvinfo = igb_get_drvinfo,
2166 .get_regs_len = igb_get_regs_len,
2167 .get_regs = igb_get_regs,
2168 .get_wol = igb_get_wol,
2169 .set_wol = igb_set_wol,
2170 .get_msglevel = igb_get_msglevel,
2171 .set_msglevel = igb_set_msglevel,
2172 .nway_reset = igb_nway_reset,
3145535a 2173 .get_link = igb_get_link,
9d5c8243
AK		 2174 .get_eeprom_len = igb_get_eeprom_len,
2175 .get_eeprom = igb_get_eeprom,
2176 .set_eeprom = igb_set_eeprom,
2177 .get_ringparam = igb_get_ringparam,
2178 .set_ringparam = igb_set_ringparam,
2179 .get_pauseparam = igb_get_pauseparam,
2180 .set_pauseparam = igb_set_pauseparam,
9d5c8243
AK		 2181 .self_test = igb_diag_test,
2182 .get_strings = igb_get_strings,
936db355 2183 .set_phys_id = igb_set_phys_id,
9d5c8243
AK		 2184 .get_sset_count = igb_get_sset_count,
2185 .get_ethtool_stats = igb_get_ethtool_stats,
2186 .get_coalesce = igb_get_coalesce,
2187 .set_coalesce = igb_set_coalesce,
2188};
2189
2190void igb_set_ethtool_ops(struct net_device *netdev)
2191{
2192 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2193}
Linux kernel - Deliverables
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