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Merge branch 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
65#define BUILD 3
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
113 /* required last entry */
114 {0, }
115};
116
117MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
118
119void igb_reset(struct igb_adapter *);
120static int igb_setup_all_tx_resources(struct igb_adapter *);
121static int igb_setup_all_rx_resources(struct igb_adapter *);
122static void igb_free_all_tx_resources(struct igb_adapter *);
123static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 124static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 125static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 126static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 127static int igb_sw_init(struct igb_adapter *);
128static int igb_open(struct net_device *);
129static int igb_close(struct net_device *);
53c7d064 130static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 131static void igb_configure_tx(struct igb_adapter *);
132static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 133static void igb_clean_all_tx_rings(struct igb_adapter *);
134static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 135static void igb_clean_tx_ring(struct igb_ring *);
136static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 137static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 138static void igb_update_phy_info(unsigned long);
139static void igb_watchdog(unsigned long);
140static void igb_watchdog_task(struct work_struct *);
cd392f5c 141static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 142static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
143 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 144static int igb_change_mtu(struct net_device *, int);
145static int igb_set_mac(struct net_device *, void *);
68d480c4 146static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 147static irqreturn_t igb_intr(int irq, void *);
148static irqreturn_t igb_intr_msi(int irq, void *);
149static irqreturn_t igb_msix_other(int irq, void *);
047e0030 150static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 151#ifdef CONFIG_IGB_DCA
047e0030 152static void igb_update_dca(struct igb_q_vector *);
fe4506b6 153static void igb_setup_dca(struct igb_adapter *);
421e02f0 154#endif /* CONFIG_IGB_DCA */
661086df 155static int igb_poll(struct napi_struct *, int);
13fde97a 156static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 157static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 158static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
159static void igb_tx_timeout(struct net_device *);
160static void igb_reset_task(struct work_struct *);
c8f44aff 161static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 162static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
163static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 164static void igb_restore_vlan(struct igb_adapter *);
26ad9178 165static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 166static void igb_ping_all_vfs(struct igb_adapter *);
167static void igb_msg_task(struct igb_adapter *);
4ae196df 168static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 169static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 170static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 171static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
172static int igb_ndo_set_vf_vlan(struct net_device *netdev,
173 int vf, u16 vlan, u8 qos);
174static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 175static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
176 bool setting);
8151d294
WM		 177static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
178 struct ifla_vf_info *ivi);
17dc566c 179static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 180
181#ifdef CONFIG_PCI_IOV
0224d663 182static int igb_vf_configure(struct igb_adapter *adapter, int vf);
46a01698 183#endif
9d5c8243 184
9d5c8243 185#ifdef CONFIG_PM
d9dd966d 186#ifdef CONFIG_PM_SLEEP
749ab2cd 187static int igb_suspend(struct device *);
d9dd966d 188#endif
749ab2cd
YZ		 189static int igb_resume(struct device *);
190#ifdef CONFIG_PM_RUNTIME
191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
194#endif
195static const struct dev_pm_ops igb_pm_ops = {
196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
198 igb_runtime_idle)
199};
9d5c8243
AK		 200#endif
201static void igb_shutdown(struct pci_dev *);
fa44f2f1 202static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 203#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 204static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
205static struct notifier_block dca_notifier = {
206 .notifier_call = igb_notify_dca,
207 .next = NULL,
208 .priority = 0
209};
210#endif
9d5c8243
AK		 211#ifdef CONFIG_NET_POLL_CONTROLLER
212/* for netdump / net console */
213static void igb_netpoll(struct net_device *);
214#endif
37680117 215#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 216static unsigned int max_vfs = 0;
217module_param(max_vfs, uint, 0);
218MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
219 "per physical function");
220#endif /* CONFIG_PCI_IOV */
221
9d5c8243
AK		 222static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
223 pci_channel_state_t);
224static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
225static void igb_io_resume(struct pci_dev *);
226
3646f0e5 227static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 228 .error_detected = igb_io_error_detected,
229 .slot_reset = igb_io_slot_reset,
230 .resume = igb_io_resume,
231};
232
b6e0c419 233static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 234
235static struct pci_driver igb_driver = {
236 .name = igb_driver_name,
237 .id_table = igb_pci_tbl,
238 .probe = igb_probe,
9f9a12f8 239 .remove = igb_remove,
9d5c8243 240#ifdef CONFIG_PM
749ab2cd 241 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 242#endif
243 .shutdown = igb_shutdown,
fa44f2f1 244 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 245 .err_handler = &igb_err_handler
246};
247
248MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
249MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
250MODULE_LICENSE("GPL");
251MODULE_VERSION(DRV_VERSION);
252
b3f4d599 253#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
254static int debug = -1;
255module_param(debug, int, 0);
256MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
257
c97ec42a
TI		 258struct igb_reg_info {
259 u32 ofs;
260 char *name;
261};
262
263static const struct igb_reg_info igb_reg_info_tbl[] = {
264
265 /* General Registers */
266 {E1000_CTRL, "CTRL"},
267 {E1000_STATUS, "STATUS"},
268 {E1000_CTRL_EXT, "CTRL_EXT"},
269
270 /* Interrupt Registers */
271 {E1000_ICR, "ICR"},
272
273 /* RX Registers */
274 {E1000_RCTL, "RCTL"},
275 {E1000_RDLEN(0), "RDLEN"},
276 {E1000_RDH(0), "RDH"},
277 {E1000_RDT(0), "RDT"},
278 {E1000_RXDCTL(0), "RXDCTL"},
279 {E1000_RDBAL(0), "RDBAL"},
280 {E1000_RDBAH(0), "RDBAH"},
281
282 /* TX Registers */
283 {E1000_TCTL, "TCTL"},
284 {E1000_TDBAL(0), "TDBAL"},
285 {E1000_TDBAH(0), "TDBAH"},
286 {E1000_TDLEN(0), "TDLEN"},
287 {E1000_TDH(0), "TDH"},
288 {E1000_TDT(0), "TDT"},
289 {E1000_TXDCTL(0), "TXDCTL"},
290 {E1000_TDFH, "TDFH"},
291 {E1000_TDFT, "TDFT"},
292 {E1000_TDFHS, "TDFHS"},
293 {E1000_TDFPC, "TDFPC"},
294
295 /* List Terminator */
296 {}
297};
298
b980ac18 299/* igb_regdump - register printout routine */
c97ec42a
TI		 300static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
301{
302 int n = 0;
303 char rname[16];
304 u32 regs[8];
305
306 switch (reginfo->ofs) {
307 case E1000_RDLEN(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDLEN(n));
310 break;
311 case E1000_RDH(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDH(n));
314 break;
315 case E1000_RDT(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RDT(n));
318 break;
319 case E1000_RXDCTL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RXDCTL(n));
322 break;
323 case E1000_RDBAL(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAL(n));
326 break;
327 case E1000_RDBAH(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAH(n));
330 break;
331 case E1000_TDBAL(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_RDBAL(n));
334 break;
335 case E1000_TDBAH(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDBAH(n));
338 break;
339 case E1000_TDLEN(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDLEN(n));
342 break;
343 case E1000_TDH(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDH(n));
346 break;
347 case E1000_TDT(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TDT(n));
350 break;
351 case E1000_TXDCTL(0):
352 for (n = 0; n < 4; n++)
353 regs[n] = rd32(E1000_TXDCTL(n));
354 break;
355 default:
876d2d6f 356 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 357 return;
358 }
359
360 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 361 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
362 regs[2], regs[3]);
c97ec42a
TI		 363}
364
b980ac18 365/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 366static void igb_dump(struct igb_adapter *adapter)
367{
368 struct net_device *netdev = adapter->netdev;
369 struct e1000_hw *hw = &adapter->hw;
370 struct igb_reg_info *reginfo;
c97ec42a
TI		 371 struct igb_ring *tx_ring;
372 union e1000_adv_tx_desc *tx_desc;
373 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 374 struct igb_ring *rx_ring;
375 union e1000_adv_rx_desc *rx_desc;
376 u32 staterr;
6ad4edfc 377 u16 i, n;
c97ec42a
TI		 378
379 if (!netif_msg_hw(adapter))
380 return;
381
382 /* Print netdevice Info */
383 if (netdev) {
384 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 385 pr_info("Device Name state trans_start "
386 "last_rx\n");
387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
388 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 389 }
390
391 /* Print Registers */
392 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 393 pr_info(" Register Name Value\n");
c97ec42a
TI		 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
395 reginfo->name; reginfo++) {
396 igb_regdump(hw, reginfo);
397 }
398
399 /* Print TX Ring Summary */
400 if (!netdev || !netif_running(netdev))
401 goto exit;
402
403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 405 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 406 struct igb_tx_buffer *buffer_info;
c97ec42a 407 tx_ring = adapter->tx_ring[n];
06034649 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
410 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 411 (u64)dma_unmap_addr(buffer_info, dma),
412 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 413 buffer_info->next_to_watch,
414 (u64)buffer_info->time_stamp);
c97ec42a
TI		 415 }
416
417 /* Print TX Rings */
418 if (!netif_msg_tx_done(adapter))
419 goto rx_ring_summary;
420
421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
422
423 /* Transmit Descriptor Formats
424 *
425 * Advanced Transmit Descriptor
426 * +--------------------------------------------------------------+
427 * 0 | Buffer Address [63:0] |
428 * +--------------------------------------------------------------+
429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
430 * +--------------------------------------------------------------+
431 * 63 46 45 40 39 38 36 35 32 31 24 15 0
432 */
433
434 for (n = 0; n < adapter->num_tx_queues; n++) {
435 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 436 pr_info("------------------------------------\n");
437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
438 pr_info("------------------------------------\n");
439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
440 "[bi->dma ] leng ntw timestamp "
441 "bi->skb\n");
c97ec42a
TI		 442
443 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 444 const char *next_desc;
06034649 445 struct igb_tx_buffer *buffer_info;
60136906 446 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 447 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 448 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 449 if (i == tx_ring->next_to_use &&
450 i == tx_ring->next_to_clean)
451 next_desc = " NTC/U";
452 else if (i == tx_ring->next_to_use)
453 next_desc = " NTU";
454 else if (i == tx_ring->next_to_clean)
455 next_desc = " NTC";
456 else
457 next_desc = "";
458
459 pr_info("T [0x%03X] %016llX %016llX %016llX"
460 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 461 le64_to_cpu(u0->a),
462 le64_to_cpu(u0->b),
c9f14bf3
AD		 463 (u64)dma_unmap_addr(buffer_info, dma),
464 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 465 buffer_info->next_to_watch,
466 (u64)buffer_info->time_stamp,
876d2d6f 467 buffer_info->skb, next_desc);
c97ec42a 468
b669588a 469 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 470 print_hex_dump(KERN_INFO, "",
471 DUMP_PREFIX_ADDRESS,
b669588a 472 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 473 dma_unmap_len(buffer_info, len),
474 true);
c97ec42a
TI		 475 }
476 }
477
478 /* Print RX Rings Summary */
479rx_ring_summary:
480 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 481 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 482 for (n = 0; n < adapter->num_rx_queues; n++) {
483 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 484 pr_info(" %5d %5X %5X\n",
485 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 486 }
487
488 /* Print RX Rings */
489 if (!netif_msg_rx_status(adapter))
490 goto exit;
491
492 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
493
494 /* Advanced Receive Descriptor (Read) Format
495 * 63 1 0
496 * +-----------------------------------------------------+
497 * 0 | Packet Buffer Address [63:1] |A0/NSE|
498 * +----------------------------------------------+------+
499 * 8 | Header Buffer Address [63:1] | DD |
500 * +-----------------------------------------------------+
501 *
502 *
503 * Advanced Receive Descriptor (Write-Back) Format
504 *
505 * 63 48 47 32 31 30 21 20 17 16 4 3 0
506 * +------------------------------------------------------+
507 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
508 * | Checksum Ident | | | | Type | Type |
509 * +------------------------------------------------------+
510 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
511 * +------------------------------------------------------+
512 * 63 48 47 32 31 20 19 0
513 */
514
515 for (n = 0; n < adapter->num_rx_queues; n++) {
516 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 517 pr_info("------------------------------------\n");
518 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
519 pr_info("------------------------------------\n");
520 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
521 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
522 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
523 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 524
525 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 526 const char *next_desc;
06034649
AD		 527 struct igb_rx_buffer *buffer_info;
528 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 529 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 530 u0 = (struct my_u0 *)rx_desc;
531 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 532
533 if (i == rx_ring->next_to_use)
534 next_desc = " NTU";
535 else if (i == rx_ring->next_to_clean)
536 next_desc = " NTC";
537 else
538 next_desc = "";
539
c97ec42a
TI		 540 if (staterr & E1000_RXD_STAT_DD) {
541 /* Descriptor Done */
1a1c225b
AD		 542 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
543 "RWB", i,
c97ec42a
TI		 544 le64_to_cpu(u0->a),
545 le64_to_cpu(u0->b),
1a1c225b 546 next_desc);
c97ec42a 547 } else {
1a1c225b
AD		 548 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
549 "R ", i,
c97ec42a
TI		 550 le64_to_cpu(u0->a),
551 le64_to_cpu(u0->b),
552 (u64)buffer_info->dma,
1a1c225b 553 next_desc);
c97ec42a 554
b669588a 555 if (netif_msg_pktdata(adapter) &&
1a1c225b 556 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 557 print_hex_dump(KERN_INFO, "",
558 DUMP_PREFIX_ADDRESS,
559 16, 1,
b669588a
ET		 560 page_address(buffer_info->page) +
561 buffer_info->page_offset,
de78d1f9 562 IGB_RX_BUFSZ, true);
c97ec42a
TI		 563 }
564 }
c97ec42a
TI		 565 }
566 }
567
568exit:
569 return;
570}
571
b980ac18
JK		 572/**
573 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 574 * @hw: pointer to hardware structure
575 * @i2cctl: Current value of I2CCTL register
576 *
577 * Returns the I2C data bit value
b980ac18 578 **/
441fc6fd
CW		 579static int igb_get_i2c_data(void *data)
580{
581 struct igb_adapter *adapter = (struct igb_adapter *)data;
582 struct e1000_hw *hw = &adapter->hw;
583 s32 i2cctl = rd32(E1000_I2CPARAMS);
584
585 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
586}
587
b980ac18
JK		 588/**
589 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 590 * @data: pointer to hardware structure
591 * @state: I2C data value (0 or 1) to set
592 *
593 * Sets the I2C data bit
b980ac18 594 **/
441fc6fd
CW		 595static void igb_set_i2c_data(void *data, int state)
596{
597 struct igb_adapter *adapter = (struct igb_adapter *)data;
598 struct e1000_hw *hw = &adapter->hw;
599 s32 i2cctl = rd32(E1000_I2CPARAMS);
600
601 if (state)
602 i2cctl |= E1000_I2C_DATA_OUT;
603 else
604 i2cctl &= ~E1000_I2C_DATA_OUT;
605
606 i2cctl &= ~E1000_I2C_DATA_OE_N;
607 i2cctl |= E1000_I2C_CLK_OE_N;
608 wr32(E1000_I2CPARAMS, i2cctl);
609 wrfl();
610
611}
612
b980ac18
JK		 613/**
614 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 615 * @data: pointer to hardware structure
616 * @state: state to set clock
617 *
618 * Sets the I2C clock line to state
b980ac18 619 **/
441fc6fd
CW		 620static void igb_set_i2c_clk(void *data, int state)
621{
622 struct igb_adapter *adapter = (struct igb_adapter *)data;
623 struct e1000_hw *hw = &adapter->hw;
624 s32 i2cctl = rd32(E1000_I2CPARAMS);
625
626 if (state) {
627 i2cctl |= E1000_I2C_CLK_OUT;
628 i2cctl &= ~E1000_I2C_CLK_OE_N;
629 } else {
630 i2cctl &= ~E1000_I2C_CLK_OUT;
631 i2cctl &= ~E1000_I2C_CLK_OE_N;
632 }
633 wr32(E1000_I2CPARAMS, i2cctl);
634 wrfl();
635}
636
b980ac18
JK		 637/**
638 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 639 * @data: pointer to hardware structure
640 *
641 * Gets the I2C clock state
b980ac18 642 **/
441fc6fd
CW		 643static int igb_get_i2c_clk(void *data)
644{
645 struct igb_adapter *adapter = (struct igb_adapter *)data;
646 struct e1000_hw *hw = &adapter->hw;
647 s32 i2cctl = rd32(E1000_I2CPARAMS);
648
649 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
650}
651
652static const struct i2c_algo_bit_data igb_i2c_algo = {
653 .setsda = igb_set_i2c_data,
654 .setscl = igb_set_i2c_clk,
655 .getsda = igb_get_i2c_data,
656 .getscl = igb_get_i2c_clk,
657 .udelay = 5,
658 .timeout = 20,
659};
660
9d5c8243 661/**
b980ac18
JK		 662 * igb_get_hw_dev - return device
663 * @hw: pointer to hardware structure
664 *
665 * used by hardware layer to print debugging information
9d5c8243 666 **/
c041076a 667struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 668{
669 struct igb_adapter *adapter = hw->back;
c041076a 670 return adapter->netdev;
9d5c8243 671}
38c845c7 672
9d5c8243 673/**
b980ac18 674 * igb_init_module - Driver Registration Routine
9d5c8243 675 *
b980ac18
JK		 676 * igb_init_module is the first routine called when the driver is
677 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 678 **/
679static int __init igb_init_module(void)
680{
681 int ret;
876d2d6f 682 pr_info("%s - version %s\n",
9d5c8243
AK		 683 igb_driver_string, igb_driver_version);
684
876d2d6f 685 pr_info("%s\n", igb_copyright);
9d5c8243 686
421e02f0 687#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 688 dca_register_notify(&dca_notifier);
689#endif
bbd98fe4 690 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 691 return ret;
692}
693
694module_init(igb_init_module);
695
696/**
b980ac18 697 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 698 *
b980ac18
JK		 699 * igb_exit_module is called just before the driver is removed
700 * from memory.
9d5c8243
AK		 701 **/
702static void __exit igb_exit_module(void)
703{
421e02f0 704#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 705 dca_unregister_notify(&dca_notifier);
706#endif
9d5c8243
AK		 707 pci_unregister_driver(&igb_driver);
708}
709
710module_exit(igb_exit_module);
711
26bc19ec
AD		 712#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
713/**
b980ac18
JK		 714 * igb_cache_ring_register - Descriptor ring to register mapping
715 * @adapter: board private structure to initialize
26bc19ec 716 *
b980ac18
JK		 717 * Once we know the feature-set enabled for the device, we'll cache
718 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 719 **/
720static void igb_cache_ring_register(struct igb_adapter *adapter)
721{
ee1b9f06 722 int i = 0, j = 0;
047e0030 723 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 724
725 switch (adapter->hw.mac.type) {
726 case e1000_82576:
727 /* The queues are allocated for virtualization such that VF 0
728 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
729 * In order to avoid collision we start at the first free queue
730 * and continue consuming queues in the same sequence
731 */
ee1b9f06 732 if (adapter->vfs_allocated_count) {
a99955fc 733 for (; i < adapter->rss_queues; i++)
3025a446 734 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 735 Q_IDX_82576(i);
ee1b9f06 736 }
26bc19ec 737 case e1000_82575:
55cac248 738 case e1000_82580:
d2ba2ed8 739 case e1000_i350:
ceb5f13b 740 case e1000_i354:
f96a8a0b
CW		 741 case e1000_i210:
742 case e1000_i211:
26bc19ec 743 default:
ee1b9f06 744 for (; i < adapter->num_rx_queues; i++)
3025a446 745 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 746 for (; j < adapter->num_tx_queues; j++)
3025a446 747 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 748 break;
749 }
750}
751
4be000c8
AD		 752/**
753 * igb_write_ivar - configure ivar for given MSI-X vector
754 * @hw: pointer to the HW structure
755 * @msix_vector: vector number we are allocating to a given ring
756 * @index: row index of IVAR register to write within IVAR table
757 * @offset: column offset of in IVAR, should be multiple of 8
758 *
759 * This function is intended to handle the writing of the IVAR register
760 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
761 * each containing an cause allocation for an Rx and Tx ring, and a
762 * variable number of rows depending on the number of queues supported.
763 **/
764static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
765 int index, int offset)
766{
767 u32 ivar = array_rd32(E1000_IVAR0, index);
768
769 /* clear any bits that are currently set */
770 ivar &= ~((u32)0xFF << offset);
771
772 /* write vector and valid bit */
773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
774
775 array_wr32(E1000_IVAR0, index, ivar);
776}
777
9d5c8243 778#define IGB_N0_QUEUE -1
047e0030 779static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 780{
047e0030 781 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 782 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 783 int rx_queue = IGB_N0_QUEUE;
784 int tx_queue = IGB_N0_QUEUE;
4be000c8 785 u32 msixbm = 0;
047e0030 786
0ba82994
AD		 787 if (q_vector->rx.ring)
788 rx_queue = q_vector->rx.ring->reg_idx;
789 if (q_vector->tx.ring)
790 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 791
792 switch (hw->mac.type) {
793 case e1000_82575:
9d5c8243 794 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 795 * bitmask for the EICR/EIMS/EIMC registers. To assign one
796 * or more queues to a vector, we write the appropriate bits
797 * into the MSIXBM register for that vector.
798 */
047e0030 799 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 801 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 803 if (!adapter->msix_entries && msix_vector == 0)
804 msixbm |= E1000_EIMS_OTHER;
9d5c8243 805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 806 q_vector->eims_value = msixbm;
2d064c06
AD		 807 break;
808 case e1000_82576:
b980ac18 809 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 810 * with 8 rows. The ordering is column-major so we use the
811 * lower 3 bits as the row index, and the 4th bit as the
812 * column offset.
813 */
814 if (rx_queue > IGB_N0_QUEUE)
815 igb_write_ivar(hw, msix_vector,
816 rx_queue & 0x7,
817 (rx_queue & 0x8) << 1);
818 if (tx_queue > IGB_N0_QUEUE)
819 igb_write_ivar(hw, msix_vector,
820 tx_queue & 0x7,
821 ((tx_queue & 0x8) << 1) + 8);
047e0030 822 q_vector->eims_value = 1 << msix_vector;
2d064c06 823 break;
55cac248 824 case e1000_82580:
d2ba2ed8 825 case e1000_i350:
ceb5f13b 826 case e1000_i354:
f96a8a0b
CW		 827 case e1000_i210:
828 case e1000_i211:
b980ac18 829 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 830 * however instead of ordering column-major we have things
831 * ordered row-major. So we traverse the table by using
832 * bit 0 as the column offset, and the remaining bits as the
833 * row index.
834 */
835 if (rx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 rx_queue >> 1,
838 (rx_queue & 0x1) << 4);
839 if (tx_queue > IGB_N0_QUEUE)
840 igb_write_ivar(hw, msix_vector,
841 tx_queue >> 1,
842 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 843 q_vector->eims_value = 1 << msix_vector;
844 break;
2d064c06
AD		 845 default:
846 BUG();
847 break;
848 }
26b39276
AD		 849
850 /* add q_vector eims value to global eims_enable_mask */
851 adapter->eims_enable_mask |= q_vector->eims_value;
852
853 /* configure q_vector to set itr on first interrupt */
854 q_vector->set_itr = 1;
9d5c8243
AK		 855}
856
857/**
b980ac18
JK		 858 * igb_configure_msix - Configure MSI-X hardware
859 * @adapter: board private structure to initialize
9d5c8243 860 *
b980ac18
JK		 861 * igb_configure_msix sets up the hardware to properly
862 * generate MSI-X interrupts.
9d5c8243
AK		 863 **/
864static void igb_configure_msix(struct igb_adapter *adapter)
865{
866 u32 tmp;
867 int i, vector = 0;
868 struct e1000_hw *hw = &adapter->hw;
869
870 adapter->eims_enable_mask = 0;
9d5c8243
AK		 871
872 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 873 switch (hw->mac.type) {
874 case e1000_82575:
9d5c8243
AK		 875 tmp = rd32(E1000_CTRL_EXT);
876 /* enable MSI-X PBA support*/
877 tmp |= E1000_CTRL_EXT_PBA_CLR;
878
879 /* Auto-Mask interrupts upon ICR read. */
880 tmp |= E1000_CTRL_EXT_EIAME;
881 tmp |= E1000_CTRL_EXT_IRCA;
882
883 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 884
885 /* enable msix_other interrupt */
b980ac18 886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 887 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 888
2d064c06
AD		 889 break;
890
891 case e1000_82576:
55cac248 892 case e1000_82580:
d2ba2ed8 893 case e1000_i350:
ceb5f13b 894 case e1000_i354:
f96a8a0b
CW		 895 case e1000_i210:
896 case e1000_i211:
047e0030 897 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 898 * won't stick. And it will take days to debug.
899 */
047e0030 900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 901 E1000_GPIE_PBA | E1000_GPIE_EIAME |
902 E1000_GPIE_NSICR);
047e0030
AD		 903
904 /* enable msix_other interrupt */
905 adapter->eims_other = 1 << vector;
2d064c06 906 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 907
047e0030 908 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 909 break;
910 default:
911 /* do nothing, since nothing else supports MSI-X */
912 break;
913 } /* switch (hw->mac.type) */
047e0030
AD		 914
915 adapter->eims_enable_mask |= adapter->eims_other;
916
26b39276
AD		 917 for (i = 0; i < adapter->num_q_vectors; i++)
918 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 919
9d5c8243
AK		 920 wrfl();
921}
922
923/**
b980ac18
JK		 924 * igb_request_msix - Initialize MSI-X interrupts
925 * @adapter: board private structure to initialize
9d5c8243 926 *
b980ac18
JK		 927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
928 * kernel.
9d5c8243
AK		 929 **/
930static int igb_request_msix(struct igb_adapter *adapter)
931{
932 struct net_device *netdev = adapter->netdev;
047e0030 933 struct e1000_hw *hw = &adapter->hw;
52285b76 934 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 935
047e0030 936 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 937 igb_msix_other, 0, netdev->name, adapter);
047e0030 938 if (err)
52285b76 939 goto err_out;
047e0030
AD		 940
941 for (i = 0; i < adapter->num_q_vectors; i++) {
942 struct igb_q_vector *q_vector = adapter->q_vector[i];
943
52285b76
SA		 944 vector++;
945
047e0030
AD		 946 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
947
0ba82994 948 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 949 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 950 q_vector->rx.ring->queue_index);
951 else if (q_vector->tx.ring)
047e0030 952 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 953 q_vector->tx.ring->queue_index);
954 else if (q_vector->rx.ring)
047e0030 955 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 956 q_vector->rx.ring->queue_index);
9d5c8243 957 else
047e0030
AD		 958 sprintf(q_vector->name, "%s-unused", netdev->name);
959
9d5c8243 960 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 961 igb_msix_ring, 0, q_vector->name,
962 q_vector);
9d5c8243 963 if (err)
52285b76 964 goto err_free;
9d5c8243
AK		 965 }
966
9d5c8243
AK		 967 igb_configure_msix(adapter);
968 return 0;
52285b76
SA		 969
970err_free:
971 /* free already assigned IRQs */
972 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
973
974 vector--;
975 for (i = 0; i < vector; i++) {
976 free_irq(adapter->msix_entries[free_vector++].vector,
977 adapter->q_vector[i]);
978 }
979err_out:
9d5c8243
AK		 980 return err;
981}
982
983static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
984{
985 if (adapter->msix_entries) {
986 pci_disable_msix(adapter->pdev);
987 kfree(adapter->msix_entries);
988 adapter->msix_entries = NULL;
047e0030 989 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 990 pci_disable_msi(adapter->pdev);
047e0030 991 }
9d5c8243
AK		 992}
993
5536d210 994/**
b980ac18
JK		 995 * igb_free_q_vector - Free memory allocated for specific interrupt vector
996 * @adapter: board private structure to initialize
997 * @v_idx: Index of vector to be freed
5536d210 998 *
b980ac18
JK		 999 * This function frees the memory allocated to the q_vector. In addition if
1000 * NAPI is enabled it will delete any references to the NAPI struct prior
1001 * to freeing the q_vector.
5536d210
AD		 1002 **/
1003static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1004{
1005 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1006
1007 if (q_vector->tx.ring)
1008 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1009
1010 if (q_vector->rx.ring)
1011 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1012
1013 adapter->q_vector[v_idx] = NULL;
1014 netif_napi_del(&q_vector->napi);
1015
b980ac18 1016 /* ixgbe_get_stats64() might access the rings on this vector,
5536d210
AD		 1017 * we must wait a grace period before freeing it.
1018 */
1019 kfree_rcu(q_vector, rcu);
1020}
1021
047e0030 1022/**
b980ac18
JK		 1023 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1024 * @adapter: board private structure to initialize
047e0030 1025 *
b980ac18
JK		 1026 * This function frees the memory allocated to the q_vectors. In addition if
1027 * NAPI is enabled it will delete any references to the NAPI struct prior
1028 * to freeing the q_vector.
047e0030
AD		 1029 **/
1030static void igb_free_q_vectors(struct igb_adapter *adapter)
1031{
5536d210
AD		 1032 int v_idx = adapter->num_q_vectors;
1033
1034 adapter->num_tx_queues = 0;
1035 adapter->num_rx_queues = 0;
047e0030 1036 adapter->num_q_vectors = 0;
5536d210
AD		 1037
1038 while (v_idx--)
1039 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1040}
1041
1042/**
b980ac18
JK		 1043 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1044 * @adapter: board private structure to initialize
047e0030 1045 *
b980ac18
JK		 1046 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1047 * MSI-X interrupts allocated.
047e0030
AD		 1048 */
1049static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1050{
047e0030
AD		 1051 igb_free_q_vectors(adapter);
1052 igb_reset_interrupt_capability(adapter);
1053}
9d5c8243
AK		 1054
1055/**
b980ac18
JK		 1056 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1057 * @adapter: board private structure to initialize
1058 * @msix: boolean value of MSIX capability
9d5c8243 1059 *
b980ac18
JK		 1060 * Attempt to configure interrupts using the best available
1061 * capabilities of the hardware and kernel.
9d5c8243 1062 **/
53c7d064 1063static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1064{
1065 int err;
1066 int numvecs, i;
1067
53c7d064
SA		 1068 if (!msix)
1069 goto msi_only;
1070
83b7180d 1071 /* Number of supported queues. */
a99955fc 1072 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1073 if (adapter->vfs_allocated_count)
1074 adapter->num_tx_queues = 1;
1075 else
1076 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1077
b980ac18 1078 /* start with one vector for every Rx queue */
047e0030
AD		 1079 numvecs = adapter->num_rx_queues;
1080
b980ac18 1081 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1082 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1083 numvecs += adapter->num_tx_queues;
047e0030
AD		 1084
1085 /* store the number of vectors reserved for queues */
1086 adapter->num_q_vectors = numvecs;
1087
1088 /* add 1 vector for link status interrupts */
1089 numvecs++;
9d5c8243
AK		 1090 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1091 GFP_KERNEL);
f96a8a0b 1092
9d5c8243
AK		 1093 if (!adapter->msix_entries)
1094 goto msi_only;
1095
1096 for (i = 0; i < numvecs; i++)
1097 adapter->msix_entries[i].entry = i;
1098
1099 err = pci_enable_msix(adapter->pdev,
1100 adapter->msix_entries,
1101 numvecs);
1102 if (err == 0)
0c2cc02e 1103 return;
9d5c8243
AK		 1104
1105 igb_reset_interrupt_capability(adapter);
1106
1107 /* If we can't do MSI-X, try MSI */
1108msi_only:
2a3abf6d
AD		 1109#ifdef CONFIG_PCI_IOV
1110 /* disable SR-IOV for non MSI-X configurations */
1111 if (adapter->vf_data) {
1112 struct e1000_hw *hw = &adapter->hw;
1113 /* disable iov and allow time for transactions to clear */
1114 pci_disable_sriov(adapter->pdev);
1115 msleep(500);
1116
1117 kfree(adapter->vf_data);
1118 adapter->vf_data = NULL;
1119 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1120 wrfl();
2a3abf6d
AD		 1121 msleep(100);
1122 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1123 }
1124#endif
4fc82adf 1125 adapter->vfs_allocated_count = 0;
a99955fc 1126 adapter->rss_queues = 1;
4fc82adf 1127 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1128 adapter->num_rx_queues = 1;
661086df 1129 adapter->num_tx_queues = 1;
047e0030 1130 adapter->num_q_vectors = 1;
9d5c8243 1131 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1132 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1133}
1134
5536d210
AD		 1135static void igb_add_ring(struct igb_ring *ring,
1136 struct igb_ring_container *head)
1137{
1138 head->ring = ring;
1139 head->count++;
1140}
1141
047e0030 1142/**
b980ac18
JK		 1143 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1144 * @adapter: board private structure to initialize
1145 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1146 * @v_idx: index of vector in adapter struct
1147 * @txr_count: total number of Tx rings to allocate
1148 * @txr_idx: index of first Tx ring to allocate
1149 * @rxr_count: total number of Rx rings to allocate
1150 * @rxr_idx: index of first Rx ring to allocate
047e0030 1151 *
b980ac18 1152 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1153 **/
5536d210
AD		 1154static int igb_alloc_q_vector(struct igb_adapter *adapter,
1155 int v_count, int v_idx,
1156 int txr_count, int txr_idx,
1157 int rxr_count, int rxr_idx)
047e0030
AD		 1158{
1159 struct igb_q_vector *q_vector;
5536d210
AD		 1160 struct igb_ring *ring;
1161 int ring_count, size;
047e0030 1162
5536d210
AD		 1163 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1164 if (txr_count > 1 || rxr_count > 1)
1165 return -ENOMEM;
1166
1167 ring_count = txr_count + rxr_count;
1168 size = sizeof(struct igb_q_vector) +
1169 (sizeof(struct igb_ring) * ring_count);
1170
1171 /* allocate q_vector and rings */
1172 q_vector = kzalloc(size, GFP_KERNEL);
1173 if (!q_vector)
1174 return -ENOMEM;
1175
1176 /* initialize NAPI */
1177 netif_napi_add(adapter->netdev, &q_vector->napi,
1178 igb_poll, 64);
1179
1180 /* tie q_vector and adapter together */
1181 adapter->q_vector[v_idx] = q_vector;
1182 q_vector->adapter = adapter;
1183
1184 /* initialize work limits */
1185 q_vector->tx.work_limit = adapter->tx_work_limit;
1186
1187 /* initialize ITR configuration */
1188 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1189 q_vector->itr_val = IGB_START_ITR;
1190
1191 /* initialize pointer to rings */
1192 ring = q_vector->ring;
1193
4e227667
AD		 1194 /* intialize ITR */
1195 if (rxr_count) {
1196 /* rx or rx/tx vector */
1197 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1198 q_vector->itr_val = adapter->rx_itr_setting;
1199 } else {
1200 /* tx only vector */
1201 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1202 q_vector->itr_val = adapter->tx_itr_setting;
1203 }
1204
5536d210
AD		 1205 if (txr_count) {
1206 /* assign generic ring traits */
1207 ring->dev = &adapter->pdev->dev;
1208 ring->netdev = adapter->netdev;
1209
1210 /* configure backlink on ring */
1211 ring->q_vector = q_vector;
1212
1213 /* update q_vector Tx values */
1214 igb_add_ring(ring, &q_vector->tx);
1215
1216 /* For 82575, context index must be unique per ring. */
1217 if (adapter->hw.mac.type == e1000_82575)
1218 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1219
1220 /* apply Tx specific ring traits */
1221 ring->count = adapter->tx_ring_count;
1222 ring->queue_index = txr_idx;
1223
1224 /* assign ring to adapter */
1225 adapter->tx_ring[txr_idx] = ring;
1226
1227 /* push pointer to next ring */
1228 ring++;
047e0030 1229 }
81c2fc22 1230
5536d210
AD		 1231 if (rxr_count) {
1232 /* assign generic ring traits */
1233 ring->dev = &adapter->pdev->dev;
1234 ring->netdev = adapter->netdev;
047e0030 1235
5536d210
AD		 1236 /* configure backlink on ring */
1237 ring->q_vector = q_vector;
047e0030 1238
5536d210
AD		 1239 /* update q_vector Rx values */
1240 igb_add_ring(ring, &q_vector->rx);
047e0030 1241
5536d210
AD		 1242 /* set flag indicating ring supports SCTP checksum offload */
1243 if (adapter->hw.mac.type >= e1000_82576)
1244 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1245
ceb5f13b
CW		 1246 /*
1247 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1248 * have the tag byte-swapped.
b980ac18 1249 */
5536d210
AD		 1250 if (adapter->hw.mac.type >= e1000_i350)
1251 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1252
5536d210
AD		 1253 /* apply Rx specific ring traits */
1254 ring->count = adapter->rx_ring_count;
1255 ring->queue_index = rxr_idx;
1256
1257 /* assign ring to adapter */
1258 adapter->rx_ring[rxr_idx] = ring;
1259 }
1260
1261 return 0;
047e0030
AD		 1262}
1263
5536d210 1264
047e0030 1265/**
b980ac18
JK		 1266 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1267 * @adapter: board private structure to initialize
047e0030 1268 *
b980ac18
JK		 1269 * We allocate one q_vector per queue interrupt. If allocation fails we
1270 * return -ENOMEM.
047e0030 1271 **/
5536d210 1272static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1273{
5536d210
AD		 1274 int q_vectors = adapter->num_q_vectors;
1275 int rxr_remaining = adapter->num_rx_queues;
1276 int txr_remaining = adapter->num_tx_queues;
1277 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1278 int err;
047e0030 1279
5536d210
AD		 1280 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1281 for (; rxr_remaining; v_idx++) {
1282 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1283 0, 0, 1, rxr_idx);
047e0030 1284
5536d210
AD		 1285 if (err)
1286 goto err_out;
1287
1288 /* update counts and index */
1289 rxr_remaining--;
1290 rxr_idx++;
047e0030 1291 }
047e0030 1292 }
5536d210
AD		 1293
1294 for (; v_idx < q_vectors; v_idx++) {
1295 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1296 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1297 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1298 tqpv, txr_idx, rqpv, rxr_idx);
1299
1300 if (err)
1301 goto err_out;
1302
1303 /* update counts and index */
1304 rxr_remaining -= rqpv;
1305 txr_remaining -= tqpv;
1306 rxr_idx++;
1307 txr_idx++;
1308 }
1309
047e0030 1310 return 0;
5536d210
AD		 1311
1312err_out:
1313 adapter->num_tx_queues = 0;
1314 adapter->num_rx_queues = 0;
1315 adapter->num_q_vectors = 0;
1316
1317 while (v_idx--)
1318 igb_free_q_vector(adapter, v_idx);
1319
1320 return -ENOMEM;
047e0030
AD		 1321}
1322
1323/**
b980ac18
JK		 1324 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1325 * @adapter: board private structure to initialize
1326 * @msix: boolean value of MSIX capability
047e0030 1327 *
b980ac18 1328 * This function initializes the interrupts and allocates all of the queues.
047e0030 1329 **/
53c7d064 1330static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1331{
1332 struct pci_dev *pdev = adapter->pdev;
1333 int err;
1334
53c7d064 1335 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1336
1337 err = igb_alloc_q_vectors(adapter);
1338 if (err) {
1339 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1340 goto err_alloc_q_vectors;
1341 }
1342
5536d210 1343 igb_cache_ring_register(adapter);
047e0030
AD		 1344
1345 return 0;
5536d210 1346
047e0030
AD		 1347err_alloc_q_vectors:
1348 igb_reset_interrupt_capability(adapter);
1349 return err;
1350}
1351
9d5c8243 1352/**
b980ac18
JK		 1353 * igb_request_irq - initialize interrupts
1354 * @adapter: board private structure to initialize
9d5c8243 1355 *
b980ac18
JK		 1356 * Attempts to configure interrupts using the best available
1357 * capabilities of the hardware and kernel.
9d5c8243
AK		 1358 **/
1359static int igb_request_irq(struct igb_adapter *adapter)
1360{
1361 struct net_device *netdev = adapter->netdev;
047e0030 1362 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1363 int err = 0;
1364
1365 if (adapter->msix_entries) {
1366 err = igb_request_msix(adapter);
844290e5 1367 if (!err)
9d5c8243 1368 goto request_done;
9d5c8243 1369 /* fall back to MSI */
5536d210
AD		 1370 igb_free_all_tx_resources(adapter);
1371 igb_free_all_rx_resources(adapter);
53c7d064 1372
047e0030 1373 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1374 err = igb_init_interrupt_scheme(adapter, false);
1375 if (err)
047e0030 1376 goto request_done;
53c7d064 1377
047e0030
AD		 1378 igb_setup_all_tx_resources(adapter);
1379 igb_setup_all_rx_resources(adapter);
53c7d064 1380 igb_configure(adapter);
9d5c8243 1381 }
844290e5 1382
c74d588e
AD		 1383 igb_assign_vector(adapter->q_vector[0], 0);
1384
7dfc16fa 1385 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1386 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1387 netdev->name, adapter);
9d5c8243
AK		 1388 if (!err)
1389 goto request_done;
047e0030 1390
9d5c8243
AK		 1391 /* fall back to legacy interrupts */
1392 igb_reset_interrupt_capability(adapter);
7dfc16fa 1393 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1394 }
1395
c74d588e 1396 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1397 netdev->name, adapter);
9d5c8243 1398
6cb5e577 1399 if (err)
c74d588e 1400 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1401 err);
9d5c8243
AK		 1402
1403request_done:
1404 return err;
1405}
1406
1407static void igb_free_irq(struct igb_adapter *adapter)
1408{
9d5c8243
AK		 1409 if (adapter->msix_entries) {
1410 int vector = 0, i;
1411
047e0030 1412 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1413
0d1ae7f4 1414 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1415 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1416 adapter->q_vector[i]);
047e0030
AD		 1417 } else {
1418 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1419 }
9d5c8243
AK		 1420}
1421
1422/**
b980ac18
JK		 1423 * igb_irq_disable - Mask off interrupt generation on the NIC
1424 * @adapter: board private structure
9d5c8243
AK		 1425 **/
1426static void igb_irq_disable(struct igb_adapter *adapter)
1427{
1428 struct e1000_hw *hw = &adapter->hw;
1429
b980ac18 1430 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1431 * mapped into these registers and so clearing the bits can cause
1432 * issues on the VF drivers so we only need to clear what we set
1433 */
9d5c8243 1434 if (adapter->msix_entries) {
2dfd1212
AD		 1435 u32 regval = rd32(E1000_EIAM);
1436 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1437 wr32(E1000_EIMC, adapter->eims_enable_mask);
1438 regval = rd32(E1000_EIAC);
1439 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1440 }
844290e5
PW		 1441
1442 wr32(E1000_IAM, 0);
9d5c8243
AK		 1443 wr32(E1000_IMC, ~0);
1444 wrfl();
81a61859
ET		 1445 if (adapter->msix_entries) {
1446 int i;
1447 for (i = 0; i < adapter->num_q_vectors; i++)
1448 synchronize_irq(adapter->msix_entries[i].vector);
1449 } else {
1450 synchronize_irq(adapter->pdev->irq);
1451 }
9d5c8243
AK		 1452}
1453
1454/**
b980ac18
JK		 1455 * igb_irq_enable - Enable default interrupt generation settings
1456 * @adapter: board private structure
9d5c8243
AK		 1457 **/
1458static void igb_irq_enable(struct igb_adapter *adapter)
1459{
1460 struct e1000_hw *hw = &adapter->hw;
1461
1462 if (adapter->msix_entries) {
06218a8d 1463 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1464 u32 regval = rd32(E1000_EIAC);
1465 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1466 regval = rd32(E1000_EIAM);
1467 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1468 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1469 if (adapter->vfs_allocated_count) {
4ae196df 1470 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1471 ims |= E1000_IMS_VMMB;
1472 }
1473 wr32(E1000_IMS, ims);
844290e5 1474 } else {
55cac248
AD		 1475 wr32(E1000_IMS, IMS_ENABLE_MASK |
1476 E1000_IMS_DRSTA);
1477 wr32(E1000_IAM, IMS_ENABLE_MASK |
1478 E1000_IMS_DRSTA);
844290e5 1479 }
9d5c8243
AK		 1480}
1481
1482static void igb_update_mng_vlan(struct igb_adapter *adapter)
1483{
51466239 1484 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1485 u16 vid = adapter->hw.mng_cookie.vlan_id;
1486 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1487
1488 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1489 /* add VID to filter table */
1490 igb_vfta_set(hw, vid, true);
1491 adapter->mng_vlan_id = vid;
1492 } else {
1493 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1494 }
1495
1496 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1497 (vid != old_vid) &&
b2cb09b1 1498 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1499 /* remove VID from filter table */
1500 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1501 }
1502}
1503
1504/**
b980ac18
JK		 1505 * igb_release_hw_control - release control of the h/w to f/w
1506 * @adapter: address of board private structure
9d5c8243 1507 *
b980ac18
JK		 1508 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1509 * For ASF and Pass Through versions of f/w this means that the
1510 * driver is no longer loaded.
9d5c8243
AK		 1511 **/
1512static void igb_release_hw_control(struct igb_adapter *adapter)
1513{
1514 struct e1000_hw *hw = &adapter->hw;
1515 u32 ctrl_ext;
1516
1517 /* Let firmware take over control of h/w */
1518 ctrl_ext = rd32(E1000_CTRL_EXT);
1519 wr32(E1000_CTRL_EXT,
1520 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1521}
1522
9d5c8243 1523/**
b980ac18
JK		 1524 * igb_get_hw_control - get control of the h/w from f/w
1525 * @adapter: address of board private structure
9d5c8243 1526 *
b980ac18
JK		 1527 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1528 * For ASF and Pass Through versions of f/w this means that
1529 * the driver is loaded.
9d5c8243
AK		 1530 **/
1531static void igb_get_hw_control(struct igb_adapter *adapter)
1532{
1533 struct e1000_hw *hw = &adapter->hw;
1534 u32 ctrl_ext;
1535
1536 /* Let firmware know the driver has taken over */
1537 ctrl_ext = rd32(E1000_CTRL_EXT);
1538 wr32(E1000_CTRL_EXT,
1539 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1540}
1541
9d5c8243 1542/**
b980ac18
JK		 1543 * igb_configure - configure the hardware for RX and TX
1544 * @adapter: private board structure
9d5c8243
AK		 1545 **/
1546static void igb_configure(struct igb_adapter *adapter)
1547{
1548 struct net_device *netdev = adapter->netdev;
1549 int i;
1550
1551 igb_get_hw_control(adapter);
ff41f8dc 1552 igb_set_rx_mode(netdev);
9d5c8243
AK		 1553
1554 igb_restore_vlan(adapter);
9d5c8243 1555
85b430b4 1556 igb_setup_tctl(adapter);
06cf2666 1557 igb_setup_mrqc(adapter);
9d5c8243 1558 igb_setup_rctl(adapter);
85b430b4
AD		 1559
1560 igb_configure_tx(adapter);
9d5c8243 1561 igb_configure_rx(adapter);
662d7205
AD		 1562
1563 igb_rx_fifo_flush_82575(&adapter->hw);
1564
c493ea45 1565 /* call igb_desc_unused which always leaves
9d5c8243 1566 * at least 1 descriptor unused to make sure
b980ac18
JK		 1567 * next_to_use != next_to_clean
1568 */
9d5c8243 1569 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1570 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1571 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1572 }
9d5c8243
AK		 1573}
1574
88a268c1 1575/**
b980ac18
JK		 1576 * igb_power_up_link - Power up the phy/serdes link
1577 * @adapter: address of board private structure
88a268c1
NN		 1578 **/
1579void igb_power_up_link(struct igb_adapter *adapter)
1580{
76886596
AA		 1581 igb_reset_phy(&adapter->hw);
1582
88a268c1
NN		 1583 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1584 igb_power_up_phy_copper(&adapter->hw);
1585 else
1586 igb_power_up_serdes_link_82575(&adapter->hw);
1587}
1588
1589/**
b980ac18
JK		 1590 * igb_power_down_link - Power down the phy/serdes link
1591 * @adapter: address of board private structure
88a268c1
NN		 1592 */
1593static void igb_power_down_link(struct igb_adapter *adapter)
1594{
1595 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1596 igb_power_down_phy_copper_82575(&adapter->hw);
1597 else
1598 igb_shutdown_serdes_link_82575(&adapter->hw);
1599}
9d5c8243
AK		 1600
1601/**
b980ac18
JK		 1602 * igb_up - Open the interface and prepare it to handle traffic
1603 * @adapter: board private structure
9d5c8243 1604 **/
9d5c8243
AK		 1605int igb_up(struct igb_adapter *adapter)
1606{
1607 struct e1000_hw *hw = &adapter->hw;
1608 int i;
1609
1610 /* hardware has been reset, we need to reload some things */
1611 igb_configure(adapter);
1612
1613 clear_bit(__IGB_DOWN, &adapter->state);
1614
0d1ae7f4
AD		 1615 for (i = 0; i < adapter->num_q_vectors; i++)
1616 napi_enable(&(adapter->q_vector[i]->napi));
1617
844290e5 1618 if (adapter->msix_entries)
9d5c8243 1619 igb_configure_msix(adapter);
feeb2721
AD		 1620 else
1621 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1622
1623 /* Clear any pending interrupts. */
1624 rd32(E1000_ICR);
1625 igb_irq_enable(adapter);
1626
d4960307
AD		 1627 /* notify VFs that reset has been completed */
1628 if (adapter->vfs_allocated_count) {
1629 u32 reg_data = rd32(E1000_CTRL_EXT);
1630 reg_data |= E1000_CTRL_EXT_PFRSTD;
1631 wr32(E1000_CTRL_EXT, reg_data);
1632 }
1633
4cb9be7a
JB		 1634 netif_tx_start_all_queues(adapter->netdev);
1635
25568a53
AD		 1636 /* start the watchdog. */
1637 hw->mac.get_link_status = 1;
1638 schedule_work(&adapter->watchdog_task);
1639
9d5c8243
AK		 1640 return 0;
1641}
1642
1643void igb_down(struct igb_adapter *adapter)
1644{
9d5c8243 1645 struct net_device *netdev = adapter->netdev;
330a6d6a 1646 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1647 u32 tctl, rctl;
1648 int i;
1649
1650 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1651 * reschedule our watchdog timer
1652 */
9d5c8243
AK		 1653 set_bit(__IGB_DOWN, &adapter->state);
1654
1655 /* disable receives in the hardware */
1656 rctl = rd32(E1000_RCTL);
1657 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1658 /* flush and sleep below */
1659
fd2ea0a7 1660 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1661
1662 /* disable transmits in the hardware */
1663 tctl = rd32(E1000_TCTL);
1664 tctl &= ~E1000_TCTL_EN;
1665 wr32(E1000_TCTL, tctl);
1666 /* flush both disables and wait for them to finish */
1667 wrfl();
1668 msleep(10);
1669
41f149a2
CW		 1670 igb_irq_disable(adapter);
1671
1672 for (i = 0; i < adapter->num_q_vectors; i++) {
1673 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1674 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1675 }
9d5c8243 1676
9d5c8243
AK		 1677
1678 del_timer_sync(&adapter->watchdog_timer);
1679 del_timer_sync(&adapter->phy_info_timer);
1680
9d5c8243 1681 netif_carrier_off(netdev);
04fe6358
AD		 1682
1683 /* record the stats before reset*/
12dcd86b
ED		 1684 spin_lock(&adapter->stats64_lock);
1685 igb_update_stats(adapter, &adapter->stats64);
1686 spin_unlock(&adapter->stats64_lock);
04fe6358 1687
9d5c8243
AK		 1688 adapter->link_speed = 0;
1689 adapter->link_duplex = 0;
1690
3023682e
JK		 1691 if (!pci_channel_offline(adapter->pdev))
1692 igb_reset(adapter);
9d5c8243
AK		 1693 igb_clean_all_tx_rings(adapter);
1694 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1695#ifdef CONFIG_IGB_DCA
1696
1697 /* since we reset the hardware DCA settings were cleared */
1698 igb_setup_dca(adapter);
1699#endif
9d5c8243
AK		 1700}
1701
1702void igb_reinit_locked(struct igb_adapter *adapter)
1703{
1704 WARN_ON(in_interrupt());
1705 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1706 msleep(1);
1707 igb_down(adapter);
1708 igb_up(adapter);
1709 clear_bit(__IGB_RESETTING, &adapter->state);
1710}
1711
1712void igb_reset(struct igb_adapter *adapter)
1713{
090b1795 1714 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1715 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1716 struct e1000_mac_info *mac = &hw->mac;
1717 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1718 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1719
1720 /* Repartition Pba for greater than 9k mtu
1721 * To take effect CTRL.RST is required.
1722 */
fa4dfae0 1723 switch (mac->type) {
d2ba2ed8 1724 case e1000_i350:
ceb5f13b 1725 case e1000_i354:
55cac248
AD		 1726 case e1000_82580:
1727 pba = rd32(E1000_RXPBS);
1728 pba = igb_rxpbs_adjust_82580(pba);
1729 break;
fa4dfae0 1730 case e1000_82576:
d249be54
AD		 1731 pba = rd32(E1000_RXPBS);
1732 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1733 break;
1734 case e1000_82575:
f96a8a0b
CW		 1735 case e1000_i210:
1736 case e1000_i211:
fa4dfae0
AD		 1737 default:
1738 pba = E1000_PBA_34K;
1739 break;
2d064c06 1740 }
9d5c8243 1741
2d064c06
AD		 1742 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1743 (mac->type < e1000_82576)) {
9d5c8243
AK		 1744 /* adjust PBA for jumbo frames */
1745 wr32(E1000_PBA, pba);
1746
1747 /* To maintain wire speed transmits, the Tx FIFO should be
1748 * large enough to accommodate two full transmit packets,
1749 * rounded up to the next 1KB and expressed in KB. Likewise,
1750 * the Rx FIFO should be large enough to accommodate at least
1751 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1752 * expressed in KB.
1753 */
9d5c8243
AK		 1754 pba = rd32(E1000_PBA);
1755 /* upper 16 bits has Tx packet buffer allocation size in KB */
1756 tx_space = pba >> 16;
1757 /* lower 16 bits has Rx packet buffer allocation size in KB */
1758 pba &= 0xffff;
b980ac18
JK		 1759 /* the Tx fifo also stores 16 bytes of information about the Tx
1760 * but don't include ethernet FCS because hardware appends it
1761 */
9d5c8243 1762 min_tx_space = (adapter->max_frame_size +
85e8d004 1763 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1764 ETH_FCS_LEN) * 2;
1765 min_tx_space = ALIGN(min_tx_space, 1024);
1766 min_tx_space >>= 10;
1767 /* software strips receive CRC, so leave room for it */
1768 min_rx_space = adapter->max_frame_size;
1769 min_rx_space = ALIGN(min_rx_space, 1024);
1770 min_rx_space >>= 10;
1771
1772 /* If current Tx allocation is less than the min Tx FIFO size,
1773 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1774 * allocation, take space away from current Rx allocation
1775 */
9d5c8243
AK		 1776 if (tx_space < min_tx_space &&
1777 ((min_tx_space - tx_space) < pba)) {
1778 pba = pba - (min_tx_space - tx_space);
1779
b980ac18
JK		 1780 /* if short on Rx space, Rx wins and must trump Tx
1781 * adjustment
1782 */
9d5c8243
AK		 1783 if (pba < min_rx_space)
1784 pba = min_rx_space;
1785 }
2d064c06 1786 wr32(E1000_PBA, pba);
9d5c8243 1787 }
9d5c8243
AK		 1788
1789 /* flow control settings */
1790 /* The high water mark must be low enough to fit one full frame
1791 * (or the size used for early receive) above it in the Rx FIFO.
1792 * Set it to the lower of:
1793 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1794 * - the full Rx FIFO size minus one full frame
1795 */
9d5c8243 1796 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1797 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1798
d48507fe 1799 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1800 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1801 fc->pause_time = 0xFFFF;
1802 fc->send_xon = 1;
0cce119a 1803 fc->current_mode = fc->requested_mode;
9d5c8243 1804
4ae196df
AD		 1805 /* disable receive for all VFs and wait one second */
1806 if (adapter->vfs_allocated_count) {
1807 int i;
1808 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1809 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1810
1811 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1812 igb_ping_all_vfs(adapter);
4ae196df
AD		 1813
1814 /* disable transmits and receives */
1815 wr32(E1000_VFRE, 0);
1816 wr32(E1000_VFTE, 0);
1817 }
1818
9d5c8243 1819 /* Allow time for pending master requests to run */
330a6d6a 1820 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1821 wr32(E1000_WUC, 0);
1822
330a6d6a 1823 if (hw->mac.ops.init_hw(hw))
090b1795 1824 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1825
b980ac18 1826 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1827 * control is off when forcing speed.
1828 */
1829 if (!hw->mac.autoneg)
1830 igb_force_mac_fc(hw);
1831
b6e0c419 1832 igb_init_dmac(adapter, pba);
e428893b
CW		 1833#ifdef CONFIG_IGB_HWMON
1834 /* Re-initialize the thermal sensor on i350 devices. */
1835 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1836 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1837 /* If present, re-initialize the external thermal sensor
1838 * interface.
1839 */
1840 if (adapter->ets)
1841 mac->ops.init_thermal_sensor_thresh(hw);
1842 }
1843 }
1844#endif
88a268c1
NN		 1845 if (!netif_running(adapter->netdev))
1846 igb_power_down_link(adapter);
1847
9d5c8243
AK		 1848 igb_update_mng_vlan(adapter);
1849
1850 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1851 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1852
1f6e8178
MV		 1853 /* Re-enable PTP, where applicable. */
1854 igb_ptp_reset(adapter);
1f6e8178 1855
330a6d6a 1856 igb_get_phy_info(hw);
9d5c8243
AK		 1857}
1858
c8f44aff
MM		 1859static netdev_features_t igb_fix_features(struct net_device *netdev,
1860 netdev_features_t features)
b2cb09b1 1861{
b980ac18
JK		 1862 /* Since there is no support for separate Rx/Tx vlan accel
1863 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1864 */
f646968f
PM		 1865 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1866 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1867 else
f646968f 1868 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1869
1870 return features;
1871}
1872
c8f44aff
MM		 1873static int igb_set_features(struct net_device *netdev,
1874 netdev_features_t features)
ac52caa3 1875{
c8f44aff 1876 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1877 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1878
f646968f 1879 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1880 igb_vlan_mode(netdev, features);
1881
89eaefb6
BG		 1882 if (!(changed & NETIF_F_RXALL))
1883 return 0;
1884
1885 netdev->features = features;
1886
1887 if (netif_running(netdev))
1888 igb_reinit_locked(adapter);
1889 else
1890 igb_reset(adapter);
1891
ac52caa3
MM		 1892 return 0;
1893}
1894
2e5c6922 1895static const struct net_device_ops igb_netdev_ops = {
559e9c49 1896 .ndo_open = igb_open,
2e5c6922 1897 .ndo_stop = igb_close,
cd392f5c 1898 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1899 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1900 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1901 .ndo_set_mac_address = igb_set_mac,
1902 .ndo_change_mtu = igb_change_mtu,
1903 .ndo_do_ioctl = igb_ioctl,
1904 .ndo_tx_timeout = igb_tx_timeout,
1905 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1906 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1907 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1908 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1909 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1910 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1911 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1912 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1913#ifdef CONFIG_NET_POLL_CONTROLLER
1914 .ndo_poll_controller = igb_netpoll,
1915#endif
b2cb09b1
JP		 1916 .ndo_fix_features = igb_fix_features,
1917 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1918};
1919
d67974f0
CW		 1920/**
1921 * igb_set_fw_version - Configure version string for ethtool
1922 * @adapter: adapter struct
d67974f0
CW		 1923 **/
1924void igb_set_fw_version(struct igb_adapter *adapter)
1925{
1926 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1927 struct e1000_fw_version fw;
1928
1929 igb_get_fw_version(hw, &fw);
1930
1931 switch (hw->mac.type) {
1932 case e1000_i211:
d67974f0 1933 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1934 "%2d.%2d-%d",
1935 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1936 break;
1937
1938 default:
1939 /* if option is rom valid, display its version too */
1940 if (fw.or_valid) {
1941 snprintf(adapter->fw_version,
1942 sizeof(adapter->fw_version),
1943 "%d.%d, 0x%08x, %d.%d.%d",
1944 fw.eep_major, fw.eep_minor, fw.etrack_id,
1945 fw.or_major, fw.or_build, fw.or_patch);
1946 /* no option rom */
1947 } else {
1948 snprintf(adapter->fw_version,
1949 sizeof(adapter->fw_version),
1950 "%d.%d, 0x%08x",
1951 fw.eep_major, fw.eep_minor, fw.etrack_id);
1952 }
1953 break;
d67974f0 1954 }
d67974f0
CW		 1955 return;
1956}
1957
b980ac18
JK		 1958/**
1959 * igb_init_i2c - Init I2C interface
441fc6fd 1960 * @adapter: pointer to adapter structure
b980ac18 1961 **/
441fc6fd
CW		 1962static s32 igb_init_i2c(struct igb_adapter *adapter)
1963{
1964 s32 status = E1000_SUCCESS;
1965
1966 /* I2C interface supported on i350 devices */
1967 if (adapter->hw.mac.type != e1000_i350)
1968 return E1000_SUCCESS;
1969
1970 /* Initialize the i2c bus which is controlled by the registers.
1971 * This bus will use the i2c_algo_bit structue that implements
1972 * the protocol through toggling of the 4 bits in the register.
1973 */
1974 adapter->i2c_adap.owner = THIS_MODULE;
1975 adapter->i2c_algo = igb_i2c_algo;
1976 adapter->i2c_algo.data = adapter;
1977 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1978 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1979 strlcpy(adapter->i2c_adap.name, "igb BB",
1980 sizeof(adapter->i2c_adap.name));
1981 status = i2c_bit_add_bus(&adapter->i2c_adap);
1982 return status;
1983}
1984
9d5c8243 1985/**
b980ac18
JK		 1986 * igb_probe - Device Initialization Routine
1987 * @pdev: PCI device information struct
1988 * @ent: entry in igb_pci_tbl
9d5c8243 1989 *
b980ac18 1990 * Returns 0 on success, negative on failure
9d5c8243 1991 *
b980ac18
JK		 1992 * igb_probe initializes an adapter identified by a pci_dev structure.
1993 * The OS initialization, configuring of the adapter private structure,
1994 * and a hardware reset occur.
9d5c8243 1995 **/
1dd06ae8 1996static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1997{
1998 struct net_device *netdev;
1999 struct igb_adapter *adapter;
2000 struct e1000_hw *hw;
4337e993 2001 u16 eeprom_data = 0;
9835fd73 2002 s32 ret_val;
4337e993 2003 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 2004 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2005 unsigned long mmio_start, mmio_len;
2d6a5e95 2006 int err, pci_using_dac;
9835fd73 2007 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2008
bded64a7
AG		 2009 /* Catch broken hardware that put the wrong VF device ID in
2010 * the PCIe SR-IOV capability.
2011 */
2012 if (pdev->is_virtfn) {
2013 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2014 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2015 return -EINVAL;
2016 }
2017
aed5dec3 2018 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2019 if (err)
2020 return err;
2021
2022 pci_using_dac = 0;
59d71989 2023 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2024 if (!err) {
59d71989 2025 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 2026 if (!err)
2027 pci_using_dac = 1;
2028 } else {
59d71989 2029 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2030 if (err) {
b980ac18
JK		 2031 err = dma_set_coherent_mask(&pdev->dev,
2032 DMA_BIT_MASK(32));
9d5c8243 2033 if (err) {
b980ac18
JK		 2034 dev_err(&pdev->dev,
2035 "No usable DMA configuration, aborting\n");
9d5c8243
AK		 2036 goto err_dma;
2037 }
2038 }
2039 }
2040
aed5dec3 2041 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2042 IORESOURCE_MEM),
2043 igb_driver_name);
9d5c8243
AK		 2044 if (err)
2045 goto err_pci_reg;
2046
19d5afd4 2047 pci_enable_pcie_error_reporting(pdev);
40a914fa 2048
9d5c8243 2049 pci_set_master(pdev);
c682fc23 2050 pci_save_state(pdev);
9d5c8243
AK		 2051
2052 err = -ENOMEM;
1bfaf07b 2053 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2054 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2055 if (!netdev)
2056 goto err_alloc_etherdev;
2057
2058 SET_NETDEV_DEV(netdev, &pdev->dev);
2059
2060 pci_set_drvdata(pdev, netdev);
2061 adapter = netdev_priv(netdev);
2062 adapter->netdev = netdev;
2063 adapter->pdev = pdev;
2064 hw = &adapter->hw;
2065 hw->back = adapter;
b3f4d599 2066 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2067
2068 mmio_start = pci_resource_start(pdev, 0);
2069 mmio_len = pci_resource_len(pdev, 0);
2070
2071 err = -EIO;
28b0759c
AD		 2072 hw->hw_addr = ioremap(mmio_start, mmio_len);
2073 if (!hw->hw_addr)
9d5c8243
AK		 2074 goto err_ioremap;
2075
2e5c6922 2076 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2077 igb_set_ethtool_ops(netdev);
9d5c8243 2078 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2079
2080 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2081
2082 netdev->mem_start = mmio_start;
2083 netdev->mem_end = mmio_start + mmio_len;
2084
9d5c8243
AK		 2085 /* PCI config space info */
2086 hw->vendor_id = pdev->vendor;
2087 hw->device_id = pdev->device;
2088 hw->revision_id = pdev->revision;
2089 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2090 hw->subsystem_device_id = pdev->subsystem_device;
2091
9d5c8243
AK		 2092 /* Copy the default MAC, PHY and NVM function pointers */
2093 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2094 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2095 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2096 /* Initialize skew-specific constants */
2097 err = ei->get_invariants(hw);
2098 if (err)
450c87c8 2099 goto err_sw_init;
9d5c8243 2100
450c87c8 2101 /* setup the private structure */
9d5c8243
AK		 2102 err = igb_sw_init(adapter);
2103 if (err)
2104 goto err_sw_init;
2105
2106 igb_get_bus_info_pcie(hw);
2107
2108 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2109
2110 /* Copper options */
2111 if (hw->phy.media_type == e1000_media_type_copper) {
2112 hw->phy.mdix = AUTO_ALL_MODES;
2113 hw->phy.disable_polarity_correction = false;
2114 hw->phy.ms_type = e1000_ms_hw_default;
2115 }
2116
2117 if (igb_check_reset_block(hw))
2118 dev_info(&pdev->dev,
2119 "PHY reset is blocked due to SOL/IDER session.\n");
2120
b980ac18 2121 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2122 * set by igb_sw_init so we should use an or instead of an
2123 * assignment.
2124 */
2125 netdev->features |= NETIF_F_SG |
2126 NETIF_F_IP_CSUM |
2127 NETIF_F_IPV6_CSUM |
2128 NETIF_F_TSO |
2129 NETIF_F_TSO6 |
2130 NETIF_F_RXHASH |
2131 NETIF_F_RXCSUM |
f646968f
PM		 2132 NETIF_F_HW_VLAN_CTAG_RX |
2133 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2134
2135 /* copy netdev features into list of user selectable features */
2136 netdev->hw_features |= netdev->features;
89eaefb6 2137 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2138
2139 /* set this bit last since it cannot be part of hw_features */
f646968f 2140 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2141
2142 netdev->vlan_features |= NETIF_F_TSO |
2143 NETIF_F_TSO6 |
2144 NETIF_F_IP_CSUM |
2145 NETIF_F_IPV6_CSUM |
2146 NETIF_F_SG;
48f29ffc 2147
6b8f0922
BG		 2148 netdev->priv_flags |= IFF_SUPP_NOFCS;
2149
7b872a55 2150 if (pci_using_dac) {
9d5c8243 2151 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2152 netdev->vlan_features |= NETIF_F_HIGHDMA;
2153 }
9d5c8243 2154
ac52caa3
MM		 2155 if (hw->mac.type >= e1000_82576) {
2156 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2157 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2158 }
b9473560 2159
01789349
JP		 2160 netdev->priv_flags |= IFF_UNICAST_FLT;
2161
330a6d6a 2162 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2163
2164 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2165 * known good starting state
2166 */
9d5c8243
AK		 2167 hw->mac.ops.reset_hw(hw);
2168
b980ac18 2169 /* make sure the NVM is good , i211 parts have special NVM that
f96a8a0b
CW		 2170 * doesn't contain a checksum
2171 */
2172 if (hw->mac.type != e1000_i211) {
2173 if (hw->nvm.ops.validate(hw) < 0) {
2174 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2175 err = -EIO;
2176 goto err_eeprom;
2177 }
9d5c8243
AK		 2178 }
2179
2180 /* copy the MAC address out of the NVM */
2181 if (hw->mac.ops.read_mac_addr(hw))
2182 dev_err(&pdev->dev, "NVM Read Error\n");
2183
2184 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2185
aaeb6cdf 2186 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2187 dev_err(&pdev->dev, "Invalid MAC Address\n");
2188 err = -EIO;
2189 goto err_eeprom;
2190 }
2191
d67974f0
CW		 2192 /* get firmware version for ethtool -i */
2193 igb_set_fw_version(adapter);
2194
c061b18d 2195 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2196 (unsigned long) adapter);
c061b18d 2197 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2198 (unsigned long) adapter);
9d5c8243
AK		 2199
2200 INIT_WORK(&adapter->reset_task, igb_reset_task);
2201 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2202
450c87c8 2203 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2204 adapter->fc_autoneg = true;
2205 hw->mac.autoneg = true;
2206 hw->phy.autoneg_advertised = 0x2f;
2207
0cce119a
AD		 2208 hw->fc.requested_mode = e1000_fc_default;
2209 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2210
9d5c8243
AK		 2211 igb_validate_mdi_setting(hw);
2212
63d4a8f9 2213 /* By default, support wake on port A */
a2cf8b6c 2214 if (hw->bus.func == 0)
63d4a8f9
MV		 2215 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2216
2217 /* Check the NVM for wake support on non-port A ports */
2218 if (hw->mac.type >= e1000_82580)
55cac248 2219 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2220 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2221 &eeprom_data);
a2cf8b6c
AD		 2222 else if (hw->bus.func == 1)
2223 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2224
63d4a8f9
MV		 2225 if (eeprom_data & IGB_EEPROM_APME)
2226 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2227
2228 /* now that we have the eeprom settings, apply the special cases where
2229 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2230 * lan on a particular port
2231 */
9d5c8243
AK		 2232 switch (pdev->device) {
2233 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2234 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2235 break;
2236 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2237 case E1000_DEV_ID_82576_FIBER:
2238 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2239 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2240 * regardless of eeprom setting
2241 */
9d5c8243 2242 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2243 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2244 break;
c8ea5ea9 2245 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2246 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2247 /* if quad port adapter, disable WoL on all but port A */
2248 if (global_quad_port_a != 0)
63d4a8f9 2249 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2250 else
2251 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2252 /* Reset for multiple quad port adapters */
2253 if (++global_quad_port_a == 4)
2254 global_quad_port_a = 0;
2255 break;
63d4a8f9
MV		 2256 default:
2257 /* If the device can't wake, don't set software support */
2258 if (!device_can_wakeup(&adapter->pdev->dev))
2259 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2260 }
2261
2262 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2263 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2264 adapter->wol |= E1000_WUFC_MAG;
2265
2266 /* Some vendors want WoL disabled by default, but still supported */
2267 if ((hw->mac.type == e1000_i350) &&
2268 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2269 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2270 adapter->wol = 0;
2271 }
2272
2273 device_set_wakeup_enable(&adapter->pdev->dev,
2274 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2275
2276 /* reset the hardware with the new settings */
2277 igb_reset(adapter);
2278
441fc6fd
CW		 2279 /* Init the I2C interface */
2280 err = igb_init_i2c(adapter);
2281 if (err) {
2282 dev_err(&pdev->dev, "failed to init i2c interface\n");
2283 goto err_eeprom;
2284 }
2285
9d5c8243
AK		 2286 /* let the f/w know that the h/w is now under the control of the
2287 * driver. */
2288 igb_get_hw_control(adapter);
2289
9d5c8243
AK		 2290 strcpy(netdev->name, "eth%d");
2291 err = register_netdev(netdev);
2292 if (err)
2293 goto err_register;
2294
b168dfc5
JB		 2295 /* carrier off reporting is important to ethtool even BEFORE open */
2296 netif_carrier_off(netdev);
2297
421e02f0 2298#ifdef CONFIG_IGB_DCA
bbd98fe4 2299 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2300 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2301 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2302 igb_setup_dca(adapter);
2303 }
fe4506b6 2304
38c845c7 2305#endif
e428893b
CW		 2306#ifdef CONFIG_IGB_HWMON
2307 /* Initialize the thermal sensor on i350 devices. */
2308 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2309 u16 ets_word;
3c89f6d0 2310
b980ac18 2311 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2312 * external thermal sensor.
2313 */
2314 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2315 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2316 adapter->ets = true;
2317 else
2318 adapter->ets = false;
2319 if (igb_sysfs_init(adapter))
2320 dev_err(&pdev->dev,
2321 "failed to allocate sysfs resources\n");
2322 } else {
2323 adapter->ets = false;
2324 }
2325#endif
673b8b70 2326 /* do hw tstamp init after resetting */
7ebae817 2327 igb_ptp_init(adapter);
673b8b70 2328
9d5c8243 2329 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2330 /* print bus type/speed/width info, not applicable to i354 */
2331 if (hw->mac.type != e1000_i354) {
2332 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2333 netdev->name,
2334 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2335 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2336 "unknown"),
2337 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2338 "Width x4" :
2339 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2340 "Width x2" :
2341 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2342 "Width x1" : "unknown"), netdev->dev_addr);
2343 }
9d5c8243 2344
9835fd73
CW		 2345 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2346 if (ret_val)
2347 strcpy(part_str, "Unknown");
2348 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2349 dev_info(&pdev->dev,
2350 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2351 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2352 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2353 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2354 switch (hw->mac.type) {
2355 case e1000_i350:
f96a8a0b
CW		 2356 case e1000_i210:
2357 case e1000_i211:
09b068d4
CW		 2358 igb_set_eee_i350(hw);
2359 break;
ceb5f13b
CW		 2360 case e1000_i354:
2361 if (hw->phy.media_type == e1000_media_type_copper) {
2362 if ((rd32(E1000_CTRL_EXT) &
2363 E1000_CTRL_EXT_LINK_MODE_SGMII))
2364 igb_set_eee_i354(hw);
2365 }
2366 break;
09b068d4
CW		 2367 default:
2368 break;
2369 }
749ab2cd
YZ		 2370
2371 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2372 return 0;
2373
2374err_register:
2375 igb_release_hw_control(adapter);
441fc6fd 2376 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2377err_eeprom:
2378 if (!igb_check_reset_block(hw))
f5f4cf08 2379 igb_reset_phy(hw);
9d5c8243
AK		 2380
2381 if (hw->flash_address)
2382 iounmap(hw->flash_address);
9d5c8243 2383err_sw_init:
047e0030 2384 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2385 iounmap(hw->hw_addr);
2386err_ioremap:
2387 free_netdev(netdev);
2388err_alloc_etherdev:
559e9c49 2389 pci_release_selected_regions(pdev,
b980ac18 2390 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2391err_pci_reg:
2392err_dma:
2393 pci_disable_device(pdev);
2394 return err;
2395}
2396
fa44f2f1
GR		 2397#ifdef CONFIG_PCI_IOV
2398static int igb_disable_sriov(struct pci_dev *pdev)
2399{
2400 struct net_device *netdev = pci_get_drvdata(pdev);
2401 struct igb_adapter *adapter = netdev_priv(netdev);
2402 struct e1000_hw *hw = &adapter->hw;
2403
2404 /* reclaim resources allocated to VFs */
2405 if (adapter->vf_data) {
2406 /* disable iov and allow time for transactions to clear */
b09186d2 2407 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2408 dev_warn(&pdev->dev,
2409 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2410 return -EPERM;
2411 } else {
2412 pci_disable_sriov(pdev);
2413 msleep(500);
2414 }
2415
2416 kfree(adapter->vf_data);
2417 adapter->vf_data = NULL;
2418 adapter->vfs_allocated_count = 0;
2419 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2420 wrfl();
2421 msleep(100);
2422 dev_info(&pdev->dev, "IOV Disabled\n");
2423
2424 /* Re-enable DMA Coalescing flag since IOV is turned off */
2425 adapter->flags |= IGB_FLAG_DMAC;
2426 }
2427
2428 return 0;
2429}
2430
2431static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2432{
2433 struct net_device *netdev = pci_get_drvdata(pdev);
2434 struct igb_adapter *adapter = netdev_priv(netdev);
2435 int old_vfs = pci_num_vf(pdev);
2436 int err = 0;
2437 int i;
2438
2439 if (!num_vfs)
2440 goto out;
2441 else if (old_vfs && old_vfs == num_vfs)
2442 goto out;
2443 else if (old_vfs && old_vfs != num_vfs)
2444 err = igb_disable_sriov(pdev);
2445
2446 if (err)
2447 goto out;
2448
2449 if (num_vfs > 7) {
2450 err = -EPERM;
2451 goto out;
2452 }
2453
2454 adapter->vfs_allocated_count = num_vfs;
2455
2456 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2457 sizeof(struct vf_data_storage), GFP_KERNEL);
2458
2459 /* if allocation failed then we do not support SR-IOV */
2460 if (!adapter->vf_data) {
2461 adapter->vfs_allocated_count = 0;
2462 dev_err(&pdev->dev,
2463 "Unable to allocate memory for VF Data Storage\n");
2464 err = -ENOMEM;
2465 goto out;
2466 }
2467
2468 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2469 if (err)
2470 goto err_out;
2471
2472 dev_info(&pdev->dev, "%d VFs allocated\n",
2473 adapter->vfs_allocated_count);
2474 for (i = 0; i < adapter->vfs_allocated_count; i++)
2475 igb_vf_configure(adapter, i);
2476
2477 /* DMA Coalescing is not supported in IOV mode. */
2478 adapter->flags &= ~IGB_FLAG_DMAC;
2479 goto out;
2480
2481err_out:
2482 kfree(adapter->vf_data);
2483 adapter->vf_data = NULL;
2484 adapter->vfs_allocated_count = 0;
2485out:
2486 return err;
2487}
2488
2489#endif
b980ac18 2490/**
441fc6fd
CW		 2491 * igb_remove_i2c - Cleanup I2C interface
2492 * @adapter: pointer to adapter structure
b980ac18 2493 **/
441fc6fd
CW		 2494static void igb_remove_i2c(struct igb_adapter *adapter)
2495{
441fc6fd
CW		 2496 /* free the adapter bus structure */
2497 i2c_del_adapter(&adapter->i2c_adap);
2498}
2499
9d5c8243 2500/**
b980ac18
JK		 2501 * igb_remove - Device Removal Routine
2502 * @pdev: PCI device information struct
9d5c8243 2503 *
b980ac18
JK		 2504 * igb_remove is called by the PCI subsystem to alert the driver
2505 * that it should release a PCI device. The could be caused by a
2506 * Hot-Plug event, or because the driver is going to be removed from
2507 * memory.
9d5c8243 2508 **/
9f9a12f8 2509static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2510{
2511 struct net_device *netdev = pci_get_drvdata(pdev);
2512 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2513 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2514
749ab2cd 2515 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2516#ifdef CONFIG_IGB_HWMON
2517 igb_sysfs_exit(adapter);
2518#endif
441fc6fd 2519 igb_remove_i2c(adapter);
a79f4f88 2520 igb_ptp_stop(adapter);
b980ac18 2521 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2522 * disable watchdog from being rescheduled.
2523 */
9d5c8243
AK		 2524 set_bit(__IGB_DOWN, &adapter->state);
2525 del_timer_sync(&adapter->watchdog_timer);
2526 del_timer_sync(&adapter->phy_info_timer);
2527
760141a5
TH		 2528 cancel_work_sync(&adapter->reset_task);
2529 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2530
421e02f0 2531#ifdef CONFIG_IGB_DCA
7dfc16fa 2532 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2533 dev_info(&pdev->dev, "DCA disabled\n");
2534 dca_remove_requester(&pdev->dev);
7dfc16fa 2535 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2536 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2537 }
2538#endif
2539
9d5c8243 2540 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2541 * would have already happened in close and is redundant.
2542 */
9d5c8243
AK		 2543 igb_release_hw_control(adapter);
2544
2545 unregister_netdev(netdev);
2546
047e0030 2547 igb_clear_interrupt_scheme(adapter);
9d5c8243 2548
37680117 2549#ifdef CONFIG_PCI_IOV
fa44f2f1 2550 igb_disable_sriov(pdev);
37680117 2551#endif
559e9c49 2552
28b0759c
AD		 2553 iounmap(hw->hw_addr);
2554 if (hw->flash_address)
2555 iounmap(hw->flash_address);
559e9c49 2556 pci_release_selected_regions(pdev,
b980ac18 2557 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2558
1128c756 2559 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2560 free_netdev(netdev);
2561
19d5afd4 2562 pci_disable_pcie_error_reporting(pdev);
40a914fa 2563
9d5c8243
AK		 2564 pci_disable_device(pdev);
2565}
2566
a6b623e0 2567/**
b980ac18
JK		 2568 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2569 * @adapter: board private structure to initialize
a6b623e0 2570 *
b980ac18
JK		 2571 * This function initializes the vf specific data storage and then attempts to
2572 * allocate the VFs. The reason for ordering it this way is because it is much
2573 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2574 * the memory for the VFs.
a6b623e0 2575 **/
9f9a12f8 2576static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2577{
2578#ifdef CONFIG_PCI_IOV
2579 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2580 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2581
f96a8a0b
CW		 2582 /* Virtualization features not supported on i210 family. */
2583 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2584 return;
2585
fa44f2f1 2586 pci_sriov_set_totalvfs(pdev, 7);
d5e51a10 2587 igb_enable_sriov(pdev, max_vfs);
0224d663 2588
a6b623e0
AD		 2589#endif /* CONFIG_PCI_IOV */
2590}
2591
fa44f2f1 2592static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2593{
2594 struct e1000_hw *hw = &adapter->hw;
374a542d 2595 u32 max_rss_queues;
9d5c8243 2596
374a542d 2597 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2598 switch (hw->mac.type) {
374a542d
MV		 2599 case e1000_i211:
2600 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2601 break;
2602 case e1000_82575:
f96a8a0b 2603 case e1000_i210:
374a542d
MV		 2604 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2605 break;
2606 case e1000_i350:
2607 /* I350 cannot do RSS and SR-IOV at the same time */
2608 if (!!adapter->vfs_allocated_count) {
2609 max_rss_queues = 1;
2610 break;
2611 }
2612 /* fall through */
2613 case e1000_82576:
2614 if (!!adapter->vfs_allocated_count) {
2615 max_rss_queues = 2;
2616 break;
2617 }
2618 /* fall through */
2619 case e1000_82580:
ceb5f13b 2620 case e1000_i354:
374a542d
MV		 2621 default:
2622 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2623 break;
374a542d
MV		 2624 }
2625
2626 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2627
2628 /* Determine if we need to pair queues. */
2629 switch (hw->mac.type) {
2630 case e1000_82575:
f96a8a0b 2631 case e1000_i211:
374a542d 2632 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2633 break;
374a542d 2634 case e1000_82576:
b980ac18 2635 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2636 * should pair the queues in order to conserve interrupts due
2637 * to limited supply.
2638 */
2639 if ((adapter->rss_queues > 1) &&
2640 (adapter->vfs_allocated_count > 6))
2641 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2642 /* fall through */
2643 case e1000_82580:
2644 case e1000_i350:
ceb5f13b 2645 case e1000_i354:
374a542d 2646 case e1000_i210:
f96a8a0b 2647 default:
b980ac18 2648 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2649 * order to conserve interrupts due to limited supply.
2650 */
2651 if (adapter->rss_queues > (max_rss_queues / 2))
2652 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2653 break;
2654 }
fa44f2f1
GR		 2655}
2656
2657/**
b980ac18
JK		 2658 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2659 * @adapter: board private structure to initialize
fa44f2f1 2660 *
b980ac18
JK		 2661 * igb_sw_init initializes the Adapter private data structure.
2662 * Fields are initialized based on PCI device information and
2663 * OS network device settings (MTU size).
fa44f2f1
GR		 2664 **/
2665static int igb_sw_init(struct igb_adapter *adapter)
2666{
2667 struct e1000_hw *hw = &adapter->hw;
2668 struct net_device *netdev = adapter->netdev;
2669 struct pci_dev *pdev = adapter->pdev;
2670
2671 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2672
2673 /* set default ring sizes */
2674 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2675 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2676
2677 /* set default ITR values */
2678 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2679 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2680
2681 /* set default work limits */
2682 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2683
2684 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2685 VLAN_HLEN;
2686 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2687
2688 spin_lock_init(&adapter->stats64_lock);
2689#ifdef CONFIG_PCI_IOV
2690 switch (hw->mac.type) {
2691 case e1000_82576:
2692 case e1000_i350:
2693 if (max_vfs > 7) {
2694 dev_warn(&pdev->dev,
2695 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2696 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2697 } else
2698 adapter->vfs_allocated_count = max_vfs;
2699 if (adapter->vfs_allocated_count)
2700 dev_warn(&pdev->dev,
2701 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2702 break;
2703 default:
2704 break;
2705 }
2706#endif /* CONFIG_PCI_IOV */
2707
2708 igb_init_queue_configuration(adapter);
a99955fc 2709
1128c756 2710 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2711 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2712 GFP_ATOMIC);
1128c756 2713
a6b623e0 2714 /* This call may decrease the number of queues */
53c7d064 2715 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2716 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2717 return -ENOMEM;
2718 }
2719
a6b623e0
AD		 2720 igb_probe_vfs(adapter);
2721
9d5c8243
AK		 2722 /* Explicitly disable IRQ since the NIC can be in any state. */
2723 igb_irq_disable(adapter);
2724
f96a8a0b 2725 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2726 adapter->flags &= ~IGB_FLAG_DMAC;
2727
9d5c8243
AK		 2728 set_bit(__IGB_DOWN, &adapter->state);
2729 return 0;
2730}
2731
2732/**
b980ac18
JK		 2733 * igb_open - Called when a network interface is made active
2734 * @netdev: network interface device structure
9d5c8243 2735 *
b980ac18 2736 * Returns 0 on success, negative value on failure
9d5c8243 2737 *
b980ac18
JK		 2738 * The open entry point is called when a network interface is made
2739 * active by the system (IFF_UP). At this point all resources needed
2740 * for transmit and receive operations are allocated, the interrupt
2741 * handler is registered with the OS, the watchdog timer is started,
2742 * and the stack is notified that the interface is ready.
9d5c8243 2743 **/
749ab2cd 2744static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2745{
2746 struct igb_adapter *adapter = netdev_priv(netdev);
2747 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2748 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2749 int err;
2750 int i;
2751
2752 /* disallow open during test */
749ab2cd
YZ		 2753 if (test_bit(__IGB_TESTING, &adapter->state)) {
2754 WARN_ON(resuming);
9d5c8243 2755 return -EBUSY;
749ab2cd
YZ		 2756 }
2757
2758 if (!resuming)
2759 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2760
b168dfc5
JB		 2761 netif_carrier_off(netdev);
2762
9d5c8243
AK		 2763 /* allocate transmit descriptors */
2764 err = igb_setup_all_tx_resources(adapter);
2765 if (err)
2766 goto err_setup_tx;
2767
2768 /* allocate receive descriptors */
2769 err = igb_setup_all_rx_resources(adapter);
2770 if (err)
2771 goto err_setup_rx;
2772
88a268c1 2773 igb_power_up_link(adapter);
9d5c8243 2774
9d5c8243
AK		 2775 /* before we allocate an interrupt, we must be ready to handle it.
2776 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2777 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2778 * clean_rx handler before we do so.
2779 */
9d5c8243
AK		 2780 igb_configure(adapter);
2781
2782 err = igb_request_irq(adapter);
2783 if (err)
2784 goto err_req_irq;
2785
0c2cc02e
AD		 2786 /* Notify the stack of the actual queue counts. */
2787 err = netif_set_real_num_tx_queues(adapter->netdev,
2788 adapter->num_tx_queues);
2789 if (err)
2790 goto err_set_queues;
2791
2792 err = netif_set_real_num_rx_queues(adapter->netdev,
2793 adapter->num_rx_queues);
2794 if (err)
2795 goto err_set_queues;
2796
9d5c8243
AK		 2797 /* From here on the code is the same as igb_up() */
2798 clear_bit(__IGB_DOWN, &adapter->state);
2799
0d1ae7f4
AD		 2800 for (i = 0; i < adapter->num_q_vectors; i++)
2801 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2802
2803 /* Clear any pending interrupts. */
2804 rd32(E1000_ICR);
844290e5
PW		 2805
2806 igb_irq_enable(adapter);
2807
d4960307
AD		 2808 /* notify VFs that reset has been completed */
2809 if (adapter->vfs_allocated_count) {
2810 u32 reg_data = rd32(E1000_CTRL_EXT);
2811 reg_data |= E1000_CTRL_EXT_PFRSTD;
2812 wr32(E1000_CTRL_EXT, reg_data);
2813 }
2814
d55b53ff
JK		 2815 netif_tx_start_all_queues(netdev);
2816
749ab2cd
YZ		 2817 if (!resuming)
2818 pm_runtime_put(&pdev->dev);
2819
25568a53
AD		 2820 /* start the watchdog. */
2821 hw->mac.get_link_status = 1;
2822 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2823
2824 return 0;
2825
0c2cc02e
AD		 2826err_set_queues:
2827 igb_free_irq(adapter);
9d5c8243
AK		 2828err_req_irq:
2829 igb_release_hw_control(adapter);
88a268c1 2830 igb_power_down_link(adapter);
9d5c8243
AK		 2831 igb_free_all_rx_resources(adapter);
2832err_setup_rx:
2833 igb_free_all_tx_resources(adapter);
2834err_setup_tx:
2835 igb_reset(adapter);
749ab2cd
YZ		 2836 if (!resuming)
2837 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2838
2839 return err;
2840}
2841
749ab2cd
YZ		 2842static int igb_open(struct net_device *netdev)
2843{
2844 return __igb_open(netdev, false);
2845}
2846
9d5c8243 2847/**
b980ac18
JK		 2848 * igb_close - Disables a network interface
2849 * @netdev: network interface device structure
9d5c8243 2850 *
b980ac18 2851 * Returns 0, this is not allowed to fail
9d5c8243 2852 *
b980ac18
JK		 2853 * The close entry point is called when an interface is de-activated
2854 * by the OS. The hardware is still under the driver's control, but
2855 * needs to be disabled. A global MAC reset is issued to stop the
2856 * hardware, and all transmit and receive resources are freed.
9d5c8243 2857 **/
749ab2cd 2858static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2859{
2860 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2861 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2862
2863 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2864
749ab2cd
YZ		 2865 if (!suspending)
2866 pm_runtime_get_sync(&pdev->dev);
2867
2868 igb_down(adapter);
9d5c8243
AK		 2869 igb_free_irq(adapter);
2870
2871 igb_free_all_tx_resources(adapter);
2872 igb_free_all_rx_resources(adapter);
2873
749ab2cd
YZ		 2874 if (!suspending)
2875 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2876 return 0;
2877}
2878
749ab2cd
YZ		 2879static int igb_close(struct net_device *netdev)
2880{
2881 return __igb_close(netdev, false);
2882}
2883
9d5c8243 2884/**
b980ac18
JK		 2885 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2886 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2887 *
b980ac18 2888 * Return 0 on success, negative on failure
9d5c8243 2889 **/
80785298 2890int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2891{
59d71989 2892 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2893 int size;
2894
06034649 2895 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2896
2897 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2898 if (!tx_ring->tx_buffer_info)
9d5c8243 2899 goto err;
9d5c8243
AK		 2900
2901 /* round up to nearest 4K */
85e8d004 2902 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2903 tx_ring->size = ALIGN(tx_ring->size, 4096);
2904
5536d210
AD		 2905 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2906 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2907 if (!tx_ring->desc)
2908 goto err;
2909
9d5c8243
AK		 2910 tx_ring->next_to_use = 0;
2911 tx_ring->next_to_clean = 0;
81c2fc22 2912
9d5c8243
AK		 2913 return 0;
2914
2915err:
06034649 2916 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2917 tx_ring->tx_buffer_info = NULL;
2918 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2919 return -ENOMEM;
2920}
2921
2922/**
b980ac18
JK		 2923 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2924 * (Descriptors) for all queues
2925 * @adapter: board private structure
9d5c8243 2926 *
b980ac18 2927 * Return 0 on success, negative on failure
9d5c8243
AK		 2928 **/
2929static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2930{
439705e1 2931 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2932 int i, err = 0;
2933
2934 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2935 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2936 if (err) {
439705e1 2937 dev_err(&pdev->dev,
9d5c8243
AK		 2938 "Allocation for Tx Queue %u failed\n", i);
2939 for (i--; i >= 0; i--)
3025a446 2940 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2941 break;
2942 }
2943 }
2944
2945 return err;
2946}
2947
2948/**
b980ac18
JK		 2949 * igb_setup_tctl - configure the transmit control registers
2950 * @adapter: Board private structure
9d5c8243 2951 **/
d7ee5b3a 2952void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2953{
9d5c8243
AK		 2954 struct e1000_hw *hw = &adapter->hw;
2955 u32 tctl;
9d5c8243 2956
85b430b4
AD		 2957 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2958 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2959
2960 /* Program the Transmit Control Register */
9d5c8243
AK		 2961 tctl = rd32(E1000_TCTL);
2962 tctl &= ~E1000_TCTL_CT;
2963 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2964 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2965
2966 igb_config_collision_dist(hw);
2967
9d5c8243
AK		 2968 /* Enable transmits */
2969 tctl |= E1000_TCTL_EN;
2970
2971 wr32(E1000_TCTL, tctl);
2972}
2973
85b430b4 2974/**
b980ac18
JK		 2975 * igb_configure_tx_ring - Configure transmit ring after Reset
2976 * @adapter: board private structure
2977 * @ring: tx ring to configure
85b430b4 2978 *
b980ac18 2979 * Configure a transmit ring after a reset.
85b430b4 2980 **/
d7ee5b3a
AD		 2981void igb_configure_tx_ring(struct igb_adapter *adapter,
2982 struct igb_ring *ring)
85b430b4
AD		 2983{
2984 struct e1000_hw *hw = &adapter->hw;
a74420e0 2985 u32 txdctl = 0;
85b430b4
AD		 2986 u64 tdba = ring->dma;
2987 int reg_idx = ring->reg_idx;
2988
2989 /* disable the queue */
a74420e0 2990 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2991 wrfl();
2992 mdelay(10);
2993
2994 wr32(E1000_TDLEN(reg_idx),
b980ac18 2995 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 2996 wr32(E1000_TDBAL(reg_idx),
b980ac18 2997 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 2998 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2999
fce99e34 3000 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3001 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3002 writel(0, ring->tail);
85b430b4
AD		 3003
3004 txdctl |= IGB_TX_PTHRESH;
3005 txdctl |= IGB_TX_HTHRESH << 8;
3006 txdctl |= IGB_TX_WTHRESH << 16;
3007
3008 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3009 wr32(E1000_TXDCTL(reg_idx), txdctl);
3010}
3011
3012/**
b980ac18
JK		 3013 * igb_configure_tx - Configure transmit Unit after Reset
3014 * @adapter: board private structure
85b430b4 3015 *
b980ac18 3016 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3017 **/
3018static void igb_configure_tx(struct igb_adapter *adapter)
3019{
3020 int i;
3021
3022 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3023 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3024}
3025
9d5c8243 3026/**
b980ac18
JK		 3027 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3028 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3029 *
b980ac18 3030 * Returns 0 on success, negative on failure
9d5c8243 3031 **/
80785298 3032int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3033{
59d71989 3034 struct device *dev = rx_ring->dev;
f33005a6 3035 int size;
9d5c8243 3036
06034649 3037 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3038
3039 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3040 if (!rx_ring->rx_buffer_info)
9d5c8243 3041 goto err;
9d5c8243 3042
9d5c8243 3043 /* Round up to nearest 4K */
f33005a6 3044 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3045 rx_ring->size = ALIGN(rx_ring->size, 4096);
3046
5536d210
AD		 3047 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3048 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3049 if (!rx_ring->desc)
3050 goto err;
3051
cbc8e55f 3052 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3053 rx_ring->next_to_clean = 0;
3054 rx_ring->next_to_use = 0;
9d5c8243 3055
9d5c8243
AK		 3056 return 0;
3057
3058err:
06034649
AD		 3059 vfree(rx_ring->rx_buffer_info);
3060 rx_ring->rx_buffer_info = NULL;
f33005a6 3061 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3062 return -ENOMEM;
3063}
3064
3065/**
b980ac18
JK		 3066 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3067 * (Descriptors) for all queues
3068 * @adapter: board private structure
9d5c8243 3069 *
b980ac18 3070 * Return 0 on success, negative on failure
9d5c8243
AK		 3071 **/
3072static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3073{
439705e1 3074 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3075 int i, err = 0;
3076
3077 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3078 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3079 if (err) {
439705e1 3080 dev_err(&pdev->dev,
9d5c8243
AK		 3081 "Allocation for Rx Queue %u failed\n", i);
3082 for (i--; i >= 0; i--)
3025a446 3083 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3084 break;
3085 }
3086 }
3087
3088 return err;
3089}
3090
06cf2666 3091/**
b980ac18
JK		 3092 * igb_setup_mrqc - configure the multiple receive queue control registers
3093 * @adapter: Board private structure
06cf2666
AD		 3094 **/
3095static void igb_setup_mrqc(struct igb_adapter *adapter)
3096{
3097 struct e1000_hw *hw = &adapter->hw;
3098 u32 mrqc, rxcsum;
797fd4be 3099 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 3100 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3101 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3102 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3103 0xFA01ACBE };
06cf2666
AD		 3104
3105 /* Fill out hash function seeds */
a57fe23e
AD		 3106 for (j = 0; j < 10; j++)
3107 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3108
a99955fc 3109 num_rx_queues = adapter->rss_queues;
06cf2666 3110
797fd4be
AD		 3111 switch (hw->mac.type) {
3112 case e1000_82575:
3113 shift = 6;
3114 break;
3115 case e1000_82576:
3116 /* 82576 supports 2 RSS queues for SR-IOV */
3117 if (adapter->vfs_allocated_count) {
06cf2666
AD		 3118 shift = 3;
3119 num_rx_queues = 2;
06cf2666 3120 }
797fd4be
AD		 3121 break;
3122 default:
3123 break;
06cf2666
AD		 3124 }
3125
b980ac18 3126 /* Populate the indirection table 4 entries at a time. To do this
797fd4be
AD		 3127 * we are generating the results for n and n+2 and then interleaving
3128 * those with the results with n+1 and n+3.
3129 */
3130 for (j = 0; j < 32; j++) {
3131 /* first pass generates n and n+2 */
3132 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3133 u32 reta = (base & 0x07800780) >> (7 - shift);
3134
3135 /* second pass generates n+1 and n+3 */
3136 base += 0x00010001 * num_rx_queues;
3137 reta |= (base & 0x07800780) << (1 + shift);
3138
3139 wr32(E1000_RETA(j), reta);
06cf2666
AD		 3140 }
3141
b980ac18 3142 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3143 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3144 * offloads as they are enabled by default
3145 */
3146 rxcsum = rd32(E1000_RXCSUM);
3147 rxcsum |= E1000_RXCSUM_PCSD;
3148
3149 if (adapter->hw.mac.type >= e1000_82576)
3150 /* Enable Receive Checksum Offload for SCTP */
3151 rxcsum |= E1000_RXCSUM_CRCOFL;
3152
3153 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3154 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3155
039454a8
AA		 3156 /* Generate RSS hash based on packet types, TCP/UDP
3157 * port numbers and/or IPv4/v6 src and dst addresses
3158 */
f96a8a0b
CW		 3159 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3160 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3161 E1000_MRQC_RSS_FIELD_IPV6 |
3162 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3163 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3164
039454a8
AA		 3165 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3166 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3167 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3168 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3169
06cf2666
AD		 3170 /* If VMDq is enabled then we set the appropriate mode for that, else
3171 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3172 * if we are only using one queue
3173 */
06cf2666
AD		 3174 if (adapter->vfs_allocated_count) {
3175 if (hw->mac.type > e1000_82575) {
3176 /* Set the default pool for the PF's first queue */
3177 u32 vtctl = rd32(E1000_VT_CTL);
3178 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3179 E1000_VT_CTL_DISABLE_DEF_POOL);
3180 vtctl |= adapter->vfs_allocated_count <<
3181 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3182 wr32(E1000_VT_CTL, vtctl);
3183 }
a99955fc 3184 if (adapter->rss_queues > 1)
f96a8a0b 3185 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3186 else
f96a8a0b 3187 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3188 } else {
f96a8a0b
CW		 3189 if (hw->mac.type != e1000_i211)
3190 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3191 }
3192 igb_vmm_control(adapter);
3193
06cf2666
AD		 3194 wr32(E1000_MRQC, mrqc);
3195}
3196
9d5c8243 3197/**
b980ac18
JK		 3198 * igb_setup_rctl - configure the receive control registers
3199 * @adapter: Board private structure
9d5c8243 3200 **/
d7ee5b3a 3201void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3202{
3203 struct e1000_hw *hw = &adapter->hw;
3204 u32 rctl;
9d5c8243
AK		 3205
3206 rctl = rd32(E1000_RCTL);
3207
3208 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3209 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3210
69d728ba 3211 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3212 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3213
b980ac18 3214 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3215 * redirection as it did with e1000. Newer features require
3216 * that the HW strips the CRC.
73cd78f1 3217 */
87cb7e8c 3218 rctl |= E1000_RCTL_SECRC;
9d5c8243 3219
559e9c49 3220 /* disable store bad packets and clear size bits. */
ec54d7d6 3221 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3222
6ec43fe6
AD		 3223 /* enable LPE to prevent packets larger than max_frame_size */
3224 rctl |= E1000_RCTL_LPE;
9d5c8243 3225
952f72a8
AD		 3226 /* disable queue 0 to prevent tail write w/o re-config */
3227 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3228
e1739522
AD		 3229 /* Attention!!! For SR-IOV PF driver operations you must enable
3230 * queue drop for all VF and PF queues to prevent head of line blocking
3231 * if an un-trusted VF does not provide descriptors to hardware.
3232 */
3233 if (adapter->vfs_allocated_count) {
e1739522
AD		 3234 /* set all queue drop enable bits */
3235 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3236 }
3237
89eaefb6
BG		 3238 /* This is useful for sniffing bad packets. */
3239 if (adapter->netdev->features & NETIF_F_RXALL) {
3240 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3241 * in e1000e_set_rx_mode
3242 */
89eaefb6
BG		 3243 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3244 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3245 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3246
3247 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3248 E1000_RCTL_DPF | /* Allow filtered pause */
3249 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3250 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3251 * and that breaks VLANs.
3252 */
3253 }
3254
9d5c8243
AK		 3255 wr32(E1000_RCTL, rctl);
3256}
3257
7d5753f0
AD		 3258static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3259 int vfn)
3260{
3261 struct e1000_hw *hw = &adapter->hw;
3262 u32 vmolr;
3263
3264 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3265 * increase the size to support vlan tags
3266 */
7d5753f0
AD		 3267 if (vfn < adapter->vfs_allocated_count &&
3268 adapter->vf_data[vfn].vlans_enabled)
3269 size += VLAN_TAG_SIZE;
3270
3271 vmolr = rd32(E1000_VMOLR(vfn));
3272 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3273 vmolr |= size | E1000_VMOLR_LPE;
3274 wr32(E1000_VMOLR(vfn), vmolr);
3275
3276 return 0;
3277}
3278
e1739522 3279/**
b980ac18
JK		 3280 * igb_rlpml_set - set maximum receive packet size
3281 * @adapter: board private structure
e1739522 3282 *
b980ac18 3283 * Configure maximum receivable packet size.
e1739522
AD		 3284 **/
3285static void igb_rlpml_set(struct igb_adapter *adapter)
3286{
153285f9 3287 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3288 struct e1000_hw *hw = &adapter->hw;
3289 u16 pf_id = adapter->vfs_allocated_count;
3290
e1739522
AD		 3291 if (pf_id) {
3292 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3293 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3294 * to our max jumbo frame size, in case we need to enable
3295 * jumbo frames on one of the rings later.
3296 * This will not pass over-length frames into the default
3297 * queue because it's gated by the VMOLR.RLPML.
3298 */
7d5753f0 3299 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3300 }
3301
3302 wr32(E1000_RLPML, max_frame_size);
3303}
3304
8151d294
WM		 3305static inline void igb_set_vmolr(struct igb_adapter *adapter,
3306 int vfn, bool aupe)
7d5753f0
AD		 3307{
3308 struct e1000_hw *hw = &adapter->hw;
3309 u32 vmolr;
3310
b980ac18 3311 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3312 * we should exit and do nothing
3313 */
3314 if (hw->mac.type < e1000_82576)
3315 return;
3316
3317 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3318 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3319 if (aupe)
b980ac18 3320 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3321 else
3322 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3323
3324 /* clear all bits that might not be set */
3325 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3326
a99955fc 3327 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3328 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3329 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3330 * multicast packets
3331 */
3332 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3333 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3334
3335 wr32(E1000_VMOLR(vfn), vmolr);
3336}
3337
85b430b4 3338/**
b980ac18
JK		 3339 * igb_configure_rx_ring - Configure a receive ring after Reset
3340 * @adapter: board private structure
3341 * @ring: receive ring to be configured
85b430b4 3342 *
b980ac18 3343 * Configure the Rx unit of the MAC after a reset.
85b430b4 3344 **/
d7ee5b3a 3345void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3346 struct igb_ring *ring)
85b430b4
AD		 3347{
3348 struct e1000_hw *hw = &adapter->hw;
3349 u64 rdba = ring->dma;
3350 int reg_idx = ring->reg_idx;
a74420e0 3351 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3352
3353 /* disable the queue */
a74420e0 3354 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3355
3356 /* Set DMA base address registers */
3357 wr32(E1000_RDBAL(reg_idx),
3358 rdba & 0x00000000ffffffffULL);
3359 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3360 wr32(E1000_RDLEN(reg_idx),
b980ac18 3361 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3362
3363 /* initialize head and tail */
fce99e34 3364 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3365 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3366 writel(0, ring->tail);
85b430b4 3367
952f72a8 3368 /* set descriptor configuration */
44390ca6 3369 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3370 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3371 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3372 if (hw->mac.type >= e1000_82580)
757b77e2 3373 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3374 /* Only set Drop Enable if we are supporting multiple queues */
3375 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3376 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3377
3378 wr32(E1000_SRRCTL(reg_idx), srrctl);
3379
7d5753f0 3380 /* set filtering for VMDQ pools */
8151d294 3381 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3382
85b430b4
AD		 3383 rxdctl |= IGB_RX_PTHRESH;
3384 rxdctl |= IGB_RX_HTHRESH << 8;
3385 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3386
3387 /* enable receive descriptor fetching */
3388 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3389 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3390}
3391
9d5c8243 3392/**
b980ac18
JK		 3393 * igb_configure_rx - Configure receive Unit after Reset
3394 * @adapter: board private structure
9d5c8243 3395 *
b980ac18 3396 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3397 **/
3398static void igb_configure_rx(struct igb_adapter *adapter)
3399{
9107584e 3400 int i;
9d5c8243 3401
68d480c4
AD		 3402 /* set UTA to appropriate mode */
3403 igb_set_uta(adapter);
3404
26ad9178
AD		 3405 /* set the correct pool for the PF default MAC address in entry 0 */
3406 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3407 adapter->vfs_allocated_count);
26ad9178 3408
06cf2666 3409 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3410 * the Base and Length of the Rx Descriptor Ring
3411 */
f9d40f6a
AD		 3412 for (i = 0; i < adapter->num_rx_queues; i++)
3413 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3414}
3415
3416/**
b980ac18
JK		 3417 * igb_free_tx_resources - Free Tx Resources per Queue
3418 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3419 *
b980ac18 3420 * Free all transmit software resources
9d5c8243 3421 **/
68fd9910 3422void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3423{
3b644cf6 3424 igb_clean_tx_ring(tx_ring);
9d5c8243 3425
06034649
AD		 3426 vfree(tx_ring->tx_buffer_info);
3427 tx_ring->tx_buffer_info = NULL;
9d5c8243 3428
439705e1
AD		 3429 /* if not set, then don't free */
3430 if (!tx_ring->desc)
3431 return;
3432
59d71989
AD		 3433 dma_free_coherent(tx_ring->dev, tx_ring->size,
3434 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3435
3436 tx_ring->desc = NULL;
3437}
3438
3439/**
b980ac18
JK		 3440 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3441 * @adapter: board private structure
9d5c8243 3442 *
b980ac18 3443 * Free all transmit software resources
9d5c8243
AK		 3444 **/
3445static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3446{
3447 int i;
3448
3449 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3450 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3451}
3452
ebe42d16
AD		 3453void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3454 struct igb_tx_buffer *tx_buffer)
3455{
3456 if (tx_buffer->skb) {
3457 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3458 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3459 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3460 dma_unmap_addr(tx_buffer, dma),
3461 dma_unmap_len(tx_buffer, len),
ebe42d16 3462 DMA_TO_DEVICE);
c9f14bf3 3463 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3464 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3465 dma_unmap_addr(tx_buffer, dma),
3466 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3467 DMA_TO_DEVICE);
3468 }
3469 tx_buffer->next_to_watch = NULL;
3470 tx_buffer->skb = NULL;
c9f14bf3 3471 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3472 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3473}
3474
3475/**
b980ac18
JK		 3476 * igb_clean_tx_ring - Free Tx Buffers
3477 * @tx_ring: ring to be cleaned
9d5c8243 3478 **/
3b644cf6 3479static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3480{
06034649 3481 struct igb_tx_buffer *buffer_info;
9d5c8243 3482 unsigned long size;
6ad4edfc 3483 u16 i;
9d5c8243 3484
06034649 3485 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3486 return;
3487 /* Free all the Tx ring sk_buffs */
3488
3489 for (i = 0; i < tx_ring->count; i++) {
06034649 3490 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3491 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3492 }
3493
dad8a3b3
JF		 3494 netdev_tx_reset_queue(txring_txq(tx_ring));
3495
06034649
AD		 3496 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3497 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3498
3499 /* Zero out the descriptor ring */
9d5c8243
AK		 3500 memset(tx_ring->desc, 0, tx_ring->size);
3501
3502 tx_ring->next_to_use = 0;
3503 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3504}
3505
3506/**
b980ac18
JK		 3507 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3508 * @adapter: board private structure
9d5c8243
AK		 3509 **/
3510static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3511{
3512 int i;
3513
3514 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3515 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3516}
3517
3518/**
b980ac18
JK		 3519 * igb_free_rx_resources - Free Rx Resources
3520 * @rx_ring: ring to clean the resources from
9d5c8243 3521 *
b980ac18 3522 * Free all receive software resources
9d5c8243 3523 **/
68fd9910 3524void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3525{
3b644cf6 3526 igb_clean_rx_ring(rx_ring);
9d5c8243 3527
06034649
AD		 3528 vfree(rx_ring->rx_buffer_info);
3529 rx_ring->rx_buffer_info = NULL;
9d5c8243 3530
439705e1
AD		 3531 /* if not set, then don't free */
3532 if (!rx_ring->desc)
3533 return;
3534
59d71989
AD		 3535 dma_free_coherent(rx_ring->dev, rx_ring->size,
3536 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3537
3538 rx_ring->desc = NULL;
3539}
3540
3541/**
b980ac18
JK		 3542 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3543 * @adapter: board private structure
9d5c8243 3544 *
b980ac18 3545 * Free all receive software resources
9d5c8243
AK		 3546 **/
3547static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3548{
3549 int i;
3550
3551 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3552 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3553}
3554
3555/**
b980ac18
JK		 3556 * igb_clean_rx_ring - Free Rx Buffers per Queue
3557 * @rx_ring: ring to free buffers from
9d5c8243 3558 **/
3b644cf6 3559static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3560{
9d5c8243 3561 unsigned long size;
c023cd88 3562 u16 i;
9d5c8243 3563
1a1c225b
AD		 3564 if (rx_ring->skb)
3565 dev_kfree_skb(rx_ring->skb);
3566 rx_ring->skb = NULL;
3567
06034649 3568 if (!rx_ring->rx_buffer_info)
9d5c8243 3569 return;
439705e1 3570
9d5c8243
AK		 3571 /* Free all the Rx ring sk_buffs */
3572 for (i = 0; i < rx_ring->count; i++) {
06034649 3573 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3574
cbc8e55f
AD		 3575 if (!buffer_info->page)
3576 continue;
3577
3578 dma_unmap_page(rx_ring->dev,
3579 buffer_info->dma,
3580 PAGE_SIZE,
3581 DMA_FROM_DEVICE);
3582 __free_page(buffer_info->page);
3583
1a1c225b 3584 buffer_info->page = NULL;
9d5c8243
AK		 3585 }
3586
06034649
AD		 3587 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3588 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3589
3590 /* Zero out the descriptor ring */
3591 memset(rx_ring->desc, 0, rx_ring->size);
3592
cbc8e55f 3593 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3594 rx_ring->next_to_clean = 0;
3595 rx_ring->next_to_use = 0;
9d5c8243
AK		 3596}
3597
3598/**
b980ac18
JK		 3599 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3600 * @adapter: board private structure
9d5c8243
AK		 3601 **/
3602static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3603{
3604 int i;
3605
3606 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3607 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3608}
3609
3610/**
b980ac18
JK		 3611 * igb_set_mac - Change the Ethernet Address of the NIC
3612 * @netdev: network interface device structure
3613 * @p: pointer to an address structure
9d5c8243 3614 *
b980ac18 3615 * Returns 0 on success, negative on failure
9d5c8243
AK		 3616 **/
3617static int igb_set_mac(struct net_device *netdev, void *p)
3618{
3619 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3620 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3621 struct sockaddr *addr = p;
3622
3623 if (!is_valid_ether_addr(addr->sa_data))
3624 return -EADDRNOTAVAIL;
3625
3626 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3627 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3628
26ad9178
AD		 3629 /* set the correct pool for the new PF MAC address in entry 0 */
3630 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3631 adapter->vfs_allocated_count);
e1739522 3632
9d5c8243
AK		 3633 return 0;
3634}
3635
3636/**
b980ac18
JK		 3637 * igb_write_mc_addr_list - write multicast addresses to MTA
3638 * @netdev: network interface device structure
9d5c8243 3639 *
b980ac18
JK		 3640 * Writes multicast address list to the MTA hash table.
3641 * Returns: -ENOMEM on failure
3642 * 0 on no addresses written
3643 * X on writing X addresses to MTA
9d5c8243 3644 **/
68d480c4 3645static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3646{
3647 struct igb_adapter *adapter = netdev_priv(netdev);
3648 struct e1000_hw *hw = &adapter->hw;
22bedad3 3649 struct netdev_hw_addr *ha;
68d480c4 3650 u8 *mta_list;
9d5c8243
AK		 3651 int i;
3652
4cd24eaf 3653 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3654 /* nothing to program, so clear mc list */
3655 igb_update_mc_addr_list(hw, NULL, 0);
3656 igb_restore_vf_multicasts(adapter);
3657 return 0;
3658 }
9d5c8243 3659
4cd24eaf 3660 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3661 if (!mta_list)
3662 return -ENOMEM;
ff41f8dc 3663
68d480c4 3664 /* The shared function expects a packed array of only addresses. */
48e2f183 3665 i = 0;
22bedad3
JP		 3666 netdev_for_each_mc_addr(ha, netdev)
3667 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3668
68d480c4
AD		 3669 igb_update_mc_addr_list(hw, mta_list, i);
3670 kfree(mta_list);
3671
4cd24eaf 3672 return netdev_mc_count(netdev);
68d480c4
AD		 3673}
3674
3675/**
b980ac18
JK		 3676 * igb_write_uc_addr_list - write unicast addresses to RAR table
3677 * @netdev: network interface device structure
68d480c4 3678 *
b980ac18
JK		 3679 * Writes unicast address list to the RAR table.
3680 * Returns: -ENOMEM on failure/insufficient address space
3681 * 0 on no addresses written
3682 * X on writing X addresses to the RAR table
68d480c4
AD		 3683 **/
3684static int igb_write_uc_addr_list(struct net_device *netdev)
3685{
3686 struct igb_adapter *adapter = netdev_priv(netdev);
3687 struct e1000_hw *hw = &adapter->hw;
3688 unsigned int vfn = adapter->vfs_allocated_count;
3689 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3690 int count = 0;
3691
3692 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3693 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3694 return -ENOMEM;
9d5c8243 3695
32e7bfc4 3696 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3697 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3698
3699 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3700 if (!rar_entries)
3701 break;
26ad9178 3702 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3703 rar_entries--,
3704 vfn);
68d480c4 3705 count++;
ff41f8dc
AD		 3706 }
3707 }
3708 /* write the addresses in reverse order to avoid write combining */
3709 for (; rar_entries > 0 ; rar_entries--) {
3710 wr32(E1000_RAH(rar_entries), 0);
3711 wr32(E1000_RAL(rar_entries), 0);
3712 }
3713 wrfl();
3714
68d480c4
AD		 3715 return count;
3716}
3717
3718/**
b980ac18
JK		 3719 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3720 * @netdev: network interface device structure
68d480c4 3721 *
b980ac18
JK		 3722 * The set_rx_mode entry point is called whenever the unicast or multicast
3723 * address lists or the network interface flags are updated. This routine is
3724 * responsible for configuring the hardware for proper unicast, multicast,
3725 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3726 **/
3727static void igb_set_rx_mode(struct net_device *netdev)
3728{
3729 struct igb_adapter *adapter = netdev_priv(netdev);
3730 struct e1000_hw *hw = &adapter->hw;
3731 unsigned int vfn = adapter->vfs_allocated_count;
3732 u32 rctl, vmolr = 0;
3733 int count;
3734
3735 /* Check for Promiscuous and All Multicast modes */
3736 rctl = rd32(E1000_RCTL);
3737
3738 /* clear the effected bits */
3739 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3740
3741 if (netdev->flags & IFF_PROMISC) {
6f3dc319
GR		 3742 u32 mrqc = rd32(E1000_MRQC);
3743 /* retain VLAN HW filtering if in VT mode */
3744 if (mrqc & E1000_MRQC_ENABLE_VMDQ)
3745 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3746 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3747 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3748 } else {
3749 if (netdev->flags & IFF_ALLMULTI) {
3750 rctl |= E1000_RCTL_MPE;
3751 vmolr |= E1000_VMOLR_MPME;
3752 } else {
b980ac18 3753 /* Write addresses to the MTA, if the attempt fails
25985edc 3754 * then we should just turn on promiscuous mode so
68d480c4
AD		 3755 * that we can at least receive multicast traffic
3756 */
3757 count = igb_write_mc_addr_list(netdev);
3758 if (count < 0) {
3759 rctl |= E1000_RCTL_MPE;
3760 vmolr |= E1000_VMOLR_MPME;
3761 } else if (count) {
3762 vmolr |= E1000_VMOLR_ROMPE;
3763 }
3764 }
b980ac18 3765 /* Write addresses to available RAR registers, if there is not
68d480c4 3766 * sufficient space to store all the addresses then enable
25985edc 3767 * unicast promiscuous mode
68d480c4
AD		 3768 */
3769 count = igb_write_uc_addr_list(netdev);
3770 if (count < 0) {
3771 rctl |= E1000_RCTL_UPE;
3772 vmolr |= E1000_VMOLR_ROPE;
3773 }
3774 rctl |= E1000_RCTL_VFE;
28fc06f5 3775 }
68d480c4 3776 wr32(E1000_RCTL, rctl);
28fc06f5 3777
b980ac18 3778 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3779 * the VMOLR to enable the appropriate modes. Without this workaround
3780 * we will have issues with VLAN tag stripping not being done for frames
3781 * that are only arriving because we are the default pool
3782 */
f96a8a0b 3783 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3784 return;
9d5c8243 3785
68d480c4 3786 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3787 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3788 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3789 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3790}
3791
13800469
GR		 3792static void igb_check_wvbr(struct igb_adapter *adapter)
3793{
3794 struct e1000_hw *hw = &adapter->hw;
3795 u32 wvbr = 0;
3796
3797 switch (hw->mac.type) {
3798 case e1000_82576:
3799 case e1000_i350:
3800 if (!(wvbr = rd32(E1000_WVBR)))
3801 return;
3802 break;
3803 default:
3804 break;
3805 }
3806
3807 adapter->wvbr |= wvbr;
3808}
3809
3810#define IGB_STAGGERED_QUEUE_OFFSET 8
3811
3812static void igb_spoof_check(struct igb_adapter *adapter)
3813{
3814 int j;
3815
3816 if (!adapter->wvbr)
3817 return;
3818
3819 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3820 if (adapter->wvbr & (1 << j) ||
3821 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3822 dev_warn(&adapter->pdev->dev,
3823 "Spoof event(s) detected on VF %d\n", j);
3824 adapter->wvbr &=
3825 ~((1 << j) |
3826 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3827 }
3828 }
3829}
3830
9d5c8243 3831/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3832 * the phy
3833 */
9d5c8243
AK		 3834static void igb_update_phy_info(unsigned long data)
3835{
3836 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3837 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3838}
3839
4d6b725e 3840/**
b980ac18
JK		 3841 * igb_has_link - check shared code for link and determine up/down
3842 * @adapter: pointer to driver private info
4d6b725e 3843 **/
3145535a 3844bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3845{
3846 struct e1000_hw *hw = &adapter->hw;
3847 bool link_active = false;
3848 s32 ret_val = 0;
3849
3850 /* get_link_status is set on LSC (link status) interrupt or
3851 * rx sequence error interrupt. get_link_status will stay
3852 * false until the e1000_check_for_link establishes link
3853 * for copper adapters ONLY
3854 */
3855 switch (hw->phy.media_type) {
3856 case e1000_media_type_copper:
3857 if (hw->mac.get_link_status) {
3858 ret_val = hw->mac.ops.check_for_link(hw);
3859 link_active = !hw->mac.get_link_status;
3860 } else {
3861 link_active = true;
3862 }
3863 break;
4d6b725e
AD		 3864 case e1000_media_type_internal_serdes:
3865 ret_val = hw->mac.ops.check_for_link(hw);
3866 link_active = hw->mac.serdes_has_link;
3867 break;
3868 default:
3869 case e1000_media_type_unknown:
3870 break;
3871 }
3872
3873 return link_active;
3874}
3875
563988dc
SA		 3876static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3877{
3878 bool ret = false;
3879 u32 ctrl_ext, thstat;
3880
f96a8a0b 3881 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3882 if (hw->mac.type == e1000_i350) {
3883 thstat = rd32(E1000_THSTAT);
3884 ctrl_ext = rd32(E1000_CTRL_EXT);
3885
3886 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3887 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3888 ret = !!(thstat & event);
563988dc
SA		 3889 }
3890
3891 return ret;
3892}
3893
9d5c8243 3894/**
b980ac18
JK		 3895 * igb_watchdog - Timer Call-back
3896 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3897 **/
3898static void igb_watchdog(unsigned long data)
3899{
3900 struct igb_adapter *adapter = (struct igb_adapter *)data;
3901 /* Do the rest outside of interrupt context */
3902 schedule_work(&adapter->watchdog_task);
3903}
3904
3905static void igb_watchdog_task(struct work_struct *work)
3906{
3907 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3908 struct igb_adapter,
3909 watchdog_task);
9d5c8243 3910 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3911 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3912 struct net_device *netdev = adapter->netdev;
563988dc 3913 u32 link;
7a6ea550 3914 int i;
9d5c8243 3915
4d6b725e 3916 link = igb_has_link(adapter);
9d5c8243 3917 if (link) {
749ab2cd
YZ		 3918 /* Cancel scheduled suspend requests. */
3919 pm_runtime_resume(netdev->dev.parent);
3920
9d5c8243
AK		 3921 if (!netif_carrier_ok(netdev)) {
3922 u32 ctrl;
330a6d6a 3923 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3924 &adapter->link_speed,
3925 &adapter->link_duplex);
9d5c8243
AK		 3926
3927 ctrl = rd32(E1000_CTRL);
527d47c1 3928 /* Links status message must follow this format */
876d2d6f
JK		 3929 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3930 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3931 netdev->name,
3932 adapter->link_speed,
3933 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3934 "Full" : "Half",
3935 (ctrl & E1000_CTRL_TFCE) &&
3936 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3937 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3938 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3939
c0ba4778
KS		 3940 /* check if SmartSpeed worked */
3941 igb_check_downshift(hw);
3942 if (phy->speed_downgraded)
3943 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3944
563988dc 3945 /* check for thermal sensor event */
876d2d6f
JK		 3946 if (igb_thermal_sensor_event(hw,
3947 E1000_THSTAT_LINK_THROTTLE)) {
3948 netdev_info(netdev, "The network adapter link "
3949 "speed was downshifted because it "
3950 "overheated\n");
7ef5ed1c 3951 }
563988dc 3952
d07f3e37 3953 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3954 adapter->tx_timeout_factor = 1;
3955 switch (adapter->link_speed) {
3956 case SPEED_10:
9d5c8243
AK		 3957 adapter->tx_timeout_factor = 14;
3958 break;
3959 case SPEED_100:
9d5c8243
AK		 3960 /* maybe add some timeout factor ? */
3961 break;
3962 }
3963
3964 netif_carrier_on(netdev);
9d5c8243 3965
4ae196df 3966 igb_ping_all_vfs(adapter);
17dc566c 3967 igb_check_vf_rate_limit(adapter);
4ae196df 3968
4b1a9877 3969 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3970 if (!test_bit(__IGB_DOWN, &adapter->state))
3971 mod_timer(&adapter->phy_info_timer,
3972 round_jiffies(jiffies + 2 * HZ));
3973 }
3974 } else {
3975 if (netif_carrier_ok(netdev)) {
3976 adapter->link_speed = 0;
3977 adapter->link_duplex = 0;
563988dc
SA		 3978
3979 /* check for thermal sensor event */
876d2d6f
JK		 3980 if (igb_thermal_sensor_event(hw,
3981 E1000_THSTAT_PWR_DOWN)) {
3982 netdev_err(netdev, "The network adapter was "
3983 "stopped because it overheated\n");
7ef5ed1c 3984 }
563988dc 3985
527d47c1
AD		 3986 /* Links status message must follow this format */
3987 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3988 netdev->name);
9d5c8243 3989 netif_carrier_off(netdev);
4b1a9877 3990
4ae196df
AD		 3991 igb_ping_all_vfs(adapter);
3992
4b1a9877 3993 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3994 if (!test_bit(__IGB_DOWN, &adapter->state))
3995 mod_timer(&adapter->phy_info_timer,
3996 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3997
3998 pm_schedule_suspend(netdev->dev.parent,
3999 MSEC_PER_SEC * 5);
9d5c8243
AK		 4000 }
4001 }
4002
12dcd86b
ED		 4003 spin_lock(&adapter->stats64_lock);
4004 igb_update_stats(adapter, &adapter->stats64);
4005 spin_unlock(&adapter->stats64_lock);
9d5c8243 4006
dbabb065 4007 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4008 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4009 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4010 /* We've lost link, so the controller stops DMA,
4011 * but we've got queued Tx work that's never going
4012 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4013 * (Do the reset outside of interrupt context).
4014 */
dbabb065
AD		 4015 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4016 adapter->tx_timeout_count++;
4017 schedule_work(&adapter->reset_task);
4018 /* return immediately since reset is imminent */
4019 return;
4020 }
9d5c8243 4021 }
9d5c8243 4022
dbabb065 4023 /* Force detection of hung controller every watchdog period */
6d095fa8 4024 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4025 }
f7ba205e 4026
b980ac18 4027 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4028 if (adapter->msix_entries) {
047e0030 4029 u32 eics = 0;
0d1ae7f4
AD		 4030 for (i = 0; i < adapter->num_q_vectors; i++)
4031 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4032 wr32(E1000_EICS, eics);
4033 } else {
4034 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4035 }
9d5c8243 4036
13800469 4037 igb_spoof_check(adapter);
fc580751 4038 igb_ptp_rx_hang(adapter);
13800469 4039
9d5c8243
AK		 4040 /* Reset the timer */
4041 if (!test_bit(__IGB_DOWN, &adapter->state))
4042 mod_timer(&adapter->watchdog_timer,
4043 round_jiffies(jiffies + 2 * HZ));
4044}
4045
4046enum latency_range {
4047 lowest_latency = 0,
4048 low_latency = 1,
4049 bulk_latency = 2,
4050 latency_invalid = 255
4051};
4052
6eb5a7f1 4053/**
b980ac18
JK		 4054 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4055 * @q_vector: pointer to q_vector
6eb5a7f1 4056 *
b980ac18
JK		 4057 * Stores a new ITR value based on strictly on packet size. This
4058 * algorithm is less sophisticated than that used in igb_update_itr,
4059 * due to the difficulty of synchronizing statistics across multiple
4060 * receive rings. The divisors and thresholds used by this function
4061 * were determined based on theoretical maximum wire speed and testing
4062 * data, in order to minimize response time while increasing bulk
4063 * throughput.
4064 * This functionality is controlled by the InterruptThrottleRate module
4065 * parameter (see igb_param.c)
4066 * NOTE: This function is called only when operating in a multiqueue
4067 * receive environment.
6eb5a7f1 4068 **/
047e0030 4069static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4070{
047e0030 4071 int new_val = q_vector->itr_val;
6eb5a7f1 4072 int avg_wire_size = 0;
047e0030 4073 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4074 unsigned int packets;
9d5c8243 4075
6eb5a7f1
AD		 4076 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4077 * ints/sec - ITR timer value of 120 ticks.
4078 */
4079 if (adapter->link_speed != SPEED_1000) {
0ba82994 4080 new_val = IGB_4K_ITR;
6eb5a7f1 4081 goto set_itr_val;
9d5c8243 4082 }
047e0030 4083
0ba82994
AD		 4084 packets = q_vector->rx.total_packets;
4085 if (packets)
4086 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4087
0ba82994
AD		 4088 packets = q_vector->tx.total_packets;
4089 if (packets)
4090 avg_wire_size = max_t(u32, avg_wire_size,
4091 q_vector->tx.total_bytes / packets);
047e0030
AD		 4092
4093 /* if avg_wire_size isn't set no work was done */
4094 if (!avg_wire_size)
4095 goto clear_counts;
9d5c8243 4096
6eb5a7f1
AD		 4097 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4098 avg_wire_size += 24;
4099
4100 /* Don't starve jumbo frames */
4101 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4102
6eb5a7f1
AD		 4103 /* Give a little boost to mid-size frames */
4104 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4105 new_val = avg_wire_size / 3;
4106 else
4107 new_val = avg_wire_size / 2;
9d5c8243 4108
0ba82994
AD		 4109 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4110 if (new_val < IGB_20K_ITR &&
4111 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4112 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4113 new_val = IGB_20K_ITR;
abe1c363 4114
6eb5a7f1 4115set_itr_val:
047e0030
AD		 4116 if (new_val != q_vector->itr_val) {
4117 q_vector->itr_val = new_val;
4118 q_vector->set_itr = 1;
9d5c8243 4119 }
6eb5a7f1 4120clear_counts:
0ba82994
AD		 4121 q_vector->rx.total_bytes = 0;
4122 q_vector->rx.total_packets = 0;
4123 q_vector->tx.total_bytes = 0;
4124 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4125}
4126
4127/**
b980ac18
JK		 4128 * igb_update_itr - update the dynamic ITR value based on statistics
4129 * @q_vector: pointer to q_vector
4130 * @ring_container: ring info to update the itr for
4131 *
4132 * Stores a new ITR value based on packets and byte
4133 * counts during the last interrupt. The advantage of per interrupt
4134 * computation is faster updates and more accurate ITR for the current
4135 * traffic pattern. Constants in this function were computed
4136 * based on theoretical maximum wire speed and thresholds were set based
4137 * on testing data as well as attempting to minimize response time
4138 * while increasing bulk throughput.
4139 * this functionality is controlled by the InterruptThrottleRate module
4140 * parameter (see igb_param.c)
4141 * NOTE: These calculations are only valid when operating in a single-
4142 * queue environment.
9d5c8243 4143 **/
0ba82994
AD		 4144static void igb_update_itr(struct igb_q_vector *q_vector,
4145 struct igb_ring_container *ring_container)
9d5c8243 4146{
0ba82994
AD		 4147 unsigned int packets = ring_container->total_packets;
4148 unsigned int bytes = ring_container->total_bytes;
4149 u8 itrval = ring_container->itr;
9d5c8243 4150
0ba82994 4151 /* no packets, exit with status unchanged */
9d5c8243 4152 if (packets == 0)
0ba82994 4153 return;
9d5c8243 4154
0ba82994 4155 switch (itrval) {
9d5c8243
AK		 4156 case lowest_latency:
4157 /* handle TSO and jumbo frames */
4158 if (bytes/packets > 8000)
0ba82994 4159 itrval = bulk_latency;
9d5c8243 4160 else if ((packets < 5) && (bytes > 512))
0ba82994 4161 itrval = low_latency;
9d5c8243
AK		 4162 break;
4163 case low_latency: /* 50 usec aka 20000 ints/s */
4164 if (bytes > 10000) {
4165 /* this if handles the TSO accounting */
4166 if (bytes/packets > 8000) {
0ba82994 4167 itrval = bulk_latency;
9d5c8243 4168 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4169 itrval = bulk_latency;
9d5c8243 4170 } else if ((packets > 35)) {
0ba82994 4171 itrval = lowest_latency;
9d5c8243
AK		 4172 }
4173 } else if (bytes/packets > 2000) {
0ba82994 4174 itrval = bulk_latency;
9d5c8243 4175 } else if (packets <= 2 && bytes < 512) {
0ba82994 4176 itrval = lowest_latency;
9d5c8243
AK		 4177 }
4178 break;
4179 case bulk_latency: /* 250 usec aka 4000 ints/s */
4180 if (bytes > 25000) {
4181 if (packets > 35)
0ba82994 4182 itrval = low_latency;
1e5c3d21 4183 } else if (bytes < 1500) {
0ba82994 4184 itrval = low_latency;
9d5c8243
AK		 4185 }
4186 break;
4187 }
4188
0ba82994
AD		 4189 /* clear work counters since we have the values we need */
4190 ring_container->total_bytes = 0;
4191 ring_container->total_packets = 0;
4192
4193 /* write updated itr to ring container */
4194 ring_container->itr = itrval;
9d5c8243
AK		 4195}
4196
0ba82994 4197static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4198{
0ba82994 4199 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4200 u32 new_itr = q_vector->itr_val;
0ba82994 4201 u8 current_itr = 0;
9d5c8243
AK		 4202
4203 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4204 if (adapter->link_speed != SPEED_1000) {
4205 current_itr = 0;
0ba82994 4206 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4207 goto set_itr_now;
4208 }
4209
0ba82994
AD		 4210 igb_update_itr(q_vector, &q_vector->tx);
4211 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4212
0ba82994 4213 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4214
6eb5a7f1 4215 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4216 if (current_itr == lowest_latency &&
4217 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4218 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4219 current_itr = low_latency;
4220
9d5c8243
AK		 4221 switch (current_itr) {
4222 /* counts and packets in update_itr are dependent on these numbers */
4223 case lowest_latency:
0ba82994 4224 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4225 break;
4226 case low_latency:
0ba82994 4227 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4228 break;
4229 case bulk_latency:
0ba82994 4230 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4231 break;
4232 default:
4233 break;
4234 }
4235
4236set_itr_now:
047e0030 4237 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4238 /* this attempts to bias the interrupt rate towards Bulk
4239 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4240 * increasing
4241 */
047e0030 4242 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4243 max((new_itr * q_vector->itr_val) /
4244 (new_itr + (q_vector->itr_val >> 2)),
4245 new_itr) : new_itr;
9d5c8243
AK		 4246 /* Don't write the value here; it resets the adapter's
4247 * internal timer, and causes us to delay far longer than
4248 * we should between interrupts. Instead, we write the ITR
4249 * value at the beginning of the next interrupt so the timing
4250 * ends up being correct.
4251 */
047e0030
AD		 4252 q_vector->itr_val = new_itr;
4253 q_vector->set_itr = 1;
9d5c8243 4254 }
9d5c8243
AK		 4255}
4256
c50b52a0
SH		 4257static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4258 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4259{
4260 struct e1000_adv_tx_context_desc *context_desc;
4261 u16 i = tx_ring->next_to_use;
4262
4263 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4264
4265 i++;
4266 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4267
4268 /* set bits to identify this as an advanced context descriptor */
4269 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4270
4271 /* For 82575, context index must be unique per ring. */
866cff06 4272 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4273 mss_l4len_idx |= tx_ring->reg_idx << 4;
4274
4275 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4276 context_desc->seqnum_seed = 0;
4277 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4278 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4279}
4280
7af40ad9
AD		 4281static int igb_tso(struct igb_ring *tx_ring,
4282 struct igb_tx_buffer *first,
4283 u8 *hdr_len)
9d5c8243 4284{
7af40ad9 4285 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4286 u32 vlan_macip_lens, type_tucmd;
4287 u32 mss_l4len_idx, l4len;
4288
ed6aa105
AD		 4289 if (skb->ip_summed != CHECKSUM_PARTIAL)
4290 return 0;
4291
7d13a7d0
AD		 4292 if (!skb_is_gso(skb))
4293 return 0;
9d5c8243
AK		 4294
4295 if (skb_header_cloned(skb)) {
7af40ad9 4296 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4297 if (err)
4298 return err;
4299 }
4300
7d13a7d0
AD		 4301 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4302 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4303
7af40ad9 4304 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4305 struct iphdr *iph = ip_hdr(skb);
4306 iph->tot_len = 0;
4307 iph->check = 0;
4308 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4309 iph->daddr, 0,
4310 IPPROTO_TCP,
4311 0);
7d13a7d0 4312 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4313 first->tx_flags |= IGB_TX_FLAGS_TSO |
4314 IGB_TX_FLAGS_CSUM |
4315 IGB_TX_FLAGS_IPV4;
8e1e8a47 4316 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4317 ipv6_hdr(skb)->payload_len = 0;
4318 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4319 &ipv6_hdr(skb)->daddr,
4320 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4321 first->tx_flags |= IGB_TX_FLAGS_TSO |
4322 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4323 }
4324
7af40ad9 4325 /* compute header lengths */
7d13a7d0
AD		 4326 l4len = tcp_hdrlen(skb);
4327 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4328
7af40ad9
AD		 4329 /* update gso size and bytecount with header size */
4330 first->gso_segs = skb_shinfo(skb)->gso_segs;
4331 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4332
9d5c8243 4333 /* MSS L4LEN IDX */
7d13a7d0
AD		 4334 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4335 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4336
7d13a7d0
AD		 4337 /* VLAN MACLEN IPLEN */
4338 vlan_macip_lens = skb_network_header_len(skb);
4339 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4340 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4341
7d13a7d0 4342 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4343
7d13a7d0 4344 return 1;
9d5c8243
AK		 4345}
4346
7af40ad9 4347static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4348{
7af40ad9 4349 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4350 u32 vlan_macip_lens = 0;
4351 u32 mss_l4len_idx = 0;
4352 u32 type_tucmd = 0;
9d5c8243 4353
7d13a7d0 4354 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4355 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4356 return;
7d13a7d0
AD		 4357 } else {
4358 u8 l4_hdr = 0;
7af40ad9 4359 switch (first->protocol) {
7d13a7d0
AD		 4360 case __constant_htons(ETH_P_IP):
4361 vlan_macip_lens |= skb_network_header_len(skb);
4362 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4363 l4_hdr = ip_hdr(skb)->protocol;
4364 break;
4365 case __constant_htons(ETH_P_IPV6):
4366 vlan_macip_lens |= skb_network_header_len(skb);
4367 l4_hdr = ipv6_hdr(skb)->nexthdr;
4368 break;
4369 default:
4370 if (unlikely(net_ratelimit())) {
4371 dev_warn(tx_ring->dev,
b980ac18
JK		 4372 "partial checksum but proto=%x!\n",
4373 first->protocol);
fa4a7ef3 4374 }
7d13a7d0
AD		 4375 break;
4376 }
fa4a7ef3 4377
7d13a7d0
AD		 4378 switch (l4_hdr) {
4379 case IPPROTO_TCP:
4380 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4381 mss_l4len_idx = tcp_hdrlen(skb) <<
4382 E1000_ADVTXD_L4LEN_SHIFT;
4383 break;
4384 case IPPROTO_SCTP:
4385 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4386 mss_l4len_idx = sizeof(struct sctphdr) <<
4387 E1000_ADVTXD_L4LEN_SHIFT;
4388 break;
4389 case IPPROTO_UDP:
4390 mss_l4len_idx = sizeof(struct udphdr) <<
4391 E1000_ADVTXD_L4LEN_SHIFT;
4392 break;
4393 default:
4394 if (unlikely(net_ratelimit())) {
4395 dev_warn(tx_ring->dev,
b980ac18
JK		 4396 "partial checksum but l4 proto=%x!\n",
4397 l4_hdr);
44b0cda3 4398 }
7d13a7d0 4399 break;
9d5c8243 4400 }
7af40ad9
AD		 4401
4402 /* update TX checksum flag */
4403 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4404 }
9d5c8243 4405
7d13a7d0 4406 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4407 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4408
7d13a7d0 4409 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4410}
4411
1d9daf45
AD		 4412#define IGB_SET_FLAG(_input, _flag, _result) \
4413 ((_flag <= _result) ? \
4414 ((u32)(_input & _flag) * (_result / _flag)) : \
4415 ((u32)(_input & _flag) / (_flag / _result)))
4416
4417static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4418{
4419 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4420 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4421 E1000_ADVTXD_DCMD_DEXT |
4422 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4423
4424 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4425 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4426 (E1000_ADVTXD_DCMD_VLE));
4427
4428 /* set segmentation bits for TSO */
4429 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4430 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4431
4432 /* set timestamp bit if present */
1d9daf45
AD		 4433 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4434 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4435
1d9daf45
AD		 4436 /* insert frame checksum */
4437 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4438
4439 return cmd_type;
4440}
4441
7af40ad9
AD		 4442static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4443 union e1000_adv_tx_desc *tx_desc,
4444 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4445{
4446 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4447
1d9daf45
AD		 4448 /* 82575 requires a unique index per ring */
4449 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4450 olinfo_status |= tx_ring->reg_idx << 4;
4451
4452 /* insert L4 checksum */
1d9daf45
AD		 4453 olinfo_status |= IGB_SET_FLAG(tx_flags,
4454 IGB_TX_FLAGS_CSUM,
4455 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4456
1d9daf45
AD		 4457 /* insert IPv4 checksum */
4458 olinfo_status |= IGB_SET_FLAG(tx_flags,
4459 IGB_TX_FLAGS_IPV4,
4460 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4461
7af40ad9 4462 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4463}
4464
7af40ad9
AD		 4465static void igb_tx_map(struct igb_ring *tx_ring,
4466 struct igb_tx_buffer *first,
ebe42d16 4467 const u8 hdr_len)
9d5c8243 4468{
7af40ad9 4469 struct sk_buff *skb = first->skb;
c9f14bf3 4470 struct igb_tx_buffer *tx_buffer;
ebe42d16 4471 union e1000_adv_tx_desc *tx_desc;
80d0759e 4472 struct skb_frag_struct *frag;
ebe42d16 4473 dma_addr_t dma;
80d0759e 4474 unsigned int data_len, size;
7af40ad9 4475 u32 tx_flags = first->tx_flags;
1d9daf45 4476 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4477 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4478
4479 tx_desc = IGB_TX_DESC(tx_ring, i);
4480
80d0759e
AD		 4481 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4482
4483 size = skb_headlen(skb);
4484 data_len = skb->data_len;
ebe42d16
AD		 4485
4486 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4487
80d0759e
AD		 4488 tx_buffer = first;
4489
4490 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4491 if (dma_mapping_error(tx_ring->dev, dma))
4492 goto dma_error;
4493
4494 /* record length, and DMA address */
4495 dma_unmap_len_set(tx_buffer, len, size);
4496 dma_unmap_addr_set(tx_buffer, dma, dma);
4497
4498 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4499
ebe42d16
AD		 4500 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4501 tx_desc->read.cmd_type_len =
1d9daf45 4502 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4503
4504 i++;
4505 tx_desc++;
4506 if (i == tx_ring->count) {
4507 tx_desc = IGB_TX_DESC(tx_ring, 0);
4508 i = 0;
4509 }
80d0759e 4510 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4511
4512 dma += IGB_MAX_DATA_PER_TXD;
4513 size -= IGB_MAX_DATA_PER_TXD;
4514
ebe42d16
AD		 4515 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4516 }
4517
4518 if (likely(!data_len))
4519 break;
2bbfebe2 4520
1d9daf45 4521 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4522
65689fef 4523 i++;
ebe42d16
AD		 4524 tx_desc++;
4525 if (i == tx_ring->count) {
4526 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4527 i = 0;
ebe42d16 4528 }
80d0759e 4529 tx_desc->read.olinfo_status = 0;
65689fef 4530
9e903e08 4531 size = skb_frag_size(frag);
ebe42d16
AD		 4532 data_len -= size;
4533
4534 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4535 size, DMA_TO_DEVICE);
6366ad33 4536
c9f14bf3 4537 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4538 }
4539
ebe42d16 4540 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4541 cmd_type |= size | IGB_TXD_DCMD;
4542 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4543
80d0759e
AD		 4544 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4545
8542db05
AD		 4546 /* set the timestamp */
4547 first->time_stamp = jiffies;
4548
b980ac18 4549 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4550 * are new descriptors to fetch. (Only applicable for weak-ordered
4551 * memory model archs, such as IA-64).
4552 *
4553 * We also need this memory barrier to make certain all of the
4554 * status bits have been updated before next_to_watch is written.
4555 */
4556 wmb();
4557
8542db05 4558 /* set next_to_watch value indicating a packet is present */
ebe42d16 4559 first->next_to_watch = tx_desc;
9d5c8243 4560
ebe42d16
AD		 4561 i++;
4562 if (i == tx_ring->count)
4563 i = 0;
6366ad33 4564
ebe42d16 4565 tx_ring->next_to_use = i;
6366ad33 4566
ebe42d16 4567 writel(i, tx_ring->tail);
6366ad33 4568
ebe42d16 4569 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4570 * at a time, it synchronizes IO on IA64/Altix systems
4571 */
ebe42d16
AD		 4572 mmiowb();
4573
4574 return;
4575
4576dma_error:
4577 dev_err(tx_ring->dev, "TX DMA map failed\n");
4578
4579 /* clear dma mappings for failed tx_buffer_info map */
4580 for (;;) {
c9f14bf3
AD		 4581 tx_buffer = &tx_ring->tx_buffer_info[i];
4582 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4583 if (tx_buffer == first)
ebe42d16 4584 break;
a77ff709
NN		 4585 if (i == 0)
4586 i = tx_ring->count;
6366ad33 4587 i--;
6366ad33
AD		 4588 }
4589
9d5c8243 4590 tx_ring->next_to_use = i;
9d5c8243
AK		 4591}
4592
6ad4edfc 4593static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4594{
e694e964
AD		 4595 struct net_device *netdev = tx_ring->netdev;
4596
661086df 4597 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4598
9d5c8243
AK		 4599 /* Herbert's original patch had:
4600 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4601 * but since that doesn't exist yet, just open code it.
4602 */
9d5c8243
AK		 4603 smp_mb();
4604
4605 /* We need to check again in a case another CPU has just
b980ac18
JK		 4606 * made room available.
4607 */
c493ea45 4608 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4609 return -EBUSY;
4610
4611 /* A reprieve! */
661086df 4612 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4613
4614 u64_stats_update_begin(&tx_ring->tx_syncp2);
4615 tx_ring->tx_stats.restart_queue2++;
4616 u64_stats_update_end(&tx_ring->tx_syncp2);
4617
9d5c8243
AK		 4618 return 0;
4619}
4620
6ad4edfc 4621static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4622{
c493ea45 4623 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4624 return 0;
e694e964 4625 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4626}
4627
cd392f5c
AD		 4628netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4629 struct igb_ring *tx_ring)
9d5c8243 4630{
8542db05 4631 struct igb_tx_buffer *first;
ebe42d16 4632 int tso;
91d4ee33 4633 u32 tx_flags = 0;
21ba6fe1 4634 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4635 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4636 u8 hdr_len = 0;
9d5c8243 4637
21ba6fe1
AD		 4638 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4639 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4640 * + 2 desc gap to keep tail from touching head,
9d5c8243 4641 * + 1 desc for context descriptor,
21ba6fe1
AD		 4642 * otherwise try next time
4643 */
4644 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4645 unsigned short f;
4646 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4647 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4648 } else {
4649 count += skb_shinfo(skb)->nr_frags;
4650 }
4651
4652 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4653 /* this is a hard error */
9d5c8243
AK		 4654 return NETDEV_TX_BUSY;
4655 }
33af6bcc 4656
7af40ad9
AD		 4657 /* record the location of the first descriptor for this packet */
4658 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4659 first->skb = skb;
4660 first->bytecount = skb->len;
4661 first->gso_segs = 1;
4662
b66e2397
MV		 4663 skb_tx_timestamp(skb);
4664
b646c22e
AD		 4665 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4666 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4667
b646c22e
AD		 4668 if (!(adapter->ptp_tx_skb)) {
4669 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4670 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4671
4672 adapter->ptp_tx_skb = skb_get(skb);
4673 adapter->ptp_tx_start = jiffies;
4674 if (adapter->hw.mac.type == e1000_82576)
4675 schedule_work(&adapter->ptp_tx_work);
4676 }
33af6bcc 4677 }
9d5c8243 4678
eab6d18d 4679 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4680 tx_flags |= IGB_TX_FLAGS_VLAN;
4681 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4682 }
4683
7af40ad9
AD		 4684 /* record initial flags and protocol */
4685 first->tx_flags = tx_flags;
4686 first->protocol = protocol;
cdfd01fc 4687
7af40ad9
AD		 4688 tso = igb_tso(tx_ring, first, &hdr_len);
4689 if (tso < 0)
7d13a7d0 4690 goto out_drop;
7af40ad9
AD		 4691 else if (!tso)
4692 igb_tx_csum(tx_ring, first);
9d5c8243 4693
7af40ad9 4694 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4695
4696 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4697 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4698
9d5c8243 4699 return NETDEV_TX_OK;
7d13a7d0
AD		 4700
4701out_drop:
7af40ad9
AD		 4702 igb_unmap_and_free_tx_resource(tx_ring, first);
4703
7d13a7d0 4704 return NETDEV_TX_OK;
9d5c8243
AK		 4705}
4706
1cc3bd87
AD		 4707static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4708 struct sk_buff *skb)
4709{
4710 unsigned int r_idx = skb->queue_mapping;
4711
4712 if (r_idx >= adapter->num_tx_queues)
4713 r_idx = r_idx % adapter->num_tx_queues;
4714
4715 return adapter->tx_ring[r_idx];
4716}
4717
cd392f5c
AD		 4718static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4719 struct net_device *netdev)
9d5c8243
AK		 4720{
4721 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4722
4723 if (test_bit(__IGB_DOWN, &adapter->state)) {
4724 dev_kfree_skb_any(skb);
4725 return NETDEV_TX_OK;
4726 }
4727
4728 if (skb->len <= 0) {
4729 dev_kfree_skb_any(skb);
4730 return NETDEV_TX_OK;
4731 }
4732
b980ac18 4733 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4734 * in order to meet this minimum size requirement.
4735 */
ea5ceeab
TD		 4736 if (unlikely(skb->len < 17)) {
4737 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4738 return NETDEV_TX_OK;
4739 skb->len = 17;
ea5ceeab 4740 skb_set_tail_pointer(skb, 17);
1cc3bd87 4741 }
9d5c8243 4742
1cc3bd87 4743 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4744}
4745
4746/**
b980ac18
JK		 4747 * igb_tx_timeout - Respond to a Tx Hang
4748 * @netdev: network interface device structure
9d5c8243
AK		 4749 **/
4750static void igb_tx_timeout(struct net_device *netdev)
4751{
4752 struct igb_adapter *adapter = netdev_priv(netdev);
4753 struct e1000_hw *hw = &adapter->hw;
4754
4755 /* Do the reset outside of interrupt context */
4756 adapter->tx_timeout_count++;
f7ba205e 4757
06218a8d 4758 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4759 hw->dev_spec._82575.global_device_reset = true;
4760
9d5c8243 4761 schedule_work(&adapter->reset_task);
265de409
AD		 4762 wr32(E1000_EICS,
4763 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4764}
4765
4766static void igb_reset_task(struct work_struct *work)
4767{
4768 struct igb_adapter *adapter;
4769 adapter = container_of(work, struct igb_adapter, reset_task);
4770
c97ec42a
TI		 4771 igb_dump(adapter);
4772 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4773 igb_reinit_locked(adapter);
4774}
4775
4776/**
b980ac18
JK		 4777 * igb_get_stats64 - Get System Network Statistics
4778 * @netdev: network interface device structure
4779 * @stats: rtnl_link_stats64 pointer
9d5c8243 4780 **/
12dcd86b 4781static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4782 struct rtnl_link_stats64 *stats)
9d5c8243 4783{
12dcd86b
ED		 4784 struct igb_adapter *adapter = netdev_priv(netdev);
4785
4786 spin_lock(&adapter->stats64_lock);
4787 igb_update_stats(adapter, &adapter->stats64);
4788 memcpy(stats, &adapter->stats64, sizeof(*stats));
4789 spin_unlock(&adapter->stats64_lock);
4790
4791 return stats;
9d5c8243
AK		 4792}
4793
4794/**
b980ac18
JK		 4795 * igb_change_mtu - Change the Maximum Transfer Unit
4796 * @netdev: network interface device structure
4797 * @new_mtu: new value for maximum frame size
9d5c8243 4798 *
b980ac18 4799 * Returns 0 on success, negative on failure
9d5c8243
AK		 4800 **/
4801static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4802{
4803 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4804 struct pci_dev *pdev = adapter->pdev;
153285f9 4805 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4806
c809d227 4807 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4808 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4809 return -EINVAL;
4810 }
4811
153285f9 4812#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4813 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4814 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4815 return -EINVAL;
4816 }
4817
4818 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4819 msleep(1);
73cd78f1 4820
9d5c8243
AK		 4821 /* igb_down has a dependency on max_frame_size */
4822 adapter->max_frame_size = max_frame;
559e9c49 4823
4c844851
AD		 4824 if (netif_running(netdev))
4825 igb_down(adapter);
9d5c8243 4826
090b1795 4827 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4828 netdev->mtu, new_mtu);
4829 netdev->mtu = new_mtu;
4830
4831 if (netif_running(netdev))
4832 igb_up(adapter);
4833 else
4834 igb_reset(adapter);
4835
4836 clear_bit(__IGB_RESETTING, &adapter->state);
4837
4838 return 0;
4839}
4840
4841/**
b980ac18
JK		 4842 * igb_update_stats - Update the board statistics counters
4843 * @adapter: board private structure
9d5c8243 4844 **/
12dcd86b
ED		 4845void igb_update_stats(struct igb_adapter *adapter,
4846 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4847{
4848 struct e1000_hw *hw = &adapter->hw;
4849 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4850 u32 reg, mpc;
9d5c8243 4851 u16 phy_tmp;
3f9c0164
AD		 4852 int i;
4853 u64 bytes, packets;
12dcd86b
ED		 4854 unsigned int start;
4855 u64 _bytes, _packets;
9d5c8243
AK		 4856
4857#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4858
b980ac18 4859 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4860 * connection is down.
4861 */
4862 if (adapter->link_speed == 0)
4863 return;
4864 if (pci_channel_offline(pdev))
4865 return;
4866
3f9c0164
AD		 4867 bytes = 0;
4868 packets = 0;
4869 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4870 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4871 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4872
ae1c07a6
AD		 4873 if (rqdpc) {
4874 ring->rx_stats.drops += rqdpc;
4875 net_stats->rx_fifo_errors += rqdpc;
4876 }
12dcd86b
ED		 4877
4878 do {
4879 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4880 _bytes = ring->rx_stats.bytes;
4881 _packets = ring->rx_stats.packets;
4882 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4883 bytes += _bytes;
4884 packets += _packets;
3f9c0164
AD		 4885 }
4886
128e45eb
AD		 4887 net_stats->rx_bytes = bytes;
4888 net_stats->rx_packets = packets;
3f9c0164
AD		 4889
4890 bytes = 0;
4891 packets = 0;
4892 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4893 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4894 do {
4895 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4896 _bytes = ring->tx_stats.bytes;
4897 _packets = ring->tx_stats.packets;
4898 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4899 bytes += _bytes;
4900 packets += _packets;
3f9c0164 4901 }
128e45eb
AD		 4902 net_stats->tx_bytes = bytes;
4903 net_stats->tx_packets = packets;
3f9c0164
AD		 4904
4905 /* read stats registers */
9d5c8243
AK		 4906 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4907 adapter->stats.gprc += rd32(E1000_GPRC);
4908 adapter->stats.gorc += rd32(E1000_GORCL);
4909 rd32(E1000_GORCH); /* clear GORCL */
4910 adapter->stats.bprc += rd32(E1000_BPRC);
4911 adapter->stats.mprc += rd32(E1000_MPRC);
4912 adapter->stats.roc += rd32(E1000_ROC);
4913
4914 adapter->stats.prc64 += rd32(E1000_PRC64);
4915 adapter->stats.prc127 += rd32(E1000_PRC127);
4916 adapter->stats.prc255 += rd32(E1000_PRC255);
4917 adapter->stats.prc511 += rd32(E1000_PRC511);
4918 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4919 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4920 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4921 adapter->stats.sec += rd32(E1000_SEC);
4922
fa3d9a6d
MW		 4923 mpc = rd32(E1000_MPC);
4924 adapter->stats.mpc += mpc;
4925 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4926 adapter->stats.scc += rd32(E1000_SCC);
4927 adapter->stats.ecol += rd32(E1000_ECOL);
4928 adapter->stats.mcc += rd32(E1000_MCC);
4929 adapter->stats.latecol += rd32(E1000_LATECOL);
4930 adapter->stats.dc += rd32(E1000_DC);
4931 adapter->stats.rlec += rd32(E1000_RLEC);
4932 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4933 adapter->stats.xontxc += rd32(E1000_XONTXC);
4934 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4935 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4936 adapter->stats.fcruc += rd32(E1000_FCRUC);
4937 adapter->stats.gptc += rd32(E1000_GPTC);
4938 adapter->stats.gotc += rd32(E1000_GOTCL);
4939 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4940 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4941 adapter->stats.ruc += rd32(E1000_RUC);
4942 adapter->stats.rfc += rd32(E1000_RFC);
4943 adapter->stats.rjc += rd32(E1000_RJC);
4944 adapter->stats.tor += rd32(E1000_TORH);
4945 adapter->stats.tot += rd32(E1000_TOTH);
4946 adapter->stats.tpr += rd32(E1000_TPR);
4947
4948 adapter->stats.ptc64 += rd32(E1000_PTC64);
4949 adapter->stats.ptc127 += rd32(E1000_PTC127);
4950 adapter->stats.ptc255 += rd32(E1000_PTC255);
4951 adapter->stats.ptc511 += rd32(E1000_PTC511);
4952 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4953 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4954
4955 adapter->stats.mptc += rd32(E1000_MPTC);
4956 adapter->stats.bptc += rd32(E1000_BPTC);
4957
2d0b0f69
NN		 4958 adapter->stats.tpt += rd32(E1000_TPT);
4959 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4960
4961 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4962 /* read internal phy specific stats */
4963 reg = rd32(E1000_CTRL_EXT);
4964 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4965 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4966
4967 /* this stat has invalid values on i210/i211 */
4968 if ((hw->mac.type != e1000_i210) &&
4969 (hw->mac.type != e1000_i211))
4970 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4971 }
4972
9d5c8243
AK		 4973 adapter->stats.tsctc += rd32(E1000_TSCTC);
4974 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4975
4976 adapter->stats.iac += rd32(E1000_IAC);
4977 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4978 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4979 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4980 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4981 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4982 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4983 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4984 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4985
4986 /* Fill out the OS statistics structure */
128e45eb
AD		 4987 net_stats->multicast = adapter->stats.mprc;
4988 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4989
4990 /* Rx Errors */
4991
4992 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 4993 * our own version based on RUC and ROC
4994 */
128e45eb 4995 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4996 adapter->stats.crcerrs + adapter->stats.algnerrc +
4997 adapter->stats.ruc + adapter->stats.roc +
4998 adapter->stats.cexterr;
128e45eb
AD		 4999 net_stats->rx_length_errors = adapter->stats.ruc +
5000 adapter->stats.roc;
5001 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5002 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5003 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5004
5005 /* Tx Errors */
128e45eb
AD		 5006 net_stats->tx_errors = adapter->stats.ecol +
5007 adapter->stats.latecol;
5008 net_stats->tx_aborted_errors = adapter->stats.ecol;
5009 net_stats->tx_window_errors = adapter->stats.latecol;
5010 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5011
5012 /* Tx Dropped needs to be maintained elsewhere */
5013
5014 /* Phy Stats */
5015 if (hw->phy.media_type == e1000_media_type_copper) {
5016 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5017 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5018 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5019 adapter->phy_stats.idle_errors += phy_tmp;
5020 }
5021 }
5022
5023 /* Management Stats */
5024 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5025 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5026 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5027
5028 /* OS2BMC Stats */
5029 reg = rd32(E1000_MANC);
5030 if (reg & E1000_MANC_EN_BMC2OS) {
5031 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5032 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5033 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5034 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5035 }
9d5c8243
AK		 5036}
5037
9d5c8243
AK		 5038static irqreturn_t igb_msix_other(int irq, void *data)
5039{
047e0030 5040 struct igb_adapter *adapter = data;
9d5c8243 5041 struct e1000_hw *hw = &adapter->hw;
844290e5 5042 u32 icr = rd32(E1000_ICR);
844290e5 5043 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5044
7f081d40
AD		 5045 if (icr & E1000_ICR_DRSTA)
5046 schedule_work(&adapter->reset_task);
5047
047e0030 5048 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5049 /* HW is reporting DMA is out of sync */
5050 adapter->stats.doosync++;
13800469
GR		 5051 /* The DMA Out of Sync is also indication of a spoof event
5052 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5053 * see if it is really a spoof event.
5054 */
13800469 5055 igb_check_wvbr(adapter);
dda0e083 5056 }
eebbbdba 5057
4ae196df
AD		 5058 /* Check for a mailbox event */
5059 if (icr & E1000_ICR_VMMB)
5060 igb_msg_task(adapter);
5061
5062 if (icr & E1000_ICR_LSC) {
5063 hw->mac.get_link_status = 1;
5064 /* guard against interrupt when we're going down */
5065 if (!test_bit(__IGB_DOWN, &adapter->state))
5066 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5067 }
5068
1f6e8178
MV		 5069 if (icr & E1000_ICR_TS) {
5070 u32 tsicr = rd32(E1000_TSICR);
5071
5072 if (tsicr & E1000_TSICR_TXTS) {
5073 /* acknowledge the interrupt */
5074 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5075 /* retrieve hardware timestamp */
5076 schedule_work(&adapter->ptp_tx_work);
5077 }
5078 }
1f6e8178 5079
844290e5 5080 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5081
5082 return IRQ_HANDLED;
5083}
5084
047e0030 5085static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5086{
26b39276 5087 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5088 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5089
047e0030
AD		 5090 if (!q_vector->set_itr)
5091 return;
73cd78f1 5092
047e0030
AD		 5093 if (!itr_val)
5094 itr_val = 0x4;
661086df 5095
26b39276
AD		 5096 if (adapter->hw.mac.type == e1000_82575)
5097 itr_val |= itr_val << 16;
661086df 5098 else
0ba82994 5099 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5100
047e0030
AD		 5101 writel(itr_val, q_vector->itr_register);
5102 q_vector->set_itr = 0;
6eb5a7f1
AD		 5103}
5104
047e0030 5105static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5106{
047e0030 5107 struct igb_q_vector *q_vector = data;
9d5c8243 5108
047e0030
AD		 5109 /* Write the ITR value calculated from the previous interrupt. */
5110 igb_write_itr(q_vector);
9d5c8243 5111
047e0030 5112 napi_schedule(&q_vector->napi);
844290e5 5113
047e0030 5114 return IRQ_HANDLED;
fe4506b6
JC		 5115}
5116
421e02f0 5117#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5118static void igb_update_tx_dca(struct igb_adapter *adapter,
5119 struct igb_ring *tx_ring,
5120 int cpu)
5121{
5122 struct e1000_hw *hw = &adapter->hw;
5123 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5124
5125 if (hw->mac.type != e1000_82575)
5126 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5127
b980ac18 5128 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5129 * DCA is enabled. This is due to a known issue in some chipsets
5130 * which will cause the DCA tag to be cleared.
5131 */
5132 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5133 E1000_DCA_TXCTRL_DATA_RRO_EN |
5134 E1000_DCA_TXCTRL_DESC_DCA_EN;
5135
5136 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5137}
5138
5139static void igb_update_rx_dca(struct igb_adapter *adapter,
5140 struct igb_ring *rx_ring,
5141 int cpu)
5142{
5143 struct e1000_hw *hw = &adapter->hw;
5144 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5145
5146 if (hw->mac.type != e1000_82575)
5147 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5148
b980ac18 5149 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5150 * DCA is enabled. This is due to a known issue in some chipsets
5151 * which will cause the DCA tag to be cleared.
5152 */
5153 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5154 E1000_DCA_RXCTRL_DESC_DCA_EN;
5155
5156 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5157}
5158
047e0030 5159static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5160{
047e0030 5161 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5162 int cpu = get_cpu();
fe4506b6 5163
047e0030
AD		 5164 if (q_vector->cpu == cpu)
5165 goto out_no_update;
5166
6a05004a
AD		 5167 if (q_vector->tx.ring)
5168 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5169
5170 if (q_vector->rx.ring)
5171 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5172
047e0030
AD		 5173 q_vector->cpu = cpu;
5174out_no_update:
fe4506b6
JC		 5175 put_cpu();
5176}
5177
5178static void igb_setup_dca(struct igb_adapter *adapter)
5179{
7e0e99ef 5180 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5181 int i;
5182
7dfc16fa 5183 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5184 return;
5185
7e0e99ef
AD		 5186 /* Always use CB2 mode, difference is masked in the CB driver. */
5187 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5188
047e0030 5189 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5190 adapter->q_vector[i]->cpu = -1;
5191 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5192 }
5193}
5194
5195static int __igb_notify_dca(struct device *dev, void *data)
5196{
5197 struct net_device *netdev = dev_get_drvdata(dev);
5198 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5199 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5200 struct e1000_hw *hw = &adapter->hw;
5201 unsigned long event = *(unsigned long *)data;
5202
5203 switch (event) {
5204 case DCA_PROVIDER_ADD:
5205 /* if already enabled, don't do it again */
7dfc16fa 5206 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5207 break;
fe4506b6 5208 if (dca_add_requester(dev) == 0) {
bbd98fe4 5209 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5210 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5211 igb_setup_dca(adapter);
5212 break;
5213 }
5214 /* Fall Through since DCA is disabled. */
5215 case DCA_PROVIDER_REMOVE:
7dfc16fa 5216 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5217 /* without this a class_device is left
b980ac18
JK		 5218 * hanging around in the sysfs model
5219 */
fe4506b6 5220 dca_remove_requester(dev);
090b1795 5221 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5222 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5223 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5224 }
5225 break;
5226 }
bbd98fe4 5227
fe4506b6 5228 return 0;
9d5c8243
AK		 5229}
5230
fe4506b6 5231static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5232 void *p)
fe4506b6
JC		 5233{
5234 int ret_val;
5235
5236 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5237 __igb_notify_dca);
fe4506b6
JC		 5238
5239 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5240}
421e02f0 5241#endif /* CONFIG_IGB_DCA */
9d5c8243 5242
0224d663
GR		 5243#ifdef CONFIG_PCI_IOV
5244static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5245{
5246 unsigned char mac_addr[ETH_ALEN];
0224d663 5247
5ac6f91d 5248 eth_zero_addr(mac_addr);
0224d663
GR		 5249 igb_set_vf_mac(adapter, vf, mac_addr);
5250
70ea4783
LL		 5251 /* By default spoof check is enabled for all VFs */
5252 adapter->vf_data[vf].spoofchk_enabled = true;
5253
f557147c 5254 return 0;
0224d663
GR		 5255}
5256
0224d663 5257#endif
4ae196df
AD		 5258static void igb_ping_all_vfs(struct igb_adapter *adapter)
5259{
5260 struct e1000_hw *hw = &adapter->hw;
5261 u32 ping;
5262 int i;
5263
5264 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5265 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5266 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5267 ping |= E1000_VT_MSGTYPE_CTS;
5268 igb_write_mbx(hw, &ping, 1, i);
5269 }
5270}
5271
7d5753f0
AD		 5272static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5273{
5274 struct e1000_hw *hw = &adapter->hw;
5275 u32 vmolr = rd32(E1000_VMOLR(vf));
5276 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5277
d85b9004 5278 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5279 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5280 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5281
5282 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5283 vmolr |= E1000_VMOLR_MPME;
d85b9004 5284 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5285 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5286 } else {
b980ac18 5287 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5288 * flag we need to write the hashes to the MTA as this step
5289 * was previously skipped
5290 */
5291 if (vf_data->num_vf_mc_hashes > 30) {
5292 vmolr |= E1000_VMOLR_MPME;
5293 } else if (vf_data->num_vf_mc_hashes) {
5294 int j;
5295 vmolr |= E1000_VMOLR_ROMPE;
5296 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5297 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5298 }
5299 }
5300
5301 wr32(E1000_VMOLR(vf), vmolr);
5302
5303 /* there are flags left unprocessed, likely not supported */
5304 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5305 return -EINVAL;
5306
5307 return 0;
7d5753f0
AD		 5308}
5309
4ae196df
AD		 5310static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5311 u32 *msgbuf, u32 vf)
5312{
5313 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5314 u16 *hash_list = (u16 *)&msgbuf[1];
5315 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5316 int i;
5317
7d5753f0 5318 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5319 * to this VF for later use to restore when the PF multi cast
5320 * list changes
5321 */
5322 vf_data->num_vf_mc_hashes = n;
5323
7d5753f0
AD		 5324 /* only up to 30 hash values supported */
5325 if (n > 30)
5326 n = 30;
5327
5328 /* store the hashes for later use */
4ae196df 5329 for (i = 0; i < n; i++)
a419aef8 5330 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5331
5332 /* Flush and reset the mta with the new values */
ff41f8dc 5333 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5334
5335 return 0;
5336}
5337
5338static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5339{
5340 struct e1000_hw *hw = &adapter->hw;
5341 struct vf_data_storage *vf_data;
5342 int i, j;
5343
5344 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5345 u32 vmolr = rd32(E1000_VMOLR(i));
5346 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5347
4ae196df 5348 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5349
5350 if ((vf_data->num_vf_mc_hashes > 30) ||
5351 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5352 vmolr |= E1000_VMOLR_MPME;
5353 } else if (vf_data->num_vf_mc_hashes) {
5354 vmolr |= E1000_VMOLR_ROMPE;
5355 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5356 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5357 }
5358 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5359 }
5360}
5361
5362static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5363{
5364 struct e1000_hw *hw = &adapter->hw;
5365 u32 pool_mask, reg, vid;
5366 int i;
5367
5368 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5369
5370 /* Find the vlan filter for this id */
5371 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5372 reg = rd32(E1000_VLVF(i));
5373
5374 /* remove the vf from the pool */
5375 reg &= ~pool_mask;
5376
5377 /* if pool is empty then remove entry from vfta */
5378 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5379 (reg & E1000_VLVF_VLANID_ENABLE)) {
5380 reg = 0;
5381 vid = reg & E1000_VLVF_VLANID_MASK;
5382 igb_vfta_set(hw, vid, false);
5383 }
5384
5385 wr32(E1000_VLVF(i), reg);
5386 }
ae641bdc
AD		 5387
5388 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5389}
5390
5391static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5392{
5393 struct e1000_hw *hw = &adapter->hw;
5394 u32 reg, i;
5395
51466239
AD		 5396 /* The vlvf table only exists on 82576 hardware and newer */
5397 if (hw->mac.type < e1000_82576)
5398 return -1;
5399
5400 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5401 if (!adapter->vfs_allocated_count)
5402 return -1;
5403
5404 /* Find the vlan filter for this id */
5405 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5406 reg = rd32(E1000_VLVF(i));
5407 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5408 vid == (reg & E1000_VLVF_VLANID_MASK))
5409 break;
5410 }
5411
5412 if (add) {
5413 if (i == E1000_VLVF_ARRAY_SIZE) {
5414 /* Did not find a matching VLAN ID entry that was
5415 * enabled. Search for a free filter entry, i.e.
5416 * one without the enable bit set
5417 */
5418 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5419 reg = rd32(E1000_VLVF(i));
5420 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5421 break;
5422 }
5423 }
5424 if (i < E1000_VLVF_ARRAY_SIZE) {
5425 /* Found an enabled/available entry */
5426 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5427
5428 /* if !enabled we need to set this up in vfta */
5429 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5430 /* add VID to filter table */
5431 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5432 reg |= E1000_VLVF_VLANID_ENABLE;
5433 }
cad6d05f
AD		 5434 reg &= ~E1000_VLVF_VLANID_MASK;
5435 reg |= vid;
4ae196df 5436 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5437
5438 /* do not modify RLPML for PF devices */
5439 if (vf >= adapter->vfs_allocated_count)
5440 return 0;
5441
5442 if (!adapter->vf_data[vf].vlans_enabled) {
5443 u32 size;
5444 reg = rd32(E1000_VMOLR(vf));
5445 size = reg & E1000_VMOLR_RLPML_MASK;
5446 size += 4;
5447 reg &= ~E1000_VMOLR_RLPML_MASK;
5448 reg |= size;
5449 wr32(E1000_VMOLR(vf), reg);
5450 }
ae641bdc 5451
51466239 5452 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5453 }
5454 } else {
5455 if (i < E1000_VLVF_ARRAY_SIZE) {
5456 /* remove vf from the pool */
5457 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5458 /* if pool is empty then remove entry from vfta */
5459 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5460 reg = 0;
5461 igb_vfta_set(hw, vid, false);
5462 }
5463 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5464
5465 /* do not modify RLPML for PF devices */
5466 if (vf >= adapter->vfs_allocated_count)
5467 return 0;
5468
5469 adapter->vf_data[vf].vlans_enabled--;
5470 if (!adapter->vf_data[vf].vlans_enabled) {
5471 u32 size;
5472 reg = rd32(E1000_VMOLR(vf));
5473 size = reg & E1000_VMOLR_RLPML_MASK;
5474 size -= 4;
5475 reg &= ~E1000_VMOLR_RLPML_MASK;
5476 reg |= size;
5477 wr32(E1000_VMOLR(vf), reg);
5478 }
4ae196df
AD		 5479 }
5480 }
8151d294
WM		 5481 return 0;
5482}
5483
5484static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5485{
5486 struct e1000_hw *hw = &adapter->hw;
5487
5488 if (vid)
5489 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5490 else
5491 wr32(E1000_VMVIR(vf), 0);
5492}
5493
5494static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5495 int vf, u16 vlan, u8 qos)
5496{
5497 int err = 0;
5498 struct igb_adapter *adapter = netdev_priv(netdev);
5499
5500 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5501 return -EINVAL;
5502 if (vlan || qos) {
5503 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5504 if (err)
5505 goto out;
5506 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5507 igb_set_vmolr(adapter, vf, !vlan);
5508 adapter->vf_data[vf].pf_vlan = vlan;
5509 adapter->vf_data[vf].pf_qos = qos;
5510 dev_info(&adapter->pdev->dev,
5511 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5512 if (test_bit(__IGB_DOWN, &adapter->state)) {
5513 dev_warn(&adapter->pdev->dev,
b980ac18 5514 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5515 dev_warn(&adapter->pdev->dev,
b980ac18 5516 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5517 }
5518 } else {
5519 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5520 false, vf);
8151d294
WM		 5521 igb_set_vmvir(adapter, vlan, vf);
5522 igb_set_vmolr(adapter, vf, true);
5523 adapter->vf_data[vf].pf_vlan = 0;
5524 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5525 }
8151d294 5526out:
b980ac18 5527 return err;
4ae196df
AD		 5528}
5529
6f3dc319
GR		 5530static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5531{
5532 struct e1000_hw *hw = &adapter->hw;
5533 int i;
5534 u32 reg;
5535
5536 /* Find the vlan filter for this id */
5537 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5538 reg = rd32(E1000_VLVF(i));
5539 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5540 vid == (reg & E1000_VLVF_VLANID_MASK))
5541 break;
5542 }
5543
5544 if (i >= E1000_VLVF_ARRAY_SIZE)
5545 i = -1;
5546
5547 return i;
5548}
5549
4ae196df
AD		 5550static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5551{
6f3dc319 5552 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5553 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5554 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5555 int err = 0;
4ae196df 5556
6f3dc319
GR		 5557 /* If in promiscuous mode we need to make sure the PF also has
5558 * the VLAN filter set.
5559 */
5560 if (add && (adapter->netdev->flags & IFF_PROMISC))
5561 err = igb_vlvf_set(adapter, vid, add,
5562 adapter->vfs_allocated_count);
5563 if (err)
5564 goto out;
5565
5566 err = igb_vlvf_set(adapter, vid, add, vf);
5567
5568 if (err)
5569 goto out;
5570
5571 /* Go through all the checks to see if the VLAN filter should
5572 * be wiped completely.
5573 */
5574 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5575 u32 vlvf, bits;
5576
5577 int regndx = igb_find_vlvf_entry(adapter, vid);
5578 if (regndx < 0)
5579 goto out;
5580 /* See if any other pools are set for this VLAN filter
5581 * entry other than the PF.
5582 */
5583 vlvf = bits = rd32(E1000_VLVF(regndx));
5584 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5585 adapter->vfs_allocated_count);
5586 /* If the filter was removed then ensure PF pool bit
5587 * is cleared if the PF only added itself to the pool
5588 * because the PF is in promiscuous mode.
5589 */
5590 if ((vlvf & VLAN_VID_MASK) == vid &&
5591 !test_bit(vid, adapter->active_vlans) &&
5592 !bits)
5593 igb_vlvf_set(adapter, vid, add,
5594 adapter->vfs_allocated_count);
5595 }
5596
5597out:
5598 return err;
4ae196df
AD		 5599}
5600
f2ca0dbe 5601static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5602{
8fa7e0f7
GR		 5603 /* clear flags - except flag that indicates PF has set the MAC */
5604 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5605 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5606
5607 /* reset offloads to defaults */
8151d294 5608 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5609
5610 /* reset vlans for device */
5611 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5612 if (adapter->vf_data[vf].pf_vlan)
5613 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5614 adapter->vf_data[vf].pf_vlan,
5615 adapter->vf_data[vf].pf_qos);
5616 else
5617 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5618
5619 /* reset multicast table array for vf */
5620 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5621
5622 /* Flush and reset the mta with the new values */
ff41f8dc 5623 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5624}
5625
f2ca0dbe
AD		 5626static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5627{
5628 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5629
5ac6f91d 5630 /* clear mac address as we were hotplug removed/added */
8151d294 5631 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5632 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5633
5634 /* process remaining reset events */
5635 igb_vf_reset(adapter, vf);
5636}
5637
5638static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5639{
5640 struct e1000_hw *hw = &adapter->hw;
5641 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5642 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5643 u32 reg, msgbuf[3];
5644 u8 *addr = (u8 *)(&msgbuf[1]);
5645
5646 /* process all the same items cleared in a function level reset */
f2ca0dbe 5647 igb_vf_reset(adapter, vf);
4ae196df
AD		 5648
5649 /* set vf mac address */
26ad9178 5650 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5651
5652 /* enable transmit and receive for vf */
5653 reg = rd32(E1000_VFTE);
5654 wr32(E1000_VFTE, reg | (1 << vf));
5655 reg = rd32(E1000_VFRE);
5656 wr32(E1000_VFRE, reg | (1 << vf));
5657
8fa7e0f7 5658 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5659
5660 /* reply to reset with ack and vf mac address */
5661 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5662 memcpy(addr, vf_mac, 6);
5663 igb_write_mbx(hw, msgbuf, 3, vf);
5664}
5665
5666static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5667{
b980ac18 5668 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5669 * starting at the second 32 bit word of the msg array
5670 */
f2ca0dbe
AD		 5671 unsigned char *addr = (char *)&msg[1];
5672 int err = -1;
4ae196df 5673
f2ca0dbe
AD		 5674 if (is_valid_ether_addr(addr))
5675 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5676
f2ca0dbe 5677 return err;
4ae196df
AD		 5678}
5679
5680static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5681{
5682 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5683 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5684 u32 msg = E1000_VT_MSGTYPE_NACK;
5685
5686 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5687 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5688 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5689 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5690 vf_data->last_nack = jiffies;
4ae196df
AD		 5691 }
5692}
5693
f2ca0dbe 5694static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5695{
f2ca0dbe
AD		 5696 struct pci_dev *pdev = adapter->pdev;
5697 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5698 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5699 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5700 s32 retval;
5701
f2ca0dbe 5702 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5703
fef45f4c
AD		 5704 if (retval) {
5705 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5706 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5707 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5708 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5709 return;
5710 goto out;
5711 }
4ae196df
AD		 5712
5713 /* this is a message we already processed, do nothing */
5714 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5715 return;
4ae196df 5716
b980ac18 5717 /* until the vf completes a reset it should not be
4ae196df
AD		 5718 * allowed to start any configuration.
5719 */
4ae196df
AD		 5720 if (msgbuf[0] == E1000_VF_RESET) {
5721 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5722 return;
4ae196df
AD		 5723 }
5724
f2ca0dbe 5725 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5726 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5727 return;
5728 retval = -1;
5729 goto out;
4ae196df
AD		 5730 }
5731
5732 switch ((msgbuf[0] & 0xFFFF)) {
5733 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5734 retval = -EINVAL;
5735 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5736 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5737 else
5738 dev_warn(&pdev->dev,
b980ac18
JK		 5739 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5740 vf);
4ae196df 5741 break;
7d5753f0
AD		 5742 case E1000_VF_SET_PROMISC:
5743 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5744 break;
4ae196df
AD		 5745 case E1000_VF_SET_MULTICAST:
5746 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5747 break;
5748 case E1000_VF_SET_LPE:
5749 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5750 break;
5751 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5752 retval = -1;
5753 if (vf_data->pf_vlan)
5754 dev_warn(&pdev->dev,
b980ac18
JK		 5755 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5756 vf);
8151d294
WM		 5757 else
5758 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5759 break;
5760 default:
090b1795 5761 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5762 retval = -1;
5763 break;
5764 }
5765
fef45f4c
AD		 5766 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5767out:
4ae196df
AD		 5768 /* notify the VF of the results of what it sent us */
5769 if (retval)
5770 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5771 else
5772 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5773
4ae196df 5774 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5775}
4ae196df 5776
f2ca0dbe
AD		 5777static void igb_msg_task(struct igb_adapter *adapter)
5778{
5779 struct e1000_hw *hw = &adapter->hw;
5780 u32 vf;
5781
5782 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5783 /* process any reset requests */
5784 if (!igb_check_for_rst(hw, vf))
5785 igb_vf_reset_event(adapter, vf);
5786
5787 /* process any messages pending */
5788 if (!igb_check_for_msg(hw, vf))
5789 igb_rcv_msg_from_vf(adapter, vf);
5790
5791 /* process any acks */
5792 if (!igb_check_for_ack(hw, vf))
5793 igb_rcv_ack_from_vf(adapter, vf);
5794 }
4ae196df
AD		 5795}
5796
68d480c4
AD		 5797/**
5798 * igb_set_uta - Set unicast filter table address
5799 * @adapter: board private structure
5800 *
5801 * The unicast table address is a register array of 32-bit registers.
5802 * The table is meant to be used in a way similar to how the MTA is used
5803 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5804 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5805 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5806 **/
5807static void igb_set_uta(struct igb_adapter *adapter)
5808{
5809 struct e1000_hw *hw = &adapter->hw;
5810 int i;
5811
5812 /* The UTA table only exists on 82576 hardware and newer */
5813 if (hw->mac.type < e1000_82576)
5814 return;
5815
5816 /* we only need to do this if VMDq is enabled */
5817 if (!adapter->vfs_allocated_count)
5818 return;
5819
5820 for (i = 0; i < hw->mac.uta_reg_count; i++)
5821 array_wr32(E1000_UTA, i, ~0);
5822}
5823
9d5c8243 5824/**
b980ac18
JK		 5825 * igb_intr_msi - Interrupt Handler
5826 * @irq: interrupt number
5827 * @data: pointer to a network interface device structure
9d5c8243
AK		 5828 **/
5829static irqreturn_t igb_intr_msi(int irq, void *data)
5830{
047e0030
AD		 5831 struct igb_adapter *adapter = data;
5832 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5833 struct e1000_hw *hw = &adapter->hw;
5834 /* read ICR disables interrupts using IAM */
5835 u32 icr = rd32(E1000_ICR);
5836
047e0030 5837 igb_write_itr(q_vector);
9d5c8243 5838
7f081d40
AD		 5839 if (icr & E1000_ICR_DRSTA)
5840 schedule_work(&adapter->reset_task);
5841
047e0030 5842 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5843 /* HW is reporting DMA is out of sync */
5844 adapter->stats.doosync++;
5845 }
5846
9d5c8243
AK		 5847 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5848 hw->mac.get_link_status = 1;
5849 if (!test_bit(__IGB_DOWN, &adapter->state))
5850 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5851 }
5852
1f6e8178
MV		 5853 if (icr & E1000_ICR_TS) {
5854 u32 tsicr = rd32(E1000_TSICR);
5855
5856 if (tsicr & E1000_TSICR_TXTS) {
5857 /* acknowledge the interrupt */
5858 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5859 /* retrieve hardware timestamp */
5860 schedule_work(&adapter->ptp_tx_work);
5861 }
5862 }
1f6e8178 5863
047e0030 5864 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5865
5866 return IRQ_HANDLED;
5867}
5868
5869/**
b980ac18
JK		 5870 * igb_intr - Legacy Interrupt Handler
5871 * @irq: interrupt number
5872 * @data: pointer to a network interface device structure
9d5c8243
AK		 5873 **/
5874static irqreturn_t igb_intr(int irq, void *data)
5875{
047e0030
AD		 5876 struct igb_adapter *adapter = data;
5877 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5878 struct e1000_hw *hw = &adapter->hw;
5879 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5880 * need for the IMC write
5881 */
9d5c8243 5882 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5883
5884 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5885 * not set, then the adapter didn't send an interrupt
5886 */
9d5c8243
AK		 5887 if (!(icr & E1000_ICR_INT_ASSERTED))
5888 return IRQ_NONE;
5889
0ba82994
AD		 5890 igb_write_itr(q_vector);
5891
7f081d40
AD		 5892 if (icr & E1000_ICR_DRSTA)
5893 schedule_work(&adapter->reset_task);
5894
047e0030 5895 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5896 /* HW is reporting DMA is out of sync */
5897 adapter->stats.doosync++;
5898 }
5899
9d5c8243
AK		 5900 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5901 hw->mac.get_link_status = 1;
5902 /* guard against interrupt when we're going down */
5903 if (!test_bit(__IGB_DOWN, &adapter->state))
5904 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5905 }
5906
1f6e8178
MV		 5907 if (icr & E1000_ICR_TS) {
5908 u32 tsicr = rd32(E1000_TSICR);
5909
5910 if (tsicr & E1000_TSICR_TXTS) {
5911 /* acknowledge the interrupt */
5912 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5913 /* retrieve hardware timestamp */
5914 schedule_work(&adapter->ptp_tx_work);
5915 }
5916 }
1f6e8178 5917
047e0030 5918 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5919
5920 return IRQ_HANDLED;
5921}
5922
c50b52a0 5923static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5924{
047e0030 5925 struct igb_adapter *adapter = q_vector->adapter;
46544258 5926 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5927
0ba82994
AD		 5928 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5929 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5930 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5931 igb_set_itr(q_vector);
46544258 5932 else
047e0030 5933 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5934 }
5935
46544258
AD		 5936 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5937 if (adapter->msix_entries)
047e0030 5938 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5939 else
5940 igb_irq_enable(adapter);
5941 }
9d5c8243
AK		 5942}
5943
46544258 5944/**
b980ac18
JK		 5945 * igb_poll - NAPI Rx polling callback
5946 * @napi: napi polling structure
5947 * @budget: count of how many packets we should handle
46544258
AD		 5948 **/
5949static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5950{
047e0030 5951 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 5952 struct igb_q_vector,
5953 napi);
16eb8815 5954 bool clean_complete = true;
9d5c8243 5955
421e02f0 5956#ifdef CONFIG_IGB_DCA
047e0030
AD		 5957 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5958 igb_update_dca(q_vector);
fe4506b6 5959#endif
0ba82994 5960 if (q_vector->tx.ring)
13fde97a 5961 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5962
0ba82994 5963 if (q_vector->rx.ring)
cd392f5c 5964 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5965
16eb8815
AD		 5966 /* If all work not completed, return budget and keep polling */
5967 if (!clean_complete)
5968 return budget;
46544258 5969
9d5c8243 5970 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5971 napi_complete(napi);
5972 igb_ring_irq_enable(q_vector);
9d5c8243 5973
16eb8815 5974 return 0;
9d5c8243 5975}
6d8126f9 5976
9d5c8243 5977/**
b980ac18
JK		 5978 * igb_clean_tx_irq - Reclaim resources after transmit completes
5979 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5980 *
b980ac18 5981 * returns true if ring is completely cleaned
9d5c8243 5982 **/
047e0030 5983static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5984{
047e0030 5985 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5986 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5987 struct igb_tx_buffer *tx_buffer;
f4128785 5988 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5989 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5990 unsigned int budget = q_vector->tx.work_limit;
8542db05 5991 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5992
13fde97a
AD		 5993 if (test_bit(__IGB_DOWN, &adapter->state))
5994 return true;
0e014cb1 5995
06034649 5996 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5997 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5998 i -= tx_ring->count;
9d5c8243 5999
f4128785
AD		 6000 do {
6001 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6002
6003 /* if next_to_watch is not set then there is no work pending */
6004 if (!eop_desc)
6005 break;
13fde97a 6006
f4128785 6007 /* prevent any other reads prior to eop_desc */
70d289bc 6008 read_barrier_depends();
f4128785 6009
13fde97a
AD		 6010 /* if DD is not set pending work has not been completed */
6011 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6012 break;
6013
8542db05
AD		 6014 /* clear next_to_watch to prevent false hangs */
6015 tx_buffer->next_to_watch = NULL;
9d5c8243 6016
ebe42d16
AD		 6017 /* update the statistics for this packet */
6018 total_bytes += tx_buffer->bytecount;
6019 total_packets += tx_buffer->gso_segs;
13fde97a 6020
ebe42d16
AD		 6021 /* free the skb */
6022 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6023
ebe42d16
AD		 6024 /* unmap skb header data */
6025 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6026 dma_unmap_addr(tx_buffer, dma),
6027 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6028 DMA_TO_DEVICE);
6029
c9f14bf3
AD		 6030 /* clear tx_buffer data */
6031 tx_buffer->skb = NULL;
6032 dma_unmap_len_set(tx_buffer, len, 0);
6033
ebe42d16
AD		 6034 /* clear last DMA location and unmap remaining buffers */
6035 while (tx_desc != eop_desc) {
13fde97a
AD		 6036 tx_buffer++;
6037 tx_desc++;
9d5c8243 6038 i++;
8542db05
AD		 6039 if (unlikely(!i)) {
6040 i -= tx_ring->count;
06034649 6041 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6042 tx_desc = IGB_TX_DESC(tx_ring, 0);
6043 }
ebe42d16
AD		 6044
6045 /* unmap any remaining paged data */
c9f14bf3 6046 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6047 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6048 dma_unmap_addr(tx_buffer, dma),
6049 dma_unmap_len(tx_buffer, len),
ebe42d16 6050 DMA_TO_DEVICE);
c9f14bf3 6051 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6052 }
6053 }
6054
ebe42d16
AD		 6055 /* move us one more past the eop_desc for start of next pkt */
6056 tx_buffer++;
6057 tx_desc++;
6058 i++;
6059 if (unlikely(!i)) {
6060 i -= tx_ring->count;
6061 tx_buffer = tx_ring->tx_buffer_info;
6062 tx_desc = IGB_TX_DESC(tx_ring, 0);
6063 }
f4128785
AD		 6064
6065 /* issue prefetch for next Tx descriptor */
6066 prefetch(tx_desc);
6067
6068 /* update budget accounting */
6069 budget--;
6070 } while (likely(budget));
0e014cb1 6071
bdbc0631
ED		 6072 netdev_tx_completed_queue(txring_txq(tx_ring),
6073 total_packets, total_bytes);
8542db05 6074 i += tx_ring->count;
9d5c8243 6075 tx_ring->next_to_clean = i;
13fde97a
AD		 6076 u64_stats_update_begin(&tx_ring->tx_syncp);
6077 tx_ring->tx_stats.bytes += total_bytes;
6078 tx_ring->tx_stats.packets += total_packets;
6079 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6080 q_vector->tx.total_bytes += total_bytes;
6081 q_vector->tx.total_packets += total_packets;
9d5c8243 6082
6d095fa8 6083 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6084 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6085
9d5c8243 6086 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6087 * check with the clearing of time_stamp and movement of i
6088 */
6d095fa8 6089 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6090 if (tx_buffer->next_to_watch &&
8542db05 6091 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6092 (adapter->tx_timeout_factor * HZ)) &&
6093 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6094
9d5c8243 6095 /* detected Tx unit hang */
59d71989 6096 dev_err(tx_ring->dev,
9d5c8243 6097 "Detected Tx Unit Hang\n"
2d064c06 6098 " Tx Queue <%d>\n"
9d5c8243
AK		 6099 " TDH <%x>\n"
6100 " TDT <%x>\n"
6101 " next_to_use <%x>\n"
6102 " next_to_clean <%x>\n"
9d5c8243
AK		 6103 "buffer_info[next_to_clean]\n"
6104 " time_stamp <%lx>\n"
8542db05 6105 " next_to_watch <%p>\n"
9d5c8243
AK		 6106 " jiffies <%lx>\n"
6107 " desc.status <%x>\n",
2d064c06 6108 tx_ring->queue_index,
238ac817 6109 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6110 readl(tx_ring->tail),
9d5c8243
AK		 6111 tx_ring->next_to_use,
6112 tx_ring->next_to_clean,
8542db05 6113 tx_buffer->time_stamp,
f4128785 6114 tx_buffer->next_to_watch,
9d5c8243 6115 jiffies,
f4128785 6116 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6117 netif_stop_subqueue(tx_ring->netdev,
6118 tx_ring->queue_index);
6119
6120 /* we are about to reset, no point in enabling stuff */
6121 return true;
9d5c8243
AK		 6122 }
6123 }
13fde97a 6124
21ba6fe1 6125#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6126 if (unlikely(total_packets &&
b980ac18
JK		 6127 netif_carrier_ok(tx_ring->netdev) &&
6128 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6129 /* Make sure that anybody stopping the queue after this
6130 * sees the new next_to_clean.
6131 */
6132 smp_mb();
6133 if (__netif_subqueue_stopped(tx_ring->netdev,
6134 tx_ring->queue_index) &&
6135 !(test_bit(__IGB_DOWN, &adapter->state))) {
6136 netif_wake_subqueue(tx_ring->netdev,
6137 tx_ring->queue_index);
6138
6139 u64_stats_update_begin(&tx_ring->tx_syncp);
6140 tx_ring->tx_stats.restart_queue++;
6141 u64_stats_update_end(&tx_ring->tx_syncp);
6142 }
6143 }
6144
6145 return !!budget;
9d5c8243
AK		 6146}
6147
cbc8e55f 6148/**
b980ac18
JK		 6149 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6150 * @rx_ring: rx descriptor ring to store buffers on
6151 * @old_buff: donor buffer to have page reused
cbc8e55f 6152 *
b980ac18 6153 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6154 **/
6155static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6156 struct igb_rx_buffer *old_buff)
6157{
6158 struct igb_rx_buffer *new_buff;
6159 u16 nta = rx_ring->next_to_alloc;
6160
6161 new_buff = &rx_ring->rx_buffer_info[nta];
6162
6163 /* update, and store next to alloc */
6164 nta++;
6165 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6166
6167 /* transfer page from old buffer to new buffer */
6168 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6169
6170 /* sync the buffer for use by the device */
6171 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6172 old_buff->page_offset,
de78d1f9 6173 IGB_RX_BUFSZ,
cbc8e55f
AD		 6174 DMA_FROM_DEVICE);
6175}
6176
74e238ea
AD		 6177static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6178 struct page *page,
6179 unsigned int truesize)
6180{
6181 /* avoid re-using remote pages */
6182 if (unlikely(page_to_nid(page) != numa_node_id()))
6183 return false;
6184
6185#if (PAGE_SIZE < 8192)
6186 /* if we are only owner of page we can reuse it */
6187 if (unlikely(page_count(page) != 1))
6188 return false;
6189
6190 /* flip page offset to other buffer */
6191 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6192
6193 /* since we are the only owner of the page and we need to
6194 * increment it, just set the value to 2 in order to avoid
6195 * an unnecessary locked operation
6196 */
6197 atomic_set(&page->_count, 2);
6198#else
6199 /* move offset up to the next cache line */
6200 rx_buffer->page_offset += truesize;
6201
6202 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6203 return false;
6204
6205 /* bump ref count on page before it is given to the stack */
6206 get_page(page);
6207#endif
6208
6209 return true;
6210}
6211
cbc8e55f 6212/**
b980ac18
JK		 6213 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6214 * @rx_ring: rx descriptor ring to transact packets on
6215 * @rx_buffer: buffer containing page to add
6216 * @rx_desc: descriptor containing length of buffer written by hardware
6217 * @skb: sk_buff to place the data into
cbc8e55f 6218 *
b980ac18
JK		 6219 * This function will add the data contained in rx_buffer->page to the skb.
6220 * This is done either through a direct copy if the data in the buffer is
6221 * less than the skb header size, otherwise it will just attach the page as
6222 * a frag to the skb.
cbc8e55f 6223 *
b980ac18
JK		 6224 * The function will then update the page offset if necessary and return
6225 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6226 **/
6227static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6228 struct igb_rx_buffer *rx_buffer,
6229 union e1000_adv_rx_desc *rx_desc,
6230 struct sk_buff *skb)
6231{
6232 struct page *page = rx_buffer->page;
6233 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6234#if (PAGE_SIZE < 8192)
6235 unsigned int truesize = IGB_RX_BUFSZ;
6236#else
6237 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6238#endif
cbc8e55f
AD		 6239
6240 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6241 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6242
cbc8e55f
AD		 6243 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6244 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6245 va += IGB_TS_HDR_LEN;
6246 size -= IGB_TS_HDR_LEN;
6247 }
6248
cbc8e55f
AD		 6249 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6250
6251 /* we can reuse buffer as-is, just make sure it is local */
6252 if (likely(page_to_nid(page) == numa_node_id()))
6253 return true;
6254
6255 /* this page cannot be reused so discard it */
6256 put_page(page);
6257 return false;
6258 }
6259
6260 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6261 rx_buffer->page_offset, size, truesize);
cbc8e55f 6262
74e238ea
AD		 6263 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6264}
cbc8e55f 6265
2e334eee
AD		 6266static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6267 union e1000_adv_rx_desc *rx_desc,
6268 struct sk_buff *skb)
6269{
6270 struct igb_rx_buffer *rx_buffer;
6271 struct page *page;
6272
6273 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6274
2e334eee
AD		 6275 page = rx_buffer->page;
6276 prefetchw(page);
6277
6278 if (likely(!skb)) {
6279 void *page_addr = page_address(page) +
6280 rx_buffer->page_offset;
6281
6282 /* prefetch first cache line of first page */
6283 prefetch(page_addr);
6284#if L1_CACHE_BYTES < 128
6285 prefetch(page_addr + L1_CACHE_BYTES);
6286#endif
6287
6288 /* allocate a skb to store the frags */
6289 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6290 IGB_RX_HDR_LEN);
6291 if (unlikely(!skb)) {
6292 rx_ring->rx_stats.alloc_failed++;
6293 return NULL;
6294 }
6295
b980ac18 6296 /* we will be copying header into skb->data in
2e334eee
AD		 6297 * pskb_may_pull so it is in our interest to prefetch
6298 * it now to avoid a possible cache miss
6299 */
6300 prefetchw(skb->data);
6301 }
6302
6303 /* we are reusing so sync this buffer for CPU use */
6304 dma_sync_single_range_for_cpu(rx_ring->dev,
6305 rx_buffer->dma,
6306 rx_buffer->page_offset,
de78d1f9 6307 IGB_RX_BUFSZ,
2e334eee
AD		 6308 DMA_FROM_DEVICE);
6309
6310 /* pull page into skb */
6311 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6312 /* hand second half of page back to the ring */
6313 igb_reuse_rx_page(rx_ring, rx_buffer);
6314 } else {
6315 /* we are not reusing the buffer so unmap it */
6316 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6317 PAGE_SIZE, DMA_FROM_DEVICE);
6318 }
6319
6320 /* clear contents of rx_buffer */
6321 rx_buffer->page = NULL;
6322
6323 return skb;
6324}
6325
cd392f5c 6326static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6327 union e1000_adv_rx_desc *rx_desc,
6328 struct sk_buff *skb)
9d5c8243 6329{
bc8acf2c 6330 skb_checksum_none_assert(skb);
9d5c8243 6331
294e7d78 6332 /* Ignore Checksum bit is set */
3ceb90fd 6333 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6334 return;
6335
6336 /* Rx checksum disabled via ethtool */
6337 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6338 return;
85ad76b2 6339
9d5c8243 6340 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6341 if (igb_test_staterr(rx_desc,
6342 E1000_RXDEXT_STATERR_TCPE |
6343 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6344 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6345 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6346 * packets, (aka let the stack check the crc32c)
6347 */
866cff06
AD		 6348 if (!((skb->len == 60) &&
6349 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6350 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6351 ring->rx_stats.csum_err++;
12dcd86b
ED		 6352 u64_stats_update_end(&ring->rx_syncp);
6353 }
9d5c8243 6354 /* let the stack verify checksum errors */
9d5c8243
AK		 6355 return;
6356 }
6357 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6358 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6359 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6360 skb->ip_summed = CHECKSUM_UNNECESSARY;
6361
3ceb90fd
AD		 6362 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6363 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6364}
6365
077887c3
AD		 6366static inline void igb_rx_hash(struct igb_ring *ring,
6367 union e1000_adv_rx_desc *rx_desc,
6368 struct sk_buff *skb)
6369{
6370 if (ring->netdev->features & NETIF_F_RXHASH)
6371 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6372}
6373
2e334eee 6374/**
b980ac18
JK		 6375 * igb_is_non_eop - process handling of non-EOP buffers
6376 * @rx_ring: Rx ring being processed
6377 * @rx_desc: Rx descriptor for current buffer
6378 * @skb: current socket buffer containing buffer in progress
2e334eee 6379 *
b980ac18
JK		 6380 * This function updates next to clean. If the buffer is an EOP buffer
6381 * this function exits returning false, otherwise it will place the
6382 * sk_buff in the next buffer to be chained and return true indicating
6383 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6384 **/
6385static bool igb_is_non_eop(struct igb_ring *rx_ring,
6386 union e1000_adv_rx_desc *rx_desc)
6387{
6388 u32 ntc = rx_ring->next_to_clean + 1;
6389
6390 /* fetch, update, and store next to clean */
6391 ntc = (ntc < rx_ring->count) ? ntc : 0;
6392 rx_ring->next_to_clean = ntc;
6393
6394 prefetch(IGB_RX_DESC(rx_ring, ntc));
6395
6396 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6397 return false;
6398
6399 return true;
6400}
6401
1a1c225b 6402/**
b980ac18
JK		 6403 * igb_get_headlen - determine size of header for LRO/GRO
6404 * @data: pointer to the start of the headers
6405 * @max_len: total length of section to find headers in
1a1c225b 6406 *
b980ac18
JK		 6407 * This function is meant to determine the length of headers that will
6408 * be recognized by hardware for LRO, and GRO offloads. The main
6409 * motivation of doing this is to only perform one pull for IPv4 TCP
6410 * packets so that we can do basic things like calculating the gso_size
6411 * based on the average data per packet.
1a1c225b
AD		 6412 **/
6413static unsigned int igb_get_headlen(unsigned char *data,
6414 unsigned int max_len)
6415{
6416 union {
6417 unsigned char *network;
6418 /* l2 headers */
6419 struct ethhdr *eth;
6420 struct vlan_hdr *vlan;
6421 /* l3 headers */
6422 struct iphdr *ipv4;
6423 struct ipv6hdr *ipv6;
6424 } hdr;
6425 __be16 protocol;
6426 u8 nexthdr = 0; /* default to not TCP */
6427 u8 hlen;
6428
6429 /* this should never happen, but better safe than sorry */
6430 if (max_len < ETH_HLEN)
6431 return max_len;
6432
6433 /* initialize network frame pointer */
6434 hdr.network = data;
6435
6436 /* set first protocol and move network header forward */
6437 protocol = hdr.eth->h_proto;
6438 hdr.network += ETH_HLEN;
6439
6440 /* handle any vlan tag if present */
6441 if (protocol == __constant_htons(ETH_P_8021Q)) {
6442 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6443 return max_len;
6444
6445 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6446 hdr.network += VLAN_HLEN;
6447 }
6448
6449 /* handle L3 protocols */
6450 if (protocol == __constant_htons(ETH_P_IP)) {
6451 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6452 return max_len;
6453
6454 /* access ihl as a u8 to avoid unaligned access on ia64 */
6455 hlen = (hdr.network[0] & 0x0F) << 2;
6456
6457 /* verify hlen meets minimum size requirements */
6458 if (hlen < sizeof(struct iphdr))
6459 return hdr.network - data;
6460
f2fb4ab2 6461 /* record next protocol if header is present */
b9555f66 6462 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6463 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6464 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6465 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6466 return max_len;
6467
6468 /* record next protocol */
6469 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6470 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6471 } else {
6472 return hdr.network - data;
6473 }
6474
f2fb4ab2
AD		 6475 /* relocate pointer to start of L4 header */
6476 hdr.network += hlen;
6477
1a1c225b
AD		 6478 /* finally sort out TCP */
6479 if (nexthdr == IPPROTO_TCP) {
6480 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6481 return max_len;
6482
6483 /* access doff as a u8 to avoid unaligned access on ia64 */
6484 hlen = (hdr.network[12] & 0xF0) >> 2;
6485
6486 /* verify hlen meets minimum size requirements */
6487 if (hlen < sizeof(struct tcphdr))
6488 return hdr.network - data;
6489
6490 hdr.network += hlen;
6491 } else if (nexthdr == IPPROTO_UDP) {
6492 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6493 return max_len;
6494
6495 hdr.network += sizeof(struct udphdr);
6496 }
6497
b980ac18 6498 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6499 * data section of the packet and will be the end of the header.
6500 * If not then it probably represents the end of the last recognized
6501 * header.
6502 */
6503 if ((hdr.network - data) < max_len)
6504 return hdr.network - data;
6505 else
6506 return max_len;
6507}
6508
6509/**
b980ac18
JK		 6510 * igb_pull_tail - igb specific version of skb_pull_tail
6511 * @rx_ring: rx descriptor ring packet is being transacted on
6512 * @rx_desc: pointer to the EOP Rx descriptor
6513 * @skb: pointer to current skb being adjusted
1a1c225b 6514 *
b980ac18
JK		 6515 * This function is an igb specific version of __pskb_pull_tail. The
6516 * main difference between this version and the original function is that
6517 * this function can make several assumptions about the state of things
6518 * that allow for significant optimizations versus the standard function.
6519 * As a result we can do things like drop a frag and maintain an accurate
6520 * truesize for the skb.
1a1c225b
AD		 6521 */
6522static void igb_pull_tail(struct igb_ring *rx_ring,
6523 union e1000_adv_rx_desc *rx_desc,
6524 struct sk_buff *skb)
2d94d8ab 6525{
1a1c225b
AD		 6526 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6527 unsigned char *va;
6528 unsigned int pull_len;
6529
b980ac18 6530 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6531 * working with pages allocated out of the lomem pool per
6532 * alloc_page(GFP_ATOMIC)
2d94d8ab 6533 */
1a1c225b
AD		 6534 va = skb_frag_address(frag);
6535
1a1c225b
AD		 6536 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6537 /* retrieve timestamp from buffer */
6538 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6539
6540 /* update pointers to remove timestamp header */
6541 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6542 frag->page_offset += IGB_TS_HDR_LEN;
6543 skb->data_len -= IGB_TS_HDR_LEN;
6544 skb->len -= IGB_TS_HDR_LEN;
6545
6546 /* move va to start of packet data */
6547 va += IGB_TS_HDR_LEN;
6548 }
6549
b980ac18 6550 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6551 * 60 bytes if the skb->len is less than 60 for skb_pad.
6552 */
6553 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6554
6555 /* align pull length to size of long to optimize memcpy performance */
6556 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6557
6558 /* update all of the pointers */
6559 skb_frag_size_sub(frag, pull_len);
6560 frag->page_offset += pull_len;
6561 skb->data_len -= pull_len;
6562 skb->tail += pull_len;
6563}
6564
6565/**
b980ac18
JK		 6566 * igb_cleanup_headers - Correct corrupted or empty headers
6567 * @rx_ring: rx descriptor ring packet is being transacted on
6568 * @rx_desc: pointer to the EOP Rx descriptor
6569 * @skb: pointer to current skb being fixed
1a1c225b 6570 *
b980ac18
JK		 6571 * Address the case where we are pulling data in on pages only
6572 * and as such no data is present in the skb header.
1a1c225b 6573 *
b980ac18
JK		 6574 * In addition if skb is not at least 60 bytes we need to pad it so that
6575 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6576 *
b980ac18 6577 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6578 **/
6579static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6580 union e1000_adv_rx_desc *rx_desc,
6581 struct sk_buff *skb)
6582{
1a1c225b
AD		 6583 if (unlikely((igb_test_staterr(rx_desc,
6584 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6585 struct net_device *netdev = rx_ring->netdev;
6586 if (!(netdev->features & NETIF_F_RXALL)) {
6587 dev_kfree_skb_any(skb);
6588 return true;
6589 }
6590 }
6591
6592 /* place header in linear portion of buffer */
6593 if (skb_is_nonlinear(skb))
6594 igb_pull_tail(rx_ring, rx_desc, skb);
6595
6596 /* if skb_pad returns an error the skb was freed */
6597 if (unlikely(skb->len < 60)) {
6598 int pad_len = 60 - skb->len;
6599
6600 if (skb_pad(skb, pad_len))
6601 return true;
6602 __skb_put(skb, pad_len);
6603 }
6604
6605 return false;
2d94d8ab
AD		 6606}
6607
db2ee5bd 6608/**
b980ac18
JK		 6609 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6610 * @rx_ring: rx descriptor ring packet is being transacted on
6611 * @rx_desc: pointer to the EOP Rx descriptor
6612 * @skb: pointer to current skb being populated
db2ee5bd 6613 *
b980ac18
JK		 6614 * This function checks the ring, descriptor, and packet information in
6615 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6616 * other fields within the skb.
db2ee5bd
AD		 6617 **/
6618static void igb_process_skb_fields(struct igb_ring *rx_ring,
6619 union e1000_adv_rx_desc *rx_desc,
6620 struct sk_buff *skb)
6621{
6622 struct net_device *dev = rx_ring->netdev;
6623
6624 igb_rx_hash(rx_ring, rx_desc, skb);
6625
6626 igb_rx_checksum(rx_ring, rx_desc, skb);
6627
20a48412 6628 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6629
f646968f 6630 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6631 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6632 u16 vid;
6633 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6634 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6635 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6636 else
6637 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6638
86a9bad3 6639 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6640 }
6641
6642 skb_record_rx_queue(skb, rx_ring->queue_index);
6643
6644 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6645}
6646
2e334eee 6647static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6648{
0ba82994 6649 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6650 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6651 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6652 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6653
2e334eee
AD		 6654 do {
6655 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6656
2e334eee
AD		 6657 /* return some buffers to hardware, one at a time is too slow */
6658 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6659 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6660 cleaned_count = 0;
6661 }
bf36c1a0 6662
2e334eee 6663 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6664
2e334eee
AD		 6665 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6666 break;
9d5c8243 6667
74e238ea
AD		 6668 /* This memory barrier is needed to keep us from reading
6669 * any other fields out of the rx_desc until we know the
6670 * RXD_STAT_DD bit is set
6671 */
6672 rmb();
6673
2e334eee 6674 /* retrieve a buffer from the ring */
f9d40f6a 6675 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6676
2e334eee
AD		 6677 /* exit if we failed to retrieve a buffer */
6678 if (!skb)
6679 break;
1a1c225b 6680
2e334eee 6681 cleaned_count++;
1a1c225b 6682
2e334eee
AD		 6683 /* fetch next buffer in frame if non-eop */
6684 if (igb_is_non_eop(rx_ring, rx_desc))
6685 continue;
1a1c225b
AD		 6686
6687 /* verify the packet layout is correct */
6688 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6689 skb = NULL;
6690 continue;
9d5c8243 6691 }
9d5c8243 6692
db2ee5bd 6693 /* probably a little skewed due to removing CRC */
3ceb90fd 6694 total_bytes += skb->len;
3ceb90fd 6695
db2ee5bd
AD		 6696 /* populate checksum, timestamp, VLAN, and protocol */
6697 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6698
b2cb09b1 6699 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6700
1a1c225b
AD		 6701 /* reset skb pointer */
6702 skb = NULL;
6703
2e334eee
AD		 6704 /* update budget accounting */
6705 total_packets++;
6706 } while (likely(total_packets < budget));
bf36c1a0 6707
1a1c225b
AD		 6708 /* place incomplete frames back on ring for completion */
6709 rx_ring->skb = skb;
6710
12dcd86b 6711 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6712 rx_ring->rx_stats.packets += total_packets;
6713 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6714 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6715 q_vector->rx.total_packets += total_packets;
6716 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6717
6718 if (cleaned_count)
cd392f5c 6719 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6720
2e334eee 6721 return (total_packets < budget);
9d5c8243
AK		 6722}
6723
c023cd88 6724static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6725 struct igb_rx_buffer *bi)
c023cd88
AD		 6726{
6727 struct page *page = bi->page;
cbc8e55f 6728 dma_addr_t dma;
c023cd88 6729
cbc8e55f
AD		 6730 /* since we are recycling buffers we should seldom need to alloc */
6731 if (likely(page))
c023cd88
AD		 6732 return true;
6733
cbc8e55f
AD		 6734 /* alloc new page for storage */
6735 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6736 if (unlikely(!page)) {
6737 rx_ring->rx_stats.alloc_failed++;
6738 return false;
c023cd88
AD		 6739 }
6740
cbc8e55f
AD		 6741 /* map page for use */
6742 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6743
b980ac18 6744 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6745 * there isn't much point in holding memory we can't use
6746 */
1a1c225b 6747 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6748 __free_page(page);
6749
c023cd88
AD		 6750 rx_ring->rx_stats.alloc_failed++;
6751 return false;
6752 }
6753
1a1c225b 6754 bi->dma = dma;
cbc8e55f
AD		 6755 bi->page = page;
6756 bi->page_offset = 0;
1a1c225b 6757
c023cd88
AD		 6758 return true;
6759}
6760
9d5c8243 6761/**
b980ac18
JK		 6762 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6763 * @adapter: address of board private structure
9d5c8243 6764 **/
cd392f5c 6765void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6766{
9d5c8243 6767 union e1000_adv_rx_desc *rx_desc;
06034649 6768 struct igb_rx_buffer *bi;
c023cd88 6769 u16 i = rx_ring->next_to_use;
9d5c8243 6770
cbc8e55f
AD		 6771 /* nothing to do */
6772 if (!cleaned_count)
6773 return;
6774
60136906 6775 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6776 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6777 i -= rx_ring->count;
9d5c8243 6778
cbc8e55f 6779 do {
1a1c225b 6780 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6781 break;
9d5c8243 6782
b980ac18 6783 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6784 * because each write-back erases this info.
6785 */
f9d40f6a 6786 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6787
c023cd88
AD		 6788 rx_desc++;
6789 bi++;
9d5c8243 6790 i++;
c023cd88 6791 if (unlikely(!i)) {
60136906 6792 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6793 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6794 i -= rx_ring->count;
6795 }
6796
6797 /* clear the hdr_addr for the next_to_use descriptor */
6798 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6799
6800 cleaned_count--;
6801 } while (cleaned_count);
9d5c8243 6802
c023cd88
AD		 6803 i += rx_ring->count;
6804
9d5c8243 6805 if (rx_ring->next_to_use != i) {
cbc8e55f 6806 /* record the next descriptor to use */
9d5c8243 6807 rx_ring->next_to_use = i;
9d5c8243 6808
cbc8e55f
AD		 6809 /* update next to alloc since we have filled the ring */
6810 rx_ring->next_to_alloc = i;
6811
b980ac18 6812 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6813 * know there are new descriptors to fetch. (Only
6814 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6815 * such as IA-64).
6816 */
9d5c8243 6817 wmb();
fce99e34 6818 writel(i, rx_ring->tail);
9d5c8243
AK		 6819 }
6820}
6821
6822/**
6823 * igb_mii_ioctl -
6824 * @netdev:
6825 * @ifreq:
6826 * @cmd:
6827 **/
6828static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6829{
6830 struct igb_adapter *adapter = netdev_priv(netdev);
6831 struct mii_ioctl_data *data = if_mii(ifr);
6832
6833 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6834 return -EOPNOTSUPP;
6835
6836 switch (cmd) {
6837 case SIOCGMIIPHY:
6838 data->phy_id = adapter->hw.phy.addr;
6839 break;
6840 case SIOCGMIIREG:
f5f4cf08
AD		 6841 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6842 &data->val_out))
9d5c8243
AK		 6843 return -EIO;
6844 break;
6845 case SIOCSMIIREG:
6846 default:
6847 return -EOPNOTSUPP;
6848 }
6849 return 0;
6850}
6851
6852/**
6853 * igb_ioctl -
6854 * @netdev:
6855 * @ifreq:
6856 * @cmd:
6857 **/
6858static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6859{
6860 switch (cmd) {
6861 case SIOCGMIIPHY:
6862 case SIOCGMIIREG:
6863 case SIOCSMIIREG:
6864 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6865 case SIOCSHWTSTAMP:
a79f4f88 6866 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6867 default:
6868 return -EOPNOTSUPP;
6869 }
6870}
6871
009bc06e
AD		 6872s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6873{
6874 struct igb_adapter *adapter = hw->back;
009bc06e 6875
23d028cc 6876 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6877 return -E1000_ERR_CONFIG;
6878
009bc06e
AD		 6879 return 0;
6880}
6881
6882s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6883{
6884 struct igb_adapter *adapter = hw->back;
009bc06e 6885
23d028cc 6886 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6887 return -E1000_ERR_CONFIG;
6888
009bc06e
AD		 6889 return 0;
6890}
6891
c8f44aff 6892static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6893{
6894 struct igb_adapter *adapter = netdev_priv(netdev);
6895 struct e1000_hw *hw = &adapter->hw;
6896 u32 ctrl, rctl;
f646968f 6897 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6898
5faf030c 6899 if (enable) {
9d5c8243
AK		 6900 /* enable VLAN tag insert/strip */
6901 ctrl = rd32(E1000_CTRL);
6902 ctrl |= E1000_CTRL_VME;
6903 wr32(E1000_CTRL, ctrl);
6904
51466239 6905 /* Disable CFI check */
9d5c8243 6906 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6907 rctl &= ~E1000_RCTL_CFIEN;
6908 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6909 } else {
6910 /* disable VLAN tag insert/strip */
6911 ctrl = rd32(E1000_CTRL);
6912 ctrl &= ~E1000_CTRL_VME;
6913 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6914 }
6915
e1739522 6916 igb_rlpml_set(adapter);
9d5c8243
AK		 6917}
6918
80d5c368
PM		 6919static int igb_vlan_rx_add_vid(struct net_device *netdev,
6920 __be16 proto, u16 vid)
9d5c8243
AK		 6921{
6922 struct igb_adapter *adapter = netdev_priv(netdev);
6923 struct e1000_hw *hw = &adapter->hw;
4ae196df 6924 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6925
51466239
AD		 6926 /* attempt to add filter to vlvf array */
6927 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6928
51466239
AD		 6929 /* add the filter since PF can receive vlans w/o entry in vlvf */
6930 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6931
6932 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6933
6934 return 0;
9d5c8243
AK		 6935}
6936
80d5c368
PM		 6937static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6938 __be16 proto, u16 vid)
9d5c8243
AK		 6939{
6940 struct igb_adapter *adapter = netdev_priv(netdev);
6941 struct e1000_hw *hw = &adapter->hw;
4ae196df 6942 int pf_id = adapter->vfs_allocated_count;
51466239 6943 s32 err;
9d5c8243 6944
51466239
AD		 6945 /* remove vlan from VLVF table array */
6946 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6947
51466239
AD		 6948 /* if vid was not present in VLVF just remove it from table */
6949 if (err)
4ae196df 6950 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6951
6952 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6953
6954 return 0;
9d5c8243
AK		 6955}
6956
6957static void igb_restore_vlan(struct igb_adapter *adapter)
6958{
b2cb09b1 6959 u16 vid;
9d5c8243 6960
5faf030c
AD		 6961 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6962
b2cb09b1 6963 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 6964 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 6965}
6966
14ad2513 6967int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6968{
090b1795 6969 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6970 struct e1000_mac_info *mac = &adapter->hw.mac;
6971
6972 mac->autoneg = 0;
6973
14ad2513 6974 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 6975 * for the switch() below to work
6976 */
14ad2513
DD		 6977 if ((spd & 1) || (dplx & ~1))
6978 goto err_inval;
6979
f502ef7d
AA		 6980 /* Fiber NIC's only allow 1000 gbps Full duplex
6981 * and 100Mbps Full duplex for 100baseFx sfp
6982 */
6983 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
6984 switch (spd + dplx) {
6985 case SPEED_10 + DUPLEX_HALF:
6986 case SPEED_10 + DUPLEX_FULL:
6987 case SPEED_100 + DUPLEX_HALF:
6988 goto err_inval;
6989 default:
6990 break;
6991 }
6992 }
cd2638a8 6993
14ad2513 6994 switch (spd + dplx) {
9d5c8243
AK		 6995 case SPEED_10 + DUPLEX_HALF:
6996 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6997 break;
6998 case SPEED_10 + DUPLEX_FULL:
6999 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7000 break;
7001 case SPEED_100 + DUPLEX_HALF:
7002 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7003 break;
7004 case SPEED_100 + DUPLEX_FULL:
7005 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7006 break;
7007 case SPEED_1000 + DUPLEX_FULL:
7008 mac->autoneg = 1;
7009 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7010 break;
7011 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7012 default:
14ad2513 7013 goto err_inval;
9d5c8243 7014 }
8376dad0
JB		 7015
7016 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7017 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7018
9d5c8243 7019 return 0;
14ad2513
DD		 7020
7021err_inval:
7022 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7023 return -EINVAL;
9d5c8243
AK		 7024}
7025
749ab2cd
YZ		 7026static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7027 bool runtime)
9d5c8243
AK		 7028{
7029 struct net_device *netdev = pci_get_drvdata(pdev);
7030 struct igb_adapter *adapter = netdev_priv(netdev);
7031 struct e1000_hw *hw = &adapter->hw;
2d064c06 7032 u32 ctrl, rctl, status;
749ab2cd 7033 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7034#ifdef CONFIG_PM
7035 int retval = 0;
7036#endif
7037
7038 netif_device_detach(netdev);
7039
a88f10ec 7040 if (netif_running(netdev))
749ab2cd 7041 __igb_close(netdev, true);
a88f10ec 7042
047e0030 7043 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7044
7045#ifdef CONFIG_PM
7046 retval = pci_save_state(pdev);
7047 if (retval)
7048 return retval;
7049#endif
7050
7051 status = rd32(E1000_STATUS);
7052 if (status & E1000_STATUS_LU)
7053 wufc &= ~E1000_WUFC_LNKC;
7054
7055 if (wufc) {
7056 igb_setup_rctl(adapter);
ff41f8dc 7057 igb_set_rx_mode(netdev);
9d5c8243
AK		 7058
7059 /* turn on all-multi mode if wake on multicast is enabled */
7060 if (wufc & E1000_WUFC_MC) {
7061 rctl = rd32(E1000_RCTL);
7062 rctl |= E1000_RCTL_MPE;
7063 wr32(E1000_RCTL, rctl);
7064 }
7065
7066 ctrl = rd32(E1000_CTRL);
7067 /* advertise wake from D3Cold */
7068 #define E1000_CTRL_ADVD3WUC 0x00100000
7069 /* phy power management enable */
7070 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7071 ctrl |= E1000_CTRL_ADVD3WUC;
7072 wr32(E1000_CTRL, ctrl);
7073
9d5c8243 7074 /* Allow time for pending master requests to run */
330a6d6a 7075 igb_disable_pcie_master(hw);
9d5c8243
AK		 7076
7077 wr32(E1000_WUC, E1000_WUC_PME_EN);
7078 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7079 } else {
7080 wr32(E1000_WUC, 0);
7081 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7082 }
7083
3fe7c4c9
RW		 7084 *enable_wake = wufc || adapter->en_mng_pt;
7085 if (!*enable_wake)
88a268c1
NN		 7086 igb_power_down_link(adapter);
7087 else
7088 igb_power_up_link(adapter);
9d5c8243
AK		 7089
7090 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7091 * would have already happened in close and is redundant.
7092 */
9d5c8243
AK		 7093 igb_release_hw_control(adapter);
7094
7095 pci_disable_device(pdev);
7096
9d5c8243
AK		 7097 return 0;
7098}
7099
7100#ifdef CONFIG_PM
d9dd966d 7101#ifdef CONFIG_PM_SLEEP
749ab2cd 7102static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7103{
7104 int retval;
7105 bool wake;
749ab2cd 7106 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7107
749ab2cd 7108 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7109 if (retval)
7110 return retval;
7111
7112 if (wake) {
7113 pci_prepare_to_sleep(pdev);
7114 } else {
7115 pci_wake_from_d3(pdev, false);
7116 pci_set_power_state(pdev, PCI_D3hot);
7117 }
7118
7119 return 0;
7120}
d9dd966d 7121#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7122
749ab2cd 7123static int igb_resume(struct device *dev)
9d5c8243 7124{
749ab2cd 7125 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7126 struct net_device *netdev = pci_get_drvdata(pdev);
7127 struct igb_adapter *adapter = netdev_priv(netdev);
7128 struct e1000_hw *hw = &adapter->hw;
7129 u32 err;
7130
7131 pci_set_power_state(pdev, PCI_D0);
7132 pci_restore_state(pdev);
b94f2d77 7133 pci_save_state(pdev);
42bfd33a 7134
aed5dec3 7135 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7136 if (err) {
7137 dev_err(&pdev->dev,
7138 "igb: Cannot enable PCI device from suspend\n");
7139 return err;
7140 }
7141 pci_set_master(pdev);
7142
7143 pci_enable_wake(pdev, PCI_D3hot, 0);
7144 pci_enable_wake(pdev, PCI_D3cold, 0);
7145
53c7d064 7146 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7147 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7148 return -ENOMEM;
9d5c8243
AK		 7149 }
7150
9d5c8243 7151 igb_reset(adapter);
a8564f03
AD		 7152
7153 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7154 * driver.
7155 */
a8564f03
AD		 7156 igb_get_hw_control(adapter);
7157
9d5c8243
AK		 7158 wr32(E1000_WUS, ~0);
7159
749ab2cd 7160 if (netdev->flags & IFF_UP) {
0c2cc02e 7161 rtnl_lock();
749ab2cd 7162 err = __igb_open(netdev, true);
0c2cc02e 7163 rtnl_unlock();
a88f10ec
AD		 7164 if (err)
7165 return err;
7166 }
9d5c8243
AK		 7167
7168 netif_device_attach(netdev);
749ab2cd
YZ		 7169 return 0;
7170}
7171
7172#ifdef CONFIG_PM_RUNTIME
7173static int igb_runtime_idle(struct device *dev)
7174{
7175 struct pci_dev *pdev = to_pci_dev(dev);
7176 struct net_device *netdev = pci_get_drvdata(pdev);
7177 struct igb_adapter *adapter = netdev_priv(netdev);
7178
7179 if (!igb_has_link(adapter))
7180 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7181
7182 return -EBUSY;
7183}
7184
7185static int igb_runtime_suspend(struct device *dev)
7186{
7187 struct pci_dev *pdev = to_pci_dev(dev);
7188 int retval;
7189 bool wake;
7190
7191 retval = __igb_shutdown(pdev, &wake, 1);
7192 if (retval)
7193 return retval;
7194
7195 if (wake) {
7196 pci_prepare_to_sleep(pdev);
7197 } else {
7198 pci_wake_from_d3(pdev, false);
7199 pci_set_power_state(pdev, PCI_D3hot);
7200 }
9d5c8243 7201
9d5c8243
AK		 7202 return 0;
7203}
749ab2cd
YZ		 7204
7205static int igb_runtime_resume(struct device *dev)
7206{
7207 return igb_resume(dev);
7208}
7209#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7210#endif
7211
7212static void igb_shutdown(struct pci_dev *pdev)
7213{
3fe7c4c9
RW		 7214 bool wake;
7215
749ab2cd 7216 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7217
7218 if (system_state == SYSTEM_POWER_OFF) {
7219 pci_wake_from_d3(pdev, wake);
7220 pci_set_power_state(pdev, PCI_D3hot);
7221 }
9d5c8243
AK		 7222}
7223
fa44f2f1
GR		 7224#ifdef CONFIG_PCI_IOV
7225static int igb_sriov_reinit(struct pci_dev *dev)
7226{
7227 struct net_device *netdev = pci_get_drvdata(dev);
7228 struct igb_adapter *adapter = netdev_priv(netdev);
7229 struct pci_dev *pdev = adapter->pdev;
7230
7231 rtnl_lock();
7232
7233 if (netif_running(netdev))
7234 igb_close(netdev);
7235
7236 igb_clear_interrupt_scheme(adapter);
7237
7238 igb_init_queue_configuration(adapter);
7239
7240 if (igb_init_interrupt_scheme(adapter, true)) {
7241 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7242 return -ENOMEM;
7243 }
7244
7245 if (netif_running(netdev))
7246 igb_open(netdev);
7247
7248 rtnl_unlock();
7249
7250 return 0;
7251}
7252
7253static int igb_pci_disable_sriov(struct pci_dev *dev)
7254{
7255 int err = igb_disable_sriov(dev);
7256
7257 if (!err)
7258 err = igb_sriov_reinit(dev);
7259
7260 return err;
7261}
7262
7263static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7264{
7265 int err = igb_enable_sriov(dev, num_vfs);
7266
7267 if (err)
7268 goto out;
7269
7270 err = igb_sriov_reinit(dev);
7271 if (!err)
7272 return num_vfs;
7273
7274out:
7275 return err;
7276}
7277
7278#endif
7279static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7280{
7281#ifdef CONFIG_PCI_IOV
7282 if (num_vfs == 0)
7283 return igb_pci_disable_sriov(dev);
7284 else
7285 return igb_pci_enable_sriov(dev, num_vfs);
7286#endif
7287 return 0;
7288}
7289
9d5c8243 7290#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7291/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7292 * without having to re-enable interrupts. It's not called while
7293 * the interrupt routine is executing.
7294 */
7295static void igb_netpoll(struct net_device *netdev)
7296{
7297 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7298 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7299 struct igb_q_vector *q_vector;
9d5c8243 7300 int i;
9d5c8243 7301
047e0030 7302 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7303 q_vector = adapter->q_vector[i];
7304 if (adapter->msix_entries)
7305 wr32(E1000_EIMC, q_vector->eims_value);
7306 else
7307 igb_irq_disable(adapter);
047e0030 7308 napi_schedule(&q_vector->napi);
eebbbdba 7309 }
9d5c8243
AK		 7310}
7311#endif /* CONFIG_NET_POLL_CONTROLLER */
7312
7313/**
b980ac18
JK		 7314 * igb_io_error_detected - called when PCI error is detected
7315 * @pdev: Pointer to PCI device
7316 * @state: The current pci connection state
9d5c8243 7317 *
b980ac18
JK		 7318 * This function is called after a PCI bus error affecting
7319 * this device has been detected.
7320 **/
9d5c8243
AK		 7321static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7322 pci_channel_state_t state)
7323{
7324 struct net_device *netdev = pci_get_drvdata(pdev);
7325 struct igb_adapter *adapter = netdev_priv(netdev);
7326
7327 netif_device_detach(netdev);
7328
59ed6eec
AD		 7329 if (state == pci_channel_io_perm_failure)
7330 return PCI_ERS_RESULT_DISCONNECT;
7331
9d5c8243
AK		 7332 if (netif_running(netdev))
7333 igb_down(adapter);
7334 pci_disable_device(pdev);
7335
7336 /* Request a slot slot reset. */
7337 return PCI_ERS_RESULT_NEED_RESET;
7338}
7339
7340/**
b980ac18
JK		 7341 * igb_io_slot_reset - called after the pci bus has been reset.
7342 * @pdev: Pointer to PCI device
9d5c8243 7343 *
b980ac18
JK		 7344 * Restart the card from scratch, as if from a cold-boot. Implementation
7345 * resembles the first-half of the igb_resume routine.
7346 **/
9d5c8243
AK		 7347static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7348{
7349 struct net_device *netdev = pci_get_drvdata(pdev);
7350 struct igb_adapter *adapter = netdev_priv(netdev);
7351 struct e1000_hw *hw = &adapter->hw;
40a914fa 7352 pci_ers_result_t result;
42bfd33a 7353 int err;
9d5c8243 7354
aed5dec3 7355 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7356 dev_err(&pdev->dev,
7357 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7358 result = PCI_ERS_RESULT_DISCONNECT;
7359 } else {
7360 pci_set_master(pdev);
7361 pci_restore_state(pdev);
b94f2d77 7362 pci_save_state(pdev);
9d5c8243 7363
40a914fa
AD		 7364 pci_enable_wake(pdev, PCI_D3hot, 0);
7365 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7366
40a914fa
AD		 7367 igb_reset(adapter);
7368 wr32(E1000_WUS, ~0);
7369 result = PCI_ERS_RESULT_RECOVERED;
7370 }
9d5c8243 7371
ea943d41
JK		 7372 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7373 if (err) {
b980ac18
JK		 7374 dev_err(&pdev->dev,
7375 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7376 err);
ea943d41
JK		 7377 /* non-fatal, continue */
7378 }
40a914fa
AD		 7379
7380 return result;
9d5c8243
AK		 7381}
7382
7383/**
b980ac18
JK		 7384 * igb_io_resume - called when traffic can start flowing again.
7385 * @pdev: Pointer to PCI device
9d5c8243 7386 *
b980ac18
JK		 7387 * This callback is called when the error recovery driver tells us that
7388 * its OK to resume normal operation. Implementation resembles the
7389 * second-half of the igb_resume routine.
9d5c8243
AK		 7390 */
7391static void igb_io_resume(struct pci_dev *pdev)
7392{
7393 struct net_device *netdev = pci_get_drvdata(pdev);
7394 struct igb_adapter *adapter = netdev_priv(netdev);
7395
9d5c8243
AK		 7396 if (netif_running(netdev)) {
7397 if (igb_up(adapter)) {
7398 dev_err(&pdev->dev, "igb_up failed after reset\n");
7399 return;
7400 }
7401 }
7402
7403 netif_device_attach(netdev);
7404
7405 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7406 * driver.
7407 */
9d5c8243 7408 igb_get_hw_control(adapter);
9d5c8243
AK		 7409}
7410
26ad9178 7411static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7412 u8 qsel)
26ad9178
AD		 7413{
7414 u32 rar_low, rar_high;
7415 struct e1000_hw *hw = &adapter->hw;
7416
7417 /* HW expects these in little endian so we reverse the byte order
7418 * from network order (big endian) to little endian
7419 */
7420 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7421 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7422 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7423
7424 /* Indicate to hardware the Address is Valid. */
7425 rar_high |= E1000_RAH_AV;
7426
7427 if (hw->mac.type == e1000_82575)
7428 rar_high |= E1000_RAH_POOL_1 * qsel;
7429 else
7430 rar_high |= E1000_RAH_POOL_1 << qsel;
7431
7432 wr32(E1000_RAL(index), rar_low);
7433 wrfl();
7434 wr32(E1000_RAH(index), rar_high);
7435 wrfl();
7436}
7437
4ae196df 7438static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7439 int vf, unsigned char *mac_addr)
4ae196df
AD		 7440{
7441 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7442 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7443 * towards the first, as a result a collision should not be possible
7444 */
ff41f8dc 7445 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7446
37680117 7447 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7448
26ad9178 7449 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7450
7451 return 0;
7452}
7453
8151d294
WM		 7454static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7455{
7456 struct igb_adapter *adapter = netdev_priv(netdev);
7457 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7458 return -EINVAL;
7459 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7460 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7461 dev_info(&adapter->pdev->dev,
7462 "Reload the VF driver to make this change effective.");
8151d294 7463 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7464 dev_warn(&adapter->pdev->dev,
7465 "The VF MAC address has been set, but the PF device is not up.\n");
7466 dev_warn(&adapter->pdev->dev,
7467 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7468 }
7469 return igb_set_vf_mac(adapter, vf, mac);
7470}
7471
17dc566c
LL		 7472static int igb_link_mbps(int internal_link_speed)
7473{
7474 switch (internal_link_speed) {
7475 case SPEED_100:
7476 return 100;
7477 case SPEED_1000:
7478 return 1000;
7479 default:
7480 return 0;
7481 }
7482}
7483
7484static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7485 int link_speed)
7486{
7487 int rf_dec, rf_int;
7488 u32 bcnrc_val;
7489
7490 if (tx_rate != 0) {
7491 /* Calculate the rate factor values to set */
7492 rf_int = link_speed / tx_rate;
7493 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7494 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7495 tx_rate;
17dc566c
LL		 7496
7497 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7498 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7499 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7500 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7501 } else {
7502 bcnrc_val = 0;
7503 }
7504
7505 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7506 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7507 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7508 */
7509 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7510 wr32(E1000_RTTBCNRC, bcnrc_val);
7511}
7512
7513static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7514{
7515 int actual_link_speed, i;
7516 bool reset_rate = false;
7517
7518 /* VF TX rate limit was not set or not supported */
7519 if ((adapter->vf_rate_link_speed == 0) ||
7520 (adapter->hw.mac.type != e1000_82576))
7521 return;
7522
7523 actual_link_speed = igb_link_mbps(adapter->link_speed);
7524 if (actual_link_speed != adapter->vf_rate_link_speed) {
7525 reset_rate = true;
7526 adapter->vf_rate_link_speed = 0;
7527 dev_info(&adapter->pdev->dev,
b980ac18 7528 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7529 }
7530
7531 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7532 if (reset_rate)
7533 adapter->vf_data[i].tx_rate = 0;
7534
7535 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7536 adapter->vf_data[i].tx_rate,
7537 actual_link_speed);
17dc566c
LL		 7538 }
7539}
7540
8151d294
WM		 7541static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7542{
17dc566c
LL		 7543 struct igb_adapter *adapter = netdev_priv(netdev);
7544 struct e1000_hw *hw = &adapter->hw;
7545 int actual_link_speed;
7546
7547 if (hw->mac.type != e1000_82576)
7548 return -EOPNOTSUPP;
7549
7550 actual_link_speed = igb_link_mbps(adapter->link_speed);
7551 if ((vf >= adapter->vfs_allocated_count) ||
7552 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7553 (tx_rate < 0) || (tx_rate > actual_link_speed))
7554 return -EINVAL;
7555
7556 adapter->vf_rate_link_speed = actual_link_speed;
7557 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7558 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7559
7560 return 0;
8151d294
WM		 7561}
7562
70ea4783
LL		 7563static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7564 bool setting)
7565{
7566 struct igb_adapter *adapter = netdev_priv(netdev);
7567 struct e1000_hw *hw = &adapter->hw;
7568 u32 reg_val, reg_offset;
7569
7570 if (!adapter->vfs_allocated_count)
7571 return -EOPNOTSUPP;
7572
7573 if (vf >= adapter->vfs_allocated_count)
7574 return -EINVAL;
7575
7576 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7577 reg_val = rd32(reg_offset);
7578 if (setting)
7579 reg_val |= ((1 << vf) |
7580 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7581 else
7582 reg_val &= ~((1 << vf) |
7583 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7584 wr32(reg_offset, reg_val);
7585
7586 adapter->vf_data[vf].spoofchk_enabled = setting;
7587 return E1000_SUCCESS;
7588}
7589
8151d294
WM		 7590static int igb_ndo_get_vf_config(struct net_device *netdev,
7591 int vf, struct ifla_vf_info *ivi)
7592{
7593 struct igb_adapter *adapter = netdev_priv(netdev);
7594 if (vf >= adapter->vfs_allocated_count)
7595 return -EINVAL;
7596 ivi->vf = vf;
7597 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7598 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7599 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7600 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7601 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7602 return 0;
7603}
7604
4ae196df
AD		 7605static void igb_vmm_control(struct igb_adapter *adapter)
7606{
7607 struct e1000_hw *hw = &adapter->hw;
10d8e907 7608 u32 reg;
4ae196df 7609
52a1dd4d
AD		 7610 switch (hw->mac.type) {
7611 case e1000_82575:
f96a8a0b
CW		 7612 case e1000_i210:
7613 case e1000_i211:
ceb5f13b 7614 case e1000_i354:
52a1dd4d
AD		 7615 default:
7616 /* replication is not supported for 82575 */
4ae196df 7617 return;
52a1dd4d
AD		 7618 case e1000_82576:
7619 /* notify HW that the MAC is adding vlan tags */
7620 reg = rd32(E1000_DTXCTL);
7621 reg |= E1000_DTXCTL_VLAN_ADDED;
7622 wr32(E1000_DTXCTL, reg);
7623 case e1000_82580:
7624 /* enable replication vlan tag stripping */
7625 reg = rd32(E1000_RPLOLR);
7626 reg |= E1000_RPLOLR_STRVLAN;
7627 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7628 case e1000_i350:
7629 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7630 break;
7631 }
10d8e907 7632
d4960307
AD		 7633 if (adapter->vfs_allocated_count) {
7634 igb_vmdq_set_loopback_pf(hw, true);
7635 igb_vmdq_set_replication_pf(hw, true);
13800469 7636 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7637 adapter->vfs_allocated_count);
d4960307
AD		 7638 } else {
7639 igb_vmdq_set_loopback_pf(hw, false);
7640 igb_vmdq_set_replication_pf(hw, false);
7641 }
4ae196df
AD		 7642}
7643
b6e0c419
CW		 7644static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7645{
7646 struct e1000_hw *hw = &adapter->hw;
7647 u32 dmac_thr;
7648 u16 hwm;
7649
7650 if (hw->mac.type > e1000_82580) {
7651 if (adapter->flags & IGB_FLAG_DMAC) {
7652 u32 reg;
7653
7654 /* force threshold to 0. */
7655 wr32(E1000_DMCTXTH, 0);
7656
b980ac18 7657 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7658 * than the Rx threshold. Set hwm to PBA - max frame
7659 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7660 */
e8c626e9
MV		 7661 hwm = 64 * pba - adapter->max_frame_size / 16;
7662 if (hwm < 64 * (pba - 6))
7663 hwm = 64 * (pba - 6);
7664 reg = rd32(E1000_FCRTC);
7665 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7666 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7667 & E1000_FCRTC_RTH_COAL_MASK);
7668 wr32(E1000_FCRTC, reg);
7669
b980ac18 7670 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7671 * frame size, capping it at PBA - 10KB.
7672 */
7673 dmac_thr = pba - adapter->max_frame_size / 512;
7674 if (dmac_thr < pba - 10)
7675 dmac_thr = pba - 10;
b6e0c419
CW		 7676 reg = rd32(E1000_DMACR);
7677 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7678 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7679 & E1000_DMACR_DMACTHR_MASK);
7680
7681 /* transition to L0x or L1 if available..*/
7682 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7683
7684 /* watchdog timer= +-1000 usec in 32usec intervals */
7685 reg |= (1000 >> 5);
0c02dd98
MV		 7686
7687 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7688 if (hw->mac.type != e1000_i354)
7689 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7690
b6e0c419
CW		 7691 wr32(E1000_DMACR, reg);
7692
b980ac18 7693 /* no lower threshold to disable
b6e0c419
CW		 7694 * coalescing(smart fifb)-UTRESH=0
7695 */
7696 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7697
7698 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7699
7700 wr32(E1000_DMCTLX, reg);
7701
b980ac18 7702 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7703 * DMA coal
7704 */
7705 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7706 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7707
b980ac18 7708 /* make low power state decision controlled
b6e0c419
CW		 7709 * by DMA coal
7710 */
7711 reg = rd32(E1000_PCIEMISC);
7712 reg &= ~E1000_PCIEMISC_LX_DECISION;
7713 wr32(E1000_PCIEMISC, reg);
7714 } /* endif adapter->dmac is not disabled */
7715 } else if (hw->mac.type == e1000_82580) {
7716 u32 reg = rd32(E1000_PCIEMISC);
7717 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7718 wr32(E1000_DMACR, 0);
7719 }
7720}
7721
b980ac18
JK		 7722/**
7723 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7724 * @hw: pointer to hardware structure
7725 * @byte_offset: byte offset to read
7726 * @dev_addr: device address
7727 * @data: value read
7728 *
7729 * Performs byte read operation over I2C interface at
7730 * a specified device address.
b980ac18 7731 **/
441fc6fd 7732s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7733 u8 dev_addr, u8 *data)
441fc6fd
CW		 7734{
7735 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7736 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7737 s32 status;
7738 u16 swfw_mask = 0;
7739
7740 if (!this_client)
7741 return E1000_ERR_I2C;
7742
7743 swfw_mask = E1000_SWFW_PHY0_SM;
7744
7745 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7746 != E1000_SUCCESS)
7747 return E1000_ERR_SWFW_SYNC;
7748
7749 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7750 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7751
7752 if (status < 0)
7753 return E1000_ERR_I2C;
7754 else {
7755 *data = status;
7756 return E1000_SUCCESS;
7757 }
7758}
7759
b980ac18
JK		 7760/**
7761 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7762 * @hw: pointer to hardware structure
7763 * @byte_offset: byte offset to write
7764 * @dev_addr: device address
7765 * @data: value to write
7766 *
7767 * Performs byte write operation over I2C interface at
7768 * a specified device address.
b980ac18 7769 **/
441fc6fd 7770s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7771 u8 dev_addr, u8 data)
441fc6fd
CW		 7772{
7773 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7774 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7775 s32 status;
7776 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7777
7778 if (!this_client)
7779 return E1000_ERR_I2C;
7780
7781 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7782 return E1000_ERR_SWFW_SYNC;
7783 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7784 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7785
7786 if (status)
7787 return E1000_ERR_I2C;
7788 else
7789 return E1000_SUCCESS;
7790
7791}
9d5c8243 7792/* igb_main.c */
Linux kernel - Deliverables
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