projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: Fix queue allocation method to accommodate changing during runtime
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
66f40b8a 65#define BUILD 5
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 126static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 128static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
53c7d064 132static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 139static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
cd392f5c 143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
68d480c4 148static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
047e0030 152static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 153#ifdef CONFIG_IGB_DCA
047e0030 154static void igb_update_dca(struct igb_q_vector *);
fe4506b6 155static void igb_setup_dca(struct igb_adapter *);
421e02f0 156#endif /* CONFIG_IGB_DCA */
661086df 157static int igb_poll(struct napi_struct *, int);
13fde97a 158static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
c8f44aff 163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 166static void igb_restore_vlan(struct igb_adapter *);
26ad9178 167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
4ae196df 170static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
8151d294
WM		 179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
17dc566c 181static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 185static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 186#endif
9d5c8243 187
9d5c8243 188#ifdef CONFIG_PM
d9dd966d 189#ifdef CONFIG_PM_SLEEP
749ab2cd 190static int igb_suspend(struct device *);
d9dd966d 191#endif
749ab2cd
YZ		 192static int igb_resume(struct device *);
193#ifdef CONFIG_PM_RUNTIME
194static int igb_runtime_suspend(struct device *dev);
195static int igb_runtime_resume(struct device *dev);
196static int igb_runtime_idle(struct device *dev);
197#endif
198static const struct dev_pm_ops igb_pm_ops = {
199 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
200 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
201 igb_runtime_idle)
202};
9d5c8243
AK		 203#endif
204static void igb_shutdown(struct pci_dev *);
fa44f2f1 205static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
208static struct notifier_block dca_notifier = {
209 .notifier_call = igb_notify_dca,
210 .next = NULL,
211 .priority = 0
212};
213#endif
9d5c8243
AK		 214#ifdef CONFIG_NET_POLL_CONTROLLER
215/* for netdump / net console */
216static void igb_netpoll(struct net_device *);
217#endif
37680117 218#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 219static unsigned int max_vfs = 0;
220module_param(max_vfs, uint, 0);
221MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
222 "per physical function");
223#endif /* CONFIG_PCI_IOV */
224
9d5c8243
AK		 225static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
226 pci_channel_state_t);
227static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
228static void igb_io_resume(struct pci_dev *);
229
3646f0e5 230static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 231 .error_detected = igb_io_error_detected,
232 .slot_reset = igb_io_slot_reset,
233 .resume = igb_io_resume,
234};
235
b6e0c419 236static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 237
238static struct pci_driver igb_driver = {
239 .name = igb_driver_name,
240 .id_table = igb_pci_tbl,
241 .probe = igb_probe,
9f9a12f8 242 .remove = igb_remove,
9d5c8243 243#ifdef CONFIG_PM
749ab2cd 244 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 245#endif
246 .shutdown = igb_shutdown,
fa44f2f1 247 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 248 .err_handler = &igb_err_handler
249};
250
251MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
252MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
253MODULE_LICENSE("GPL");
254MODULE_VERSION(DRV_VERSION);
255
b3f4d599 256#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
257static int debug = -1;
258module_param(debug, int, 0);
259MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
260
c97ec42a
TI		 261struct igb_reg_info {
262 u32 ofs;
263 char *name;
264};
265
266static const struct igb_reg_info igb_reg_info_tbl[] = {
267
268 /* General Registers */
269 {E1000_CTRL, "CTRL"},
270 {E1000_STATUS, "STATUS"},
271 {E1000_CTRL_EXT, "CTRL_EXT"},
272
273 /* Interrupt Registers */
274 {E1000_ICR, "ICR"},
275
276 /* RX Registers */
277 {E1000_RCTL, "RCTL"},
278 {E1000_RDLEN(0), "RDLEN"},
279 {E1000_RDH(0), "RDH"},
280 {E1000_RDT(0), "RDT"},
281 {E1000_RXDCTL(0), "RXDCTL"},
282 {E1000_RDBAL(0), "RDBAL"},
283 {E1000_RDBAH(0), "RDBAH"},
284
285 /* TX Registers */
286 {E1000_TCTL, "TCTL"},
287 {E1000_TDBAL(0), "TDBAL"},
288 {E1000_TDBAH(0), "TDBAH"},
289 {E1000_TDLEN(0), "TDLEN"},
290 {E1000_TDH(0), "TDH"},
291 {E1000_TDT(0), "TDT"},
292 {E1000_TXDCTL(0), "TXDCTL"},
293 {E1000_TDFH, "TDFH"},
294 {E1000_TDFT, "TDFT"},
295 {E1000_TDFHS, "TDFHS"},
296 {E1000_TDFPC, "TDFPC"},
297
298 /* List Terminator */
299 {}
300};
301
b980ac18 302/* igb_regdump - register printout routine */
c97ec42a
TI		 303static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
304{
305 int n = 0;
306 char rname[16];
307 u32 regs[8];
308
309 switch (reginfo->ofs) {
310 case E1000_RDLEN(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDLEN(n));
313 break;
314 case E1000_RDH(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDH(n));
317 break;
318 case E1000_RDT(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RDT(n));
321 break;
322 case E1000_RXDCTL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RXDCTL(n));
325 break;
326 case E1000_RDBAL(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAL(n));
329 break;
330 case E1000_RDBAH(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAH(n));
333 break;
334 case E1000_TDBAL(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_RDBAL(n));
337 break;
338 case E1000_TDBAH(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDBAH(n));
341 break;
342 case E1000_TDLEN(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDLEN(n));
345 break;
346 case E1000_TDH(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDH(n));
349 break;
350 case E1000_TDT(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TDT(n));
353 break;
354 case E1000_TXDCTL(0):
355 for (n = 0; n < 4; n++)
356 regs[n] = rd32(E1000_TXDCTL(n));
357 break;
358 default:
876d2d6f 359 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 360 return;
361 }
362
363 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 364 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
365 regs[2], regs[3]);
c97ec42a
TI		 366}
367
b980ac18 368/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 369static void igb_dump(struct igb_adapter *adapter)
370{
371 struct net_device *netdev = adapter->netdev;
372 struct e1000_hw *hw = &adapter->hw;
373 struct igb_reg_info *reginfo;
c97ec42a
TI		 374 struct igb_ring *tx_ring;
375 union e1000_adv_tx_desc *tx_desc;
376 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 377 struct igb_ring *rx_ring;
378 union e1000_adv_rx_desc *rx_desc;
379 u32 staterr;
6ad4edfc 380 u16 i, n;
c97ec42a
TI		 381
382 if (!netif_msg_hw(adapter))
383 return;
384
385 /* Print netdevice Info */
386 if (netdev) {
387 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 388 pr_info("Device Name state trans_start "
389 "last_rx\n");
390 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
391 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 392 }
393
394 /* Print Registers */
395 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 396 pr_info(" Register Name Value\n");
c97ec42a
TI		 397 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
398 reginfo->name; reginfo++) {
399 igb_regdump(hw, reginfo);
400 }
401
402 /* Print TX Ring Summary */
403 if (!netdev || !netif_running(netdev))
404 goto exit;
405
406 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 407 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 408 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 409 struct igb_tx_buffer *buffer_info;
c97ec42a 410 tx_ring = adapter->tx_ring[n];
06034649 411 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 412 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
413 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 414 (u64)dma_unmap_addr(buffer_info, dma),
415 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 416 buffer_info->next_to_watch,
417 (u64)buffer_info->time_stamp);
c97ec42a
TI		 418 }
419
420 /* Print TX Rings */
421 if (!netif_msg_tx_done(adapter))
422 goto rx_ring_summary;
423
424 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
425
426 /* Transmit Descriptor Formats
427 *
428 * Advanced Transmit Descriptor
429 * +--------------------------------------------------------------+
430 * 0 | Buffer Address [63:0] |
431 * +--------------------------------------------------------------+
432 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
433 * +--------------------------------------------------------------+
434 * 63 46 45 40 39 38 36 35 32 31 24 15 0
435 */
436
437 for (n = 0; n < adapter->num_tx_queues; n++) {
438 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 439 pr_info("------------------------------------\n");
440 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
441 pr_info("------------------------------------\n");
442 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
443 "[bi->dma ] leng ntw timestamp "
444 "bi->skb\n");
c97ec42a
TI		 445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 447 const char *next_desc;
06034649 448 struct igb_tx_buffer *buffer_info;
60136906 449 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 450 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 451 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 452 if (i == tx_ring->next_to_use &&
453 i == tx_ring->next_to_clean)
454 next_desc = " NTC/U";
455 else if (i == tx_ring->next_to_use)
456 next_desc = " NTU";
457 else if (i == tx_ring->next_to_clean)
458 next_desc = " NTC";
459 else
460 next_desc = "";
461
462 pr_info("T [0x%03X] %016llX %016llX %016llX"
463 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 464 le64_to_cpu(u0->a),
465 le64_to_cpu(u0->b),
c9f14bf3
AD		 466 (u64)dma_unmap_addr(buffer_info, dma),
467 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 468 buffer_info->next_to_watch,
469 (u64)buffer_info->time_stamp,
876d2d6f 470 buffer_info->skb, next_desc);
c97ec42a 471
b669588a 472 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 473 print_hex_dump(KERN_INFO, "",
474 DUMP_PREFIX_ADDRESS,
b669588a 475 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 476 dma_unmap_len(buffer_info, len),
477 true);
c97ec42a
TI		 478 }
479 }
480
481 /* Print RX Rings Summary */
482rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 484 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 487 pr_info(" %5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
497 /* Advanced Receive Descriptor (Read) Format
498 * 63 1 0
499 * +-----------------------------------------------------+
500 * 0 | Packet Buffer Address [63:1] |A0/NSE|
501 * +----------------------------------------------+------+
502 * 8 | Header Buffer Address [63:1] | DD |
503 * +-----------------------------------------------------+
504 *
505 *
506 * Advanced Receive Descriptor (Write-Back) Format
507 *
508 * 63 48 47 32 31 30 21 20 17 16 4 3 0
509 * +------------------------------------------------------+
510 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
511 * | Checksum Ident | | | | Type | Type |
512 * +------------------------------------------------------+
513 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
514 * +------------------------------------------------------+
515 * 63 48 47 32 31 20 19 0
516 */
517
518 for (n = 0; n < adapter->num_rx_queues; n++) {
519 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 520 pr_info("------------------------------------\n");
521 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
522 pr_info("------------------------------------\n");
523 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
524 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
525 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
526 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 527
528 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 529 const char *next_desc;
06034649
AD		 530 struct igb_rx_buffer *buffer_info;
531 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 532 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 533 u0 = (struct my_u0 *)rx_desc;
534 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 535
536 if (i == rx_ring->next_to_use)
537 next_desc = " NTU";
538 else if (i == rx_ring->next_to_clean)
539 next_desc = " NTC";
540 else
541 next_desc = "";
542
c97ec42a
TI		 543 if (staterr & E1000_RXD_STAT_DD) {
544 /* Descriptor Done */
1a1c225b
AD		 545 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
546 "RWB", i,
c97ec42a
TI		 547 le64_to_cpu(u0->a),
548 le64_to_cpu(u0->b),
1a1c225b 549 next_desc);
c97ec42a 550 } else {
1a1c225b
AD		 551 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
552 "R ", i,
c97ec42a
TI		 553 le64_to_cpu(u0->a),
554 le64_to_cpu(u0->b),
555 (u64)buffer_info->dma,
1a1c225b 556 next_desc);
c97ec42a 557
b669588a 558 if (netif_msg_pktdata(adapter) &&
1a1c225b 559 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 560 print_hex_dump(KERN_INFO, "",
561 DUMP_PREFIX_ADDRESS,
562 16, 1,
b669588a
ET		 563 page_address(buffer_info->page) +
564 buffer_info->page_offset,
de78d1f9 565 IGB_RX_BUFSZ, true);
c97ec42a
TI		 566 }
567 }
c97ec42a
TI		 568 }
569 }
570
571exit:
572 return;
573}
574
b980ac18
JK		 575/**
576 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 577 * @hw: pointer to hardware structure
578 * @i2cctl: Current value of I2CCTL register
579 *
580 * Returns the I2C data bit value
b980ac18 581 **/
441fc6fd
CW		 582static int igb_get_i2c_data(void *data)
583{
584 struct igb_adapter *adapter = (struct igb_adapter *)data;
585 struct e1000_hw *hw = &adapter->hw;
586 s32 i2cctl = rd32(E1000_I2CPARAMS);
587
588 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
589}
590
b980ac18
JK		 591/**
592 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 593 * @data: pointer to hardware structure
594 * @state: I2C data value (0 or 1) to set
595 *
596 * Sets the I2C data bit
b980ac18 597 **/
441fc6fd
CW		 598static void igb_set_i2c_data(void *data, int state)
599{
600 struct igb_adapter *adapter = (struct igb_adapter *)data;
601 struct e1000_hw *hw = &adapter->hw;
602 s32 i2cctl = rd32(E1000_I2CPARAMS);
603
604 if (state)
605 i2cctl |= E1000_I2C_DATA_OUT;
606 else
607 i2cctl &= ~E1000_I2C_DATA_OUT;
608
609 i2cctl &= ~E1000_I2C_DATA_OE_N;
610 i2cctl |= E1000_I2C_CLK_OE_N;
611 wr32(E1000_I2CPARAMS, i2cctl);
612 wrfl();
613
614}
615
b980ac18
JK		 616/**
617 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 618 * @data: pointer to hardware structure
619 * @state: state to set clock
620 *
621 * Sets the I2C clock line to state
b980ac18 622 **/
441fc6fd
CW		 623static void igb_set_i2c_clk(void *data, int state)
624{
625 struct igb_adapter *adapter = (struct igb_adapter *)data;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 i2cctl = rd32(E1000_I2CPARAMS);
628
629 if (state) {
630 i2cctl |= E1000_I2C_CLK_OUT;
631 i2cctl &= ~E1000_I2C_CLK_OE_N;
632 } else {
633 i2cctl &= ~E1000_I2C_CLK_OUT;
634 i2cctl &= ~E1000_I2C_CLK_OE_N;
635 }
636 wr32(E1000_I2CPARAMS, i2cctl);
637 wrfl();
638}
639
b980ac18
JK		 640/**
641 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 642 * @data: pointer to hardware structure
643 *
644 * Gets the I2C clock state
b980ac18 645 **/
441fc6fd
CW		 646static int igb_get_i2c_clk(void *data)
647{
648 struct igb_adapter *adapter = (struct igb_adapter *)data;
649 struct e1000_hw *hw = &adapter->hw;
650 s32 i2cctl = rd32(E1000_I2CPARAMS);
651
652 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
653}
654
655static const struct i2c_algo_bit_data igb_i2c_algo = {
656 .setsda = igb_set_i2c_data,
657 .setscl = igb_set_i2c_clk,
658 .getsda = igb_get_i2c_data,
659 .getscl = igb_get_i2c_clk,
660 .udelay = 5,
661 .timeout = 20,
662};
663
9d5c8243 664/**
b980ac18
JK		 665 * igb_get_hw_dev - return device
666 * @hw: pointer to hardware structure
667 *
668 * used by hardware layer to print debugging information
9d5c8243 669 **/
c041076a 670struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 671{
672 struct igb_adapter *adapter = hw->back;
c041076a 673 return adapter->netdev;
9d5c8243 674}
38c845c7 675
9d5c8243 676/**
b980ac18 677 * igb_init_module - Driver Registration Routine
9d5c8243 678 *
b980ac18
JK		 679 * igb_init_module is the first routine called when the driver is
680 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 681 **/
682static int __init igb_init_module(void)
683{
684 int ret;
876d2d6f 685 pr_info("%s - version %s\n",
9d5c8243
AK		 686 igb_driver_string, igb_driver_version);
687
876d2d6f 688 pr_info("%s\n", igb_copyright);
9d5c8243 689
421e02f0 690#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 691 dca_register_notify(&dca_notifier);
692#endif
bbd98fe4 693 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 694 return ret;
695}
696
697module_init(igb_init_module);
698
699/**
b980ac18 700 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 701 *
b980ac18
JK		 702 * igb_exit_module is called just before the driver is removed
703 * from memory.
9d5c8243
AK		 704 **/
705static void __exit igb_exit_module(void)
706{
421e02f0 707#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 708 dca_unregister_notify(&dca_notifier);
709#endif
9d5c8243
AK		 710 pci_unregister_driver(&igb_driver);
711}
712
713module_exit(igb_exit_module);
714
26bc19ec
AD		 715#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
716/**
b980ac18
JK		 717 * igb_cache_ring_register - Descriptor ring to register mapping
718 * @adapter: board private structure to initialize
26bc19ec 719 *
b980ac18
JK		 720 * Once we know the feature-set enabled for the device, we'll cache
721 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 722 **/
723static void igb_cache_ring_register(struct igb_adapter *adapter)
724{
ee1b9f06 725 int i = 0, j = 0;
047e0030 726 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 727
728 switch (adapter->hw.mac.type) {
729 case e1000_82576:
730 /* The queues are allocated for virtualization such that VF 0
731 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
732 * In order to avoid collision we start at the first free queue
733 * and continue consuming queues in the same sequence
734 */
ee1b9f06 735 if (adapter->vfs_allocated_count) {
a99955fc 736 for (; i < adapter->rss_queues; i++)
3025a446 737 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 738 Q_IDX_82576(i);
ee1b9f06 739 }
26bc19ec 740 case e1000_82575:
55cac248 741 case e1000_82580:
d2ba2ed8 742 case e1000_i350:
ceb5f13b 743 case e1000_i354:
f96a8a0b
CW		 744 case e1000_i210:
745 case e1000_i211:
26bc19ec 746 default:
ee1b9f06 747 for (; i < adapter->num_rx_queues; i++)
3025a446 748 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 749 for (; j < adapter->num_tx_queues; j++)
3025a446 750 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 751 break;
752 }
753}
754
4be000c8
AD		 755/**
756 * igb_write_ivar - configure ivar for given MSI-X vector
757 * @hw: pointer to the HW structure
758 * @msix_vector: vector number we are allocating to a given ring
759 * @index: row index of IVAR register to write within IVAR table
760 * @offset: column offset of in IVAR, should be multiple of 8
761 *
762 * This function is intended to handle the writing of the IVAR register
763 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
764 * each containing an cause allocation for an Rx and Tx ring, and a
765 * variable number of rows depending on the number of queues supported.
766 **/
767static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
768 int index, int offset)
769{
770 u32 ivar = array_rd32(E1000_IVAR0, index);
771
772 /* clear any bits that are currently set */
773 ivar &= ~((u32)0xFF << offset);
774
775 /* write vector and valid bit */
776 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
777
778 array_wr32(E1000_IVAR0, index, ivar);
779}
780
9d5c8243 781#define IGB_N0_QUEUE -1
047e0030 782static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 783{
047e0030 784 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 785 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 786 int rx_queue = IGB_N0_QUEUE;
787 int tx_queue = IGB_N0_QUEUE;
4be000c8 788 u32 msixbm = 0;
047e0030 789
0ba82994
AD		 790 if (q_vector->rx.ring)
791 rx_queue = q_vector->rx.ring->reg_idx;
792 if (q_vector->tx.ring)
793 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 794
795 switch (hw->mac.type) {
796 case e1000_82575:
9d5c8243 797 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 798 * bitmask for the EICR/EIMS/EIMC registers. To assign one
799 * or more queues to a vector, we write the appropriate bits
800 * into the MSIXBM register for that vector.
801 */
047e0030 802 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 803 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 804 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 805 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 806 if (!adapter->msix_entries && msix_vector == 0)
807 msixbm |= E1000_EIMS_OTHER;
9d5c8243 808 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 809 q_vector->eims_value = msixbm;
2d064c06
AD		 810 break;
811 case e1000_82576:
b980ac18 812 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 813 * with 8 rows. The ordering is column-major so we use the
814 * lower 3 bits as the row index, and the 4th bit as the
815 * column offset.
816 */
817 if (rx_queue > IGB_N0_QUEUE)
818 igb_write_ivar(hw, msix_vector,
819 rx_queue & 0x7,
820 (rx_queue & 0x8) << 1);
821 if (tx_queue > IGB_N0_QUEUE)
822 igb_write_ivar(hw, msix_vector,
823 tx_queue & 0x7,
824 ((tx_queue & 0x8) << 1) + 8);
047e0030 825 q_vector->eims_value = 1 << msix_vector;
2d064c06 826 break;
55cac248 827 case e1000_82580:
d2ba2ed8 828 case e1000_i350:
ceb5f13b 829 case e1000_i354:
f96a8a0b
CW		 830 case e1000_i210:
831 case e1000_i211:
b980ac18 832 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 833 * however instead of ordering column-major we have things
834 * ordered row-major. So we traverse the table by using
835 * bit 0 as the column offset, and the remaining bits as the
836 * row index.
837 */
838 if (rx_queue > IGB_N0_QUEUE)
839 igb_write_ivar(hw, msix_vector,
840 rx_queue >> 1,
841 (rx_queue & 0x1) << 4);
842 if (tx_queue > IGB_N0_QUEUE)
843 igb_write_ivar(hw, msix_vector,
844 tx_queue >> 1,
845 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 846 q_vector->eims_value = 1 << msix_vector;
847 break;
2d064c06
AD		 848 default:
849 BUG();
850 break;
851 }
26b39276
AD		 852
853 /* add q_vector eims value to global eims_enable_mask */
854 adapter->eims_enable_mask |= q_vector->eims_value;
855
856 /* configure q_vector to set itr on first interrupt */
857 q_vector->set_itr = 1;
9d5c8243
AK		 858}
859
860/**
b980ac18
JK		 861 * igb_configure_msix - Configure MSI-X hardware
862 * @adapter: board private structure to initialize
9d5c8243 863 *
b980ac18
JK		 864 * igb_configure_msix sets up the hardware to properly
865 * generate MSI-X interrupts.
9d5c8243
AK		 866 **/
867static void igb_configure_msix(struct igb_adapter *adapter)
868{
869 u32 tmp;
870 int i, vector = 0;
871 struct e1000_hw *hw = &adapter->hw;
872
873 adapter->eims_enable_mask = 0;
9d5c8243
AK		 874
875 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 876 switch (hw->mac.type) {
877 case e1000_82575:
9d5c8243
AK		 878 tmp = rd32(E1000_CTRL_EXT);
879 /* enable MSI-X PBA support*/
880 tmp |= E1000_CTRL_EXT_PBA_CLR;
881
882 /* Auto-Mask interrupts upon ICR read. */
883 tmp |= E1000_CTRL_EXT_EIAME;
884 tmp |= E1000_CTRL_EXT_IRCA;
885
886 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 887
888 /* enable msix_other interrupt */
b980ac18 889 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 890 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 891
2d064c06
AD		 892 break;
893
894 case e1000_82576:
55cac248 895 case e1000_82580:
d2ba2ed8 896 case e1000_i350:
ceb5f13b 897 case e1000_i354:
f96a8a0b
CW		 898 case e1000_i210:
899 case e1000_i211:
047e0030 900 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 901 * won't stick. And it will take days to debug.
902 */
047e0030 903 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 904 E1000_GPIE_PBA | E1000_GPIE_EIAME |
905 E1000_GPIE_NSICR);
047e0030
AD		 906
907 /* enable msix_other interrupt */
908 adapter->eims_other = 1 << vector;
2d064c06 909 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 910
047e0030 911 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 912 break;
913 default:
914 /* do nothing, since nothing else supports MSI-X */
915 break;
916 } /* switch (hw->mac.type) */
047e0030
AD		 917
918 adapter->eims_enable_mask |= adapter->eims_other;
919
26b39276
AD		 920 for (i = 0; i < adapter->num_q_vectors; i++)
921 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 922
9d5c8243
AK		 923 wrfl();
924}
925
926/**
b980ac18
JK		 927 * igb_request_msix - Initialize MSI-X interrupts
928 * @adapter: board private structure to initialize
9d5c8243 929 *
b980ac18
JK		 930 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
931 * kernel.
9d5c8243
AK		 932 **/
933static int igb_request_msix(struct igb_adapter *adapter)
934{
935 struct net_device *netdev = adapter->netdev;
047e0030 936 struct e1000_hw *hw = &adapter->hw;
52285b76 937 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 938
047e0030 939 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 940 igb_msix_other, 0, netdev->name, adapter);
047e0030 941 if (err)
52285b76 942 goto err_out;
047e0030
AD		 943
944 for (i = 0; i < adapter->num_q_vectors; i++) {
945 struct igb_q_vector *q_vector = adapter->q_vector[i];
946
52285b76
SA		 947 vector++;
948
047e0030
AD		 949 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
950
0ba82994 951 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 952 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 953 q_vector->rx.ring->queue_index);
954 else if (q_vector->tx.ring)
047e0030 955 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 956 q_vector->tx.ring->queue_index);
957 else if (q_vector->rx.ring)
047e0030 958 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 959 q_vector->rx.ring->queue_index);
9d5c8243 960 else
047e0030
AD		 961 sprintf(q_vector->name, "%s-unused", netdev->name);
962
9d5c8243 963 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 964 igb_msix_ring, 0, q_vector->name,
965 q_vector);
9d5c8243 966 if (err)
52285b76 967 goto err_free;
9d5c8243
AK		 968 }
969
9d5c8243
AK		 970 igb_configure_msix(adapter);
971 return 0;
52285b76
SA		 972
973err_free:
974 /* free already assigned IRQs */
975 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
976
977 vector--;
978 for (i = 0; i < vector; i++) {
979 free_irq(adapter->msix_entries[free_vector++].vector,
980 adapter->q_vector[i]);
981 }
982err_out:
9d5c8243
AK		 983 return err;
984}
985
5536d210 986/**
b980ac18
JK		 987 * igb_free_q_vector - Free memory allocated for specific interrupt vector
988 * @adapter: board private structure to initialize
989 * @v_idx: Index of vector to be freed
5536d210 990 *
02ef6e1d 991 * This function frees the memory allocated to the q_vector.
5536d210
AD		 992 **/
993static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
994{
995 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
996
02ef6e1d
CW		 997 adapter->q_vector[v_idx] = NULL;
998
999 /* igb_get_stats64() might access the rings on this vector,
1000 * we must wait a grace period before freeing it.
1001 */
1002 kfree_rcu(q_vector, rcu);
1003}
1004
1005/**
1006 * igb_reset_q_vector - Reset config for interrupt vector
1007 * @adapter: board private structure to initialize
1008 * @v_idx: Index of vector to be reset
1009 *
1010 * If NAPI is enabled it will delete any references to the
1011 * NAPI struct. This is preparation for igb_free_q_vector.
1012 **/
1013static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1014{
1015 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1016
5536d210
AD		 1017 if (q_vector->tx.ring)
1018 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1019
1020 if (q_vector->rx.ring)
1021 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1022
5536d210
AD		 1023 netif_napi_del(&q_vector->napi);
1024
02ef6e1d
CW		 1025}
1026
1027static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1028{
1029 int v_idx = adapter->num_q_vectors;
1030
1031 if (adapter->msix_entries) {
1032 pci_disable_msix(adapter->pdev);
1033 kfree(adapter->msix_entries);
1034 adapter->msix_entries = NULL;
1035 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1036 pci_disable_msi(adapter->pdev);
1037 }
1038
1039 while (v_idx--)
1040 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1041}
1042
047e0030 1043/**
b980ac18
JK		 1044 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1045 * @adapter: board private structure to initialize
047e0030 1046 *
b980ac18
JK		 1047 * This function frees the memory allocated to the q_vectors. In addition if
1048 * NAPI is enabled it will delete any references to the NAPI struct prior
1049 * to freeing the q_vector.
047e0030
AD		 1050 **/
1051static void igb_free_q_vectors(struct igb_adapter *adapter)
1052{
5536d210
AD		 1053 int v_idx = adapter->num_q_vectors;
1054
1055 adapter->num_tx_queues = 0;
1056 adapter->num_rx_queues = 0;
047e0030 1057 adapter->num_q_vectors = 0;
5536d210 1058
02ef6e1d
CW		 1059 while (v_idx--) {
1060 igb_reset_q_vector(adapter, v_idx);
5536d210 1061 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1062 }
047e0030
AD		 1063}
1064
1065/**
b980ac18
JK		 1066 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1067 * @adapter: board private structure to initialize
047e0030 1068 *
b980ac18
JK		 1069 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1070 * MSI-X interrupts allocated.
047e0030
AD		 1071 */
1072static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1073{
047e0030
AD		 1074 igb_free_q_vectors(adapter);
1075 igb_reset_interrupt_capability(adapter);
1076}
9d5c8243
AK		 1077
1078/**
b980ac18
JK		 1079 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1080 * @adapter: board private structure to initialize
1081 * @msix: boolean value of MSIX capability
9d5c8243 1082 *
b980ac18
JK		 1083 * Attempt to configure interrupts using the best available
1084 * capabilities of the hardware and kernel.
9d5c8243 1085 **/
53c7d064 1086static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1087{
1088 int err;
1089 int numvecs, i;
1090
53c7d064
SA		 1091 if (!msix)
1092 goto msi_only;
1093
83b7180d 1094 /* Number of supported queues. */
a99955fc 1095 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1096 if (adapter->vfs_allocated_count)
1097 adapter->num_tx_queues = 1;
1098 else
1099 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1100
b980ac18 1101 /* start with one vector for every Rx queue */
047e0030
AD		 1102 numvecs = adapter->num_rx_queues;
1103
b980ac18 1104 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1105 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1106 numvecs += adapter->num_tx_queues;
047e0030
AD		 1107
1108 /* store the number of vectors reserved for queues */
1109 adapter->num_q_vectors = numvecs;
1110
1111 /* add 1 vector for link status interrupts */
1112 numvecs++;
9d5c8243
AK		 1113 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1114 GFP_KERNEL);
f96a8a0b 1115
9d5c8243
AK		 1116 if (!adapter->msix_entries)
1117 goto msi_only;
1118
1119 for (i = 0; i < numvecs; i++)
1120 adapter->msix_entries[i].entry = i;
1121
1122 err = pci_enable_msix(adapter->pdev,
1123 adapter->msix_entries,
1124 numvecs);
1125 if (err == 0)
0c2cc02e 1126 return;
9d5c8243
AK		 1127
1128 igb_reset_interrupt_capability(adapter);
1129
1130 /* If we can't do MSI-X, try MSI */
1131msi_only:
2a3abf6d
AD		 1132#ifdef CONFIG_PCI_IOV
1133 /* disable SR-IOV for non MSI-X configurations */
1134 if (adapter->vf_data) {
1135 struct e1000_hw *hw = &adapter->hw;
1136 /* disable iov and allow time for transactions to clear */
1137 pci_disable_sriov(adapter->pdev);
1138 msleep(500);
1139
1140 kfree(adapter->vf_data);
1141 adapter->vf_data = NULL;
1142 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1143 wrfl();
2a3abf6d
AD		 1144 msleep(100);
1145 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1146 }
1147#endif
4fc82adf 1148 adapter->vfs_allocated_count = 0;
a99955fc 1149 adapter->rss_queues = 1;
4fc82adf 1150 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1151 adapter->num_rx_queues = 1;
661086df 1152 adapter->num_tx_queues = 1;
047e0030 1153 adapter->num_q_vectors = 1;
9d5c8243 1154 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1155 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1156}
1157
5536d210
AD		 1158static void igb_add_ring(struct igb_ring *ring,
1159 struct igb_ring_container *head)
1160{
1161 head->ring = ring;
1162 head->count++;
1163}
1164
047e0030 1165/**
b980ac18
JK		 1166 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1167 * @adapter: board private structure to initialize
1168 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1169 * @v_idx: index of vector in adapter struct
1170 * @txr_count: total number of Tx rings to allocate
1171 * @txr_idx: index of first Tx ring to allocate
1172 * @rxr_count: total number of Rx rings to allocate
1173 * @rxr_idx: index of first Rx ring to allocate
047e0030 1174 *
b980ac18 1175 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1176 **/
5536d210
AD		 1177static int igb_alloc_q_vector(struct igb_adapter *adapter,
1178 int v_count, int v_idx,
1179 int txr_count, int txr_idx,
1180 int rxr_count, int rxr_idx)
047e0030
AD		 1181{
1182 struct igb_q_vector *q_vector;
5536d210
AD		 1183 struct igb_ring *ring;
1184 int ring_count, size;
047e0030 1185
5536d210
AD		 1186 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1187 if (txr_count > 1 || rxr_count > 1)
1188 return -ENOMEM;
1189
1190 ring_count = txr_count + rxr_count;
1191 size = sizeof(struct igb_q_vector) +
1192 (sizeof(struct igb_ring) * ring_count);
1193
1194 /* allocate q_vector and rings */
02ef6e1d
CW		 1195 q_vector = adapter->q_vector[v_idx];
1196 if (!q_vector)
1197 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1198 if (!q_vector)
1199 return -ENOMEM;
1200
1201 /* initialize NAPI */
1202 netif_napi_add(adapter->netdev, &q_vector->napi,
1203 igb_poll, 64);
1204
1205 /* tie q_vector and adapter together */
1206 adapter->q_vector[v_idx] = q_vector;
1207 q_vector->adapter = adapter;
1208
1209 /* initialize work limits */
1210 q_vector->tx.work_limit = adapter->tx_work_limit;
1211
1212 /* initialize ITR configuration */
1213 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1214 q_vector->itr_val = IGB_START_ITR;
1215
1216 /* initialize pointer to rings */
1217 ring = q_vector->ring;
1218
4e227667
AD		 1219 /* intialize ITR */
1220 if (rxr_count) {
1221 /* rx or rx/tx vector */
1222 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1223 q_vector->itr_val = adapter->rx_itr_setting;
1224 } else {
1225 /* tx only vector */
1226 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1227 q_vector->itr_val = adapter->tx_itr_setting;
1228 }
1229
5536d210
AD		 1230 if (txr_count) {
1231 /* assign generic ring traits */
1232 ring->dev = &adapter->pdev->dev;
1233 ring->netdev = adapter->netdev;
1234
1235 /* configure backlink on ring */
1236 ring->q_vector = q_vector;
1237
1238 /* update q_vector Tx values */
1239 igb_add_ring(ring, &q_vector->tx);
1240
1241 /* For 82575, context index must be unique per ring. */
1242 if (adapter->hw.mac.type == e1000_82575)
1243 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1244
1245 /* apply Tx specific ring traits */
1246 ring->count = adapter->tx_ring_count;
1247 ring->queue_index = txr_idx;
1248
827da44c
JS		 1249 u64_stats_init(&ring->tx_syncp);
1250 u64_stats_init(&ring->tx_syncp2);
1251
5536d210
AD		 1252 /* assign ring to adapter */
1253 adapter->tx_ring[txr_idx] = ring;
1254
1255 /* push pointer to next ring */
1256 ring++;
047e0030 1257 }
81c2fc22 1258
5536d210
AD		 1259 if (rxr_count) {
1260 /* assign generic ring traits */
1261 ring->dev = &adapter->pdev->dev;
1262 ring->netdev = adapter->netdev;
047e0030 1263
5536d210
AD		 1264 /* configure backlink on ring */
1265 ring->q_vector = q_vector;
047e0030 1266
5536d210
AD		 1267 /* update q_vector Rx values */
1268 igb_add_ring(ring, &q_vector->rx);
047e0030 1269
5536d210
AD		 1270 /* set flag indicating ring supports SCTP checksum offload */
1271 if (adapter->hw.mac.type >= e1000_82576)
1272 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1273
ceb5f13b
CW		 1274 /*
1275 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1276 * have the tag byte-swapped.
b980ac18 1277 */
5536d210
AD		 1278 if (adapter->hw.mac.type >= e1000_i350)
1279 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1280
5536d210
AD		 1281 /* apply Rx specific ring traits */
1282 ring->count = adapter->rx_ring_count;
1283 ring->queue_index = rxr_idx;
1284
827da44c
JS		 1285 u64_stats_init(&ring->rx_syncp);
1286
5536d210
AD		 1287 /* assign ring to adapter */
1288 adapter->rx_ring[rxr_idx] = ring;
1289 }
1290
1291 return 0;
047e0030
AD		 1292}
1293
5536d210 1294
047e0030 1295/**
b980ac18
JK		 1296 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1297 * @adapter: board private structure to initialize
047e0030 1298 *
b980ac18
JK		 1299 * We allocate one q_vector per queue interrupt. If allocation fails we
1300 * return -ENOMEM.
047e0030 1301 **/
5536d210 1302static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1303{
5536d210
AD		 1304 int q_vectors = adapter->num_q_vectors;
1305 int rxr_remaining = adapter->num_rx_queues;
1306 int txr_remaining = adapter->num_tx_queues;
1307 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1308 int err;
047e0030 1309
5536d210
AD		 1310 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1311 for (; rxr_remaining; v_idx++) {
1312 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1313 0, 0, 1, rxr_idx);
047e0030 1314
5536d210
AD		 1315 if (err)
1316 goto err_out;
1317
1318 /* update counts and index */
1319 rxr_remaining--;
1320 rxr_idx++;
047e0030 1321 }
047e0030 1322 }
5536d210
AD		 1323
1324 for (; v_idx < q_vectors; v_idx++) {
1325 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1326 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1327 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1328 tqpv, txr_idx, rqpv, rxr_idx);
1329
1330 if (err)
1331 goto err_out;
1332
1333 /* update counts and index */
1334 rxr_remaining -= rqpv;
1335 txr_remaining -= tqpv;
1336 rxr_idx++;
1337 txr_idx++;
1338 }
1339
047e0030 1340 return 0;
5536d210
AD		 1341
1342err_out:
1343 adapter->num_tx_queues = 0;
1344 adapter->num_rx_queues = 0;
1345 adapter->num_q_vectors = 0;
1346
1347 while (v_idx--)
1348 igb_free_q_vector(adapter, v_idx);
1349
1350 return -ENOMEM;
047e0030
AD		 1351}
1352
1353/**
b980ac18
JK		 1354 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1355 * @adapter: board private structure to initialize
1356 * @msix: boolean value of MSIX capability
047e0030 1357 *
b980ac18 1358 * This function initializes the interrupts and allocates all of the queues.
047e0030 1359 **/
53c7d064 1360static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1361{
1362 struct pci_dev *pdev = adapter->pdev;
1363 int err;
1364
53c7d064 1365 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1366
1367 err = igb_alloc_q_vectors(adapter);
1368 if (err) {
1369 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1370 goto err_alloc_q_vectors;
1371 }
1372
5536d210 1373 igb_cache_ring_register(adapter);
047e0030
AD		 1374
1375 return 0;
5536d210 1376
047e0030
AD		 1377err_alloc_q_vectors:
1378 igb_reset_interrupt_capability(adapter);
1379 return err;
1380}
1381
9d5c8243 1382/**
b980ac18
JK		 1383 * igb_request_irq - initialize interrupts
1384 * @adapter: board private structure to initialize
9d5c8243 1385 *
b980ac18
JK		 1386 * Attempts to configure interrupts using the best available
1387 * capabilities of the hardware and kernel.
9d5c8243
AK		 1388 **/
1389static int igb_request_irq(struct igb_adapter *adapter)
1390{
1391 struct net_device *netdev = adapter->netdev;
047e0030 1392 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1393 int err = 0;
1394
1395 if (adapter->msix_entries) {
1396 err = igb_request_msix(adapter);
844290e5 1397 if (!err)
9d5c8243 1398 goto request_done;
9d5c8243 1399 /* fall back to MSI */
5536d210
AD		 1400 igb_free_all_tx_resources(adapter);
1401 igb_free_all_rx_resources(adapter);
53c7d064 1402
047e0030 1403 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1404 err = igb_init_interrupt_scheme(adapter, false);
1405 if (err)
047e0030 1406 goto request_done;
53c7d064 1407
047e0030
AD		 1408 igb_setup_all_tx_resources(adapter);
1409 igb_setup_all_rx_resources(adapter);
53c7d064 1410 igb_configure(adapter);
9d5c8243 1411 }
844290e5 1412
c74d588e
AD		 1413 igb_assign_vector(adapter->q_vector[0], 0);
1414
7dfc16fa 1415 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1416 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1417 netdev->name, adapter);
9d5c8243
AK		 1418 if (!err)
1419 goto request_done;
047e0030 1420
9d5c8243
AK		 1421 /* fall back to legacy interrupts */
1422 igb_reset_interrupt_capability(adapter);
7dfc16fa 1423 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1424 }
1425
c74d588e 1426 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1427 netdev->name, adapter);
9d5c8243 1428
6cb5e577 1429 if (err)
c74d588e 1430 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1431 err);
9d5c8243
AK		 1432
1433request_done:
1434 return err;
1435}
1436
1437static void igb_free_irq(struct igb_adapter *adapter)
1438{
9d5c8243
AK		 1439 if (adapter->msix_entries) {
1440 int vector = 0, i;
1441
047e0030 1442 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1443
0d1ae7f4 1444 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1445 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1446 adapter->q_vector[i]);
047e0030
AD		 1447 } else {
1448 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1449 }
9d5c8243
AK		 1450}
1451
1452/**
b980ac18
JK		 1453 * igb_irq_disable - Mask off interrupt generation on the NIC
1454 * @adapter: board private structure
9d5c8243
AK		 1455 **/
1456static void igb_irq_disable(struct igb_adapter *adapter)
1457{
1458 struct e1000_hw *hw = &adapter->hw;
1459
b980ac18 1460 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1461 * mapped into these registers and so clearing the bits can cause
1462 * issues on the VF drivers so we only need to clear what we set
1463 */
9d5c8243 1464 if (adapter->msix_entries) {
2dfd1212
AD		 1465 u32 regval = rd32(E1000_EIAM);
1466 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1467 wr32(E1000_EIMC, adapter->eims_enable_mask);
1468 regval = rd32(E1000_EIAC);
1469 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1470 }
844290e5
PW		 1471
1472 wr32(E1000_IAM, 0);
9d5c8243
AK		 1473 wr32(E1000_IMC, ~0);
1474 wrfl();
81a61859
ET		 1475 if (adapter->msix_entries) {
1476 int i;
1477 for (i = 0; i < adapter->num_q_vectors; i++)
1478 synchronize_irq(adapter->msix_entries[i].vector);
1479 } else {
1480 synchronize_irq(adapter->pdev->irq);
1481 }
9d5c8243
AK		 1482}
1483
1484/**
b980ac18
JK		 1485 * igb_irq_enable - Enable default interrupt generation settings
1486 * @adapter: board private structure
9d5c8243
AK		 1487 **/
1488static void igb_irq_enable(struct igb_adapter *adapter)
1489{
1490 struct e1000_hw *hw = &adapter->hw;
1491
1492 if (adapter->msix_entries) {
06218a8d 1493 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1494 u32 regval = rd32(E1000_EIAC);
1495 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1496 regval = rd32(E1000_EIAM);
1497 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1498 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1499 if (adapter->vfs_allocated_count) {
4ae196df 1500 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1501 ims |= E1000_IMS_VMMB;
1502 }
1503 wr32(E1000_IMS, ims);
844290e5 1504 } else {
55cac248
AD		 1505 wr32(E1000_IMS, IMS_ENABLE_MASK |
1506 E1000_IMS_DRSTA);
1507 wr32(E1000_IAM, IMS_ENABLE_MASK |
1508 E1000_IMS_DRSTA);
844290e5 1509 }
9d5c8243
AK		 1510}
1511
1512static void igb_update_mng_vlan(struct igb_adapter *adapter)
1513{
51466239 1514 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1515 u16 vid = adapter->hw.mng_cookie.vlan_id;
1516 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1517
1518 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1519 /* add VID to filter table */
1520 igb_vfta_set(hw, vid, true);
1521 adapter->mng_vlan_id = vid;
1522 } else {
1523 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1524 }
1525
1526 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1527 (vid != old_vid) &&
b2cb09b1 1528 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1529 /* remove VID from filter table */
1530 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1531 }
1532}
1533
1534/**
b980ac18
JK		 1535 * igb_release_hw_control - release control of the h/w to f/w
1536 * @adapter: address of board private structure
9d5c8243 1537 *
b980ac18
JK		 1538 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1539 * For ASF and Pass Through versions of f/w this means that the
1540 * driver is no longer loaded.
9d5c8243
AK		 1541 **/
1542static void igb_release_hw_control(struct igb_adapter *adapter)
1543{
1544 struct e1000_hw *hw = &adapter->hw;
1545 u32 ctrl_ext;
1546
1547 /* Let firmware take over control of h/w */
1548 ctrl_ext = rd32(E1000_CTRL_EXT);
1549 wr32(E1000_CTRL_EXT,
1550 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1551}
1552
9d5c8243 1553/**
b980ac18
JK		 1554 * igb_get_hw_control - get control of the h/w from f/w
1555 * @adapter: address of board private structure
9d5c8243 1556 *
b980ac18
JK		 1557 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1558 * For ASF and Pass Through versions of f/w this means that
1559 * the driver is loaded.
9d5c8243
AK		 1560 **/
1561static void igb_get_hw_control(struct igb_adapter *adapter)
1562{
1563 struct e1000_hw *hw = &adapter->hw;
1564 u32 ctrl_ext;
1565
1566 /* Let firmware know the driver has taken over */
1567 ctrl_ext = rd32(E1000_CTRL_EXT);
1568 wr32(E1000_CTRL_EXT,
1569 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1570}
1571
9d5c8243 1572/**
b980ac18
JK		 1573 * igb_configure - configure the hardware for RX and TX
1574 * @adapter: private board structure
9d5c8243
AK		 1575 **/
1576static void igb_configure(struct igb_adapter *adapter)
1577{
1578 struct net_device *netdev = adapter->netdev;
1579 int i;
1580
1581 igb_get_hw_control(adapter);
ff41f8dc 1582 igb_set_rx_mode(netdev);
9d5c8243
AK		 1583
1584 igb_restore_vlan(adapter);
9d5c8243 1585
85b430b4 1586 igb_setup_tctl(adapter);
06cf2666 1587 igb_setup_mrqc(adapter);
9d5c8243 1588 igb_setup_rctl(adapter);
85b430b4
AD		 1589
1590 igb_configure_tx(adapter);
9d5c8243 1591 igb_configure_rx(adapter);
662d7205
AD		 1592
1593 igb_rx_fifo_flush_82575(&adapter->hw);
1594
c493ea45 1595 /* call igb_desc_unused which always leaves
9d5c8243 1596 * at least 1 descriptor unused to make sure
b980ac18
JK		 1597 * next_to_use != next_to_clean
1598 */
9d5c8243 1599 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1600 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1601 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1602 }
9d5c8243
AK		 1603}
1604
88a268c1 1605/**
b980ac18
JK		 1606 * igb_power_up_link - Power up the phy/serdes link
1607 * @adapter: address of board private structure
88a268c1
NN		 1608 **/
1609void igb_power_up_link(struct igb_adapter *adapter)
1610{
76886596
AA		 1611 igb_reset_phy(&adapter->hw);
1612
88a268c1
NN		 1613 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1614 igb_power_up_phy_copper(&adapter->hw);
1615 else
1616 igb_power_up_serdes_link_82575(&adapter->hw);
1617}
1618
1619/**
b980ac18
JK		 1620 * igb_power_down_link - Power down the phy/serdes link
1621 * @adapter: address of board private structure
88a268c1
NN		 1622 */
1623static void igb_power_down_link(struct igb_adapter *adapter)
1624{
1625 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1626 igb_power_down_phy_copper_82575(&adapter->hw);
1627 else
1628 igb_shutdown_serdes_link_82575(&adapter->hw);
1629}
9d5c8243 1630
56cec249
CW		 1631/**
1632 * Detect and switch function for Media Auto Sense
1633 * @adapter: address of the board private structure
1634 **/
1635static void igb_check_swap_media(struct igb_adapter *adapter)
1636{
1637 struct e1000_hw *hw = &adapter->hw;
1638 u32 ctrl_ext, connsw;
1639 bool swap_now = false;
1640
1641 ctrl_ext = rd32(E1000_CTRL_EXT);
1642 connsw = rd32(E1000_CONNSW);
1643
1644 /* need to live swap if current media is copper and we have fiber/serdes
1645 * to go to.
1646 */
1647
1648 if ((hw->phy.media_type == e1000_media_type_copper) &&
1649 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1650 swap_now = true;
1651 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1652 /* copper signal takes time to appear */
1653 if (adapter->copper_tries < 4) {
1654 adapter->copper_tries++;
1655 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1656 wr32(E1000_CONNSW, connsw);
1657 return;
1658 } else {
1659 adapter->copper_tries = 0;
1660 if ((connsw & E1000_CONNSW_PHYSD) &&
1661 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1662 swap_now = true;
1663 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1664 wr32(E1000_CONNSW, connsw);
1665 }
1666 }
1667 }
1668
1669 if (!swap_now)
1670 return;
1671
1672 switch (hw->phy.media_type) {
1673 case e1000_media_type_copper:
1674 netdev_info(adapter->netdev,
1675 "MAS: changing media to fiber/serdes\n");
1676 ctrl_ext |=
1677 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1678 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1679 adapter->copper_tries = 0;
1680 break;
1681 case e1000_media_type_internal_serdes:
1682 case e1000_media_type_fiber:
1683 netdev_info(adapter->netdev,
1684 "MAS: changing media to copper\n");
1685 ctrl_ext &=
1686 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1687 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1688 break;
1689 default:
1690 /* shouldn't get here during regular operation */
1691 netdev_err(adapter->netdev,
1692 "AMS: Invalid media type found, returning\n");
1693 break;
1694 }
1695 wr32(E1000_CTRL_EXT, ctrl_ext);
1696}
1697
9d5c8243 1698/**
b980ac18
JK		 1699 * igb_up - Open the interface and prepare it to handle traffic
1700 * @adapter: board private structure
9d5c8243 1701 **/
9d5c8243
AK		 1702int igb_up(struct igb_adapter *adapter)
1703{
1704 struct e1000_hw *hw = &adapter->hw;
1705 int i;
1706
1707 /* hardware has been reset, we need to reload some things */
1708 igb_configure(adapter);
1709
1710 clear_bit(__IGB_DOWN, &adapter->state);
1711
0d1ae7f4
AD		 1712 for (i = 0; i < adapter->num_q_vectors; i++)
1713 napi_enable(&(adapter->q_vector[i]->napi));
1714
844290e5 1715 if (adapter->msix_entries)
9d5c8243 1716 igb_configure_msix(adapter);
feeb2721
AD		 1717 else
1718 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1719
1720 /* Clear any pending interrupts. */
1721 rd32(E1000_ICR);
1722 igb_irq_enable(adapter);
1723
d4960307
AD		 1724 /* notify VFs that reset has been completed */
1725 if (adapter->vfs_allocated_count) {
1726 u32 reg_data = rd32(E1000_CTRL_EXT);
1727 reg_data |= E1000_CTRL_EXT_PFRSTD;
1728 wr32(E1000_CTRL_EXT, reg_data);
1729 }
1730
4cb9be7a
JB		 1731 netif_tx_start_all_queues(adapter->netdev);
1732
25568a53
AD		 1733 /* start the watchdog. */
1734 hw->mac.get_link_status = 1;
1735 schedule_work(&adapter->watchdog_task);
1736
9d5c8243
AK		 1737 return 0;
1738}
1739
1740void igb_down(struct igb_adapter *adapter)
1741{
9d5c8243 1742 struct net_device *netdev = adapter->netdev;
330a6d6a 1743 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1744 u32 tctl, rctl;
1745 int i;
1746
1747 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1748 * reschedule our watchdog timer
1749 */
9d5c8243
AK		 1750 set_bit(__IGB_DOWN, &adapter->state);
1751
1752 /* disable receives in the hardware */
1753 rctl = rd32(E1000_RCTL);
1754 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1755 /* flush and sleep below */
1756
fd2ea0a7 1757 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1758
1759 /* disable transmits in the hardware */
1760 tctl = rd32(E1000_TCTL);
1761 tctl &= ~E1000_TCTL_EN;
1762 wr32(E1000_TCTL, tctl);
1763 /* flush both disables and wait for them to finish */
1764 wrfl();
1765 msleep(10);
1766
41f149a2
CW		 1767 igb_irq_disable(adapter);
1768
aa9b8cc4
AA		 1769 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1770
41f149a2
CW		 1771 for (i = 0; i < adapter->num_q_vectors; i++) {
1772 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1773 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1774 }
9d5c8243 1775
9d5c8243
AK		 1776
1777 del_timer_sync(&adapter->watchdog_timer);
1778 del_timer_sync(&adapter->phy_info_timer);
1779
9d5c8243 1780 netif_carrier_off(netdev);
04fe6358
AD		 1781
1782 /* record the stats before reset*/
12dcd86b
ED		 1783 spin_lock(&adapter->stats64_lock);
1784 igb_update_stats(adapter, &adapter->stats64);
1785 spin_unlock(&adapter->stats64_lock);
04fe6358 1786
9d5c8243
AK		 1787 adapter->link_speed = 0;
1788 adapter->link_duplex = 0;
1789
3023682e
JK		 1790 if (!pci_channel_offline(adapter->pdev))
1791 igb_reset(adapter);
9d5c8243
AK		 1792 igb_clean_all_tx_rings(adapter);
1793 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1794#ifdef CONFIG_IGB_DCA
1795
1796 /* since we reset the hardware DCA settings were cleared */
1797 igb_setup_dca(adapter);
1798#endif
9d5c8243
AK		 1799}
1800
1801void igb_reinit_locked(struct igb_adapter *adapter)
1802{
1803 WARN_ON(in_interrupt());
1804 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1805 msleep(1);
1806 igb_down(adapter);
1807 igb_up(adapter);
1808 clear_bit(__IGB_RESETTING, &adapter->state);
1809}
1810
56cec249
CW		 1811/** igb_enable_mas - Media Autosense re-enable after swap
1812 *
1813 * @adapter: adapter struct
1814 **/
1815static s32 igb_enable_mas(struct igb_adapter *adapter)
1816{
1817 struct e1000_hw *hw = &adapter->hw;
1818 u32 connsw;
1819 s32 ret_val = 0;
1820
1821 connsw = rd32(E1000_CONNSW);
1822 if (!(hw->phy.media_type == e1000_media_type_copper))
1823 return ret_val;
1824
1825 /* configure for SerDes media detect */
1826 if (!(connsw & E1000_CONNSW_SERDESD)) {
1827 connsw |= E1000_CONNSW_ENRGSRC;
1828 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1829 wr32(E1000_CONNSW, connsw);
1830 wrfl();
1831 } else if (connsw & E1000_CONNSW_SERDESD) {
1832 /* already SerDes, no need to enable anything */
1833 return ret_val;
1834 } else {
1835 netdev_info(adapter->netdev,
1836 "MAS: Unable to configure feature, disabling..\n");
1837 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1838 }
1839 return ret_val;
1840}
1841
9d5c8243
AK		 1842void igb_reset(struct igb_adapter *adapter)
1843{
090b1795 1844 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1845 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1846 struct e1000_mac_info *mac = &hw->mac;
1847 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1848 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1849
1850 /* Repartition Pba for greater than 9k mtu
1851 * To take effect CTRL.RST is required.
1852 */
fa4dfae0 1853 switch (mac->type) {
d2ba2ed8 1854 case e1000_i350:
ceb5f13b 1855 case e1000_i354:
55cac248
AD		 1856 case e1000_82580:
1857 pba = rd32(E1000_RXPBS);
1858 pba = igb_rxpbs_adjust_82580(pba);
1859 break;
fa4dfae0 1860 case e1000_82576:
d249be54
AD		 1861 pba = rd32(E1000_RXPBS);
1862 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1863 break;
1864 case e1000_82575:
f96a8a0b
CW		 1865 case e1000_i210:
1866 case e1000_i211:
fa4dfae0
AD		 1867 default:
1868 pba = E1000_PBA_34K;
1869 break;
2d064c06 1870 }
9d5c8243 1871
2d064c06
AD		 1872 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1873 (mac->type < e1000_82576)) {
9d5c8243
AK		 1874 /* adjust PBA for jumbo frames */
1875 wr32(E1000_PBA, pba);
1876
1877 /* To maintain wire speed transmits, the Tx FIFO should be
1878 * large enough to accommodate two full transmit packets,
1879 * rounded up to the next 1KB and expressed in KB. Likewise,
1880 * the Rx FIFO should be large enough to accommodate at least
1881 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1882 * expressed in KB.
1883 */
9d5c8243
AK		 1884 pba = rd32(E1000_PBA);
1885 /* upper 16 bits has Tx packet buffer allocation size in KB */
1886 tx_space = pba >> 16;
1887 /* lower 16 bits has Rx packet buffer allocation size in KB */
1888 pba &= 0xffff;
b980ac18
JK		 1889 /* the Tx fifo also stores 16 bytes of information about the Tx
1890 * but don't include ethernet FCS because hardware appends it
1891 */
9d5c8243 1892 min_tx_space = (adapter->max_frame_size +
85e8d004 1893 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1894 ETH_FCS_LEN) * 2;
1895 min_tx_space = ALIGN(min_tx_space, 1024);
1896 min_tx_space >>= 10;
1897 /* software strips receive CRC, so leave room for it */
1898 min_rx_space = adapter->max_frame_size;
1899 min_rx_space = ALIGN(min_rx_space, 1024);
1900 min_rx_space >>= 10;
1901
1902 /* If current Tx allocation is less than the min Tx FIFO size,
1903 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1904 * allocation, take space away from current Rx allocation
1905 */
9d5c8243
AK		 1906 if (tx_space < min_tx_space &&
1907 ((min_tx_space - tx_space) < pba)) {
1908 pba = pba - (min_tx_space - tx_space);
1909
b980ac18
JK		 1910 /* if short on Rx space, Rx wins and must trump Tx
1911 * adjustment
1912 */
9d5c8243
AK		 1913 if (pba < min_rx_space)
1914 pba = min_rx_space;
1915 }
2d064c06 1916 wr32(E1000_PBA, pba);
9d5c8243 1917 }
9d5c8243
AK		 1918
1919 /* flow control settings */
1920 /* The high water mark must be low enough to fit one full frame
1921 * (or the size used for early receive) above it in the Rx FIFO.
1922 * Set it to the lower of:
1923 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1924 * - the full Rx FIFO size minus one full frame
1925 */
9d5c8243 1926 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1927 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1928
d48507fe 1929 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1930 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1931 fc->pause_time = 0xFFFF;
1932 fc->send_xon = 1;
0cce119a 1933 fc->current_mode = fc->requested_mode;
9d5c8243 1934
4ae196df
AD		 1935 /* disable receive for all VFs and wait one second */
1936 if (adapter->vfs_allocated_count) {
1937 int i;
1938 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1939 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1940
1941 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1942 igb_ping_all_vfs(adapter);
4ae196df
AD		 1943
1944 /* disable transmits and receives */
1945 wr32(E1000_VFRE, 0);
1946 wr32(E1000_VFTE, 0);
1947 }
1948
9d5c8243 1949 /* Allow time for pending master requests to run */
330a6d6a 1950 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1951 wr32(E1000_WUC, 0);
1952
56cec249
CW		 1953 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1954 /* need to resetup here after media swap */
1955 adapter->ei.get_invariants(hw);
1956 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1957 }
1958 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1959 if (igb_enable_mas(adapter))
1960 dev_err(&pdev->dev,
1961 "Error enabling Media Auto Sense\n");
1962 }
330a6d6a 1963 if (hw->mac.ops.init_hw(hw))
090b1795 1964 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1965
b980ac18 1966 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1967 * control is off when forcing speed.
1968 */
1969 if (!hw->mac.autoneg)
1970 igb_force_mac_fc(hw);
1971
b6e0c419 1972 igb_init_dmac(adapter, pba);
e428893b
CW		 1973#ifdef CONFIG_IGB_HWMON
1974 /* Re-initialize the thermal sensor on i350 devices. */
1975 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1976 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1977 /* If present, re-initialize the external thermal sensor
1978 * interface.
1979 */
1980 if (adapter->ets)
1981 mac->ops.init_thermal_sensor_thresh(hw);
1982 }
1983 }
1984#endif
88a268c1
NN		 1985 if (!netif_running(adapter->netdev))
1986 igb_power_down_link(adapter);
1987
9d5c8243
AK		 1988 igb_update_mng_vlan(adapter);
1989
1990 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1991 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1992
1f6e8178
MV		 1993 /* Re-enable PTP, where applicable. */
1994 igb_ptp_reset(adapter);
1f6e8178 1995
330a6d6a 1996 igb_get_phy_info(hw);
9d5c8243
AK		 1997}
1998
c8f44aff
MM		 1999static netdev_features_t igb_fix_features(struct net_device *netdev,
2000 netdev_features_t features)
b2cb09b1 2001{
b980ac18
JK		 2002 /* Since there is no support for separate Rx/Tx vlan accel
2003 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2004 */
f646968f
PM		 2005 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2006 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2007 else
f646968f 2008 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2009
2010 return features;
2011}
2012
c8f44aff
MM		 2013static int igb_set_features(struct net_device *netdev,
2014 netdev_features_t features)
ac52caa3 2015{
c8f44aff 2016 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2017 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2018
f646968f 2019 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2020 igb_vlan_mode(netdev, features);
2021
89eaefb6
BG		 2022 if (!(changed & NETIF_F_RXALL))
2023 return 0;
2024
2025 netdev->features = features;
2026
2027 if (netif_running(netdev))
2028 igb_reinit_locked(adapter);
2029 else
2030 igb_reset(adapter);
2031
ac52caa3
MM		 2032 return 0;
2033}
2034
2e5c6922 2035static const struct net_device_ops igb_netdev_ops = {
559e9c49 2036 .ndo_open = igb_open,
2e5c6922 2037 .ndo_stop = igb_close,
cd392f5c 2038 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2039 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2040 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2041 .ndo_set_mac_address = igb_set_mac,
2042 .ndo_change_mtu = igb_change_mtu,
2043 .ndo_do_ioctl = igb_ioctl,
2044 .ndo_tx_timeout = igb_tx_timeout,
2045 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2046 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2047 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2048 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2049 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2050 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 2051 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2052 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2053#ifdef CONFIG_NET_POLL_CONTROLLER
2054 .ndo_poll_controller = igb_netpoll,
2055#endif
b2cb09b1
JP		 2056 .ndo_fix_features = igb_fix_features,
2057 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2058};
2059
d67974f0
CW		 2060/**
2061 * igb_set_fw_version - Configure version string for ethtool
2062 * @adapter: adapter struct
d67974f0
CW		 2063 **/
2064void igb_set_fw_version(struct igb_adapter *adapter)
2065{
2066 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2067 struct e1000_fw_version fw;
2068
2069 igb_get_fw_version(hw, &fw);
2070
2071 switch (hw->mac.type) {
7dc98a62 2072 case e1000_i210:
0b1a6f2e 2073 case e1000_i211:
7dc98a62
CW		 2074 if (!(igb_get_flash_presence_i210(hw))) {
2075 snprintf(adapter->fw_version,
2076 sizeof(adapter->fw_version),
2077 "%2d.%2d-%d",
2078 fw.invm_major, fw.invm_minor,
2079 fw.invm_img_type);
2080 break;
2081 }
2082 /* fall through */
0b1a6f2e
CW		 2083 default:
2084 /* if option is rom valid, display its version too */
2085 if (fw.or_valid) {
2086 snprintf(adapter->fw_version,
2087 sizeof(adapter->fw_version),
2088 "%d.%d, 0x%08x, %d.%d.%d",
2089 fw.eep_major, fw.eep_minor, fw.etrack_id,
2090 fw.or_major, fw.or_build, fw.or_patch);
2091 /* no option rom */
7dc98a62 2092 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2093 snprintf(adapter->fw_version,
7dc98a62
CW		 2094 sizeof(adapter->fw_version),
2095 "%d.%d, 0x%08x",
2096 fw.eep_major, fw.eep_minor, fw.etrack_id);
2097 } else {
2098 snprintf(adapter->fw_version,
2099 sizeof(adapter->fw_version),
2100 "%d.%d.%d",
2101 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2102 }
2103 break;
d67974f0 2104 }
d67974f0
CW		 2105 return;
2106}
2107
56cec249
CW		 2108/**
2109 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2110 *
2111 * @adapter: adapter struct
2112 **/
2113static void igb_init_mas(struct igb_adapter *adapter)
2114{
2115 struct e1000_hw *hw = &adapter->hw;
2116 u16 eeprom_data;
2117
2118 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2119 switch (hw->bus.func) {
2120 case E1000_FUNC_0:
2121 if (eeprom_data & IGB_MAS_ENABLE_0) {
2122 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2123 netdev_info(adapter->netdev,
2124 "MAS: Enabling Media Autosense for port %d\n",
2125 hw->bus.func);
2126 }
2127 break;
2128 case E1000_FUNC_1:
2129 if (eeprom_data & IGB_MAS_ENABLE_1) {
2130 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2131 netdev_info(adapter->netdev,
2132 "MAS: Enabling Media Autosense for port %d\n",
2133 hw->bus.func);
2134 }
2135 break;
2136 case E1000_FUNC_2:
2137 if (eeprom_data & IGB_MAS_ENABLE_2) {
2138 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2139 netdev_info(adapter->netdev,
2140 "MAS: Enabling Media Autosense for port %d\n",
2141 hw->bus.func);
2142 }
2143 break;
2144 case E1000_FUNC_3:
2145 if (eeprom_data & IGB_MAS_ENABLE_3) {
2146 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2147 netdev_info(adapter->netdev,
2148 "MAS: Enabling Media Autosense for port %d\n",
2149 hw->bus.func);
2150 }
2151 break;
2152 default:
2153 /* Shouldn't get here */
2154 netdev_err(adapter->netdev,
2155 "MAS: Invalid port configuration, returning\n");
2156 break;
2157 }
2158}
2159
b980ac18
JK		 2160/**
2161 * igb_init_i2c - Init I2C interface
441fc6fd 2162 * @adapter: pointer to adapter structure
b980ac18 2163 **/
441fc6fd
CW		 2164static s32 igb_init_i2c(struct igb_adapter *adapter)
2165{
2166 s32 status = E1000_SUCCESS;
2167
2168 /* I2C interface supported on i350 devices */
2169 if (adapter->hw.mac.type != e1000_i350)
2170 return E1000_SUCCESS;
2171
2172 /* Initialize the i2c bus which is controlled by the registers.
2173 * This bus will use the i2c_algo_bit structue that implements
2174 * the protocol through toggling of the 4 bits in the register.
2175 */
2176 adapter->i2c_adap.owner = THIS_MODULE;
2177 adapter->i2c_algo = igb_i2c_algo;
2178 adapter->i2c_algo.data = adapter;
2179 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2180 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2181 strlcpy(adapter->i2c_adap.name, "igb BB",
2182 sizeof(adapter->i2c_adap.name));
2183 status = i2c_bit_add_bus(&adapter->i2c_adap);
2184 return status;
2185}
2186
9d5c8243 2187/**
b980ac18
JK		 2188 * igb_probe - Device Initialization Routine
2189 * @pdev: PCI device information struct
2190 * @ent: entry in igb_pci_tbl
9d5c8243 2191 *
b980ac18 2192 * Returns 0 on success, negative on failure
9d5c8243 2193 *
b980ac18
JK		 2194 * igb_probe initializes an adapter identified by a pci_dev structure.
2195 * The OS initialization, configuring of the adapter private structure,
2196 * and a hardware reset occur.
9d5c8243 2197 **/
1dd06ae8 2198static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2199{
2200 struct net_device *netdev;
2201 struct igb_adapter *adapter;
2202 struct e1000_hw *hw;
4337e993 2203 u16 eeprom_data = 0;
9835fd73 2204 s32 ret_val;
4337e993 2205 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2206 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2207 int err, pci_using_dac;
9835fd73 2208 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2209
bded64a7
AG		 2210 /* Catch broken hardware that put the wrong VF device ID in
2211 * the PCIe SR-IOV capability.
2212 */
2213 if (pdev->is_virtfn) {
2214 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2215 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2216 return -EINVAL;
2217 }
2218
aed5dec3 2219 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2220 if (err)
2221 return err;
2222
2223 pci_using_dac = 0;
dc4ff9bb 2224 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2225 if (!err) {
dc4ff9bb 2226 pci_using_dac = 1;
9d5c8243 2227 } else {
dc4ff9bb 2228 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2229 if (err) {
dc4ff9bb
RK		 2230 dev_err(&pdev->dev,
2231 "No usable DMA configuration, aborting\n");
2232 goto err_dma;
9d5c8243
AK		 2233 }
2234 }
2235
aed5dec3 2236 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2237 IORESOURCE_MEM),
2238 igb_driver_name);
9d5c8243
AK		 2239 if (err)
2240 goto err_pci_reg;
2241
19d5afd4 2242 pci_enable_pcie_error_reporting(pdev);
40a914fa 2243
9d5c8243 2244 pci_set_master(pdev);
c682fc23 2245 pci_save_state(pdev);
9d5c8243
AK		 2246
2247 err = -ENOMEM;
1bfaf07b 2248 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2249 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2250 if (!netdev)
2251 goto err_alloc_etherdev;
2252
2253 SET_NETDEV_DEV(netdev, &pdev->dev);
2254
2255 pci_set_drvdata(pdev, netdev);
2256 adapter = netdev_priv(netdev);
2257 adapter->netdev = netdev;
2258 adapter->pdev = pdev;
2259 hw = &adapter->hw;
2260 hw->back = adapter;
b3f4d599 2261 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2262
9d5c8243 2263 err = -EIO;
89dbefb2 2264 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2265 if (!hw->hw_addr)
9d5c8243
AK		 2266 goto err_ioremap;
2267
2e5c6922 2268 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2269 igb_set_ethtool_ops(netdev);
9d5c8243 2270 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2271
2272 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2273
89dbefb2
AS		 2274 netdev->mem_start = pci_resource_start(pdev, 0);
2275 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2276
9d5c8243
AK		 2277 /* PCI config space info */
2278 hw->vendor_id = pdev->vendor;
2279 hw->device_id = pdev->device;
2280 hw->revision_id = pdev->revision;
2281 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2282 hw->subsystem_device_id = pdev->subsystem_device;
2283
9d5c8243
AK		 2284 /* Copy the default MAC, PHY and NVM function pointers */
2285 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2286 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2287 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2288 /* Initialize skew-specific constants */
2289 err = ei->get_invariants(hw);
2290 if (err)
450c87c8 2291 goto err_sw_init;
9d5c8243 2292
450c87c8 2293 /* setup the private structure */
9d5c8243
AK		 2294 err = igb_sw_init(adapter);
2295 if (err)
2296 goto err_sw_init;
2297
2298 igb_get_bus_info_pcie(hw);
2299
2300 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2301
2302 /* Copper options */
2303 if (hw->phy.media_type == e1000_media_type_copper) {
2304 hw->phy.mdix = AUTO_ALL_MODES;
2305 hw->phy.disable_polarity_correction = false;
2306 hw->phy.ms_type = e1000_ms_hw_default;
2307 }
2308
2309 if (igb_check_reset_block(hw))
2310 dev_info(&pdev->dev,
2311 "PHY reset is blocked due to SOL/IDER session.\n");
2312
b980ac18 2313 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2314 * set by igb_sw_init so we should use an or instead of an
2315 * assignment.
2316 */
2317 netdev->features |= NETIF_F_SG |
2318 NETIF_F_IP_CSUM |
2319 NETIF_F_IPV6_CSUM |
2320 NETIF_F_TSO |
2321 NETIF_F_TSO6 |
2322 NETIF_F_RXHASH |
2323 NETIF_F_RXCSUM |
f646968f
PM		 2324 NETIF_F_HW_VLAN_CTAG_RX |
2325 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2326
2327 /* copy netdev features into list of user selectable features */
2328 netdev->hw_features |= netdev->features;
89eaefb6 2329 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2330
2331 /* set this bit last since it cannot be part of hw_features */
f646968f 2332 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2333
2334 netdev->vlan_features |= NETIF_F_TSO |
2335 NETIF_F_TSO6 |
2336 NETIF_F_IP_CSUM |
2337 NETIF_F_IPV6_CSUM |
2338 NETIF_F_SG;
48f29ffc 2339
6b8f0922
BG		 2340 netdev->priv_flags |= IFF_SUPP_NOFCS;
2341
7b872a55 2342 if (pci_using_dac) {
9d5c8243 2343 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2344 netdev->vlan_features |= NETIF_F_HIGHDMA;
2345 }
9d5c8243 2346
ac52caa3
MM		 2347 if (hw->mac.type >= e1000_82576) {
2348 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2349 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2350 }
b9473560 2351
01789349
JP		 2352 netdev->priv_flags |= IFF_UNICAST_FLT;
2353
330a6d6a 2354 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2355
2356 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2357 * known good starting state
2358 */
9d5c8243
AK		 2359 hw->mac.ops.reset_hw(hw);
2360
ef3a0092
CW		 2361 /* make sure the NVM is good , i211/i210 parts can have special NVM
2362 * that doesn't contain a checksum
f96a8a0b 2363 */
ef3a0092
CW		 2364 switch (hw->mac.type) {
2365 case e1000_i210:
2366 case e1000_i211:
2367 if (igb_get_flash_presence_i210(hw)) {
2368 if (hw->nvm.ops.validate(hw) < 0) {
2369 dev_err(&pdev->dev,
2370 "The NVM Checksum Is Not Valid\n");
2371 err = -EIO;
2372 goto err_eeprom;
2373 }
2374 }
2375 break;
2376 default:
f96a8a0b
CW		 2377 if (hw->nvm.ops.validate(hw) < 0) {
2378 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2379 err = -EIO;
2380 goto err_eeprom;
2381 }
ef3a0092 2382 break;
9d5c8243
AK		 2383 }
2384
2385 /* copy the MAC address out of the NVM */
2386 if (hw->mac.ops.read_mac_addr(hw))
2387 dev_err(&pdev->dev, "NVM Read Error\n");
2388
2389 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2390
aaeb6cdf 2391 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2392 dev_err(&pdev->dev, "Invalid MAC Address\n");
2393 err = -EIO;
2394 goto err_eeprom;
2395 }
2396
d67974f0
CW		 2397 /* get firmware version for ethtool -i */
2398 igb_set_fw_version(adapter);
2399
c061b18d 2400 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2401 (unsigned long) adapter);
c061b18d 2402 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2403 (unsigned long) adapter);
9d5c8243
AK		 2404
2405 INIT_WORK(&adapter->reset_task, igb_reset_task);
2406 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2407
450c87c8 2408 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2409 adapter->fc_autoneg = true;
2410 hw->mac.autoneg = true;
2411 hw->phy.autoneg_advertised = 0x2f;
2412
0cce119a
AD		 2413 hw->fc.requested_mode = e1000_fc_default;
2414 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2415
9d5c8243
AK		 2416 igb_validate_mdi_setting(hw);
2417
63d4a8f9 2418 /* By default, support wake on port A */
a2cf8b6c 2419 if (hw->bus.func == 0)
63d4a8f9
MV		 2420 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2421
2422 /* Check the NVM for wake support on non-port A ports */
2423 if (hw->mac.type >= e1000_82580)
55cac248 2424 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2425 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2426 &eeprom_data);
a2cf8b6c
AD		 2427 else if (hw->bus.func == 1)
2428 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2429
63d4a8f9
MV		 2430 if (eeprom_data & IGB_EEPROM_APME)
2431 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2432
2433 /* now that we have the eeprom settings, apply the special cases where
2434 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2435 * lan on a particular port
2436 */
9d5c8243
AK		 2437 switch (pdev->device) {
2438 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2439 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2440 break;
2441 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2442 case E1000_DEV_ID_82576_FIBER:
2443 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2444 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2445 * regardless of eeprom setting
2446 */
9d5c8243 2447 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2448 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2449 break;
c8ea5ea9 2450 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2451 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2452 /* if quad port adapter, disable WoL on all but port A */
2453 if (global_quad_port_a != 0)
63d4a8f9 2454 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2455 else
2456 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2457 /* Reset for multiple quad port adapters */
2458 if (++global_quad_port_a == 4)
2459 global_quad_port_a = 0;
2460 break;
63d4a8f9
MV		 2461 default:
2462 /* If the device can't wake, don't set software support */
2463 if (!device_can_wakeup(&adapter->pdev->dev))
2464 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2465 }
2466
2467 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2468 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2469 adapter->wol |= E1000_WUFC_MAG;
2470
2471 /* Some vendors want WoL disabled by default, but still supported */
2472 if ((hw->mac.type == e1000_i350) &&
2473 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2474 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2475 adapter->wol = 0;
2476 }
2477
2478 device_set_wakeup_enable(&adapter->pdev->dev,
2479 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2480
2481 /* reset the hardware with the new settings */
2482 igb_reset(adapter);
2483
441fc6fd
CW		 2484 /* Init the I2C interface */
2485 err = igb_init_i2c(adapter);
2486 if (err) {
2487 dev_err(&pdev->dev, "failed to init i2c interface\n");
2488 goto err_eeprom;
2489 }
2490
9d5c8243
AK		 2491 /* let the f/w know that the h/w is now under the control of the
2492 * driver. */
2493 igb_get_hw_control(adapter);
2494
9d5c8243
AK		 2495 strcpy(netdev->name, "eth%d");
2496 err = register_netdev(netdev);
2497 if (err)
2498 goto err_register;
2499
b168dfc5
JB		 2500 /* carrier off reporting is important to ethtool even BEFORE open */
2501 netif_carrier_off(netdev);
2502
421e02f0 2503#ifdef CONFIG_IGB_DCA
bbd98fe4 2504 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2505 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2506 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2507 igb_setup_dca(adapter);
2508 }
fe4506b6 2509
38c845c7 2510#endif
e428893b
CW		 2511#ifdef CONFIG_IGB_HWMON
2512 /* Initialize the thermal sensor on i350 devices. */
2513 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2514 u16 ets_word;
3c89f6d0 2515
b980ac18 2516 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2517 * external thermal sensor.
2518 */
2519 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2520 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2521 adapter->ets = true;
2522 else
2523 adapter->ets = false;
2524 if (igb_sysfs_init(adapter))
2525 dev_err(&pdev->dev,
2526 "failed to allocate sysfs resources\n");
2527 } else {
2528 adapter->ets = false;
2529 }
2530#endif
56cec249
CW		 2531 /* Check if Media Autosense is enabled */
2532 adapter->ei = *ei;
2533 if (hw->dev_spec._82575.mas_capable)
2534 igb_init_mas(adapter);
2535
673b8b70 2536 /* do hw tstamp init after resetting */
7ebae817 2537 igb_ptp_init(adapter);
673b8b70 2538
9d5c8243 2539 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2540 /* print bus type/speed/width info, not applicable to i354 */
2541 if (hw->mac.type != e1000_i354) {
2542 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2543 netdev->name,
2544 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2545 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2546 "unknown"),
2547 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2548 "Width x4" :
2549 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2550 "Width x2" :
2551 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2552 "Width x1" : "unknown"), netdev->dev_addr);
2553 }
9d5c8243 2554
53ea6c7e
TF		 2555 if ((hw->mac.type >= e1000_i210 ||
2556 igb_get_flash_presence_i210(hw))) {
2557 ret_val = igb_read_part_string(hw, part_str,
2558 E1000_PBANUM_LENGTH);
2559 } else {
2560 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2561 }
2562
9835fd73
CW		 2563 if (ret_val)
2564 strcpy(part_str, "Unknown");
2565 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2566 dev_info(&pdev->dev,
2567 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2568 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2569 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2570 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2571 switch (hw->mac.type) {
2572 case e1000_i350:
f96a8a0b
CW		 2573 case e1000_i210:
2574 case e1000_i211:
09b068d4
CW		 2575 igb_set_eee_i350(hw);
2576 break;
ceb5f13b
CW		 2577 case e1000_i354:
2578 if (hw->phy.media_type == e1000_media_type_copper) {
2579 if ((rd32(E1000_CTRL_EXT) &
2580 E1000_CTRL_EXT_LINK_MODE_SGMII))
2581 igb_set_eee_i354(hw);
2582 }
2583 break;
09b068d4
CW		 2584 default:
2585 break;
2586 }
749ab2cd
YZ		 2587
2588 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2589 return 0;
2590
2591err_register:
2592 igb_release_hw_control(adapter);
441fc6fd 2593 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2594err_eeprom:
2595 if (!igb_check_reset_block(hw))
f5f4cf08 2596 igb_reset_phy(hw);
9d5c8243
AK		 2597
2598 if (hw->flash_address)
2599 iounmap(hw->flash_address);
9d5c8243 2600err_sw_init:
047e0030 2601 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2602 iounmap(hw->hw_addr);
2603err_ioremap:
2604 free_netdev(netdev);
2605err_alloc_etherdev:
559e9c49 2606 pci_release_selected_regions(pdev,
b980ac18 2607 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2608err_pci_reg:
2609err_dma:
2610 pci_disable_device(pdev);
2611 return err;
2612}
2613
fa44f2f1 2614#ifdef CONFIG_PCI_IOV
781798a1 2615static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2616{
2617 struct net_device *netdev = pci_get_drvdata(pdev);
2618 struct igb_adapter *adapter = netdev_priv(netdev);
2619 struct e1000_hw *hw = &adapter->hw;
2620
2621 /* reclaim resources allocated to VFs */
2622 if (adapter->vf_data) {
2623 /* disable iov and allow time for transactions to clear */
b09186d2 2624 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2625 dev_warn(&pdev->dev,
2626 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2627 return -EPERM;
2628 } else {
2629 pci_disable_sriov(pdev);
2630 msleep(500);
2631 }
2632
2633 kfree(adapter->vf_data);
2634 adapter->vf_data = NULL;
2635 adapter->vfs_allocated_count = 0;
2636 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2637 wrfl();
2638 msleep(100);
2639 dev_info(&pdev->dev, "IOV Disabled\n");
2640
2641 /* Re-enable DMA Coalescing flag since IOV is turned off */
2642 adapter->flags |= IGB_FLAG_DMAC;
2643 }
2644
2645 return 0;
2646}
2647
2648static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2649{
2650 struct net_device *netdev = pci_get_drvdata(pdev);
2651 struct igb_adapter *adapter = netdev_priv(netdev);
2652 int old_vfs = pci_num_vf(pdev);
2653 int err = 0;
2654 int i;
2655
781798a1 2656 if (!adapter->msix_entries || num_vfs > 7) {
50267196
MW		 2657 err = -EPERM;
2658 goto out;
2659 }
fa44f2f1
GR		 2660 if (!num_vfs)
2661 goto out;
fa44f2f1 2662
781798a1
SA		 2663 if (old_vfs) {
2664 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2665 old_vfs, max_vfs);
2666 adapter->vfs_allocated_count = old_vfs;
2667 } else
2668 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2669
2670 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2671 sizeof(struct vf_data_storage), GFP_KERNEL);
2672
2673 /* if allocation failed then we do not support SR-IOV */
2674 if (!adapter->vf_data) {
2675 adapter->vfs_allocated_count = 0;
2676 dev_err(&pdev->dev,
2677 "Unable to allocate memory for VF Data Storage\n");
2678 err = -ENOMEM;
2679 goto out;
2680 }
2681
781798a1
SA		 2682 /* only call pci_enable_sriov() if no VFs are allocated already */
2683 if (!old_vfs) {
2684 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2685 if (err)
2686 goto err_out;
2687 }
fa44f2f1
GR		 2688 dev_info(&pdev->dev, "%d VFs allocated\n",
2689 adapter->vfs_allocated_count);
2690 for (i = 0; i < adapter->vfs_allocated_count; i++)
2691 igb_vf_configure(adapter, i);
2692
2693 /* DMA Coalescing is not supported in IOV mode. */
2694 adapter->flags &= ~IGB_FLAG_DMAC;
2695 goto out;
2696
2697err_out:
2698 kfree(adapter->vf_data);
2699 adapter->vf_data = NULL;
2700 adapter->vfs_allocated_count = 0;
2701out:
2702 return err;
2703}
2704
2705#endif
b980ac18 2706/**
441fc6fd
CW		 2707 * igb_remove_i2c - Cleanup I2C interface
2708 * @adapter: pointer to adapter structure
b980ac18 2709 **/
441fc6fd
CW		 2710static void igb_remove_i2c(struct igb_adapter *adapter)
2711{
441fc6fd
CW		 2712 /* free the adapter bus structure */
2713 i2c_del_adapter(&adapter->i2c_adap);
2714}
2715
9d5c8243 2716/**
b980ac18
JK		 2717 * igb_remove - Device Removal Routine
2718 * @pdev: PCI device information struct
9d5c8243 2719 *
b980ac18
JK		 2720 * igb_remove is called by the PCI subsystem to alert the driver
2721 * that it should release a PCI device. The could be caused by a
2722 * Hot-Plug event, or because the driver is going to be removed from
2723 * memory.
9d5c8243 2724 **/
9f9a12f8 2725static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2726{
2727 struct net_device *netdev = pci_get_drvdata(pdev);
2728 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2729 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2730
749ab2cd 2731 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2732#ifdef CONFIG_IGB_HWMON
2733 igb_sysfs_exit(adapter);
2734#endif
441fc6fd 2735 igb_remove_i2c(adapter);
a79f4f88 2736 igb_ptp_stop(adapter);
b980ac18 2737 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2738 * disable watchdog from being rescheduled.
2739 */
9d5c8243
AK		 2740 set_bit(__IGB_DOWN, &adapter->state);
2741 del_timer_sync(&adapter->watchdog_timer);
2742 del_timer_sync(&adapter->phy_info_timer);
2743
760141a5
TH		 2744 cancel_work_sync(&adapter->reset_task);
2745 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2746
421e02f0 2747#ifdef CONFIG_IGB_DCA
7dfc16fa 2748 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2749 dev_info(&pdev->dev, "DCA disabled\n");
2750 dca_remove_requester(&pdev->dev);
7dfc16fa 2751 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2752 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2753 }
2754#endif
2755
9d5c8243 2756 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2757 * would have already happened in close and is redundant.
2758 */
9d5c8243
AK		 2759 igb_release_hw_control(adapter);
2760
2761 unregister_netdev(netdev);
2762
047e0030 2763 igb_clear_interrupt_scheme(adapter);
9d5c8243 2764
37680117 2765#ifdef CONFIG_PCI_IOV
fa44f2f1 2766 igb_disable_sriov(pdev);
37680117 2767#endif
559e9c49 2768
28b0759c
AD		 2769 iounmap(hw->hw_addr);
2770 if (hw->flash_address)
2771 iounmap(hw->flash_address);
559e9c49 2772 pci_release_selected_regions(pdev,
b980ac18 2773 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2774
1128c756 2775 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2776 free_netdev(netdev);
2777
19d5afd4 2778 pci_disable_pcie_error_reporting(pdev);
40a914fa 2779
9d5c8243
AK		 2780 pci_disable_device(pdev);
2781}
2782
a6b623e0 2783/**
b980ac18
JK		 2784 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2785 * @adapter: board private structure to initialize
a6b623e0 2786 *
b980ac18
JK		 2787 * This function initializes the vf specific data storage and then attempts to
2788 * allocate the VFs. The reason for ordering it this way is because it is much
2789 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2790 * the memory for the VFs.
a6b623e0 2791 **/
9f9a12f8 2792static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2793{
2794#ifdef CONFIG_PCI_IOV
2795 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2796 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2797
f96a8a0b
CW		 2798 /* Virtualization features not supported on i210 family. */
2799 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2800 return;
2801
fa44f2f1 2802 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2803 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2804
a6b623e0
AD		 2805#endif /* CONFIG_PCI_IOV */
2806}
2807
fa44f2f1 2808static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2809{
2810 struct e1000_hw *hw = &adapter->hw;
374a542d 2811 u32 max_rss_queues;
9d5c8243 2812
374a542d 2813 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2814 switch (hw->mac.type) {
374a542d
MV		 2815 case e1000_i211:
2816 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2817 break;
2818 case e1000_82575:
f96a8a0b 2819 case e1000_i210:
374a542d
MV		 2820 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2821 break;
2822 case e1000_i350:
2823 /* I350 cannot do RSS and SR-IOV at the same time */
2824 if (!!adapter->vfs_allocated_count) {
2825 max_rss_queues = 1;
2826 break;
2827 }
2828 /* fall through */
2829 case e1000_82576:
2830 if (!!adapter->vfs_allocated_count) {
2831 max_rss_queues = 2;
2832 break;
2833 }
2834 /* fall through */
2835 case e1000_82580:
ceb5f13b 2836 case e1000_i354:
374a542d
MV		 2837 default:
2838 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2839 break;
374a542d
MV		 2840 }
2841
2842 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2843
2844 /* Determine if we need to pair queues. */
2845 switch (hw->mac.type) {
2846 case e1000_82575:
f96a8a0b 2847 case e1000_i211:
374a542d 2848 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2849 break;
374a542d 2850 case e1000_82576:
b980ac18 2851 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2852 * should pair the queues in order to conserve interrupts due
2853 * to limited supply.
2854 */
2855 if ((adapter->rss_queues > 1) &&
2856 (adapter->vfs_allocated_count > 6))
2857 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2858 /* fall through */
2859 case e1000_82580:
2860 case e1000_i350:
ceb5f13b 2861 case e1000_i354:
374a542d 2862 case e1000_i210:
f96a8a0b 2863 default:
b980ac18 2864 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2865 * order to conserve interrupts due to limited supply.
2866 */
2867 if (adapter->rss_queues > (max_rss_queues / 2))
2868 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2869 break;
2870 }
fa44f2f1
GR		 2871}
2872
2873/**
b980ac18
JK		 2874 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2875 * @adapter: board private structure to initialize
fa44f2f1 2876 *
b980ac18
JK		 2877 * igb_sw_init initializes the Adapter private data structure.
2878 * Fields are initialized based on PCI device information and
2879 * OS network device settings (MTU size).
fa44f2f1
GR		 2880 **/
2881static int igb_sw_init(struct igb_adapter *adapter)
2882{
2883 struct e1000_hw *hw = &adapter->hw;
2884 struct net_device *netdev = adapter->netdev;
2885 struct pci_dev *pdev = adapter->pdev;
2886
2887 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2888
2889 /* set default ring sizes */
2890 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2891 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2892
2893 /* set default ITR values */
2894 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2895 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2896
2897 /* set default work limits */
2898 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2899
2900 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2901 VLAN_HLEN;
2902 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2903
2904 spin_lock_init(&adapter->stats64_lock);
2905#ifdef CONFIG_PCI_IOV
2906 switch (hw->mac.type) {
2907 case e1000_82576:
2908 case e1000_i350:
2909 if (max_vfs > 7) {
2910 dev_warn(&pdev->dev,
2911 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2912 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2913 } else
2914 adapter->vfs_allocated_count = max_vfs;
2915 if (adapter->vfs_allocated_count)
2916 dev_warn(&pdev->dev,
2917 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2918 break;
2919 default:
2920 break;
2921 }
2922#endif /* CONFIG_PCI_IOV */
2923
2924 igb_init_queue_configuration(adapter);
a99955fc 2925
1128c756 2926 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2927 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2928 GFP_ATOMIC);
1128c756 2929
a6b623e0 2930 /* This call may decrease the number of queues */
53c7d064 2931 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2932 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2933 return -ENOMEM;
2934 }
2935
a6b623e0
AD		 2936 igb_probe_vfs(adapter);
2937
9d5c8243
AK		 2938 /* Explicitly disable IRQ since the NIC can be in any state. */
2939 igb_irq_disable(adapter);
2940
f96a8a0b 2941 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2942 adapter->flags &= ~IGB_FLAG_DMAC;
2943
9d5c8243
AK		 2944 set_bit(__IGB_DOWN, &adapter->state);
2945 return 0;
2946}
2947
2948/**
b980ac18
JK		 2949 * igb_open - Called when a network interface is made active
2950 * @netdev: network interface device structure
9d5c8243 2951 *
b980ac18 2952 * Returns 0 on success, negative value on failure
9d5c8243 2953 *
b980ac18
JK		 2954 * The open entry point is called when a network interface is made
2955 * active by the system (IFF_UP). At this point all resources needed
2956 * for transmit and receive operations are allocated, the interrupt
2957 * handler is registered with the OS, the watchdog timer is started,
2958 * and the stack is notified that the interface is ready.
9d5c8243 2959 **/
749ab2cd 2960static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2961{
2962 struct igb_adapter *adapter = netdev_priv(netdev);
2963 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2964 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2965 int err;
2966 int i;
2967
2968 /* disallow open during test */
749ab2cd
YZ		 2969 if (test_bit(__IGB_TESTING, &adapter->state)) {
2970 WARN_ON(resuming);
9d5c8243 2971 return -EBUSY;
749ab2cd
YZ		 2972 }
2973
2974 if (!resuming)
2975 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2976
b168dfc5
JB		 2977 netif_carrier_off(netdev);
2978
9d5c8243
AK		 2979 /* allocate transmit descriptors */
2980 err = igb_setup_all_tx_resources(adapter);
2981 if (err)
2982 goto err_setup_tx;
2983
2984 /* allocate receive descriptors */
2985 err = igb_setup_all_rx_resources(adapter);
2986 if (err)
2987 goto err_setup_rx;
2988
88a268c1 2989 igb_power_up_link(adapter);
9d5c8243 2990
9d5c8243
AK		 2991 /* before we allocate an interrupt, we must be ready to handle it.
2992 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2993 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2994 * clean_rx handler before we do so.
2995 */
9d5c8243
AK		 2996 igb_configure(adapter);
2997
2998 err = igb_request_irq(adapter);
2999 if (err)
3000 goto err_req_irq;
3001
0c2cc02e
AD		 3002 /* Notify the stack of the actual queue counts. */
3003 err = netif_set_real_num_tx_queues(adapter->netdev,
3004 adapter->num_tx_queues);
3005 if (err)
3006 goto err_set_queues;
3007
3008 err = netif_set_real_num_rx_queues(adapter->netdev,
3009 adapter->num_rx_queues);
3010 if (err)
3011 goto err_set_queues;
3012
9d5c8243
AK		 3013 /* From here on the code is the same as igb_up() */
3014 clear_bit(__IGB_DOWN, &adapter->state);
3015
0d1ae7f4
AD		 3016 for (i = 0; i < adapter->num_q_vectors; i++)
3017 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3018
3019 /* Clear any pending interrupts. */
3020 rd32(E1000_ICR);
844290e5
PW		 3021
3022 igb_irq_enable(adapter);
3023
d4960307
AD		 3024 /* notify VFs that reset has been completed */
3025 if (adapter->vfs_allocated_count) {
3026 u32 reg_data = rd32(E1000_CTRL_EXT);
3027 reg_data |= E1000_CTRL_EXT_PFRSTD;
3028 wr32(E1000_CTRL_EXT, reg_data);
3029 }
3030
d55b53ff
JK		 3031 netif_tx_start_all_queues(netdev);
3032
749ab2cd
YZ		 3033 if (!resuming)
3034 pm_runtime_put(&pdev->dev);
3035
25568a53
AD		 3036 /* start the watchdog. */
3037 hw->mac.get_link_status = 1;
3038 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3039
3040 return 0;
3041
0c2cc02e
AD		 3042err_set_queues:
3043 igb_free_irq(adapter);
9d5c8243
AK		 3044err_req_irq:
3045 igb_release_hw_control(adapter);
88a268c1 3046 igb_power_down_link(adapter);
9d5c8243
AK		 3047 igb_free_all_rx_resources(adapter);
3048err_setup_rx:
3049 igb_free_all_tx_resources(adapter);
3050err_setup_tx:
3051 igb_reset(adapter);
749ab2cd
YZ		 3052 if (!resuming)
3053 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3054
3055 return err;
3056}
3057
749ab2cd
YZ		 3058static int igb_open(struct net_device *netdev)
3059{
3060 return __igb_open(netdev, false);
3061}
3062
9d5c8243 3063/**
b980ac18
JK		 3064 * igb_close - Disables a network interface
3065 * @netdev: network interface device structure
9d5c8243 3066 *
b980ac18 3067 * Returns 0, this is not allowed to fail
9d5c8243 3068 *
b980ac18
JK		 3069 * The close entry point is called when an interface is de-activated
3070 * by the OS. The hardware is still under the driver's control, but
3071 * needs to be disabled. A global MAC reset is issued to stop the
3072 * hardware, and all transmit and receive resources are freed.
9d5c8243 3073 **/
749ab2cd 3074static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3075{
3076 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3077 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3078
3079 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3080
749ab2cd
YZ		 3081 if (!suspending)
3082 pm_runtime_get_sync(&pdev->dev);
3083
3084 igb_down(adapter);
9d5c8243
AK		 3085 igb_free_irq(adapter);
3086
3087 igb_free_all_tx_resources(adapter);
3088 igb_free_all_rx_resources(adapter);
3089
749ab2cd
YZ		 3090 if (!suspending)
3091 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3092 return 0;
3093}
3094
749ab2cd
YZ		 3095static int igb_close(struct net_device *netdev)
3096{
3097 return __igb_close(netdev, false);
3098}
3099
9d5c8243 3100/**
b980ac18
JK		 3101 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3102 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3103 *
b980ac18 3104 * Return 0 on success, negative on failure
9d5c8243 3105 **/
80785298 3106int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3107{
59d71989 3108 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3109 int size;
3110
06034649 3111 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3112
3113 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3114 if (!tx_ring->tx_buffer_info)
9d5c8243 3115 goto err;
9d5c8243
AK		 3116
3117 /* round up to nearest 4K */
85e8d004 3118 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3119 tx_ring->size = ALIGN(tx_ring->size, 4096);
3120
5536d210
AD		 3121 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3122 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3123 if (!tx_ring->desc)
3124 goto err;
3125
9d5c8243
AK		 3126 tx_ring->next_to_use = 0;
3127 tx_ring->next_to_clean = 0;
81c2fc22 3128
9d5c8243
AK		 3129 return 0;
3130
3131err:
06034649 3132 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3133 tx_ring->tx_buffer_info = NULL;
3134 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3135 return -ENOMEM;
3136}
3137
3138/**
b980ac18
JK		 3139 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3140 * (Descriptors) for all queues
3141 * @adapter: board private structure
9d5c8243 3142 *
b980ac18 3143 * Return 0 on success, negative on failure
9d5c8243
AK		 3144 **/
3145static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3146{
439705e1 3147 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3148 int i, err = 0;
3149
3150 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3151 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3152 if (err) {
439705e1 3153 dev_err(&pdev->dev,
9d5c8243
AK		 3154 "Allocation for Tx Queue %u failed\n", i);
3155 for (i--; i >= 0; i--)
3025a446 3156 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3157 break;
3158 }
3159 }
3160
3161 return err;
3162}
3163
3164/**
b980ac18
JK		 3165 * igb_setup_tctl - configure the transmit control registers
3166 * @adapter: Board private structure
9d5c8243 3167 **/
d7ee5b3a 3168void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3169{
9d5c8243
AK		 3170 struct e1000_hw *hw = &adapter->hw;
3171 u32 tctl;
9d5c8243 3172
85b430b4
AD		 3173 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3174 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3175
3176 /* Program the Transmit Control Register */
9d5c8243
AK		 3177 tctl = rd32(E1000_TCTL);
3178 tctl &= ~E1000_TCTL_CT;
3179 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3180 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3181
3182 igb_config_collision_dist(hw);
3183
9d5c8243
AK		 3184 /* Enable transmits */
3185 tctl |= E1000_TCTL_EN;
3186
3187 wr32(E1000_TCTL, tctl);
3188}
3189
85b430b4 3190/**
b980ac18
JK		 3191 * igb_configure_tx_ring - Configure transmit ring after Reset
3192 * @adapter: board private structure
3193 * @ring: tx ring to configure
85b430b4 3194 *
b980ac18 3195 * Configure a transmit ring after a reset.
85b430b4 3196 **/
d7ee5b3a
AD		 3197void igb_configure_tx_ring(struct igb_adapter *adapter,
3198 struct igb_ring *ring)
85b430b4
AD		 3199{
3200 struct e1000_hw *hw = &adapter->hw;
a74420e0 3201 u32 txdctl = 0;
85b430b4
AD		 3202 u64 tdba = ring->dma;
3203 int reg_idx = ring->reg_idx;
3204
3205 /* disable the queue */
a74420e0 3206 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3207 wrfl();
3208 mdelay(10);
3209
3210 wr32(E1000_TDLEN(reg_idx),
b980ac18 3211 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3212 wr32(E1000_TDBAL(reg_idx),
b980ac18 3213 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3214 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3215
fce99e34 3216 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3217 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3218 writel(0, ring->tail);
85b430b4
AD		 3219
3220 txdctl |= IGB_TX_PTHRESH;
3221 txdctl |= IGB_TX_HTHRESH << 8;
3222 txdctl |= IGB_TX_WTHRESH << 16;
3223
3224 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3225 wr32(E1000_TXDCTL(reg_idx), txdctl);
3226}
3227
3228/**
b980ac18
JK		 3229 * igb_configure_tx - Configure transmit Unit after Reset
3230 * @adapter: board private structure
85b430b4 3231 *
b980ac18 3232 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3233 **/
3234static void igb_configure_tx(struct igb_adapter *adapter)
3235{
3236 int i;
3237
3238 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3239 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3240}
3241
9d5c8243 3242/**
b980ac18
JK		 3243 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3244 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3245 *
b980ac18 3246 * Returns 0 on success, negative on failure
9d5c8243 3247 **/
80785298 3248int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3249{
59d71989 3250 struct device *dev = rx_ring->dev;
f33005a6 3251 int size;
9d5c8243 3252
06034649 3253 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3254
3255 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3256 if (!rx_ring->rx_buffer_info)
9d5c8243 3257 goto err;
9d5c8243 3258
9d5c8243 3259 /* Round up to nearest 4K */
f33005a6 3260 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3261 rx_ring->size = ALIGN(rx_ring->size, 4096);
3262
5536d210
AD		 3263 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3264 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3265 if (!rx_ring->desc)
3266 goto err;
3267
cbc8e55f 3268 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3269 rx_ring->next_to_clean = 0;
3270 rx_ring->next_to_use = 0;
9d5c8243 3271
9d5c8243
AK		 3272 return 0;
3273
3274err:
06034649
AD		 3275 vfree(rx_ring->rx_buffer_info);
3276 rx_ring->rx_buffer_info = NULL;
f33005a6 3277 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3278 return -ENOMEM;
3279}
3280
3281/**
b980ac18
JK		 3282 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3283 * (Descriptors) for all queues
3284 * @adapter: board private structure
9d5c8243 3285 *
b980ac18 3286 * Return 0 on success, negative on failure
9d5c8243
AK		 3287 **/
3288static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3289{
439705e1 3290 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3291 int i, err = 0;
3292
3293 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3294 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3295 if (err) {
439705e1 3296 dev_err(&pdev->dev,
9d5c8243
AK		 3297 "Allocation for Rx Queue %u failed\n", i);
3298 for (i--; i >= 0; i--)
3025a446 3299 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3300 break;
3301 }
3302 }
3303
3304 return err;
3305}
3306
06cf2666 3307/**
b980ac18
JK		 3308 * igb_setup_mrqc - configure the multiple receive queue control registers
3309 * @adapter: Board private structure
06cf2666
AD		 3310 **/
3311static void igb_setup_mrqc(struct igb_adapter *adapter)
3312{
3313 struct e1000_hw *hw = &adapter->hw;
3314 u32 mrqc, rxcsum;
ed12cc9a 3315 u32 j, num_rx_queues;
a57fe23e
AD		 3316 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3317 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3318 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3319 0xFA01ACBE };
06cf2666
AD		 3320
3321 /* Fill out hash function seeds */
a57fe23e
AD		 3322 for (j = 0; j < 10; j++)
3323 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3324
a99955fc 3325 num_rx_queues = adapter->rss_queues;
06cf2666 3326
797fd4be 3327 switch (hw->mac.type) {
797fd4be
AD		 3328 case e1000_82576:
3329 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3330 if (adapter->vfs_allocated_count)
06cf2666 3331 num_rx_queues = 2;
797fd4be
AD		 3332 break;
3333 default:
3334 break;
06cf2666
AD		 3335 }
3336
ed12cc9a
LMV		 3337 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3338 for (j = 0; j < IGB_RETA_SIZE; j++)
3339 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3340 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3341 }
ed12cc9a 3342 igb_write_rss_indir_tbl(adapter);
06cf2666 3343
b980ac18 3344 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3345 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3346 * offloads as they are enabled by default
3347 */
3348 rxcsum = rd32(E1000_RXCSUM);
3349 rxcsum |= E1000_RXCSUM_PCSD;
3350
3351 if (adapter->hw.mac.type >= e1000_82576)
3352 /* Enable Receive Checksum Offload for SCTP */
3353 rxcsum |= E1000_RXCSUM_CRCOFL;
3354
3355 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3356 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3357
039454a8
AA		 3358 /* Generate RSS hash based on packet types, TCP/UDP
3359 * port numbers and/or IPv4/v6 src and dst addresses
3360 */
f96a8a0b
CW		 3361 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3362 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3363 E1000_MRQC_RSS_FIELD_IPV6 |
3364 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3365 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3366
039454a8
AA		 3367 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3368 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3369 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3370 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3371
06cf2666
AD		 3372 /* If VMDq is enabled then we set the appropriate mode for that, else
3373 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3374 * if we are only using one queue
3375 */
06cf2666
AD		 3376 if (adapter->vfs_allocated_count) {
3377 if (hw->mac.type > e1000_82575) {
3378 /* Set the default pool for the PF's first queue */
3379 u32 vtctl = rd32(E1000_VT_CTL);
3380 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3381 E1000_VT_CTL_DISABLE_DEF_POOL);
3382 vtctl |= adapter->vfs_allocated_count <<
3383 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3384 wr32(E1000_VT_CTL, vtctl);
3385 }
a99955fc 3386 if (adapter->rss_queues > 1)
f96a8a0b 3387 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3388 else
f96a8a0b 3389 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3390 } else {
f96a8a0b
CW		 3391 if (hw->mac.type != e1000_i211)
3392 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3393 }
3394 igb_vmm_control(adapter);
3395
06cf2666
AD		 3396 wr32(E1000_MRQC, mrqc);
3397}
3398
9d5c8243 3399/**
b980ac18
JK		 3400 * igb_setup_rctl - configure the receive control registers
3401 * @adapter: Board private structure
9d5c8243 3402 **/
d7ee5b3a 3403void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3404{
3405 struct e1000_hw *hw = &adapter->hw;
3406 u32 rctl;
9d5c8243
AK		 3407
3408 rctl = rd32(E1000_RCTL);
3409
3410 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3411 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3412
69d728ba 3413 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3414 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3415
b980ac18 3416 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3417 * redirection as it did with e1000. Newer features require
3418 * that the HW strips the CRC.
73cd78f1 3419 */
87cb7e8c 3420 rctl |= E1000_RCTL_SECRC;
9d5c8243 3421
559e9c49 3422 /* disable store bad packets and clear size bits. */
ec54d7d6 3423 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3424
6ec43fe6
AD		 3425 /* enable LPE to prevent packets larger than max_frame_size */
3426 rctl |= E1000_RCTL_LPE;
9d5c8243 3427
952f72a8
AD		 3428 /* disable queue 0 to prevent tail write w/o re-config */
3429 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3430
e1739522
AD		 3431 /* Attention!!! For SR-IOV PF driver operations you must enable
3432 * queue drop for all VF and PF queues to prevent head of line blocking
3433 * if an un-trusted VF does not provide descriptors to hardware.
3434 */
3435 if (adapter->vfs_allocated_count) {
e1739522
AD		 3436 /* set all queue drop enable bits */
3437 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3438 }
3439
89eaefb6
BG		 3440 /* This is useful for sniffing bad packets. */
3441 if (adapter->netdev->features & NETIF_F_RXALL) {
3442 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3443 * in e1000e_set_rx_mode
3444 */
89eaefb6
BG		 3445 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3446 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3447 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3448
3449 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3450 E1000_RCTL_DPF | /* Allow filtered pause */
3451 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3452 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3453 * and that breaks VLANs.
3454 */
3455 }
3456
9d5c8243
AK		 3457 wr32(E1000_RCTL, rctl);
3458}
3459
7d5753f0
AD		 3460static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3461 int vfn)
3462{
3463 struct e1000_hw *hw = &adapter->hw;
3464 u32 vmolr;
3465
3466 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3467 * increase the size to support vlan tags
3468 */
7d5753f0
AD		 3469 if (vfn < adapter->vfs_allocated_count &&
3470 adapter->vf_data[vfn].vlans_enabled)
3471 size += VLAN_TAG_SIZE;
3472
3473 vmolr = rd32(E1000_VMOLR(vfn));
3474 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3475 vmolr |= size | E1000_VMOLR_LPE;
3476 wr32(E1000_VMOLR(vfn), vmolr);
3477
3478 return 0;
3479}
3480
e1739522 3481/**
b980ac18
JK		 3482 * igb_rlpml_set - set maximum receive packet size
3483 * @adapter: board private structure
e1739522 3484 *
b980ac18 3485 * Configure maximum receivable packet size.
e1739522
AD		 3486 **/
3487static void igb_rlpml_set(struct igb_adapter *adapter)
3488{
153285f9 3489 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3490 struct e1000_hw *hw = &adapter->hw;
3491 u16 pf_id = adapter->vfs_allocated_count;
3492
e1739522
AD		 3493 if (pf_id) {
3494 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3495 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3496 * to our max jumbo frame size, in case we need to enable
3497 * jumbo frames on one of the rings later.
3498 * This will not pass over-length frames into the default
3499 * queue because it's gated by the VMOLR.RLPML.
3500 */
7d5753f0 3501 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3502 }
3503
3504 wr32(E1000_RLPML, max_frame_size);
3505}
3506
8151d294
WM		 3507static inline void igb_set_vmolr(struct igb_adapter *adapter,
3508 int vfn, bool aupe)
7d5753f0
AD		 3509{
3510 struct e1000_hw *hw = &adapter->hw;
3511 u32 vmolr;
3512
b980ac18 3513 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3514 * we should exit and do nothing
3515 */
3516 if (hw->mac.type < e1000_82576)
3517 return;
3518
3519 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3520 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3521 if (aupe)
b980ac18 3522 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3523 else
3524 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3525
3526 /* clear all bits that might not be set */
3527 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3528
a99955fc 3529 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3530 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3531 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3532 * multicast packets
3533 */
3534 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3535 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3536
3537 wr32(E1000_VMOLR(vfn), vmolr);
3538}
3539
85b430b4 3540/**
b980ac18
JK		 3541 * igb_configure_rx_ring - Configure a receive ring after Reset
3542 * @adapter: board private structure
3543 * @ring: receive ring to be configured
85b430b4 3544 *
b980ac18 3545 * Configure the Rx unit of the MAC after a reset.
85b430b4 3546 **/
d7ee5b3a 3547void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3548 struct igb_ring *ring)
85b430b4
AD		 3549{
3550 struct e1000_hw *hw = &adapter->hw;
3551 u64 rdba = ring->dma;
3552 int reg_idx = ring->reg_idx;
a74420e0 3553 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3554
3555 /* disable the queue */
a74420e0 3556 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3557
3558 /* Set DMA base address registers */
3559 wr32(E1000_RDBAL(reg_idx),
3560 rdba & 0x00000000ffffffffULL);
3561 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3562 wr32(E1000_RDLEN(reg_idx),
b980ac18 3563 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3564
3565 /* initialize head and tail */
fce99e34 3566 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3567 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3568 writel(0, ring->tail);
85b430b4 3569
952f72a8 3570 /* set descriptor configuration */
44390ca6 3571 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3572 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3573 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3574 if (hw->mac.type >= e1000_82580)
757b77e2 3575 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3576 /* Only set Drop Enable if we are supporting multiple queues */
3577 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3578 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3579
3580 wr32(E1000_SRRCTL(reg_idx), srrctl);
3581
7d5753f0 3582 /* set filtering for VMDQ pools */
8151d294 3583 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3584
85b430b4
AD		 3585 rxdctl |= IGB_RX_PTHRESH;
3586 rxdctl |= IGB_RX_HTHRESH << 8;
3587 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3588
3589 /* enable receive descriptor fetching */
3590 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3591 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3592}
3593
9d5c8243 3594/**
b980ac18
JK		 3595 * igb_configure_rx - Configure receive Unit after Reset
3596 * @adapter: board private structure
9d5c8243 3597 *
b980ac18 3598 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3599 **/
3600static void igb_configure_rx(struct igb_adapter *adapter)
3601{
9107584e 3602 int i;
9d5c8243 3603
68d480c4
AD		 3604 /* set UTA to appropriate mode */
3605 igb_set_uta(adapter);
3606
26ad9178
AD		 3607 /* set the correct pool for the PF default MAC address in entry 0 */
3608 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3609 adapter->vfs_allocated_count);
26ad9178 3610
06cf2666 3611 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3612 * the Base and Length of the Rx Descriptor Ring
3613 */
f9d40f6a
AD		 3614 for (i = 0; i < adapter->num_rx_queues; i++)
3615 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3616}
3617
3618/**
b980ac18
JK		 3619 * igb_free_tx_resources - Free Tx Resources per Queue
3620 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3621 *
b980ac18 3622 * Free all transmit software resources
9d5c8243 3623 **/
68fd9910 3624void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3625{
3b644cf6 3626 igb_clean_tx_ring(tx_ring);
9d5c8243 3627
06034649
AD		 3628 vfree(tx_ring->tx_buffer_info);
3629 tx_ring->tx_buffer_info = NULL;
9d5c8243 3630
439705e1
AD		 3631 /* if not set, then don't free */
3632 if (!tx_ring->desc)
3633 return;
3634
59d71989
AD		 3635 dma_free_coherent(tx_ring->dev, tx_ring->size,
3636 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3637
3638 tx_ring->desc = NULL;
3639}
3640
3641/**
b980ac18
JK		 3642 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3643 * @adapter: board private structure
9d5c8243 3644 *
b980ac18 3645 * Free all transmit software resources
9d5c8243
AK		 3646 **/
3647static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3648{
3649 int i;
3650
3651 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3652 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3653}
3654
ebe42d16
AD		 3655void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3656 struct igb_tx_buffer *tx_buffer)
3657{
3658 if (tx_buffer->skb) {
3659 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3660 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3661 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3662 dma_unmap_addr(tx_buffer, dma),
3663 dma_unmap_len(tx_buffer, len),
ebe42d16 3664 DMA_TO_DEVICE);
c9f14bf3 3665 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3666 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3667 dma_unmap_addr(tx_buffer, dma),
3668 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3669 DMA_TO_DEVICE);
3670 }
3671 tx_buffer->next_to_watch = NULL;
3672 tx_buffer->skb = NULL;
c9f14bf3 3673 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3674 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3675}
3676
3677/**
b980ac18
JK		 3678 * igb_clean_tx_ring - Free Tx Buffers
3679 * @tx_ring: ring to be cleaned
9d5c8243 3680 **/
3b644cf6 3681static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3682{
06034649 3683 struct igb_tx_buffer *buffer_info;
9d5c8243 3684 unsigned long size;
6ad4edfc 3685 u16 i;
9d5c8243 3686
06034649 3687 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3688 return;
3689 /* Free all the Tx ring sk_buffs */
3690
3691 for (i = 0; i < tx_ring->count; i++) {
06034649 3692 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3693 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3694 }
3695
dad8a3b3
JF		 3696 netdev_tx_reset_queue(txring_txq(tx_ring));
3697
06034649
AD		 3698 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3699 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3700
3701 /* Zero out the descriptor ring */
9d5c8243
AK		 3702 memset(tx_ring->desc, 0, tx_ring->size);
3703
3704 tx_ring->next_to_use = 0;
3705 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3706}
3707
3708/**
b980ac18
JK		 3709 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3710 * @adapter: board private structure
9d5c8243
AK		 3711 **/
3712static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3713{
3714 int i;
3715
3716 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3717 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3718}
3719
3720/**
b980ac18
JK		 3721 * igb_free_rx_resources - Free Rx Resources
3722 * @rx_ring: ring to clean the resources from
9d5c8243 3723 *
b980ac18 3724 * Free all receive software resources
9d5c8243 3725 **/
68fd9910 3726void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3727{
3b644cf6 3728 igb_clean_rx_ring(rx_ring);
9d5c8243 3729
06034649
AD		 3730 vfree(rx_ring->rx_buffer_info);
3731 rx_ring->rx_buffer_info = NULL;
9d5c8243 3732
439705e1
AD		 3733 /* if not set, then don't free */
3734 if (!rx_ring->desc)
3735 return;
3736
59d71989
AD		 3737 dma_free_coherent(rx_ring->dev, rx_ring->size,
3738 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3739
3740 rx_ring->desc = NULL;
3741}
3742
3743/**
b980ac18
JK		 3744 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3745 * @adapter: board private structure
9d5c8243 3746 *
b980ac18 3747 * Free all receive software resources
9d5c8243
AK		 3748 **/
3749static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3750{
3751 int i;
3752
3753 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3754 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3755}
3756
3757/**
b980ac18
JK		 3758 * igb_clean_rx_ring - Free Rx Buffers per Queue
3759 * @rx_ring: ring to free buffers from
9d5c8243 3760 **/
3b644cf6 3761static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3762{
9d5c8243 3763 unsigned long size;
c023cd88 3764 u16 i;
9d5c8243 3765
1a1c225b
AD		 3766 if (rx_ring->skb)
3767 dev_kfree_skb(rx_ring->skb);
3768 rx_ring->skb = NULL;
3769
06034649 3770 if (!rx_ring->rx_buffer_info)
9d5c8243 3771 return;
439705e1 3772
9d5c8243
AK		 3773 /* Free all the Rx ring sk_buffs */
3774 for (i = 0; i < rx_ring->count; i++) {
06034649 3775 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3776
cbc8e55f
AD		 3777 if (!buffer_info->page)
3778 continue;
3779
3780 dma_unmap_page(rx_ring->dev,
3781 buffer_info->dma,
3782 PAGE_SIZE,
3783 DMA_FROM_DEVICE);
3784 __free_page(buffer_info->page);
3785
1a1c225b 3786 buffer_info->page = NULL;
9d5c8243
AK		 3787 }
3788
06034649
AD		 3789 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3790 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3791
3792 /* Zero out the descriptor ring */
3793 memset(rx_ring->desc, 0, rx_ring->size);
3794
cbc8e55f 3795 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3796 rx_ring->next_to_clean = 0;
3797 rx_ring->next_to_use = 0;
9d5c8243
AK		 3798}
3799
3800/**
b980ac18
JK		 3801 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3802 * @adapter: board private structure
9d5c8243
AK		 3803 **/
3804static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3805{
3806 int i;
3807
3808 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3809 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3810}
3811
3812/**
b980ac18
JK		 3813 * igb_set_mac - Change the Ethernet Address of the NIC
3814 * @netdev: network interface device structure
3815 * @p: pointer to an address structure
9d5c8243 3816 *
b980ac18 3817 * Returns 0 on success, negative on failure
9d5c8243
AK		 3818 **/
3819static int igb_set_mac(struct net_device *netdev, void *p)
3820{
3821 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3822 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3823 struct sockaddr *addr = p;
3824
3825 if (!is_valid_ether_addr(addr->sa_data))
3826 return -EADDRNOTAVAIL;
3827
3828 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3829 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3830
26ad9178
AD		 3831 /* set the correct pool for the new PF MAC address in entry 0 */
3832 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3833 adapter->vfs_allocated_count);
e1739522 3834
9d5c8243
AK		 3835 return 0;
3836}
3837
3838/**
b980ac18
JK		 3839 * igb_write_mc_addr_list - write multicast addresses to MTA
3840 * @netdev: network interface device structure
9d5c8243 3841 *
b980ac18
JK		 3842 * Writes multicast address list to the MTA hash table.
3843 * Returns: -ENOMEM on failure
3844 * 0 on no addresses written
3845 * X on writing X addresses to MTA
9d5c8243 3846 **/
68d480c4 3847static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3848{
3849 struct igb_adapter *adapter = netdev_priv(netdev);
3850 struct e1000_hw *hw = &adapter->hw;
22bedad3 3851 struct netdev_hw_addr *ha;
68d480c4 3852 u8 *mta_list;
9d5c8243
AK		 3853 int i;
3854
4cd24eaf 3855 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3856 /* nothing to program, so clear mc list */
3857 igb_update_mc_addr_list(hw, NULL, 0);
3858 igb_restore_vf_multicasts(adapter);
3859 return 0;
3860 }
9d5c8243 3861
4cd24eaf 3862 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3863 if (!mta_list)
3864 return -ENOMEM;
ff41f8dc 3865
68d480c4 3866 /* The shared function expects a packed array of only addresses. */
48e2f183 3867 i = 0;
22bedad3
JP		 3868 netdev_for_each_mc_addr(ha, netdev)
3869 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3870
68d480c4
AD		 3871 igb_update_mc_addr_list(hw, mta_list, i);
3872 kfree(mta_list);
3873
4cd24eaf 3874 return netdev_mc_count(netdev);
68d480c4
AD		 3875}
3876
3877/**
b980ac18
JK		 3878 * igb_write_uc_addr_list - write unicast addresses to RAR table
3879 * @netdev: network interface device structure
68d480c4 3880 *
b980ac18
JK		 3881 * Writes unicast address list to the RAR table.
3882 * Returns: -ENOMEM on failure/insufficient address space
3883 * 0 on no addresses written
3884 * X on writing X addresses to the RAR table
68d480c4
AD		 3885 **/
3886static int igb_write_uc_addr_list(struct net_device *netdev)
3887{
3888 struct igb_adapter *adapter = netdev_priv(netdev);
3889 struct e1000_hw *hw = &adapter->hw;
3890 unsigned int vfn = adapter->vfs_allocated_count;
3891 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3892 int count = 0;
3893
3894 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3895 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3896 return -ENOMEM;
9d5c8243 3897
32e7bfc4 3898 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3899 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3900
3901 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3902 if (!rar_entries)
3903 break;
26ad9178 3904 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3905 rar_entries--,
3906 vfn);
68d480c4 3907 count++;
ff41f8dc
AD		 3908 }
3909 }
3910 /* write the addresses in reverse order to avoid write combining */
3911 for (; rar_entries > 0 ; rar_entries--) {
3912 wr32(E1000_RAH(rar_entries), 0);
3913 wr32(E1000_RAL(rar_entries), 0);
3914 }
3915 wrfl();
3916
68d480c4
AD		 3917 return count;
3918}
3919
3920/**
b980ac18
JK		 3921 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3922 * @netdev: network interface device structure
68d480c4 3923 *
b980ac18
JK		 3924 * The set_rx_mode entry point is called whenever the unicast or multicast
3925 * address lists or the network interface flags are updated. This routine is
3926 * responsible for configuring the hardware for proper unicast, multicast,
3927 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3928 **/
3929static void igb_set_rx_mode(struct net_device *netdev)
3930{
3931 struct igb_adapter *adapter = netdev_priv(netdev);
3932 struct e1000_hw *hw = &adapter->hw;
3933 unsigned int vfn = adapter->vfs_allocated_count;
3934 u32 rctl, vmolr = 0;
3935 int count;
3936
3937 /* Check for Promiscuous and All Multicast modes */
3938 rctl = rd32(E1000_RCTL);
3939
3940 /* clear the effected bits */
3941 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3942
3943 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3944 /* retain VLAN HW filtering if in VT mode */
7e44892c 3945 if (adapter->vfs_allocated_count)
6f3dc319 3946 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3947 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3948 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3949 } else {
3950 if (netdev->flags & IFF_ALLMULTI) {
3951 rctl |= E1000_RCTL_MPE;
3952 vmolr |= E1000_VMOLR_MPME;
3953 } else {
b980ac18 3954 /* Write addresses to the MTA, if the attempt fails
25985edc 3955 * then we should just turn on promiscuous mode so
68d480c4
AD		 3956 * that we can at least receive multicast traffic
3957 */
3958 count = igb_write_mc_addr_list(netdev);
3959 if (count < 0) {
3960 rctl |= E1000_RCTL_MPE;
3961 vmolr |= E1000_VMOLR_MPME;
3962 } else if (count) {
3963 vmolr |= E1000_VMOLR_ROMPE;
3964 }
3965 }
b980ac18 3966 /* Write addresses to available RAR registers, if there is not
68d480c4 3967 * sufficient space to store all the addresses then enable
25985edc 3968 * unicast promiscuous mode
68d480c4
AD		 3969 */
3970 count = igb_write_uc_addr_list(netdev);
3971 if (count < 0) {
3972 rctl |= E1000_RCTL_UPE;
3973 vmolr |= E1000_VMOLR_ROPE;
3974 }
3975 rctl |= E1000_RCTL_VFE;
28fc06f5 3976 }
68d480c4 3977 wr32(E1000_RCTL, rctl);
28fc06f5 3978
b980ac18 3979 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3980 * the VMOLR to enable the appropriate modes. Without this workaround
3981 * we will have issues with VLAN tag stripping not being done for frames
3982 * that are only arriving because we are the default pool
3983 */
f96a8a0b 3984 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3985 return;
9d5c8243 3986
68d480c4 3987 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3988 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3989 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3990 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3991}
3992
13800469
GR		 3993static void igb_check_wvbr(struct igb_adapter *adapter)
3994{
3995 struct e1000_hw *hw = &adapter->hw;
3996 u32 wvbr = 0;
3997
3998 switch (hw->mac.type) {
3999 case e1000_82576:
4000 case e1000_i350:
4001 if (!(wvbr = rd32(E1000_WVBR)))
4002 return;
4003 break;
4004 default:
4005 break;
4006 }
4007
4008 adapter->wvbr |= wvbr;
4009}
4010
4011#define IGB_STAGGERED_QUEUE_OFFSET 8
4012
4013static void igb_spoof_check(struct igb_adapter *adapter)
4014{
4015 int j;
4016
4017 if (!adapter->wvbr)
4018 return;
4019
4020 for(j = 0; j < adapter->vfs_allocated_count; j++) {
4021 if (adapter->wvbr & (1 << j) ||
4022 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4023 dev_warn(&adapter->pdev->dev,
4024 "Spoof event(s) detected on VF %d\n", j);
4025 adapter->wvbr &=
4026 ~((1 << j) |
4027 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4028 }
4029 }
4030}
4031
9d5c8243 4032/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4033 * the phy
4034 */
9d5c8243
AK		 4035static void igb_update_phy_info(unsigned long data)
4036{
4037 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4038 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4039}
4040
4d6b725e 4041/**
b980ac18
JK		 4042 * igb_has_link - check shared code for link and determine up/down
4043 * @adapter: pointer to driver private info
4d6b725e 4044 **/
3145535a 4045bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4046{
4047 struct e1000_hw *hw = &adapter->hw;
4048 bool link_active = false;
4d6b725e
AD		 4049
4050 /* get_link_status is set on LSC (link status) interrupt or
4051 * rx sequence error interrupt. get_link_status will stay
4052 * false until the e1000_check_for_link establishes link
4053 * for copper adapters ONLY
4054 */
4055 switch (hw->phy.media_type) {
4056 case e1000_media_type_copper:
e5c3370f
AA		 4057 if (!hw->mac.get_link_status)
4058 return true;
4d6b725e 4059 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4060 hw->mac.ops.check_for_link(hw);
4061 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4062 break;
4063 default:
4064 case e1000_media_type_unknown:
4065 break;
4066 }
4067
aa9b8cc4
AA		 4068 if (((hw->mac.type == e1000_i210) ||
4069 (hw->mac.type == e1000_i211)) &&
4070 (hw->phy.id == I210_I_PHY_ID)) {
4071 if (!netif_carrier_ok(adapter->netdev)) {
4072 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4073 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4074 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4075 adapter->link_check_timeout = jiffies;
4076 }
4077 }
4078
4d6b725e
AD		 4079 return link_active;
4080}
4081
563988dc
SA		 4082static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4083{
4084 bool ret = false;
4085 u32 ctrl_ext, thstat;
4086
f96a8a0b 4087 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4088 if (hw->mac.type == e1000_i350) {
4089 thstat = rd32(E1000_THSTAT);
4090 ctrl_ext = rd32(E1000_CTRL_EXT);
4091
4092 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4093 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4094 ret = !!(thstat & event);
563988dc
SA		 4095 }
4096
4097 return ret;
4098}
4099
9d5c8243 4100/**
b980ac18
JK		 4101 * igb_watchdog - Timer Call-back
4102 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4103 **/
4104static void igb_watchdog(unsigned long data)
4105{
4106 struct igb_adapter *adapter = (struct igb_adapter *)data;
4107 /* Do the rest outside of interrupt context */
4108 schedule_work(&adapter->watchdog_task);
4109}
4110
4111static void igb_watchdog_task(struct work_struct *work)
4112{
4113 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4114 struct igb_adapter,
4115 watchdog_task);
9d5c8243 4116 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4117 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4118 struct net_device *netdev = adapter->netdev;
563988dc 4119 u32 link;
7a6ea550 4120 int i;
56cec249 4121 u32 connsw;
9d5c8243 4122
4d6b725e 4123 link = igb_has_link(adapter);
aa9b8cc4
AA		 4124
4125 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4126 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4127 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4128 else
4129 link = false;
4130 }
4131
56cec249
CW		 4132 /* Force link down if we have fiber to swap to */
4133 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4134 if (hw->phy.media_type == e1000_media_type_copper) {
4135 connsw = rd32(E1000_CONNSW);
4136 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4137 link = 0;
4138 }
4139 }
9d5c8243 4140 if (link) {
2bdfc4e2
CW		 4141 /* Perform a reset if the media type changed. */
4142 if (hw->dev_spec._82575.media_changed) {
4143 hw->dev_spec._82575.media_changed = false;
4144 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4145 igb_reset(adapter);
4146 }
749ab2cd
YZ		 4147 /* Cancel scheduled suspend requests. */
4148 pm_runtime_resume(netdev->dev.parent);
4149
9d5c8243
AK		 4150 if (!netif_carrier_ok(netdev)) {
4151 u32 ctrl;
330a6d6a 4152 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4153 &adapter->link_speed,
4154 &adapter->link_duplex);
9d5c8243
AK		 4155
4156 ctrl = rd32(E1000_CTRL);
527d47c1 4157 /* Links status message must follow this format */
876d2d6f
JK		 4158 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
4159 "Duplex, Flow Control: %s\n",
559e9c49
AD		 4160 netdev->name,
4161 adapter->link_speed,
4162 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4163 "Full" : "Half",
4164 (ctrl & E1000_CTRL_TFCE) &&
4165 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4166 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4167 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4168
c0ba4778
KS		 4169 /* check if SmartSpeed worked */
4170 igb_check_downshift(hw);
4171 if (phy->speed_downgraded)
4172 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4173
563988dc 4174 /* check for thermal sensor event */
876d2d6f
JK		 4175 if (igb_thermal_sensor_event(hw,
4176 E1000_THSTAT_LINK_THROTTLE)) {
4177 netdev_info(netdev, "The network adapter link "
4178 "speed was downshifted because it "
4179 "overheated\n");
7ef5ed1c 4180 }
563988dc 4181
d07f3e37 4182 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4183 adapter->tx_timeout_factor = 1;
4184 switch (adapter->link_speed) {
4185 case SPEED_10:
9d5c8243
AK		 4186 adapter->tx_timeout_factor = 14;
4187 break;
4188 case SPEED_100:
9d5c8243
AK		 4189 /* maybe add some timeout factor ? */
4190 break;
4191 }
4192
4193 netif_carrier_on(netdev);
9d5c8243 4194
4ae196df 4195 igb_ping_all_vfs(adapter);
17dc566c 4196 igb_check_vf_rate_limit(adapter);
4ae196df 4197
4b1a9877 4198 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4199 if (!test_bit(__IGB_DOWN, &adapter->state))
4200 mod_timer(&adapter->phy_info_timer,
4201 round_jiffies(jiffies + 2 * HZ));
4202 }
4203 } else {
4204 if (netif_carrier_ok(netdev)) {
4205 adapter->link_speed = 0;
4206 adapter->link_duplex = 0;
563988dc
SA		 4207
4208 /* check for thermal sensor event */
876d2d6f
JK		 4209 if (igb_thermal_sensor_event(hw,
4210 E1000_THSTAT_PWR_DOWN)) {
4211 netdev_err(netdev, "The network adapter was "
4212 "stopped because it overheated\n");
7ef5ed1c 4213 }
563988dc 4214
527d47c1
AD		 4215 /* Links status message must follow this format */
4216 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4217 netdev->name);
9d5c8243 4218 netif_carrier_off(netdev);
4b1a9877 4219
4ae196df
AD		 4220 igb_ping_all_vfs(adapter);
4221
4b1a9877 4222 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4223 if (!test_bit(__IGB_DOWN, &adapter->state))
4224 mod_timer(&adapter->phy_info_timer,
4225 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4226
56cec249
CW		 4227 /* link is down, time to check for alternate media */
4228 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4229 igb_check_swap_media(adapter);
4230 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4231 schedule_work(&adapter->reset_task);
4232 /* return immediately */
4233 return;
4234 }
4235 }
749ab2cd
YZ		 4236 pm_schedule_suspend(netdev->dev.parent,
4237 MSEC_PER_SEC * 5);
56cec249
CW		 4238
4239 /* also check for alternate media here */
4240 } else if (!netif_carrier_ok(netdev) &&
4241 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4242 igb_check_swap_media(adapter);
4243 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4244 schedule_work(&adapter->reset_task);
4245 /* return immediately */
4246 return;
4247 }
9d5c8243
AK		 4248 }
4249 }
4250
12dcd86b
ED		 4251 spin_lock(&adapter->stats64_lock);
4252 igb_update_stats(adapter, &adapter->stats64);
4253 spin_unlock(&adapter->stats64_lock);
9d5c8243 4254
dbabb065 4255 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4256 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4257 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4258 /* We've lost link, so the controller stops DMA,
4259 * but we've got queued Tx work that's never going
4260 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4261 * (Do the reset outside of interrupt context).
4262 */
dbabb065
AD		 4263 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4264 adapter->tx_timeout_count++;
4265 schedule_work(&adapter->reset_task);
4266 /* return immediately since reset is imminent */
4267 return;
4268 }
9d5c8243 4269 }
9d5c8243 4270
dbabb065 4271 /* Force detection of hung controller every watchdog period */
6d095fa8 4272 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4273 }
f7ba205e 4274
b980ac18 4275 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4276 if (adapter->msix_entries) {
047e0030 4277 u32 eics = 0;
0d1ae7f4
AD		 4278 for (i = 0; i < adapter->num_q_vectors; i++)
4279 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4280 wr32(E1000_EICS, eics);
4281 } else {
4282 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4283 }
9d5c8243 4284
13800469 4285 igb_spoof_check(adapter);
fc580751 4286 igb_ptp_rx_hang(adapter);
13800469 4287
9d5c8243 4288 /* Reset the timer */
aa9b8cc4
AA		 4289 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4290 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4291 mod_timer(&adapter->watchdog_timer,
4292 round_jiffies(jiffies + HZ));
4293 else
4294 mod_timer(&adapter->watchdog_timer,
4295 round_jiffies(jiffies + 2 * HZ));
4296 }
9d5c8243
AK		 4297}
4298
4299enum latency_range {
4300 lowest_latency = 0,
4301 low_latency = 1,
4302 bulk_latency = 2,
4303 latency_invalid = 255
4304};
4305
6eb5a7f1 4306/**
b980ac18
JK		 4307 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4308 * @q_vector: pointer to q_vector
6eb5a7f1 4309 *
b980ac18
JK		 4310 * Stores a new ITR value based on strictly on packet size. This
4311 * algorithm is less sophisticated than that used in igb_update_itr,
4312 * due to the difficulty of synchronizing statistics across multiple
4313 * receive rings. The divisors and thresholds used by this function
4314 * were determined based on theoretical maximum wire speed and testing
4315 * data, in order to minimize response time while increasing bulk
4316 * throughput.
4317 * This functionality is controlled by the InterruptThrottleRate module
4318 * parameter (see igb_param.c)
4319 * NOTE: This function is called only when operating in a multiqueue
4320 * receive environment.
6eb5a7f1 4321 **/
047e0030 4322static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4323{
047e0030 4324 int new_val = q_vector->itr_val;
6eb5a7f1 4325 int avg_wire_size = 0;
047e0030 4326 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4327 unsigned int packets;
9d5c8243 4328
6eb5a7f1
AD		 4329 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4330 * ints/sec - ITR timer value of 120 ticks.
4331 */
4332 if (adapter->link_speed != SPEED_1000) {
0ba82994 4333 new_val = IGB_4K_ITR;
6eb5a7f1 4334 goto set_itr_val;
9d5c8243 4335 }
047e0030 4336
0ba82994
AD		 4337 packets = q_vector->rx.total_packets;
4338 if (packets)
4339 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4340
0ba82994
AD		 4341 packets = q_vector->tx.total_packets;
4342 if (packets)
4343 avg_wire_size = max_t(u32, avg_wire_size,
4344 q_vector->tx.total_bytes / packets);
047e0030
AD		 4345
4346 /* if avg_wire_size isn't set no work was done */
4347 if (!avg_wire_size)
4348 goto clear_counts;
9d5c8243 4349
6eb5a7f1
AD		 4350 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4351 avg_wire_size += 24;
4352
4353 /* Don't starve jumbo frames */
4354 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4355
6eb5a7f1
AD		 4356 /* Give a little boost to mid-size frames */
4357 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4358 new_val = avg_wire_size / 3;
4359 else
4360 new_val = avg_wire_size / 2;
9d5c8243 4361
0ba82994
AD		 4362 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4363 if (new_val < IGB_20K_ITR &&
4364 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4365 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4366 new_val = IGB_20K_ITR;
abe1c363 4367
6eb5a7f1 4368set_itr_val:
047e0030
AD		 4369 if (new_val != q_vector->itr_val) {
4370 q_vector->itr_val = new_val;
4371 q_vector->set_itr = 1;
9d5c8243 4372 }
6eb5a7f1 4373clear_counts:
0ba82994
AD		 4374 q_vector->rx.total_bytes = 0;
4375 q_vector->rx.total_packets = 0;
4376 q_vector->tx.total_bytes = 0;
4377 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4378}
4379
4380/**
b980ac18
JK		 4381 * igb_update_itr - update the dynamic ITR value based on statistics
4382 * @q_vector: pointer to q_vector
4383 * @ring_container: ring info to update the itr for
4384 *
4385 * Stores a new ITR value based on packets and byte
4386 * counts during the last interrupt. The advantage of per interrupt
4387 * computation is faster updates and more accurate ITR for the current
4388 * traffic pattern. Constants in this function were computed
4389 * based on theoretical maximum wire speed and thresholds were set based
4390 * on testing data as well as attempting to minimize response time
4391 * while increasing bulk throughput.
4392 * this functionality is controlled by the InterruptThrottleRate module
4393 * parameter (see igb_param.c)
4394 * NOTE: These calculations are only valid when operating in a single-
4395 * queue environment.
9d5c8243 4396 **/
0ba82994
AD		 4397static void igb_update_itr(struct igb_q_vector *q_vector,
4398 struct igb_ring_container *ring_container)
9d5c8243 4399{
0ba82994
AD		 4400 unsigned int packets = ring_container->total_packets;
4401 unsigned int bytes = ring_container->total_bytes;
4402 u8 itrval = ring_container->itr;
9d5c8243 4403
0ba82994 4404 /* no packets, exit with status unchanged */
9d5c8243 4405 if (packets == 0)
0ba82994 4406 return;
9d5c8243 4407
0ba82994 4408 switch (itrval) {
9d5c8243
AK		 4409 case lowest_latency:
4410 /* handle TSO and jumbo frames */
4411 if (bytes/packets > 8000)
0ba82994 4412 itrval = bulk_latency;
9d5c8243 4413 else if ((packets < 5) && (bytes > 512))
0ba82994 4414 itrval = low_latency;
9d5c8243
AK		 4415 break;
4416 case low_latency: /* 50 usec aka 20000 ints/s */
4417 if (bytes > 10000) {
4418 /* this if handles the TSO accounting */
4419 if (bytes/packets > 8000) {
0ba82994 4420 itrval = bulk_latency;
9d5c8243 4421 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4422 itrval = bulk_latency;
9d5c8243 4423 } else if ((packets > 35)) {
0ba82994 4424 itrval = lowest_latency;
9d5c8243
AK		 4425 }
4426 } else if (bytes/packets > 2000) {
0ba82994 4427 itrval = bulk_latency;
9d5c8243 4428 } else if (packets <= 2 && bytes < 512) {
0ba82994 4429 itrval = lowest_latency;
9d5c8243
AK		 4430 }
4431 break;
4432 case bulk_latency: /* 250 usec aka 4000 ints/s */
4433 if (bytes > 25000) {
4434 if (packets > 35)
0ba82994 4435 itrval = low_latency;
1e5c3d21 4436 } else if (bytes < 1500) {
0ba82994 4437 itrval = low_latency;
9d5c8243
AK		 4438 }
4439 break;
4440 }
4441
0ba82994
AD		 4442 /* clear work counters since we have the values we need */
4443 ring_container->total_bytes = 0;
4444 ring_container->total_packets = 0;
4445
4446 /* write updated itr to ring container */
4447 ring_container->itr = itrval;
9d5c8243
AK		 4448}
4449
0ba82994 4450static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4451{
0ba82994 4452 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4453 u32 new_itr = q_vector->itr_val;
0ba82994 4454 u8 current_itr = 0;
9d5c8243
AK		 4455
4456 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4457 if (adapter->link_speed != SPEED_1000) {
4458 current_itr = 0;
0ba82994 4459 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4460 goto set_itr_now;
4461 }
4462
0ba82994
AD		 4463 igb_update_itr(q_vector, &q_vector->tx);
4464 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4465
0ba82994 4466 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4467
6eb5a7f1 4468 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4469 if (current_itr == lowest_latency &&
4470 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4471 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4472 current_itr = low_latency;
4473
9d5c8243
AK		 4474 switch (current_itr) {
4475 /* counts and packets in update_itr are dependent on these numbers */
4476 case lowest_latency:
0ba82994 4477 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4478 break;
4479 case low_latency:
0ba82994 4480 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4481 break;
4482 case bulk_latency:
0ba82994 4483 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4484 break;
4485 default:
4486 break;
4487 }
4488
4489set_itr_now:
047e0030 4490 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4491 /* this attempts to bias the interrupt rate towards Bulk
4492 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4493 * increasing
4494 */
047e0030 4495 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4496 max((new_itr * q_vector->itr_val) /
4497 (new_itr + (q_vector->itr_val >> 2)),
4498 new_itr) : new_itr;
9d5c8243
AK		 4499 /* Don't write the value here; it resets the adapter's
4500 * internal timer, and causes us to delay far longer than
4501 * we should between interrupts. Instead, we write the ITR
4502 * value at the beginning of the next interrupt so the timing
4503 * ends up being correct.
4504 */
047e0030
AD		 4505 q_vector->itr_val = new_itr;
4506 q_vector->set_itr = 1;
9d5c8243 4507 }
9d5c8243
AK		 4508}
4509
c50b52a0
SH		 4510static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4511 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4512{
4513 struct e1000_adv_tx_context_desc *context_desc;
4514 u16 i = tx_ring->next_to_use;
4515
4516 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4517
4518 i++;
4519 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4520
4521 /* set bits to identify this as an advanced context descriptor */
4522 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4523
4524 /* For 82575, context index must be unique per ring. */
866cff06 4525 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4526 mss_l4len_idx |= tx_ring->reg_idx << 4;
4527
4528 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4529 context_desc->seqnum_seed = 0;
4530 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4531 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4532}
4533
7af40ad9
AD		 4534static int igb_tso(struct igb_ring *tx_ring,
4535 struct igb_tx_buffer *first,
4536 u8 *hdr_len)
9d5c8243 4537{
7af40ad9 4538 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4539 u32 vlan_macip_lens, type_tucmd;
4540 u32 mss_l4len_idx, l4len;
4541
ed6aa105
AD		 4542 if (skb->ip_summed != CHECKSUM_PARTIAL)
4543 return 0;
4544
7d13a7d0
AD		 4545 if (!skb_is_gso(skb))
4546 return 0;
9d5c8243
AK		 4547
4548 if (skb_header_cloned(skb)) {
7af40ad9 4549 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4550 if (err)
4551 return err;
4552 }
4553
7d13a7d0
AD		 4554 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4555 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4556
7af40ad9 4557 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4558 struct iphdr *iph = ip_hdr(skb);
4559 iph->tot_len = 0;
4560 iph->check = 0;
4561 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4562 iph->daddr, 0,
4563 IPPROTO_TCP,
4564 0);
7d13a7d0 4565 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4566 first->tx_flags |= IGB_TX_FLAGS_TSO |
4567 IGB_TX_FLAGS_CSUM |
4568 IGB_TX_FLAGS_IPV4;
8e1e8a47 4569 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4570 ipv6_hdr(skb)->payload_len = 0;
4571 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4572 &ipv6_hdr(skb)->daddr,
4573 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4574 first->tx_flags |= IGB_TX_FLAGS_TSO |
4575 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4576 }
4577
7af40ad9 4578 /* compute header lengths */
7d13a7d0
AD		 4579 l4len = tcp_hdrlen(skb);
4580 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4581
7af40ad9
AD		 4582 /* update gso size and bytecount with header size */
4583 first->gso_segs = skb_shinfo(skb)->gso_segs;
4584 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4585
9d5c8243 4586 /* MSS L4LEN IDX */
7d13a7d0
AD		 4587 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4588 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4589
7d13a7d0
AD		 4590 /* VLAN MACLEN IPLEN */
4591 vlan_macip_lens = skb_network_header_len(skb);
4592 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4593 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4594
7d13a7d0 4595 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4596
7d13a7d0 4597 return 1;
9d5c8243
AK		 4598}
4599
7af40ad9 4600static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4601{
7af40ad9 4602 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4603 u32 vlan_macip_lens = 0;
4604 u32 mss_l4len_idx = 0;
4605 u32 type_tucmd = 0;
9d5c8243 4606
7d13a7d0 4607 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4608 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4609 return;
7d13a7d0
AD		 4610 } else {
4611 u8 l4_hdr = 0;
7af40ad9 4612 switch (first->protocol) {
7d13a7d0
AD		 4613 case __constant_htons(ETH_P_IP):
4614 vlan_macip_lens |= skb_network_header_len(skb);
4615 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4616 l4_hdr = ip_hdr(skb)->protocol;
4617 break;
4618 case __constant_htons(ETH_P_IPV6):
4619 vlan_macip_lens |= skb_network_header_len(skb);
4620 l4_hdr = ipv6_hdr(skb)->nexthdr;
4621 break;
4622 default:
4623 if (unlikely(net_ratelimit())) {
4624 dev_warn(tx_ring->dev,
b980ac18
JK		 4625 "partial checksum but proto=%x!\n",
4626 first->protocol);
fa4a7ef3 4627 }
7d13a7d0
AD		 4628 break;
4629 }
fa4a7ef3 4630
7d13a7d0
AD		 4631 switch (l4_hdr) {
4632 case IPPROTO_TCP:
4633 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4634 mss_l4len_idx = tcp_hdrlen(skb) <<
4635 E1000_ADVTXD_L4LEN_SHIFT;
4636 break;
4637 case IPPROTO_SCTP:
4638 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4639 mss_l4len_idx = sizeof(struct sctphdr) <<
4640 E1000_ADVTXD_L4LEN_SHIFT;
4641 break;
4642 case IPPROTO_UDP:
4643 mss_l4len_idx = sizeof(struct udphdr) <<
4644 E1000_ADVTXD_L4LEN_SHIFT;
4645 break;
4646 default:
4647 if (unlikely(net_ratelimit())) {
4648 dev_warn(tx_ring->dev,
b980ac18
JK		 4649 "partial checksum but l4 proto=%x!\n",
4650 l4_hdr);
44b0cda3 4651 }
7d13a7d0 4652 break;
9d5c8243 4653 }
7af40ad9
AD		 4654
4655 /* update TX checksum flag */
4656 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4657 }
9d5c8243 4658
7d13a7d0 4659 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4660 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4661
7d13a7d0 4662 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4663}
4664
1d9daf45
AD		 4665#define IGB_SET_FLAG(_input, _flag, _result) \
4666 ((_flag <= _result) ? \
4667 ((u32)(_input & _flag) * (_result / _flag)) : \
4668 ((u32)(_input & _flag) / (_flag / _result)))
4669
4670static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4671{
4672 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4673 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4674 E1000_ADVTXD_DCMD_DEXT |
4675 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4676
4677 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4678 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4679 (E1000_ADVTXD_DCMD_VLE));
4680
4681 /* set segmentation bits for TSO */
4682 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4683 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4684
4685 /* set timestamp bit if present */
1d9daf45
AD		 4686 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4687 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4688
1d9daf45
AD		 4689 /* insert frame checksum */
4690 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4691
4692 return cmd_type;
4693}
4694
7af40ad9
AD		 4695static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4696 union e1000_adv_tx_desc *tx_desc,
4697 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4698{
4699 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4700
1d9daf45
AD		 4701 /* 82575 requires a unique index per ring */
4702 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4703 olinfo_status |= tx_ring->reg_idx << 4;
4704
4705 /* insert L4 checksum */
1d9daf45
AD		 4706 olinfo_status |= IGB_SET_FLAG(tx_flags,
4707 IGB_TX_FLAGS_CSUM,
4708 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4709
1d9daf45
AD		 4710 /* insert IPv4 checksum */
4711 olinfo_status |= IGB_SET_FLAG(tx_flags,
4712 IGB_TX_FLAGS_IPV4,
4713 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4714
7af40ad9 4715 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4716}
4717
7af40ad9
AD		 4718static void igb_tx_map(struct igb_ring *tx_ring,
4719 struct igb_tx_buffer *first,
ebe42d16 4720 const u8 hdr_len)
9d5c8243 4721{
7af40ad9 4722 struct sk_buff *skb = first->skb;
c9f14bf3 4723 struct igb_tx_buffer *tx_buffer;
ebe42d16 4724 union e1000_adv_tx_desc *tx_desc;
80d0759e 4725 struct skb_frag_struct *frag;
ebe42d16 4726 dma_addr_t dma;
80d0759e 4727 unsigned int data_len, size;
7af40ad9 4728 u32 tx_flags = first->tx_flags;
1d9daf45 4729 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4730 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4731
4732 tx_desc = IGB_TX_DESC(tx_ring, i);
4733
80d0759e
AD		 4734 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4735
4736 size = skb_headlen(skb);
4737 data_len = skb->data_len;
ebe42d16
AD		 4738
4739 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4740
80d0759e
AD		 4741 tx_buffer = first;
4742
4743 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4744 if (dma_mapping_error(tx_ring->dev, dma))
4745 goto dma_error;
4746
4747 /* record length, and DMA address */
4748 dma_unmap_len_set(tx_buffer, len, size);
4749 dma_unmap_addr_set(tx_buffer, dma, dma);
4750
4751 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4752
ebe42d16
AD		 4753 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4754 tx_desc->read.cmd_type_len =
1d9daf45 4755 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4756
4757 i++;
4758 tx_desc++;
4759 if (i == tx_ring->count) {
4760 tx_desc = IGB_TX_DESC(tx_ring, 0);
4761 i = 0;
4762 }
80d0759e 4763 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4764
4765 dma += IGB_MAX_DATA_PER_TXD;
4766 size -= IGB_MAX_DATA_PER_TXD;
4767
ebe42d16
AD		 4768 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4769 }
4770
4771 if (likely(!data_len))
4772 break;
2bbfebe2 4773
1d9daf45 4774 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4775
65689fef 4776 i++;
ebe42d16
AD		 4777 tx_desc++;
4778 if (i == tx_ring->count) {
4779 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4780 i = 0;
ebe42d16 4781 }
80d0759e 4782 tx_desc->read.olinfo_status = 0;
65689fef 4783
9e903e08 4784 size = skb_frag_size(frag);
ebe42d16
AD		 4785 data_len -= size;
4786
4787 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4788 size, DMA_TO_DEVICE);
6366ad33 4789
c9f14bf3 4790 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4791 }
4792
ebe42d16 4793 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4794 cmd_type |= size | IGB_TXD_DCMD;
4795 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4796
80d0759e
AD		 4797 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4798
8542db05
AD		 4799 /* set the timestamp */
4800 first->time_stamp = jiffies;
4801
b980ac18 4802 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4803 * are new descriptors to fetch. (Only applicable for weak-ordered
4804 * memory model archs, such as IA-64).
4805 *
4806 * We also need this memory barrier to make certain all of the
4807 * status bits have been updated before next_to_watch is written.
4808 */
4809 wmb();
4810
8542db05 4811 /* set next_to_watch value indicating a packet is present */
ebe42d16 4812 first->next_to_watch = tx_desc;
9d5c8243 4813
ebe42d16
AD		 4814 i++;
4815 if (i == tx_ring->count)
4816 i = 0;
6366ad33 4817
ebe42d16 4818 tx_ring->next_to_use = i;
6366ad33 4819
ebe42d16 4820 writel(i, tx_ring->tail);
6366ad33 4821
ebe42d16 4822 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4823 * at a time, it synchronizes IO on IA64/Altix systems
4824 */
ebe42d16
AD		 4825 mmiowb();
4826
4827 return;
4828
4829dma_error:
4830 dev_err(tx_ring->dev, "TX DMA map failed\n");
4831
4832 /* clear dma mappings for failed tx_buffer_info map */
4833 for (;;) {
c9f14bf3
AD		 4834 tx_buffer = &tx_ring->tx_buffer_info[i];
4835 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4836 if (tx_buffer == first)
ebe42d16 4837 break;
a77ff709
NN		 4838 if (i == 0)
4839 i = tx_ring->count;
6366ad33 4840 i--;
6366ad33
AD		 4841 }
4842
9d5c8243 4843 tx_ring->next_to_use = i;
9d5c8243
AK		 4844}
4845
6ad4edfc 4846static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4847{
e694e964
AD		 4848 struct net_device *netdev = tx_ring->netdev;
4849
661086df 4850 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4851
9d5c8243
AK		 4852 /* Herbert's original patch had:
4853 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4854 * but since that doesn't exist yet, just open code it.
4855 */
9d5c8243
AK		 4856 smp_mb();
4857
4858 /* We need to check again in a case another CPU has just
b980ac18
JK		 4859 * made room available.
4860 */
c493ea45 4861 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4862 return -EBUSY;
4863
4864 /* A reprieve! */
661086df 4865 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4866
4867 u64_stats_update_begin(&tx_ring->tx_syncp2);
4868 tx_ring->tx_stats.restart_queue2++;
4869 u64_stats_update_end(&tx_ring->tx_syncp2);
4870
9d5c8243
AK		 4871 return 0;
4872}
4873
6ad4edfc 4874static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4875{
c493ea45 4876 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4877 return 0;
e694e964 4878 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4879}
4880
cd392f5c
AD		 4881netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4882 struct igb_ring *tx_ring)
9d5c8243 4883{
8542db05 4884 struct igb_tx_buffer *first;
ebe42d16 4885 int tso;
91d4ee33 4886 u32 tx_flags = 0;
21ba6fe1 4887 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4888 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4889 u8 hdr_len = 0;
9d5c8243 4890
21ba6fe1
AD		 4891 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4892 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4893 * + 2 desc gap to keep tail from touching head,
9d5c8243 4894 * + 1 desc for context descriptor,
21ba6fe1
AD		 4895 * otherwise try next time
4896 */
4897 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4898 unsigned short f;
4899 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4900 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4901 } else {
4902 count += skb_shinfo(skb)->nr_frags;
4903 }
4904
4905 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4906 /* this is a hard error */
9d5c8243
AK		 4907 return NETDEV_TX_BUSY;
4908 }
33af6bcc 4909
7af40ad9
AD		 4910 /* record the location of the first descriptor for this packet */
4911 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4912 first->skb = skb;
4913 first->bytecount = skb->len;
4914 first->gso_segs = 1;
4915
b66e2397
MV		 4916 skb_tx_timestamp(skb);
4917
b646c22e
AD		 4918 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4919 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4920
b646c22e
AD		 4921 if (!(adapter->ptp_tx_skb)) {
4922 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4923 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4924
4925 adapter->ptp_tx_skb = skb_get(skb);
4926 adapter->ptp_tx_start = jiffies;
4927 if (adapter->hw.mac.type == e1000_82576)
4928 schedule_work(&adapter->ptp_tx_work);
4929 }
33af6bcc 4930 }
9d5c8243 4931
eab6d18d 4932 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4933 tx_flags |= IGB_TX_FLAGS_VLAN;
4934 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4935 }
4936
7af40ad9
AD		 4937 /* record initial flags and protocol */
4938 first->tx_flags = tx_flags;
4939 first->protocol = protocol;
cdfd01fc 4940
7af40ad9
AD		 4941 tso = igb_tso(tx_ring, first, &hdr_len);
4942 if (tso < 0)
7d13a7d0 4943 goto out_drop;
7af40ad9
AD		 4944 else if (!tso)
4945 igb_tx_csum(tx_ring, first);
9d5c8243 4946
7af40ad9 4947 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4948
4949 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4950 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4951
9d5c8243 4952 return NETDEV_TX_OK;
7d13a7d0
AD		 4953
4954out_drop:
7af40ad9
AD		 4955 igb_unmap_and_free_tx_resource(tx_ring, first);
4956
7d13a7d0 4957 return NETDEV_TX_OK;
9d5c8243
AK		 4958}
4959
1cc3bd87
AD		 4960static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4961 struct sk_buff *skb)
4962{
4963 unsigned int r_idx = skb->queue_mapping;
4964
4965 if (r_idx >= adapter->num_tx_queues)
4966 r_idx = r_idx % adapter->num_tx_queues;
4967
4968 return adapter->tx_ring[r_idx];
4969}
4970
cd392f5c
AD		 4971static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4972 struct net_device *netdev)
9d5c8243
AK		 4973{
4974 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4975
4976 if (test_bit(__IGB_DOWN, &adapter->state)) {
4977 dev_kfree_skb_any(skb);
4978 return NETDEV_TX_OK;
4979 }
4980
4981 if (skb->len <= 0) {
4982 dev_kfree_skb_any(skb);
4983 return NETDEV_TX_OK;
4984 }
4985
b980ac18 4986 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4987 * in order to meet this minimum size requirement.
4988 */
ea5ceeab
TD		 4989 if (unlikely(skb->len < 17)) {
4990 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4991 return NETDEV_TX_OK;
4992 skb->len = 17;
ea5ceeab 4993 skb_set_tail_pointer(skb, 17);
1cc3bd87 4994 }
9d5c8243 4995
1cc3bd87 4996 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4997}
4998
4999/**
b980ac18
JK		 5000 * igb_tx_timeout - Respond to a Tx Hang
5001 * @netdev: network interface device structure
9d5c8243
AK		 5002 **/
5003static void igb_tx_timeout(struct net_device *netdev)
5004{
5005 struct igb_adapter *adapter = netdev_priv(netdev);
5006 struct e1000_hw *hw = &adapter->hw;
5007
5008 /* Do the reset outside of interrupt context */
5009 adapter->tx_timeout_count++;
f7ba205e 5010
06218a8d 5011 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5012 hw->dev_spec._82575.global_device_reset = true;
5013
9d5c8243 5014 schedule_work(&adapter->reset_task);
265de409
AD		 5015 wr32(E1000_EICS,
5016 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5017}
5018
5019static void igb_reset_task(struct work_struct *work)
5020{
5021 struct igb_adapter *adapter;
5022 adapter = container_of(work, struct igb_adapter, reset_task);
5023
c97ec42a
TI		 5024 igb_dump(adapter);
5025 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5026 igb_reinit_locked(adapter);
5027}
5028
5029/**
b980ac18
JK		 5030 * igb_get_stats64 - Get System Network Statistics
5031 * @netdev: network interface device structure
5032 * @stats: rtnl_link_stats64 pointer
9d5c8243 5033 **/
12dcd86b 5034static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5035 struct rtnl_link_stats64 *stats)
9d5c8243 5036{
12dcd86b
ED		 5037 struct igb_adapter *adapter = netdev_priv(netdev);
5038
5039 spin_lock(&adapter->stats64_lock);
5040 igb_update_stats(adapter, &adapter->stats64);
5041 memcpy(stats, &adapter->stats64, sizeof(*stats));
5042 spin_unlock(&adapter->stats64_lock);
5043
5044 return stats;
9d5c8243
AK		 5045}
5046
5047/**
b980ac18
JK		 5048 * igb_change_mtu - Change the Maximum Transfer Unit
5049 * @netdev: network interface device structure
5050 * @new_mtu: new value for maximum frame size
9d5c8243 5051 *
b980ac18 5052 * Returns 0 on success, negative on failure
9d5c8243
AK		 5053 **/
5054static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5055{
5056 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5057 struct pci_dev *pdev = adapter->pdev;
153285f9 5058 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5059
c809d227 5060 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5061 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5062 return -EINVAL;
5063 }
5064
153285f9 5065#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5066 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5067 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5068 return -EINVAL;
5069 }
5070
2ccd994c
AD		 5071 /* adjust max frame to be at least the size of a standard frame */
5072 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5073 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5074
9d5c8243
AK		 5075 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5076 msleep(1);
73cd78f1 5077
9d5c8243
AK		 5078 /* igb_down has a dependency on max_frame_size */
5079 adapter->max_frame_size = max_frame;
559e9c49 5080
4c844851
AD		 5081 if (netif_running(netdev))
5082 igb_down(adapter);
9d5c8243 5083
090b1795 5084 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5085 netdev->mtu, new_mtu);
5086 netdev->mtu = new_mtu;
5087
5088 if (netif_running(netdev))
5089 igb_up(adapter);
5090 else
5091 igb_reset(adapter);
5092
5093 clear_bit(__IGB_RESETTING, &adapter->state);
5094
5095 return 0;
5096}
5097
5098/**
b980ac18
JK		 5099 * igb_update_stats - Update the board statistics counters
5100 * @adapter: board private structure
9d5c8243 5101 **/
12dcd86b
ED		 5102void igb_update_stats(struct igb_adapter *adapter,
5103 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5104{
5105 struct e1000_hw *hw = &adapter->hw;
5106 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5107 u32 reg, mpc;
9d5c8243 5108 u16 phy_tmp;
3f9c0164
AD		 5109 int i;
5110 u64 bytes, packets;
12dcd86b
ED		 5111 unsigned int start;
5112 u64 _bytes, _packets;
9d5c8243
AK		 5113
5114#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
5115
b980ac18 5116 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5117 * connection is down.
5118 */
5119 if (adapter->link_speed == 0)
5120 return;
5121 if (pci_channel_offline(pdev))
5122 return;
5123
3f9c0164
AD		 5124 bytes = 0;
5125 packets = 0;
7f90128e
AA		 5126
5127 rcu_read_lock();
3f9c0164 5128 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 5129 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 5130 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 5131
ae1c07a6
AD		 5132 if (rqdpc) {
5133 ring->rx_stats.drops += rqdpc;
5134 net_stats->rx_fifo_errors += rqdpc;
5135 }
12dcd86b
ED		 5136
5137 do {
5138 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
5139 _bytes = ring->rx_stats.bytes;
5140 _packets = ring->rx_stats.packets;
5141 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
5142 bytes += _bytes;
5143 packets += _packets;
3f9c0164
AD		 5144 }
5145
128e45eb
AD		 5146 net_stats->rx_bytes = bytes;
5147 net_stats->rx_packets = packets;
3f9c0164
AD		 5148
5149 bytes = 0;
5150 packets = 0;
5151 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5152 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 5153 do {
5154 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
5155 _bytes = ring->tx_stats.bytes;
5156 _packets = ring->tx_stats.packets;
5157 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
5158 bytes += _bytes;
5159 packets += _packets;
3f9c0164 5160 }
128e45eb
AD		 5161 net_stats->tx_bytes = bytes;
5162 net_stats->tx_packets = packets;
7f90128e 5163 rcu_read_unlock();
3f9c0164
AD		 5164
5165 /* read stats registers */
9d5c8243
AK		 5166 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5167 adapter->stats.gprc += rd32(E1000_GPRC);
5168 adapter->stats.gorc += rd32(E1000_GORCL);
5169 rd32(E1000_GORCH); /* clear GORCL */
5170 adapter->stats.bprc += rd32(E1000_BPRC);
5171 adapter->stats.mprc += rd32(E1000_MPRC);
5172 adapter->stats.roc += rd32(E1000_ROC);
5173
5174 adapter->stats.prc64 += rd32(E1000_PRC64);
5175 adapter->stats.prc127 += rd32(E1000_PRC127);
5176 adapter->stats.prc255 += rd32(E1000_PRC255);
5177 adapter->stats.prc511 += rd32(E1000_PRC511);
5178 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5179 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5180 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5181 adapter->stats.sec += rd32(E1000_SEC);
5182
fa3d9a6d
MW		 5183 mpc = rd32(E1000_MPC);
5184 adapter->stats.mpc += mpc;
5185 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5186 adapter->stats.scc += rd32(E1000_SCC);
5187 adapter->stats.ecol += rd32(E1000_ECOL);
5188 adapter->stats.mcc += rd32(E1000_MCC);
5189 adapter->stats.latecol += rd32(E1000_LATECOL);
5190 adapter->stats.dc += rd32(E1000_DC);
5191 adapter->stats.rlec += rd32(E1000_RLEC);
5192 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5193 adapter->stats.xontxc += rd32(E1000_XONTXC);
5194 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5195 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5196 adapter->stats.fcruc += rd32(E1000_FCRUC);
5197 adapter->stats.gptc += rd32(E1000_GPTC);
5198 adapter->stats.gotc += rd32(E1000_GOTCL);
5199 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5200 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5201 adapter->stats.ruc += rd32(E1000_RUC);
5202 adapter->stats.rfc += rd32(E1000_RFC);
5203 adapter->stats.rjc += rd32(E1000_RJC);
5204 adapter->stats.tor += rd32(E1000_TORH);
5205 adapter->stats.tot += rd32(E1000_TOTH);
5206 adapter->stats.tpr += rd32(E1000_TPR);
5207
5208 adapter->stats.ptc64 += rd32(E1000_PTC64);
5209 adapter->stats.ptc127 += rd32(E1000_PTC127);
5210 adapter->stats.ptc255 += rd32(E1000_PTC255);
5211 adapter->stats.ptc511 += rd32(E1000_PTC511);
5212 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5213 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5214
5215 adapter->stats.mptc += rd32(E1000_MPTC);
5216 adapter->stats.bptc += rd32(E1000_BPTC);
5217
2d0b0f69
NN		 5218 adapter->stats.tpt += rd32(E1000_TPT);
5219 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5220
5221 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5222 /* read internal phy specific stats */
5223 reg = rd32(E1000_CTRL_EXT);
5224 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5225 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5226
5227 /* this stat has invalid values on i210/i211 */
5228 if ((hw->mac.type != e1000_i210) &&
5229 (hw->mac.type != e1000_i211))
5230 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5231 }
5232
9d5c8243
AK		 5233 adapter->stats.tsctc += rd32(E1000_TSCTC);
5234 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5235
5236 adapter->stats.iac += rd32(E1000_IAC);
5237 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5238 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5239 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5240 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5241 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5242 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5243 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5244 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5245
5246 /* Fill out the OS statistics structure */
128e45eb
AD		 5247 net_stats->multicast = adapter->stats.mprc;
5248 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5249
5250 /* Rx Errors */
5251
5252 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5253 * our own version based on RUC and ROC
5254 */
128e45eb 5255 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5256 adapter->stats.crcerrs + adapter->stats.algnerrc +
5257 adapter->stats.ruc + adapter->stats.roc +
5258 adapter->stats.cexterr;
128e45eb
AD		 5259 net_stats->rx_length_errors = adapter->stats.ruc +
5260 adapter->stats.roc;
5261 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5262 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5263 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5264
5265 /* Tx Errors */
128e45eb
AD		 5266 net_stats->tx_errors = adapter->stats.ecol +
5267 adapter->stats.latecol;
5268 net_stats->tx_aborted_errors = adapter->stats.ecol;
5269 net_stats->tx_window_errors = adapter->stats.latecol;
5270 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5271
5272 /* Tx Dropped needs to be maintained elsewhere */
5273
5274 /* Phy Stats */
5275 if (hw->phy.media_type == e1000_media_type_copper) {
5276 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5277 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5278 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5279 adapter->phy_stats.idle_errors += phy_tmp;
5280 }
5281 }
5282
5283 /* Management Stats */
5284 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5285 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5286 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5287
5288 /* OS2BMC Stats */
5289 reg = rd32(E1000_MANC);
5290 if (reg & E1000_MANC_EN_BMC2OS) {
5291 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5292 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5293 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5294 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5295 }
9d5c8243
AK		 5296}
5297
9d5c8243
AK		 5298static irqreturn_t igb_msix_other(int irq, void *data)
5299{
047e0030 5300 struct igb_adapter *adapter = data;
9d5c8243 5301 struct e1000_hw *hw = &adapter->hw;
844290e5 5302 u32 icr = rd32(E1000_ICR);
844290e5 5303 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5304
7f081d40
AD		 5305 if (icr & E1000_ICR_DRSTA)
5306 schedule_work(&adapter->reset_task);
5307
047e0030 5308 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5309 /* HW is reporting DMA is out of sync */
5310 adapter->stats.doosync++;
13800469
GR		 5311 /* The DMA Out of Sync is also indication of a spoof event
5312 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5313 * see if it is really a spoof event.
5314 */
13800469 5315 igb_check_wvbr(adapter);
dda0e083 5316 }
eebbbdba 5317
4ae196df
AD		 5318 /* Check for a mailbox event */
5319 if (icr & E1000_ICR_VMMB)
5320 igb_msg_task(adapter);
5321
5322 if (icr & E1000_ICR_LSC) {
5323 hw->mac.get_link_status = 1;
5324 /* guard against interrupt when we're going down */
5325 if (!test_bit(__IGB_DOWN, &adapter->state))
5326 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5327 }
5328
1f6e8178
MV		 5329 if (icr & E1000_ICR_TS) {
5330 u32 tsicr = rd32(E1000_TSICR);
5331
5332 if (tsicr & E1000_TSICR_TXTS) {
5333 /* acknowledge the interrupt */
5334 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5335 /* retrieve hardware timestamp */
5336 schedule_work(&adapter->ptp_tx_work);
5337 }
5338 }
1f6e8178 5339
844290e5 5340 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5341
5342 return IRQ_HANDLED;
5343}
5344
047e0030 5345static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5346{
26b39276 5347 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5348 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5349
047e0030
AD		 5350 if (!q_vector->set_itr)
5351 return;
73cd78f1 5352
047e0030
AD		 5353 if (!itr_val)
5354 itr_val = 0x4;
661086df 5355
26b39276
AD		 5356 if (adapter->hw.mac.type == e1000_82575)
5357 itr_val |= itr_val << 16;
661086df 5358 else
0ba82994 5359 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5360
047e0030
AD		 5361 writel(itr_val, q_vector->itr_register);
5362 q_vector->set_itr = 0;
6eb5a7f1
AD		 5363}
5364
047e0030 5365static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5366{
047e0030 5367 struct igb_q_vector *q_vector = data;
9d5c8243 5368
047e0030
AD		 5369 /* Write the ITR value calculated from the previous interrupt. */
5370 igb_write_itr(q_vector);
9d5c8243 5371
047e0030 5372 napi_schedule(&q_vector->napi);
844290e5 5373
047e0030 5374 return IRQ_HANDLED;
fe4506b6
JC		 5375}
5376
421e02f0 5377#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5378static void igb_update_tx_dca(struct igb_adapter *adapter,
5379 struct igb_ring *tx_ring,
5380 int cpu)
5381{
5382 struct e1000_hw *hw = &adapter->hw;
5383 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5384
5385 if (hw->mac.type != e1000_82575)
5386 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5387
b980ac18 5388 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5389 * DCA is enabled. This is due to a known issue in some chipsets
5390 * which will cause the DCA tag to be cleared.
5391 */
5392 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5393 E1000_DCA_TXCTRL_DATA_RRO_EN |
5394 E1000_DCA_TXCTRL_DESC_DCA_EN;
5395
5396 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5397}
5398
5399static void igb_update_rx_dca(struct igb_adapter *adapter,
5400 struct igb_ring *rx_ring,
5401 int cpu)
5402{
5403 struct e1000_hw *hw = &adapter->hw;
5404 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5405
5406 if (hw->mac.type != e1000_82575)
5407 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5408
b980ac18 5409 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5410 * DCA is enabled. This is due to a known issue in some chipsets
5411 * which will cause the DCA tag to be cleared.
5412 */
5413 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5414 E1000_DCA_RXCTRL_DESC_DCA_EN;
5415
5416 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5417}
5418
047e0030 5419static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5420{
047e0030 5421 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5422 int cpu = get_cpu();
fe4506b6 5423
047e0030
AD		 5424 if (q_vector->cpu == cpu)
5425 goto out_no_update;
5426
6a05004a
AD		 5427 if (q_vector->tx.ring)
5428 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5429
5430 if (q_vector->rx.ring)
5431 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5432
047e0030
AD		 5433 q_vector->cpu = cpu;
5434out_no_update:
fe4506b6
JC		 5435 put_cpu();
5436}
5437
5438static void igb_setup_dca(struct igb_adapter *adapter)
5439{
7e0e99ef 5440 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5441 int i;
5442
7dfc16fa 5443 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5444 return;
5445
7e0e99ef
AD		 5446 /* Always use CB2 mode, difference is masked in the CB driver. */
5447 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5448
047e0030 5449 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5450 adapter->q_vector[i]->cpu = -1;
5451 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5452 }
5453}
5454
5455static int __igb_notify_dca(struct device *dev, void *data)
5456{
5457 struct net_device *netdev = dev_get_drvdata(dev);
5458 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5459 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5460 struct e1000_hw *hw = &adapter->hw;
5461 unsigned long event = *(unsigned long *)data;
5462
5463 switch (event) {
5464 case DCA_PROVIDER_ADD:
5465 /* if already enabled, don't do it again */
7dfc16fa 5466 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5467 break;
fe4506b6 5468 if (dca_add_requester(dev) == 0) {
bbd98fe4 5469 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5470 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5471 igb_setup_dca(adapter);
5472 break;
5473 }
5474 /* Fall Through since DCA is disabled. */
5475 case DCA_PROVIDER_REMOVE:
7dfc16fa 5476 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5477 /* without this a class_device is left
b980ac18
JK		 5478 * hanging around in the sysfs model
5479 */
fe4506b6 5480 dca_remove_requester(dev);
090b1795 5481 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5482 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5483 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5484 }
5485 break;
5486 }
bbd98fe4 5487
fe4506b6 5488 return 0;
9d5c8243
AK		 5489}
5490
fe4506b6 5491static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5492 void *p)
fe4506b6
JC		 5493{
5494 int ret_val;
5495
5496 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5497 __igb_notify_dca);
fe4506b6
JC		 5498
5499 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5500}
421e02f0 5501#endif /* CONFIG_IGB_DCA */
9d5c8243 5502
0224d663
GR		 5503#ifdef CONFIG_PCI_IOV
5504static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5505{
5506 unsigned char mac_addr[ETH_ALEN];
0224d663 5507
5ac6f91d 5508 eth_zero_addr(mac_addr);
0224d663
GR		 5509 igb_set_vf_mac(adapter, vf, mac_addr);
5510
70ea4783
LL		 5511 /* By default spoof check is enabled for all VFs */
5512 adapter->vf_data[vf].spoofchk_enabled = true;
5513
f557147c 5514 return 0;
0224d663
GR		 5515}
5516
0224d663 5517#endif
4ae196df
AD		 5518static void igb_ping_all_vfs(struct igb_adapter *adapter)
5519{
5520 struct e1000_hw *hw = &adapter->hw;
5521 u32 ping;
5522 int i;
5523
5524 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5525 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5526 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5527 ping |= E1000_VT_MSGTYPE_CTS;
5528 igb_write_mbx(hw, &ping, 1, i);
5529 }
5530}
5531
7d5753f0
AD		 5532static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5533{
5534 struct e1000_hw *hw = &adapter->hw;
5535 u32 vmolr = rd32(E1000_VMOLR(vf));
5536 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5537
d85b9004 5538 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5539 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5540 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5541
5542 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5543 vmolr |= E1000_VMOLR_MPME;
d85b9004 5544 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5545 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5546 } else {
b980ac18 5547 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5548 * flag we need to write the hashes to the MTA as this step
5549 * was previously skipped
5550 */
5551 if (vf_data->num_vf_mc_hashes > 30) {
5552 vmolr |= E1000_VMOLR_MPME;
5553 } else if (vf_data->num_vf_mc_hashes) {
5554 int j;
5555 vmolr |= E1000_VMOLR_ROMPE;
5556 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5557 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5558 }
5559 }
5560
5561 wr32(E1000_VMOLR(vf), vmolr);
5562
5563 /* there are flags left unprocessed, likely not supported */
5564 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5565 return -EINVAL;
5566
5567 return 0;
7d5753f0
AD		 5568}
5569
4ae196df
AD		 5570static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5571 u32 *msgbuf, u32 vf)
5572{
5573 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5574 u16 *hash_list = (u16 *)&msgbuf[1];
5575 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5576 int i;
5577
7d5753f0 5578 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5579 * to this VF for later use to restore when the PF multi cast
5580 * list changes
5581 */
5582 vf_data->num_vf_mc_hashes = n;
5583
7d5753f0
AD		 5584 /* only up to 30 hash values supported */
5585 if (n > 30)
5586 n = 30;
5587
5588 /* store the hashes for later use */
4ae196df 5589 for (i = 0; i < n; i++)
a419aef8 5590 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5591
5592 /* Flush and reset the mta with the new values */
ff41f8dc 5593 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5594
5595 return 0;
5596}
5597
5598static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5599{
5600 struct e1000_hw *hw = &adapter->hw;
5601 struct vf_data_storage *vf_data;
5602 int i, j;
5603
5604 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5605 u32 vmolr = rd32(E1000_VMOLR(i));
5606 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5607
4ae196df 5608 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5609
5610 if ((vf_data->num_vf_mc_hashes > 30) ||
5611 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5612 vmolr |= E1000_VMOLR_MPME;
5613 } else if (vf_data->num_vf_mc_hashes) {
5614 vmolr |= E1000_VMOLR_ROMPE;
5615 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5616 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5617 }
5618 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5619 }
5620}
5621
5622static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5623{
5624 struct e1000_hw *hw = &adapter->hw;
5625 u32 pool_mask, reg, vid;
5626 int i;
5627
5628 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5629
5630 /* Find the vlan filter for this id */
5631 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5632 reg = rd32(E1000_VLVF(i));
5633
5634 /* remove the vf from the pool */
5635 reg &= ~pool_mask;
5636
5637 /* if pool is empty then remove entry from vfta */
5638 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5639 (reg & E1000_VLVF_VLANID_ENABLE)) {
5640 reg = 0;
5641 vid = reg & E1000_VLVF_VLANID_MASK;
5642 igb_vfta_set(hw, vid, false);
5643 }
5644
5645 wr32(E1000_VLVF(i), reg);
5646 }
ae641bdc
AD		 5647
5648 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5649}
5650
5651static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5652{
5653 struct e1000_hw *hw = &adapter->hw;
5654 u32 reg, i;
5655
51466239
AD		 5656 /* The vlvf table only exists on 82576 hardware and newer */
5657 if (hw->mac.type < e1000_82576)
5658 return -1;
5659
5660 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5661 if (!adapter->vfs_allocated_count)
5662 return -1;
5663
5664 /* Find the vlan filter for this id */
5665 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5666 reg = rd32(E1000_VLVF(i));
5667 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5668 vid == (reg & E1000_VLVF_VLANID_MASK))
5669 break;
5670 }
5671
5672 if (add) {
5673 if (i == E1000_VLVF_ARRAY_SIZE) {
5674 /* Did not find a matching VLAN ID entry that was
5675 * enabled. Search for a free filter entry, i.e.
5676 * one without the enable bit set
5677 */
5678 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5679 reg = rd32(E1000_VLVF(i));
5680 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5681 break;
5682 }
5683 }
5684 if (i < E1000_VLVF_ARRAY_SIZE) {
5685 /* Found an enabled/available entry */
5686 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5687
5688 /* if !enabled we need to set this up in vfta */
5689 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5690 /* add VID to filter table */
5691 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5692 reg |= E1000_VLVF_VLANID_ENABLE;
5693 }
cad6d05f
AD		 5694 reg &= ~E1000_VLVF_VLANID_MASK;
5695 reg |= vid;
4ae196df 5696 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5697
5698 /* do not modify RLPML for PF devices */
5699 if (vf >= adapter->vfs_allocated_count)
5700 return 0;
5701
5702 if (!adapter->vf_data[vf].vlans_enabled) {
5703 u32 size;
5704 reg = rd32(E1000_VMOLR(vf));
5705 size = reg & E1000_VMOLR_RLPML_MASK;
5706 size += 4;
5707 reg &= ~E1000_VMOLR_RLPML_MASK;
5708 reg |= size;
5709 wr32(E1000_VMOLR(vf), reg);
5710 }
ae641bdc 5711
51466239 5712 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5713 }
5714 } else {
5715 if (i < E1000_VLVF_ARRAY_SIZE) {
5716 /* remove vf from the pool */
5717 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5718 /* if pool is empty then remove entry from vfta */
5719 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5720 reg = 0;
5721 igb_vfta_set(hw, vid, false);
5722 }
5723 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5724
5725 /* do not modify RLPML for PF devices */
5726 if (vf >= adapter->vfs_allocated_count)
5727 return 0;
5728
5729 adapter->vf_data[vf].vlans_enabled--;
5730 if (!adapter->vf_data[vf].vlans_enabled) {
5731 u32 size;
5732 reg = rd32(E1000_VMOLR(vf));
5733 size = reg & E1000_VMOLR_RLPML_MASK;
5734 size -= 4;
5735 reg &= ~E1000_VMOLR_RLPML_MASK;
5736 reg |= size;
5737 wr32(E1000_VMOLR(vf), reg);
5738 }
4ae196df
AD		 5739 }
5740 }
8151d294
WM		 5741 return 0;
5742}
5743
5744static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5745{
5746 struct e1000_hw *hw = &adapter->hw;
5747
5748 if (vid)
5749 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5750 else
5751 wr32(E1000_VMVIR(vf), 0);
5752}
5753
5754static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5755 int vf, u16 vlan, u8 qos)
5756{
5757 int err = 0;
5758 struct igb_adapter *adapter = netdev_priv(netdev);
5759
5760 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5761 return -EINVAL;
5762 if (vlan || qos) {
5763 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5764 if (err)
5765 goto out;
5766 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5767 igb_set_vmolr(adapter, vf, !vlan);
5768 adapter->vf_data[vf].pf_vlan = vlan;
5769 adapter->vf_data[vf].pf_qos = qos;
5770 dev_info(&adapter->pdev->dev,
5771 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5772 if (test_bit(__IGB_DOWN, &adapter->state)) {
5773 dev_warn(&adapter->pdev->dev,
b980ac18 5774 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5775 dev_warn(&adapter->pdev->dev,
b980ac18 5776 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5777 }
5778 } else {
5779 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5780 false, vf);
8151d294
WM		 5781 igb_set_vmvir(adapter, vlan, vf);
5782 igb_set_vmolr(adapter, vf, true);
5783 adapter->vf_data[vf].pf_vlan = 0;
5784 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5785 }
8151d294 5786out:
b980ac18 5787 return err;
4ae196df
AD		 5788}
5789
6f3dc319
GR		 5790static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5791{
5792 struct e1000_hw *hw = &adapter->hw;
5793 int i;
5794 u32 reg;
5795
5796 /* Find the vlan filter for this id */
5797 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5798 reg = rd32(E1000_VLVF(i));
5799 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5800 vid == (reg & E1000_VLVF_VLANID_MASK))
5801 break;
5802 }
5803
5804 if (i >= E1000_VLVF_ARRAY_SIZE)
5805 i = -1;
5806
5807 return i;
5808}
5809
4ae196df
AD		 5810static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5811{
6f3dc319 5812 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5813 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5814 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5815 int err = 0;
4ae196df 5816
6f3dc319
GR		 5817 /* If in promiscuous mode we need to make sure the PF also has
5818 * the VLAN filter set.
5819 */
5820 if (add && (adapter->netdev->flags & IFF_PROMISC))
5821 err = igb_vlvf_set(adapter, vid, add,
5822 adapter->vfs_allocated_count);
5823 if (err)
5824 goto out;
5825
5826 err = igb_vlvf_set(adapter, vid, add, vf);
5827
5828 if (err)
5829 goto out;
5830
5831 /* Go through all the checks to see if the VLAN filter should
5832 * be wiped completely.
5833 */
5834 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5835 u32 vlvf, bits;
5836
5837 int regndx = igb_find_vlvf_entry(adapter, vid);
5838 if (regndx < 0)
5839 goto out;
5840 /* See if any other pools are set for this VLAN filter
5841 * entry other than the PF.
5842 */
5843 vlvf = bits = rd32(E1000_VLVF(regndx));
5844 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5845 adapter->vfs_allocated_count);
5846 /* If the filter was removed then ensure PF pool bit
5847 * is cleared if the PF only added itself to the pool
5848 * because the PF is in promiscuous mode.
5849 */
5850 if ((vlvf & VLAN_VID_MASK) == vid &&
5851 !test_bit(vid, adapter->active_vlans) &&
5852 !bits)
5853 igb_vlvf_set(adapter, vid, add,
5854 adapter->vfs_allocated_count);
5855 }
5856
5857out:
5858 return err;
4ae196df
AD		 5859}
5860
f2ca0dbe 5861static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5862{
8fa7e0f7
GR		 5863 /* clear flags - except flag that indicates PF has set the MAC */
5864 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5865 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5866
5867 /* reset offloads to defaults */
8151d294 5868 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5869
5870 /* reset vlans for device */
5871 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5872 if (adapter->vf_data[vf].pf_vlan)
5873 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5874 adapter->vf_data[vf].pf_vlan,
5875 adapter->vf_data[vf].pf_qos);
5876 else
5877 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5878
5879 /* reset multicast table array for vf */
5880 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5881
5882 /* Flush and reset the mta with the new values */
ff41f8dc 5883 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5884}
5885
f2ca0dbe
AD		 5886static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5887{
5888 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5889
5ac6f91d 5890 /* clear mac address as we were hotplug removed/added */
8151d294 5891 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5892 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5893
5894 /* process remaining reset events */
5895 igb_vf_reset(adapter, vf);
5896}
5897
5898static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5899{
5900 struct e1000_hw *hw = &adapter->hw;
5901 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5902 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5903 u32 reg, msgbuf[3];
5904 u8 *addr = (u8 *)(&msgbuf[1]);
5905
5906 /* process all the same items cleared in a function level reset */
f2ca0dbe 5907 igb_vf_reset(adapter, vf);
4ae196df
AD		 5908
5909 /* set vf mac address */
26ad9178 5910 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5911
5912 /* enable transmit and receive for vf */
5913 reg = rd32(E1000_VFTE);
5914 wr32(E1000_VFTE, reg | (1 << vf));
5915 reg = rd32(E1000_VFRE);
5916 wr32(E1000_VFRE, reg | (1 << vf));
5917
8fa7e0f7 5918 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5919
5920 /* reply to reset with ack and vf mac address */
5921 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5922 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5923 igb_write_mbx(hw, msgbuf, 3, vf);
5924}
5925
5926static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5927{
b980ac18 5928 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5929 * starting at the second 32 bit word of the msg array
5930 */
f2ca0dbe
AD		 5931 unsigned char *addr = (char *)&msg[1];
5932 int err = -1;
4ae196df 5933
f2ca0dbe
AD		 5934 if (is_valid_ether_addr(addr))
5935 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5936
f2ca0dbe 5937 return err;
4ae196df
AD		 5938}
5939
5940static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5941{
5942 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5943 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5944 u32 msg = E1000_VT_MSGTYPE_NACK;
5945
5946 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5947 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5948 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5949 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5950 vf_data->last_nack = jiffies;
4ae196df
AD		 5951 }
5952}
5953
f2ca0dbe 5954static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5955{
f2ca0dbe
AD		 5956 struct pci_dev *pdev = adapter->pdev;
5957 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5958 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5959 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5960 s32 retval;
5961
f2ca0dbe 5962 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5963
fef45f4c
AD		 5964 if (retval) {
5965 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5966 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5967 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5968 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5969 return;
5970 goto out;
5971 }
4ae196df
AD		 5972
5973 /* this is a message we already processed, do nothing */
5974 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5975 return;
4ae196df 5976
b980ac18 5977 /* until the vf completes a reset it should not be
4ae196df
AD		 5978 * allowed to start any configuration.
5979 */
4ae196df
AD		 5980 if (msgbuf[0] == E1000_VF_RESET) {
5981 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5982 return;
4ae196df
AD		 5983 }
5984
f2ca0dbe 5985 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5986 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5987 return;
5988 retval = -1;
5989 goto out;
4ae196df
AD		 5990 }
5991
5992 switch ((msgbuf[0] & 0xFFFF)) {
5993 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5994 retval = -EINVAL;
5995 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5996 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5997 else
5998 dev_warn(&pdev->dev,
b980ac18
JK		 5999 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6000 vf);
4ae196df 6001 break;
7d5753f0
AD		 6002 case E1000_VF_SET_PROMISC:
6003 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6004 break;
4ae196df
AD		 6005 case E1000_VF_SET_MULTICAST:
6006 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6007 break;
6008 case E1000_VF_SET_LPE:
6009 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6010 break;
6011 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6012 retval = -1;
6013 if (vf_data->pf_vlan)
6014 dev_warn(&pdev->dev,
b980ac18
JK		 6015 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6016 vf);
8151d294
WM		 6017 else
6018 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6019 break;
6020 default:
090b1795 6021 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6022 retval = -1;
6023 break;
6024 }
6025
fef45f4c
AD		 6026 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6027out:
4ae196df
AD		 6028 /* notify the VF of the results of what it sent us */
6029 if (retval)
6030 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6031 else
6032 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6033
4ae196df 6034 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6035}
4ae196df 6036
f2ca0dbe
AD		 6037static void igb_msg_task(struct igb_adapter *adapter)
6038{
6039 struct e1000_hw *hw = &adapter->hw;
6040 u32 vf;
6041
6042 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6043 /* process any reset requests */
6044 if (!igb_check_for_rst(hw, vf))
6045 igb_vf_reset_event(adapter, vf);
6046
6047 /* process any messages pending */
6048 if (!igb_check_for_msg(hw, vf))
6049 igb_rcv_msg_from_vf(adapter, vf);
6050
6051 /* process any acks */
6052 if (!igb_check_for_ack(hw, vf))
6053 igb_rcv_ack_from_vf(adapter, vf);
6054 }
4ae196df
AD		 6055}
6056
68d480c4
AD		 6057/**
6058 * igb_set_uta - Set unicast filter table address
6059 * @adapter: board private structure
6060 *
6061 * The unicast table address is a register array of 32-bit registers.
6062 * The table is meant to be used in a way similar to how the MTA is used
6063 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6064 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6065 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6066 **/
6067static void igb_set_uta(struct igb_adapter *adapter)
6068{
6069 struct e1000_hw *hw = &adapter->hw;
6070 int i;
6071
6072 /* The UTA table only exists on 82576 hardware and newer */
6073 if (hw->mac.type < e1000_82576)
6074 return;
6075
6076 /* we only need to do this if VMDq is enabled */
6077 if (!adapter->vfs_allocated_count)
6078 return;
6079
6080 for (i = 0; i < hw->mac.uta_reg_count; i++)
6081 array_wr32(E1000_UTA, i, ~0);
6082}
6083
9d5c8243 6084/**
b980ac18
JK		 6085 * igb_intr_msi - Interrupt Handler
6086 * @irq: interrupt number
6087 * @data: pointer to a network interface device structure
9d5c8243
AK		 6088 **/
6089static irqreturn_t igb_intr_msi(int irq, void *data)
6090{
047e0030
AD		 6091 struct igb_adapter *adapter = data;
6092 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6093 struct e1000_hw *hw = &adapter->hw;
6094 /* read ICR disables interrupts using IAM */
6095 u32 icr = rd32(E1000_ICR);
6096
047e0030 6097 igb_write_itr(q_vector);
9d5c8243 6098
7f081d40
AD		 6099 if (icr & E1000_ICR_DRSTA)
6100 schedule_work(&adapter->reset_task);
6101
047e0030 6102 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6103 /* HW is reporting DMA is out of sync */
6104 adapter->stats.doosync++;
6105 }
6106
9d5c8243
AK		 6107 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6108 hw->mac.get_link_status = 1;
6109 if (!test_bit(__IGB_DOWN, &adapter->state))
6110 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6111 }
6112
1f6e8178
MV		 6113 if (icr & E1000_ICR_TS) {
6114 u32 tsicr = rd32(E1000_TSICR);
6115
6116 if (tsicr & E1000_TSICR_TXTS) {
6117 /* acknowledge the interrupt */
6118 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6119 /* retrieve hardware timestamp */
6120 schedule_work(&adapter->ptp_tx_work);
6121 }
6122 }
1f6e8178 6123
047e0030 6124 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6125
6126 return IRQ_HANDLED;
6127}
6128
6129/**
b980ac18
JK		 6130 * igb_intr - Legacy Interrupt Handler
6131 * @irq: interrupt number
6132 * @data: pointer to a network interface device structure
9d5c8243
AK		 6133 **/
6134static irqreturn_t igb_intr(int irq, void *data)
6135{
047e0030
AD		 6136 struct igb_adapter *adapter = data;
6137 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6138 struct e1000_hw *hw = &adapter->hw;
6139 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6140 * need for the IMC write
6141 */
9d5c8243 6142 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6143
6144 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6145 * not set, then the adapter didn't send an interrupt
6146 */
9d5c8243
AK		 6147 if (!(icr & E1000_ICR_INT_ASSERTED))
6148 return IRQ_NONE;
6149
0ba82994
AD		 6150 igb_write_itr(q_vector);
6151
7f081d40
AD		 6152 if (icr & E1000_ICR_DRSTA)
6153 schedule_work(&adapter->reset_task);
6154
047e0030 6155 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6156 /* HW is reporting DMA is out of sync */
6157 adapter->stats.doosync++;
6158 }
6159
9d5c8243
AK		 6160 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6161 hw->mac.get_link_status = 1;
6162 /* guard against interrupt when we're going down */
6163 if (!test_bit(__IGB_DOWN, &adapter->state))
6164 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6165 }
6166
1f6e8178
MV		 6167 if (icr & E1000_ICR_TS) {
6168 u32 tsicr = rd32(E1000_TSICR);
6169
6170 if (tsicr & E1000_TSICR_TXTS) {
6171 /* acknowledge the interrupt */
6172 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6173 /* retrieve hardware timestamp */
6174 schedule_work(&adapter->ptp_tx_work);
6175 }
6176 }
1f6e8178 6177
047e0030 6178 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6179
6180 return IRQ_HANDLED;
6181}
6182
c50b52a0 6183static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6184{
047e0030 6185 struct igb_adapter *adapter = q_vector->adapter;
46544258 6186 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6187
0ba82994
AD		 6188 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6189 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6190 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6191 igb_set_itr(q_vector);
46544258 6192 else
047e0030 6193 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6194 }
6195
46544258
AD		 6196 if (!test_bit(__IGB_DOWN, &adapter->state)) {
6197 if (adapter->msix_entries)
047e0030 6198 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6199 else
6200 igb_irq_enable(adapter);
6201 }
9d5c8243
AK		 6202}
6203
46544258 6204/**
b980ac18
JK		 6205 * igb_poll - NAPI Rx polling callback
6206 * @napi: napi polling structure
6207 * @budget: count of how many packets we should handle
46544258
AD		 6208 **/
6209static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6210{
047e0030 6211 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6212 struct igb_q_vector,
6213 napi);
16eb8815 6214 bool clean_complete = true;
9d5c8243 6215
421e02f0 6216#ifdef CONFIG_IGB_DCA
047e0030
AD		 6217 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6218 igb_update_dca(q_vector);
fe4506b6 6219#endif
0ba82994 6220 if (q_vector->tx.ring)
13fde97a 6221 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6222
0ba82994 6223 if (q_vector->rx.ring)
cd392f5c 6224 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6225
16eb8815
AD		 6226 /* If all work not completed, return budget and keep polling */
6227 if (!clean_complete)
6228 return budget;
46544258 6229
9d5c8243 6230 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6231 napi_complete(napi);
6232 igb_ring_irq_enable(q_vector);
9d5c8243 6233
16eb8815 6234 return 0;
9d5c8243 6235}
6d8126f9 6236
9d5c8243 6237/**
b980ac18
JK		 6238 * igb_clean_tx_irq - Reclaim resources after transmit completes
6239 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6240 *
b980ac18 6241 * returns true if ring is completely cleaned
9d5c8243 6242 **/
047e0030 6243static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6244{
047e0030 6245 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6246 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6247 struct igb_tx_buffer *tx_buffer;
f4128785 6248 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6249 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6250 unsigned int budget = q_vector->tx.work_limit;
8542db05 6251 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6252
13fde97a
AD		 6253 if (test_bit(__IGB_DOWN, &adapter->state))
6254 return true;
0e014cb1 6255
06034649 6256 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6257 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6258 i -= tx_ring->count;
9d5c8243 6259
f4128785
AD		 6260 do {
6261 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6262
6263 /* if next_to_watch is not set then there is no work pending */
6264 if (!eop_desc)
6265 break;
13fde97a 6266
f4128785 6267 /* prevent any other reads prior to eop_desc */
70d289bc 6268 read_barrier_depends();
f4128785 6269
13fde97a
AD		 6270 /* if DD is not set pending work has not been completed */
6271 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6272 break;
6273
8542db05
AD		 6274 /* clear next_to_watch to prevent false hangs */
6275 tx_buffer->next_to_watch = NULL;
9d5c8243 6276
ebe42d16
AD		 6277 /* update the statistics for this packet */
6278 total_bytes += tx_buffer->bytecount;
6279 total_packets += tx_buffer->gso_segs;
13fde97a 6280
ebe42d16
AD		 6281 /* free the skb */
6282 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6283
ebe42d16
AD		 6284 /* unmap skb header data */
6285 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6286 dma_unmap_addr(tx_buffer, dma),
6287 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6288 DMA_TO_DEVICE);
6289
c9f14bf3
AD		 6290 /* clear tx_buffer data */
6291 tx_buffer->skb = NULL;
6292 dma_unmap_len_set(tx_buffer, len, 0);
6293
ebe42d16
AD		 6294 /* clear last DMA location and unmap remaining buffers */
6295 while (tx_desc != eop_desc) {
13fde97a
AD		 6296 tx_buffer++;
6297 tx_desc++;
9d5c8243 6298 i++;
8542db05
AD		 6299 if (unlikely(!i)) {
6300 i -= tx_ring->count;
06034649 6301 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6302 tx_desc = IGB_TX_DESC(tx_ring, 0);
6303 }
ebe42d16
AD		 6304
6305 /* unmap any remaining paged data */
c9f14bf3 6306 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6307 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6308 dma_unmap_addr(tx_buffer, dma),
6309 dma_unmap_len(tx_buffer, len),
ebe42d16 6310 DMA_TO_DEVICE);
c9f14bf3 6311 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6312 }
6313 }
6314
ebe42d16
AD		 6315 /* move us one more past the eop_desc for start of next pkt */
6316 tx_buffer++;
6317 tx_desc++;
6318 i++;
6319 if (unlikely(!i)) {
6320 i -= tx_ring->count;
6321 tx_buffer = tx_ring->tx_buffer_info;
6322 tx_desc = IGB_TX_DESC(tx_ring, 0);
6323 }
f4128785
AD		 6324
6325 /* issue prefetch for next Tx descriptor */
6326 prefetch(tx_desc);
6327
6328 /* update budget accounting */
6329 budget--;
6330 } while (likely(budget));
0e014cb1 6331
bdbc0631
ED		 6332 netdev_tx_completed_queue(txring_txq(tx_ring),
6333 total_packets, total_bytes);
8542db05 6334 i += tx_ring->count;
9d5c8243 6335 tx_ring->next_to_clean = i;
13fde97a
AD		 6336 u64_stats_update_begin(&tx_ring->tx_syncp);
6337 tx_ring->tx_stats.bytes += total_bytes;
6338 tx_ring->tx_stats.packets += total_packets;
6339 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6340 q_vector->tx.total_bytes += total_bytes;
6341 q_vector->tx.total_packets += total_packets;
9d5c8243 6342
6d095fa8 6343 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6344 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6345
9d5c8243 6346 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6347 * check with the clearing of time_stamp and movement of i
6348 */
6d095fa8 6349 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6350 if (tx_buffer->next_to_watch &&
8542db05 6351 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6352 (adapter->tx_timeout_factor * HZ)) &&
6353 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6354
9d5c8243 6355 /* detected Tx unit hang */
59d71989 6356 dev_err(tx_ring->dev,
9d5c8243 6357 "Detected Tx Unit Hang\n"
2d064c06 6358 " Tx Queue <%d>\n"
9d5c8243
AK		 6359 " TDH <%x>\n"
6360 " TDT <%x>\n"
6361 " next_to_use <%x>\n"
6362 " next_to_clean <%x>\n"
9d5c8243
AK		 6363 "buffer_info[next_to_clean]\n"
6364 " time_stamp <%lx>\n"
8542db05 6365 " next_to_watch <%p>\n"
9d5c8243
AK		 6366 " jiffies <%lx>\n"
6367 " desc.status <%x>\n",
2d064c06 6368 tx_ring->queue_index,
238ac817 6369 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6370 readl(tx_ring->tail),
9d5c8243
AK		 6371 tx_ring->next_to_use,
6372 tx_ring->next_to_clean,
8542db05 6373 tx_buffer->time_stamp,
f4128785 6374 tx_buffer->next_to_watch,
9d5c8243 6375 jiffies,
f4128785 6376 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6377 netif_stop_subqueue(tx_ring->netdev,
6378 tx_ring->queue_index);
6379
6380 /* we are about to reset, no point in enabling stuff */
6381 return true;
9d5c8243
AK		 6382 }
6383 }
13fde97a 6384
21ba6fe1 6385#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6386 if (unlikely(total_packets &&
b980ac18
JK		 6387 netif_carrier_ok(tx_ring->netdev) &&
6388 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6389 /* Make sure that anybody stopping the queue after this
6390 * sees the new next_to_clean.
6391 */
6392 smp_mb();
6393 if (__netif_subqueue_stopped(tx_ring->netdev,
6394 tx_ring->queue_index) &&
6395 !(test_bit(__IGB_DOWN, &adapter->state))) {
6396 netif_wake_subqueue(tx_ring->netdev,
6397 tx_ring->queue_index);
6398
6399 u64_stats_update_begin(&tx_ring->tx_syncp);
6400 tx_ring->tx_stats.restart_queue++;
6401 u64_stats_update_end(&tx_ring->tx_syncp);
6402 }
6403 }
6404
6405 return !!budget;
9d5c8243
AK		 6406}
6407
cbc8e55f 6408/**
b980ac18
JK		 6409 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6410 * @rx_ring: rx descriptor ring to store buffers on
6411 * @old_buff: donor buffer to have page reused
cbc8e55f 6412 *
b980ac18 6413 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6414 **/
6415static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6416 struct igb_rx_buffer *old_buff)
6417{
6418 struct igb_rx_buffer *new_buff;
6419 u16 nta = rx_ring->next_to_alloc;
6420
6421 new_buff = &rx_ring->rx_buffer_info[nta];
6422
6423 /* update, and store next to alloc */
6424 nta++;
6425 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6426
6427 /* transfer page from old buffer to new buffer */
6428 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6429
6430 /* sync the buffer for use by the device */
6431 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6432 old_buff->page_offset,
de78d1f9 6433 IGB_RX_BUFSZ,
cbc8e55f
AD		 6434 DMA_FROM_DEVICE);
6435}
6436
74e238ea
AD		 6437static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6438 struct page *page,
6439 unsigned int truesize)
6440{
6441 /* avoid re-using remote pages */
6442 if (unlikely(page_to_nid(page) != numa_node_id()))
6443 return false;
6444
6445#if (PAGE_SIZE < 8192)
6446 /* if we are only owner of page we can reuse it */
6447 if (unlikely(page_count(page) != 1))
6448 return false;
6449
6450 /* flip page offset to other buffer */
6451 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6452
6453 /* since we are the only owner of the page and we need to
6454 * increment it, just set the value to 2 in order to avoid
6455 * an unnecessary locked operation
6456 */
6457 atomic_set(&page->_count, 2);
6458#else
6459 /* move offset up to the next cache line */
6460 rx_buffer->page_offset += truesize;
6461
6462 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6463 return false;
6464
6465 /* bump ref count on page before it is given to the stack */
6466 get_page(page);
6467#endif
6468
6469 return true;
6470}
6471
cbc8e55f 6472/**
b980ac18
JK		 6473 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6474 * @rx_ring: rx descriptor ring to transact packets on
6475 * @rx_buffer: buffer containing page to add
6476 * @rx_desc: descriptor containing length of buffer written by hardware
6477 * @skb: sk_buff to place the data into
cbc8e55f 6478 *
b980ac18
JK		 6479 * This function will add the data contained in rx_buffer->page to the skb.
6480 * This is done either through a direct copy if the data in the buffer is
6481 * less than the skb header size, otherwise it will just attach the page as
6482 * a frag to the skb.
cbc8e55f 6483 *
b980ac18
JK		 6484 * The function will then update the page offset if necessary and return
6485 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6486 **/
6487static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6488 struct igb_rx_buffer *rx_buffer,
6489 union e1000_adv_rx_desc *rx_desc,
6490 struct sk_buff *skb)
6491{
6492 struct page *page = rx_buffer->page;
6493 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6494#if (PAGE_SIZE < 8192)
6495 unsigned int truesize = IGB_RX_BUFSZ;
6496#else
6497 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6498#endif
cbc8e55f
AD		 6499
6500 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6501 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6502
cbc8e55f
AD		 6503 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6504 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6505 va += IGB_TS_HDR_LEN;
6506 size -= IGB_TS_HDR_LEN;
6507 }
6508
cbc8e55f
AD		 6509 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6510
6511 /* we can reuse buffer as-is, just make sure it is local */
6512 if (likely(page_to_nid(page) == numa_node_id()))
6513 return true;
6514
6515 /* this page cannot be reused so discard it */
6516 put_page(page);
6517 return false;
6518 }
6519
6520 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6521 rx_buffer->page_offset, size, truesize);
cbc8e55f 6522
74e238ea
AD		 6523 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6524}
cbc8e55f 6525
2e334eee
AD		 6526static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6527 union e1000_adv_rx_desc *rx_desc,
6528 struct sk_buff *skb)
6529{
6530 struct igb_rx_buffer *rx_buffer;
6531 struct page *page;
6532
6533 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6534
2e334eee
AD		 6535 page = rx_buffer->page;
6536 prefetchw(page);
6537
6538 if (likely(!skb)) {
6539 void *page_addr = page_address(page) +
6540 rx_buffer->page_offset;
6541
6542 /* prefetch first cache line of first page */
6543 prefetch(page_addr);
6544#if L1_CACHE_BYTES < 128
6545 prefetch(page_addr + L1_CACHE_BYTES);
6546#endif
6547
6548 /* allocate a skb to store the frags */
6549 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6550 IGB_RX_HDR_LEN);
6551 if (unlikely(!skb)) {
6552 rx_ring->rx_stats.alloc_failed++;
6553 return NULL;
6554 }
6555
b980ac18 6556 /* we will be copying header into skb->data in
2e334eee
AD		 6557 * pskb_may_pull so it is in our interest to prefetch
6558 * it now to avoid a possible cache miss
6559 */
6560 prefetchw(skb->data);
6561 }
6562
6563 /* we are reusing so sync this buffer for CPU use */
6564 dma_sync_single_range_for_cpu(rx_ring->dev,
6565 rx_buffer->dma,
6566 rx_buffer->page_offset,
de78d1f9 6567 IGB_RX_BUFSZ,
2e334eee
AD		 6568 DMA_FROM_DEVICE);
6569
6570 /* pull page into skb */
6571 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6572 /* hand second half of page back to the ring */
6573 igb_reuse_rx_page(rx_ring, rx_buffer);
6574 } else {
6575 /* we are not reusing the buffer so unmap it */
6576 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6577 PAGE_SIZE, DMA_FROM_DEVICE);
6578 }
6579
6580 /* clear contents of rx_buffer */
6581 rx_buffer->page = NULL;
6582
6583 return skb;
6584}
6585
cd392f5c 6586static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6587 union e1000_adv_rx_desc *rx_desc,
6588 struct sk_buff *skb)
9d5c8243 6589{
bc8acf2c 6590 skb_checksum_none_assert(skb);
9d5c8243 6591
294e7d78 6592 /* Ignore Checksum bit is set */
3ceb90fd 6593 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6594 return;
6595
6596 /* Rx checksum disabled via ethtool */
6597 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6598 return;
85ad76b2 6599
9d5c8243 6600 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6601 if (igb_test_staterr(rx_desc,
6602 E1000_RXDEXT_STATERR_TCPE |
6603 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6604 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6605 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6606 * packets, (aka let the stack check the crc32c)
6607 */
866cff06
AD		 6608 if (!((skb->len == 60) &&
6609 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6610 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6611 ring->rx_stats.csum_err++;
12dcd86b
ED		 6612 u64_stats_update_end(&ring->rx_syncp);
6613 }
9d5c8243 6614 /* let the stack verify checksum errors */
9d5c8243
AK		 6615 return;
6616 }
6617 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6618 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6619 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6620 skb->ip_summed = CHECKSUM_UNNECESSARY;
6621
3ceb90fd
AD		 6622 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6623 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6624}
6625
077887c3
AD		 6626static inline void igb_rx_hash(struct igb_ring *ring,
6627 union e1000_adv_rx_desc *rx_desc,
6628 struct sk_buff *skb)
6629{
6630 if (ring->netdev->features & NETIF_F_RXHASH)
6631 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6632}
6633
2e334eee 6634/**
b980ac18
JK		 6635 * igb_is_non_eop - process handling of non-EOP buffers
6636 * @rx_ring: Rx ring being processed
6637 * @rx_desc: Rx descriptor for current buffer
6638 * @skb: current socket buffer containing buffer in progress
2e334eee 6639 *
b980ac18
JK		 6640 * This function updates next to clean. If the buffer is an EOP buffer
6641 * this function exits returning false, otherwise it will place the
6642 * sk_buff in the next buffer to be chained and return true indicating
6643 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6644 **/
6645static bool igb_is_non_eop(struct igb_ring *rx_ring,
6646 union e1000_adv_rx_desc *rx_desc)
6647{
6648 u32 ntc = rx_ring->next_to_clean + 1;
6649
6650 /* fetch, update, and store next to clean */
6651 ntc = (ntc < rx_ring->count) ? ntc : 0;
6652 rx_ring->next_to_clean = ntc;
6653
6654 prefetch(IGB_RX_DESC(rx_ring, ntc));
6655
6656 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6657 return false;
6658
6659 return true;
6660}
6661
1a1c225b 6662/**
b980ac18
JK		 6663 * igb_get_headlen - determine size of header for LRO/GRO
6664 * @data: pointer to the start of the headers
6665 * @max_len: total length of section to find headers in
1a1c225b 6666 *
b980ac18
JK		 6667 * This function is meant to determine the length of headers that will
6668 * be recognized by hardware for LRO, and GRO offloads. The main
6669 * motivation of doing this is to only perform one pull for IPv4 TCP
6670 * packets so that we can do basic things like calculating the gso_size
6671 * based on the average data per packet.
1a1c225b
AD		 6672 **/
6673static unsigned int igb_get_headlen(unsigned char *data,
6674 unsigned int max_len)
6675{
6676 union {
6677 unsigned char *network;
6678 /* l2 headers */
6679 struct ethhdr *eth;
6680 struct vlan_hdr *vlan;
6681 /* l3 headers */
6682 struct iphdr *ipv4;
6683 struct ipv6hdr *ipv6;
6684 } hdr;
6685 __be16 protocol;
6686 u8 nexthdr = 0; /* default to not TCP */
6687 u8 hlen;
6688
6689 /* this should never happen, but better safe than sorry */
6690 if (max_len < ETH_HLEN)
6691 return max_len;
6692
6693 /* initialize network frame pointer */
6694 hdr.network = data;
6695
6696 /* set first protocol and move network header forward */
6697 protocol = hdr.eth->h_proto;
6698 hdr.network += ETH_HLEN;
6699
6700 /* handle any vlan tag if present */
6701 if (protocol == __constant_htons(ETH_P_8021Q)) {
6702 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6703 return max_len;
6704
6705 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6706 hdr.network += VLAN_HLEN;
6707 }
6708
6709 /* handle L3 protocols */
6710 if (protocol == __constant_htons(ETH_P_IP)) {
6711 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6712 return max_len;
6713
6714 /* access ihl as a u8 to avoid unaligned access on ia64 */
6715 hlen = (hdr.network[0] & 0x0F) << 2;
6716
6717 /* verify hlen meets minimum size requirements */
6718 if (hlen < sizeof(struct iphdr))
6719 return hdr.network - data;
6720
f2fb4ab2 6721 /* record next protocol if header is present */
b9555f66 6722 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6723 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6724 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6725 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6726 return max_len;
6727
6728 /* record next protocol */
6729 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6730 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6731 } else {
6732 return hdr.network - data;
6733 }
6734
f2fb4ab2
AD		 6735 /* relocate pointer to start of L4 header */
6736 hdr.network += hlen;
6737
1a1c225b
AD		 6738 /* finally sort out TCP */
6739 if (nexthdr == IPPROTO_TCP) {
6740 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6741 return max_len;
6742
6743 /* access doff as a u8 to avoid unaligned access on ia64 */
6744 hlen = (hdr.network[12] & 0xF0) >> 2;
6745
6746 /* verify hlen meets minimum size requirements */
6747 if (hlen < sizeof(struct tcphdr))
6748 return hdr.network - data;
6749
6750 hdr.network += hlen;
6751 } else if (nexthdr == IPPROTO_UDP) {
6752 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6753 return max_len;
6754
6755 hdr.network += sizeof(struct udphdr);
6756 }
6757
b980ac18 6758 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6759 * data section of the packet and will be the end of the header.
6760 * If not then it probably represents the end of the last recognized
6761 * header.
6762 */
6763 if ((hdr.network - data) < max_len)
6764 return hdr.network - data;
6765 else
6766 return max_len;
6767}
6768
6769/**
b980ac18
JK		 6770 * igb_pull_tail - igb specific version of skb_pull_tail
6771 * @rx_ring: rx descriptor ring packet is being transacted on
6772 * @rx_desc: pointer to the EOP Rx descriptor
6773 * @skb: pointer to current skb being adjusted
1a1c225b 6774 *
b980ac18
JK		 6775 * This function is an igb specific version of __pskb_pull_tail. The
6776 * main difference between this version and the original function is that
6777 * this function can make several assumptions about the state of things
6778 * that allow for significant optimizations versus the standard function.
6779 * As a result we can do things like drop a frag and maintain an accurate
6780 * truesize for the skb.
1a1c225b
AD		 6781 */
6782static void igb_pull_tail(struct igb_ring *rx_ring,
6783 union e1000_adv_rx_desc *rx_desc,
6784 struct sk_buff *skb)
2d94d8ab 6785{
1a1c225b
AD		 6786 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6787 unsigned char *va;
6788 unsigned int pull_len;
6789
b980ac18 6790 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6791 * working with pages allocated out of the lomem pool per
6792 * alloc_page(GFP_ATOMIC)
2d94d8ab 6793 */
1a1c225b
AD		 6794 va = skb_frag_address(frag);
6795
1a1c225b
AD		 6796 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6797 /* retrieve timestamp from buffer */
6798 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6799
6800 /* update pointers to remove timestamp header */
6801 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6802 frag->page_offset += IGB_TS_HDR_LEN;
6803 skb->data_len -= IGB_TS_HDR_LEN;
6804 skb->len -= IGB_TS_HDR_LEN;
6805
6806 /* move va to start of packet data */
6807 va += IGB_TS_HDR_LEN;
6808 }
6809
b980ac18 6810 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6811 * 60 bytes if the skb->len is less than 60 for skb_pad.
6812 */
6813 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6814
6815 /* align pull length to size of long to optimize memcpy performance */
6816 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6817
6818 /* update all of the pointers */
6819 skb_frag_size_sub(frag, pull_len);
6820 frag->page_offset += pull_len;
6821 skb->data_len -= pull_len;
6822 skb->tail += pull_len;
6823}
6824
6825/**
b980ac18
JK		 6826 * igb_cleanup_headers - Correct corrupted or empty headers
6827 * @rx_ring: rx descriptor ring packet is being transacted on
6828 * @rx_desc: pointer to the EOP Rx descriptor
6829 * @skb: pointer to current skb being fixed
1a1c225b 6830 *
b980ac18
JK		 6831 * Address the case where we are pulling data in on pages only
6832 * and as such no data is present in the skb header.
1a1c225b 6833 *
b980ac18
JK		 6834 * In addition if skb is not at least 60 bytes we need to pad it so that
6835 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6836 *
b980ac18 6837 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6838 **/
6839static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6840 union e1000_adv_rx_desc *rx_desc,
6841 struct sk_buff *skb)
6842{
1a1c225b
AD		 6843 if (unlikely((igb_test_staterr(rx_desc,
6844 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6845 struct net_device *netdev = rx_ring->netdev;
6846 if (!(netdev->features & NETIF_F_RXALL)) {
6847 dev_kfree_skb_any(skb);
6848 return true;
6849 }
6850 }
6851
6852 /* place header in linear portion of buffer */
6853 if (skb_is_nonlinear(skb))
6854 igb_pull_tail(rx_ring, rx_desc, skb);
6855
6856 /* if skb_pad returns an error the skb was freed */
6857 if (unlikely(skb->len < 60)) {
6858 int pad_len = 60 - skb->len;
6859
6860 if (skb_pad(skb, pad_len))
6861 return true;
6862 __skb_put(skb, pad_len);
6863 }
6864
6865 return false;
2d94d8ab
AD		 6866}
6867
db2ee5bd 6868/**
b980ac18
JK		 6869 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6870 * @rx_ring: rx descriptor ring packet is being transacted on
6871 * @rx_desc: pointer to the EOP Rx descriptor
6872 * @skb: pointer to current skb being populated
db2ee5bd 6873 *
b980ac18
JK		 6874 * This function checks the ring, descriptor, and packet information in
6875 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6876 * other fields within the skb.
db2ee5bd
AD		 6877 **/
6878static void igb_process_skb_fields(struct igb_ring *rx_ring,
6879 union e1000_adv_rx_desc *rx_desc,
6880 struct sk_buff *skb)
6881{
6882 struct net_device *dev = rx_ring->netdev;
6883
6884 igb_rx_hash(rx_ring, rx_desc, skb);
6885
6886 igb_rx_checksum(rx_ring, rx_desc, skb);
6887
20a48412 6888 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6889
f646968f 6890 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6891 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6892 u16 vid;
6893 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6894 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6895 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6896 else
6897 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6898
86a9bad3 6899 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6900 }
6901
6902 skb_record_rx_queue(skb, rx_ring->queue_index);
6903
6904 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6905}
6906
2e334eee 6907static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6908{
0ba82994 6909 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6910 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6911 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6912 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6913
2e334eee
AD		 6914 do {
6915 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6916
2e334eee
AD		 6917 /* return some buffers to hardware, one at a time is too slow */
6918 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6919 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6920 cleaned_count = 0;
6921 }
bf36c1a0 6922
2e334eee 6923 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6924
2e334eee
AD		 6925 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6926 break;
9d5c8243 6927
74e238ea
AD		 6928 /* This memory barrier is needed to keep us from reading
6929 * any other fields out of the rx_desc until we know the
6930 * RXD_STAT_DD bit is set
6931 */
6932 rmb();
6933
2e334eee 6934 /* retrieve a buffer from the ring */
f9d40f6a 6935 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6936
2e334eee
AD		 6937 /* exit if we failed to retrieve a buffer */
6938 if (!skb)
6939 break;
1a1c225b 6940
2e334eee 6941 cleaned_count++;
1a1c225b 6942
2e334eee
AD		 6943 /* fetch next buffer in frame if non-eop */
6944 if (igb_is_non_eop(rx_ring, rx_desc))
6945 continue;
1a1c225b
AD		 6946
6947 /* verify the packet layout is correct */
6948 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6949 skb = NULL;
6950 continue;
9d5c8243 6951 }
9d5c8243 6952
db2ee5bd 6953 /* probably a little skewed due to removing CRC */
3ceb90fd 6954 total_bytes += skb->len;
3ceb90fd 6955
db2ee5bd
AD		 6956 /* populate checksum, timestamp, VLAN, and protocol */
6957 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6958
b2cb09b1 6959 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6960
1a1c225b
AD		 6961 /* reset skb pointer */
6962 skb = NULL;
6963
2e334eee
AD		 6964 /* update budget accounting */
6965 total_packets++;
6966 } while (likely(total_packets < budget));
bf36c1a0 6967
1a1c225b
AD		 6968 /* place incomplete frames back on ring for completion */
6969 rx_ring->skb = skb;
6970
12dcd86b 6971 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6972 rx_ring->rx_stats.packets += total_packets;
6973 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6974 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6975 q_vector->rx.total_packets += total_packets;
6976 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6977
6978 if (cleaned_count)
cd392f5c 6979 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6980
2e334eee 6981 return (total_packets < budget);
9d5c8243
AK		 6982}
6983
c023cd88 6984static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6985 struct igb_rx_buffer *bi)
c023cd88
AD		 6986{
6987 struct page *page = bi->page;
cbc8e55f 6988 dma_addr_t dma;
c023cd88 6989
cbc8e55f
AD		 6990 /* since we are recycling buffers we should seldom need to alloc */
6991 if (likely(page))
c023cd88
AD		 6992 return true;
6993
cbc8e55f
AD		 6994 /* alloc new page for storage */
6995 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6996 if (unlikely(!page)) {
6997 rx_ring->rx_stats.alloc_failed++;
6998 return false;
c023cd88
AD		 6999 }
7000
cbc8e55f
AD		 7001 /* map page for use */
7002 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7003
b980ac18 7004 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7005 * there isn't much point in holding memory we can't use
7006 */
1a1c225b 7007 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7008 __free_page(page);
7009
c023cd88
AD		 7010 rx_ring->rx_stats.alloc_failed++;
7011 return false;
7012 }
7013
1a1c225b 7014 bi->dma = dma;
cbc8e55f
AD		 7015 bi->page = page;
7016 bi->page_offset = 0;
1a1c225b 7017
c023cd88
AD		 7018 return true;
7019}
7020
9d5c8243 7021/**
b980ac18
JK		 7022 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7023 * @adapter: address of board private structure
9d5c8243 7024 **/
cd392f5c 7025void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7026{
9d5c8243 7027 union e1000_adv_rx_desc *rx_desc;
06034649 7028 struct igb_rx_buffer *bi;
c023cd88 7029 u16 i = rx_ring->next_to_use;
9d5c8243 7030
cbc8e55f
AD		 7031 /* nothing to do */
7032 if (!cleaned_count)
7033 return;
7034
60136906 7035 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7036 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7037 i -= rx_ring->count;
9d5c8243 7038
cbc8e55f 7039 do {
1a1c225b 7040 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7041 break;
9d5c8243 7042
b980ac18 7043 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7044 * because each write-back erases this info.
7045 */
f9d40f6a 7046 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7047
c023cd88
AD		 7048 rx_desc++;
7049 bi++;
9d5c8243 7050 i++;
c023cd88 7051 if (unlikely(!i)) {
60136906 7052 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7053 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7054 i -= rx_ring->count;
7055 }
7056
7057 /* clear the hdr_addr for the next_to_use descriptor */
7058 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7059
7060 cleaned_count--;
7061 } while (cleaned_count);
9d5c8243 7062
c023cd88
AD		 7063 i += rx_ring->count;
7064
9d5c8243 7065 if (rx_ring->next_to_use != i) {
cbc8e55f 7066 /* record the next descriptor to use */
9d5c8243 7067 rx_ring->next_to_use = i;
9d5c8243 7068
cbc8e55f
AD		 7069 /* update next to alloc since we have filled the ring */
7070 rx_ring->next_to_alloc = i;
7071
b980ac18 7072 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7073 * know there are new descriptors to fetch. (Only
7074 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7075 * such as IA-64).
7076 */
9d5c8243 7077 wmb();
fce99e34 7078 writel(i, rx_ring->tail);
9d5c8243
AK		 7079 }
7080}
7081
7082/**
7083 * igb_mii_ioctl -
7084 * @netdev:
7085 * @ifreq:
7086 * @cmd:
7087 **/
7088static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7089{
7090 struct igb_adapter *adapter = netdev_priv(netdev);
7091 struct mii_ioctl_data *data = if_mii(ifr);
7092
7093 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7094 return -EOPNOTSUPP;
7095
7096 switch (cmd) {
7097 case SIOCGMIIPHY:
7098 data->phy_id = adapter->hw.phy.addr;
7099 break;
7100 case SIOCGMIIREG:
f5f4cf08
AD		 7101 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7102 &data->val_out))
9d5c8243
AK		 7103 return -EIO;
7104 break;
7105 case SIOCSMIIREG:
7106 default:
7107 return -EOPNOTSUPP;
7108 }
7109 return 0;
7110}
7111
7112/**
7113 * igb_ioctl -
7114 * @netdev:
7115 * @ifreq:
7116 * @cmd:
7117 **/
7118static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7119{
7120 switch (cmd) {
7121 case SIOCGMIIPHY:
7122 case SIOCGMIIREG:
7123 case SIOCSMIIREG:
7124 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 7125 case SIOCSHWTSTAMP:
a79f4f88 7126 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 7127 default:
7128 return -EOPNOTSUPP;
7129 }
7130}
7131
009bc06e
AD		 7132s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7133{
7134 struct igb_adapter *adapter = hw->back;
009bc06e 7135
23d028cc 7136 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7137 return -E1000_ERR_CONFIG;
7138
009bc06e
AD		 7139 return 0;
7140}
7141
7142s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7143{
7144 struct igb_adapter *adapter = hw->back;
009bc06e 7145
23d028cc 7146 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7147 return -E1000_ERR_CONFIG;
7148
009bc06e
AD		 7149 return 0;
7150}
7151
c8f44aff 7152static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7153{
7154 struct igb_adapter *adapter = netdev_priv(netdev);
7155 struct e1000_hw *hw = &adapter->hw;
7156 u32 ctrl, rctl;
f646968f 7157 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7158
5faf030c 7159 if (enable) {
9d5c8243
AK		 7160 /* enable VLAN tag insert/strip */
7161 ctrl = rd32(E1000_CTRL);
7162 ctrl |= E1000_CTRL_VME;
7163 wr32(E1000_CTRL, ctrl);
7164
51466239 7165 /* Disable CFI check */
9d5c8243 7166 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7167 rctl &= ~E1000_RCTL_CFIEN;
7168 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7169 } else {
7170 /* disable VLAN tag insert/strip */
7171 ctrl = rd32(E1000_CTRL);
7172 ctrl &= ~E1000_CTRL_VME;
7173 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7174 }
7175
e1739522 7176 igb_rlpml_set(adapter);
9d5c8243
AK		 7177}
7178
80d5c368
PM		 7179static int igb_vlan_rx_add_vid(struct net_device *netdev,
7180 __be16 proto, u16 vid)
9d5c8243
AK		 7181{
7182 struct igb_adapter *adapter = netdev_priv(netdev);
7183 struct e1000_hw *hw = &adapter->hw;
4ae196df 7184 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7185
51466239
AD		 7186 /* attempt to add filter to vlvf array */
7187 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7188
51466239
AD		 7189 /* add the filter since PF can receive vlans w/o entry in vlvf */
7190 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7191
7192 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7193
7194 return 0;
9d5c8243
AK		 7195}
7196
80d5c368
PM		 7197static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7198 __be16 proto, u16 vid)
9d5c8243
AK		 7199{
7200 struct igb_adapter *adapter = netdev_priv(netdev);
7201 struct e1000_hw *hw = &adapter->hw;
4ae196df 7202 int pf_id = adapter->vfs_allocated_count;
51466239 7203 s32 err;
9d5c8243 7204
51466239
AD		 7205 /* remove vlan from VLVF table array */
7206 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7207
51466239
AD		 7208 /* if vid was not present in VLVF just remove it from table */
7209 if (err)
4ae196df 7210 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7211
7212 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7213
7214 return 0;
9d5c8243
AK		 7215}
7216
7217static void igb_restore_vlan(struct igb_adapter *adapter)
7218{
b2cb09b1 7219 u16 vid;
9d5c8243 7220
5faf030c
AD		 7221 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7222
b2cb09b1 7223 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7224 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7225}
7226
14ad2513 7227int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7228{
090b1795 7229 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7230 struct e1000_mac_info *mac = &adapter->hw.mac;
7231
7232 mac->autoneg = 0;
7233
14ad2513 7234 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7235 * for the switch() below to work
7236 */
14ad2513
DD		 7237 if ((spd & 1) || (dplx & ~1))
7238 goto err_inval;
7239
f502ef7d
AA		 7240 /* Fiber NIC's only allow 1000 gbps Full duplex
7241 * and 100Mbps Full duplex for 100baseFx sfp
7242 */
7243 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7244 switch (spd + dplx) {
7245 case SPEED_10 + DUPLEX_HALF:
7246 case SPEED_10 + DUPLEX_FULL:
7247 case SPEED_100 + DUPLEX_HALF:
7248 goto err_inval;
7249 default:
7250 break;
7251 }
7252 }
cd2638a8 7253
14ad2513 7254 switch (spd + dplx) {
9d5c8243
AK		 7255 case SPEED_10 + DUPLEX_HALF:
7256 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7257 break;
7258 case SPEED_10 + DUPLEX_FULL:
7259 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7260 break;
7261 case SPEED_100 + DUPLEX_HALF:
7262 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7263 break;
7264 case SPEED_100 + DUPLEX_FULL:
7265 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7266 break;
7267 case SPEED_1000 + DUPLEX_FULL:
7268 mac->autoneg = 1;
7269 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7270 break;
7271 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7272 default:
14ad2513 7273 goto err_inval;
9d5c8243 7274 }
8376dad0
JB		 7275
7276 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7277 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7278
9d5c8243 7279 return 0;
14ad2513
DD		 7280
7281err_inval:
7282 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7283 return -EINVAL;
9d5c8243
AK		 7284}
7285
749ab2cd
YZ		 7286static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7287 bool runtime)
9d5c8243
AK		 7288{
7289 struct net_device *netdev = pci_get_drvdata(pdev);
7290 struct igb_adapter *adapter = netdev_priv(netdev);
7291 struct e1000_hw *hw = &adapter->hw;
2d064c06 7292 u32 ctrl, rctl, status;
749ab2cd 7293 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7294#ifdef CONFIG_PM
7295 int retval = 0;
7296#endif
7297
7298 netif_device_detach(netdev);
7299
a88f10ec 7300 if (netif_running(netdev))
749ab2cd 7301 __igb_close(netdev, true);
a88f10ec 7302
047e0030 7303 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7304
7305#ifdef CONFIG_PM
7306 retval = pci_save_state(pdev);
7307 if (retval)
7308 return retval;
7309#endif
7310
7311 status = rd32(E1000_STATUS);
7312 if (status & E1000_STATUS_LU)
7313 wufc &= ~E1000_WUFC_LNKC;
7314
7315 if (wufc) {
7316 igb_setup_rctl(adapter);
ff41f8dc 7317 igb_set_rx_mode(netdev);
9d5c8243
AK		 7318
7319 /* turn on all-multi mode if wake on multicast is enabled */
7320 if (wufc & E1000_WUFC_MC) {
7321 rctl = rd32(E1000_RCTL);
7322 rctl |= E1000_RCTL_MPE;
7323 wr32(E1000_RCTL, rctl);
7324 }
7325
7326 ctrl = rd32(E1000_CTRL);
7327 /* advertise wake from D3Cold */
7328 #define E1000_CTRL_ADVD3WUC 0x00100000
7329 /* phy power management enable */
7330 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7331 ctrl |= E1000_CTRL_ADVD3WUC;
7332 wr32(E1000_CTRL, ctrl);
7333
9d5c8243 7334 /* Allow time for pending master requests to run */
330a6d6a 7335 igb_disable_pcie_master(hw);
9d5c8243
AK		 7336
7337 wr32(E1000_WUC, E1000_WUC_PME_EN);
7338 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7339 } else {
7340 wr32(E1000_WUC, 0);
7341 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7342 }
7343
3fe7c4c9
RW		 7344 *enable_wake = wufc || adapter->en_mng_pt;
7345 if (!*enable_wake)
88a268c1
NN		 7346 igb_power_down_link(adapter);
7347 else
7348 igb_power_up_link(adapter);
9d5c8243
AK		 7349
7350 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7351 * would have already happened in close and is redundant.
7352 */
9d5c8243
AK		 7353 igb_release_hw_control(adapter);
7354
7355 pci_disable_device(pdev);
7356
9d5c8243
AK		 7357 return 0;
7358}
7359
7360#ifdef CONFIG_PM
d9dd966d 7361#ifdef CONFIG_PM_SLEEP
749ab2cd 7362static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7363{
7364 int retval;
7365 bool wake;
749ab2cd 7366 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7367
749ab2cd 7368 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7369 if (retval)
7370 return retval;
7371
7372 if (wake) {
7373 pci_prepare_to_sleep(pdev);
7374 } else {
7375 pci_wake_from_d3(pdev, false);
7376 pci_set_power_state(pdev, PCI_D3hot);
7377 }
7378
7379 return 0;
7380}
d9dd966d 7381#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7382
749ab2cd 7383static int igb_resume(struct device *dev)
9d5c8243 7384{
749ab2cd 7385 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7386 struct net_device *netdev = pci_get_drvdata(pdev);
7387 struct igb_adapter *adapter = netdev_priv(netdev);
7388 struct e1000_hw *hw = &adapter->hw;
7389 u32 err;
7390
7391 pci_set_power_state(pdev, PCI_D0);
7392 pci_restore_state(pdev);
b94f2d77 7393 pci_save_state(pdev);
42bfd33a 7394
aed5dec3 7395 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7396 if (err) {
7397 dev_err(&pdev->dev,
7398 "igb: Cannot enable PCI device from suspend\n");
7399 return err;
7400 }
7401 pci_set_master(pdev);
7402
7403 pci_enable_wake(pdev, PCI_D3hot, 0);
7404 pci_enable_wake(pdev, PCI_D3cold, 0);
7405
53c7d064 7406 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7407 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7408 return -ENOMEM;
9d5c8243
AK		 7409 }
7410
9d5c8243 7411 igb_reset(adapter);
a8564f03
AD		 7412
7413 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7414 * driver.
7415 */
a8564f03
AD		 7416 igb_get_hw_control(adapter);
7417
9d5c8243
AK		 7418 wr32(E1000_WUS, ~0);
7419
749ab2cd 7420 if (netdev->flags & IFF_UP) {
0c2cc02e 7421 rtnl_lock();
749ab2cd 7422 err = __igb_open(netdev, true);
0c2cc02e 7423 rtnl_unlock();
a88f10ec
AD		 7424 if (err)
7425 return err;
7426 }
9d5c8243
AK		 7427
7428 netif_device_attach(netdev);
749ab2cd
YZ		 7429 return 0;
7430}
7431
7432#ifdef CONFIG_PM_RUNTIME
7433static int igb_runtime_idle(struct device *dev)
7434{
7435 struct pci_dev *pdev = to_pci_dev(dev);
7436 struct net_device *netdev = pci_get_drvdata(pdev);
7437 struct igb_adapter *adapter = netdev_priv(netdev);
7438
7439 if (!igb_has_link(adapter))
7440 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7441
7442 return -EBUSY;
7443}
7444
7445static int igb_runtime_suspend(struct device *dev)
7446{
7447 struct pci_dev *pdev = to_pci_dev(dev);
7448 int retval;
7449 bool wake;
7450
7451 retval = __igb_shutdown(pdev, &wake, 1);
7452 if (retval)
7453 return retval;
7454
7455 if (wake) {
7456 pci_prepare_to_sleep(pdev);
7457 } else {
7458 pci_wake_from_d3(pdev, false);
7459 pci_set_power_state(pdev, PCI_D3hot);
7460 }
9d5c8243 7461
9d5c8243
AK		 7462 return 0;
7463}
749ab2cd
YZ		 7464
7465static int igb_runtime_resume(struct device *dev)
7466{
7467 return igb_resume(dev);
7468}
7469#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7470#endif
7471
7472static void igb_shutdown(struct pci_dev *pdev)
7473{
3fe7c4c9
RW		 7474 bool wake;
7475
749ab2cd 7476 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7477
7478 if (system_state == SYSTEM_POWER_OFF) {
7479 pci_wake_from_d3(pdev, wake);
7480 pci_set_power_state(pdev, PCI_D3hot);
7481 }
9d5c8243
AK		 7482}
7483
fa44f2f1
GR		 7484#ifdef CONFIG_PCI_IOV
7485static int igb_sriov_reinit(struct pci_dev *dev)
7486{
7487 struct net_device *netdev = pci_get_drvdata(dev);
7488 struct igb_adapter *adapter = netdev_priv(netdev);
7489 struct pci_dev *pdev = adapter->pdev;
7490
7491 rtnl_lock();
7492
7493 if (netif_running(netdev))
7494 igb_close(netdev);
7495
7496 igb_clear_interrupt_scheme(adapter);
7497
7498 igb_init_queue_configuration(adapter);
7499
7500 if (igb_init_interrupt_scheme(adapter, true)) {
7501 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7502 return -ENOMEM;
7503 }
7504
7505 if (netif_running(netdev))
7506 igb_open(netdev);
7507
7508 rtnl_unlock();
7509
7510 return 0;
7511}
7512
7513static int igb_pci_disable_sriov(struct pci_dev *dev)
7514{
7515 int err = igb_disable_sriov(dev);
7516
7517 if (!err)
7518 err = igb_sriov_reinit(dev);
7519
7520 return err;
7521}
7522
7523static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7524{
7525 int err = igb_enable_sriov(dev, num_vfs);
7526
7527 if (err)
7528 goto out;
7529
7530 err = igb_sriov_reinit(dev);
7531 if (!err)
7532 return num_vfs;
7533
7534out:
7535 return err;
7536}
7537
7538#endif
7539static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7540{
7541#ifdef CONFIG_PCI_IOV
7542 if (num_vfs == 0)
7543 return igb_pci_disable_sriov(dev);
7544 else
7545 return igb_pci_enable_sriov(dev, num_vfs);
7546#endif
7547 return 0;
7548}
7549
9d5c8243 7550#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7551/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7552 * without having to re-enable interrupts. It's not called while
7553 * the interrupt routine is executing.
7554 */
7555static void igb_netpoll(struct net_device *netdev)
7556{
7557 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7558 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7559 struct igb_q_vector *q_vector;
9d5c8243 7560 int i;
9d5c8243 7561
047e0030 7562 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7563 q_vector = adapter->q_vector[i];
7564 if (adapter->msix_entries)
7565 wr32(E1000_EIMC, q_vector->eims_value);
7566 else
7567 igb_irq_disable(adapter);
047e0030 7568 napi_schedule(&q_vector->napi);
eebbbdba 7569 }
9d5c8243
AK		 7570}
7571#endif /* CONFIG_NET_POLL_CONTROLLER */
7572
7573/**
b980ac18
JK		 7574 * igb_io_error_detected - called when PCI error is detected
7575 * @pdev: Pointer to PCI device
7576 * @state: The current pci connection state
9d5c8243 7577 *
b980ac18
JK		 7578 * This function is called after a PCI bus error affecting
7579 * this device has been detected.
7580 **/
9d5c8243
AK		 7581static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7582 pci_channel_state_t state)
7583{
7584 struct net_device *netdev = pci_get_drvdata(pdev);
7585 struct igb_adapter *adapter = netdev_priv(netdev);
7586
7587 netif_device_detach(netdev);
7588
59ed6eec
AD		 7589 if (state == pci_channel_io_perm_failure)
7590 return PCI_ERS_RESULT_DISCONNECT;
7591
9d5c8243
AK		 7592 if (netif_running(netdev))
7593 igb_down(adapter);
7594 pci_disable_device(pdev);
7595
7596 /* Request a slot slot reset. */
7597 return PCI_ERS_RESULT_NEED_RESET;
7598}
7599
7600/**
b980ac18
JK		 7601 * igb_io_slot_reset - called after the pci bus has been reset.
7602 * @pdev: Pointer to PCI device
9d5c8243 7603 *
b980ac18
JK		 7604 * Restart the card from scratch, as if from a cold-boot. Implementation
7605 * resembles the first-half of the igb_resume routine.
7606 **/
9d5c8243
AK		 7607static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7608{
7609 struct net_device *netdev = pci_get_drvdata(pdev);
7610 struct igb_adapter *adapter = netdev_priv(netdev);
7611 struct e1000_hw *hw = &adapter->hw;
40a914fa 7612 pci_ers_result_t result;
42bfd33a 7613 int err;
9d5c8243 7614
aed5dec3 7615 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7616 dev_err(&pdev->dev,
7617 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7618 result = PCI_ERS_RESULT_DISCONNECT;
7619 } else {
7620 pci_set_master(pdev);
7621 pci_restore_state(pdev);
b94f2d77 7622 pci_save_state(pdev);
9d5c8243 7623
40a914fa
AD		 7624 pci_enable_wake(pdev, PCI_D3hot, 0);
7625 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7626
40a914fa
AD		 7627 igb_reset(adapter);
7628 wr32(E1000_WUS, ~0);
7629 result = PCI_ERS_RESULT_RECOVERED;
7630 }
9d5c8243 7631
ea943d41
JK		 7632 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7633 if (err) {
b980ac18
JK		 7634 dev_err(&pdev->dev,
7635 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7636 err);
ea943d41
JK		 7637 /* non-fatal, continue */
7638 }
40a914fa
AD		 7639
7640 return result;
9d5c8243
AK		 7641}
7642
7643/**
b980ac18
JK		 7644 * igb_io_resume - called when traffic can start flowing again.
7645 * @pdev: Pointer to PCI device
9d5c8243 7646 *
b980ac18
JK		 7647 * This callback is called when the error recovery driver tells us that
7648 * its OK to resume normal operation. Implementation resembles the
7649 * second-half of the igb_resume routine.
9d5c8243
AK		 7650 */
7651static void igb_io_resume(struct pci_dev *pdev)
7652{
7653 struct net_device *netdev = pci_get_drvdata(pdev);
7654 struct igb_adapter *adapter = netdev_priv(netdev);
7655
9d5c8243
AK		 7656 if (netif_running(netdev)) {
7657 if (igb_up(adapter)) {
7658 dev_err(&pdev->dev, "igb_up failed after reset\n");
7659 return;
7660 }
7661 }
7662
7663 netif_device_attach(netdev);
7664
7665 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7666 * driver.
7667 */
9d5c8243 7668 igb_get_hw_control(adapter);
9d5c8243
AK		 7669}
7670
26ad9178 7671static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7672 u8 qsel)
26ad9178
AD		 7673{
7674 u32 rar_low, rar_high;
7675 struct e1000_hw *hw = &adapter->hw;
7676
7677 /* HW expects these in little endian so we reverse the byte order
7678 * from network order (big endian) to little endian
7679 */
7680 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7681 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7682 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7683
7684 /* Indicate to hardware the Address is Valid. */
7685 rar_high |= E1000_RAH_AV;
7686
7687 if (hw->mac.type == e1000_82575)
7688 rar_high |= E1000_RAH_POOL_1 * qsel;
7689 else
7690 rar_high |= E1000_RAH_POOL_1 << qsel;
7691
7692 wr32(E1000_RAL(index), rar_low);
7693 wrfl();
7694 wr32(E1000_RAH(index), rar_high);
7695 wrfl();
7696}
7697
4ae196df 7698static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7699 int vf, unsigned char *mac_addr)
4ae196df
AD		 7700{
7701 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7702 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7703 * towards the first, as a result a collision should not be possible
7704 */
ff41f8dc 7705 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7706
37680117 7707 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7708
26ad9178 7709 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7710
7711 return 0;
7712}
7713
8151d294
WM		 7714static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7715{
7716 struct igb_adapter *adapter = netdev_priv(netdev);
7717 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7718 return -EINVAL;
7719 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7720 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7721 dev_info(&adapter->pdev->dev,
7722 "Reload the VF driver to make this change effective.");
8151d294 7723 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7724 dev_warn(&adapter->pdev->dev,
7725 "The VF MAC address has been set, but the PF device is not up.\n");
7726 dev_warn(&adapter->pdev->dev,
7727 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7728 }
7729 return igb_set_vf_mac(adapter, vf, mac);
7730}
7731
17dc566c
LL		 7732static int igb_link_mbps(int internal_link_speed)
7733{
7734 switch (internal_link_speed) {
7735 case SPEED_100:
7736 return 100;
7737 case SPEED_1000:
7738 return 1000;
7739 default:
7740 return 0;
7741 }
7742}
7743
7744static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7745 int link_speed)
7746{
7747 int rf_dec, rf_int;
7748 u32 bcnrc_val;
7749
7750 if (tx_rate != 0) {
7751 /* Calculate the rate factor values to set */
7752 rf_int = link_speed / tx_rate;
7753 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7754 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7755 tx_rate;
17dc566c
LL		 7756
7757 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7758 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7759 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7760 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7761 } else {
7762 bcnrc_val = 0;
7763 }
7764
7765 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7766 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7767 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7768 */
7769 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7770 wr32(E1000_RTTBCNRC, bcnrc_val);
7771}
7772
7773static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7774{
7775 int actual_link_speed, i;
7776 bool reset_rate = false;
7777
7778 /* VF TX rate limit was not set or not supported */
7779 if ((adapter->vf_rate_link_speed == 0) ||
7780 (adapter->hw.mac.type != e1000_82576))
7781 return;
7782
7783 actual_link_speed = igb_link_mbps(adapter->link_speed);
7784 if (actual_link_speed != adapter->vf_rate_link_speed) {
7785 reset_rate = true;
7786 adapter->vf_rate_link_speed = 0;
7787 dev_info(&adapter->pdev->dev,
b980ac18 7788 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7789 }
7790
7791 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7792 if (reset_rate)
7793 adapter->vf_data[i].tx_rate = 0;
7794
7795 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7796 adapter->vf_data[i].tx_rate,
7797 actual_link_speed);
17dc566c
LL		 7798 }
7799}
7800
8151d294
WM		 7801static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7802{
17dc566c
LL		 7803 struct igb_adapter *adapter = netdev_priv(netdev);
7804 struct e1000_hw *hw = &adapter->hw;
7805 int actual_link_speed;
7806
7807 if (hw->mac.type != e1000_82576)
7808 return -EOPNOTSUPP;
7809
7810 actual_link_speed = igb_link_mbps(adapter->link_speed);
7811 if ((vf >= adapter->vfs_allocated_count) ||
7812 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7813 (tx_rate < 0) || (tx_rate > actual_link_speed))
7814 return -EINVAL;
7815
7816 adapter->vf_rate_link_speed = actual_link_speed;
7817 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7818 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7819
7820 return 0;
8151d294
WM		 7821}
7822
70ea4783
LL		 7823static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7824 bool setting)
7825{
7826 struct igb_adapter *adapter = netdev_priv(netdev);
7827 struct e1000_hw *hw = &adapter->hw;
7828 u32 reg_val, reg_offset;
7829
7830 if (!adapter->vfs_allocated_count)
7831 return -EOPNOTSUPP;
7832
7833 if (vf >= adapter->vfs_allocated_count)
7834 return -EINVAL;
7835
7836 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7837 reg_val = rd32(reg_offset);
7838 if (setting)
7839 reg_val |= ((1 << vf) |
7840 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7841 else
7842 reg_val &= ~((1 << vf) |
7843 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7844 wr32(reg_offset, reg_val);
7845
7846 adapter->vf_data[vf].spoofchk_enabled = setting;
7847 return E1000_SUCCESS;
7848}
7849
8151d294
WM		 7850static int igb_ndo_get_vf_config(struct net_device *netdev,
7851 int vf, struct ifla_vf_info *ivi)
7852{
7853 struct igb_adapter *adapter = netdev_priv(netdev);
7854 if (vf >= adapter->vfs_allocated_count)
7855 return -EINVAL;
7856 ivi->vf = vf;
7857 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7858 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7859 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7860 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7861 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7862 return 0;
7863}
7864
4ae196df
AD		 7865static void igb_vmm_control(struct igb_adapter *adapter)
7866{
7867 struct e1000_hw *hw = &adapter->hw;
10d8e907 7868 u32 reg;
4ae196df 7869
52a1dd4d
AD		 7870 switch (hw->mac.type) {
7871 case e1000_82575:
f96a8a0b
CW		 7872 case e1000_i210:
7873 case e1000_i211:
ceb5f13b 7874 case e1000_i354:
52a1dd4d
AD		 7875 default:
7876 /* replication is not supported for 82575 */
4ae196df 7877 return;
52a1dd4d
AD		 7878 case e1000_82576:
7879 /* notify HW that the MAC is adding vlan tags */
7880 reg = rd32(E1000_DTXCTL);
7881 reg |= E1000_DTXCTL_VLAN_ADDED;
7882 wr32(E1000_DTXCTL, reg);
7883 case e1000_82580:
7884 /* enable replication vlan tag stripping */
7885 reg = rd32(E1000_RPLOLR);
7886 reg |= E1000_RPLOLR_STRVLAN;
7887 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7888 case e1000_i350:
7889 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7890 break;
7891 }
10d8e907 7892
d4960307
AD		 7893 if (adapter->vfs_allocated_count) {
7894 igb_vmdq_set_loopback_pf(hw, true);
7895 igb_vmdq_set_replication_pf(hw, true);
13800469 7896 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7897 adapter->vfs_allocated_count);
d4960307
AD		 7898 } else {
7899 igb_vmdq_set_loopback_pf(hw, false);
7900 igb_vmdq_set_replication_pf(hw, false);
7901 }
4ae196df
AD		 7902}
7903
b6e0c419
CW		 7904static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7905{
7906 struct e1000_hw *hw = &adapter->hw;
7907 u32 dmac_thr;
7908 u16 hwm;
7909
7910 if (hw->mac.type > e1000_82580) {
7911 if (adapter->flags & IGB_FLAG_DMAC) {
7912 u32 reg;
7913
7914 /* force threshold to 0. */
7915 wr32(E1000_DMCTXTH, 0);
7916
b980ac18 7917 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7918 * than the Rx threshold. Set hwm to PBA - max frame
7919 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7920 */
e8c626e9
MV		 7921 hwm = 64 * pba - adapter->max_frame_size / 16;
7922 if (hwm < 64 * (pba - 6))
7923 hwm = 64 * (pba - 6);
7924 reg = rd32(E1000_FCRTC);
7925 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7926 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7927 & E1000_FCRTC_RTH_COAL_MASK);
7928 wr32(E1000_FCRTC, reg);
7929
b980ac18 7930 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7931 * frame size, capping it at PBA - 10KB.
7932 */
7933 dmac_thr = pba - adapter->max_frame_size / 512;
7934 if (dmac_thr < pba - 10)
7935 dmac_thr = pba - 10;
b6e0c419
CW		 7936 reg = rd32(E1000_DMACR);
7937 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7938 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7939 & E1000_DMACR_DMACTHR_MASK);
7940
7941 /* transition to L0x or L1 if available..*/
7942 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7943
7944 /* watchdog timer= +-1000 usec in 32usec intervals */
7945 reg |= (1000 >> 5);
0c02dd98
MV		 7946
7947 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7948 if (hw->mac.type != e1000_i354)
7949 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7950
b6e0c419
CW		 7951 wr32(E1000_DMACR, reg);
7952
b980ac18 7953 /* no lower threshold to disable
b6e0c419
CW		 7954 * coalescing(smart fifb)-UTRESH=0
7955 */
7956 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7957
7958 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7959
7960 wr32(E1000_DMCTLX, reg);
7961
b980ac18 7962 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7963 * DMA coal
7964 */
7965 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7966 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7967
b980ac18 7968 /* make low power state decision controlled
b6e0c419
CW		 7969 * by DMA coal
7970 */
7971 reg = rd32(E1000_PCIEMISC);
7972 reg &= ~E1000_PCIEMISC_LX_DECISION;
7973 wr32(E1000_PCIEMISC, reg);
7974 } /* endif adapter->dmac is not disabled */
7975 } else if (hw->mac.type == e1000_82580) {
7976 u32 reg = rd32(E1000_PCIEMISC);
7977 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7978 wr32(E1000_DMACR, 0);
7979 }
7980}
7981
b980ac18
JK		 7982/**
7983 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7984 * @hw: pointer to hardware structure
7985 * @byte_offset: byte offset to read
7986 * @dev_addr: device address
7987 * @data: value read
7988 *
7989 * Performs byte read operation over I2C interface at
7990 * a specified device address.
b980ac18 7991 **/
441fc6fd 7992s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7993 u8 dev_addr, u8 *data)
441fc6fd
CW		 7994{
7995 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7996 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7997 s32 status;
7998 u16 swfw_mask = 0;
7999
8000 if (!this_client)
8001 return E1000_ERR_I2C;
8002
8003 swfw_mask = E1000_SWFW_PHY0_SM;
8004
8005 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
8006 != E1000_SUCCESS)
8007 return E1000_ERR_SWFW_SYNC;
8008
8009 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8010 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8011
8012 if (status < 0)
8013 return E1000_ERR_I2C;
8014 else {
8015 *data = status;
8016 return E1000_SUCCESS;
8017 }
8018}
8019
b980ac18
JK		 8020/**
8021 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8022 * @hw: pointer to hardware structure
8023 * @byte_offset: byte offset to write
8024 * @dev_addr: device address
8025 * @data: value to write
8026 *
8027 * Performs byte write operation over I2C interface at
8028 * a specified device address.
b980ac18 8029 **/
441fc6fd 8030s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8031 u8 dev_addr, u8 data)
441fc6fd
CW		 8032{
8033 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8034 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8035 s32 status;
8036 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8037
8038 if (!this_client)
8039 return E1000_ERR_I2C;
8040
8041 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
8042 return E1000_ERR_SWFW_SYNC;
8043 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8044 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8045
8046 if (status)
8047 return E1000_ERR_I2C;
8048 else
8049 return E1000_SUCCESS;
8050
8051}
907b7835
LMV		 8052
8053int igb_reinit_queues(struct igb_adapter *adapter)
8054{
8055 struct net_device *netdev = adapter->netdev;
8056 struct pci_dev *pdev = adapter->pdev;
8057 int err = 0;
8058
8059 if (netif_running(netdev))
8060 igb_close(netdev);
8061
02ef6e1d 8062 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8063
8064 if (igb_init_interrupt_scheme(adapter, true)) {
8065 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8066 return -ENOMEM;
8067 }
8068
8069 if (netif_running(netdev))
8070 err = igb_open(netdev);
8071
8072 return err;
8073}
9d5c8243 8074/* igb_main.c */
Linux kernel - Deliverables
This page took 1.419494 seconds and 5 git commands to generate.