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bnx2x: remove __dev* attributes
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
6e861326 4 Copyright(c) 2007-2012 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
9d5c8243
AK		 60#include "igb.h"
61
200e5fd5
CW		 62#define MAJ 4
63#define MIN 0
3db73804 64#define BUILD 17
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
6e861326 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
9d5c8243 72
9d5c8243
AK		 73static const struct e1000_info *igb_info_tbl[] = {
74 [board_82575] = &e1000_82575_info,
75};
76
a3aa1884 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
108 /* required last entry */
109 {0, }
110};
111
112MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
113
114void igb_reset(struct igb_adapter *);
115static int igb_setup_all_tx_resources(struct igb_adapter *);
116static int igb_setup_all_rx_resources(struct igb_adapter *);
117static void igb_free_all_tx_resources(struct igb_adapter *);
118static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 119static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 120static int igb_probe(struct pci_dev *, const struct pci_device_id *);
121static void __devexit igb_remove(struct pci_dev *pdev);
122static int igb_sw_init(struct igb_adapter *);
123static int igb_open(struct net_device *);
124static int igb_close(struct net_device *);
125static void igb_configure_tx(struct igb_adapter *);
126static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 127static void igb_clean_all_tx_rings(struct igb_adapter *);
128static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 129static void igb_clean_tx_ring(struct igb_ring *);
130static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 131static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 132static void igb_update_phy_info(unsigned long);
133static void igb_watchdog(unsigned long);
134static void igb_watchdog_task(struct work_struct *);
cd392f5c 135static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 136static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
137 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 138static int igb_change_mtu(struct net_device *, int);
139static int igb_set_mac(struct net_device *, void *);
68d480c4 140static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 141static irqreturn_t igb_intr(int irq, void *);
142static irqreturn_t igb_intr_msi(int irq, void *);
143static irqreturn_t igb_msix_other(int irq, void *);
047e0030 144static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 145#ifdef CONFIG_IGB_DCA
047e0030 146static void igb_update_dca(struct igb_q_vector *);
fe4506b6 147static void igb_setup_dca(struct igb_adapter *);
421e02f0 148#endif /* CONFIG_IGB_DCA */
661086df 149static int igb_poll(struct napi_struct *, int);
13fde97a 150static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 151static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 152static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
153static void igb_tx_timeout(struct net_device *);
154static void igb_reset_task(struct work_struct *);
c8f44aff 155static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 156static int igb_vlan_rx_add_vid(struct net_device *, u16);
157static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 158static void igb_restore_vlan(struct igb_adapter *);
26ad9178 159static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 160static void igb_ping_all_vfs(struct igb_adapter *);
161static void igb_msg_task(struct igb_adapter *);
4ae196df 162static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 163static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 164static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 165static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
166static int igb_ndo_set_vf_vlan(struct net_device *netdev,
167 int vf, u16 vlan, u8 qos);
168static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
169static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
170 struct ifla_vf_info *ivi);
17dc566c 171static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 172
173#ifdef CONFIG_PCI_IOV
0224d663 174static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 175static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 176#endif
9d5c8243 177
9d5c8243 178#ifdef CONFIG_PM
d9dd966d 179#ifdef CONFIG_PM_SLEEP
749ab2cd 180static int igb_suspend(struct device *);
d9dd966d 181#endif
749ab2cd
YZ		 182static int igb_resume(struct device *);
183#ifdef CONFIG_PM_RUNTIME
184static int igb_runtime_suspend(struct device *dev);
185static int igb_runtime_resume(struct device *dev);
186static int igb_runtime_idle(struct device *dev);
187#endif
188static const struct dev_pm_ops igb_pm_ops = {
189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
191 igb_runtime_idle)
192};
9d5c8243
AK		 193#endif
194static void igb_shutdown(struct pci_dev *);
421e02f0 195#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 196static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197static struct notifier_block dca_notifier = {
198 .notifier_call = igb_notify_dca,
199 .next = NULL,
200 .priority = 0
201};
202#endif
9d5c8243
AK		 203#ifdef CONFIG_NET_POLL_CONTROLLER
204/* for netdump / net console */
205static void igb_netpoll(struct net_device *);
206#endif
37680117 207#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 208static unsigned int max_vfs = 0;
209module_param(max_vfs, uint, 0);
210MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
211 "per physical function");
212#endif /* CONFIG_PCI_IOV */
213
9d5c8243
AK		 214static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
215 pci_channel_state_t);
216static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
217static void igb_io_resume(struct pci_dev *);
218
3646f0e5 219static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 220 .error_detected = igb_io_error_detected,
221 .slot_reset = igb_io_slot_reset,
222 .resume = igb_io_resume,
223};
224
b6e0c419 225static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 226
227static struct pci_driver igb_driver = {
228 .name = igb_driver_name,
229 .id_table = igb_pci_tbl,
230 .probe = igb_probe,
231 .remove = __devexit_p(igb_remove),
232#ifdef CONFIG_PM
749ab2cd 233 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 234#endif
235 .shutdown = igb_shutdown,
236 .err_handler = &igb_err_handler
237};
238
239MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
240MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
241MODULE_LICENSE("GPL");
242MODULE_VERSION(DRV_VERSION);
243
b3f4d599 244#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
245static int debug = -1;
246module_param(debug, int, 0);
247MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
248
c97ec42a
TI		 249struct igb_reg_info {
250 u32 ofs;
251 char *name;
252};
253
254static const struct igb_reg_info igb_reg_info_tbl[] = {
255
256 /* General Registers */
257 {E1000_CTRL, "CTRL"},
258 {E1000_STATUS, "STATUS"},
259 {E1000_CTRL_EXT, "CTRL_EXT"},
260
261 /* Interrupt Registers */
262 {E1000_ICR, "ICR"},
263
264 /* RX Registers */
265 {E1000_RCTL, "RCTL"},
266 {E1000_RDLEN(0), "RDLEN"},
267 {E1000_RDH(0), "RDH"},
268 {E1000_RDT(0), "RDT"},
269 {E1000_RXDCTL(0), "RXDCTL"},
270 {E1000_RDBAL(0), "RDBAL"},
271 {E1000_RDBAH(0), "RDBAH"},
272
273 /* TX Registers */
274 {E1000_TCTL, "TCTL"},
275 {E1000_TDBAL(0), "TDBAL"},
276 {E1000_TDBAH(0), "TDBAH"},
277 {E1000_TDLEN(0), "TDLEN"},
278 {E1000_TDH(0), "TDH"},
279 {E1000_TDT(0), "TDT"},
280 {E1000_TXDCTL(0), "TXDCTL"},
281 {E1000_TDFH, "TDFH"},
282 {E1000_TDFT, "TDFT"},
283 {E1000_TDFHS, "TDFHS"},
284 {E1000_TDFPC, "TDFPC"},
285
286 /* List Terminator */
287 {}
288};
289
290/*
291 * igb_regdump - register printout routine
292 */
293static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
294{
295 int n = 0;
296 char rname[16];
297 u32 regs[8];
298
299 switch (reginfo->ofs) {
300 case E1000_RDLEN(0):
301 for (n = 0; n < 4; n++)
302 regs[n] = rd32(E1000_RDLEN(n));
303 break;
304 case E1000_RDH(0):
305 for (n = 0; n < 4; n++)
306 regs[n] = rd32(E1000_RDH(n));
307 break;
308 case E1000_RDT(0):
309 for (n = 0; n < 4; n++)
310 regs[n] = rd32(E1000_RDT(n));
311 break;
312 case E1000_RXDCTL(0):
313 for (n = 0; n < 4; n++)
314 regs[n] = rd32(E1000_RXDCTL(n));
315 break;
316 case E1000_RDBAL(0):
317 for (n = 0; n < 4; n++)
318 regs[n] = rd32(E1000_RDBAL(n));
319 break;
320 case E1000_RDBAH(0):
321 for (n = 0; n < 4; n++)
322 regs[n] = rd32(E1000_RDBAH(n));
323 break;
324 case E1000_TDBAL(0):
325 for (n = 0; n < 4; n++)
326 regs[n] = rd32(E1000_RDBAL(n));
327 break;
328 case E1000_TDBAH(0):
329 for (n = 0; n < 4; n++)
330 regs[n] = rd32(E1000_TDBAH(n));
331 break;
332 case E1000_TDLEN(0):
333 for (n = 0; n < 4; n++)
334 regs[n] = rd32(E1000_TDLEN(n));
335 break;
336 case E1000_TDH(0):
337 for (n = 0; n < 4; n++)
338 regs[n] = rd32(E1000_TDH(n));
339 break;
340 case E1000_TDT(0):
341 for (n = 0; n < 4; n++)
342 regs[n] = rd32(E1000_TDT(n));
343 break;
344 case E1000_TXDCTL(0):
345 for (n = 0; n < 4; n++)
346 regs[n] = rd32(E1000_TXDCTL(n));
347 break;
348 default:
876d2d6f 349 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 350 return;
351 }
352
353 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 354 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
355 regs[2], regs[3]);
c97ec42a
TI		 356}
357
358/*
359 * igb_dump - Print registers, tx-rings and rx-rings
360 */
361static void igb_dump(struct igb_adapter *adapter)
362{
363 struct net_device *netdev = adapter->netdev;
364 struct e1000_hw *hw = &adapter->hw;
365 struct igb_reg_info *reginfo;
c97ec42a
TI		 366 struct igb_ring *tx_ring;
367 union e1000_adv_tx_desc *tx_desc;
368 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 369 struct igb_ring *rx_ring;
370 union e1000_adv_rx_desc *rx_desc;
371 u32 staterr;
6ad4edfc 372 u16 i, n;
c97ec42a
TI		 373
374 if (!netif_msg_hw(adapter))
375 return;
376
377 /* Print netdevice Info */
378 if (netdev) {
379 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 380 pr_info("Device Name state trans_start "
381 "last_rx\n");
382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 388 pr_info(" Register Name Value\n");
c97ec42a
TI		 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 400 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 401 struct igb_tx_buffer *buffer_info;
c97ec42a 402 tx_ring = adapter->tx_ring[n];
06034649 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
c97ec42a
TI		 410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
435 "[bi->dma ] leng ntw timestamp "
436 "bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
454 pr_info("T [0x%03X] %016llX %016llX %016llX"
455 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 456 le64_to_cpu(u0->a),
457 le64_to_cpu(u0->b),
c9f14bf3
AD		 458 (u64)dma_unmap_addr(buffer_info, dma),
459 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 460 buffer_info->next_to_watch,
461 (u64)buffer_info->time_stamp,
876d2d6f 462 buffer_info->skb, next_desc);
c97ec42a 463
b669588a 464 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 465 print_hex_dump(KERN_INFO, "",
466 DUMP_PREFIX_ADDRESS,
b669588a 467 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 468 dma_unmap_len(buffer_info, len),
469 true);
c97ec42a
TI		 470 }
471 }
472
473 /* Print RX Rings Summary */
474rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 476 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
516 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
517 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
518 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 519
520 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 521 const char *next_desc;
06034649
AD		 522 struct igb_rx_buffer *buffer_info;
523 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 524 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 525 u0 = (struct my_u0 *)rx_desc;
526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 527
528 if (i == rx_ring->next_to_use)
529 next_desc = " NTU";
530 else if (i == rx_ring->next_to_clean)
531 next_desc = " NTC";
532 else
533 next_desc = "";
534
c97ec42a
TI		 535 if (staterr & E1000_RXD_STAT_DD) {
536 /* Descriptor Done */
1a1c225b
AD		 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
538 "RWB", i,
c97ec42a
TI		 539 le64_to_cpu(u0->a),
540 le64_to_cpu(u0->b),
1a1c225b 541 next_desc);
c97ec42a 542 } else {
1a1c225b
AD		 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
544 "R ", i,
c97ec42a
TI		 545 le64_to_cpu(u0->a),
546 le64_to_cpu(u0->b),
547 (u64)buffer_info->dma,
1a1c225b 548 next_desc);
c97ec42a 549
b669588a 550 if (netif_msg_pktdata(adapter) &&
1a1c225b 551 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 552 print_hex_dump(KERN_INFO, "",
553 DUMP_PREFIX_ADDRESS,
554 16, 1,
b669588a
ET		 555 page_address(buffer_info->page) +
556 buffer_info->page_offset,
de78d1f9 557 IGB_RX_BUFSZ, true);
c97ec42a
TI		 558 }
559 }
c97ec42a
TI		 560 }
561 }
562
563exit:
564 return;
565}
566
9d5c8243 567/**
c041076a 568 * igb_get_hw_dev - return device
9d5c8243
AK		 569 * used by hardware layer to print debugging information
570 **/
c041076a 571struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 572{
573 struct igb_adapter *adapter = hw->back;
c041076a 574 return adapter->netdev;
9d5c8243 575}
38c845c7 576
9d5c8243
AK		 577/**
578 * igb_init_module - Driver Registration Routine
579 *
580 * igb_init_module is the first routine called when the driver is
581 * loaded. All it does is register with the PCI subsystem.
582 **/
583static int __init igb_init_module(void)
584{
585 int ret;
876d2d6f 586 pr_info("%s - version %s\n",
9d5c8243
AK		 587 igb_driver_string, igb_driver_version);
588
876d2d6f 589 pr_info("%s\n", igb_copyright);
9d5c8243 590
421e02f0 591#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 592 dca_register_notify(&dca_notifier);
593#endif
bbd98fe4 594 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 595 return ret;
596}
597
598module_init(igb_init_module);
599
600/**
601 * igb_exit_module - Driver Exit Cleanup Routine
602 *
603 * igb_exit_module is called just before the driver is removed
604 * from memory.
605 **/
606static void __exit igb_exit_module(void)
607{
421e02f0 608#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 609 dca_unregister_notify(&dca_notifier);
610#endif
9d5c8243
AK		 611 pci_unregister_driver(&igb_driver);
612}
613
614module_exit(igb_exit_module);
615
26bc19ec
AD		 616#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
617/**
618 * igb_cache_ring_register - Descriptor ring to register mapping
619 * @adapter: board private structure to initialize
620 *
621 * Once we know the feature-set enabled for the device, we'll cache
622 * the register offset the descriptor ring is assigned to.
623 **/
624static void igb_cache_ring_register(struct igb_adapter *adapter)
625{
ee1b9f06 626 int i = 0, j = 0;
047e0030 627 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 628
629 switch (adapter->hw.mac.type) {
630 case e1000_82576:
631 /* The queues are allocated for virtualization such that VF 0
632 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
633 * In order to avoid collision we start at the first free queue
634 * and continue consuming queues in the same sequence
635 */
ee1b9f06 636 if (adapter->vfs_allocated_count) {
a99955fc 637 for (; i < adapter->rss_queues; i++)
3025a446
AD		 638 adapter->rx_ring[i]->reg_idx = rbase_offset +
639 Q_IDX_82576(i);
ee1b9f06 640 }
26bc19ec 641 case e1000_82575:
55cac248 642 case e1000_82580:
d2ba2ed8 643 case e1000_i350:
f96a8a0b
CW		 644 case e1000_i210:
645 case e1000_i211:
26bc19ec 646 default:
ee1b9f06 647 for (; i < adapter->num_rx_queues; i++)
3025a446 648 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 649 for (; j < adapter->num_tx_queues; j++)
3025a446 650 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 651 break;
652 }
653}
654
4be000c8
AD		 655/**
656 * igb_write_ivar - configure ivar for given MSI-X vector
657 * @hw: pointer to the HW structure
658 * @msix_vector: vector number we are allocating to a given ring
659 * @index: row index of IVAR register to write within IVAR table
660 * @offset: column offset of in IVAR, should be multiple of 8
661 *
662 * This function is intended to handle the writing of the IVAR register
663 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
664 * each containing an cause allocation for an Rx and Tx ring, and a
665 * variable number of rows depending on the number of queues supported.
666 **/
667static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
668 int index, int offset)
669{
670 u32 ivar = array_rd32(E1000_IVAR0, index);
671
672 /* clear any bits that are currently set */
673 ivar &= ~((u32)0xFF << offset);
674
675 /* write vector and valid bit */
676 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
677
678 array_wr32(E1000_IVAR0, index, ivar);
679}
680
9d5c8243 681#define IGB_N0_QUEUE -1
047e0030 682static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 683{
047e0030 684 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 685 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 686 int rx_queue = IGB_N0_QUEUE;
687 int tx_queue = IGB_N0_QUEUE;
4be000c8 688 u32 msixbm = 0;
047e0030 689
0ba82994
AD		 690 if (q_vector->rx.ring)
691 rx_queue = q_vector->rx.ring->reg_idx;
692 if (q_vector->tx.ring)
693 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 694
695 switch (hw->mac.type) {
696 case e1000_82575:
9d5c8243
AK		 697 /* The 82575 assigns vectors using a bitmask, which matches the
698 bitmask for the EICR/EIMS/EIMC registers. To assign one
699 or more queues to a vector, we write the appropriate bits
700 into the MSIXBM register for that vector. */
047e0030 701 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 702 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 703 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 704 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 705 if (!adapter->msix_entries && msix_vector == 0)
706 msixbm |= E1000_EIMS_OTHER;
9d5c8243 707 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 708 q_vector->eims_value = msixbm;
2d064c06
AD		 709 break;
710 case e1000_82576:
4be000c8
AD		 711 /*
712 * 82576 uses a table that essentially consists of 2 columns
713 * with 8 rows. The ordering is column-major so we use the
714 * lower 3 bits as the row index, and the 4th bit as the
715 * column offset.
716 */
717 if (rx_queue > IGB_N0_QUEUE)
718 igb_write_ivar(hw, msix_vector,
719 rx_queue & 0x7,
720 (rx_queue & 0x8) << 1);
721 if (tx_queue > IGB_N0_QUEUE)
722 igb_write_ivar(hw, msix_vector,
723 tx_queue & 0x7,
724 ((tx_queue & 0x8) << 1) + 8);
047e0030 725 q_vector->eims_value = 1 << msix_vector;
2d064c06 726 break;
55cac248 727 case e1000_82580:
d2ba2ed8 728 case e1000_i350:
f96a8a0b
CW		 729 case e1000_i210:
730 case e1000_i211:
4be000c8
AD		 731 /*
732 * On 82580 and newer adapters the scheme is similar to 82576
733 * however instead of ordering column-major we have things
734 * ordered row-major. So we traverse the table by using
735 * bit 0 as the column offset, and the remaining bits as the
736 * row index.
737 */
738 if (rx_queue > IGB_N0_QUEUE)
739 igb_write_ivar(hw, msix_vector,
740 rx_queue >> 1,
741 (rx_queue & 0x1) << 4);
742 if (tx_queue > IGB_N0_QUEUE)
743 igb_write_ivar(hw, msix_vector,
744 tx_queue >> 1,
745 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 746 q_vector->eims_value = 1 << msix_vector;
747 break;
2d064c06
AD		 748 default:
749 BUG();
750 break;
751 }
26b39276
AD		 752
753 /* add q_vector eims value to global eims_enable_mask */
754 adapter->eims_enable_mask |= q_vector->eims_value;
755
756 /* configure q_vector to set itr on first interrupt */
757 q_vector->set_itr = 1;
9d5c8243
AK		 758}
759
760/**
761 * igb_configure_msix - Configure MSI-X hardware
762 *
763 * igb_configure_msix sets up the hardware to properly
764 * generate MSI-X interrupts.
765 **/
766static void igb_configure_msix(struct igb_adapter *adapter)
767{
768 u32 tmp;
769 int i, vector = 0;
770 struct e1000_hw *hw = &adapter->hw;
771
772 adapter->eims_enable_mask = 0;
9d5c8243
AK		 773
774 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 775 switch (hw->mac.type) {
776 case e1000_82575:
9d5c8243
AK		 777 tmp = rd32(E1000_CTRL_EXT);
778 /* enable MSI-X PBA support*/
779 tmp |= E1000_CTRL_EXT_PBA_CLR;
780
781 /* Auto-Mask interrupts upon ICR read. */
782 tmp |= E1000_CTRL_EXT_EIAME;
783 tmp |= E1000_CTRL_EXT_IRCA;
784
785 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 786
787 /* enable msix_other interrupt */
788 array_wr32(E1000_MSIXBM(0), vector++,
789 E1000_EIMS_OTHER);
844290e5 790 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 791
2d064c06
AD		 792 break;
793
794 case e1000_82576:
55cac248 795 case e1000_82580:
d2ba2ed8 796 case e1000_i350:
f96a8a0b
CW		 797 case e1000_i210:
798 case e1000_i211:
047e0030
AD		 799 /* Turn on MSI-X capability first, or our settings
800 * won't stick. And it will take days to debug. */
801 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
802 E1000_GPIE_PBA | E1000_GPIE_EIAME |
803 E1000_GPIE_NSICR);
804
805 /* enable msix_other interrupt */
806 adapter->eims_other = 1 << vector;
2d064c06 807 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 808
047e0030 809 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 810 break;
811 default:
812 /* do nothing, since nothing else supports MSI-X */
813 break;
814 } /* switch (hw->mac.type) */
047e0030
AD		 815
816 adapter->eims_enable_mask |= adapter->eims_other;
817
26b39276
AD		 818 for (i = 0; i < adapter->num_q_vectors; i++)
819 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 820
9d5c8243
AK		 821 wrfl();
822}
823
824/**
825 * igb_request_msix - Initialize MSI-X interrupts
826 *
827 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
828 * kernel.
829 **/
830static int igb_request_msix(struct igb_adapter *adapter)
831{
832 struct net_device *netdev = adapter->netdev;
047e0030 833 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 834 int i, err = 0, vector = 0;
835
047e0030 836 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 837 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 838 if (err)
839 goto out;
840 vector++;
841
842 for (i = 0; i < adapter->num_q_vectors; i++) {
843 struct igb_q_vector *q_vector = adapter->q_vector[i];
844
845 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
846
0ba82994 847 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 848 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 849 q_vector->rx.ring->queue_index);
850 else if (q_vector->tx.ring)
047e0030 851 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 852 q_vector->tx.ring->queue_index);
853 else if (q_vector->rx.ring)
047e0030 854 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 855 q_vector->rx.ring->queue_index);
9d5c8243 856 else
047e0030
AD		 857 sprintf(q_vector->name, "%s-unused", netdev->name);
858
9d5c8243 859 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 860 igb_msix_ring, 0, q_vector->name,
047e0030 861 q_vector);
9d5c8243
AK		 862 if (err)
863 goto out;
9d5c8243
AK		 864 vector++;
865 }
866
9d5c8243
AK		 867 igb_configure_msix(adapter);
868 return 0;
869out:
870 return err;
871}
872
873static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
874{
875 if (adapter->msix_entries) {
876 pci_disable_msix(adapter->pdev);
877 kfree(adapter->msix_entries);
878 adapter->msix_entries = NULL;
047e0030 879 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 880 pci_disable_msi(adapter->pdev);
047e0030 881 }
9d5c8243
AK		 882}
883
5536d210
AD		 884/**
885 * igb_free_q_vector - Free memory allocated for specific interrupt vector
886 * @adapter: board private structure to initialize
887 * @v_idx: Index of vector to be freed
888 *
889 * This function frees the memory allocated to the q_vector. In addition if
890 * NAPI is enabled it will delete any references to the NAPI struct prior
891 * to freeing the q_vector.
892 **/
893static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
894{
895 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
896
897 if (q_vector->tx.ring)
898 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
899
900 if (q_vector->rx.ring)
901 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
902
903 adapter->q_vector[v_idx] = NULL;
904 netif_napi_del(&q_vector->napi);
905
906 /*
907 * ixgbe_get_stats64() might access the rings on this vector,
908 * we must wait a grace period before freeing it.
909 */
910 kfree_rcu(q_vector, rcu);
911}
912
047e0030
AD		 913/**
914 * igb_free_q_vectors - Free memory allocated for interrupt vectors
915 * @adapter: board private structure to initialize
916 *
917 * This function frees the memory allocated to the q_vectors. In addition if
918 * NAPI is enabled it will delete any references to the NAPI struct prior
919 * to freeing the q_vector.
920 **/
921static void igb_free_q_vectors(struct igb_adapter *adapter)
922{
5536d210
AD		 923 int v_idx = adapter->num_q_vectors;
924
925 adapter->num_tx_queues = 0;
926 adapter->num_rx_queues = 0;
047e0030 927 adapter->num_q_vectors = 0;
5536d210
AD		 928
929 while (v_idx--)
930 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 931}
932
933/**
934 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
935 *
936 * This function resets the device so that it has 0 rx queues, tx queues, and
937 * MSI-X interrupts allocated.
938 */
939static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
940{
047e0030
AD		 941 igb_free_q_vectors(adapter);
942 igb_reset_interrupt_capability(adapter);
943}
9d5c8243
AK		 944
945/**
946 * igb_set_interrupt_capability - set MSI or MSI-X if supported
947 *
948 * Attempt to configure interrupts using the best available
949 * capabilities of the hardware and kernel.
950 **/
0c2cc02e 951static void igb_set_interrupt_capability(struct igb_adapter *adapter)
9d5c8243
AK		 952{
953 int err;
954 int numvecs, i;
955
83b7180d 956 /* Number of supported queues. */
a99955fc 957 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 958 if (adapter->vfs_allocated_count)
959 adapter->num_tx_queues = 1;
960 else
961 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 962
047e0030
AD		 963 /* start with one vector for every rx queue */
964 numvecs = adapter->num_rx_queues;
965
3ad2f3fb 966 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 967 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
968 numvecs += adapter->num_tx_queues;
047e0030
AD		 969
970 /* store the number of vectors reserved for queues */
971 adapter->num_q_vectors = numvecs;
972
973 /* add 1 vector for link status interrupts */
974 numvecs++;
9d5c8243
AK		 975 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
976 GFP_KERNEL);
f96a8a0b 977
9d5c8243
AK		 978 if (!adapter->msix_entries)
979 goto msi_only;
980
981 for (i = 0; i < numvecs; i++)
982 adapter->msix_entries[i].entry = i;
983
984 err = pci_enable_msix(adapter->pdev,
985 adapter->msix_entries,
986 numvecs);
987 if (err == 0)
0c2cc02e 988 return;
9d5c8243
AK		 989
990 igb_reset_interrupt_capability(adapter);
991
992 /* If we can't do MSI-X, try MSI */
993msi_only:
2a3abf6d
AD		 994#ifdef CONFIG_PCI_IOV
995 /* disable SR-IOV for non MSI-X configurations */
996 if (adapter->vf_data) {
997 struct e1000_hw *hw = &adapter->hw;
998 /* disable iov and allow time for transactions to clear */
999 pci_disable_sriov(adapter->pdev);
1000 msleep(500);
1001
1002 kfree(adapter->vf_data);
1003 adapter->vf_data = NULL;
1004 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1005 wrfl();
2a3abf6d
AD		 1006 msleep(100);
1007 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1008 }
1009#endif
4fc82adf 1010 adapter->vfs_allocated_count = 0;
a99955fc 1011 adapter->rss_queues = 1;
4fc82adf 1012 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1013 adapter->num_rx_queues = 1;
661086df 1014 adapter->num_tx_queues = 1;
047e0030 1015 adapter->num_q_vectors = 1;
9d5c8243 1016 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1017 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1018}
1019
5536d210
AD		 1020static void igb_add_ring(struct igb_ring *ring,
1021 struct igb_ring_container *head)
1022{
1023 head->ring = ring;
1024 head->count++;
1025}
1026
047e0030 1027/**
5536d210 1028 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1029 * @adapter: board private structure to initialize
5536d210
AD		 1030 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1031 * @v_idx: index of vector in adapter struct
1032 * @txr_count: total number of Tx rings to allocate
1033 * @txr_idx: index of first Tx ring to allocate
1034 * @rxr_count: total number of Rx rings to allocate
1035 * @rxr_idx: index of first Rx ring to allocate
047e0030 1036 *
5536d210 1037 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1038 **/
5536d210
AD		 1039static int igb_alloc_q_vector(struct igb_adapter *adapter,
1040 int v_count, int v_idx,
1041 int txr_count, int txr_idx,
1042 int rxr_count, int rxr_idx)
047e0030
AD		 1043{
1044 struct igb_q_vector *q_vector;
5536d210
AD		 1045 struct igb_ring *ring;
1046 int ring_count, size;
047e0030 1047
5536d210
AD		 1048 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1049 if (txr_count > 1 || rxr_count > 1)
1050 return -ENOMEM;
1051
1052 ring_count = txr_count + rxr_count;
1053 size = sizeof(struct igb_q_vector) +
1054 (sizeof(struct igb_ring) * ring_count);
1055
1056 /* allocate q_vector and rings */
1057 q_vector = kzalloc(size, GFP_KERNEL);
1058 if (!q_vector)
1059 return -ENOMEM;
1060
1061 /* initialize NAPI */
1062 netif_napi_add(adapter->netdev, &q_vector->napi,
1063 igb_poll, 64);
1064
1065 /* tie q_vector and adapter together */
1066 adapter->q_vector[v_idx] = q_vector;
1067 q_vector->adapter = adapter;
1068
1069 /* initialize work limits */
1070 q_vector->tx.work_limit = adapter->tx_work_limit;
1071
1072 /* initialize ITR configuration */
1073 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1074 q_vector->itr_val = IGB_START_ITR;
1075
1076 /* initialize pointer to rings */
1077 ring = q_vector->ring;
1078
1079 if (txr_count) {
1080 /* assign generic ring traits */
1081 ring->dev = &adapter->pdev->dev;
1082 ring->netdev = adapter->netdev;
1083
1084 /* configure backlink on ring */
1085 ring->q_vector = q_vector;
1086
1087 /* update q_vector Tx values */
1088 igb_add_ring(ring, &q_vector->tx);
1089
1090 /* For 82575, context index must be unique per ring. */
1091 if (adapter->hw.mac.type == e1000_82575)
1092 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1093
1094 /* apply Tx specific ring traits */
1095 ring->count = adapter->tx_ring_count;
1096 ring->queue_index = txr_idx;
1097
1098 /* assign ring to adapter */
1099 adapter->tx_ring[txr_idx] = ring;
1100
1101 /* push pointer to next ring */
1102 ring++;
047e0030 1103 }
81c2fc22 1104
5536d210
AD		 1105 if (rxr_count) {
1106 /* assign generic ring traits */
1107 ring->dev = &adapter->pdev->dev;
1108 ring->netdev = adapter->netdev;
047e0030 1109
5536d210
AD		 1110 /* configure backlink on ring */
1111 ring->q_vector = q_vector;
047e0030 1112
5536d210
AD		 1113 /* update q_vector Rx values */
1114 igb_add_ring(ring, &q_vector->rx);
047e0030 1115
5536d210
AD		 1116 /* set flag indicating ring supports SCTP checksum offload */
1117 if (adapter->hw.mac.type >= e1000_82576)
1118 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1119
5536d210
AD		 1120 /*
1121 * On i350, i210, and i211, loopback VLAN packets
1122 * have the tag byte-swapped.
1123 * */
1124 if (adapter->hw.mac.type >= e1000_i350)
1125 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1126
5536d210
AD		 1127 /* apply Rx specific ring traits */
1128 ring->count = adapter->rx_ring_count;
1129 ring->queue_index = rxr_idx;
1130
1131 /* assign ring to adapter */
1132 adapter->rx_ring[rxr_idx] = ring;
1133 }
1134
1135 return 0;
047e0030
AD		 1136}
1137
5536d210 1138
047e0030 1139/**
5536d210
AD		 1140 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1141 * @adapter: board private structure to initialize
047e0030 1142 *
5536d210
AD		 1143 * We allocate one q_vector per queue interrupt. If allocation fails we
1144 * return -ENOMEM.
047e0030 1145 **/
5536d210 1146static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1147{
5536d210
AD		 1148 int q_vectors = adapter->num_q_vectors;
1149 int rxr_remaining = adapter->num_rx_queues;
1150 int txr_remaining = adapter->num_tx_queues;
1151 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1152 int err;
047e0030 1153
5536d210
AD		 1154 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1155 for (; rxr_remaining; v_idx++) {
1156 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1157 0, 0, 1, rxr_idx);
047e0030 1158
5536d210
AD		 1159 if (err)
1160 goto err_out;
1161
1162 /* update counts and index */
1163 rxr_remaining--;
1164 rxr_idx++;
047e0030 1165 }
047e0030 1166 }
5536d210
AD		 1167
1168 for (; v_idx < q_vectors; v_idx++) {
1169 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1170 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1171 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1172 tqpv, txr_idx, rqpv, rxr_idx);
1173
1174 if (err)
1175 goto err_out;
1176
1177 /* update counts and index */
1178 rxr_remaining -= rqpv;
1179 txr_remaining -= tqpv;
1180 rxr_idx++;
1181 txr_idx++;
1182 }
1183
047e0030 1184 return 0;
5536d210
AD		 1185
1186err_out:
1187 adapter->num_tx_queues = 0;
1188 adapter->num_rx_queues = 0;
1189 adapter->num_q_vectors = 0;
1190
1191 while (v_idx--)
1192 igb_free_q_vector(adapter, v_idx);
1193
1194 return -ENOMEM;
047e0030
AD		 1195}
1196
1197/**
1198 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1199 *
1200 * This function initializes the interrupts and allocates all of the queues.
1201 **/
1202static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1203{
1204 struct pci_dev *pdev = adapter->pdev;
1205 int err;
1206
0c2cc02e 1207 igb_set_interrupt_capability(adapter);
047e0030
AD		 1208
1209 err = igb_alloc_q_vectors(adapter);
1210 if (err) {
1211 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1212 goto err_alloc_q_vectors;
1213 }
1214
5536d210 1215 igb_cache_ring_register(adapter);
047e0030
AD		 1216
1217 return 0;
5536d210 1218
047e0030
AD		 1219err_alloc_q_vectors:
1220 igb_reset_interrupt_capability(adapter);
1221 return err;
1222}
1223
9d5c8243
AK		 1224/**
1225 * igb_request_irq - initialize interrupts
1226 *
1227 * Attempts to configure interrupts using the best available
1228 * capabilities of the hardware and kernel.
1229 **/
1230static int igb_request_irq(struct igb_adapter *adapter)
1231{
1232 struct net_device *netdev = adapter->netdev;
047e0030 1233 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1234 int err = 0;
1235
1236 if (adapter->msix_entries) {
1237 err = igb_request_msix(adapter);
844290e5 1238 if (!err)
9d5c8243 1239 goto request_done;
9d5c8243 1240 /* fall back to MSI */
5536d210
AD		 1241 igb_free_all_tx_resources(adapter);
1242 igb_free_all_rx_resources(adapter);
047e0030 1243 igb_clear_interrupt_scheme(adapter);
c74d588e 1244 if (!pci_enable_msi(pdev))
7dfc16fa 1245 adapter->flags |= IGB_FLAG_HAS_MSI;
047e0030 1246 adapter->num_tx_queues = 1;
9d5c8243 1247 adapter->num_rx_queues = 1;
047e0030
AD		 1248 adapter->num_q_vectors = 1;
1249 err = igb_alloc_q_vectors(adapter);
1250 if (err) {
1251 dev_err(&pdev->dev,
1252 "Unable to allocate memory for vectors\n");
1253 goto request_done;
1254 }
047e0030
AD		 1255 igb_setup_all_tx_resources(adapter);
1256 igb_setup_all_rx_resources(adapter);
9d5c8243 1257 }
844290e5 1258
c74d588e
AD		 1259 igb_assign_vector(adapter->q_vector[0], 0);
1260
7dfc16fa 1261 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1262 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1263 netdev->name, adapter);
9d5c8243
AK		 1264 if (!err)
1265 goto request_done;
047e0030 1266
9d5c8243
AK		 1267 /* fall back to legacy interrupts */
1268 igb_reset_interrupt_capability(adapter);
7dfc16fa 1269 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1270 }
1271
c74d588e 1272 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1273 netdev->name, adapter);
9d5c8243 1274
6cb5e577 1275 if (err)
c74d588e 1276 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1277 err);
9d5c8243
AK		 1278
1279request_done:
1280 return err;
1281}
1282
1283static void igb_free_irq(struct igb_adapter *adapter)
1284{
9d5c8243
AK		 1285 if (adapter->msix_entries) {
1286 int vector = 0, i;
1287
047e0030 1288 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1289
0d1ae7f4 1290 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1291 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1292 adapter->q_vector[i]);
047e0030
AD		 1293 } else {
1294 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1295 }
9d5c8243
AK		 1296}
1297
1298/**
1299 * igb_irq_disable - Mask off interrupt generation on the NIC
1300 * @adapter: board private structure
1301 **/
1302static void igb_irq_disable(struct igb_adapter *adapter)
1303{
1304 struct e1000_hw *hw = &adapter->hw;
1305
25568a53
AD		 1306 /*
1307 * we need to be careful when disabling interrupts. The VFs are also
1308 * mapped into these registers and so clearing the bits can cause
1309 * issues on the VF drivers so we only need to clear what we set
1310 */
9d5c8243 1311 if (adapter->msix_entries) {
2dfd1212
AD		 1312 u32 regval = rd32(E1000_EIAM);
1313 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1314 wr32(E1000_EIMC, adapter->eims_enable_mask);
1315 regval = rd32(E1000_EIAC);
1316 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1317 }
844290e5
PW		 1318
1319 wr32(E1000_IAM, 0);
9d5c8243
AK		 1320 wr32(E1000_IMC, ~0);
1321 wrfl();
81a61859
ET		 1322 if (adapter->msix_entries) {
1323 int i;
1324 for (i = 0; i < adapter->num_q_vectors; i++)
1325 synchronize_irq(adapter->msix_entries[i].vector);
1326 } else {
1327 synchronize_irq(adapter->pdev->irq);
1328 }
9d5c8243
AK		 1329}
1330
1331/**
1332 * igb_irq_enable - Enable default interrupt generation settings
1333 * @adapter: board private structure
1334 **/
1335static void igb_irq_enable(struct igb_adapter *adapter)
1336{
1337 struct e1000_hw *hw = &adapter->hw;
1338
1339 if (adapter->msix_entries) {
06218a8d 1340 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1341 u32 regval = rd32(E1000_EIAC);
1342 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1343 regval = rd32(E1000_EIAM);
1344 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1345 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1346 if (adapter->vfs_allocated_count) {
4ae196df 1347 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1348 ims |= E1000_IMS_VMMB;
1349 }
1350 wr32(E1000_IMS, ims);
844290e5 1351 } else {
55cac248
AD		 1352 wr32(E1000_IMS, IMS_ENABLE_MASK |
1353 E1000_IMS_DRSTA);
1354 wr32(E1000_IAM, IMS_ENABLE_MASK |
1355 E1000_IMS_DRSTA);
844290e5 1356 }
9d5c8243
AK		 1357}
1358
1359static void igb_update_mng_vlan(struct igb_adapter *adapter)
1360{
51466239 1361 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1362 u16 vid = adapter->hw.mng_cookie.vlan_id;
1363 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1364
1365 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1366 /* add VID to filter table */
1367 igb_vfta_set(hw, vid, true);
1368 adapter->mng_vlan_id = vid;
1369 } else {
1370 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1371 }
1372
1373 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1374 (vid != old_vid) &&
b2cb09b1 1375 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1376 /* remove VID from filter table */
1377 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1378 }
1379}
1380
1381/**
1382 * igb_release_hw_control - release control of the h/w to f/w
1383 * @adapter: address of board private structure
1384 *
1385 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1386 * For ASF and Pass Through versions of f/w this means that the
1387 * driver is no longer loaded.
1388 *
1389 **/
1390static void igb_release_hw_control(struct igb_adapter *adapter)
1391{
1392 struct e1000_hw *hw = &adapter->hw;
1393 u32 ctrl_ext;
1394
1395 /* Let firmware take over control of h/w */
1396 ctrl_ext = rd32(E1000_CTRL_EXT);
1397 wr32(E1000_CTRL_EXT,
1398 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1399}
1400
9d5c8243
AK		 1401/**
1402 * igb_get_hw_control - get control of the h/w from f/w
1403 * @adapter: address of board private structure
1404 *
1405 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1406 * For ASF and Pass Through versions of f/w this means that
1407 * the driver is loaded.
1408 *
1409 **/
1410static void igb_get_hw_control(struct igb_adapter *adapter)
1411{
1412 struct e1000_hw *hw = &adapter->hw;
1413 u32 ctrl_ext;
1414
1415 /* Let firmware know the driver has taken over */
1416 ctrl_ext = rd32(E1000_CTRL_EXT);
1417 wr32(E1000_CTRL_EXT,
1418 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1419}
1420
9d5c8243
AK		 1421/**
1422 * igb_configure - configure the hardware for RX and TX
1423 * @adapter: private board structure
1424 **/
1425static void igb_configure(struct igb_adapter *adapter)
1426{
1427 struct net_device *netdev = adapter->netdev;
1428 int i;
1429
1430 igb_get_hw_control(adapter);
ff41f8dc 1431 igb_set_rx_mode(netdev);
9d5c8243
AK		 1432
1433 igb_restore_vlan(adapter);
9d5c8243 1434
85b430b4 1435 igb_setup_tctl(adapter);
06cf2666 1436 igb_setup_mrqc(adapter);
9d5c8243 1437 igb_setup_rctl(adapter);
85b430b4
AD		 1438
1439 igb_configure_tx(adapter);
9d5c8243 1440 igb_configure_rx(adapter);
662d7205
AD		 1441
1442 igb_rx_fifo_flush_82575(&adapter->hw);
1443
c493ea45 1444 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1445 * at least 1 descriptor unused to make sure
1446 * next_to_use != next_to_clean */
1447 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1448 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1449 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1450 }
9d5c8243
AK		 1451}
1452
88a268c1
NN		 1453/**
1454 * igb_power_up_link - Power up the phy/serdes link
1455 * @adapter: address of board private structure
1456 **/
1457void igb_power_up_link(struct igb_adapter *adapter)
1458{
76886596
AA		 1459 igb_reset_phy(&adapter->hw);
1460
88a268c1
NN		 1461 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1462 igb_power_up_phy_copper(&adapter->hw);
1463 else
1464 igb_power_up_serdes_link_82575(&adapter->hw);
1465}
1466
1467/**
1468 * igb_power_down_link - Power down the phy/serdes link
1469 * @adapter: address of board private structure
1470 */
1471static void igb_power_down_link(struct igb_adapter *adapter)
1472{
1473 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1474 igb_power_down_phy_copper_82575(&adapter->hw);
1475 else
1476 igb_shutdown_serdes_link_82575(&adapter->hw);
1477}
9d5c8243
AK		 1478
1479/**
1480 * igb_up - Open the interface and prepare it to handle traffic
1481 * @adapter: board private structure
1482 **/
9d5c8243
AK		 1483int igb_up(struct igb_adapter *adapter)
1484{
1485 struct e1000_hw *hw = &adapter->hw;
1486 int i;
1487
1488 /* hardware has been reset, we need to reload some things */
1489 igb_configure(adapter);
1490
1491 clear_bit(__IGB_DOWN, &adapter->state);
1492
0d1ae7f4
AD		 1493 for (i = 0; i < adapter->num_q_vectors; i++)
1494 napi_enable(&(adapter->q_vector[i]->napi));
1495
844290e5 1496 if (adapter->msix_entries)
9d5c8243 1497 igb_configure_msix(adapter);
feeb2721
AD		 1498 else
1499 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1500
1501 /* Clear any pending interrupts. */
1502 rd32(E1000_ICR);
1503 igb_irq_enable(adapter);
1504
d4960307
AD		 1505 /* notify VFs that reset has been completed */
1506 if (adapter->vfs_allocated_count) {
1507 u32 reg_data = rd32(E1000_CTRL_EXT);
1508 reg_data |= E1000_CTRL_EXT_PFRSTD;
1509 wr32(E1000_CTRL_EXT, reg_data);
1510 }
1511
4cb9be7a
JB		 1512 netif_tx_start_all_queues(adapter->netdev);
1513
25568a53
AD		 1514 /* start the watchdog. */
1515 hw->mac.get_link_status = 1;
1516 schedule_work(&adapter->watchdog_task);
1517
9d5c8243
AK		 1518 return 0;
1519}
1520
1521void igb_down(struct igb_adapter *adapter)
1522{
9d5c8243 1523 struct net_device *netdev = adapter->netdev;
330a6d6a 1524 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1525 u32 tctl, rctl;
1526 int i;
1527
1528 /* signal that we're down so the interrupt handler does not
1529 * reschedule our watchdog timer */
1530 set_bit(__IGB_DOWN, &adapter->state);
1531
1532 /* disable receives in the hardware */
1533 rctl = rd32(E1000_RCTL);
1534 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1535 /* flush and sleep below */
1536
fd2ea0a7 1537 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1538
1539 /* disable transmits in the hardware */
1540 tctl = rd32(E1000_TCTL);
1541 tctl &= ~E1000_TCTL_EN;
1542 wr32(E1000_TCTL, tctl);
1543 /* flush both disables and wait for them to finish */
1544 wrfl();
1545 msleep(10);
1546
0d1ae7f4
AD		 1547 for (i = 0; i < adapter->num_q_vectors; i++)
1548 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1549
9d5c8243
AK		 1550 igb_irq_disable(adapter);
1551
1552 del_timer_sync(&adapter->watchdog_timer);
1553 del_timer_sync(&adapter->phy_info_timer);
1554
9d5c8243 1555 netif_carrier_off(netdev);
04fe6358
AD		 1556
1557 /* record the stats before reset*/
12dcd86b
ED		 1558 spin_lock(&adapter->stats64_lock);
1559 igb_update_stats(adapter, &adapter->stats64);
1560 spin_unlock(&adapter->stats64_lock);
04fe6358 1561
9d5c8243
AK		 1562 adapter->link_speed = 0;
1563 adapter->link_duplex = 0;
1564
3023682e
JK		 1565 if (!pci_channel_offline(adapter->pdev))
1566 igb_reset(adapter);
9d5c8243
AK		 1567 igb_clean_all_tx_rings(adapter);
1568 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1569#ifdef CONFIG_IGB_DCA
1570
1571 /* since we reset the hardware DCA settings were cleared */
1572 igb_setup_dca(adapter);
1573#endif
9d5c8243
AK		 1574}
1575
1576void igb_reinit_locked(struct igb_adapter *adapter)
1577{
1578 WARN_ON(in_interrupt());
1579 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1580 msleep(1);
1581 igb_down(adapter);
1582 igb_up(adapter);
1583 clear_bit(__IGB_RESETTING, &adapter->state);
1584}
1585
1586void igb_reset(struct igb_adapter *adapter)
1587{
090b1795 1588 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1589 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1590 struct e1000_mac_info *mac = &hw->mac;
1591 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1592 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1593
1594 /* Repartition Pba for greater than 9k mtu
1595 * To take effect CTRL.RST is required.
1596 */
fa4dfae0 1597 switch (mac->type) {
d2ba2ed8 1598 case e1000_i350:
55cac248
AD		 1599 case e1000_82580:
1600 pba = rd32(E1000_RXPBS);
1601 pba = igb_rxpbs_adjust_82580(pba);
1602 break;
fa4dfae0 1603 case e1000_82576:
d249be54
AD		 1604 pba = rd32(E1000_RXPBS);
1605 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1606 break;
1607 case e1000_82575:
f96a8a0b
CW		 1608 case e1000_i210:
1609 case e1000_i211:
fa4dfae0
AD		 1610 default:
1611 pba = E1000_PBA_34K;
1612 break;
2d064c06 1613 }
9d5c8243 1614
2d064c06
AD		 1615 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1616 (mac->type < e1000_82576)) {
9d5c8243
AK		 1617 /* adjust PBA for jumbo frames */
1618 wr32(E1000_PBA, pba);
1619
1620 /* To maintain wire speed transmits, the Tx FIFO should be
1621 * large enough to accommodate two full transmit packets,
1622 * rounded up to the next 1KB and expressed in KB. Likewise,
1623 * the Rx FIFO should be large enough to accommodate at least
1624 * one full receive packet and is similarly rounded up and
1625 * expressed in KB. */
1626 pba = rd32(E1000_PBA);
1627 /* upper 16 bits has Tx packet buffer allocation size in KB */
1628 tx_space = pba >> 16;
1629 /* lower 16 bits has Rx packet buffer allocation size in KB */
1630 pba &= 0xffff;
1631 /* the tx fifo also stores 16 bytes of information about the tx
1632 * but don't include ethernet FCS because hardware appends it */
1633 min_tx_space = (adapter->max_frame_size +
85e8d004 1634 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1635 ETH_FCS_LEN) * 2;
1636 min_tx_space = ALIGN(min_tx_space, 1024);
1637 min_tx_space >>= 10;
1638 /* software strips receive CRC, so leave room for it */
1639 min_rx_space = adapter->max_frame_size;
1640 min_rx_space = ALIGN(min_rx_space, 1024);
1641 min_rx_space >>= 10;
1642
1643 /* If current Tx allocation is less than the min Tx FIFO size,
1644 * and the min Tx FIFO size is less than the current Rx FIFO
1645 * allocation, take space away from current Rx allocation */
1646 if (tx_space < min_tx_space &&
1647 ((min_tx_space - tx_space) < pba)) {
1648 pba = pba - (min_tx_space - tx_space);
1649
1650 /* if short on rx space, rx wins and must trump tx
1651 * adjustment */
1652 if (pba < min_rx_space)
1653 pba = min_rx_space;
1654 }
2d064c06 1655 wr32(E1000_PBA, pba);
9d5c8243 1656 }
9d5c8243
AK		 1657
1658 /* flow control settings */
1659 /* The high water mark must be low enough to fit one full frame
1660 * (or the size used for early receive) above it in the Rx FIFO.
1661 * Set it to the lower of:
1662 * - 90% of the Rx FIFO size, or
1663 * - the full Rx FIFO size minus one full frame */
1664 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1665 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1666
d48507fe 1667 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1668 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1669 fc->pause_time = 0xFFFF;
1670 fc->send_xon = 1;
0cce119a 1671 fc->current_mode = fc->requested_mode;
9d5c8243 1672
4ae196df
AD		 1673 /* disable receive for all VFs and wait one second */
1674 if (adapter->vfs_allocated_count) {
1675 int i;
1676 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1677 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1678
1679 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1680 igb_ping_all_vfs(adapter);
4ae196df
AD		 1681
1682 /* disable transmits and receives */
1683 wr32(E1000_VFRE, 0);
1684 wr32(E1000_VFTE, 0);
1685 }
1686
9d5c8243 1687 /* Allow time for pending master requests to run */
330a6d6a 1688 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1689 wr32(E1000_WUC, 0);
1690
330a6d6a 1691 if (hw->mac.ops.init_hw(hw))
090b1795 1692 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1693
a27416bb
MV		 1694 /*
1695 * Flow control settings reset on hardware reset, so guarantee flow
1696 * control is off when forcing speed.
1697 */
1698 if (!hw->mac.autoneg)
1699 igb_force_mac_fc(hw);
1700
b6e0c419 1701 igb_init_dmac(adapter, pba);
88a268c1
NN		 1702 if (!netif_running(adapter->netdev))
1703 igb_power_down_link(adapter);
1704
9d5c8243
AK		 1705 igb_update_mng_vlan(adapter);
1706
1707 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1708 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1709
1f6e8178
MV		 1710 /* Re-enable PTP, where applicable. */
1711 igb_ptp_reset(adapter);
1f6e8178 1712
330a6d6a 1713 igb_get_phy_info(hw);
9d5c8243
AK		 1714}
1715
c8f44aff
MM		 1716static netdev_features_t igb_fix_features(struct net_device *netdev,
1717 netdev_features_t features)
b2cb09b1
JP		 1718{
1719 /*
1720 * Since there is no support for separate rx/tx vlan accel
1721 * enable/disable make sure tx flag is always in same state as rx.
1722 */
1723 if (features & NETIF_F_HW_VLAN_RX)
1724 features |= NETIF_F_HW_VLAN_TX;
1725 else
1726 features &= ~NETIF_F_HW_VLAN_TX;
1727
1728 return features;
1729}
1730
c8f44aff
MM		 1731static int igb_set_features(struct net_device *netdev,
1732 netdev_features_t features)
ac52caa3 1733{
c8f44aff 1734 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1735 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1736
b2cb09b1
JP		 1737 if (changed & NETIF_F_HW_VLAN_RX)
1738 igb_vlan_mode(netdev, features);
1739
89eaefb6
BG		 1740 if (!(changed & NETIF_F_RXALL))
1741 return 0;
1742
1743 netdev->features = features;
1744
1745 if (netif_running(netdev))
1746 igb_reinit_locked(adapter);
1747 else
1748 igb_reset(adapter);
1749
ac52caa3
MM		 1750 return 0;
1751}
1752
2e5c6922 1753static const struct net_device_ops igb_netdev_ops = {
559e9c49 1754 .ndo_open = igb_open,
2e5c6922 1755 .ndo_stop = igb_close,
cd392f5c 1756 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1757 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1758 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1759 .ndo_set_mac_address = igb_set_mac,
1760 .ndo_change_mtu = igb_change_mtu,
1761 .ndo_do_ioctl = igb_ioctl,
1762 .ndo_tx_timeout = igb_tx_timeout,
1763 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1764 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1765 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1766 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1767 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1768 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1769 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1770#ifdef CONFIG_NET_POLL_CONTROLLER
1771 .ndo_poll_controller = igb_netpoll,
1772#endif
b2cb09b1
JP		 1773 .ndo_fix_features = igb_fix_features,
1774 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1775};
1776
d67974f0
CW		 1777/**
1778 * igb_set_fw_version - Configure version string for ethtool
1779 * @adapter: adapter struct
1780 *
1781 **/
1782void igb_set_fw_version(struct igb_adapter *adapter)
1783{
1784 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1785 struct e1000_fw_version fw;
1786
1787 igb_get_fw_version(hw, &fw);
1788
1789 switch (hw->mac.type) {
1790 case e1000_i211:
d67974f0 1791 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1792 "%2d.%2d-%d",
1793 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1794 break;
1795
1796 default:
1797 /* if option is rom valid, display its version too */
1798 if (fw.or_valid) {
1799 snprintf(adapter->fw_version,
1800 sizeof(adapter->fw_version),
1801 "%d.%d, 0x%08x, %d.%d.%d",
1802 fw.eep_major, fw.eep_minor, fw.etrack_id,
1803 fw.or_major, fw.or_build, fw.or_patch);
1804 /* no option rom */
1805 } else {
1806 snprintf(adapter->fw_version,
1807 sizeof(adapter->fw_version),
1808 "%d.%d, 0x%08x",
1809 fw.eep_major, fw.eep_minor, fw.etrack_id);
1810 }
1811 break;
d67974f0 1812 }
d67974f0
CW		 1813 return;
1814}
1815
9d5c8243
AK		 1816/**
1817 * igb_probe - Device Initialization Routine
1818 * @pdev: PCI device information struct
1819 * @ent: entry in igb_pci_tbl
1820 *
1821 * Returns 0 on success, negative on failure
1822 *
1823 * igb_probe initializes an adapter identified by a pci_dev structure.
1824 * The OS initialization, configuring of the adapter private structure,
1825 * and a hardware reset occur.
1826 **/
1827static int __devinit igb_probe(struct pci_dev *pdev,
1828 const struct pci_device_id *ent)
1829{
1830 struct net_device *netdev;
1831 struct igb_adapter *adapter;
1832 struct e1000_hw *hw;
4337e993 1833 u16 eeprom_data = 0;
9835fd73 1834 s32 ret_val;
4337e993 1835 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1836 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1837 unsigned long mmio_start, mmio_len;
2d6a5e95 1838 int err, pci_using_dac;
9835fd73 1839 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1840
bded64a7
AG		 1841 /* Catch broken hardware that put the wrong VF device ID in
1842 * the PCIe SR-IOV capability.
1843 */
1844 if (pdev->is_virtfn) {
1845 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1846 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1847 return -EINVAL;
1848 }
1849
aed5dec3 1850 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1851 if (err)
1852 return err;
1853
1854 pci_using_dac = 0;
59d71989 1855 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1856 if (!err) {
59d71989 1857 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1858 if (!err)
1859 pci_using_dac = 1;
1860 } else {
59d71989 1861 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1862 if (err) {
59d71989 1863 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1864 if (err) {
1865 dev_err(&pdev->dev, "No usable DMA "
1866 "configuration, aborting\n");
1867 goto err_dma;
1868 }
1869 }
1870 }
1871
aed5dec3
AD		 1872 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1873 IORESOURCE_MEM),
1874 igb_driver_name);
9d5c8243
AK		 1875 if (err)
1876 goto err_pci_reg;
1877
19d5afd4 1878 pci_enable_pcie_error_reporting(pdev);
40a914fa 1879
9d5c8243 1880 pci_set_master(pdev);
c682fc23 1881 pci_save_state(pdev);
9d5c8243
AK		 1882
1883 err = -ENOMEM;
1bfaf07b 1884 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 1885 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1886 if (!netdev)
1887 goto err_alloc_etherdev;
1888
1889 SET_NETDEV_DEV(netdev, &pdev->dev);
1890
1891 pci_set_drvdata(pdev, netdev);
1892 adapter = netdev_priv(netdev);
1893 adapter->netdev = netdev;
1894 adapter->pdev = pdev;
1895 hw = &adapter->hw;
1896 hw->back = adapter;
b3f4d599 1897 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 1898
1899 mmio_start = pci_resource_start(pdev, 0);
1900 mmio_len = pci_resource_len(pdev, 0);
1901
1902 err = -EIO;
28b0759c
AD		 1903 hw->hw_addr = ioremap(mmio_start, mmio_len);
1904 if (!hw->hw_addr)
9d5c8243
AK		 1905 goto err_ioremap;
1906
2e5c6922 1907 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1908 igb_set_ethtool_ops(netdev);
9d5c8243 1909 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1910
1911 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1912
1913 netdev->mem_start = mmio_start;
1914 netdev->mem_end = mmio_start + mmio_len;
1915
9d5c8243
AK		 1916 /* PCI config space info */
1917 hw->vendor_id = pdev->vendor;
1918 hw->device_id = pdev->device;
1919 hw->revision_id = pdev->revision;
1920 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1921 hw->subsystem_device_id = pdev->subsystem_device;
1922
9d5c8243
AK		 1923 /* Copy the default MAC, PHY and NVM function pointers */
1924 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1925 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1926 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1927 /* Initialize skew-specific constants */
1928 err = ei->get_invariants(hw);
1929 if (err)
450c87c8 1930 goto err_sw_init;
9d5c8243 1931
450c87c8 1932 /* setup the private structure */
9d5c8243
AK		 1933 err = igb_sw_init(adapter);
1934 if (err)
1935 goto err_sw_init;
1936
1937 igb_get_bus_info_pcie(hw);
1938
1939 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1940
1941 /* Copper options */
1942 if (hw->phy.media_type == e1000_media_type_copper) {
1943 hw->phy.mdix = AUTO_ALL_MODES;
1944 hw->phy.disable_polarity_correction = false;
1945 hw->phy.ms_type = e1000_ms_hw_default;
1946 }
1947
1948 if (igb_check_reset_block(hw))
1949 dev_info(&pdev->dev,
1950 "PHY reset is blocked due to SOL/IDER session.\n");
1951
077887c3
AD		 1952 /*
1953 * features is initialized to 0 in allocation, it might have bits
1954 * set by igb_sw_init so we should use an or instead of an
1955 * assignment.
1956 */
1957 netdev->features |= NETIF_F_SG |
1958 NETIF_F_IP_CSUM |
1959 NETIF_F_IPV6_CSUM |
1960 NETIF_F_TSO |
1961 NETIF_F_TSO6 |
1962 NETIF_F_RXHASH |
1963 NETIF_F_RXCSUM |
1964 NETIF_F_HW_VLAN_RX |
1965 NETIF_F_HW_VLAN_TX;
1966
1967 /* copy netdev features into list of user selectable features */
1968 netdev->hw_features |= netdev->features;
89eaefb6 1969 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 1970
1971 /* set this bit last since it cannot be part of hw_features */
1972 netdev->features |= NETIF_F_HW_VLAN_FILTER;
1973
1974 netdev->vlan_features |= NETIF_F_TSO |
1975 NETIF_F_TSO6 |
1976 NETIF_F_IP_CSUM |
1977 NETIF_F_IPV6_CSUM |
1978 NETIF_F_SG;
48f29ffc 1979
6b8f0922
BG		 1980 netdev->priv_flags |= IFF_SUPP_NOFCS;
1981
7b872a55 1982 if (pci_using_dac) {
9d5c8243 1983 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1984 netdev->vlan_features |= NETIF_F_HIGHDMA;
1985 }
9d5c8243 1986
ac52caa3
MM		 1987 if (hw->mac.type >= e1000_82576) {
1988 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 1989 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 1990 }
b9473560 1991
01789349
JP		 1992 netdev->priv_flags |= IFF_UNICAST_FLT;
1993
330a6d6a 1994 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 1995
1996 /* before reading the NVM, reset the controller to put the device in a
1997 * known good starting state */
1998 hw->mac.ops.reset_hw(hw);
1999
f96a8a0b
CW		 2000 /*
2001 * make sure the NVM is good , i211 parts have special NVM that
2002 * doesn't contain a checksum
2003 */
2004 if (hw->mac.type != e1000_i211) {
2005 if (hw->nvm.ops.validate(hw) < 0) {
2006 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2007 err = -EIO;
2008 goto err_eeprom;
2009 }
9d5c8243
AK		 2010 }
2011
2012 /* copy the MAC address out of the NVM */
2013 if (hw->mac.ops.read_mac_addr(hw))
2014 dev_err(&pdev->dev, "NVM Read Error\n");
2015
2016 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2017 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2018
2019 if (!is_valid_ether_addr(netdev->perm_addr)) {
2020 dev_err(&pdev->dev, "Invalid MAC Address\n");
2021 err = -EIO;
2022 goto err_eeprom;
2023 }
2024
d67974f0
CW		 2025 /* get firmware version for ethtool -i */
2026 igb_set_fw_version(adapter);
2027
c061b18d 2028 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2029 (unsigned long) adapter);
c061b18d 2030 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2031 (unsigned long) adapter);
9d5c8243
AK		 2032
2033 INIT_WORK(&adapter->reset_task, igb_reset_task);
2034 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2035
450c87c8 2036 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2037 adapter->fc_autoneg = true;
2038 hw->mac.autoneg = true;
2039 hw->phy.autoneg_advertised = 0x2f;
2040
0cce119a
AD		 2041 hw->fc.requested_mode = e1000_fc_default;
2042 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2043
9d5c8243
AK		 2044 igb_validate_mdi_setting(hw);
2045
63d4a8f9 2046 /* By default, support wake on port A */
a2cf8b6c 2047 if (hw->bus.func == 0)
63d4a8f9
MV		 2048 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2049
2050 /* Check the NVM for wake support on non-port A ports */
2051 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2052 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2053 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2054 &eeprom_data);
a2cf8b6c
AD		 2055 else if (hw->bus.func == 1)
2056 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2057
63d4a8f9
MV		 2058 if (eeprom_data & IGB_EEPROM_APME)
2059 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2060
2061 /* now that we have the eeprom settings, apply the special cases where
2062 * the eeprom may be wrong or the board simply won't support wake on
2063 * lan on a particular port */
2064 switch (pdev->device) {
2065 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2066 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2067 break;
2068 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2069 case E1000_DEV_ID_82576_FIBER:
2070 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2071 /* Wake events only supported on port A for dual fiber
2072 * regardless of eeprom setting */
2073 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2074 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2075 break;
c8ea5ea9 2076 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2077 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2078 /* if quad port adapter, disable WoL on all but port A */
2079 if (global_quad_port_a != 0)
63d4a8f9 2080 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2081 else
2082 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2083 /* Reset for multiple quad port adapters */
2084 if (++global_quad_port_a == 4)
2085 global_quad_port_a = 0;
2086 break;
63d4a8f9
MV		 2087 default:
2088 /* If the device can't wake, don't set software support */
2089 if (!device_can_wakeup(&adapter->pdev->dev))
2090 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2091 }
2092
2093 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2094 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2095 adapter->wol |= E1000_WUFC_MAG;
2096
2097 /* Some vendors want WoL disabled by default, but still supported */
2098 if ((hw->mac.type == e1000_i350) &&
2099 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2100 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2101 adapter->wol = 0;
2102 }
2103
2104 device_set_wakeup_enable(&adapter->pdev->dev,
2105 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2106
2107 /* reset the hardware with the new settings */
2108 igb_reset(adapter);
2109
2110 /* let the f/w know that the h/w is now under the control of the
2111 * driver. */
2112 igb_get_hw_control(adapter);
2113
9d5c8243
AK		 2114 strcpy(netdev->name, "eth%d");
2115 err = register_netdev(netdev);
2116 if (err)
2117 goto err_register;
2118
b168dfc5
JB		 2119 /* carrier off reporting is important to ethtool even BEFORE open */
2120 netif_carrier_off(netdev);
2121
421e02f0 2122#ifdef CONFIG_IGB_DCA
bbd98fe4 2123 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2124 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2125 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2126 igb_setup_dca(adapter);
2127 }
fe4506b6 2128
38c845c7 2129#endif
3c89f6d0 2130
673b8b70 2131 /* do hw tstamp init after resetting */
7ebae817 2132 igb_ptp_init(adapter);
673b8b70 2133
9d5c8243
AK		 2134 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2135 /* print bus type/speed/width info */
7c510e4b 2136 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2137 netdev->name,
559e9c49 2138 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2139 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2140 "unknown"),
59c3de89
AD		 2141 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2142 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2143 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2144 "unknown"),
7c510e4b 2145 netdev->dev_addr);
9d5c8243 2146
9835fd73
CW		 2147 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2148 if (ret_val)
2149 strcpy(part_str, "Unknown");
2150 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2151 dev_info(&pdev->dev,
2152 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2153 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2154 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2155 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2156 switch (hw->mac.type) {
2157 case e1000_i350:
f96a8a0b
CW		 2158 case e1000_i210:
2159 case e1000_i211:
09b068d4
CW		 2160 igb_set_eee_i350(hw);
2161 break;
2162 default:
2163 break;
2164 }
749ab2cd
YZ		 2165
2166 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2167 return 0;
2168
2169err_register:
2170 igb_release_hw_control(adapter);
2171err_eeprom:
2172 if (!igb_check_reset_block(hw))
f5f4cf08 2173 igb_reset_phy(hw);
9d5c8243
AK		 2174
2175 if (hw->flash_address)
2176 iounmap(hw->flash_address);
9d5c8243 2177err_sw_init:
047e0030 2178 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2179 iounmap(hw->hw_addr);
2180err_ioremap:
2181 free_netdev(netdev);
2182err_alloc_etherdev:
559e9c49
AD		 2183 pci_release_selected_regions(pdev,
2184 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2185err_pci_reg:
2186err_dma:
2187 pci_disable_device(pdev);
2188 return err;
2189}
2190
2191/**
2192 * igb_remove - Device Removal Routine
2193 * @pdev: PCI device information struct
2194 *
2195 * igb_remove is called by the PCI subsystem to alert the driver
2196 * that it should release a PCI device. The could be caused by a
2197 * Hot-Plug event, or because the driver is going to be removed from
2198 * memory.
2199 **/
2200static void __devexit igb_remove(struct pci_dev *pdev)
2201{
2202 struct net_device *netdev = pci_get_drvdata(pdev);
2203 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2204 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2205
749ab2cd 2206 pm_runtime_get_noresume(&pdev->dev);
a79f4f88 2207 igb_ptp_stop(adapter);
749ab2cd 2208
760141a5
TH		 2209 /*
2210 * The watchdog timer may be rescheduled, so explicitly
2211 * disable watchdog from being rescheduled.
2212 */
9d5c8243
AK		 2213 set_bit(__IGB_DOWN, &adapter->state);
2214 del_timer_sync(&adapter->watchdog_timer);
2215 del_timer_sync(&adapter->phy_info_timer);
2216
760141a5
TH		 2217 cancel_work_sync(&adapter->reset_task);
2218 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2219
421e02f0 2220#ifdef CONFIG_IGB_DCA
7dfc16fa 2221 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2222 dev_info(&pdev->dev, "DCA disabled\n");
2223 dca_remove_requester(&pdev->dev);
7dfc16fa 2224 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2225 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2226 }
2227#endif
2228
9d5c8243
AK		 2229 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2230 * would have already happened in close and is redundant. */
2231 igb_release_hw_control(adapter);
2232
2233 unregister_netdev(netdev);
2234
047e0030 2235 igb_clear_interrupt_scheme(adapter);
9d5c8243 2236
37680117
AD		 2237#ifdef CONFIG_PCI_IOV
2238 /* reclaim resources allocated to VFs */
2239 if (adapter->vf_data) {
2240 /* disable iov and allow time for transactions to clear */
f557147c
SA		 2241 if (igb_vfs_are_assigned(adapter)) {
2242 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2243 } else {
0224d663
GR		 2244 pci_disable_sriov(pdev);
2245 msleep(500);
0224d663 2246 }
37680117
AD		 2247
2248 kfree(adapter->vf_data);
2249 adapter->vf_data = NULL;
2250 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 2251 wrfl();
37680117
AD		 2252 msleep(100);
2253 dev_info(&pdev->dev, "IOV Disabled\n");
2254 }
2255#endif
559e9c49 2256
28b0759c
AD		 2257 iounmap(hw->hw_addr);
2258 if (hw->flash_address)
2259 iounmap(hw->flash_address);
559e9c49
AD		 2260 pci_release_selected_regions(pdev,
2261 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2262
1128c756 2263 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2264 free_netdev(netdev);
2265
19d5afd4 2266 pci_disable_pcie_error_reporting(pdev);
40a914fa 2267
9d5c8243
AK		 2268 pci_disable_device(pdev);
2269}
2270
a6b623e0
AD		 2271/**
2272 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2273 * @adapter: board private structure to initialize
2274 *
2275 * This function initializes the vf specific data storage and then attempts to
2276 * allocate the VFs. The reason for ordering it this way is because it is much
2277 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2278 * the memory for the VFs.
2279 **/
2280static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2281{
2282#ifdef CONFIG_PCI_IOV
2283 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2284 struct e1000_hw *hw = &adapter->hw;
f557147c 2285 int old_vfs = pci_num_vf(adapter->pdev);
0224d663 2286 int i;
a6b623e0 2287
f96a8a0b
CW		 2288 /* Virtualization features not supported on i210 family. */
2289 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2290 return;
2291
0224d663
GR		 2292 if (old_vfs) {
2293 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2294 "max_vfs setting of %d\n", old_vfs, max_vfs);
2295 adapter->vfs_allocated_count = old_vfs;
a6b623e0
AD		 2296 }
2297
0224d663
GR		 2298 if (!adapter->vfs_allocated_count)
2299 return;
2300
2301 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2302 sizeof(struct vf_data_storage), GFP_KERNEL);
f96a8a0b 2303
0224d663
GR		 2304 /* if allocation failed then we do not support SR-IOV */
2305 if (!adapter->vf_data) {
a6b623e0 2306 adapter->vfs_allocated_count = 0;
0224d663
GR		 2307 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2308 "Data Storage\n");
2309 goto out;
a6b623e0 2310 }
0224d663
GR		 2311
2312 if (!old_vfs) {
2313 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2314 goto err_out;
2315 }
2316 dev_info(&pdev->dev, "%d VFs allocated\n",
2317 adapter->vfs_allocated_count);
2318 for (i = 0; i < adapter->vfs_allocated_count; i++)
2319 igb_vf_configure(adapter, i);
2320
2321 /* DMA Coalescing is not supported in IOV mode. */
2322 adapter->flags &= ~IGB_FLAG_DMAC;
2323 goto out;
2324err_out:
2325 kfree(adapter->vf_data);
2326 adapter->vf_data = NULL;
2327 adapter->vfs_allocated_count = 0;
2328out:
2329 return;
a6b623e0
AD		 2330#endif /* CONFIG_PCI_IOV */
2331}
2332
9d5c8243
AK		 2333/**
2334 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2335 * @adapter: board private structure to initialize
2336 *
2337 * igb_sw_init initializes the Adapter private data structure.
2338 * Fields are initialized based on PCI device information and
2339 * OS network device settings (MTU size).
2340 **/
2341static int __devinit igb_sw_init(struct igb_adapter *adapter)
2342{
2343 struct e1000_hw *hw = &adapter->hw;
2344 struct net_device *netdev = adapter->netdev;
2345 struct pci_dev *pdev = adapter->pdev;
374a542d 2346 u32 max_rss_queues;
9d5c8243
AK		 2347
2348 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2349
13fde97a 2350 /* set default ring sizes */
68fd9910
AD		 2351 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2352 adapter->rx_ring_count = IGB_DEFAULT_RXD;
13fde97a
AD		 2353
2354 /* set default ITR values */
4fc82adf
AD		 2355 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2356 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2357
13fde97a
AD		 2358 /* set default work limits */
2359 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2360
153285f9
AD		 2361 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2362 VLAN_HLEN;
9d5c8243
AK		 2363 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2364
12dcd86b 2365 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2366#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2367 switch (hw->mac.type) {
2368 case e1000_82576:
2369 case e1000_i350:
9b082d73
SA		 2370 if (max_vfs > 7) {
2371 dev_warn(&pdev->dev,
2372 "Maximum of 7 VFs per PF, using max\n");
2373 adapter->vfs_allocated_count = 7;
2374 } else
2375 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2376 break;
2377 default:
2378 break;
2379 }
a6b623e0 2380#endif /* CONFIG_PCI_IOV */
374a542d
MV		 2381
2382 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2383 switch (hw->mac.type) {
374a542d
MV		 2384 case e1000_i211:
2385 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2386 break;
2387 case e1000_82575:
f96a8a0b 2388 case e1000_i210:
374a542d
MV		 2389 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2390 break;
2391 case e1000_i350:
2392 /* I350 cannot do RSS and SR-IOV at the same time */
2393 if (!!adapter->vfs_allocated_count) {
2394 max_rss_queues = 1;
2395 break;
2396 }
2397 /* fall through */
2398 case e1000_82576:
2399 if (!!adapter->vfs_allocated_count) {
2400 max_rss_queues = 2;
2401 break;
2402 }
2403 /* fall through */
2404 case e1000_82580:
2405 default:
2406 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2407 break;
374a542d
MV		 2408 }
2409
2410 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2411
2412 /* Determine if we need to pair queues. */
2413 switch (hw->mac.type) {
2414 case e1000_82575:
f96a8a0b 2415 case e1000_i211:
374a542d 2416 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2417 break;
374a542d
MV		 2418 case e1000_82576:
2419 /*
2420 * If VFs are going to be allocated with RSS queues then we
2421 * should pair the queues in order to conserve interrupts due
2422 * to limited supply.
2423 */
2424 if ((adapter->rss_queues > 1) &&
2425 (adapter->vfs_allocated_count > 6))
2426 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2427 /* fall through */
2428 case e1000_82580:
2429 case e1000_i350:
2430 case e1000_i210:
f96a8a0b 2431 default:
374a542d
MV		 2432 /*
2433 * If rss_queues > half of max_rss_queues, pair the queues in
2434 * order to conserve interrupts due to limited supply.
2435 */
2436 if (adapter->rss_queues > (max_rss_queues / 2))
2437 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2438 break;
2439 }
a99955fc 2440
1128c756
CW		 2441 /* Setup and initialize a copy of the hw vlan table array */
2442 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2443 E1000_VLAN_FILTER_TBL_SIZE,
2444 GFP_ATOMIC);
2445
a6b623e0 2446 /* This call may decrease the number of queues */
047e0030 2447 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2448 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2449 return -ENOMEM;
2450 }
2451
a6b623e0
AD		 2452 igb_probe_vfs(adapter);
2453
9d5c8243
AK		 2454 /* Explicitly disable IRQ since the NIC can be in any state. */
2455 igb_irq_disable(adapter);
2456
f96a8a0b 2457 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2458 adapter->flags &= ~IGB_FLAG_DMAC;
2459
9d5c8243
AK		 2460 set_bit(__IGB_DOWN, &adapter->state);
2461 return 0;
2462}
2463
2464/**
2465 * igb_open - Called when a network interface is made active
2466 * @netdev: network interface device structure
2467 *
2468 * Returns 0 on success, negative value on failure
2469 *
2470 * The open entry point is called when a network interface is made
2471 * active by the system (IFF_UP). At this point all resources needed
2472 * for transmit and receive operations are allocated, the interrupt
2473 * handler is registered with the OS, the watchdog timer is started,
2474 * and the stack is notified that the interface is ready.
2475 **/
749ab2cd 2476static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2477{
2478 struct igb_adapter *adapter = netdev_priv(netdev);
2479 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2480 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2481 int err;
2482 int i;
2483
2484 /* disallow open during test */
749ab2cd
YZ		 2485 if (test_bit(__IGB_TESTING, &adapter->state)) {
2486 WARN_ON(resuming);
9d5c8243 2487 return -EBUSY;
749ab2cd
YZ		 2488 }
2489
2490 if (!resuming)
2491 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2492
b168dfc5
JB		 2493 netif_carrier_off(netdev);
2494
9d5c8243
AK		 2495 /* allocate transmit descriptors */
2496 err = igb_setup_all_tx_resources(adapter);
2497 if (err)
2498 goto err_setup_tx;
2499
2500 /* allocate receive descriptors */
2501 err = igb_setup_all_rx_resources(adapter);
2502 if (err)
2503 goto err_setup_rx;
2504
88a268c1 2505 igb_power_up_link(adapter);
9d5c8243 2506
9d5c8243
AK		 2507 /* before we allocate an interrupt, we must be ready to handle it.
2508 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2509 * as soon as we call pci_request_irq, so we have to setup our
2510 * clean_rx handler before we do so. */
2511 igb_configure(adapter);
2512
2513 err = igb_request_irq(adapter);
2514 if (err)
2515 goto err_req_irq;
2516
0c2cc02e
AD		 2517 /* Notify the stack of the actual queue counts. */
2518 err = netif_set_real_num_tx_queues(adapter->netdev,
2519 adapter->num_tx_queues);
2520 if (err)
2521 goto err_set_queues;
2522
2523 err = netif_set_real_num_rx_queues(adapter->netdev,
2524 adapter->num_rx_queues);
2525 if (err)
2526 goto err_set_queues;
2527
9d5c8243
AK		 2528 /* From here on the code is the same as igb_up() */
2529 clear_bit(__IGB_DOWN, &adapter->state);
2530
0d1ae7f4
AD		 2531 for (i = 0; i < adapter->num_q_vectors; i++)
2532 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2533
2534 /* Clear any pending interrupts. */
2535 rd32(E1000_ICR);
844290e5
PW		 2536
2537 igb_irq_enable(adapter);
2538
d4960307
AD		 2539 /* notify VFs that reset has been completed */
2540 if (adapter->vfs_allocated_count) {
2541 u32 reg_data = rd32(E1000_CTRL_EXT);
2542 reg_data |= E1000_CTRL_EXT_PFRSTD;
2543 wr32(E1000_CTRL_EXT, reg_data);
2544 }
2545
d55b53ff
JK		 2546 netif_tx_start_all_queues(netdev);
2547
749ab2cd
YZ		 2548 if (!resuming)
2549 pm_runtime_put(&pdev->dev);
2550
25568a53
AD		 2551 /* start the watchdog. */
2552 hw->mac.get_link_status = 1;
2553 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2554
2555 return 0;
2556
0c2cc02e
AD		 2557err_set_queues:
2558 igb_free_irq(adapter);
9d5c8243
AK		 2559err_req_irq:
2560 igb_release_hw_control(adapter);
88a268c1 2561 igb_power_down_link(adapter);
9d5c8243
AK		 2562 igb_free_all_rx_resources(adapter);
2563err_setup_rx:
2564 igb_free_all_tx_resources(adapter);
2565err_setup_tx:
2566 igb_reset(adapter);
749ab2cd
YZ		 2567 if (!resuming)
2568 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2569
2570 return err;
2571}
2572
749ab2cd
YZ		 2573static int igb_open(struct net_device *netdev)
2574{
2575 return __igb_open(netdev, false);
2576}
2577
9d5c8243
AK		 2578/**
2579 * igb_close - Disables a network interface
2580 * @netdev: network interface device structure
2581 *
2582 * Returns 0, this is not allowed to fail
2583 *
2584 * The close entry point is called when an interface is de-activated
2585 * by the OS. The hardware is still under the driver's control, but
2586 * needs to be disabled. A global MAC reset is issued to stop the
2587 * hardware, and all transmit and receive resources are freed.
2588 **/
749ab2cd 2589static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2590{
2591 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2592 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2593
2594 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2595
749ab2cd
YZ		 2596 if (!suspending)
2597 pm_runtime_get_sync(&pdev->dev);
2598
2599 igb_down(adapter);
9d5c8243
AK		 2600 igb_free_irq(adapter);
2601
2602 igb_free_all_tx_resources(adapter);
2603 igb_free_all_rx_resources(adapter);
2604
749ab2cd
YZ		 2605 if (!suspending)
2606 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2607 return 0;
2608}
2609
749ab2cd
YZ		 2610static int igb_close(struct net_device *netdev)
2611{
2612 return __igb_close(netdev, false);
2613}
2614
9d5c8243
AK		 2615/**
2616 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2617 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2618 *
2619 * Return 0 on success, negative on failure
2620 **/
80785298 2621int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2622{
59d71989 2623 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2624 int size;
2625
06034649 2626 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2627
2628 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2629 if (!tx_ring->tx_buffer_info)
9d5c8243 2630 goto err;
9d5c8243
AK		 2631
2632 /* round up to nearest 4K */
85e8d004 2633 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2634 tx_ring->size = ALIGN(tx_ring->size, 4096);
2635
5536d210
AD		 2636 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2637 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2638 if (!tx_ring->desc)
2639 goto err;
2640
9d5c8243
AK		 2641 tx_ring->next_to_use = 0;
2642 tx_ring->next_to_clean = 0;
81c2fc22 2643
9d5c8243
AK		 2644 return 0;
2645
2646err:
06034649 2647 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2648 tx_ring->tx_buffer_info = NULL;
2649 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2650 return -ENOMEM;
2651}
2652
2653/**
2654 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2655 * (Descriptors) for all queues
2656 * @adapter: board private structure
2657 *
2658 * Return 0 on success, negative on failure
2659 **/
2660static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2661{
439705e1 2662 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2663 int i, err = 0;
2664
2665 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2666 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2667 if (err) {
439705e1 2668 dev_err(&pdev->dev,
9d5c8243
AK		 2669 "Allocation for Tx Queue %u failed\n", i);
2670 for (i--; i >= 0; i--)
3025a446 2671 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2672 break;
2673 }
2674 }
2675
2676 return err;
2677}
2678
2679/**
85b430b4
AD		 2680 * igb_setup_tctl - configure the transmit control registers
2681 * @adapter: Board private structure
9d5c8243 2682 **/
d7ee5b3a 2683void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2684{
9d5c8243
AK		 2685 struct e1000_hw *hw = &adapter->hw;
2686 u32 tctl;
9d5c8243 2687
85b430b4
AD		 2688 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2689 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2690
2691 /* Program the Transmit Control Register */
9d5c8243
AK		 2692 tctl = rd32(E1000_TCTL);
2693 tctl &= ~E1000_TCTL_CT;
2694 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2695 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2696
2697 igb_config_collision_dist(hw);
2698
9d5c8243
AK		 2699 /* Enable transmits */
2700 tctl |= E1000_TCTL_EN;
2701
2702 wr32(E1000_TCTL, tctl);
2703}
2704
85b430b4
AD		 2705/**
2706 * igb_configure_tx_ring - Configure transmit ring after Reset
2707 * @adapter: board private structure
2708 * @ring: tx ring to configure
2709 *
2710 * Configure a transmit ring after a reset.
2711 **/
d7ee5b3a
AD		 2712void igb_configure_tx_ring(struct igb_adapter *adapter,
2713 struct igb_ring *ring)
85b430b4
AD		 2714{
2715 struct e1000_hw *hw = &adapter->hw;
a74420e0 2716 u32 txdctl = 0;
85b430b4
AD		 2717 u64 tdba = ring->dma;
2718 int reg_idx = ring->reg_idx;
2719
2720 /* disable the queue */
a74420e0 2721 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2722 wrfl();
2723 mdelay(10);
2724
2725 wr32(E1000_TDLEN(reg_idx),
2726 ring->count * sizeof(union e1000_adv_tx_desc));
2727 wr32(E1000_TDBAL(reg_idx),
2728 tdba & 0x00000000ffffffffULL);
2729 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2730
fce99e34 2731 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2732 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2733 writel(0, ring->tail);
85b430b4
AD		 2734
2735 txdctl |= IGB_TX_PTHRESH;
2736 txdctl |= IGB_TX_HTHRESH << 8;
2737 txdctl |= IGB_TX_WTHRESH << 16;
2738
2739 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2740 wr32(E1000_TXDCTL(reg_idx), txdctl);
2741}
2742
2743/**
2744 * igb_configure_tx - Configure transmit Unit after Reset
2745 * @adapter: board private structure
2746 *
2747 * Configure the Tx unit of the MAC after a reset.
2748 **/
2749static void igb_configure_tx(struct igb_adapter *adapter)
2750{
2751 int i;
2752
2753 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2754 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2755}
2756
9d5c8243
AK		 2757/**
2758 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2759 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2760 *
2761 * Returns 0 on success, negative on failure
2762 **/
80785298 2763int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2764{
59d71989 2765 struct device *dev = rx_ring->dev;
f33005a6 2766 int size;
9d5c8243 2767
06034649 2768 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 2769
2770 rx_ring->rx_buffer_info = vzalloc(size);
06034649 2771 if (!rx_ring->rx_buffer_info)
9d5c8243 2772 goto err;
9d5c8243 2773
9d5c8243 2774 /* Round up to nearest 4K */
f33005a6 2775 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 2776 rx_ring->size = ALIGN(rx_ring->size, 4096);
2777
5536d210
AD		 2778 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2779 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2780 if (!rx_ring->desc)
2781 goto err;
2782
cbc8e55f 2783 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 2784 rx_ring->next_to_clean = 0;
2785 rx_ring->next_to_use = 0;
9d5c8243 2786
9d5c8243
AK		 2787 return 0;
2788
2789err:
06034649
AD		 2790 vfree(rx_ring->rx_buffer_info);
2791 rx_ring->rx_buffer_info = NULL;
f33005a6 2792 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 2793 return -ENOMEM;
2794}
2795
2796/**
2797 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2798 * (Descriptors) for all queues
2799 * @adapter: board private structure
2800 *
2801 * Return 0 on success, negative on failure
2802 **/
2803static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2804{
439705e1 2805 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2806 int i, err = 0;
2807
2808 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2809 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2810 if (err) {
439705e1 2811 dev_err(&pdev->dev,
9d5c8243
AK		 2812 "Allocation for Rx Queue %u failed\n", i);
2813 for (i--; i >= 0; i--)
3025a446 2814 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2815 break;
2816 }
2817 }
2818
2819 return err;
2820}
2821
06cf2666
AD		 2822/**
2823 * igb_setup_mrqc - configure the multiple receive queue control registers
2824 * @adapter: Board private structure
2825 **/
2826static void igb_setup_mrqc(struct igb_adapter *adapter)
2827{
2828 struct e1000_hw *hw = &adapter->hw;
2829 u32 mrqc, rxcsum;
797fd4be 2830 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 2831 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2832 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2833 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2834 0xFA01ACBE };
06cf2666
AD		 2835
2836 /* Fill out hash function seeds */
a57fe23e
AD		 2837 for (j = 0; j < 10; j++)
2838 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 2839
a99955fc 2840 num_rx_queues = adapter->rss_queues;
06cf2666 2841
797fd4be
AD		 2842 switch (hw->mac.type) {
2843 case e1000_82575:
2844 shift = 6;
2845 break;
2846 case e1000_82576:
2847 /* 82576 supports 2 RSS queues for SR-IOV */
2848 if (adapter->vfs_allocated_count) {
06cf2666
AD		 2849 shift = 3;
2850 num_rx_queues = 2;
06cf2666 2851 }
797fd4be
AD		 2852 break;
2853 default:
2854 break;
06cf2666
AD		 2855 }
2856
797fd4be
AD		 2857 /*
2858 * Populate the indirection table 4 entries at a time. To do this
2859 * we are generating the results for n and n+2 and then interleaving
2860 * those with the results with n+1 and n+3.
2861 */
2862 for (j = 0; j < 32; j++) {
2863 /* first pass generates n and n+2 */
2864 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2865 u32 reta = (base & 0x07800780) >> (7 - shift);
2866
2867 /* second pass generates n+1 and n+3 */
2868 base += 0x00010001 * num_rx_queues;
2869 reta |= (base & 0x07800780) << (1 + shift);
2870
2871 wr32(E1000_RETA(j), reta);
06cf2666
AD		 2872 }
2873
2874 /*
2875 * Disable raw packet checksumming so that RSS hash is placed in
2876 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2877 * offloads as they are enabled by default
2878 */
2879 rxcsum = rd32(E1000_RXCSUM);
2880 rxcsum |= E1000_RXCSUM_PCSD;
2881
2882 if (adapter->hw.mac.type >= e1000_82576)
2883 /* Enable Receive Checksum Offload for SCTP */
2884 rxcsum |= E1000_RXCSUM_CRCOFL;
2885
2886 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2887 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 2888
039454a8
AA		 2889 /* Generate RSS hash based on packet types, TCP/UDP
2890 * port numbers and/or IPv4/v6 src and dst addresses
2891 */
f96a8a0b
CW		 2892 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2893 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2894 E1000_MRQC_RSS_FIELD_IPV6 |
2895 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2896 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 2897
039454a8
AA		 2898 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2899 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2900 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2901 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2902
06cf2666
AD		 2903 /* If VMDq is enabled then we set the appropriate mode for that, else
2904 * we default to RSS so that an RSS hash is calculated per packet even
2905 * if we are only using one queue */
2906 if (adapter->vfs_allocated_count) {
2907 if (hw->mac.type > e1000_82575) {
2908 /* Set the default pool for the PF's first queue */
2909 u32 vtctl = rd32(E1000_VT_CTL);
2910 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2911 E1000_VT_CTL_DISABLE_DEF_POOL);
2912 vtctl |= adapter->vfs_allocated_count <<
2913 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2914 wr32(E1000_VT_CTL, vtctl);
2915 }
a99955fc 2916 if (adapter->rss_queues > 1)
f96a8a0b 2917 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 2918 else
f96a8a0b 2919 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 2920 } else {
f96a8a0b
CW		 2921 if (hw->mac.type != e1000_i211)
2922 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 2923 }
2924 igb_vmm_control(adapter);
2925
06cf2666
AD		 2926 wr32(E1000_MRQC, mrqc);
2927}
2928
9d5c8243
AK		 2929/**
2930 * igb_setup_rctl - configure the receive control registers
2931 * @adapter: Board private structure
2932 **/
d7ee5b3a 2933void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2934{
2935 struct e1000_hw *hw = &adapter->hw;
2936 u32 rctl;
9d5c8243
AK		 2937
2938 rctl = rd32(E1000_RCTL);
2939
2940 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2941 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2942
69d728ba 2943 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2944 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2945
87cb7e8c
AK		 2946 /*
2947 * enable stripping of CRC. It's unlikely this will break BMC
2948 * redirection as it did with e1000. Newer features require
2949 * that the HW strips the CRC.
73cd78f1 2950 */
87cb7e8c 2951 rctl |= E1000_RCTL_SECRC;
9d5c8243 2952
559e9c49 2953 /* disable store bad packets and clear size bits. */
ec54d7d6 2954 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2955
6ec43fe6
AD		 2956 /* enable LPE to prevent packets larger than max_frame_size */
2957 rctl |= E1000_RCTL_LPE;
9d5c8243 2958
952f72a8
AD		 2959 /* disable queue 0 to prevent tail write w/o re-config */
2960 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2961
e1739522
AD		 2962 /* Attention!!! For SR-IOV PF driver operations you must enable
2963 * queue drop for all VF and PF queues to prevent head of line blocking
2964 * if an un-trusted VF does not provide descriptors to hardware.
2965 */
2966 if (adapter->vfs_allocated_count) {
e1739522
AD		 2967 /* set all queue drop enable bits */
2968 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2969 }
2970
89eaefb6
BG		 2971 /* This is useful for sniffing bad packets. */
2972 if (adapter->netdev->features & NETIF_F_RXALL) {
2973 /* UPE and MPE will be handled by normal PROMISC logic
2974 * in e1000e_set_rx_mode */
2975 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2976 E1000_RCTL_BAM | /* RX All Bcast Pkts */
2977 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2978
2979 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2980 E1000_RCTL_DPF | /* Allow filtered pause */
2981 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2982 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2983 * and that breaks VLANs.
2984 */
2985 }
2986
9d5c8243
AK		 2987 wr32(E1000_RCTL, rctl);
2988}
2989
7d5753f0
AD		 2990static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2991 int vfn)
2992{
2993 struct e1000_hw *hw = &adapter->hw;
2994 u32 vmolr;
2995
2996 /* if it isn't the PF check to see if VFs are enabled and
2997 * increase the size to support vlan tags */
2998 if (vfn < adapter->vfs_allocated_count &&
2999 adapter->vf_data[vfn].vlans_enabled)
3000 size += VLAN_TAG_SIZE;
3001
3002 vmolr = rd32(E1000_VMOLR(vfn));
3003 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3004 vmolr |= size | E1000_VMOLR_LPE;
3005 wr32(E1000_VMOLR(vfn), vmolr);
3006
3007 return 0;
3008}
3009
e1739522
AD		 3010/**
3011 * igb_rlpml_set - set maximum receive packet size
3012 * @adapter: board private structure
3013 *
3014 * Configure maximum receivable packet size.
3015 **/
3016static void igb_rlpml_set(struct igb_adapter *adapter)
3017{
153285f9 3018 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3019 struct e1000_hw *hw = &adapter->hw;
3020 u16 pf_id = adapter->vfs_allocated_count;
3021
e1739522
AD		 3022 if (pf_id) {
3023 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3024 /*
3025 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3026 * to our max jumbo frame size, in case we need to enable
3027 * jumbo frames on one of the rings later.
3028 * This will not pass over-length frames into the default
3029 * queue because it's gated by the VMOLR.RLPML.
3030 */
7d5753f0 3031 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3032 }
3033
3034 wr32(E1000_RLPML, max_frame_size);
3035}
3036
8151d294
WM		 3037static inline void igb_set_vmolr(struct igb_adapter *adapter,
3038 int vfn, bool aupe)
7d5753f0
AD		 3039{
3040 struct e1000_hw *hw = &adapter->hw;
3041 u32 vmolr;
3042
3043 /*
3044 * This register exists only on 82576 and newer so if we are older then
3045 * we should exit and do nothing
3046 */
3047 if (hw->mac.type < e1000_82576)
3048 return;
3049
3050 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3051 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3052 if (aupe)
3053 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3054 else
3055 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3056
3057 /* clear all bits that might not be set */
3058 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3059
a99955fc 3060 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3061 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3062 /*
3063 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3064 * multicast packets
3065 */
3066 if (vfn <= adapter->vfs_allocated_count)
3067 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3068
3069 wr32(E1000_VMOLR(vfn), vmolr);
3070}
3071
85b430b4
AD		 3072/**
3073 * igb_configure_rx_ring - Configure a receive ring after Reset
3074 * @adapter: board private structure
3075 * @ring: receive ring to be configured
3076 *
3077 * Configure the Rx unit of the MAC after a reset.
3078 **/
d7ee5b3a
AD		 3079void igb_configure_rx_ring(struct igb_adapter *adapter,
3080 struct igb_ring *ring)
85b430b4
AD		 3081{
3082 struct e1000_hw *hw = &adapter->hw;
3083 u64 rdba = ring->dma;
3084 int reg_idx = ring->reg_idx;
a74420e0 3085 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3086
3087 /* disable the queue */
a74420e0 3088 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3089
3090 /* Set DMA base address registers */
3091 wr32(E1000_RDBAL(reg_idx),
3092 rdba & 0x00000000ffffffffULL);
3093 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3094 wr32(E1000_RDLEN(reg_idx),
3095 ring->count * sizeof(union e1000_adv_rx_desc));
3096
3097 /* initialize head and tail */
fce99e34 3098 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3099 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3100 writel(0, ring->tail);
85b430b4 3101
952f72a8 3102 /* set descriptor configuration */
44390ca6 3103 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3104 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3105 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3106 if (hw->mac.type >= e1000_82580)
757b77e2 3107 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3108 /* Only set Drop Enable if we are supporting multiple queues */
3109 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3110 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3111
3112 wr32(E1000_SRRCTL(reg_idx), srrctl);
3113
7d5753f0 3114 /* set filtering for VMDQ pools */
8151d294 3115 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3116
85b430b4
AD		 3117 rxdctl |= IGB_RX_PTHRESH;
3118 rxdctl |= IGB_RX_HTHRESH << 8;
3119 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3120
3121 /* enable receive descriptor fetching */
3122 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3123 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3124}
3125
9d5c8243
AK		 3126/**
3127 * igb_configure_rx - Configure receive Unit after Reset
3128 * @adapter: board private structure
3129 *
3130 * Configure the Rx unit of the MAC after a reset.
3131 **/
3132static void igb_configure_rx(struct igb_adapter *adapter)
3133{
9107584e 3134 int i;
9d5c8243 3135
68d480c4
AD		 3136 /* set UTA to appropriate mode */
3137 igb_set_uta(adapter);
3138
26ad9178
AD		 3139 /* set the correct pool for the PF default MAC address in entry 0 */
3140 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3141 adapter->vfs_allocated_count);
3142
06cf2666
AD		 3143 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3144 * the Base and Length of the Rx Descriptor Ring */
3145 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3146 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3147}
3148
3149/**
3150 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3151 * @tx_ring: Tx descriptor ring for a specific queue
3152 *
3153 * Free all transmit software resources
3154 **/
68fd9910 3155void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3156{
3b644cf6 3157 igb_clean_tx_ring(tx_ring);
9d5c8243 3158
06034649
AD		 3159 vfree(tx_ring->tx_buffer_info);
3160 tx_ring->tx_buffer_info = NULL;
9d5c8243 3161
439705e1
AD		 3162 /* if not set, then don't free */
3163 if (!tx_ring->desc)
3164 return;
3165
59d71989
AD		 3166 dma_free_coherent(tx_ring->dev, tx_ring->size,
3167 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3168
3169 tx_ring->desc = NULL;
3170}
3171
3172/**
3173 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3174 * @adapter: board private structure
3175 *
3176 * Free all transmit software resources
3177 **/
3178static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3179{
3180 int i;
3181
3182 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3183 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3184}
3185
ebe42d16
AD		 3186void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3187 struct igb_tx_buffer *tx_buffer)
3188{
3189 if (tx_buffer->skb) {
3190 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3191 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3192 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3193 dma_unmap_addr(tx_buffer, dma),
3194 dma_unmap_len(tx_buffer, len),
ebe42d16 3195 DMA_TO_DEVICE);
c9f14bf3 3196 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3197 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3198 dma_unmap_addr(tx_buffer, dma),
3199 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3200 DMA_TO_DEVICE);
3201 }
3202 tx_buffer->next_to_watch = NULL;
3203 tx_buffer->skb = NULL;
c9f14bf3 3204 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3205 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3206}
3207
3208/**
3209 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3210 * @tx_ring: ring to be cleaned
3211 **/
3b644cf6 3212static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3213{
06034649 3214 struct igb_tx_buffer *buffer_info;
9d5c8243 3215 unsigned long size;
6ad4edfc 3216 u16 i;
9d5c8243 3217
06034649 3218 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3219 return;
3220 /* Free all the Tx ring sk_buffs */
3221
3222 for (i = 0; i < tx_ring->count; i++) {
06034649 3223 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3224 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3225 }
3226
dad8a3b3
JF		 3227 netdev_tx_reset_queue(txring_txq(tx_ring));
3228
06034649
AD		 3229 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3230 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3231
3232 /* Zero out the descriptor ring */
9d5c8243
AK		 3233 memset(tx_ring->desc, 0, tx_ring->size);
3234
3235 tx_ring->next_to_use = 0;
3236 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3237}
3238
3239/**
3240 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3241 * @adapter: board private structure
3242 **/
3243static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3244{
3245 int i;
3246
3247 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3248 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3249}
3250
3251/**
3252 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3253 * @rx_ring: ring to clean the resources from
3254 *
3255 * Free all receive software resources
3256 **/
68fd9910 3257void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3258{
3b644cf6 3259 igb_clean_rx_ring(rx_ring);
9d5c8243 3260
06034649
AD		 3261 vfree(rx_ring->rx_buffer_info);
3262 rx_ring->rx_buffer_info = NULL;
9d5c8243 3263
439705e1
AD		 3264 /* if not set, then don't free */
3265 if (!rx_ring->desc)
3266 return;
3267
59d71989
AD		 3268 dma_free_coherent(rx_ring->dev, rx_ring->size,
3269 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3270
3271 rx_ring->desc = NULL;
3272}
3273
3274/**
3275 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3276 * @adapter: board private structure
3277 *
3278 * Free all receive software resources
3279 **/
3280static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3281{
3282 int i;
3283
3284 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3285 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3286}
3287
3288/**
3289 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3290 * @rx_ring: ring to free buffers from
3291 **/
3b644cf6 3292static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3293{
9d5c8243 3294 unsigned long size;
c023cd88 3295 u16 i;
9d5c8243 3296
1a1c225b
AD		 3297 if (rx_ring->skb)
3298 dev_kfree_skb(rx_ring->skb);
3299 rx_ring->skb = NULL;
3300
06034649 3301 if (!rx_ring->rx_buffer_info)
9d5c8243 3302 return;
439705e1 3303
9d5c8243
AK		 3304 /* Free all the Rx ring sk_buffs */
3305 for (i = 0; i < rx_ring->count; i++) {
06034649 3306 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3307
cbc8e55f
AD		 3308 if (!buffer_info->page)
3309 continue;
3310
3311 dma_unmap_page(rx_ring->dev,
3312 buffer_info->dma,
3313 PAGE_SIZE,
3314 DMA_FROM_DEVICE);
3315 __free_page(buffer_info->page);
3316
1a1c225b 3317 buffer_info->page = NULL;
9d5c8243
AK		 3318 }
3319
06034649
AD		 3320 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3321 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3322
3323 /* Zero out the descriptor ring */
3324 memset(rx_ring->desc, 0, rx_ring->size);
3325
cbc8e55f 3326 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3327 rx_ring->next_to_clean = 0;
3328 rx_ring->next_to_use = 0;
9d5c8243
AK		 3329}
3330
3331/**
3332 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3333 * @adapter: board private structure
3334 **/
3335static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3336{
3337 int i;
3338
3339 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3340 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3341}
3342
3343/**
3344 * igb_set_mac - Change the Ethernet Address of the NIC
3345 * @netdev: network interface device structure
3346 * @p: pointer to an address structure
3347 *
3348 * Returns 0 on success, negative on failure
3349 **/
3350static int igb_set_mac(struct net_device *netdev, void *p)
3351{
3352 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3353 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3354 struct sockaddr *addr = p;
3355
3356 if (!is_valid_ether_addr(addr->sa_data))
3357 return -EADDRNOTAVAIL;
3358
3359 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3360 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3361
26ad9178
AD		 3362 /* set the correct pool for the new PF MAC address in entry 0 */
3363 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3364 adapter->vfs_allocated_count);
e1739522 3365
9d5c8243
AK		 3366 return 0;
3367}
3368
3369/**
68d480c4 3370 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3371 * @netdev: network interface device structure
3372 *
68d480c4
AD		 3373 * Writes multicast address list to the MTA hash table.
3374 * Returns: -ENOMEM on failure
3375 * 0 on no addresses written
3376 * X on writing X addresses to MTA
9d5c8243 3377 **/
68d480c4 3378static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3379{
3380 struct igb_adapter *adapter = netdev_priv(netdev);
3381 struct e1000_hw *hw = &adapter->hw;
22bedad3 3382 struct netdev_hw_addr *ha;
68d480c4 3383 u8 *mta_list;
9d5c8243
AK		 3384 int i;
3385
4cd24eaf 3386 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3387 /* nothing to program, so clear mc list */
3388 igb_update_mc_addr_list(hw, NULL, 0);
3389 igb_restore_vf_multicasts(adapter);
3390 return 0;
3391 }
9d5c8243 3392
4cd24eaf 3393 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3394 if (!mta_list)
3395 return -ENOMEM;
ff41f8dc 3396
68d480c4 3397 /* The shared function expects a packed array of only addresses. */
48e2f183 3398 i = 0;
22bedad3
JP		 3399 netdev_for_each_mc_addr(ha, netdev)
3400 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3401
68d480c4
AD		 3402 igb_update_mc_addr_list(hw, mta_list, i);
3403 kfree(mta_list);
3404
4cd24eaf 3405 return netdev_mc_count(netdev);
68d480c4
AD		 3406}
3407
3408/**
3409 * igb_write_uc_addr_list - write unicast addresses to RAR table
3410 * @netdev: network interface device structure
3411 *
3412 * Writes unicast address list to the RAR table.
3413 * Returns: -ENOMEM on failure/insufficient address space
3414 * 0 on no addresses written
3415 * X on writing X addresses to the RAR table
3416 **/
3417static int igb_write_uc_addr_list(struct net_device *netdev)
3418{
3419 struct igb_adapter *adapter = netdev_priv(netdev);
3420 struct e1000_hw *hw = &adapter->hw;
3421 unsigned int vfn = adapter->vfs_allocated_count;
3422 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3423 int count = 0;
3424
3425 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3426 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3427 return -ENOMEM;
9d5c8243 3428
32e7bfc4 3429 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3430 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3431
3432 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3433 if (!rar_entries)
3434 break;
26ad9178
AD		 3435 igb_rar_set_qsel(adapter, ha->addr,
3436 rar_entries--,
68d480c4
AD		 3437 vfn);
3438 count++;
ff41f8dc
AD		 3439 }
3440 }
3441 /* write the addresses in reverse order to avoid write combining */
3442 for (; rar_entries > 0 ; rar_entries--) {
3443 wr32(E1000_RAH(rar_entries), 0);
3444 wr32(E1000_RAL(rar_entries), 0);
3445 }
3446 wrfl();
3447
68d480c4
AD		 3448 return count;
3449}
3450
3451/**
3452 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3453 * @netdev: network interface device structure
3454 *
3455 * The set_rx_mode entry point is called whenever the unicast or multicast
3456 * address lists or the network interface flags are updated. This routine is
3457 * responsible for configuring the hardware for proper unicast, multicast,
3458 * promiscuous mode, and all-multi behavior.
3459 **/
3460static void igb_set_rx_mode(struct net_device *netdev)
3461{
3462 struct igb_adapter *adapter = netdev_priv(netdev);
3463 struct e1000_hw *hw = &adapter->hw;
3464 unsigned int vfn = adapter->vfs_allocated_count;
3465 u32 rctl, vmolr = 0;
3466 int count;
3467
3468 /* Check for Promiscuous and All Multicast modes */
3469 rctl = rd32(E1000_RCTL);
3470
3471 /* clear the effected bits */
3472 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3473
3474 if (netdev->flags & IFF_PROMISC) {
3475 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3476 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3477 } else {
3478 if (netdev->flags & IFF_ALLMULTI) {
3479 rctl |= E1000_RCTL_MPE;
3480 vmolr |= E1000_VMOLR_MPME;
3481 } else {
3482 /*
3483 * Write addresses to the MTA, if the attempt fails
25985edc 3484 * then we should just turn on promiscuous mode so
68d480c4
AD		 3485 * that we can at least receive multicast traffic
3486 */
3487 count = igb_write_mc_addr_list(netdev);
3488 if (count < 0) {
3489 rctl |= E1000_RCTL_MPE;
3490 vmolr |= E1000_VMOLR_MPME;
3491 } else if (count) {
3492 vmolr |= E1000_VMOLR_ROMPE;
3493 }
3494 }
3495 /*
3496 * Write addresses to available RAR registers, if there is not
3497 * sufficient space to store all the addresses then enable
25985edc 3498 * unicast promiscuous mode
68d480c4
AD		 3499 */
3500 count = igb_write_uc_addr_list(netdev);
3501 if (count < 0) {
3502 rctl |= E1000_RCTL_UPE;
3503 vmolr |= E1000_VMOLR_ROPE;
3504 }
3505 rctl |= E1000_RCTL_VFE;
28fc06f5 3506 }
68d480c4 3507 wr32(E1000_RCTL, rctl);
28fc06f5 3508
68d480c4
AD		 3509 /*
3510 * In order to support SR-IOV and eventually VMDq it is necessary to set
3511 * the VMOLR to enable the appropriate modes. Without this workaround
3512 * we will have issues with VLAN tag stripping not being done for frames
3513 * that are only arriving because we are the default pool
3514 */
f96a8a0b 3515 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3516 return;
9d5c8243 3517
68d480c4
AD		 3518 vmolr |= rd32(E1000_VMOLR(vfn)) &
3519 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3520 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3521 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3522}
3523
13800469
GR		 3524static void igb_check_wvbr(struct igb_adapter *adapter)
3525{
3526 struct e1000_hw *hw = &adapter->hw;
3527 u32 wvbr = 0;
3528
3529 switch (hw->mac.type) {
3530 case e1000_82576:
3531 case e1000_i350:
3532 if (!(wvbr = rd32(E1000_WVBR)))
3533 return;
3534 break;
3535 default:
3536 break;
3537 }
3538
3539 adapter->wvbr |= wvbr;
3540}
3541
3542#define IGB_STAGGERED_QUEUE_OFFSET 8
3543
3544static void igb_spoof_check(struct igb_adapter *adapter)
3545{
3546 int j;
3547
3548 if (!adapter->wvbr)
3549 return;
3550
3551 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3552 if (adapter->wvbr & (1 << j) ||
3553 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3554 dev_warn(&adapter->pdev->dev,
3555 "Spoof event(s) detected on VF %d\n", j);
3556 adapter->wvbr &=
3557 ~((1 << j) |
3558 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3559 }
3560 }
3561}
3562
9d5c8243
AK		 3563/* Need to wait a few seconds after link up to get diagnostic information from
3564 * the phy */
3565static void igb_update_phy_info(unsigned long data)
3566{
3567 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3568 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3569}
3570
4d6b725e
AD		 3571/**
3572 * igb_has_link - check shared code for link and determine up/down
3573 * @adapter: pointer to driver private info
3574 **/
3145535a 3575bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3576{
3577 struct e1000_hw *hw = &adapter->hw;
3578 bool link_active = false;
3579 s32 ret_val = 0;
3580
3581 /* get_link_status is set on LSC (link status) interrupt or
3582 * rx sequence error interrupt. get_link_status will stay
3583 * false until the e1000_check_for_link establishes link
3584 * for copper adapters ONLY
3585 */
3586 switch (hw->phy.media_type) {
3587 case e1000_media_type_copper:
3588 if (hw->mac.get_link_status) {
3589 ret_val = hw->mac.ops.check_for_link(hw);
3590 link_active = !hw->mac.get_link_status;
3591 } else {
3592 link_active = true;
3593 }
3594 break;
4d6b725e
AD		 3595 case e1000_media_type_internal_serdes:
3596 ret_val = hw->mac.ops.check_for_link(hw);
3597 link_active = hw->mac.serdes_has_link;
3598 break;
3599 default:
3600 case e1000_media_type_unknown:
3601 break;
3602 }
3603
3604 return link_active;
3605}
3606
563988dc
SA		 3607static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3608{
3609 bool ret = false;
3610 u32 ctrl_ext, thstat;
3611
f96a8a0b 3612 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3613 if (hw->mac.type == e1000_i350) {
3614 thstat = rd32(E1000_THSTAT);
3615 ctrl_ext = rd32(E1000_CTRL_EXT);
3616
3617 if ((hw->phy.media_type == e1000_media_type_copper) &&
3618 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3619 ret = !!(thstat & event);
3620 }
3621 }
3622
3623 return ret;
3624}
3625
9d5c8243
AK		 3626/**
3627 * igb_watchdog - Timer Call-back
3628 * @data: pointer to adapter cast into an unsigned long
3629 **/
3630static void igb_watchdog(unsigned long data)
3631{
3632 struct igb_adapter *adapter = (struct igb_adapter *)data;
3633 /* Do the rest outside of interrupt context */
3634 schedule_work(&adapter->watchdog_task);
3635}
3636
3637static void igb_watchdog_task(struct work_struct *work)
3638{
3639 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3640 struct igb_adapter,
3641 watchdog_task);
9d5c8243 3642 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3643 struct net_device *netdev = adapter->netdev;
563988dc 3644 u32 link;
7a6ea550 3645 int i;
9d5c8243 3646
4d6b725e 3647 link = igb_has_link(adapter);
9d5c8243 3648 if (link) {
749ab2cd
YZ		 3649 /* Cancel scheduled suspend requests. */
3650 pm_runtime_resume(netdev->dev.parent);
3651
9d5c8243
AK		 3652 if (!netif_carrier_ok(netdev)) {
3653 u32 ctrl;
330a6d6a
AD		 3654 hw->mac.ops.get_speed_and_duplex(hw,
3655 &adapter->link_speed,
3656 &adapter->link_duplex);
9d5c8243
AK		 3657
3658 ctrl = rd32(E1000_CTRL);
527d47c1 3659 /* Links status message must follow this format */
876d2d6f
JK		 3660 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3661 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3662 netdev->name,
3663 adapter->link_speed,
3664 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3665 "Full" : "Half",
3666 (ctrl & E1000_CTRL_TFCE) &&
3667 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3668 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3669 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3670
563988dc 3671 /* check for thermal sensor event */
876d2d6f
JK		 3672 if (igb_thermal_sensor_event(hw,
3673 E1000_THSTAT_LINK_THROTTLE)) {
3674 netdev_info(netdev, "The network adapter link "
3675 "speed was downshifted because it "
3676 "overheated\n");
7ef5ed1c 3677 }
563988dc 3678
d07f3e37 3679 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3680 adapter->tx_timeout_factor = 1;
3681 switch (adapter->link_speed) {
3682 case SPEED_10:
9d5c8243
AK		 3683 adapter->tx_timeout_factor = 14;
3684 break;
3685 case SPEED_100:
9d5c8243
AK		 3686 /* maybe add some timeout factor ? */
3687 break;
3688 }
3689
3690 netif_carrier_on(netdev);
9d5c8243 3691
4ae196df 3692 igb_ping_all_vfs(adapter);
17dc566c 3693 igb_check_vf_rate_limit(adapter);
4ae196df 3694
4b1a9877 3695 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3696 if (!test_bit(__IGB_DOWN, &adapter->state))
3697 mod_timer(&adapter->phy_info_timer,
3698 round_jiffies(jiffies + 2 * HZ));
3699 }
3700 } else {
3701 if (netif_carrier_ok(netdev)) {
3702 adapter->link_speed = 0;
3703 adapter->link_duplex = 0;
563988dc
SA		 3704
3705 /* check for thermal sensor event */
876d2d6f
JK		 3706 if (igb_thermal_sensor_event(hw,
3707 E1000_THSTAT_PWR_DOWN)) {
3708 netdev_err(netdev, "The network adapter was "
3709 "stopped because it overheated\n");
7ef5ed1c 3710 }
563988dc 3711
527d47c1
AD		 3712 /* Links status message must follow this format */
3713 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3714 netdev->name);
9d5c8243 3715 netif_carrier_off(netdev);
4b1a9877 3716
4ae196df
AD		 3717 igb_ping_all_vfs(adapter);
3718
4b1a9877 3719 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3720 if (!test_bit(__IGB_DOWN, &adapter->state))
3721 mod_timer(&adapter->phy_info_timer,
3722 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3723
3724 pm_schedule_suspend(netdev->dev.parent,
3725 MSEC_PER_SEC * 5);
9d5c8243
AK		 3726 }
3727 }
3728
12dcd86b
ED		 3729 spin_lock(&adapter->stats64_lock);
3730 igb_update_stats(adapter, &adapter->stats64);
3731 spin_unlock(&adapter->stats64_lock);
9d5c8243 3732
dbabb065 3733 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3734 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3735 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3736 /* We've lost link, so the controller stops DMA,
3737 * but we've got queued Tx work that's never going
3738 * to get done, so reset controller to flush Tx.
3739 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3740 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3741 adapter->tx_timeout_count++;
3742 schedule_work(&adapter->reset_task);
3743 /* return immediately since reset is imminent */
3744 return;
3745 }
9d5c8243 3746 }
9d5c8243 3747
dbabb065 3748 /* Force detection of hung controller every watchdog period */
6d095fa8 3749 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3750 }
f7ba205e 3751
9d5c8243 3752 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3753 if (adapter->msix_entries) {
047e0030 3754 u32 eics = 0;
0d1ae7f4
AD		 3755 for (i = 0; i < adapter->num_q_vectors; i++)
3756 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3757 wr32(E1000_EICS, eics);
3758 } else {
3759 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3760 }
9d5c8243 3761
13800469
GR		 3762 igb_spoof_check(adapter);
3763
9d5c8243
AK		 3764 /* Reset the timer */
3765 if (!test_bit(__IGB_DOWN, &adapter->state))
3766 mod_timer(&adapter->watchdog_timer,
3767 round_jiffies(jiffies + 2 * HZ));
3768}
3769
3770enum latency_range {
3771 lowest_latency = 0,
3772 low_latency = 1,
3773 bulk_latency = 2,
3774 latency_invalid = 255
3775};
3776
6eb5a7f1
AD		 3777/**
3778 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3779 *
3780 * Stores a new ITR value based on strictly on packet size. This
3781 * algorithm is less sophisticated than that used in igb_update_itr,
3782 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3783 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3784 * were determined based on theoretical maximum wire speed and testing
3785 * data, in order to minimize response time while increasing bulk
3786 * throughput.
3787 * This functionality is controlled by the InterruptThrottleRate module
3788 * parameter (see igb_param.c)
3789 * NOTE: This function is called only when operating in a multiqueue
3790 * receive environment.
047e0030 3791 * @q_vector: pointer to q_vector
6eb5a7f1 3792 **/
047e0030 3793static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3794{
047e0030 3795 int new_val = q_vector->itr_val;
6eb5a7f1 3796 int avg_wire_size = 0;
047e0030 3797 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 3798 unsigned int packets;
9d5c8243 3799
6eb5a7f1
AD		 3800 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3801 * ints/sec - ITR timer value of 120 ticks.
3802 */
3803 if (adapter->link_speed != SPEED_1000) {
0ba82994 3804 new_val = IGB_4K_ITR;
6eb5a7f1 3805 goto set_itr_val;
9d5c8243 3806 }
047e0030 3807
0ba82994
AD		 3808 packets = q_vector->rx.total_packets;
3809 if (packets)
3810 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 3811
0ba82994
AD		 3812 packets = q_vector->tx.total_packets;
3813 if (packets)
3814 avg_wire_size = max_t(u32, avg_wire_size,
3815 q_vector->tx.total_bytes / packets);
047e0030
AD		 3816
3817 /* if avg_wire_size isn't set no work was done */
3818 if (!avg_wire_size)
3819 goto clear_counts;
9d5c8243 3820
6eb5a7f1
AD		 3821 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3822 avg_wire_size += 24;
3823
3824 /* Don't starve jumbo frames */
3825 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3826
6eb5a7f1
AD		 3827 /* Give a little boost to mid-size frames */
3828 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3829 new_val = avg_wire_size / 3;
3830 else
3831 new_val = avg_wire_size / 2;
9d5c8243 3832
0ba82994
AD		 3833 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3834 if (new_val < IGB_20K_ITR &&
3835 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3836 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3837 new_val = IGB_20K_ITR;
abe1c363 3838
6eb5a7f1 3839set_itr_val:
047e0030
AD		 3840 if (new_val != q_vector->itr_val) {
3841 q_vector->itr_val = new_val;
3842 q_vector->set_itr = 1;
9d5c8243 3843 }
6eb5a7f1 3844clear_counts:
0ba82994
AD		 3845 q_vector->rx.total_bytes = 0;
3846 q_vector->rx.total_packets = 0;
3847 q_vector->tx.total_bytes = 0;
3848 q_vector->tx.total_packets = 0;
9d5c8243
AK		 3849}
3850
3851/**
3852 * igb_update_itr - update the dynamic ITR value based on statistics
3853 * Stores a new ITR value based on packets and byte
3854 * counts during the last interrupt. The advantage of per interrupt
3855 * computation is faster updates and more accurate ITR for the current
3856 * traffic pattern. Constants in this function were computed
3857 * based on theoretical maximum wire speed and thresholds were set based
3858 * on testing data as well as attempting to minimize response time
3859 * while increasing bulk throughput.
3860 * this functionality is controlled by the InterruptThrottleRate module
3861 * parameter (see igb_param.c)
3862 * NOTE: These calculations are only valid when operating in a single-
3863 * queue environment.
0ba82994
AD		 3864 * @q_vector: pointer to q_vector
3865 * @ring_container: ring info to update the itr for
9d5c8243 3866 **/
0ba82994
AD		 3867static void igb_update_itr(struct igb_q_vector *q_vector,
3868 struct igb_ring_container *ring_container)
9d5c8243 3869{
0ba82994
AD		 3870 unsigned int packets = ring_container->total_packets;
3871 unsigned int bytes = ring_container->total_bytes;
3872 u8 itrval = ring_container->itr;
9d5c8243 3873
0ba82994 3874 /* no packets, exit with status unchanged */
9d5c8243 3875 if (packets == 0)
0ba82994 3876 return;
9d5c8243 3877
0ba82994 3878 switch (itrval) {
9d5c8243
AK		 3879 case lowest_latency:
3880 /* handle TSO and jumbo frames */
3881 if (bytes/packets > 8000)
0ba82994 3882 itrval = bulk_latency;
9d5c8243 3883 else if ((packets < 5) && (bytes > 512))
0ba82994 3884 itrval = low_latency;
9d5c8243
AK		 3885 break;
3886 case low_latency: /* 50 usec aka 20000 ints/s */
3887 if (bytes > 10000) {
3888 /* this if handles the TSO accounting */
3889 if (bytes/packets > 8000) {
0ba82994 3890 itrval = bulk_latency;
9d5c8243 3891 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 3892 itrval = bulk_latency;
9d5c8243 3893 } else if ((packets > 35)) {
0ba82994 3894 itrval = lowest_latency;
9d5c8243
AK		 3895 }
3896 } else if (bytes/packets > 2000) {
0ba82994 3897 itrval = bulk_latency;
9d5c8243 3898 } else if (packets <= 2 && bytes < 512) {
0ba82994 3899 itrval = lowest_latency;
9d5c8243
AK		 3900 }
3901 break;
3902 case bulk_latency: /* 250 usec aka 4000 ints/s */
3903 if (bytes > 25000) {
3904 if (packets > 35)
0ba82994 3905 itrval = low_latency;
1e5c3d21 3906 } else if (bytes < 1500) {
0ba82994 3907 itrval = low_latency;
9d5c8243
AK		 3908 }
3909 break;
3910 }
3911
0ba82994
AD		 3912 /* clear work counters since we have the values we need */
3913 ring_container->total_bytes = 0;
3914 ring_container->total_packets = 0;
3915
3916 /* write updated itr to ring container */
3917 ring_container->itr = itrval;
9d5c8243
AK		 3918}
3919
0ba82994 3920static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 3921{
0ba82994 3922 struct igb_adapter *adapter = q_vector->adapter;
047e0030 3923 u32 new_itr = q_vector->itr_val;
0ba82994 3924 u8 current_itr = 0;
9d5c8243
AK		 3925
3926 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3927 if (adapter->link_speed != SPEED_1000) {
3928 current_itr = 0;
0ba82994 3929 new_itr = IGB_4K_ITR;
9d5c8243
AK		 3930 goto set_itr_now;
3931 }
3932
0ba82994
AD		 3933 igb_update_itr(q_vector, &q_vector->tx);
3934 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 3935
0ba82994 3936 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 3937
6eb5a7f1 3938 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 3939 if (current_itr == lowest_latency &&
3940 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3941 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 3942 current_itr = low_latency;
3943
9d5c8243
AK		 3944 switch (current_itr) {
3945 /* counts and packets in update_itr are dependent on these numbers */
3946 case lowest_latency:
0ba82994 3947 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 3948 break;
3949 case low_latency:
0ba82994 3950 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 3951 break;
3952 case bulk_latency:
0ba82994 3953 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 3954 break;
3955 default:
3956 break;
3957 }
3958
3959set_itr_now:
047e0030 3960 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3961 /* this attempts to bias the interrupt rate towards Bulk
3962 * by adding intermediate steps when interrupt rate is
3963 * increasing */
047e0030
AD		 3964 new_itr = new_itr > q_vector->itr_val ?
3965 max((new_itr * q_vector->itr_val) /
3966 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 3967 new_itr) :
9d5c8243
AK		 3968 new_itr;
3969 /* Don't write the value here; it resets the adapter's
3970 * internal timer, and causes us to delay far longer than
3971 * we should between interrupts. Instead, we write the ITR
3972 * value at the beginning of the next interrupt so the timing
3973 * ends up being correct.
3974 */
047e0030
AD		 3975 q_vector->itr_val = new_itr;
3976 q_vector->set_itr = 1;
9d5c8243 3977 }
9d5c8243
AK		 3978}
3979
c50b52a0
SH		 3980static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3981 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 3982{
3983 struct e1000_adv_tx_context_desc *context_desc;
3984 u16 i = tx_ring->next_to_use;
3985
3986 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3987
3988 i++;
3989 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3990
3991 /* set bits to identify this as an advanced context descriptor */
3992 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
3993
3994 /* For 82575, context index must be unique per ring. */
866cff06 3995 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 3996 mss_l4len_idx |= tx_ring->reg_idx << 4;
3997
3998 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3999 context_desc->seqnum_seed = 0;
4000 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4001 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4002}
4003
7af40ad9
AD		 4004static int igb_tso(struct igb_ring *tx_ring,
4005 struct igb_tx_buffer *first,
4006 u8 *hdr_len)
9d5c8243 4007{
7af40ad9 4008 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4009 u32 vlan_macip_lens, type_tucmd;
4010 u32 mss_l4len_idx, l4len;
4011
ed6aa105
AD		 4012 if (skb->ip_summed != CHECKSUM_PARTIAL)
4013 return 0;
4014
7d13a7d0
AD		 4015 if (!skb_is_gso(skb))
4016 return 0;
9d5c8243
AK		 4017
4018 if (skb_header_cloned(skb)) {
7af40ad9 4019 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4020 if (err)
4021 return err;
4022 }
4023
7d13a7d0
AD		 4024 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4025 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4026
7af40ad9 4027 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4028 struct iphdr *iph = ip_hdr(skb);
4029 iph->tot_len = 0;
4030 iph->check = 0;
4031 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4032 iph->daddr, 0,
4033 IPPROTO_TCP,
4034 0);
7d13a7d0 4035 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4036 first->tx_flags |= IGB_TX_FLAGS_TSO |
4037 IGB_TX_FLAGS_CSUM |
4038 IGB_TX_FLAGS_IPV4;
8e1e8a47 4039 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4040 ipv6_hdr(skb)->payload_len = 0;
4041 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4042 &ipv6_hdr(skb)->daddr,
4043 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4044 first->tx_flags |= IGB_TX_FLAGS_TSO |
4045 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4046 }
4047
7af40ad9 4048 /* compute header lengths */
7d13a7d0
AD		 4049 l4len = tcp_hdrlen(skb);
4050 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4051
7af40ad9
AD		 4052 /* update gso size and bytecount with header size */
4053 first->gso_segs = skb_shinfo(skb)->gso_segs;
4054 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4055
9d5c8243 4056 /* MSS L4LEN IDX */
7d13a7d0
AD		 4057 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4058 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4059
7d13a7d0
AD		 4060 /* VLAN MACLEN IPLEN */
4061 vlan_macip_lens = skb_network_header_len(skb);
4062 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4063 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4064
7d13a7d0 4065 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4066
7d13a7d0 4067 return 1;
9d5c8243
AK		 4068}
4069
7af40ad9 4070static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4071{
7af40ad9 4072 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4073 u32 vlan_macip_lens = 0;
4074 u32 mss_l4len_idx = 0;
4075 u32 type_tucmd = 0;
9d5c8243 4076
7d13a7d0 4077 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4078 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4079 return;
7d13a7d0
AD		 4080 } else {
4081 u8 l4_hdr = 0;
7af40ad9 4082 switch (first->protocol) {
7d13a7d0
AD		 4083 case __constant_htons(ETH_P_IP):
4084 vlan_macip_lens |= skb_network_header_len(skb);
4085 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4086 l4_hdr = ip_hdr(skb)->protocol;
4087 break;
4088 case __constant_htons(ETH_P_IPV6):
4089 vlan_macip_lens |= skb_network_header_len(skb);
4090 l4_hdr = ipv6_hdr(skb)->nexthdr;
4091 break;
4092 default:
4093 if (unlikely(net_ratelimit())) {
4094 dev_warn(tx_ring->dev,
4095 "partial checksum but proto=%x!\n",
7af40ad9 4096 first->protocol);
fa4a7ef3 4097 }
7d13a7d0
AD		 4098 break;
4099 }
fa4a7ef3 4100
7d13a7d0
AD		 4101 switch (l4_hdr) {
4102 case IPPROTO_TCP:
4103 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4104 mss_l4len_idx = tcp_hdrlen(skb) <<
4105 E1000_ADVTXD_L4LEN_SHIFT;
4106 break;
4107 case IPPROTO_SCTP:
4108 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4109 mss_l4len_idx = sizeof(struct sctphdr) <<
4110 E1000_ADVTXD_L4LEN_SHIFT;
4111 break;
4112 case IPPROTO_UDP:
4113 mss_l4len_idx = sizeof(struct udphdr) <<
4114 E1000_ADVTXD_L4LEN_SHIFT;
4115 break;
4116 default:
4117 if (unlikely(net_ratelimit())) {
4118 dev_warn(tx_ring->dev,
4119 "partial checksum but l4 proto=%x!\n",
4120 l4_hdr);
44b0cda3 4121 }
7d13a7d0 4122 break;
9d5c8243 4123 }
7af40ad9
AD		 4124
4125 /* update TX checksum flag */
4126 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4127 }
9d5c8243 4128
7d13a7d0 4129 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4130 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4131
7d13a7d0 4132 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4133}
4134
1d9daf45
AD		 4135#define IGB_SET_FLAG(_input, _flag, _result) \
4136 ((_flag <= _result) ? \
4137 ((u32)(_input & _flag) * (_result / _flag)) : \
4138 ((u32)(_input & _flag) / (_flag / _result)))
4139
4140static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4141{
4142 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4143 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4144 E1000_ADVTXD_DCMD_DEXT |
4145 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4146
4147 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4148 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4149 (E1000_ADVTXD_DCMD_VLE));
4150
4151 /* set segmentation bits for TSO */
4152 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4153 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4154
4155 /* set timestamp bit if present */
1d9daf45
AD		 4156 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4157 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4158
1d9daf45
AD		 4159 /* insert frame checksum */
4160 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4161
4162 return cmd_type;
4163}
4164
7af40ad9
AD		 4165static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4166 union e1000_adv_tx_desc *tx_desc,
4167 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4168{
4169 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4170
1d9daf45
AD		 4171 /* 82575 requires a unique index per ring */
4172 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4173 olinfo_status |= tx_ring->reg_idx << 4;
4174
4175 /* insert L4 checksum */
1d9daf45
AD		 4176 olinfo_status |= IGB_SET_FLAG(tx_flags,
4177 IGB_TX_FLAGS_CSUM,
4178 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4179
1d9daf45
AD		 4180 /* insert IPv4 checksum */
4181 olinfo_status |= IGB_SET_FLAG(tx_flags,
4182 IGB_TX_FLAGS_IPV4,
4183 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4184
7af40ad9 4185 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4186}
4187
ebe42d16
AD		 4188/*
4189 * The largest size we can write to the descriptor is 65535. In order to
4190 * maintain a power of two alignment we have to limit ourselves to 32K.
4191 */
4192#define IGB_MAX_TXD_PWR 15
7af40ad9 4193#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4194
7af40ad9
AD		 4195static void igb_tx_map(struct igb_ring *tx_ring,
4196 struct igb_tx_buffer *first,
ebe42d16 4197 const u8 hdr_len)
9d5c8243 4198{
7af40ad9 4199 struct sk_buff *skb = first->skb;
c9f14bf3 4200 struct igb_tx_buffer *tx_buffer;
ebe42d16 4201 union e1000_adv_tx_desc *tx_desc;
80d0759e 4202 struct skb_frag_struct *frag;
ebe42d16 4203 dma_addr_t dma;
80d0759e 4204 unsigned int data_len, size;
7af40ad9 4205 u32 tx_flags = first->tx_flags;
1d9daf45 4206 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4207 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4208
4209 tx_desc = IGB_TX_DESC(tx_ring, i);
4210
80d0759e
AD		 4211 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4212
4213 size = skb_headlen(skb);
4214 data_len = skb->data_len;
ebe42d16
AD		 4215
4216 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4217
80d0759e
AD		 4218 tx_buffer = first;
4219
4220 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4221 if (dma_mapping_error(tx_ring->dev, dma))
4222 goto dma_error;
4223
4224 /* record length, and DMA address */
4225 dma_unmap_len_set(tx_buffer, len, size);
4226 dma_unmap_addr_set(tx_buffer, dma, dma);
4227
4228 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4229
ebe42d16
AD		 4230 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4231 tx_desc->read.cmd_type_len =
1d9daf45 4232 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4233
4234 i++;
4235 tx_desc++;
4236 if (i == tx_ring->count) {
4237 tx_desc = IGB_TX_DESC(tx_ring, 0);
4238 i = 0;
4239 }
80d0759e 4240 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4241
4242 dma += IGB_MAX_DATA_PER_TXD;
4243 size -= IGB_MAX_DATA_PER_TXD;
4244
ebe42d16
AD		 4245 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4246 }
4247
4248 if (likely(!data_len))
4249 break;
2bbfebe2 4250
1d9daf45 4251 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4252
65689fef 4253 i++;
ebe42d16
AD		 4254 tx_desc++;
4255 if (i == tx_ring->count) {
4256 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4257 i = 0;
ebe42d16 4258 }
80d0759e 4259 tx_desc->read.olinfo_status = 0;
65689fef 4260
9e903e08 4261 size = skb_frag_size(frag);
ebe42d16
AD		 4262 data_len -= size;
4263
4264 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4265 size, DMA_TO_DEVICE);
6366ad33 4266
c9f14bf3 4267 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4268 }
4269
ebe42d16 4270 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4271 cmd_type |= size | IGB_TXD_DCMD;
4272 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4273
80d0759e
AD		 4274 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4275
8542db05
AD		 4276 /* set the timestamp */
4277 first->time_stamp = jiffies;
4278
ebe42d16
AD		 4279 /*
4280 * Force memory writes to complete before letting h/w know there
4281 * are new descriptors to fetch. (Only applicable for weak-ordered
4282 * memory model archs, such as IA-64).
4283 *
4284 * We also need this memory barrier to make certain all of the
4285 * status bits have been updated before next_to_watch is written.
4286 */
4287 wmb();
4288
8542db05 4289 /* set next_to_watch value indicating a packet is present */
ebe42d16 4290 first->next_to_watch = tx_desc;
9d5c8243 4291
ebe42d16
AD		 4292 i++;
4293 if (i == tx_ring->count)
4294 i = 0;
6366ad33 4295
ebe42d16 4296 tx_ring->next_to_use = i;
6366ad33 4297
ebe42d16 4298 writel(i, tx_ring->tail);
6366ad33 4299
ebe42d16
AD		 4300 /* we need this if more than one processor can write to our tail
4301 * at a time, it syncronizes IO on IA64/Altix systems */
4302 mmiowb();
4303
4304 return;
4305
4306dma_error:
4307 dev_err(tx_ring->dev, "TX DMA map failed\n");
4308
4309 /* clear dma mappings for failed tx_buffer_info map */
4310 for (;;) {
c9f14bf3
AD		 4311 tx_buffer = &tx_ring->tx_buffer_info[i];
4312 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4313 if (tx_buffer == first)
ebe42d16 4314 break;
a77ff709
NN		 4315 if (i == 0)
4316 i = tx_ring->count;
6366ad33 4317 i--;
6366ad33
AD		 4318 }
4319
9d5c8243 4320 tx_ring->next_to_use = i;
9d5c8243
AK		 4321}
4322
6ad4edfc 4323static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4324{
e694e964
AD		 4325 struct net_device *netdev = tx_ring->netdev;
4326
661086df 4327 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4328
9d5c8243
AK		 4329 /* Herbert's original patch had:
4330 * smp_mb__after_netif_stop_queue();
4331 * but since that doesn't exist yet, just open code it. */
4332 smp_mb();
4333
4334 /* We need to check again in a case another CPU has just
4335 * made room available. */
c493ea45 4336 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4337 return -EBUSY;
4338
4339 /* A reprieve! */
661086df 4340 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4341
4342 u64_stats_update_begin(&tx_ring->tx_syncp2);
4343 tx_ring->tx_stats.restart_queue2++;
4344 u64_stats_update_end(&tx_ring->tx_syncp2);
4345
9d5c8243
AK		 4346 return 0;
4347}
4348
6ad4edfc 4349static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4350{
c493ea45 4351 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4352 return 0;
e694e964 4353 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4354}
4355
cd392f5c
AD		 4356netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4357 struct igb_ring *tx_ring)
9d5c8243 4358{
1f6e8178 4359 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4360 struct igb_tx_buffer *first;
ebe42d16 4361 int tso;
91d4ee33 4362 u32 tx_flags = 0;
31f6adbb 4363 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4364 u8 hdr_len = 0;
9d5c8243 4365
9d5c8243
AK		 4366 /* need: 1 descriptor per page,
4367 * + 2 desc gap to keep tail from touching head,
4368 * + 1 desc for skb->data,
4369 * + 1 desc for context descriptor,
4370 * otherwise try next time */
e694e964 4371 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4372 /* this is a hard error */
9d5c8243
AK		 4373 return NETDEV_TX_BUSY;
4374 }
33af6bcc 4375
7af40ad9
AD		 4376 /* record the location of the first descriptor for this packet */
4377 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4378 first->skb = skb;
4379 first->bytecount = skb->len;
4380 first->gso_segs = 1;
4381
1f6e8178
MV		 4382 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4383 !(adapter->ptp_tx_skb))) {
2244d07b 4384 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4385 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4386
4387 adapter->ptp_tx_skb = skb_get(skb);
4388 if (adapter->hw.mac.type == e1000_82576)
4389 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4390 }
9d5c8243 4391
eab6d18d 4392 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4393 tx_flags |= IGB_TX_FLAGS_VLAN;
4394 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4395 }
4396
7af40ad9
AD		 4397 /* record initial flags and protocol */
4398 first->tx_flags = tx_flags;
4399 first->protocol = protocol;
cdfd01fc 4400
7af40ad9
AD		 4401 tso = igb_tso(tx_ring, first, &hdr_len);
4402 if (tso < 0)
7d13a7d0 4403 goto out_drop;
7af40ad9
AD		 4404 else if (!tso)
4405 igb_tx_csum(tx_ring, first);
9d5c8243 4406
7af40ad9 4407 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4408
4409 /* Make sure there is space in the ring for the next send. */
e694e964 4410 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4411
9d5c8243 4412 return NETDEV_TX_OK;
7d13a7d0
AD		 4413
4414out_drop:
7af40ad9
AD		 4415 igb_unmap_and_free_tx_resource(tx_ring, first);
4416
7d13a7d0 4417 return NETDEV_TX_OK;
9d5c8243
AK		 4418}
4419
1cc3bd87
AD		 4420static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4421 struct sk_buff *skb)
4422{
4423 unsigned int r_idx = skb->queue_mapping;
4424
4425 if (r_idx >= adapter->num_tx_queues)
4426 r_idx = r_idx % adapter->num_tx_queues;
4427
4428 return adapter->tx_ring[r_idx];
4429}
4430
cd392f5c
AD		 4431static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4432 struct net_device *netdev)
9d5c8243
AK		 4433{
4434 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4435
4436 if (test_bit(__IGB_DOWN, &adapter->state)) {
4437 dev_kfree_skb_any(skb);
4438 return NETDEV_TX_OK;
4439 }
4440
4441 if (skb->len <= 0) {
4442 dev_kfree_skb_any(skb);
4443 return NETDEV_TX_OK;
4444 }
4445
1cc3bd87
AD		 4446 /*
4447 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4448 * in order to meet this minimum size requirement.
4449 */
ea5ceeab
TD		 4450 if (unlikely(skb->len < 17)) {
4451 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4452 return NETDEV_TX_OK;
4453 skb->len = 17;
ea5ceeab 4454 skb_set_tail_pointer(skb, 17);
1cc3bd87 4455 }
9d5c8243 4456
1cc3bd87 4457 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4458}
4459
4460/**
4461 * igb_tx_timeout - Respond to a Tx Hang
4462 * @netdev: network interface device structure
4463 **/
4464static void igb_tx_timeout(struct net_device *netdev)
4465{
4466 struct igb_adapter *adapter = netdev_priv(netdev);
4467 struct e1000_hw *hw = &adapter->hw;
4468
4469 /* Do the reset outside of interrupt context */
4470 adapter->tx_timeout_count++;
f7ba205e 4471
06218a8d 4472 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4473 hw->dev_spec._82575.global_device_reset = true;
4474
9d5c8243 4475 schedule_work(&adapter->reset_task);
265de409
AD		 4476 wr32(E1000_EICS,
4477 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4478}
4479
4480static void igb_reset_task(struct work_struct *work)
4481{
4482 struct igb_adapter *adapter;
4483 adapter = container_of(work, struct igb_adapter, reset_task);
4484
c97ec42a
TI		 4485 igb_dump(adapter);
4486 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4487 igb_reinit_locked(adapter);
4488}
4489
4490/**
12dcd86b 4491 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4492 * @netdev: network interface device structure
12dcd86b 4493 * @stats: rtnl_link_stats64 pointer
9d5c8243 4494 *
9d5c8243 4495 **/
12dcd86b
ED		 4496static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4497 struct rtnl_link_stats64 *stats)
9d5c8243 4498{
12dcd86b
ED		 4499 struct igb_adapter *adapter = netdev_priv(netdev);
4500
4501 spin_lock(&adapter->stats64_lock);
4502 igb_update_stats(adapter, &adapter->stats64);
4503 memcpy(stats, &adapter->stats64, sizeof(*stats));
4504 spin_unlock(&adapter->stats64_lock);
4505
4506 return stats;
9d5c8243
AK		 4507}
4508
4509/**
4510 * igb_change_mtu - Change the Maximum Transfer Unit
4511 * @netdev: network interface device structure
4512 * @new_mtu: new value for maximum frame size
4513 *
4514 * Returns 0 on success, negative on failure
4515 **/
4516static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4517{
4518 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4519 struct pci_dev *pdev = adapter->pdev;
153285f9 4520 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4521
c809d227 4522 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4523 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4524 return -EINVAL;
4525 }
4526
153285f9 4527#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4528 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4529 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4530 return -EINVAL;
4531 }
4532
4533 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4534 msleep(1);
73cd78f1 4535
9d5c8243
AK		 4536 /* igb_down has a dependency on max_frame_size */
4537 adapter->max_frame_size = max_frame;
559e9c49 4538
4c844851
AD		 4539 if (netif_running(netdev))
4540 igb_down(adapter);
9d5c8243 4541
090b1795 4542 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4543 netdev->mtu, new_mtu);
4544 netdev->mtu = new_mtu;
4545
4546 if (netif_running(netdev))
4547 igb_up(adapter);
4548 else
4549 igb_reset(adapter);
4550
4551 clear_bit(__IGB_RESETTING, &adapter->state);
4552
4553 return 0;
4554}
4555
4556/**
4557 * igb_update_stats - Update the board statistics counters
4558 * @adapter: board private structure
4559 **/
4560
12dcd86b
ED		 4561void igb_update_stats(struct igb_adapter *adapter,
4562 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4563{
4564 struct e1000_hw *hw = &adapter->hw;
4565 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4566 u32 reg, mpc;
9d5c8243 4567 u16 phy_tmp;
3f9c0164
AD		 4568 int i;
4569 u64 bytes, packets;
12dcd86b
ED		 4570 unsigned int start;
4571 u64 _bytes, _packets;
9d5c8243
AK		 4572
4573#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4574
4575 /*
4576 * Prevent stats update while adapter is being reset, or if the pci
4577 * connection is down.
4578 */
4579 if (adapter->link_speed == 0)
4580 return;
4581 if (pci_channel_offline(pdev))
4582 return;
4583
3f9c0164
AD		 4584 bytes = 0;
4585 packets = 0;
4586 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4587 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4588 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4589
ae1c07a6
AD		 4590 if (rqdpc) {
4591 ring->rx_stats.drops += rqdpc;
4592 net_stats->rx_fifo_errors += rqdpc;
4593 }
12dcd86b
ED		 4594
4595 do {
4596 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4597 _bytes = ring->rx_stats.bytes;
4598 _packets = ring->rx_stats.packets;
4599 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4600 bytes += _bytes;
4601 packets += _packets;
3f9c0164
AD		 4602 }
4603
128e45eb
AD		 4604 net_stats->rx_bytes = bytes;
4605 net_stats->rx_packets = packets;
3f9c0164
AD		 4606
4607 bytes = 0;
4608 packets = 0;
4609 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4610 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4611 do {
4612 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4613 _bytes = ring->tx_stats.bytes;
4614 _packets = ring->tx_stats.packets;
4615 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4616 bytes += _bytes;
4617 packets += _packets;
3f9c0164 4618 }
128e45eb
AD		 4619 net_stats->tx_bytes = bytes;
4620 net_stats->tx_packets = packets;
3f9c0164
AD		 4621
4622 /* read stats registers */
9d5c8243
AK		 4623 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4624 adapter->stats.gprc += rd32(E1000_GPRC);
4625 adapter->stats.gorc += rd32(E1000_GORCL);
4626 rd32(E1000_GORCH); /* clear GORCL */
4627 adapter->stats.bprc += rd32(E1000_BPRC);
4628 adapter->stats.mprc += rd32(E1000_MPRC);
4629 adapter->stats.roc += rd32(E1000_ROC);
4630
4631 adapter->stats.prc64 += rd32(E1000_PRC64);
4632 adapter->stats.prc127 += rd32(E1000_PRC127);
4633 adapter->stats.prc255 += rd32(E1000_PRC255);
4634 adapter->stats.prc511 += rd32(E1000_PRC511);
4635 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4636 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4637 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4638 adapter->stats.sec += rd32(E1000_SEC);
4639
fa3d9a6d
MW		 4640 mpc = rd32(E1000_MPC);
4641 adapter->stats.mpc += mpc;
4642 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4643 adapter->stats.scc += rd32(E1000_SCC);
4644 adapter->stats.ecol += rd32(E1000_ECOL);
4645 adapter->stats.mcc += rd32(E1000_MCC);
4646 adapter->stats.latecol += rd32(E1000_LATECOL);
4647 adapter->stats.dc += rd32(E1000_DC);
4648 adapter->stats.rlec += rd32(E1000_RLEC);
4649 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4650 adapter->stats.xontxc += rd32(E1000_XONTXC);
4651 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4652 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4653 adapter->stats.fcruc += rd32(E1000_FCRUC);
4654 adapter->stats.gptc += rd32(E1000_GPTC);
4655 adapter->stats.gotc += rd32(E1000_GOTCL);
4656 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4657 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4658 adapter->stats.ruc += rd32(E1000_RUC);
4659 adapter->stats.rfc += rd32(E1000_RFC);
4660 adapter->stats.rjc += rd32(E1000_RJC);
4661 adapter->stats.tor += rd32(E1000_TORH);
4662 adapter->stats.tot += rd32(E1000_TOTH);
4663 adapter->stats.tpr += rd32(E1000_TPR);
4664
4665 adapter->stats.ptc64 += rd32(E1000_PTC64);
4666 adapter->stats.ptc127 += rd32(E1000_PTC127);
4667 adapter->stats.ptc255 += rd32(E1000_PTC255);
4668 adapter->stats.ptc511 += rd32(E1000_PTC511);
4669 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4670 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4671
4672 adapter->stats.mptc += rd32(E1000_MPTC);
4673 adapter->stats.bptc += rd32(E1000_BPTC);
4674
2d0b0f69
NN		 4675 adapter->stats.tpt += rd32(E1000_TPT);
4676 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4677
4678 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4679 /* read internal phy specific stats */
4680 reg = rd32(E1000_CTRL_EXT);
4681 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4682 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4683
4684 /* this stat has invalid values on i210/i211 */
4685 if ((hw->mac.type != e1000_i210) &&
4686 (hw->mac.type != e1000_i211))
4687 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4688 }
4689
9d5c8243
AK		 4690 adapter->stats.tsctc += rd32(E1000_TSCTC);
4691 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4692
4693 adapter->stats.iac += rd32(E1000_IAC);
4694 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4695 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4696 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4697 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4698 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4699 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4700 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4701 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4702
4703 /* Fill out the OS statistics structure */
128e45eb
AD		 4704 net_stats->multicast = adapter->stats.mprc;
4705 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4706
4707 /* Rx Errors */
4708
4709 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4710 * our own version based on RUC and ROC */
128e45eb 4711 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4712 adapter->stats.crcerrs + adapter->stats.algnerrc +
4713 adapter->stats.ruc + adapter->stats.roc +
4714 adapter->stats.cexterr;
128e45eb
AD		 4715 net_stats->rx_length_errors = adapter->stats.ruc +
4716 adapter->stats.roc;
4717 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4718 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4719 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4720
4721 /* Tx Errors */
128e45eb
AD		 4722 net_stats->tx_errors = adapter->stats.ecol +
4723 adapter->stats.latecol;
4724 net_stats->tx_aborted_errors = adapter->stats.ecol;
4725 net_stats->tx_window_errors = adapter->stats.latecol;
4726 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4727
4728 /* Tx Dropped needs to be maintained elsewhere */
4729
4730 /* Phy Stats */
4731 if (hw->phy.media_type == e1000_media_type_copper) {
4732 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4733 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4734 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4735 adapter->phy_stats.idle_errors += phy_tmp;
4736 }
4737 }
4738
4739 /* Management Stats */
4740 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4741 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4742 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4743
4744 /* OS2BMC Stats */
4745 reg = rd32(E1000_MANC);
4746 if (reg & E1000_MANC_EN_BMC2OS) {
4747 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4748 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4749 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4750 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4751 }
9d5c8243
AK		 4752}
4753
9d5c8243
AK		 4754static irqreturn_t igb_msix_other(int irq, void *data)
4755{
047e0030 4756 struct igb_adapter *adapter = data;
9d5c8243 4757 struct e1000_hw *hw = &adapter->hw;
844290e5 4758 u32 icr = rd32(E1000_ICR);
844290e5 4759 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4760
7f081d40
AD		 4761 if (icr & E1000_ICR_DRSTA)
4762 schedule_work(&adapter->reset_task);
4763
047e0030 4764 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4765 /* HW is reporting DMA is out of sync */
4766 adapter->stats.doosync++;
13800469
GR		 4767 /* The DMA Out of Sync is also indication of a spoof event
4768 * in IOV mode. Check the Wrong VM Behavior register to
4769 * see if it is really a spoof event. */
4770 igb_check_wvbr(adapter);
dda0e083 4771 }
eebbbdba 4772
4ae196df
AD		 4773 /* Check for a mailbox event */
4774 if (icr & E1000_ICR_VMMB)
4775 igb_msg_task(adapter);
4776
4777 if (icr & E1000_ICR_LSC) {
4778 hw->mac.get_link_status = 1;
4779 /* guard against interrupt when we're going down */
4780 if (!test_bit(__IGB_DOWN, &adapter->state))
4781 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4782 }
4783
1f6e8178
MV		 4784 if (icr & E1000_ICR_TS) {
4785 u32 tsicr = rd32(E1000_TSICR);
4786
4787 if (tsicr & E1000_TSICR_TXTS) {
4788 /* acknowledge the interrupt */
4789 wr32(E1000_TSICR, E1000_TSICR_TXTS);
4790 /* retrieve hardware timestamp */
4791 schedule_work(&adapter->ptp_tx_work);
4792 }
4793 }
1f6e8178 4794
844290e5 4795 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4796
4797 return IRQ_HANDLED;
4798}
4799
047e0030 4800static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4801{
26b39276 4802 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4803 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4804
047e0030
AD		 4805 if (!q_vector->set_itr)
4806 return;
73cd78f1 4807
047e0030
AD		 4808 if (!itr_val)
4809 itr_val = 0x4;
661086df 4810
26b39276
AD		 4811 if (adapter->hw.mac.type == e1000_82575)
4812 itr_val |= itr_val << 16;
661086df 4813 else
0ba82994 4814 itr_val |= E1000_EITR_CNT_IGNR;
661086df 4815
047e0030
AD		 4816 writel(itr_val, q_vector->itr_register);
4817 q_vector->set_itr = 0;
6eb5a7f1
AD		 4818}
4819
047e0030 4820static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4821{
047e0030 4822 struct igb_q_vector *q_vector = data;
9d5c8243 4823
047e0030
AD		 4824 /* Write the ITR value calculated from the previous interrupt. */
4825 igb_write_itr(q_vector);
9d5c8243 4826
047e0030 4827 napi_schedule(&q_vector->napi);
844290e5 4828
047e0030 4829 return IRQ_HANDLED;
fe4506b6
JC		 4830}
4831
421e02f0 4832#ifdef CONFIG_IGB_DCA
6a05004a
AD		 4833static void igb_update_tx_dca(struct igb_adapter *adapter,
4834 struct igb_ring *tx_ring,
4835 int cpu)
4836{
4837 struct e1000_hw *hw = &adapter->hw;
4838 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4839
4840 if (hw->mac.type != e1000_82575)
4841 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4842
4843 /*
4844 * We can enable relaxed ordering for reads, but not writes when
4845 * DCA is enabled. This is due to a known issue in some chipsets
4846 * which will cause the DCA tag to be cleared.
4847 */
4848 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4849 E1000_DCA_TXCTRL_DATA_RRO_EN |
4850 E1000_DCA_TXCTRL_DESC_DCA_EN;
4851
4852 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4853}
4854
4855static void igb_update_rx_dca(struct igb_adapter *adapter,
4856 struct igb_ring *rx_ring,
4857 int cpu)
4858{
4859 struct e1000_hw *hw = &adapter->hw;
4860 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4861
4862 if (hw->mac.type != e1000_82575)
4863 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4864
4865 /*
4866 * We can enable relaxed ordering for reads, but not writes when
4867 * DCA is enabled. This is due to a known issue in some chipsets
4868 * which will cause the DCA tag to be cleared.
4869 */
4870 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4871 E1000_DCA_RXCTRL_DESC_DCA_EN;
4872
4873 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4874}
4875
047e0030 4876static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4877{
047e0030 4878 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 4879 int cpu = get_cpu();
fe4506b6 4880
047e0030
AD		 4881 if (q_vector->cpu == cpu)
4882 goto out_no_update;
4883
6a05004a
AD		 4884 if (q_vector->tx.ring)
4885 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4886
4887 if (q_vector->rx.ring)
4888 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4889
047e0030
AD		 4890 q_vector->cpu = cpu;
4891out_no_update:
fe4506b6
JC		 4892 put_cpu();
4893}
4894
4895static void igb_setup_dca(struct igb_adapter *adapter)
4896{
7e0e99ef 4897 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4898 int i;
4899
7dfc16fa 4900 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4901 return;
4902
7e0e99ef
AD		 4903 /* Always use CB2 mode, difference is masked in the CB driver. */
4904 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4905
047e0030 4906 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4907 adapter->q_vector[i]->cpu = -1;
4908 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4909 }
4910}
4911
4912static int __igb_notify_dca(struct device *dev, void *data)
4913{
4914 struct net_device *netdev = dev_get_drvdata(dev);
4915 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4916 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4917 struct e1000_hw *hw = &adapter->hw;
4918 unsigned long event = *(unsigned long *)data;
4919
4920 switch (event) {
4921 case DCA_PROVIDER_ADD:
4922 /* if already enabled, don't do it again */
7dfc16fa 4923 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4924 break;
fe4506b6 4925 if (dca_add_requester(dev) == 0) {
bbd98fe4 4926 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4927 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4928 igb_setup_dca(adapter);
4929 break;
4930 }
4931 /* Fall Through since DCA is disabled. */
4932 case DCA_PROVIDER_REMOVE:
7dfc16fa 4933 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4934 /* without this a class_device is left
047e0030 4935 * hanging around in the sysfs model */
fe4506b6 4936 dca_remove_requester(dev);
090b1795 4937 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4938 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4939 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4940 }
4941 break;
4942 }
bbd98fe4 4943
fe4506b6 4944 return 0;
9d5c8243
AK		 4945}
4946
fe4506b6
JC		 4947static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4948 void *p)
4949{
4950 int ret_val;
4951
4952 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4953 __igb_notify_dca);
4954
4955 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4956}
421e02f0 4957#endif /* CONFIG_IGB_DCA */
9d5c8243 4958
0224d663
GR		 4959#ifdef CONFIG_PCI_IOV
4960static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4961{
4962 unsigned char mac_addr[ETH_ALEN];
0224d663 4963
7efd26d0 4964 eth_random_addr(mac_addr);
0224d663
GR		 4965 igb_set_vf_mac(adapter, vf, mac_addr);
4966
f557147c 4967 return 0;
0224d663
GR		 4968}
4969
f557147c 4970static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 4971{
0224d663 4972 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 4973 struct pci_dev *vfdev;
4974 int dev_id;
0224d663
GR		 4975
4976 switch (adapter->hw.mac.type) {
4977 case e1000_82576:
f557147c 4978 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 4979 break;
4980 case e1000_i350:
f557147c 4981 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 4982 break;
4983 default:
f557147c 4984 return false;
0224d663
GR		 4985 }
4986
f557147c
SA		 4987 /* loop through all the VFs to see if we own any that are assigned */
4988 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
4989 while (vfdev) {
4990 /* if we don't own it we don't care */
4991 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
4992 /* if it is assigned we cannot release it */
4993 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 4994 return true;
4995 }
f557147c
SA		 4996
4997 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 4998 }
f557147c 4999
0224d663
GR		 5000 return false;
5001}
5002
5003#endif
4ae196df
AD		 5004static void igb_ping_all_vfs(struct igb_adapter *adapter)
5005{
5006 struct e1000_hw *hw = &adapter->hw;
5007 u32 ping;
5008 int i;
5009
5010 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5011 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5012 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5013 ping |= E1000_VT_MSGTYPE_CTS;
5014 igb_write_mbx(hw, &ping, 1, i);
5015 }
5016}
5017
7d5753f0
AD		 5018static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5019{
5020 struct e1000_hw *hw = &adapter->hw;
5021 u32 vmolr = rd32(E1000_VMOLR(vf));
5022 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5023
d85b9004 5024 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5025 IGB_VF_FLAG_MULTI_PROMISC);
5026 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5027
5028 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5029 vmolr |= E1000_VMOLR_MPME;
d85b9004 5030 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5031 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5032 } else {
5033 /*
5034 * if we have hashes and we are clearing a multicast promisc
5035 * flag we need to write the hashes to the MTA as this step
5036 * was previously skipped
5037 */
5038 if (vf_data->num_vf_mc_hashes > 30) {
5039 vmolr |= E1000_VMOLR_MPME;
5040 } else if (vf_data->num_vf_mc_hashes) {
5041 int j;
5042 vmolr |= E1000_VMOLR_ROMPE;
5043 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5044 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5045 }
5046 }
5047
5048 wr32(E1000_VMOLR(vf), vmolr);
5049
5050 /* there are flags left unprocessed, likely not supported */
5051 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5052 return -EINVAL;
5053
5054 return 0;
5055
5056}
5057
4ae196df
AD		 5058static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5059 u32 *msgbuf, u32 vf)
5060{
5061 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5062 u16 *hash_list = (u16 *)&msgbuf[1];
5063 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5064 int i;
5065
7d5753f0 5066 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5067 * to this VF for later use to restore when the PF multi cast
5068 * list changes
5069 */
5070 vf_data->num_vf_mc_hashes = n;
5071
7d5753f0
AD		 5072 /* only up to 30 hash values supported */
5073 if (n > 30)
5074 n = 30;
5075
5076 /* store the hashes for later use */
4ae196df 5077 for (i = 0; i < n; i++)
a419aef8 5078 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5079
5080 /* Flush and reset the mta with the new values */
ff41f8dc 5081 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5082
5083 return 0;
5084}
5085
5086static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5087{
5088 struct e1000_hw *hw = &adapter->hw;
5089 struct vf_data_storage *vf_data;
5090 int i, j;
5091
5092 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5093 u32 vmolr = rd32(E1000_VMOLR(i));
5094 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5095
4ae196df 5096 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5097
5098 if ((vf_data->num_vf_mc_hashes > 30) ||
5099 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5100 vmolr |= E1000_VMOLR_MPME;
5101 } else if (vf_data->num_vf_mc_hashes) {
5102 vmolr |= E1000_VMOLR_ROMPE;
5103 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5104 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5105 }
5106 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5107 }
5108}
5109
5110static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5111{
5112 struct e1000_hw *hw = &adapter->hw;
5113 u32 pool_mask, reg, vid;
5114 int i;
5115
5116 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5117
5118 /* Find the vlan filter for this id */
5119 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5120 reg = rd32(E1000_VLVF(i));
5121
5122 /* remove the vf from the pool */
5123 reg &= ~pool_mask;
5124
5125 /* if pool is empty then remove entry from vfta */
5126 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5127 (reg & E1000_VLVF_VLANID_ENABLE)) {
5128 reg = 0;
5129 vid = reg & E1000_VLVF_VLANID_MASK;
5130 igb_vfta_set(hw, vid, false);
5131 }
5132
5133 wr32(E1000_VLVF(i), reg);
5134 }
ae641bdc
AD		 5135
5136 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5137}
5138
5139static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5140{
5141 struct e1000_hw *hw = &adapter->hw;
5142 u32 reg, i;
5143
51466239
AD		 5144 /* The vlvf table only exists on 82576 hardware and newer */
5145 if (hw->mac.type < e1000_82576)
5146 return -1;
5147
5148 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5149 if (!adapter->vfs_allocated_count)
5150 return -1;
5151
5152 /* Find the vlan filter for this id */
5153 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5154 reg = rd32(E1000_VLVF(i));
5155 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5156 vid == (reg & E1000_VLVF_VLANID_MASK))
5157 break;
5158 }
5159
5160 if (add) {
5161 if (i == E1000_VLVF_ARRAY_SIZE) {
5162 /* Did not find a matching VLAN ID entry that was
5163 * enabled. Search for a free filter entry, i.e.
5164 * one without the enable bit set
5165 */
5166 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5167 reg = rd32(E1000_VLVF(i));
5168 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5169 break;
5170 }
5171 }
5172 if (i < E1000_VLVF_ARRAY_SIZE) {
5173 /* Found an enabled/available entry */
5174 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5175
5176 /* if !enabled we need to set this up in vfta */
5177 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5178 /* add VID to filter table */
5179 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5180 reg |= E1000_VLVF_VLANID_ENABLE;
5181 }
cad6d05f
AD		 5182 reg &= ~E1000_VLVF_VLANID_MASK;
5183 reg |= vid;
4ae196df 5184 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5185
5186 /* do not modify RLPML for PF devices */
5187 if (vf >= adapter->vfs_allocated_count)
5188 return 0;
5189
5190 if (!adapter->vf_data[vf].vlans_enabled) {
5191 u32 size;
5192 reg = rd32(E1000_VMOLR(vf));
5193 size = reg & E1000_VMOLR_RLPML_MASK;
5194 size += 4;
5195 reg &= ~E1000_VMOLR_RLPML_MASK;
5196 reg |= size;
5197 wr32(E1000_VMOLR(vf), reg);
5198 }
ae641bdc 5199
51466239 5200 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5201 }
5202 } else {
5203 if (i < E1000_VLVF_ARRAY_SIZE) {
5204 /* remove vf from the pool */
5205 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5206 /* if pool is empty then remove entry from vfta */
5207 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5208 reg = 0;
5209 igb_vfta_set(hw, vid, false);
5210 }
5211 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5212
5213 /* do not modify RLPML for PF devices */
5214 if (vf >= adapter->vfs_allocated_count)
5215 return 0;
5216
5217 adapter->vf_data[vf].vlans_enabled--;
5218 if (!adapter->vf_data[vf].vlans_enabled) {
5219 u32 size;
5220 reg = rd32(E1000_VMOLR(vf));
5221 size = reg & E1000_VMOLR_RLPML_MASK;
5222 size -= 4;
5223 reg &= ~E1000_VMOLR_RLPML_MASK;
5224 reg |= size;
5225 wr32(E1000_VMOLR(vf), reg);
5226 }
4ae196df
AD		 5227 }
5228 }
8151d294
WM		 5229 return 0;
5230}
5231
5232static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5233{
5234 struct e1000_hw *hw = &adapter->hw;
5235
5236 if (vid)
5237 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5238 else
5239 wr32(E1000_VMVIR(vf), 0);
5240}
5241
5242static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5243 int vf, u16 vlan, u8 qos)
5244{
5245 int err = 0;
5246 struct igb_adapter *adapter = netdev_priv(netdev);
5247
5248 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5249 return -EINVAL;
5250 if (vlan || qos) {
5251 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5252 if (err)
5253 goto out;
5254 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5255 igb_set_vmolr(adapter, vf, !vlan);
5256 adapter->vf_data[vf].pf_vlan = vlan;
5257 adapter->vf_data[vf].pf_qos = qos;
5258 dev_info(&adapter->pdev->dev,
5259 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5260 if (test_bit(__IGB_DOWN, &adapter->state)) {
5261 dev_warn(&adapter->pdev->dev,
5262 "The VF VLAN has been set,"
5263 " but the PF device is not up.\n");
5264 dev_warn(&adapter->pdev->dev,
5265 "Bring the PF device up before"
5266 " attempting to use the VF device.\n");
5267 }
5268 } else {
5269 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5270 false, vf);
5271 igb_set_vmvir(adapter, vlan, vf);
5272 igb_set_vmolr(adapter, vf, true);
5273 adapter->vf_data[vf].pf_vlan = 0;
5274 adapter->vf_data[vf].pf_qos = 0;
5275 }
5276out:
5277 return err;
4ae196df
AD		 5278}
5279
5280static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5281{
5282 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5283 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5284
5285 return igb_vlvf_set(adapter, vid, add, vf);
5286}
5287
f2ca0dbe 5288static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5289{
8fa7e0f7
GR		 5290 /* clear flags - except flag that indicates PF has set the MAC */
5291 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5292 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5293
5294 /* reset offloads to defaults */
8151d294 5295 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5296
5297 /* reset vlans for device */
5298 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5299 if (adapter->vf_data[vf].pf_vlan)
5300 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5301 adapter->vf_data[vf].pf_vlan,
5302 adapter->vf_data[vf].pf_qos);
5303 else
5304 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5305
5306 /* reset multicast table array for vf */
5307 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5308
5309 /* Flush and reset the mta with the new values */
ff41f8dc 5310 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5311}
5312
f2ca0dbe
AD		 5313static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5314{
5315 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5316
5317 /* generate a new mac address as we were hotplug removed/added */
8151d294 5318 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5319 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5320
5321 /* process remaining reset events */
5322 igb_vf_reset(adapter, vf);
5323}
5324
5325static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5326{
5327 struct e1000_hw *hw = &adapter->hw;
5328 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5329 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5330 u32 reg, msgbuf[3];
5331 u8 *addr = (u8 *)(&msgbuf[1]);
5332
5333 /* process all the same items cleared in a function level reset */
f2ca0dbe 5334 igb_vf_reset(adapter, vf);
4ae196df
AD		 5335
5336 /* set vf mac address */
26ad9178 5337 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5338
5339 /* enable transmit and receive for vf */
5340 reg = rd32(E1000_VFTE);
5341 wr32(E1000_VFTE, reg | (1 << vf));
5342 reg = rd32(E1000_VFRE);
5343 wr32(E1000_VFRE, reg | (1 << vf));
5344
8fa7e0f7 5345 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5346
5347 /* reply to reset with ack and vf mac address */
5348 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5349 memcpy(addr, vf_mac, 6);
5350 igb_write_mbx(hw, msgbuf, 3, vf);
5351}
5352
5353static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5354{
de42edde
GR		 5355 /*
5356 * The VF MAC Address is stored in a packed array of bytes
5357 * starting at the second 32 bit word of the msg array
5358 */
f2ca0dbe
AD		 5359 unsigned char *addr = (char *)&msg[1];
5360 int err = -1;
4ae196df 5361
f2ca0dbe
AD		 5362 if (is_valid_ether_addr(addr))
5363 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5364
f2ca0dbe 5365 return err;
4ae196df
AD		 5366}
5367
5368static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5369{
5370 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5371 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5372 u32 msg = E1000_VT_MSGTYPE_NACK;
5373
5374 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5375 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5376 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5377 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5378 vf_data->last_nack = jiffies;
4ae196df
AD		 5379 }
5380}
5381
f2ca0dbe 5382static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5383{
f2ca0dbe
AD		 5384 struct pci_dev *pdev = adapter->pdev;
5385 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5386 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5387 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5388 s32 retval;
5389
f2ca0dbe 5390 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5391
fef45f4c
AD		 5392 if (retval) {
5393 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5394 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5395 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5396 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5397 return;
5398 goto out;
5399 }
4ae196df
AD		 5400
5401 /* this is a message we already processed, do nothing */
5402 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5403 return;
4ae196df
AD		 5404
5405 /*
5406 * until the vf completes a reset it should not be
5407 * allowed to start any configuration.
5408 */
5409
5410 if (msgbuf[0] == E1000_VF_RESET) {
5411 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5412 return;
4ae196df
AD		 5413 }
5414
f2ca0dbe 5415 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5416 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5417 return;
5418 retval = -1;
5419 goto out;
4ae196df
AD		 5420 }
5421
5422 switch ((msgbuf[0] & 0xFFFF)) {
5423 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5424 retval = -EINVAL;
5425 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5426 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5427 else
5428 dev_warn(&pdev->dev,
5429 "VF %d attempted to override administratively "
5430 "set MAC address\nReload the VF driver to "
5431 "resume operations\n", vf);
4ae196df 5432 break;
7d5753f0
AD		 5433 case E1000_VF_SET_PROMISC:
5434 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5435 break;
4ae196df
AD		 5436 case E1000_VF_SET_MULTICAST:
5437 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5438 break;
5439 case E1000_VF_SET_LPE:
5440 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5441 break;
5442 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5443 retval = -1;
5444 if (vf_data->pf_vlan)
5445 dev_warn(&pdev->dev,
5446 "VF %d attempted to override administratively "
5447 "set VLAN tag\nReload the VF driver to "
5448 "resume operations\n", vf);
8151d294
WM		 5449 else
5450 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5451 break;
5452 default:
090b1795 5453 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5454 retval = -1;
5455 break;
5456 }
5457
fef45f4c
AD		 5458 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5459out:
4ae196df
AD		 5460 /* notify the VF of the results of what it sent us */
5461 if (retval)
5462 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5463 else
5464 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5465
4ae196df 5466 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5467}
4ae196df 5468
f2ca0dbe
AD		 5469static void igb_msg_task(struct igb_adapter *adapter)
5470{
5471 struct e1000_hw *hw = &adapter->hw;
5472 u32 vf;
5473
5474 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5475 /* process any reset requests */
5476 if (!igb_check_for_rst(hw, vf))
5477 igb_vf_reset_event(adapter, vf);
5478
5479 /* process any messages pending */
5480 if (!igb_check_for_msg(hw, vf))
5481 igb_rcv_msg_from_vf(adapter, vf);
5482
5483 /* process any acks */
5484 if (!igb_check_for_ack(hw, vf))
5485 igb_rcv_ack_from_vf(adapter, vf);
5486 }
4ae196df
AD		 5487}
5488
68d480c4
AD		 5489/**
5490 * igb_set_uta - Set unicast filter table address
5491 * @adapter: board private structure
5492 *
5493 * The unicast table address is a register array of 32-bit registers.
5494 * The table is meant to be used in a way similar to how the MTA is used
5495 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5496 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5497 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5498 **/
5499static void igb_set_uta(struct igb_adapter *adapter)
5500{
5501 struct e1000_hw *hw = &adapter->hw;
5502 int i;
5503
5504 /* The UTA table only exists on 82576 hardware and newer */
5505 if (hw->mac.type < e1000_82576)
5506 return;
5507
5508 /* we only need to do this if VMDq is enabled */
5509 if (!adapter->vfs_allocated_count)
5510 return;
5511
5512 for (i = 0; i < hw->mac.uta_reg_count; i++)
5513 array_wr32(E1000_UTA, i, ~0);
5514}
5515
9d5c8243
AK		 5516/**
5517 * igb_intr_msi - Interrupt Handler
5518 * @irq: interrupt number
5519 * @data: pointer to a network interface device structure
5520 **/
5521static irqreturn_t igb_intr_msi(int irq, void *data)
5522{
047e0030
AD		 5523 struct igb_adapter *adapter = data;
5524 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5525 struct e1000_hw *hw = &adapter->hw;
5526 /* read ICR disables interrupts using IAM */
5527 u32 icr = rd32(E1000_ICR);
5528
047e0030 5529 igb_write_itr(q_vector);
9d5c8243 5530
7f081d40
AD		 5531 if (icr & E1000_ICR_DRSTA)
5532 schedule_work(&adapter->reset_task);
5533
047e0030 5534 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5535 /* HW is reporting DMA is out of sync */
5536 adapter->stats.doosync++;
5537 }
5538
9d5c8243
AK		 5539 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5540 hw->mac.get_link_status = 1;
5541 if (!test_bit(__IGB_DOWN, &adapter->state))
5542 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5543 }
5544
1f6e8178
MV		 5545 if (icr & E1000_ICR_TS) {
5546 u32 tsicr = rd32(E1000_TSICR);
5547
5548 if (tsicr & E1000_TSICR_TXTS) {
5549 /* acknowledge the interrupt */
5550 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5551 /* retrieve hardware timestamp */
5552 schedule_work(&adapter->ptp_tx_work);
5553 }
5554 }
1f6e8178 5555
047e0030 5556 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5557
5558 return IRQ_HANDLED;
5559}
5560
5561/**
4a3c6433 5562 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5563 * @irq: interrupt number
5564 * @data: pointer to a network interface device structure
5565 **/
5566static irqreturn_t igb_intr(int irq, void *data)
5567{
047e0030
AD		 5568 struct igb_adapter *adapter = data;
5569 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5570 struct e1000_hw *hw = &adapter->hw;
5571 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5572 * need for the IMC write */
5573 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5574
5575 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5576 * not set, then the adapter didn't send an interrupt */
5577 if (!(icr & E1000_ICR_INT_ASSERTED))
5578 return IRQ_NONE;
5579
0ba82994
AD		 5580 igb_write_itr(q_vector);
5581
7f081d40
AD		 5582 if (icr & E1000_ICR_DRSTA)
5583 schedule_work(&adapter->reset_task);
5584
047e0030 5585 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5586 /* HW is reporting DMA is out of sync */
5587 adapter->stats.doosync++;
5588 }
5589
9d5c8243
AK		 5590 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5591 hw->mac.get_link_status = 1;
5592 /* guard against interrupt when we're going down */
5593 if (!test_bit(__IGB_DOWN, &adapter->state))
5594 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5595 }
5596
1f6e8178
MV		 5597 if (icr & E1000_ICR_TS) {
5598 u32 tsicr = rd32(E1000_TSICR);
5599
5600 if (tsicr & E1000_TSICR_TXTS) {
5601 /* acknowledge the interrupt */
5602 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5603 /* retrieve hardware timestamp */
5604 schedule_work(&adapter->ptp_tx_work);
5605 }
5606 }
1f6e8178 5607
047e0030 5608 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5609
5610 return IRQ_HANDLED;
5611}
5612
c50b52a0 5613static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5614{
047e0030 5615 struct igb_adapter *adapter = q_vector->adapter;
46544258 5616 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5617
0ba82994
AD		 5618 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5619 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5620 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5621 igb_set_itr(q_vector);
46544258 5622 else
047e0030 5623 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5624 }
5625
46544258
AD		 5626 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5627 if (adapter->msix_entries)
047e0030 5628 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5629 else
5630 igb_irq_enable(adapter);
5631 }
9d5c8243
AK		 5632}
5633
46544258
AD		 5634/**
5635 * igb_poll - NAPI Rx polling callback
5636 * @napi: napi polling structure
5637 * @budget: count of how many packets we should handle
5638 **/
5639static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5640{
047e0030
AD		 5641 struct igb_q_vector *q_vector = container_of(napi,
5642 struct igb_q_vector,
5643 napi);
16eb8815 5644 bool clean_complete = true;
9d5c8243 5645
421e02f0 5646#ifdef CONFIG_IGB_DCA
047e0030
AD		 5647 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5648 igb_update_dca(q_vector);
fe4506b6 5649#endif
0ba82994 5650 if (q_vector->tx.ring)
13fde97a 5651 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5652
0ba82994 5653 if (q_vector->rx.ring)
cd392f5c 5654 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5655
16eb8815
AD		 5656 /* If all work not completed, return budget and keep polling */
5657 if (!clean_complete)
5658 return budget;
46544258 5659
9d5c8243 5660 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5661 napi_complete(napi);
5662 igb_ring_irq_enable(q_vector);
9d5c8243 5663
16eb8815 5664 return 0;
9d5c8243 5665}
6d8126f9 5666
9d5c8243
AK		 5667/**
5668 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5669 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5670 *
9d5c8243
AK		 5671 * returns true if ring is completely cleaned
5672 **/
047e0030 5673static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5674{
047e0030 5675 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5676 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5677 struct igb_tx_buffer *tx_buffer;
f4128785 5678 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5679 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5680 unsigned int budget = q_vector->tx.work_limit;
8542db05 5681 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5682
13fde97a
AD		 5683 if (test_bit(__IGB_DOWN, &adapter->state))
5684 return true;
0e014cb1 5685
06034649 5686 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5687 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5688 i -= tx_ring->count;
9d5c8243 5689
f4128785
AD		 5690 do {
5691 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5692
5693 /* if next_to_watch is not set then there is no work pending */
5694 if (!eop_desc)
5695 break;
13fde97a 5696
f4128785
AD		 5697 /* prevent any other reads prior to eop_desc */
5698 rmb();
5699
13fde97a
AD		 5700 /* if DD is not set pending work has not been completed */
5701 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5702 break;
5703
8542db05
AD		 5704 /* clear next_to_watch to prevent false hangs */
5705 tx_buffer->next_to_watch = NULL;
9d5c8243 5706
ebe42d16
AD		 5707 /* update the statistics for this packet */
5708 total_bytes += tx_buffer->bytecount;
5709 total_packets += tx_buffer->gso_segs;
13fde97a 5710
ebe42d16
AD		 5711 /* free the skb */
5712 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5713
ebe42d16
AD		 5714 /* unmap skb header data */
5715 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5716 dma_unmap_addr(tx_buffer, dma),
5717 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5718 DMA_TO_DEVICE);
5719
c9f14bf3
AD		 5720 /* clear tx_buffer data */
5721 tx_buffer->skb = NULL;
5722 dma_unmap_len_set(tx_buffer, len, 0);
5723
ebe42d16
AD		 5724 /* clear last DMA location and unmap remaining buffers */
5725 while (tx_desc != eop_desc) {
13fde97a
AD		 5726 tx_buffer++;
5727 tx_desc++;
9d5c8243 5728 i++;
8542db05
AD		 5729 if (unlikely(!i)) {
5730 i -= tx_ring->count;
06034649 5731 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5732 tx_desc = IGB_TX_DESC(tx_ring, 0);
5733 }
ebe42d16
AD		 5734
5735 /* unmap any remaining paged data */
c9f14bf3 5736 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5737 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5738 dma_unmap_addr(tx_buffer, dma),
5739 dma_unmap_len(tx_buffer, len),
ebe42d16 5740 DMA_TO_DEVICE);
c9f14bf3 5741 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5742 }
5743 }
5744
ebe42d16
AD		 5745 /* move us one more past the eop_desc for start of next pkt */
5746 tx_buffer++;
5747 tx_desc++;
5748 i++;
5749 if (unlikely(!i)) {
5750 i -= tx_ring->count;
5751 tx_buffer = tx_ring->tx_buffer_info;
5752 tx_desc = IGB_TX_DESC(tx_ring, 0);
5753 }
f4128785
AD		 5754
5755 /* issue prefetch for next Tx descriptor */
5756 prefetch(tx_desc);
5757
5758 /* update budget accounting */
5759 budget--;
5760 } while (likely(budget));
0e014cb1 5761
bdbc0631
ED		 5762 netdev_tx_completed_queue(txring_txq(tx_ring),
5763 total_packets, total_bytes);
8542db05 5764 i += tx_ring->count;
9d5c8243 5765 tx_ring->next_to_clean = i;
13fde97a
AD		 5766 u64_stats_update_begin(&tx_ring->tx_syncp);
5767 tx_ring->tx_stats.bytes += total_bytes;
5768 tx_ring->tx_stats.packets += total_packets;
5769 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 5770 q_vector->tx.total_bytes += total_bytes;
5771 q_vector->tx.total_packets += total_packets;
9d5c8243 5772
6d095fa8 5773 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 5774 struct e1000_hw *hw = &adapter->hw;
12dcd86b 5775
9d5c8243
AK		 5776 /* Detect a transmit hang in hardware, this serializes the
5777 * check with the clearing of time_stamp and movement of i */
6d095fa8 5778 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 5779 if (tx_buffer->next_to_watch &&
8542db05 5780 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 5781 (adapter->tx_timeout_factor * HZ)) &&
5782 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5783
9d5c8243 5784 /* detected Tx unit hang */
59d71989 5785 dev_err(tx_ring->dev,
9d5c8243 5786 "Detected Tx Unit Hang\n"
2d064c06 5787 " Tx Queue <%d>\n"
9d5c8243
AK		 5788 " TDH <%x>\n"
5789 " TDT <%x>\n"
5790 " next_to_use <%x>\n"
5791 " next_to_clean <%x>\n"
9d5c8243
AK		 5792 "buffer_info[next_to_clean]\n"
5793 " time_stamp <%lx>\n"
8542db05 5794 " next_to_watch <%p>\n"
9d5c8243
AK		 5795 " jiffies <%lx>\n"
5796 " desc.status <%x>\n",
2d064c06 5797 tx_ring->queue_index,
238ac817 5798 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5799 readl(tx_ring->tail),
9d5c8243
AK		 5800 tx_ring->next_to_use,
5801 tx_ring->next_to_clean,
8542db05 5802 tx_buffer->time_stamp,
f4128785 5803 tx_buffer->next_to_watch,
9d5c8243 5804 jiffies,
f4128785 5805 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 5806 netif_stop_subqueue(tx_ring->netdev,
5807 tx_ring->queue_index);
5808
5809 /* we are about to reset, no point in enabling stuff */
5810 return true;
9d5c8243
AK		 5811 }
5812 }
13fde97a
AD		 5813
5814 if (unlikely(total_packets &&
5815 netif_carrier_ok(tx_ring->netdev) &&
5816 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5817 /* Make sure that anybody stopping the queue after this
5818 * sees the new next_to_clean.
5819 */
5820 smp_mb();
5821 if (__netif_subqueue_stopped(tx_ring->netdev,
5822 tx_ring->queue_index) &&
5823 !(test_bit(__IGB_DOWN, &adapter->state))) {
5824 netif_wake_subqueue(tx_ring->netdev,
5825 tx_ring->queue_index);
5826
5827 u64_stats_update_begin(&tx_ring->tx_syncp);
5828 tx_ring->tx_stats.restart_queue++;
5829 u64_stats_update_end(&tx_ring->tx_syncp);
5830 }
5831 }
5832
5833 return !!budget;
9d5c8243
AK		 5834}
5835
cbc8e55f
AD		 5836/**
5837 * igb_reuse_rx_page - page flip buffer and store it back on the ring
5838 * @rx_ring: rx descriptor ring to store buffers on
5839 * @old_buff: donor buffer to have page reused
5840 *
5841 * Synchronizes page for reuse by the adapter
5842 **/
5843static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5844 struct igb_rx_buffer *old_buff)
5845{
5846 struct igb_rx_buffer *new_buff;
5847 u16 nta = rx_ring->next_to_alloc;
5848
5849 new_buff = &rx_ring->rx_buffer_info[nta];
5850
5851 /* update, and store next to alloc */
5852 nta++;
5853 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5854
5855 /* transfer page from old buffer to new buffer */
5856 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5857
5858 /* sync the buffer for use by the device */
5859 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5860 old_buff->page_offset,
de78d1f9 5861 IGB_RX_BUFSZ,
cbc8e55f
AD		 5862 DMA_FROM_DEVICE);
5863}
5864
5865/**
5866 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5867 * @rx_ring: rx descriptor ring to transact packets on
5868 * @rx_buffer: buffer containing page to add
5869 * @rx_desc: descriptor containing length of buffer written by hardware
5870 * @skb: sk_buff to place the data into
5871 *
5872 * This function will add the data contained in rx_buffer->page to the skb.
5873 * This is done either through a direct copy if the data in the buffer is
5874 * less than the skb header size, otherwise it will just attach the page as
5875 * a frag to the skb.
5876 *
5877 * The function will then update the page offset if necessary and return
5878 * true if the buffer can be reused by the adapter.
5879 **/
5880static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5881 struct igb_rx_buffer *rx_buffer,
5882 union e1000_adv_rx_desc *rx_desc,
5883 struct sk_buff *skb)
5884{
5885 struct page *page = rx_buffer->page;
5886 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5887
5888 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5889 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5890
cbc8e55f
AD		 5891 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5892 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5893 va += IGB_TS_HDR_LEN;
5894 size -= IGB_TS_HDR_LEN;
5895 }
5896
cbc8e55f
AD		 5897 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5898
5899 /* we can reuse buffer as-is, just make sure it is local */
5900 if (likely(page_to_nid(page) == numa_node_id()))
5901 return true;
5902
5903 /* this page cannot be reused so discard it */
5904 put_page(page);
5905 return false;
5906 }
5907
5908 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 5909 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 5910
5911 /* avoid re-using remote pages */
5912 if (unlikely(page_to_nid(page) != numa_node_id()))
5913 return false;
5914
de78d1f9 5915#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 5916 /* if we are only owner of page we can reuse it */
5917 if (unlikely(page_count(page) != 1))
5918 return false;
5919
5920 /* flip page offset to other buffer */
de78d1f9 5921 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 5922
5923 /*
5924 * since we are the only owner of the page and we need to
5925 * increment it, just set the value to 2 in order to avoid
5926 * an unnecessary locked operation
5927 */
5928 atomic_set(&page->_count, 2);
de78d1f9
AD		 5929#else
5930 /* move offset up to the next cache line */
5931 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5932
5933 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5934 return false;
5935
5936 /* bump ref count on page before it is given to the stack */
5937 get_page(page);
5938#endif
cbc8e55f
AD		 5939
5940 return true;
5941}
5942
2e334eee
AD		 5943static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
5944 union e1000_adv_rx_desc *rx_desc,
5945 struct sk_buff *skb)
5946{
5947 struct igb_rx_buffer *rx_buffer;
5948 struct page *page;
5949
5950 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
5951
5952 /*
5953 * This memory barrier is needed to keep us from reading
5954 * any other fields out of the rx_desc until we know the
5955 * RXD_STAT_DD bit is set
5956 */
5957 rmb();
5958
5959 page = rx_buffer->page;
5960 prefetchw(page);
5961
5962 if (likely(!skb)) {
5963 void *page_addr = page_address(page) +
5964 rx_buffer->page_offset;
5965
5966 /* prefetch first cache line of first page */
5967 prefetch(page_addr);
5968#if L1_CACHE_BYTES < 128
5969 prefetch(page_addr + L1_CACHE_BYTES);
5970#endif
5971
5972 /* allocate a skb to store the frags */
5973 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5974 IGB_RX_HDR_LEN);
5975 if (unlikely(!skb)) {
5976 rx_ring->rx_stats.alloc_failed++;
5977 return NULL;
5978 }
5979
5980 /*
5981 * we will be copying header into skb->data in
5982 * pskb_may_pull so it is in our interest to prefetch
5983 * it now to avoid a possible cache miss
5984 */
5985 prefetchw(skb->data);
5986 }
5987
5988 /* we are reusing so sync this buffer for CPU use */
5989 dma_sync_single_range_for_cpu(rx_ring->dev,
5990 rx_buffer->dma,
5991 rx_buffer->page_offset,
de78d1f9 5992 IGB_RX_BUFSZ,
2e334eee
AD		 5993 DMA_FROM_DEVICE);
5994
5995 /* pull page into skb */
5996 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
5997 /* hand second half of page back to the ring */
5998 igb_reuse_rx_page(rx_ring, rx_buffer);
5999 } else {
6000 /* we are not reusing the buffer so unmap it */
6001 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6002 PAGE_SIZE, DMA_FROM_DEVICE);
6003 }
6004
6005 /* clear contents of rx_buffer */
6006 rx_buffer->page = NULL;
6007
6008 return skb;
6009}
6010
cd392f5c 6011static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6012 union e1000_adv_rx_desc *rx_desc,
6013 struct sk_buff *skb)
9d5c8243 6014{
bc8acf2c 6015 skb_checksum_none_assert(skb);
9d5c8243 6016
294e7d78 6017 /* Ignore Checksum bit is set */
3ceb90fd 6018 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6019 return;
6020
6021 /* Rx checksum disabled via ethtool */
6022 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6023 return;
85ad76b2 6024
9d5c8243 6025 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6026 if (igb_test_staterr(rx_desc,
6027 E1000_RXDEXT_STATERR_TCPE |
6028 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6029 /*
6030 * work around errata with sctp packets where the TCPE aka
6031 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6032 * packets, (aka let the stack check the crc32c)
6033 */
866cff06
AD		 6034 if (!((skb->len == 60) &&
6035 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6036 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6037 ring->rx_stats.csum_err++;
12dcd86b
ED		 6038 u64_stats_update_end(&ring->rx_syncp);
6039 }
9d5c8243 6040 /* let the stack verify checksum errors */
9d5c8243
AK		 6041 return;
6042 }
6043 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6044 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6045 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6046 skb->ip_summed = CHECKSUM_UNNECESSARY;
6047
3ceb90fd
AD		 6048 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6049 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6050}
6051
077887c3
AD		 6052static inline void igb_rx_hash(struct igb_ring *ring,
6053 union e1000_adv_rx_desc *rx_desc,
6054 struct sk_buff *skb)
6055{
6056 if (ring->netdev->features & NETIF_F_RXHASH)
6057 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6058}
6059
2e334eee
AD		 6060/**
6061 * igb_is_non_eop - process handling of non-EOP buffers
6062 * @rx_ring: Rx ring being processed
6063 * @rx_desc: Rx descriptor for current buffer
6064 * @skb: current socket buffer containing buffer in progress
6065 *
6066 * This function updates next to clean. If the buffer is an EOP buffer
6067 * this function exits returning false, otherwise it will place the
6068 * sk_buff in the next buffer to be chained and return true indicating
6069 * that this is in fact a non-EOP buffer.
6070 **/
6071static bool igb_is_non_eop(struct igb_ring *rx_ring,
6072 union e1000_adv_rx_desc *rx_desc)
6073{
6074 u32 ntc = rx_ring->next_to_clean + 1;
6075
6076 /* fetch, update, and store next to clean */
6077 ntc = (ntc < rx_ring->count) ? ntc : 0;
6078 rx_ring->next_to_clean = ntc;
6079
6080 prefetch(IGB_RX_DESC(rx_ring, ntc));
6081
6082 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6083 return false;
6084
6085 return true;
6086}
6087
1a1c225b
AD		 6088/**
6089 * igb_get_headlen - determine size of header for LRO/GRO
6090 * @data: pointer to the start of the headers
6091 * @max_len: total length of section to find headers in
6092 *
6093 * This function is meant to determine the length of headers that will
6094 * be recognized by hardware for LRO, and GRO offloads. The main
6095 * motivation of doing this is to only perform one pull for IPv4 TCP
6096 * packets so that we can do basic things like calculating the gso_size
6097 * based on the average data per packet.
6098 **/
6099static unsigned int igb_get_headlen(unsigned char *data,
6100 unsigned int max_len)
6101{
6102 union {
6103 unsigned char *network;
6104 /* l2 headers */
6105 struct ethhdr *eth;
6106 struct vlan_hdr *vlan;
6107 /* l3 headers */
6108 struct iphdr *ipv4;
6109 struct ipv6hdr *ipv6;
6110 } hdr;
6111 __be16 protocol;
6112 u8 nexthdr = 0; /* default to not TCP */
6113 u8 hlen;
6114
6115 /* this should never happen, but better safe than sorry */
6116 if (max_len < ETH_HLEN)
6117 return max_len;
6118
6119 /* initialize network frame pointer */
6120 hdr.network = data;
6121
6122 /* set first protocol and move network header forward */
6123 protocol = hdr.eth->h_proto;
6124 hdr.network += ETH_HLEN;
6125
6126 /* handle any vlan tag if present */
6127 if (protocol == __constant_htons(ETH_P_8021Q)) {
6128 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6129 return max_len;
6130
6131 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6132 hdr.network += VLAN_HLEN;
6133 }
6134
6135 /* handle L3 protocols */
6136 if (protocol == __constant_htons(ETH_P_IP)) {
6137 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6138 return max_len;
6139
6140 /* access ihl as a u8 to avoid unaligned access on ia64 */
6141 hlen = (hdr.network[0] & 0x0F) << 2;
6142
6143 /* verify hlen meets minimum size requirements */
6144 if (hlen < sizeof(struct iphdr))
6145 return hdr.network - data;
6146
f2fb4ab2
AD		 6147 /* record next protocol if header is present */
6148 if (!hdr.ipv4->frag_off)
6149 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6150 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6151 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6152 return max_len;
6153
6154 /* record next protocol */
6155 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6156 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6157 } else {
6158 return hdr.network - data;
6159 }
6160
f2fb4ab2
AD		 6161 /* relocate pointer to start of L4 header */
6162 hdr.network += hlen;
6163
1a1c225b
AD		 6164 /* finally sort out TCP */
6165 if (nexthdr == IPPROTO_TCP) {
6166 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6167 return max_len;
6168
6169 /* access doff as a u8 to avoid unaligned access on ia64 */
6170 hlen = (hdr.network[12] & 0xF0) >> 2;
6171
6172 /* verify hlen meets minimum size requirements */
6173 if (hlen < sizeof(struct tcphdr))
6174 return hdr.network - data;
6175
6176 hdr.network += hlen;
6177 } else if (nexthdr == IPPROTO_UDP) {
6178 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6179 return max_len;
6180
6181 hdr.network += sizeof(struct udphdr);
6182 }
6183
6184 /*
6185 * If everything has gone correctly hdr.network should be the
6186 * data section of the packet and will be the end of the header.
6187 * If not then it probably represents the end of the last recognized
6188 * header.
6189 */
6190 if ((hdr.network - data) < max_len)
6191 return hdr.network - data;
6192 else
6193 return max_len;
6194}
6195
6196/**
6197 * igb_pull_tail - igb specific version of skb_pull_tail
6198 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6199 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6200 * @skb: pointer to current skb being adjusted
6201 *
6202 * This function is an igb specific version of __pskb_pull_tail. The
6203 * main difference between this version and the original function is that
6204 * this function can make several assumptions about the state of things
6205 * that allow for significant optimizations versus the standard function.
6206 * As a result we can do things like drop a frag and maintain an accurate
6207 * truesize for the skb.
6208 */
6209static void igb_pull_tail(struct igb_ring *rx_ring,
6210 union e1000_adv_rx_desc *rx_desc,
6211 struct sk_buff *skb)
2d94d8ab 6212{
1a1c225b
AD		 6213 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6214 unsigned char *va;
6215 unsigned int pull_len;
6216
6217 /*
6218 * it is valid to use page_address instead of kmap since we are
6219 * working with pages allocated out of the lomem pool per
6220 * alloc_page(GFP_ATOMIC)
2d94d8ab 6221 */
1a1c225b
AD		 6222 va = skb_frag_address(frag);
6223
1a1c225b
AD		 6224 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6225 /* retrieve timestamp from buffer */
6226 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6227
6228 /* update pointers to remove timestamp header */
6229 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6230 frag->page_offset += IGB_TS_HDR_LEN;
6231 skb->data_len -= IGB_TS_HDR_LEN;
6232 skb->len -= IGB_TS_HDR_LEN;
6233
6234 /* move va to start of packet data */
6235 va += IGB_TS_HDR_LEN;
6236 }
6237
1a1c225b
AD		 6238 /*
6239 * we need the header to contain the greater of either ETH_HLEN or
6240 * 60 bytes if the skb->len is less than 60 for skb_pad.
6241 */
6242 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6243
6244 /* align pull length to size of long to optimize memcpy performance */
6245 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6246
6247 /* update all of the pointers */
6248 skb_frag_size_sub(frag, pull_len);
6249 frag->page_offset += pull_len;
6250 skb->data_len -= pull_len;
6251 skb->tail += pull_len;
6252}
6253
6254/**
6255 * igb_cleanup_headers - Correct corrupted or empty headers
6256 * @rx_ring: rx descriptor ring packet is being transacted on
6257 * @rx_desc: pointer to the EOP Rx descriptor
6258 * @skb: pointer to current skb being fixed
6259 *
6260 * Address the case where we are pulling data in on pages only
6261 * and as such no data is present in the skb header.
6262 *
6263 * In addition if skb is not at least 60 bytes we need to pad it so that
6264 * it is large enough to qualify as a valid Ethernet frame.
6265 *
6266 * Returns true if an error was encountered and skb was freed.
6267 **/
6268static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6269 union e1000_adv_rx_desc *rx_desc,
6270 struct sk_buff *skb)
6271{
6272
6273 if (unlikely((igb_test_staterr(rx_desc,
6274 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6275 struct net_device *netdev = rx_ring->netdev;
6276 if (!(netdev->features & NETIF_F_RXALL)) {
6277 dev_kfree_skb_any(skb);
6278 return true;
6279 }
6280 }
6281
6282 /* place header in linear portion of buffer */
6283 if (skb_is_nonlinear(skb))
6284 igb_pull_tail(rx_ring, rx_desc, skb);
6285
6286 /* if skb_pad returns an error the skb was freed */
6287 if (unlikely(skb->len < 60)) {
6288 int pad_len = 60 - skb->len;
6289
6290 if (skb_pad(skb, pad_len))
6291 return true;
6292 __skb_put(skb, pad_len);
6293 }
6294
6295 return false;
2d94d8ab
AD		 6296}
6297
db2ee5bd
AD		 6298/**
6299 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6300 * @rx_ring: rx descriptor ring packet is being transacted on
6301 * @rx_desc: pointer to the EOP Rx descriptor
6302 * @skb: pointer to current skb being populated
6303 *
6304 * This function checks the ring, descriptor, and packet information in
6305 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6306 * other fields within the skb.
6307 **/
6308static void igb_process_skb_fields(struct igb_ring *rx_ring,
6309 union e1000_adv_rx_desc *rx_desc,
6310 struct sk_buff *skb)
6311{
6312 struct net_device *dev = rx_ring->netdev;
6313
6314 igb_rx_hash(rx_ring, rx_desc, skb);
6315
6316 igb_rx_checksum(rx_ring, rx_desc, skb);
6317
db2ee5bd 6318 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6319
6320 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6321 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6322 u16 vid;
6323 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6324 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6325 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6326 else
6327 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6328
6329 __vlan_hwaccel_put_tag(skb, vid);
6330 }
6331
6332 skb_record_rx_queue(skb, rx_ring->queue_index);
6333
6334 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6335}
6336
2e334eee 6337static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6338{
0ba82994 6339 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6340 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6341 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6342 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6343
2e334eee
AD		 6344 do {
6345 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6346
2e334eee
AD		 6347 /* return some buffers to hardware, one at a time is too slow */
6348 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6349 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6350 cleaned_count = 0;
6351 }
bf36c1a0 6352
2e334eee 6353 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6354
2e334eee
AD		 6355 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6356 break;
9d5c8243 6357
2e334eee
AD		 6358 /* retrieve a buffer from the ring */
6359 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6360
2e334eee
AD		 6361 /* exit if we failed to retrieve a buffer */
6362 if (!skb)
6363 break;
1a1c225b 6364
2e334eee 6365 cleaned_count++;
1a1c225b 6366
2e334eee
AD		 6367 /* fetch next buffer in frame if non-eop */
6368 if (igb_is_non_eop(rx_ring, rx_desc))
6369 continue;
1a1c225b
AD		 6370
6371 /* verify the packet layout is correct */
6372 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6373 skb = NULL;
6374 continue;
9d5c8243 6375 }
9d5c8243 6376
db2ee5bd 6377 /* probably a little skewed due to removing CRC */
3ceb90fd 6378 total_bytes += skb->len;
3ceb90fd 6379
db2ee5bd
AD		 6380 /* populate checksum, timestamp, VLAN, and protocol */
6381 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6382
b2cb09b1 6383 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6384
1a1c225b
AD		 6385 /* reset skb pointer */
6386 skb = NULL;
6387
2e334eee
AD		 6388 /* update budget accounting */
6389 total_packets++;
6390 } while (likely(total_packets < budget));
bf36c1a0 6391
1a1c225b
AD		 6392 /* place incomplete frames back on ring for completion */
6393 rx_ring->skb = skb;
6394
12dcd86b 6395 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6396 rx_ring->rx_stats.packets += total_packets;
6397 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6398 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6399 q_vector->rx.total_packets += total_packets;
6400 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6401
6402 if (cleaned_count)
cd392f5c 6403 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6404
2e334eee 6405 return (total_packets < budget);
9d5c8243
AK		 6406}
6407
c023cd88 6408static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6409 struct igb_rx_buffer *bi)
c023cd88
AD		 6410{
6411 struct page *page = bi->page;
cbc8e55f 6412 dma_addr_t dma;
c023cd88 6413
cbc8e55f
AD		 6414 /* since we are recycling buffers we should seldom need to alloc */
6415 if (likely(page))
c023cd88
AD		 6416 return true;
6417
cbc8e55f
AD		 6418 /* alloc new page for storage */
6419 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6420 if (unlikely(!page)) {
6421 rx_ring->rx_stats.alloc_failed++;
6422 return false;
c023cd88
AD		 6423 }
6424
cbc8e55f
AD		 6425 /* map page for use */
6426 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6427
cbc8e55f
AD		 6428 /*
6429 * if mapping failed free memory back to system since
6430 * there isn't much point in holding memory we can't use
6431 */
1a1c225b 6432 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6433 __free_page(page);
6434
c023cd88
AD		 6435 rx_ring->rx_stats.alloc_failed++;
6436 return false;
6437 }
6438
1a1c225b 6439 bi->dma = dma;
cbc8e55f
AD		 6440 bi->page = page;
6441 bi->page_offset = 0;
1a1c225b 6442
c023cd88
AD		 6443 return true;
6444}
6445
9d5c8243 6446/**
cd392f5c 6447 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6448 * @adapter: address of board private structure
6449 **/
cd392f5c 6450void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6451{
9d5c8243 6452 union e1000_adv_rx_desc *rx_desc;
06034649 6453 struct igb_rx_buffer *bi;
c023cd88 6454 u16 i = rx_ring->next_to_use;
9d5c8243 6455
cbc8e55f
AD		 6456 /* nothing to do */
6457 if (!cleaned_count)
6458 return;
6459
60136906 6460 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6461 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6462 i -= rx_ring->count;
9d5c8243 6463
cbc8e55f 6464 do {
1a1c225b 6465 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6466 break;
9d5c8243 6467
cbc8e55f
AD		 6468 /*
6469 * Refresh the desc even if buffer_addrs didn't change
6470 * because each write-back erases this info.
6471 */
6472 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6473
c023cd88
AD		 6474 rx_desc++;
6475 bi++;
9d5c8243 6476 i++;
c023cd88 6477 if (unlikely(!i)) {
60136906 6478 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6479 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6480 i -= rx_ring->count;
6481 }
6482
6483 /* clear the hdr_addr for the next_to_use descriptor */
6484 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6485
6486 cleaned_count--;
6487 } while (cleaned_count);
9d5c8243 6488
c023cd88
AD		 6489 i += rx_ring->count;
6490
9d5c8243 6491 if (rx_ring->next_to_use != i) {
cbc8e55f 6492 /* record the next descriptor to use */
9d5c8243 6493 rx_ring->next_to_use = i;
9d5c8243 6494
cbc8e55f
AD		 6495 /* update next to alloc since we have filled the ring */
6496 rx_ring->next_to_alloc = i;
6497
6498 /*
6499 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6500 * know there are new descriptors to fetch. (Only
6501 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6502 * such as IA-64).
6503 */
9d5c8243 6504 wmb();
fce99e34 6505 writel(i, rx_ring->tail);
9d5c8243
AK		 6506 }
6507}
6508
6509/**
6510 * igb_mii_ioctl -
6511 * @netdev:
6512 * @ifreq:
6513 * @cmd:
6514 **/
6515static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6516{
6517 struct igb_adapter *adapter = netdev_priv(netdev);
6518 struct mii_ioctl_data *data = if_mii(ifr);
6519
6520 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6521 return -EOPNOTSUPP;
6522
6523 switch (cmd) {
6524 case SIOCGMIIPHY:
6525 data->phy_id = adapter->hw.phy.addr;
6526 break;
6527 case SIOCGMIIREG:
f5f4cf08
AD		 6528 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6529 &data->val_out))
9d5c8243
AK		 6530 return -EIO;
6531 break;
6532 case SIOCSMIIREG:
6533 default:
6534 return -EOPNOTSUPP;
6535 }
6536 return 0;
6537}
6538
6539/**
6540 * igb_ioctl -
6541 * @netdev:
6542 * @ifreq:
6543 * @cmd:
6544 **/
6545static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6546{
6547 switch (cmd) {
6548 case SIOCGMIIPHY:
6549 case SIOCGMIIREG:
6550 case SIOCSMIIREG:
6551 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6552 case SIOCSHWTSTAMP:
a79f4f88 6553 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6554 default:
6555 return -EOPNOTSUPP;
6556 }
6557}
6558
009bc06e
AD		 6559s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6560{
6561 struct igb_adapter *adapter = hw->back;
009bc06e 6562
23d028cc 6563 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6564 return -E1000_ERR_CONFIG;
6565
009bc06e
AD		 6566 return 0;
6567}
6568
6569s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6570{
6571 struct igb_adapter *adapter = hw->back;
009bc06e 6572
23d028cc 6573 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6574 return -E1000_ERR_CONFIG;
6575
009bc06e
AD		 6576 return 0;
6577}
6578
c8f44aff 6579static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6580{
6581 struct igb_adapter *adapter = netdev_priv(netdev);
6582 struct e1000_hw *hw = &adapter->hw;
6583 u32 ctrl, rctl;
5faf030c 6584 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6585
5faf030c 6586 if (enable) {
9d5c8243
AK		 6587 /* enable VLAN tag insert/strip */
6588 ctrl = rd32(E1000_CTRL);
6589 ctrl |= E1000_CTRL_VME;
6590 wr32(E1000_CTRL, ctrl);
6591
51466239 6592 /* Disable CFI check */
9d5c8243 6593 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6594 rctl &= ~E1000_RCTL_CFIEN;
6595 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6596 } else {
6597 /* disable VLAN tag insert/strip */
6598 ctrl = rd32(E1000_CTRL);
6599 ctrl &= ~E1000_CTRL_VME;
6600 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6601 }
6602
e1739522 6603 igb_rlpml_set(adapter);
9d5c8243
AK		 6604}
6605
8e586137 6606static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6607{
6608 struct igb_adapter *adapter = netdev_priv(netdev);
6609 struct e1000_hw *hw = &adapter->hw;
4ae196df 6610 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6611
51466239
AD		 6612 /* attempt to add filter to vlvf array */
6613 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6614
51466239
AD		 6615 /* add the filter since PF can receive vlans w/o entry in vlvf */
6616 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6617
6618 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6619
6620 return 0;
9d5c8243
AK		 6621}
6622
8e586137 6623static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6624{
6625 struct igb_adapter *adapter = netdev_priv(netdev);
6626 struct e1000_hw *hw = &adapter->hw;
4ae196df 6627 int pf_id = adapter->vfs_allocated_count;
51466239 6628 s32 err;
9d5c8243 6629
51466239
AD		 6630 /* remove vlan from VLVF table array */
6631 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6632
51466239
AD		 6633 /* if vid was not present in VLVF just remove it from table */
6634 if (err)
4ae196df 6635 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6636
6637 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6638
6639 return 0;
9d5c8243
AK		 6640}
6641
6642static void igb_restore_vlan(struct igb_adapter *adapter)
6643{
b2cb09b1 6644 u16 vid;
9d5c8243 6645
5faf030c
AD		 6646 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6647
b2cb09b1
JP		 6648 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6649 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6650}
6651
14ad2513 6652int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6653{
090b1795 6654 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6655 struct e1000_mac_info *mac = &adapter->hw.mac;
6656
6657 mac->autoneg = 0;
6658
14ad2513
DD		 6659 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6660 * for the switch() below to work */
6661 if ((spd & 1) || (dplx & ~1))
6662 goto err_inval;
6663
cd2638a8
CW		 6664 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6665 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6666 spd != SPEED_1000 &&
6667 dplx != DUPLEX_FULL)
6668 goto err_inval;
cd2638a8 6669
14ad2513 6670 switch (spd + dplx) {
9d5c8243
AK		 6671 case SPEED_10 + DUPLEX_HALF:
6672 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6673 break;
6674 case SPEED_10 + DUPLEX_FULL:
6675 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6676 break;
6677 case SPEED_100 + DUPLEX_HALF:
6678 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6679 break;
6680 case SPEED_100 + DUPLEX_FULL:
6681 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6682 break;
6683 case SPEED_1000 + DUPLEX_FULL:
6684 mac->autoneg = 1;
6685 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6686 break;
6687 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6688 default:
14ad2513 6689 goto err_inval;
9d5c8243 6690 }
8376dad0
JB		 6691
6692 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6693 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6694
9d5c8243 6695 return 0;
14ad2513
DD		 6696
6697err_inval:
6698 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6699 return -EINVAL;
9d5c8243
AK		 6700}
6701
749ab2cd
YZ		 6702static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6703 bool runtime)
9d5c8243
AK		 6704{
6705 struct net_device *netdev = pci_get_drvdata(pdev);
6706 struct igb_adapter *adapter = netdev_priv(netdev);
6707 struct e1000_hw *hw = &adapter->hw;
2d064c06 6708 u32 ctrl, rctl, status;
749ab2cd 6709 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6710#ifdef CONFIG_PM
6711 int retval = 0;
6712#endif
6713
6714 netif_device_detach(netdev);
6715
a88f10ec 6716 if (netif_running(netdev))
749ab2cd 6717 __igb_close(netdev, true);
a88f10ec 6718
047e0030 6719 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6720
6721#ifdef CONFIG_PM
6722 retval = pci_save_state(pdev);
6723 if (retval)
6724 return retval;
6725#endif
6726
6727 status = rd32(E1000_STATUS);
6728 if (status & E1000_STATUS_LU)
6729 wufc &= ~E1000_WUFC_LNKC;
6730
6731 if (wufc) {
6732 igb_setup_rctl(adapter);
ff41f8dc 6733 igb_set_rx_mode(netdev);
9d5c8243
AK		 6734
6735 /* turn on all-multi mode if wake on multicast is enabled */
6736 if (wufc & E1000_WUFC_MC) {
6737 rctl = rd32(E1000_RCTL);
6738 rctl |= E1000_RCTL_MPE;
6739 wr32(E1000_RCTL, rctl);
6740 }
6741
6742 ctrl = rd32(E1000_CTRL);
6743 /* advertise wake from D3Cold */
6744 #define E1000_CTRL_ADVD3WUC 0x00100000
6745 /* phy power management enable */
6746 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6747 ctrl |= E1000_CTRL_ADVD3WUC;
6748 wr32(E1000_CTRL, ctrl);
6749
9d5c8243 6750 /* Allow time for pending master requests to run */
330a6d6a 6751 igb_disable_pcie_master(hw);
9d5c8243
AK		 6752
6753 wr32(E1000_WUC, E1000_WUC_PME_EN);
6754 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6755 } else {
6756 wr32(E1000_WUC, 0);
6757 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6758 }
6759
3fe7c4c9
RW		 6760 *enable_wake = wufc || adapter->en_mng_pt;
6761 if (!*enable_wake)
88a268c1
NN		 6762 igb_power_down_link(adapter);
6763 else
6764 igb_power_up_link(adapter);
9d5c8243
AK		 6765
6766 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6767 * would have already happened in close and is redundant. */
6768 igb_release_hw_control(adapter);
6769
6770 pci_disable_device(pdev);
6771
9d5c8243
AK		 6772 return 0;
6773}
6774
6775#ifdef CONFIG_PM
d9dd966d 6776#ifdef CONFIG_PM_SLEEP
749ab2cd 6777static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 6778{
6779 int retval;
6780 bool wake;
749ab2cd 6781 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 6782
749ab2cd 6783 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6784 if (retval)
6785 return retval;
6786
6787 if (wake) {
6788 pci_prepare_to_sleep(pdev);
6789 } else {
6790 pci_wake_from_d3(pdev, false);
6791 pci_set_power_state(pdev, PCI_D3hot);
6792 }
6793
6794 return 0;
6795}
d9dd966d 6796#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 6797
749ab2cd 6798static int igb_resume(struct device *dev)
9d5c8243 6799{
749ab2cd 6800 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 6801 struct net_device *netdev = pci_get_drvdata(pdev);
6802 struct igb_adapter *adapter = netdev_priv(netdev);
6803 struct e1000_hw *hw = &adapter->hw;
6804 u32 err;
6805
6806 pci_set_power_state(pdev, PCI_D0);
6807 pci_restore_state(pdev);
b94f2d77 6808 pci_save_state(pdev);
42bfd33a 6809
aed5dec3 6810 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6811 if (err) {
6812 dev_err(&pdev->dev,
6813 "igb: Cannot enable PCI device from suspend\n");
6814 return err;
6815 }
6816 pci_set_master(pdev);
6817
6818 pci_enable_wake(pdev, PCI_D3hot, 0);
6819 pci_enable_wake(pdev, PCI_D3cold, 0);
6820
cfb8c3aa 6821 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6822 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6823 return -ENOMEM;
9d5c8243
AK		 6824 }
6825
9d5c8243 6826 igb_reset(adapter);
a8564f03
AD		 6827
6828 /* let the f/w know that the h/w is now under the control of the
6829 * driver. */
6830 igb_get_hw_control(adapter);
6831
9d5c8243
AK		 6832 wr32(E1000_WUS, ~0);
6833
749ab2cd 6834 if (netdev->flags & IFF_UP) {
0c2cc02e 6835 rtnl_lock();
749ab2cd 6836 err = __igb_open(netdev, true);
0c2cc02e 6837 rtnl_unlock();
a88f10ec
AD		 6838 if (err)
6839 return err;
6840 }
9d5c8243
AK		 6841
6842 netif_device_attach(netdev);
749ab2cd
YZ		 6843 return 0;
6844}
6845
6846#ifdef CONFIG_PM_RUNTIME
6847static int igb_runtime_idle(struct device *dev)
6848{
6849 struct pci_dev *pdev = to_pci_dev(dev);
6850 struct net_device *netdev = pci_get_drvdata(pdev);
6851 struct igb_adapter *adapter = netdev_priv(netdev);
6852
6853 if (!igb_has_link(adapter))
6854 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6855
6856 return -EBUSY;
6857}
6858
6859static int igb_runtime_suspend(struct device *dev)
6860{
6861 struct pci_dev *pdev = to_pci_dev(dev);
6862 int retval;
6863 bool wake;
6864
6865 retval = __igb_shutdown(pdev, &wake, 1);
6866 if (retval)
6867 return retval;
6868
6869 if (wake) {
6870 pci_prepare_to_sleep(pdev);
6871 } else {
6872 pci_wake_from_d3(pdev, false);
6873 pci_set_power_state(pdev, PCI_D3hot);
6874 }
9d5c8243 6875
9d5c8243
AK		 6876 return 0;
6877}
749ab2cd
YZ		 6878
6879static int igb_runtime_resume(struct device *dev)
6880{
6881 return igb_resume(dev);
6882}
6883#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 6884#endif
6885
6886static void igb_shutdown(struct pci_dev *pdev)
6887{
3fe7c4c9
RW		 6888 bool wake;
6889
749ab2cd 6890 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6891
6892 if (system_state == SYSTEM_POWER_OFF) {
6893 pci_wake_from_d3(pdev, wake);
6894 pci_set_power_state(pdev, PCI_D3hot);
6895 }
9d5c8243
AK		 6896}
6897
6898#ifdef CONFIG_NET_POLL_CONTROLLER
6899/*
6900 * Polling 'interrupt' - used by things like netconsole to send skbs
6901 * without having to re-enable interrupts. It's not called while
6902 * the interrupt routine is executing.
6903 */
6904static void igb_netpoll(struct net_device *netdev)
6905{
6906 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6907 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 6908 struct igb_q_vector *q_vector;
9d5c8243 6909 int i;
9d5c8243 6910
047e0030 6911 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 6912 q_vector = adapter->q_vector[i];
6913 if (adapter->msix_entries)
6914 wr32(E1000_EIMC, q_vector->eims_value);
6915 else
6916 igb_irq_disable(adapter);
047e0030 6917 napi_schedule(&q_vector->napi);
eebbbdba 6918 }
9d5c8243
AK		 6919}
6920#endif /* CONFIG_NET_POLL_CONTROLLER */
6921
6922/**
6923 * igb_io_error_detected - called when PCI error is detected
6924 * @pdev: Pointer to PCI device
6925 * @state: The current pci connection state
6926 *
6927 * This function is called after a PCI bus error affecting
6928 * this device has been detected.
6929 */
6930static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6931 pci_channel_state_t state)
6932{
6933 struct net_device *netdev = pci_get_drvdata(pdev);
6934 struct igb_adapter *adapter = netdev_priv(netdev);
6935
6936 netif_device_detach(netdev);
6937
59ed6eec
AD		 6938 if (state == pci_channel_io_perm_failure)
6939 return PCI_ERS_RESULT_DISCONNECT;
6940
9d5c8243
AK		 6941 if (netif_running(netdev))
6942 igb_down(adapter);
6943 pci_disable_device(pdev);
6944
6945 /* Request a slot slot reset. */
6946 return PCI_ERS_RESULT_NEED_RESET;
6947}
6948
6949/**
6950 * igb_io_slot_reset - called after the pci bus has been reset.
6951 * @pdev: Pointer to PCI device
6952 *
6953 * Restart the card from scratch, as if from a cold-boot. Implementation
6954 * resembles the first-half of the igb_resume routine.
6955 */
6956static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6957{
6958 struct net_device *netdev = pci_get_drvdata(pdev);
6959 struct igb_adapter *adapter = netdev_priv(netdev);
6960 struct e1000_hw *hw = &adapter->hw;
40a914fa 6961 pci_ers_result_t result;
42bfd33a 6962 int err;
9d5c8243 6963
aed5dec3 6964 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6965 dev_err(&pdev->dev,
6966 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6967 result = PCI_ERS_RESULT_DISCONNECT;
6968 } else {
6969 pci_set_master(pdev);
6970 pci_restore_state(pdev);
b94f2d77 6971 pci_save_state(pdev);
9d5c8243 6972
40a914fa
AD		 6973 pci_enable_wake(pdev, PCI_D3hot, 0);
6974 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6975
40a914fa
AD		 6976 igb_reset(adapter);
6977 wr32(E1000_WUS, ~0);
6978 result = PCI_ERS_RESULT_RECOVERED;
6979 }
9d5c8243 6980
ea943d41
JK		 6981 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6982 if (err) {
6983 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6984 "failed 0x%0x\n", err);
6985 /* non-fatal, continue */
6986 }
40a914fa
AD		 6987
6988 return result;
9d5c8243
AK		 6989}
6990
6991/**
6992 * igb_io_resume - called when traffic can start flowing again.
6993 * @pdev: Pointer to PCI device
6994 *
6995 * This callback is called when the error recovery driver tells us that
6996 * its OK to resume normal operation. Implementation resembles the
6997 * second-half of the igb_resume routine.
6998 */
6999static void igb_io_resume(struct pci_dev *pdev)
7000{
7001 struct net_device *netdev = pci_get_drvdata(pdev);
7002 struct igb_adapter *adapter = netdev_priv(netdev);
7003
9d5c8243
AK		 7004 if (netif_running(netdev)) {
7005 if (igb_up(adapter)) {
7006 dev_err(&pdev->dev, "igb_up failed after reset\n");
7007 return;
7008 }
7009 }
7010
7011 netif_device_attach(netdev);
7012
7013 /* let the f/w know that the h/w is now under the control of the
7014 * driver. */
7015 igb_get_hw_control(adapter);
9d5c8243
AK		 7016}
7017
26ad9178
AD		 7018static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7019 u8 qsel)
7020{
7021 u32 rar_low, rar_high;
7022 struct e1000_hw *hw = &adapter->hw;
7023
7024 /* HW expects these in little endian so we reverse the byte order
7025 * from network order (big endian) to little endian
7026 */
7027 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7028 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7029 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7030
7031 /* Indicate to hardware the Address is Valid. */
7032 rar_high |= E1000_RAH_AV;
7033
7034 if (hw->mac.type == e1000_82575)
7035 rar_high |= E1000_RAH_POOL_1 * qsel;
7036 else
7037 rar_high |= E1000_RAH_POOL_1 << qsel;
7038
7039 wr32(E1000_RAL(index), rar_low);
7040 wrfl();
7041 wr32(E1000_RAH(index), rar_high);
7042 wrfl();
7043}
7044
4ae196df
AD		 7045static int igb_set_vf_mac(struct igb_adapter *adapter,
7046 int vf, unsigned char *mac_addr)
7047{
7048 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7049 /* VF MAC addresses start at end of receive addresses and moves
7050 * torwards the first, as a result a collision should not be possible */
7051 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7052
37680117 7053 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7054
26ad9178 7055 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7056
7057 return 0;
7058}
7059
8151d294
WM		 7060static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7061{
7062 struct igb_adapter *adapter = netdev_priv(netdev);
7063 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7064 return -EINVAL;
7065 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7066 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7067 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7068 " change effective.");
7069 if (test_bit(__IGB_DOWN, &adapter->state)) {
7070 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7071 " but the PF device is not up.\n");
7072 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7073 " attempting to use the VF device.\n");
7074 }
7075 return igb_set_vf_mac(adapter, vf, mac);
7076}
7077
17dc566c
LL		 7078static int igb_link_mbps(int internal_link_speed)
7079{
7080 switch (internal_link_speed) {
7081 case SPEED_100:
7082 return 100;
7083 case SPEED_1000:
7084 return 1000;
7085 default:
7086 return 0;
7087 }
7088}
7089
7090static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7091 int link_speed)
7092{
7093 int rf_dec, rf_int;
7094 u32 bcnrc_val;
7095
7096 if (tx_rate != 0) {
7097 /* Calculate the rate factor values to set */
7098 rf_int = link_speed / tx_rate;
7099 rf_dec = (link_speed - (rf_int * tx_rate));
7100 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7101
7102 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7103 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7104 E1000_RTTBCNRC_RF_INT_MASK);
7105 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7106 } else {
7107 bcnrc_val = 0;
7108 }
7109
7110 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7111 /*
7112 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7113 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7114 */
7115 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7116 wr32(E1000_RTTBCNRC, bcnrc_val);
7117}
7118
7119static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7120{
7121 int actual_link_speed, i;
7122 bool reset_rate = false;
7123
7124 /* VF TX rate limit was not set or not supported */
7125 if ((adapter->vf_rate_link_speed == 0) ||
7126 (adapter->hw.mac.type != e1000_82576))
7127 return;
7128
7129 actual_link_speed = igb_link_mbps(adapter->link_speed);
7130 if (actual_link_speed != adapter->vf_rate_link_speed) {
7131 reset_rate = true;
7132 adapter->vf_rate_link_speed = 0;
7133 dev_info(&adapter->pdev->dev,
7134 "Link speed has been changed. VF Transmit "
7135 "rate is disabled\n");
7136 }
7137
7138 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7139 if (reset_rate)
7140 adapter->vf_data[i].tx_rate = 0;
7141
7142 igb_set_vf_rate_limit(&adapter->hw, i,
7143 adapter->vf_data[i].tx_rate,
7144 actual_link_speed);
7145 }
7146}
7147
8151d294
WM		 7148static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7149{
17dc566c
LL		 7150 struct igb_adapter *adapter = netdev_priv(netdev);
7151 struct e1000_hw *hw = &adapter->hw;
7152 int actual_link_speed;
7153
7154 if (hw->mac.type != e1000_82576)
7155 return -EOPNOTSUPP;
7156
7157 actual_link_speed = igb_link_mbps(adapter->link_speed);
7158 if ((vf >= adapter->vfs_allocated_count) ||
7159 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7160 (tx_rate < 0) || (tx_rate > actual_link_speed))
7161 return -EINVAL;
7162
7163 adapter->vf_rate_link_speed = actual_link_speed;
7164 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7165 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7166
7167 return 0;
8151d294
WM		 7168}
7169
7170static int igb_ndo_get_vf_config(struct net_device *netdev,
7171 int vf, struct ifla_vf_info *ivi)
7172{
7173 struct igb_adapter *adapter = netdev_priv(netdev);
7174 if (vf >= adapter->vfs_allocated_count)
7175 return -EINVAL;
7176 ivi->vf = vf;
7177 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7178 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7179 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7180 ivi->qos = adapter->vf_data[vf].pf_qos;
7181 return 0;
7182}
7183
4ae196df
AD		 7184static void igb_vmm_control(struct igb_adapter *adapter)
7185{
7186 struct e1000_hw *hw = &adapter->hw;
10d8e907 7187 u32 reg;
4ae196df 7188
52a1dd4d
AD		 7189 switch (hw->mac.type) {
7190 case e1000_82575:
f96a8a0b
CW		 7191 case e1000_i210:
7192 case e1000_i211:
52a1dd4d
AD		 7193 default:
7194 /* replication is not supported for 82575 */
4ae196df 7195 return;
52a1dd4d
AD		 7196 case e1000_82576:
7197 /* notify HW that the MAC is adding vlan tags */
7198 reg = rd32(E1000_DTXCTL);
7199 reg |= E1000_DTXCTL_VLAN_ADDED;
7200 wr32(E1000_DTXCTL, reg);
7201 case e1000_82580:
7202 /* enable replication vlan tag stripping */
7203 reg = rd32(E1000_RPLOLR);
7204 reg |= E1000_RPLOLR_STRVLAN;
7205 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7206 case e1000_i350:
7207 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7208 break;
7209 }
10d8e907 7210
d4960307
AD		 7211 if (adapter->vfs_allocated_count) {
7212 igb_vmdq_set_loopback_pf(hw, true);
7213 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7214 igb_vmdq_set_anti_spoofing_pf(hw, true,
7215 adapter->vfs_allocated_count);
d4960307
AD		 7216 } else {
7217 igb_vmdq_set_loopback_pf(hw, false);
7218 igb_vmdq_set_replication_pf(hw, false);
7219 }
4ae196df
AD		 7220}
7221
b6e0c419
CW		 7222static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7223{
7224 struct e1000_hw *hw = &adapter->hw;
7225 u32 dmac_thr;
7226 u16 hwm;
7227
7228 if (hw->mac.type > e1000_82580) {
7229 if (adapter->flags & IGB_FLAG_DMAC) {
7230 u32 reg;
7231
7232 /* force threshold to 0. */
7233 wr32(E1000_DMCTXTH, 0);
7234
7235 /*
e8c626e9
MV		 7236 * DMA Coalescing high water mark needs to be greater
7237 * than the Rx threshold. Set hwm to PBA - max frame
7238 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7239 */
e8c626e9
MV		 7240 hwm = 64 * pba - adapter->max_frame_size / 16;
7241 if (hwm < 64 * (pba - 6))
7242 hwm = 64 * (pba - 6);
7243 reg = rd32(E1000_FCRTC);
7244 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7245 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7246 & E1000_FCRTC_RTH_COAL_MASK);
7247 wr32(E1000_FCRTC, reg);
7248
7249 /*
7250 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7251 * frame size, capping it at PBA - 10KB.
7252 */
7253 dmac_thr = pba - adapter->max_frame_size / 512;
7254 if (dmac_thr < pba - 10)
7255 dmac_thr = pba - 10;
b6e0c419
CW		 7256 reg = rd32(E1000_DMACR);
7257 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7258 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7259 & E1000_DMACR_DMACTHR_MASK);
7260
7261 /* transition to L0x or L1 if available..*/
7262 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7263
7264 /* watchdog timer= +-1000 usec in 32usec intervals */
7265 reg |= (1000 >> 5);
0c02dd98
MV		 7266
7267 /* Disable BMC-to-OS Watchdog Enable */
7268 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7269 wr32(E1000_DMACR, reg);
7270
7271 /*
7272 * no lower threshold to disable
7273 * coalescing(smart fifb)-UTRESH=0
7274 */
7275 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7276
7277 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7278
7279 wr32(E1000_DMCTLX, reg);
7280
7281 /*
7282 * free space in tx packet buffer to wake from
7283 * DMA coal
7284 */
7285 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7286 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7287
7288 /*
7289 * make low power state decision controlled
7290 * by DMA coal
7291 */
7292 reg = rd32(E1000_PCIEMISC);
7293 reg &= ~E1000_PCIEMISC_LX_DECISION;
7294 wr32(E1000_PCIEMISC, reg);
7295 } /* endif adapter->dmac is not disabled */
7296 } else if (hw->mac.type == e1000_82580) {
7297 u32 reg = rd32(E1000_PCIEMISC);
7298 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7299 wr32(E1000_DMACR, 0);
7300 }
7301}
7302
9d5c8243 7303/* igb_main.c */
Linux kernel - Deliverables
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