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net: stmmac: avoid using timespec
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
6fb46902
TF		 60#define MIN 3
61#define BUILD 0
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 184#endif
9d5c8243 185
9d5c8243 186#ifdef CONFIG_PM
d9dd966d 187#ifdef CONFIG_PM_SLEEP
749ab2cd 188static int igb_suspend(struct device *);
d9dd966d 189#endif
749ab2cd 190static int igb_resume(struct device *);
749ab2cd
YZ		 191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
047e0030 949 struct e1000_hw *hw = &adapter->hw;
52285b76 950 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 951
047e0030 952 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 953 igb_msix_other, 0, netdev->name, adapter);
047e0030 954 if (err)
52285b76 955 goto err_out;
047e0030
AD		 956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
52285b76
SA		 960 vector++;
961
047e0030
AD		 962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
963
0ba82994 964 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
047e0030 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
047e0030 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 972 q_vector->rx.ring->queue_index);
9d5c8243 973 else
047e0030
AD		 974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
9d5c8243 976 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
9d5c8243 979 if (err)
52285b76 980 goto err_free;
9d5c8243
AK		 981 }
982
9d5c8243
AK		 983 igb_configure_msix(adapter);
984 return 0;
52285b76
SA		 985
986err_free:
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995err_out:
9d5c8243
AK		 996 return err;
997}
998
5536d210 999/**
b980ac18
JK		 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
5536d210 1003 *
02ef6e1d 1004 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
02ef6e1d
CW		 1010 adapter->q_vector[v_idx] = NULL;
1011
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
17a402a0
CW		 1015 if (q_vector)
1016 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1017}
1018
1019/**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
cb06d102
CP		 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
5536d210
AD		 1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
2439fc4d 1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1042
5536d210
AD		 1043 netif_napi_del(&q_vector->napi);
1044
02ef6e1d
CW		 1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
cd14ef54 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1052 pci_disable_msix(adapter->pdev);
cd14ef54 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1054 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1058}
1059
047e0030 1060/**
b980ac18
JK		 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
047e0030 1063 *
b980ac18
JK		 1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
047e0030
AD		 1067 **/
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
5536d210
AD		 1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
047e0030 1074 adapter->num_q_vectors = 0;
5536d210 1075
02ef6e1d
CW		 1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
5536d210 1078 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1079 }
047e0030
AD		 1080}
1081
1082/**
b980ac18
JK		 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
047e0030 1085 *
b980ac18
JK		 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
047e0030
AD		 1088 */
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
047e0030
AD		 1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
9d5c8243
AK		 1094
1095/**
b980ac18
JK		 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
9d5c8243 1099 *
b980ac18
JK		 1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
9d5c8243 1102 **/
53c7d064 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1104{
1105 int err;
1106 int numvecs, i;
1107
53c7d064
SA		 1108 if (!msix)
1109 goto msi_only;
cd14ef54 1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1111
83b7180d 1112 /* Number of supported queues. */
a99955fc 1113 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1118
b980ac18 1119 /* start with one vector for every Rx queue */
047e0030
AD		 1120 numvecs = adapter->num_rx_queues;
1121
b980ac18 1122 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
047e0030
AD		 1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
9d5c8243
AK		 1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
479d02df
AG		 1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
0c2cc02e 1139 return;
9d5c8243
AK		 1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144msi_only:
b709323d 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1146#ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1157 wrfl();
2a3abf6d
AD		 1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
4fc82adf 1162 adapter->vfs_allocated_count = 0;
a99955fc 1163 adapter->rss_queues = 1;
4fc82adf 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1165 adapter->num_rx_queues = 1;
661086df 1166 adapter->num_tx_queues = 1;
047e0030 1167 adapter->num_q_vectors = 1;
9d5c8243 1168 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1169 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1170}
1171
5536d210
AD		 1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
047e0030 1179/**
b980ac18
JK		 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
047e0030 1188 *
b980ac18 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1190 **/
5536d210
AD		 1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
047e0030
AD		 1195{
1196 struct igb_q_vector *q_vector;
5536d210
AD		 1197 struct igb_ring *ring;
1198 int ring_count, size;
047e0030 1199
5536d210
AD		 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
02ef6e1d 1209 q_vector = adapter->q_vector[v_idx];
72ddef05 1210 if (!q_vector) {
02ef6e1d 1211 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1212 } else if (size > ksize(q_vector)) {
1213 kfree_rcu(q_vector, rcu);
1214 q_vector = kzalloc(size, GFP_KERNEL);
1215 } else {
c0a06ee1 1216 memset(q_vector, 0, size);
72ddef05 1217 }
5536d210
AD		 1218 if (!q_vector)
1219 return -ENOMEM;
1220
1221 /* initialize NAPI */
1222 netif_napi_add(adapter->netdev, &q_vector->napi,
1223 igb_poll, 64);
1224
1225 /* tie q_vector and adapter together */
1226 adapter->q_vector[v_idx] = q_vector;
1227 q_vector->adapter = adapter;
1228
1229 /* initialize work limits */
1230 q_vector->tx.work_limit = adapter->tx_work_limit;
1231
1232 /* initialize ITR configuration */
1233 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1234 q_vector->itr_val = IGB_START_ITR;
1235
1236 /* initialize pointer to rings */
1237 ring = q_vector->ring;
1238
4e227667
AD		 1239 /* intialize ITR */
1240 if (rxr_count) {
1241 /* rx or rx/tx vector */
1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 q_vector->itr_val = adapter->rx_itr_setting;
1244 } else {
1245 /* tx only vector */
1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 q_vector->itr_val = adapter->tx_itr_setting;
1248 }
1249
5536d210
AD		 1250 if (txr_count) {
1251 /* assign generic ring traits */
1252 ring->dev = &adapter->pdev->dev;
1253 ring->netdev = adapter->netdev;
1254
1255 /* configure backlink on ring */
1256 ring->q_vector = q_vector;
1257
1258 /* update q_vector Tx values */
1259 igb_add_ring(ring, &q_vector->tx);
1260
1261 /* For 82575, context index must be unique per ring. */
1262 if (adapter->hw.mac.type == e1000_82575)
1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1264
1265 /* apply Tx specific ring traits */
1266 ring->count = adapter->tx_ring_count;
1267 ring->queue_index = txr_idx;
1268
827da44c
JS		 1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1271
5536d210
AD		 1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1274
1275 /* push pointer to next ring */
1276 ring++;
047e0030 1277 }
81c2fc22 1278
5536d210
AD		 1279 if (rxr_count) {
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
047e0030 1283
5536d210
AD		 1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
047e0030 1286
5536d210
AD		 1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
047e0030 1289
5536d210
AD		 1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1293
e52c0f96 1294 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1295 * have the tag byte-swapped.
b980ac18 1296 */
5536d210
AD		 1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1299
5536d210
AD		 1300 /* apply Rx specific ring traits */
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1303
827da44c
JS		 1304 u64_stats_init(&ring->rx_syncp);
1305
5536d210
AD		 1306 /* assign ring to adapter */
1307 adapter->rx_ring[rxr_idx] = ring;
1308 }
1309
1310 return 0;
047e0030
AD		 1311}
1312
5536d210 1313
047e0030 1314/**
b980ac18
JK		 1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316 * @adapter: board private structure to initialize
047e0030 1317 *
b980ac18
JK		 1318 * We allocate one q_vector per queue interrupt. If allocation fails we
1319 * return -ENOMEM.
047e0030 1320 **/
5536d210 1321static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1322{
5536d210
AD		 1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327 int err;
047e0030 1328
5536d210
AD		 1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332 0, 0, 1, rxr_idx);
047e0030 1333
5536d210
AD		 1334 if (err)
1335 goto err_out;
1336
1337 /* update counts and index */
1338 rxr_remaining--;
1339 rxr_idx++;
047e0030 1340 }
047e0030 1341 }
5536d210
AD		 1342
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1346
5536d210
AD		 1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1349
1350 if (err)
1351 goto err_out;
1352
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1356 rxr_idx++;
1357 txr_idx++;
1358 }
1359
047e0030 1360 return 0;
5536d210
AD		 1361
1362err_out:
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1366
1367 while (v_idx--)
1368 igb_free_q_vector(adapter, v_idx);
1369
1370 return -ENOMEM;
047e0030
AD		 1371}
1372
1373/**
b980ac18
JK		 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
047e0030 1377 *
b980ac18 1378 * This function initializes the interrupts and allocates all of the queues.
047e0030 1379 **/
53c7d064 1380static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1381{
1382 struct pci_dev *pdev = adapter->pdev;
1383 int err;
1384
53c7d064 1385 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1386
1387 err = igb_alloc_q_vectors(adapter);
1388 if (err) {
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1391 }
1392
5536d210 1393 igb_cache_ring_register(adapter);
047e0030
AD		 1394
1395 return 0;
5536d210 1396
047e0030
AD		 1397err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1399 return err;
1400}
1401
9d5c8243 1402/**
b980ac18
JK		 1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
9d5c8243 1405 *
b980ac18
JK		 1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
9d5c8243
AK		 1408 **/
1409static int igb_request_irq(struct igb_adapter *adapter)
1410{
1411 struct net_device *netdev = adapter->netdev;
047e0030 1412 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1413 int err = 0;
1414
cd14ef54 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1416 err = igb_request_msix(adapter);
844290e5 1417 if (!err)
9d5c8243 1418 goto request_done;
9d5c8243 1419 /* fall back to MSI */
5536d210
AD		 1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
53c7d064 1422
047e0030 1423 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1424 err = igb_init_interrupt_scheme(adapter, false);
1425 if (err)
047e0030 1426 goto request_done;
53c7d064 1427
047e0030
AD		 1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
53c7d064 1430 igb_configure(adapter);
9d5c8243 1431 }
844290e5 1432
c74d588e
AD		 1433 igb_assign_vector(adapter->q_vector[0], 0);
1434
7dfc16fa 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1437 netdev->name, adapter);
9d5c8243
AK		 1438 if (!err)
1439 goto request_done;
047e0030 1440
9d5c8243
AK		 1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
7dfc16fa 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1444 }
1445
c74d588e 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1447 netdev->name, adapter);
9d5c8243 1448
6cb5e577 1449 if (err)
c74d588e 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1451 err);
9d5c8243
AK		 1452
1453request_done:
1454 return err;
1455}
1456
1457static void igb_free_irq(struct igb_adapter *adapter)
1458{
cd14ef54 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1460 int vector = 0, i;
1461
047e0030 1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1463
0d1ae7f4 1464 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1465 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1466 adapter->q_vector[i]);
047e0030
AD		 1467 } else {
1468 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1469 }
9d5c8243
AK		 1470}
1471
1472/**
b980ac18
JK		 1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
9d5c8243
AK		 1475 **/
1476static void igb_irq_disable(struct igb_adapter *adapter)
1477{
1478 struct e1000_hw *hw = &adapter->hw;
1479
b980ac18 1480 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1483 */
cd14ef54 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1485 u32 regval = rd32(E1000_EIAM);
9005df38 1486
2dfd1212
AD		 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1491 }
844290e5
PW		 1492
1493 wr32(E1000_IAM, 0);
9d5c8243
AK		 1494 wr32(E1000_IMC, ~0);
1495 wrfl();
cd14ef54 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1497 int i;
9005df38 1498
81a61859
ET		 1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1501 } else {
1502 synchronize_irq(adapter->pdev->irq);
1503 }
9d5c8243
AK		 1504}
1505
1506/**
b980ac18
JK		 1507 * igb_irq_enable - Enable default interrupt generation settings
1508 * @adapter: board private structure
9d5c8243
AK		 1509 **/
1510static void igb_irq_enable(struct igb_adapter *adapter)
1511{
1512 struct e1000_hw *hw = &adapter->hw;
1513
cd14ef54 1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1516 u32 regval = rd32(E1000_EIAC);
9005df38 1517
2dfd1212
AD		 1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1522 if (adapter->vfs_allocated_count) {
4ae196df 1523 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1524 ims |= E1000_IMS_VMMB;
1525 }
1526 wr32(E1000_IMS, ims);
844290e5 1527 } else {
55cac248
AD		 1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529 E1000_IMS_DRSTA);
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531 E1000_IMS_DRSTA);
844290e5 1532 }
9d5c8243
AK		 1533}
1534
1535static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536{
51466239 1537 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
1543 igb_vfta_set(hw, vid, true);
1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
b2cb09b1 1551 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1552 /* remove VID from filter table */
1553 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1554 }
1555}
1556
1557/**
b980ac18
JK		 1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
9d5c8243 1560 *
b980ac18
JK		 1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
9d5c8243
AK		 1564 **/
1565static void igb_release_hw_control(struct igb_adapter *adapter)
1566{
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574}
1575
9d5c8243 1576/**
b980ac18
JK		 1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
9d5c8243 1579 *
b980ac18
JK		 1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
9d5c8243
AK		 1583 **/
1584static void igb_get_hw_control(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593}
1594
9d5c8243 1595/**
b980ac18
JK		 1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
9d5c8243
AK		 1598 **/
1599static void igb_configure(struct igb_adapter *adapter)
1600{
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
ff41f8dc 1605 igb_set_rx_mode(netdev);
9d5c8243
AK		 1606
1607 igb_restore_vlan(adapter);
9d5c8243 1608
85b430b4 1609 igb_setup_tctl(adapter);
06cf2666 1610 igb_setup_mrqc(adapter);
9d5c8243 1611 igb_setup_rctl(adapter);
85b430b4
AD		 1612
1613 igb_configure_tx(adapter);
9d5c8243 1614 igb_configure_rx(adapter);
662d7205
AD		 1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
c493ea45 1618 /* call igb_desc_unused which always leaves
9d5c8243 1619 * at least 1 descriptor unused to make sure
b980ac18
JK		 1620 * next_to_use != next_to_clean
1621 */
9d5c8243 1622 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1623 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1625 }
9d5c8243
AK		 1626}
1627
88a268c1 1628/**
b980ac18
JK		 1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
88a268c1
NN		 1631 **/
1632void igb_power_up_link(struct igb_adapter *adapter)
1633{
76886596
AA		 1634 igb_reset_phy(&adapter->hw);
1635
88a268c1
NN		 1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1640
1641 igb_setup_link(&adapter->hw);
88a268c1
NN		 1642}
1643
1644/**
b980ac18
JK		 1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
88a268c1
NN		 1647 */
1648static void igb_power_down_link(struct igb_adapter *adapter)
1649{
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654}
9d5c8243 1655
56cec249
CW		 1656/**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660static void igb_check_swap_media(struct igb_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721}
1722
9d5c8243 1723/**
b980ac18
JK		 1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
9d5c8243 1726 **/
9d5c8243
AK		 1727int igb_up(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
0d1ae7f4
AD		 1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
cd14ef54 1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1741 igb_configure_msix(adapter);
feeb2721
AD		 1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
d4960307
AD		 1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1752
d4960307
AD		 1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
4cb9be7a
JB		 1757 netif_tx_start_all_queues(adapter->netdev);
1758
25568a53
AD		 1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
f4c01e96
CW		 1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
9d5c8243
AK		 1767 return 0;
1768}
1769
1770void igb_down(struct igb_adapter *adapter)
1771{
9d5c8243 1772 struct net_device *netdev = adapter->netdev;
330a6d6a 1773 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1778 * reschedule our watchdog timer
1779 */
9d5c8243
AK		 1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
f28ea083 1787 netif_carrier_off(netdev);
fd2ea0a7 1788 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
0d451e79 1796 usleep_range(10000, 11000);
9d5c8243 1797
41f149a2
CW		 1798 igb_irq_disable(adapter);
1799
aa9b8cc4
AA		 1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
41f149a2 1802 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
41f149a2 1807 }
9d5c8243 1808
9d5c8243
AK		 1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
04fe6358 1812 /* record the stats before reset*/
12dcd86b
ED		 1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
04fe6358 1816
9d5c8243
AK		 1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
3023682e
JK		 1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
9d5c8243
AK		 1822 igb_clean_all_tx_rings(adapter);
1823 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1824#ifdef CONFIG_IGB_DCA
1825
1826 /* since we reset the hardware DCA settings were cleared */
1827 igb_setup_dca(adapter);
1828#endif
9d5c8243
AK		 1829}
1830
1831void igb_reinit_locked(struct igb_adapter *adapter)
1832{
1833 WARN_ON(in_interrupt());
1834 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1835 usleep_range(1000, 2000);
9d5c8243
AK		 1836 igb_down(adapter);
1837 igb_up(adapter);
1838 clear_bit(__IGB_RESETTING, &adapter->state);
1839}
1840
56cec249
CW		 1841/** igb_enable_mas - Media Autosense re-enable after swap
1842 *
1843 * @adapter: adapter struct
1844 **/
8cfb879d 1845static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1846{
1847 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1848 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1849
1850 /* configure for SerDes media detect */
8cfb879d
TF		 1851 if ((hw->phy.media_type == e1000_media_type_copper) &&
1852 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1853 connsw |= E1000_CONNSW_ENRGSRC;
1854 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1855 wr32(E1000_CONNSW, connsw);
1856 wrfl();
56cec249 1857 }
56cec249
CW		 1858}
1859
9d5c8243
AK		 1860void igb_reset(struct igb_adapter *adapter)
1861{
090b1795 1862 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1863 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1864 struct e1000_mac_info *mac = &hw->mac;
1865 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1866 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1867
1868 /* Repartition Pba for greater than 9k mtu
1869 * To take effect CTRL.RST is required.
1870 */
fa4dfae0 1871 switch (mac->type) {
d2ba2ed8 1872 case e1000_i350:
ceb5f13b 1873 case e1000_i354:
55cac248
AD		 1874 case e1000_82580:
1875 pba = rd32(E1000_RXPBS);
1876 pba = igb_rxpbs_adjust_82580(pba);
1877 break;
fa4dfae0 1878 case e1000_82576:
d249be54
AD		 1879 pba = rd32(E1000_RXPBS);
1880 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1881 break;
1882 case e1000_82575:
f96a8a0b
CW		 1883 case e1000_i210:
1884 case e1000_i211:
fa4dfae0
AD		 1885 default:
1886 pba = E1000_PBA_34K;
1887 break;
2d064c06 1888 }
9d5c8243 1889
2d064c06
AD		 1890 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1891 (mac->type < e1000_82576)) {
9d5c8243
AK		 1892 /* adjust PBA for jumbo frames */
1893 wr32(E1000_PBA, pba);
1894
1895 /* To maintain wire speed transmits, the Tx FIFO should be
1896 * large enough to accommodate two full transmit packets,
1897 * rounded up to the next 1KB and expressed in KB. Likewise,
1898 * the Rx FIFO should be large enough to accommodate at least
1899 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1900 * expressed in KB.
1901 */
9d5c8243
AK		 1902 pba = rd32(E1000_PBA);
1903 /* upper 16 bits has Tx packet buffer allocation size in KB */
1904 tx_space = pba >> 16;
1905 /* lower 16 bits has Rx packet buffer allocation size in KB */
1906 pba &= 0xffff;
b980ac18
JK		 1907 /* the Tx fifo also stores 16 bytes of information about the Tx
1908 * but don't include ethernet FCS because hardware appends it
1909 */
9d5c8243 1910 min_tx_space = (adapter->max_frame_size +
85e8d004 1911 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1912 ETH_FCS_LEN) * 2;
1913 min_tx_space = ALIGN(min_tx_space, 1024);
1914 min_tx_space >>= 10;
1915 /* software strips receive CRC, so leave room for it */
1916 min_rx_space = adapter->max_frame_size;
1917 min_rx_space = ALIGN(min_rx_space, 1024);
1918 min_rx_space >>= 10;
1919
1920 /* If current Tx allocation is less than the min Tx FIFO size,
1921 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1922 * allocation, take space away from current Rx allocation
1923 */
9d5c8243
AK		 1924 if (tx_space < min_tx_space &&
1925 ((min_tx_space - tx_space) < pba)) {
1926 pba = pba - (min_tx_space - tx_space);
1927
b980ac18
JK		 1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
9d5c8243
AK		 1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
2d064c06 1934 wr32(E1000_PBA, pba);
9d5c8243 1935 }
9d5c8243
AK		 1936
1937 /* flow control settings */
1938 /* The high water mark must be low enough to fit one full frame
1939 * (or the size used for early receive) above it in the Rx FIFO.
1940 * Set it to the lower of:
1941 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1942 * - the full Rx FIFO size minus one full frame
1943 */
9d5c8243 1944 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1945 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1946
d48507fe 1947 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1948 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1949 fc->pause_time = 0xFFFF;
1950 fc->send_xon = 1;
0cce119a 1951 fc->current_mode = fc->requested_mode;
9d5c8243 1952
4ae196df
AD		 1953 /* disable receive for all VFs and wait one second */
1954 if (adapter->vfs_allocated_count) {
1955 int i;
9005df38 1956
4ae196df 1957 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1958 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1959
1960 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1961 igb_ping_all_vfs(adapter);
4ae196df
AD		 1962
1963 /* disable transmits and receives */
1964 wr32(E1000_VFRE, 0);
1965 wr32(E1000_VFTE, 0);
1966 }
1967
9d5c8243 1968 /* Allow time for pending master requests to run */
330a6d6a 1969 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1970 wr32(E1000_WUC, 0);
1971
56cec249
CW		 1972 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1973 /* need to resetup here after media swap */
1974 adapter->ei.get_invariants(hw);
1975 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1976 }
8cfb879d
TF		 1977 if ((mac->type == e1000_82575) &&
1978 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1979 igb_enable_mas(adapter);
56cec249 1980 }
330a6d6a 1981 if (hw->mac.ops.init_hw(hw))
090b1795 1982 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1983
b980ac18 1984 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1985 * control is off when forcing speed.
1986 */
1987 if (!hw->mac.autoneg)
1988 igb_force_mac_fc(hw);
1989
b6e0c419 1990 igb_init_dmac(adapter, pba);
e428893b
CW		 1991#ifdef CONFIG_IGB_HWMON
1992 /* Re-initialize the thermal sensor on i350 devices. */
1993 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1994 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1995 /* If present, re-initialize the external thermal sensor
1996 * interface.
1997 */
1998 if (adapter->ets)
1999 mac->ops.init_thermal_sensor_thresh(hw);
2000 }
2001 }
2002#endif
b936136d 2003 /* Re-establish EEE setting */
f4c01e96
CW		 2004 if (hw->phy.media_type == e1000_media_type_copper) {
2005 switch (mac->type) {
2006 case e1000_i350:
2007 case e1000_i210:
2008 case e1000_i211:
c4c112f1 2009 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2010 break;
2011 case e1000_i354:
c4c112f1 2012 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2013 break;
2014 default:
2015 break;
2016 }
2017 }
88a268c1
NN		 2018 if (!netif_running(adapter->netdev))
2019 igb_power_down_link(adapter);
2020
9d5c8243
AK		 2021 igb_update_mng_vlan(adapter);
2022
2023 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2024 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2025
1f6e8178
MV		 2026 /* Re-enable PTP, where applicable. */
2027 igb_ptp_reset(adapter);
1f6e8178 2028
330a6d6a 2029 igb_get_phy_info(hw);
9d5c8243
AK		 2030}
2031
c8f44aff
MM		 2032static netdev_features_t igb_fix_features(struct net_device *netdev,
2033 netdev_features_t features)
b2cb09b1 2034{
b980ac18
JK		 2035 /* Since there is no support for separate Rx/Tx vlan accel
2036 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2037 */
f646968f
PM		 2038 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2039 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2040 else
f646968f 2041 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2042
2043 return features;
2044}
2045
c8f44aff
MM		 2046static int igb_set_features(struct net_device *netdev,
2047 netdev_features_t features)
ac52caa3 2048{
c8f44aff 2049 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2050 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2051
f646968f 2052 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2053 igb_vlan_mode(netdev, features);
2054
89eaefb6
BG		 2055 if (!(changed & NETIF_F_RXALL))
2056 return 0;
2057
2058 netdev->features = features;
2059
2060 if (netif_running(netdev))
2061 igb_reinit_locked(adapter);
2062 else
2063 igb_reset(adapter);
2064
ac52caa3
MM		 2065 return 0;
2066}
2067
2e5c6922 2068static const struct net_device_ops igb_netdev_ops = {
559e9c49 2069 .ndo_open = igb_open,
2e5c6922 2070 .ndo_stop = igb_close,
cd392f5c 2071 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2072 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2073 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2074 .ndo_set_mac_address = igb_set_mac,
2075 .ndo_change_mtu = igb_change_mtu,
2076 .ndo_do_ioctl = igb_ioctl,
2077 .ndo_tx_timeout = igb_tx_timeout,
2078 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2079 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2080 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2081 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2082 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2083 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2084 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2085 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2086#ifdef CONFIG_NET_POLL_CONTROLLER
2087 .ndo_poll_controller = igb_netpoll,
2088#endif
b2cb09b1
JP		 2089 .ndo_fix_features = igb_fix_features,
2090 .ndo_set_features = igb_set_features,
1abbc98a 2091 .ndo_features_check = passthru_features_check,
2e5c6922
SH		 2092};
2093
d67974f0
CW		 2094/**
2095 * igb_set_fw_version - Configure version string for ethtool
2096 * @adapter: adapter struct
d67974f0
CW		 2097 **/
2098void igb_set_fw_version(struct igb_adapter *adapter)
2099{
2100 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2101 struct e1000_fw_version fw;
2102
2103 igb_get_fw_version(hw, &fw);
2104
2105 switch (hw->mac.type) {
7dc98a62 2106 case e1000_i210:
0b1a6f2e 2107 case e1000_i211:
7dc98a62
CW		 2108 if (!(igb_get_flash_presence_i210(hw))) {
2109 snprintf(adapter->fw_version,
2110 sizeof(adapter->fw_version),
2111 "%2d.%2d-%d",
2112 fw.invm_major, fw.invm_minor,
2113 fw.invm_img_type);
2114 break;
2115 }
2116 /* fall through */
0b1a6f2e
CW		 2117 default:
2118 /* if option is rom valid, display its version too */
2119 if (fw.or_valid) {
2120 snprintf(adapter->fw_version,
2121 sizeof(adapter->fw_version),
2122 "%d.%d, 0x%08x, %d.%d.%d",
2123 fw.eep_major, fw.eep_minor, fw.etrack_id,
2124 fw.or_major, fw.or_build, fw.or_patch);
2125 /* no option rom */
7dc98a62 2126 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2127 snprintf(adapter->fw_version,
7dc98a62
CW		 2128 sizeof(adapter->fw_version),
2129 "%d.%d, 0x%08x",
2130 fw.eep_major, fw.eep_minor, fw.etrack_id);
2131 } else {
2132 snprintf(adapter->fw_version,
2133 sizeof(adapter->fw_version),
2134 "%d.%d.%d",
2135 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2136 }
2137 break;
d67974f0 2138 }
d67974f0
CW		 2139}
2140
56cec249
CW		 2141/**
2142 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2143 *
2144 * @adapter: adapter struct
2145 **/
2146static void igb_init_mas(struct igb_adapter *adapter)
2147{
2148 struct e1000_hw *hw = &adapter->hw;
2149 u16 eeprom_data;
2150
2151 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2152 switch (hw->bus.func) {
2153 case E1000_FUNC_0:
2154 if (eeprom_data & IGB_MAS_ENABLE_0) {
2155 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2156 netdev_info(adapter->netdev,
2157 "MAS: Enabling Media Autosense for port %d\n",
2158 hw->bus.func);
2159 }
2160 break;
2161 case E1000_FUNC_1:
2162 if (eeprom_data & IGB_MAS_ENABLE_1) {
2163 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2164 netdev_info(adapter->netdev,
2165 "MAS: Enabling Media Autosense for port %d\n",
2166 hw->bus.func);
2167 }
2168 break;
2169 case E1000_FUNC_2:
2170 if (eeprom_data & IGB_MAS_ENABLE_2) {
2171 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2172 netdev_info(adapter->netdev,
2173 "MAS: Enabling Media Autosense for port %d\n",
2174 hw->bus.func);
2175 }
2176 break;
2177 case E1000_FUNC_3:
2178 if (eeprom_data & IGB_MAS_ENABLE_3) {
2179 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2180 netdev_info(adapter->netdev,
2181 "MAS: Enabling Media Autosense for port %d\n",
2182 hw->bus.func);
2183 }
2184 break;
2185 default:
2186 /* Shouldn't get here */
2187 netdev_err(adapter->netdev,
2188 "MAS: Invalid port configuration, returning\n");
2189 break;
2190 }
2191}
2192
b980ac18
JK		 2193/**
2194 * igb_init_i2c - Init I2C interface
441fc6fd 2195 * @adapter: pointer to adapter structure
b980ac18 2196 **/
441fc6fd
CW		 2197static s32 igb_init_i2c(struct igb_adapter *adapter)
2198{
23d87824 2199 s32 status = 0;
441fc6fd
CW		 2200
2201 /* I2C interface supported on i350 devices */
2202 if (adapter->hw.mac.type != e1000_i350)
23d87824 2203 return 0;
441fc6fd
CW		 2204
2205 /* Initialize the i2c bus which is controlled by the registers.
2206 * This bus will use the i2c_algo_bit structue that implements
2207 * the protocol through toggling of the 4 bits in the register.
2208 */
2209 adapter->i2c_adap.owner = THIS_MODULE;
2210 adapter->i2c_algo = igb_i2c_algo;
2211 adapter->i2c_algo.data = adapter;
2212 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2213 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2214 strlcpy(adapter->i2c_adap.name, "igb BB",
2215 sizeof(adapter->i2c_adap.name));
2216 status = i2c_bit_add_bus(&adapter->i2c_adap);
2217 return status;
2218}
2219
9d5c8243 2220/**
b980ac18
JK		 2221 * igb_probe - Device Initialization Routine
2222 * @pdev: PCI device information struct
2223 * @ent: entry in igb_pci_tbl
9d5c8243 2224 *
b980ac18 2225 * Returns 0 on success, negative on failure
9d5c8243 2226 *
b980ac18
JK		 2227 * igb_probe initializes an adapter identified by a pci_dev structure.
2228 * The OS initialization, configuring of the adapter private structure,
2229 * and a hardware reset occur.
9d5c8243 2230 **/
1dd06ae8 2231static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2232{
2233 struct net_device *netdev;
2234 struct igb_adapter *adapter;
2235 struct e1000_hw *hw;
4337e993 2236 u16 eeprom_data = 0;
9835fd73 2237 s32 ret_val;
4337e993 2238 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2239 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2240 int err, pci_using_dac;
9835fd73 2241 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2242
bded64a7
AG		 2243 /* Catch broken hardware that put the wrong VF device ID in
2244 * the PCIe SR-IOV capability.
2245 */
2246 if (pdev->is_virtfn) {
2247 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2248 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2249 return -EINVAL;
2250 }
2251
aed5dec3 2252 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2253 if (err)
2254 return err;
2255
2256 pci_using_dac = 0;
dc4ff9bb 2257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2258 if (!err) {
dc4ff9bb 2259 pci_using_dac = 1;
9d5c8243 2260 } else {
dc4ff9bb 2261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2262 if (err) {
dc4ff9bb
RK		 2263 dev_err(&pdev->dev,
2264 "No usable DMA configuration, aborting\n");
2265 goto err_dma;
9d5c8243
AK		 2266 }
2267 }
2268
aed5dec3 2269 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2270 IORESOURCE_MEM),
2271 igb_driver_name);
9d5c8243
AK		 2272 if (err)
2273 goto err_pci_reg;
2274
19d5afd4 2275 pci_enable_pcie_error_reporting(pdev);
40a914fa 2276
9d5c8243 2277 pci_set_master(pdev);
c682fc23 2278 pci_save_state(pdev);
9d5c8243
AK		 2279
2280 err = -ENOMEM;
1bfaf07b 2281 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2282 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2283 if (!netdev)
2284 goto err_alloc_etherdev;
2285
2286 SET_NETDEV_DEV(netdev, &pdev->dev);
2287
2288 pci_set_drvdata(pdev, netdev);
2289 adapter = netdev_priv(netdev);
2290 adapter->netdev = netdev;
2291 adapter->pdev = pdev;
2292 hw = &adapter->hw;
2293 hw->back = adapter;
b3f4d599 2294 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2295
9d5c8243 2296 err = -EIO;
89dbefb2 2297 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2298 if (!hw->hw_addr)
9d5c8243
AK		 2299 goto err_ioremap;
2300
2e5c6922 2301 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2302 igb_set_ethtool_ops(netdev);
9d5c8243 2303 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2304
2305 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2306
89dbefb2
AS		 2307 netdev->mem_start = pci_resource_start(pdev, 0);
2308 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2309
9d5c8243
AK		 2310 /* PCI config space info */
2311 hw->vendor_id = pdev->vendor;
2312 hw->device_id = pdev->device;
2313 hw->revision_id = pdev->revision;
2314 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2315 hw->subsystem_device_id = pdev->subsystem_device;
2316
9d5c8243
AK		 2317 /* Copy the default MAC, PHY and NVM function pointers */
2318 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2319 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2320 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2321 /* Initialize skew-specific constants */
2322 err = ei->get_invariants(hw);
2323 if (err)
450c87c8 2324 goto err_sw_init;
9d5c8243 2325
450c87c8 2326 /* setup the private structure */
9d5c8243
AK		 2327 err = igb_sw_init(adapter);
2328 if (err)
2329 goto err_sw_init;
2330
2331 igb_get_bus_info_pcie(hw);
2332
2333 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2334
2335 /* Copper options */
2336 if (hw->phy.media_type == e1000_media_type_copper) {
2337 hw->phy.mdix = AUTO_ALL_MODES;
2338 hw->phy.disable_polarity_correction = false;
2339 hw->phy.ms_type = e1000_ms_hw_default;
2340 }
2341
2342 if (igb_check_reset_block(hw))
2343 dev_info(&pdev->dev,
2344 "PHY reset is blocked due to SOL/IDER session.\n");
2345
b980ac18 2346 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2347 * set by igb_sw_init so we should use an or instead of an
2348 * assignment.
2349 */
2350 netdev->features |= NETIF_F_SG |
2351 NETIF_F_IP_CSUM |
2352 NETIF_F_IPV6_CSUM |
2353 NETIF_F_TSO |
2354 NETIF_F_TSO6 |
2355 NETIF_F_RXHASH |
2356 NETIF_F_RXCSUM |
f646968f
PM		 2357 NETIF_F_HW_VLAN_CTAG_RX |
2358 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2359
2360 /* copy netdev features into list of user selectable features */
2361 netdev->hw_features |= netdev->features;
89eaefb6 2362 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2363
2364 /* set this bit last since it cannot be part of hw_features */
f646968f 2365 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2366
2367 netdev->vlan_features |= NETIF_F_TSO |
2368 NETIF_F_TSO6 |
2369 NETIF_F_IP_CSUM |
2370 NETIF_F_IPV6_CSUM |
2371 NETIF_F_SG;
48f29ffc 2372
6b8f0922
BG		 2373 netdev->priv_flags |= IFF_SUPP_NOFCS;
2374
7b872a55 2375 if (pci_using_dac) {
9d5c8243 2376 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2377 netdev->vlan_features |= NETIF_F_HIGHDMA;
2378 }
9d5c8243 2379
ac52caa3
MM		 2380 if (hw->mac.type >= e1000_82576) {
2381 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2382 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2383 }
b9473560 2384
01789349
JP		 2385 netdev->priv_flags |= IFF_UNICAST_FLT;
2386
330a6d6a 2387 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2388
2389 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2390 * known good starting state
2391 */
9d5c8243
AK		 2392 hw->mac.ops.reset_hw(hw);
2393
ef3a0092
CW		 2394 /* make sure the NVM is good , i211/i210 parts can have special NVM
2395 * that doesn't contain a checksum
f96a8a0b 2396 */
ef3a0092
CW		 2397 switch (hw->mac.type) {
2398 case e1000_i210:
2399 case e1000_i211:
2400 if (igb_get_flash_presence_i210(hw)) {
2401 if (hw->nvm.ops.validate(hw) < 0) {
2402 dev_err(&pdev->dev,
2403 "The NVM Checksum Is Not Valid\n");
2404 err = -EIO;
2405 goto err_eeprom;
2406 }
2407 }
2408 break;
2409 default:
f96a8a0b
CW		 2410 if (hw->nvm.ops.validate(hw) < 0) {
2411 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2412 err = -EIO;
2413 goto err_eeprom;
2414 }
ef3a0092 2415 break;
9d5c8243
AK		 2416 }
2417
2418 /* copy the MAC address out of the NVM */
2419 if (hw->mac.ops.read_mac_addr(hw))
2420 dev_err(&pdev->dev, "NVM Read Error\n");
2421
2422 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2423
aaeb6cdf 2424 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2425 dev_err(&pdev->dev, "Invalid MAC Address\n");
2426 err = -EIO;
2427 goto err_eeprom;
2428 }
2429
d67974f0
CW		 2430 /* get firmware version for ethtool -i */
2431 igb_set_fw_version(adapter);
2432
27dff8b2
TF		 2433 /* configure RXPBSIZE and TXPBSIZE */
2434 if (hw->mac.type == e1000_i210) {
2435 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2436 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2437 }
2438
c061b18d 2439 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2440 (unsigned long) adapter);
c061b18d 2441 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2442 (unsigned long) adapter);
9d5c8243
AK		 2443
2444 INIT_WORK(&adapter->reset_task, igb_reset_task);
2445 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2446
450c87c8 2447 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2448 adapter->fc_autoneg = true;
2449 hw->mac.autoneg = true;
2450 hw->phy.autoneg_advertised = 0x2f;
2451
0cce119a
AD		 2452 hw->fc.requested_mode = e1000_fc_default;
2453 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2454
9d5c8243
AK		 2455 igb_validate_mdi_setting(hw);
2456
63d4a8f9 2457 /* By default, support wake on port A */
a2cf8b6c 2458 if (hw->bus.func == 0)
63d4a8f9
MV		 2459 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2460
2461 /* Check the NVM for wake support on non-port A ports */
2462 if (hw->mac.type >= e1000_82580)
55cac248 2463 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2464 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2465 &eeprom_data);
a2cf8b6c
AD		 2466 else if (hw->bus.func == 1)
2467 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2468
63d4a8f9
MV		 2469 if (eeprom_data & IGB_EEPROM_APME)
2470 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2471
2472 /* now that we have the eeprom settings, apply the special cases where
2473 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2474 * lan on a particular port
2475 */
9d5c8243
AK		 2476 switch (pdev->device) {
2477 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2478 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2479 break;
2480 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2481 case E1000_DEV_ID_82576_FIBER:
2482 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2483 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2484 * regardless of eeprom setting
2485 */
9d5c8243 2486 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2488 break;
c8ea5ea9 2489 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2490 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2491 /* if quad port adapter, disable WoL on all but port A */
2492 if (global_quad_port_a != 0)
63d4a8f9 2493 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2494 else
2495 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2496 /* Reset for multiple quad port adapters */
2497 if (++global_quad_port_a == 4)
2498 global_quad_port_a = 0;
2499 break;
63d4a8f9
MV		 2500 default:
2501 /* If the device can't wake, don't set software support */
2502 if (!device_can_wakeup(&adapter->pdev->dev))
2503 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2504 }
2505
2506 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2507 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2508 adapter->wol |= E1000_WUFC_MAG;
2509
2510 /* Some vendors want WoL disabled by default, but still supported */
2511 if ((hw->mac.type == e1000_i350) &&
2512 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2514 adapter->wol = 0;
2515 }
2516
2517 device_set_wakeup_enable(&adapter->pdev->dev,
2518 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2519
2520 /* reset the hardware with the new settings */
2521 igb_reset(adapter);
2522
441fc6fd
CW		 2523 /* Init the I2C interface */
2524 err = igb_init_i2c(adapter);
2525 if (err) {
2526 dev_err(&pdev->dev, "failed to init i2c interface\n");
2527 goto err_eeprom;
2528 }
2529
9d5c8243 2530 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2531 * driver.
2532 */
9d5c8243
AK		 2533 igb_get_hw_control(adapter);
2534
9d5c8243
AK		 2535 strcpy(netdev->name, "eth%d");
2536 err = register_netdev(netdev);
2537 if (err)
2538 goto err_register;
2539
b168dfc5
JB		 2540 /* carrier off reporting is important to ethtool even BEFORE open */
2541 netif_carrier_off(netdev);
2542
421e02f0 2543#ifdef CONFIG_IGB_DCA
bbd98fe4 2544 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2545 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2546 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2547 igb_setup_dca(adapter);
2548 }
fe4506b6 2549
38c845c7 2550#endif
e428893b
CW		 2551#ifdef CONFIG_IGB_HWMON
2552 /* Initialize the thermal sensor on i350 devices. */
2553 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2554 u16 ets_word;
3c89f6d0 2555
b980ac18 2556 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2557 * external thermal sensor.
2558 */
2559 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2560 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2561 adapter->ets = true;
2562 else
2563 adapter->ets = false;
2564 if (igb_sysfs_init(adapter))
2565 dev_err(&pdev->dev,
2566 "failed to allocate sysfs resources\n");
2567 } else {
2568 adapter->ets = false;
2569 }
2570#endif
56cec249
CW		 2571 /* Check if Media Autosense is enabled */
2572 adapter->ei = *ei;
2573 if (hw->dev_spec._82575.mas_capable)
2574 igb_init_mas(adapter);
2575
673b8b70 2576 /* do hw tstamp init after resetting */
7ebae817 2577 igb_ptp_init(adapter);
673b8b70 2578
9d5c8243 2579 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2580 /* print bus type/speed/width info, not applicable to i354 */
2581 if (hw->mac.type != e1000_i354) {
2582 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2583 netdev->name,
2584 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2585 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2586 "unknown"),
2587 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2588 "Width x4" :
2589 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2590 "Width x2" :
2591 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2592 "Width x1" : "unknown"), netdev->dev_addr);
2593 }
9d5c8243 2594
53ea6c7e
TF		 2595 if ((hw->mac.type >= e1000_i210 ||
2596 igb_get_flash_presence_i210(hw))) {
2597 ret_val = igb_read_part_string(hw, part_str,
2598 E1000_PBANUM_LENGTH);
2599 } else {
2600 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2601 }
2602
9835fd73
CW		 2603 if (ret_val)
2604 strcpy(part_str, "Unknown");
2605 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2606 dev_info(&pdev->dev,
2607 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2608 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2609 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2610 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2611 if (hw->phy.media_type == e1000_media_type_copper) {
2612 switch (hw->mac.type) {
2613 case e1000_i350:
2614 case e1000_i210:
2615 case e1000_i211:
2616 /* Enable EEE for internal copper PHY devices */
c4c112f1 2617 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2618 if ((!err) &&
2619 (!hw->dev_spec._82575.eee_disable)) {
2620 adapter->eee_advert =
2621 MDIO_EEE_100TX | MDIO_EEE_1000T;
2622 adapter->flags |= IGB_FLAG_EEE;
2623 }
2624 break;
2625 case e1000_i354:
ceb5f13b 2626 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2627 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2628 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2629 if ((!err) &&
2630 (!hw->dev_spec._82575.eee_disable)) {
2631 adapter->eee_advert =
2632 MDIO_EEE_100TX | MDIO_EEE_1000T;
2633 adapter->flags |= IGB_FLAG_EEE;
2634 }
2635 }
2636 break;
2637 default:
2638 break;
ceb5f13b 2639 }
09b068d4 2640 }
749ab2cd 2641 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2642 return 0;
2643
2644err_register:
2645 igb_release_hw_control(adapter);
441fc6fd 2646 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2647err_eeprom:
2648 if (!igb_check_reset_block(hw))
f5f4cf08 2649 igb_reset_phy(hw);
9d5c8243
AK		 2650
2651 if (hw->flash_address)
2652 iounmap(hw->flash_address);
9d5c8243 2653err_sw_init:
42ad1a03 2654 kfree(adapter->shadow_vfta);
047e0030 2655 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2656#ifdef CONFIG_PCI_IOV
2657 igb_disable_sriov(pdev);
2658#endif
75009b3a 2659 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2660err_ioremap:
2661 free_netdev(netdev);
2662err_alloc_etherdev:
559e9c49 2663 pci_release_selected_regions(pdev,
b980ac18 2664 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2665err_pci_reg:
2666err_dma:
2667 pci_disable_device(pdev);
2668 return err;
2669}
2670
fa44f2f1 2671#ifdef CONFIG_PCI_IOV
781798a1 2672static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2673{
2674 struct net_device *netdev = pci_get_drvdata(pdev);
2675 struct igb_adapter *adapter = netdev_priv(netdev);
2676 struct e1000_hw *hw = &adapter->hw;
2677
2678 /* reclaim resources allocated to VFs */
2679 if (adapter->vf_data) {
2680 /* disable iov and allow time for transactions to clear */
b09186d2 2681 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2682 dev_warn(&pdev->dev,
2683 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2684 return -EPERM;
2685 } else {
2686 pci_disable_sriov(pdev);
2687 msleep(500);
2688 }
2689
2690 kfree(adapter->vf_data);
2691 adapter->vf_data = NULL;
2692 adapter->vfs_allocated_count = 0;
2693 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2694 wrfl();
2695 msleep(100);
2696 dev_info(&pdev->dev, "IOV Disabled\n");
2697
2698 /* Re-enable DMA Coalescing flag since IOV is turned off */
2699 adapter->flags |= IGB_FLAG_DMAC;
2700 }
2701
2702 return 0;
2703}
2704
2705static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2706{
2707 struct net_device *netdev = pci_get_drvdata(pdev);
2708 struct igb_adapter *adapter = netdev_priv(netdev);
2709 int old_vfs = pci_num_vf(pdev);
2710 int err = 0;
2711 int i;
2712
cd14ef54 2713 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2714 err = -EPERM;
2715 goto out;
2716 }
fa44f2f1
GR		 2717 if (!num_vfs)
2718 goto out;
fa44f2f1 2719
781798a1
SA		 2720 if (old_vfs) {
2721 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2722 old_vfs, max_vfs);
2723 adapter->vfs_allocated_count = old_vfs;
2724 } else
2725 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2726
2727 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2728 sizeof(struct vf_data_storage), GFP_KERNEL);
2729
2730 /* if allocation failed then we do not support SR-IOV */
2731 if (!adapter->vf_data) {
2732 adapter->vfs_allocated_count = 0;
2733 dev_err(&pdev->dev,
2734 "Unable to allocate memory for VF Data Storage\n");
2735 err = -ENOMEM;
2736 goto out;
2737 }
2738
781798a1
SA		 2739 /* only call pci_enable_sriov() if no VFs are allocated already */
2740 if (!old_vfs) {
2741 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2742 if (err)
2743 goto err_out;
2744 }
fa44f2f1
GR		 2745 dev_info(&pdev->dev, "%d VFs allocated\n",
2746 adapter->vfs_allocated_count);
2747 for (i = 0; i < adapter->vfs_allocated_count; i++)
2748 igb_vf_configure(adapter, i);
2749
2750 /* DMA Coalescing is not supported in IOV mode. */
2751 adapter->flags &= ~IGB_FLAG_DMAC;
2752 goto out;
2753
2754err_out:
2755 kfree(adapter->vf_data);
2756 adapter->vf_data = NULL;
2757 adapter->vfs_allocated_count = 0;
2758out:
2759 return err;
2760}
2761
2762#endif
b980ac18 2763/**
441fc6fd
CW		 2764 * igb_remove_i2c - Cleanup I2C interface
2765 * @adapter: pointer to adapter structure
b980ac18 2766 **/
441fc6fd
CW		 2767static void igb_remove_i2c(struct igb_adapter *adapter)
2768{
441fc6fd
CW		 2769 /* free the adapter bus structure */
2770 i2c_del_adapter(&adapter->i2c_adap);
2771}
2772
9d5c8243 2773/**
b980ac18
JK		 2774 * igb_remove - Device Removal Routine
2775 * @pdev: PCI device information struct
9d5c8243 2776 *
b980ac18
JK		 2777 * igb_remove is called by the PCI subsystem to alert the driver
2778 * that it should release a PCI device. The could be caused by a
2779 * Hot-Plug event, or because the driver is going to be removed from
2780 * memory.
9d5c8243 2781 **/
9f9a12f8 2782static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2783{
2784 struct net_device *netdev = pci_get_drvdata(pdev);
2785 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2786 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2787
749ab2cd 2788 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2789#ifdef CONFIG_IGB_HWMON
2790 igb_sysfs_exit(adapter);
2791#endif
441fc6fd 2792 igb_remove_i2c(adapter);
a79f4f88 2793 igb_ptp_stop(adapter);
b980ac18 2794 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2795 * disable watchdog from being rescheduled.
2796 */
9d5c8243
AK		 2797 set_bit(__IGB_DOWN, &adapter->state);
2798 del_timer_sync(&adapter->watchdog_timer);
2799 del_timer_sync(&adapter->phy_info_timer);
2800
760141a5
TH		 2801 cancel_work_sync(&adapter->reset_task);
2802 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2803
421e02f0 2804#ifdef CONFIG_IGB_DCA
7dfc16fa 2805 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2806 dev_info(&pdev->dev, "DCA disabled\n");
2807 dca_remove_requester(&pdev->dev);
7dfc16fa 2808 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2809 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2810 }
2811#endif
2812
9d5c8243 2813 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2814 * would have already happened in close and is redundant.
2815 */
9d5c8243
AK		 2816 igb_release_hw_control(adapter);
2817
37680117 2818#ifdef CONFIG_PCI_IOV
fa44f2f1 2819 igb_disable_sriov(pdev);
37680117 2820#endif
559e9c49 2821
c23d92b8
AW		 2822 unregister_netdev(netdev);
2823
2824 igb_clear_interrupt_scheme(adapter);
2825
75009b3a 2826 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2827 if (hw->flash_address)
2828 iounmap(hw->flash_address);
559e9c49 2829 pci_release_selected_regions(pdev,
b980ac18 2830 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2831
1128c756 2832 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2833 free_netdev(netdev);
2834
19d5afd4 2835 pci_disable_pcie_error_reporting(pdev);
40a914fa 2836
9d5c8243
AK		 2837 pci_disable_device(pdev);
2838}
2839
a6b623e0 2840/**
b980ac18
JK		 2841 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2842 * @adapter: board private structure to initialize
a6b623e0 2843 *
b980ac18
JK		 2844 * This function initializes the vf specific data storage and then attempts to
2845 * allocate the VFs. The reason for ordering it this way is because it is much
2846 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2847 * the memory for the VFs.
a6b623e0 2848 **/
9f9a12f8 2849static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2850{
2851#ifdef CONFIG_PCI_IOV
2852 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2853 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2854
f96a8a0b
CW		 2855 /* Virtualization features not supported on i210 family. */
2856 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2857 return;
2858
fa44f2f1 2859 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2860 igb_enable_sriov(pdev, max_vfs);
0224d663 2861
a6b623e0
AD		 2862#endif /* CONFIG_PCI_IOV */
2863}
2864
fa44f2f1 2865static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2866{
2867 struct e1000_hw *hw = &adapter->hw;
374a542d 2868 u32 max_rss_queues;
9d5c8243 2869
374a542d 2870 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2871 switch (hw->mac.type) {
374a542d
MV		 2872 case e1000_i211:
2873 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2874 break;
2875 case e1000_82575:
f96a8a0b 2876 case e1000_i210:
374a542d
MV		 2877 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2878 break;
2879 case e1000_i350:
2880 /* I350 cannot do RSS and SR-IOV at the same time */
2881 if (!!adapter->vfs_allocated_count) {
2882 max_rss_queues = 1;
2883 break;
2884 }
2885 /* fall through */
2886 case e1000_82576:
2887 if (!!adapter->vfs_allocated_count) {
2888 max_rss_queues = 2;
2889 break;
2890 }
2891 /* fall through */
2892 case e1000_82580:
ceb5f13b 2893 case e1000_i354:
374a542d
MV		 2894 default:
2895 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2896 break;
374a542d
MV		 2897 }
2898
2899 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2900
72ddef05
SS		 2901 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2902}
2903
2904void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2905 const u32 max_rss_queues)
2906{
2907 struct e1000_hw *hw = &adapter->hw;
2908
374a542d
MV		 2909 /* Determine if we need to pair queues. */
2910 switch (hw->mac.type) {
2911 case e1000_82575:
f96a8a0b 2912 case e1000_i211:
374a542d 2913 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2914 break;
374a542d 2915 case e1000_82576:
b980ac18 2916 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2917 * should pair the queues in order to conserve interrupts due
2918 * to limited supply.
2919 */
2920 if ((adapter->rss_queues > 1) &&
2921 (adapter->vfs_allocated_count > 6))
2922 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2923 /* fall through */
2924 case e1000_82580:
2925 case e1000_i350:
ceb5f13b 2926 case e1000_i354:
374a542d 2927 case e1000_i210:
f96a8a0b 2928 default:
b980ac18 2929 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2930 * order to conserve interrupts due to limited supply.
2931 */
2932 if (adapter->rss_queues > (max_rss_queues / 2))
2933 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2934 break;
2935 }
fa44f2f1
GR		 2936}
2937
2938/**
b980ac18
JK		 2939 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2940 * @adapter: board private structure to initialize
fa44f2f1 2941 *
b980ac18
JK		 2942 * igb_sw_init initializes the Adapter private data structure.
2943 * Fields are initialized based on PCI device information and
2944 * OS network device settings (MTU size).
fa44f2f1
GR		 2945 **/
2946static int igb_sw_init(struct igb_adapter *adapter)
2947{
2948 struct e1000_hw *hw = &adapter->hw;
2949 struct net_device *netdev = adapter->netdev;
2950 struct pci_dev *pdev = adapter->pdev;
2951
2952 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2953
2954 /* set default ring sizes */
2955 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2956 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2957
2958 /* set default ITR values */
2959 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2960 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2961
2962 /* set default work limits */
2963 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2964
2965 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2966 VLAN_HLEN;
2967 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2968
2969 spin_lock_init(&adapter->stats64_lock);
2970#ifdef CONFIG_PCI_IOV
2971 switch (hw->mac.type) {
2972 case e1000_82576:
2973 case e1000_i350:
2974 if (max_vfs > 7) {
2975 dev_warn(&pdev->dev,
2976 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2977 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2978 } else
2979 adapter->vfs_allocated_count = max_vfs;
2980 if (adapter->vfs_allocated_count)
2981 dev_warn(&pdev->dev,
2982 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2983 break;
2984 default:
2985 break;
2986 }
2987#endif /* CONFIG_PCI_IOV */
2988
cbfe360a
SA		 2989 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
2990 adapter->flags |= IGB_FLAG_HAS_MSIX;
2991
ceee3450
TF		 2992 igb_probe_vfs(adapter);
2993
fa44f2f1 2994 igb_init_queue_configuration(adapter);
a99955fc 2995
1128c756 2996 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2997 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2998 GFP_ATOMIC);
1128c756 2999
a6b623e0 3000 /* This call may decrease the number of queues */
53c7d064 3001 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3002 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3003 return -ENOMEM;
3004 }
3005
3006 /* Explicitly disable IRQ since the NIC can be in any state. */
3007 igb_irq_disable(adapter);
3008
f96a8a0b 3009 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3010 adapter->flags &= ~IGB_FLAG_DMAC;
3011
9d5c8243
AK		 3012 set_bit(__IGB_DOWN, &adapter->state);
3013 return 0;
3014}
3015
3016/**
b980ac18
JK		 3017 * igb_open - Called when a network interface is made active
3018 * @netdev: network interface device structure
9d5c8243 3019 *
b980ac18 3020 * Returns 0 on success, negative value on failure
9d5c8243 3021 *
b980ac18
JK		 3022 * The open entry point is called when a network interface is made
3023 * active by the system (IFF_UP). At this point all resources needed
3024 * for transmit and receive operations are allocated, the interrupt
3025 * handler is registered with the OS, the watchdog timer is started,
3026 * and the stack is notified that the interface is ready.
9d5c8243 3027 **/
749ab2cd 3028static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3029{
3030 struct igb_adapter *adapter = netdev_priv(netdev);
3031 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3032 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3033 int err;
3034 int i;
3035
3036 /* disallow open during test */
749ab2cd
YZ		 3037 if (test_bit(__IGB_TESTING, &adapter->state)) {
3038 WARN_ON(resuming);
9d5c8243 3039 return -EBUSY;
749ab2cd
YZ		 3040 }
3041
3042 if (!resuming)
3043 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3044
b168dfc5
JB		 3045 netif_carrier_off(netdev);
3046
9d5c8243
AK		 3047 /* allocate transmit descriptors */
3048 err = igb_setup_all_tx_resources(adapter);
3049 if (err)
3050 goto err_setup_tx;
3051
3052 /* allocate receive descriptors */
3053 err = igb_setup_all_rx_resources(adapter);
3054 if (err)
3055 goto err_setup_rx;
3056
88a268c1 3057 igb_power_up_link(adapter);
9d5c8243 3058
9d5c8243
AK		 3059 /* before we allocate an interrupt, we must be ready to handle it.
3060 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3061 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3062 * clean_rx handler before we do so.
3063 */
9d5c8243
AK		 3064 igb_configure(adapter);
3065
3066 err = igb_request_irq(adapter);
3067 if (err)
3068 goto err_req_irq;
3069
0c2cc02e
AD		 3070 /* Notify the stack of the actual queue counts. */
3071 err = netif_set_real_num_tx_queues(adapter->netdev,
3072 adapter->num_tx_queues);
3073 if (err)
3074 goto err_set_queues;
3075
3076 err = netif_set_real_num_rx_queues(adapter->netdev,
3077 adapter->num_rx_queues);
3078 if (err)
3079 goto err_set_queues;
3080
9d5c8243
AK		 3081 /* From here on the code is the same as igb_up() */
3082 clear_bit(__IGB_DOWN, &adapter->state);
3083
0d1ae7f4
AD		 3084 for (i = 0; i < adapter->num_q_vectors; i++)
3085 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3086
3087 /* Clear any pending interrupts. */
3088 rd32(E1000_ICR);
844290e5
PW		 3089
3090 igb_irq_enable(adapter);
3091
d4960307
AD		 3092 /* notify VFs that reset has been completed */
3093 if (adapter->vfs_allocated_count) {
3094 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3095
d4960307
AD		 3096 reg_data |= E1000_CTRL_EXT_PFRSTD;
3097 wr32(E1000_CTRL_EXT, reg_data);
3098 }
3099
d55b53ff
JK		 3100 netif_tx_start_all_queues(netdev);
3101
749ab2cd
YZ		 3102 if (!resuming)
3103 pm_runtime_put(&pdev->dev);
3104
25568a53
AD		 3105 /* start the watchdog. */
3106 hw->mac.get_link_status = 1;
3107 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3108
3109 return 0;
3110
0c2cc02e
AD		 3111err_set_queues:
3112 igb_free_irq(adapter);
9d5c8243
AK		 3113err_req_irq:
3114 igb_release_hw_control(adapter);
88a268c1 3115 igb_power_down_link(adapter);
9d5c8243
AK		 3116 igb_free_all_rx_resources(adapter);
3117err_setup_rx:
3118 igb_free_all_tx_resources(adapter);
3119err_setup_tx:
3120 igb_reset(adapter);
749ab2cd
YZ		 3121 if (!resuming)
3122 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3123
3124 return err;
3125}
3126
749ab2cd
YZ		 3127static int igb_open(struct net_device *netdev)
3128{
3129 return __igb_open(netdev, false);
3130}
3131
9d5c8243 3132/**
b980ac18
JK		 3133 * igb_close - Disables a network interface
3134 * @netdev: network interface device structure
9d5c8243 3135 *
b980ac18 3136 * Returns 0, this is not allowed to fail
9d5c8243 3137 *
b980ac18
JK		 3138 * The close entry point is called when an interface is de-activated
3139 * by the OS. The hardware is still under the driver's control, but
3140 * needs to be disabled. A global MAC reset is issued to stop the
3141 * hardware, and all transmit and receive resources are freed.
9d5c8243 3142 **/
749ab2cd 3143static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3144{
3145 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3146 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3147
3148 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3149
749ab2cd
YZ		 3150 if (!suspending)
3151 pm_runtime_get_sync(&pdev->dev);
3152
3153 igb_down(adapter);
9d5c8243
AK		 3154 igb_free_irq(adapter);
3155
3156 igb_free_all_tx_resources(adapter);
3157 igb_free_all_rx_resources(adapter);
3158
749ab2cd
YZ		 3159 if (!suspending)
3160 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3161 return 0;
3162}
3163
749ab2cd
YZ		 3164static int igb_close(struct net_device *netdev)
3165{
3166 return __igb_close(netdev, false);
3167}
3168
9d5c8243 3169/**
b980ac18
JK		 3170 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3171 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3172 *
b980ac18 3173 * Return 0 on success, negative on failure
9d5c8243 3174 **/
80785298 3175int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3176{
59d71989 3177 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3178 int size;
3179
06034649 3180 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3181
3182 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3183 if (!tx_ring->tx_buffer_info)
9d5c8243 3184 goto err;
9d5c8243
AK		 3185
3186 /* round up to nearest 4K */
85e8d004 3187 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3188 tx_ring->size = ALIGN(tx_ring->size, 4096);
3189
5536d210
AD		 3190 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3191 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3192 if (!tx_ring->desc)
3193 goto err;
3194
9d5c8243
AK		 3195 tx_ring->next_to_use = 0;
3196 tx_ring->next_to_clean = 0;
81c2fc22 3197
9d5c8243
AK		 3198 return 0;
3199
3200err:
06034649 3201 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3202 tx_ring->tx_buffer_info = NULL;
3203 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3204 return -ENOMEM;
3205}
3206
3207/**
b980ac18
JK		 3208 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3209 * (Descriptors) for all queues
3210 * @adapter: board private structure
9d5c8243 3211 *
b980ac18 3212 * Return 0 on success, negative on failure
9d5c8243
AK		 3213 **/
3214static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3215{
439705e1 3216 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3217 int i, err = 0;
3218
3219 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3220 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3221 if (err) {
439705e1 3222 dev_err(&pdev->dev,
9d5c8243
AK		 3223 "Allocation for Tx Queue %u failed\n", i);
3224 for (i--; i >= 0; i--)
3025a446 3225 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3226 break;
3227 }
3228 }
3229
3230 return err;
3231}
3232
3233/**
b980ac18
JK		 3234 * igb_setup_tctl - configure the transmit control registers
3235 * @adapter: Board private structure
9d5c8243 3236 **/
d7ee5b3a 3237void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3238{
9d5c8243
AK		 3239 struct e1000_hw *hw = &adapter->hw;
3240 u32 tctl;
9d5c8243 3241
85b430b4
AD		 3242 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3243 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3244
3245 /* Program the Transmit Control Register */
9d5c8243
AK		 3246 tctl = rd32(E1000_TCTL);
3247 tctl &= ~E1000_TCTL_CT;
3248 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3249 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3250
3251 igb_config_collision_dist(hw);
3252
9d5c8243
AK		 3253 /* Enable transmits */
3254 tctl |= E1000_TCTL_EN;
3255
3256 wr32(E1000_TCTL, tctl);
3257}
3258
85b430b4 3259/**
b980ac18
JK		 3260 * igb_configure_tx_ring - Configure transmit ring after Reset
3261 * @adapter: board private structure
3262 * @ring: tx ring to configure
85b430b4 3263 *
b980ac18 3264 * Configure a transmit ring after a reset.
85b430b4 3265 **/
d7ee5b3a 3266void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3267 struct igb_ring *ring)
85b430b4
AD		 3268{
3269 struct e1000_hw *hw = &adapter->hw;
a74420e0 3270 u32 txdctl = 0;
85b430b4
AD		 3271 u64 tdba = ring->dma;
3272 int reg_idx = ring->reg_idx;
3273
3274 /* disable the queue */
a74420e0 3275 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3276 wrfl();
3277 mdelay(10);
3278
3279 wr32(E1000_TDLEN(reg_idx),
b980ac18 3280 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3281 wr32(E1000_TDBAL(reg_idx),
b980ac18 3282 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3283 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3284
fce99e34 3285 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3286 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3287 writel(0, ring->tail);
85b430b4
AD		 3288
3289 txdctl |= IGB_TX_PTHRESH;
3290 txdctl |= IGB_TX_HTHRESH << 8;
3291 txdctl |= IGB_TX_WTHRESH << 16;
3292
3293 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3294 wr32(E1000_TXDCTL(reg_idx), txdctl);
3295}
3296
3297/**
b980ac18
JK		 3298 * igb_configure_tx - Configure transmit Unit after Reset
3299 * @adapter: board private structure
85b430b4 3300 *
b980ac18 3301 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3302 **/
3303static void igb_configure_tx(struct igb_adapter *adapter)
3304{
3305 int i;
3306
3307 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3308 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3309}
3310
9d5c8243 3311/**
b980ac18
JK		 3312 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3313 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3314 *
b980ac18 3315 * Returns 0 on success, negative on failure
9d5c8243 3316 **/
80785298 3317int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3318{
59d71989 3319 struct device *dev = rx_ring->dev;
f33005a6 3320 int size;
9d5c8243 3321
06034649 3322 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3323
3324 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3325 if (!rx_ring->rx_buffer_info)
9d5c8243 3326 goto err;
9d5c8243 3327
9d5c8243 3328 /* Round up to nearest 4K */
f33005a6 3329 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3330 rx_ring->size = ALIGN(rx_ring->size, 4096);
3331
5536d210
AD		 3332 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3333 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3334 if (!rx_ring->desc)
3335 goto err;
3336
cbc8e55f 3337 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3338 rx_ring->next_to_clean = 0;
3339 rx_ring->next_to_use = 0;
9d5c8243 3340
9d5c8243
AK		 3341 return 0;
3342
3343err:
06034649
AD		 3344 vfree(rx_ring->rx_buffer_info);
3345 rx_ring->rx_buffer_info = NULL;
f33005a6 3346 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3347 return -ENOMEM;
3348}
3349
3350/**
b980ac18
JK		 3351 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3352 * (Descriptors) for all queues
3353 * @adapter: board private structure
9d5c8243 3354 *
b980ac18 3355 * Return 0 on success, negative on failure
9d5c8243
AK		 3356 **/
3357static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3358{
439705e1 3359 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3360 int i, err = 0;
3361
3362 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3363 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3364 if (err) {
439705e1 3365 dev_err(&pdev->dev,
9d5c8243
AK		 3366 "Allocation for Rx Queue %u failed\n", i);
3367 for (i--; i >= 0; i--)
3025a446 3368 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3369 break;
3370 }
3371 }
3372
3373 return err;
3374}
3375
06cf2666 3376/**
b980ac18
JK		 3377 * igb_setup_mrqc - configure the multiple receive queue control registers
3378 * @adapter: Board private structure
06cf2666
AD		 3379 **/
3380static void igb_setup_mrqc(struct igb_adapter *adapter)
3381{
3382 struct e1000_hw *hw = &adapter->hw;
3383 u32 mrqc, rxcsum;
ed12cc9a 3384 u32 j, num_rx_queues;
eb31f849 3385 u32 rss_key[10];
06cf2666 3386
eb31f849 3387 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3388 for (j = 0; j < 10; j++)
eb31f849 3389 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3390
a99955fc 3391 num_rx_queues = adapter->rss_queues;
06cf2666 3392
797fd4be 3393 switch (hw->mac.type) {
797fd4be
AD		 3394 case e1000_82576:
3395 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3396 if (adapter->vfs_allocated_count)
06cf2666 3397 num_rx_queues = 2;
797fd4be
AD		 3398 break;
3399 default:
3400 break;
06cf2666
AD		 3401 }
3402
ed12cc9a
LMV		 3403 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3404 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3405 adapter->rss_indir_tbl[j] =
3406 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3407 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3408 }
ed12cc9a 3409 igb_write_rss_indir_tbl(adapter);
06cf2666 3410
b980ac18 3411 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3412 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3413 * offloads as they are enabled by default
3414 */
3415 rxcsum = rd32(E1000_RXCSUM);
3416 rxcsum |= E1000_RXCSUM_PCSD;
3417
3418 if (adapter->hw.mac.type >= e1000_82576)
3419 /* Enable Receive Checksum Offload for SCTP */
3420 rxcsum |= E1000_RXCSUM_CRCOFL;
3421
3422 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3423 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3424
039454a8
AA		 3425 /* Generate RSS hash based on packet types, TCP/UDP
3426 * port numbers and/or IPv4/v6 src and dst addresses
3427 */
f96a8a0b
CW		 3428 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3429 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3430 E1000_MRQC_RSS_FIELD_IPV6 |
3431 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3432 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3433
039454a8
AA		 3434 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3435 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3436 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3437 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3438
06cf2666
AD		 3439 /* If VMDq is enabled then we set the appropriate mode for that, else
3440 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3441 * if we are only using one queue
3442 */
06cf2666
AD		 3443 if (adapter->vfs_allocated_count) {
3444 if (hw->mac.type > e1000_82575) {
3445 /* Set the default pool for the PF's first queue */
3446 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3447
06cf2666
AD		 3448 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3449 E1000_VT_CTL_DISABLE_DEF_POOL);
3450 vtctl |= adapter->vfs_allocated_count <<
3451 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3452 wr32(E1000_VT_CTL, vtctl);
3453 }
a99955fc 3454 if (adapter->rss_queues > 1)
f96a8a0b 3455 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3456 else
f96a8a0b 3457 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3458 } else {
f96a8a0b
CW		 3459 if (hw->mac.type != e1000_i211)
3460 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3461 }
3462 igb_vmm_control(adapter);
3463
06cf2666
AD		 3464 wr32(E1000_MRQC, mrqc);
3465}
3466
9d5c8243 3467/**
b980ac18
JK		 3468 * igb_setup_rctl - configure the receive control registers
3469 * @adapter: Board private structure
9d5c8243 3470 **/
d7ee5b3a 3471void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3472{
3473 struct e1000_hw *hw = &adapter->hw;
3474 u32 rctl;
9d5c8243
AK		 3475
3476 rctl = rd32(E1000_RCTL);
3477
3478 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3479 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3480
69d728ba 3481 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3482 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3483
b980ac18 3484 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3485 * redirection as it did with e1000. Newer features require
3486 * that the HW strips the CRC.
73cd78f1 3487 */
87cb7e8c 3488 rctl |= E1000_RCTL_SECRC;
9d5c8243 3489
559e9c49 3490 /* disable store bad packets and clear size bits. */
ec54d7d6 3491 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3492
6ec43fe6
AD		 3493 /* enable LPE to prevent packets larger than max_frame_size */
3494 rctl |= E1000_RCTL_LPE;
9d5c8243 3495
952f72a8
AD		 3496 /* disable queue 0 to prevent tail write w/o re-config */
3497 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3498
e1739522
AD		 3499 /* Attention!!! For SR-IOV PF driver operations you must enable
3500 * queue drop for all VF and PF queues to prevent head of line blocking
3501 * if an un-trusted VF does not provide descriptors to hardware.
3502 */
3503 if (adapter->vfs_allocated_count) {
e1739522
AD		 3504 /* set all queue drop enable bits */
3505 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3506 }
3507
89eaefb6
BG		 3508 /* This is useful for sniffing bad packets. */
3509 if (adapter->netdev->features & NETIF_F_RXALL) {
3510 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3511 * in e1000e_set_rx_mode
3512 */
89eaefb6
BG		 3513 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3514 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3515 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3516
3517 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3518 E1000_RCTL_DPF | /* Allow filtered pause */
3519 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3520 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3521 * and that breaks VLANs.
3522 */
3523 }
3524
9d5c8243
AK		 3525 wr32(E1000_RCTL, rctl);
3526}
3527
7d5753f0 3528static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3529 int vfn)
7d5753f0
AD		 3530{
3531 struct e1000_hw *hw = &adapter->hw;
3532 u32 vmolr;
3533
3534 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3535 * increase the size to support vlan tags
3536 */
7d5753f0
AD		 3537 if (vfn < adapter->vfs_allocated_count &&
3538 adapter->vf_data[vfn].vlans_enabled)
3539 size += VLAN_TAG_SIZE;
3540
3541 vmolr = rd32(E1000_VMOLR(vfn));
3542 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3543 vmolr |= size | E1000_VMOLR_LPE;
3544 wr32(E1000_VMOLR(vfn), vmolr);
3545
3546 return 0;
3547}
3548
e1739522 3549/**
b980ac18
JK		 3550 * igb_rlpml_set - set maximum receive packet size
3551 * @adapter: board private structure
e1739522 3552 *
b980ac18 3553 * Configure maximum receivable packet size.
e1739522
AD		 3554 **/
3555static void igb_rlpml_set(struct igb_adapter *adapter)
3556{
153285f9 3557 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3558 struct e1000_hw *hw = &adapter->hw;
3559 u16 pf_id = adapter->vfs_allocated_count;
3560
e1739522
AD		 3561 if (pf_id) {
3562 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3563 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3564 * to our max jumbo frame size, in case we need to enable
3565 * jumbo frames on one of the rings later.
3566 * This will not pass over-length frames into the default
3567 * queue because it's gated by the VMOLR.RLPML.
3568 */
7d5753f0 3569 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3570 }
3571
3572 wr32(E1000_RLPML, max_frame_size);
3573}
3574
8151d294
WM		 3575static inline void igb_set_vmolr(struct igb_adapter *adapter,
3576 int vfn, bool aupe)
7d5753f0
AD		 3577{
3578 struct e1000_hw *hw = &adapter->hw;
3579 u32 vmolr;
3580
b980ac18 3581 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3582 * we should exit and do nothing
3583 */
3584 if (hw->mac.type < e1000_82576)
3585 return;
3586
3587 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3588 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3589 if (hw->mac.type == e1000_i350) {
3590 u32 dvmolr;
3591
3592 dvmolr = rd32(E1000_DVMOLR(vfn));
3593 dvmolr |= E1000_DVMOLR_STRVLAN;
3594 wr32(E1000_DVMOLR(vfn), dvmolr);
3595 }
8151d294 3596 if (aupe)
b980ac18 3597 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3598 else
3599 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3600
3601 /* clear all bits that might not be set */
3602 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3603
a99955fc 3604 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3605 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3606 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3607 * multicast packets
3608 */
3609 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3610 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3611
3612 wr32(E1000_VMOLR(vfn), vmolr);
3613}
3614
85b430b4 3615/**
b980ac18
JK		 3616 * igb_configure_rx_ring - Configure a receive ring after Reset
3617 * @adapter: board private structure
3618 * @ring: receive ring to be configured
85b430b4 3619 *
b980ac18 3620 * Configure the Rx unit of the MAC after a reset.
85b430b4 3621 **/
d7ee5b3a 3622void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3623 struct igb_ring *ring)
85b430b4
AD		 3624{
3625 struct e1000_hw *hw = &adapter->hw;
3626 u64 rdba = ring->dma;
3627 int reg_idx = ring->reg_idx;
a74420e0 3628 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3629
3630 /* disable the queue */
a74420e0 3631 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3632
3633 /* Set DMA base address registers */
3634 wr32(E1000_RDBAL(reg_idx),
3635 rdba & 0x00000000ffffffffULL);
3636 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3637 wr32(E1000_RDLEN(reg_idx),
b980ac18 3638 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3639
3640 /* initialize head and tail */
fce99e34 3641 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3642 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3643 writel(0, ring->tail);
85b430b4 3644
952f72a8 3645 /* set descriptor configuration */
44390ca6 3646 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3647 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3648 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3649 if (hw->mac.type >= e1000_82580)
757b77e2 3650 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3651 /* Only set Drop Enable if we are supporting multiple queues */
3652 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3653 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3654
3655 wr32(E1000_SRRCTL(reg_idx), srrctl);
3656
7d5753f0 3657 /* set filtering for VMDQ pools */
8151d294 3658 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3659
85b430b4
AD		 3660 rxdctl |= IGB_RX_PTHRESH;
3661 rxdctl |= IGB_RX_HTHRESH << 8;
3662 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3663
3664 /* enable receive descriptor fetching */
3665 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3666 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3667}
3668
9d5c8243 3669/**
b980ac18
JK		 3670 * igb_configure_rx - Configure receive Unit after Reset
3671 * @adapter: board private structure
9d5c8243 3672 *
b980ac18 3673 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3674 **/
3675static void igb_configure_rx(struct igb_adapter *adapter)
3676{
9107584e 3677 int i;
9d5c8243 3678
68d480c4
AD		 3679 /* set UTA to appropriate mode */
3680 igb_set_uta(adapter);
3681
26ad9178
AD		 3682 /* set the correct pool for the PF default MAC address in entry 0 */
3683 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3684 adapter->vfs_allocated_count);
26ad9178 3685
06cf2666 3686 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3687 * the Base and Length of the Rx Descriptor Ring
3688 */
f9d40f6a
AD		 3689 for (i = 0; i < adapter->num_rx_queues; i++)
3690 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3691}
3692
3693/**
b980ac18
JK		 3694 * igb_free_tx_resources - Free Tx Resources per Queue
3695 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3696 *
b980ac18 3697 * Free all transmit software resources
9d5c8243 3698 **/
68fd9910 3699void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3700{
3b644cf6 3701 igb_clean_tx_ring(tx_ring);
9d5c8243 3702
06034649
AD		 3703 vfree(tx_ring->tx_buffer_info);
3704 tx_ring->tx_buffer_info = NULL;
9d5c8243 3705
439705e1
AD		 3706 /* if not set, then don't free */
3707 if (!tx_ring->desc)
3708 return;
3709
59d71989
AD		 3710 dma_free_coherent(tx_ring->dev, tx_ring->size,
3711 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3712
3713 tx_ring->desc = NULL;
3714}
3715
3716/**
b980ac18
JK		 3717 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3718 * @adapter: board private structure
9d5c8243 3719 *
b980ac18 3720 * Free all transmit software resources
9d5c8243
AK		 3721 **/
3722static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3723{
3724 int i;
3725
3726 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3727 if (adapter->tx_ring[i])
3728 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3729}
3730
ebe42d16
AD		 3731void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3732 struct igb_tx_buffer *tx_buffer)
3733{
3734 if (tx_buffer->skb) {
3735 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3736 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3737 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3738 dma_unmap_addr(tx_buffer, dma),
3739 dma_unmap_len(tx_buffer, len),
ebe42d16 3740 DMA_TO_DEVICE);
c9f14bf3 3741 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3742 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3743 dma_unmap_addr(tx_buffer, dma),
3744 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3745 DMA_TO_DEVICE);
3746 }
3747 tx_buffer->next_to_watch = NULL;
3748 tx_buffer->skb = NULL;
c9f14bf3 3749 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3750 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3751}
3752
3753/**
b980ac18
JK		 3754 * igb_clean_tx_ring - Free Tx Buffers
3755 * @tx_ring: ring to be cleaned
9d5c8243 3756 **/
3b644cf6 3757static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3758{
06034649 3759 struct igb_tx_buffer *buffer_info;
9d5c8243 3760 unsigned long size;
6ad4edfc 3761 u16 i;
9d5c8243 3762
06034649 3763 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3764 return;
3765 /* Free all the Tx ring sk_buffs */
3766
3767 for (i = 0; i < tx_ring->count; i++) {
06034649 3768 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3769 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3770 }
3771
dad8a3b3
JF		 3772 netdev_tx_reset_queue(txring_txq(tx_ring));
3773
06034649
AD		 3774 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3775 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3776
3777 /* Zero out the descriptor ring */
9d5c8243
AK		 3778 memset(tx_ring->desc, 0, tx_ring->size);
3779
3780 tx_ring->next_to_use = 0;
3781 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3782}
3783
3784/**
b980ac18
JK		 3785 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3786 * @adapter: board private structure
9d5c8243
AK		 3787 **/
3788static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3789{
3790 int i;
3791
3792 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3793 if (adapter->tx_ring[i])
3794 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3795}
3796
3797/**
b980ac18
JK		 3798 * igb_free_rx_resources - Free Rx Resources
3799 * @rx_ring: ring to clean the resources from
9d5c8243 3800 *
b980ac18 3801 * Free all receive software resources
9d5c8243 3802 **/
68fd9910 3803void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3804{
3b644cf6 3805 igb_clean_rx_ring(rx_ring);
9d5c8243 3806
06034649
AD		 3807 vfree(rx_ring->rx_buffer_info);
3808 rx_ring->rx_buffer_info = NULL;
9d5c8243 3809
439705e1
AD		 3810 /* if not set, then don't free */
3811 if (!rx_ring->desc)
3812 return;
3813
59d71989
AD		 3814 dma_free_coherent(rx_ring->dev, rx_ring->size,
3815 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3816
3817 rx_ring->desc = NULL;
3818}
3819
3820/**
b980ac18
JK		 3821 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3822 * @adapter: board private structure
9d5c8243 3823 *
b980ac18 3824 * Free all receive software resources
9d5c8243
AK		 3825 **/
3826static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3827{
3828 int i;
3829
3830 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3831 if (adapter->rx_ring[i])
3832 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3833}
3834
3835/**
b980ac18
JK		 3836 * igb_clean_rx_ring - Free Rx Buffers per Queue
3837 * @rx_ring: ring to free buffers from
9d5c8243 3838 **/
3b644cf6 3839static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3840{
9d5c8243 3841 unsigned long size;
c023cd88 3842 u16 i;
9d5c8243 3843
1a1c225b
AD		 3844 if (rx_ring->skb)
3845 dev_kfree_skb(rx_ring->skb);
3846 rx_ring->skb = NULL;
3847
06034649 3848 if (!rx_ring->rx_buffer_info)
9d5c8243 3849 return;
439705e1 3850
9d5c8243
AK		 3851 /* Free all the Rx ring sk_buffs */
3852 for (i = 0; i < rx_ring->count; i++) {
06034649 3853 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3854
cbc8e55f
AD		 3855 if (!buffer_info->page)
3856 continue;
3857
3858 dma_unmap_page(rx_ring->dev,
3859 buffer_info->dma,
3860 PAGE_SIZE,
3861 DMA_FROM_DEVICE);
3862 __free_page(buffer_info->page);
3863
1a1c225b 3864 buffer_info->page = NULL;
9d5c8243
AK		 3865 }
3866
06034649
AD		 3867 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3868 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3869
3870 /* Zero out the descriptor ring */
3871 memset(rx_ring->desc, 0, rx_ring->size);
3872
cbc8e55f 3873 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3874 rx_ring->next_to_clean = 0;
3875 rx_ring->next_to_use = 0;
9d5c8243
AK		 3876}
3877
3878/**
b980ac18
JK		 3879 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3880 * @adapter: board private structure
9d5c8243
AK		 3881 **/
3882static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3883{
3884 int i;
3885
3886 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3887 if (adapter->rx_ring[i])
3888 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3889}
3890
3891/**
b980ac18
JK		 3892 * igb_set_mac - Change the Ethernet Address of the NIC
3893 * @netdev: network interface device structure
3894 * @p: pointer to an address structure
9d5c8243 3895 *
b980ac18 3896 * Returns 0 on success, negative on failure
9d5c8243
AK		 3897 **/
3898static int igb_set_mac(struct net_device *netdev, void *p)
3899{
3900 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3901 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3902 struct sockaddr *addr = p;
3903
3904 if (!is_valid_ether_addr(addr->sa_data))
3905 return -EADDRNOTAVAIL;
3906
3907 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3908 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3909
26ad9178
AD		 3910 /* set the correct pool for the new PF MAC address in entry 0 */
3911 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3912 adapter->vfs_allocated_count);
e1739522 3913
9d5c8243
AK		 3914 return 0;
3915}
3916
3917/**
b980ac18
JK		 3918 * igb_write_mc_addr_list - write multicast addresses to MTA
3919 * @netdev: network interface device structure
9d5c8243 3920 *
b980ac18
JK		 3921 * Writes multicast address list to the MTA hash table.
3922 * Returns: -ENOMEM on failure
3923 * 0 on no addresses written
3924 * X on writing X addresses to MTA
9d5c8243 3925 **/
68d480c4 3926static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3927{
3928 struct igb_adapter *adapter = netdev_priv(netdev);
3929 struct e1000_hw *hw = &adapter->hw;
22bedad3 3930 struct netdev_hw_addr *ha;
68d480c4 3931 u8 *mta_list;
9d5c8243
AK		 3932 int i;
3933
4cd24eaf 3934 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3935 /* nothing to program, so clear mc list */
3936 igb_update_mc_addr_list(hw, NULL, 0);
3937 igb_restore_vf_multicasts(adapter);
3938 return 0;
3939 }
9d5c8243 3940
4cd24eaf 3941 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3942 if (!mta_list)
3943 return -ENOMEM;
ff41f8dc 3944
68d480c4 3945 /* The shared function expects a packed array of only addresses. */
48e2f183 3946 i = 0;
22bedad3
JP		 3947 netdev_for_each_mc_addr(ha, netdev)
3948 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3949
68d480c4
AD		 3950 igb_update_mc_addr_list(hw, mta_list, i);
3951 kfree(mta_list);
3952
4cd24eaf 3953 return netdev_mc_count(netdev);
68d480c4
AD		 3954}
3955
3956/**
b980ac18
JK		 3957 * igb_write_uc_addr_list - write unicast addresses to RAR table
3958 * @netdev: network interface device structure
68d480c4 3959 *
b980ac18
JK		 3960 * Writes unicast address list to the RAR table.
3961 * Returns: -ENOMEM on failure/insufficient address space
3962 * 0 on no addresses written
3963 * X on writing X addresses to the RAR table
68d480c4
AD		 3964 **/
3965static int igb_write_uc_addr_list(struct net_device *netdev)
3966{
3967 struct igb_adapter *adapter = netdev_priv(netdev);
3968 struct e1000_hw *hw = &adapter->hw;
3969 unsigned int vfn = adapter->vfs_allocated_count;
3970 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3971 int count = 0;
3972
3973 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3974 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3975 return -ENOMEM;
9d5c8243 3976
32e7bfc4 3977 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3978 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3979
3980 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3981 if (!rar_entries)
3982 break;
26ad9178 3983 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3984 rar_entries--,
3985 vfn);
68d480c4 3986 count++;
ff41f8dc
AD		 3987 }
3988 }
3989 /* write the addresses in reverse order to avoid write combining */
3990 for (; rar_entries > 0 ; rar_entries--) {
3991 wr32(E1000_RAH(rar_entries), 0);
3992 wr32(E1000_RAL(rar_entries), 0);
3993 }
3994 wrfl();
3995
68d480c4
AD		 3996 return count;
3997}
3998
3999/**
b980ac18
JK		 4000 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4001 * @netdev: network interface device structure
68d480c4 4002 *
b980ac18
JK		 4003 * The set_rx_mode entry point is called whenever the unicast or multicast
4004 * address lists or the network interface flags are updated. This routine is
4005 * responsible for configuring the hardware for proper unicast, multicast,
4006 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4007 **/
4008static void igb_set_rx_mode(struct net_device *netdev)
4009{
4010 struct igb_adapter *adapter = netdev_priv(netdev);
4011 struct e1000_hw *hw = &adapter->hw;
4012 unsigned int vfn = adapter->vfs_allocated_count;
4013 u32 rctl, vmolr = 0;
4014 int count;
4015
4016 /* Check for Promiscuous and All Multicast modes */
4017 rctl = rd32(E1000_RCTL);
4018
4019 /* clear the effected bits */
4020 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4021
4022 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4023 /* retain VLAN HW filtering if in VT mode */
7e44892c 4024 if (adapter->vfs_allocated_count)
6f3dc319 4025 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4026 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4027 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4028 } else {
4029 if (netdev->flags & IFF_ALLMULTI) {
4030 rctl |= E1000_RCTL_MPE;
4031 vmolr |= E1000_VMOLR_MPME;
4032 } else {
b980ac18 4033 /* Write addresses to the MTA, if the attempt fails
25985edc 4034 * then we should just turn on promiscuous mode so
68d480c4
AD		 4035 * that we can at least receive multicast traffic
4036 */
4037 count = igb_write_mc_addr_list(netdev);
4038 if (count < 0) {
4039 rctl |= E1000_RCTL_MPE;
4040 vmolr |= E1000_VMOLR_MPME;
4041 } else if (count) {
4042 vmolr |= E1000_VMOLR_ROMPE;
4043 }
4044 }
b980ac18 4045 /* Write addresses to available RAR registers, if there is not
68d480c4 4046 * sufficient space to store all the addresses then enable
25985edc 4047 * unicast promiscuous mode
68d480c4
AD		 4048 */
4049 count = igb_write_uc_addr_list(netdev);
4050 if (count < 0) {
4051 rctl |= E1000_RCTL_UPE;
4052 vmolr |= E1000_VMOLR_ROPE;
4053 }
4054 rctl |= E1000_RCTL_VFE;
28fc06f5 4055 }
68d480c4 4056 wr32(E1000_RCTL, rctl);
28fc06f5 4057
b980ac18 4058 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4059 * the VMOLR to enable the appropriate modes. Without this workaround
4060 * we will have issues with VLAN tag stripping not being done for frames
4061 * that are only arriving because we are the default pool
4062 */
f96a8a0b 4063 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4064 return;
9d5c8243 4065
68d480c4 4066 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4067 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4068 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4069 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4070}
4071
13800469
GR		 4072static void igb_check_wvbr(struct igb_adapter *adapter)
4073{
4074 struct e1000_hw *hw = &adapter->hw;
4075 u32 wvbr = 0;
4076
4077 switch (hw->mac.type) {
4078 case e1000_82576:
4079 case e1000_i350:
81ad807b
CW		 4080 wvbr = rd32(E1000_WVBR);
4081 if (!wvbr)
13800469
GR		 4082 return;
4083 break;
4084 default:
4085 break;
4086 }
4087
4088 adapter->wvbr |= wvbr;
4089}
4090
4091#define IGB_STAGGERED_QUEUE_OFFSET 8
4092
4093static void igb_spoof_check(struct igb_adapter *adapter)
4094{
4095 int j;
4096
4097 if (!adapter->wvbr)
4098 return;
4099
9005df38 4100 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4101 if (adapter->wvbr & (1 << j) ||
4102 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4103 dev_warn(&adapter->pdev->dev,
4104 "Spoof event(s) detected on VF %d\n", j);
4105 adapter->wvbr &=
4106 ~((1 << j) |
4107 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4108 }
4109 }
4110}
4111
9d5c8243 4112/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4113 * the phy
4114 */
9d5c8243
AK		 4115static void igb_update_phy_info(unsigned long data)
4116{
4117 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4118 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4119}
4120
4d6b725e 4121/**
b980ac18
JK		 4122 * igb_has_link - check shared code for link and determine up/down
4123 * @adapter: pointer to driver private info
4d6b725e 4124 **/
3145535a 4125bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4126{
4127 struct e1000_hw *hw = &adapter->hw;
4128 bool link_active = false;
4d6b725e
AD		 4129
4130 /* get_link_status is set on LSC (link status) interrupt or
4131 * rx sequence error interrupt. get_link_status will stay
4132 * false until the e1000_check_for_link establishes link
4133 * for copper adapters ONLY
4134 */
4135 switch (hw->phy.media_type) {
4136 case e1000_media_type_copper:
e5c3370f
AA		 4137 if (!hw->mac.get_link_status)
4138 return true;
4d6b725e 4139 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4140 hw->mac.ops.check_for_link(hw);
4141 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4142 break;
4143 default:
4144 case e1000_media_type_unknown:
4145 break;
4146 }
4147
aa9b8cc4
AA		 4148 if (((hw->mac.type == e1000_i210) ||
4149 (hw->mac.type == e1000_i211)) &&
4150 (hw->phy.id == I210_I_PHY_ID)) {
4151 if (!netif_carrier_ok(adapter->netdev)) {
4152 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4153 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4154 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4155 adapter->link_check_timeout = jiffies;
4156 }
4157 }
4158
4d6b725e
AD		 4159 return link_active;
4160}
4161
563988dc
SA		 4162static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4163{
4164 bool ret = false;
4165 u32 ctrl_ext, thstat;
4166
f96a8a0b 4167 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4168 if (hw->mac.type == e1000_i350) {
4169 thstat = rd32(E1000_THSTAT);
4170 ctrl_ext = rd32(E1000_CTRL_EXT);
4171
4172 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4173 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4174 ret = !!(thstat & event);
563988dc
SA		 4175 }
4176
4177 return ret;
4178}
4179
1516f0a6
CW		 4180/**
4181 * igb_check_lvmmc - check for malformed packets received
4182 * and indicated in LVMMC register
4183 * @adapter: pointer to adapter
4184 **/
4185static void igb_check_lvmmc(struct igb_adapter *adapter)
4186{
4187 struct e1000_hw *hw = &adapter->hw;
4188 u32 lvmmc;
4189
4190 lvmmc = rd32(E1000_LVMMC);
4191 if (lvmmc) {
4192 if (unlikely(net_ratelimit())) {
4193 netdev_warn(adapter->netdev,
4194 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4195 lvmmc);
4196 }
4197 }
4198}
4199
9d5c8243 4200/**
b980ac18
JK		 4201 * igb_watchdog - Timer Call-back
4202 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4203 **/
4204static void igb_watchdog(unsigned long data)
4205{
4206 struct igb_adapter *adapter = (struct igb_adapter *)data;
4207 /* Do the rest outside of interrupt context */
4208 schedule_work(&adapter->watchdog_task);
4209}
4210
4211static void igb_watchdog_task(struct work_struct *work)
4212{
4213 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4214 struct igb_adapter,
4215 watchdog_task);
9d5c8243 4216 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4217 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4218 struct net_device *netdev = adapter->netdev;
563988dc 4219 u32 link;
7a6ea550 4220 int i;
56cec249 4221 u32 connsw;
9d5c8243 4222
4d6b725e 4223 link = igb_has_link(adapter);
aa9b8cc4
AA		 4224
4225 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4226 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4227 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4228 else
4229 link = false;
4230 }
4231
56cec249
CW		 4232 /* Force link down if we have fiber to swap to */
4233 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4234 if (hw->phy.media_type == e1000_media_type_copper) {
4235 connsw = rd32(E1000_CONNSW);
4236 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4237 link = 0;
4238 }
4239 }
9d5c8243 4240 if (link) {
2bdfc4e2
CW		 4241 /* Perform a reset if the media type changed. */
4242 if (hw->dev_spec._82575.media_changed) {
4243 hw->dev_spec._82575.media_changed = false;
4244 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4245 igb_reset(adapter);
4246 }
749ab2cd
YZ		 4247 /* Cancel scheduled suspend requests. */
4248 pm_runtime_resume(netdev->dev.parent);
4249
9d5c8243
AK		 4250 if (!netif_carrier_ok(netdev)) {
4251 u32 ctrl;
9005df38 4252
330a6d6a 4253 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4254 &adapter->link_speed,
4255 &adapter->link_duplex);
9d5c8243
AK		 4256
4257 ctrl = rd32(E1000_CTRL);
527d47c1 4258 /* Links status message must follow this format */
c75c4edf
CW		 4259 netdev_info(netdev,
4260 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4261 netdev->name,
4262 adapter->link_speed,
4263 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4264 "Full" : "Half",
4265 (ctrl & E1000_CTRL_TFCE) &&
4266 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4267 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4268 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4269
f4c01e96
CW		 4270 /* disable EEE if enabled */
4271 if ((adapter->flags & IGB_FLAG_EEE) &&
4272 (adapter->link_duplex == HALF_DUPLEX)) {
4273 dev_info(&adapter->pdev->dev,
4274 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4275 adapter->hw.dev_spec._82575.eee_disable = true;
4276 adapter->flags &= ~IGB_FLAG_EEE;
4277 }
4278
c0ba4778
KS		 4279 /* check if SmartSpeed worked */
4280 igb_check_downshift(hw);
4281 if (phy->speed_downgraded)
4282 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4283
563988dc 4284 /* check for thermal sensor event */
876d2d6f 4285 if (igb_thermal_sensor_event(hw,
d34a15ab 4286 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4287 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4288
d07f3e37 4289 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4290 adapter->tx_timeout_factor = 1;
4291 switch (adapter->link_speed) {
4292 case SPEED_10:
9d5c8243
AK		 4293 adapter->tx_timeout_factor = 14;
4294 break;
4295 case SPEED_100:
9d5c8243
AK		 4296 /* maybe add some timeout factor ? */
4297 break;
4298 }
4299
4300 netif_carrier_on(netdev);
9d5c8243 4301
4ae196df 4302 igb_ping_all_vfs(adapter);
17dc566c 4303 igb_check_vf_rate_limit(adapter);
4ae196df 4304
4b1a9877 4305 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4306 if (!test_bit(__IGB_DOWN, &adapter->state))
4307 mod_timer(&adapter->phy_info_timer,
4308 round_jiffies(jiffies + 2 * HZ));
4309 }
4310 } else {
4311 if (netif_carrier_ok(netdev)) {
4312 adapter->link_speed = 0;
4313 adapter->link_duplex = 0;
563988dc
SA		 4314
4315 /* check for thermal sensor event */
876d2d6f
JK		 4316 if (igb_thermal_sensor_event(hw,
4317 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4318 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4319 }
563988dc 4320
527d47c1 4321 /* Links status message must follow this format */
c75c4edf 4322 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4323 netdev->name);
9d5c8243 4324 netif_carrier_off(netdev);
4b1a9877 4325
4ae196df
AD		 4326 igb_ping_all_vfs(adapter);
4327
4b1a9877 4328 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4329 if (!test_bit(__IGB_DOWN, &adapter->state))
4330 mod_timer(&adapter->phy_info_timer,
4331 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4332
56cec249
CW		 4333 /* link is down, time to check for alternate media */
4334 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4335 igb_check_swap_media(adapter);
4336 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4337 schedule_work(&adapter->reset_task);
4338 /* return immediately */
4339 return;
4340 }
4341 }
749ab2cd
YZ		 4342 pm_schedule_suspend(netdev->dev.parent,
4343 MSEC_PER_SEC * 5);
56cec249
CW		 4344
4345 /* also check for alternate media here */
4346 } else if (!netif_carrier_ok(netdev) &&
4347 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4348 igb_check_swap_media(adapter);
4349 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4350 schedule_work(&adapter->reset_task);
4351 /* return immediately */
4352 return;
4353 }
9d5c8243
AK		 4354 }
4355 }
4356
12dcd86b
ED		 4357 spin_lock(&adapter->stats64_lock);
4358 igb_update_stats(adapter, &adapter->stats64);
4359 spin_unlock(&adapter->stats64_lock);
9d5c8243 4360
dbabb065 4361 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4362 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4363 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4364 /* We've lost link, so the controller stops DMA,
4365 * but we've got queued Tx work that's never going
4366 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4367 * (Do the reset outside of interrupt context).
4368 */
dbabb065
AD		 4369 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4370 adapter->tx_timeout_count++;
4371 schedule_work(&adapter->reset_task);
4372 /* return immediately since reset is imminent */
4373 return;
4374 }
9d5c8243 4375 }
9d5c8243 4376
dbabb065 4377 /* Force detection of hung controller every watchdog period */
6d095fa8 4378 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4379 }
f7ba205e 4380
b980ac18 4381 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4382 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4383 u32 eics = 0;
9005df38 4384
0d1ae7f4
AD		 4385 for (i = 0; i < adapter->num_q_vectors; i++)
4386 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4387 wr32(E1000_EICS, eics);
4388 } else {
4389 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4390 }
9d5c8243 4391
13800469 4392 igb_spoof_check(adapter);
fc580751 4393 igb_ptp_rx_hang(adapter);
13800469 4394
1516f0a6
CW		 4395 /* Check LVMMC register on i350/i354 only */
4396 if ((adapter->hw.mac.type == e1000_i350) ||
4397 (adapter->hw.mac.type == e1000_i354))
4398 igb_check_lvmmc(adapter);
4399
9d5c8243 4400 /* Reset the timer */
aa9b8cc4
AA		 4401 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4402 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4403 mod_timer(&adapter->watchdog_timer,
4404 round_jiffies(jiffies + HZ));
4405 else
4406 mod_timer(&adapter->watchdog_timer,
4407 round_jiffies(jiffies + 2 * HZ));
4408 }
9d5c8243
AK		 4409}
4410
4411enum latency_range {
4412 lowest_latency = 0,
4413 low_latency = 1,
4414 bulk_latency = 2,
4415 latency_invalid = 255
4416};
4417
6eb5a7f1 4418/**
b980ac18
JK		 4419 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4420 * @q_vector: pointer to q_vector
6eb5a7f1 4421 *
b980ac18
JK		 4422 * Stores a new ITR value based on strictly on packet size. This
4423 * algorithm is less sophisticated than that used in igb_update_itr,
4424 * due to the difficulty of synchronizing statistics across multiple
4425 * receive rings. The divisors and thresholds used by this function
4426 * were determined based on theoretical maximum wire speed and testing
4427 * data, in order to minimize response time while increasing bulk
4428 * throughput.
406d4965 4429 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4430 * NOTE: This function is called only when operating in a multiqueue
4431 * receive environment.
6eb5a7f1 4432 **/
047e0030 4433static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4434{
047e0030 4435 int new_val = q_vector->itr_val;
6eb5a7f1 4436 int avg_wire_size = 0;
047e0030 4437 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4438 unsigned int packets;
9d5c8243 4439
6eb5a7f1
AD		 4440 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4441 * ints/sec - ITR timer value of 120 ticks.
4442 */
4443 if (adapter->link_speed != SPEED_1000) {
0ba82994 4444 new_val = IGB_4K_ITR;
6eb5a7f1 4445 goto set_itr_val;
9d5c8243 4446 }
047e0030 4447
0ba82994
AD		 4448 packets = q_vector->rx.total_packets;
4449 if (packets)
4450 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4451
0ba82994
AD		 4452 packets = q_vector->tx.total_packets;
4453 if (packets)
4454 avg_wire_size = max_t(u32, avg_wire_size,
4455 q_vector->tx.total_bytes / packets);
047e0030
AD		 4456
4457 /* if avg_wire_size isn't set no work was done */
4458 if (!avg_wire_size)
4459 goto clear_counts;
9d5c8243 4460
6eb5a7f1
AD		 4461 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4462 avg_wire_size += 24;
4463
4464 /* Don't starve jumbo frames */
4465 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4466
6eb5a7f1
AD		 4467 /* Give a little boost to mid-size frames */
4468 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4469 new_val = avg_wire_size / 3;
4470 else
4471 new_val = avg_wire_size / 2;
9d5c8243 4472
0ba82994
AD		 4473 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4474 if (new_val < IGB_20K_ITR &&
4475 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4476 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4477 new_val = IGB_20K_ITR;
abe1c363 4478
6eb5a7f1 4479set_itr_val:
047e0030
AD		 4480 if (new_val != q_vector->itr_val) {
4481 q_vector->itr_val = new_val;
4482 q_vector->set_itr = 1;
9d5c8243 4483 }
6eb5a7f1 4484clear_counts:
0ba82994
AD		 4485 q_vector->rx.total_bytes = 0;
4486 q_vector->rx.total_packets = 0;
4487 q_vector->tx.total_bytes = 0;
4488 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4489}
4490
4491/**
b980ac18
JK		 4492 * igb_update_itr - update the dynamic ITR value based on statistics
4493 * @q_vector: pointer to q_vector
4494 * @ring_container: ring info to update the itr for
4495 *
4496 * Stores a new ITR value based on packets and byte
4497 * counts during the last interrupt. The advantage of per interrupt
4498 * computation is faster updates and more accurate ITR for the current
4499 * traffic pattern. Constants in this function were computed
4500 * based on theoretical maximum wire speed and thresholds were set based
4501 * on testing data as well as attempting to minimize response time
4502 * while increasing bulk throughput.
406d4965 4503 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4504 * NOTE: These calculations are only valid when operating in a single-
4505 * queue environment.
9d5c8243 4506 **/
0ba82994
AD		 4507static void igb_update_itr(struct igb_q_vector *q_vector,
4508 struct igb_ring_container *ring_container)
9d5c8243 4509{
0ba82994
AD		 4510 unsigned int packets = ring_container->total_packets;
4511 unsigned int bytes = ring_container->total_bytes;
4512 u8 itrval = ring_container->itr;
9d5c8243 4513
0ba82994 4514 /* no packets, exit with status unchanged */
9d5c8243 4515 if (packets == 0)
0ba82994 4516 return;
9d5c8243 4517
0ba82994 4518 switch (itrval) {
9d5c8243
AK		 4519 case lowest_latency:
4520 /* handle TSO and jumbo frames */
4521 if (bytes/packets > 8000)
0ba82994 4522 itrval = bulk_latency;
9d5c8243 4523 else if ((packets < 5) && (bytes > 512))
0ba82994 4524 itrval = low_latency;
9d5c8243
AK		 4525 break;
4526 case low_latency: /* 50 usec aka 20000 ints/s */
4527 if (bytes > 10000) {
4528 /* this if handles the TSO accounting */
d34a15ab 4529 if (bytes/packets > 8000)
0ba82994 4530 itrval = bulk_latency;
d34a15ab 4531 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4532 itrval = bulk_latency;
d34a15ab 4533 else if ((packets > 35))
0ba82994 4534 itrval = lowest_latency;
9d5c8243 4535 } else if (bytes/packets > 2000) {
0ba82994 4536 itrval = bulk_latency;
9d5c8243 4537 } else if (packets <= 2 && bytes < 512) {
0ba82994 4538 itrval = lowest_latency;
9d5c8243
AK		 4539 }
4540 break;
4541 case bulk_latency: /* 250 usec aka 4000 ints/s */
4542 if (bytes > 25000) {
4543 if (packets > 35)
0ba82994 4544 itrval = low_latency;
1e5c3d21 4545 } else if (bytes < 1500) {
0ba82994 4546 itrval = low_latency;
9d5c8243
AK		 4547 }
4548 break;
4549 }
4550
0ba82994
AD		 4551 /* clear work counters since we have the values we need */
4552 ring_container->total_bytes = 0;
4553 ring_container->total_packets = 0;
4554
4555 /* write updated itr to ring container */
4556 ring_container->itr = itrval;
9d5c8243
AK		 4557}
4558
0ba82994 4559static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4560{
0ba82994 4561 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4562 u32 new_itr = q_vector->itr_val;
0ba82994 4563 u8 current_itr = 0;
9d5c8243
AK		 4564
4565 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4566 if (adapter->link_speed != SPEED_1000) {
4567 current_itr = 0;
0ba82994 4568 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4569 goto set_itr_now;
4570 }
4571
0ba82994
AD		 4572 igb_update_itr(q_vector, &q_vector->tx);
4573 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4574
0ba82994 4575 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4576
6eb5a7f1 4577 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4578 if (current_itr == lowest_latency &&
4579 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4580 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4581 current_itr = low_latency;
4582
9d5c8243
AK		 4583 switch (current_itr) {
4584 /* counts and packets in update_itr are dependent on these numbers */
4585 case lowest_latency:
0ba82994 4586 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4587 break;
4588 case low_latency:
0ba82994 4589 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4590 break;
4591 case bulk_latency:
0ba82994 4592 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4593 break;
4594 default:
4595 break;
4596 }
4597
4598set_itr_now:
047e0030 4599 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4600 /* this attempts to bias the interrupt rate towards Bulk
4601 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4602 * increasing
4603 */
047e0030 4604 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4605 max((new_itr * q_vector->itr_val) /
4606 (new_itr + (q_vector->itr_val >> 2)),
4607 new_itr) : new_itr;
9d5c8243
AK		 4608 /* Don't write the value here; it resets the adapter's
4609 * internal timer, and causes us to delay far longer than
4610 * we should between interrupts. Instead, we write the ITR
4611 * value at the beginning of the next interrupt so the timing
4612 * ends up being correct.
4613 */
047e0030
AD		 4614 q_vector->itr_val = new_itr;
4615 q_vector->set_itr = 1;
9d5c8243 4616 }
9d5c8243
AK		 4617}
4618
c50b52a0
SH		 4619static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4620 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4621{
4622 struct e1000_adv_tx_context_desc *context_desc;
4623 u16 i = tx_ring->next_to_use;
4624
4625 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4626
4627 i++;
4628 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4629
4630 /* set bits to identify this as an advanced context descriptor */
4631 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4632
4633 /* For 82575, context index must be unique per ring. */
866cff06 4634 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4635 mss_l4len_idx |= tx_ring->reg_idx << 4;
4636
4637 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4638 context_desc->seqnum_seed = 0;
4639 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4640 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4641}
4642
7af40ad9
AD		 4643static int igb_tso(struct igb_ring *tx_ring,
4644 struct igb_tx_buffer *first,
4645 u8 *hdr_len)
9d5c8243 4646{
7af40ad9 4647 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4648 u32 vlan_macip_lens, type_tucmd;
4649 u32 mss_l4len_idx, l4len;
06c14e5a 4650 int err;
7d13a7d0 4651
ed6aa105
AD		 4652 if (skb->ip_summed != CHECKSUM_PARTIAL)
4653 return 0;
4654
7d13a7d0
AD		 4655 if (!skb_is_gso(skb))
4656 return 0;
9d5c8243 4657
06c14e5a
FR		 4658 err = skb_cow_head(skb, 0);
4659 if (err < 0)
4660 return err;
9d5c8243 4661
7d13a7d0
AD		 4662 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4663 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4664
7c4d16ff 4665 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4666 struct iphdr *iph = ip_hdr(skb);
4667 iph->tot_len = 0;
4668 iph->check = 0;
4669 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4670 iph->daddr, 0,
4671 IPPROTO_TCP,
4672 0);
7d13a7d0 4673 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4674 first->tx_flags |= IGB_TX_FLAGS_TSO |
4675 IGB_TX_FLAGS_CSUM |
4676 IGB_TX_FLAGS_IPV4;
8e1e8a47 4677 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4678 ipv6_hdr(skb)->payload_len = 0;
4679 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4680 &ipv6_hdr(skb)->daddr,
4681 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4682 first->tx_flags |= IGB_TX_FLAGS_TSO |
4683 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4684 }
4685
7af40ad9 4686 /* compute header lengths */
7d13a7d0
AD		 4687 l4len = tcp_hdrlen(skb);
4688 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4689
7af40ad9
AD		 4690 /* update gso size and bytecount with header size */
4691 first->gso_segs = skb_shinfo(skb)->gso_segs;
4692 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4693
9d5c8243 4694 /* MSS L4LEN IDX */
7d13a7d0
AD		 4695 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4696 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4697
7d13a7d0
AD		 4698 /* VLAN MACLEN IPLEN */
4699 vlan_macip_lens = skb_network_header_len(skb);
4700 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4701 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4702
7d13a7d0 4703 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4704
7d13a7d0 4705 return 1;
9d5c8243
AK		 4706}
4707
7af40ad9 4708static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4709{
7af40ad9 4710 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4711 u32 vlan_macip_lens = 0;
4712 u32 mss_l4len_idx = 0;
4713 u32 type_tucmd = 0;
9d5c8243 4714
7d13a7d0 4715 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4716 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4717 return;
7d13a7d0
AD		 4718 } else {
4719 u8 l4_hdr = 0;
9005df38 4720
7af40ad9 4721 switch (first->protocol) {
7c4d16ff 4722 case htons(ETH_P_IP):
7d13a7d0
AD		 4723 vlan_macip_lens |= skb_network_header_len(skb);
4724 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4725 l4_hdr = ip_hdr(skb)->protocol;
4726 break;
7c4d16ff 4727 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4728 vlan_macip_lens |= skb_network_header_len(skb);
4729 l4_hdr = ipv6_hdr(skb)->nexthdr;
4730 break;
4731 default:
4732 if (unlikely(net_ratelimit())) {
4733 dev_warn(tx_ring->dev,
b980ac18
JK		 4734 "partial checksum but proto=%x!\n",
4735 first->protocol);
fa4a7ef3 4736 }
7d13a7d0
AD		 4737 break;
4738 }
fa4a7ef3 4739
7d13a7d0
AD		 4740 switch (l4_hdr) {
4741 case IPPROTO_TCP:
4742 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4743 mss_l4len_idx = tcp_hdrlen(skb) <<
4744 E1000_ADVTXD_L4LEN_SHIFT;
4745 break;
4746 case IPPROTO_SCTP:
4747 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4748 mss_l4len_idx = sizeof(struct sctphdr) <<
4749 E1000_ADVTXD_L4LEN_SHIFT;
4750 break;
4751 case IPPROTO_UDP:
4752 mss_l4len_idx = sizeof(struct udphdr) <<
4753 E1000_ADVTXD_L4LEN_SHIFT;
4754 break;
4755 default:
4756 if (unlikely(net_ratelimit())) {
4757 dev_warn(tx_ring->dev,
b980ac18
JK		 4758 "partial checksum but l4 proto=%x!\n",
4759 l4_hdr);
44b0cda3 4760 }
7d13a7d0 4761 break;
9d5c8243 4762 }
7af40ad9
AD		 4763
4764 /* update TX checksum flag */
4765 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4766 }
9d5c8243 4767
7d13a7d0 4768 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4769 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4770
7d13a7d0 4771 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4772}
4773
1d9daf45
AD		 4774#define IGB_SET_FLAG(_input, _flag, _result) \
4775 ((_flag <= _result) ? \
4776 ((u32)(_input & _flag) * (_result / _flag)) : \
4777 ((u32)(_input & _flag) / (_flag / _result)))
4778
4779static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4780{
4781 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4782 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4783 E1000_ADVTXD_DCMD_DEXT |
4784 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4785
4786 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4787 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4788 (E1000_ADVTXD_DCMD_VLE));
4789
4790 /* set segmentation bits for TSO */
4791 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4792 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4793
4794 /* set timestamp bit if present */
1d9daf45
AD		 4795 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4796 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4797
1d9daf45
AD		 4798 /* insert frame checksum */
4799 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4800
4801 return cmd_type;
4802}
4803
7af40ad9
AD		 4804static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4805 union e1000_adv_tx_desc *tx_desc,
4806 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4807{
4808 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4809
1d9daf45
AD		 4810 /* 82575 requires a unique index per ring */
4811 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4812 olinfo_status |= tx_ring->reg_idx << 4;
4813
4814 /* insert L4 checksum */
1d9daf45
AD		 4815 olinfo_status |= IGB_SET_FLAG(tx_flags,
4816 IGB_TX_FLAGS_CSUM,
4817 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4818
1d9daf45
AD		 4819 /* insert IPv4 checksum */
4820 olinfo_status |= IGB_SET_FLAG(tx_flags,
4821 IGB_TX_FLAGS_IPV4,
4822 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4823
7af40ad9 4824 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4825}
4826
6f19e12f
DM		 4827static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4828{
4829 struct net_device *netdev = tx_ring->netdev;
4830
4831 netif_stop_subqueue(netdev, tx_ring->queue_index);
4832
4833 /* Herbert's original patch had:
4834 * smp_mb__after_netif_stop_queue();
4835 * but since that doesn't exist yet, just open code it.
4836 */
4837 smp_mb();
4838
4839 /* We need to check again in a case another CPU has just
4840 * made room available.
4841 */
4842 if (igb_desc_unused(tx_ring) < size)
4843 return -EBUSY;
4844
4845 /* A reprieve! */
4846 netif_wake_subqueue(netdev, tx_ring->queue_index);
4847
4848 u64_stats_update_begin(&tx_ring->tx_syncp2);
4849 tx_ring->tx_stats.restart_queue2++;
4850 u64_stats_update_end(&tx_ring->tx_syncp2);
4851
4852 return 0;
4853}
4854
4855static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4856{
4857 if (igb_desc_unused(tx_ring) >= size)
4858 return 0;
4859 return __igb_maybe_stop_tx(tx_ring, size);
4860}
4861
7af40ad9
AD		 4862static void igb_tx_map(struct igb_ring *tx_ring,
4863 struct igb_tx_buffer *first,
ebe42d16 4864 const u8 hdr_len)
9d5c8243 4865{
7af40ad9 4866 struct sk_buff *skb = first->skb;
c9f14bf3 4867 struct igb_tx_buffer *tx_buffer;
ebe42d16 4868 union e1000_adv_tx_desc *tx_desc;
80d0759e 4869 struct skb_frag_struct *frag;
ebe42d16 4870 dma_addr_t dma;
80d0759e 4871 unsigned int data_len, size;
7af40ad9 4872 u32 tx_flags = first->tx_flags;
1d9daf45 4873 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4874 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4875
4876 tx_desc = IGB_TX_DESC(tx_ring, i);
4877
80d0759e
AD		 4878 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4879
4880 size = skb_headlen(skb);
4881 data_len = skb->data_len;
ebe42d16
AD		 4882
4883 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4884
80d0759e
AD		 4885 tx_buffer = first;
4886
4887 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4888 if (dma_mapping_error(tx_ring->dev, dma))
4889 goto dma_error;
4890
4891 /* record length, and DMA address */
4892 dma_unmap_len_set(tx_buffer, len, size);
4893 dma_unmap_addr_set(tx_buffer, dma, dma);
4894
4895 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4896
ebe42d16
AD		 4897 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4898 tx_desc->read.cmd_type_len =
1d9daf45 4899 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4900
4901 i++;
4902 tx_desc++;
4903 if (i == tx_ring->count) {
4904 tx_desc = IGB_TX_DESC(tx_ring, 0);
4905 i = 0;
4906 }
80d0759e 4907 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4908
4909 dma += IGB_MAX_DATA_PER_TXD;
4910 size -= IGB_MAX_DATA_PER_TXD;
4911
ebe42d16
AD		 4912 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4913 }
4914
4915 if (likely(!data_len))
4916 break;
2bbfebe2 4917
1d9daf45 4918 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4919
65689fef 4920 i++;
ebe42d16
AD		 4921 tx_desc++;
4922 if (i == tx_ring->count) {
4923 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4924 i = 0;
ebe42d16 4925 }
80d0759e 4926 tx_desc->read.olinfo_status = 0;
65689fef 4927
9e903e08 4928 size = skb_frag_size(frag);
ebe42d16
AD		 4929 data_len -= size;
4930
4931 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4932 size, DMA_TO_DEVICE);
6366ad33 4933
c9f14bf3 4934 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4935 }
4936
ebe42d16 4937 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4938 cmd_type |= size | IGB_TXD_DCMD;
4939 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4940
80d0759e
AD		 4941 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4942
8542db05
AD		 4943 /* set the timestamp */
4944 first->time_stamp = jiffies;
4945
b980ac18 4946 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4947 * are new descriptors to fetch. (Only applicable for weak-ordered
4948 * memory model archs, such as IA-64).
4949 *
4950 * We also need this memory barrier to make certain all of the
4951 * status bits have been updated before next_to_watch is written.
4952 */
4953 wmb();
4954
8542db05 4955 /* set next_to_watch value indicating a packet is present */
ebe42d16 4956 first->next_to_watch = tx_desc;
9d5c8243 4957
ebe42d16
AD		 4958 i++;
4959 if (i == tx_ring->count)
4960 i = 0;
6366ad33 4961
ebe42d16 4962 tx_ring->next_to_use = i;
6366ad33 4963
6f19e12f
DM		 4964 /* Make sure there is space in the ring for the next send. */
4965 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4966
4967 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 4968 writel(i, tx_ring->tail);
4969
4970 /* we need this if more than one processor can write to our tail
4971 * at a time, it synchronizes IO on IA64/Altix systems
4972 */
4973 mmiowb();
4974 }
ebe42d16
AD		 4975 return;
4976
4977dma_error:
4978 dev_err(tx_ring->dev, "TX DMA map failed\n");
4979
4980 /* clear dma mappings for failed tx_buffer_info map */
4981 for (;;) {
c9f14bf3
AD		 4982 tx_buffer = &tx_ring->tx_buffer_info[i];
4983 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4984 if (tx_buffer == first)
ebe42d16 4985 break;
a77ff709
NN		 4986 if (i == 0)
4987 i = tx_ring->count;
6366ad33 4988 i--;
6366ad33
AD		 4989 }
4990
9d5c8243 4991 tx_ring->next_to_use = i;
9d5c8243
AK		 4992}
4993
cd392f5c
AD		 4994netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4995 struct igb_ring *tx_ring)
9d5c8243 4996{
8542db05 4997 struct igb_tx_buffer *first;
ebe42d16 4998 int tso;
91d4ee33 4999 u32 tx_flags = 0;
2ee52ad4 5000 unsigned short f;
21ba6fe1 5001 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5002 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5003 u8 hdr_len = 0;
9d5c8243 5004
21ba6fe1
AD		 5005 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5006 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5007 * + 2 desc gap to keep tail from touching head,
9d5c8243 5008 * + 1 desc for context descriptor,
21ba6fe1
AD		 5009 * otherwise try next time
5010 */
2ee52ad4
AD		 5011 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5012 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5013
5014 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5015 /* this is a hard error */
9d5c8243
AK		 5016 return NETDEV_TX_BUSY;
5017 }
33af6bcc 5018
7af40ad9
AD		 5019 /* record the location of the first descriptor for this packet */
5020 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5021 first->skb = skb;
5022 first->bytecount = skb->len;
5023 first->gso_segs = 1;
5024
b646c22e
AD		 5025 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5026 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5027
ed4420a3
JK		 5028 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5029 &adapter->state)) {
b646c22e
AD		 5030 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5031 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5032
5033 adapter->ptp_tx_skb = skb_get(skb);
5034 adapter->ptp_tx_start = jiffies;
5035 if (adapter->hw.mac.type == e1000_82576)
5036 schedule_work(&adapter->ptp_tx_work);
5037 }
33af6bcc 5038 }
9d5c8243 5039
afc835d1
JK		 5040 skb_tx_timestamp(skb);
5041
df8a39de 5042 if (skb_vlan_tag_present(skb)) {
9d5c8243 5043 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5044 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5045 }
5046
7af40ad9
AD		 5047 /* record initial flags and protocol */
5048 first->tx_flags = tx_flags;
5049 first->protocol = protocol;
cdfd01fc 5050
7af40ad9
AD		 5051 tso = igb_tso(tx_ring, first, &hdr_len);
5052 if (tso < 0)
7d13a7d0 5053 goto out_drop;
7af40ad9
AD		 5054 else if (!tso)
5055 igb_tx_csum(tx_ring, first);
9d5c8243 5056
7af40ad9 5057 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5058
9d5c8243 5059 return NETDEV_TX_OK;
7d13a7d0
AD		 5060
5061out_drop:
7af40ad9
AD		 5062 igb_unmap_and_free_tx_resource(tx_ring, first);
5063
7d13a7d0 5064 return NETDEV_TX_OK;
9d5c8243
AK		 5065}
5066
0b725a2c
DM		 5067static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5068 struct sk_buff *skb)
1cc3bd87 5069{
0b725a2c
DM		 5070 unsigned int r_idx = skb->queue_mapping;
5071
1cc3bd87
AD		 5072 if (r_idx >= adapter->num_tx_queues)
5073 r_idx = r_idx % adapter->num_tx_queues;
5074
5075 return adapter->tx_ring[r_idx];
5076}
5077
cd392f5c
AD		 5078static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5079 struct net_device *netdev)
9d5c8243
AK		 5080{
5081 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5082
5083 if (test_bit(__IGB_DOWN, &adapter->state)) {
5084 dev_kfree_skb_any(skb);
5085 return NETDEV_TX_OK;
5086 }
5087
5088 if (skb->len <= 0) {
5089 dev_kfree_skb_any(skb);
5090 return NETDEV_TX_OK;
5091 }
5092
b980ac18 5093 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5094 * in order to meet this minimum size requirement.
5095 */
a94d9e22
AD		 5096 if (skb_put_padto(skb, 17))
5097 return NETDEV_TX_OK;
9d5c8243 5098
1cc3bd87 5099 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5100}
5101
5102/**
b980ac18
JK		 5103 * igb_tx_timeout - Respond to a Tx Hang
5104 * @netdev: network interface device structure
9d5c8243
AK		 5105 **/
5106static void igb_tx_timeout(struct net_device *netdev)
5107{
5108 struct igb_adapter *adapter = netdev_priv(netdev);
5109 struct e1000_hw *hw = &adapter->hw;
5110
5111 /* Do the reset outside of interrupt context */
5112 adapter->tx_timeout_count++;
f7ba205e 5113
06218a8d 5114 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5115 hw->dev_spec._82575.global_device_reset = true;
5116
9d5c8243 5117 schedule_work(&adapter->reset_task);
265de409
AD		 5118 wr32(E1000_EICS,
5119 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5120}
5121
5122static void igb_reset_task(struct work_struct *work)
5123{
5124 struct igb_adapter *adapter;
5125 adapter = container_of(work, struct igb_adapter, reset_task);
5126
c97ec42a
TI		 5127 igb_dump(adapter);
5128 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5129 igb_reinit_locked(adapter);
5130}
5131
5132/**
b980ac18
JK		 5133 * igb_get_stats64 - Get System Network Statistics
5134 * @netdev: network interface device structure
5135 * @stats: rtnl_link_stats64 pointer
9d5c8243 5136 **/
12dcd86b 5137static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5138 struct rtnl_link_stats64 *stats)
9d5c8243 5139{
12dcd86b
ED		 5140 struct igb_adapter *adapter = netdev_priv(netdev);
5141
5142 spin_lock(&adapter->stats64_lock);
5143 igb_update_stats(adapter, &adapter->stats64);
5144 memcpy(stats, &adapter->stats64, sizeof(*stats));
5145 spin_unlock(&adapter->stats64_lock);
5146
5147 return stats;
9d5c8243
AK		 5148}
5149
5150/**
b980ac18
JK		 5151 * igb_change_mtu - Change the Maximum Transfer Unit
5152 * @netdev: network interface device structure
5153 * @new_mtu: new value for maximum frame size
9d5c8243 5154 *
b980ac18 5155 * Returns 0 on success, negative on failure
9d5c8243
AK		 5156 **/
5157static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5158{
5159 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5160 struct pci_dev *pdev = adapter->pdev;
153285f9 5161 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5162
c809d227 5163 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5164 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5165 return -EINVAL;
5166 }
5167
153285f9 5168#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5169 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5170 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5171 return -EINVAL;
5172 }
5173
2ccd994c
AD		 5174 /* adjust max frame to be at least the size of a standard frame */
5175 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5176 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5177
9d5c8243 5178 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5179 usleep_range(1000, 2000);
73cd78f1 5180
9d5c8243
AK		 5181 /* igb_down has a dependency on max_frame_size */
5182 adapter->max_frame_size = max_frame;
559e9c49 5183
4c844851
AD		 5184 if (netif_running(netdev))
5185 igb_down(adapter);
9d5c8243 5186
090b1795 5187 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5188 netdev->mtu, new_mtu);
5189 netdev->mtu = new_mtu;
5190
5191 if (netif_running(netdev))
5192 igb_up(adapter);
5193 else
5194 igb_reset(adapter);
5195
5196 clear_bit(__IGB_RESETTING, &adapter->state);
5197
5198 return 0;
5199}
5200
5201/**
b980ac18
JK		 5202 * igb_update_stats - Update the board statistics counters
5203 * @adapter: board private structure
9d5c8243 5204 **/
12dcd86b
ED		 5205void igb_update_stats(struct igb_adapter *adapter,
5206 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5207{
5208 struct e1000_hw *hw = &adapter->hw;
5209 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5210 u32 reg, mpc;
3f9c0164
AD		 5211 int i;
5212 u64 bytes, packets;
12dcd86b
ED		 5213 unsigned int start;
5214 u64 _bytes, _packets;
9d5c8243 5215
b980ac18 5216 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5217 * connection is down.
5218 */
5219 if (adapter->link_speed == 0)
5220 return;
5221 if (pci_channel_offline(pdev))
5222 return;
5223
3f9c0164
AD		 5224 bytes = 0;
5225 packets = 0;
7f90128e
AA		 5226
5227 rcu_read_lock();
3f9c0164 5228 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5229 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5230 u32 rqdpc = rd32(E1000_RQDPC(i));
5231 if (hw->mac.type >= e1000_i210)
5232 wr32(E1000_RQDPC(i), 0);
12dcd86b 5233
ae1c07a6
AD		 5234 if (rqdpc) {
5235 ring->rx_stats.drops += rqdpc;
5236 net_stats->rx_fifo_errors += rqdpc;
5237 }
12dcd86b
ED		 5238
5239 do {
57a7744e 5240 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5241 _bytes = ring->rx_stats.bytes;
5242 _packets = ring->rx_stats.packets;
57a7744e 5243 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5244 bytes += _bytes;
5245 packets += _packets;
3f9c0164
AD		 5246 }
5247
128e45eb
AD		 5248 net_stats->rx_bytes = bytes;
5249 net_stats->rx_packets = packets;
3f9c0164
AD		 5250
5251 bytes = 0;
5252 packets = 0;
5253 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5254 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5255 do {
57a7744e 5256 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5257 _bytes = ring->tx_stats.bytes;
5258 _packets = ring->tx_stats.packets;
57a7744e 5259 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5260 bytes += _bytes;
5261 packets += _packets;
3f9c0164 5262 }
128e45eb
AD		 5263 net_stats->tx_bytes = bytes;
5264 net_stats->tx_packets = packets;
7f90128e 5265 rcu_read_unlock();
3f9c0164
AD		 5266
5267 /* read stats registers */
9d5c8243
AK		 5268 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5269 adapter->stats.gprc += rd32(E1000_GPRC);
5270 adapter->stats.gorc += rd32(E1000_GORCL);
5271 rd32(E1000_GORCH); /* clear GORCL */
5272 adapter->stats.bprc += rd32(E1000_BPRC);
5273 adapter->stats.mprc += rd32(E1000_MPRC);
5274 adapter->stats.roc += rd32(E1000_ROC);
5275
5276 adapter->stats.prc64 += rd32(E1000_PRC64);
5277 adapter->stats.prc127 += rd32(E1000_PRC127);
5278 adapter->stats.prc255 += rd32(E1000_PRC255);
5279 adapter->stats.prc511 += rd32(E1000_PRC511);
5280 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5281 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5282 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5283 adapter->stats.sec += rd32(E1000_SEC);
5284
fa3d9a6d
MW		 5285 mpc = rd32(E1000_MPC);
5286 adapter->stats.mpc += mpc;
5287 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5288 adapter->stats.scc += rd32(E1000_SCC);
5289 adapter->stats.ecol += rd32(E1000_ECOL);
5290 adapter->stats.mcc += rd32(E1000_MCC);
5291 adapter->stats.latecol += rd32(E1000_LATECOL);
5292 adapter->stats.dc += rd32(E1000_DC);
5293 adapter->stats.rlec += rd32(E1000_RLEC);
5294 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5295 adapter->stats.xontxc += rd32(E1000_XONTXC);
5296 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5297 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5298 adapter->stats.fcruc += rd32(E1000_FCRUC);
5299 adapter->stats.gptc += rd32(E1000_GPTC);
5300 adapter->stats.gotc += rd32(E1000_GOTCL);
5301 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5302 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5303 adapter->stats.ruc += rd32(E1000_RUC);
5304 adapter->stats.rfc += rd32(E1000_RFC);
5305 adapter->stats.rjc += rd32(E1000_RJC);
5306 adapter->stats.tor += rd32(E1000_TORH);
5307 adapter->stats.tot += rd32(E1000_TOTH);
5308 adapter->stats.tpr += rd32(E1000_TPR);
5309
5310 adapter->stats.ptc64 += rd32(E1000_PTC64);
5311 adapter->stats.ptc127 += rd32(E1000_PTC127);
5312 adapter->stats.ptc255 += rd32(E1000_PTC255);
5313 adapter->stats.ptc511 += rd32(E1000_PTC511);
5314 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5315 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5316
5317 adapter->stats.mptc += rd32(E1000_MPTC);
5318 adapter->stats.bptc += rd32(E1000_BPTC);
5319
2d0b0f69
NN		 5320 adapter->stats.tpt += rd32(E1000_TPT);
5321 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5322
5323 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5324 /* read internal phy specific stats */
5325 reg = rd32(E1000_CTRL_EXT);
5326 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5327 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5328
5329 /* this stat has invalid values on i210/i211 */
5330 if ((hw->mac.type != e1000_i210) &&
5331 (hw->mac.type != e1000_i211))
5332 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5333 }
5334
9d5c8243
AK		 5335 adapter->stats.tsctc += rd32(E1000_TSCTC);
5336 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5337
5338 adapter->stats.iac += rd32(E1000_IAC);
5339 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5340 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5341 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5342 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5343 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5344 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5345 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5346 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5347
5348 /* Fill out the OS statistics structure */
128e45eb
AD		 5349 net_stats->multicast = adapter->stats.mprc;
5350 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5351
5352 /* Rx Errors */
5353
5354 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5355 * our own version based on RUC and ROC
5356 */
128e45eb 5357 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5358 adapter->stats.crcerrs + adapter->stats.algnerrc +
5359 adapter->stats.ruc + adapter->stats.roc +
5360 adapter->stats.cexterr;
128e45eb
AD		 5361 net_stats->rx_length_errors = adapter->stats.ruc +
5362 adapter->stats.roc;
5363 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5364 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5365 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5366
5367 /* Tx Errors */
128e45eb
AD		 5368 net_stats->tx_errors = adapter->stats.ecol +
5369 adapter->stats.latecol;
5370 net_stats->tx_aborted_errors = adapter->stats.ecol;
5371 net_stats->tx_window_errors = adapter->stats.latecol;
5372 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5373
5374 /* Tx Dropped needs to be maintained elsewhere */
5375
9d5c8243
AK		 5376 /* Management Stats */
5377 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5378 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5379 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5380
5381 /* OS2BMC Stats */
5382 reg = rd32(E1000_MANC);
5383 if (reg & E1000_MANC_EN_BMC2OS) {
5384 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5385 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5386 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5387 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5388 }
9d5c8243
AK		 5389}
5390
61d7f75f
RC		 5391static void igb_tsync_interrupt(struct igb_adapter *adapter)
5392{
5393 struct e1000_hw *hw = &adapter->hw;
00c65578 5394 struct ptp_clock_event event;
720db4ff
RC		 5395 struct timespec ts;
5396 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5397
5398 if (tsicr & TSINTR_SYS_WRAP) {
5399 event.type = PTP_CLOCK_PPS;
5400 if (adapter->ptp_caps.pps)
5401 ptp_clock_event(adapter->ptp_clock, &event);
5402 else
5403 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5404 ack |= TSINTR_SYS_WRAP;
5405 }
61d7f75f
RC		 5406
5407 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5408 /* retrieve hardware timestamp */
5409 schedule_work(&adapter->ptp_tx_work);
00c65578 5410 ack |= E1000_TSICR_TXTS;
61d7f75f 5411 }
00c65578 5412
720db4ff
RC		 5413 if (tsicr & TSINTR_TT0) {
5414 spin_lock(&adapter->tmreg_lock);
5415 ts = timespec_add(adapter->perout[0].start,
5416 adapter->perout[0].period);
5417 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5418 wr32(E1000_TRGTTIMH0, ts.tv_sec);
5419 tsauxc = rd32(E1000_TSAUXC);
5420 tsauxc |= TSAUXC_EN_TT0;
5421 wr32(E1000_TSAUXC, tsauxc);
5422 adapter->perout[0].start = ts;
5423 spin_unlock(&adapter->tmreg_lock);
5424 ack |= TSINTR_TT0;
5425 }
5426
5427 if (tsicr & TSINTR_TT1) {
5428 spin_lock(&adapter->tmreg_lock);
5429 ts = timespec_add(adapter->perout[1].start,
5430 adapter->perout[1].period);
5431 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5432 wr32(E1000_TRGTTIMH1, ts.tv_sec);
5433 tsauxc = rd32(E1000_TSAUXC);
5434 tsauxc |= TSAUXC_EN_TT1;
5435 wr32(E1000_TSAUXC, tsauxc);
5436 adapter->perout[1].start = ts;
5437 spin_unlock(&adapter->tmreg_lock);
5438 ack |= TSINTR_TT1;
5439 }
5440
5441 if (tsicr & TSINTR_AUTT0) {
5442 nsec = rd32(E1000_AUXSTMPL0);
5443 sec = rd32(E1000_AUXSTMPH0);
5444 event.type = PTP_CLOCK_EXTTS;
5445 event.index = 0;
5446 event.timestamp = sec * 1000000000ULL + nsec;
5447 ptp_clock_event(adapter->ptp_clock, &event);
5448 ack |= TSINTR_AUTT0;
5449 }
5450
5451 if (tsicr & TSINTR_AUTT1) {
5452 nsec = rd32(E1000_AUXSTMPL1);
5453 sec = rd32(E1000_AUXSTMPH1);
5454 event.type = PTP_CLOCK_EXTTS;
5455 event.index = 1;
5456 event.timestamp = sec * 1000000000ULL + nsec;
5457 ptp_clock_event(adapter->ptp_clock, &event);
5458 ack |= TSINTR_AUTT1;
5459 }
5460
00c65578
RC		 5461 /* acknowledge the interrupts */
5462 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5463}
5464
9d5c8243
AK		 5465static irqreturn_t igb_msix_other(int irq, void *data)
5466{
047e0030 5467 struct igb_adapter *adapter = data;
9d5c8243 5468 struct e1000_hw *hw = &adapter->hw;
844290e5 5469 u32 icr = rd32(E1000_ICR);
844290e5 5470 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5471
7f081d40
AD		 5472 if (icr & E1000_ICR_DRSTA)
5473 schedule_work(&adapter->reset_task);
5474
047e0030 5475 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5476 /* HW is reporting DMA is out of sync */
5477 adapter->stats.doosync++;
13800469
GR		 5478 /* The DMA Out of Sync is also indication of a spoof event
5479 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5480 * see if it is really a spoof event.
5481 */
13800469 5482 igb_check_wvbr(adapter);
dda0e083 5483 }
eebbbdba 5484
4ae196df
AD		 5485 /* Check for a mailbox event */
5486 if (icr & E1000_ICR_VMMB)
5487 igb_msg_task(adapter);
5488
5489 if (icr & E1000_ICR_LSC) {
5490 hw->mac.get_link_status = 1;
5491 /* guard against interrupt when we're going down */
5492 if (!test_bit(__IGB_DOWN, &adapter->state))
5493 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5494 }
5495
61d7f75f
RC		 5496 if (icr & E1000_ICR_TS)
5497 igb_tsync_interrupt(adapter);
1f6e8178 5498
844290e5 5499 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5500
5501 return IRQ_HANDLED;
5502}
5503
047e0030 5504static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5505{
26b39276 5506 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5507 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5508
047e0030
AD		 5509 if (!q_vector->set_itr)
5510 return;
73cd78f1 5511
047e0030
AD		 5512 if (!itr_val)
5513 itr_val = 0x4;
661086df 5514
26b39276
AD		 5515 if (adapter->hw.mac.type == e1000_82575)
5516 itr_val |= itr_val << 16;
661086df 5517 else
0ba82994 5518 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5519
047e0030
AD		 5520 writel(itr_val, q_vector->itr_register);
5521 q_vector->set_itr = 0;
6eb5a7f1
AD		 5522}
5523
047e0030 5524static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5525{
047e0030 5526 struct igb_q_vector *q_vector = data;
9d5c8243 5527
047e0030
AD		 5528 /* Write the ITR value calculated from the previous interrupt. */
5529 igb_write_itr(q_vector);
9d5c8243 5530
047e0030 5531 napi_schedule(&q_vector->napi);
844290e5 5532
047e0030 5533 return IRQ_HANDLED;
fe4506b6
JC		 5534}
5535
421e02f0 5536#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5537static void igb_update_tx_dca(struct igb_adapter *adapter,
5538 struct igb_ring *tx_ring,
5539 int cpu)
5540{
5541 struct e1000_hw *hw = &adapter->hw;
5542 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5543
5544 if (hw->mac.type != e1000_82575)
5545 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5546
b980ac18 5547 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5548 * DCA is enabled. This is due to a known issue in some chipsets
5549 * which will cause the DCA tag to be cleared.
5550 */
5551 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5552 E1000_DCA_TXCTRL_DATA_RRO_EN |
5553 E1000_DCA_TXCTRL_DESC_DCA_EN;
5554
5555 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5556}
5557
5558static void igb_update_rx_dca(struct igb_adapter *adapter,
5559 struct igb_ring *rx_ring,
5560 int cpu)
5561{
5562 struct e1000_hw *hw = &adapter->hw;
5563 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5564
5565 if (hw->mac.type != e1000_82575)
5566 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5567
b980ac18 5568 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5569 * DCA is enabled. This is due to a known issue in some chipsets
5570 * which will cause the DCA tag to be cleared.
5571 */
5572 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5573 E1000_DCA_RXCTRL_DESC_DCA_EN;
5574
5575 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5576}
5577
047e0030 5578static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5579{
047e0030 5580 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5581 int cpu = get_cpu();
fe4506b6 5582
047e0030
AD		 5583 if (q_vector->cpu == cpu)
5584 goto out_no_update;
5585
6a05004a
AD		 5586 if (q_vector->tx.ring)
5587 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5588
5589 if (q_vector->rx.ring)
5590 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5591
047e0030
AD		 5592 q_vector->cpu = cpu;
5593out_no_update:
fe4506b6
JC		 5594 put_cpu();
5595}
5596
5597static void igb_setup_dca(struct igb_adapter *adapter)
5598{
7e0e99ef 5599 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5600 int i;
5601
7dfc16fa 5602 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5603 return;
5604
7e0e99ef
AD		 5605 /* Always use CB2 mode, difference is masked in the CB driver. */
5606 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5607
047e0030 5608 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5609 adapter->q_vector[i]->cpu = -1;
5610 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5611 }
5612}
5613
5614static int __igb_notify_dca(struct device *dev, void *data)
5615{
5616 struct net_device *netdev = dev_get_drvdata(dev);
5617 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5618 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5619 struct e1000_hw *hw = &adapter->hw;
5620 unsigned long event = *(unsigned long *)data;
5621
5622 switch (event) {
5623 case DCA_PROVIDER_ADD:
5624 /* if already enabled, don't do it again */
7dfc16fa 5625 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5626 break;
fe4506b6 5627 if (dca_add_requester(dev) == 0) {
bbd98fe4 5628 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5629 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5630 igb_setup_dca(adapter);
5631 break;
5632 }
5633 /* Fall Through since DCA is disabled. */
5634 case DCA_PROVIDER_REMOVE:
7dfc16fa 5635 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5636 /* without this a class_device is left
b980ac18
JK		 5637 * hanging around in the sysfs model
5638 */
fe4506b6 5639 dca_remove_requester(dev);
090b1795 5640 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5641 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5642 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5643 }
5644 break;
5645 }
bbd98fe4 5646
fe4506b6 5647 return 0;
9d5c8243
AK		 5648}
5649
fe4506b6 5650static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5651 void *p)
fe4506b6
JC		 5652{
5653 int ret_val;
5654
5655 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5656 __igb_notify_dca);
fe4506b6
JC		 5657
5658 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5659}
421e02f0 5660#endif /* CONFIG_IGB_DCA */
9d5c8243 5661
0224d663
GR		 5662#ifdef CONFIG_PCI_IOV
5663static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5664{
5665 unsigned char mac_addr[ETH_ALEN];
0224d663 5666
5ac6f91d 5667 eth_zero_addr(mac_addr);
0224d663
GR		 5668 igb_set_vf_mac(adapter, vf, mac_addr);
5669
70ea4783
LL		 5670 /* By default spoof check is enabled for all VFs */
5671 adapter->vf_data[vf].spoofchk_enabled = true;
5672
f557147c 5673 return 0;
0224d663
GR		 5674}
5675
0224d663 5676#endif
4ae196df
AD		 5677static void igb_ping_all_vfs(struct igb_adapter *adapter)
5678{
5679 struct e1000_hw *hw = &adapter->hw;
5680 u32 ping;
5681 int i;
5682
5683 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5684 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5685 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5686 ping |= E1000_VT_MSGTYPE_CTS;
5687 igb_write_mbx(hw, &ping, 1, i);
5688 }
5689}
5690
7d5753f0
AD		 5691static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5692{
5693 struct e1000_hw *hw = &adapter->hw;
5694 u32 vmolr = rd32(E1000_VMOLR(vf));
5695 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5696
d85b9004 5697 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5698 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5699 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5700
5701 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5702 vmolr |= E1000_VMOLR_MPME;
d85b9004 5703 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5704 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5705 } else {
b980ac18 5706 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5707 * flag we need to write the hashes to the MTA as this step
5708 * was previously skipped
5709 */
5710 if (vf_data->num_vf_mc_hashes > 30) {
5711 vmolr |= E1000_VMOLR_MPME;
5712 } else if (vf_data->num_vf_mc_hashes) {
5713 int j;
9005df38 5714
7d5753f0
AD		 5715 vmolr |= E1000_VMOLR_ROMPE;
5716 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5717 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5718 }
5719 }
5720
5721 wr32(E1000_VMOLR(vf), vmolr);
5722
5723 /* there are flags left unprocessed, likely not supported */
5724 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5725 return -EINVAL;
5726
5727 return 0;
7d5753f0
AD		 5728}
5729
4ae196df
AD		 5730static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5731 u32 *msgbuf, u32 vf)
5732{
5733 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5734 u16 *hash_list = (u16 *)&msgbuf[1];
5735 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5736 int i;
5737
7d5753f0 5738 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5739 * to this VF for later use to restore when the PF multi cast
5740 * list changes
5741 */
5742 vf_data->num_vf_mc_hashes = n;
5743
7d5753f0
AD		 5744 /* only up to 30 hash values supported */
5745 if (n > 30)
5746 n = 30;
5747
5748 /* store the hashes for later use */
4ae196df 5749 for (i = 0; i < n; i++)
a419aef8 5750 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5751
5752 /* Flush and reset the mta with the new values */
ff41f8dc 5753 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5754
5755 return 0;
5756}
5757
5758static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5759{
5760 struct e1000_hw *hw = &adapter->hw;
5761 struct vf_data_storage *vf_data;
5762 int i, j;
5763
5764 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5765 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5766
7d5753f0
AD		 5767 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5768
4ae196df 5769 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5770
5771 if ((vf_data->num_vf_mc_hashes > 30) ||
5772 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5773 vmolr |= E1000_VMOLR_MPME;
5774 } else if (vf_data->num_vf_mc_hashes) {
5775 vmolr |= E1000_VMOLR_ROMPE;
5776 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5777 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5778 }
5779 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5780 }
5781}
5782
5783static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5784{
5785 struct e1000_hw *hw = &adapter->hw;
5786 u32 pool_mask, reg, vid;
5787 int i;
5788
5789 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5790
5791 /* Find the vlan filter for this id */
5792 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5793 reg = rd32(E1000_VLVF(i));
5794
5795 /* remove the vf from the pool */
5796 reg &= ~pool_mask;
5797
5798 /* if pool is empty then remove entry from vfta */
5799 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5800 (reg & E1000_VLVF_VLANID_ENABLE)) {
5801 reg = 0;
5802 vid = reg & E1000_VLVF_VLANID_MASK;
5803 igb_vfta_set(hw, vid, false);
5804 }
5805
5806 wr32(E1000_VLVF(i), reg);
5807 }
ae641bdc
AD		 5808
5809 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5810}
5811
5812static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5813{
5814 struct e1000_hw *hw = &adapter->hw;
5815 u32 reg, i;
5816
51466239
AD		 5817 /* The vlvf table only exists on 82576 hardware and newer */
5818 if (hw->mac.type < e1000_82576)
5819 return -1;
5820
5821 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5822 if (!adapter->vfs_allocated_count)
5823 return -1;
5824
5825 /* Find the vlan filter for this id */
5826 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5827 reg = rd32(E1000_VLVF(i));
5828 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5829 vid == (reg & E1000_VLVF_VLANID_MASK))
5830 break;
5831 }
5832
5833 if (add) {
5834 if (i == E1000_VLVF_ARRAY_SIZE) {
5835 /* Did not find a matching VLAN ID entry that was
5836 * enabled. Search for a free filter entry, i.e.
5837 * one without the enable bit set
5838 */
5839 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5840 reg = rd32(E1000_VLVF(i));
5841 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5842 break;
5843 }
5844 }
5845 if (i < E1000_VLVF_ARRAY_SIZE) {
5846 /* Found an enabled/available entry */
5847 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5848
5849 /* if !enabled we need to set this up in vfta */
5850 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5851 /* add VID to filter table */
5852 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5853 reg |= E1000_VLVF_VLANID_ENABLE;
5854 }
cad6d05f
AD		 5855 reg &= ~E1000_VLVF_VLANID_MASK;
5856 reg |= vid;
4ae196df 5857 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5858
5859 /* do not modify RLPML for PF devices */
5860 if (vf >= adapter->vfs_allocated_count)
5861 return 0;
5862
5863 if (!adapter->vf_data[vf].vlans_enabled) {
5864 u32 size;
9005df38 5865
ae641bdc
AD		 5866 reg = rd32(E1000_VMOLR(vf));
5867 size = reg & E1000_VMOLR_RLPML_MASK;
5868 size += 4;
5869 reg &= ~E1000_VMOLR_RLPML_MASK;
5870 reg |= size;
5871 wr32(E1000_VMOLR(vf), reg);
5872 }
ae641bdc 5873
51466239 5874 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5875 }
5876 } else {
5877 if (i < E1000_VLVF_ARRAY_SIZE) {
5878 /* remove vf from the pool */
5879 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5880 /* if pool is empty then remove entry from vfta */
5881 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5882 reg = 0;
5883 igb_vfta_set(hw, vid, false);
5884 }
5885 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5886
5887 /* do not modify RLPML for PF devices */
5888 if (vf >= adapter->vfs_allocated_count)
5889 return 0;
5890
5891 adapter->vf_data[vf].vlans_enabled--;
5892 if (!adapter->vf_data[vf].vlans_enabled) {
5893 u32 size;
9005df38 5894
ae641bdc
AD		 5895 reg = rd32(E1000_VMOLR(vf));
5896 size = reg & E1000_VMOLR_RLPML_MASK;
5897 size -= 4;
5898 reg &= ~E1000_VMOLR_RLPML_MASK;
5899 reg |= size;
5900 wr32(E1000_VMOLR(vf), reg);
5901 }
4ae196df
AD		 5902 }
5903 }
8151d294
WM		 5904 return 0;
5905}
5906
5907static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5908{
5909 struct e1000_hw *hw = &adapter->hw;
5910
5911 if (vid)
5912 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5913 else
5914 wr32(E1000_VMVIR(vf), 0);
5915}
5916
5917static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5918 int vf, u16 vlan, u8 qos)
5919{
5920 int err = 0;
5921 struct igb_adapter *adapter = netdev_priv(netdev);
5922
5923 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5924 return -EINVAL;
5925 if (vlan || qos) {
5926 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5927 if (err)
5928 goto out;
5929 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5930 igb_set_vmolr(adapter, vf, !vlan);
5931 adapter->vf_data[vf].pf_vlan = vlan;
5932 adapter->vf_data[vf].pf_qos = qos;
5933 dev_info(&adapter->pdev->dev,
5934 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5935 if (test_bit(__IGB_DOWN, &adapter->state)) {
5936 dev_warn(&adapter->pdev->dev,
b980ac18 5937 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5938 dev_warn(&adapter->pdev->dev,
b980ac18 5939 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5940 }
5941 } else {
5942 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5943 false, vf);
8151d294
WM		 5944 igb_set_vmvir(adapter, vlan, vf);
5945 igb_set_vmolr(adapter, vf, true);
5946 adapter->vf_data[vf].pf_vlan = 0;
5947 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5948 }
8151d294 5949out:
b980ac18 5950 return err;
4ae196df
AD		 5951}
5952
6f3dc319
GR		 5953static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5954{
5955 struct e1000_hw *hw = &adapter->hw;
5956 int i;
5957 u32 reg;
5958
5959 /* Find the vlan filter for this id */
5960 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5961 reg = rd32(E1000_VLVF(i));
5962 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5963 vid == (reg & E1000_VLVF_VLANID_MASK))
5964 break;
5965 }
5966
5967 if (i >= E1000_VLVF_ARRAY_SIZE)
5968 i = -1;
5969
5970 return i;
5971}
5972
4ae196df
AD		 5973static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5974{
6f3dc319 5975 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5976 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5977 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5978 int err = 0;
4ae196df 5979
6f3dc319
GR		 5980 /* If in promiscuous mode we need to make sure the PF also has
5981 * the VLAN filter set.
5982 */
5983 if (add && (adapter->netdev->flags & IFF_PROMISC))
5984 err = igb_vlvf_set(adapter, vid, add,
5985 adapter->vfs_allocated_count);
5986 if (err)
5987 goto out;
5988
5989 err = igb_vlvf_set(adapter, vid, add, vf);
5990
5991 if (err)
5992 goto out;
5993
5994 /* Go through all the checks to see if the VLAN filter should
5995 * be wiped completely.
5996 */
5997 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5998 u32 vlvf, bits;
6f3dc319 5999 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 6000
6f3dc319
GR		 6001 if (regndx < 0)
6002 goto out;
6003 /* See if any other pools are set for this VLAN filter
6004 * entry other than the PF.
6005 */
6006 vlvf = bits = rd32(E1000_VLVF(regndx));
6007 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6008 adapter->vfs_allocated_count);
6009 /* If the filter was removed then ensure PF pool bit
6010 * is cleared if the PF only added itself to the pool
6011 * because the PF is in promiscuous mode.
6012 */
6013 if ((vlvf & VLAN_VID_MASK) == vid &&
6014 !test_bit(vid, adapter->active_vlans) &&
6015 !bits)
6016 igb_vlvf_set(adapter, vid, add,
6017 adapter->vfs_allocated_count);
6018 }
6019
6020out:
6021 return err;
4ae196df
AD		 6022}
6023
f2ca0dbe 6024static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 6025{
8fa7e0f7
GR		 6026 /* clear flags - except flag that indicates PF has set the MAC */
6027 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 6028 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 6029
6030 /* reset offloads to defaults */
8151d294 6031 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 6032
6033 /* reset vlans for device */
6034 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 6035 if (adapter->vf_data[vf].pf_vlan)
6036 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6037 adapter->vf_data[vf].pf_vlan,
6038 adapter->vf_data[vf].pf_qos);
6039 else
6040 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 6041
6042 /* reset multicast table array for vf */
6043 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6044
6045 /* Flush and reset the mta with the new values */
ff41f8dc 6046 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6047}
6048
f2ca0dbe
AD		 6049static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6050{
6051 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6052
5ac6f91d 6053 /* clear mac address as we were hotplug removed/added */
8151d294 6054 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6055 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6056
6057 /* process remaining reset events */
6058 igb_vf_reset(adapter, vf);
6059}
6060
6061static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6062{
6063 struct e1000_hw *hw = &adapter->hw;
6064 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6065 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6066 u32 reg, msgbuf[3];
6067 u8 *addr = (u8 *)(&msgbuf[1]);
6068
6069 /* process all the same items cleared in a function level reset */
f2ca0dbe 6070 igb_vf_reset(adapter, vf);
4ae196df
AD		 6071
6072 /* set vf mac address */
26ad9178 6073 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6074
6075 /* enable transmit and receive for vf */
6076 reg = rd32(E1000_VFTE);
6077 wr32(E1000_VFTE, reg | (1 << vf));
6078 reg = rd32(E1000_VFRE);
6079 wr32(E1000_VFRE, reg | (1 << vf));
6080
8fa7e0f7 6081 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6082
6083 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6084 if (!is_zero_ether_addr(vf_mac)) {
6085 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6086 memcpy(addr, vf_mac, ETH_ALEN);
6087 } else {
6088 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6089 }
4ae196df
AD		 6090 igb_write_mbx(hw, msgbuf, 3, vf);
6091}
6092
6093static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6094{
b980ac18 6095 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6096 * starting at the second 32 bit word of the msg array
6097 */
f2ca0dbe
AD		 6098 unsigned char *addr = (char *)&msg[1];
6099 int err = -1;
4ae196df 6100
f2ca0dbe
AD		 6101 if (is_valid_ether_addr(addr))
6102 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6103
f2ca0dbe 6104 return err;
4ae196df
AD		 6105}
6106
6107static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6108{
6109 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6110 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6111 u32 msg = E1000_VT_MSGTYPE_NACK;
6112
6113 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6114 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6115 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6116 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6117 vf_data->last_nack = jiffies;
4ae196df
AD		 6118 }
6119}
6120
f2ca0dbe 6121static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6122{
f2ca0dbe
AD		 6123 struct pci_dev *pdev = adapter->pdev;
6124 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6125 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6126 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6127 s32 retval;
6128
f2ca0dbe 6129 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6130
fef45f4c
AD		 6131 if (retval) {
6132 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6133 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6134 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6135 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6136 return;
6137 goto out;
6138 }
4ae196df
AD		 6139
6140 /* this is a message we already processed, do nothing */
6141 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6142 return;
4ae196df 6143
b980ac18 6144 /* until the vf completes a reset it should not be
4ae196df
AD		 6145 * allowed to start any configuration.
6146 */
4ae196df
AD		 6147 if (msgbuf[0] == E1000_VF_RESET) {
6148 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6149 return;
4ae196df
AD		 6150 }
6151
f2ca0dbe 6152 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6153 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6154 return;
6155 retval = -1;
6156 goto out;
4ae196df
AD		 6157 }
6158
6159 switch ((msgbuf[0] & 0xFFFF)) {
6160 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6161 retval = -EINVAL;
6162 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6163 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6164 else
6165 dev_warn(&pdev->dev,
b980ac18
JK		 6166 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6167 vf);
4ae196df 6168 break;
7d5753f0
AD		 6169 case E1000_VF_SET_PROMISC:
6170 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6171 break;
4ae196df
AD		 6172 case E1000_VF_SET_MULTICAST:
6173 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6174 break;
6175 case E1000_VF_SET_LPE:
6176 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6177 break;
6178 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6179 retval = -1;
6180 if (vf_data->pf_vlan)
6181 dev_warn(&pdev->dev,
b980ac18
JK		 6182 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6183 vf);
8151d294
WM		 6184 else
6185 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6186 break;
6187 default:
090b1795 6188 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6189 retval = -1;
6190 break;
6191 }
6192
fef45f4c
AD		 6193 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6194out:
4ae196df
AD		 6195 /* notify the VF of the results of what it sent us */
6196 if (retval)
6197 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6198 else
6199 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6200
4ae196df 6201 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6202}
4ae196df 6203
f2ca0dbe
AD		 6204static void igb_msg_task(struct igb_adapter *adapter)
6205{
6206 struct e1000_hw *hw = &adapter->hw;
6207 u32 vf;
6208
6209 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6210 /* process any reset requests */
6211 if (!igb_check_for_rst(hw, vf))
6212 igb_vf_reset_event(adapter, vf);
6213
6214 /* process any messages pending */
6215 if (!igb_check_for_msg(hw, vf))
6216 igb_rcv_msg_from_vf(adapter, vf);
6217
6218 /* process any acks */
6219 if (!igb_check_for_ack(hw, vf))
6220 igb_rcv_ack_from_vf(adapter, vf);
6221 }
4ae196df
AD		 6222}
6223
68d480c4
AD		 6224/**
6225 * igb_set_uta - Set unicast filter table address
6226 * @adapter: board private structure
6227 *
6228 * The unicast table address is a register array of 32-bit registers.
6229 * The table is meant to be used in a way similar to how the MTA is used
6230 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6231 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6232 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6233 **/
6234static void igb_set_uta(struct igb_adapter *adapter)
6235{
6236 struct e1000_hw *hw = &adapter->hw;
6237 int i;
6238
6239 /* The UTA table only exists on 82576 hardware and newer */
6240 if (hw->mac.type < e1000_82576)
6241 return;
6242
6243 /* we only need to do this if VMDq is enabled */
6244 if (!adapter->vfs_allocated_count)
6245 return;
6246
6247 for (i = 0; i < hw->mac.uta_reg_count; i++)
6248 array_wr32(E1000_UTA, i, ~0);
6249}
6250
9d5c8243 6251/**
b980ac18
JK		 6252 * igb_intr_msi - Interrupt Handler
6253 * @irq: interrupt number
6254 * @data: pointer to a network interface device structure
9d5c8243
AK		 6255 **/
6256static irqreturn_t igb_intr_msi(int irq, void *data)
6257{
047e0030
AD		 6258 struct igb_adapter *adapter = data;
6259 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6260 struct e1000_hw *hw = &adapter->hw;
6261 /* read ICR disables interrupts using IAM */
6262 u32 icr = rd32(E1000_ICR);
6263
047e0030 6264 igb_write_itr(q_vector);
9d5c8243 6265
7f081d40
AD		 6266 if (icr & E1000_ICR_DRSTA)
6267 schedule_work(&adapter->reset_task);
6268
047e0030 6269 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6270 /* HW is reporting DMA is out of sync */
6271 adapter->stats.doosync++;
6272 }
6273
9d5c8243
AK		 6274 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6275 hw->mac.get_link_status = 1;
6276 if (!test_bit(__IGB_DOWN, &adapter->state))
6277 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6278 }
6279
61d7f75f
RC		 6280 if (icr & E1000_ICR_TS)
6281 igb_tsync_interrupt(adapter);
1f6e8178 6282
047e0030 6283 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6284
6285 return IRQ_HANDLED;
6286}
6287
6288/**
b980ac18
JK		 6289 * igb_intr - Legacy Interrupt Handler
6290 * @irq: interrupt number
6291 * @data: pointer to a network interface device structure
9d5c8243
AK		 6292 **/
6293static irqreturn_t igb_intr(int irq, void *data)
6294{
047e0030
AD		 6295 struct igb_adapter *adapter = data;
6296 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6297 struct e1000_hw *hw = &adapter->hw;
6298 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6299 * need for the IMC write
6300 */
9d5c8243 6301 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6302
6303 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6304 * not set, then the adapter didn't send an interrupt
6305 */
9d5c8243
AK		 6306 if (!(icr & E1000_ICR_INT_ASSERTED))
6307 return IRQ_NONE;
6308
0ba82994
AD		 6309 igb_write_itr(q_vector);
6310
7f081d40
AD		 6311 if (icr & E1000_ICR_DRSTA)
6312 schedule_work(&adapter->reset_task);
6313
047e0030 6314 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6315 /* HW is reporting DMA is out of sync */
6316 adapter->stats.doosync++;
6317 }
6318
9d5c8243
AK		 6319 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6320 hw->mac.get_link_status = 1;
6321 /* guard against interrupt when we're going down */
6322 if (!test_bit(__IGB_DOWN, &adapter->state))
6323 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6324 }
6325
61d7f75f
RC		 6326 if (icr & E1000_ICR_TS)
6327 igb_tsync_interrupt(adapter);
1f6e8178 6328
047e0030 6329 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6330
6331 return IRQ_HANDLED;
6332}
6333
c50b52a0 6334static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6335{
047e0030 6336 struct igb_adapter *adapter = q_vector->adapter;
46544258 6337 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6338
0ba82994
AD		 6339 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6340 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6341 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6342 igb_set_itr(q_vector);
46544258 6343 else
047e0030 6344 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6345 }
6346
46544258 6347 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6348 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6349 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6350 else
6351 igb_irq_enable(adapter);
6352 }
9d5c8243
AK		 6353}
6354
46544258 6355/**
b980ac18
JK		 6356 * igb_poll - NAPI Rx polling callback
6357 * @napi: napi polling structure
6358 * @budget: count of how many packets we should handle
46544258
AD		 6359 **/
6360static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6361{
047e0030 6362 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6363 struct igb_q_vector,
6364 napi);
16eb8815 6365 bool clean_complete = true;
9d5c8243 6366
421e02f0 6367#ifdef CONFIG_IGB_DCA
047e0030
AD		 6368 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6369 igb_update_dca(q_vector);
fe4506b6 6370#endif
0ba82994 6371 if (q_vector->tx.ring)
13fde97a 6372 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6373
0ba82994 6374 if (q_vector->rx.ring)
cd392f5c 6375 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6376
16eb8815
AD		 6377 /* If all work not completed, return budget and keep polling */
6378 if (!clean_complete)
6379 return budget;
46544258 6380
9d5c8243 6381 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6382 napi_complete(napi);
6383 igb_ring_irq_enable(q_vector);
9d5c8243 6384
16eb8815 6385 return 0;
9d5c8243 6386}
6d8126f9 6387
9d5c8243 6388/**
b980ac18
JK		 6389 * igb_clean_tx_irq - Reclaim resources after transmit completes
6390 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6391 *
b980ac18 6392 * returns true if ring is completely cleaned
9d5c8243 6393 **/
047e0030 6394static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6395{
047e0030 6396 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6397 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6398 struct igb_tx_buffer *tx_buffer;
f4128785 6399 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6400 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6401 unsigned int budget = q_vector->tx.work_limit;
8542db05 6402 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6403
13fde97a
AD		 6404 if (test_bit(__IGB_DOWN, &adapter->state))
6405 return true;
0e014cb1 6406
06034649 6407 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6408 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6409 i -= tx_ring->count;
9d5c8243 6410
f4128785
AD		 6411 do {
6412 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6413
6414 /* if next_to_watch is not set then there is no work pending */
6415 if (!eop_desc)
6416 break;
13fde97a 6417
f4128785 6418 /* prevent any other reads prior to eop_desc */
70d289bc 6419 read_barrier_depends();
f4128785 6420
13fde97a
AD		 6421 /* if DD is not set pending work has not been completed */
6422 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6423 break;
6424
8542db05
AD		 6425 /* clear next_to_watch to prevent false hangs */
6426 tx_buffer->next_to_watch = NULL;
9d5c8243 6427
ebe42d16
AD		 6428 /* update the statistics for this packet */
6429 total_bytes += tx_buffer->bytecount;
6430 total_packets += tx_buffer->gso_segs;
13fde97a 6431
ebe42d16 6432 /* free the skb */
a81fb049 6433 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6434
ebe42d16
AD		 6435 /* unmap skb header data */
6436 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6437 dma_unmap_addr(tx_buffer, dma),
6438 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6439 DMA_TO_DEVICE);
6440
c9f14bf3
AD		 6441 /* clear tx_buffer data */
6442 tx_buffer->skb = NULL;
6443 dma_unmap_len_set(tx_buffer, len, 0);
6444
ebe42d16
AD		 6445 /* clear last DMA location and unmap remaining buffers */
6446 while (tx_desc != eop_desc) {
13fde97a
AD		 6447 tx_buffer++;
6448 tx_desc++;
9d5c8243 6449 i++;
8542db05
AD		 6450 if (unlikely(!i)) {
6451 i -= tx_ring->count;
06034649 6452 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6453 tx_desc = IGB_TX_DESC(tx_ring, 0);
6454 }
ebe42d16
AD		 6455
6456 /* unmap any remaining paged data */
c9f14bf3 6457 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6458 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6459 dma_unmap_addr(tx_buffer, dma),
6460 dma_unmap_len(tx_buffer, len),
ebe42d16 6461 DMA_TO_DEVICE);
c9f14bf3 6462 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6463 }
6464 }
6465
ebe42d16
AD		 6466 /* move us one more past the eop_desc for start of next pkt */
6467 tx_buffer++;
6468 tx_desc++;
6469 i++;
6470 if (unlikely(!i)) {
6471 i -= tx_ring->count;
6472 tx_buffer = tx_ring->tx_buffer_info;
6473 tx_desc = IGB_TX_DESC(tx_ring, 0);
6474 }
f4128785
AD		 6475
6476 /* issue prefetch for next Tx descriptor */
6477 prefetch(tx_desc);
6478
6479 /* update budget accounting */
6480 budget--;
6481 } while (likely(budget));
0e014cb1 6482
bdbc0631
ED		 6483 netdev_tx_completed_queue(txring_txq(tx_ring),
6484 total_packets, total_bytes);
8542db05 6485 i += tx_ring->count;
9d5c8243 6486 tx_ring->next_to_clean = i;
13fde97a
AD		 6487 u64_stats_update_begin(&tx_ring->tx_syncp);
6488 tx_ring->tx_stats.bytes += total_bytes;
6489 tx_ring->tx_stats.packets += total_packets;
6490 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6491 q_vector->tx.total_bytes += total_bytes;
6492 q_vector->tx.total_packets += total_packets;
9d5c8243 6493
6d095fa8 6494 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6495 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6496
9d5c8243 6497 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6498 * check with the clearing of time_stamp and movement of i
6499 */
6d095fa8 6500 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6501 if (tx_buffer->next_to_watch &&
8542db05 6502 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6503 (adapter->tx_timeout_factor * HZ)) &&
6504 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6505
9d5c8243 6506 /* detected Tx unit hang */
59d71989 6507 dev_err(tx_ring->dev,
9d5c8243 6508 "Detected Tx Unit Hang\n"
2d064c06 6509 " Tx Queue <%d>\n"
9d5c8243
AK		 6510 " TDH <%x>\n"
6511 " TDT <%x>\n"
6512 " next_to_use <%x>\n"
6513 " next_to_clean <%x>\n"
9d5c8243
AK		 6514 "buffer_info[next_to_clean]\n"
6515 " time_stamp <%lx>\n"
8542db05 6516 " next_to_watch <%p>\n"
9d5c8243
AK		 6517 " jiffies <%lx>\n"
6518 " desc.status <%x>\n",
2d064c06 6519 tx_ring->queue_index,
238ac817 6520 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6521 readl(tx_ring->tail),
9d5c8243
AK		 6522 tx_ring->next_to_use,
6523 tx_ring->next_to_clean,
8542db05 6524 tx_buffer->time_stamp,
f4128785 6525 tx_buffer->next_to_watch,
9d5c8243 6526 jiffies,
f4128785 6527 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6528 netif_stop_subqueue(tx_ring->netdev,
6529 tx_ring->queue_index);
6530
6531 /* we are about to reset, no point in enabling stuff */
6532 return true;
9d5c8243
AK		 6533 }
6534 }
13fde97a 6535
21ba6fe1 6536#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6537 if (unlikely(total_packets &&
b980ac18
JK		 6538 netif_carrier_ok(tx_ring->netdev) &&
6539 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6540 /* Make sure that anybody stopping the queue after this
6541 * sees the new next_to_clean.
6542 */
6543 smp_mb();
6544 if (__netif_subqueue_stopped(tx_ring->netdev,
6545 tx_ring->queue_index) &&
6546 !(test_bit(__IGB_DOWN, &adapter->state))) {
6547 netif_wake_subqueue(tx_ring->netdev,
6548 tx_ring->queue_index);
6549
6550 u64_stats_update_begin(&tx_ring->tx_syncp);
6551 tx_ring->tx_stats.restart_queue++;
6552 u64_stats_update_end(&tx_ring->tx_syncp);
6553 }
6554 }
6555
6556 return !!budget;
9d5c8243
AK		 6557}
6558
cbc8e55f 6559/**
b980ac18
JK		 6560 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6561 * @rx_ring: rx descriptor ring to store buffers on
6562 * @old_buff: donor buffer to have page reused
cbc8e55f 6563 *
b980ac18 6564 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6565 **/
6566static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6567 struct igb_rx_buffer *old_buff)
6568{
6569 struct igb_rx_buffer *new_buff;
6570 u16 nta = rx_ring->next_to_alloc;
6571
6572 new_buff = &rx_ring->rx_buffer_info[nta];
6573
6574 /* update, and store next to alloc */
6575 nta++;
6576 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6577
6578 /* transfer page from old buffer to new buffer */
a1f63473 6579 *new_buff = *old_buff;
cbc8e55f
AD		 6580
6581 /* sync the buffer for use by the device */
6582 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6583 old_buff->page_offset,
de78d1f9 6584 IGB_RX_BUFSZ,
cbc8e55f
AD		 6585 DMA_FROM_DEVICE);
6586}
6587
95dd44b4
AD		 6588static inline bool igb_page_is_reserved(struct page *page)
6589{
2f064f34 6590 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6591}
6592
74e238ea
AD		 6593static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6594 struct page *page,
6595 unsigned int truesize)
6596{
6597 /* avoid re-using remote pages */
95dd44b4 6598 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6599 return false;
6600
74e238ea
AD		 6601#if (PAGE_SIZE < 8192)
6602 /* if we are only owner of page we can reuse it */
6603 if (unlikely(page_count(page) != 1))
6604 return false;
6605
6606 /* flip page offset to other buffer */
6607 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6608#else
6609 /* move offset up to the next cache line */
6610 rx_buffer->page_offset += truesize;
6611
6612 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6613 return false;
74e238ea
AD		 6614#endif
6615
95dd44b4
AD		 6616 /* Even if we own the page, we are not allowed to use atomic_set()
6617 * This would break get_page_unless_zero() users.
6618 */
6619 atomic_inc(&page->_count);
6620
74e238ea
AD		 6621 return true;
6622}
6623
cbc8e55f 6624/**
b980ac18
JK		 6625 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6626 * @rx_ring: rx descriptor ring to transact packets on
6627 * @rx_buffer: buffer containing page to add
6628 * @rx_desc: descriptor containing length of buffer written by hardware
6629 * @skb: sk_buff to place the data into
cbc8e55f 6630 *
b980ac18
JK		 6631 * This function will add the data contained in rx_buffer->page to the skb.
6632 * This is done either through a direct copy if the data in the buffer is
6633 * less than the skb header size, otherwise it will just attach the page as
6634 * a frag to the skb.
cbc8e55f 6635 *
b980ac18
JK		 6636 * The function will then update the page offset if necessary and return
6637 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6638 **/
6639static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6640 struct igb_rx_buffer *rx_buffer,
6641 union e1000_adv_rx_desc *rx_desc,
6642 struct sk_buff *skb)
6643{
6644 struct page *page = rx_buffer->page;
f56e7bba 6645 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6646 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6647#if (PAGE_SIZE < 8192)
6648 unsigned int truesize = IGB_RX_BUFSZ;
6649#else
f56e7bba 6650 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6651#endif
f56e7bba 6652 unsigned int pull_len;
cbc8e55f 6653
f56e7bba
AD		 6654 if (unlikely(skb_is_nonlinear(skb)))
6655 goto add_tail_frag;
cbc8e55f 6656
f56e7bba
AD		 6657 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6658 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6659 va += IGB_TS_HDR_LEN;
6660 size -= IGB_TS_HDR_LEN;
6661 }
cbc8e55f 6662
f56e7bba 6663 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6664 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6665
95dd44b4
AD		 6666 /* page is not reserved, we can reuse buffer as-is */
6667 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6668 return true;
6669
6670 /* this page cannot be reused so discard it */
95dd44b4 6671 __free_page(page);
cbc8e55f
AD		 6672 return false;
6673 }
6674
f56e7bba
AD		 6675 /* we need the header to contain the greater of either ETH_HLEN or
6676 * 60 bytes if the skb->len is less than 60 for skb_pad.
6677 */
6678 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6679
6680 /* align pull length to size of long to optimize memcpy performance */
6681 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6682
6683 /* update all of the pointers */
6684 va += pull_len;
6685 size -= pull_len;
6686
6687add_tail_frag:
cbc8e55f 6688 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6689 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6690
74e238ea
AD		 6691 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6692}
cbc8e55f 6693
2e334eee
AD		 6694static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6695 union e1000_adv_rx_desc *rx_desc,
6696 struct sk_buff *skb)
6697{
6698 struct igb_rx_buffer *rx_buffer;
6699 struct page *page;
6700
6701 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6702 page = rx_buffer->page;
6703 prefetchw(page);
6704
6705 if (likely(!skb)) {
6706 void *page_addr = page_address(page) +
6707 rx_buffer->page_offset;
6708
6709 /* prefetch first cache line of first page */
6710 prefetch(page_addr);
6711#if L1_CACHE_BYTES < 128
6712 prefetch(page_addr + L1_CACHE_BYTES);
6713#endif
6714
6715 /* allocate a skb to store the frags */
67fd893e 6716 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6717 if (unlikely(!skb)) {
6718 rx_ring->rx_stats.alloc_failed++;
6719 return NULL;
6720 }
6721
b980ac18 6722 /* we will be copying header into skb->data in
2e334eee
AD		 6723 * pskb_may_pull so it is in our interest to prefetch
6724 * it now to avoid a possible cache miss
6725 */
6726 prefetchw(skb->data);
6727 }
6728
6729 /* we are reusing so sync this buffer for CPU use */
6730 dma_sync_single_range_for_cpu(rx_ring->dev,
6731 rx_buffer->dma,
6732 rx_buffer->page_offset,
de78d1f9 6733 IGB_RX_BUFSZ,
2e334eee
AD		 6734 DMA_FROM_DEVICE);
6735
6736 /* pull page into skb */
6737 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6738 /* hand second half of page back to the ring */
6739 igb_reuse_rx_page(rx_ring, rx_buffer);
6740 } else {
6741 /* we are not reusing the buffer so unmap it */
6742 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6743 PAGE_SIZE, DMA_FROM_DEVICE);
6744 }
6745
6746 /* clear contents of rx_buffer */
6747 rx_buffer->page = NULL;
6748
6749 return skb;
6750}
6751
cd392f5c 6752static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6753 union e1000_adv_rx_desc *rx_desc,
6754 struct sk_buff *skb)
9d5c8243 6755{
bc8acf2c 6756 skb_checksum_none_assert(skb);
9d5c8243 6757
294e7d78 6758 /* Ignore Checksum bit is set */
3ceb90fd 6759 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6760 return;
6761
6762 /* Rx checksum disabled via ethtool */
6763 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6764 return;
85ad76b2 6765
9d5c8243 6766 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6767 if (igb_test_staterr(rx_desc,
6768 E1000_RXDEXT_STATERR_TCPE |
6769 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6770 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6771 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6772 * packets, (aka let the stack check the crc32c)
6773 */
866cff06
AD		 6774 if (!((skb->len == 60) &&
6775 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6776 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6777 ring->rx_stats.csum_err++;
12dcd86b
ED		 6778 u64_stats_update_end(&ring->rx_syncp);
6779 }
9d5c8243 6780 /* let the stack verify checksum errors */
9d5c8243
AK		 6781 return;
6782 }
6783 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6784 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6785 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6786 skb->ip_summed = CHECKSUM_UNNECESSARY;
6787
3ceb90fd
AD		 6788 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6789 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6790}
6791
077887c3
AD		 6792static inline void igb_rx_hash(struct igb_ring *ring,
6793 union e1000_adv_rx_desc *rx_desc,
6794 struct sk_buff *skb)
6795{
6796 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6797 skb_set_hash(skb,
6798 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6799 PKT_HASH_TYPE_L3);
077887c3
AD		 6800}
6801
2e334eee 6802/**
b980ac18
JK		 6803 * igb_is_non_eop - process handling of non-EOP buffers
6804 * @rx_ring: Rx ring being processed
6805 * @rx_desc: Rx descriptor for current buffer
6806 * @skb: current socket buffer containing buffer in progress
2e334eee 6807 *
b980ac18
JK		 6808 * This function updates next to clean. If the buffer is an EOP buffer
6809 * this function exits returning false, otherwise it will place the
6810 * sk_buff in the next buffer to be chained and return true indicating
6811 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6812 **/
6813static bool igb_is_non_eop(struct igb_ring *rx_ring,
6814 union e1000_adv_rx_desc *rx_desc)
6815{
6816 u32 ntc = rx_ring->next_to_clean + 1;
6817
6818 /* fetch, update, and store next to clean */
6819 ntc = (ntc < rx_ring->count) ? ntc : 0;
6820 rx_ring->next_to_clean = ntc;
6821
6822 prefetch(IGB_RX_DESC(rx_ring, ntc));
6823
6824 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6825 return false;
6826
6827 return true;
6828}
6829
1a1c225b 6830/**
b980ac18
JK		 6831 * igb_cleanup_headers - Correct corrupted or empty headers
6832 * @rx_ring: rx descriptor ring packet is being transacted on
6833 * @rx_desc: pointer to the EOP Rx descriptor
6834 * @skb: pointer to current skb being fixed
1a1c225b 6835 *
b980ac18
JK		 6836 * Address the case where we are pulling data in on pages only
6837 * and as such no data is present in the skb header.
1a1c225b 6838 *
b980ac18
JK		 6839 * In addition if skb is not at least 60 bytes we need to pad it so that
6840 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6841 *
b980ac18 6842 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6843 **/
6844static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6845 union e1000_adv_rx_desc *rx_desc,
6846 struct sk_buff *skb)
6847{
1a1c225b
AD		 6848 if (unlikely((igb_test_staterr(rx_desc,
6849 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6850 struct net_device *netdev = rx_ring->netdev;
6851 if (!(netdev->features & NETIF_F_RXALL)) {
6852 dev_kfree_skb_any(skb);
6853 return true;
6854 }
6855 }
6856
a94d9e22
AD		 6857 /* if eth_skb_pad returns an error the skb was freed */
6858 if (eth_skb_pad(skb))
6859 return true;
1a1c225b
AD		 6860
6861 return false;
2d94d8ab
AD		 6862}
6863
db2ee5bd 6864/**
b980ac18
JK		 6865 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6866 * @rx_ring: rx descriptor ring packet is being transacted on
6867 * @rx_desc: pointer to the EOP Rx descriptor
6868 * @skb: pointer to current skb being populated
db2ee5bd 6869 *
b980ac18
JK		 6870 * This function checks the ring, descriptor, and packet information in
6871 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6872 * other fields within the skb.
db2ee5bd
AD		 6873 **/
6874static void igb_process_skb_fields(struct igb_ring *rx_ring,
6875 union e1000_adv_rx_desc *rx_desc,
6876 struct sk_buff *skb)
6877{
6878 struct net_device *dev = rx_ring->netdev;
6879
6880 igb_rx_hash(rx_ring, rx_desc, skb);
6881
6882 igb_rx_checksum(rx_ring, rx_desc, skb);
6883
5499a968
JK		 6884 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6885 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6886 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6887
f646968f 6888 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6889 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6890 u16 vid;
9005df38 6891
db2ee5bd
AD		 6892 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6893 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6894 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6895 else
6896 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6897
86a9bad3 6898 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6899 }
6900
6901 skb_record_rx_queue(skb, rx_ring->queue_index);
6902
6903 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6904}
6905
2e334eee 6906static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6907{
0ba82994 6908 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6909 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6910 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6911 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6912
57ba34c9 6913 while (likely(total_packets < budget)) {
2e334eee 6914 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6915
2e334eee
AD		 6916 /* return some buffers to hardware, one at a time is too slow */
6917 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6918 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6919 cleaned_count = 0;
6920 }
bf36c1a0 6921
2e334eee 6922 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6923
124b74c1 6924 if (!rx_desc->wb.upper.status_error)
2e334eee 6925 break;
9d5c8243 6926
74e238ea
AD		 6927 /* This memory barrier is needed to keep us from reading
6928 * any other fields out of the rx_desc until we know the
124b74c1 6929 * descriptor has been written back
74e238ea 6930 */
124b74c1 6931 dma_rmb();
74e238ea 6932
2e334eee 6933 /* retrieve a buffer from the ring */
f9d40f6a 6934 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6935
2e334eee
AD		 6936 /* exit if we failed to retrieve a buffer */
6937 if (!skb)
6938 break;
1a1c225b 6939
2e334eee 6940 cleaned_count++;
1a1c225b 6941
2e334eee
AD		 6942 /* fetch next buffer in frame if non-eop */
6943 if (igb_is_non_eop(rx_ring, rx_desc))
6944 continue;
1a1c225b
AD		 6945
6946 /* verify the packet layout is correct */
6947 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6948 skb = NULL;
6949 continue;
9d5c8243 6950 }
9d5c8243 6951
db2ee5bd 6952 /* probably a little skewed due to removing CRC */
3ceb90fd 6953 total_bytes += skb->len;
3ceb90fd 6954
db2ee5bd
AD		 6955 /* populate checksum, timestamp, VLAN, and protocol */
6956 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6957
b2cb09b1 6958 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6959
1a1c225b
AD		 6960 /* reset skb pointer */
6961 skb = NULL;
6962
2e334eee
AD		 6963 /* update budget accounting */
6964 total_packets++;
57ba34c9 6965 }
bf36c1a0 6966
1a1c225b
AD		 6967 /* place incomplete frames back on ring for completion */
6968 rx_ring->skb = skb;
6969
12dcd86b 6970 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6971 rx_ring->rx_stats.packets += total_packets;
6972 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6973 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6974 q_vector->rx.total_packets += total_packets;
6975 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6976
6977 if (cleaned_count)
cd392f5c 6978 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6979
da1f1dfe 6980 return total_packets < budget;
9d5c8243
AK		 6981}
6982
c023cd88 6983static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6984 struct igb_rx_buffer *bi)
c023cd88
AD		 6985{
6986 struct page *page = bi->page;
cbc8e55f 6987 dma_addr_t dma;
c023cd88 6988
cbc8e55f
AD		 6989 /* since we are recycling buffers we should seldom need to alloc */
6990 if (likely(page))
c023cd88
AD		 6991 return true;
6992
cbc8e55f 6993 /* alloc new page for storage */
42b17f09 6994 page = dev_alloc_page();
cbc8e55f
AD		 6995 if (unlikely(!page)) {
6996 rx_ring->rx_stats.alloc_failed++;
6997 return false;
c023cd88
AD		 6998 }
6999
cbc8e55f
AD		 7000 /* map page for use */
7001 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7002
b980ac18 7003 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7004 * there isn't much point in holding memory we can't use
7005 */
1a1c225b 7006 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7007 __free_page(page);
7008
c023cd88
AD		 7009 rx_ring->rx_stats.alloc_failed++;
7010 return false;
7011 }
7012
1a1c225b 7013 bi->dma = dma;
cbc8e55f
AD		 7014 bi->page = page;
7015 bi->page_offset = 0;
1a1c225b 7016
c023cd88
AD		 7017 return true;
7018}
7019
9d5c8243 7020/**
b980ac18
JK		 7021 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7022 * @adapter: address of board private structure
9d5c8243 7023 **/
cd392f5c 7024void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7025{
9d5c8243 7026 union e1000_adv_rx_desc *rx_desc;
06034649 7027 struct igb_rx_buffer *bi;
c023cd88 7028 u16 i = rx_ring->next_to_use;
9d5c8243 7029
cbc8e55f
AD		 7030 /* nothing to do */
7031 if (!cleaned_count)
7032 return;
7033
60136906 7034 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7035 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7036 i -= rx_ring->count;
9d5c8243 7037
cbc8e55f 7038 do {
1a1c225b 7039 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7040 break;
9d5c8243 7041
b980ac18 7042 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7043 * because each write-back erases this info.
7044 */
f9d40f6a 7045 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7046
c023cd88
AD		 7047 rx_desc++;
7048 bi++;
9d5c8243 7049 i++;
c023cd88 7050 if (unlikely(!i)) {
60136906 7051 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7052 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7053 i -= rx_ring->count;
7054 }
7055
95dd44b4
AD		 7056 /* clear the status bits for the next_to_use descriptor */
7057 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7058
7059 cleaned_count--;
7060 } while (cleaned_count);
9d5c8243 7061
c023cd88
AD		 7062 i += rx_ring->count;
7063
9d5c8243 7064 if (rx_ring->next_to_use != i) {
cbc8e55f 7065 /* record the next descriptor to use */
9d5c8243 7066 rx_ring->next_to_use = i;
9d5c8243 7067
cbc8e55f
AD		 7068 /* update next to alloc since we have filled the ring */
7069 rx_ring->next_to_alloc = i;
7070
b980ac18 7071 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7072 * know there are new descriptors to fetch. (Only
7073 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7074 * such as IA-64).
7075 */
9d5c8243 7076 wmb();
fce99e34 7077 writel(i, rx_ring->tail);
9d5c8243
AK		 7078 }
7079}
7080
7081/**
7082 * igb_mii_ioctl -
7083 * @netdev:
7084 * @ifreq:
7085 * @cmd:
7086 **/
7087static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7088{
7089 struct igb_adapter *adapter = netdev_priv(netdev);
7090 struct mii_ioctl_data *data = if_mii(ifr);
7091
7092 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7093 return -EOPNOTSUPP;
7094
7095 switch (cmd) {
7096 case SIOCGMIIPHY:
7097 data->phy_id = adapter->hw.phy.addr;
7098 break;
7099 case SIOCGMIIREG:
f5f4cf08 7100 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7101 &data->val_out))
9d5c8243
AK		 7102 return -EIO;
7103 break;
7104 case SIOCSMIIREG:
7105 default:
7106 return -EOPNOTSUPP;
7107 }
7108 return 0;
7109}
7110
7111/**
7112 * igb_ioctl -
7113 * @netdev:
7114 * @ifreq:
7115 * @cmd:
7116 **/
7117static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7118{
7119 switch (cmd) {
7120 case SIOCGMIIPHY:
7121 case SIOCGMIIREG:
7122 case SIOCSMIIREG:
7123 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7124 case SIOCGHWTSTAMP:
7125 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7126 case SIOCSHWTSTAMP:
6ab5f7b2 7127 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7128 default:
7129 return -EOPNOTSUPP;
7130 }
7131}
7132
94826487
TF		 7133void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7134{
7135 struct igb_adapter *adapter = hw->back;
7136
7137 pci_read_config_word(adapter->pdev, reg, value);
7138}
7139
7140void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7141{
7142 struct igb_adapter *adapter = hw->back;
7143
7144 pci_write_config_word(adapter->pdev, reg, *value);
7145}
7146
009bc06e
AD		 7147s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7148{
7149 struct igb_adapter *adapter = hw->back;
009bc06e 7150
23d028cc 7151 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7152 return -E1000_ERR_CONFIG;
7153
009bc06e
AD		 7154 return 0;
7155}
7156
7157s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7158{
7159 struct igb_adapter *adapter = hw->back;
009bc06e 7160
23d028cc 7161 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7162 return -E1000_ERR_CONFIG;
7163
009bc06e
AD		 7164 return 0;
7165}
7166
c8f44aff 7167static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7168{
7169 struct igb_adapter *adapter = netdev_priv(netdev);
7170 struct e1000_hw *hw = &adapter->hw;
7171 u32 ctrl, rctl;
f646968f 7172 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7173
5faf030c 7174 if (enable) {
9d5c8243
AK		 7175 /* enable VLAN tag insert/strip */
7176 ctrl = rd32(E1000_CTRL);
7177 ctrl |= E1000_CTRL_VME;
7178 wr32(E1000_CTRL, ctrl);
7179
51466239 7180 /* Disable CFI check */
9d5c8243 7181 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7182 rctl &= ~E1000_RCTL_CFIEN;
7183 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7184 } else {
7185 /* disable VLAN tag insert/strip */
7186 ctrl = rd32(E1000_CTRL);
7187 ctrl &= ~E1000_CTRL_VME;
7188 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7189 }
7190
e1739522 7191 igb_rlpml_set(adapter);
9d5c8243
AK		 7192}
7193
80d5c368
PM		 7194static int igb_vlan_rx_add_vid(struct net_device *netdev,
7195 __be16 proto, u16 vid)
9d5c8243
AK		 7196{
7197 struct igb_adapter *adapter = netdev_priv(netdev);
7198 struct e1000_hw *hw = &adapter->hw;
4ae196df 7199 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7200
51466239
AD		 7201 /* attempt to add filter to vlvf array */
7202 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7203
51466239
AD		 7204 /* add the filter since PF can receive vlans w/o entry in vlvf */
7205 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7206
7207 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7208
7209 return 0;
9d5c8243
AK		 7210}
7211
80d5c368
PM		 7212static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7213 __be16 proto, u16 vid)
9d5c8243
AK		 7214{
7215 struct igb_adapter *adapter = netdev_priv(netdev);
7216 struct e1000_hw *hw = &adapter->hw;
4ae196df 7217 int pf_id = adapter->vfs_allocated_count;
51466239 7218 s32 err;
9d5c8243 7219
51466239
AD		 7220 /* remove vlan from VLVF table array */
7221 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7222
51466239
AD		 7223 /* if vid was not present in VLVF just remove it from table */
7224 if (err)
4ae196df 7225 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7226
7227 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7228
7229 return 0;
9d5c8243
AK		 7230}
7231
7232static void igb_restore_vlan(struct igb_adapter *adapter)
7233{
b2cb09b1 7234 u16 vid;
9d5c8243 7235
5faf030c
AD		 7236 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7237
b2cb09b1 7238 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7239 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7240}
7241
14ad2513 7242int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7243{
090b1795 7244 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7245 struct e1000_mac_info *mac = &adapter->hw.mac;
7246
7247 mac->autoneg = 0;
7248
14ad2513 7249 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7250 * for the switch() below to work
7251 */
14ad2513
DD		 7252 if ((spd & 1) || (dplx & ~1))
7253 goto err_inval;
7254
f502ef7d
AA		 7255 /* Fiber NIC's only allow 1000 gbps Full duplex
7256 * and 100Mbps Full duplex for 100baseFx sfp
7257 */
7258 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7259 switch (spd + dplx) {
7260 case SPEED_10 + DUPLEX_HALF:
7261 case SPEED_10 + DUPLEX_FULL:
7262 case SPEED_100 + DUPLEX_HALF:
7263 goto err_inval;
7264 default:
7265 break;
7266 }
7267 }
cd2638a8 7268
14ad2513 7269 switch (spd + dplx) {
9d5c8243
AK		 7270 case SPEED_10 + DUPLEX_HALF:
7271 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7272 break;
7273 case SPEED_10 + DUPLEX_FULL:
7274 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7275 break;
7276 case SPEED_100 + DUPLEX_HALF:
7277 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7278 break;
7279 case SPEED_100 + DUPLEX_FULL:
7280 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7281 break;
7282 case SPEED_1000 + DUPLEX_FULL:
7283 mac->autoneg = 1;
7284 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7285 break;
7286 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7287 default:
14ad2513 7288 goto err_inval;
9d5c8243 7289 }
8376dad0
JB		 7290
7291 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7292 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7293
9d5c8243 7294 return 0;
14ad2513
DD		 7295
7296err_inval:
7297 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7298 return -EINVAL;
9d5c8243
AK		 7299}
7300
749ab2cd
YZ		 7301static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7302 bool runtime)
9d5c8243
AK		 7303{
7304 struct net_device *netdev = pci_get_drvdata(pdev);
7305 struct igb_adapter *adapter = netdev_priv(netdev);
7306 struct e1000_hw *hw = &adapter->hw;
2d064c06 7307 u32 ctrl, rctl, status;
749ab2cd 7308 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7309#ifdef CONFIG_PM
7310 int retval = 0;
7311#endif
7312
7313 netif_device_detach(netdev);
7314
a88f10ec 7315 if (netif_running(netdev))
749ab2cd 7316 __igb_close(netdev, true);
a88f10ec 7317
047e0030 7318 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7319
7320#ifdef CONFIG_PM
7321 retval = pci_save_state(pdev);
7322 if (retval)
7323 return retval;
7324#endif
7325
7326 status = rd32(E1000_STATUS);
7327 if (status & E1000_STATUS_LU)
7328 wufc &= ~E1000_WUFC_LNKC;
7329
7330 if (wufc) {
7331 igb_setup_rctl(adapter);
ff41f8dc 7332 igb_set_rx_mode(netdev);
9d5c8243
AK		 7333
7334 /* turn on all-multi mode if wake on multicast is enabled */
7335 if (wufc & E1000_WUFC_MC) {
7336 rctl = rd32(E1000_RCTL);
7337 rctl |= E1000_RCTL_MPE;
7338 wr32(E1000_RCTL, rctl);
7339 }
7340
7341 ctrl = rd32(E1000_CTRL);
7342 /* advertise wake from D3Cold */
7343 #define E1000_CTRL_ADVD3WUC 0x00100000
7344 /* phy power management enable */
7345 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7346 ctrl |= E1000_CTRL_ADVD3WUC;
7347 wr32(E1000_CTRL, ctrl);
7348
9d5c8243 7349 /* Allow time for pending master requests to run */
330a6d6a 7350 igb_disable_pcie_master(hw);
9d5c8243
AK		 7351
7352 wr32(E1000_WUC, E1000_WUC_PME_EN);
7353 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7354 } else {
7355 wr32(E1000_WUC, 0);
7356 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7357 }
7358
3fe7c4c9
RW		 7359 *enable_wake = wufc || adapter->en_mng_pt;
7360 if (!*enable_wake)
88a268c1
NN		 7361 igb_power_down_link(adapter);
7362 else
7363 igb_power_up_link(adapter);
9d5c8243
AK		 7364
7365 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7366 * would have already happened in close and is redundant.
7367 */
9d5c8243
AK		 7368 igb_release_hw_control(adapter);
7369
7370 pci_disable_device(pdev);
7371
9d5c8243
AK		 7372 return 0;
7373}
7374
7375#ifdef CONFIG_PM
d9dd966d 7376#ifdef CONFIG_PM_SLEEP
749ab2cd 7377static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7378{
7379 int retval;
7380 bool wake;
749ab2cd 7381 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7382
749ab2cd 7383 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7384 if (retval)
7385 return retval;
7386
7387 if (wake) {
7388 pci_prepare_to_sleep(pdev);
7389 } else {
7390 pci_wake_from_d3(pdev, false);
7391 pci_set_power_state(pdev, PCI_D3hot);
7392 }
7393
7394 return 0;
7395}
d9dd966d 7396#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7397
749ab2cd 7398static int igb_resume(struct device *dev)
9d5c8243 7399{
749ab2cd 7400 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7401 struct net_device *netdev = pci_get_drvdata(pdev);
7402 struct igb_adapter *adapter = netdev_priv(netdev);
7403 struct e1000_hw *hw = &adapter->hw;
7404 u32 err;
7405
7406 pci_set_power_state(pdev, PCI_D0);
7407 pci_restore_state(pdev);
b94f2d77 7408 pci_save_state(pdev);
42bfd33a 7409
17a402a0
CW		 7410 if (!pci_device_is_present(pdev))
7411 return -ENODEV;
aed5dec3 7412 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7413 if (err) {
7414 dev_err(&pdev->dev,
7415 "igb: Cannot enable PCI device from suspend\n");
7416 return err;
7417 }
7418 pci_set_master(pdev);
7419
7420 pci_enable_wake(pdev, PCI_D3hot, 0);
7421 pci_enable_wake(pdev, PCI_D3cold, 0);
7422
53c7d064 7423 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec 7424 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3eb14ea8 7425 rtnl_unlock();
a88f10ec 7426 return -ENOMEM;
9d5c8243
AK		 7427 }
7428
9d5c8243 7429 igb_reset(adapter);
a8564f03
AD		 7430
7431 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7432 * driver.
7433 */
a8564f03
AD		 7434 igb_get_hw_control(adapter);
7435
9d5c8243
AK		 7436 wr32(E1000_WUS, ~0);
7437
749ab2cd 7438 if (netdev->flags & IFF_UP) {
0c2cc02e 7439 rtnl_lock();
749ab2cd 7440 err = __igb_open(netdev, true);
0c2cc02e 7441 rtnl_unlock();
a88f10ec
AD		 7442 if (err)
7443 return err;
7444 }
9d5c8243
AK		 7445
7446 netif_device_attach(netdev);
749ab2cd
YZ		 7447 return 0;
7448}
7449
749ab2cd
YZ		 7450static int igb_runtime_idle(struct device *dev)
7451{
7452 struct pci_dev *pdev = to_pci_dev(dev);
7453 struct net_device *netdev = pci_get_drvdata(pdev);
7454 struct igb_adapter *adapter = netdev_priv(netdev);
7455
7456 if (!igb_has_link(adapter))
7457 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7458
7459 return -EBUSY;
7460}
7461
7462static int igb_runtime_suspend(struct device *dev)
7463{
7464 struct pci_dev *pdev = to_pci_dev(dev);
7465 int retval;
7466 bool wake;
7467
7468 retval = __igb_shutdown(pdev, &wake, 1);
7469 if (retval)
7470 return retval;
7471
7472 if (wake) {
7473 pci_prepare_to_sleep(pdev);
7474 } else {
7475 pci_wake_from_d3(pdev, false);
7476 pci_set_power_state(pdev, PCI_D3hot);
7477 }
9d5c8243 7478
9d5c8243
AK		 7479 return 0;
7480}
749ab2cd
YZ		 7481
7482static int igb_runtime_resume(struct device *dev)
7483{
7484 return igb_resume(dev);
7485}
d61c81cb 7486#endif /* CONFIG_PM */
9d5c8243
AK		 7487
7488static void igb_shutdown(struct pci_dev *pdev)
7489{
3fe7c4c9
RW		 7490 bool wake;
7491
749ab2cd 7492 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7493
7494 if (system_state == SYSTEM_POWER_OFF) {
7495 pci_wake_from_d3(pdev, wake);
7496 pci_set_power_state(pdev, PCI_D3hot);
7497 }
9d5c8243
AK		 7498}
7499
fa44f2f1
GR		 7500#ifdef CONFIG_PCI_IOV
7501static int igb_sriov_reinit(struct pci_dev *dev)
7502{
7503 struct net_device *netdev = pci_get_drvdata(dev);
7504 struct igb_adapter *adapter = netdev_priv(netdev);
7505 struct pci_dev *pdev = adapter->pdev;
7506
7507 rtnl_lock();
7508
7509 if (netif_running(netdev))
7510 igb_close(netdev);
76252723
SA		 7511 else
7512 igb_reset(adapter);
fa44f2f1
GR		 7513
7514 igb_clear_interrupt_scheme(adapter);
7515
7516 igb_init_queue_configuration(adapter);
7517
7518 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7519 rtnl_unlock();
fa44f2f1
GR		 7520 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7521 return -ENOMEM;
7522 }
7523
7524 if (netif_running(netdev))
7525 igb_open(netdev);
7526
7527 rtnl_unlock();
7528
7529 return 0;
7530}
7531
7532static int igb_pci_disable_sriov(struct pci_dev *dev)
7533{
7534 int err = igb_disable_sriov(dev);
7535
7536 if (!err)
7537 err = igb_sriov_reinit(dev);
7538
7539 return err;
7540}
7541
7542static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7543{
7544 int err = igb_enable_sriov(dev, num_vfs);
7545
7546 if (err)
7547 goto out;
7548
7549 err = igb_sriov_reinit(dev);
7550 if (!err)
7551 return num_vfs;
7552
7553out:
7554 return err;
7555}
7556
7557#endif
7558static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7559{
7560#ifdef CONFIG_PCI_IOV
7561 if (num_vfs == 0)
7562 return igb_pci_disable_sriov(dev);
7563 else
7564 return igb_pci_enable_sriov(dev, num_vfs);
7565#endif
7566 return 0;
7567}
7568
9d5c8243 7569#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7570/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7571 * without having to re-enable interrupts. It's not called while
7572 * the interrupt routine is executing.
7573 */
7574static void igb_netpoll(struct net_device *netdev)
7575{
7576 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7577 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7578 struct igb_q_vector *q_vector;
9d5c8243 7579 int i;
9d5c8243 7580
047e0030 7581 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7582 q_vector = adapter->q_vector[i];
cd14ef54 7583 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7584 wr32(E1000_EIMC, q_vector->eims_value);
7585 else
7586 igb_irq_disable(adapter);
047e0030 7587 napi_schedule(&q_vector->napi);
eebbbdba 7588 }
9d5c8243
AK		 7589}
7590#endif /* CONFIG_NET_POLL_CONTROLLER */
7591
7592/**
b980ac18
JK		 7593 * igb_io_error_detected - called when PCI error is detected
7594 * @pdev: Pointer to PCI device
7595 * @state: The current pci connection state
9d5c8243 7596 *
b980ac18
JK		 7597 * This function is called after a PCI bus error affecting
7598 * this device has been detected.
7599 **/
9d5c8243
AK		 7600static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7601 pci_channel_state_t state)
7602{
7603 struct net_device *netdev = pci_get_drvdata(pdev);
7604 struct igb_adapter *adapter = netdev_priv(netdev);
7605
7606 netif_device_detach(netdev);
7607
59ed6eec
AD		 7608 if (state == pci_channel_io_perm_failure)
7609 return PCI_ERS_RESULT_DISCONNECT;
7610
9d5c8243
AK		 7611 if (netif_running(netdev))
7612 igb_down(adapter);
7613 pci_disable_device(pdev);
7614
7615 /* Request a slot slot reset. */
7616 return PCI_ERS_RESULT_NEED_RESET;
7617}
7618
7619/**
b980ac18
JK		 7620 * igb_io_slot_reset - called after the pci bus has been reset.
7621 * @pdev: Pointer to PCI device
9d5c8243 7622 *
b980ac18
JK		 7623 * Restart the card from scratch, as if from a cold-boot. Implementation
7624 * resembles the first-half of the igb_resume routine.
7625 **/
9d5c8243
AK		 7626static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7627{
7628 struct net_device *netdev = pci_get_drvdata(pdev);
7629 struct igb_adapter *adapter = netdev_priv(netdev);
7630 struct e1000_hw *hw = &adapter->hw;
40a914fa 7631 pci_ers_result_t result;
42bfd33a 7632 int err;
9d5c8243 7633
aed5dec3 7634 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7635 dev_err(&pdev->dev,
7636 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7637 result = PCI_ERS_RESULT_DISCONNECT;
7638 } else {
7639 pci_set_master(pdev);
7640 pci_restore_state(pdev);
b94f2d77 7641 pci_save_state(pdev);
9d5c8243 7642
40a914fa
AD		 7643 pci_enable_wake(pdev, PCI_D3hot, 0);
7644 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7645
40a914fa
AD		 7646 igb_reset(adapter);
7647 wr32(E1000_WUS, ~0);
7648 result = PCI_ERS_RESULT_RECOVERED;
7649 }
9d5c8243 7650
ea943d41
JK		 7651 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7652 if (err) {
b980ac18
JK		 7653 dev_err(&pdev->dev,
7654 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7655 err);
ea943d41
JK		 7656 /* non-fatal, continue */
7657 }
40a914fa
AD		 7658
7659 return result;
9d5c8243
AK		 7660}
7661
7662/**
b980ac18
JK		 7663 * igb_io_resume - called when traffic can start flowing again.
7664 * @pdev: Pointer to PCI device
9d5c8243 7665 *
b980ac18
JK		 7666 * This callback is called when the error recovery driver tells us that
7667 * its OK to resume normal operation. Implementation resembles the
7668 * second-half of the igb_resume routine.
9d5c8243
AK		 7669 */
7670static void igb_io_resume(struct pci_dev *pdev)
7671{
7672 struct net_device *netdev = pci_get_drvdata(pdev);
7673 struct igb_adapter *adapter = netdev_priv(netdev);
7674
9d5c8243
AK		 7675 if (netif_running(netdev)) {
7676 if (igb_up(adapter)) {
7677 dev_err(&pdev->dev, "igb_up failed after reset\n");
7678 return;
7679 }
7680 }
7681
7682 netif_device_attach(netdev);
7683
7684 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7685 * driver.
7686 */
9d5c8243 7687 igb_get_hw_control(adapter);
9d5c8243
AK		 7688}
7689
26ad9178 7690static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7691 u8 qsel)
26ad9178
AD		 7692{
7693 u32 rar_low, rar_high;
7694 struct e1000_hw *hw = &adapter->hw;
7695
7696 /* HW expects these in little endian so we reverse the byte order
7697 * from network order (big endian) to little endian
7698 */
7699 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7700 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7701 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7702
7703 /* Indicate to hardware the Address is Valid. */
7704 rar_high |= E1000_RAH_AV;
7705
7706 if (hw->mac.type == e1000_82575)
7707 rar_high |= E1000_RAH_POOL_1 * qsel;
7708 else
7709 rar_high |= E1000_RAH_POOL_1 << qsel;
7710
7711 wr32(E1000_RAL(index), rar_low);
7712 wrfl();
7713 wr32(E1000_RAH(index), rar_high);
7714 wrfl();
7715}
7716
4ae196df 7717static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7718 int vf, unsigned char *mac_addr)
4ae196df
AD		 7719{
7720 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7721 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7722 * towards the first, as a result a collision should not be possible
7723 */
ff41f8dc 7724 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7725
37680117 7726 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7727
26ad9178 7728 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7729
7730 return 0;
7731}
7732
8151d294
WM		 7733static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7734{
7735 struct igb_adapter *adapter = netdev_priv(netdev);
7736 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7737 return -EINVAL;
7738 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7739 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7740 dev_info(&adapter->pdev->dev,
7741 "Reload the VF driver to make this change effective.");
8151d294 7742 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7743 dev_warn(&adapter->pdev->dev,
7744 "The VF MAC address has been set, but the PF device is not up.\n");
7745 dev_warn(&adapter->pdev->dev,
7746 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7747 }
7748 return igb_set_vf_mac(adapter, vf, mac);
7749}
7750
17dc566c
LL		 7751static int igb_link_mbps(int internal_link_speed)
7752{
7753 switch (internal_link_speed) {
7754 case SPEED_100:
7755 return 100;
7756 case SPEED_1000:
7757 return 1000;
7758 default:
7759 return 0;
7760 }
7761}
7762
7763static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7764 int link_speed)
7765{
7766 int rf_dec, rf_int;
7767 u32 bcnrc_val;
7768
7769 if (tx_rate != 0) {
7770 /* Calculate the rate factor values to set */
7771 rf_int = link_speed / tx_rate;
7772 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7773 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7774 tx_rate;
17dc566c
LL		 7775
7776 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7777 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7778 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7779 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7780 } else {
7781 bcnrc_val = 0;
7782 }
7783
7784 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7785 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7786 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7787 */
7788 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7789 wr32(E1000_RTTBCNRC, bcnrc_val);
7790}
7791
7792static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7793{
7794 int actual_link_speed, i;
7795 bool reset_rate = false;
7796
7797 /* VF TX rate limit was not set or not supported */
7798 if ((adapter->vf_rate_link_speed == 0) ||
7799 (adapter->hw.mac.type != e1000_82576))
7800 return;
7801
7802 actual_link_speed = igb_link_mbps(adapter->link_speed);
7803 if (actual_link_speed != adapter->vf_rate_link_speed) {
7804 reset_rate = true;
7805 adapter->vf_rate_link_speed = 0;
7806 dev_info(&adapter->pdev->dev,
b980ac18 7807 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7808 }
7809
7810 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7811 if (reset_rate)
7812 adapter->vf_data[i].tx_rate = 0;
7813
7814 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7815 adapter->vf_data[i].tx_rate,
7816 actual_link_speed);
17dc566c
LL		 7817 }
7818}
7819
ed616689
SC		 7820static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7821 int min_tx_rate, int max_tx_rate)
8151d294 7822{
17dc566c
LL		 7823 struct igb_adapter *adapter = netdev_priv(netdev);
7824 struct e1000_hw *hw = &adapter->hw;
7825 int actual_link_speed;
7826
7827 if (hw->mac.type != e1000_82576)
7828 return -EOPNOTSUPP;
7829
ed616689
SC		 7830 if (min_tx_rate)
7831 return -EINVAL;
7832
17dc566c
LL		 7833 actual_link_speed = igb_link_mbps(adapter->link_speed);
7834 if ((vf >= adapter->vfs_allocated_count) ||
7835 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7836 (max_tx_rate < 0) ||
7837 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7838 return -EINVAL;
7839
7840 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7841 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7842 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7843
7844 return 0;
8151d294
WM		 7845}
7846
70ea4783
LL		 7847static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7848 bool setting)
7849{
7850 struct igb_adapter *adapter = netdev_priv(netdev);
7851 struct e1000_hw *hw = &adapter->hw;
7852 u32 reg_val, reg_offset;
7853
7854 if (!adapter->vfs_allocated_count)
7855 return -EOPNOTSUPP;
7856
7857 if (vf >= adapter->vfs_allocated_count)
7858 return -EINVAL;
7859
7860 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7861 reg_val = rd32(reg_offset);
7862 if (setting)
7863 reg_val |= ((1 << vf) |
7864 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7865 else
7866 reg_val &= ~((1 << vf) |
7867 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7868 wr32(reg_offset, reg_val);
7869
7870 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7871 return 0;
70ea4783
LL		 7872}
7873
8151d294
WM		 7874static int igb_ndo_get_vf_config(struct net_device *netdev,
7875 int vf, struct ifla_vf_info *ivi)
7876{
7877 struct igb_adapter *adapter = netdev_priv(netdev);
7878 if (vf >= adapter->vfs_allocated_count)
7879 return -EINVAL;
7880 ivi->vf = vf;
7881 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7882 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7883 ivi->min_tx_rate = 0;
8151d294
WM		 7884 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7885 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7886 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7887 return 0;
7888}
7889
4ae196df
AD		 7890static void igb_vmm_control(struct igb_adapter *adapter)
7891{
7892 struct e1000_hw *hw = &adapter->hw;
10d8e907 7893 u32 reg;
4ae196df 7894
52a1dd4d
AD		 7895 switch (hw->mac.type) {
7896 case e1000_82575:
f96a8a0b
CW		 7897 case e1000_i210:
7898 case e1000_i211:
ceb5f13b 7899 case e1000_i354:
52a1dd4d
AD		 7900 default:
7901 /* replication is not supported for 82575 */
4ae196df 7902 return;
52a1dd4d
AD		 7903 case e1000_82576:
7904 /* notify HW that the MAC is adding vlan tags */
7905 reg = rd32(E1000_DTXCTL);
7906 reg |= E1000_DTXCTL_VLAN_ADDED;
7907 wr32(E1000_DTXCTL, reg);
b26141d4 7908 /* Fall through */
52a1dd4d
AD		 7909 case e1000_82580:
7910 /* enable replication vlan tag stripping */
7911 reg = rd32(E1000_RPLOLR);
7912 reg |= E1000_RPLOLR_STRVLAN;
7913 wr32(E1000_RPLOLR, reg);
b26141d4 7914 /* Fall through */
d2ba2ed8
AD		 7915 case e1000_i350:
7916 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7917 break;
7918 }
10d8e907 7919
d4960307
AD		 7920 if (adapter->vfs_allocated_count) {
7921 igb_vmdq_set_loopback_pf(hw, true);
7922 igb_vmdq_set_replication_pf(hw, true);
13800469 7923 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7924 adapter->vfs_allocated_count);
d4960307
AD		 7925 } else {
7926 igb_vmdq_set_loopback_pf(hw, false);
7927 igb_vmdq_set_replication_pf(hw, false);
7928 }
4ae196df
AD		 7929}
7930
b6e0c419
CW		 7931static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7932{
7933 struct e1000_hw *hw = &adapter->hw;
7934 u32 dmac_thr;
7935 u16 hwm;
7936
7937 if (hw->mac.type > e1000_82580) {
7938 if (adapter->flags & IGB_FLAG_DMAC) {
7939 u32 reg;
7940
7941 /* force threshold to 0. */
7942 wr32(E1000_DMCTXTH, 0);
7943
b980ac18 7944 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7945 * than the Rx threshold. Set hwm to PBA - max frame
7946 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7947 */
e8c626e9
MV		 7948 hwm = 64 * pba - adapter->max_frame_size / 16;
7949 if (hwm < 64 * (pba - 6))
7950 hwm = 64 * (pba - 6);
7951 reg = rd32(E1000_FCRTC);
7952 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7953 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7954 & E1000_FCRTC_RTH_COAL_MASK);
7955 wr32(E1000_FCRTC, reg);
7956
b980ac18 7957 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7958 * frame size, capping it at PBA - 10KB.
7959 */
7960 dmac_thr = pba - adapter->max_frame_size / 512;
7961 if (dmac_thr < pba - 10)
7962 dmac_thr = pba - 10;
b6e0c419
CW		 7963 reg = rd32(E1000_DMACR);
7964 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7965 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7966 & E1000_DMACR_DMACTHR_MASK);
7967
7968 /* transition to L0x or L1 if available..*/
7969 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7970
7971 /* watchdog timer= +-1000 usec in 32usec intervals */
7972 reg |= (1000 >> 5);
0c02dd98
MV		 7973
7974 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7975 if (hw->mac.type != e1000_i354)
7976 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7977
b6e0c419
CW		 7978 wr32(E1000_DMACR, reg);
7979
b980ac18 7980 /* no lower threshold to disable
b6e0c419
CW		 7981 * coalescing(smart fifb)-UTRESH=0
7982 */
7983 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7984
7985 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7986
7987 wr32(E1000_DMCTLX, reg);
7988
b980ac18 7989 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7990 * DMA coal
7991 */
7992 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7993 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7994
b980ac18 7995 /* make low power state decision controlled
b6e0c419
CW		 7996 * by DMA coal
7997 */
7998 reg = rd32(E1000_PCIEMISC);
7999 reg &= ~E1000_PCIEMISC_LX_DECISION;
8000 wr32(E1000_PCIEMISC, reg);
8001 } /* endif adapter->dmac is not disabled */
8002 } else if (hw->mac.type == e1000_82580) {
8003 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8004
b6e0c419
CW		 8005 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8006 wr32(E1000_DMACR, 0);
8007 }
8008}
8009
b980ac18
JK		 8010/**
8011 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8012 * @hw: pointer to hardware structure
8013 * @byte_offset: byte offset to read
8014 * @dev_addr: device address
8015 * @data: value read
8016 *
8017 * Performs byte read operation over I2C interface at
8018 * a specified device address.
b980ac18 8019 **/
441fc6fd 8020s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8021 u8 dev_addr, u8 *data)
441fc6fd
CW		 8022{
8023 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8024 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8025 s32 status;
8026 u16 swfw_mask = 0;
8027
8028 if (!this_client)
8029 return E1000_ERR_I2C;
8030
8031 swfw_mask = E1000_SWFW_PHY0_SM;
8032
23d87824 8033 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8034 return E1000_ERR_SWFW_SYNC;
8035
8036 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8037 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8038
8039 if (status < 0)
8040 return E1000_ERR_I2C;
8041 else {
8042 *data = status;
23d87824 8043 return 0;
441fc6fd
CW		 8044 }
8045}
8046
b980ac18
JK		 8047/**
8048 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8049 * @hw: pointer to hardware structure
8050 * @byte_offset: byte offset to write
8051 * @dev_addr: device address
8052 * @data: value to write
8053 *
8054 * Performs byte write operation over I2C interface at
8055 * a specified device address.
b980ac18 8056 **/
441fc6fd 8057s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8058 u8 dev_addr, u8 data)
441fc6fd
CW		 8059{
8060 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8061 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8062 s32 status;
8063 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8064
8065 if (!this_client)
8066 return E1000_ERR_I2C;
8067
23d87824 8068 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8069 return E1000_ERR_SWFW_SYNC;
8070 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8071 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8072
8073 if (status)
8074 return E1000_ERR_I2C;
8075 else
23d87824 8076 return 0;
441fc6fd
CW		 8077
8078}
907b7835
LMV		 8079
8080int igb_reinit_queues(struct igb_adapter *adapter)
8081{
8082 struct net_device *netdev = adapter->netdev;
8083 struct pci_dev *pdev = adapter->pdev;
8084 int err = 0;
8085
8086 if (netif_running(netdev))
8087 igb_close(netdev);
8088
02ef6e1d 8089 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8090
8091 if (igb_init_interrupt_scheme(adapter, true)) {
8092 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8093 return -ENOMEM;
8094 }
8095
8096 if (netif_running(netdev))
8097 err = igb_open(netdev);
8098
8099 return err;
8100}
9d5c8243 8101/* igb_main.c */
Linux kernel - Deliverables
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