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igb: Add support for VLAN promiscuous with SR-IOV and NTUPLE
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
6fb46902
TF		 60#define MIN 3
61#define BUILD 0
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
32b3e08f 154static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 184#endif
9d5c8243 185
9d5c8243 186#ifdef CONFIG_PM
d9dd966d 187#ifdef CONFIG_PM_SLEEP
749ab2cd 188static int igb_suspend(struct device *);
d9dd966d 189#endif
749ab2cd 190static int igb_resume(struct device *);
749ab2cd
YZ		 191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
52285b76 949 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 950
047e0030 951 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 952 igb_msix_other, 0, netdev->name, adapter);
047e0030 953 if (err)
52285b76 954 goto err_out;
047e0030
AD		 955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
52285b76
SA		 959 vector++;
960
7b06a690 961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 962
0ba82994 963 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
047e0030 967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
047e0030 970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 971 q_vector->rx.ring->queue_index);
9d5c8243 972 else
047e0030
AD		 973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
9d5c8243 975 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
9d5c8243 978 if (err)
52285b76 979 goto err_free;
9d5c8243
AK		 980 }
981
9d5c8243
AK		 982 igb_configure_msix(adapter);
983 return 0;
52285b76
SA		 984
985err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994err_out:
9d5c8243
AK		 995 return err;
996}
997
5536d210 998/**
b980ac18
JK		 999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
5536d210 1002 *
02ef6e1d 1003 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
02ef6e1d
CW		 1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
17a402a0
CW		 1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
cb06d102
CP		 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
5536d210
AD		 1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
2439fc4d 1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1041
5536d210
AD		 1042 netif_napi_del(&q_vector->napi);
1043
02ef6e1d
CW		 1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
cd14ef54 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1051 pci_disable_msix(adapter->pdev);
cd14ef54 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1053 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1057}
1058
047e0030 1059/**
b980ac18
JK		 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
047e0030 1062 *
b980ac18
JK		 1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
047e0030
AD		 1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
5536d210
AD		 1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
047e0030 1073 adapter->num_q_vectors = 0;
5536d210 1074
02ef6e1d
CW		 1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
5536d210 1077 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1078 }
047e0030
AD		 1079}
1080
1081/**
b980ac18
JK		 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
047e0030 1084 *
b980ac18
JK		 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
047e0030
AD		 1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
047e0030
AD		 1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
9d5c8243
AK		 1093
1094/**
b980ac18
JK		 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
9d5c8243 1098 *
b980ac18
JK		 1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
9d5c8243 1101 **/
53c7d064 1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1103{
1104 int err;
1105 int numvecs, i;
1106
53c7d064
SA		 1107 if (!msix)
1108 goto msi_only;
cd14ef54 1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1110
83b7180d 1111 /* Number of supported queues. */
a99955fc 1112 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1117
b980ac18 1118 /* start with one vector for every Rx queue */
047e0030
AD		 1119 numvecs = adapter->num_rx_queues;
1120
b980ac18 1121 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
047e0030
AD		 1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
9d5c8243
AK		 1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
479d02df
AG		 1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
0c2cc02e 1138 return;
9d5c8243
AK		 1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
b709323d 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1156 wrfl();
2a3abf6d
AD		 1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
4fc82adf 1161 adapter->vfs_allocated_count = 0;
a99955fc 1162 adapter->rss_queues = 1;
4fc82adf 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1164 adapter->num_rx_queues = 1;
661086df 1165 adapter->num_tx_queues = 1;
047e0030 1166 adapter->num_q_vectors = 1;
9d5c8243 1167 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1168 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1169}
1170
5536d210
AD		 1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
047e0030 1178/**
b980ac18
JK		 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
047e0030 1187 *
b980ac18 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1189 **/
5536d210
AD		 1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
047e0030
AD		 1194{
1195 struct igb_q_vector *q_vector;
5536d210
AD		 1196 struct igb_ring *ring;
1197 int ring_count, size;
047e0030 1198
5536d210
AD		 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
02ef6e1d 1208 q_vector = adapter->q_vector[v_idx];
72ddef05 1209 if (!q_vector) {
02ef6e1d 1210 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
c0a06ee1 1215 memset(q_vector, 0, size);
72ddef05 1216 }
5536d210
AD		 1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
7b06a690 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
4e227667
AD		 1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
5536d210
AD		 1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
827da44c
JS		 1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
5536d210
AD		 1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
047e0030 1276 }
81c2fc22 1277
5536d210
AD		 1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
047e0030 1282
5536d210
AD		 1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
047e0030 1285
5536d210
AD		 1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
047e0030 1288
5536d210
AD		 1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1292
e52c0f96 1293 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1294 * have the tag byte-swapped.
b980ac18 1295 */
5536d210
AD		 1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1298
5536d210
AD		 1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
827da44c
JS		 1303 u64_stats_init(&ring->rx_syncp);
1304
5536d210
AD		 1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
047e0030
AD		 1310}
1311
5536d210 1312
047e0030 1313/**
b980ac18
JK		 1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
047e0030 1316 *
b980ac18
JK		 1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
047e0030 1319 **/
5536d210 1320static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1321{
5536d210
AD		 1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
047e0030 1327
5536d210
AD		 1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
047e0030 1332
5536d210
AD		 1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
047e0030 1339 }
047e0030 1340 }
5536d210
AD		 1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1345
5536d210
AD		 1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
047e0030 1359 return 0;
5536d210
AD		 1360
1361err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
047e0030
AD		 1370}
1371
1372/**
b980ac18
JK		 1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
047e0030 1376 *
b980ac18 1377 * This function initializes the interrupts and allocates all of the queues.
047e0030 1378 **/
53c7d064 1379static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1380{
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
53c7d064 1384 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
5536d210 1392 igb_cache_ring_register(adapter);
047e0030
AD		 1393
1394 return 0;
5536d210 1395
047e0030
AD		 1396err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399}
1400
9d5c8243 1401/**
b980ac18
JK		 1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
9d5c8243 1404 *
b980ac18
JK		 1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
9d5c8243
AK		 1407 **/
1408static int igb_request_irq(struct igb_adapter *adapter)
1409{
1410 struct net_device *netdev = adapter->netdev;
047e0030 1411 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1412 int err = 0;
1413
cd14ef54 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1415 err = igb_request_msix(adapter);
844290e5 1416 if (!err)
9d5c8243 1417 goto request_done;
9d5c8243 1418 /* fall back to MSI */
5536d210
AD		 1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
53c7d064 1421
047e0030 1422 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
047e0030 1425 goto request_done;
53c7d064 1426
047e0030
AD		 1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
53c7d064 1429 igb_configure(adapter);
9d5c8243 1430 }
844290e5 1431
c74d588e
AD		 1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
7dfc16fa 1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1436 netdev->name, adapter);
9d5c8243
AK		 1437 if (!err)
1438 goto request_done;
047e0030 1439
9d5c8243
AK		 1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
7dfc16fa 1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1443 }
1444
c74d588e 1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1446 netdev->name, adapter);
9d5c8243 1447
6cb5e577 1448 if (err)
c74d588e 1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1450 err);
9d5c8243
AK		 1451
1452request_done:
1453 return err;
1454}
1455
1456static void igb_free_irq(struct igb_adapter *adapter)
1457{
cd14ef54 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1459 int vector = 0, i;
1460
047e0030 1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1462
0d1ae7f4 1463 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1464 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1465 adapter->q_vector[i]);
047e0030
AD		 1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1468 }
9d5c8243
AK		 1469}
1470
1471/**
b980ac18
JK		 1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
9d5c8243
AK		 1474 **/
1475static void igb_irq_disable(struct igb_adapter *adapter)
1476{
1477 struct e1000_hw *hw = &adapter->hw;
1478
b980ac18 1479 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
cd14ef54 1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1484 u32 regval = rd32(E1000_EIAM);
9005df38 1485
2dfd1212
AD		 1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1490 }
844290e5
PW		 1491
1492 wr32(E1000_IAM, 0);
9d5c8243
AK		 1493 wr32(E1000_IMC, ~0);
1494 wrfl();
cd14ef54 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1496 int i;
9005df38 1497
81a61859
ET		 1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
9d5c8243
AK		 1503}
1504
1505/**
b980ac18
JK		 1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
9d5c8243
AK		 1508 **/
1509static void igb_irq_enable(struct igb_adapter *adapter)
1510{
1511 struct e1000_hw *hw = &adapter->hw;
1512
cd14ef54 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1515 u32 regval = rd32(E1000_EIAC);
9005df38 1516
2dfd1212
AD		 1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1521 if (adapter->vfs_allocated_count) {
4ae196df 1522 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
844290e5 1526 } else {
55cac248
AD		 1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
844290e5 1531 }
9d5c8243
AK		 1532}
1533
1534static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535{
51466239 1536 struct e1000_hw *hw = &adapter->hw;
8b77c6b2 1537 u16 pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
8b77c6b2 1543 igb_vfta_set(hw, vid, pf_id, true, true);
51466239
AD		 1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
b2cb09b1 1551 !test_bit(old_vid, adapter->active_vlans)) {
51466239 1552 /* remove VID from filter table */
8b77c6b2 1553 igb_vfta_set(hw, vid, pf_id, false, true);
9d5c8243
AK		 1554 }
1555}
1556
1557/**
b980ac18
JK		 1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
9d5c8243 1560 *
b980ac18
JK		 1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
9d5c8243
AK		 1564 **/
1565static void igb_release_hw_control(struct igb_adapter *adapter)
1566{
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574}
1575
9d5c8243 1576/**
b980ac18
JK		 1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
9d5c8243 1579 *
b980ac18
JK		 1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
9d5c8243
AK		 1583 **/
1584static void igb_get_hw_control(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593}
1594
9d5c8243 1595/**
b980ac18
JK		 1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
9d5c8243
AK		 1598 **/
1599static void igb_configure(struct igb_adapter *adapter)
1600{
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
ff41f8dc 1605 igb_set_rx_mode(netdev);
9d5c8243
AK		 1606
1607 igb_restore_vlan(adapter);
9d5c8243 1608
85b430b4 1609 igb_setup_tctl(adapter);
06cf2666 1610 igb_setup_mrqc(adapter);
9d5c8243 1611 igb_setup_rctl(adapter);
85b430b4
AD		 1612
1613 igb_configure_tx(adapter);
9d5c8243 1614 igb_configure_rx(adapter);
662d7205
AD		 1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
c493ea45 1618 /* call igb_desc_unused which always leaves
9d5c8243 1619 * at least 1 descriptor unused to make sure
b980ac18
JK		 1620 * next_to_use != next_to_clean
1621 */
9d5c8243 1622 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1623 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1625 }
9d5c8243
AK		 1626}
1627
88a268c1 1628/**
b980ac18
JK		 1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
88a268c1
NN		 1631 **/
1632void igb_power_up_link(struct igb_adapter *adapter)
1633{
76886596
AA		 1634 igb_reset_phy(&adapter->hw);
1635
88a268c1
NN		 1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1640
1641 igb_setup_link(&adapter->hw);
88a268c1
NN		 1642}
1643
1644/**
b980ac18
JK		 1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
88a268c1
NN		 1647 */
1648static void igb_power_down_link(struct igb_adapter *adapter)
1649{
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654}
9d5c8243 1655
56cec249
CW		 1656/**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660static void igb_check_swap_media(struct igb_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721}
1722
9d5c8243 1723/**
b980ac18
JK		 1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
9d5c8243 1726 **/
9d5c8243
AK		 1727int igb_up(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
0d1ae7f4
AD		 1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
cd14ef54 1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1741 igb_configure_msix(adapter);
feeb2721
AD		 1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
d4960307
AD		 1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1752
d4960307
AD		 1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
4cb9be7a
JB		 1757 netif_tx_start_all_queues(adapter->netdev);
1758
25568a53
AD		 1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
f4c01e96
CW		 1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
9d5c8243
AK		 1767 return 0;
1768}
1769
1770void igb_down(struct igb_adapter *adapter)
1771{
9d5c8243 1772 struct net_device *netdev = adapter->netdev;
330a6d6a 1773 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1778 * reschedule our watchdog timer
1779 */
9d5c8243
AK		 1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
f28ea083 1787 netif_carrier_off(netdev);
fd2ea0a7 1788 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
0d451e79 1796 usleep_range(10000, 11000);
9d5c8243 1797
41f149a2
CW		 1798 igb_irq_disable(adapter);
1799
aa9b8cc4
AA		 1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
41f149a2 1802 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
41f149a2 1807 }
9d5c8243 1808
9d5c8243
AK		 1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
04fe6358 1812 /* record the stats before reset*/
12dcd86b
ED		 1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
04fe6358 1816
9d5c8243
AK		 1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
3023682e
JK		 1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
16903caa
AD		 1822
1823 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1824 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1825
9d5c8243
AK		 1826 igb_clean_all_tx_rings(adapter);
1827 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1828#ifdef CONFIG_IGB_DCA
1829
1830 /* since we reset the hardware DCA settings were cleared */
1831 igb_setup_dca(adapter);
1832#endif
9d5c8243
AK		 1833}
1834
1835void igb_reinit_locked(struct igb_adapter *adapter)
1836{
1837 WARN_ON(in_interrupt());
1838 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1839 usleep_range(1000, 2000);
9d5c8243
AK		 1840 igb_down(adapter);
1841 igb_up(adapter);
1842 clear_bit(__IGB_RESETTING, &adapter->state);
1843}
1844
56cec249
CW		 1845/** igb_enable_mas - Media Autosense re-enable after swap
1846 *
1847 * @adapter: adapter struct
1848 **/
8cfb879d 1849static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1850{
1851 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1852 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1853
1854 /* configure for SerDes media detect */
8cfb879d
TF		 1855 if ((hw->phy.media_type == e1000_media_type_copper) &&
1856 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1857 connsw |= E1000_CONNSW_ENRGSRC;
1858 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1859 wr32(E1000_CONNSW, connsw);
1860 wrfl();
56cec249 1861 }
56cec249
CW		 1862}
1863
9d5c8243
AK		 1864void igb_reset(struct igb_adapter *adapter)
1865{
090b1795 1866 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1867 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1868 struct e1000_mac_info *mac = &hw->mac;
1869 struct e1000_fc_info *fc = &hw->fc;
45693bcb 1870 u32 pba, hwm;
9d5c8243
AK		 1871
1872 /* Repartition Pba for greater than 9k mtu
1873 * To take effect CTRL.RST is required.
1874 */
fa4dfae0 1875 switch (mac->type) {
d2ba2ed8 1876 case e1000_i350:
ceb5f13b 1877 case e1000_i354:
55cac248
AD		 1878 case e1000_82580:
1879 pba = rd32(E1000_RXPBS);
1880 pba = igb_rxpbs_adjust_82580(pba);
1881 break;
fa4dfae0 1882 case e1000_82576:
d249be54
AD		 1883 pba = rd32(E1000_RXPBS);
1884 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1885 break;
1886 case e1000_82575:
f96a8a0b
CW		 1887 case e1000_i210:
1888 case e1000_i211:
fa4dfae0
AD		 1889 default:
1890 pba = E1000_PBA_34K;
1891 break;
2d064c06 1892 }
9d5c8243 1893
45693bcb
AD		 1894 if (mac->type == e1000_82575) {
1895 u32 min_rx_space, min_tx_space, needed_tx_space;
1896
1897 /* write Rx PBA so that hardware can report correct Tx PBA */
9d5c8243
AK		 1898 wr32(E1000_PBA, pba);
1899
1900 /* To maintain wire speed transmits, the Tx FIFO should be
1901 * large enough to accommodate two full transmit packets,
1902 * rounded up to the next 1KB and expressed in KB. Likewise,
1903 * the Rx FIFO should be large enough to accommodate at least
1904 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1905 * expressed in KB.
1906 */
45693bcb
AD		 1907 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1908
1909 /* The Tx FIFO also stores 16 bytes of information about the Tx
1910 * but don't include Ethernet FCS because hardware appends it.
1911 * We only need to round down to the nearest 512 byte block
1912 * count since the value we care about is 2 frames, not 1.
b980ac18 1913 */
45693bcb
AD		 1914 min_tx_space = adapter->max_frame_size;
1915 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1916 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1917
1918 /* upper 16 bits has Tx packet buffer allocation size in KB */
1919 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
9d5c8243
AK		 1920
1921 /* If current Tx allocation is less than the min Tx FIFO size,
1922 * and the min Tx FIFO size is less than the current Rx FIFO
45693bcb 1923 * allocation, take space away from current Rx allocation.
b980ac18 1924 */
45693bcb
AD		 1925 if (needed_tx_space < pba) {
1926 pba -= needed_tx_space;
9d5c8243 1927
b980ac18
JK		 1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
9d5c8243
AK		 1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
45693bcb
AD		 1934
1935 /* adjust PBA for jumbo frames */
2d064c06 1936 wr32(E1000_PBA, pba);
9d5c8243 1937 }
9d5c8243 1938
45693bcb
AD		 1939 /* flow control settings
1940 * The high water mark must be low enough to fit one full frame
1941 * after transmitting the pause frame. As such we must have enough
1942 * space to allow for us to complete our current transmit and then
1943 * receive the frame that is in progress from the link partner.
1944 * Set it to:
1945 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
b980ac18 1946 */
45693bcb 1947 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
9d5c8243 1948
d48507fe 1949 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1950 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1951 fc->pause_time = 0xFFFF;
1952 fc->send_xon = 1;
0cce119a 1953 fc->current_mode = fc->requested_mode;
9d5c8243 1954
4ae196df
AD		 1955 /* disable receive for all VFs and wait one second */
1956 if (adapter->vfs_allocated_count) {
1957 int i;
9005df38 1958
4ae196df 1959 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1960 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1961
1962 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1963 igb_ping_all_vfs(adapter);
4ae196df
AD		 1964
1965 /* disable transmits and receives */
1966 wr32(E1000_VFRE, 0);
1967 wr32(E1000_VFTE, 0);
1968 }
1969
9d5c8243 1970 /* Allow time for pending master requests to run */
330a6d6a 1971 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1972 wr32(E1000_WUC, 0);
1973
56cec249
CW		 1974 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1975 /* need to resetup here after media swap */
1976 adapter->ei.get_invariants(hw);
1977 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1978 }
8cfb879d
TF		 1979 if ((mac->type == e1000_82575) &&
1980 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1981 igb_enable_mas(adapter);
56cec249 1982 }
330a6d6a 1983 if (hw->mac.ops.init_hw(hw))
090b1795 1984 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1985
b980ac18 1986 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1987 * control is off when forcing speed.
1988 */
1989 if (!hw->mac.autoneg)
1990 igb_force_mac_fc(hw);
1991
b6e0c419 1992 igb_init_dmac(adapter, pba);
e428893b
CW		 1993#ifdef CONFIG_IGB_HWMON
1994 /* Re-initialize the thermal sensor on i350 devices. */
1995 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1996 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1997 /* If present, re-initialize the external thermal sensor
1998 * interface.
1999 */
2000 if (adapter->ets)
2001 mac->ops.init_thermal_sensor_thresh(hw);
2002 }
2003 }
2004#endif
b936136d 2005 /* Re-establish EEE setting */
f4c01e96
CW		 2006 if (hw->phy.media_type == e1000_media_type_copper) {
2007 switch (mac->type) {
2008 case e1000_i350:
2009 case e1000_i210:
2010 case e1000_i211:
c4c112f1 2011 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2012 break;
2013 case e1000_i354:
c4c112f1 2014 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2015 break;
2016 default:
2017 break;
2018 }
2019 }
88a268c1
NN		 2020 if (!netif_running(adapter->netdev))
2021 igb_power_down_link(adapter);
2022
9d5c8243
AK		 2023 igb_update_mng_vlan(adapter);
2024
2025 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2026 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2027
1f6e8178
MV		 2028 /* Re-enable PTP, where applicable. */
2029 igb_ptp_reset(adapter);
1f6e8178 2030
330a6d6a 2031 igb_get_phy_info(hw);
9d5c8243
AK		 2032}
2033
c8f44aff
MM		 2034static netdev_features_t igb_fix_features(struct net_device *netdev,
2035 netdev_features_t features)
b2cb09b1 2036{
b980ac18
JK		 2037 /* Since there is no support for separate Rx/Tx vlan accel
2038 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2039 */
f646968f
PM		 2040 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2041 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2042 else
f646968f 2043 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2044
2045 return features;
2046}
2047
c8f44aff
MM		 2048static int igb_set_features(struct net_device *netdev,
2049 netdev_features_t features)
ac52caa3 2050{
c8f44aff 2051 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2052 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2053
f646968f 2054 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2055 igb_vlan_mode(netdev, features);
2056
16903caa 2057 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
89eaefb6
BG		 2058 return 0;
2059
2060 netdev->features = features;
2061
2062 if (netif_running(netdev))
2063 igb_reinit_locked(adapter);
2064 else
2065 igb_reset(adapter);
2066
ac52caa3
MM		 2067 return 0;
2068}
2069
2e5c6922 2070static const struct net_device_ops igb_netdev_ops = {
559e9c49 2071 .ndo_open = igb_open,
2e5c6922 2072 .ndo_stop = igb_close,
cd392f5c 2073 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2074 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2075 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2076 .ndo_set_mac_address = igb_set_mac,
2077 .ndo_change_mtu = igb_change_mtu,
2078 .ndo_do_ioctl = igb_ioctl,
2079 .ndo_tx_timeout = igb_tx_timeout,
2080 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2081 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2082 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2083 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2084 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2085 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2086 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2087 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2088#ifdef CONFIG_NET_POLL_CONTROLLER
2089 .ndo_poll_controller = igb_netpoll,
2090#endif
b2cb09b1
JP		 2091 .ndo_fix_features = igb_fix_features,
2092 .ndo_set_features = igb_set_features,
1abbc98a 2093 .ndo_features_check = passthru_features_check,
2e5c6922
SH		 2094};
2095
d67974f0
CW		 2096/**
2097 * igb_set_fw_version - Configure version string for ethtool
2098 * @adapter: adapter struct
d67974f0
CW		 2099 **/
2100void igb_set_fw_version(struct igb_adapter *adapter)
2101{
2102 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2103 struct e1000_fw_version fw;
2104
2105 igb_get_fw_version(hw, &fw);
2106
2107 switch (hw->mac.type) {
7dc98a62 2108 case e1000_i210:
0b1a6f2e 2109 case e1000_i211:
7dc98a62
CW		 2110 if (!(igb_get_flash_presence_i210(hw))) {
2111 snprintf(adapter->fw_version,
2112 sizeof(adapter->fw_version),
2113 "%2d.%2d-%d",
2114 fw.invm_major, fw.invm_minor,
2115 fw.invm_img_type);
2116 break;
2117 }
2118 /* fall through */
0b1a6f2e
CW		 2119 default:
2120 /* if option is rom valid, display its version too */
2121 if (fw.or_valid) {
2122 snprintf(adapter->fw_version,
2123 sizeof(adapter->fw_version),
2124 "%d.%d, 0x%08x, %d.%d.%d",
2125 fw.eep_major, fw.eep_minor, fw.etrack_id,
2126 fw.or_major, fw.or_build, fw.or_patch);
2127 /* no option rom */
7dc98a62 2128 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2129 snprintf(adapter->fw_version,
7dc98a62
CW		 2130 sizeof(adapter->fw_version),
2131 "%d.%d, 0x%08x",
2132 fw.eep_major, fw.eep_minor, fw.etrack_id);
2133 } else {
2134 snprintf(adapter->fw_version,
2135 sizeof(adapter->fw_version),
2136 "%d.%d.%d",
2137 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2138 }
2139 break;
d67974f0 2140 }
d67974f0
CW		 2141}
2142
56cec249
CW		 2143/**
2144 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2145 *
2146 * @adapter: adapter struct
2147 **/
2148static void igb_init_mas(struct igb_adapter *adapter)
2149{
2150 struct e1000_hw *hw = &adapter->hw;
2151 u16 eeprom_data;
2152
2153 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2154 switch (hw->bus.func) {
2155 case E1000_FUNC_0:
2156 if (eeprom_data & IGB_MAS_ENABLE_0) {
2157 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2158 netdev_info(adapter->netdev,
2159 "MAS: Enabling Media Autosense for port %d\n",
2160 hw->bus.func);
2161 }
2162 break;
2163 case E1000_FUNC_1:
2164 if (eeprom_data & IGB_MAS_ENABLE_1) {
2165 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2166 netdev_info(adapter->netdev,
2167 "MAS: Enabling Media Autosense for port %d\n",
2168 hw->bus.func);
2169 }
2170 break;
2171 case E1000_FUNC_2:
2172 if (eeprom_data & IGB_MAS_ENABLE_2) {
2173 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2174 netdev_info(adapter->netdev,
2175 "MAS: Enabling Media Autosense for port %d\n",
2176 hw->bus.func);
2177 }
2178 break;
2179 case E1000_FUNC_3:
2180 if (eeprom_data & IGB_MAS_ENABLE_3) {
2181 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2182 netdev_info(adapter->netdev,
2183 "MAS: Enabling Media Autosense for port %d\n",
2184 hw->bus.func);
2185 }
2186 break;
2187 default:
2188 /* Shouldn't get here */
2189 netdev_err(adapter->netdev,
2190 "MAS: Invalid port configuration, returning\n");
2191 break;
2192 }
2193}
2194
b980ac18
JK		 2195/**
2196 * igb_init_i2c - Init I2C interface
441fc6fd 2197 * @adapter: pointer to adapter structure
b980ac18 2198 **/
441fc6fd
CW		 2199static s32 igb_init_i2c(struct igb_adapter *adapter)
2200{
23d87824 2201 s32 status = 0;
441fc6fd
CW		 2202
2203 /* I2C interface supported on i350 devices */
2204 if (adapter->hw.mac.type != e1000_i350)
23d87824 2205 return 0;
441fc6fd
CW		 2206
2207 /* Initialize the i2c bus which is controlled by the registers.
2208 * This bus will use the i2c_algo_bit structue that implements
2209 * the protocol through toggling of the 4 bits in the register.
2210 */
2211 adapter->i2c_adap.owner = THIS_MODULE;
2212 adapter->i2c_algo = igb_i2c_algo;
2213 adapter->i2c_algo.data = adapter;
2214 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2215 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2216 strlcpy(adapter->i2c_adap.name, "igb BB",
2217 sizeof(adapter->i2c_adap.name));
2218 status = i2c_bit_add_bus(&adapter->i2c_adap);
2219 return status;
2220}
2221
9d5c8243 2222/**
b980ac18
JK		 2223 * igb_probe - Device Initialization Routine
2224 * @pdev: PCI device information struct
2225 * @ent: entry in igb_pci_tbl
9d5c8243 2226 *
b980ac18 2227 * Returns 0 on success, negative on failure
9d5c8243 2228 *
b980ac18
JK		 2229 * igb_probe initializes an adapter identified by a pci_dev structure.
2230 * The OS initialization, configuring of the adapter private structure,
2231 * and a hardware reset occur.
9d5c8243 2232 **/
1dd06ae8 2233static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2234{
2235 struct net_device *netdev;
2236 struct igb_adapter *adapter;
2237 struct e1000_hw *hw;
4337e993 2238 u16 eeprom_data = 0;
9835fd73 2239 s32 ret_val;
4337e993 2240 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2241 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2242 int err, pci_using_dac;
9835fd73 2243 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2244
bded64a7
AG		 2245 /* Catch broken hardware that put the wrong VF device ID in
2246 * the PCIe SR-IOV capability.
2247 */
2248 if (pdev->is_virtfn) {
2249 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2250 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2251 return -EINVAL;
2252 }
2253
aed5dec3 2254 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2255 if (err)
2256 return err;
2257
2258 pci_using_dac = 0;
dc4ff9bb 2259 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2260 if (!err) {
dc4ff9bb 2261 pci_using_dac = 1;
9d5c8243 2262 } else {
dc4ff9bb 2263 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2264 if (err) {
dc4ff9bb
RK		 2265 dev_err(&pdev->dev,
2266 "No usable DMA configuration, aborting\n");
2267 goto err_dma;
9d5c8243
AK		 2268 }
2269 }
2270
aed5dec3 2271 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2272 IORESOURCE_MEM),
2273 igb_driver_name);
9d5c8243
AK		 2274 if (err)
2275 goto err_pci_reg;
2276
19d5afd4 2277 pci_enable_pcie_error_reporting(pdev);
40a914fa 2278
9d5c8243 2279 pci_set_master(pdev);
c682fc23 2280 pci_save_state(pdev);
9d5c8243
AK		 2281
2282 err = -ENOMEM;
1bfaf07b 2283 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2284 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2285 if (!netdev)
2286 goto err_alloc_etherdev;
2287
2288 SET_NETDEV_DEV(netdev, &pdev->dev);
2289
2290 pci_set_drvdata(pdev, netdev);
2291 adapter = netdev_priv(netdev);
2292 adapter->netdev = netdev;
2293 adapter->pdev = pdev;
2294 hw = &adapter->hw;
2295 hw->back = adapter;
b3f4d599 2296 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2297
9d5c8243 2298 err = -EIO;
73bf8048
JW		 2299 adapter->io_addr = pci_iomap(pdev, 0, 0);
2300 if (!adapter->io_addr)
9d5c8243 2301 goto err_ioremap;
73bf8048
JW		 2302 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2303 hw->hw_addr = adapter->io_addr;
9d5c8243 2304
2e5c6922 2305 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2306 igb_set_ethtool_ops(netdev);
9d5c8243 2307 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2308
2309 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2310
89dbefb2
AS		 2311 netdev->mem_start = pci_resource_start(pdev, 0);
2312 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2313
9d5c8243
AK		 2314 /* PCI config space info */
2315 hw->vendor_id = pdev->vendor;
2316 hw->device_id = pdev->device;
2317 hw->revision_id = pdev->revision;
2318 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2319 hw->subsystem_device_id = pdev->subsystem_device;
2320
9d5c8243
AK		 2321 /* Copy the default MAC, PHY and NVM function pointers */
2322 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2323 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2324 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2325 /* Initialize skew-specific constants */
2326 err = ei->get_invariants(hw);
2327 if (err)
450c87c8 2328 goto err_sw_init;
9d5c8243 2329
450c87c8 2330 /* setup the private structure */
9d5c8243
AK		 2331 err = igb_sw_init(adapter);
2332 if (err)
2333 goto err_sw_init;
2334
2335 igb_get_bus_info_pcie(hw);
2336
2337 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2338
2339 /* Copper options */
2340 if (hw->phy.media_type == e1000_media_type_copper) {
2341 hw->phy.mdix = AUTO_ALL_MODES;
2342 hw->phy.disable_polarity_correction = false;
2343 hw->phy.ms_type = e1000_ms_hw_default;
2344 }
2345
2346 if (igb_check_reset_block(hw))
2347 dev_info(&pdev->dev,
2348 "PHY reset is blocked due to SOL/IDER session.\n");
2349
b980ac18 2350 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2351 * set by igb_sw_init so we should use an or instead of an
2352 * assignment.
2353 */
2354 netdev->features |= NETIF_F_SG |
2355 NETIF_F_IP_CSUM |
2356 NETIF_F_IPV6_CSUM |
2357 NETIF_F_TSO |
2358 NETIF_F_TSO6 |
2359 NETIF_F_RXHASH |
2360 NETIF_F_RXCSUM |
f646968f
PM		 2361 NETIF_F_HW_VLAN_CTAG_RX |
2362 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2363
2364 /* copy netdev features into list of user selectable features */
2365 netdev->hw_features |= netdev->features;
89eaefb6 2366 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2367
2368 /* set this bit last since it cannot be part of hw_features */
f646968f 2369 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2370
2371 netdev->vlan_features |= NETIF_F_TSO |
2372 NETIF_F_TSO6 |
2373 NETIF_F_IP_CSUM |
2374 NETIF_F_IPV6_CSUM |
2375 NETIF_F_SG;
48f29ffc 2376
6b8f0922
BG		 2377 netdev->priv_flags |= IFF_SUPP_NOFCS;
2378
7b872a55 2379 if (pci_using_dac) {
9d5c8243 2380 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2381 netdev->vlan_features |= NETIF_F_HIGHDMA;
2382 }
9d5c8243 2383
ac52caa3 2384 if (hw->mac.type >= e1000_82576) {
53692b1d
TH		 2385 netdev->hw_features |= NETIF_F_SCTP_CRC;
2386 netdev->features |= NETIF_F_SCTP_CRC;
ac52caa3 2387 }
b9473560 2388
01789349
JP		 2389 netdev->priv_flags |= IFF_UNICAST_FLT;
2390
330a6d6a 2391 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2392
2393 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2394 * known good starting state
2395 */
9d5c8243
AK		 2396 hw->mac.ops.reset_hw(hw);
2397
ef3a0092
CW		 2398 /* make sure the NVM is good , i211/i210 parts can have special NVM
2399 * that doesn't contain a checksum
f96a8a0b 2400 */
ef3a0092
CW		 2401 switch (hw->mac.type) {
2402 case e1000_i210:
2403 case e1000_i211:
2404 if (igb_get_flash_presence_i210(hw)) {
2405 if (hw->nvm.ops.validate(hw) < 0) {
2406 dev_err(&pdev->dev,
2407 "The NVM Checksum Is Not Valid\n");
2408 err = -EIO;
2409 goto err_eeprom;
2410 }
2411 }
2412 break;
2413 default:
f96a8a0b
CW		 2414 if (hw->nvm.ops.validate(hw) < 0) {
2415 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2416 err = -EIO;
2417 goto err_eeprom;
2418 }
ef3a0092 2419 break;
9d5c8243
AK		 2420 }
2421
2422 /* copy the MAC address out of the NVM */
2423 if (hw->mac.ops.read_mac_addr(hw))
2424 dev_err(&pdev->dev, "NVM Read Error\n");
2425
2426 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2427
aaeb6cdf 2428 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2429 dev_err(&pdev->dev, "Invalid MAC Address\n");
2430 err = -EIO;
2431 goto err_eeprom;
2432 }
2433
d67974f0
CW		 2434 /* get firmware version for ethtool -i */
2435 igb_set_fw_version(adapter);
2436
27dff8b2
TF		 2437 /* configure RXPBSIZE and TXPBSIZE */
2438 if (hw->mac.type == e1000_i210) {
2439 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2440 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2441 }
2442
c061b18d 2443 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2444 (unsigned long) adapter);
c061b18d 2445 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2446 (unsigned long) adapter);
9d5c8243
AK		 2447
2448 INIT_WORK(&adapter->reset_task, igb_reset_task);
2449 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2450
450c87c8 2451 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2452 adapter->fc_autoneg = true;
2453 hw->mac.autoneg = true;
2454 hw->phy.autoneg_advertised = 0x2f;
2455
0cce119a
AD		 2456 hw->fc.requested_mode = e1000_fc_default;
2457 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2458
9d5c8243
AK		 2459 igb_validate_mdi_setting(hw);
2460
63d4a8f9 2461 /* By default, support wake on port A */
a2cf8b6c 2462 if (hw->bus.func == 0)
63d4a8f9
MV		 2463 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2464
2465 /* Check the NVM for wake support on non-port A ports */
2466 if (hw->mac.type >= e1000_82580)
55cac248 2467 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2468 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2469 &eeprom_data);
a2cf8b6c
AD		 2470 else if (hw->bus.func == 1)
2471 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2472
63d4a8f9
MV		 2473 if (eeprom_data & IGB_EEPROM_APME)
2474 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2475
2476 /* now that we have the eeprom settings, apply the special cases where
2477 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2478 * lan on a particular port
2479 */
9d5c8243
AK		 2480 switch (pdev->device) {
2481 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2482 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2483 break;
2484 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2485 case E1000_DEV_ID_82576_FIBER:
2486 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2487 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2488 * regardless of eeprom setting
2489 */
9d5c8243 2490 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2491 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2492 break;
c8ea5ea9 2493 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2494 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2495 /* if quad port adapter, disable WoL on all but port A */
2496 if (global_quad_port_a != 0)
63d4a8f9 2497 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2498 else
2499 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2500 /* Reset for multiple quad port adapters */
2501 if (++global_quad_port_a == 4)
2502 global_quad_port_a = 0;
2503 break;
63d4a8f9
MV		 2504 default:
2505 /* If the device can't wake, don't set software support */
2506 if (!device_can_wakeup(&adapter->pdev->dev))
2507 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2508 }
2509
2510 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2511 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2512 adapter->wol |= E1000_WUFC_MAG;
2513
2514 /* Some vendors want WoL disabled by default, but still supported */
2515 if ((hw->mac.type == e1000_i350) &&
2516 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2517 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2518 adapter->wol = 0;
2519 }
2520
2521 device_set_wakeup_enable(&adapter->pdev->dev,
2522 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2523
2524 /* reset the hardware with the new settings */
2525 igb_reset(adapter);
2526
441fc6fd
CW		 2527 /* Init the I2C interface */
2528 err = igb_init_i2c(adapter);
2529 if (err) {
2530 dev_err(&pdev->dev, "failed to init i2c interface\n");
2531 goto err_eeprom;
2532 }
2533
9d5c8243 2534 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2535 * driver.
2536 */
9d5c8243
AK		 2537 igb_get_hw_control(adapter);
2538
9d5c8243
AK		 2539 strcpy(netdev->name, "eth%d");
2540 err = register_netdev(netdev);
2541 if (err)
2542 goto err_register;
2543
b168dfc5
JB		 2544 /* carrier off reporting is important to ethtool even BEFORE open */
2545 netif_carrier_off(netdev);
2546
421e02f0 2547#ifdef CONFIG_IGB_DCA
bbd98fe4 2548 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2549 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2550 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2551 igb_setup_dca(adapter);
2552 }
fe4506b6 2553
38c845c7 2554#endif
e428893b
CW		 2555#ifdef CONFIG_IGB_HWMON
2556 /* Initialize the thermal sensor on i350 devices. */
2557 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2558 u16 ets_word;
3c89f6d0 2559
b980ac18 2560 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2561 * external thermal sensor.
2562 */
2563 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2564 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2565 adapter->ets = true;
2566 else
2567 adapter->ets = false;
2568 if (igb_sysfs_init(adapter))
2569 dev_err(&pdev->dev,
2570 "failed to allocate sysfs resources\n");
2571 } else {
2572 adapter->ets = false;
2573 }
2574#endif
56cec249
CW		 2575 /* Check if Media Autosense is enabled */
2576 adapter->ei = *ei;
2577 if (hw->dev_spec._82575.mas_capable)
2578 igb_init_mas(adapter);
2579
673b8b70 2580 /* do hw tstamp init after resetting */
7ebae817 2581 igb_ptp_init(adapter);
673b8b70 2582
9d5c8243 2583 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2584 /* print bus type/speed/width info, not applicable to i354 */
2585 if (hw->mac.type != e1000_i354) {
2586 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2587 netdev->name,
2588 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2589 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2590 "unknown"),
2591 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2592 "Width x4" :
2593 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2594 "Width x2" :
2595 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2596 "Width x1" : "unknown"), netdev->dev_addr);
2597 }
9d5c8243 2598
53ea6c7e
TF		 2599 if ((hw->mac.type >= e1000_i210 ||
2600 igb_get_flash_presence_i210(hw))) {
2601 ret_val = igb_read_part_string(hw, part_str,
2602 E1000_PBANUM_LENGTH);
2603 } else {
2604 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2605 }
2606
9835fd73
CW		 2607 if (ret_val)
2608 strcpy(part_str, "Unknown");
2609 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2610 dev_info(&pdev->dev,
2611 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2612 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2613 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2614 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2615 if (hw->phy.media_type == e1000_media_type_copper) {
2616 switch (hw->mac.type) {
2617 case e1000_i350:
2618 case e1000_i210:
2619 case e1000_i211:
2620 /* Enable EEE for internal copper PHY devices */
c4c112f1 2621 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2622 if ((!err) &&
2623 (!hw->dev_spec._82575.eee_disable)) {
2624 adapter->eee_advert =
2625 MDIO_EEE_100TX | MDIO_EEE_1000T;
2626 adapter->flags |= IGB_FLAG_EEE;
2627 }
2628 break;
2629 case e1000_i354:
ceb5f13b 2630 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2631 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2632 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2633 if ((!err) &&
2634 (!hw->dev_spec._82575.eee_disable)) {
2635 adapter->eee_advert =
2636 MDIO_EEE_100TX | MDIO_EEE_1000T;
2637 adapter->flags |= IGB_FLAG_EEE;
2638 }
2639 }
2640 break;
2641 default:
2642 break;
ceb5f13b 2643 }
09b068d4 2644 }
749ab2cd 2645 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2646 return 0;
2647
2648err_register:
2649 igb_release_hw_control(adapter);
441fc6fd 2650 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2651err_eeprom:
2652 if (!igb_check_reset_block(hw))
f5f4cf08 2653 igb_reset_phy(hw);
9d5c8243
AK		 2654
2655 if (hw->flash_address)
2656 iounmap(hw->flash_address);
9d5c8243 2657err_sw_init:
42ad1a03 2658 kfree(adapter->shadow_vfta);
047e0030 2659 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2660#ifdef CONFIG_PCI_IOV
2661 igb_disable_sriov(pdev);
2662#endif
73bf8048 2663 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2664err_ioremap:
2665 free_netdev(netdev);
2666err_alloc_etherdev:
559e9c49 2667 pci_release_selected_regions(pdev,
b980ac18 2668 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2669err_pci_reg:
2670err_dma:
2671 pci_disable_device(pdev);
2672 return err;
2673}
2674
fa44f2f1 2675#ifdef CONFIG_PCI_IOV
781798a1 2676static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2677{
2678 struct net_device *netdev = pci_get_drvdata(pdev);
2679 struct igb_adapter *adapter = netdev_priv(netdev);
2680 struct e1000_hw *hw = &adapter->hw;
2681
2682 /* reclaim resources allocated to VFs */
2683 if (adapter->vf_data) {
2684 /* disable iov and allow time for transactions to clear */
b09186d2 2685 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2686 dev_warn(&pdev->dev,
2687 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2688 return -EPERM;
2689 } else {
2690 pci_disable_sriov(pdev);
2691 msleep(500);
2692 }
2693
2694 kfree(adapter->vf_data);
2695 adapter->vf_data = NULL;
2696 adapter->vfs_allocated_count = 0;
2697 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2698 wrfl();
2699 msleep(100);
2700 dev_info(&pdev->dev, "IOV Disabled\n");
2701
2702 /* Re-enable DMA Coalescing flag since IOV is turned off */
2703 adapter->flags |= IGB_FLAG_DMAC;
2704 }
2705
2706 return 0;
2707}
2708
2709static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2710{
2711 struct net_device *netdev = pci_get_drvdata(pdev);
2712 struct igb_adapter *adapter = netdev_priv(netdev);
2713 int old_vfs = pci_num_vf(pdev);
2714 int err = 0;
2715 int i;
2716
cd14ef54 2717 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2718 err = -EPERM;
2719 goto out;
2720 }
fa44f2f1
GR		 2721 if (!num_vfs)
2722 goto out;
fa44f2f1 2723
781798a1
SA		 2724 if (old_vfs) {
2725 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2726 old_vfs, max_vfs);
2727 adapter->vfs_allocated_count = old_vfs;
2728 } else
2729 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2730
2731 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2732 sizeof(struct vf_data_storage), GFP_KERNEL);
2733
2734 /* if allocation failed then we do not support SR-IOV */
2735 if (!adapter->vf_data) {
2736 adapter->vfs_allocated_count = 0;
2737 dev_err(&pdev->dev,
2738 "Unable to allocate memory for VF Data Storage\n");
2739 err = -ENOMEM;
2740 goto out;
2741 }
2742
781798a1
SA		 2743 /* only call pci_enable_sriov() if no VFs are allocated already */
2744 if (!old_vfs) {
2745 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2746 if (err)
2747 goto err_out;
2748 }
fa44f2f1
GR		 2749 dev_info(&pdev->dev, "%d VFs allocated\n",
2750 adapter->vfs_allocated_count);
2751 for (i = 0; i < adapter->vfs_allocated_count; i++)
2752 igb_vf_configure(adapter, i);
2753
2754 /* DMA Coalescing is not supported in IOV mode. */
2755 adapter->flags &= ~IGB_FLAG_DMAC;
2756 goto out;
2757
2758err_out:
2759 kfree(adapter->vf_data);
2760 adapter->vf_data = NULL;
2761 adapter->vfs_allocated_count = 0;
2762out:
2763 return err;
2764}
2765
2766#endif
b980ac18 2767/**
441fc6fd
CW		 2768 * igb_remove_i2c - Cleanup I2C interface
2769 * @adapter: pointer to adapter structure
b980ac18 2770 **/
441fc6fd
CW		 2771static void igb_remove_i2c(struct igb_adapter *adapter)
2772{
441fc6fd
CW		 2773 /* free the adapter bus structure */
2774 i2c_del_adapter(&adapter->i2c_adap);
2775}
2776
9d5c8243 2777/**
b980ac18
JK		 2778 * igb_remove - Device Removal Routine
2779 * @pdev: PCI device information struct
9d5c8243 2780 *
b980ac18
JK		 2781 * igb_remove is called by the PCI subsystem to alert the driver
2782 * that it should release a PCI device. The could be caused by a
2783 * Hot-Plug event, or because the driver is going to be removed from
2784 * memory.
9d5c8243 2785 **/
9f9a12f8 2786static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2787{
2788 struct net_device *netdev = pci_get_drvdata(pdev);
2789 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2790 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2791
749ab2cd 2792 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2793#ifdef CONFIG_IGB_HWMON
2794 igb_sysfs_exit(adapter);
2795#endif
441fc6fd 2796 igb_remove_i2c(adapter);
a79f4f88 2797 igb_ptp_stop(adapter);
b980ac18 2798 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2799 * disable watchdog from being rescheduled.
2800 */
9d5c8243
AK		 2801 set_bit(__IGB_DOWN, &adapter->state);
2802 del_timer_sync(&adapter->watchdog_timer);
2803 del_timer_sync(&adapter->phy_info_timer);
2804
760141a5
TH		 2805 cancel_work_sync(&adapter->reset_task);
2806 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2807
421e02f0 2808#ifdef CONFIG_IGB_DCA
7dfc16fa 2809 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2810 dev_info(&pdev->dev, "DCA disabled\n");
2811 dca_remove_requester(&pdev->dev);
7dfc16fa 2812 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2813 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2814 }
2815#endif
2816
9d5c8243 2817 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2818 * would have already happened in close and is redundant.
2819 */
9d5c8243
AK		 2820 igb_release_hw_control(adapter);
2821
37680117 2822#ifdef CONFIG_PCI_IOV
fa44f2f1 2823 igb_disable_sriov(pdev);
37680117 2824#endif
559e9c49 2825
c23d92b8
AW		 2826 unregister_netdev(netdev);
2827
2828 igb_clear_interrupt_scheme(adapter);
2829
73bf8048 2830 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2831 if (hw->flash_address)
2832 iounmap(hw->flash_address);
559e9c49 2833 pci_release_selected_regions(pdev,
b980ac18 2834 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2835
1128c756 2836 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2837 free_netdev(netdev);
2838
19d5afd4 2839 pci_disable_pcie_error_reporting(pdev);
40a914fa 2840
9d5c8243
AK		 2841 pci_disable_device(pdev);
2842}
2843
a6b623e0 2844/**
b980ac18
JK		 2845 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2846 * @adapter: board private structure to initialize
a6b623e0 2847 *
b980ac18
JK		 2848 * This function initializes the vf specific data storage and then attempts to
2849 * allocate the VFs. The reason for ordering it this way is because it is much
2850 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2851 * the memory for the VFs.
a6b623e0 2852 **/
9f9a12f8 2853static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2854{
2855#ifdef CONFIG_PCI_IOV
2856 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2857 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2858
f96a8a0b
CW		 2859 /* Virtualization features not supported on i210 family. */
2860 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2861 return;
2862
be06998f
JB		 2863 /* Of the below we really only want the effect of getting
2864 * IGB_FLAG_HAS_MSIX set (if available), without which
2865 * igb_enable_sriov() has no effect.
2866 */
2867 igb_set_interrupt_capability(adapter, true);
2868 igb_reset_interrupt_capability(adapter);
2869
fa44f2f1 2870 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2871 igb_enable_sriov(pdev, max_vfs);
0224d663 2872
a6b623e0
AD		 2873#endif /* CONFIG_PCI_IOV */
2874}
2875
fa44f2f1 2876static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2877{
2878 struct e1000_hw *hw = &adapter->hw;
374a542d 2879 u32 max_rss_queues;
9d5c8243 2880
374a542d 2881 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2882 switch (hw->mac.type) {
374a542d
MV		 2883 case e1000_i211:
2884 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2885 break;
2886 case e1000_82575:
f96a8a0b 2887 case e1000_i210:
374a542d
MV		 2888 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2889 break;
2890 case e1000_i350:
2891 /* I350 cannot do RSS and SR-IOV at the same time */
2892 if (!!adapter->vfs_allocated_count) {
2893 max_rss_queues = 1;
2894 break;
2895 }
2896 /* fall through */
2897 case e1000_82576:
2898 if (!!adapter->vfs_allocated_count) {
2899 max_rss_queues = 2;
2900 break;
2901 }
2902 /* fall through */
2903 case e1000_82580:
ceb5f13b 2904 case e1000_i354:
374a542d
MV		 2905 default:
2906 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2907 break;
374a542d
MV		 2908 }
2909
2910 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2911
72ddef05
SS		 2912 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2913}
2914
2915void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2916 const u32 max_rss_queues)
2917{
2918 struct e1000_hw *hw = &adapter->hw;
2919
374a542d
MV		 2920 /* Determine if we need to pair queues. */
2921 switch (hw->mac.type) {
2922 case e1000_82575:
f96a8a0b 2923 case e1000_i211:
374a542d 2924 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2925 break;
374a542d 2926 case e1000_82576:
374a542d
MV		 2927 case e1000_82580:
2928 case e1000_i350:
ceb5f13b 2929 case e1000_i354:
374a542d 2930 case e1000_i210:
f96a8a0b 2931 default:
b980ac18 2932 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2933 * order to conserve interrupts due to limited supply.
2934 */
2935 if (adapter->rss_queues > (max_rss_queues / 2))
2936 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
37a5d163
SS		 2937 else
2938 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2939 break;
2940 }
fa44f2f1
GR		 2941}
2942
2943/**
b980ac18
JK		 2944 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2945 * @adapter: board private structure to initialize
fa44f2f1 2946 *
b980ac18
JK		 2947 * igb_sw_init initializes the Adapter private data structure.
2948 * Fields are initialized based on PCI device information and
2949 * OS network device settings (MTU size).
fa44f2f1
GR		 2950 **/
2951static int igb_sw_init(struct igb_adapter *adapter)
2952{
2953 struct e1000_hw *hw = &adapter->hw;
2954 struct net_device *netdev = adapter->netdev;
2955 struct pci_dev *pdev = adapter->pdev;
2956
2957 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2958
2959 /* set default ring sizes */
2960 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2961 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2962
2963 /* set default ITR values */
2964 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2965 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2966
2967 /* set default work limits */
2968 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2969
2970 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2971 VLAN_HLEN;
2972 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2973
2974 spin_lock_init(&adapter->stats64_lock);
2975#ifdef CONFIG_PCI_IOV
2976 switch (hw->mac.type) {
2977 case e1000_82576:
2978 case e1000_i350:
2979 if (max_vfs > 7) {
2980 dev_warn(&pdev->dev,
2981 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2982 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2983 } else
2984 adapter->vfs_allocated_count = max_vfs;
2985 if (adapter->vfs_allocated_count)
2986 dev_warn(&pdev->dev,
2987 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2988 break;
2989 default:
2990 break;
2991 }
2992#endif /* CONFIG_PCI_IOV */
2993
cbfe360a
SA		 2994 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
2995 adapter->flags |= IGB_FLAG_HAS_MSIX;
2996
ceee3450
TF		 2997 igb_probe_vfs(adapter);
2998
fa44f2f1 2999 igb_init_queue_configuration(adapter);
a99955fc 3000
1128c756 3001 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 3002 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3003 GFP_ATOMIC);
1128c756 3004
a6b623e0 3005 /* This call may decrease the number of queues */
53c7d064 3006 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3007 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3008 return -ENOMEM;
3009 }
3010
3011 /* Explicitly disable IRQ since the NIC can be in any state. */
3012 igb_irq_disable(adapter);
3013
f96a8a0b 3014 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3015 adapter->flags &= ~IGB_FLAG_DMAC;
3016
9d5c8243
AK		 3017 set_bit(__IGB_DOWN, &adapter->state);
3018 return 0;
3019}
3020
3021/**
b980ac18
JK		 3022 * igb_open - Called when a network interface is made active
3023 * @netdev: network interface device structure
9d5c8243 3024 *
b980ac18 3025 * Returns 0 on success, negative value on failure
9d5c8243 3026 *
b980ac18
JK		 3027 * The open entry point is called when a network interface is made
3028 * active by the system (IFF_UP). At this point all resources needed
3029 * for transmit and receive operations are allocated, the interrupt
3030 * handler is registered with the OS, the watchdog timer is started,
3031 * and the stack is notified that the interface is ready.
9d5c8243 3032 **/
749ab2cd 3033static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3034{
3035 struct igb_adapter *adapter = netdev_priv(netdev);
3036 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3037 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3038 int err;
3039 int i;
3040
3041 /* disallow open during test */
749ab2cd
YZ		 3042 if (test_bit(__IGB_TESTING, &adapter->state)) {
3043 WARN_ON(resuming);
9d5c8243 3044 return -EBUSY;
749ab2cd
YZ		 3045 }
3046
3047 if (!resuming)
3048 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3049
b168dfc5
JB		 3050 netif_carrier_off(netdev);
3051
9d5c8243
AK		 3052 /* allocate transmit descriptors */
3053 err = igb_setup_all_tx_resources(adapter);
3054 if (err)
3055 goto err_setup_tx;
3056
3057 /* allocate receive descriptors */
3058 err = igb_setup_all_rx_resources(adapter);
3059 if (err)
3060 goto err_setup_rx;
3061
88a268c1 3062 igb_power_up_link(adapter);
9d5c8243 3063
9d5c8243
AK		 3064 /* before we allocate an interrupt, we must be ready to handle it.
3065 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3066 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3067 * clean_rx handler before we do so.
3068 */
9d5c8243
AK		 3069 igb_configure(adapter);
3070
3071 err = igb_request_irq(adapter);
3072 if (err)
3073 goto err_req_irq;
3074
0c2cc02e
AD		 3075 /* Notify the stack of the actual queue counts. */
3076 err = netif_set_real_num_tx_queues(adapter->netdev,
3077 adapter->num_tx_queues);
3078 if (err)
3079 goto err_set_queues;
3080
3081 err = netif_set_real_num_rx_queues(adapter->netdev,
3082 adapter->num_rx_queues);
3083 if (err)
3084 goto err_set_queues;
3085
9d5c8243
AK		 3086 /* From here on the code is the same as igb_up() */
3087 clear_bit(__IGB_DOWN, &adapter->state);
3088
0d1ae7f4
AD		 3089 for (i = 0; i < adapter->num_q_vectors; i++)
3090 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3091
3092 /* Clear any pending interrupts. */
3093 rd32(E1000_ICR);
844290e5
PW		 3094
3095 igb_irq_enable(adapter);
3096
d4960307
AD		 3097 /* notify VFs that reset has been completed */
3098 if (adapter->vfs_allocated_count) {
3099 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3100
d4960307
AD		 3101 reg_data |= E1000_CTRL_EXT_PFRSTD;
3102 wr32(E1000_CTRL_EXT, reg_data);
3103 }
3104
d55b53ff
JK		 3105 netif_tx_start_all_queues(netdev);
3106
749ab2cd
YZ		 3107 if (!resuming)
3108 pm_runtime_put(&pdev->dev);
3109
25568a53
AD		 3110 /* start the watchdog. */
3111 hw->mac.get_link_status = 1;
3112 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3113
3114 return 0;
3115
0c2cc02e
AD		 3116err_set_queues:
3117 igb_free_irq(adapter);
9d5c8243
AK		 3118err_req_irq:
3119 igb_release_hw_control(adapter);
88a268c1 3120 igb_power_down_link(adapter);
9d5c8243
AK		 3121 igb_free_all_rx_resources(adapter);
3122err_setup_rx:
3123 igb_free_all_tx_resources(adapter);
3124err_setup_tx:
3125 igb_reset(adapter);
749ab2cd
YZ		 3126 if (!resuming)
3127 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3128
3129 return err;
3130}
3131
749ab2cd
YZ		 3132static int igb_open(struct net_device *netdev)
3133{
3134 return __igb_open(netdev, false);
3135}
3136
9d5c8243 3137/**
b980ac18
JK		 3138 * igb_close - Disables a network interface
3139 * @netdev: network interface device structure
9d5c8243 3140 *
b980ac18 3141 * Returns 0, this is not allowed to fail
9d5c8243 3142 *
b980ac18
JK		 3143 * The close entry point is called when an interface is de-activated
3144 * by the OS. The hardware is still under the driver's control, but
3145 * needs to be disabled. A global MAC reset is issued to stop the
3146 * hardware, and all transmit and receive resources are freed.
9d5c8243 3147 **/
749ab2cd 3148static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3149{
3150 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3151 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3152
3153 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3154
749ab2cd
YZ		 3155 if (!suspending)
3156 pm_runtime_get_sync(&pdev->dev);
3157
3158 igb_down(adapter);
9d5c8243
AK		 3159 igb_free_irq(adapter);
3160
3161 igb_free_all_tx_resources(adapter);
3162 igb_free_all_rx_resources(adapter);
3163
749ab2cd
YZ		 3164 if (!suspending)
3165 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3166 return 0;
3167}
3168
749ab2cd
YZ		 3169static int igb_close(struct net_device *netdev)
3170{
3171 return __igb_close(netdev, false);
3172}
3173
9d5c8243 3174/**
b980ac18
JK		 3175 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3176 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3177 *
b980ac18 3178 * Return 0 on success, negative on failure
9d5c8243 3179 **/
80785298 3180int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3181{
59d71989 3182 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3183 int size;
3184
06034649 3185 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3186
3187 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3188 if (!tx_ring->tx_buffer_info)
9d5c8243 3189 goto err;
9d5c8243
AK		 3190
3191 /* round up to nearest 4K */
85e8d004 3192 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3193 tx_ring->size = ALIGN(tx_ring->size, 4096);
3194
5536d210
AD		 3195 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3196 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3197 if (!tx_ring->desc)
3198 goto err;
3199
9d5c8243
AK		 3200 tx_ring->next_to_use = 0;
3201 tx_ring->next_to_clean = 0;
81c2fc22 3202
9d5c8243
AK		 3203 return 0;
3204
3205err:
06034649 3206 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3207 tx_ring->tx_buffer_info = NULL;
3208 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3209 return -ENOMEM;
3210}
3211
3212/**
b980ac18
JK		 3213 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3214 * (Descriptors) for all queues
3215 * @adapter: board private structure
9d5c8243 3216 *
b980ac18 3217 * Return 0 on success, negative on failure
9d5c8243
AK		 3218 **/
3219static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3220{
439705e1 3221 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3222 int i, err = 0;
3223
3224 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3225 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3226 if (err) {
439705e1 3227 dev_err(&pdev->dev,
9d5c8243
AK		 3228 "Allocation for Tx Queue %u failed\n", i);
3229 for (i--; i >= 0; i--)
3025a446 3230 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3231 break;
3232 }
3233 }
3234
3235 return err;
3236}
3237
3238/**
b980ac18
JK		 3239 * igb_setup_tctl - configure the transmit control registers
3240 * @adapter: Board private structure
9d5c8243 3241 **/
d7ee5b3a 3242void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3243{
9d5c8243
AK		 3244 struct e1000_hw *hw = &adapter->hw;
3245 u32 tctl;
9d5c8243 3246
85b430b4
AD		 3247 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3248 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3249
3250 /* Program the Transmit Control Register */
9d5c8243
AK		 3251 tctl = rd32(E1000_TCTL);
3252 tctl &= ~E1000_TCTL_CT;
3253 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3254 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3255
3256 igb_config_collision_dist(hw);
3257
9d5c8243
AK		 3258 /* Enable transmits */
3259 tctl |= E1000_TCTL_EN;
3260
3261 wr32(E1000_TCTL, tctl);
3262}
3263
85b430b4 3264/**
b980ac18
JK		 3265 * igb_configure_tx_ring - Configure transmit ring after Reset
3266 * @adapter: board private structure
3267 * @ring: tx ring to configure
85b430b4 3268 *
b980ac18 3269 * Configure a transmit ring after a reset.
85b430b4 3270 **/
d7ee5b3a 3271void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3272 struct igb_ring *ring)
85b430b4
AD		 3273{
3274 struct e1000_hw *hw = &adapter->hw;
a74420e0 3275 u32 txdctl = 0;
85b430b4
AD		 3276 u64 tdba = ring->dma;
3277 int reg_idx = ring->reg_idx;
3278
3279 /* disable the queue */
a74420e0 3280 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3281 wrfl();
3282 mdelay(10);
3283
3284 wr32(E1000_TDLEN(reg_idx),
b980ac18 3285 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3286 wr32(E1000_TDBAL(reg_idx),
b980ac18 3287 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3288 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3289
fce99e34 3290 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3291 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3292 writel(0, ring->tail);
85b430b4
AD		 3293
3294 txdctl |= IGB_TX_PTHRESH;
3295 txdctl |= IGB_TX_HTHRESH << 8;
3296 txdctl |= IGB_TX_WTHRESH << 16;
3297
3298 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3299 wr32(E1000_TXDCTL(reg_idx), txdctl);
3300}
3301
3302/**
b980ac18
JK		 3303 * igb_configure_tx - Configure transmit Unit after Reset
3304 * @adapter: board private structure
85b430b4 3305 *
b980ac18 3306 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3307 **/
3308static void igb_configure_tx(struct igb_adapter *adapter)
3309{
3310 int i;
3311
3312 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3313 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3314}
3315
9d5c8243 3316/**
b980ac18
JK		 3317 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3318 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3319 *
b980ac18 3320 * Returns 0 on success, negative on failure
9d5c8243 3321 **/
80785298 3322int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3323{
59d71989 3324 struct device *dev = rx_ring->dev;
f33005a6 3325 int size;
9d5c8243 3326
06034649 3327 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3328
3329 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3330 if (!rx_ring->rx_buffer_info)
9d5c8243 3331 goto err;
9d5c8243 3332
9d5c8243 3333 /* Round up to nearest 4K */
f33005a6 3334 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3335 rx_ring->size = ALIGN(rx_ring->size, 4096);
3336
5536d210
AD		 3337 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3338 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3339 if (!rx_ring->desc)
3340 goto err;
3341
cbc8e55f 3342 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3343 rx_ring->next_to_clean = 0;
3344 rx_ring->next_to_use = 0;
9d5c8243 3345
9d5c8243
AK		 3346 return 0;
3347
3348err:
06034649
AD		 3349 vfree(rx_ring->rx_buffer_info);
3350 rx_ring->rx_buffer_info = NULL;
f33005a6 3351 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3352 return -ENOMEM;
3353}
3354
3355/**
b980ac18
JK		 3356 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3357 * (Descriptors) for all queues
3358 * @adapter: board private structure
9d5c8243 3359 *
b980ac18 3360 * Return 0 on success, negative on failure
9d5c8243
AK		 3361 **/
3362static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3363{
439705e1 3364 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3365 int i, err = 0;
3366
3367 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3368 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3369 if (err) {
439705e1 3370 dev_err(&pdev->dev,
9d5c8243
AK		 3371 "Allocation for Rx Queue %u failed\n", i);
3372 for (i--; i >= 0; i--)
3025a446 3373 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3374 break;
3375 }
3376 }
3377
3378 return err;
3379}
3380
06cf2666 3381/**
b980ac18
JK		 3382 * igb_setup_mrqc - configure the multiple receive queue control registers
3383 * @adapter: Board private structure
06cf2666
AD		 3384 **/
3385static void igb_setup_mrqc(struct igb_adapter *adapter)
3386{
3387 struct e1000_hw *hw = &adapter->hw;
3388 u32 mrqc, rxcsum;
ed12cc9a 3389 u32 j, num_rx_queues;
eb31f849 3390 u32 rss_key[10];
06cf2666 3391
eb31f849 3392 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3393 for (j = 0; j < 10; j++)
eb31f849 3394 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3395
a99955fc 3396 num_rx_queues = adapter->rss_queues;
06cf2666 3397
797fd4be 3398 switch (hw->mac.type) {
797fd4be
AD		 3399 case e1000_82576:
3400 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3401 if (adapter->vfs_allocated_count)
06cf2666 3402 num_rx_queues = 2;
797fd4be
AD		 3403 break;
3404 default:
3405 break;
06cf2666
AD		 3406 }
3407
ed12cc9a
LMV		 3408 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3409 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3410 adapter->rss_indir_tbl[j] =
3411 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3412 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3413 }
ed12cc9a 3414 igb_write_rss_indir_tbl(adapter);
06cf2666 3415
b980ac18 3416 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3417 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3418 * offloads as they are enabled by default
3419 */
3420 rxcsum = rd32(E1000_RXCSUM);
3421 rxcsum |= E1000_RXCSUM_PCSD;
3422
3423 if (adapter->hw.mac.type >= e1000_82576)
3424 /* Enable Receive Checksum Offload for SCTP */
3425 rxcsum |= E1000_RXCSUM_CRCOFL;
3426
3427 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3428 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3429
039454a8
AA		 3430 /* Generate RSS hash based on packet types, TCP/UDP
3431 * port numbers and/or IPv4/v6 src and dst addresses
3432 */
f96a8a0b
CW		 3433 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3434 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3435 E1000_MRQC_RSS_FIELD_IPV6 |
3436 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3437 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3438
039454a8
AA		 3439 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3440 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3441 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3442 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3443
06cf2666
AD		 3444 /* If VMDq is enabled then we set the appropriate mode for that, else
3445 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3446 * if we are only using one queue
3447 */
06cf2666
AD		 3448 if (adapter->vfs_allocated_count) {
3449 if (hw->mac.type > e1000_82575) {
3450 /* Set the default pool for the PF's first queue */
3451 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3452
06cf2666
AD		 3453 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3454 E1000_VT_CTL_DISABLE_DEF_POOL);
3455 vtctl |= adapter->vfs_allocated_count <<
3456 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3457 wr32(E1000_VT_CTL, vtctl);
3458 }
a99955fc 3459 if (adapter->rss_queues > 1)
f96a8a0b 3460 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3461 else
f96a8a0b 3462 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3463 } else {
f96a8a0b
CW		 3464 if (hw->mac.type != e1000_i211)
3465 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3466 }
3467 igb_vmm_control(adapter);
3468
06cf2666
AD		 3469 wr32(E1000_MRQC, mrqc);
3470}
3471
9d5c8243 3472/**
b980ac18
JK		 3473 * igb_setup_rctl - configure the receive control registers
3474 * @adapter: Board private structure
9d5c8243 3475 **/
d7ee5b3a 3476void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3477{
3478 struct e1000_hw *hw = &adapter->hw;
3479 u32 rctl;
9d5c8243
AK		 3480
3481 rctl = rd32(E1000_RCTL);
3482
3483 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3484 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3485
69d728ba 3486 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3487 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3488
b980ac18 3489 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3490 * redirection as it did with e1000. Newer features require
3491 * that the HW strips the CRC.
73cd78f1 3492 */
87cb7e8c 3493 rctl |= E1000_RCTL_SECRC;
9d5c8243 3494
559e9c49 3495 /* disable store bad packets and clear size bits. */
ec54d7d6 3496 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3497
45693bcb 3498 /* enable LPE to allow for reception of jumbo frames */
6ec43fe6 3499 rctl |= E1000_RCTL_LPE;
9d5c8243 3500
952f72a8
AD		 3501 /* disable queue 0 to prevent tail write w/o re-config */
3502 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3503
e1739522
AD		 3504 /* Attention!!! For SR-IOV PF driver operations you must enable
3505 * queue drop for all VF and PF queues to prevent head of line blocking
3506 * if an un-trusted VF does not provide descriptors to hardware.
3507 */
3508 if (adapter->vfs_allocated_count) {
e1739522
AD		 3509 /* set all queue drop enable bits */
3510 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3511 }
3512
89eaefb6
BG		 3513 /* This is useful for sniffing bad packets. */
3514 if (adapter->netdev->features & NETIF_F_RXALL) {
3515 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3516 * in e1000e_set_rx_mode
3517 */
89eaefb6
BG		 3518 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3519 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3520 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3521
16903caa 3522 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
89eaefb6
BG		 3523 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3524 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3525 * and that breaks VLANs.
3526 */
3527 }
3528
9d5c8243
AK		 3529 wr32(E1000_RCTL, rctl);
3530}
3531
7d5753f0 3532static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3533 int vfn)
7d5753f0
AD		 3534{
3535 struct e1000_hw *hw = &adapter->hw;
3536 u32 vmolr;
3537
d3836f8e
AD		 3538 if (size > MAX_JUMBO_FRAME_SIZE)
3539 size = MAX_JUMBO_FRAME_SIZE;
7d5753f0
AD		 3540
3541 vmolr = rd32(E1000_VMOLR(vfn));
3542 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3543 vmolr |= size | E1000_VMOLR_LPE;
3544 wr32(E1000_VMOLR(vfn), vmolr);
3545
3546 return 0;
3547}
3548
8151d294
WM		 3549static inline void igb_set_vmolr(struct igb_adapter *adapter,
3550 int vfn, bool aupe)
7d5753f0
AD		 3551{
3552 struct e1000_hw *hw = &adapter->hw;
3553 u32 vmolr;
3554
b980ac18 3555 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3556 * we should exit and do nothing
3557 */
3558 if (hw->mac.type < e1000_82576)
3559 return;
3560
3561 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3562 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3563 if (hw->mac.type == e1000_i350) {
3564 u32 dvmolr;
3565
3566 dvmolr = rd32(E1000_DVMOLR(vfn));
3567 dvmolr |= E1000_DVMOLR_STRVLAN;
3568 wr32(E1000_DVMOLR(vfn), dvmolr);
3569 }
8151d294 3570 if (aupe)
b980ac18 3571 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3572 else
3573 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3574
3575 /* clear all bits that might not be set */
3576 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3577
a99955fc 3578 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3579 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3580 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3581 * multicast packets
3582 */
3583 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3584 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3585
3586 wr32(E1000_VMOLR(vfn), vmolr);
3587}
3588
85b430b4 3589/**
b980ac18
JK		 3590 * igb_configure_rx_ring - Configure a receive ring after Reset
3591 * @adapter: board private structure
3592 * @ring: receive ring to be configured
85b430b4 3593 *
b980ac18 3594 * Configure the Rx unit of the MAC after a reset.
85b430b4 3595 **/
d7ee5b3a 3596void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3597 struct igb_ring *ring)
85b430b4
AD		 3598{
3599 struct e1000_hw *hw = &adapter->hw;
3600 u64 rdba = ring->dma;
3601 int reg_idx = ring->reg_idx;
a74420e0 3602 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3603
3604 /* disable the queue */
a74420e0 3605 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3606
3607 /* Set DMA base address registers */
3608 wr32(E1000_RDBAL(reg_idx),
3609 rdba & 0x00000000ffffffffULL);
3610 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3611 wr32(E1000_RDLEN(reg_idx),
b980ac18 3612 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3613
3614 /* initialize head and tail */
fce99e34 3615 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3616 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3617 writel(0, ring->tail);
85b430b4 3618
952f72a8 3619 /* set descriptor configuration */
44390ca6 3620 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3621 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3622 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3623 if (hw->mac.type >= e1000_82580)
757b77e2 3624 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3625 /* Only set Drop Enable if we are supporting multiple queues */
3626 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3627 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3628
3629 wr32(E1000_SRRCTL(reg_idx), srrctl);
3630
7d5753f0 3631 /* set filtering for VMDQ pools */
8151d294 3632 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3633
85b430b4
AD		 3634 rxdctl |= IGB_RX_PTHRESH;
3635 rxdctl |= IGB_RX_HTHRESH << 8;
3636 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3637
3638 /* enable receive descriptor fetching */
3639 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3640 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3641}
3642
9d5c8243 3643/**
b980ac18
JK		 3644 * igb_configure_rx - Configure receive Unit after Reset
3645 * @adapter: board private structure
9d5c8243 3646 *
b980ac18 3647 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3648 **/
3649static void igb_configure_rx(struct igb_adapter *adapter)
3650{
9107584e 3651 int i;
9d5c8243 3652
68d480c4
AD		 3653 /* set UTA to appropriate mode */
3654 igb_set_uta(adapter);
3655
26ad9178
AD		 3656 /* set the correct pool for the PF default MAC address in entry 0 */
3657 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3658 adapter->vfs_allocated_count);
26ad9178 3659
06cf2666 3660 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3661 * the Base and Length of the Rx Descriptor Ring
3662 */
f9d40f6a
AD		 3663 for (i = 0; i < adapter->num_rx_queues; i++)
3664 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3665}
3666
3667/**
b980ac18
JK		 3668 * igb_free_tx_resources - Free Tx Resources per Queue
3669 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3670 *
b980ac18 3671 * Free all transmit software resources
9d5c8243 3672 **/
68fd9910 3673void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3674{
3b644cf6 3675 igb_clean_tx_ring(tx_ring);
9d5c8243 3676
06034649
AD		 3677 vfree(tx_ring->tx_buffer_info);
3678 tx_ring->tx_buffer_info = NULL;
9d5c8243 3679
439705e1
AD		 3680 /* if not set, then don't free */
3681 if (!tx_ring->desc)
3682 return;
3683
59d71989
AD		 3684 dma_free_coherent(tx_ring->dev, tx_ring->size,
3685 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3686
3687 tx_ring->desc = NULL;
3688}
3689
3690/**
b980ac18
JK		 3691 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3692 * @adapter: board private structure
9d5c8243 3693 *
b980ac18 3694 * Free all transmit software resources
9d5c8243
AK		 3695 **/
3696static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3697{
3698 int i;
3699
3700 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3701 if (adapter->tx_ring[i])
3702 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3703}
3704
ebe42d16
AD		 3705void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3706 struct igb_tx_buffer *tx_buffer)
3707{
3708 if (tx_buffer->skb) {
3709 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3710 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3711 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3712 dma_unmap_addr(tx_buffer, dma),
3713 dma_unmap_len(tx_buffer, len),
ebe42d16 3714 DMA_TO_DEVICE);
c9f14bf3 3715 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3716 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3717 dma_unmap_addr(tx_buffer, dma),
3718 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3719 DMA_TO_DEVICE);
3720 }
3721 tx_buffer->next_to_watch = NULL;
3722 tx_buffer->skb = NULL;
c9f14bf3 3723 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3724 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3725}
3726
3727/**
b980ac18
JK		 3728 * igb_clean_tx_ring - Free Tx Buffers
3729 * @tx_ring: ring to be cleaned
9d5c8243 3730 **/
3b644cf6 3731static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3732{
06034649 3733 struct igb_tx_buffer *buffer_info;
9d5c8243 3734 unsigned long size;
6ad4edfc 3735 u16 i;
9d5c8243 3736
06034649 3737 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3738 return;
3739 /* Free all the Tx ring sk_buffs */
3740
3741 for (i = 0; i < tx_ring->count; i++) {
06034649 3742 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3743 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3744 }
3745
dad8a3b3
JF		 3746 netdev_tx_reset_queue(txring_txq(tx_ring));
3747
06034649
AD		 3748 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3749 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3750
3751 /* Zero out the descriptor ring */
9d5c8243
AK		 3752 memset(tx_ring->desc, 0, tx_ring->size);
3753
3754 tx_ring->next_to_use = 0;
3755 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3756}
3757
3758/**
b980ac18
JK		 3759 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3760 * @adapter: board private structure
9d5c8243
AK		 3761 **/
3762static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3763{
3764 int i;
3765
3766 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3767 if (adapter->tx_ring[i])
3768 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3769}
3770
3771/**
b980ac18
JK		 3772 * igb_free_rx_resources - Free Rx Resources
3773 * @rx_ring: ring to clean the resources from
9d5c8243 3774 *
b980ac18 3775 * Free all receive software resources
9d5c8243 3776 **/
68fd9910 3777void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3778{
3b644cf6 3779 igb_clean_rx_ring(rx_ring);
9d5c8243 3780
06034649
AD		 3781 vfree(rx_ring->rx_buffer_info);
3782 rx_ring->rx_buffer_info = NULL;
9d5c8243 3783
439705e1
AD		 3784 /* if not set, then don't free */
3785 if (!rx_ring->desc)
3786 return;
3787
59d71989
AD		 3788 dma_free_coherent(rx_ring->dev, rx_ring->size,
3789 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3790
3791 rx_ring->desc = NULL;
3792}
3793
3794/**
b980ac18
JK		 3795 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3796 * @adapter: board private structure
9d5c8243 3797 *
b980ac18 3798 * Free all receive software resources
9d5c8243
AK		 3799 **/
3800static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3801{
3802 int i;
3803
3804 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3805 if (adapter->rx_ring[i])
3806 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3807}
3808
3809/**
b980ac18
JK		 3810 * igb_clean_rx_ring - Free Rx Buffers per Queue
3811 * @rx_ring: ring to free buffers from
9d5c8243 3812 **/
3b644cf6 3813static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3814{
9d5c8243 3815 unsigned long size;
c023cd88 3816 u16 i;
9d5c8243 3817
1a1c225b
AD		 3818 if (rx_ring->skb)
3819 dev_kfree_skb(rx_ring->skb);
3820 rx_ring->skb = NULL;
3821
06034649 3822 if (!rx_ring->rx_buffer_info)
9d5c8243 3823 return;
439705e1 3824
9d5c8243
AK		 3825 /* Free all the Rx ring sk_buffs */
3826 for (i = 0; i < rx_ring->count; i++) {
06034649 3827 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3828
cbc8e55f
AD		 3829 if (!buffer_info->page)
3830 continue;
3831
3832 dma_unmap_page(rx_ring->dev,
3833 buffer_info->dma,
3834 PAGE_SIZE,
3835 DMA_FROM_DEVICE);
3836 __free_page(buffer_info->page);
3837
1a1c225b 3838 buffer_info->page = NULL;
9d5c8243
AK		 3839 }
3840
06034649
AD		 3841 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3842 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3843
3844 /* Zero out the descriptor ring */
3845 memset(rx_ring->desc, 0, rx_ring->size);
3846
cbc8e55f 3847 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3848 rx_ring->next_to_clean = 0;
3849 rx_ring->next_to_use = 0;
9d5c8243
AK		 3850}
3851
3852/**
b980ac18
JK		 3853 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3854 * @adapter: board private structure
9d5c8243
AK		 3855 **/
3856static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3857{
3858 int i;
3859
3860 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3861 if (adapter->rx_ring[i])
3862 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3863}
3864
3865/**
b980ac18
JK		 3866 * igb_set_mac - Change the Ethernet Address of the NIC
3867 * @netdev: network interface device structure
3868 * @p: pointer to an address structure
9d5c8243 3869 *
b980ac18 3870 * Returns 0 on success, negative on failure
9d5c8243
AK		 3871 **/
3872static int igb_set_mac(struct net_device *netdev, void *p)
3873{
3874 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3875 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3876 struct sockaddr *addr = p;
3877
3878 if (!is_valid_ether_addr(addr->sa_data))
3879 return -EADDRNOTAVAIL;
3880
3881 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3882 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3883
26ad9178
AD		 3884 /* set the correct pool for the new PF MAC address in entry 0 */
3885 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3886 adapter->vfs_allocated_count);
e1739522 3887
9d5c8243
AK		 3888 return 0;
3889}
3890
3891/**
b980ac18
JK		 3892 * igb_write_mc_addr_list - write multicast addresses to MTA
3893 * @netdev: network interface device structure
9d5c8243 3894 *
b980ac18
JK		 3895 * Writes multicast address list to the MTA hash table.
3896 * Returns: -ENOMEM on failure
3897 * 0 on no addresses written
3898 * X on writing X addresses to MTA
9d5c8243 3899 **/
68d480c4 3900static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3901{
3902 struct igb_adapter *adapter = netdev_priv(netdev);
3903 struct e1000_hw *hw = &adapter->hw;
22bedad3 3904 struct netdev_hw_addr *ha;
68d480c4 3905 u8 *mta_list;
9d5c8243
AK		 3906 int i;
3907
4cd24eaf 3908 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3909 /* nothing to program, so clear mc list */
3910 igb_update_mc_addr_list(hw, NULL, 0);
3911 igb_restore_vf_multicasts(adapter);
3912 return 0;
3913 }
9d5c8243 3914
4cd24eaf 3915 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3916 if (!mta_list)
3917 return -ENOMEM;
ff41f8dc 3918
68d480c4 3919 /* The shared function expects a packed array of only addresses. */
48e2f183 3920 i = 0;
22bedad3
JP		 3921 netdev_for_each_mc_addr(ha, netdev)
3922 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3923
68d480c4
AD		 3924 igb_update_mc_addr_list(hw, mta_list, i);
3925 kfree(mta_list);
3926
4cd24eaf 3927 return netdev_mc_count(netdev);
68d480c4
AD		 3928}
3929
3930/**
b980ac18
JK		 3931 * igb_write_uc_addr_list - write unicast addresses to RAR table
3932 * @netdev: network interface device structure
68d480c4 3933 *
b980ac18
JK		 3934 * Writes unicast address list to the RAR table.
3935 * Returns: -ENOMEM on failure/insufficient address space
3936 * 0 on no addresses written
3937 * X on writing X addresses to the RAR table
68d480c4
AD		 3938 **/
3939static int igb_write_uc_addr_list(struct net_device *netdev)
3940{
3941 struct igb_adapter *adapter = netdev_priv(netdev);
3942 struct e1000_hw *hw = &adapter->hw;
3943 unsigned int vfn = adapter->vfs_allocated_count;
3944 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3945 int count = 0;
3946
3947 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3948 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3949 return -ENOMEM;
9d5c8243 3950
32e7bfc4 3951 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3952 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3953
3954 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3955 if (!rar_entries)
3956 break;
26ad9178 3957 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3958 rar_entries--,
3959 vfn);
68d480c4 3960 count++;
ff41f8dc
AD		 3961 }
3962 }
3963 /* write the addresses in reverse order to avoid write combining */
3964 for (; rar_entries > 0 ; rar_entries--) {
3965 wr32(E1000_RAH(rar_entries), 0);
3966 wr32(E1000_RAL(rar_entries), 0);
3967 }
3968 wrfl();
3969
68d480c4
AD		 3970 return count;
3971}
3972
16903caa
AD		 3973static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
3974{
3975 struct e1000_hw *hw = &adapter->hw;
3976 u32 i, pf_id;
3977
3978 switch (hw->mac.type) {
3979 case e1000_i210:
3980 case e1000_i211:
3981 case e1000_i350:
3982 /* VLAN filtering needed for VLAN prio filter */
3983 if (adapter->netdev->features & NETIF_F_NTUPLE)
3984 break;
3985 /* fall through */
3986 case e1000_82576:
3987 case e1000_82580:
3988 case e1000_i354:
3989 /* VLAN filtering needed for pool filtering */
3990 if (adapter->vfs_allocated_count)
3991 break;
3992 /* fall through */
3993 default:
3994 return 1;
3995 }
3996
3997 /* We are already in VLAN promisc, nothing to do */
3998 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
3999 return 0;
4000
4001 if (!adapter->vfs_allocated_count)
4002 goto set_vfta;
4003
4004 /* Add PF to all active pools */
4005 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4006
4007 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4008 u32 vlvf = rd32(E1000_VLVF(i));
4009
4010 vlvf |= 1 << pf_id;
4011 wr32(E1000_VLVF(i), vlvf);
4012 }
4013
4014set_vfta:
4015 /* Set all bits in the VLAN filter table array */
4016 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4017 hw->mac.ops.write_vfta(hw, i, ~0U);
4018
4019 /* Set flag so we don't redo unnecessary work */
4020 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4021
4022 return 0;
4023}
4024
4025#define VFTA_BLOCK_SIZE 8
4026static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4027{
4028 struct e1000_hw *hw = &adapter->hw;
4029 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4030 u32 vid_start = vfta_offset * 32;
4031 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4032 u32 i, vid, word, bits, pf_id;
4033
4034 /* guarantee that we don't scrub out management VLAN */
4035 vid = adapter->mng_vlan_id;
4036 if (vid >= vid_start && vid < vid_end)
4037 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4038
4039 if (!adapter->vfs_allocated_count)
4040 goto set_vfta;
4041
4042 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4043
4044 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4045 u32 vlvf = rd32(E1000_VLVF(i));
4046
4047 /* pull VLAN ID from VLVF */
4048 vid = vlvf & VLAN_VID_MASK;
4049
4050 /* only concern ourselves with a certain range */
4051 if (vid < vid_start || vid >= vid_end)
4052 continue;
4053
4054 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4055 /* record VLAN ID in VFTA */
4056 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4057
4058 /* if PF is part of this then continue */
4059 if (test_bit(vid, adapter->active_vlans))
4060 continue;
4061 }
4062
4063 /* remove PF from the pool */
4064 bits = ~(1 << pf_id);
4065 bits &= rd32(E1000_VLVF(i));
4066 wr32(E1000_VLVF(i), bits);
4067 }
4068
4069set_vfta:
4070 /* extract values from active_vlans and write back to VFTA */
4071 for (i = VFTA_BLOCK_SIZE; i--;) {
4072 vid = (vfta_offset + i) * 32;
4073 word = vid / BITS_PER_LONG;
4074 bits = vid % BITS_PER_LONG;
4075
4076 vfta[i] |= adapter->active_vlans[word] >> bits;
4077
4078 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4079 }
4080}
4081
4082static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4083{
4084 u32 i;
4085
4086 /* We are not in VLAN promisc, nothing to do */
4087 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4088 return;
4089
4090 /* Set flag so we don't redo unnecessary work */
4091 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4092
4093 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4094 igb_scrub_vfta(adapter, i);
4095}
4096
68d480c4 4097/**
b980ac18
JK		 4098 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4099 * @netdev: network interface device structure
68d480c4 4100 *
b980ac18
JK		 4101 * The set_rx_mode entry point is called whenever the unicast or multicast
4102 * address lists or the network interface flags are updated. This routine is
4103 * responsible for configuring the hardware for proper unicast, multicast,
4104 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4105 **/
4106static void igb_set_rx_mode(struct net_device *netdev)
4107{
4108 struct igb_adapter *adapter = netdev_priv(netdev);
4109 struct e1000_hw *hw = &adapter->hw;
4110 unsigned int vfn = adapter->vfs_allocated_count;
16903caa 4111 u32 rctl = 0, vmolr = 0;
68d480c4
AD		 4112 int count;
4113
4114 /* Check for Promiscuous and All Multicast modes */
68d480c4 4115 if (netdev->flags & IFF_PROMISC) {
16903caa
AD		 4116 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
4117 vmolr |= E1000_VMOLR_ROPE | E1000_VMOLR_MPME;
68d480c4
AD		 4118 } else {
4119 if (netdev->flags & IFF_ALLMULTI) {
4120 rctl |= E1000_RCTL_MPE;
4121 vmolr |= E1000_VMOLR_MPME;
4122 } else {
b980ac18 4123 /* Write addresses to the MTA, if the attempt fails
25985edc 4124 * then we should just turn on promiscuous mode so
68d480c4
AD		 4125 * that we can at least receive multicast traffic
4126 */
4127 count = igb_write_mc_addr_list(netdev);
4128 if (count < 0) {
4129 rctl |= E1000_RCTL_MPE;
4130 vmolr |= E1000_VMOLR_MPME;
4131 } else if (count) {
4132 vmolr |= E1000_VMOLR_ROMPE;
4133 }
4134 }
b980ac18 4135 /* Write addresses to available RAR registers, if there is not
68d480c4 4136 * sufficient space to store all the addresses then enable
25985edc 4137 * unicast promiscuous mode
68d480c4
AD		 4138 */
4139 count = igb_write_uc_addr_list(netdev);
4140 if (count < 0) {
4141 rctl |= E1000_RCTL_UPE;
4142 vmolr |= E1000_VMOLR_ROPE;
4143 }
28fc06f5 4144 }
16903caa
AD		 4145
4146 /* enable VLAN filtering by default */
4147 rctl |= E1000_RCTL_VFE;
4148
4149 /* disable VLAN filtering for modes that require it */
4150 if ((netdev->flags & IFF_PROMISC) ||
4151 (netdev->features & NETIF_F_RXALL)) {
4152 /* if we fail to set all rules then just clear VFE */
4153 if (igb_vlan_promisc_enable(adapter))
4154 rctl &= ~E1000_RCTL_VFE;
4155 } else {
4156 igb_vlan_promisc_disable(adapter);
4157 }
4158
4159 /* update state of unicast, multicast, and VLAN filtering modes */
4160 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4161 E1000_RCTL_VFE);
68d480c4 4162 wr32(E1000_RCTL, rctl);
28fc06f5 4163
b980ac18 4164 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4165 * the VMOLR to enable the appropriate modes. Without this workaround
4166 * we will have issues with VLAN tag stripping not being done for frames
4167 * that are only arriving because we are the default pool
4168 */
f96a8a0b 4169 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4170 return;
9d5c8243 4171
68d480c4 4172 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4173 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
45693bcb
AD		 4174
4175 /* enable Rx jumbo frames, no need for restriction */
4176 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4177 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4178
68d480c4 4179 wr32(E1000_VMOLR(vfn), vmolr);
45693bcb
AD		 4180 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4181
28fc06f5 4182 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4183}
4184
13800469
GR		 4185static void igb_check_wvbr(struct igb_adapter *adapter)
4186{
4187 struct e1000_hw *hw = &adapter->hw;
4188 u32 wvbr = 0;
4189
4190 switch (hw->mac.type) {
4191 case e1000_82576:
4192 case e1000_i350:
81ad807b
CW		 4193 wvbr = rd32(E1000_WVBR);
4194 if (!wvbr)
13800469
GR		 4195 return;
4196 break;
4197 default:
4198 break;
4199 }
4200
4201 adapter->wvbr |= wvbr;
4202}
4203
4204#define IGB_STAGGERED_QUEUE_OFFSET 8
4205
4206static void igb_spoof_check(struct igb_adapter *adapter)
4207{
4208 int j;
4209
4210 if (!adapter->wvbr)
4211 return;
4212
9005df38 4213 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4214 if (adapter->wvbr & (1 << j) ||
4215 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4216 dev_warn(&adapter->pdev->dev,
4217 "Spoof event(s) detected on VF %d\n", j);
4218 adapter->wvbr &=
4219 ~((1 << j) |
4220 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4221 }
4222 }
4223}
4224
9d5c8243 4225/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4226 * the phy
4227 */
9d5c8243
AK		 4228static void igb_update_phy_info(unsigned long data)
4229{
4230 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4231 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4232}
4233
4d6b725e 4234/**
b980ac18
JK		 4235 * igb_has_link - check shared code for link and determine up/down
4236 * @adapter: pointer to driver private info
4d6b725e 4237 **/
3145535a 4238bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4239{
4240 struct e1000_hw *hw = &adapter->hw;
4241 bool link_active = false;
4d6b725e
AD		 4242
4243 /* get_link_status is set on LSC (link status) interrupt or
4244 * rx sequence error interrupt. get_link_status will stay
4245 * false until the e1000_check_for_link establishes link
4246 * for copper adapters ONLY
4247 */
4248 switch (hw->phy.media_type) {
4249 case e1000_media_type_copper:
e5c3370f
AA		 4250 if (!hw->mac.get_link_status)
4251 return true;
4d6b725e 4252 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4253 hw->mac.ops.check_for_link(hw);
4254 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4255 break;
4256 default:
4257 case e1000_media_type_unknown:
4258 break;
4259 }
4260
aa9b8cc4
AA		 4261 if (((hw->mac.type == e1000_i210) ||
4262 (hw->mac.type == e1000_i211)) &&
4263 (hw->phy.id == I210_I_PHY_ID)) {
4264 if (!netif_carrier_ok(adapter->netdev)) {
4265 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4266 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4267 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4268 adapter->link_check_timeout = jiffies;
4269 }
4270 }
4271
4d6b725e
AD		 4272 return link_active;
4273}
4274
563988dc
SA		 4275static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4276{
4277 bool ret = false;
4278 u32 ctrl_ext, thstat;
4279
f96a8a0b 4280 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4281 if (hw->mac.type == e1000_i350) {
4282 thstat = rd32(E1000_THSTAT);
4283 ctrl_ext = rd32(E1000_CTRL_EXT);
4284
4285 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4286 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4287 ret = !!(thstat & event);
563988dc
SA		 4288 }
4289
4290 return ret;
4291}
4292
1516f0a6
CW		 4293/**
4294 * igb_check_lvmmc - check for malformed packets received
4295 * and indicated in LVMMC register
4296 * @adapter: pointer to adapter
4297 **/
4298static void igb_check_lvmmc(struct igb_adapter *adapter)
4299{
4300 struct e1000_hw *hw = &adapter->hw;
4301 u32 lvmmc;
4302
4303 lvmmc = rd32(E1000_LVMMC);
4304 if (lvmmc) {
4305 if (unlikely(net_ratelimit())) {
4306 netdev_warn(adapter->netdev,
4307 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4308 lvmmc);
4309 }
4310 }
4311}
4312
9d5c8243 4313/**
b980ac18
JK		 4314 * igb_watchdog - Timer Call-back
4315 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4316 **/
4317static void igb_watchdog(unsigned long data)
4318{
4319 struct igb_adapter *adapter = (struct igb_adapter *)data;
4320 /* Do the rest outside of interrupt context */
4321 schedule_work(&adapter->watchdog_task);
4322}
4323
4324static void igb_watchdog_task(struct work_struct *work)
4325{
4326 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4327 struct igb_adapter,
4328 watchdog_task);
9d5c8243 4329 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4330 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4331 struct net_device *netdev = adapter->netdev;
563988dc 4332 u32 link;
7a6ea550 4333 int i;
56cec249 4334 u32 connsw;
9d5c8243 4335
4d6b725e 4336 link = igb_has_link(adapter);
aa9b8cc4
AA		 4337
4338 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4339 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4340 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4341 else
4342 link = false;
4343 }
4344
56cec249
CW		 4345 /* Force link down if we have fiber to swap to */
4346 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4347 if (hw->phy.media_type == e1000_media_type_copper) {
4348 connsw = rd32(E1000_CONNSW);
4349 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4350 link = 0;
4351 }
4352 }
9d5c8243 4353 if (link) {
2bdfc4e2
CW		 4354 /* Perform a reset if the media type changed. */
4355 if (hw->dev_spec._82575.media_changed) {
4356 hw->dev_spec._82575.media_changed = false;
4357 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4358 igb_reset(adapter);
4359 }
749ab2cd
YZ		 4360 /* Cancel scheduled suspend requests. */
4361 pm_runtime_resume(netdev->dev.parent);
4362
9d5c8243
AK		 4363 if (!netif_carrier_ok(netdev)) {
4364 u32 ctrl;
9005df38 4365
330a6d6a 4366 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4367 &adapter->link_speed,
4368 &adapter->link_duplex);
9d5c8243
AK		 4369
4370 ctrl = rd32(E1000_CTRL);
527d47c1 4371 /* Links status message must follow this format */
c75c4edf
CW		 4372 netdev_info(netdev,
4373 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4374 netdev->name,
4375 adapter->link_speed,
4376 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4377 "Full" : "Half",
4378 (ctrl & E1000_CTRL_TFCE) &&
4379 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4380 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4381 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4382
f4c01e96
CW		 4383 /* disable EEE if enabled */
4384 if ((adapter->flags & IGB_FLAG_EEE) &&
4385 (adapter->link_duplex == HALF_DUPLEX)) {
4386 dev_info(&adapter->pdev->dev,
4387 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4388 adapter->hw.dev_spec._82575.eee_disable = true;
4389 adapter->flags &= ~IGB_FLAG_EEE;
4390 }
4391
c0ba4778
KS		 4392 /* check if SmartSpeed worked */
4393 igb_check_downshift(hw);
4394 if (phy->speed_downgraded)
4395 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4396
563988dc 4397 /* check for thermal sensor event */
876d2d6f 4398 if (igb_thermal_sensor_event(hw,
d34a15ab 4399 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4400 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4401
d07f3e37 4402 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4403 adapter->tx_timeout_factor = 1;
4404 switch (adapter->link_speed) {
4405 case SPEED_10:
9d5c8243
AK		 4406 adapter->tx_timeout_factor = 14;
4407 break;
4408 case SPEED_100:
9d5c8243
AK		 4409 /* maybe add some timeout factor ? */
4410 break;
4411 }
4412
4413 netif_carrier_on(netdev);
9d5c8243 4414
4ae196df 4415 igb_ping_all_vfs(adapter);
17dc566c 4416 igb_check_vf_rate_limit(adapter);
4ae196df 4417
4b1a9877 4418 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4419 if (!test_bit(__IGB_DOWN, &adapter->state))
4420 mod_timer(&adapter->phy_info_timer,
4421 round_jiffies(jiffies + 2 * HZ));
4422 }
4423 } else {
4424 if (netif_carrier_ok(netdev)) {
4425 adapter->link_speed = 0;
4426 adapter->link_duplex = 0;
563988dc
SA		 4427
4428 /* check for thermal sensor event */
876d2d6f
JK		 4429 if (igb_thermal_sensor_event(hw,
4430 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4431 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4432 }
563988dc 4433
527d47c1 4434 /* Links status message must follow this format */
c75c4edf 4435 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4436 netdev->name);
9d5c8243 4437 netif_carrier_off(netdev);
4b1a9877 4438
4ae196df
AD		 4439 igb_ping_all_vfs(adapter);
4440
4b1a9877 4441 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4442 if (!test_bit(__IGB_DOWN, &adapter->state))
4443 mod_timer(&adapter->phy_info_timer,
4444 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4445
56cec249
CW		 4446 /* link is down, time to check for alternate media */
4447 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4448 igb_check_swap_media(adapter);
4449 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4450 schedule_work(&adapter->reset_task);
4451 /* return immediately */
4452 return;
4453 }
4454 }
749ab2cd
YZ		 4455 pm_schedule_suspend(netdev->dev.parent,
4456 MSEC_PER_SEC * 5);
56cec249
CW		 4457
4458 /* also check for alternate media here */
4459 } else if (!netif_carrier_ok(netdev) &&
4460 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4461 igb_check_swap_media(adapter);
4462 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4463 schedule_work(&adapter->reset_task);
4464 /* return immediately */
4465 return;
4466 }
9d5c8243
AK		 4467 }
4468 }
4469
12dcd86b
ED		 4470 spin_lock(&adapter->stats64_lock);
4471 igb_update_stats(adapter, &adapter->stats64);
4472 spin_unlock(&adapter->stats64_lock);
9d5c8243 4473
dbabb065 4474 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4475 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4476 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4477 /* We've lost link, so the controller stops DMA,
4478 * but we've got queued Tx work that's never going
4479 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4480 * (Do the reset outside of interrupt context).
4481 */
dbabb065
AD		 4482 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4483 adapter->tx_timeout_count++;
4484 schedule_work(&adapter->reset_task);
4485 /* return immediately since reset is imminent */
4486 return;
4487 }
9d5c8243 4488 }
9d5c8243 4489
dbabb065 4490 /* Force detection of hung controller every watchdog period */
6d095fa8 4491 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4492 }
f7ba205e 4493
b980ac18 4494 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4496 u32 eics = 0;
9005df38 4497
0d1ae7f4
AD		 4498 for (i = 0; i < adapter->num_q_vectors; i++)
4499 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4500 wr32(E1000_EICS, eics);
4501 } else {
4502 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4503 }
9d5c8243 4504
13800469 4505 igb_spoof_check(adapter);
fc580751 4506 igb_ptp_rx_hang(adapter);
13800469 4507
1516f0a6
CW		 4508 /* Check LVMMC register on i350/i354 only */
4509 if ((adapter->hw.mac.type == e1000_i350) ||
4510 (adapter->hw.mac.type == e1000_i354))
4511 igb_check_lvmmc(adapter);
4512
9d5c8243 4513 /* Reset the timer */
aa9b8cc4
AA		 4514 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4515 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4516 mod_timer(&adapter->watchdog_timer,
4517 round_jiffies(jiffies + HZ));
4518 else
4519 mod_timer(&adapter->watchdog_timer,
4520 round_jiffies(jiffies + 2 * HZ));
4521 }
9d5c8243
AK		 4522}
4523
4524enum latency_range {
4525 lowest_latency = 0,
4526 low_latency = 1,
4527 bulk_latency = 2,
4528 latency_invalid = 255
4529};
4530
6eb5a7f1 4531/**
b980ac18
JK		 4532 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4533 * @q_vector: pointer to q_vector
6eb5a7f1 4534 *
b980ac18
JK		 4535 * Stores a new ITR value based on strictly on packet size. This
4536 * algorithm is less sophisticated than that used in igb_update_itr,
4537 * due to the difficulty of synchronizing statistics across multiple
4538 * receive rings. The divisors and thresholds used by this function
4539 * were determined based on theoretical maximum wire speed and testing
4540 * data, in order to minimize response time while increasing bulk
4541 * throughput.
406d4965 4542 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4543 * NOTE: This function is called only when operating in a multiqueue
4544 * receive environment.
6eb5a7f1 4545 **/
047e0030 4546static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4547{
047e0030 4548 int new_val = q_vector->itr_val;
6eb5a7f1 4549 int avg_wire_size = 0;
047e0030 4550 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4551 unsigned int packets;
9d5c8243 4552
6eb5a7f1
AD		 4553 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4554 * ints/sec - ITR timer value of 120 ticks.
4555 */
4556 if (adapter->link_speed != SPEED_1000) {
0ba82994 4557 new_val = IGB_4K_ITR;
6eb5a7f1 4558 goto set_itr_val;
9d5c8243 4559 }
047e0030 4560
0ba82994
AD		 4561 packets = q_vector->rx.total_packets;
4562 if (packets)
4563 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4564
0ba82994
AD		 4565 packets = q_vector->tx.total_packets;
4566 if (packets)
4567 avg_wire_size = max_t(u32, avg_wire_size,
4568 q_vector->tx.total_bytes / packets);
047e0030
AD		 4569
4570 /* if avg_wire_size isn't set no work was done */
4571 if (!avg_wire_size)
4572 goto clear_counts;
9d5c8243 4573
6eb5a7f1
AD		 4574 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4575 avg_wire_size += 24;
4576
4577 /* Don't starve jumbo frames */
4578 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4579
6eb5a7f1
AD		 4580 /* Give a little boost to mid-size frames */
4581 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4582 new_val = avg_wire_size / 3;
4583 else
4584 new_val = avg_wire_size / 2;
9d5c8243 4585
0ba82994
AD		 4586 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4587 if (new_val < IGB_20K_ITR &&
4588 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4589 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4590 new_val = IGB_20K_ITR;
abe1c363 4591
6eb5a7f1 4592set_itr_val:
047e0030
AD		 4593 if (new_val != q_vector->itr_val) {
4594 q_vector->itr_val = new_val;
4595 q_vector->set_itr = 1;
9d5c8243 4596 }
6eb5a7f1 4597clear_counts:
0ba82994
AD		 4598 q_vector->rx.total_bytes = 0;
4599 q_vector->rx.total_packets = 0;
4600 q_vector->tx.total_bytes = 0;
4601 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4602}
4603
4604/**
b980ac18
JK		 4605 * igb_update_itr - update the dynamic ITR value based on statistics
4606 * @q_vector: pointer to q_vector
4607 * @ring_container: ring info to update the itr for
4608 *
4609 * Stores a new ITR value based on packets and byte
4610 * counts during the last interrupt. The advantage of per interrupt
4611 * computation is faster updates and more accurate ITR for the current
4612 * traffic pattern. Constants in this function were computed
4613 * based on theoretical maximum wire speed and thresholds were set based
4614 * on testing data as well as attempting to minimize response time
4615 * while increasing bulk throughput.
406d4965 4616 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4617 * NOTE: These calculations are only valid when operating in a single-
4618 * queue environment.
9d5c8243 4619 **/
0ba82994
AD		 4620static void igb_update_itr(struct igb_q_vector *q_vector,
4621 struct igb_ring_container *ring_container)
9d5c8243 4622{
0ba82994
AD		 4623 unsigned int packets = ring_container->total_packets;
4624 unsigned int bytes = ring_container->total_bytes;
4625 u8 itrval = ring_container->itr;
9d5c8243 4626
0ba82994 4627 /* no packets, exit with status unchanged */
9d5c8243 4628 if (packets == 0)
0ba82994 4629 return;
9d5c8243 4630
0ba82994 4631 switch (itrval) {
9d5c8243
AK		 4632 case lowest_latency:
4633 /* handle TSO and jumbo frames */
4634 if (bytes/packets > 8000)
0ba82994 4635 itrval = bulk_latency;
9d5c8243 4636 else if ((packets < 5) && (bytes > 512))
0ba82994 4637 itrval = low_latency;
9d5c8243
AK		 4638 break;
4639 case low_latency: /* 50 usec aka 20000 ints/s */
4640 if (bytes > 10000) {
4641 /* this if handles the TSO accounting */
d34a15ab 4642 if (bytes/packets > 8000)
0ba82994 4643 itrval = bulk_latency;
d34a15ab 4644 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4645 itrval = bulk_latency;
d34a15ab 4646 else if ((packets > 35))
0ba82994 4647 itrval = lowest_latency;
9d5c8243 4648 } else if (bytes/packets > 2000) {
0ba82994 4649 itrval = bulk_latency;
9d5c8243 4650 } else if (packets <= 2 && bytes < 512) {
0ba82994 4651 itrval = lowest_latency;
9d5c8243
AK		 4652 }
4653 break;
4654 case bulk_latency: /* 250 usec aka 4000 ints/s */
4655 if (bytes > 25000) {
4656 if (packets > 35)
0ba82994 4657 itrval = low_latency;
1e5c3d21 4658 } else if (bytes < 1500) {
0ba82994 4659 itrval = low_latency;
9d5c8243
AK		 4660 }
4661 break;
4662 }
4663
0ba82994
AD		 4664 /* clear work counters since we have the values we need */
4665 ring_container->total_bytes = 0;
4666 ring_container->total_packets = 0;
4667
4668 /* write updated itr to ring container */
4669 ring_container->itr = itrval;
9d5c8243
AK		 4670}
4671
0ba82994 4672static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4673{
0ba82994 4674 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4675 u32 new_itr = q_vector->itr_val;
0ba82994 4676 u8 current_itr = 0;
9d5c8243
AK		 4677
4678 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4679 if (adapter->link_speed != SPEED_1000) {
4680 current_itr = 0;
0ba82994 4681 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4682 goto set_itr_now;
4683 }
4684
0ba82994
AD		 4685 igb_update_itr(q_vector, &q_vector->tx);
4686 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4687
0ba82994 4688 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4689
6eb5a7f1 4690 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4691 if (current_itr == lowest_latency &&
4692 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4693 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4694 current_itr = low_latency;
4695
9d5c8243
AK		 4696 switch (current_itr) {
4697 /* counts and packets in update_itr are dependent on these numbers */
4698 case lowest_latency:
0ba82994 4699 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4700 break;
4701 case low_latency:
0ba82994 4702 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4703 break;
4704 case bulk_latency:
0ba82994 4705 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4706 break;
4707 default:
4708 break;
4709 }
4710
4711set_itr_now:
047e0030 4712 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4713 /* this attempts to bias the interrupt rate towards Bulk
4714 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4715 * increasing
4716 */
047e0030 4717 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4718 max((new_itr * q_vector->itr_val) /
4719 (new_itr + (q_vector->itr_val >> 2)),
4720 new_itr) : new_itr;
9d5c8243
AK		 4721 /* Don't write the value here; it resets the adapter's
4722 * internal timer, and causes us to delay far longer than
4723 * we should between interrupts. Instead, we write the ITR
4724 * value at the beginning of the next interrupt so the timing
4725 * ends up being correct.
4726 */
047e0030
AD		 4727 q_vector->itr_val = new_itr;
4728 q_vector->set_itr = 1;
9d5c8243 4729 }
9d5c8243
AK		 4730}
4731
c50b52a0
SH		 4732static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4733 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4734{
4735 struct e1000_adv_tx_context_desc *context_desc;
4736 u16 i = tx_ring->next_to_use;
4737
4738 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4739
4740 i++;
4741 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4742
4743 /* set bits to identify this as an advanced context descriptor */
4744 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4745
4746 /* For 82575, context index must be unique per ring. */
866cff06 4747 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4748 mss_l4len_idx |= tx_ring->reg_idx << 4;
4749
4750 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4751 context_desc->seqnum_seed = 0;
4752 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4753 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4754}
4755
7af40ad9
AD		 4756static int igb_tso(struct igb_ring *tx_ring,
4757 struct igb_tx_buffer *first,
4758 u8 *hdr_len)
9d5c8243 4759{
7af40ad9 4760 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4761 u32 vlan_macip_lens, type_tucmd;
4762 u32 mss_l4len_idx, l4len;
06c14e5a 4763 int err;
7d13a7d0 4764
ed6aa105
AD		 4765 if (skb->ip_summed != CHECKSUM_PARTIAL)
4766 return 0;
4767
7d13a7d0
AD		 4768 if (!skb_is_gso(skb))
4769 return 0;
9d5c8243 4770
06c14e5a
FR		 4771 err = skb_cow_head(skb, 0);
4772 if (err < 0)
4773 return err;
9d5c8243 4774
7d13a7d0
AD		 4775 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4776 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4777
7c4d16ff 4778 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4779 struct iphdr *iph = ip_hdr(skb);
4780 iph->tot_len = 0;
4781 iph->check = 0;
4782 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4783 iph->daddr, 0,
4784 IPPROTO_TCP,
4785 0);
7d13a7d0 4786 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4787 first->tx_flags |= IGB_TX_FLAGS_TSO |
4788 IGB_TX_FLAGS_CSUM |
4789 IGB_TX_FLAGS_IPV4;
8e1e8a47 4790 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4791 ipv6_hdr(skb)->payload_len = 0;
4792 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4793 &ipv6_hdr(skb)->daddr,
4794 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4795 first->tx_flags |= IGB_TX_FLAGS_TSO |
4796 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4797 }
4798
7af40ad9 4799 /* compute header lengths */
7d13a7d0
AD		 4800 l4len = tcp_hdrlen(skb);
4801 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4802
7af40ad9
AD		 4803 /* update gso size and bytecount with header size */
4804 first->gso_segs = skb_shinfo(skb)->gso_segs;
4805 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4806
9d5c8243 4807 /* MSS L4LEN IDX */
7d13a7d0
AD		 4808 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4809 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4810
7d13a7d0
AD		 4811 /* VLAN MACLEN IPLEN */
4812 vlan_macip_lens = skb_network_header_len(skb);
4813 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4814 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4815
7d13a7d0 4816 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4817
7d13a7d0 4818 return 1;
9d5c8243
AK		 4819}
4820
7af40ad9 4821static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4822{
7af40ad9 4823 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4824 u32 vlan_macip_lens = 0;
4825 u32 mss_l4len_idx = 0;
4826 u32 type_tucmd = 0;
9d5c8243 4827
7d13a7d0 4828 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4829 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4830 return;
7d13a7d0
AD		 4831 } else {
4832 u8 l4_hdr = 0;
9005df38 4833
7af40ad9 4834 switch (first->protocol) {
7c4d16ff 4835 case htons(ETH_P_IP):
7d13a7d0
AD		 4836 vlan_macip_lens |= skb_network_header_len(skb);
4837 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4838 l4_hdr = ip_hdr(skb)->protocol;
4839 break;
7c4d16ff 4840 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4841 vlan_macip_lens |= skb_network_header_len(skb);
4842 l4_hdr = ipv6_hdr(skb)->nexthdr;
4843 break;
4844 default:
4845 if (unlikely(net_ratelimit())) {
4846 dev_warn(tx_ring->dev,
b980ac18
JK		 4847 "partial checksum but proto=%x!\n",
4848 first->protocol);
fa4a7ef3 4849 }
7d13a7d0
AD		 4850 break;
4851 }
fa4a7ef3 4852
7d13a7d0
AD		 4853 switch (l4_hdr) {
4854 case IPPROTO_TCP:
4855 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4856 mss_l4len_idx = tcp_hdrlen(skb) <<
4857 E1000_ADVTXD_L4LEN_SHIFT;
4858 break;
4859 case IPPROTO_SCTP:
4860 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4861 mss_l4len_idx = sizeof(struct sctphdr) <<
4862 E1000_ADVTXD_L4LEN_SHIFT;
4863 break;
4864 case IPPROTO_UDP:
4865 mss_l4len_idx = sizeof(struct udphdr) <<
4866 E1000_ADVTXD_L4LEN_SHIFT;
4867 break;
4868 default:
4869 if (unlikely(net_ratelimit())) {
4870 dev_warn(tx_ring->dev,
b980ac18
JK		 4871 "partial checksum but l4 proto=%x!\n",
4872 l4_hdr);
44b0cda3 4873 }
7d13a7d0 4874 break;
9d5c8243 4875 }
7af40ad9
AD		 4876
4877 /* update TX checksum flag */
4878 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4879 }
9d5c8243 4880
7d13a7d0 4881 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4882 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4883
7d13a7d0 4884 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4885}
4886
1d9daf45
AD		 4887#define IGB_SET_FLAG(_input, _flag, _result) \
4888 ((_flag <= _result) ? \
4889 ((u32)(_input & _flag) * (_result / _flag)) : \
4890 ((u32)(_input & _flag) / (_flag / _result)))
4891
4892static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4893{
4894 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4895 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4896 E1000_ADVTXD_DCMD_DEXT |
4897 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4898
4899 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4900 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4901 (E1000_ADVTXD_DCMD_VLE));
4902
4903 /* set segmentation bits for TSO */
4904 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4905 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4906
4907 /* set timestamp bit if present */
1d9daf45
AD		 4908 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4909 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4910
1d9daf45
AD		 4911 /* insert frame checksum */
4912 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4913
4914 return cmd_type;
4915}
4916
7af40ad9
AD		 4917static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4918 union e1000_adv_tx_desc *tx_desc,
4919 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4920{
4921 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4922
1d9daf45
AD		 4923 /* 82575 requires a unique index per ring */
4924 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4925 olinfo_status |= tx_ring->reg_idx << 4;
4926
4927 /* insert L4 checksum */
1d9daf45
AD		 4928 olinfo_status |= IGB_SET_FLAG(tx_flags,
4929 IGB_TX_FLAGS_CSUM,
4930 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4931
1d9daf45
AD		 4932 /* insert IPv4 checksum */
4933 olinfo_status |= IGB_SET_FLAG(tx_flags,
4934 IGB_TX_FLAGS_IPV4,
4935 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4936
7af40ad9 4937 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4938}
4939
6f19e12f
DM		 4940static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4941{
4942 struct net_device *netdev = tx_ring->netdev;
4943
4944 netif_stop_subqueue(netdev, tx_ring->queue_index);
4945
4946 /* Herbert's original patch had:
4947 * smp_mb__after_netif_stop_queue();
4948 * but since that doesn't exist yet, just open code it.
4949 */
4950 smp_mb();
4951
4952 /* We need to check again in a case another CPU has just
4953 * made room available.
4954 */
4955 if (igb_desc_unused(tx_ring) < size)
4956 return -EBUSY;
4957
4958 /* A reprieve! */
4959 netif_wake_subqueue(netdev, tx_ring->queue_index);
4960
4961 u64_stats_update_begin(&tx_ring->tx_syncp2);
4962 tx_ring->tx_stats.restart_queue2++;
4963 u64_stats_update_end(&tx_ring->tx_syncp2);
4964
4965 return 0;
4966}
4967
4968static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4969{
4970 if (igb_desc_unused(tx_ring) >= size)
4971 return 0;
4972 return __igb_maybe_stop_tx(tx_ring, size);
4973}
4974
7af40ad9
AD		 4975static void igb_tx_map(struct igb_ring *tx_ring,
4976 struct igb_tx_buffer *first,
ebe42d16 4977 const u8 hdr_len)
9d5c8243 4978{
7af40ad9 4979 struct sk_buff *skb = first->skb;
c9f14bf3 4980 struct igb_tx_buffer *tx_buffer;
ebe42d16 4981 union e1000_adv_tx_desc *tx_desc;
80d0759e 4982 struct skb_frag_struct *frag;
ebe42d16 4983 dma_addr_t dma;
80d0759e 4984 unsigned int data_len, size;
7af40ad9 4985 u32 tx_flags = first->tx_flags;
1d9daf45 4986 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4987 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4988
4989 tx_desc = IGB_TX_DESC(tx_ring, i);
4990
80d0759e
AD		 4991 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4992
4993 size = skb_headlen(skb);
4994 data_len = skb->data_len;
ebe42d16
AD		 4995
4996 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4997
80d0759e
AD		 4998 tx_buffer = first;
4999
5000 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5001 if (dma_mapping_error(tx_ring->dev, dma))
5002 goto dma_error;
5003
5004 /* record length, and DMA address */
5005 dma_unmap_len_set(tx_buffer, len, size);
5006 dma_unmap_addr_set(tx_buffer, dma, dma);
5007
5008 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 5009
ebe42d16
AD		 5010 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5011 tx_desc->read.cmd_type_len =
1d9daf45 5012 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 5013
5014 i++;
5015 tx_desc++;
5016 if (i == tx_ring->count) {
5017 tx_desc = IGB_TX_DESC(tx_ring, 0);
5018 i = 0;
5019 }
80d0759e 5020 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 5021
5022 dma += IGB_MAX_DATA_PER_TXD;
5023 size -= IGB_MAX_DATA_PER_TXD;
5024
ebe42d16
AD		 5025 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5026 }
5027
5028 if (likely(!data_len))
5029 break;
2bbfebe2 5030
1d9daf45 5031 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 5032
65689fef 5033 i++;
ebe42d16
AD		 5034 tx_desc++;
5035 if (i == tx_ring->count) {
5036 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 5037 i = 0;
ebe42d16 5038 }
80d0759e 5039 tx_desc->read.olinfo_status = 0;
65689fef 5040
9e903e08 5041 size = skb_frag_size(frag);
ebe42d16
AD		 5042 data_len -= size;
5043
5044 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 5045 size, DMA_TO_DEVICE);
6366ad33 5046
c9f14bf3 5047 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 5048 }
5049
ebe42d16 5050 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 5051 cmd_type |= size | IGB_TXD_DCMD;
5052 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 5053
80d0759e
AD		 5054 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5055
8542db05
AD		 5056 /* set the timestamp */
5057 first->time_stamp = jiffies;
5058
b980ac18 5059 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 5060 * are new descriptors to fetch. (Only applicable for weak-ordered
5061 * memory model archs, such as IA-64).
5062 *
5063 * We also need this memory barrier to make certain all of the
5064 * status bits have been updated before next_to_watch is written.
5065 */
5066 wmb();
5067
8542db05 5068 /* set next_to_watch value indicating a packet is present */
ebe42d16 5069 first->next_to_watch = tx_desc;
9d5c8243 5070
ebe42d16
AD		 5071 i++;
5072 if (i == tx_ring->count)
5073 i = 0;
6366ad33 5074
ebe42d16 5075 tx_ring->next_to_use = i;
6366ad33 5076
6f19e12f
DM		 5077 /* Make sure there is space in the ring for the next send. */
5078 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5079
5080 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 5081 writel(i, tx_ring->tail);
5082
5083 /* we need this if more than one processor can write to our tail
5084 * at a time, it synchronizes IO on IA64/Altix systems
5085 */
5086 mmiowb();
5087 }
ebe42d16
AD		 5088 return;
5089
5090dma_error:
5091 dev_err(tx_ring->dev, "TX DMA map failed\n");
5092
5093 /* clear dma mappings for failed tx_buffer_info map */
5094 for (;;) {
c9f14bf3
AD		 5095 tx_buffer = &tx_ring->tx_buffer_info[i];
5096 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5097 if (tx_buffer == first)
ebe42d16 5098 break;
a77ff709
NN		 5099 if (i == 0)
5100 i = tx_ring->count;
6366ad33 5101 i--;
6366ad33
AD		 5102 }
5103
9d5c8243 5104 tx_ring->next_to_use = i;
9d5c8243
AK		 5105}
5106
cd392f5c
AD		 5107netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5108 struct igb_ring *tx_ring)
9d5c8243 5109{
8542db05 5110 struct igb_tx_buffer *first;
ebe42d16 5111 int tso;
91d4ee33 5112 u32 tx_flags = 0;
2ee52ad4 5113 unsigned short f;
21ba6fe1 5114 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5115 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5116 u8 hdr_len = 0;
9d5c8243 5117
21ba6fe1
AD		 5118 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5119 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5120 * + 2 desc gap to keep tail from touching head,
9d5c8243 5121 * + 1 desc for context descriptor,
21ba6fe1
AD		 5122 * otherwise try next time
5123 */
2ee52ad4
AD		 5124 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5125 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5126
5127 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5128 /* this is a hard error */
9d5c8243
AK		 5129 return NETDEV_TX_BUSY;
5130 }
33af6bcc 5131
7af40ad9
AD		 5132 /* record the location of the first descriptor for this packet */
5133 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5134 first->skb = skb;
5135 first->bytecount = skb->len;
5136 first->gso_segs = 1;
5137
b646c22e
AD		 5138 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5139 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5140
ed4420a3
JK		 5141 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5142 &adapter->state)) {
b646c22e
AD		 5143 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5144 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5145
5146 adapter->ptp_tx_skb = skb_get(skb);
5147 adapter->ptp_tx_start = jiffies;
5148 if (adapter->hw.mac.type == e1000_82576)
5149 schedule_work(&adapter->ptp_tx_work);
5150 }
33af6bcc 5151 }
9d5c8243 5152
afc835d1
JK		 5153 skb_tx_timestamp(skb);
5154
df8a39de 5155 if (skb_vlan_tag_present(skb)) {
9d5c8243 5156 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5157 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5158 }
5159
7af40ad9
AD		 5160 /* record initial flags and protocol */
5161 first->tx_flags = tx_flags;
5162 first->protocol = protocol;
cdfd01fc 5163
7af40ad9
AD		 5164 tso = igb_tso(tx_ring, first, &hdr_len);
5165 if (tso < 0)
7d13a7d0 5166 goto out_drop;
7af40ad9
AD		 5167 else if (!tso)
5168 igb_tx_csum(tx_ring, first);
9d5c8243 5169
7af40ad9 5170 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5171
9d5c8243 5172 return NETDEV_TX_OK;
7d13a7d0
AD		 5173
5174out_drop:
7af40ad9
AD		 5175 igb_unmap_and_free_tx_resource(tx_ring, first);
5176
7d13a7d0 5177 return NETDEV_TX_OK;
9d5c8243
AK		 5178}
5179
0b725a2c
DM		 5180static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5181 struct sk_buff *skb)
1cc3bd87 5182{
0b725a2c
DM		 5183 unsigned int r_idx = skb->queue_mapping;
5184
1cc3bd87
AD		 5185 if (r_idx >= adapter->num_tx_queues)
5186 r_idx = r_idx % adapter->num_tx_queues;
5187
5188 return adapter->tx_ring[r_idx];
5189}
5190
cd392f5c
AD		 5191static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5192 struct net_device *netdev)
9d5c8243
AK		 5193{
5194 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5195
5196 if (test_bit(__IGB_DOWN, &adapter->state)) {
5197 dev_kfree_skb_any(skb);
5198 return NETDEV_TX_OK;
5199 }
5200
5201 if (skb->len <= 0) {
5202 dev_kfree_skb_any(skb);
5203 return NETDEV_TX_OK;
5204 }
5205
b980ac18 5206 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5207 * in order to meet this minimum size requirement.
5208 */
a94d9e22
AD		 5209 if (skb_put_padto(skb, 17))
5210 return NETDEV_TX_OK;
9d5c8243 5211
1cc3bd87 5212 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5213}
5214
5215/**
b980ac18
JK		 5216 * igb_tx_timeout - Respond to a Tx Hang
5217 * @netdev: network interface device structure
9d5c8243
AK		 5218 **/
5219static void igb_tx_timeout(struct net_device *netdev)
5220{
5221 struct igb_adapter *adapter = netdev_priv(netdev);
5222 struct e1000_hw *hw = &adapter->hw;
5223
5224 /* Do the reset outside of interrupt context */
5225 adapter->tx_timeout_count++;
f7ba205e 5226
06218a8d 5227 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5228 hw->dev_spec._82575.global_device_reset = true;
5229
9d5c8243 5230 schedule_work(&adapter->reset_task);
265de409
AD		 5231 wr32(E1000_EICS,
5232 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5233}
5234
5235static void igb_reset_task(struct work_struct *work)
5236{
5237 struct igb_adapter *adapter;
5238 adapter = container_of(work, struct igb_adapter, reset_task);
5239
c97ec42a
TI		 5240 igb_dump(adapter);
5241 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5242 igb_reinit_locked(adapter);
5243}
5244
5245/**
b980ac18
JK		 5246 * igb_get_stats64 - Get System Network Statistics
5247 * @netdev: network interface device structure
5248 * @stats: rtnl_link_stats64 pointer
9d5c8243 5249 **/
12dcd86b 5250static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5251 struct rtnl_link_stats64 *stats)
9d5c8243 5252{
12dcd86b
ED		 5253 struct igb_adapter *adapter = netdev_priv(netdev);
5254
5255 spin_lock(&adapter->stats64_lock);
5256 igb_update_stats(adapter, &adapter->stats64);
5257 memcpy(stats, &adapter->stats64, sizeof(*stats));
5258 spin_unlock(&adapter->stats64_lock);
5259
5260 return stats;
9d5c8243
AK		 5261}
5262
5263/**
b980ac18
JK		 5264 * igb_change_mtu - Change the Maximum Transfer Unit
5265 * @netdev: network interface device structure
5266 * @new_mtu: new value for maximum frame size
9d5c8243 5267 *
b980ac18 5268 * Returns 0 on success, negative on failure
9d5c8243
AK		 5269 **/
5270static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5271{
5272 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5273 struct pci_dev *pdev = adapter->pdev;
153285f9 5274 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5275
c809d227 5276 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5277 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5278 return -EINVAL;
5279 }
5280
153285f9 5281#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5282 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5283 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5284 return -EINVAL;
5285 }
5286
2ccd994c
AD		 5287 /* adjust max frame to be at least the size of a standard frame */
5288 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5289 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5290
9d5c8243 5291 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5292 usleep_range(1000, 2000);
73cd78f1 5293
9d5c8243
AK		 5294 /* igb_down has a dependency on max_frame_size */
5295 adapter->max_frame_size = max_frame;
559e9c49 5296
4c844851
AD		 5297 if (netif_running(netdev))
5298 igb_down(adapter);
9d5c8243 5299
090b1795 5300 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5301 netdev->mtu, new_mtu);
5302 netdev->mtu = new_mtu;
5303
5304 if (netif_running(netdev))
5305 igb_up(adapter);
5306 else
5307 igb_reset(adapter);
5308
5309 clear_bit(__IGB_RESETTING, &adapter->state);
5310
5311 return 0;
5312}
5313
5314/**
b980ac18
JK		 5315 * igb_update_stats - Update the board statistics counters
5316 * @adapter: board private structure
9d5c8243 5317 **/
12dcd86b
ED		 5318void igb_update_stats(struct igb_adapter *adapter,
5319 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5320{
5321 struct e1000_hw *hw = &adapter->hw;
5322 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5323 u32 reg, mpc;
3f9c0164
AD		 5324 int i;
5325 u64 bytes, packets;
12dcd86b
ED		 5326 unsigned int start;
5327 u64 _bytes, _packets;
9d5c8243 5328
b980ac18 5329 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5330 * connection is down.
5331 */
5332 if (adapter->link_speed == 0)
5333 return;
5334 if (pci_channel_offline(pdev))
5335 return;
5336
3f9c0164
AD		 5337 bytes = 0;
5338 packets = 0;
7f90128e
AA		 5339
5340 rcu_read_lock();
3f9c0164 5341 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5342 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5343 u32 rqdpc = rd32(E1000_RQDPC(i));
5344 if (hw->mac.type >= e1000_i210)
5345 wr32(E1000_RQDPC(i), 0);
12dcd86b 5346
ae1c07a6
AD		 5347 if (rqdpc) {
5348 ring->rx_stats.drops += rqdpc;
5349 net_stats->rx_fifo_errors += rqdpc;
5350 }
12dcd86b
ED		 5351
5352 do {
57a7744e 5353 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5354 _bytes = ring->rx_stats.bytes;
5355 _packets = ring->rx_stats.packets;
57a7744e 5356 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5357 bytes += _bytes;
5358 packets += _packets;
3f9c0164
AD		 5359 }
5360
128e45eb
AD		 5361 net_stats->rx_bytes = bytes;
5362 net_stats->rx_packets = packets;
3f9c0164
AD		 5363
5364 bytes = 0;
5365 packets = 0;
5366 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5367 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5368 do {
57a7744e 5369 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5370 _bytes = ring->tx_stats.bytes;
5371 _packets = ring->tx_stats.packets;
57a7744e 5372 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5373 bytes += _bytes;
5374 packets += _packets;
3f9c0164 5375 }
128e45eb
AD		 5376 net_stats->tx_bytes = bytes;
5377 net_stats->tx_packets = packets;
7f90128e 5378 rcu_read_unlock();
3f9c0164
AD		 5379
5380 /* read stats registers */
9d5c8243
AK		 5381 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5382 adapter->stats.gprc += rd32(E1000_GPRC);
5383 adapter->stats.gorc += rd32(E1000_GORCL);
5384 rd32(E1000_GORCH); /* clear GORCL */
5385 adapter->stats.bprc += rd32(E1000_BPRC);
5386 adapter->stats.mprc += rd32(E1000_MPRC);
5387 adapter->stats.roc += rd32(E1000_ROC);
5388
5389 adapter->stats.prc64 += rd32(E1000_PRC64);
5390 adapter->stats.prc127 += rd32(E1000_PRC127);
5391 adapter->stats.prc255 += rd32(E1000_PRC255);
5392 adapter->stats.prc511 += rd32(E1000_PRC511);
5393 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5394 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5395 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5396 adapter->stats.sec += rd32(E1000_SEC);
5397
fa3d9a6d
MW		 5398 mpc = rd32(E1000_MPC);
5399 adapter->stats.mpc += mpc;
5400 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5401 adapter->stats.scc += rd32(E1000_SCC);
5402 adapter->stats.ecol += rd32(E1000_ECOL);
5403 adapter->stats.mcc += rd32(E1000_MCC);
5404 adapter->stats.latecol += rd32(E1000_LATECOL);
5405 adapter->stats.dc += rd32(E1000_DC);
5406 adapter->stats.rlec += rd32(E1000_RLEC);
5407 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5408 adapter->stats.xontxc += rd32(E1000_XONTXC);
5409 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5410 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5411 adapter->stats.fcruc += rd32(E1000_FCRUC);
5412 adapter->stats.gptc += rd32(E1000_GPTC);
5413 adapter->stats.gotc += rd32(E1000_GOTCL);
5414 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5415 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5416 adapter->stats.ruc += rd32(E1000_RUC);
5417 adapter->stats.rfc += rd32(E1000_RFC);
5418 adapter->stats.rjc += rd32(E1000_RJC);
5419 adapter->stats.tor += rd32(E1000_TORH);
5420 adapter->stats.tot += rd32(E1000_TOTH);
5421 adapter->stats.tpr += rd32(E1000_TPR);
5422
5423 adapter->stats.ptc64 += rd32(E1000_PTC64);
5424 adapter->stats.ptc127 += rd32(E1000_PTC127);
5425 adapter->stats.ptc255 += rd32(E1000_PTC255);
5426 adapter->stats.ptc511 += rd32(E1000_PTC511);
5427 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5428 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5429
5430 adapter->stats.mptc += rd32(E1000_MPTC);
5431 adapter->stats.bptc += rd32(E1000_BPTC);
5432
2d0b0f69
NN		 5433 adapter->stats.tpt += rd32(E1000_TPT);
5434 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5435
5436 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5437 /* read internal phy specific stats */
5438 reg = rd32(E1000_CTRL_EXT);
5439 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5440 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5441
5442 /* this stat has invalid values on i210/i211 */
5443 if ((hw->mac.type != e1000_i210) &&
5444 (hw->mac.type != e1000_i211))
5445 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5446 }
5447
9d5c8243
AK		 5448 adapter->stats.tsctc += rd32(E1000_TSCTC);
5449 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5450
5451 adapter->stats.iac += rd32(E1000_IAC);
5452 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5453 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5454 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5455 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5456 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5457 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5458 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5459 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5460
5461 /* Fill out the OS statistics structure */
128e45eb
AD		 5462 net_stats->multicast = adapter->stats.mprc;
5463 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5464
5465 /* Rx Errors */
5466
5467 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5468 * our own version based on RUC and ROC
5469 */
128e45eb 5470 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5471 adapter->stats.crcerrs + adapter->stats.algnerrc +
5472 adapter->stats.ruc + adapter->stats.roc +
5473 adapter->stats.cexterr;
128e45eb
AD		 5474 net_stats->rx_length_errors = adapter->stats.ruc +
5475 adapter->stats.roc;
5476 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5477 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5478 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5479
5480 /* Tx Errors */
128e45eb
AD		 5481 net_stats->tx_errors = adapter->stats.ecol +
5482 adapter->stats.latecol;
5483 net_stats->tx_aborted_errors = adapter->stats.ecol;
5484 net_stats->tx_window_errors = adapter->stats.latecol;
5485 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5486
5487 /* Tx Dropped needs to be maintained elsewhere */
5488
9d5c8243
AK		 5489 /* Management Stats */
5490 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5491 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5492 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5493
5494 /* OS2BMC Stats */
5495 reg = rd32(E1000_MANC);
5496 if (reg & E1000_MANC_EN_BMC2OS) {
5497 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5498 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5499 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5500 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5501 }
9d5c8243
AK		 5502}
5503
61d7f75f
RC		 5504static void igb_tsync_interrupt(struct igb_adapter *adapter)
5505{
5506 struct e1000_hw *hw = &adapter->hw;
00c65578 5507 struct ptp_clock_event event;
40c9b079 5508 struct timespec64 ts;
720db4ff 5509 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5510
5511 if (tsicr & TSINTR_SYS_WRAP) {
5512 event.type = PTP_CLOCK_PPS;
5513 if (adapter->ptp_caps.pps)
5514 ptp_clock_event(adapter->ptp_clock, &event);
5515 else
5516 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5517 ack |= TSINTR_SYS_WRAP;
5518 }
61d7f75f
RC		 5519
5520 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5521 /* retrieve hardware timestamp */
5522 schedule_work(&adapter->ptp_tx_work);
00c65578 5523 ack |= E1000_TSICR_TXTS;
61d7f75f 5524 }
00c65578 5525
720db4ff
RC		 5526 if (tsicr & TSINTR_TT0) {
5527 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5528 ts = timespec64_add(adapter->perout[0].start,
5529 adapter->perout[0].period);
5530 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5531 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5532 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5533 tsauxc = rd32(E1000_TSAUXC);
5534 tsauxc |= TSAUXC_EN_TT0;
5535 wr32(E1000_TSAUXC, tsauxc);
5536 adapter->perout[0].start = ts;
5537 spin_unlock(&adapter->tmreg_lock);
5538 ack |= TSINTR_TT0;
5539 }
5540
5541 if (tsicr & TSINTR_TT1) {
5542 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5543 ts = timespec64_add(adapter->perout[1].start,
5544 adapter->perout[1].period);
720db4ff 5545 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5546 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5547 tsauxc = rd32(E1000_TSAUXC);
5548 tsauxc |= TSAUXC_EN_TT1;
5549 wr32(E1000_TSAUXC, tsauxc);
5550 adapter->perout[1].start = ts;
5551 spin_unlock(&adapter->tmreg_lock);
5552 ack |= TSINTR_TT1;
5553 }
5554
5555 if (tsicr & TSINTR_AUTT0) {
5556 nsec = rd32(E1000_AUXSTMPL0);
5557 sec = rd32(E1000_AUXSTMPH0);
5558 event.type = PTP_CLOCK_EXTTS;
5559 event.index = 0;
5560 event.timestamp = sec * 1000000000ULL + nsec;
5561 ptp_clock_event(adapter->ptp_clock, &event);
5562 ack |= TSINTR_AUTT0;
5563 }
5564
5565 if (tsicr & TSINTR_AUTT1) {
5566 nsec = rd32(E1000_AUXSTMPL1);
5567 sec = rd32(E1000_AUXSTMPH1);
5568 event.type = PTP_CLOCK_EXTTS;
5569 event.index = 1;
5570 event.timestamp = sec * 1000000000ULL + nsec;
5571 ptp_clock_event(adapter->ptp_clock, &event);
5572 ack |= TSINTR_AUTT1;
5573 }
5574
00c65578
RC		 5575 /* acknowledge the interrupts */
5576 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5577}
5578
9d5c8243
AK		 5579static irqreturn_t igb_msix_other(int irq, void *data)
5580{
047e0030 5581 struct igb_adapter *adapter = data;
9d5c8243 5582 struct e1000_hw *hw = &adapter->hw;
844290e5 5583 u32 icr = rd32(E1000_ICR);
844290e5 5584 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5585
7f081d40
AD		 5586 if (icr & E1000_ICR_DRSTA)
5587 schedule_work(&adapter->reset_task);
5588
047e0030 5589 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5590 /* HW is reporting DMA is out of sync */
5591 adapter->stats.doosync++;
13800469
GR		 5592 /* The DMA Out of Sync is also indication of a spoof event
5593 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5594 * see if it is really a spoof event.
5595 */
13800469 5596 igb_check_wvbr(adapter);
dda0e083 5597 }
eebbbdba 5598
4ae196df
AD		 5599 /* Check for a mailbox event */
5600 if (icr & E1000_ICR_VMMB)
5601 igb_msg_task(adapter);
5602
5603 if (icr & E1000_ICR_LSC) {
5604 hw->mac.get_link_status = 1;
5605 /* guard against interrupt when we're going down */
5606 if (!test_bit(__IGB_DOWN, &adapter->state))
5607 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5608 }
5609
61d7f75f
RC		 5610 if (icr & E1000_ICR_TS)
5611 igb_tsync_interrupt(adapter);
1f6e8178 5612
844290e5 5613 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5614
5615 return IRQ_HANDLED;
5616}
5617
047e0030 5618static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5619{
26b39276 5620 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5621 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5622
047e0030
AD		 5623 if (!q_vector->set_itr)
5624 return;
73cd78f1 5625
047e0030
AD		 5626 if (!itr_val)
5627 itr_val = 0x4;
661086df 5628
26b39276
AD		 5629 if (adapter->hw.mac.type == e1000_82575)
5630 itr_val |= itr_val << 16;
661086df 5631 else
0ba82994 5632 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5633
047e0030
AD		 5634 writel(itr_val, q_vector->itr_register);
5635 q_vector->set_itr = 0;
6eb5a7f1
AD		 5636}
5637
047e0030 5638static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5639{
047e0030 5640 struct igb_q_vector *q_vector = data;
9d5c8243 5641
047e0030
AD		 5642 /* Write the ITR value calculated from the previous interrupt. */
5643 igb_write_itr(q_vector);
9d5c8243 5644
047e0030 5645 napi_schedule(&q_vector->napi);
844290e5 5646
047e0030 5647 return IRQ_HANDLED;
fe4506b6
JC		 5648}
5649
421e02f0 5650#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5651static void igb_update_tx_dca(struct igb_adapter *adapter,
5652 struct igb_ring *tx_ring,
5653 int cpu)
5654{
5655 struct e1000_hw *hw = &adapter->hw;
5656 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5657
5658 if (hw->mac.type != e1000_82575)
5659 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5660
b980ac18 5661 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5662 * DCA is enabled. This is due to a known issue in some chipsets
5663 * which will cause the DCA tag to be cleared.
5664 */
5665 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5666 E1000_DCA_TXCTRL_DATA_RRO_EN |
5667 E1000_DCA_TXCTRL_DESC_DCA_EN;
5668
5669 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5670}
5671
5672static void igb_update_rx_dca(struct igb_adapter *adapter,
5673 struct igb_ring *rx_ring,
5674 int cpu)
5675{
5676 struct e1000_hw *hw = &adapter->hw;
5677 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5678
5679 if (hw->mac.type != e1000_82575)
5680 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5681
b980ac18 5682 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5683 * DCA is enabled. This is due to a known issue in some chipsets
5684 * which will cause the DCA tag to be cleared.
5685 */
5686 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5687 E1000_DCA_RXCTRL_DESC_DCA_EN;
5688
5689 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5690}
5691
047e0030 5692static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5693{
047e0030 5694 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5695 int cpu = get_cpu();
fe4506b6 5696
047e0030
AD		 5697 if (q_vector->cpu == cpu)
5698 goto out_no_update;
5699
6a05004a
AD		 5700 if (q_vector->tx.ring)
5701 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5702
5703 if (q_vector->rx.ring)
5704 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5705
047e0030
AD		 5706 q_vector->cpu = cpu;
5707out_no_update:
fe4506b6
JC		 5708 put_cpu();
5709}
5710
5711static void igb_setup_dca(struct igb_adapter *adapter)
5712{
7e0e99ef 5713 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5714 int i;
5715
7dfc16fa 5716 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5717 return;
5718
7e0e99ef
AD		 5719 /* Always use CB2 mode, difference is masked in the CB driver. */
5720 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5721
047e0030 5722 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5723 adapter->q_vector[i]->cpu = -1;
5724 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5725 }
5726}
5727
5728static int __igb_notify_dca(struct device *dev, void *data)
5729{
5730 struct net_device *netdev = dev_get_drvdata(dev);
5731 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5732 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5733 struct e1000_hw *hw = &adapter->hw;
5734 unsigned long event = *(unsigned long *)data;
5735
5736 switch (event) {
5737 case DCA_PROVIDER_ADD:
5738 /* if already enabled, don't do it again */
7dfc16fa 5739 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5740 break;
fe4506b6 5741 if (dca_add_requester(dev) == 0) {
bbd98fe4 5742 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5743 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5744 igb_setup_dca(adapter);
5745 break;
5746 }
5747 /* Fall Through since DCA is disabled. */
5748 case DCA_PROVIDER_REMOVE:
7dfc16fa 5749 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5750 /* without this a class_device is left
b980ac18
JK		 5751 * hanging around in the sysfs model
5752 */
fe4506b6 5753 dca_remove_requester(dev);
090b1795 5754 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5755 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5756 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5757 }
5758 break;
5759 }
bbd98fe4 5760
fe4506b6 5761 return 0;
9d5c8243
AK		 5762}
5763
fe4506b6 5764static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5765 void *p)
fe4506b6
JC		 5766{
5767 int ret_val;
5768
5769 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5770 __igb_notify_dca);
fe4506b6
JC		 5771
5772 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5773}
421e02f0 5774#endif /* CONFIG_IGB_DCA */
9d5c8243 5775
0224d663
GR		 5776#ifdef CONFIG_PCI_IOV
5777static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5778{
5779 unsigned char mac_addr[ETH_ALEN];
0224d663 5780
5ac6f91d 5781 eth_zero_addr(mac_addr);
0224d663
GR		 5782 igb_set_vf_mac(adapter, vf, mac_addr);
5783
70ea4783
LL		 5784 /* By default spoof check is enabled for all VFs */
5785 adapter->vf_data[vf].spoofchk_enabled = true;
5786
f557147c 5787 return 0;
0224d663
GR		 5788}
5789
0224d663 5790#endif
4ae196df
AD		 5791static void igb_ping_all_vfs(struct igb_adapter *adapter)
5792{
5793 struct e1000_hw *hw = &adapter->hw;
5794 u32 ping;
5795 int i;
5796
5797 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5798 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5799 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5800 ping |= E1000_VT_MSGTYPE_CTS;
5801 igb_write_mbx(hw, &ping, 1, i);
5802 }
5803}
5804
7d5753f0
AD		 5805static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5806{
5807 struct e1000_hw *hw = &adapter->hw;
5808 u32 vmolr = rd32(E1000_VMOLR(vf));
5809 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5810
d85b9004 5811 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5812 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5813 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5814
5815 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5816 vmolr |= E1000_VMOLR_MPME;
d85b9004 5817 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5818 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5819 } else {
b980ac18 5820 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5821 * flag we need to write the hashes to the MTA as this step
5822 * was previously skipped
5823 */
5824 if (vf_data->num_vf_mc_hashes > 30) {
5825 vmolr |= E1000_VMOLR_MPME;
5826 } else if (vf_data->num_vf_mc_hashes) {
5827 int j;
9005df38 5828
7d5753f0
AD		 5829 vmolr |= E1000_VMOLR_ROMPE;
5830 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5831 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5832 }
5833 }
5834
5835 wr32(E1000_VMOLR(vf), vmolr);
5836
5837 /* there are flags left unprocessed, likely not supported */
5838 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5839 return -EINVAL;
5840
5841 return 0;
7d5753f0
AD		 5842}
5843
4ae196df
AD		 5844static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5845 u32 *msgbuf, u32 vf)
5846{
5847 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5848 u16 *hash_list = (u16 *)&msgbuf[1];
5849 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5850 int i;
5851
7d5753f0 5852 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5853 * to this VF for later use to restore when the PF multi cast
5854 * list changes
5855 */
5856 vf_data->num_vf_mc_hashes = n;
5857
7d5753f0
AD		 5858 /* only up to 30 hash values supported */
5859 if (n > 30)
5860 n = 30;
5861
5862 /* store the hashes for later use */
4ae196df 5863 for (i = 0; i < n; i++)
a419aef8 5864 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5865
5866 /* Flush and reset the mta with the new values */
ff41f8dc 5867 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5868
5869 return 0;
5870}
5871
5872static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5873{
5874 struct e1000_hw *hw = &adapter->hw;
5875 struct vf_data_storage *vf_data;
5876 int i, j;
5877
5878 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5879 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5880
7d5753f0
AD		 5881 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5882
4ae196df 5883 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5884
5885 if ((vf_data->num_vf_mc_hashes > 30) ||
5886 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5887 vmolr |= E1000_VMOLR_MPME;
5888 } else if (vf_data->num_vf_mc_hashes) {
5889 vmolr |= E1000_VMOLR_ROMPE;
5890 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5891 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5892 }
5893 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5894 }
5895}
5896
5897static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5898{
5899 struct e1000_hw *hw = &adapter->hw;
16903caa 5900 u32 pool_mask, vlvf_mask, i;
4ae196df 5901
16903caa
AD		 5902 /* create mask for VF and other pools */
5903 pool_mask = E1000_VLVF_POOLSEL_MASK;
5904 vlvf_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5905
5906 /* drop PF from pool bits */
5907 pool_mask &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT +
5908 adapter->vfs_allocated_count));
4ae196df
AD		 5909
5910 /* Find the vlan filter for this id */
16903caa
AD		 5911 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
5912 u32 vlvf = rd32(E1000_VLVF(i));
5913 u32 vfta_mask, vid, vfta;
4ae196df
AD		 5914
5915 /* remove the vf from the pool */
16903caa
AD		 5916 if (!(vlvf & vlvf_mask))
5917 continue;
5918
5919 /* clear out bit from VLVF */
5920 vlvf ^= vlvf_mask;
5921
5922 /* if other pools are present, just remove ourselves */
5923 if (vlvf & pool_mask)
5924 goto update_vlvfb;
5925
5926 /* if PF is present, leave VFTA */
5927 if (vlvf & E1000_VLVF_POOLSEL_MASK)
5928 goto update_vlvf;
4ae196df 5929
16903caa
AD		 5930 vid = vlvf & E1000_VLVF_VLANID_MASK;
5931 vfta_mask = 1 << (vid % 32);
5932
5933 /* clear bit from VFTA */
5934 vfta = adapter->shadow_vfta[vid / 32];
5935 if (vfta & vfta_mask)
5936 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
5937update_vlvf:
5938 /* clear pool selection enable */
5939 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5940 vlvf &= E1000_VLVF_POOLSEL_MASK;
5941 else
5942 vlvf = 0;
5943update_vlvfb:
5944 /* clear pool bits */
5945 wr32(E1000_VLVF(i), vlvf);
4ae196df
AD		 5946 }
5947}
5948
16903caa 5949static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6f3dc319 5950{
16903caa
AD		 5951 u32 vlvf;
5952 int idx;
6f3dc319 5953
16903caa
AD		 5954 /* short cut the special case */
5955 if (vlan == 0)
5956 return 0;
5957
5958 /* Search for the VLAN id in the VLVF entries */
5959 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
5960 vlvf = rd32(E1000_VLVF(idx));
5961 if ((vlvf & VLAN_VID_MASK) == vlan)
6f3dc319
GR		 5962 break;
5963 }
5964
16903caa
AD		 5965 return idx;
5966}
5967
5968void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
5969{
5970 struct e1000_hw *hw = &adapter->hw;
5971 u32 bits, pf_id;
5972 int idx;
5973
5974 idx = igb_find_vlvf_entry(hw, vid);
5975 if (!idx)
5976 return;
6f3dc319 5977
16903caa
AD		 5978 /* See if any other pools are set for this VLAN filter
5979 * entry other than the PF.
5980 */
5981 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5982 bits = ~(1 << pf_id) & E1000_VLVF_POOLSEL_MASK;
5983 bits &= rd32(E1000_VLVF(idx));
5984
5985 /* Disable the filter so this falls into the default pool. */
5986 if (!bits) {
5987 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5988 wr32(E1000_VLVF(idx), 1 << pf_id);
5989 else
5990 wr32(E1000_VLVF(idx), 0);
5991 }
6f3dc319
GR		 5992}
5993
a15d9259
AD		 5994static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
5995 bool add, u32 vf)
4ae196df 5996{
a15d9259 5997 int pf_id = adapter->vfs_allocated_count;
6f3dc319 5998 struct e1000_hw *hw = &adapter->hw;
a15d9259 5999 int err;
4ae196df 6000
a15d9259
AD		 6001 /* If VLAN overlaps with one the PF is currently monitoring make
6002 * sure that we are able to allocate a VLVF entry. This may be
6003 * redundant but it guarantees PF will maintain visibility to
6004 * the VLAN.
6f3dc319 6005 */
16903caa 6006 if (add && test_bit(vid, adapter->active_vlans)) {
a15d9259
AD		 6007 err = igb_vfta_set(hw, vid, pf_id, true, false);
6008 if (err)
6009 return err;
6010 }
6f3dc319 6011
a15d9259 6012 err = igb_vfta_set(hw, vid, vf, add, false);
6f3dc319 6013
16903caa
AD		 6014 if (add && !err)
6015 return err;
6f3dc319 6016
16903caa
AD		 6017 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6018 * we may need to drop the PF pool bit in order to allow us to free
6019 * up the VLVF resources.
6f3dc319 6020 */
16903caa
AD		 6021 if (test_bit(vid, adapter->active_vlans) ||
6022 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6023 igb_update_pf_vlvf(adapter, vid);
6f3dc319 6024
6f3dc319 6025 return err;
4ae196df
AD		 6026}
6027
a15d9259 6028static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4ae196df 6029{
a15d9259
AD		 6030 struct e1000_hw *hw = &adapter->hw;
6031
6032 if (vid)
6033 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6034 else
6035 wr32(E1000_VMVIR(vf), 0);
6036}
6037
6038static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6039 u16 vlan, u8 qos)
6040{
6041 int err;
6042
6043 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6044 if (err)
6045 return err;
6046
6047 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6048 igb_set_vmolr(adapter, vf, !vlan);
6049
6050 /* revoke access to previous VLAN */
6051 if (vlan != adapter->vf_data[vf].pf_vlan)
6052 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6053 false, vf);
6054
6055 adapter->vf_data[vf].pf_vlan = vlan;
6056 adapter->vf_data[vf].pf_qos = qos;
6057 dev_info(&adapter->pdev->dev,
6058 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6059 if (test_bit(__IGB_DOWN, &adapter->state)) {
6060 dev_warn(&adapter->pdev->dev,
6061 "The VF VLAN has been set, but the PF device is not up.\n");
6062 dev_warn(&adapter->pdev->dev,
6063 "Bring the PF device up before attempting to use the VF device.\n");
6064 }
6065
6066 return err;
6067}
4ae196df 6068
a15d9259
AD		 6069static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6070{
6071 /* Restore tagless access via VLAN 0 */
6072 igb_set_vf_vlan(adapter, 0, true, vf);
6073
6074 igb_set_vmvir(adapter, 0, vf);
8151d294 6075 igb_set_vmolr(adapter, vf, true);
4ae196df 6076
a15d9259
AD		 6077 /* Remove any PF assigned VLAN */
6078 if (adapter->vf_data[vf].pf_vlan)
6079 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6080 false, vf);
6081
6082 adapter->vf_data[vf].pf_vlan = 0;
6083 adapter->vf_data[vf].pf_qos = 0;
6084
6085 return 0;
6086}
6087
6088static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6089 int vf, u16 vlan, u8 qos)
6090{
6091 struct igb_adapter *adapter = netdev_priv(netdev);
6092
6093 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6094 return -EINVAL;
6095
6096 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6097 igb_disable_port_vlan(adapter, vf);
6098}
6099
6100static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6101{
6102 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6103 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6104
6105 if (adapter->vf_data[vf].pf_vlan)
6106 return -1;
6107
6108 /* VLAN 0 is a special case, don't allow it to be removed */
6109 if (!vid && !add)
6110 return 0;
6111
6112 return igb_set_vf_vlan(adapter, vid, !!add, vf);
6113}
6114
6115static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6116{
6117 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6118
6119 /* clear flags - except flag that indicates PF has set the MAC */
6120 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6121 vf_data->last_nack = jiffies;
6122
4ae196df
AD		 6123 /* reset vlans for device */
6124 igb_clear_vf_vfta(adapter, vf);
a15d9259
AD		 6125 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6126 igb_set_vmvir(adapter, vf_data->pf_vlan |
6127 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6128 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
4ae196df
AD		 6129
6130 /* reset multicast table array for vf */
6131 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6132
6133 /* Flush and reset the mta with the new values */
ff41f8dc 6134 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6135}
6136
f2ca0dbe
AD		 6137static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6138{
6139 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6140
5ac6f91d 6141 /* clear mac address as we were hotplug removed/added */
8151d294 6142 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6143 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6144
6145 /* process remaining reset events */
6146 igb_vf_reset(adapter, vf);
6147}
6148
6149static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6150{
6151 struct e1000_hw *hw = &adapter->hw;
6152 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6153 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6154 u32 reg, msgbuf[3];
6155 u8 *addr = (u8 *)(&msgbuf[1]);
6156
6157 /* process all the same items cleared in a function level reset */
f2ca0dbe 6158 igb_vf_reset(adapter, vf);
4ae196df
AD		 6159
6160 /* set vf mac address */
26ad9178 6161 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6162
6163 /* enable transmit and receive for vf */
6164 reg = rd32(E1000_VFTE);
6165 wr32(E1000_VFTE, reg | (1 << vf));
6166 reg = rd32(E1000_VFRE);
6167 wr32(E1000_VFRE, reg | (1 << vf));
6168
8fa7e0f7 6169 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6170
6171 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6172 if (!is_zero_ether_addr(vf_mac)) {
6173 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6174 memcpy(addr, vf_mac, ETH_ALEN);
6175 } else {
6176 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6177 }
4ae196df
AD		 6178 igb_write_mbx(hw, msgbuf, 3, vf);
6179}
6180
6181static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6182{
b980ac18 6183 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6184 * starting at the second 32 bit word of the msg array
6185 */
f2ca0dbe
AD		 6186 unsigned char *addr = (char *)&msg[1];
6187 int err = -1;
4ae196df 6188
f2ca0dbe
AD		 6189 if (is_valid_ether_addr(addr))
6190 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6191
f2ca0dbe 6192 return err;
4ae196df
AD		 6193}
6194
6195static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6196{
6197 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6198 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6199 u32 msg = E1000_VT_MSGTYPE_NACK;
6200
6201 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6202 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6203 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6204 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6205 vf_data->last_nack = jiffies;
4ae196df
AD		 6206 }
6207}
6208
f2ca0dbe 6209static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6210{
f2ca0dbe
AD		 6211 struct pci_dev *pdev = adapter->pdev;
6212 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6213 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6214 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6215 s32 retval;
6216
f2ca0dbe 6217 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6218
fef45f4c
AD		 6219 if (retval) {
6220 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6221 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6222 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6223 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6224 return;
6225 goto out;
6226 }
4ae196df
AD		 6227
6228 /* this is a message we already processed, do nothing */
6229 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6230 return;
4ae196df 6231
b980ac18 6232 /* until the vf completes a reset it should not be
4ae196df
AD		 6233 * allowed to start any configuration.
6234 */
4ae196df
AD		 6235 if (msgbuf[0] == E1000_VF_RESET) {
6236 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6237 return;
4ae196df
AD		 6238 }
6239
f2ca0dbe 6240 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6241 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6242 return;
6243 retval = -1;
6244 goto out;
4ae196df
AD		 6245 }
6246
6247 switch ((msgbuf[0] & 0xFFFF)) {
6248 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6249 retval = -EINVAL;
6250 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6251 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6252 else
6253 dev_warn(&pdev->dev,
b980ac18
JK		 6254 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6255 vf);
4ae196df 6256 break;
7d5753f0
AD		 6257 case E1000_VF_SET_PROMISC:
6258 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6259 break;
4ae196df
AD		 6260 case E1000_VF_SET_MULTICAST:
6261 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6262 break;
6263 case E1000_VF_SET_LPE:
6264 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6265 break;
6266 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6267 retval = -1;
6268 if (vf_data->pf_vlan)
6269 dev_warn(&pdev->dev,
b980ac18
JK		 6270 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6271 vf);
8151d294 6272 else
a15d9259 6273 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
4ae196df
AD		 6274 break;
6275 default:
090b1795 6276 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6277 retval = -1;
6278 break;
6279 }
6280
fef45f4c
AD		 6281 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6282out:
4ae196df
AD		 6283 /* notify the VF of the results of what it sent us */
6284 if (retval)
6285 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6286 else
6287 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6288
4ae196df 6289 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6290}
4ae196df 6291
f2ca0dbe
AD		 6292static void igb_msg_task(struct igb_adapter *adapter)
6293{
6294 struct e1000_hw *hw = &adapter->hw;
6295 u32 vf;
6296
6297 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6298 /* process any reset requests */
6299 if (!igb_check_for_rst(hw, vf))
6300 igb_vf_reset_event(adapter, vf);
6301
6302 /* process any messages pending */
6303 if (!igb_check_for_msg(hw, vf))
6304 igb_rcv_msg_from_vf(adapter, vf);
6305
6306 /* process any acks */
6307 if (!igb_check_for_ack(hw, vf))
6308 igb_rcv_ack_from_vf(adapter, vf);
6309 }
4ae196df
AD		 6310}
6311
68d480c4
AD		 6312/**
6313 * igb_set_uta - Set unicast filter table address
6314 * @adapter: board private structure
6315 *
6316 * The unicast table address is a register array of 32-bit registers.
6317 * The table is meant to be used in a way similar to how the MTA is used
6318 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6319 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6320 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6321 **/
6322static void igb_set_uta(struct igb_adapter *adapter)
6323{
6324 struct e1000_hw *hw = &adapter->hw;
6325 int i;
6326
6327 /* The UTA table only exists on 82576 hardware and newer */
6328 if (hw->mac.type < e1000_82576)
6329 return;
6330
6331 /* we only need to do this if VMDq is enabled */
6332 if (!adapter->vfs_allocated_count)
6333 return;
6334
6335 for (i = 0; i < hw->mac.uta_reg_count; i++)
6336 array_wr32(E1000_UTA, i, ~0);
6337}
6338
9d5c8243 6339/**
b980ac18
JK		 6340 * igb_intr_msi - Interrupt Handler
6341 * @irq: interrupt number
6342 * @data: pointer to a network interface device structure
9d5c8243
AK		 6343 **/
6344static irqreturn_t igb_intr_msi(int irq, void *data)
6345{
047e0030
AD		 6346 struct igb_adapter *adapter = data;
6347 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6348 struct e1000_hw *hw = &adapter->hw;
6349 /* read ICR disables interrupts using IAM */
6350 u32 icr = rd32(E1000_ICR);
6351
047e0030 6352 igb_write_itr(q_vector);
9d5c8243 6353
7f081d40
AD		 6354 if (icr & E1000_ICR_DRSTA)
6355 schedule_work(&adapter->reset_task);
6356
047e0030 6357 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6358 /* HW is reporting DMA is out of sync */
6359 adapter->stats.doosync++;
6360 }
6361
9d5c8243
AK		 6362 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6363 hw->mac.get_link_status = 1;
6364 if (!test_bit(__IGB_DOWN, &adapter->state))
6365 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6366 }
6367
61d7f75f
RC		 6368 if (icr & E1000_ICR_TS)
6369 igb_tsync_interrupt(adapter);
1f6e8178 6370
047e0030 6371 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6372
6373 return IRQ_HANDLED;
6374}
6375
6376/**
b980ac18
JK		 6377 * igb_intr - Legacy Interrupt Handler
6378 * @irq: interrupt number
6379 * @data: pointer to a network interface device structure
9d5c8243
AK		 6380 **/
6381static irqreturn_t igb_intr(int irq, void *data)
6382{
047e0030
AD		 6383 struct igb_adapter *adapter = data;
6384 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6385 struct e1000_hw *hw = &adapter->hw;
6386 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6387 * need for the IMC write
6388 */
9d5c8243 6389 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6390
6391 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6392 * not set, then the adapter didn't send an interrupt
6393 */
9d5c8243
AK		 6394 if (!(icr & E1000_ICR_INT_ASSERTED))
6395 return IRQ_NONE;
6396
0ba82994
AD		 6397 igb_write_itr(q_vector);
6398
7f081d40
AD		 6399 if (icr & E1000_ICR_DRSTA)
6400 schedule_work(&adapter->reset_task);
6401
047e0030 6402 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6403 /* HW is reporting DMA is out of sync */
6404 adapter->stats.doosync++;
6405 }
6406
9d5c8243
AK		 6407 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6408 hw->mac.get_link_status = 1;
6409 /* guard against interrupt when we're going down */
6410 if (!test_bit(__IGB_DOWN, &adapter->state))
6411 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6412 }
6413
61d7f75f
RC		 6414 if (icr & E1000_ICR_TS)
6415 igb_tsync_interrupt(adapter);
1f6e8178 6416
047e0030 6417 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6418
6419 return IRQ_HANDLED;
6420}
6421
c50b52a0 6422static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6423{
047e0030 6424 struct igb_adapter *adapter = q_vector->adapter;
46544258 6425 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6426
0ba82994
AD		 6427 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6428 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6429 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6430 igb_set_itr(q_vector);
46544258 6431 else
047e0030 6432 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6433 }
6434
46544258 6435 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6436 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6437 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6438 else
6439 igb_irq_enable(adapter);
6440 }
9d5c8243
AK		 6441}
6442
46544258 6443/**
b980ac18
JK		 6444 * igb_poll - NAPI Rx polling callback
6445 * @napi: napi polling structure
6446 * @budget: count of how many packets we should handle
46544258
AD		 6447 **/
6448static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6449{
047e0030 6450 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6451 struct igb_q_vector,
6452 napi);
16eb8815 6453 bool clean_complete = true;
32b3e08f 6454 int work_done = 0;
9d5c8243 6455
421e02f0 6456#ifdef CONFIG_IGB_DCA
047e0030
AD		 6457 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6458 igb_update_dca(q_vector);
fe4506b6 6459#endif
0ba82994 6460 if (q_vector->tx.ring)
13fde97a 6461 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6462
32b3e08f
JB		 6463 if (q_vector->rx.ring) {
6464 int cleaned = igb_clean_rx_irq(q_vector, budget);
6465
6466 work_done += cleaned;
6467 clean_complete &= (cleaned < budget);
6468 }
047e0030 6469
16eb8815
AD		 6470 /* If all work not completed, return budget and keep polling */
6471 if (!clean_complete)
6472 return budget;
46544258 6473
9d5c8243 6474 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6475 napi_complete_done(napi, work_done);
16eb8815 6476 igb_ring_irq_enable(q_vector);
9d5c8243 6477
16eb8815 6478 return 0;
9d5c8243 6479}
6d8126f9 6480
9d5c8243 6481/**
b980ac18
JK		 6482 * igb_clean_tx_irq - Reclaim resources after transmit completes
6483 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6484 *
b980ac18 6485 * returns true if ring is completely cleaned
9d5c8243 6486 **/
047e0030 6487static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6488{
047e0030 6489 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6490 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6491 struct igb_tx_buffer *tx_buffer;
f4128785 6492 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6493 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6494 unsigned int budget = q_vector->tx.work_limit;
8542db05 6495 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6496
13fde97a
AD		 6497 if (test_bit(__IGB_DOWN, &adapter->state))
6498 return true;
0e014cb1 6499
06034649 6500 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6501 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6502 i -= tx_ring->count;
9d5c8243 6503
f4128785
AD		 6504 do {
6505 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6506
6507 /* if next_to_watch is not set then there is no work pending */
6508 if (!eop_desc)
6509 break;
13fde97a 6510
f4128785 6511 /* prevent any other reads prior to eop_desc */
70d289bc 6512 read_barrier_depends();
f4128785 6513
13fde97a
AD		 6514 /* if DD is not set pending work has not been completed */
6515 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6516 break;
6517
8542db05
AD		 6518 /* clear next_to_watch to prevent false hangs */
6519 tx_buffer->next_to_watch = NULL;
9d5c8243 6520
ebe42d16
AD		 6521 /* update the statistics for this packet */
6522 total_bytes += tx_buffer->bytecount;
6523 total_packets += tx_buffer->gso_segs;
13fde97a 6524
ebe42d16 6525 /* free the skb */
a81fb049 6526 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6527
ebe42d16
AD		 6528 /* unmap skb header data */
6529 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6530 dma_unmap_addr(tx_buffer, dma),
6531 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6532 DMA_TO_DEVICE);
6533
c9f14bf3
AD		 6534 /* clear tx_buffer data */
6535 tx_buffer->skb = NULL;
6536 dma_unmap_len_set(tx_buffer, len, 0);
6537
ebe42d16
AD		 6538 /* clear last DMA location and unmap remaining buffers */
6539 while (tx_desc != eop_desc) {
13fde97a
AD		 6540 tx_buffer++;
6541 tx_desc++;
9d5c8243 6542 i++;
8542db05
AD		 6543 if (unlikely(!i)) {
6544 i -= tx_ring->count;
06034649 6545 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6546 tx_desc = IGB_TX_DESC(tx_ring, 0);
6547 }
ebe42d16
AD		 6548
6549 /* unmap any remaining paged data */
c9f14bf3 6550 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6551 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6552 dma_unmap_addr(tx_buffer, dma),
6553 dma_unmap_len(tx_buffer, len),
ebe42d16 6554 DMA_TO_DEVICE);
c9f14bf3 6555 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6556 }
6557 }
6558
ebe42d16
AD		 6559 /* move us one more past the eop_desc for start of next pkt */
6560 tx_buffer++;
6561 tx_desc++;
6562 i++;
6563 if (unlikely(!i)) {
6564 i -= tx_ring->count;
6565 tx_buffer = tx_ring->tx_buffer_info;
6566 tx_desc = IGB_TX_DESC(tx_ring, 0);
6567 }
f4128785
AD		 6568
6569 /* issue prefetch for next Tx descriptor */
6570 prefetch(tx_desc);
6571
6572 /* update budget accounting */
6573 budget--;
6574 } while (likely(budget));
0e014cb1 6575
bdbc0631
ED		 6576 netdev_tx_completed_queue(txring_txq(tx_ring),
6577 total_packets, total_bytes);
8542db05 6578 i += tx_ring->count;
9d5c8243 6579 tx_ring->next_to_clean = i;
13fde97a
AD		 6580 u64_stats_update_begin(&tx_ring->tx_syncp);
6581 tx_ring->tx_stats.bytes += total_bytes;
6582 tx_ring->tx_stats.packets += total_packets;
6583 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6584 q_vector->tx.total_bytes += total_bytes;
6585 q_vector->tx.total_packets += total_packets;
9d5c8243 6586
6d095fa8 6587 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6588 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6589
9d5c8243 6590 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6591 * check with the clearing of time_stamp and movement of i
6592 */
6d095fa8 6593 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6594 if (tx_buffer->next_to_watch &&
8542db05 6595 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6596 (adapter->tx_timeout_factor * HZ)) &&
6597 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6598
9d5c8243 6599 /* detected Tx unit hang */
59d71989 6600 dev_err(tx_ring->dev,
9d5c8243 6601 "Detected Tx Unit Hang\n"
2d064c06 6602 " Tx Queue <%d>\n"
9d5c8243
AK		 6603 " TDH <%x>\n"
6604 " TDT <%x>\n"
6605 " next_to_use <%x>\n"
6606 " next_to_clean <%x>\n"
9d5c8243
AK		 6607 "buffer_info[next_to_clean]\n"
6608 " time_stamp <%lx>\n"
8542db05 6609 " next_to_watch <%p>\n"
9d5c8243
AK		 6610 " jiffies <%lx>\n"
6611 " desc.status <%x>\n",
2d064c06 6612 tx_ring->queue_index,
238ac817 6613 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6614 readl(tx_ring->tail),
9d5c8243
AK		 6615 tx_ring->next_to_use,
6616 tx_ring->next_to_clean,
8542db05 6617 tx_buffer->time_stamp,
f4128785 6618 tx_buffer->next_to_watch,
9d5c8243 6619 jiffies,
f4128785 6620 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6621 netif_stop_subqueue(tx_ring->netdev,
6622 tx_ring->queue_index);
6623
6624 /* we are about to reset, no point in enabling stuff */
6625 return true;
9d5c8243
AK		 6626 }
6627 }
13fde97a 6628
21ba6fe1 6629#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6630 if (unlikely(total_packets &&
b980ac18
JK		 6631 netif_carrier_ok(tx_ring->netdev) &&
6632 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6633 /* Make sure that anybody stopping the queue after this
6634 * sees the new next_to_clean.
6635 */
6636 smp_mb();
6637 if (__netif_subqueue_stopped(tx_ring->netdev,
6638 tx_ring->queue_index) &&
6639 !(test_bit(__IGB_DOWN, &adapter->state))) {
6640 netif_wake_subqueue(tx_ring->netdev,
6641 tx_ring->queue_index);
6642
6643 u64_stats_update_begin(&tx_ring->tx_syncp);
6644 tx_ring->tx_stats.restart_queue++;
6645 u64_stats_update_end(&tx_ring->tx_syncp);
6646 }
6647 }
6648
6649 return !!budget;
9d5c8243
AK		 6650}
6651
cbc8e55f 6652/**
b980ac18
JK		 6653 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6654 * @rx_ring: rx descriptor ring to store buffers on
6655 * @old_buff: donor buffer to have page reused
cbc8e55f 6656 *
b980ac18 6657 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6658 **/
6659static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6660 struct igb_rx_buffer *old_buff)
6661{
6662 struct igb_rx_buffer *new_buff;
6663 u16 nta = rx_ring->next_to_alloc;
6664
6665 new_buff = &rx_ring->rx_buffer_info[nta];
6666
6667 /* update, and store next to alloc */
6668 nta++;
6669 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6670
6671 /* transfer page from old buffer to new buffer */
a1f63473 6672 *new_buff = *old_buff;
cbc8e55f
AD		 6673
6674 /* sync the buffer for use by the device */
6675 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6676 old_buff->page_offset,
de78d1f9 6677 IGB_RX_BUFSZ,
cbc8e55f
AD		 6678 DMA_FROM_DEVICE);
6679}
6680
95dd44b4
AD		 6681static inline bool igb_page_is_reserved(struct page *page)
6682{
2f064f34 6683 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6684}
6685
74e238ea
AD		 6686static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6687 struct page *page,
6688 unsigned int truesize)
6689{
6690 /* avoid re-using remote pages */
95dd44b4 6691 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6692 return false;
6693
74e238ea
AD		 6694#if (PAGE_SIZE < 8192)
6695 /* if we are only owner of page we can reuse it */
6696 if (unlikely(page_count(page) != 1))
6697 return false;
6698
6699 /* flip page offset to other buffer */
6700 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6701#else
6702 /* move offset up to the next cache line */
6703 rx_buffer->page_offset += truesize;
6704
6705 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6706 return false;
74e238ea
AD		 6707#endif
6708
95dd44b4
AD		 6709 /* Even if we own the page, we are not allowed to use atomic_set()
6710 * This would break get_page_unless_zero() users.
6711 */
6712 atomic_inc(&page->_count);
6713
74e238ea
AD		 6714 return true;
6715}
6716
cbc8e55f 6717/**
b980ac18
JK		 6718 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6719 * @rx_ring: rx descriptor ring to transact packets on
6720 * @rx_buffer: buffer containing page to add
6721 * @rx_desc: descriptor containing length of buffer written by hardware
6722 * @skb: sk_buff to place the data into
cbc8e55f 6723 *
b980ac18
JK		 6724 * This function will add the data contained in rx_buffer->page to the skb.
6725 * This is done either through a direct copy if the data in the buffer is
6726 * less than the skb header size, otherwise it will just attach the page as
6727 * a frag to the skb.
cbc8e55f 6728 *
b980ac18
JK		 6729 * The function will then update the page offset if necessary and return
6730 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6731 **/
6732static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6733 struct igb_rx_buffer *rx_buffer,
6734 union e1000_adv_rx_desc *rx_desc,
6735 struct sk_buff *skb)
6736{
6737 struct page *page = rx_buffer->page;
f56e7bba 6738 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6739 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6740#if (PAGE_SIZE < 8192)
6741 unsigned int truesize = IGB_RX_BUFSZ;
6742#else
f56e7bba 6743 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6744#endif
f56e7bba 6745 unsigned int pull_len;
cbc8e55f 6746
f56e7bba
AD		 6747 if (unlikely(skb_is_nonlinear(skb)))
6748 goto add_tail_frag;
cbc8e55f 6749
f56e7bba
AD		 6750 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6751 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6752 va += IGB_TS_HDR_LEN;
6753 size -= IGB_TS_HDR_LEN;
6754 }
cbc8e55f 6755
f56e7bba 6756 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6757 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6758
95dd44b4
AD		 6759 /* page is not reserved, we can reuse buffer as-is */
6760 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6761 return true;
6762
6763 /* this page cannot be reused so discard it */
95dd44b4 6764 __free_page(page);
cbc8e55f
AD		 6765 return false;
6766 }
6767
f56e7bba
AD		 6768 /* we need the header to contain the greater of either ETH_HLEN or
6769 * 60 bytes if the skb->len is less than 60 for skb_pad.
6770 */
6771 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6772
6773 /* align pull length to size of long to optimize memcpy performance */
6774 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6775
6776 /* update all of the pointers */
6777 va += pull_len;
6778 size -= pull_len;
6779
6780add_tail_frag:
cbc8e55f 6781 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6782 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6783
74e238ea
AD		 6784 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6785}
cbc8e55f 6786
2e334eee
AD		 6787static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6788 union e1000_adv_rx_desc *rx_desc,
6789 struct sk_buff *skb)
6790{
6791 struct igb_rx_buffer *rx_buffer;
6792 struct page *page;
6793
6794 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6795 page = rx_buffer->page;
6796 prefetchw(page);
6797
6798 if (likely(!skb)) {
6799 void *page_addr = page_address(page) +
6800 rx_buffer->page_offset;
6801
6802 /* prefetch first cache line of first page */
6803 prefetch(page_addr);
6804#if L1_CACHE_BYTES < 128
6805 prefetch(page_addr + L1_CACHE_BYTES);
6806#endif
6807
6808 /* allocate a skb to store the frags */
67fd893e 6809 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6810 if (unlikely(!skb)) {
6811 rx_ring->rx_stats.alloc_failed++;
6812 return NULL;
6813 }
6814
b980ac18 6815 /* we will be copying header into skb->data in
2e334eee
AD		 6816 * pskb_may_pull so it is in our interest to prefetch
6817 * it now to avoid a possible cache miss
6818 */
6819 prefetchw(skb->data);
6820 }
6821
6822 /* we are reusing so sync this buffer for CPU use */
6823 dma_sync_single_range_for_cpu(rx_ring->dev,
6824 rx_buffer->dma,
6825 rx_buffer->page_offset,
de78d1f9 6826 IGB_RX_BUFSZ,
2e334eee
AD		 6827 DMA_FROM_DEVICE);
6828
6829 /* pull page into skb */
6830 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6831 /* hand second half of page back to the ring */
6832 igb_reuse_rx_page(rx_ring, rx_buffer);
6833 } else {
6834 /* we are not reusing the buffer so unmap it */
6835 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6836 PAGE_SIZE, DMA_FROM_DEVICE);
6837 }
6838
6839 /* clear contents of rx_buffer */
6840 rx_buffer->page = NULL;
6841
6842 return skb;
6843}
6844
cd392f5c 6845static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6846 union e1000_adv_rx_desc *rx_desc,
6847 struct sk_buff *skb)
9d5c8243 6848{
bc8acf2c 6849 skb_checksum_none_assert(skb);
9d5c8243 6850
294e7d78 6851 /* Ignore Checksum bit is set */
3ceb90fd 6852 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6853 return;
6854
6855 /* Rx checksum disabled via ethtool */
6856 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6857 return;
85ad76b2 6858
9d5c8243 6859 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6860 if (igb_test_staterr(rx_desc,
6861 E1000_RXDEXT_STATERR_TCPE |
6862 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6863 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6864 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6865 * packets, (aka let the stack check the crc32c)
6866 */
866cff06
AD		 6867 if (!((skb->len == 60) &&
6868 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6869 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6870 ring->rx_stats.csum_err++;
12dcd86b
ED		 6871 u64_stats_update_end(&ring->rx_syncp);
6872 }
9d5c8243 6873 /* let the stack verify checksum errors */
9d5c8243
AK		 6874 return;
6875 }
6876 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6877 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6878 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6879 skb->ip_summed = CHECKSUM_UNNECESSARY;
6880
3ceb90fd
AD		 6881 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6882 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6883}
6884
077887c3
AD		 6885static inline void igb_rx_hash(struct igb_ring *ring,
6886 union e1000_adv_rx_desc *rx_desc,
6887 struct sk_buff *skb)
6888{
6889 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6890 skb_set_hash(skb,
6891 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6892 PKT_HASH_TYPE_L3);
077887c3
AD		 6893}
6894
2e334eee 6895/**
b980ac18
JK		 6896 * igb_is_non_eop - process handling of non-EOP buffers
6897 * @rx_ring: Rx ring being processed
6898 * @rx_desc: Rx descriptor for current buffer
6899 * @skb: current socket buffer containing buffer in progress
2e334eee 6900 *
b980ac18
JK		 6901 * This function updates next to clean. If the buffer is an EOP buffer
6902 * this function exits returning false, otherwise it will place the
6903 * sk_buff in the next buffer to be chained and return true indicating
6904 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6905 **/
6906static bool igb_is_non_eop(struct igb_ring *rx_ring,
6907 union e1000_adv_rx_desc *rx_desc)
6908{
6909 u32 ntc = rx_ring->next_to_clean + 1;
6910
6911 /* fetch, update, and store next to clean */
6912 ntc = (ntc < rx_ring->count) ? ntc : 0;
6913 rx_ring->next_to_clean = ntc;
6914
6915 prefetch(IGB_RX_DESC(rx_ring, ntc));
6916
6917 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6918 return false;
6919
6920 return true;
6921}
6922
1a1c225b 6923/**
b980ac18
JK		 6924 * igb_cleanup_headers - Correct corrupted or empty headers
6925 * @rx_ring: rx descriptor ring packet is being transacted on
6926 * @rx_desc: pointer to the EOP Rx descriptor
6927 * @skb: pointer to current skb being fixed
1a1c225b 6928 *
b980ac18
JK		 6929 * Address the case where we are pulling data in on pages only
6930 * and as such no data is present in the skb header.
1a1c225b 6931 *
b980ac18
JK		 6932 * In addition if skb is not at least 60 bytes we need to pad it so that
6933 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6934 *
b980ac18 6935 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6936 **/
6937static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6938 union e1000_adv_rx_desc *rx_desc,
6939 struct sk_buff *skb)
6940{
1a1c225b
AD		 6941 if (unlikely((igb_test_staterr(rx_desc,
6942 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6943 struct net_device *netdev = rx_ring->netdev;
6944 if (!(netdev->features & NETIF_F_RXALL)) {
6945 dev_kfree_skb_any(skb);
6946 return true;
6947 }
6948 }
6949
a94d9e22
AD		 6950 /* if eth_skb_pad returns an error the skb was freed */
6951 if (eth_skb_pad(skb))
6952 return true;
1a1c225b
AD		 6953
6954 return false;
2d94d8ab
AD		 6955}
6956
db2ee5bd 6957/**
b980ac18
JK		 6958 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6959 * @rx_ring: rx descriptor ring packet is being transacted on
6960 * @rx_desc: pointer to the EOP Rx descriptor
6961 * @skb: pointer to current skb being populated
db2ee5bd 6962 *
b980ac18
JK		 6963 * This function checks the ring, descriptor, and packet information in
6964 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6965 * other fields within the skb.
db2ee5bd
AD		 6966 **/
6967static void igb_process_skb_fields(struct igb_ring *rx_ring,
6968 union e1000_adv_rx_desc *rx_desc,
6969 struct sk_buff *skb)
6970{
6971 struct net_device *dev = rx_ring->netdev;
6972
6973 igb_rx_hash(rx_ring, rx_desc, skb);
6974
6975 igb_rx_checksum(rx_ring, rx_desc, skb);
6976
5499a968
JK		 6977 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6978 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6979 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6980
f646968f 6981 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6982 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6983 u16 vid;
9005df38 6984
db2ee5bd
AD		 6985 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6986 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6987 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6988 else
6989 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6990
86a9bad3 6991 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6992 }
6993
6994 skb_record_rx_queue(skb, rx_ring->queue_index);
6995
6996 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6997}
6998
32b3e08f 6999static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 7000{
0ba82994 7001 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 7002 struct sk_buff *skb = rx_ring->skb;
9d5c8243 7003 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 7004 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 7005
57ba34c9 7006 while (likely(total_packets < budget)) {
2e334eee 7007 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7008
2e334eee
AD		 7009 /* return some buffers to hardware, one at a time is too slow */
7010 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7011 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7012 cleaned_count = 0;
7013 }
bf36c1a0 7014
2e334eee 7015 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7016
124b74c1 7017 if (!rx_desc->wb.upper.status_error)
2e334eee 7018 break;
9d5c8243 7019
74e238ea
AD		 7020 /* This memory barrier is needed to keep us from reading
7021 * any other fields out of the rx_desc until we know the
124b74c1 7022 * descriptor has been written back
74e238ea 7023 */
124b74c1 7024 dma_rmb();
74e238ea 7025
2e334eee 7026 /* retrieve a buffer from the ring */
f9d40f6a 7027 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7028
2e334eee
AD		 7029 /* exit if we failed to retrieve a buffer */
7030 if (!skb)
7031 break;
1a1c225b 7032
2e334eee 7033 cleaned_count++;
1a1c225b 7034
2e334eee
AD		 7035 /* fetch next buffer in frame if non-eop */
7036 if (igb_is_non_eop(rx_ring, rx_desc))
7037 continue;
1a1c225b
AD		 7038
7039 /* verify the packet layout is correct */
7040 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7041 skb = NULL;
7042 continue;
9d5c8243 7043 }
9d5c8243 7044
db2ee5bd 7045 /* probably a little skewed due to removing CRC */
3ceb90fd 7046 total_bytes += skb->len;
3ceb90fd 7047
db2ee5bd
AD		 7048 /* populate checksum, timestamp, VLAN, and protocol */
7049 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7050
b2cb09b1 7051 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7052
1a1c225b
AD		 7053 /* reset skb pointer */
7054 skb = NULL;
7055
2e334eee
AD		 7056 /* update budget accounting */
7057 total_packets++;
57ba34c9 7058 }
bf36c1a0 7059
1a1c225b
AD		 7060 /* place incomplete frames back on ring for completion */
7061 rx_ring->skb = skb;
7062
12dcd86b 7063 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7064 rx_ring->rx_stats.packets += total_packets;
7065 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7066 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7067 q_vector->rx.total_packets += total_packets;
7068 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7069
7070 if (cleaned_count)
cd392f5c 7071 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7072
32b3e08f 7073 return total_packets;
9d5c8243
AK		 7074}
7075
c023cd88 7076static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7077 struct igb_rx_buffer *bi)
c023cd88
AD		 7078{
7079 struct page *page = bi->page;
cbc8e55f 7080 dma_addr_t dma;
c023cd88 7081
cbc8e55f
AD		 7082 /* since we are recycling buffers we should seldom need to alloc */
7083 if (likely(page))
c023cd88
AD		 7084 return true;
7085
cbc8e55f 7086 /* alloc new page for storage */
42b17f09 7087 page = dev_alloc_page();
cbc8e55f
AD		 7088 if (unlikely(!page)) {
7089 rx_ring->rx_stats.alloc_failed++;
7090 return false;
c023cd88
AD		 7091 }
7092
cbc8e55f
AD		 7093 /* map page for use */
7094 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7095
b980ac18 7096 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7097 * there isn't much point in holding memory we can't use
7098 */
1a1c225b 7099 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7100 __free_page(page);
7101
c023cd88
AD		 7102 rx_ring->rx_stats.alloc_failed++;
7103 return false;
7104 }
7105
1a1c225b 7106 bi->dma = dma;
cbc8e55f
AD		 7107 bi->page = page;
7108 bi->page_offset = 0;
1a1c225b 7109
c023cd88
AD		 7110 return true;
7111}
7112
9d5c8243 7113/**
b980ac18
JK		 7114 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7115 * @adapter: address of board private structure
9d5c8243 7116 **/
cd392f5c 7117void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7118{
9d5c8243 7119 union e1000_adv_rx_desc *rx_desc;
06034649 7120 struct igb_rx_buffer *bi;
c023cd88 7121 u16 i = rx_ring->next_to_use;
9d5c8243 7122
cbc8e55f
AD		 7123 /* nothing to do */
7124 if (!cleaned_count)
7125 return;
7126
60136906 7127 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7128 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7129 i -= rx_ring->count;
9d5c8243 7130
cbc8e55f 7131 do {
1a1c225b 7132 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7133 break;
9d5c8243 7134
b980ac18 7135 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7136 * because each write-back erases this info.
7137 */
f9d40f6a 7138 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7139
c023cd88
AD		 7140 rx_desc++;
7141 bi++;
9d5c8243 7142 i++;
c023cd88 7143 if (unlikely(!i)) {
60136906 7144 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7145 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7146 i -= rx_ring->count;
7147 }
7148
95dd44b4
AD		 7149 /* clear the status bits for the next_to_use descriptor */
7150 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7151
7152 cleaned_count--;
7153 } while (cleaned_count);
9d5c8243 7154
c023cd88
AD		 7155 i += rx_ring->count;
7156
9d5c8243 7157 if (rx_ring->next_to_use != i) {
cbc8e55f 7158 /* record the next descriptor to use */
9d5c8243 7159 rx_ring->next_to_use = i;
9d5c8243 7160
cbc8e55f
AD		 7161 /* update next to alloc since we have filled the ring */
7162 rx_ring->next_to_alloc = i;
7163
b980ac18 7164 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7165 * know there are new descriptors to fetch. (Only
7166 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7167 * such as IA-64).
7168 */
9d5c8243 7169 wmb();
fce99e34 7170 writel(i, rx_ring->tail);
9d5c8243
AK		 7171 }
7172}
7173
7174/**
7175 * igb_mii_ioctl -
7176 * @netdev:
7177 * @ifreq:
7178 * @cmd:
7179 **/
7180static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7181{
7182 struct igb_adapter *adapter = netdev_priv(netdev);
7183 struct mii_ioctl_data *data = if_mii(ifr);
7184
7185 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7186 return -EOPNOTSUPP;
7187
7188 switch (cmd) {
7189 case SIOCGMIIPHY:
7190 data->phy_id = adapter->hw.phy.addr;
7191 break;
7192 case SIOCGMIIREG:
f5f4cf08 7193 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7194 &data->val_out))
9d5c8243
AK		 7195 return -EIO;
7196 break;
7197 case SIOCSMIIREG:
7198 default:
7199 return -EOPNOTSUPP;
7200 }
7201 return 0;
7202}
7203
7204/**
7205 * igb_ioctl -
7206 * @netdev:
7207 * @ifreq:
7208 * @cmd:
7209 **/
7210static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7211{
7212 switch (cmd) {
7213 case SIOCGMIIPHY:
7214 case SIOCGMIIREG:
7215 case SIOCSMIIREG:
7216 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7217 case SIOCGHWTSTAMP:
7218 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7219 case SIOCSHWTSTAMP:
6ab5f7b2 7220 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7221 default:
7222 return -EOPNOTSUPP;
7223 }
7224}
7225
94826487
TF		 7226void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7227{
7228 struct igb_adapter *adapter = hw->back;
7229
7230 pci_read_config_word(adapter->pdev, reg, value);
7231}
7232
7233void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7234{
7235 struct igb_adapter *adapter = hw->back;
7236
7237 pci_write_config_word(adapter->pdev, reg, *value);
7238}
7239
009bc06e
AD		 7240s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7241{
7242 struct igb_adapter *adapter = hw->back;
009bc06e 7243
23d028cc 7244 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7245 return -E1000_ERR_CONFIG;
7246
009bc06e
AD		 7247 return 0;
7248}
7249
7250s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7251{
7252 struct igb_adapter *adapter = hw->back;
009bc06e 7253
23d028cc 7254 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7255 return -E1000_ERR_CONFIG;
7256
009bc06e
AD		 7257 return 0;
7258}
7259
c8f44aff 7260static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7261{
7262 struct igb_adapter *adapter = netdev_priv(netdev);
7263 struct e1000_hw *hw = &adapter->hw;
7264 u32 ctrl, rctl;
f646968f 7265 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7266
5faf030c 7267 if (enable) {
9d5c8243
AK		 7268 /* enable VLAN tag insert/strip */
7269 ctrl = rd32(E1000_CTRL);
7270 ctrl |= E1000_CTRL_VME;
7271 wr32(E1000_CTRL, ctrl);
7272
51466239 7273 /* Disable CFI check */
9d5c8243 7274 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7275 rctl &= ~E1000_RCTL_CFIEN;
7276 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7277 } else {
7278 /* disable VLAN tag insert/strip */
7279 ctrl = rd32(E1000_CTRL);
7280 ctrl &= ~E1000_CTRL_VME;
7281 wr32(E1000_CTRL, ctrl);
9d5c8243 7282 }
9d5c8243
AK		 7283}
7284
80d5c368
PM		 7285static int igb_vlan_rx_add_vid(struct net_device *netdev,
7286 __be16 proto, u16 vid)
9d5c8243
AK		 7287{
7288 struct igb_adapter *adapter = netdev_priv(netdev);
7289 struct e1000_hw *hw = &adapter->hw;
4ae196df 7290 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7291
51466239 7292 /* add the filter since PF can receive vlans w/o entry in vlvf */
16903caa
AD		 7293 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7294 igb_vfta_set(hw, vid, pf_id, true, !!vid);
7295
b2cb09b1 7296 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7297
7298 return 0;
9d5c8243
AK		 7299}
7300
80d5c368
PM		 7301static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7302 __be16 proto, u16 vid)
9d5c8243
AK		 7303{
7304 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 7305 int pf_id = adapter->vfs_allocated_count;
8b77c6b2 7306 struct e1000_hw *hw = &adapter->hw;
9d5c8243 7307
8b77c6b2 7308 /* remove VID from filter table */
16903caa
AD		 7309 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7310 igb_vfta_set(hw, vid, pf_id, false, true);
b2cb09b1
JP		 7311
7312 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7313
7314 return 0;
9d5c8243
AK		 7315}
7316
7317static void igb_restore_vlan(struct igb_adapter *adapter)
7318{
5982a556 7319 u16 vid = 1;
9d5c8243 7320
5faf030c 7321 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
5982a556 7322 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
5faf030c 7323
5982a556 7324 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7325 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7326}
7327
14ad2513 7328int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7329{
090b1795 7330 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7331 struct e1000_mac_info *mac = &adapter->hw.mac;
7332
7333 mac->autoneg = 0;
7334
14ad2513 7335 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7336 * for the switch() below to work
7337 */
14ad2513
DD		 7338 if ((spd & 1) || (dplx & ~1))
7339 goto err_inval;
7340
f502ef7d
AA		 7341 /* Fiber NIC's only allow 1000 gbps Full duplex
7342 * and 100Mbps Full duplex for 100baseFx sfp
7343 */
7344 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7345 switch (spd + dplx) {
7346 case SPEED_10 + DUPLEX_HALF:
7347 case SPEED_10 + DUPLEX_FULL:
7348 case SPEED_100 + DUPLEX_HALF:
7349 goto err_inval;
7350 default:
7351 break;
7352 }
7353 }
cd2638a8 7354
14ad2513 7355 switch (spd + dplx) {
9d5c8243
AK		 7356 case SPEED_10 + DUPLEX_HALF:
7357 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7358 break;
7359 case SPEED_10 + DUPLEX_FULL:
7360 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7361 break;
7362 case SPEED_100 + DUPLEX_HALF:
7363 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7364 break;
7365 case SPEED_100 + DUPLEX_FULL:
7366 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7367 break;
7368 case SPEED_1000 + DUPLEX_FULL:
7369 mac->autoneg = 1;
7370 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7371 break;
7372 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7373 default:
14ad2513 7374 goto err_inval;
9d5c8243 7375 }
8376dad0
JB		 7376
7377 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7378 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7379
9d5c8243 7380 return 0;
14ad2513
DD		 7381
7382err_inval:
7383 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7384 return -EINVAL;
9d5c8243
AK		 7385}
7386
749ab2cd
YZ		 7387static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7388 bool runtime)
9d5c8243
AK		 7389{
7390 struct net_device *netdev = pci_get_drvdata(pdev);
7391 struct igb_adapter *adapter = netdev_priv(netdev);
7392 struct e1000_hw *hw = &adapter->hw;
2d064c06 7393 u32 ctrl, rctl, status;
749ab2cd 7394 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7395#ifdef CONFIG_PM
7396 int retval = 0;
7397#endif
7398
7399 netif_device_detach(netdev);
7400
a88f10ec 7401 if (netif_running(netdev))
749ab2cd 7402 __igb_close(netdev, true);
a88f10ec 7403
047e0030 7404 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7405
7406#ifdef CONFIG_PM
7407 retval = pci_save_state(pdev);
7408 if (retval)
7409 return retval;
7410#endif
7411
7412 status = rd32(E1000_STATUS);
7413 if (status & E1000_STATUS_LU)
7414 wufc &= ~E1000_WUFC_LNKC;
7415
7416 if (wufc) {
7417 igb_setup_rctl(adapter);
ff41f8dc 7418 igb_set_rx_mode(netdev);
9d5c8243
AK		 7419
7420 /* turn on all-multi mode if wake on multicast is enabled */
7421 if (wufc & E1000_WUFC_MC) {
7422 rctl = rd32(E1000_RCTL);
7423 rctl |= E1000_RCTL_MPE;
7424 wr32(E1000_RCTL, rctl);
7425 }
7426
7427 ctrl = rd32(E1000_CTRL);
7428 /* advertise wake from D3Cold */
7429 #define E1000_CTRL_ADVD3WUC 0x00100000
7430 /* phy power management enable */
7431 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7432 ctrl |= E1000_CTRL_ADVD3WUC;
7433 wr32(E1000_CTRL, ctrl);
7434
9d5c8243 7435 /* Allow time for pending master requests to run */
330a6d6a 7436 igb_disable_pcie_master(hw);
9d5c8243
AK		 7437
7438 wr32(E1000_WUC, E1000_WUC_PME_EN);
7439 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7440 } else {
7441 wr32(E1000_WUC, 0);
7442 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7443 }
7444
3fe7c4c9
RW		 7445 *enable_wake = wufc || adapter->en_mng_pt;
7446 if (!*enable_wake)
88a268c1
NN		 7447 igb_power_down_link(adapter);
7448 else
7449 igb_power_up_link(adapter);
9d5c8243
AK		 7450
7451 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7452 * would have already happened in close and is redundant.
7453 */
9d5c8243
AK		 7454 igb_release_hw_control(adapter);
7455
7456 pci_disable_device(pdev);
7457
9d5c8243
AK		 7458 return 0;
7459}
7460
7461#ifdef CONFIG_PM
d9dd966d 7462#ifdef CONFIG_PM_SLEEP
749ab2cd 7463static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7464{
7465 int retval;
7466 bool wake;
749ab2cd 7467 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7468
749ab2cd 7469 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7470 if (retval)
7471 return retval;
7472
7473 if (wake) {
7474 pci_prepare_to_sleep(pdev);
7475 } else {
7476 pci_wake_from_d3(pdev, false);
7477 pci_set_power_state(pdev, PCI_D3hot);
7478 }
7479
7480 return 0;
7481}
d9dd966d 7482#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7483
749ab2cd 7484static int igb_resume(struct device *dev)
9d5c8243 7485{
749ab2cd 7486 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7487 struct net_device *netdev = pci_get_drvdata(pdev);
7488 struct igb_adapter *adapter = netdev_priv(netdev);
7489 struct e1000_hw *hw = &adapter->hw;
7490 u32 err;
7491
7492 pci_set_power_state(pdev, PCI_D0);
7493 pci_restore_state(pdev);
b94f2d77 7494 pci_save_state(pdev);
42bfd33a 7495
17a402a0
CW		 7496 if (!pci_device_is_present(pdev))
7497 return -ENODEV;
aed5dec3 7498 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7499 if (err) {
7500 dev_err(&pdev->dev,
7501 "igb: Cannot enable PCI device from suspend\n");
7502 return err;
7503 }
7504 pci_set_master(pdev);
7505
7506 pci_enable_wake(pdev, PCI_D3hot, 0);
7507 pci_enable_wake(pdev, PCI_D3cold, 0);
7508
53c7d064 7509 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec 7510 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3eb14ea8 7511 rtnl_unlock();
a88f10ec 7512 return -ENOMEM;
9d5c8243
AK		 7513 }
7514
9d5c8243 7515 igb_reset(adapter);
a8564f03
AD		 7516
7517 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7518 * driver.
7519 */
a8564f03
AD		 7520 igb_get_hw_control(adapter);
7521
9d5c8243
AK		 7522 wr32(E1000_WUS, ~0);
7523
749ab2cd 7524 if (netdev->flags & IFF_UP) {
0c2cc02e 7525 rtnl_lock();
749ab2cd 7526 err = __igb_open(netdev, true);
0c2cc02e 7527 rtnl_unlock();
a88f10ec
AD		 7528 if (err)
7529 return err;
7530 }
9d5c8243
AK		 7531
7532 netif_device_attach(netdev);
749ab2cd
YZ		 7533 return 0;
7534}
7535
749ab2cd
YZ		 7536static int igb_runtime_idle(struct device *dev)
7537{
7538 struct pci_dev *pdev = to_pci_dev(dev);
7539 struct net_device *netdev = pci_get_drvdata(pdev);
7540 struct igb_adapter *adapter = netdev_priv(netdev);
7541
7542 if (!igb_has_link(adapter))
7543 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7544
7545 return -EBUSY;
7546}
7547
7548static int igb_runtime_suspend(struct device *dev)
7549{
7550 struct pci_dev *pdev = to_pci_dev(dev);
7551 int retval;
7552 bool wake;
7553
7554 retval = __igb_shutdown(pdev, &wake, 1);
7555 if (retval)
7556 return retval;
7557
7558 if (wake) {
7559 pci_prepare_to_sleep(pdev);
7560 } else {
7561 pci_wake_from_d3(pdev, false);
7562 pci_set_power_state(pdev, PCI_D3hot);
7563 }
9d5c8243 7564
9d5c8243
AK		 7565 return 0;
7566}
749ab2cd
YZ		 7567
7568static int igb_runtime_resume(struct device *dev)
7569{
7570 return igb_resume(dev);
7571}
d61c81cb 7572#endif /* CONFIG_PM */
9d5c8243
AK		 7573
7574static void igb_shutdown(struct pci_dev *pdev)
7575{
3fe7c4c9
RW		 7576 bool wake;
7577
749ab2cd 7578 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7579
7580 if (system_state == SYSTEM_POWER_OFF) {
7581 pci_wake_from_d3(pdev, wake);
7582 pci_set_power_state(pdev, PCI_D3hot);
7583 }
9d5c8243
AK		 7584}
7585
fa44f2f1
GR		 7586#ifdef CONFIG_PCI_IOV
7587static int igb_sriov_reinit(struct pci_dev *dev)
7588{
7589 struct net_device *netdev = pci_get_drvdata(dev);
7590 struct igb_adapter *adapter = netdev_priv(netdev);
7591 struct pci_dev *pdev = adapter->pdev;
7592
7593 rtnl_lock();
7594
7595 if (netif_running(netdev))
7596 igb_close(netdev);
76252723
SA		 7597 else
7598 igb_reset(adapter);
fa44f2f1
GR		 7599
7600 igb_clear_interrupt_scheme(adapter);
7601
7602 igb_init_queue_configuration(adapter);
7603
7604 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7605 rtnl_unlock();
fa44f2f1
GR		 7606 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7607 return -ENOMEM;
7608 }
7609
7610 if (netif_running(netdev))
7611 igb_open(netdev);
7612
7613 rtnl_unlock();
7614
7615 return 0;
7616}
7617
7618static int igb_pci_disable_sriov(struct pci_dev *dev)
7619{
7620 int err = igb_disable_sriov(dev);
7621
7622 if (!err)
7623 err = igb_sriov_reinit(dev);
7624
7625 return err;
7626}
7627
7628static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7629{
7630 int err = igb_enable_sriov(dev, num_vfs);
7631
7632 if (err)
7633 goto out;
7634
7635 err = igb_sriov_reinit(dev);
7636 if (!err)
7637 return num_vfs;
7638
7639out:
7640 return err;
7641}
7642
7643#endif
7644static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7645{
7646#ifdef CONFIG_PCI_IOV
7647 if (num_vfs == 0)
7648 return igb_pci_disable_sriov(dev);
7649 else
7650 return igb_pci_enable_sriov(dev, num_vfs);
7651#endif
7652 return 0;
7653}
7654
9d5c8243 7655#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7656/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7657 * without having to re-enable interrupts. It's not called while
7658 * the interrupt routine is executing.
7659 */
7660static void igb_netpoll(struct net_device *netdev)
7661{
7662 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7663 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7664 struct igb_q_vector *q_vector;
9d5c8243 7665 int i;
9d5c8243 7666
047e0030 7667 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7668 q_vector = adapter->q_vector[i];
cd14ef54 7669 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7670 wr32(E1000_EIMC, q_vector->eims_value);
7671 else
7672 igb_irq_disable(adapter);
047e0030 7673 napi_schedule(&q_vector->napi);
eebbbdba 7674 }
9d5c8243
AK		 7675}
7676#endif /* CONFIG_NET_POLL_CONTROLLER */
7677
7678/**
b980ac18
JK		 7679 * igb_io_error_detected - called when PCI error is detected
7680 * @pdev: Pointer to PCI device
7681 * @state: The current pci connection state
9d5c8243 7682 *
b980ac18
JK		 7683 * This function is called after a PCI bus error affecting
7684 * this device has been detected.
7685 **/
9d5c8243
AK		 7686static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7687 pci_channel_state_t state)
7688{
7689 struct net_device *netdev = pci_get_drvdata(pdev);
7690 struct igb_adapter *adapter = netdev_priv(netdev);
7691
7692 netif_device_detach(netdev);
7693
59ed6eec
AD		 7694 if (state == pci_channel_io_perm_failure)
7695 return PCI_ERS_RESULT_DISCONNECT;
7696
9d5c8243
AK		 7697 if (netif_running(netdev))
7698 igb_down(adapter);
7699 pci_disable_device(pdev);
7700
7701 /* Request a slot slot reset. */
7702 return PCI_ERS_RESULT_NEED_RESET;
7703}
7704
7705/**
b980ac18
JK		 7706 * igb_io_slot_reset - called after the pci bus has been reset.
7707 * @pdev: Pointer to PCI device
9d5c8243 7708 *
b980ac18
JK		 7709 * Restart the card from scratch, as if from a cold-boot. Implementation
7710 * resembles the first-half of the igb_resume routine.
7711 **/
9d5c8243
AK		 7712static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7713{
7714 struct net_device *netdev = pci_get_drvdata(pdev);
7715 struct igb_adapter *adapter = netdev_priv(netdev);
7716 struct e1000_hw *hw = &adapter->hw;
40a914fa 7717 pci_ers_result_t result;
42bfd33a 7718 int err;
9d5c8243 7719
aed5dec3 7720 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7721 dev_err(&pdev->dev,
7722 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7723 result = PCI_ERS_RESULT_DISCONNECT;
7724 } else {
7725 pci_set_master(pdev);
7726 pci_restore_state(pdev);
b94f2d77 7727 pci_save_state(pdev);
9d5c8243 7728
40a914fa
AD		 7729 pci_enable_wake(pdev, PCI_D3hot, 0);
7730 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7731
40a914fa
AD		 7732 igb_reset(adapter);
7733 wr32(E1000_WUS, ~0);
7734 result = PCI_ERS_RESULT_RECOVERED;
7735 }
9d5c8243 7736
ea943d41
JK		 7737 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7738 if (err) {
b980ac18
JK		 7739 dev_err(&pdev->dev,
7740 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7741 err);
ea943d41
JK		 7742 /* non-fatal, continue */
7743 }
40a914fa
AD		 7744
7745 return result;
9d5c8243
AK		 7746}
7747
7748/**
b980ac18
JK		 7749 * igb_io_resume - called when traffic can start flowing again.
7750 * @pdev: Pointer to PCI device
9d5c8243 7751 *
b980ac18
JK		 7752 * This callback is called when the error recovery driver tells us that
7753 * its OK to resume normal operation. Implementation resembles the
7754 * second-half of the igb_resume routine.
9d5c8243
AK		 7755 */
7756static void igb_io_resume(struct pci_dev *pdev)
7757{
7758 struct net_device *netdev = pci_get_drvdata(pdev);
7759 struct igb_adapter *adapter = netdev_priv(netdev);
7760
9d5c8243
AK		 7761 if (netif_running(netdev)) {
7762 if (igb_up(adapter)) {
7763 dev_err(&pdev->dev, "igb_up failed after reset\n");
7764 return;
7765 }
7766 }
7767
7768 netif_device_attach(netdev);
7769
7770 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7771 * driver.
7772 */
9d5c8243 7773 igb_get_hw_control(adapter);
9d5c8243
AK		 7774}
7775
26ad9178 7776static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7777 u8 qsel)
26ad9178 7778{
26ad9178 7779 struct e1000_hw *hw = &adapter->hw;
c3278587 7780 u32 rar_low, rar_high;
26ad9178
AD		 7781
7782 /* HW expects these in little endian so we reverse the byte order
c3278587 7783 * from network order (big endian) to CPU endian
26ad9178 7784 */
c3278587
AD		 7785 rar_low = le32_to_cpup((__be32 *)(addr));
7786 rar_high = le16_to_cpup((__be16 *)(addr + 4));
26ad9178
AD		 7787
7788 /* Indicate to hardware the Address is Valid. */
7789 rar_high |= E1000_RAH_AV;
7790
7791 if (hw->mac.type == e1000_82575)
7792 rar_high |= E1000_RAH_POOL_1 * qsel;
7793 else
7794 rar_high |= E1000_RAH_POOL_1 << qsel;
7795
7796 wr32(E1000_RAL(index), rar_low);
7797 wrfl();
7798 wr32(E1000_RAH(index), rar_high);
7799 wrfl();
7800}
7801
4ae196df 7802static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7803 int vf, unsigned char *mac_addr)
4ae196df
AD		 7804{
7805 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7806 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7807 * towards the first, as a result a collision should not be possible
7808 */
ff41f8dc 7809 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7810
37680117 7811 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7812
26ad9178 7813 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7814
7815 return 0;
7816}
7817
8151d294
WM		 7818static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7819{
7820 struct igb_adapter *adapter = netdev_priv(netdev);
7821 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7822 return -EINVAL;
7823 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7824 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7825 dev_info(&adapter->pdev->dev,
7826 "Reload the VF driver to make this change effective.");
8151d294 7827 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7828 dev_warn(&adapter->pdev->dev,
7829 "The VF MAC address has been set, but the PF device is not up.\n");
7830 dev_warn(&adapter->pdev->dev,
7831 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7832 }
7833 return igb_set_vf_mac(adapter, vf, mac);
7834}
7835
17dc566c
LL		 7836static int igb_link_mbps(int internal_link_speed)
7837{
7838 switch (internal_link_speed) {
7839 case SPEED_100:
7840 return 100;
7841 case SPEED_1000:
7842 return 1000;
7843 default:
7844 return 0;
7845 }
7846}
7847
7848static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7849 int link_speed)
7850{
7851 int rf_dec, rf_int;
7852 u32 bcnrc_val;
7853
7854 if (tx_rate != 0) {
7855 /* Calculate the rate factor values to set */
7856 rf_int = link_speed / tx_rate;
7857 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7858 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7859 tx_rate;
17dc566c
LL		 7860
7861 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7862 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7863 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7864 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7865 } else {
7866 bcnrc_val = 0;
7867 }
7868
7869 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7870 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7871 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7872 */
7873 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7874 wr32(E1000_RTTBCNRC, bcnrc_val);
7875}
7876
7877static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7878{
7879 int actual_link_speed, i;
7880 bool reset_rate = false;
7881
7882 /* VF TX rate limit was not set or not supported */
7883 if ((adapter->vf_rate_link_speed == 0) ||
7884 (adapter->hw.mac.type != e1000_82576))
7885 return;
7886
7887 actual_link_speed = igb_link_mbps(adapter->link_speed);
7888 if (actual_link_speed != adapter->vf_rate_link_speed) {
7889 reset_rate = true;
7890 adapter->vf_rate_link_speed = 0;
7891 dev_info(&adapter->pdev->dev,
b980ac18 7892 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7893 }
7894
7895 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7896 if (reset_rate)
7897 adapter->vf_data[i].tx_rate = 0;
7898
7899 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7900 adapter->vf_data[i].tx_rate,
7901 actual_link_speed);
17dc566c
LL		 7902 }
7903}
7904
ed616689
SC		 7905static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7906 int min_tx_rate, int max_tx_rate)
8151d294 7907{
17dc566c
LL		 7908 struct igb_adapter *adapter = netdev_priv(netdev);
7909 struct e1000_hw *hw = &adapter->hw;
7910 int actual_link_speed;
7911
7912 if (hw->mac.type != e1000_82576)
7913 return -EOPNOTSUPP;
7914
ed616689
SC		 7915 if (min_tx_rate)
7916 return -EINVAL;
7917
17dc566c
LL		 7918 actual_link_speed = igb_link_mbps(adapter->link_speed);
7919 if ((vf >= adapter->vfs_allocated_count) ||
7920 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7921 (max_tx_rate < 0) ||
7922 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7923 return -EINVAL;
7924
7925 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7926 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7927 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7928
7929 return 0;
8151d294
WM		 7930}
7931
70ea4783
LL		 7932static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7933 bool setting)
7934{
7935 struct igb_adapter *adapter = netdev_priv(netdev);
7936 struct e1000_hw *hw = &adapter->hw;
7937 u32 reg_val, reg_offset;
7938
7939 if (!adapter->vfs_allocated_count)
7940 return -EOPNOTSUPP;
7941
7942 if (vf >= adapter->vfs_allocated_count)
7943 return -EINVAL;
7944
7945 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7946 reg_val = rd32(reg_offset);
7947 if (setting)
7948 reg_val |= ((1 << vf) |
7949 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7950 else
7951 reg_val &= ~((1 << vf) |
7952 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7953 wr32(reg_offset, reg_val);
7954
7955 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7956 return 0;
70ea4783
LL		 7957}
7958
8151d294
WM		 7959static int igb_ndo_get_vf_config(struct net_device *netdev,
7960 int vf, struct ifla_vf_info *ivi)
7961{
7962 struct igb_adapter *adapter = netdev_priv(netdev);
7963 if (vf >= adapter->vfs_allocated_count)
7964 return -EINVAL;
7965 ivi->vf = vf;
7966 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7967 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7968 ivi->min_tx_rate = 0;
8151d294
WM		 7969 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7970 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7971 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7972 return 0;
7973}
7974
4ae196df
AD		 7975static void igb_vmm_control(struct igb_adapter *adapter)
7976{
7977 struct e1000_hw *hw = &adapter->hw;
10d8e907 7978 u32 reg;
4ae196df 7979
52a1dd4d
AD		 7980 switch (hw->mac.type) {
7981 case e1000_82575:
f96a8a0b
CW		 7982 case e1000_i210:
7983 case e1000_i211:
ceb5f13b 7984 case e1000_i354:
52a1dd4d
AD		 7985 default:
7986 /* replication is not supported for 82575 */
4ae196df 7987 return;
52a1dd4d
AD		 7988 case e1000_82576:
7989 /* notify HW that the MAC is adding vlan tags */
7990 reg = rd32(E1000_DTXCTL);
7991 reg |= E1000_DTXCTL_VLAN_ADDED;
7992 wr32(E1000_DTXCTL, reg);
b26141d4 7993 /* Fall through */
52a1dd4d
AD		 7994 case e1000_82580:
7995 /* enable replication vlan tag stripping */
7996 reg = rd32(E1000_RPLOLR);
7997 reg |= E1000_RPLOLR_STRVLAN;
7998 wr32(E1000_RPLOLR, reg);
b26141d4 7999 /* Fall through */
d2ba2ed8
AD		 8000 case e1000_i350:
8001 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8002 break;
8003 }
10d8e907 8004
d4960307
AD		 8005 if (adapter->vfs_allocated_count) {
8006 igb_vmdq_set_loopback_pf(hw, true);
8007 igb_vmdq_set_replication_pf(hw, true);
13800469 8008 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8009 adapter->vfs_allocated_count);
d4960307
AD		 8010 } else {
8011 igb_vmdq_set_loopback_pf(hw, false);
8012 igb_vmdq_set_replication_pf(hw, false);
8013 }
4ae196df
AD		 8014}
8015
b6e0c419
CW		 8016static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8017{
8018 struct e1000_hw *hw = &adapter->hw;
8019 u32 dmac_thr;
8020 u16 hwm;
8021
8022 if (hw->mac.type > e1000_82580) {
8023 if (adapter->flags & IGB_FLAG_DMAC) {
8024 u32 reg;
8025
8026 /* force threshold to 0. */
8027 wr32(E1000_DMCTXTH, 0);
8028
b980ac18 8029 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8030 * than the Rx threshold. Set hwm to PBA - max frame
8031 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8032 */
45693bcb 8033 hwm = 64 * (pba - 6);
e8c626e9
MV		 8034 reg = rd32(E1000_FCRTC);
8035 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8036 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8037 & E1000_FCRTC_RTH_COAL_MASK);
8038 wr32(E1000_FCRTC, reg);
8039
b980ac18 8040 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8041 * frame size, capping it at PBA - 10KB.
8042 */
45693bcb 8043 dmac_thr = pba - 10;
b6e0c419
CW		 8044 reg = rd32(E1000_DMACR);
8045 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8046 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8047 & E1000_DMACR_DMACTHR_MASK);
8048
8049 /* transition to L0x or L1 if available..*/
8050 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8051
8052 /* watchdog timer= +-1000 usec in 32usec intervals */
8053 reg |= (1000 >> 5);
0c02dd98
MV		 8054
8055 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8056 if (hw->mac.type != e1000_i354)
8057 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8058
b6e0c419
CW		 8059 wr32(E1000_DMACR, reg);
8060
b980ac18 8061 /* no lower threshold to disable
b6e0c419
CW		 8062 * coalescing(smart fifb)-UTRESH=0
8063 */
8064 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8065
8066 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8067
8068 wr32(E1000_DMCTLX, reg);
8069
b980ac18 8070 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8071 * DMA coal
8072 */
8073 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8074 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8075
b980ac18 8076 /* make low power state decision controlled
b6e0c419
CW		 8077 * by DMA coal
8078 */
8079 reg = rd32(E1000_PCIEMISC);
8080 reg &= ~E1000_PCIEMISC_LX_DECISION;
8081 wr32(E1000_PCIEMISC, reg);
8082 } /* endif adapter->dmac is not disabled */
8083 } else if (hw->mac.type == e1000_82580) {
8084 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8085
b6e0c419
CW		 8086 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8087 wr32(E1000_DMACR, 0);
8088 }
8089}
8090
b980ac18
JK		 8091/**
8092 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8093 * @hw: pointer to hardware structure
8094 * @byte_offset: byte offset to read
8095 * @dev_addr: device address
8096 * @data: value read
8097 *
8098 * Performs byte read operation over I2C interface at
8099 * a specified device address.
b980ac18 8100 **/
441fc6fd 8101s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8102 u8 dev_addr, u8 *data)
441fc6fd
CW		 8103{
8104 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8105 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8106 s32 status;
8107 u16 swfw_mask = 0;
8108
8109 if (!this_client)
8110 return E1000_ERR_I2C;
8111
8112 swfw_mask = E1000_SWFW_PHY0_SM;
8113
23d87824 8114 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8115 return E1000_ERR_SWFW_SYNC;
8116
8117 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8118 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8119
8120 if (status < 0)
8121 return E1000_ERR_I2C;
8122 else {
8123 *data = status;
23d87824 8124 return 0;
441fc6fd
CW		 8125 }
8126}
8127
b980ac18
JK		 8128/**
8129 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8130 * @hw: pointer to hardware structure
8131 * @byte_offset: byte offset to write
8132 * @dev_addr: device address
8133 * @data: value to write
8134 *
8135 * Performs byte write operation over I2C interface at
8136 * a specified device address.
b980ac18 8137 **/
441fc6fd 8138s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8139 u8 dev_addr, u8 data)
441fc6fd
CW		 8140{
8141 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8142 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8143 s32 status;
8144 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8145
8146 if (!this_client)
8147 return E1000_ERR_I2C;
8148
23d87824 8149 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8150 return E1000_ERR_SWFW_SYNC;
8151 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8152 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8153
8154 if (status)
8155 return E1000_ERR_I2C;
8156 else
23d87824 8157 return 0;
441fc6fd
CW		 8158
8159}
907b7835
LMV		 8160
8161int igb_reinit_queues(struct igb_adapter *adapter)
8162{
8163 struct net_device *netdev = adapter->netdev;
8164 struct pci_dev *pdev = adapter->pdev;
8165 int err = 0;
8166
8167 if (netif_running(netdev))
8168 igb_close(netdev);
8169
02ef6e1d 8170 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8171
8172 if (igb_init_interrupt_scheme(adapter, true)) {
8173 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8174 return -ENOMEM;
8175 }
8176
8177 if (netif_running(netdev))
8178 err = igb_open(netdev);
8179
8180 return err;
8181}
9d5c8243 8182/* igb_main.c */
Linux kernel - Deliverables
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