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igb: Do not use header split, instead receive all frames into a single buffer
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
6e861326 4 Copyright(c) 2007-2012 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
9d5c8243
AK		 60#include "igb.h"
61
200e5fd5
CW		 62#define MAJ 4
63#define MIN 0
64#define BUILD 1
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
6e861326 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
9d5c8243 72
9d5c8243
AK		 73static const struct e1000_info *igb_info_tbl[] = {
74 [board_82575] = &e1000_82575_info,
75};
76
a3aa1884 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
108 /* required last entry */
109 {0, }
110};
111
112MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
113
114void igb_reset(struct igb_adapter *);
115static int igb_setup_all_tx_resources(struct igb_adapter *);
116static int igb_setup_all_rx_resources(struct igb_adapter *);
117static void igb_free_all_tx_resources(struct igb_adapter *);
118static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 119static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243
AK		 120static int igb_probe(struct pci_dev *, const struct pci_device_id *);
121static void __devexit igb_remove(struct pci_dev *pdev);
122static int igb_sw_init(struct igb_adapter *);
123static int igb_open(struct net_device *);
124static int igb_close(struct net_device *);
125static void igb_configure_tx(struct igb_adapter *);
126static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 127static void igb_clean_all_tx_rings(struct igb_adapter *);
128static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 129static void igb_clean_tx_ring(struct igb_ring *);
130static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 131static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 132static void igb_update_phy_info(unsigned long);
133static void igb_watchdog(unsigned long);
134static void igb_watchdog_task(struct work_struct *);
cd392f5c 135static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 136static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
137 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 138static int igb_change_mtu(struct net_device *, int);
139static int igb_set_mac(struct net_device *, void *);
68d480c4 140static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 141static irqreturn_t igb_intr(int irq, void *);
142static irqreturn_t igb_intr_msi(int irq, void *);
143static irqreturn_t igb_msix_other(int irq, void *);
047e0030 144static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 145#ifdef CONFIG_IGB_DCA
047e0030 146static void igb_update_dca(struct igb_q_vector *);
fe4506b6 147static void igb_setup_dca(struct igb_adapter *);
421e02f0 148#endif /* CONFIG_IGB_DCA */
661086df 149static int igb_poll(struct napi_struct *, int);
13fde97a 150static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 151static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 152static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
153static void igb_tx_timeout(struct net_device *);
154static void igb_reset_task(struct work_struct *);
c8f44aff 155static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 156static int igb_vlan_rx_add_vid(struct net_device *, u16);
157static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 158static void igb_restore_vlan(struct igb_adapter *);
26ad9178 159static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 160static void igb_ping_all_vfs(struct igb_adapter *);
161static void igb_msg_task(struct igb_adapter *);
4ae196df 162static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 163static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 164static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 165static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
166static int igb_ndo_set_vf_vlan(struct net_device *netdev,
167 int vf, u16 vlan, u8 qos);
168static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
169static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
170 struct ifla_vf_info *ivi);
17dc566c 171static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 172
173#ifdef CONFIG_PCI_IOV
0224d663 174static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 175static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 176#endif
9d5c8243 177
9d5c8243 178#ifdef CONFIG_PM
d9dd966d 179#ifdef CONFIG_PM_SLEEP
749ab2cd 180static int igb_suspend(struct device *);
d9dd966d 181#endif
749ab2cd
YZ		 182static int igb_resume(struct device *);
183#ifdef CONFIG_PM_RUNTIME
184static int igb_runtime_suspend(struct device *dev);
185static int igb_runtime_resume(struct device *dev);
186static int igb_runtime_idle(struct device *dev);
187#endif
188static const struct dev_pm_ops igb_pm_ops = {
189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
191 igb_runtime_idle)
192};
9d5c8243
AK		 193#endif
194static void igb_shutdown(struct pci_dev *);
421e02f0 195#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 196static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
197static struct notifier_block dca_notifier = {
198 .notifier_call = igb_notify_dca,
199 .next = NULL,
200 .priority = 0
201};
202#endif
9d5c8243
AK		 203#ifdef CONFIG_NET_POLL_CONTROLLER
204/* for netdump / net console */
205static void igb_netpoll(struct net_device *);
206#endif
37680117 207#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 208static unsigned int max_vfs = 0;
209module_param(max_vfs, uint, 0);
210MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
211 "per physical function");
212#endif /* CONFIG_PCI_IOV */
213
9d5c8243
AK		 214static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
215 pci_channel_state_t);
216static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
217static void igb_io_resume(struct pci_dev *);
218
3646f0e5 219static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 220 .error_detected = igb_io_error_detected,
221 .slot_reset = igb_io_slot_reset,
222 .resume = igb_io_resume,
223};
224
b6e0c419 225static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 226
227static struct pci_driver igb_driver = {
228 .name = igb_driver_name,
229 .id_table = igb_pci_tbl,
230 .probe = igb_probe,
231 .remove = __devexit_p(igb_remove),
232#ifdef CONFIG_PM
749ab2cd 233 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 234#endif
235 .shutdown = igb_shutdown,
236 .err_handler = &igb_err_handler
237};
238
239MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
240MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
241MODULE_LICENSE("GPL");
242MODULE_VERSION(DRV_VERSION);
243
b3f4d599 244#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
245static int debug = -1;
246module_param(debug, int, 0);
247MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
248
c97ec42a
TI		 249struct igb_reg_info {
250 u32 ofs;
251 char *name;
252};
253
254static const struct igb_reg_info igb_reg_info_tbl[] = {
255
256 /* General Registers */
257 {E1000_CTRL, "CTRL"},
258 {E1000_STATUS, "STATUS"},
259 {E1000_CTRL_EXT, "CTRL_EXT"},
260
261 /* Interrupt Registers */
262 {E1000_ICR, "ICR"},
263
264 /* RX Registers */
265 {E1000_RCTL, "RCTL"},
266 {E1000_RDLEN(0), "RDLEN"},
267 {E1000_RDH(0), "RDH"},
268 {E1000_RDT(0), "RDT"},
269 {E1000_RXDCTL(0), "RXDCTL"},
270 {E1000_RDBAL(0), "RDBAL"},
271 {E1000_RDBAH(0), "RDBAH"},
272
273 /* TX Registers */
274 {E1000_TCTL, "TCTL"},
275 {E1000_TDBAL(0), "TDBAL"},
276 {E1000_TDBAH(0), "TDBAH"},
277 {E1000_TDLEN(0), "TDLEN"},
278 {E1000_TDH(0), "TDH"},
279 {E1000_TDT(0), "TDT"},
280 {E1000_TXDCTL(0), "TXDCTL"},
281 {E1000_TDFH, "TDFH"},
282 {E1000_TDFT, "TDFT"},
283 {E1000_TDFHS, "TDFHS"},
284 {E1000_TDFPC, "TDFPC"},
285
286 /* List Terminator */
287 {}
288};
289
290/*
291 * igb_regdump - register printout routine
292 */
293static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
294{
295 int n = 0;
296 char rname[16];
297 u32 regs[8];
298
299 switch (reginfo->ofs) {
300 case E1000_RDLEN(0):
301 for (n = 0; n < 4; n++)
302 regs[n] = rd32(E1000_RDLEN(n));
303 break;
304 case E1000_RDH(0):
305 for (n = 0; n < 4; n++)
306 regs[n] = rd32(E1000_RDH(n));
307 break;
308 case E1000_RDT(0):
309 for (n = 0; n < 4; n++)
310 regs[n] = rd32(E1000_RDT(n));
311 break;
312 case E1000_RXDCTL(0):
313 for (n = 0; n < 4; n++)
314 regs[n] = rd32(E1000_RXDCTL(n));
315 break;
316 case E1000_RDBAL(0):
317 for (n = 0; n < 4; n++)
318 regs[n] = rd32(E1000_RDBAL(n));
319 break;
320 case E1000_RDBAH(0):
321 for (n = 0; n < 4; n++)
322 regs[n] = rd32(E1000_RDBAH(n));
323 break;
324 case E1000_TDBAL(0):
325 for (n = 0; n < 4; n++)
326 regs[n] = rd32(E1000_RDBAL(n));
327 break;
328 case E1000_TDBAH(0):
329 for (n = 0; n < 4; n++)
330 regs[n] = rd32(E1000_TDBAH(n));
331 break;
332 case E1000_TDLEN(0):
333 for (n = 0; n < 4; n++)
334 regs[n] = rd32(E1000_TDLEN(n));
335 break;
336 case E1000_TDH(0):
337 for (n = 0; n < 4; n++)
338 regs[n] = rd32(E1000_TDH(n));
339 break;
340 case E1000_TDT(0):
341 for (n = 0; n < 4; n++)
342 regs[n] = rd32(E1000_TDT(n));
343 break;
344 case E1000_TXDCTL(0):
345 for (n = 0; n < 4; n++)
346 regs[n] = rd32(E1000_TXDCTL(n));
347 break;
348 default:
876d2d6f 349 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 350 return;
351 }
352
353 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 354 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
355 regs[2], regs[3]);
c97ec42a
TI		 356}
357
358/*
359 * igb_dump - Print registers, tx-rings and rx-rings
360 */
361static void igb_dump(struct igb_adapter *adapter)
362{
363 struct net_device *netdev = adapter->netdev;
364 struct e1000_hw *hw = &adapter->hw;
365 struct igb_reg_info *reginfo;
c97ec42a
TI		 366 struct igb_ring *tx_ring;
367 union e1000_adv_tx_desc *tx_desc;
368 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 369 struct igb_ring *rx_ring;
370 union e1000_adv_rx_desc *rx_desc;
371 u32 staterr;
6ad4edfc 372 u16 i, n;
c97ec42a
TI		 373
374 if (!netif_msg_hw(adapter))
375 return;
376
377 /* Print netdevice Info */
378 if (netdev) {
379 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 380 pr_info("Device Name state trans_start "
381 "last_rx\n");
382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 388 pr_info(" Register Name Value\n");
c97ec42a
TI		 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 400 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 401 struct igb_tx_buffer *buffer_info;
c97ec42a 402 tx_ring = adapter->tx_ring[n];
06034649 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
c97ec42a
TI		 410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
435 "[bi->dma ] leng ntw timestamp "
436 "bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
454 pr_info("T [0x%03X] %016llX %016llX %016llX"
455 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 456 le64_to_cpu(u0->a),
457 le64_to_cpu(u0->b),
c9f14bf3
AD		 458 (u64)dma_unmap_addr(buffer_info, dma),
459 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 460 buffer_info->next_to_watch,
461 (u64)buffer_info->time_stamp,
876d2d6f 462 buffer_info->skb, next_desc);
c97ec42a 463
b669588a 464 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 465 print_hex_dump(KERN_INFO, "",
466 DUMP_PREFIX_ADDRESS,
b669588a 467 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 468 dma_unmap_len(buffer_info, len),
469 true);
c97ec42a
TI		 470 }
471 }
472
473 /* Print RX Rings Summary */
474rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 476 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
516 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
517 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
518 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 519
520 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 521 const char *next_desc;
06034649
AD		 522 struct igb_rx_buffer *buffer_info;
523 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 524 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 525 u0 = (struct my_u0 *)rx_desc;
526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 527
528 if (i == rx_ring->next_to_use)
529 next_desc = " NTU";
530 else if (i == rx_ring->next_to_clean)
531 next_desc = " NTC";
532 else
533 next_desc = "";
534
c97ec42a
TI		 535 if (staterr & E1000_RXD_STAT_DD) {
536 /* Descriptor Done */
1a1c225b
AD		 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
538 "RWB", i,
c97ec42a
TI		 539 le64_to_cpu(u0->a),
540 le64_to_cpu(u0->b),
1a1c225b 541 next_desc);
c97ec42a 542 } else {
1a1c225b
AD		 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
544 "R ", i,
c97ec42a
TI		 545 le64_to_cpu(u0->a),
546 le64_to_cpu(u0->b),
547 (u64)buffer_info->dma,
1a1c225b 548 next_desc);
c97ec42a 549
b669588a 550 if (netif_msg_pktdata(adapter) &&
1a1c225b 551 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 552 print_hex_dump(KERN_INFO, "",
553 DUMP_PREFIX_ADDRESS,
554 16, 1,
b669588a
ET		 555 page_address(buffer_info->page) +
556 buffer_info->page_offset,
44390ca6 557 PAGE_SIZE/2, true);
c97ec42a
TI		 558 }
559 }
c97ec42a
TI		 560 }
561 }
562
563exit:
564 return;
565}
566
9d5c8243 567/**
c041076a 568 * igb_get_hw_dev - return device
9d5c8243
AK		 569 * used by hardware layer to print debugging information
570 **/
c041076a 571struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 572{
573 struct igb_adapter *adapter = hw->back;
c041076a 574 return adapter->netdev;
9d5c8243 575}
38c845c7 576
9d5c8243
AK		 577/**
578 * igb_init_module - Driver Registration Routine
579 *
580 * igb_init_module is the first routine called when the driver is
581 * loaded. All it does is register with the PCI subsystem.
582 **/
583static int __init igb_init_module(void)
584{
585 int ret;
876d2d6f 586 pr_info("%s - version %s\n",
9d5c8243
AK		 587 igb_driver_string, igb_driver_version);
588
876d2d6f 589 pr_info("%s\n", igb_copyright);
9d5c8243 590
421e02f0 591#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 592 dca_register_notify(&dca_notifier);
593#endif
bbd98fe4 594 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 595 return ret;
596}
597
598module_init(igb_init_module);
599
600/**
601 * igb_exit_module - Driver Exit Cleanup Routine
602 *
603 * igb_exit_module is called just before the driver is removed
604 * from memory.
605 **/
606static void __exit igb_exit_module(void)
607{
421e02f0 608#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 609 dca_unregister_notify(&dca_notifier);
610#endif
9d5c8243
AK		 611 pci_unregister_driver(&igb_driver);
612}
613
614module_exit(igb_exit_module);
615
26bc19ec
AD		 616#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
617/**
618 * igb_cache_ring_register - Descriptor ring to register mapping
619 * @adapter: board private structure to initialize
620 *
621 * Once we know the feature-set enabled for the device, we'll cache
622 * the register offset the descriptor ring is assigned to.
623 **/
624static void igb_cache_ring_register(struct igb_adapter *adapter)
625{
ee1b9f06 626 int i = 0, j = 0;
047e0030 627 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 628
629 switch (adapter->hw.mac.type) {
630 case e1000_82576:
631 /* The queues are allocated for virtualization such that VF 0
632 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
633 * In order to avoid collision we start at the first free queue
634 * and continue consuming queues in the same sequence
635 */
ee1b9f06 636 if (adapter->vfs_allocated_count) {
a99955fc 637 for (; i < adapter->rss_queues; i++)
3025a446
AD		 638 adapter->rx_ring[i]->reg_idx = rbase_offset +
639 Q_IDX_82576(i);
ee1b9f06 640 }
26bc19ec 641 case e1000_82575:
55cac248 642 case e1000_82580:
d2ba2ed8 643 case e1000_i350:
f96a8a0b
CW		 644 case e1000_i210:
645 case e1000_i211:
26bc19ec 646 default:
ee1b9f06 647 for (; i < adapter->num_rx_queues; i++)
3025a446 648 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 649 for (; j < adapter->num_tx_queues; j++)
3025a446 650 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 651 break;
652 }
653}
654
047e0030
AD		 655static void igb_free_queues(struct igb_adapter *adapter)
656{
3025a446 657 int i;
047e0030 658
3025a446
AD		 659 for (i = 0; i < adapter->num_tx_queues; i++) {
660 kfree(adapter->tx_ring[i]);
661 adapter->tx_ring[i] = NULL;
662 }
663 for (i = 0; i < adapter->num_rx_queues; i++) {
664 kfree(adapter->rx_ring[i]);
665 adapter->rx_ring[i] = NULL;
666 }
047e0030
AD		 667 adapter->num_rx_queues = 0;
668 adapter->num_tx_queues = 0;
669}
670
9d5c8243
AK		 671/**
672 * igb_alloc_queues - Allocate memory for all rings
673 * @adapter: board private structure to initialize
674 *
675 * We allocate one ring per queue at run-time since we don't know the
676 * number of queues at compile-time.
677 **/
678static int igb_alloc_queues(struct igb_adapter *adapter)
679{
3025a446 680 struct igb_ring *ring;
9d5c8243
AK		 681 int i;
682
661086df 683 for (i = 0; i < adapter->num_tx_queues; i++) {
f33005a6 684 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
3025a446
AD		 685 if (!ring)
686 goto err;
68fd9910 687 ring->count = adapter->tx_ring_count;
661086df 688 ring->queue_index = i;
59d71989 689 ring->dev = &adapter->pdev->dev;
e694e964 690 ring->netdev = adapter->netdev;
85ad76b2
AD		 691 /* For 82575, context index must be unique per ring. */
692 if (adapter->hw.mac.type == e1000_82575)
866cff06 693 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
3025a446 694 adapter->tx_ring[i] = ring;
661086df 695 }
85ad76b2 696
9d5c8243 697 for (i = 0; i < adapter->num_rx_queues; i++) {
f33005a6 698 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
3025a446
AD		 699 if (!ring)
700 goto err;
68fd9910 701 ring->count = adapter->rx_ring_count;
844290e5 702 ring->queue_index = i;
59d71989 703 ring->dev = &adapter->pdev->dev;
e694e964 704 ring->netdev = adapter->netdev;
85ad76b2
AD		 705 /* set flag indicating ring supports SCTP checksum offload */
706 if (adapter->hw.mac.type >= e1000_82576)
866cff06 707 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
8be10e91 708
f96a8a0b
CW		 709 /*
710 * On i350, i210, and i211, loopback VLAN packets
711 * have the tag byte-swapped.
712 * */
713 if (adapter->hw.mac.type >= e1000_i350)
8be10e91
AD		 714 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
715
3025a446 716 adapter->rx_ring[i] = ring;
9d5c8243 717 }
26bc19ec
AD		 718
719 igb_cache_ring_register(adapter);
9d5c8243 720
047e0030 721 return 0;
a88f10ec 722
047e0030
AD		 723err:
724 igb_free_queues(adapter);
d1a8c9e1 725
047e0030 726 return -ENOMEM;
a88f10ec
AD		 727}
728
4be000c8
AD		 729/**
730 * igb_write_ivar - configure ivar for given MSI-X vector
731 * @hw: pointer to the HW structure
732 * @msix_vector: vector number we are allocating to a given ring
733 * @index: row index of IVAR register to write within IVAR table
734 * @offset: column offset of in IVAR, should be multiple of 8
735 *
736 * This function is intended to handle the writing of the IVAR register
737 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
738 * each containing an cause allocation for an Rx and Tx ring, and a
739 * variable number of rows depending on the number of queues supported.
740 **/
741static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
742 int index, int offset)
743{
744 u32 ivar = array_rd32(E1000_IVAR0, index);
745
746 /* clear any bits that are currently set */
747 ivar &= ~((u32)0xFF << offset);
748
749 /* write vector and valid bit */
750 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
751
752 array_wr32(E1000_IVAR0, index, ivar);
753}
754
9d5c8243 755#define IGB_N0_QUEUE -1
047e0030 756static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 757{
047e0030 758 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 759 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 760 int rx_queue = IGB_N0_QUEUE;
761 int tx_queue = IGB_N0_QUEUE;
4be000c8 762 u32 msixbm = 0;
047e0030 763
0ba82994
AD		 764 if (q_vector->rx.ring)
765 rx_queue = q_vector->rx.ring->reg_idx;
766 if (q_vector->tx.ring)
767 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 768
769 switch (hw->mac.type) {
770 case e1000_82575:
9d5c8243
AK		 771 /* The 82575 assigns vectors using a bitmask, which matches the
772 bitmask for the EICR/EIMS/EIMC registers. To assign one
773 or more queues to a vector, we write the appropriate bits
774 into the MSIXBM register for that vector. */
047e0030 775 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 776 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 777 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 778 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 779 if (!adapter->msix_entries && msix_vector == 0)
780 msixbm |= E1000_EIMS_OTHER;
9d5c8243 781 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 782 q_vector->eims_value = msixbm;
2d064c06
AD		 783 break;
784 case e1000_82576:
4be000c8
AD		 785 /*
786 * 82576 uses a table that essentially consists of 2 columns
787 * with 8 rows. The ordering is column-major so we use the
788 * lower 3 bits as the row index, and the 4th bit as the
789 * column offset.
790 */
791 if (rx_queue > IGB_N0_QUEUE)
792 igb_write_ivar(hw, msix_vector,
793 rx_queue & 0x7,
794 (rx_queue & 0x8) << 1);
795 if (tx_queue > IGB_N0_QUEUE)
796 igb_write_ivar(hw, msix_vector,
797 tx_queue & 0x7,
798 ((tx_queue & 0x8) << 1) + 8);
047e0030 799 q_vector->eims_value = 1 << msix_vector;
2d064c06 800 break;
55cac248 801 case e1000_82580:
d2ba2ed8 802 case e1000_i350:
f96a8a0b
CW		 803 case e1000_i210:
804 case e1000_i211:
4be000c8
AD		 805 /*
806 * On 82580 and newer adapters the scheme is similar to 82576
807 * however instead of ordering column-major we have things
808 * ordered row-major. So we traverse the table by using
809 * bit 0 as the column offset, and the remaining bits as the
810 * row index.
811 */
812 if (rx_queue > IGB_N0_QUEUE)
813 igb_write_ivar(hw, msix_vector,
814 rx_queue >> 1,
815 (rx_queue & 0x1) << 4);
816 if (tx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 tx_queue >> 1,
819 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 820 q_vector->eims_value = 1 << msix_vector;
821 break;
2d064c06
AD		 822 default:
823 BUG();
824 break;
825 }
26b39276
AD		 826
827 /* add q_vector eims value to global eims_enable_mask */
828 adapter->eims_enable_mask |= q_vector->eims_value;
829
830 /* configure q_vector to set itr on first interrupt */
831 q_vector->set_itr = 1;
9d5c8243
AK		 832}
833
834/**
835 * igb_configure_msix - Configure MSI-X hardware
836 *
837 * igb_configure_msix sets up the hardware to properly
838 * generate MSI-X interrupts.
839 **/
840static void igb_configure_msix(struct igb_adapter *adapter)
841{
842 u32 tmp;
843 int i, vector = 0;
844 struct e1000_hw *hw = &adapter->hw;
845
846 adapter->eims_enable_mask = 0;
9d5c8243
AK		 847
848 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 849 switch (hw->mac.type) {
850 case e1000_82575:
9d5c8243
AK		 851 tmp = rd32(E1000_CTRL_EXT);
852 /* enable MSI-X PBA support*/
853 tmp |= E1000_CTRL_EXT_PBA_CLR;
854
855 /* Auto-Mask interrupts upon ICR read. */
856 tmp |= E1000_CTRL_EXT_EIAME;
857 tmp |= E1000_CTRL_EXT_IRCA;
858
859 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 860
861 /* enable msix_other interrupt */
862 array_wr32(E1000_MSIXBM(0), vector++,
863 E1000_EIMS_OTHER);
844290e5 864 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 865
2d064c06
AD		 866 break;
867
868 case e1000_82576:
55cac248 869 case e1000_82580:
d2ba2ed8 870 case e1000_i350:
f96a8a0b
CW		 871 case e1000_i210:
872 case e1000_i211:
047e0030
AD		 873 /* Turn on MSI-X capability first, or our settings
874 * won't stick. And it will take days to debug. */
875 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
876 E1000_GPIE_PBA | E1000_GPIE_EIAME |
877 E1000_GPIE_NSICR);
878
879 /* enable msix_other interrupt */
880 adapter->eims_other = 1 << vector;
2d064c06 881 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 882
047e0030 883 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 884 break;
885 default:
886 /* do nothing, since nothing else supports MSI-X */
887 break;
888 } /* switch (hw->mac.type) */
047e0030
AD		 889
890 adapter->eims_enable_mask |= adapter->eims_other;
891
26b39276
AD		 892 for (i = 0; i < adapter->num_q_vectors; i++)
893 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 894
9d5c8243
AK		 895 wrfl();
896}
897
898/**
899 * igb_request_msix - Initialize MSI-X interrupts
900 *
901 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
902 * kernel.
903 **/
904static int igb_request_msix(struct igb_adapter *adapter)
905{
906 struct net_device *netdev = adapter->netdev;
047e0030 907 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 908 int i, err = 0, vector = 0;
909
047e0030 910 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 911 igb_msix_other, 0, netdev->name, adapter);
047e0030
AD		 912 if (err)
913 goto out;
914 vector++;
915
916 for (i = 0; i < adapter->num_q_vectors; i++) {
917 struct igb_q_vector *q_vector = adapter->q_vector[i];
918
919 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
920
0ba82994 921 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 922 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 923 q_vector->rx.ring->queue_index);
924 else if (q_vector->tx.ring)
047e0030 925 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 926 q_vector->tx.ring->queue_index);
927 else if (q_vector->rx.ring)
047e0030 928 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 929 q_vector->rx.ring->queue_index);
9d5c8243 930 else
047e0030
AD		 931 sprintf(q_vector->name, "%s-unused", netdev->name);
932
9d5c8243 933 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 934 igb_msix_ring, 0, q_vector->name,
047e0030 935 q_vector);
9d5c8243
AK		 936 if (err)
937 goto out;
9d5c8243
AK		 938 vector++;
939 }
940
9d5c8243
AK		 941 igb_configure_msix(adapter);
942 return 0;
943out:
944 return err;
945}
946
947static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
948{
949 if (adapter->msix_entries) {
950 pci_disable_msix(adapter->pdev);
951 kfree(adapter->msix_entries);
952 adapter->msix_entries = NULL;
047e0030 953 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 954 pci_disable_msi(adapter->pdev);
047e0030 955 }
9d5c8243
AK		 956}
957
047e0030
AD		 958/**
959 * igb_free_q_vectors - Free memory allocated for interrupt vectors
960 * @adapter: board private structure to initialize
961 *
962 * This function frees the memory allocated to the q_vectors. In addition if
963 * NAPI is enabled it will delete any references to the NAPI struct prior
964 * to freeing the q_vector.
965 **/
966static void igb_free_q_vectors(struct igb_adapter *adapter)
967{
968 int v_idx;
969
970 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
971 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
972 adapter->q_vector[v_idx] = NULL;
fe0592b4
NN		 973 if (!q_vector)
974 continue;
047e0030
AD		 975 netif_napi_del(&q_vector->napi);
976 kfree(q_vector);
977 }
978 adapter->num_q_vectors = 0;
979}
980
981/**
982 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
983 *
984 * This function resets the device so that it has 0 rx queues, tx queues, and
985 * MSI-X interrupts allocated.
986 */
987static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
988{
989 igb_free_queues(adapter);
990 igb_free_q_vectors(adapter);
991 igb_reset_interrupt_capability(adapter);
992}
9d5c8243
AK		 993
994/**
995 * igb_set_interrupt_capability - set MSI or MSI-X if supported
996 *
997 * Attempt to configure interrupts using the best available
998 * capabilities of the hardware and kernel.
999 **/
21adef3e 1000static int igb_set_interrupt_capability(struct igb_adapter *adapter)
9d5c8243
AK		 1001{
1002 int err;
1003 int numvecs, i;
1004
83b7180d 1005 /* Number of supported queues. */
a99955fc 1006 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1007 if (adapter->vfs_allocated_count)
1008 adapter->num_tx_queues = 1;
1009 else
1010 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1011
047e0030
AD		 1012 /* start with one vector for every rx queue */
1013 numvecs = adapter->num_rx_queues;
1014
3ad2f3fb 1015 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 1016 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1017 numvecs += adapter->num_tx_queues;
047e0030
AD		 1018
1019 /* store the number of vectors reserved for queues */
1020 adapter->num_q_vectors = numvecs;
1021
1022 /* add 1 vector for link status interrupts */
1023 numvecs++;
9d5c8243
AK		 1024 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1025 GFP_KERNEL);
f96a8a0b 1026
9d5c8243
AK		 1027 if (!adapter->msix_entries)
1028 goto msi_only;
1029
1030 for (i = 0; i < numvecs; i++)
1031 adapter->msix_entries[i].entry = i;
1032
1033 err = pci_enable_msix(adapter->pdev,
1034 adapter->msix_entries,
1035 numvecs);
1036 if (err == 0)
34a20e89 1037 goto out;
9d5c8243
AK		 1038
1039 igb_reset_interrupt_capability(adapter);
1040
1041 /* If we can't do MSI-X, try MSI */
1042msi_only:
2a3abf6d
AD		 1043#ifdef CONFIG_PCI_IOV
1044 /* disable SR-IOV for non MSI-X configurations */
1045 if (adapter->vf_data) {
1046 struct e1000_hw *hw = &adapter->hw;
1047 /* disable iov and allow time for transactions to clear */
1048 pci_disable_sriov(adapter->pdev);
1049 msleep(500);
1050
1051 kfree(adapter->vf_data);
1052 adapter->vf_data = NULL;
1053 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1054 wrfl();
2a3abf6d
AD		 1055 msleep(100);
1056 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1057 }
1058#endif
4fc82adf 1059 adapter->vfs_allocated_count = 0;
a99955fc 1060 adapter->rss_queues = 1;
4fc82adf 1061 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1062 adapter->num_rx_queues = 1;
661086df 1063 adapter->num_tx_queues = 1;
047e0030 1064 adapter->num_q_vectors = 1;
9d5c8243 1065 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1066 adapter->flags |= IGB_FLAG_HAS_MSI;
34a20e89 1067out:
21adef3e 1068 /* Notify the stack of the (possibly) reduced queue counts. */
cfb8c3aa 1069 rtnl_lock();
21adef3e 1070 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
cfb8c3aa
BP		 1071 err = netif_set_real_num_rx_queues(adapter->netdev,
1072 adapter->num_rx_queues);
1073 rtnl_unlock();
1074 return err;
9d5c8243
AK		 1075}
1076
047e0030
AD		 1077/**
1078 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1079 * @adapter: board private structure to initialize
1080 *
1081 * We allocate one q_vector per queue interrupt. If allocation fails we
1082 * return -ENOMEM.
1083 **/
1084static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1085{
1086 struct igb_q_vector *q_vector;
1087 struct e1000_hw *hw = &adapter->hw;
1088 int v_idx;
1089
1090 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
f33005a6
AD		 1091 q_vector = kzalloc(sizeof(struct igb_q_vector),
1092 GFP_KERNEL);
047e0030
AD		 1093 if (!q_vector)
1094 goto err_out;
1095 q_vector->adapter = adapter;
047e0030
AD		 1096 q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
1097 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1098 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
1099 adapter->q_vector[v_idx] = q_vector;
1100 }
81c2fc22 1101
047e0030
AD		 1102 return 0;
1103
1104err_out:
fe0592b4 1105 igb_free_q_vectors(adapter);
047e0030
AD		 1106 return -ENOMEM;
1107}
1108
1109static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
1110 int ring_idx, int v_idx)
1111{
3025a446 1112 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1113
0ba82994
AD		 1114 q_vector->rx.ring = adapter->rx_ring[ring_idx];
1115 q_vector->rx.ring->q_vector = q_vector;
1116 q_vector->rx.count++;
4fc82adf
AD		 1117 q_vector->itr_val = adapter->rx_itr_setting;
1118 if (q_vector->itr_val && q_vector->itr_val <= 3)
1119 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1120}
1121
1122static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
1123 int ring_idx, int v_idx)
1124{
3025a446 1125 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
047e0030 1126
0ba82994
AD		 1127 q_vector->tx.ring = adapter->tx_ring[ring_idx];
1128 q_vector->tx.ring->q_vector = q_vector;
1129 q_vector->tx.count++;
4fc82adf 1130 q_vector->itr_val = adapter->tx_itr_setting;
0ba82994 1131 q_vector->tx.work_limit = adapter->tx_work_limit;
4fc82adf
AD		 1132 if (q_vector->itr_val && q_vector->itr_val <= 3)
1133 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 1134}
1135
1136/**
1137 * igb_map_ring_to_vector - maps allocated queues to vectors
1138 *
1139 * This function maps the recently allocated queues to vectors.
1140 **/
1141static int igb_map_ring_to_vector(struct igb_adapter *adapter)
1142{
1143 int i;
1144 int v_idx = 0;
1145
1146 if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
1147 (adapter->num_q_vectors < adapter->num_tx_queues))
1148 return -ENOMEM;
1149
1150 if (adapter->num_q_vectors >=
1151 (adapter->num_rx_queues + adapter->num_tx_queues)) {
1152 for (i = 0; i < adapter->num_rx_queues; i++)
1153 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1154 for (i = 0; i < adapter->num_tx_queues; i++)
1155 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1156 } else {
1157 for (i = 0; i < adapter->num_rx_queues; i++) {
1158 if (i < adapter->num_tx_queues)
1159 igb_map_tx_ring_to_vector(adapter, i, v_idx);
1160 igb_map_rx_ring_to_vector(adapter, i, v_idx++);
1161 }
1162 for (; i < adapter->num_tx_queues; i++)
1163 igb_map_tx_ring_to_vector(adapter, i, v_idx++);
1164 }
1165 return 0;
1166}
1167
1168/**
1169 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1170 *
1171 * This function initializes the interrupts and allocates all of the queues.
1172 **/
1173static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
1174{
1175 struct pci_dev *pdev = adapter->pdev;
1176 int err;
1177
21adef3e
BH		 1178 err = igb_set_interrupt_capability(adapter);
1179 if (err)
1180 return err;
047e0030
AD		 1181
1182 err = igb_alloc_q_vectors(adapter);
1183 if (err) {
1184 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1185 goto err_alloc_q_vectors;
1186 }
1187
1188 err = igb_alloc_queues(adapter);
1189 if (err) {
1190 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1191 goto err_alloc_queues;
1192 }
1193
1194 err = igb_map_ring_to_vector(adapter);
1195 if (err) {
1196 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
1197 goto err_map_queues;
1198 }
1199
1200
1201 return 0;
1202err_map_queues:
1203 igb_free_queues(adapter);
1204err_alloc_queues:
1205 igb_free_q_vectors(adapter);
1206err_alloc_q_vectors:
1207 igb_reset_interrupt_capability(adapter);
1208 return err;
1209}
1210
9d5c8243
AK		 1211/**
1212 * igb_request_irq - initialize interrupts
1213 *
1214 * Attempts to configure interrupts using the best available
1215 * capabilities of the hardware and kernel.
1216 **/
1217static int igb_request_irq(struct igb_adapter *adapter)
1218{
1219 struct net_device *netdev = adapter->netdev;
047e0030 1220 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1221 int err = 0;
1222
1223 if (adapter->msix_entries) {
1224 err = igb_request_msix(adapter);
844290e5 1225 if (!err)
9d5c8243 1226 goto request_done;
9d5c8243 1227 /* fall back to MSI */
047e0030 1228 igb_clear_interrupt_scheme(adapter);
c74d588e 1229 if (!pci_enable_msi(pdev))
7dfc16fa 1230 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1231 igb_free_all_tx_resources(adapter);
1232 igb_free_all_rx_resources(adapter);
047e0030 1233 adapter->num_tx_queues = 1;
9d5c8243 1234 adapter->num_rx_queues = 1;
047e0030
AD		 1235 adapter->num_q_vectors = 1;
1236 err = igb_alloc_q_vectors(adapter);
1237 if (err) {
1238 dev_err(&pdev->dev,
1239 "Unable to allocate memory for vectors\n");
1240 goto request_done;
1241 }
1242 err = igb_alloc_queues(adapter);
1243 if (err) {
1244 dev_err(&pdev->dev,
1245 "Unable to allocate memory for queues\n");
1246 igb_free_q_vectors(adapter);
1247 goto request_done;
1248 }
1249 igb_setup_all_tx_resources(adapter);
1250 igb_setup_all_rx_resources(adapter);
9d5c8243 1251 }
844290e5 1252
c74d588e
AD		 1253 igb_assign_vector(adapter->q_vector[0], 0);
1254
7dfc16fa 1255 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1256 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1257 netdev->name, adapter);
9d5c8243
AK		 1258 if (!err)
1259 goto request_done;
047e0030 1260
9d5c8243
AK		 1261 /* fall back to legacy interrupts */
1262 igb_reset_interrupt_capability(adapter);
7dfc16fa 1263 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1264 }
1265
c74d588e 1266 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1267 netdev->name, adapter);
9d5c8243 1268
6cb5e577 1269 if (err)
c74d588e 1270 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1271 err);
9d5c8243
AK		 1272
1273request_done:
1274 return err;
1275}
1276
1277static void igb_free_irq(struct igb_adapter *adapter)
1278{
9d5c8243
AK		 1279 if (adapter->msix_entries) {
1280 int vector = 0, i;
1281
047e0030 1282 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1283
0d1ae7f4 1284 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1285 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1286 adapter->q_vector[i]);
047e0030
AD		 1287 } else {
1288 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1289 }
9d5c8243
AK		 1290}
1291
1292/**
1293 * igb_irq_disable - Mask off interrupt generation on the NIC
1294 * @adapter: board private structure
1295 **/
1296static void igb_irq_disable(struct igb_adapter *adapter)
1297{
1298 struct e1000_hw *hw = &adapter->hw;
1299
25568a53
AD		 1300 /*
1301 * we need to be careful when disabling interrupts. The VFs are also
1302 * mapped into these registers and so clearing the bits can cause
1303 * issues on the VF drivers so we only need to clear what we set
1304 */
9d5c8243 1305 if (adapter->msix_entries) {
2dfd1212
AD		 1306 u32 regval = rd32(E1000_EIAM);
1307 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1308 wr32(E1000_EIMC, adapter->eims_enable_mask);
1309 regval = rd32(E1000_EIAC);
1310 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1311 }
844290e5
PW		 1312
1313 wr32(E1000_IAM, 0);
9d5c8243
AK		 1314 wr32(E1000_IMC, ~0);
1315 wrfl();
81a61859
ET		 1316 if (adapter->msix_entries) {
1317 int i;
1318 for (i = 0; i < adapter->num_q_vectors; i++)
1319 synchronize_irq(adapter->msix_entries[i].vector);
1320 } else {
1321 synchronize_irq(adapter->pdev->irq);
1322 }
9d5c8243
AK		 1323}
1324
1325/**
1326 * igb_irq_enable - Enable default interrupt generation settings
1327 * @adapter: board private structure
1328 **/
1329static void igb_irq_enable(struct igb_adapter *adapter)
1330{
1331 struct e1000_hw *hw = &adapter->hw;
1332
1333 if (adapter->msix_entries) {
06218a8d 1334 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1335 u32 regval = rd32(E1000_EIAC);
1336 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1337 regval = rd32(E1000_EIAM);
1338 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1339 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1340 if (adapter->vfs_allocated_count) {
4ae196df 1341 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1342 ims |= E1000_IMS_VMMB;
1343 }
1344 wr32(E1000_IMS, ims);
844290e5 1345 } else {
55cac248
AD		 1346 wr32(E1000_IMS, IMS_ENABLE_MASK |
1347 E1000_IMS_DRSTA);
1348 wr32(E1000_IAM, IMS_ENABLE_MASK |
1349 E1000_IMS_DRSTA);
844290e5 1350 }
9d5c8243
AK		 1351}
1352
1353static void igb_update_mng_vlan(struct igb_adapter *adapter)
1354{
51466239 1355 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1356 u16 vid = adapter->hw.mng_cookie.vlan_id;
1357 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1358
1359 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1360 /* add VID to filter table */
1361 igb_vfta_set(hw, vid, true);
1362 adapter->mng_vlan_id = vid;
1363 } else {
1364 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1365 }
1366
1367 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1368 (vid != old_vid) &&
b2cb09b1 1369 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1370 /* remove VID from filter table */
1371 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1372 }
1373}
1374
1375/**
1376 * igb_release_hw_control - release control of the h/w to f/w
1377 * @adapter: address of board private structure
1378 *
1379 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1380 * For ASF and Pass Through versions of f/w this means that the
1381 * driver is no longer loaded.
1382 *
1383 **/
1384static void igb_release_hw_control(struct igb_adapter *adapter)
1385{
1386 struct e1000_hw *hw = &adapter->hw;
1387 u32 ctrl_ext;
1388
1389 /* Let firmware take over control of h/w */
1390 ctrl_ext = rd32(E1000_CTRL_EXT);
1391 wr32(E1000_CTRL_EXT,
1392 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1393}
1394
9d5c8243
AK		 1395/**
1396 * igb_get_hw_control - get control of the h/w from f/w
1397 * @adapter: address of board private structure
1398 *
1399 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1400 * For ASF and Pass Through versions of f/w this means that
1401 * the driver is loaded.
1402 *
1403 **/
1404static void igb_get_hw_control(struct igb_adapter *adapter)
1405{
1406 struct e1000_hw *hw = &adapter->hw;
1407 u32 ctrl_ext;
1408
1409 /* Let firmware know the driver has taken over */
1410 ctrl_ext = rd32(E1000_CTRL_EXT);
1411 wr32(E1000_CTRL_EXT,
1412 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1413}
1414
9d5c8243
AK		 1415/**
1416 * igb_configure - configure the hardware for RX and TX
1417 * @adapter: private board structure
1418 **/
1419static void igb_configure(struct igb_adapter *adapter)
1420{
1421 struct net_device *netdev = adapter->netdev;
1422 int i;
1423
1424 igb_get_hw_control(adapter);
ff41f8dc 1425 igb_set_rx_mode(netdev);
9d5c8243
AK		 1426
1427 igb_restore_vlan(adapter);
9d5c8243 1428
85b430b4 1429 igb_setup_tctl(adapter);
06cf2666 1430 igb_setup_mrqc(adapter);
9d5c8243 1431 igb_setup_rctl(adapter);
85b430b4
AD		 1432
1433 igb_configure_tx(adapter);
9d5c8243 1434 igb_configure_rx(adapter);
662d7205
AD		 1435
1436 igb_rx_fifo_flush_82575(&adapter->hw);
1437
c493ea45 1438 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1439 * at least 1 descriptor unused to make sure
1440 * next_to_use != next_to_clean */
1441 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1442 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1443 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1444 }
9d5c8243
AK		 1445}
1446
88a268c1
NN		 1447/**
1448 * igb_power_up_link - Power up the phy/serdes link
1449 * @adapter: address of board private structure
1450 **/
1451void igb_power_up_link(struct igb_adapter *adapter)
1452{
76886596
AA		 1453 igb_reset_phy(&adapter->hw);
1454
88a268c1
NN		 1455 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1456 igb_power_up_phy_copper(&adapter->hw);
1457 else
1458 igb_power_up_serdes_link_82575(&adapter->hw);
1459}
1460
1461/**
1462 * igb_power_down_link - Power down the phy/serdes link
1463 * @adapter: address of board private structure
1464 */
1465static void igb_power_down_link(struct igb_adapter *adapter)
1466{
1467 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1468 igb_power_down_phy_copper_82575(&adapter->hw);
1469 else
1470 igb_shutdown_serdes_link_82575(&adapter->hw);
1471}
9d5c8243
AK		 1472
1473/**
1474 * igb_up - Open the interface and prepare it to handle traffic
1475 * @adapter: board private structure
1476 **/
9d5c8243
AK		 1477int igb_up(struct igb_adapter *adapter)
1478{
1479 struct e1000_hw *hw = &adapter->hw;
1480 int i;
1481
1482 /* hardware has been reset, we need to reload some things */
1483 igb_configure(adapter);
1484
1485 clear_bit(__IGB_DOWN, &adapter->state);
1486
0d1ae7f4
AD		 1487 for (i = 0; i < adapter->num_q_vectors; i++)
1488 napi_enable(&(adapter->q_vector[i]->napi));
1489
844290e5 1490 if (adapter->msix_entries)
9d5c8243 1491 igb_configure_msix(adapter);
feeb2721
AD		 1492 else
1493 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1494
1495 /* Clear any pending interrupts. */
1496 rd32(E1000_ICR);
1497 igb_irq_enable(adapter);
1498
d4960307
AD		 1499 /* notify VFs that reset has been completed */
1500 if (adapter->vfs_allocated_count) {
1501 u32 reg_data = rd32(E1000_CTRL_EXT);
1502 reg_data |= E1000_CTRL_EXT_PFRSTD;
1503 wr32(E1000_CTRL_EXT, reg_data);
1504 }
1505
4cb9be7a
JB		 1506 netif_tx_start_all_queues(adapter->netdev);
1507
25568a53
AD		 1508 /* start the watchdog. */
1509 hw->mac.get_link_status = 1;
1510 schedule_work(&adapter->watchdog_task);
1511
9d5c8243
AK		 1512 return 0;
1513}
1514
1515void igb_down(struct igb_adapter *adapter)
1516{
9d5c8243 1517 struct net_device *netdev = adapter->netdev;
330a6d6a 1518 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1519 u32 tctl, rctl;
1520 int i;
1521
1522 /* signal that we're down so the interrupt handler does not
1523 * reschedule our watchdog timer */
1524 set_bit(__IGB_DOWN, &adapter->state);
1525
1526 /* disable receives in the hardware */
1527 rctl = rd32(E1000_RCTL);
1528 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1529 /* flush and sleep below */
1530
fd2ea0a7 1531 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1532
1533 /* disable transmits in the hardware */
1534 tctl = rd32(E1000_TCTL);
1535 tctl &= ~E1000_TCTL_EN;
1536 wr32(E1000_TCTL, tctl);
1537 /* flush both disables and wait for them to finish */
1538 wrfl();
1539 msleep(10);
1540
0d1ae7f4
AD		 1541 for (i = 0; i < adapter->num_q_vectors; i++)
1542 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1543
9d5c8243
AK		 1544 igb_irq_disable(adapter);
1545
1546 del_timer_sync(&adapter->watchdog_timer);
1547 del_timer_sync(&adapter->phy_info_timer);
1548
9d5c8243 1549 netif_carrier_off(netdev);
04fe6358
AD		 1550
1551 /* record the stats before reset*/
12dcd86b
ED		 1552 spin_lock(&adapter->stats64_lock);
1553 igb_update_stats(adapter, &adapter->stats64);
1554 spin_unlock(&adapter->stats64_lock);
04fe6358 1555
9d5c8243
AK		 1556 adapter->link_speed = 0;
1557 adapter->link_duplex = 0;
1558
3023682e
JK		 1559 if (!pci_channel_offline(adapter->pdev))
1560 igb_reset(adapter);
9d5c8243
AK		 1561 igb_clean_all_tx_rings(adapter);
1562 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1563#ifdef CONFIG_IGB_DCA
1564
1565 /* since we reset the hardware DCA settings were cleared */
1566 igb_setup_dca(adapter);
1567#endif
9d5c8243
AK		 1568}
1569
1570void igb_reinit_locked(struct igb_adapter *adapter)
1571{
1572 WARN_ON(in_interrupt());
1573 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1574 msleep(1);
1575 igb_down(adapter);
1576 igb_up(adapter);
1577 clear_bit(__IGB_RESETTING, &adapter->state);
1578}
1579
1580void igb_reset(struct igb_adapter *adapter)
1581{
090b1795 1582 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1583 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1584 struct e1000_mac_info *mac = &hw->mac;
1585 struct e1000_fc_info *fc = &hw->fc;
9d5c8243
AK		 1586 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1587 u16 hwm;
1588
1589 /* Repartition Pba for greater than 9k mtu
1590 * To take effect CTRL.RST is required.
1591 */
fa4dfae0 1592 switch (mac->type) {
d2ba2ed8 1593 case e1000_i350:
55cac248
AD		 1594 case e1000_82580:
1595 pba = rd32(E1000_RXPBS);
1596 pba = igb_rxpbs_adjust_82580(pba);
1597 break;
fa4dfae0 1598 case e1000_82576:
d249be54
AD		 1599 pba = rd32(E1000_RXPBS);
1600 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1601 break;
1602 case e1000_82575:
f96a8a0b
CW		 1603 case e1000_i210:
1604 case e1000_i211:
fa4dfae0
AD		 1605 default:
1606 pba = E1000_PBA_34K;
1607 break;
2d064c06 1608 }
9d5c8243 1609
2d064c06
AD		 1610 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1611 (mac->type < e1000_82576)) {
9d5c8243
AK		 1612 /* adjust PBA for jumbo frames */
1613 wr32(E1000_PBA, pba);
1614
1615 /* To maintain wire speed transmits, the Tx FIFO should be
1616 * large enough to accommodate two full transmit packets,
1617 * rounded up to the next 1KB and expressed in KB. Likewise,
1618 * the Rx FIFO should be large enough to accommodate at least
1619 * one full receive packet and is similarly rounded up and
1620 * expressed in KB. */
1621 pba = rd32(E1000_PBA);
1622 /* upper 16 bits has Tx packet buffer allocation size in KB */
1623 tx_space = pba >> 16;
1624 /* lower 16 bits has Rx packet buffer allocation size in KB */
1625 pba &= 0xffff;
1626 /* the tx fifo also stores 16 bytes of information about the tx
1627 * but don't include ethernet FCS because hardware appends it */
1628 min_tx_space = (adapter->max_frame_size +
85e8d004 1629 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1630 ETH_FCS_LEN) * 2;
1631 min_tx_space = ALIGN(min_tx_space, 1024);
1632 min_tx_space >>= 10;
1633 /* software strips receive CRC, so leave room for it */
1634 min_rx_space = adapter->max_frame_size;
1635 min_rx_space = ALIGN(min_rx_space, 1024);
1636 min_rx_space >>= 10;
1637
1638 /* If current Tx allocation is less than the min Tx FIFO size,
1639 * and the min Tx FIFO size is less than the current Rx FIFO
1640 * allocation, take space away from current Rx allocation */
1641 if (tx_space < min_tx_space &&
1642 ((min_tx_space - tx_space) < pba)) {
1643 pba = pba - (min_tx_space - tx_space);
1644
1645 /* if short on rx space, rx wins and must trump tx
1646 * adjustment */
1647 if (pba < min_rx_space)
1648 pba = min_rx_space;
1649 }
2d064c06 1650 wr32(E1000_PBA, pba);
9d5c8243 1651 }
9d5c8243
AK		 1652
1653 /* flow control settings */
1654 /* The high water mark must be low enough to fit one full frame
1655 * (or the size used for early receive) above it in the Rx FIFO.
1656 * Set it to the lower of:
1657 * - 90% of the Rx FIFO size, or
1658 * - the full Rx FIFO size minus one full frame */
1659 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1660 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1661
d405ea3e
AD		 1662 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1663 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1664 fc->pause_time = 0xFFFF;
1665 fc->send_xon = 1;
0cce119a 1666 fc->current_mode = fc->requested_mode;
9d5c8243 1667
4ae196df
AD		 1668 /* disable receive for all VFs and wait one second */
1669 if (adapter->vfs_allocated_count) {
1670 int i;
1671 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1672 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1673
1674 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1675 igb_ping_all_vfs(adapter);
4ae196df
AD		 1676
1677 /* disable transmits and receives */
1678 wr32(E1000_VFRE, 0);
1679 wr32(E1000_VFTE, 0);
1680 }
1681
9d5c8243 1682 /* Allow time for pending master requests to run */
330a6d6a 1683 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1684 wr32(E1000_WUC, 0);
1685
330a6d6a 1686 if (hw->mac.ops.init_hw(hw))
090b1795 1687 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1688
a27416bb
MV		 1689 /*
1690 * Flow control settings reset on hardware reset, so guarantee flow
1691 * control is off when forcing speed.
1692 */
1693 if (!hw->mac.autoneg)
1694 igb_force_mac_fc(hw);
1695
b6e0c419 1696 igb_init_dmac(adapter, pba);
88a268c1
NN		 1697 if (!netif_running(adapter->netdev))
1698 igb_power_down_link(adapter);
1699
9d5c8243
AK		 1700 igb_update_mng_vlan(adapter);
1701
1702 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1703 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1704
1f6e8178
MV		 1705#ifdef CONFIG_IGB_PTP
1706 /* Re-enable PTP, where applicable. */
1707 igb_ptp_reset(adapter);
1708#endif /* CONFIG_IGB_PTP */
1709
330a6d6a 1710 igb_get_phy_info(hw);
9d5c8243
AK		 1711}
1712
c8f44aff
MM		 1713static netdev_features_t igb_fix_features(struct net_device *netdev,
1714 netdev_features_t features)
b2cb09b1
JP		 1715{
1716 /*
1717 * Since there is no support for separate rx/tx vlan accel
1718 * enable/disable make sure tx flag is always in same state as rx.
1719 */
1720 if (features & NETIF_F_HW_VLAN_RX)
1721 features |= NETIF_F_HW_VLAN_TX;
1722 else
1723 features &= ~NETIF_F_HW_VLAN_TX;
1724
1725 return features;
1726}
1727
c8f44aff
MM		 1728static int igb_set_features(struct net_device *netdev,
1729 netdev_features_t features)
ac52caa3 1730{
c8f44aff 1731 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1732 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1733
b2cb09b1
JP		 1734 if (changed & NETIF_F_HW_VLAN_RX)
1735 igb_vlan_mode(netdev, features);
1736
89eaefb6
BG		 1737 if (!(changed & NETIF_F_RXALL))
1738 return 0;
1739
1740 netdev->features = features;
1741
1742 if (netif_running(netdev))
1743 igb_reinit_locked(adapter);
1744 else
1745 igb_reset(adapter);
1746
ac52caa3
MM		 1747 return 0;
1748}
1749
2e5c6922 1750static const struct net_device_ops igb_netdev_ops = {
559e9c49 1751 .ndo_open = igb_open,
2e5c6922 1752 .ndo_stop = igb_close,
cd392f5c 1753 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1754 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1755 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1756 .ndo_set_mac_address = igb_set_mac,
1757 .ndo_change_mtu = igb_change_mtu,
1758 .ndo_do_ioctl = igb_ioctl,
1759 .ndo_tx_timeout = igb_tx_timeout,
1760 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1761 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1762 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1763 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1764 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1765 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1766 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1767#ifdef CONFIG_NET_POLL_CONTROLLER
1768 .ndo_poll_controller = igb_netpoll,
1769#endif
b2cb09b1
JP		 1770 .ndo_fix_features = igb_fix_features,
1771 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1772};
1773
d67974f0
CW		 1774/**
1775 * igb_set_fw_version - Configure version string for ethtool
1776 * @adapter: adapter struct
1777 *
1778 **/
1779void igb_set_fw_version(struct igb_adapter *adapter)
1780{
1781 struct e1000_hw *hw = &adapter->hw;
1782 u16 eeprom_verh, eeprom_verl, comb_verh, comb_verl, comb_offset;
1783 u16 major, build, patch, fw_version;
1784 u32 etrack_id;
1785
1786 hw->nvm.ops.read(hw, 5, 1, &fw_version);
1787 if (adapter->hw.mac.type != e1000_i211) {
1788 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
1789 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
1790 etrack_id = (eeprom_verh << IGB_ETRACK_SHIFT) | eeprom_verl;
1791
1792 /* combo image version needs to be found */
1793 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1794 if ((comb_offset != 0x0) &&
1795 (comb_offset != IGB_NVM_VER_INVALID)) {
1796 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
1797 + 1), 1, &comb_verh);
1798 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
1799 1, &comb_verl);
1800
1801 /* Only display Option Rom if it exists and is valid */
1802 if ((comb_verh && comb_verl) &&
1803 ((comb_verh != IGB_NVM_VER_INVALID) &&
1804 (comb_verl != IGB_NVM_VER_INVALID))) {
1805 major = comb_verl >> IGB_COMB_VER_SHFT;
1806 build = (comb_verl << IGB_COMB_VER_SHFT) |
1807 (comb_verh >> IGB_COMB_VER_SHFT);
1808 patch = comb_verh & IGB_COMB_VER_MASK;
1809 snprintf(adapter->fw_version,
1810 sizeof(adapter->fw_version),
1811 "%d.%d%d, 0x%08x, %d.%d.%d",
1812 (fw_version & IGB_MAJOR_MASK) >>
1813 IGB_MAJOR_SHIFT,
1814 (fw_version & IGB_MINOR_MASK) >>
1815 IGB_MINOR_SHIFT,
1816 (fw_version & IGB_BUILD_MASK),
1817 etrack_id, major, build, patch);
1818 goto out;
1819 }
1820 }
1821 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1822 "%d.%d%d, 0x%08x",
1823 (fw_version & IGB_MAJOR_MASK) >> IGB_MAJOR_SHIFT,
1824 (fw_version & IGB_MINOR_MASK) >> IGB_MINOR_SHIFT,
1825 (fw_version & IGB_BUILD_MASK), etrack_id);
1826 } else {
1827 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1828 "%d.%d%d",
1829 (fw_version & IGB_MAJOR_MASK) >> IGB_MAJOR_SHIFT,
1830 (fw_version & IGB_MINOR_MASK) >> IGB_MINOR_SHIFT,
1831 (fw_version & IGB_BUILD_MASK));
1832 }
1833out:
1834 return;
1835}
1836
9d5c8243
AK		 1837/**
1838 * igb_probe - Device Initialization Routine
1839 * @pdev: PCI device information struct
1840 * @ent: entry in igb_pci_tbl
1841 *
1842 * Returns 0 on success, negative on failure
1843 *
1844 * igb_probe initializes an adapter identified by a pci_dev structure.
1845 * The OS initialization, configuring of the adapter private structure,
1846 * and a hardware reset occur.
1847 **/
1848static int __devinit igb_probe(struct pci_dev *pdev,
1849 const struct pci_device_id *ent)
1850{
1851 struct net_device *netdev;
1852 struct igb_adapter *adapter;
1853 struct e1000_hw *hw;
4337e993 1854 u16 eeprom_data = 0;
9835fd73 1855 s32 ret_val;
4337e993 1856 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1857 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1858 unsigned long mmio_start, mmio_len;
2d6a5e95 1859 int err, pci_using_dac;
9d5c8243 1860 u16 eeprom_apme_mask = IGB_EEPROM_APME;
9835fd73 1861 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1862
bded64a7
AG		 1863 /* Catch broken hardware that put the wrong VF device ID in
1864 * the PCIe SR-IOV capability.
1865 */
1866 if (pdev->is_virtfn) {
1867 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1868 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1869 return -EINVAL;
1870 }
1871
aed5dec3 1872 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1873 if (err)
1874 return err;
1875
1876 pci_using_dac = 0;
59d71989 1877 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1878 if (!err) {
59d71989 1879 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1880 if (!err)
1881 pci_using_dac = 1;
1882 } else {
59d71989 1883 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1884 if (err) {
59d71989 1885 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1886 if (err) {
1887 dev_err(&pdev->dev, "No usable DMA "
1888 "configuration, aborting\n");
1889 goto err_dma;
1890 }
1891 }
1892 }
1893
aed5dec3
AD		 1894 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1895 IORESOURCE_MEM),
1896 igb_driver_name);
9d5c8243
AK		 1897 if (err)
1898 goto err_pci_reg;
1899
19d5afd4 1900 pci_enable_pcie_error_reporting(pdev);
40a914fa 1901
9d5c8243 1902 pci_set_master(pdev);
c682fc23 1903 pci_save_state(pdev);
9d5c8243
AK		 1904
1905 err = -ENOMEM;
1bfaf07b 1906 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 1907 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1908 if (!netdev)
1909 goto err_alloc_etherdev;
1910
1911 SET_NETDEV_DEV(netdev, &pdev->dev);
1912
1913 pci_set_drvdata(pdev, netdev);
1914 adapter = netdev_priv(netdev);
1915 adapter->netdev = netdev;
1916 adapter->pdev = pdev;
1917 hw = &adapter->hw;
1918 hw->back = adapter;
b3f4d599 1919 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 1920
1921 mmio_start = pci_resource_start(pdev, 0);
1922 mmio_len = pci_resource_len(pdev, 0);
1923
1924 err = -EIO;
28b0759c
AD		 1925 hw->hw_addr = ioremap(mmio_start, mmio_len);
1926 if (!hw->hw_addr)
9d5c8243
AK		 1927 goto err_ioremap;
1928
2e5c6922 1929 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1930 igb_set_ethtool_ops(netdev);
9d5c8243 1931 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1932
1933 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1934
1935 netdev->mem_start = mmio_start;
1936 netdev->mem_end = mmio_start + mmio_len;
1937
9d5c8243
AK		 1938 /* PCI config space info */
1939 hw->vendor_id = pdev->vendor;
1940 hw->device_id = pdev->device;
1941 hw->revision_id = pdev->revision;
1942 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1943 hw->subsystem_device_id = pdev->subsystem_device;
1944
9d5c8243
AK		 1945 /* Copy the default MAC, PHY and NVM function pointers */
1946 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1947 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1948 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1949 /* Initialize skew-specific constants */
1950 err = ei->get_invariants(hw);
1951 if (err)
450c87c8 1952 goto err_sw_init;
9d5c8243 1953
450c87c8 1954 /* setup the private structure */
9d5c8243
AK		 1955 err = igb_sw_init(adapter);
1956 if (err)
1957 goto err_sw_init;
1958
1959 igb_get_bus_info_pcie(hw);
1960
1961 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1962
1963 /* Copper options */
1964 if (hw->phy.media_type == e1000_media_type_copper) {
1965 hw->phy.mdix = AUTO_ALL_MODES;
1966 hw->phy.disable_polarity_correction = false;
1967 hw->phy.ms_type = e1000_ms_hw_default;
1968 }
1969
1970 if (igb_check_reset_block(hw))
1971 dev_info(&pdev->dev,
1972 "PHY reset is blocked due to SOL/IDER session.\n");
1973
077887c3
AD		 1974 /*
1975 * features is initialized to 0 in allocation, it might have bits
1976 * set by igb_sw_init so we should use an or instead of an
1977 * assignment.
1978 */
1979 netdev->features |= NETIF_F_SG |
1980 NETIF_F_IP_CSUM |
1981 NETIF_F_IPV6_CSUM |
1982 NETIF_F_TSO |
1983 NETIF_F_TSO6 |
1984 NETIF_F_RXHASH |
1985 NETIF_F_RXCSUM |
1986 NETIF_F_HW_VLAN_RX |
1987 NETIF_F_HW_VLAN_TX;
1988
1989 /* copy netdev features into list of user selectable features */
1990 netdev->hw_features |= netdev->features;
89eaefb6 1991 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 1992
1993 /* set this bit last since it cannot be part of hw_features */
1994 netdev->features |= NETIF_F_HW_VLAN_FILTER;
1995
1996 netdev->vlan_features |= NETIF_F_TSO |
1997 NETIF_F_TSO6 |
1998 NETIF_F_IP_CSUM |
1999 NETIF_F_IPV6_CSUM |
2000 NETIF_F_SG;
48f29ffc 2001
6b8f0922
BG		 2002 netdev->priv_flags |= IFF_SUPP_NOFCS;
2003
7b872a55 2004 if (pci_using_dac) {
9d5c8243 2005 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2006 netdev->vlan_features |= NETIF_F_HIGHDMA;
2007 }
9d5c8243 2008
ac52caa3
MM		 2009 if (hw->mac.type >= e1000_82576) {
2010 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2011 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2012 }
b9473560 2013
01789349
JP		 2014 netdev->priv_flags |= IFF_UNICAST_FLT;
2015
330a6d6a 2016 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2017
2018 /* before reading the NVM, reset the controller to put the device in a
2019 * known good starting state */
2020 hw->mac.ops.reset_hw(hw);
2021
f96a8a0b
CW		 2022 /*
2023 * make sure the NVM is good , i211 parts have special NVM that
2024 * doesn't contain a checksum
2025 */
2026 if (hw->mac.type != e1000_i211) {
2027 if (hw->nvm.ops.validate(hw) < 0) {
2028 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2029 err = -EIO;
2030 goto err_eeprom;
2031 }
9d5c8243
AK		 2032 }
2033
2034 /* copy the MAC address out of the NVM */
2035 if (hw->mac.ops.read_mac_addr(hw))
2036 dev_err(&pdev->dev, "NVM Read Error\n");
2037
2038 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2039 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2040
2041 if (!is_valid_ether_addr(netdev->perm_addr)) {
2042 dev_err(&pdev->dev, "Invalid MAC Address\n");
2043 err = -EIO;
2044 goto err_eeprom;
2045 }
2046
d67974f0
CW		 2047 /* get firmware version for ethtool -i */
2048 igb_set_fw_version(adapter);
2049
c061b18d 2050 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2051 (unsigned long) adapter);
c061b18d 2052 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2053 (unsigned long) adapter);
9d5c8243
AK		 2054
2055 INIT_WORK(&adapter->reset_task, igb_reset_task);
2056 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2057
450c87c8 2058 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2059 adapter->fc_autoneg = true;
2060 hw->mac.autoneg = true;
2061 hw->phy.autoneg_advertised = 0x2f;
2062
0cce119a
AD		 2063 hw->fc.requested_mode = e1000_fc_default;
2064 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2065
9d5c8243
AK		 2066 igb_validate_mdi_setting(hw);
2067
9d5c8243
AK		 2068 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
2069 * enable the ACPI Magic Packet filter
2070 */
2071
a2cf8b6c 2072 if (hw->bus.func == 0)
312c75ae 2073 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6d337dce 2074 else if (hw->mac.type >= e1000_82580)
55cac248
AD		 2075 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2076 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2077 &eeprom_data);
a2cf8b6c
AD		 2078 else if (hw->bus.func == 1)
2079 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243
AK		 2080
2081 if (eeprom_data & eeprom_apme_mask)
2082 adapter->eeprom_wol |= E1000_WUFC_MAG;
2083
2084 /* now that we have the eeprom settings, apply the special cases where
2085 * the eeprom may be wrong or the board simply won't support wake on
2086 * lan on a particular port */
2087 switch (pdev->device) {
2088 case E1000_DEV_ID_82575GB_QUAD_COPPER:
2089 adapter->eeprom_wol = 0;
2090 break;
2091 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2092 case E1000_DEV_ID_82576_FIBER:
2093 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2094 /* Wake events only supported on port A for dual fiber
2095 * regardless of eeprom setting */
2096 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2097 adapter->eeprom_wol = 0;
2098 break;
c8ea5ea9 2099 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2100 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2101 /* if quad port adapter, disable WoL on all but port A */
2102 if (global_quad_port_a != 0)
2103 adapter->eeprom_wol = 0;
2104 else
2105 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2106 /* Reset for multiple quad port adapters */
2107 if (++global_quad_port_a == 4)
2108 global_quad_port_a = 0;
2109 break;
9d5c8243
AK		 2110 }
2111
2112 /* initialize the wol settings based on the eeprom settings */
2113 adapter->wol = adapter->eeprom_wol;
e1b86d84 2114 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9d5c8243
AK		 2115
2116 /* reset the hardware with the new settings */
2117 igb_reset(adapter);
2118
2119 /* let the f/w know that the h/w is now under the control of the
2120 * driver. */
2121 igb_get_hw_control(adapter);
2122
9d5c8243
AK		 2123 strcpy(netdev->name, "eth%d");
2124 err = register_netdev(netdev);
2125 if (err)
2126 goto err_register;
2127
b168dfc5
JB		 2128 /* carrier off reporting is important to ethtool even BEFORE open */
2129 netif_carrier_off(netdev);
2130
421e02f0 2131#ifdef CONFIG_IGB_DCA
bbd98fe4 2132 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2133 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2134 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2135 igb_setup_dca(adapter);
2136 }
fe4506b6 2137
38c845c7 2138#endif
3c89f6d0 2139
7ebae817 2140#ifdef CONFIG_IGB_PTP
673b8b70 2141 /* do hw tstamp init after resetting */
7ebae817 2142 igb_ptp_init(adapter);
3c89f6d0 2143#endif /* CONFIG_IGB_PTP */
673b8b70 2144
9d5c8243
AK		 2145 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2146 /* print bus type/speed/width info */
7c510e4b 2147 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2148 netdev->name,
559e9c49 2149 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2150 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2151 "unknown"),
59c3de89
AD		 2152 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2153 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2154 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2155 "unknown"),
7c510e4b 2156 netdev->dev_addr);
9d5c8243 2157
9835fd73
CW		 2158 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2159 if (ret_val)
2160 strcpy(part_str, "Unknown");
2161 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2162 dev_info(&pdev->dev,
2163 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2164 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2165 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2166 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2167 switch (hw->mac.type) {
2168 case e1000_i350:
f96a8a0b
CW		 2169 case e1000_i210:
2170 case e1000_i211:
09b068d4
CW		 2171 igb_set_eee_i350(hw);
2172 break;
2173 default:
2174 break;
2175 }
749ab2cd
YZ		 2176
2177 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2178 return 0;
2179
2180err_register:
2181 igb_release_hw_control(adapter);
2182err_eeprom:
2183 if (!igb_check_reset_block(hw))
f5f4cf08 2184 igb_reset_phy(hw);
9d5c8243
AK		 2185
2186 if (hw->flash_address)
2187 iounmap(hw->flash_address);
9d5c8243 2188err_sw_init:
047e0030 2189 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2190 iounmap(hw->hw_addr);
2191err_ioremap:
2192 free_netdev(netdev);
2193err_alloc_etherdev:
559e9c49
AD		 2194 pci_release_selected_regions(pdev,
2195 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2196err_pci_reg:
2197err_dma:
2198 pci_disable_device(pdev);
2199 return err;
2200}
2201
2202/**
2203 * igb_remove - Device Removal Routine
2204 * @pdev: PCI device information struct
2205 *
2206 * igb_remove is called by the PCI subsystem to alert the driver
2207 * that it should release a PCI device. The could be caused by a
2208 * Hot-Plug event, or because the driver is going to be removed from
2209 * memory.
2210 **/
2211static void __devexit igb_remove(struct pci_dev *pdev)
2212{
2213 struct net_device *netdev = pci_get_drvdata(pdev);
2214 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2215 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2216
749ab2cd 2217 pm_runtime_get_noresume(&pdev->dev);
7ebae817 2218#ifdef CONFIG_IGB_PTP
a79f4f88 2219 igb_ptp_stop(adapter);
3c89f6d0 2220#endif /* CONFIG_IGB_PTP */
749ab2cd 2221
760141a5
TH		 2222 /*
2223 * The watchdog timer may be rescheduled, so explicitly
2224 * disable watchdog from being rescheduled.
2225 */
9d5c8243
AK		 2226 set_bit(__IGB_DOWN, &adapter->state);
2227 del_timer_sync(&adapter->watchdog_timer);
2228 del_timer_sync(&adapter->phy_info_timer);
2229
760141a5
TH		 2230 cancel_work_sync(&adapter->reset_task);
2231 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2232
421e02f0 2233#ifdef CONFIG_IGB_DCA
7dfc16fa 2234 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2235 dev_info(&pdev->dev, "DCA disabled\n");
2236 dca_remove_requester(&pdev->dev);
7dfc16fa 2237 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2238 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2239 }
2240#endif
2241
9d5c8243
AK		 2242 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2243 * would have already happened in close and is redundant. */
2244 igb_release_hw_control(adapter);
2245
2246 unregister_netdev(netdev);
2247
047e0030 2248 igb_clear_interrupt_scheme(adapter);
9d5c8243 2249
37680117
AD		 2250#ifdef CONFIG_PCI_IOV
2251 /* reclaim resources allocated to VFs */
2252 if (adapter->vf_data) {
2253 /* disable iov and allow time for transactions to clear */
f557147c
SA		 2254 if (igb_vfs_are_assigned(adapter)) {
2255 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2256 } else {
0224d663
GR		 2257 pci_disable_sriov(pdev);
2258 msleep(500);
0224d663 2259 }
37680117
AD		 2260
2261 kfree(adapter->vf_data);
2262 adapter->vf_data = NULL;
2263 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 2264 wrfl();
37680117
AD		 2265 msleep(100);
2266 dev_info(&pdev->dev, "IOV Disabled\n");
2267 }
2268#endif
559e9c49 2269
28b0759c
AD		 2270 iounmap(hw->hw_addr);
2271 if (hw->flash_address)
2272 iounmap(hw->flash_address);
559e9c49
AD		 2273 pci_release_selected_regions(pdev,
2274 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2275
1128c756 2276 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2277 free_netdev(netdev);
2278
19d5afd4 2279 pci_disable_pcie_error_reporting(pdev);
40a914fa 2280
9d5c8243
AK		 2281 pci_disable_device(pdev);
2282}
2283
a6b623e0
AD		 2284/**
2285 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2286 * @adapter: board private structure to initialize
2287 *
2288 * This function initializes the vf specific data storage and then attempts to
2289 * allocate the VFs. The reason for ordering it this way is because it is much
2290 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2291 * the memory for the VFs.
2292 **/
2293static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
2294{
2295#ifdef CONFIG_PCI_IOV
2296 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2297 struct e1000_hw *hw = &adapter->hw;
f557147c 2298 int old_vfs = pci_num_vf(adapter->pdev);
0224d663 2299 int i;
a6b623e0 2300
f96a8a0b
CW		 2301 /* Virtualization features not supported on i210 family. */
2302 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2303 return;
2304
0224d663
GR		 2305 if (old_vfs) {
2306 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2307 "max_vfs setting of %d\n", old_vfs, max_vfs);
2308 adapter->vfs_allocated_count = old_vfs;
a6b623e0
AD		 2309 }
2310
0224d663
GR		 2311 if (!adapter->vfs_allocated_count)
2312 return;
2313
2314 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2315 sizeof(struct vf_data_storage), GFP_KERNEL);
f96a8a0b 2316
0224d663
GR		 2317 /* if allocation failed then we do not support SR-IOV */
2318 if (!adapter->vf_data) {
a6b623e0 2319 adapter->vfs_allocated_count = 0;
0224d663
GR		 2320 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2321 "Data Storage\n");
2322 goto out;
a6b623e0 2323 }
0224d663
GR		 2324
2325 if (!old_vfs) {
2326 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2327 goto err_out;
2328 }
2329 dev_info(&pdev->dev, "%d VFs allocated\n",
2330 adapter->vfs_allocated_count);
2331 for (i = 0; i < adapter->vfs_allocated_count; i++)
2332 igb_vf_configure(adapter, i);
2333
2334 /* DMA Coalescing is not supported in IOV mode. */
2335 adapter->flags &= ~IGB_FLAG_DMAC;
2336 goto out;
2337err_out:
2338 kfree(adapter->vf_data);
2339 adapter->vf_data = NULL;
2340 adapter->vfs_allocated_count = 0;
2341out:
2342 return;
a6b623e0
AD		 2343#endif /* CONFIG_PCI_IOV */
2344}
2345
9d5c8243
AK		 2346/**
2347 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2348 * @adapter: board private structure to initialize
2349 *
2350 * igb_sw_init initializes the Adapter private data structure.
2351 * Fields are initialized based on PCI device information and
2352 * OS network device settings (MTU size).
2353 **/
2354static int __devinit igb_sw_init(struct igb_adapter *adapter)
2355{
2356 struct e1000_hw *hw = &adapter->hw;
2357 struct net_device *netdev = adapter->netdev;
2358 struct pci_dev *pdev = adapter->pdev;
374a542d 2359 u32 max_rss_queues;
9d5c8243
AK		 2360
2361 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2362
13fde97a 2363 /* set default ring sizes */
68fd9910
AD		 2364 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2365 adapter->rx_ring_count = IGB_DEFAULT_RXD;
13fde97a
AD		 2366
2367 /* set default ITR values */
4fc82adf
AD		 2368 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2369 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2370
13fde97a
AD		 2371 /* set default work limits */
2372 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2373
153285f9
AD		 2374 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2375 VLAN_HLEN;
9d5c8243
AK		 2376 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2377
12dcd86b 2378 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2379#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2380 switch (hw->mac.type) {
2381 case e1000_82576:
2382 case e1000_i350:
9b082d73
SA		 2383 if (max_vfs > 7) {
2384 dev_warn(&pdev->dev,
2385 "Maximum of 7 VFs per PF, using max\n");
2386 adapter->vfs_allocated_count = 7;
2387 } else
2388 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2389 break;
2390 default:
2391 break;
2392 }
a6b623e0 2393#endif /* CONFIG_PCI_IOV */
374a542d
MV		 2394
2395 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2396 switch (hw->mac.type) {
374a542d
MV		 2397 case e1000_i211:
2398 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2399 break;
2400 case e1000_82575:
f96a8a0b 2401 case e1000_i210:
374a542d
MV		 2402 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2403 break;
2404 case e1000_i350:
2405 /* I350 cannot do RSS and SR-IOV at the same time */
2406 if (!!adapter->vfs_allocated_count) {
2407 max_rss_queues = 1;
2408 break;
2409 }
2410 /* fall through */
2411 case e1000_82576:
2412 if (!!adapter->vfs_allocated_count) {
2413 max_rss_queues = 2;
2414 break;
2415 }
2416 /* fall through */
2417 case e1000_82580:
2418 default:
2419 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2420 break;
374a542d
MV		 2421 }
2422
2423 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2424
2425 /* Determine if we need to pair queues. */
2426 switch (hw->mac.type) {
2427 case e1000_82575:
f96a8a0b 2428 case e1000_i211:
374a542d 2429 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2430 break;
374a542d
MV		 2431 case e1000_82576:
2432 /*
2433 * If VFs are going to be allocated with RSS queues then we
2434 * should pair the queues in order to conserve interrupts due
2435 * to limited supply.
2436 */
2437 if ((adapter->rss_queues > 1) &&
2438 (adapter->vfs_allocated_count > 6))
2439 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2440 /* fall through */
2441 case e1000_82580:
2442 case e1000_i350:
2443 case e1000_i210:
f96a8a0b 2444 default:
374a542d
MV		 2445 /*
2446 * If rss_queues > half of max_rss_queues, pair the queues in
2447 * order to conserve interrupts due to limited supply.
2448 */
2449 if (adapter->rss_queues > (max_rss_queues / 2))
2450 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2451 break;
2452 }
a99955fc 2453
1128c756
CW		 2454 /* Setup and initialize a copy of the hw vlan table array */
2455 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2456 E1000_VLAN_FILTER_TBL_SIZE,
2457 GFP_ATOMIC);
2458
a6b623e0 2459 /* This call may decrease the number of queues */
047e0030 2460 if (igb_init_interrupt_scheme(adapter)) {
9d5c8243
AK		 2461 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2462 return -ENOMEM;
2463 }
2464
a6b623e0
AD		 2465 igb_probe_vfs(adapter);
2466
9d5c8243
AK		 2467 /* Explicitly disable IRQ since the NIC can be in any state. */
2468 igb_irq_disable(adapter);
2469
f96a8a0b 2470 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2471 adapter->flags &= ~IGB_FLAG_DMAC;
2472
9d5c8243
AK		 2473 set_bit(__IGB_DOWN, &adapter->state);
2474 return 0;
2475}
2476
2477/**
2478 * igb_open - Called when a network interface is made active
2479 * @netdev: network interface device structure
2480 *
2481 * Returns 0 on success, negative value on failure
2482 *
2483 * The open entry point is called when a network interface is made
2484 * active by the system (IFF_UP). At this point all resources needed
2485 * for transmit and receive operations are allocated, the interrupt
2486 * handler is registered with the OS, the watchdog timer is started,
2487 * and the stack is notified that the interface is ready.
2488 **/
749ab2cd 2489static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2490{
2491 struct igb_adapter *adapter = netdev_priv(netdev);
2492 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2493 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2494 int err;
2495 int i;
2496
2497 /* disallow open during test */
749ab2cd
YZ		 2498 if (test_bit(__IGB_TESTING, &adapter->state)) {
2499 WARN_ON(resuming);
9d5c8243 2500 return -EBUSY;
749ab2cd
YZ		 2501 }
2502
2503 if (!resuming)
2504 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2505
b168dfc5
JB		 2506 netif_carrier_off(netdev);
2507
9d5c8243
AK		 2508 /* allocate transmit descriptors */
2509 err = igb_setup_all_tx_resources(adapter);
2510 if (err)
2511 goto err_setup_tx;
2512
2513 /* allocate receive descriptors */
2514 err = igb_setup_all_rx_resources(adapter);
2515 if (err)
2516 goto err_setup_rx;
2517
88a268c1 2518 igb_power_up_link(adapter);
9d5c8243 2519
9d5c8243
AK		 2520 /* before we allocate an interrupt, we must be ready to handle it.
2521 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2522 * as soon as we call pci_request_irq, so we have to setup our
2523 * clean_rx handler before we do so. */
2524 igb_configure(adapter);
2525
2526 err = igb_request_irq(adapter);
2527 if (err)
2528 goto err_req_irq;
2529
2530 /* From here on the code is the same as igb_up() */
2531 clear_bit(__IGB_DOWN, &adapter->state);
2532
0d1ae7f4
AD		 2533 for (i = 0; i < adapter->num_q_vectors; i++)
2534 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2535
2536 /* Clear any pending interrupts. */
2537 rd32(E1000_ICR);
844290e5
PW		 2538
2539 igb_irq_enable(adapter);
2540
d4960307
AD		 2541 /* notify VFs that reset has been completed */
2542 if (adapter->vfs_allocated_count) {
2543 u32 reg_data = rd32(E1000_CTRL_EXT);
2544 reg_data |= E1000_CTRL_EXT_PFRSTD;
2545 wr32(E1000_CTRL_EXT, reg_data);
2546 }
2547
d55b53ff
JK		 2548 netif_tx_start_all_queues(netdev);
2549
749ab2cd
YZ		 2550 if (!resuming)
2551 pm_runtime_put(&pdev->dev);
2552
25568a53
AD		 2553 /* start the watchdog. */
2554 hw->mac.get_link_status = 1;
2555 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2556
2557 return 0;
2558
2559err_req_irq:
2560 igb_release_hw_control(adapter);
88a268c1 2561 igb_power_down_link(adapter);
9d5c8243
AK		 2562 igb_free_all_rx_resources(adapter);
2563err_setup_rx:
2564 igb_free_all_tx_resources(adapter);
2565err_setup_tx:
2566 igb_reset(adapter);
749ab2cd
YZ		 2567 if (!resuming)
2568 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2569
2570 return err;
2571}
2572
749ab2cd
YZ		 2573static int igb_open(struct net_device *netdev)
2574{
2575 return __igb_open(netdev, false);
2576}
2577
9d5c8243
AK		 2578/**
2579 * igb_close - Disables a network interface
2580 * @netdev: network interface device structure
2581 *
2582 * Returns 0, this is not allowed to fail
2583 *
2584 * The close entry point is called when an interface is de-activated
2585 * by the OS. The hardware is still under the driver's control, but
2586 * needs to be disabled. A global MAC reset is issued to stop the
2587 * hardware, and all transmit and receive resources are freed.
2588 **/
749ab2cd 2589static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2590{
2591 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2592 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2593
2594 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2595
749ab2cd
YZ		 2596 if (!suspending)
2597 pm_runtime_get_sync(&pdev->dev);
2598
2599 igb_down(adapter);
9d5c8243
AK		 2600 igb_free_irq(adapter);
2601
2602 igb_free_all_tx_resources(adapter);
2603 igb_free_all_rx_resources(adapter);
2604
749ab2cd
YZ		 2605 if (!suspending)
2606 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2607 return 0;
2608}
2609
749ab2cd
YZ		 2610static int igb_close(struct net_device *netdev)
2611{
2612 return __igb_close(netdev, false);
2613}
2614
9d5c8243
AK		 2615/**
2616 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2617 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2618 *
2619 * Return 0 on success, negative on failure
2620 **/
80785298 2621int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2622{
59d71989 2623 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2624 int size;
2625
06034649 2626 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2627
2628 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2629 if (!tx_ring->tx_buffer_info)
9d5c8243 2630 goto err;
9d5c8243
AK		 2631
2632 /* round up to nearest 4K */
85e8d004 2633 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2634 tx_ring->size = ALIGN(tx_ring->size, 4096);
2635
59d71989
AD		 2636 tx_ring->desc = dma_alloc_coherent(dev,
2637 tx_ring->size,
2638 &tx_ring->dma,
2639 GFP_KERNEL);
9d5c8243
AK		 2640 if (!tx_ring->desc)
2641 goto err;
2642
9d5c8243
AK		 2643 tx_ring->next_to_use = 0;
2644 tx_ring->next_to_clean = 0;
81c2fc22 2645
9d5c8243
AK		 2646 return 0;
2647
2648err:
06034649 2649 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2650 tx_ring->tx_buffer_info = NULL;
2651 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2652 return -ENOMEM;
2653}
2654
2655/**
2656 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2657 * (Descriptors) for all queues
2658 * @adapter: board private structure
2659 *
2660 * Return 0 on success, negative on failure
2661 **/
2662static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2663{
439705e1 2664 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2665 int i, err = 0;
2666
2667 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2668 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2669 if (err) {
439705e1 2670 dev_err(&pdev->dev,
9d5c8243
AK		 2671 "Allocation for Tx Queue %u failed\n", i);
2672 for (i--; i >= 0; i--)
3025a446 2673 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2674 break;
2675 }
2676 }
2677
2678 return err;
2679}
2680
2681/**
85b430b4
AD		 2682 * igb_setup_tctl - configure the transmit control registers
2683 * @adapter: Board private structure
9d5c8243 2684 **/
d7ee5b3a 2685void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2686{
9d5c8243
AK		 2687 struct e1000_hw *hw = &adapter->hw;
2688 u32 tctl;
9d5c8243 2689
85b430b4
AD		 2690 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2691 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2692
2693 /* Program the Transmit Control Register */
9d5c8243
AK		 2694 tctl = rd32(E1000_TCTL);
2695 tctl &= ~E1000_TCTL_CT;
2696 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2697 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2698
2699 igb_config_collision_dist(hw);
2700
9d5c8243
AK		 2701 /* Enable transmits */
2702 tctl |= E1000_TCTL_EN;
2703
2704 wr32(E1000_TCTL, tctl);
2705}
2706
85b430b4
AD		 2707/**
2708 * igb_configure_tx_ring - Configure transmit ring after Reset
2709 * @adapter: board private structure
2710 * @ring: tx ring to configure
2711 *
2712 * Configure a transmit ring after a reset.
2713 **/
d7ee5b3a
AD		 2714void igb_configure_tx_ring(struct igb_adapter *adapter,
2715 struct igb_ring *ring)
85b430b4
AD		 2716{
2717 struct e1000_hw *hw = &adapter->hw;
a74420e0 2718 u32 txdctl = 0;
85b430b4
AD		 2719 u64 tdba = ring->dma;
2720 int reg_idx = ring->reg_idx;
2721
2722 /* disable the queue */
a74420e0 2723 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2724 wrfl();
2725 mdelay(10);
2726
2727 wr32(E1000_TDLEN(reg_idx),
2728 ring->count * sizeof(union e1000_adv_tx_desc));
2729 wr32(E1000_TDBAL(reg_idx),
2730 tdba & 0x00000000ffffffffULL);
2731 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2732
fce99e34 2733 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2734 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2735 writel(0, ring->tail);
85b430b4
AD		 2736
2737 txdctl |= IGB_TX_PTHRESH;
2738 txdctl |= IGB_TX_HTHRESH << 8;
2739 txdctl |= IGB_TX_WTHRESH << 16;
2740
2741 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2742 wr32(E1000_TXDCTL(reg_idx), txdctl);
2743}
2744
2745/**
2746 * igb_configure_tx - Configure transmit Unit after Reset
2747 * @adapter: board private structure
2748 *
2749 * Configure the Tx unit of the MAC after a reset.
2750 **/
2751static void igb_configure_tx(struct igb_adapter *adapter)
2752{
2753 int i;
2754
2755 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2756 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2757}
2758
9d5c8243
AK		 2759/**
2760 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2761 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2762 *
2763 * Returns 0 on success, negative on failure
2764 **/
80785298 2765int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2766{
59d71989 2767 struct device *dev = rx_ring->dev;
f33005a6 2768 int size;
9d5c8243 2769
06034649 2770 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 2771
2772 rx_ring->rx_buffer_info = vzalloc(size);
06034649 2773 if (!rx_ring->rx_buffer_info)
9d5c8243 2774 goto err;
9d5c8243 2775
9d5c8243
AK		 2776
2777 /* Round up to nearest 4K */
f33005a6 2778 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 2779 rx_ring->size = ALIGN(rx_ring->size, 4096);
2780
59d71989
AD		 2781 rx_ring->desc = dma_alloc_coherent(dev,
2782 rx_ring->size,
2783 &rx_ring->dma,
2784 GFP_KERNEL);
9d5c8243
AK		 2785 if (!rx_ring->desc)
2786 goto err;
2787
2788 rx_ring->next_to_clean = 0;
2789 rx_ring->next_to_use = 0;
9d5c8243 2790
9d5c8243
AK		 2791 return 0;
2792
2793err:
06034649
AD		 2794 vfree(rx_ring->rx_buffer_info);
2795 rx_ring->rx_buffer_info = NULL;
f33005a6 2796 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 2797 return -ENOMEM;
2798}
2799
2800/**
2801 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2802 * (Descriptors) for all queues
2803 * @adapter: board private structure
2804 *
2805 * Return 0 on success, negative on failure
2806 **/
2807static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2808{
439705e1 2809 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2810 int i, err = 0;
2811
2812 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2813 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2814 if (err) {
439705e1 2815 dev_err(&pdev->dev,
9d5c8243
AK		 2816 "Allocation for Rx Queue %u failed\n", i);
2817 for (i--; i >= 0; i--)
3025a446 2818 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2819 break;
2820 }
2821 }
2822
2823 return err;
2824}
2825
06cf2666
AD		 2826/**
2827 * igb_setup_mrqc - configure the multiple receive queue control registers
2828 * @adapter: Board private structure
2829 **/
2830static void igb_setup_mrqc(struct igb_adapter *adapter)
2831{
2832 struct e1000_hw *hw = &adapter->hw;
2833 u32 mrqc, rxcsum;
797fd4be 2834 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 2835 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2836 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2837 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2838 0xFA01ACBE };
06cf2666
AD		 2839
2840 /* Fill out hash function seeds */
a57fe23e
AD		 2841 for (j = 0; j < 10; j++)
2842 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 2843
a99955fc 2844 num_rx_queues = adapter->rss_queues;
06cf2666 2845
797fd4be
AD		 2846 switch (hw->mac.type) {
2847 case e1000_82575:
2848 shift = 6;
2849 break;
2850 case e1000_82576:
2851 /* 82576 supports 2 RSS queues for SR-IOV */
2852 if (adapter->vfs_allocated_count) {
06cf2666
AD		 2853 shift = 3;
2854 num_rx_queues = 2;
06cf2666 2855 }
797fd4be
AD		 2856 break;
2857 default:
2858 break;
06cf2666
AD		 2859 }
2860
797fd4be
AD		 2861 /*
2862 * Populate the indirection table 4 entries at a time. To do this
2863 * we are generating the results for n and n+2 and then interleaving
2864 * those with the results with n+1 and n+3.
2865 */
2866 for (j = 0; j < 32; j++) {
2867 /* first pass generates n and n+2 */
2868 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2869 u32 reta = (base & 0x07800780) >> (7 - shift);
2870
2871 /* second pass generates n+1 and n+3 */
2872 base += 0x00010001 * num_rx_queues;
2873 reta |= (base & 0x07800780) << (1 + shift);
2874
2875 wr32(E1000_RETA(j), reta);
06cf2666
AD		 2876 }
2877
2878 /*
2879 * Disable raw packet checksumming so that RSS hash is placed in
2880 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2881 * offloads as they are enabled by default
2882 */
2883 rxcsum = rd32(E1000_RXCSUM);
2884 rxcsum |= E1000_RXCSUM_PCSD;
2885
2886 if (adapter->hw.mac.type >= e1000_82576)
2887 /* Enable Receive Checksum Offload for SCTP */
2888 rxcsum |= E1000_RXCSUM_CRCOFL;
2889
2890 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2891 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b
CW		 2892 /*
2893 * Generate RSS hash based on TCP port numbers and/or
2894 * IPv4/v6 src and dst addresses since UDP cannot be
2895 * hashed reliably due to IP fragmentation
2896 */
2897
2898 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2899 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2900 E1000_MRQC_RSS_FIELD_IPV6 |
2901 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2902 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666
AD		 2903
2904 /* If VMDq is enabled then we set the appropriate mode for that, else
2905 * we default to RSS so that an RSS hash is calculated per packet even
2906 * if we are only using one queue */
2907 if (adapter->vfs_allocated_count) {
2908 if (hw->mac.type > e1000_82575) {
2909 /* Set the default pool for the PF's first queue */
2910 u32 vtctl = rd32(E1000_VT_CTL);
2911 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2912 E1000_VT_CTL_DISABLE_DEF_POOL);
2913 vtctl |= adapter->vfs_allocated_count <<
2914 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2915 wr32(E1000_VT_CTL, vtctl);
2916 }
a99955fc 2917 if (adapter->rss_queues > 1)
f96a8a0b 2918 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 2919 else
f96a8a0b 2920 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 2921 } else {
f96a8a0b
CW		 2922 if (hw->mac.type != e1000_i211)
2923 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 2924 }
2925 igb_vmm_control(adapter);
2926
06cf2666
AD		 2927 wr32(E1000_MRQC, mrqc);
2928}
2929
9d5c8243
AK		 2930/**
2931 * igb_setup_rctl - configure the receive control registers
2932 * @adapter: Board private structure
2933 **/
d7ee5b3a 2934void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2935{
2936 struct e1000_hw *hw = &adapter->hw;
2937 u32 rctl;
9d5c8243
AK		 2938
2939 rctl = rd32(E1000_RCTL);
2940
2941 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2942 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2943
69d728ba 2944 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2945 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2946
87cb7e8c
AK		 2947 /*
2948 * enable stripping of CRC. It's unlikely this will break BMC
2949 * redirection as it did with e1000. Newer features require
2950 * that the HW strips the CRC.
73cd78f1 2951 */
87cb7e8c 2952 rctl |= E1000_RCTL_SECRC;
9d5c8243 2953
559e9c49 2954 /* disable store bad packets and clear size bits. */
ec54d7d6 2955 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2956
6ec43fe6
AD		 2957 /* enable LPE to prevent packets larger than max_frame_size */
2958 rctl |= E1000_RCTL_LPE;
9d5c8243 2959
952f72a8
AD		 2960 /* disable queue 0 to prevent tail write w/o re-config */
2961 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2962
e1739522
AD		 2963 /* Attention!!! For SR-IOV PF driver operations you must enable
2964 * queue drop for all VF and PF queues to prevent head of line blocking
2965 * if an un-trusted VF does not provide descriptors to hardware.
2966 */
2967 if (adapter->vfs_allocated_count) {
e1739522
AD		 2968 /* set all queue drop enable bits */
2969 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2970 }
2971
89eaefb6
BG		 2972 /* This is useful for sniffing bad packets. */
2973 if (adapter->netdev->features & NETIF_F_RXALL) {
2974 /* UPE and MPE will be handled by normal PROMISC logic
2975 * in e1000e_set_rx_mode */
2976 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2977 E1000_RCTL_BAM | /* RX All Bcast Pkts */
2978 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2979
2980 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2981 E1000_RCTL_DPF | /* Allow filtered pause */
2982 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2983 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2984 * and that breaks VLANs.
2985 */
2986 }
2987
9d5c8243
AK		 2988 wr32(E1000_RCTL, rctl);
2989}
2990
7d5753f0
AD		 2991static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2992 int vfn)
2993{
2994 struct e1000_hw *hw = &adapter->hw;
2995 u32 vmolr;
2996
2997 /* if it isn't the PF check to see if VFs are enabled and
2998 * increase the size to support vlan tags */
2999 if (vfn < adapter->vfs_allocated_count &&
3000 adapter->vf_data[vfn].vlans_enabled)
3001 size += VLAN_TAG_SIZE;
3002
3003 vmolr = rd32(E1000_VMOLR(vfn));
3004 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3005 vmolr |= size | E1000_VMOLR_LPE;
3006 wr32(E1000_VMOLR(vfn), vmolr);
3007
3008 return 0;
3009}
3010
e1739522
AD		 3011/**
3012 * igb_rlpml_set - set maximum receive packet size
3013 * @adapter: board private structure
3014 *
3015 * Configure maximum receivable packet size.
3016 **/
3017static void igb_rlpml_set(struct igb_adapter *adapter)
3018{
153285f9 3019 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3020 struct e1000_hw *hw = &adapter->hw;
3021 u16 pf_id = adapter->vfs_allocated_count;
3022
e1739522
AD		 3023 if (pf_id) {
3024 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3025 /*
3026 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3027 * to our max jumbo frame size, in case we need to enable
3028 * jumbo frames on one of the rings later.
3029 * This will not pass over-length frames into the default
3030 * queue because it's gated by the VMOLR.RLPML.
3031 */
7d5753f0 3032 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3033 }
3034
3035 wr32(E1000_RLPML, max_frame_size);
3036}
3037
8151d294
WM		 3038static inline void igb_set_vmolr(struct igb_adapter *adapter,
3039 int vfn, bool aupe)
7d5753f0
AD		 3040{
3041 struct e1000_hw *hw = &adapter->hw;
3042 u32 vmolr;
3043
3044 /*
3045 * This register exists only on 82576 and newer so if we are older then
3046 * we should exit and do nothing
3047 */
3048 if (hw->mac.type < e1000_82576)
3049 return;
3050
3051 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3052 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3053 if (aupe)
3054 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3055 else
3056 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3057
3058 /* clear all bits that might not be set */
3059 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3060
a99955fc 3061 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3062 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3063 /*
3064 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3065 * multicast packets
3066 */
3067 if (vfn <= adapter->vfs_allocated_count)
3068 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3069
3070 wr32(E1000_VMOLR(vfn), vmolr);
3071}
3072
85b430b4
AD		 3073/**
3074 * igb_configure_rx_ring - Configure a receive ring after Reset
3075 * @adapter: board private structure
3076 * @ring: receive ring to be configured
3077 *
3078 * Configure the Rx unit of the MAC after a reset.
3079 **/
d7ee5b3a
AD		 3080void igb_configure_rx_ring(struct igb_adapter *adapter,
3081 struct igb_ring *ring)
85b430b4
AD		 3082{
3083 struct e1000_hw *hw = &adapter->hw;
3084 u64 rdba = ring->dma;
3085 int reg_idx = ring->reg_idx;
a74420e0 3086 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3087
3088 /* disable the queue */
a74420e0 3089 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3090
3091 /* Set DMA base address registers */
3092 wr32(E1000_RDBAL(reg_idx),
3093 rdba & 0x00000000ffffffffULL);
3094 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3095 wr32(E1000_RDLEN(reg_idx),
3096 ring->count * sizeof(union e1000_adv_rx_desc));
3097
3098 /* initialize head and tail */
fce99e34 3099 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3100 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3101 writel(0, ring->tail);
85b430b4 3102
952f72a8 3103 /* set descriptor configuration */
44390ca6 3104 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
952f72a8 3105#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
44390ca6 3106 srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
952f72a8 3107#else
44390ca6 3108 srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT;
952f72a8 3109#endif
1a1c225b 3110 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3c89f6d0 3111#ifdef CONFIG_IGB_PTP
06218a8d 3112 if (hw->mac.type >= e1000_82580)
757b77e2 3113 srrctl |= E1000_SRRCTL_TIMESTAMP;
3c89f6d0 3114#endif /* CONFIG_IGB_PTP */
e6bdb6fe
NN		 3115 /* Only set Drop Enable if we are supporting multiple queues */
3116 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3117 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3118
3119 wr32(E1000_SRRCTL(reg_idx), srrctl);
3120
7d5753f0 3121 /* set filtering for VMDQ pools */
8151d294 3122 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3123
85b430b4
AD		 3124 rxdctl |= IGB_RX_PTHRESH;
3125 rxdctl |= IGB_RX_HTHRESH << 8;
3126 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3127
3128 /* enable receive descriptor fetching */
3129 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3130 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3131}
3132
9d5c8243
AK		 3133/**
3134 * igb_configure_rx - Configure receive Unit after Reset
3135 * @adapter: board private structure
3136 *
3137 * Configure the Rx unit of the MAC after a reset.
3138 **/
3139static void igb_configure_rx(struct igb_adapter *adapter)
3140{
9107584e 3141 int i;
9d5c8243 3142
68d480c4
AD		 3143 /* set UTA to appropriate mode */
3144 igb_set_uta(adapter);
3145
26ad9178
AD		 3146 /* set the correct pool for the PF default MAC address in entry 0 */
3147 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3148 adapter->vfs_allocated_count);
3149
06cf2666
AD		 3150 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3151 * the Base and Length of the Rx Descriptor Ring */
3152 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3153 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3154}
3155
3156/**
3157 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3158 * @tx_ring: Tx descriptor ring for a specific queue
3159 *
3160 * Free all transmit software resources
3161 **/
68fd9910 3162void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3163{
3b644cf6 3164 igb_clean_tx_ring(tx_ring);
9d5c8243 3165
06034649
AD		 3166 vfree(tx_ring->tx_buffer_info);
3167 tx_ring->tx_buffer_info = NULL;
9d5c8243 3168
439705e1
AD		 3169 /* if not set, then don't free */
3170 if (!tx_ring->desc)
3171 return;
3172
59d71989
AD		 3173 dma_free_coherent(tx_ring->dev, tx_ring->size,
3174 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3175
3176 tx_ring->desc = NULL;
3177}
3178
3179/**
3180 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3181 * @adapter: board private structure
3182 *
3183 * Free all transmit software resources
3184 **/
3185static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3186{
3187 int i;
3188
3189 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3190 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3191}
3192
ebe42d16
AD		 3193void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3194 struct igb_tx_buffer *tx_buffer)
3195{
3196 if (tx_buffer->skb) {
3197 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3198 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3199 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3200 dma_unmap_addr(tx_buffer, dma),
3201 dma_unmap_len(tx_buffer, len),
ebe42d16 3202 DMA_TO_DEVICE);
c9f14bf3 3203 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3204 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3205 dma_unmap_addr(tx_buffer, dma),
3206 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3207 DMA_TO_DEVICE);
3208 }
3209 tx_buffer->next_to_watch = NULL;
3210 tx_buffer->skb = NULL;
c9f14bf3 3211 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3212 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3213}
3214
3215/**
3216 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3217 * @tx_ring: ring to be cleaned
3218 **/
3b644cf6 3219static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3220{
06034649 3221 struct igb_tx_buffer *buffer_info;
9d5c8243 3222 unsigned long size;
6ad4edfc 3223 u16 i;
9d5c8243 3224
06034649 3225 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3226 return;
3227 /* Free all the Tx ring sk_buffs */
3228
3229 for (i = 0; i < tx_ring->count; i++) {
06034649 3230 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3231 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3232 }
3233
dad8a3b3
JF		 3234 netdev_tx_reset_queue(txring_txq(tx_ring));
3235
06034649
AD		 3236 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3237 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3238
3239 /* Zero out the descriptor ring */
9d5c8243
AK		 3240 memset(tx_ring->desc, 0, tx_ring->size);
3241
3242 tx_ring->next_to_use = 0;
3243 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3244}
3245
3246/**
3247 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3248 * @adapter: board private structure
3249 **/
3250static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3251{
3252 int i;
3253
3254 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3255 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3256}
3257
3258/**
3259 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3260 * @rx_ring: ring to clean the resources from
3261 *
3262 * Free all receive software resources
3263 **/
68fd9910 3264void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3265{
3b644cf6 3266 igb_clean_rx_ring(rx_ring);
9d5c8243 3267
06034649
AD		 3268 vfree(rx_ring->rx_buffer_info);
3269 rx_ring->rx_buffer_info = NULL;
9d5c8243 3270
439705e1
AD		 3271 /* if not set, then don't free */
3272 if (!rx_ring->desc)
3273 return;
3274
59d71989
AD		 3275 dma_free_coherent(rx_ring->dev, rx_ring->size,
3276 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3277
3278 rx_ring->desc = NULL;
3279}
3280
3281/**
3282 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3283 * @adapter: board private structure
3284 *
3285 * Free all receive software resources
3286 **/
3287static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3288{
3289 int i;
3290
3291 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3292 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3293}
3294
3295/**
3296 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3297 * @rx_ring: ring to free buffers from
3298 **/
3b644cf6 3299static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3300{
9d5c8243 3301 unsigned long size;
c023cd88 3302 u16 i;
9d5c8243 3303
1a1c225b
AD		 3304 if (rx_ring->skb)
3305 dev_kfree_skb(rx_ring->skb);
3306 rx_ring->skb = NULL;
3307
06034649 3308 if (!rx_ring->rx_buffer_info)
9d5c8243 3309 return;
439705e1 3310
9d5c8243
AK		 3311 /* Free all the Rx ring sk_buffs */
3312 for (i = 0; i < rx_ring->count; i++) {
06034649 3313 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3314
1a1c225b 3315 if (buffer_info->dma)
59d71989 3316 dma_unmap_page(rx_ring->dev,
1a1c225b 3317 buffer_info->dma,
6ec43fe6 3318 PAGE_SIZE / 2,
59d71989 3319 DMA_FROM_DEVICE);
1a1c225b
AD		 3320 buffer_info->dma = 0;
3321 if (buffer_info->page)
3322 __free_page(buffer_info->page);
3323 buffer_info->page = NULL;
3324 buffer_info->page_offset = 0;
9d5c8243
AK		 3325 }
3326
06034649
AD		 3327 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3328 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3329
3330 /* Zero out the descriptor ring */
3331 memset(rx_ring->desc, 0, rx_ring->size);
3332
3333 rx_ring->next_to_clean = 0;
3334 rx_ring->next_to_use = 0;
9d5c8243
AK		 3335}
3336
3337/**
3338 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3339 * @adapter: board private structure
3340 **/
3341static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3342{
3343 int i;
3344
3345 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3346 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3347}
3348
3349/**
3350 * igb_set_mac - Change the Ethernet Address of the NIC
3351 * @netdev: network interface device structure
3352 * @p: pointer to an address structure
3353 *
3354 * Returns 0 on success, negative on failure
3355 **/
3356static int igb_set_mac(struct net_device *netdev, void *p)
3357{
3358 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3359 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3360 struct sockaddr *addr = p;
3361
3362 if (!is_valid_ether_addr(addr->sa_data))
3363 return -EADDRNOTAVAIL;
3364
3365 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3366 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3367
26ad9178
AD		 3368 /* set the correct pool for the new PF MAC address in entry 0 */
3369 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3370 adapter->vfs_allocated_count);
e1739522 3371
9d5c8243
AK		 3372 return 0;
3373}
3374
3375/**
68d480c4 3376 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3377 * @netdev: network interface device structure
3378 *
68d480c4
AD		 3379 * Writes multicast address list to the MTA hash table.
3380 * Returns: -ENOMEM on failure
3381 * 0 on no addresses written
3382 * X on writing X addresses to MTA
9d5c8243 3383 **/
68d480c4 3384static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3385{
3386 struct igb_adapter *adapter = netdev_priv(netdev);
3387 struct e1000_hw *hw = &adapter->hw;
22bedad3 3388 struct netdev_hw_addr *ha;
68d480c4 3389 u8 *mta_list;
9d5c8243
AK		 3390 int i;
3391
4cd24eaf 3392 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3393 /* nothing to program, so clear mc list */
3394 igb_update_mc_addr_list(hw, NULL, 0);
3395 igb_restore_vf_multicasts(adapter);
3396 return 0;
3397 }
9d5c8243 3398
4cd24eaf 3399 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3400 if (!mta_list)
3401 return -ENOMEM;
ff41f8dc 3402
68d480c4 3403 /* The shared function expects a packed array of only addresses. */
48e2f183 3404 i = 0;
22bedad3
JP		 3405 netdev_for_each_mc_addr(ha, netdev)
3406 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3407
68d480c4
AD		 3408 igb_update_mc_addr_list(hw, mta_list, i);
3409 kfree(mta_list);
3410
4cd24eaf 3411 return netdev_mc_count(netdev);
68d480c4
AD		 3412}
3413
3414/**
3415 * igb_write_uc_addr_list - write unicast addresses to RAR table
3416 * @netdev: network interface device structure
3417 *
3418 * Writes unicast address list to the RAR table.
3419 * Returns: -ENOMEM on failure/insufficient address space
3420 * 0 on no addresses written
3421 * X on writing X addresses to the RAR table
3422 **/
3423static int igb_write_uc_addr_list(struct net_device *netdev)
3424{
3425 struct igb_adapter *adapter = netdev_priv(netdev);
3426 struct e1000_hw *hw = &adapter->hw;
3427 unsigned int vfn = adapter->vfs_allocated_count;
3428 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3429 int count = 0;
3430
3431 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3432 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3433 return -ENOMEM;
9d5c8243 3434
32e7bfc4 3435 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3436 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3437
3438 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3439 if (!rar_entries)
3440 break;
26ad9178
AD		 3441 igb_rar_set_qsel(adapter, ha->addr,
3442 rar_entries--,
68d480c4
AD		 3443 vfn);
3444 count++;
ff41f8dc
AD		 3445 }
3446 }
3447 /* write the addresses in reverse order to avoid write combining */
3448 for (; rar_entries > 0 ; rar_entries--) {
3449 wr32(E1000_RAH(rar_entries), 0);
3450 wr32(E1000_RAL(rar_entries), 0);
3451 }
3452 wrfl();
3453
68d480c4
AD		 3454 return count;
3455}
3456
3457/**
3458 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3459 * @netdev: network interface device structure
3460 *
3461 * The set_rx_mode entry point is called whenever the unicast or multicast
3462 * address lists or the network interface flags are updated. This routine is
3463 * responsible for configuring the hardware for proper unicast, multicast,
3464 * promiscuous mode, and all-multi behavior.
3465 **/
3466static void igb_set_rx_mode(struct net_device *netdev)
3467{
3468 struct igb_adapter *adapter = netdev_priv(netdev);
3469 struct e1000_hw *hw = &adapter->hw;
3470 unsigned int vfn = adapter->vfs_allocated_count;
3471 u32 rctl, vmolr = 0;
3472 int count;
3473
3474 /* Check for Promiscuous and All Multicast modes */
3475 rctl = rd32(E1000_RCTL);
3476
3477 /* clear the effected bits */
3478 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3479
3480 if (netdev->flags & IFF_PROMISC) {
3481 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3482 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3483 } else {
3484 if (netdev->flags & IFF_ALLMULTI) {
3485 rctl |= E1000_RCTL_MPE;
3486 vmolr |= E1000_VMOLR_MPME;
3487 } else {
3488 /*
3489 * Write addresses to the MTA, if the attempt fails
25985edc 3490 * then we should just turn on promiscuous mode so
68d480c4
AD		 3491 * that we can at least receive multicast traffic
3492 */
3493 count = igb_write_mc_addr_list(netdev);
3494 if (count < 0) {
3495 rctl |= E1000_RCTL_MPE;
3496 vmolr |= E1000_VMOLR_MPME;
3497 } else if (count) {
3498 vmolr |= E1000_VMOLR_ROMPE;
3499 }
3500 }
3501 /*
3502 * Write addresses to available RAR registers, if there is not
3503 * sufficient space to store all the addresses then enable
25985edc 3504 * unicast promiscuous mode
68d480c4
AD		 3505 */
3506 count = igb_write_uc_addr_list(netdev);
3507 if (count < 0) {
3508 rctl |= E1000_RCTL_UPE;
3509 vmolr |= E1000_VMOLR_ROPE;
3510 }
3511 rctl |= E1000_RCTL_VFE;
28fc06f5 3512 }
68d480c4 3513 wr32(E1000_RCTL, rctl);
28fc06f5 3514
68d480c4
AD		 3515 /*
3516 * In order to support SR-IOV and eventually VMDq it is necessary to set
3517 * the VMOLR to enable the appropriate modes. Without this workaround
3518 * we will have issues with VLAN tag stripping not being done for frames
3519 * that are only arriving because we are the default pool
3520 */
f96a8a0b 3521 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3522 return;
9d5c8243 3523
68d480c4
AD		 3524 vmolr |= rd32(E1000_VMOLR(vfn)) &
3525 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3526 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3527 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3528}
3529
13800469
GR		 3530static void igb_check_wvbr(struct igb_adapter *adapter)
3531{
3532 struct e1000_hw *hw = &adapter->hw;
3533 u32 wvbr = 0;
3534
3535 switch (hw->mac.type) {
3536 case e1000_82576:
3537 case e1000_i350:
3538 if (!(wvbr = rd32(E1000_WVBR)))
3539 return;
3540 break;
3541 default:
3542 break;
3543 }
3544
3545 adapter->wvbr |= wvbr;
3546}
3547
3548#define IGB_STAGGERED_QUEUE_OFFSET 8
3549
3550static void igb_spoof_check(struct igb_adapter *adapter)
3551{
3552 int j;
3553
3554 if (!adapter->wvbr)
3555 return;
3556
3557 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3558 if (adapter->wvbr & (1 << j) ||
3559 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3560 dev_warn(&adapter->pdev->dev,
3561 "Spoof event(s) detected on VF %d\n", j);
3562 adapter->wvbr &=
3563 ~((1 << j) |
3564 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3565 }
3566 }
3567}
3568
9d5c8243
AK		 3569/* Need to wait a few seconds after link up to get diagnostic information from
3570 * the phy */
3571static void igb_update_phy_info(unsigned long data)
3572{
3573 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3574 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3575}
3576
4d6b725e
AD		 3577/**
3578 * igb_has_link - check shared code for link and determine up/down
3579 * @adapter: pointer to driver private info
3580 **/
3145535a 3581bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3582{
3583 struct e1000_hw *hw = &adapter->hw;
3584 bool link_active = false;
3585 s32 ret_val = 0;
3586
3587 /* get_link_status is set on LSC (link status) interrupt or
3588 * rx sequence error interrupt. get_link_status will stay
3589 * false until the e1000_check_for_link establishes link
3590 * for copper adapters ONLY
3591 */
3592 switch (hw->phy.media_type) {
3593 case e1000_media_type_copper:
3594 if (hw->mac.get_link_status) {
3595 ret_val = hw->mac.ops.check_for_link(hw);
3596 link_active = !hw->mac.get_link_status;
3597 } else {
3598 link_active = true;
3599 }
3600 break;
4d6b725e
AD		 3601 case e1000_media_type_internal_serdes:
3602 ret_val = hw->mac.ops.check_for_link(hw);
3603 link_active = hw->mac.serdes_has_link;
3604 break;
3605 default:
3606 case e1000_media_type_unknown:
3607 break;
3608 }
3609
3610 return link_active;
3611}
3612
563988dc
SA		 3613static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3614{
3615 bool ret = false;
3616 u32 ctrl_ext, thstat;
3617
f96a8a0b 3618 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3619 if (hw->mac.type == e1000_i350) {
3620 thstat = rd32(E1000_THSTAT);
3621 ctrl_ext = rd32(E1000_CTRL_EXT);
3622
3623 if ((hw->phy.media_type == e1000_media_type_copper) &&
3624 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3625 ret = !!(thstat & event);
3626 }
3627 }
3628
3629 return ret;
3630}
3631
9d5c8243
AK		 3632/**
3633 * igb_watchdog - Timer Call-back
3634 * @data: pointer to adapter cast into an unsigned long
3635 **/
3636static void igb_watchdog(unsigned long data)
3637{
3638 struct igb_adapter *adapter = (struct igb_adapter *)data;
3639 /* Do the rest outside of interrupt context */
3640 schedule_work(&adapter->watchdog_task);
3641}
3642
3643static void igb_watchdog_task(struct work_struct *work)
3644{
3645 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3646 struct igb_adapter,
3647 watchdog_task);
9d5c8243 3648 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3649 struct net_device *netdev = adapter->netdev;
563988dc 3650 u32 link;
7a6ea550 3651 int i;
9d5c8243 3652
4d6b725e 3653 link = igb_has_link(adapter);
9d5c8243 3654 if (link) {
749ab2cd
YZ		 3655 /* Cancel scheduled suspend requests. */
3656 pm_runtime_resume(netdev->dev.parent);
3657
9d5c8243
AK		 3658 if (!netif_carrier_ok(netdev)) {
3659 u32 ctrl;
330a6d6a
AD		 3660 hw->mac.ops.get_speed_and_duplex(hw,
3661 &adapter->link_speed,
3662 &adapter->link_duplex);
9d5c8243
AK		 3663
3664 ctrl = rd32(E1000_CTRL);
527d47c1 3665 /* Links status message must follow this format */
876d2d6f
JK		 3666 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3667 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3668 netdev->name,
3669 adapter->link_speed,
3670 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3671 "Full" : "Half",
3672 (ctrl & E1000_CTRL_TFCE) &&
3673 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3674 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3675 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3676
563988dc 3677 /* check for thermal sensor event */
876d2d6f
JK		 3678 if (igb_thermal_sensor_event(hw,
3679 E1000_THSTAT_LINK_THROTTLE)) {
3680 netdev_info(netdev, "The network adapter link "
3681 "speed was downshifted because it "
3682 "overheated\n");
7ef5ed1c 3683 }
563988dc 3684
d07f3e37 3685 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3686 adapter->tx_timeout_factor = 1;
3687 switch (adapter->link_speed) {
3688 case SPEED_10:
9d5c8243
AK		 3689 adapter->tx_timeout_factor = 14;
3690 break;
3691 case SPEED_100:
9d5c8243
AK		 3692 /* maybe add some timeout factor ? */
3693 break;
3694 }
3695
3696 netif_carrier_on(netdev);
9d5c8243 3697
4ae196df 3698 igb_ping_all_vfs(adapter);
17dc566c 3699 igb_check_vf_rate_limit(adapter);
4ae196df 3700
4b1a9877 3701 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3702 if (!test_bit(__IGB_DOWN, &adapter->state))
3703 mod_timer(&adapter->phy_info_timer,
3704 round_jiffies(jiffies + 2 * HZ));
3705 }
3706 } else {
3707 if (netif_carrier_ok(netdev)) {
3708 adapter->link_speed = 0;
3709 adapter->link_duplex = 0;
563988dc
SA		 3710
3711 /* check for thermal sensor event */
876d2d6f
JK		 3712 if (igb_thermal_sensor_event(hw,
3713 E1000_THSTAT_PWR_DOWN)) {
3714 netdev_err(netdev, "The network adapter was "
3715 "stopped because it overheated\n");
7ef5ed1c 3716 }
563988dc 3717
527d47c1
AD		 3718 /* Links status message must follow this format */
3719 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3720 netdev->name);
9d5c8243 3721 netif_carrier_off(netdev);
4b1a9877 3722
4ae196df
AD		 3723 igb_ping_all_vfs(adapter);
3724
4b1a9877 3725 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3726 if (!test_bit(__IGB_DOWN, &adapter->state))
3727 mod_timer(&adapter->phy_info_timer,
3728 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3729
3730 pm_schedule_suspend(netdev->dev.parent,
3731 MSEC_PER_SEC * 5);
9d5c8243
AK		 3732 }
3733 }
3734
12dcd86b
ED		 3735 spin_lock(&adapter->stats64_lock);
3736 igb_update_stats(adapter, &adapter->stats64);
3737 spin_unlock(&adapter->stats64_lock);
9d5c8243 3738
dbabb065 3739 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3740 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3741 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3742 /* We've lost link, so the controller stops DMA,
3743 * but we've got queued Tx work that's never going
3744 * to get done, so reset controller to flush Tx.
3745 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3746 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3747 adapter->tx_timeout_count++;
3748 schedule_work(&adapter->reset_task);
3749 /* return immediately since reset is imminent */
3750 return;
3751 }
9d5c8243 3752 }
9d5c8243 3753
dbabb065 3754 /* Force detection of hung controller every watchdog period */
6d095fa8 3755 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3756 }
f7ba205e 3757
9d5c8243 3758 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3759 if (adapter->msix_entries) {
047e0030 3760 u32 eics = 0;
0d1ae7f4
AD		 3761 for (i = 0; i < adapter->num_q_vectors; i++)
3762 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3763 wr32(E1000_EICS, eics);
3764 } else {
3765 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3766 }
9d5c8243 3767
13800469
GR		 3768 igb_spoof_check(adapter);
3769
9d5c8243
AK		 3770 /* Reset the timer */
3771 if (!test_bit(__IGB_DOWN, &adapter->state))
3772 mod_timer(&adapter->watchdog_timer,
3773 round_jiffies(jiffies + 2 * HZ));
3774}
3775
3776enum latency_range {
3777 lowest_latency = 0,
3778 low_latency = 1,
3779 bulk_latency = 2,
3780 latency_invalid = 255
3781};
3782
6eb5a7f1
AD		 3783/**
3784 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3785 *
3786 * Stores a new ITR value based on strictly on packet size. This
3787 * algorithm is less sophisticated than that used in igb_update_itr,
3788 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3789 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3790 * were determined based on theoretical maximum wire speed and testing
3791 * data, in order to minimize response time while increasing bulk
3792 * throughput.
3793 * This functionality is controlled by the InterruptThrottleRate module
3794 * parameter (see igb_param.c)
3795 * NOTE: This function is called only when operating in a multiqueue
3796 * receive environment.
047e0030 3797 * @q_vector: pointer to q_vector
6eb5a7f1 3798 **/
047e0030 3799static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3800{
047e0030 3801 int new_val = q_vector->itr_val;
6eb5a7f1 3802 int avg_wire_size = 0;
047e0030 3803 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 3804 unsigned int packets;
9d5c8243 3805
6eb5a7f1
AD		 3806 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3807 * ints/sec - ITR timer value of 120 ticks.
3808 */
3809 if (adapter->link_speed != SPEED_1000) {
0ba82994 3810 new_val = IGB_4K_ITR;
6eb5a7f1 3811 goto set_itr_val;
9d5c8243 3812 }
047e0030 3813
0ba82994
AD		 3814 packets = q_vector->rx.total_packets;
3815 if (packets)
3816 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 3817
0ba82994
AD		 3818 packets = q_vector->tx.total_packets;
3819 if (packets)
3820 avg_wire_size = max_t(u32, avg_wire_size,
3821 q_vector->tx.total_bytes / packets);
047e0030
AD		 3822
3823 /* if avg_wire_size isn't set no work was done */
3824 if (!avg_wire_size)
3825 goto clear_counts;
9d5c8243 3826
6eb5a7f1
AD		 3827 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3828 avg_wire_size += 24;
3829
3830 /* Don't starve jumbo frames */
3831 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3832
6eb5a7f1
AD		 3833 /* Give a little boost to mid-size frames */
3834 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3835 new_val = avg_wire_size / 3;
3836 else
3837 new_val = avg_wire_size / 2;
9d5c8243 3838
0ba82994
AD		 3839 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3840 if (new_val < IGB_20K_ITR &&
3841 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3842 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3843 new_val = IGB_20K_ITR;
abe1c363 3844
6eb5a7f1 3845set_itr_val:
047e0030
AD		 3846 if (new_val != q_vector->itr_val) {
3847 q_vector->itr_val = new_val;
3848 q_vector->set_itr = 1;
9d5c8243 3849 }
6eb5a7f1 3850clear_counts:
0ba82994
AD		 3851 q_vector->rx.total_bytes = 0;
3852 q_vector->rx.total_packets = 0;
3853 q_vector->tx.total_bytes = 0;
3854 q_vector->tx.total_packets = 0;
9d5c8243
AK		 3855}
3856
3857/**
3858 * igb_update_itr - update the dynamic ITR value based on statistics
3859 * Stores a new ITR value based on packets and byte
3860 * counts during the last interrupt. The advantage of per interrupt
3861 * computation is faster updates and more accurate ITR for the current
3862 * traffic pattern. Constants in this function were computed
3863 * based on theoretical maximum wire speed and thresholds were set based
3864 * on testing data as well as attempting to minimize response time
3865 * while increasing bulk throughput.
3866 * this functionality is controlled by the InterruptThrottleRate module
3867 * parameter (see igb_param.c)
3868 * NOTE: These calculations are only valid when operating in a single-
3869 * queue environment.
0ba82994
AD		 3870 * @q_vector: pointer to q_vector
3871 * @ring_container: ring info to update the itr for
9d5c8243 3872 **/
0ba82994
AD		 3873static void igb_update_itr(struct igb_q_vector *q_vector,
3874 struct igb_ring_container *ring_container)
9d5c8243 3875{
0ba82994
AD		 3876 unsigned int packets = ring_container->total_packets;
3877 unsigned int bytes = ring_container->total_bytes;
3878 u8 itrval = ring_container->itr;
9d5c8243 3879
0ba82994 3880 /* no packets, exit with status unchanged */
9d5c8243 3881 if (packets == 0)
0ba82994 3882 return;
9d5c8243 3883
0ba82994 3884 switch (itrval) {
9d5c8243
AK		 3885 case lowest_latency:
3886 /* handle TSO and jumbo frames */
3887 if (bytes/packets > 8000)
0ba82994 3888 itrval = bulk_latency;
9d5c8243 3889 else if ((packets < 5) && (bytes > 512))
0ba82994 3890 itrval = low_latency;
9d5c8243
AK		 3891 break;
3892 case low_latency: /* 50 usec aka 20000 ints/s */
3893 if (bytes > 10000) {
3894 /* this if handles the TSO accounting */
3895 if (bytes/packets > 8000) {
0ba82994 3896 itrval = bulk_latency;
9d5c8243 3897 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 3898 itrval = bulk_latency;
9d5c8243 3899 } else if ((packets > 35)) {
0ba82994 3900 itrval = lowest_latency;
9d5c8243
AK		 3901 }
3902 } else if (bytes/packets > 2000) {
0ba82994 3903 itrval = bulk_latency;
9d5c8243 3904 } else if (packets <= 2 && bytes < 512) {
0ba82994 3905 itrval = lowest_latency;
9d5c8243
AK		 3906 }
3907 break;
3908 case bulk_latency: /* 250 usec aka 4000 ints/s */
3909 if (bytes > 25000) {
3910 if (packets > 35)
0ba82994 3911 itrval = low_latency;
1e5c3d21 3912 } else if (bytes < 1500) {
0ba82994 3913 itrval = low_latency;
9d5c8243
AK		 3914 }
3915 break;
3916 }
3917
0ba82994
AD		 3918 /* clear work counters since we have the values we need */
3919 ring_container->total_bytes = 0;
3920 ring_container->total_packets = 0;
3921
3922 /* write updated itr to ring container */
3923 ring_container->itr = itrval;
9d5c8243
AK		 3924}
3925
0ba82994 3926static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 3927{
0ba82994 3928 struct igb_adapter *adapter = q_vector->adapter;
047e0030 3929 u32 new_itr = q_vector->itr_val;
0ba82994 3930 u8 current_itr = 0;
9d5c8243
AK		 3931
3932 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3933 if (adapter->link_speed != SPEED_1000) {
3934 current_itr = 0;
0ba82994 3935 new_itr = IGB_4K_ITR;
9d5c8243
AK		 3936 goto set_itr_now;
3937 }
3938
0ba82994
AD		 3939 igb_update_itr(q_vector, &q_vector->tx);
3940 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 3941
0ba82994 3942 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 3943
6eb5a7f1 3944 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 3945 if (current_itr == lowest_latency &&
3946 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3947 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 3948 current_itr = low_latency;
3949
9d5c8243
AK		 3950 switch (current_itr) {
3951 /* counts and packets in update_itr are dependent on these numbers */
3952 case lowest_latency:
0ba82994 3953 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 3954 break;
3955 case low_latency:
0ba82994 3956 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 3957 break;
3958 case bulk_latency:
0ba82994 3959 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 3960 break;
3961 default:
3962 break;
3963 }
3964
3965set_itr_now:
047e0030 3966 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3967 /* this attempts to bias the interrupt rate towards Bulk
3968 * by adding intermediate steps when interrupt rate is
3969 * increasing */
047e0030
AD		 3970 new_itr = new_itr > q_vector->itr_val ?
3971 max((new_itr * q_vector->itr_val) /
3972 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 3973 new_itr) :
9d5c8243
AK		 3974 new_itr;
3975 /* Don't write the value here; it resets the adapter's
3976 * internal timer, and causes us to delay far longer than
3977 * we should between interrupts. Instead, we write the ITR
3978 * value at the beginning of the next interrupt so the timing
3979 * ends up being correct.
3980 */
047e0030
AD		 3981 q_vector->itr_val = new_itr;
3982 q_vector->set_itr = 1;
9d5c8243 3983 }
9d5c8243
AK		 3984}
3985
c50b52a0
SH		 3986static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3987 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 3988{
3989 struct e1000_adv_tx_context_desc *context_desc;
3990 u16 i = tx_ring->next_to_use;
3991
3992 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3993
3994 i++;
3995 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3996
3997 /* set bits to identify this as an advanced context descriptor */
3998 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
3999
4000 /* For 82575, context index must be unique per ring. */
866cff06 4001 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4002 mss_l4len_idx |= tx_ring->reg_idx << 4;
4003
4004 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4005 context_desc->seqnum_seed = 0;
4006 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4007 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4008}
4009
7af40ad9
AD		 4010static int igb_tso(struct igb_ring *tx_ring,
4011 struct igb_tx_buffer *first,
4012 u8 *hdr_len)
9d5c8243 4013{
7af40ad9 4014 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4015 u32 vlan_macip_lens, type_tucmd;
4016 u32 mss_l4len_idx, l4len;
4017
4018 if (!skb_is_gso(skb))
4019 return 0;
9d5c8243
AK		 4020
4021 if (skb_header_cloned(skb)) {
7af40ad9 4022 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4023 if (err)
4024 return err;
4025 }
4026
7d13a7d0
AD		 4027 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4028 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4029
7af40ad9 4030 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4031 struct iphdr *iph = ip_hdr(skb);
4032 iph->tot_len = 0;
4033 iph->check = 0;
4034 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4035 iph->daddr, 0,
4036 IPPROTO_TCP,
4037 0);
7d13a7d0 4038 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4039 first->tx_flags |= IGB_TX_FLAGS_TSO |
4040 IGB_TX_FLAGS_CSUM |
4041 IGB_TX_FLAGS_IPV4;
8e1e8a47 4042 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4043 ipv6_hdr(skb)->payload_len = 0;
4044 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4045 &ipv6_hdr(skb)->daddr,
4046 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4047 first->tx_flags |= IGB_TX_FLAGS_TSO |
4048 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4049 }
4050
7af40ad9 4051 /* compute header lengths */
7d13a7d0
AD		 4052 l4len = tcp_hdrlen(skb);
4053 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4054
7af40ad9
AD		 4055 /* update gso size and bytecount with header size */
4056 first->gso_segs = skb_shinfo(skb)->gso_segs;
4057 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4058
9d5c8243 4059 /* MSS L4LEN IDX */
7d13a7d0
AD		 4060 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4061 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4062
7d13a7d0
AD		 4063 /* VLAN MACLEN IPLEN */
4064 vlan_macip_lens = skb_network_header_len(skb);
4065 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4066 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4067
7d13a7d0 4068 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4069
7d13a7d0 4070 return 1;
9d5c8243
AK		 4071}
4072
7af40ad9 4073static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4074{
7af40ad9 4075 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4076 u32 vlan_macip_lens = 0;
4077 u32 mss_l4len_idx = 0;
4078 u32 type_tucmd = 0;
9d5c8243 4079
7d13a7d0 4080 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4081 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4082 return;
7d13a7d0
AD		 4083 } else {
4084 u8 l4_hdr = 0;
7af40ad9 4085 switch (first->protocol) {
7d13a7d0
AD		 4086 case __constant_htons(ETH_P_IP):
4087 vlan_macip_lens |= skb_network_header_len(skb);
4088 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4089 l4_hdr = ip_hdr(skb)->protocol;
4090 break;
4091 case __constant_htons(ETH_P_IPV6):
4092 vlan_macip_lens |= skb_network_header_len(skb);
4093 l4_hdr = ipv6_hdr(skb)->nexthdr;
4094 break;
4095 default:
4096 if (unlikely(net_ratelimit())) {
4097 dev_warn(tx_ring->dev,
4098 "partial checksum but proto=%x!\n",
7af40ad9 4099 first->protocol);
fa4a7ef3 4100 }
7d13a7d0
AD		 4101 break;
4102 }
fa4a7ef3 4103
7d13a7d0
AD		 4104 switch (l4_hdr) {
4105 case IPPROTO_TCP:
4106 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4107 mss_l4len_idx = tcp_hdrlen(skb) <<
4108 E1000_ADVTXD_L4LEN_SHIFT;
4109 break;
4110 case IPPROTO_SCTP:
4111 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4112 mss_l4len_idx = sizeof(struct sctphdr) <<
4113 E1000_ADVTXD_L4LEN_SHIFT;
4114 break;
4115 case IPPROTO_UDP:
4116 mss_l4len_idx = sizeof(struct udphdr) <<
4117 E1000_ADVTXD_L4LEN_SHIFT;
4118 break;
4119 default:
4120 if (unlikely(net_ratelimit())) {
4121 dev_warn(tx_ring->dev,
4122 "partial checksum but l4 proto=%x!\n",
4123 l4_hdr);
44b0cda3 4124 }
7d13a7d0 4125 break;
9d5c8243 4126 }
7af40ad9
AD		 4127
4128 /* update TX checksum flag */
4129 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4130 }
9d5c8243 4131
7d13a7d0 4132 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4133 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4134
7d13a7d0 4135 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4136}
4137
e032afc8
AD		 4138static __le32 igb_tx_cmd_type(u32 tx_flags)
4139{
4140 /* set type for advanced descriptor with frame checksum insertion */
4141 __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA |
4142 E1000_ADVTXD_DCMD_IFCS |
4143 E1000_ADVTXD_DCMD_DEXT);
4144
4145 /* set HW vlan bit if vlan is present */
4146 if (tx_flags & IGB_TX_FLAGS_VLAN)
4147 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE);
4148
3c89f6d0 4149#ifdef CONFIG_IGB_PTP
e032afc8 4150 /* set timestamp bit if present */
1f6e8178 4151 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP))
e032afc8 4152 cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP);
3c89f6d0 4153#endif /* CONFIG_IGB_PTP */
e032afc8
AD		 4154
4155 /* set segmentation bits for TSO */
4156 if (tx_flags & IGB_TX_FLAGS_TSO)
4157 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE);
4158
4159 return cmd_type;
4160}
4161
7af40ad9
AD		 4162static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4163 union e1000_adv_tx_desc *tx_desc,
4164 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4165{
4166 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4167
4168 /* 82575 requires a unique index per ring if any offload is enabled */
4169 if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) &&
866cff06 4170 test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4171 olinfo_status |= tx_ring->reg_idx << 4;
4172
4173 /* insert L4 checksum */
4174 if (tx_flags & IGB_TX_FLAGS_CSUM) {
4175 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
4176
4177 /* insert IPv4 checksum */
4178 if (tx_flags & IGB_TX_FLAGS_IPV4)
4179 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
4180 }
4181
7af40ad9 4182 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4183}
4184
ebe42d16
AD		 4185/*
4186 * The largest size we can write to the descriptor is 65535. In order to
4187 * maintain a power of two alignment we have to limit ourselves to 32K.
4188 */
4189#define IGB_MAX_TXD_PWR 15
7af40ad9 4190#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4191
7af40ad9
AD		 4192static void igb_tx_map(struct igb_ring *tx_ring,
4193 struct igb_tx_buffer *first,
ebe42d16 4194 const u8 hdr_len)
9d5c8243 4195{
7af40ad9 4196 struct sk_buff *skb = first->skb;
c9f14bf3 4197 struct igb_tx_buffer *tx_buffer;
ebe42d16
AD		 4198 union e1000_adv_tx_desc *tx_desc;
4199 dma_addr_t dma;
4200 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
4201 unsigned int data_len = skb->data_len;
4202 unsigned int size = skb_headlen(skb);
4203 unsigned int paylen = skb->len - hdr_len;
4204 __le32 cmd_type;
7af40ad9 4205 u32 tx_flags = first->tx_flags;
ebe42d16 4206 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4207
4208 tx_desc = IGB_TX_DESC(tx_ring, i);
4209
7af40ad9 4210 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen);
ebe42d16
AD		 4211 cmd_type = igb_tx_cmd_type(tx_flags);
4212
4213 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4214 if (dma_mapping_error(tx_ring->dev, dma))
6366ad33 4215 goto dma_error;
9d5c8243 4216
ebe42d16 4217 /* record length, and DMA address */
c9f14bf3
AD		 4218 dma_unmap_len_set(first, len, size);
4219 dma_unmap_addr_set(first, dma, dma);
ebe42d16
AD		 4220 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4221
4222 for (;;) {
4223 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4224 tx_desc->read.cmd_type_len =
4225 cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD);
4226
4227 i++;
4228 tx_desc++;
4229 if (i == tx_ring->count) {
4230 tx_desc = IGB_TX_DESC(tx_ring, 0);
4231 i = 0;
4232 }
4233
4234 dma += IGB_MAX_DATA_PER_TXD;
4235 size -= IGB_MAX_DATA_PER_TXD;
4236
4237 tx_desc->read.olinfo_status = 0;
4238 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4239 }
4240
4241 if (likely(!data_len))
4242 break;
2bbfebe2 4243
ebe42d16 4244 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9d5c8243 4245
65689fef 4246 i++;
ebe42d16
AD		 4247 tx_desc++;
4248 if (i == tx_ring->count) {
4249 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4250 i = 0;
ebe42d16 4251 }
65689fef 4252
9e903e08 4253 size = skb_frag_size(frag);
ebe42d16
AD		 4254 data_len -= size;
4255
4256 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4257 size, DMA_TO_DEVICE);
4258 if (dma_mapping_error(tx_ring->dev, dma))
6366ad33
AD		 4259 goto dma_error;
4260
c9f14bf3
AD		 4261 tx_buffer = &tx_ring->tx_buffer_info[i];
4262 dma_unmap_len_set(tx_buffer, len, size);
4263 dma_unmap_addr_set(tx_buffer, dma, dma);
ebe42d16
AD		 4264
4265 tx_desc->read.olinfo_status = 0;
4266 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4267
4268 frag++;
9d5c8243
AK		 4269 }
4270
bdbc0631
ED		 4271 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4272
ebe42d16
AD		 4273 /* write last descriptor with RS and EOP bits */
4274 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD);
6b8f0922
BG		 4275 if (unlikely(skb->no_fcs))
4276 cmd_type &= ~(cpu_to_le32(E1000_ADVTXD_DCMD_IFCS));
ebe42d16 4277 tx_desc->read.cmd_type_len = cmd_type;
8542db05
AD		 4278
4279 /* set the timestamp */
4280 first->time_stamp = jiffies;
4281
ebe42d16
AD		 4282 /*
4283 * Force memory writes to complete before letting h/w know there
4284 * are new descriptors to fetch. (Only applicable for weak-ordered
4285 * memory model archs, such as IA-64).
4286 *
4287 * We also need this memory barrier to make certain all of the
4288 * status bits have been updated before next_to_watch is written.
4289 */
4290 wmb();
4291
8542db05 4292 /* set next_to_watch value indicating a packet is present */
ebe42d16 4293 first->next_to_watch = tx_desc;
9d5c8243 4294
ebe42d16
AD		 4295 i++;
4296 if (i == tx_ring->count)
4297 i = 0;
6366ad33 4298
ebe42d16 4299 tx_ring->next_to_use = i;
6366ad33 4300
ebe42d16 4301 writel(i, tx_ring->tail);
6366ad33 4302
ebe42d16
AD		 4303 /* we need this if more than one processor can write to our tail
4304 * at a time, it syncronizes IO on IA64/Altix systems */
4305 mmiowb();
4306
4307 return;
4308
4309dma_error:
4310 dev_err(tx_ring->dev, "TX DMA map failed\n");
4311
4312 /* clear dma mappings for failed tx_buffer_info map */
4313 for (;;) {
c9f14bf3
AD		 4314 tx_buffer = &tx_ring->tx_buffer_info[i];
4315 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4316 if (tx_buffer == first)
ebe42d16 4317 break;
a77ff709
NN		 4318 if (i == 0)
4319 i = tx_ring->count;
6366ad33 4320 i--;
6366ad33
AD		 4321 }
4322
9d5c8243 4323 tx_ring->next_to_use = i;
9d5c8243
AK		 4324}
4325
6ad4edfc 4326static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4327{
e694e964
AD		 4328 struct net_device *netdev = tx_ring->netdev;
4329
661086df 4330 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4331
9d5c8243
AK		 4332 /* Herbert's original patch had:
4333 * smp_mb__after_netif_stop_queue();
4334 * but since that doesn't exist yet, just open code it. */
4335 smp_mb();
4336
4337 /* We need to check again in a case another CPU has just
4338 * made room available. */
c493ea45 4339 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4340 return -EBUSY;
4341
4342 /* A reprieve! */
661086df 4343 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4344
4345 u64_stats_update_begin(&tx_ring->tx_syncp2);
4346 tx_ring->tx_stats.restart_queue2++;
4347 u64_stats_update_end(&tx_ring->tx_syncp2);
4348
9d5c8243
AK		 4349 return 0;
4350}
4351
6ad4edfc 4352static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4353{
c493ea45 4354 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4355 return 0;
e694e964 4356 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4357}
4358
cd392f5c
AD		 4359netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4360 struct igb_ring *tx_ring)
9d5c8243 4361{
1f6e8178
MV		 4362#ifdef CONFIG_IGB_PTP
4363 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4364#endif /* CONFIG_IGB_PTP */
8542db05 4365 struct igb_tx_buffer *first;
ebe42d16 4366 int tso;
91d4ee33 4367 u32 tx_flags = 0;
31f6adbb 4368 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4369 u8 hdr_len = 0;
9d5c8243 4370
9d5c8243
AK		 4371 /* need: 1 descriptor per page,
4372 * + 2 desc gap to keep tail from touching head,
4373 * + 1 desc for skb->data,
4374 * + 1 desc for context descriptor,
4375 * otherwise try next time */
e694e964 4376 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4377 /* this is a hard error */
9d5c8243
AK		 4378 return NETDEV_TX_BUSY;
4379 }
33af6bcc 4380
7af40ad9
AD		 4381 /* record the location of the first descriptor for this packet */
4382 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4383 first->skb = skb;
4384 first->bytecount = skb->len;
4385 first->gso_segs = 1;
4386
3c89f6d0 4387#ifdef CONFIG_IGB_PTP
1f6e8178
MV		 4388 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4389 !(adapter->ptp_tx_skb))) {
2244d07b 4390 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4391 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4392
4393 adapter->ptp_tx_skb = skb_get(skb);
4394 if (adapter->hw.mac.type == e1000_82576)
4395 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4396 }
3c89f6d0 4397#endif /* CONFIG_IGB_PTP */
9d5c8243 4398
eab6d18d 4399 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4400 tx_flags |= IGB_TX_FLAGS_VLAN;
4401 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4402 }
4403
7af40ad9
AD		 4404 /* record initial flags and protocol */
4405 first->tx_flags = tx_flags;
4406 first->protocol = protocol;
cdfd01fc 4407
7af40ad9
AD		 4408 tso = igb_tso(tx_ring, first, &hdr_len);
4409 if (tso < 0)
7d13a7d0 4410 goto out_drop;
7af40ad9
AD		 4411 else if (!tso)
4412 igb_tx_csum(tx_ring, first);
9d5c8243 4413
7af40ad9 4414 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4415
4416 /* Make sure there is space in the ring for the next send. */
e694e964 4417 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4418
9d5c8243 4419 return NETDEV_TX_OK;
7d13a7d0
AD		 4420
4421out_drop:
7af40ad9
AD		 4422 igb_unmap_and_free_tx_resource(tx_ring, first);
4423
7d13a7d0 4424 return NETDEV_TX_OK;
9d5c8243
AK		 4425}
4426
1cc3bd87
AD		 4427static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4428 struct sk_buff *skb)
4429{
4430 unsigned int r_idx = skb->queue_mapping;
4431
4432 if (r_idx >= adapter->num_tx_queues)
4433 r_idx = r_idx % adapter->num_tx_queues;
4434
4435 return adapter->tx_ring[r_idx];
4436}
4437
cd392f5c
AD		 4438static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4439 struct net_device *netdev)
9d5c8243
AK		 4440{
4441 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4442
4443 if (test_bit(__IGB_DOWN, &adapter->state)) {
4444 dev_kfree_skb_any(skb);
4445 return NETDEV_TX_OK;
4446 }
4447
4448 if (skb->len <= 0) {
4449 dev_kfree_skb_any(skb);
4450 return NETDEV_TX_OK;
4451 }
4452
1cc3bd87
AD		 4453 /*
4454 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4455 * in order to meet this minimum size requirement.
4456 */
ea5ceeab
TD		 4457 if (unlikely(skb->len < 17)) {
4458 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4459 return NETDEV_TX_OK;
4460 skb->len = 17;
ea5ceeab 4461 skb_set_tail_pointer(skb, 17);
1cc3bd87 4462 }
9d5c8243 4463
1cc3bd87 4464 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4465}
4466
4467/**
4468 * igb_tx_timeout - Respond to a Tx Hang
4469 * @netdev: network interface device structure
4470 **/
4471static void igb_tx_timeout(struct net_device *netdev)
4472{
4473 struct igb_adapter *adapter = netdev_priv(netdev);
4474 struct e1000_hw *hw = &adapter->hw;
4475
4476 /* Do the reset outside of interrupt context */
4477 adapter->tx_timeout_count++;
f7ba205e 4478
06218a8d 4479 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4480 hw->dev_spec._82575.global_device_reset = true;
4481
9d5c8243 4482 schedule_work(&adapter->reset_task);
265de409
AD		 4483 wr32(E1000_EICS,
4484 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4485}
4486
4487static void igb_reset_task(struct work_struct *work)
4488{
4489 struct igb_adapter *adapter;
4490 adapter = container_of(work, struct igb_adapter, reset_task);
4491
c97ec42a
TI		 4492 igb_dump(adapter);
4493 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4494 igb_reinit_locked(adapter);
4495}
4496
4497/**
12dcd86b 4498 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4499 * @netdev: network interface device structure
12dcd86b 4500 * @stats: rtnl_link_stats64 pointer
9d5c8243 4501 *
9d5c8243 4502 **/
12dcd86b
ED		 4503static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4504 struct rtnl_link_stats64 *stats)
9d5c8243 4505{
12dcd86b
ED		 4506 struct igb_adapter *adapter = netdev_priv(netdev);
4507
4508 spin_lock(&adapter->stats64_lock);
4509 igb_update_stats(adapter, &adapter->stats64);
4510 memcpy(stats, &adapter->stats64, sizeof(*stats));
4511 spin_unlock(&adapter->stats64_lock);
4512
4513 return stats;
9d5c8243
AK		 4514}
4515
4516/**
4517 * igb_change_mtu - Change the Maximum Transfer Unit
4518 * @netdev: network interface device structure
4519 * @new_mtu: new value for maximum frame size
4520 *
4521 * Returns 0 on success, negative on failure
4522 **/
4523static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4524{
4525 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4526 struct pci_dev *pdev = adapter->pdev;
153285f9 4527 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4528
c809d227 4529 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4530 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4531 return -EINVAL;
4532 }
4533
153285f9 4534#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4535 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4536 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4537 return -EINVAL;
4538 }
4539
4540 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4541 msleep(1);
73cd78f1 4542
9d5c8243
AK		 4543 /* igb_down has a dependency on max_frame_size */
4544 adapter->max_frame_size = max_frame;
559e9c49 4545
4c844851
AD		 4546 if (netif_running(netdev))
4547 igb_down(adapter);
9d5c8243 4548
090b1795 4549 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4550 netdev->mtu, new_mtu);
4551 netdev->mtu = new_mtu;
4552
4553 if (netif_running(netdev))
4554 igb_up(adapter);
4555 else
4556 igb_reset(adapter);
4557
4558 clear_bit(__IGB_RESETTING, &adapter->state);
4559
4560 return 0;
4561}
4562
4563/**
4564 * igb_update_stats - Update the board statistics counters
4565 * @adapter: board private structure
4566 **/
4567
12dcd86b
ED		 4568void igb_update_stats(struct igb_adapter *adapter,
4569 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4570{
4571 struct e1000_hw *hw = &adapter->hw;
4572 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4573 u32 reg, mpc;
9d5c8243 4574 u16 phy_tmp;
3f9c0164
AD		 4575 int i;
4576 u64 bytes, packets;
12dcd86b
ED		 4577 unsigned int start;
4578 u64 _bytes, _packets;
9d5c8243
AK		 4579
4580#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4581
4582 /*
4583 * Prevent stats update while adapter is being reset, or if the pci
4584 * connection is down.
4585 */
4586 if (adapter->link_speed == 0)
4587 return;
4588 if (pci_channel_offline(pdev))
4589 return;
4590
3f9c0164
AD		 4591 bytes = 0;
4592 packets = 0;
4593 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4594 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4595 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4596
ae1c07a6
AD		 4597 if (rqdpc) {
4598 ring->rx_stats.drops += rqdpc;
4599 net_stats->rx_fifo_errors += rqdpc;
4600 }
12dcd86b
ED		 4601
4602 do {
4603 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4604 _bytes = ring->rx_stats.bytes;
4605 _packets = ring->rx_stats.packets;
4606 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4607 bytes += _bytes;
4608 packets += _packets;
3f9c0164
AD		 4609 }
4610
128e45eb
AD		 4611 net_stats->rx_bytes = bytes;
4612 net_stats->rx_packets = packets;
3f9c0164
AD		 4613
4614 bytes = 0;
4615 packets = 0;
4616 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4617 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4618 do {
4619 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4620 _bytes = ring->tx_stats.bytes;
4621 _packets = ring->tx_stats.packets;
4622 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4623 bytes += _bytes;
4624 packets += _packets;
3f9c0164 4625 }
128e45eb
AD		 4626 net_stats->tx_bytes = bytes;
4627 net_stats->tx_packets = packets;
3f9c0164
AD		 4628
4629 /* read stats registers */
9d5c8243
AK		 4630 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4631 adapter->stats.gprc += rd32(E1000_GPRC);
4632 adapter->stats.gorc += rd32(E1000_GORCL);
4633 rd32(E1000_GORCH); /* clear GORCL */
4634 adapter->stats.bprc += rd32(E1000_BPRC);
4635 adapter->stats.mprc += rd32(E1000_MPRC);
4636 adapter->stats.roc += rd32(E1000_ROC);
4637
4638 adapter->stats.prc64 += rd32(E1000_PRC64);
4639 adapter->stats.prc127 += rd32(E1000_PRC127);
4640 adapter->stats.prc255 += rd32(E1000_PRC255);
4641 adapter->stats.prc511 += rd32(E1000_PRC511);
4642 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4643 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4644 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4645 adapter->stats.sec += rd32(E1000_SEC);
4646
fa3d9a6d
MW		 4647 mpc = rd32(E1000_MPC);
4648 adapter->stats.mpc += mpc;
4649 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4650 adapter->stats.scc += rd32(E1000_SCC);
4651 adapter->stats.ecol += rd32(E1000_ECOL);
4652 adapter->stats.mcc += rd32(E1000_MCC);
4653 adapter->stats.latecol += rd32(E1000_LATECOL);
4654 adapter->stats.dc += rd32(E1000_DC);
4655 adapter->stats.rlec += rd32(E1000_RLEC);
4656 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4657 adapter->stats.xontxc += rd32(E1000_XONTXC);
4658 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4659 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4660 adapter->stats.fcruc += rd32(E1000_FCRUC);
4661 adapter->stats.gptc += rd32(E1000_GPTC);
4662 adapter->stats.gotc += rd32(E1000_GOTCL);
4663 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4664 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4665 adapter->stats.ruc += rd32(E1000_RUC);
4666 adapter->stats.rfc += rd32(E1000_RFC);
4667 adapter->stats.rjc += rd32(E1000_RJC);
4668 adapter->stats.tor += rd32(E1000_TORH);
4669 adapter->stats.tot += rd32(E1000_TOTH);
4670 adapter->stats.tpr += rd32(E1000_TPR);
4671
4672 adapter->stats.ptc64 += rd32(E1000_PTC64);
4673 adapter->stats.ptc127 += rd32(E1000_PTC127);
4674 adapter->stats.ptc255 += rd32(E1000_PTC255);
4675 adapter->stats.ptc511 += rd32(E1000_PTC511);
4676 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4677 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4678
4679 adapter->stats.mptc += rd32(E1000_MPTC);
4680 adapter->stats.bptc += rd32(E1000_BPTC);
4681
2d0b0f69
NN		 4682 adapter->stats.tpt += rd32(E1000_TPT);
4683 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4684
4685 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4686 /* read internal phy specific stats */
4687 reg = rd32(E1000_CTRL_EXT);
4688 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4689 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4690
4691 /* this stat has invalid values on i210/i211 */
4692 if ((hw->mac.type != e1000_i210) &&
4693 (hw->mac.type != e1000_i211))
4694 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4695 }
4696
9d5c8243
AK		 4697 adapter->stats.tsctc += rd32(E1000_TSCTC);
4698 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4699
4700 adapter->stats.iac += rd32(E1000_IAC);
4701 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4702 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4703 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4704 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4705 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4706 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4707 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4708 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4709
4710 /* Fill out the OS statistics structure */
128e45eb
AD		 4711 net_stats->multicast = adapter->stats.mprc;
4712 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4713
4714 /* Rx Errors */
4715
4716 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4717 * our own version based on RUC and ROC */
128e45eb 4718 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4719 adapter->stats.crcerrs + adapter->stats.algnerrc +
4720 adapter->stats.ruc + adapter->stats.roc +
4721 adapter->stats.cexterr;
128e45eb
AD		 4722 net_stats->rx_length_errors = adapter->stats.ruc +
4723 adapter->stats.roc;
4724 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4725 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4726 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4727
4728 /* Tx Errors */
128e45eb
AD		 4729 net_stats->tx_errors = adapter->stats.ecol +
4730 adapter->stats.latecol;
4731 net_stats->tx_aborted_errors = adapter->stats.ecol;
4732 net_stats->tx_window_errors = adapter->stats.latecol;
4733 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4734
4735 /* Tx Dropped needs to be maintained elsewhere */
4736
4737 /* Phy Stats */
4738 if (hw->phy.media_type == e1000_media_type_copper) {
4739 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4740 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4741 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4742 adapter->phy_stats.idle_errors += phy_tmp;
4743 }
4744 }
4745
4746 /* Management Stats */
4747 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4748 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4749 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4750
4751 /* OS2BMC Stats */
4752 reg = rd32(E1000_MANC);
4753 if (reg & E1000_MANC_EN_BMC2OS) {
4754 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4755 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4756 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4757 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4758 }
9d5c8243
AK		 4759}
4760
9d5c8243
AK		 4761static irqreturn_t igb_msix_other(int irq, void *data)
4762{
047e0030 4763 struct igb_adapter *adapter = data;
9d5c8243 4764 struct e1000_hw *hw = &adapter->hw;
844290e5 4765 u32 icr = rd32(E1000_ICR);
844290e5 4766 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4767
7f081d40
AD		 4768 if (icr & E1000_ICR_DRSTA)
4769 schedule_work(&adapter->reset_task);
4770
047e0030 4771 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4772 /* HW is reporting DMA is out of sync */
4773 adapter->stats.doosync++;
13800469
GR		 4774 /* The DMA Out of Sync is also indication of a spoof event
4775 * in IOV mode. Check the Wrong VM Behavior register to
4776 * see if it is really a spoof event. */
4777 igb_check_wvbr(adapter);
dda0e083 4778 }
eebbbdba 4779
4ae196df
AD		 4780 /* Check for a mailbox event */
4781 if (icr & E1000_ICR_VMMB)
4782 igb_msg_task(adapter);
4783
4784 if (icr & E1000_ICR_LSC) {
4785 hw->mac.get_link_status = 1;
4786 /* guard against interrupt when we're going down */
4787 if (!test_bit(__IGB_DOWN, &adapter->state))
4788 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4789 }
4790
1f6e8178
MV		 4791#ifdef CONFIG_IGB_PTP
4792 if (icr & E1000_ICR_TS) {
4793 u32 tsicr = rd32(E1000_TSICR);
4794
4795 if (tsicr & E1000_TSICR_TXTS) {
4796 /* acknowledge the interrupt */
4797 wr32(E1000_TSICR, E1000_TSICR_TXTS);
4798 /* retrieve hardware timestamp */
4799 schedule_work(&adapter->ptp_tx_work);
4800 }
4801 }
4802#endif /* CONFIG_IGB_PTP */
4803
844290e5 4804 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4805
4806 return IRQ_HANDLED;
4807}
4808
047e0030 4809static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4810{
26b39276 4811 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4812 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4813
047e0030
AD		 4814 if (!q_vector->set_itr)
4815 return;
73cd78f1 4816
047e0030
AD		 4817 if (!itr_val)
4818 itr_val = 0x4;
661086df 4819
26b39276
AD		 4820 if (adapter->hw.mac.type == e1000_82575)
4821 itr_val |= itr_val << 16;
661086df 4822 else
0ba82994 4823 itr_val |= E1000_EITR_CNT_IGNR;
661086df 4824
047e0030
AD		 4825 writel(itr_val, q_vector->itr_register);
4826 q_vector->set_itr = 0;
6eb5a7f1
AD		 4827}
4828
047e0030 4829static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4830{
047e0030 4831 struct igb_q_vector *q_vector = data;
9d5c8243 4832
047e0030
AD		 4833 /* Write the ITR value calculated from the previous interrupt. */
4834 igb_write_itr(q_vector);
9d5c8243 4835
047e0030 4836 napi_schedule(&q_vector->napi);
844290e5 4837
047e0030 4838 return IRQ_HANDLED;
fe4506b6
JC		 4839}
4840
421e02f0 4841#ifdef CONFIG_IGB_DCA
047e0030 4842static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4843{
047e0030 4844 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6
JC		 4845 struct e1000_hw *hw = &adapter->hw;
4846 int cpu = get_cpu();
fe4506b6 4847
047e0030
AD		 4848 if (q_vector->cpu == cpu)
4849 goto out_no_update;
4850
0ba82994
AD		 4851 if (q_vector->tx.ring) {
4852 int q = q_vector->tx.ring->reg_idx;
047e0030
AD		 4853 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
4854 if (hw->mac.type == e1000_82575) {
4855 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
4856 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
2d064c06 4857 } else {
047e0030
AD		 4858 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
4859 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4860 E1000_DCA_TXCTRL_CPUID_SHIFT;
4861 }
4862 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
4863 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
4864 }
0ba82994
AD		 4865 if (q_vector->rx.ring) {
4866 int q = q_vector->rx.ring->reg_idx;
047e0030
AD		 4867 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
4868 if (hw->mac.type == e1000_82575) {
2d064c06 4869 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
92be7917 4870 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
047e0030
AD		 4871 } else {
4872 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
4873 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
4874 E1000_DCA_RXCTRL_CPUID_SHIFT;
2d064c06 4875 }
fe4506b6
JC		 4876 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
4877 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
4878 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
4879 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
fe4506b6 4880 }
047e0030
AD		 4881 q_vector->cpu = cpu;
4882out_no_update:
fe4506b6
JC		 4883 put_cpu();
4884}
4885
4886static void igb_setup_dca(struct igb_adapter *adapter)
4887{
7e0e99ef 4888 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4889 int i;
4890
7dfc16fa 4891 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4892 return;
4893
7e0e99ef
AD		 4894 /* Always use CB2 mode, difference is masked in the CB driver. */
4895 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4896
047e0030 4897 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4898 adapter->q_vector[i]->cpu = -1;
4899 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4900 }
4901}
4902
4903static int __igb_notify_dca(struct device *dev, void *data)
4904{
4905 struct net_device *netdev = dev_get_drvdata(dev);
4906 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4907 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4908 struct e1000_hw *hw = &adapter->hw;
4909 unsigned long event = *(unsigned long *)data;
4910
4911 switch (event) {
4912 case DCA_PROVIDER_ADD:
4913 /* if already enabled, don't do it again */
7dfc16fa 4914 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4915 break;
fe4506b6 4916 if (dca_add_requester(dev) == 0) {
bbd98fe4 4917 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4918 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4919 igb_setup_dca(adapter);
4920 break;
4921 }
4922 /* Fall Through since DCA is disabled. */
4923 case DCA_PROVIDER_REMOVE:
7dfc16fa 4924 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4925 /* without this a class_device is left
047e0030 4926 * hanging around in the sysfs model */
fe4506b6 4927 dca_remove_requester(dev);
090b1795 4928 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4929 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4930 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4931 }
4932 break;
4933 }
bbd98fe4 4934
fe4506b6 4935 return 0;
9d5c8243
AK		 4936}
4937
fe4506b6
JC		 4938static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4939 void *p)
4940{
4941 int ret_val;
4942
4943 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4944 __igb_notify_dca);
4945
4946 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4947}
421e02f0 4948#endif /* CONFIG_IGB_DCA */
9d5c8243 4949
0224d663
GR		 4950#ifdef CONFIG_PCI_IOV
4951static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4952{
4953 unsigned char mac_addr[ETH_ALEN];
0224d663 4954
7efd26d0 4955 eth_random_addr(mac_addr);
0224d663
GR		 4956 igb_set_vf_mac(adapter, vf, mac_addr);
4957
f557147c 4958 return 0;
0224d663
GR		 4959}
4960
f557147c 4961static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 4962{
0224d663 4963 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 4964 struct pci_dev *vfdev;
4965 int dev_id;
0224d663
GR		 4966
4967 switch (adapter->hw.mac.type) {
4968 case e1000_82576:
f557147c 4969 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 4970 break;
4971 case e1000_i350:
f557147c 4972 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 4973 break;
4974 default:
f557147c 4975 return false;
0224d663
GR		 4976 }
4977
f557147c
SA		 4978 /* loop through all the VFs to see if we own any that are assigned */
4979 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
4980 while (vfdev) {
4981 /* if we don't own it we don't care */
4982 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
4983 /* if it is assigned we cannot release it */
4984 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 4985 return true;
4986 }
f557147c
SA		 4987
4988 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 4989 }
f557147c 4990
0224d663
GR		 4991 return false;
4992}
4993
4994#endif
4ae196df
AD		 4995static void igb_ping_all_vfs(struct igb_adapter *adapter)
4996{
4997 struct e1000_hw *hw = &adapter->hw;
4998 u32 ping;
4999 int i;
5000
5001 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5002 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5003 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5004 ping |= E1000_VT_MSGTYPE_CTS;
5005 igb_write_mbx(hw, &ping, 1, i);
5006 }
5007}
5008
7d5753f0
AD		 5009static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5010{
5011 struct e1000_hw *hw = &adapter->hw;
5012 u32 vmolr = rd32(E1000_VMOLR(vf));
5013 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5014
d85b9004 5015 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5016 IGB_VF_FLAG_MULTI_PROMISC);
5017 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5018
5019 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5020 vmolr |= E1000_VMOLR_MPME;
d85b9004 5021 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5022 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5023 } else {
5024 /*
5025 * if we have hashes and we are clearing a multicast promisc
5026 * flag we need to write the hashes to the MTA as this step
5027 * was previously skipped
5028 */
5029 if (vf_data->num_vf_mc_hashes > 30) {
5030 vmolr |= E1000_VMOLR_MPME;
5031 } else if (vf_data->num_vf_mc_hashes) {
5032 int j;
5033 vmolr |= E1000_VMOLR_ROMPE;
5034 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5035 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5036 }
5037 }
5038
5039 wr32(E1000_VMOLR(vf), vmolr);
5040
5041 /* there are flags left unprocessed, likely not supported */
5042 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5043 return -EINVAL;
5044
5045 return 0;
5046
5047}
5048
4ae196df
AD		 5049static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5050 u32 *msgbuf, u32 vf)
5051{
5052 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5053 u16 *hash_list = (u16 *)&msgbuf[1];
5054 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5055 int i;
5056
7d5753f0 5057 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5058 * to this VF for later use to restore when the PF multi cast
5059 * list changes
5060 */
5061 vf_data->num_vf_mc_hashes = n;
5062
7d5753f0
AD		 5063 /* only up to 30 hash values supported */
5064 if (n > 30)
5065 n = 30;
5066
5067 /* store the hashes for later use */
4ae196df 5068 for (i = 0; i < n; i++)
a419aef8 5069 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5070
5071 /* Flush and reset the mta with the new values */
ff41f8dc 5072 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5073
5074 return 0;
5075}
5076
5077static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5078{
5079 struct e1000_hw *hw = &adapter->hw;
5080 struct vf_data_storage *vf_data;
5081 int i, j;
5082
5083 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5084 u32 vmolr = rd32(E1000_VMOLR(i));
5085 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5086
4ae196df 5087 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5088
5089 if ((vf_data->num_vf_mc_hashes > 30) ||
5090 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5091 vmolr |= E1000_VMOLR_MPME;
5092 } else if (vf_data->num_vf_mc_hashes) {
5093 vmolr |= E1000_VMOLR_ROMPE;
5094 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5095 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5096 }
5097 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5098 }
5099}
5100
5101static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5102{
5103 struct e1000_hw *hw = &adapter->hw;
5104 u32 pool_mask, reg, vid;
5105 int i;
5106
5107 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5108
5109 /* Find the vlan filter for this id */
5110 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5111 reg = rd32(E1000_VLVF(i));
5112
5113 /* remove the vf from the pool */
5114 reg &= ~pool_mask;
5115
5116 /* if pool is empty then remove entry from vfta */
5117 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5118 (reg & E1000_VLVF_VLANID_ENABLE)) {
5119 reg = 0;
5120 vid = reg & E1000_VLVF_VLANID_MASK;
5121 igb_vfta_set(hw, vid, false);
5122 }
5123
5124 wr32(E1000_VLVF(i), reg);
5125 }
ae641bdc
AD		 5126
5127 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5128}
5129
5130static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5131{
5132 struct e1000_hw *hw = &adapter->hw;
5133 u32 reg, i;
5134
51466239
AD		 5135 /* The vlvf table only exists on 82576 hardware and newer */
5136 if (hw->mac.type < e1000_82576)
5137 return -1;
5138
5139 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5140 if (!adapter->vfs_allocated_count)
5141 return -1;
5142
5143 /* Find the vlan filter for this id */
5144 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5145 reg = rd32(E1000_VLVF(i));
5146 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5147 vid == (reg & E1000_VLVF_VLANID_MASK))
5148 break;
5149 }
5150
5151 if (add) {
5152 if (i == E1000_VLVF_ARRAY_SIZE) {
5153 /* Did not find a matching VLAN ID entry that was
5154 * enabled. Search for a free filter entry, i.e.
5155 * one without the enable bit set
5156 */
5157 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5158 reg = rd32(E1000_VLVF(i));
5159 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5160 break;
5161 }
5162 }
5163 if (i < E1000_VLVF_ARRAY_SIZE) {
5164 /* Found an enabled/available entry */
5165 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5166
5167 /* if !enabled we need to set this up in vfta */
5168 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5169 /* add VID to filter table */
5170 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5171 reg |= E1000_VLVF_VLANID_ENABLE;
5172 }
cad6d05f
AD		 5173 reg &= ~E1000_VLVF_VLANID_MASK;
5174 reg |= vid;
4ae196df 5175 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5176
5177 /* do not modify RLPML for PF devices */
5178 if (vf >= adapter->vfs_allocated_count)
5179 return 0;
5180
5181 if (!adapter->vf_data[vf].vlans_enabled) {
5182 u32 size;
5183 reg = rd32(E1000_VMOLR(vf));
5184 size = reg & E1000_VMOLR_RLPML_MASK;
5185 size += 4;
5186 reg &= ~E1000_VMOLR_RLPML_MASK;
5187 reg |= size;
5188 wr32(E1000_VMOLR(vf), reg);
5189 }
ae641bdc 5190
51466239 5191 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5192 }
5193 } else {
5194 if (i < E1000_VLVF_ARRAY_SIZE) {
5195 /* remove vf from the pool */
5196 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5197 /* if pool is empty then remove entry from vfta */
5198 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5199 reg = 0;
5200 igb_vfta_set(hw, vid, false);
5201 }
5202 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5203
5204 /* do not modify RLPML for PF devices */
5205 if (vf >= adapter->vfs_allocated_count)
5206 return 0;
5207
5208 adapter->vf_data[vf].vlans_enabled--;
5209 if (!adapter->vf_data[vf].vlans_enabled) {
5210 u32 size;
5211 reg = rd32(E1000_VMOLR(vf));
5212 size = reg & E1000_VMOLR_RLPML_MASK;
5213 size -= 4;
5214 reg &= ~E1000_VMOLR_RLPML_MASK;
5215 reg |= size;
5216 wr32(E1000_VMOLR(vf), reg);
5217 }
4ae196df
AD		 5218 }
5219 }
8151d294
WM		 5220 return 0;
5221}
5222
5223static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5224{
5225 struct e1000_hw *hw = &adapter->hw;
5226
5227 if (vid)
5228 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5229 else
5230 wr32(E1000_VMVIR(vf), 0);
5231}
5232
5233static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5234 int vf, u16 vlan, u8 qos)
5235{
5236 int err = 0;
5237 struct igb_adapter *adapter = netdev_priv(netdev);
5238
5239 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5240 return -EINVAL;
5241 if (vlan || qos) {
5242 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5243 if (err)
5244 goto out;
5245 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5246 igb_set_vmolr(adapter, vf, !vlan);
5247 adapter->vf_data[vf].pf_vlan = vlan;
5248 adapter->vf_data[vf].pf_qos = qos;
5249 dev_info(&adapter->pdev->dev,
5250 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5251 if (test_bit(__IGB_DOWN, &adapter->state)) {
5252 dev_warn(&adapter->pdev->dev,
5253 "The VF VLAN has been set,"
5254 " but the PF device is not up.\n");
5255 dev_warn(&adapter->pdev->dev,
5256 "Bring the PF device up before"
5257 " attempting to use the VF device.\n");
5258 }
5259 } else {
5260 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5261 false, vf);
5262 igb_set_vmvir(adapter, vlan, vf);
5263 igb_set_vmolr(adapter, vf, true);
5264 adapter->vf_data[vf].pf_vlan = 0;
5265 adapter->vf_data[vf].pf_qos = 0;
5266 }
5267out:
5268 return err;
4ae196df
AD		 5269}
5270
5271static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5272{
5273 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5274 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5275
5276 return igb_vlvf_set(adapter, vid, add, vf);
5277}
5278
f2ca0dbe 5279static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5280{
8fa7e0f7
GR		 5281 /* clear flags - except flag that indicates PF has set the MAC */
5282 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5283 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5284
5285 /* reset offloads to defaults */
8151d294 5286 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5287
5288 /* reset vlans for device */
5289 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5290 if (adapter->vf_data[vf].pf_vlan)
5291 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5292 adapter->vf_data[vf].pf_vlan,
5293 adapter->vf_data[vf].pf_qos);
5294 else
5295 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5296
5297 /* reset multicast table array for vf */
5298 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5299
5300 /* Flush and reset the mta with the new values */
ff41f8dc 5301 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5302}
5303
f2ca0dbe
AD		 5304static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5305{
5306 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5307
5308 /* generate a new mac address as we were hotplug removed/added */
8151d294 5309 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5310 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5311
5312 /* process remaining reset events */
5313 igb_vf_reset(adapter, vf);
5314}
5315
5316static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5317{
5318 struct e1000_hw *hw = &adapter->hw;
5319 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5320 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5321 u32 reg, msgbuf[3];
5322 u8 *addr = (u8 *)(&msgbuf[1]);
5323
5324 /* process all the same items cleared in a function level reset */
f2ca0dbe 5325 igb_vf_reset(adapter, vf);
4ae196df
AD		 5326
5327 /* set vf mac address */
26ad9178 5328 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5329
5330 /* enable transmit and receive for vf */
5331 reg = rd32(E1000_VFTE);
5332 wr32(E1000_VFTE, reg | (1 << vf));
5333 reg = rd32(E1000_VFRE);
5334 wr32(E1000_VFRE, reg | (1 << vf));
5335
8fa7e0f7 5336 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5337
5338 /* reply to reset with ack and vf mac address */
5339 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5340 memcpy(addr, vf_mac, 6);
5341 igb_write_mbx(hw, msgbuf, 3, vf);
5342}
5343
5344static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5345{
de42edde
GR		 5346 /*
5347 * The VF MAC Address is stored in a packed array of bytes
5348 * starting at the second 32 bit word of the msg array
5349 */
f2ca0dbe
AD		 5350 unsigned char *addr = (char *)&msg[1];
5351 int err = -1;
4ae196df 5352
f2ca0dbe
AD		 5353 if (is_valid_ether_addr(addr))
5354 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5355
f2ca0dbe 5356 return err;
4ae196df
AD		 5357}
5358
5359static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5360{
5361 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5362 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5363 u32 msg = E1000_VT_MSGTYPE_NACK;
5364
5365 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5366 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5367 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5368 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5369 vf_data->last_nack = jiffies;
4ae196df
AD		 5370 }
5371}
5372
f2ca0dbe 5373static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5374{
f2ca0dbe
AD		 5375 struct pci_dev *pdev = adapter->pdev;
5376 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5377 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5378 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5379 s32 retval;
5380
f2ca0dbe 5381 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5382
fef45f4c
AD		 5383 if (retval) {
5384 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5385 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5386 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5387 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5388 return;
5389 goto out;
5390 }
4ae196df
AD		 5391
5392 /* this is a message we already processed, do nothing */
5393 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5394 return;
4ae196df
AD		 5395
5396 /*
5397 * until the vf completes a reset it should not be
5398 * allowed to start any configuration.
5399 */
5400
5401 if (msgbuf[0] == E1000_VF_RESET) {
5402 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5403 return;
4ae196df
AD		 5404 }
5405
f2ca0dbe 5406 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5407 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5408 return;
5409 retval = -1;
5410 goto out;
4ae196df
AD		 5411 }
5412
5413 switch ((msgbuf[0] & 0xFFFF)) {
5414 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5415 retval = -EINVAL;
5416 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5417 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5418 else
5419 dev_warn(&pdev->dev,
5420 "VF %d attempted to override administratively "
5421 "set MAC address\nReload the VF driver to "
5422 "resume operations\n", vf);
4ae196df 5423 break;
7d5753f0
AD		 5424 case E1000_VF_SET_PROMISC:
5425 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5426 break;
4ae196df
AD		 5427 case E1000_VF_SET_MULTICAST:
5428 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5429 break;
5430 case E1000_VF_SET_LPE:
5431 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5432 break;
5433 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5434 retval = -1;
5435 if (vf_data->pf_vlan)
5436 dev_warn(&pdev->dev,
5437 "VF %d attempted to override administratively "
5438 "set VLAN tag\nReload the VF driver to "
5439 "resume operations\n", vf);
8151d294
WM		 5440 else
5441 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5442 break;
5443 default:
090b1795 5444 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5445 retval = -1;
5446 break;
5447 }
5448
fef45f4c
AD		 5449 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5450out:
4ae196df
AD		 5451 /* notify the VF of the results of what it sent us */
5452 if (retval)
5453 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5454 else
5455 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5456
4ae196df 5457 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5458}
4ae196df 5459
f2ca0dbe
AD		 5460static void igb_msg_task(struct igb_adapter *adapter)
5461{
5462 struct e1000_hw *hw = &adapter->hw;
5463 u32 vf;
5464
5465 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5466 /* process any reset requests */
5467 if (!igb_check_for_rst(hw, vf))
5468 igb_vf_reset_event(adapter, vf);
5469
5470 /* process any messages pending */
5471 if (!igb_check_for_msg(hw, vf))
5472 igb_rcv_msg_from_vf(adapter, vf);
5473
5474 /* process any acks */
5475 if (!igb_check_for_ack(hw, vf))
5476 igb_rcv_ack_from_vf(adapter, vf);
5477 }
4ae196df
AD		 5478}
5479
68d480c4
AD		 5480/**
5481 * igb_set_uta - Set unicast filter table address
5482 * @adapter: board private structure
5483 *
5484 * The unicast table address is a register array of 32-bit registers.
5485 * The table is meant to be used in a way similar to how the MTA is used
5486 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5487 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5488 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5489 **/
5490static void igb_set_uta(struct igb_adapter *adapter)
5491{
5492 struct e1000_hw *hw = &adapter->hw;
5493 int i;
5494
5495 /* The UTA table only exists on 82576 hardware and newer */
5496 if (hw->mac.type < e1000_82576)
5497 return;
5498
5499 /* we only need to do this if VMDq is enabled */
5500 if (!adapter->vfs_allocated_count)
5501 return;
5502
5503 for (i = 0; i < hw->mac.uta_reg_count; i++)
5504 array_wr32(E1000_UTA, i, ~0);
5505}
5506
9d5c8243
AK		 5507/**
5508 * igb_intr_msi - Interrupt Handler
5509 * @irq: interrupt number
5510 * @data: pointer to a network interface device structure
5511 **/
5512static irqreturn_t igb_intr_msi(int irq, void *data)
5513{
047e0030
AD		 5514 struct igb_adapter *adapter = data;
5515 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5516 struct e1000_hw *hw = &adapter->hw;
5517 /* read ICR disables interrupts using IAM */
5518 u32 icr = rd32(E1000_ICR);
5519
047e0030 5520 igb_write_itr(q_vector);
9d5c8243 5521
7f081d40
AD		 5522 if (icr & E1000_ICR_DRSTA)
5523 schedule_work(&adapter->reset_task);
5524
047e0030 5525 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5526 /* HW is reporting DMA is out of sync */
5527 adapter->stats.doosync++;
5528 }
5529
9d5c8243
AK		 5530 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5531 hw->mac.get_link_status = 1;
5532 if (!test_bit(__IGB_DOWN, &adapter->state))
5533 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5534 }
5535
1f6e8178
MV		 5536#ifdef CONFIG_IGB_PTP
5537 if (icr & E1000_ICR_TS) {
5538 u32 tsicr = rd32(E1000_TSICR);
5539
5540 if (tsicr & E1000_TSICR_TXTS) {
5541 /* acknowledge the interrupt */
5542 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5543 /* retrieve hardware timestamp */
5544 schedule_work(&adapter->ptp_tx_work);
5545 }
5546 }
5547#endif /* CONFIG_IGB_PTP */
5548
047e0030 5549 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5550
5551 return IRQ_HANDLED;
5552}
5553
5554/**
4a3c6433 5555 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5556 * @irq: interrupt number
5557 * @data: pointer to a network interface device structure
5558 **/
5559static irqreturn_t igb_intr(int irq, void *data)
5560{
047e0030
AD		 5561 struct igb_adapter *adapter = data;
5562 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5563 struct e1000_hw *hw = &adapter->hw;
5564 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5565 * need for the IMC write */
5566 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5567
5568 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5569 * not set, then the adapter didn't send an interrupt */
5570 if (!(icr & E1000_ICR_INT_ASSERTED))
5571 return IRQ_NONE;
5572
0ba82994
AD		 5573 igb_write_itr(q_vector);
5574
7f081d40
AD		 5575 if (icr & E1000_ICR_DRSTA)
5576 schedule_work(&adapter->reset_task);
5577
047e0030 5578 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5579 /* HW is reporting DMA is out of sync */
5580 adapter->stats.doosync++;
5581 }
5582
9d5c8243
AK		 5583 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5584 hw->mac.get_link_status = 1;
5585 /* guard against interrupt when we're going down */
5586 if (!test_bit(__IGB_DOWN, &adapter->state))
5587 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5588 }
5589
1f6e8178
MV		 5590#ifdef CONFIG_IGB_PTP
5591 if (icr & E1000_ICR_TS) {
5592 u32 tsicr = rd32(E1000_TSICR);
5593
5594 if (tsicr & E1000_TSICR_TXTS) {
5595 /* acknowledge the interrupt */
5596 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5597 /* retrieve hardware timestamp */
5598 schedule_work(&adapter->ptp_tx_work);
5599 }
5600 }
5601#endif /* CONFIG_IGB_PTP */
5602
047e0030 5603 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5604
5605 return IRQ_HANDLED;
5606}
5607
c50b52a0 5608static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5609{
047e0030 5610 struct igb_adapter *adapter = q_vector->adapter;
46544258 5611 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5612
0ba82994
AD		 5613 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5614 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5615 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5616 igb_set_itr(q_vector);
46544258 5617 else
047e0030 5618 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5619 }
5620
46544258
AD		 5621 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5622 if (adapter->msix_entries)
047e0030 5623 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5624 else
5625 igb_irq_enable(adapter);
5626 }
9d5c8243
AK		 5627}
5628
46544258
AD		 5629/**
5630 * igb_poll - NAPI Rx polling callback
5631 * @napi: napi polling structure
5632 * @budget: count of how many packets we should handle
5633 **/
5634static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5635{
047e0030
AD		 5636 struct igb_q_vector *q_vector = container_of(napi,
5637 struct igb_q_vector,
5638 napi);
16eb8815 5639 bool clean_complete = true;
9d5c8243 5640
421e02f0 5641#ifdef CONFIG_IGB_DCA
047e0030
AD		 5642 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5643 igb_update_dca(q_vector);
fe4506b6 5644#endif
0ba82994 5645 if (q_vector->tx.ring)
13fde97a 5646 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5647
0ba82994 5648 if (q_vector->rx.ring)
cd392f5c 5649 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5650
16eb8815
AD		 5651 /* If all work not completed, return budget and keep polling */
5652 if (!clean_complete)
5653 return budget;
46544258 5654
9d5c8243 5655 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5656 napi_complete(napi);
5657 igb_ring_irq_enable(q_vector);
9d5c8243 5658
16eb8815 5659 return 0;
9d5c8243 5660}
6d8126f9 5661
9d5c8243
AK		 5662/**
5663 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5664 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5665 *
9d5c8243
AK		 5666 * returns true if ring is completely cleaned
5667 **/
047e0030 5668static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5669{
047e0030 5670 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5671 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5672 struct igb_tx_buffer *tx_buffer;
f4128785 5673 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5674 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5675 unsigned int budget = q_vector->tx.work_limit;
8542db05 5676 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5677
13fde97a
AD		 5678 if (test_bit(__IGB_DOWN, &adapter->state))
5679 return true;
0e014cb1 5680
06034649 5681 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5682 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5683 i -= tx_ring->count;
9d5c8243 5684
f4128785
AD		 5685 do {
5686 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5687
5688 /* if next_to_watch is not set then there is no work pending */
5689 if (!eop_desc)
5690 break;
13fde97a 5691
f4128785
AD		 5692 /* prevent any other reads prior to eop_desc */
5693 rmb();
5694
13fde97a
AD		 5695 /* if DD is not set pending work has not been completed */
5696 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5697 break;
5698
8542db05
AD		 5699 /* clear next_to_watch to prevent false hangs */
5700 tx_buffer->next_to_watch = NULL;
9d5c8243 5701
ebe42d16
AD		 5702 /* update the statistics for this packet */
5703 total_bytes += tx_buffer->bytecount;
5704 total_packets += tx_buffer->gso_segs;
13fde97a 5705
ebe42d16
AD		 5706 /* free the skb */
5707 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5708
ebe42d16
AD		 5709 /* unmap skb header data */
5710 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5711 dma_unmap_addr(tx_buffer, dma),
5712 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5713 DMA_TO_DEVICE);
5714
c9f14bf3
AD		 5715 /* clear tx_buffer data */
5716 tx_buffer->skb = NULL;
5717 dma_unmap_len_set(tx_buffer, len, 0);
5718
ebe42d16
AD		 5719 /* clear last DMA location and unmap remaining buffers */
5720 while (tx_desc != eop_desc) {
13fde97a
AD		 5721 tx_buffer++;
5722 tx_desc++;
9d5c8243 5723 i++;
8542db05
AD		 5724 if (unlikely(!i)) {
5725 i -= tx_ring->count;
06034649 5726 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5727 tx_desc = IGB_TX_DESC(tx_ring, 0);
5728 }
ebe42d16
AD		 5729
5730 /* unmap any remaining paged data */
c9f14bf3 5731 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5732 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5733 dma_unmap_addr(tx_buffer, dma),
5734 dma_unmap_len(tx_buffer, len),
ebe42d16 5735 DMA_TO_DEVICE);
c9f14bf3 5736 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5737 }
5738 }
5739
ebe42d16
AD		 5740 /* move us one more past the eop_desc for start of next pkt */
5741 tx_buffer++;
5742 tx_desc++;
5743 i++;
5744 if (unlikely(!i)) {
5745 i -= tx_ring->count;
5746 tx_buffer = tx_ring->tx_buffer_info;
5747 tx_desc = IGB_TX_DESC(tx_ring, 0);
5748 }
f4128785
AD		 5749
5750 /* issue prefetch for next Tx descriptor */
5751 prefetch(tx_desc);
5752
5753 /* update budget accounting */
5754 budget--;
5755 } while (likely(budget));
0e014cb1 5756
bdbc0631
ED		 5757 netdev_tx_completed_queue(txring_txq(tx_ring),
5758 total_packets, total_bytes);
8542db05 5759 i += tx_ring->count;
9d5c8243 5760 tx_ring->next_to_clean = i;
13fde97a
AD		 5761 u64_stats_update_begin(&tx_ring->tx_syncp);
5762 tx_ring->tx_stats.bytes += total_bytes;
5763 tx_ring->tx_stats.packets += total_packets;
5764 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 5765 q_vector->tx.total_bytes += total_bytes;
5766 q_vector->tx.total_packets += total_packets;
9d5c8243 5767
6d095fa8 5768 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 5769 struct e1000_hw *hw = &adapter->hw;
12dcd86b 5770
9d5c8243
AK		 5771 /* Detect a transmit hang in hardware, this serializes the
5772 * check with the clearing of time_stamp and movement of i */
6d095fa8 5773 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 5774 if (tx_buffer->next_to_watch &&
8542db05 5775 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 5776 (adapter->tx_timeout_factor * HZ)) &&
5777 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5778
9d5c8243 5779 /* detected Tx unit hang */
59d71989 5780 dev_err(tx_ring->dev,
9d5c8243 5781 "Detected Tx Unit Hang\n"
2d064c06 5782 " Tx Queue <%d>\n"
9d5c8243
AK		 5783 " TDH <%x>\n"
5784 " TDT <%x>\n"
5785 " next_to_use <%x>\n"
5786 " next_to_clean <%x>\n"
9d5c8243
AK		 5787 "buffer_info[next_to_clean]\n"
5788 " time_stamp <%lx>\n"
8542db05 5789 " next_to_watch <%p>\n"
9d5c8243
AK		 5790 " jiffies <%lx>\n"
5791 " desc.status <%x>\n",
2d064c06 5792 tx_ring->queue_index,
238ac817 5793 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5794 readl(tx_ring->tail),
9d5c8243
AK		 5795 tx_ring->next_to_use,
5796 tx_ring->next_to_clean,
8542db05 5797 tx_buffer->time_stamp,
f4128785 5798 tx_buffer->next_to_watch,
9d5c8243 5799 jiffies,
f4128785 5800 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 5801 netif_stop_subqueue(tx_ring->netdev,
5802 tx_ring->queue_index);
5803
5804 /* we are about to reset, no point in enabling stuff */
5805 return true;
9d5c8243
AK		 5806 }
5807 }
13fde97a
AD		 5808
5809 if (unlikely(total_packets &&
5810 netif_carrier_ok(tx_ring->netdev) &&
5811 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5812 /* Make sure that anybody stopping the queue after this
5813 * sees the new next_to_clean.
5814 */
5815 smp_mb();
5816 if (__netif_subqueue_stopped(tx_ring->netdev,
5817 tx_ring->queue_index) &&
5818 !(test_bit(__IGB_DOWN, &adapter->state))) {
5819 netif_wake_subqueue(tx_ring->netdev,
5820 tx_ring->queue_index);
5821
5822 u64_stats_update_begin(&tx_ring->tx_syncp);
5823 tx_ring->tx_stats.restart_queue++;
5824 u64_stats_update_end(&tx_ring->tx_syncp);
5825 }
5826 }
5827
5828 return !!budget;
9d5c8243
AK		 5829}
5830
cd392f5c 5831static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 5832 union e1000_adv_rx_desc *rx_desc,
5833 struct sk_buff *skb)
9d5c8243 5834{
bc8acf2c 5835 skb_checksum_none_assert(skb);
9d5c8243 5836
294e7d78 5837 /* Ignore Checksum bit is set */
3ceb90fd 5838 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 5839 return;
5840
5841 /* Rx checksum disabled via ethtool */
5842 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 5843 return;
85ad76b2 5844
9d5c8243 5845 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 5846 if (igb_test_staterr(rx_desc,
5847 E1000_RXDEXT_STATERR_TCPE |
5848 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 5849 /*
5850 * work around errata with sctp packets where the TCPE aka
5851 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
5852 * packets, (aka let the stack check the crc32c)
5853 */
866cff06
AD		 5854 if (!((skb->len == 60) &&
5855 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 5856 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 5857 ring->rx_stats.csum_err++;
12dcd86b
ED		 5858 u64_stats_update_end(&ring->rx_syncp);
5859 }
9d5c8243 5860 /* let the stack verify checksum errors */
9d5c8243
AK		 5861 return;
5862 }
5863 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 5864 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
5865 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 5866 skb->ip_summed = CHECKSUM_UNNECESSARY;
5867
3ceb90fd
AD		 5868 dev_dbg(ring->dev, "cksum success: bits %08X\n",
5869 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 5870}
5871
077887c3
AD		 5872static inline void igb_rx_hash(struct igb_ring *ring,
5873 union e1000_adv_rx_desc *rx_desc,
5874 struct sk_buff *skb)
5875{
5876 if (ring->netdev->features & NETIF_F_RXHASH)
5877 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
5878}
5879
8be10e91
AD		 5880static void igb_rx_vlan(struct igb_ring *ring,
5881 union e1000_adv_rx_desc *rx_desc,
5882 struct sk_buff *skb)
5883{
5884 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
5885 u16 vid;
5886 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
5887 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags))
5888 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
5889 else
5890 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
5891
5892 __vlan_hwaccel_put_tag(skb, vid);
5893 }
5894}
5895
1a1c225b
AD		 5896/**
5897 * igb_get_headlen - determine size of header for LRO/GRO
5898 * @data: pointer to the start of the headers
5899 * @max_len: total length of section to find headers in
5900 *
5901 * This function is meant to determine the length of headers that will
5902 * be recognized by hardware for LRO, and GRO offloads. The main
5903 * motivation of doing this is to only perform one pull for IPv4 TCP
5904 * packets so that we can do basic things like calculating the gso_size
5905 * based on the average data per packet.
5906 **/
5907static unsigned int igb_get_headlen(unsigned char *data,
5908 unsigned int max_len)
5909{
5910 union {
5911 unsigned char *network;
5912 /* l2 headers */
5913 struct ethhdr *eth;
5914 struct vlan_hdr *vlan;
5915 /* l3 headers */
5916 struct iphdr *ipv4;
5917 struct ipv6hdr *ipv6;
5918 } hdr;
5919 __be16 protocol;
5920 u8 nexthdr = 0; /* default to not TCP */
5921 u8 hlen;
5922
5923 /* this should never happen, but better safe than sorry */
5924 if (max_len < ETH_HLEN)
5925 return max_len;
5926
5927 /* initialize network frame pointer */
5928 hdr.network = data;
5929
5930 /* set first protocol and move network header forward */
5931 protocol = hdr.eth->h_proto;
5932 hdr.network += ETH_HLEN;
5933
5934 /* handle any vlan tag if present */
5935 if (protocol == __constant_htons(ETH_P_8021Q)) {
5936 if ((hdr.network - data) > (max_len - VLAN_HLEN))
5937 return max_len;
5938
5939 protocol = hdr.vlan->h_vlan_encapsulated_proto;
5940 hdr.network += VLAN_HLEN;
5941 }
5942
5943 /* handle L3 protocols */
5944 if (protocol == __constant_htons(ETH_P_IP)) {
5945 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
5946 return max_len;
5947
5948 /* access ihl as a u8 to avoid unaligned access on ia64 */
5949 hlen = (hdr.network[0] & 0x0F) << 2;
5950
5951 /* verify hlen meets minimum size requirements */
5952 if (hlen < sizeof(struct iphdr))
5953 return hdr.network - data;
5954
5955 /* record next protocol */
5956 nexthdr = hdr.ipv4->protocol;
5957 hdr.network += hlen;
5958 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
5959 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
5960 return max_len;
5961
5962 /* record next protocol */
5963 nexthdr = hdr.ipv6->nexthdr;
5964 hdr.network += sizeof(struct ipv6hdr);
5965 } else {
5966 return hdr.network - data;
5967 }
5968
5969 /* finally sort out TCP */
5970 if (nexthdr == IPPROTO_TCP) {
5971 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
5972 return max_len;
5973
5974 /* access doff as a u8 to avoid unaligned access on ia64 */
5975 hlen = (hdr.network[12] & 0xF0) >> 2;
5976
5977 /* verify hlen meets minimum size requirements */
5978 if (hlen < sizeof(struct tcphdr))
5979 return hdr.network - data;
5980
5981 hdr.network += hlen;
5982 } else if (nexthdr == IPPROTO_UDP) {
5983 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
5984 return max_len;
5985
5986 hdr.network += sizeof(struct udphdr);
5987 }
5988
5989 /*
5990 * If everything has gone correctly hdr.network should be the
5991 * data section of the packet and will be the end of the header.
5992 * If not then it probably represents the end of the last recognized
5993 * header.
5994 */
5995 if ((hdr.network - data) < max_len)
5996 return hdr.network - data;
5997 else
5998 return max_len;
5999}
6000
6001/**
6002 * igb_pull_tail - igb specific version of skb_pull_tail
6003 * @rx_ring: rx descriptor ring packet is being transacted on
6004 * @skb: pointer to current skb being adjusted
6005 *
6006 * This function is an igb specific version of __pskb_pull_tail. The
6007 * main difference between this version and the original function is that
6008 * this function can make several assumptions about the state of things
6009 * that allow for significant optimizations versus the standard function.
6010 * As a result we can do things like drop a frag and maintain an accurate
6011 * truesize for the skb.
6012 */
6013static void igb_pull_tail(struct igb_ring *rx_ring,
6014 union e1000_adv_rx_desc *rx_desc,
6015 struct sk_buff *skb)
2d94d8ab 6016{
1a1c225b
AD		 6017 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6018 unsigned char *va;
6019 unsigned int pull_len;
6020
6021 /*
6022 * it is valid to use page_address instead of kmap since we are
6023 * working with pages allocated out of the lomem pool per
6024 * alloc_page(GFP_ATOMIC)
2d94d8ab 6025 */
1a1c225b
AD		 6026 va = skb_frag_address(frag);
6027
6028#ifdef CONFIG_IGB_PTP
6029 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6030 /* retrieve timestamp from buffer */
6031 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6032
6033 /* update pointers to remove timestamp header */
6034 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6035 frag->page_offset += IGB_TS_HDR_LEN;
6036 skb->data_len -= IGB_TS_HDR_LEN;
6037 skb->len -= IGB_TS_HDR_LEN;
6038
6039 /* move va to start of packet data */
6040 va += IGB_TS_HDR_LEN;
6041 }
6042
6043#endif
6044 /*
6045 * we need the header to contain the greater of either ETH_HLEN or
6046 * 60 bytes if the skb->len is less than 60 for skb_pad.
6047 */
6048 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6049
6050 /* align pull length to size of long to optimize memcpy performance */
6051 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6052
6053 /* update all of the pointers */
6054 skb_frag_size_sub(frag, pull_len);
6055 frag->page_offset += pull_len;
6056 skb->data_len -= pull_len;
6057 skb->tail += pull_len;
6058}
6059
6060/**
6061 * igb_cleanup_headers - Correct corrupted or empty headers
6062 * @rx_ring: rx descriptor ring packet is being transacted on
6063 * @rx_desc: pointer to the EOP Rx descriptor
6064 * @skb: pointer to current skb being fixed
6065 *
6066 * Address the case where we are pulling data in on pages only
6067 * and as such no data is present in the skb header.
6068 *
6069 * In addition if skb is not at least 60 bytes we need to pad it so that
6070 * it is large enough to qualify as a valid Ethernet frame.
6071 *
6072 * Returns true if an error was encountered and skb was freed.
6073 **/
6074static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6075 union e1000_adv_rx_desc *rx_desc,
6076 struct sk_buff *skb)
6077{
6078
6079 if (unlikely((igb_test_staterr(rx_desc,
6080 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6081 struct net_device *netdev = rx_ring->netdev;
6082 if (!(netdev->features & NETIF_F_RXALL)) {
6083 dev_kfree_skb_any(skb);
6084 return true;
6085 }
6086 }
6087
6088 /* place header in linear portion of buffer */
6089 if (skb_is_nonlinear(skb))
6090 igb_pull_tail(rx_ring, rx_desc, skb);
6091
6092 /* if skb_pad returns an error the skb was freed */
6093 if (unlikely(skb->len < 60)) {
6094 int pad_len = 60 - skb->len;
6095
6096 if (skb_pad(skb, pad_len))
6097 return true;
6098 __skb_put(skb, pad_len);
6099 }
6100
6101 return false;
2d94d8ab
AD		 6102}
6103
cd392f5c 6104static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget)
9d5c8243 6105{
0ba82994 6106 struct igb_ring *rx_ring = q_vector->rx.ring;
16eb8815 6107 union e1000_adv_rx_desc *rx_desc;
1a1c225b 6108 struct sk_buff *skb = rx_ring->skb;
16eb8815 6109 const int current_node = numa_node_id();
9d5c8243 6110 unsigned int total_bytes = 0, total_packets = 0;
16eb8815
AD		 6111 u16 cleaned_count = igb_desc_unused(rx_ring);
6112 u16 i = rx_ring->next_to_clean;
9d5c8243 6113
60136906 6114 rx_desc = IGB_RX_DESC(rx_ring, i);
9d5c8243 6115
3ceb90fd 6116 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
06034649 6117 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
1a1c225b 6118 struct page *page;
16eb8815 6119 union e1000_adv_rx_desc *next_rxd;
9d5c8243 6120
69d3ca53
AD		 6121 i++;
6122 if (i == rx_ring->count)
6123 i = 0;
42d0781a 6124
60136906 6125 next_rxd = IGB_RX_DESC(rx_ring, i);
69d3ca53 6126 prefetch(next_rxd);
9d5c8243 6127
16eb8815
AD		 6128 /*
6129 * This memory barrier is needed to keep us from reading
6130 * any other fields out of the rx_desc until we know the
6131 * RXD_STAT_DD bit is set
6132 */
6133 rmb();
9d5c8243 6134
1a1c225b
AD		 6135 page = buffer_info->page;
6136 prefetchw(page);
bf36c1a0 6137
1a1c225b
AD		 6138 if (likely(!skb)) {
6139 void *page_addr = page_address(page) +
6140 buffer_info->page_offset;
bf36c1a0 6141
1a1c225b
AD		 6142 /* prefetch first cache line of first page */
6143 prefetch(page_addr);
6144#if L1_CACHE_BYTES < 128
6145 prefetch(page_addr + L1_CACHE_BYTES);
6146#endif
16eb8815 6147
1a1c225b
AD		 6148 /* allocate a skb to store the frags */
6149 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6150 IGB_RX_HDR_LEN);
6151 if (unlikely(!skb)) {
6152 rx_ring->rx_stats.alloc_failed++;
6153 break;
6154 }
9d5c8243 6155
1a1c225b
AD		 6156 /*
6157 * we will be copying header into skb->data in
6158 * pskb_may_pull so it is in our interest to prefetch
6159 * it now to avoid a possible cache miss
6160 */
6161 prefetchw(skb->data);
9d5c8243 6162 }
9d5c8243 6163
1a1c225b
AD		 6164 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6165 buffer_info->page_offset,
6166 le16_to_cpu(rx_desc->wb.upper.length),
6167 PAGE_SIZE / 2);
44390ca6 6168
1a1c225b
AD		 6169 if ((page_count(buffer_info->page) != 1) ||
6170 (page_to_nid(buffer_info->page) != current_node))
6171 buffer_info->page = NULL;
6172 else
6173 get_page(buffer_info->page);
6174
6175 dma_unmap_page(rx_ring->dev, buffer_info->dma,
6176 PAGE_SIZE / 2, DMA_FROM_DEVICE);
6177 buffer_info->dma = 0;
6178
6179 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))
9d5c8243 6180 goto next_desc;
1a1c225b
AD		 6181
6182 /* verify the packet layout is correct */
6183 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6184 skb = NULL;
6185 continue;
9d5c8243 6186 }
9d5c8243 6187
7ebae817 6188#ifdef CONFIG_IGB_PTP
a79f4f88 6189 igb_ptp_rx_hwtstamp(q_vector, rx_desc, skb);
3c89f6d0 6190#endif /* CONFIG_IGB_PTP */
077887c3 6191 igb_rx_hash(rx_ring, rx_desc, skb);
3ceb90fd 6192 igb_rx_checksum(rx_ring, rx_desc, skb);
8be10e91 6193 igb_rx_vlan(rx_ring, rx_desc, skb);
3ceb90fd
AD		 6194
6195 total_bytes += skb->len;
6196 total_packets++;
6197
1a1c225b 6198 skb_record_rx_queue(skb, rx_ring->queue_index);
3ceb90fd
AD		 6199 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6200
b2cb09b1 6201 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6202
1a1c225b
AD		 6203 /* reset skb pointer */
6204 skb = NULL;
6205
16eb8815 6206 budget--;
9d5c8243 6207next_desc:
16eb8815
AD		 6208 if (!budget)
6209 break;
6210
6211 cleaned_count++;
9d5c8243
AK		 6212 /* return some buffers to hardware, one at a time is too slow */
6213 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
cd392f5c 6214 igb_alloc_rx_buffers(rx_ring, cleaned_count);
9d5c8243
AK		 6215 cleaned_count = 0;
6216 }
6217
6218 /* use prefetched values */
6219 rx_desc = next_rxd;
9d5c8243 6220 }
bf36c1a0 6221
1a1c225b
AD		 6222 /* place incomplete frames back on ring for completion */
6223 rx_ring->skb = skb;
6224
9d5c8243 6225 rx_ring->next_to_clean = i;
12dcd86b 6226 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6227 rx_ring->rx_stats.packets += total_packets;
6228 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6229 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6230 q_vector->rx.total_packets += total_packets;
6231 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6232
6233 if (cleaned_count)
cd392f5c 6234 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6235
16eb8815 6236 return !!budget;
9d5c8243
AK		 6237}
6238
c023cd88 6239static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6240 struct igb_rx_buffer *bi)
c023cd88
AD		 6241{
6242 struct page *page = bi->page;
1a1c225b 6243 dma_addr_t dma = bi->dma;
c023cd88
AD		 6244 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
6245
1a1c225b 6246 if (dma)
c023cd88
AD		 6247 return true;
6248
6249 if (!page) {
1a1c225b 6250 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
c023cd88
AD		 6251 if (unlikely(!page)) {
6252 rx_ring->rx_stats.alloc_failed++;
6253 return false;
6254 }
1a1c225b 6255 bi->page = page;
c023cd88
AD		 6256 }
6257
1a1c225b
AD		 6258 dma = dma_map_page(rx_ring->dev, page,
6259 page_offset, PAGE_SIZE / 2,
6260 DMA_FROM_DEVICE);
c023cd88 6261
1a1c225b 6262 if (dma_mapping_error(rx_ring->dev, dma)) {
c023cd88
AD		 6263 rx_ring->rx_stats.alloc_failed++;
6264 return false;
6265 }
6266
1a1c225b 6267 bi->dma = dma;
c023cd88 6268 bi->page_offset = page_offset;
1a1c225b 6269
c023cd88
AD		 6270 return true;
6271}
6272
9d5c8243 6273/**
cd392f5c 6274 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6275 * @adapter: address of board private structure
6276 **/
cd392f5c 6277void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6278{
9d5c8243 6279 union e1000_adv_rx_desc *rx_desc;
06034649 6280 struct igb_rx_buffer *bi;
c023cd88 6281 u16 i = rx_ring->next_to_use;
9d5c8243 6282
60136906 6283 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6284 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6285 i -= rx_ring->count;
9d5c8243
AK		 6286
6287 while (cleaned_count--) {
1a1c225b 6288 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6289 break;
9d5c8243 6290
c023cd88
AD		 6291 /* Refresh the desc even if buffer_addrs didn't change
6292 * because each write-back erases this info. */
1a1c225b 6293 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9d5c8243 6294
c023cd88
AD		 6295 rx_desc++;
6296 bi++;
9d5c8243 6297 i++;
c023cd88 6298 if (unlikely(!i)) {
60136906 6299 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6300 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6301 i -= rx_ring->count;
6302 }
6303
6304 /* clear the hdr_addr for the next_to_use descriptor */
6305 rx_desc->read.hdr_addr = 0;
9d5c8243
AK		 6306 }
6307
c023cd88
AD		 6308 i += rx_ring->count;
6309
9d5c8243
AK		 6310 if (rx_ring->next_to_use != i) {
6311 rx_ring->next_to_use = i;
9d5c8243
AK		 6312
6313 /* Force memory writes to complete before letting h/w
6314 * know there are new descriptors to fetch. (Only
6315 * applicable for weak-ordered memory model archs,
6316 * such as IA-64). */
6317 wmb();
fce99e34 6318 writel(i, rx_ring->tail);
9d5c8243
AK		 6319 }
6320}
6321
6322/**
6323 * igb_mii_ioctl -
6324 * @netdev:
6325 * @ifreq:
6326 * @cmd:
6327 **/
6328static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6329{
6330 struct igb_adapter *adapter = netdev_priv(netdev);
6331 struct mii_ioctl_data *data = if_mii(ifr);
6332
6333 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6334 return -EOPNOTSUPP;
6335
6336 switch (cmd) {
6337 case SIOCGMIIPHY:
6338 data->phy_id = adapter->hw.phy.addr;
6339 break;
6340 case SIOCGMIIREG:
f5f4cf08
AD		 6341 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6342 &data->val_out))
9d5c8243
AK		 6343 return -EIO;
6344 break;
6345 case SIOCSMIIREG:
6346 default:
6347 return -EOPNOTSUPP;
6348 }
6349 return 0;
6350}
6351
6352/**
6353 * igb_ioctl -
6354 * @netdev:
6355 * @ifreq:
6356 * @cmd:
6357 **/
6358static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6359{
6360 switch (cmd) {
6361 case SIOCGMIIPHY:
6362 case SIOCGMIIREG:
6363 case SIOCSMIIREG:
6364 return igb_mii_ioctl(netdev, ifr, cmd);
3c89f6d0 6365#ifdef CONFIG_IGB_PTP
c6cb090b 6366 case SIOCSHWTSTAMP:
a79f4f88 6367 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
3c89f6d0 6368#endif /* CONFIG_IGB_PTP */
9d5c8243
AK		 6369 default:
6370 return -EOPNOTSUPP;
6371 }
6372}
6373
009bc06e
AD		 6374s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6375{
6376 struct igb_adapter *adapter = hw->back;
009bc06e 6377
23d028cc 6378 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6379 return -E1000_ERR_CONFIG;
6380
009bc06e
AD		 6381 return 0;
6382}
6383
6384s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6385{
6386 struct igb_adapter *adapter = hw->back;
009bc06e 6387
23d028cc 6388 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6389 return -E1000_ERR_CONFIG;
6390
009bc06e
AD		 6391 return 0;
6392}
6393
c8f44aff 6394static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6395{
6396 struct igb_adapter *adapter = netdev_priv(netdev);
6397 struct e1000_hw *hw = &adapter->hw;
6398 u32 ctrl, rctl;
5faf030c 6399 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6400
5faf030c 6401 if (enable) {
9d5c8243
AK		 6402 /* enable VLAN tag insert/strip */
6403 ctrl = rd32(E1000_CTRL);
6404 ctrl |= E1000_CTRL_VME;
6405 wr32(E1000_CTRL, ctrl);
6406
51466239 6407 /* Disable CFI check */
9d5c8243 6408 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6409 rctl &= ~E1000_RCTL_CFIEN;
6410 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6411 } else {
6412 /* disable VLAN tag insert/strip */
6413 ctrl = rd32(E1000_CTRL);
6414 ctrl &= ~E1000_CTRL_VME;
6415 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6416 }
6417
e1739522 6418 igb_rlpml_set(adapter);
9d5c8243
AK		 6419}
6420
8e586137 6421static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6422{
6423 struct igb_adapter *adapter = netdev_priv(netdev);
6424 struct e1000_hw *hw = &adapter->hw;
4ae196df 6425 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6426
51466239
AD		 6427 /* attempt to add filter to vlvf array */
6428 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6429
51466239
AD		 6430 /* add the filter since PF can receive vlans w/o entry in vlvf */
6431 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6432
6433 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6434
6435 return 0;
9d5c8243
AK		 6436}
6437
8e586137 6438static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6439{
6440 struct igb_adapter *adapter = netdev_priv(netdev);
6441 struct e1000_hw *hw = &adapter->hw;
4ae196df 6442 int pf_id = adapter->vfs_allocated_count;
51466239 6443 s32 err;
9d5c8243 6444
51466239
AD		 6445 /* remove vlan from VLVF table array */
6446 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6447
51466239
AD		 6448 /* if vid was not present in VLVF just remove it from table */
6449 if (err)
4ae196df 6450 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6451
6452 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6453
6454 return 0;
9d5c8243
AK		 6455}
6456
6457static void igb_restore_vlan(struct igb_adapter *adapter)
6458{
b2cb09b1 6459 u16 vid;
9d5c8243 6460
5faf030c
AD		 6461 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6462
b2cb09b1
JP		 6463 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6464 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6465}
6466
14ad2513 6467int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6468{
090b1795 6469 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6470 struct e1000_mac_info *mac = &adapter->hw.mac;
6471
6472 mac->autoneg = 0;
6473
14ad2513
DD		 6474 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6475 * for the switch() below to work */
6476 if ((spd & 1) || (dplx & ~1))
6477 goto err_inval;
6478
cd2638a8
CW		 6479 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6480 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6481 spd != SPEED_1000 &&
6482 dplx != DUPLEX_FULL)
6483 goto err_inval;
cd2638a8 6484
14ad2513 6485 switch (spd + dplx) {
9d5c8243
AK		 6486 case SPEED_10 + DUPLEX_HALF:
6487 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6488 break;
6489 case SPEED_10 + DUPLEX_FULL:
6490 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6491 break;
6492 case SPEED_100 + DUPLEX_HALF:
6493 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6494 break;
6495 case SPEED_100 + DUPLEX_FULL:
6496 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6497 break;
6498 case SPEED_1000 + DUPLEX_FULL:
6499 mac->autoneg = 1;
6500 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6501 break;
6502 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6503 default:
14ad2513 6504 goto err_inval;
9d5c8243 6505 }
8376dad0
JB		 6506
6507 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6508 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6509
9d5c8243 6510 return 0;
14ad2513
DD		 6511
6512err_inval:
6513 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6514 return -EINVAL;
9d5c8243
AK		 6515}
6516
749ab2cd
YZ		 6517static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6518 bool runtime)
9d5c8243
AK		 6519{
6520 struct net_device *netdev = pci_get_drvdata(pdev);
6521 struct igb_adapter *adapter = netdev_priv(netdev);
6522 struct e1000_hw *hw = &adapter->hw;
2d064c06 6523 u32 ctrl, rctl, status;
749ab2cd 6524 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6525#ifdef CONFIG_PM
6526 int retval = 0;
6527#endif
6528
6529 netif_device_detach(netdev);
6530
a88f10ec 6531 if (netif_running(netdev))
749ab2cd 6532 __igb_close(netdev, true);
a88f10ec 6533
047e0030 6534 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6535
6536#ifdef CONFIG_PM
6537 retval = pci_save_state(pdev);
6538 if (retval)
6539 return retval;
6540#endif
6541
6542 status = rd32(E1000_STATUS);
6543 if (status & E1000_STATUS_LU)
6544 wufc &= ~E1000_WUFC_LNKC;
6545
6546 if (wufc) {
6547 igb_setup_rctl(adapter);
ff41f8dc 6548 igb_set_rx_mode(netdev);
9d5c8243
AK		 6549
6550 /* turn on all-multi mode if wake on multicast is enabled */
6551 if (wufc & E1000_WUFC_MC) {
6552 rctl = rd32(E1000_RCTL);
6553 rctl |= E1000_RCTL_MPE;
6554 wr32(E1000_RCTL, rctl);
6555 }
6556
6557 ctrl = rd32(E1000_CTRL);
6558 /* advertise wake from D3Cold */
6559 #define E1000_CTRL_ADVD3WUC 0x00100000
6560 /* phy power management enable */
6561 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6562 ctrl |= E1000_CTRL_ADVD3WUC;
6563 wr32(E1000_CTRL, ctrl);
6564
9d5c8243 6565 /* Allow time for pending master requests to run */
330a6d6a 6566 igb_disable_pcie_master(hw);
9d5c8243
AK		 6567
6568 wr32(E1000_WUC, E1000_WUC_PME_EN);
6569 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6570 } else {
6571 wr32(E1000_WUC, 0);
6572 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6573 }
6574
3fe7c4c9
RW		 6575 *enable_wake = wufc || adapter->en_mng_pt;
6576 if (!*enable_wake)
88a268c1
NN		 6577 igb_power_down_link(adapter);
6578 else
6579 igb_power_up_link(adapter);
9d5c8243
AK		 6580
6581 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6582 * would have already happened in close and is redundant. */
6583 igb_release_hw_control(adapter);
6584
6585 pci_disable_device(pdev);
6586
9d5c8243
AK		 6587 return 0;
6588}
6589
6590#ifdef CONFIG_PM
d9dd966d 6591#ifdef CONFIG_PM_SLEEP
749ab2cd 6592static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 6593{
6594 int retval;
6595 bool wake;
749ab2cd 6596 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 6597
749ab2cd 6598 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6599 if (retval)
6600 return retval;
6601
6602 if (wake) {
6603 pci_prepare_to_sleep(pdev);
6604 } else {
6605 pci_wake_from_d3(pdev, false);
6606 pci_set_power_state(pdev, PCI_D3hot);
6607 }
6608
6609 return 0;
6610}
d9dd966d 6611#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 6612
749ab2cd 6613static int igb_resume(struct device *dev)
9d5c8243 6614{
749ab2cd 6615 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 6616 struct net_device *netdev = pci_get_drvdata(pdev);
6617 struct igb_adapter *adapter = netdev_priv(netdev);
6618 struct e1000_hw *hw = &adapter->hw;
6619 u32 err;
6620
6621 pci_set_power_state(pdev, PCI_D0);
6622 pci_restore_state(pdev);
b94f2d77 6623 pci_save_state(pdev);
42bfd33a 6624
aed5dec3 6625 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6626 if (err) {
6627 dev_err(&pdev->dev,
6628 "igb: Cannot enable PCI device from suspend\n");
6629 return err;
6630 }
6631 pci_set_master(pdev);
6632
6633 pci_enable_wake(pdev, PCI_D3hot, 0);
6634 pci_enable_wake(pdev, PCI_D3cold, 0);
6635
cfb8c3aa 6636 if (igb_init_interrupt_scheme(adapter)) {
a88f10ec
AD		 6637 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6638 return -ENOMEM;
9d5c8243
AK		 6639 }
6640
9d5c8243 6641 igb_reset(adapter);
a8564f03
AD		 6642
6643 /* let the f/w know that the h/w is now under the control of the
6644 * driver. */
6645 igb_get_hw_control(adapter);
6646
9d5c8243
AK		 6647 wr32(E1000_WUS, ~0);
6648
749ab2cd
YZ		 6649 if (netdev->flags & IFF_UP) {
6650 err = __igb_open(netdev, true);
a88f10ec
AD		 6651 if (err)
6652 return err;
6653 }
9d5c8243
AK		 6654
6655 netif_device_attach(netdev);
749ab2cd
YZ		 6656 return 0;
6657}
6658
6659#ifdef CONFIG_PM_RUNTIME
6660static int igb_runtime_idle(struct device *dev)
6661{
6662 struct pci_dev *pdev = to_pci_dev(dev);
6663 struct net_device *netdev = pci_get_drvdata(pdev);
6664 struct igb_adapter *adapter = netdev_priv(netdev);
6665
6666 if (!igb_has_link(adapter))
6667 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6668
6669 return -EBUSY;
6670}
6671
6672static int igb_runtime_suspend(struct device *dev)
6673{
6674 struct pci_dev *pdev = to_pci_dev(dev);
6675 int retval;
6676 bool wake;
6677
6678 retval = __igb_shutdown(pdev, &wake, 1);
6679 if (retval)
6680 return retval;
6681
6682 if (wake) {
6683 pci_prepare_to_sleep(pdev);
6684 } else {
6685 pci_wake_from_d3(pdev, false);
6686 pci_set_power_state(pdev, PCI_D3hot);
6687 }
9d5c8243 6688
9d5c8243
AK		 6689 return 0;
6690}
749ab2cd
YZ		 6691
6692static int igb_runtime_resume(struct device *dev)
6693{
6694 return igb_resume(dev);
6695}
6696#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 6697#endif
6698
6699static void igb_shutdown(struct pci_dev *pdev)
6700{
3fe7c4c9
RW		 6701 bool wake;
6702
749ab2cd 6703 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6704
6705 if (system_state == SYSTEM_POWER_OFF) {
6706 pci_wake_from_d3(pdev, wake);
6707 pci_set_power_state(pdev, PCI_D3hot);
6708 }
9d5c8243
AK		 6709}
6710
6711#ifdef CONFIG_NET_POLL_CONTROLLER
6712/*
6713 * Polling 'interrupt' - used by things like netconsole to send skbs
6714 * without having to re-enable interrupts. It's not called while
6715 * the interrupt routine is executing.
6716 */
6717static void igb_netpoll(struct net_device *netdev)
6718{
6719 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6720 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 6721 struct igb_q_vector *q_vector;
9d5c8243 6722 int i;
9d5c8243 6723
047e0030 6724 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 6725 q_vector = adapter->q_vector[i];
6726 if (adapter->msix_entries)
6727 wr32(E1000_EIMC, q_vector->eims_value);
6728 else
6729 igb_irq_disable(adapter);
047e0030 6730 napi_schedule(&q_vector->napi);
eebbbdba 6731 }
9d5c8243
AK		 6732}
6733#endif /* CONFIG_NET_POLL_CONTROLLER */
6734
6735/**
6736 * igb_io_error_detected - called when PCI error is detected
6737 * @pdev: Pointer to PCI device
6738 * @state: The current pci connection state
6739 *
6740 * This function is called after a PCI bus error affecting
6741 * this device has been detected.
6742 */
6743static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6744 pci_channel_state_t state)
6745{
6746 struct net_device *netdev = pci_get_drvdata(pdev);
6747 struct igb_adapter *adapter = netdev_priv(netdev);
6748
6749 netif_device_detach(netdev);
6750
59ed6eec
AD		 6751 if (state == pci_channel_io_perm_failure)
6752 return PCI_ERS_RESULT_DISCONNECT;
6753
9d5c8243
AK		 6754 if (netif_running(netdev))
6755 igb_down(adapter);
6756 pci_disable_device(pdev);
6757
6758 /* Request a slot slot reset. */
6759 return PCI_ERS_RESULT_NEED_RESET;
6760}
6761
6762/**
6763 * igb_io_slot_reset - called after the pci bus has been reset.
6764 * @pdev: Pointer to PCI device
6765 *
6766 * Restart the card from scratch, as if from a cold-boot. Implementation
6767 * resembles the first-half of the igb_resume routine.
6768 */
6769static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6770{
6771 struct net_device *netdev = pci_get_drvdata(pdev);
6772 struct igb_adapter *adapter = netdev_priv(netdev);
6773 struct e1000_hw *hw = &adapter->hw;
40a914fa 6774 pci_ers_result_t result;
42bfd33a 6775 int err;
9d5c8243 6776
aed5dec3 6777 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6778 dev_err(&pdev->dev,
6779 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6780 result = PCI_ERS_RESULT_DISCONNECT;
6781 } else {
6782 pci_set_master(pdev);
6783 pci_restore_state(pdev);
b94f2d77 6784 pci_save_state(pdev);
9d5c8243 6785
40a914fa
AD		 6786 pci_enable_wake(pdev, PCI_D3hot, 0);
6787 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6788
40a914fa
AD		 6789 igb_reset(adapter);
6790 wr32(E1000_WUS, ~0);
6791 result = PCI_ERS_RESULT_RECOVERED;
6792 }
9d5c8243 6793
ea943d41
JK		 6794 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6795 if (err) {
6796 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6797 "failed 0x%0x\n", err);
6798 /* non-fatal, continue */
6799 }
40a914fa
AD		 6800
6801 return result;
9d5c8243
AK		 6802}
6803
6804/**
6805 * igb_io_resume - called when traffic can start flowing again.
6806 * @pdev: Pointer to PCI device
6807 *
6808 * This callback is called when the error recovery driver tells us that
6809 * its OK to resume normal operation. Implementation resembles the
6810 * second-half of the igb_resume routine.
6811 */
6812static void igb_io_resume(struct pci_dev *pdev)
6813{
6814 struct net_device *netdev = pci_get_drvdata(pdev);
6815 struct igb_adapter *adapter = netdev_priv(netdev);
6816
9d5c8243
AK		 6817 if (netif_running(netdev)) {
6818 if (igb_up(adapter)) {
6819 dev_err(&pdev->dev, "igb_up failed after reset\n");
6820 return;
6821 }
6822 }
6823
6824 netif_device_attach(netdev);
6825
6826 /* let the f/w know that the h/w is now under the control of the
6827 * driver. */
6828 igb_get_hw_control(adapter);
9d5c8243
AK		 6829}
6830
26ad9178
AD		 6831static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
6832 u8 qsel)
6833{
6834 u32 rar_low, rar_high;
6835 struct e1000_hw *hw = &adapter->hw;
6836
6837 /* HW expects these in little endian so we reverse the byte order
6838 * from network order (big endian) to little endian
6839 */
6840 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
6841 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
6842 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
6843
6844 /* Indicate to hardware the Address is Valid. */
6845 rar_high |= E1000_RAH_AV;
6846
6847 if (hw->mac.type == e1000_82575)
6848 rar_high |= E1000_RAH_POOL_1 * qsel;
6849 else
6850 rar_high |= E1000_RAH_POOL_1 << qsel;
6851
6852 wr32(E1000_RAL(index), rar_low);
6853 wrfl();
6854 wr32(E1000_RAH(index), rar_high);
6855 wrfl();
6856}
6857
4ae196df
AD		 6858static int igb_set_vf_mac(struct igb_adapter *adapter,
6859 int vf, unsigned char *mac_addr)
6860{
6861 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 6862 /* VF MAC addresses start at end of receive addresses and moves
6863 * torwards the first, as a result a collision should not be possible */
6864 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 6865
37680117 6866 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 6867
26ad9178 6868 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 6869
6870 return 0;
6871}
6872
8151d294
WM		 6873static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
6874{
6875 struct igb_adapter *adapter = netdev_priv(netdev);
6876 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
6877 return -EINVAL;
6878 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
6879 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
6880 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
6881 " change effective.");
6882 if (test_bit(__IGB_DOWN, &adapter->state)) {
6883 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
6884 " but the PF device is not up.\n");
6885 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
6886 " attempting to use the VF device.\n");
6887 }
6888 return igb_set_vf_mac(adapter, vf, mac);
6889}
6890
17dc566c
LL		 6891static int igb_link_mbps(int internal_link_speed)
6892{
6893 switch (internal_link_speed) {
6894 case SPEED_100:
6895 return 100;
6896 case SPEED_1000:
6897 return 1000;
6898 default:
6899 return 0;
6900 }
6901}
6902
6903static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
6904 int link_speed)
6905{
6906 int rf_dec, rf_int;
6907 u32 bcnrc_val;
6908
6909 if (tx_rate != 0) {
6910 /* Calculate the rate factor values to set */
6911 rf_int = link_speed / tx_rate;
6912 rf_dec = (link_speed - (rf_int * tx_rate));
6913 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
6914
6915 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
6916 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
6917 E1000_RTTBCNRC_RF_INT_MASK);
6918 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
6919 } else {
6920 bcnrc_val = 0;
6921 }
6922
6923 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 6924 /*
6925 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6926 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
6927 */
6928 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 6929 wr32(E1000_RTTBCNRC, bcnrc_val);
6930}
6931
6932static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
6933{
6934 int actual_link_speed, i;
6935 bool reset_rate = false;
6936
6937 /* VF TX rate limit was not set or not supported */
6938 if ((adapter->vf_rate_link_speed == 0) ||
6939 (adapter->hw.mac.type != e1000_82576))
6940 return;
6941
6942 actual_link_speed = igb_link_mbps(adapter->link_speed);
6943 if (actual_link_speed != adapter->vf_rate_link_speed) {
6944 reset_rate = true;
6945 adapter->vf_rate_link_speed = 0;
6946 dev_info(&adapter->pdev->dev,
6947 "Link speed has been changed. VF Transmit "
6948 "rate is disabled\n");
6949 }
6950
6951 for (i = 0; i < adapter->vfs_allocated_count; i++) {
6952 if (reset_rate)
6953 adapter->vf_data[i].tx_rate = 0;
6954
6955 igb_set_vf_rate_limit(&adapter->hw, i,
6956 adapter->vf_data[i].tx_rate,
6957 actual_link_speed);
6958 }
6959}
6960
8151d294
WM		 6961static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
6962{
17dc566c
LL		 6963 struct igb_adapter *adapter = netdev_priv(netdev);
6964 struct e1000_hw *hw = &adapter->hw;
6965 int actual_link_speed;
6966
6967 if (hw->mac.type != e1000_82576)
6968 return -EOPNOTSUPP;
6969
6970 actual_link_speed = igb_link_mbps(adapter->link_speed);
6971 if ((vf >= adapter->vfs_allocated_count) ||
6972 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
6973 (tx_rate < 0) || (tx_rate > actual_link_speed))
6974 return -EINVAL;
6975
6976 adapter->vf_rate_link_speed = actual_link_speed;
6977 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
6978 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
6979
6980 return 0;
8151d294
WM		 6981}
6982
6983static int igb_ndo_get_vf_config(struct net_device *netdev,
6984 int vf, struct ifla_vf_info *ivi)
6985{
6986 struct igb_adapter *adapter = netdev_priv(netdev);
6987 if (vf >= adapter->vfs_allocated_count)
6988 return -EINVAL;
6989 ivi->vf = vf;
6990 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 6991 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 6992 ivi->vlan = adapter->vf_data[vf].pf_vlan;
6993 ivi->qos = adapter->vf_data[vf].pf_qos;
6994 return 0;
6995}
6996
4ae196df
AD		 6997static void igb_vmm_control(struct igb_adapter *adapter)
6998{
6999 struct e1000_hw *hw = &adapter->hw;
10d8e907 7000 u32 reg;
4ae196df 7001
52a1dd4d
AD		 7002 switch (hw->mac.type) {
7003 case e1000_82575:
f96a8a0b
CW		 7004 case e1000_i210:
7005 case e1000_i211:
52a1dd4d
AD		 7006 default:
7007 /* replication is not supported for 82575 */
4ae196df 7008 return;
52a1dd4d
AD		 7009 case e1000_82576:
7010 /* notify HW that the MAC is adding vlan tags */
7011 reg = rd32(E1000_DTXCTL);
7012 reg |= E1000_DTXCTL_VLAN_ADDED;
7013 wr32(E1000_DTXCTL, reg);
7014 case e1000_82580:
7015 /* enable replication vlan tag stripping */
7016 reg = rd32(E1000_RPLOLR);
7017 reg |= E1000_RPLOLR_STRVLAN;
7018 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7019 case e1000_i350:
7020 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7021 break;
7022 }
10d8e907 7023
d4960307
AD		 7024 if (adapter->vfs_allocated_count) {
7025 igb_vmdq_set_loopback_pf(hw, true);
7026 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7027 igb_vmdq_set_anti_spoofing_pf(hw, true,
7028 adapter->vfs_allocated_count);
d4960307
AD		 7029 } else {
7030 igb_vmdq_set_loopback_pf(hw, false);
7031 igb_vmdq_set_replication_pf(hw, false);
7032 }
4ae196df
AD		 7033}
7034
b6e0c419
CW		 7035static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7036{
7037 struct e1000_hw *hw = &adapter->hw;
7038 u32 dmac_thr;
7039 u16 hwm;
7040
7041 if (hw->mac.type > e1000_82580) {
7042 if (adapter->flags & IGB_FLAG_DMAC) {
7043 u32 reg;
7044
7045 /* force threshold to 0. */
7046 wr32(E1000_DMCTXTH, 0);
7047
7048 /*
e8c626e9
MV		 7049 * DMA Coalescing high water mark needs to be greater
7050 * than the Rx threshold. Set hwm to PBA - max frame
7051 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7052 */
e8c626e9
MV		 7053 hwm = 64 * pba - adapter->max_frame_size / 16;
7054 if (hwm < 64 * (pba - 6))
7055 hwm = 64 * (pba - 6);
7056 reg = rd32(E1000_FCRTC);
7057 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7058 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7059 & E1000_FCRTC_RTH_COAL_MASK);
7060 wr32(E1000_FCRTC, reg);
7061
7062 /*
7063 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7064 * frame size, capping it at PBA - 10KB.
7065 */
7066 dmac_thr = pba - adapter->max_frame_size / 512;
7067 if (dmac_thr < pba - 10)
7068 dmac_thr = pba - 10;
b6e0c419
CW		 7069 reg = rd32(E1000_DMACR);
7070 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7071 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7072 & E1000_DMACR_DMACTHR_MASK);
7073
7074 /* transition to L0x or L1 if available..*/
7075 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7076
7077 /* watchdog timer= +-1000 usec in 32usec intervals */
7078 reg |= (1000 >> 5);
0c02dd98
MV		 7079
7080 /* Disable BMC-to-OS Watchdog Enable */
7081 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7082 wr32(E1000_DMACR, reg);
7083
7084 /*
7085 * no lower threshold to disable
7086 * coalescing(smart fifb)-UTRESH=0
7087 */
7088 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7089
7090 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7091
7092 wr32(E1000_DMCTLX, reg);
7093
7094 /*
7095 * free space in tx packet buffer to wake from
7096 * DMA coal
7097 */
7098 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7099 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7100
7101 /*
7102 * make low power state decision controlled
7103 * by DMA coal
7104 */
7105 reg = rd32(E1000_PCIEMISC);
7106 reg &= ~E1000_PCIEMISC_LX_DECISION;
7107 wr32(E1000_PCIEMISC, reg);
7108 } /* endif adapter->dmac is not disabled */
7109 } else if (hw->mac.type == e1000_82580) {
7110 u32 reg = rd32(E1000_PCIEMISC);
7111 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7112 wr32(E1000_DMACR, 0);
7113 }
7114}
7115
9d5c8243 7116/* igb_main.c */
Linux kernel - Deliverables
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