projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: Enable use of "bridge fdb add" to set unicast table entries
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
6fb46902
TF		 60#define MIN 3
61#define BUILD 0
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
32b3e08f 154static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 184#endif
9d5c8243 185
9d5c8243 186#ifdef CONFIG_PM
d9dd966d 187#ifdef CONFIG_PM_SLEEP
749ab2cd 188static int igb_suspend(struct device *);
d9dd966d 189#endif
749ab2cd 190static int igb_resume(struct device *);
749ab2cd
YZ		 191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
52285b76 949 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 950
047e0030 951 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 952 igb_msix_other, 0, netdev->name, adapter);
047e0030 953 if (err)
52285b76 954 goto err_out;
047e0030
AD		 955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
52285b76
SA		 959 vector++;
960
7b06a690 961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 962
0ba82994 963 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
047e0030 967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
047e0030 970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 971 q_vector->rx.ring->queue_index);
9d5c8243 972 else
047e0030
AD		 973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
9d5c8243 975 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
9d5c8243 978 if (err)
52285b76 979 goto err_free;
9d5c8243
AK		 980 }
981
9d5c8243
AK		 982 igb_configure_msix(adapter);
983 return 0;
52285b76
SA		 984
985err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994err_out:
9d5c8243
AK		 995 return err;
996}
997
5536d210 998/**
b980ac18
JK		 999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
5536d210 1002 *
02ef6e1d 1003 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
02ef6e1d
CW		 1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
17a402a0
CW		 1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
cb06d102
CP		 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
5536d210
AD		 1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
2439fc4d 1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1041
5536d210
AD		 1042 netif_napi_del(&q_vector->napi);
1043
02ef6e1d
CW		 1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
cd14ef54 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1051 pci_disable_msix(adapter->pdev);
cd14ef54 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1053 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1057}
1058
047e0030 1059/**
b980ac18
JK		 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
047e0030 1062 *
b980ac18
JK		 1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
047e0030
AD		 1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
5536d210
AD		 1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
047e0030 1073 adapter->num_q_vectors = 0;
5536d210 1074
02ef6e1d
CW		 1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
5536d210 1077 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1078 }
047e0030
AD		 1079}
1080
1081/**
b980ac18
JK		 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
047e0030 1084 *
b980ac18
JK		 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
047e0030
AD		 1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
047e0030
AD		 1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
9d5c8243
AK		 1093
1094/**
b980ac18
JK		 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
9d5c8243 1098 *
b980ac18
JK		 1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
9d5c8243 1101 **/
53c7d064 1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1103{
1104 int err;
1105 int numvecs, i;
1106
53c7d064
SA		 1107 if (!msix)
1108 goto msi_only;
cd14ef54 1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1110
83b7180d 1111 /* Number of supported queues. */
a99955fc 1112 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1117
b980ac18 1118 /* start with one vector for every Rx queue */
047e0030
AD		 1119 numvecs = adapter->num_rx_queues;
1120
b980ac18 1121 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
047e0030
AD		 1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
9d5c8243
AK		 1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
479d02df
AG		 1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
0c2cc02e 1138 return;
9d5c8243
AK		 1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
b709323d 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1156 wrfl();
2a3abf6d
AD		 1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
4fc82adf 1161 adapter->vfs_allocated_count = 0;
a99955fc 1162 adapter->rss_queues = 1;
4fc82adf 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1164 adapter->num_rx_queues = 1;
661086df 1165 adapter->num_tx_queues = 1;
047e0030 1166 adapter->num_q_vectors = 1;
9d5c8243 1167 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1168 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1169}
1170
5536d210
AD		 1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
047e0030 1178/**
b980ac18
JK		 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
047e0030 1187 *
b980ac18 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1189 **/
5536d210
AD		 1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
047e0030
AD		 1194{
1195 struct igb_q_vector *q_vector;
5536d210
AD		 1196 struct igb_ring *ring;
1197 int ring_count, size;
047e0030 1198
5536d210
AD		 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
02ef6e1d 1208 q_vector = adapter->q_vector[v_idx];
72ddef05 1209 if (!q_vector) {
02ef6e1d 1210 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
c0a06ee1 1215 memset(q_vector, 0, size);
72ddef05 1216 }
5536d210
AD		 1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
7b06a690 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
4e227667
AD		 1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
5536d210
AD		 1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
827da44c
JS		 1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
5536d210
AD		 1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
047e0030 1276 }
81c2fc22 1277
5536d210
AD		 1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
047e0030 1282
5536d210
AD		 1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
047e0030 1285
5536d210
AD		 1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
047e0030 1288
5536d210
AD		 1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1292
e52c0f96 1293 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1294 * have the tag byte-swapped.
b980ac18 1295 */
5536d210
AD		 1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1298
5536d210
AD		 1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
827da44c
JS		 1303 u64_stats_init(&ring->rx_syncp);
1304
5536d210
AD		 1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
047e0030
AD		 1310}
1311
5536d210 1312
047e0030 1313/**
b980ac18
JK		 1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
047e0030 1316 *
b980ac18
JK		 1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
047e0030 1319 **/
5536d210 1320static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1321{
5536d210
AD		 1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
047e0030 1327
5536d210
AD		 1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
047e0030 1332
5536d210
AD		 1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
047e0030 1339 }
047e0030 1340 }
5536d210
AD		 1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1345
5536d210
AD		 1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
047e0030 1359 return 0;
5536d210
AD		 1360
1361err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
047e0030
AD		 1370}
1371
1372/**
b980ac18
JK		 1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
047e0030 1376 *
b980ac18 1377 * This function initializes the interrupts and allocates all of the queues.
047e0030 1378 **/
53c7d064 1379static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1380{
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
53c7d064 1384 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
5536d210 1392 igb_cache_ring_register(adapter);
047e0030
AD		 1393
1394 return 0;
5536d210 1395
047e0030
AD		 1396err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399}
1400
9d5c8243 1401/**
b980ac18
JK		 1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
9d5c8243 1404 *
b980ac18
JK		 1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
9d5c8243
AK		 1407 **/
1408static int igb_request_irq(struct igb_adapter *adapter)
1409{
1410 struct net_device *netdev = adapter->netdev;
047e0030 1411 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1412 int err = 0;
1413
cd14ef54 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1415 err = igb_request_msix(adapter);
844290e5 1416 if (!err)
9d5c8243 1417 goto request_done;
9d5c8243 1418 /* fall back to MSI */
5536d210
AD		 1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
53c7d064 1421
047e0030 1422 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
047e0030 1425 goto request_done;
53c7d064 1426
047e0030
AD		 1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
53c7d064 1429 igb_configure(adapter);
9d5c8243 1430 }
844290e5 1431
c74d588e
AD		 1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
7dfc16fa 1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1436 netdev->name, adapter);
9d5c8243
AK		 1437 if (!err)
1438 goto request_done;
047e0030 1439
9d5c8243
AK		 1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
7dfc16fa 1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1443 }
1444
c74d588e 1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1446 netdev->name, adapter);
9d5c8243 1447
6cb5e577 1448 if (err)
c74d588e 1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1450 err);
9d5c8243
AK		 1451
1452request_done:
1453 return err;
1454}
1455
1456static void igb_free_irq(struct igb_adapter *adapter)
1457{
cd14ef54 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1459 int vector = 0, i;
1460
047e0030 1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1462
0d1ae7f4 1463 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1464 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1465 adapter->q_vector[i]);
047e0030
AD		 1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1468 }
9d5c8243
AK		 1469}
1470
1471/**
b980ac18
JK		 1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
9d5c8243
AK		 1474 **/
1475static void igb_irq_disable(struct igb_adapter *adapter)
1476{
1477 struct e1000_hw *hw = &adapter->hw;
1478
b980ac18 1479 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
cd14ef54 1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1484 u32 regval = rd32(E1000_EIAM);
9005df38 1485
2dfd1212
AD		 1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1490 }
844290e5
PW		 1491
1492 wr32(E1000_IAM, 0);
9d5c8243
AK		 1493 wr32(E1000_IMC, ~0);
1494 wrfl();
cd14ef54 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1496 int i;
9005df38 1497
81a61859
ET		 1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
9d5c8243
AK		 1503}
1504
1505/**
b980ac18
JK		 1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
9d5c8243
AK		 1508 **/
1509static void igb_irq_enable(struct igb_adapter *adapter)
1510{
1511 struct e1000_hw *hw = &adapter->hw;
1512
cd14ef54 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1515 u32 regval = rd32(E1000_EIAC);
9005df38 1516
2dfd1212
AD		 1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1521 if (adapter->vfs_allocated_count) {
4ae196df 1522 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
844290e5 1526 } else {
55cac248
AD		 1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
844290e5 1531 }
9d5c8243
AK		 1532}
1533
1534static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535{
51466239 1536 struct e1000_hw *hw = &adapter->hw;
8b77c6b2 1537 u16 pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
8b77c6b2 1543 igb_vfta_set(hw, vid, pf_id, true, true);
51466239
AD		 1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
b2cb09b1 1551 !test_bit(old_vid, adapter->active_vlans)) {
51466239 1552 /* remove VID from filter table */
8b77c6b2 1553 igb_vfta_set(hw, vid, pf_id, false, true);
9d5c8243
AK		 1554 }
1555}
1556
1557/**
b980ac18
JK		 1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
9d5c8243 1560 *
b980ac18
JK		 1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
9d5c8243
AK		 1564 **/
1565static void igb_release_hw_control(struct igb_adapter *adapter)
1566{
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574}
1575
9d5c8243 1576/**
b980ac18
JK		 1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
9d5c8243 1579 *
b980ac18
JK		 1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
9d5c8243
AK		 1583 **/
1584static void igb_get_hw_control(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593}
1594
9d5c8243 1595/**
b980ac18
JK		 1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
9d5c8243
AK		 1598 **/
1599static void igb_configure(struct igb_adapter *adapter)
1600{
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
ff41f8dc 1605 igb_set_rx_mode(netdev);
9d5c8243
AK		 1606
1607 igb_restore_vlan(adapter);
9d5c8243 1608
85b430b4 1609 igb_setup_tctl(adapter);
06cf2666 1610 igb_setup_mrqc(adapter);
9d5c8243 1611 igb_setup_rctl(adapter);
85b430b4
AD		 1612
1613 igb_configure_tx(adapter);
9d5c8243 1614 igb_configure_rx(adapter);
662d7205
AD		 1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
c493ea45 1618 /* call igb_desc_unused which always leaves
9d5c8243 1619 * at least 1 descriptor unused to make sure
b980ac18
JK		 1620 * next_to_use != next_to_clean
1621 */
9d5c8243 1622 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1623 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1625 }
9d5c8243
AK		 1626}
1627
88a268c1 1628/**
b980ac18
JK		 1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
88a268c1
NN		 1631 **/
1632void igb_power_up_link(struct igb_adapter *adapter)
1633{
76886596
AA		 1634 igb_reset_phy(&adapter->hw);
1635
88a268c1
NN		 1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1640
1641 igb_setup_link(&adapter->hw);
88a268c1
NN		 1642}
1643
1644/**
b980ac18
JK		 1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
88a268c1
NN		 1647 */
1648static void igb_power_down_link(struct igb_adapter *adapter)
1649{
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654}
9d5c8243 1655
56cec249
CW		 1656/**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660static void igb_check_swap_media(struct igb_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721}
1722
9d5c8243 1723/**
b980ac18
JK		 1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
9d5c8243 1726 **/
9d5c8243
AK		 1727int igb_up(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
0d1ae7f4
AD		 1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
cd14ef54 1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1741 igb_configure_msix(adapter);
feeb2721
AD		 1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
d4960307
AD		 1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1752
d4960307
AD		 1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
4cb9be7a
JB		 1757 netif_tx_start_all_queues(adapter->netdev);
1758
25568a53
AD		 1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
f4c01e96
CW		 1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
9d5c8243
AK		 1767 return 0;
1768}
1769
1770void igb_down(struct igb_adapter *adapter)
1771{
9d5c8243 1772 struct net_device *netdev = adapter->netdev;
330a6d6a 1773 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1778 * reschedule our watchdog timer
1779 */
9d5c8243
AK		 1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
f28ea083 1787 netif_carrier_off(netdev);
fd2ea0a7 1788 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
0d451e79 1796 usleep_range(10000, 11000);
9d5c8243 1797
41f149a2
CW		 1798 igb_irq_disable(adapter);
1799
aa9b8cc4
AA		 1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
41f149a2 1802 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
41f149a2 1807 }
9d5c8243 1808
9d5c8243
AK		 1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
04fe6358 1812 /* record the stats before reset*/
12dcd86b
ED		 1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
04fe6358 1816
9d5c8243
AK		 1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
3023682e
JK		 1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
16903caa
AD		 1822
1823 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1824 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1825
9d5c8243
AK		 1826 igb_clean_all_tx_rings(adapter);
1827 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1828#ifdef CONFIG_IGB_DCA
1829
1830 /* since we reset the hardware DCA settings were cleared */
1831 igb_setup_dca(adapter);
1832#endif
9d5c8243
AK		 1833}
1834
1835void igb_reinit_locked(struct igb_adapter *adapter)
1836{
1837 WARN_ON(in_interrupt());
1838 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1839 usleep_range(1000, 2000);
9d5c8243
AK		 1840 igb_down(adapter);
1841 igb_up(adapter);
1842 clear_bit(__IGB_RESETTING, &adapter->state);
1843}
1844
56cec249
CW		 1845/** igb_enable_mas - Media Autosense re-enable after swap
1846 *
1847 * @adapter: adapter struct
1848 **/
8cfb879d 1849static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1850{
1851 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1852 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1853
1854 /* configure for SerDes media detect */
8cfb879d
TF		 1855 if ((hw->phy.media_type == e1000_media_type_copper) &&
1856 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1857 connsw |= E1000_CONNSW_ENRGSRC;
1858 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1859 wr32(E1000_CONNSW, connsw);
1860 wrfl();
56cec249 1861 }
56cec249
CW		 1862}
1863
9d5c8243
AK		 1864void igb_reset(struct igb_adapter *adapter)
1865{
090b1795 1866 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1867 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1868 struct e1000_mac_info *mac = &hw->mac;
1869 struct e1000_fc_info *fc = &hw->fc;
45693bcb 1870 u32 pba, hwm;
9d5c8243
AK		 1871
1872 /* Repartition Pba for greater than 9k mtu
1873 * To take effect CTRL.RST is required.
1874 */
fa4dfae0 1875 switch (mac->type) {
d2ba2ed8 1876 case e1000_i350:
ceb5f13b 1877 case e1000_i354:
55cac248
AD		 1878 case e1000_82580:
1879 pba = rd32(E1000_RXPBS);
1880 pba = igb_rxpbs_adjust_82580(pba);
1881 break;
fa4dfae0 1882 case e1000_82576:
d249be54
AD		 1883 pba = rd32(E1000_RXPBS);
1884 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1885 break;
1886 case e1000_82575:
f96a8a0b
CW		 1887 case e1000_i210:
1888 case e1000_i211:
fa4dfae0
AD		 1889 default:
1890 pba = E1000_PBA_34K;
1891 break;
2d064c06 1892 }
9d5c8243 1893
45693bcb
AD		 1894 if (mac->type == e1000_82575) {
1895 u32 min_rx_space, min_tx_space, needed_tx_space;
1896
1897 /* write Rx PBA so that hardware can report correct Tx PBA */
9d5c8243
AK		 1898 wr32(E1000_PBA, pba);
1899
1900 /* To maintain wire speed transmits, the Tx FIFO should be
1901 * large enough to accommodate two full transmit packets,
1902 * rounded up to the next 1KB and expressed in KB. Likewise,
1903 * the Rx FIFO should be large enough to accommodate at least
1904 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1905 * expressed in KB.
1906 */
45693bcb
AD		 1907 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1908
1909 /* The Tx FIFO also stores 16 bytes of information about the Tx
1910 * but don't include Ethernet FCS because hardware appends it.
1911 * We only need to round down to the nearest 512 byte block
1912 * count since the value we care about is 2 frames, not 1.
b980ac18 1913 */
45693bcb
AD		 1914 min_tx_space = adapter->max_frame_size;
1915 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1916 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1917
1918 /* upper 16 bits has Tx packet buffer allocation size in KB */
1919 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
9d5c8243
AK		 1920
1921 /* If current Tx allocation is less than the min Tx FIFO size,
1922 * and the min Tx FIFO size is less than the current Rx FIFO
45693bcb 1923 * allocation, take space away from current Rx allocation.
b980ac18 1924 */
45693bcb
AD		 1925 if (needed_tx_space < pba) {
1926 pba -= needed_tx_space;
9d5c8243 1927
b980ac18
JK		 1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
9d5c8243
AK		 1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
45693bcb
AD		 1934
1935 /* adjust PBA for jumbo frames */
2d064c06 1936 wr32(E1000_PBA, pba);
9d5c8243 1937 }
9d5c8243 1938
45693bcb
AD		 1939 /* flow control settings
1940 * The high water mark must be low enough to fit one full frame
1941 * after transmitting the pause frame. As such we must have enough
1942 * space to allow for us to complete our current transmit and then
1943 * receive the frame that is in progress from the link partner.
1944 * Set it to:
1945 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
b980ac18 1946 */
45693bcb 1947 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
9d5c8243 1948
d48507fe 1949 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1950 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1951 fc->pause_time = 0xFFFF;
1952 fc->send_xon = 1;
0cce119a 1953 fc->current_mode = fc->requested_mode;
9d5c8243 1954
4ae196df
AD		 1955 /* disable receive for all VFs and wait one second */
1956 if (adapter->vfs_allocated_count) {
1957 int i;
9005df38 1958
4ae196df 1959 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1960 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1961
1962 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1963 igb_ping_all_vfs(adapter);
4ae196df
AD		 1964
1965 /* disable transmits and receives */
1966 wr32(E1000_VFRE, 0);
1967 wr32(E1000_VFTE, 0);
1968 }
1969
9d5c8243 1970 /* Allow time for pending master requests to run */
330a6d6a 1971 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1972 wr32(E1000_WUC, 0);
1973
56cec249
CW		 1974 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1975 /* need to resetup here after media swap */
1976 adapter->ei.get_invariants(hw);
1977 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1978 }
8cfb879d
TF		 1979 if ((mac->type == e1000_82575) &&
1980 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1981 igb_enable_mas(adapter);
56cec249 1982 }
330a6d6a 1983 if (hw->mac.ops.init_hw(hw))
090b1795 1984 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1985
b980ac18 1986 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1987 * control is off when forcing speed.
1988 */
1989 if (!hw->mac.autoneg)
1990 igb_force_mac_fc(hw);
1991
b6e0c419 1992 igb_init_dmac(adapter, pba);
e428893b
CW		 1993#ifdef CONFIG_IGB_HWMON
1994 /* Re-initialize the thermal sensor on i350 devices. */
1995 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1996 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1997 /* If present, re-initialize the external thermal sensor
1998 * interface.
1999 */
2000 if (adapter->ets)
2001 mac->ops.init_thermal_sensor_thresh(hw);
2002 }
2003 }
2004#endif
b936136d 2005 /* Re-establish EEE setting */
f4c01e96
CW		 2006 if (hw->phy.media_type == e1000_media_type_copper) {
2007 switch (mac->type) {
2008 case e1000_i350:
2009 case e1000_i210:
2010 case e1000_i211:
c4c112f1 2011 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2012 break;
2013 case e1000_i354:
c4c112f1 2014 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2015 break;
2016 default:
2017 break;
2018 }
2019 }
88a268c1
NN		 2020 if (!netif_running(adapter->netdev))
2021 igb_power_down_link(adapter);
2022
9d5c8243
AK		 2023 igb_update_mng_vlan(adapter);
2024
2025 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2026 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2027
1f6e8178
MV		 2028 /* Re-enable PTP, where applicable. */
2029 igb_ptp_reset(adapter);
1f6e8178 2030
330a6d6a 2031 igb_get_phy_info(hw);
9d5c8243
AK		 2032}
2033
c8f44aff
MM		 2034static netdev_features_t igb_fix_features(struct net_device *netdev,
2035 netdev_features_t features)
b2cb09b1 2036{
b980ac18
JK		 2037 /* Since there is no support for separate Rx/Tx vlan accel
2038 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2039 */
f646968f
PM		 2040 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2041 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2042 else
f646968f 2043 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2044
2045 return features;
2046}
2047
c8f44aff
MM		 2048static int igb_set_features(struct net_device *netdev,
2049 netdev_features_t features)
ac52caa3 2050{
c8f44aff 2051 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2052 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2053
f646968f 2054 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2055 igb_vlan_mode(netdev, features);
2056
16903caa 2057 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
89eaefb6
BG		 2058 return 0;
2059
2060 netdev->features = features;
2061
2062 if (netif_running(netdev))
2063 igb_reinit_locked(adapter);
2064 else
2065 igb_reset(adapter);
2066
ac52caa3
MM		 2067 return 0;
2068}
2069
268f9d33
AD		 2070static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2071 struct net_device *dev,
2072 const unsigned char *addr, u16 vid,
2073 u16 flags)
2074{
2075 /* guarantee we can provide a unique filter for the unicast address */
2076 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2077 struct igb_adapter *adapter = netdev_priv(dev);
2078 struct e1000_hw *hw = &adapter->hw;
2079 int vfn = adapter->vfs_allocated_count;
2080 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2081
2082 if (netdev_uc_count(dev) >= rar_entries)
2083 return -ENOMEM;
2084 }
2085
2086 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2087}
2088
2e5c6922 2089static const struct net_device_ops igb_netdev_ops = {
559e9c49 2090 .ndo_open = igb_open,
2e5c6922 2091 .ndo_stop = igb_close,
cd392f5c 2092 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2093 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2094 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2095 .ndo_set_mac_address = igb_set_mac,
2096 .ndo_change_mtu = igb_change_mtu,
2097 .ndo_do_ioctl = igb_ioctl,
2098 .ndo_tx_timeout = igb_tx_timeout,
2099 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2100 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2101 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2102 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2103 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2104 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2105 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2106 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2107#ifdef CONFIG_NET_POLL_CONTROLLER
2108 .ndo_poll_controller = igb_netpoll,
2109#endif
b2cb09b1
JP		 2110 .ndo_fix_features = igb_fix_features,
2111 .ndo_set_features = igb_set_features,
268f9d33 2112 .ndo_fdb_add = igb_ndo_fdb_add,
1abbc98a 2113 .ndo_features_check = passthru_features_check,
2e5c6922
SH		 2114};
2115
d67974f0
CW		 2116/**
2117 * igb_set_fw_version - Configure version string for ethtool
2118 * @adapter: adapter struct
d67974f0
CW		 2119 **/
2120void igb_set_fw_version(struct igb_adapter *adapter)
2121{
2122 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2123 struct e1000_fw_version fw;
2124
2125 igb_get_fw_version(hw, &fw);
2126
2127 switch (hw->mac.type) {
7dc98a62 2128 case e1000_i210:
0b1a6f2e 2129 case e1000_i211:
7dc98a62
CW		 2130 if (!(igb_get_flash_presence_i210(hw))) {
2131 snprintf(adapter->fw_version,
2132 sizeof(adapter->fw_version),
2133 "%2d.%2d-%d",
2134 fw.invm_major, fw.invm_minor,
2135 fw.invm_img_type);
2136 break;
2137 }
2138 /* fall through */
0b1a6f2e
CW		 2139 default:
2140 /* if option is rom valid, display its version too */
2141 if (fw.or_valid) {
2142 snprintf(adapter->fw_version,
2143 sizeof(adapter->fw_version),
2144 "%d.%d, 0x%08x, %d.%d.%d",
2145 fw.eep_major, fw.eep_minor, fw.etrack_id,
2146 fw.or_major, fw.or_build, fw.or_patch);
2147 /* no option rom */
7dc98a62 2148 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2149 snprintf(adapter->fw_version,
7dc98a62
CW		 2150 sizeof(adapter->fw_version),
2151 "%d.%d, 0x%08x",
2152 fw.eep_major, fw.eep_minor, fw.etrack_id);
2153 } else {
2154 snprintf(adapter->fw_version,
2155 sizeof(adapter->fw_version),
2156 "%d.%d.%d",
2157 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2158 }
2159 break;
d67974f0 2160 }
d67974f0
CW		 2161}
2162
56cec249
CW		 2163/**
2164 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2165 *
2166 * @adapter: adapter struct
2167 **/
2168static void igb_init_mas(struct igb_adapter *adapter)
2169{
2170 struct e1000_hw *hw = &adapter->hw;
2171 u16 eeprom_data;
2172
2173 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2174 switch (hw->bus.func) {
2175 case E1000_FUNC_0:
2176 if (eeprom_data & IGB_MAS_ENABLE_0) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 case E1000_FUNC_1:
2184 if (eeprom_data & IGB_MAS_ENABLE_1) {
2185 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2186 netdev_info(adapter->netdev,
2187 "MAS: Enabling Media Autosense for port %d\n",
2188 hw->bus.func);
2189 }
2190 break;
2191 case E1000_FUNC_2:
2192 if (eeprom_data & IGB_MAS_ENABLE_2) {
2193 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2194 netdev_info(adapter->netdev,
2195 "MAS: Enabling Media Autosense for port %d\n",
2196 hw->bus.func);
2197 }
2198 break;
2199 case E1000_FUNC_3:
2200 if (eeprom_data & IGB_MAS_ENABLE_3) {
2201 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2202 netdev_info(adapter->netdev,
2203 "MAS: Enabling Media Autosense for port %d\n",
2204 hw->bus.func);
2205 }
2206 break;
2207 default:
2208 /* Shouldn't get here */
2209 netdev_err(adapter->netdev,
2210 "MAS: Invalid port configuration, returning\n");
2211 break;
2212 }
2213}
2214
b980ac18
JK		 2215/**
2216 * igb_init_i2c - Init I2C interface
441fc6fd 2217 * @adapter: pointer to adapter structure
b980ac18 2218 **/
441fc6fd
CW		 2219static s32 igb_init_i2c(struct igb_adapter *adapter)
2220{
23d87824 2221 s32 status = 0;
441fc6fd
CW		 2222
2223 /* I2C interface supported on i350 devices */
2224 if (adapter->hw.mac.type != e1000_i350)
23d87824 2225 return 0;
441fc6fd
CW		 2226
2227 /* Initialize the i2c bus which is controlled by the registers.
2228 * This bus will use the i2c_algo_bit structue that implements
2229 * the protocol through toggling of the 4 bits in the register.
2230 */
2231 adapter->i2c_adap.owner = THIS_MODULE;
2232 adapter->i2c_algo = igb_i2c_algo;
2233 adapter->i2c_algo.data = adapter;
2234 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2235 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2236 strlcpy(adapter->i2c_adap.name, "igb BB",
2237 sizeof(adapter->i2c_adap.name));
2238 status = i2c_bit_add_bus(&adapter->i2c_adap);
2239 return status;
2240}
2241
9d5c8243 2242/**
b980ac18
JK		 2243 * igb_probe - Device Initialization Routine
2244 * @pdev: PCI device information struct
2245 * @ent: entry in igb_pci_tbl
9d5c8243 2246 *
b980ac18 2247 * Returns 0 on success, negative on failure
9d5c8243 2248 *
b980ac18
JK		 2249 * igb_probe initializes an adapter identified by a pci_dev structure.
2250 * The OS initialization, configuring of the adapter private structure,
2251 * and a hardware reset occur.
9d5c8243 2252 **/
1dd06ae8 2253static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2254{
2255 struct net_device *netdev;
2256 struct igb_adapter *adapter;
2257 struct e1000_hw *hw;
4337e993 2258 u16 eeprom_data = 0;
9835fd73 2259 s32 ret_val;
4337e993 2260 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2261 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2262 int err, pci_using_dac;
9835fd73 2263 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2264
bded64a7
AG		 2265 /* Catch broken hardware that put the wrong VF device ID in
2266 * the PCIe SR-IOV capability.
2267 */
2268 if (pdev->is_virtfn) {
2269 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2270 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2271 return -EINVAL;
2272 }
2273
aed5dec3 2274 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2275 if (err)
2276 return err;
2277
2278 pci_using_dac = 0;
dc4ff9bb 2279 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2280 if (!err) {
dc4ff9bb 2281 pci_using_dac = 1;
9d5c8243 2282 } else {
dc4ff9bb 2283 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2284 if (err) {
dc4ff9bb
RK		 2285 dev_err(&pdev->dev,
2286 "No usable DMA configuration, aborting\n");
2287 goto err_dma;
9d5c8243
AK		 2288 }
2289 }
2290
aed5dec3 2291 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2292 IORESOURCE_MEM),
2293 igb_driver_name);
9d5c8243
AK		 2294 if (err)
2295 goto err_pci_reg;
2296
19d5afd4 2297 pci_enable_pcie_error_reporting(pdev);
40a914fa 2298
9d5c8243 2299 pci_set_master(pdev);
c682fc23 2300 pci_save_state(pdev);
9d5c8243
AK		 2301
2302 err = -ENOMEM;
1bfaf07b 2303 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2304 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2305 if (!netdev)
2306 goto err_alloc_etherdev;
2307
2308 SET_NETDEV_DEV(netdev, &pdev->dev);
2309
2310 pci_set_drvdata(pdev, netdev);
2311 adapter = netdev_priv(netdev);
2312 adapter->netdev = netdev;
2313 adapter->pdev = pdev;
2314 hw = &adapter->hw;
2315 hw->back = adapter;
b3f4d599 2316 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2317
9d5c8243 2318 err = -EIO;
73bf8048
JW		 2319 adapter->io_addr = pci_iomap(pdev, 0, 0);
2320 if (!adapter->io_addr)
9d5c8243 2321 goto err_ioremap;
73bf8048
JW		 2322 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2323 hw->hw_addr = adapter->io_addr;
9d5c8243 2324
2e5c6922 2325 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2326 igb_set_ethtool_ops(netdev);
9d5c8243 2327 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2328
2329 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2330
89dbefb2
AS		 2331 netdev->mem_start = pci_resource_start(pdev, 0);
2332 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2333
9d5c8243
AK		 2334 /* PCI config space info */
2335 hw->vendor_id = pdev->vendor;
2336 hw->device_id = pdev->device;
2337 hw->revision_id = pdev->revision;
2338 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2339 hw->subsystem_device_id = pdev->subsystem_device;
2340
9d5c8243
AK		 2341 /* Copy the default MAC, PHY and NVM function pointers */
2342 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2343 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2344 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2345 /* Initialize skew-specific constants */
2346 err = ei->get_invariants(hw);
2347 if (err)
450c87c8 2348 goto err_sw_init;
9d5c8243 2349
450c87c8 2350 /* setup the private structure */
9d5c8243
AK		 2351 err = igb_sw_init(adapter);
2352 if (err)
2353 goto err_sw_init;
2354
2355 igb_get_bus_info_pcie(hw);
2356
2357 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2358
2359 /* Copper options */
2360 if (hw->phy.media_type == e1000_media_type_copper) {
2361 hw->phy.mdix = AUTO_ALL_MODES;
2362 hw->phy.disable_polarity_correction = false;
2363 hw->phy.ms_type = e1000_ms_hw_default;
2364 }
2365
2366 if (igb_check_reset_block(hw))
2367 dev_info(&pdev->dev,
2368 "PHY reset is blocked due to SOL/IDER session.\n");
2369
b980ac18 2370 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2371 * set by igb_sw_init so we should use an or instead of an
2372 * assignment.
2373 */
2374 netdev->features |= NETIF_F_SG |
2375 NETIF_F_IP_CSUM |
2376 NETIF_F_IPV6_CSUM |
2377 NETIF_F_TSO |
2378 NETIF_F_TSO6 |
2379 NETIF_F_RXHASH |
2380 NETIF_F_RXCSUM |
f646968f
PM		 2381 NETIF_F_HW_VLAN_CTAG_RX |
2382 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2383
2384 /* copy netdev features into list of user selectable features */
2385 netdev->hw_features |= netdev->features;
89eaefb6 2386 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2387
2388 /* set this bit last since it cannot be part of hw_features */
f646968f 2389 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2390
2391 netdev->vlan_features |= NETIF_F_TSO |
2392 NETIF_F_TSO6 |
2393 NETIF_F_IP_CSUM |
2394 NETIF_F_IPV6_CSUM |
2395 NETIF_F_SG;
48f29ffc 2396
6b8f0922
BG		 2397 netdev->priv_flags |= IFF_SUPP_NOFCS;
2398
7b872a55 2399 if (pci_using_dac) {
9d5c8243 2400 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2401 netdev->vlan_features |= NETIF_F_HIGHDMA;
2402 }
9d5c8243 2403
ac52caa3 2404 if (hw->mac.type >= e1000_82576) {
53692b1d
TH		 2405 netdev->hw_features |= NETIF_F_SCTP_CRC;
2406 netdev->features |= NETIF_F_SCTP_CRC;
ac52caa3 2407 }
b9473560 2408
01789349
JP		 2409 netdev->priv_flags |= IFF_UNICAST_FLT;
2410
330a6d6a 2411 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2412
2413 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2414 * known good starting state
2415 */
9d5c8243
AK		 2416 hw->mac.ops.reset_hw(hw);
2417
ef3a0092
CW		 2418 /* make sure the NVM is good , i211/i210 parts can have special NVM
2419 * that doesn't contain a checksum
f96a8a0b 2420 */
ef3a0092
CW		 2421 switch (hw->mac.type) {
2422 case e1000_i210:
2423 case e1000_i211:
2424 if (igb_get_flash_presence_i210(hw)) {
2425 if (hw->nvm.ops.validate(hw) < 0) {
2426 dev_err(&pdev->dev,
2427 "The NVM Checksum Is Not Valid\n");
2428 err = -EIO;
2429 goto err_eeprom;
2430 }
2431 }
2432 break;
2433 default:
f96a8a0b
CW		 2434 if (hw->nvm.ops.validate(hw) < 0) {
2435 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2436 err = -EIO;
2437 goto err_eeprom;
2438 }
ef3a0092 2439 break;
9d5c8243
AK		 2440 }
2441
2442 /* copy the MAC address out of the NVM */
2443 if (hw->mac.ops.read_mac_addr(hw))
2444 dev_err(&pdev->dev, "NVM Read Error\n");
2445
2446 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2447
aaeb6cdf 2448 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2449 dev_err(&pdev->dev, "Invalid MAC Address\n");
2450 err = -EIO;
2451 goto err_eeprom;
2452 }
2453
d67974f0
CW		 2454 /* get firmware version for ethtool -i */
2455 igb_set_fw_version(adapter);
2456
27dff8b2
TF		 2457 /* configure RXPBSIZE and TXPBSIZE */
2458 if (hw->mac.type == e1000_i210) {
2459 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2460 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2461 }
2462
c061b18d 2463 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2464 (unsigned long) adapter);
c061b18d 2465 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2466 (unsigned long) adapter);
9d5c8243
AK		 2467
2468 INIT_WORK(&adapter->reset_task, igb_reset_task);
2469 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2470
450c87c8 2471 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2472 adapter->fc_autoneg = true;
2473 hw->mac.autoneg = true;
2474 hw->phy.autoneg_advertised = 0x2f;
2475
0cce119a
AD		 2476 hw->fc.requested_mode = e1000_fc_default;
2477 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2478
9d5c8243
AK		 2479 igb_validate_mdi_setting(hw);
2480
63d4a8f9 2481 /* By default, support wake on port A */
a2cf8b6c 2482 if (hw->bus.func == 0)
63d4a8f9
MV		 2483 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2484
2485 /* Check the NVM for wake support on non-port A ports */
2486 if (hw->mac.type >= e1000_82580)
55cac248 2487 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2488 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2489 &eeprom_data);
a2cf8b6c
AD		 2490 else if (hw->bus.func == 1)
2491 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2492
63d4a8f9
MV		 2493 if (eeprom_data & IGB_EEPROM_APME)
2494 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2495
2496 /* now that we have the eeprom settings, apply the special cases where
2497 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2498 * lan on a particular port
2499 */
9d5c8243
AK		 2500 switch (pdev->device) {
2501 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2502 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2503 break;
2504 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2505 case E1000_DEV_ID_82576_FIBER:
2506 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2507 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2508 * regardless of eeprom setting
2509 */
9d5c8243 2510 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2511 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2512 break;
c8ea5ea9 2513 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2514 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2515 /* if quad port adapter, disable WoL on all but port A */
2516 if (global_quad_port_a != 0)
63d4a8f9 2517 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2518 else
2519 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2520 /* Reset for multiple quad port adapters */
2521 if (++global_quad_port_a == 4)
2522 global_quad_port_a = 0;
2523 break;
63d4a8f9
MV		 2524 default:
2525 /* If the device can't wake, don't set software support */
2526 if (!device_can_wakeup(&adapter->pdev->dev))
2527 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2528 }
2529
2530 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2531 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2532 adapter->wol |= E1000_WUFC_MAG;
2533
2534 /* Some vendors want WoL disabled by default, but still supported */
2535 if ((hw->mac.type == e1000_i350) &&
2536 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2537 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2538 adapter->wol = 0;
2539 }
2540
2541 device_set_wakeup_enable(&adapter->pdev->dev,
2542 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2543
2544 /* reset the hardware with the new settings */
2545 igb_reset(adapter);
2546
441fc6fd
CW		 2547 /* Init the I2C interface */
2548 err = igb_init_i2c(adapter);
2549 if (err) {
2550 dev_err(&pdev->dev, "failed to init i2c interface\n");
2551 goto err_eeprom;
2552 }
2553
9d5c8243 2554 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2555 * driver.
2556 */
9d5c8243
AK		 2557 igb_get_hw_control(adapter);
2558
9d5c8243
AK		 2559 strcpy(netdev->name, "eth%d");
2560 err = register_netdev(netdev);
2561 if (err)
2562 goto err_register;
2563
b168dfc5
JB		 2564 /* carrier off reporting is important to ethtool even BEFORE open */
2565 netif_carrier_off(netdev);
2566
421e02f0 2567#ifdef CONFIG_IGB_DCA
bbd98fe4 2568 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2569 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2570 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2571 igb_setup_dca(adapter);
2572 }
fe4506b6 2573
38c845c7 2574#endif
e428893b
CW		 2575#ifdef CONFIG_IGB_HWMON
2576 /* Initialize the thermal sensor on i350 devices. */
2577 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2578 u16 ets_word;
3c89f6d0 2579
b980ac18 2580 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2581 * external thermal sensor.
2582 */
2583 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2584 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2585 adapter->ets = true;
2586 else
2587 adapter->ets = false;
2588 if (igb_sysfs_init(adapter))
2589 dev_err(&pdev->dev,
2590 "failed to allocate sysfs resources\n");
2591 } else {
2592 adapter->ets = false;
2593 }
2594#endif
56cec249
CW		 2595 /* Check if Media Autosense is enabled */
2596 adapter->ei = *ei;
2597 if (hw->dev_spec._82575.mas_capable)
2598 igb_init_mas(adapter);
2599
673b8b70 2600 /* do hw tstamp init after resetting */
7ebae817 2601 igb_ptp_init(adapter);
673b8b70 2602
9d5c8243 2603 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2604 /* print bus type/speed/width info, not applicable to i354 */
2605 if (hw->mac.type != e1000_i354) {
2606 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2607 netdev->name,
2608 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2609 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2610 "unknown"),
2611 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2612 "Width x4" :
2613 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2614 "Width x2" :
2615 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2616 "Width x1" : "unknown"), netdev->dev_addr);
2617 }
9d5c8243 2618
53ea6c7e
TF		 2619 if ((hw->mac.type >= e1000_i210 ||
2620 igb_get_flash_presence_i210(hw))) {
2621 ret_val = igb_read_part_string(hw, part_str,
2622 E1000_PBANUM_LENGTH);
2623 } else {
2624 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2625 }
2626
9835fd73
CW		 2627 if (ret_val)
2628 strcpy(part_str, "Unknown");
2629 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2630 dev_info(&pdev->dev,
2631 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2632 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2633 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2634 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2635 if (hw->phy.media_type == e1000_media_type_copper) {
2636 switch (hw->mac.type) {
2637 case e1000_i350:
2638 case e1000_i210:
2639 case e1000_i211:
2640 /* Enable EEE for internal copper PHY devices */
c4c112f1 2641 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2642 if ((!err) &&
2643 (!hw->dev_spec._82575.eee_disable)) {
2644 adapter->eee_advert =
2645 MDIO_EEE_100TX | MDIO_EEE_1000T;
2646 adapter->flags |= IGB_FLAG_EEE;
2647 }
2648 break;
2649 case e1000_i354:
ceb5f13b 2650 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2651 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2652 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2653 if ((!err) &&
2654 (!hw->dev_spec._82575.eee_disable)) {
2655 adapter->eee_advert =
2656 MDIO_EEE_100TX | MDIO_EEE_1000T;
2657 adapter->flags |= IGB_FLAG_EEE;
2658 }
2659 }
2660 break;
2661 default:
2662 break;
ceb5f13b 2663 }
09b068d4 2664 }
749ab2cd 2665 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2666 return 0;
2667
2668err_register:
2669 igb_release_hw_control(adapter);
441fc6fd 2670 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2671err_eeprom:
2672 if (!igb_check_reset_block(hw))
f5f4cf08 2673 igb_reset_phy(hw);
9d5c8243
AK		 2674
2675 if (hw->flash_address)
2676 iounmap(hw->flash_address);
9d5c8243 2677err_sw_init:
42ad1a03 2678 kfree(adapter->shadow_vfta);
047e0030 2679 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2680#ifdef CONFIG_PCI_IOV
2681 igb_disable_sriov(pdev);
2682#endif
73bf8048 2683 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2684err_ioremap:
2685 free_netdev(netdev);
2686err_alloc_etherdev:
559e9c49 2687 pci_release_selected_regions(pdev,
b980ac18 2688 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2689err_pci_reg:
2690err_dma:
2691 pci_disable_device(pdev);
2692 return err;
2693}
2694
fa44f2f1 2695#ifdef CONFIG_PCI_IOV
781798a1 2696static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2697{
2698 struct net_device *netdev = pci_get_drvdata(pdev);
2699 struct igb_adapter *adapter = netdev_priv(netdev);
2700 struct e1000_hw *hw = &adapter->hw;
2701
2702 /* reclaim resources allocated to VFs */
2703 if (adapter->vf_data) {
2704 /* disable iov and allow time for transactions to clear */
b09186d2 2705 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2706 dev_warn(&pdev->dev,
2707 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2708 return -EPERM;
2709 } else {
2710 pci_disable_sriov(pdev);
2711 msleep(500);
2712 }
2713
2714 kfree(adapter->vf_data);
2715 adapter->vf_data = NULL;
2716 adapter->vfs_allocated_count = 0;
2717 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2718 wrfl();
2719 msleep(100);
2720 dev_info(&pdev->dev, "IOV Disabled\n");
2721
2722 /* Re-enable DMA Coalescing flag since IOV is turned off */
2723 adapter->flags |= IGB_FLAG_DMAC;
2724 }
2725
2726 return 0;
2727}
2728
2729static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2730{
2731 struct net_device *netdev = pci_get_drvdata(pdev);
2732 struct igb_adapter *adapter = netdev_priv(netdev);
2733 int old_vfs = pci_num_vf(pdev);
2734 int err = 0;
2735 int i;
2736
cd14ef54 2737 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2738 err = -EPERM;
2739 goto out;
2740 }
fa44f2f1
GR		 2741 if (!num_vfs)
2742 goto out;
fa44f2f1 2743
781798a1
SA		 2744 if (old_vfs) {
2745 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2746 old_vfs, max_vfs);
2747 adapter->vfs_allocated_count = old_vfs;
2748 } else
2749 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2750
2751 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2752 sizeof(struct vf_data_storage), GFP_KERNEL);
2753
2754 /* if allocation failed then we do not support SR-IOV */
2755 if (!adapter->vf_data) {
2756 adapter->vfs_allocated_count = 0;
2757 dev_err(&pdev->dev,
2758 "Unable to allocate memory for VF Data Storage\n");
2759 err = -ENOMEM;
2760 goto out;
2761 }
2762
781798a1
SA		 2763 /* only call pci_enable_sriov() if no VFs are allocated already */
2764 if (!old_vfs) {
2765 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2766 if (err)
2767 goto err_out;
2768 }
fa44f2f1
GR		 2769 dev_info(&pdev->dev, "%d VFs allocated\n",
2770 adapter->vfs_allocated_count);
2771 for (i = 0; i < adapter->vfs_allocated_count; i++)
2772 igb_vf_configure(adapter, i);
2773
2774 /* DMA Coalescing is not supported in IOV mode. */
2775 adapter->flags &= ~IGB_FLAG_DMAC;
2776 goto out;
2777
2778err_out:
2779 kfree(adapter->vf_data);
2780 adapter->vf_data = NULL;
2781 adapter->vfs_allocated_count = 0;
2782out:
2783 return err;
2784}
2785
2786#endif
b980ac18 2787/**
441fc6fd
CW		 2788 * igb_remove_i2c - Cleanup I2C interface
2789 * @adapter: pointer to adapter structure
b980ac18 2790 **/
441fc6fd
CW		 2791static void igb_remove_i2c(struct igb_adapter *adapter)
2792{
441fc6fd
CW		 2793 /* free the adapter bus structure */
2794 i2c_del_adapter(&adapter->i2c_adap);
2795}
2796
9d5c8243 2797/**
b980ac18
JK		 2798 * igb_remove - Device Removal Routine
2799 * @pdev: PCI device information struct
9d5c8243 2800 *
b980ac18
JK		 2801 * igb_remove is called by the PCI subsystem to alert the driver
2802 * that it should release a PCI device. The could be caused by a
2803 * Hot-Plug event, or because the driver is going to be removed from
2804 * memory.
9d5c8243 2805 **/
9f9a12f8 2806static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2807{
2808 struct net_device *netdev = pci_get_drvdata(pdev);
2809 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2810 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2811
749ab2cd 2812 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2813#ifdef CONFIG_IGB_HWMON
2814 igb_sysfs_exit(adapter);
2815#endif
441fc6fd 2816 igb_remove_i2c(adapter);
a79f4f88 2817 igb_ptp_stop(adapter);
b980ac18 2818 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2819 * disable watchdog from being rescheduled.
2820 */
9d5c8243
AK		 2821 set_bit(__IGB_DOWN, &adapter->state);
2822 del_timer_sync(&adapter->watchdog_timer);
2823 del_timer_sync(&adapter->phy_info_timer);
2824
760141a5
TH		 2825 cancel_work_sync(&adapter->reset_task);
2826 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2827
421e02f0 2828#ifdef CONFIG_IGB_DCA
7dfc16fa 2829 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2830 dev_info(&pdev->dev, "DCA disabled\n");
2831 dca_remove_requester(&pdev->dev);
7dfc16fa 2832 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2833 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2834 }
2835#endif
2836
9d5c8243 2837 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2838 * would have already happened in close and is redundant.
2839 */
9d5c8243
AK		 2840 igb_release_hw_control(adapter);
2841
37680117 2842#ifdef CONFIG_PCI_IOV
fa44f2f1 2843 igb_disable_sriov(pdev);
37680117 2844#endif
559e9c49 2845
c23d92b8
AW		 2846 unregister_netdev(netdev);
2847
2848 igb_clear_interrupt_scheme(adapter);
2849
73bf8048 2850 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2851 if (hw->flash_address)
2852 iounmap(hw->flash_address);
559e9c49 2853 pci_release_selected_regions(pdev,
b980ac18 2854 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2855
1128c756 2856 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2857 free_netdev(netdev);
2858
19d5afd4 2859 pci_disable_pcie_error_reporting(pdev);
40a914fa 2860
9d5c8243
AK		 2861 pci_disable_device(pdev);
2862}
2863
a6b623e0 2864/**
b980ac18
JK		 2865 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2866 * @adapter: board private structure to initialize
a6b623e0 2867 *
b980ac18
JK		 2868 * This function initializes the vf specific data storage and then attempts to
2869 * allocate the VFs. The reason for ordering it this way is because it is much
2870 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2871 * the memory for the VFs.
a6b623e0 2872 **/
9f9a12f8 2873static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2874{
2875#ifdef CONFIG_PCI_IOV
2876 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2877 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2878
f96a8a0b
CW		 2879 /* Virtualization features not supported on i210 family. */
2880 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2881 return;
2882
be06998f
JB		 2883 /* Of the below we really only want the effect of getting
2884 * IGB_FLAG_HAS_MSIX set (if available), without which
2885 * igb_enable_sriov() has no effect.
2886 */
2887 igb_set_interrupt_capability(adapter, true);
2888 igb_reset_interrupt_capability(adapter);
2889
fa44f2f1 2890 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2891 igb_enable_sriov(pdev, max_vfs);
0224d663 2892
a6b623e0
AD		 2893#endif /* CONFIG_PCI_IOV */
2894}
2895
fa44f2f1 2896static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2897{
2898 struct e1000_hw *hw = &adapter->hw;
374a542d 2899 u32 max_rss_queues;
9d5c8243 2900
374a542d 2901 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2902 switch (hw->mac.type) {
374a542d
MV		 2903 case e1000_i211:
2904 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2905 break;
2906 case e1000_82575:
f96a8a0b 2907 case e1000_i210:
374a542d
MV		 2908 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2909 break;
2910 case e1000_i350:
2911 /* I350 cannot do RSS and SR-IOV at the same time */
2912 if (!!adapter->vfs_allocated_count) {
2913 max_rss_queues = 1;
2914 break;
2915 }
2916 /* fall through */
2917 case e1000_82576:
2918 if (!!adapter->vfs_allocated_count) {
2919 max_rss_queues = 2;
2920 break;
2921 }
2922 /* fall through */
2923 case e1000_82580:
ceb5f13b 2924 case e1000_i354:
374a542d
MV		 2925 default:
2926 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2927 break;
374a542d
MV		 2928 }
2929
2930 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2931
72ddef05
SS		 2932 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2933}
2934
2935void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2936 const u32 max_rss_queues)
2937{
2938 struct e1000_hw *hw = &adapter->hw;
2939
374a542d
MV		 2940 /* Determine if we need to pair queues. */
2941 switch (hw->mac.type) {
2942 case e1000_82575:
f96a8a0b 2943 case e1000_i211:
374a542d 2944 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2945 break;
374a542d 2946 case e1000_82576:
374a542d
MV		 2947 case e1000_82580:
2948 case e1000_i350:
ceb5f13b 2949 case e1000_i354:
374a542d 2950 case e1000_i210:
f96a8a0b 2951 default:
b980ac18 2952 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2953 * order to conserve interrupts due to limited supply.
2954 */
2955 if (adapter->rss_queues > (max_rss_queues / 2))
2956 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
37a5d163
SS		 2957 else
2958 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2959 break;
2960 }
fa44f2f1
GR		 2961}
2962
2963/**
b980ac18
JK		 2964 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2965 * @adapter: board private structure to initialize
fa44f2f1 2966 *
b980ac18
JK		 2967 * igb_sw_init initializes the Adapter private data structure.
2968 * Fields are initialized based on PCI device information and
2969 * OS network device settings (MTU size).
fa44f2f1
GR		 2970 **/
2971static int igb_sw_init(struct igb_adapter *adapter)
2972{
2973 struct e1000_hw *hw = &adapter->hw;
2974 struct net_device *netdev = adapter->netdev;
2975 struct pci_dev *pdev = adapter->pdev;
2976
2977 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2978
2979 /* set default ring sizes */
2980 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2981 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2982
2983 /* set default ITR values */
2984 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2985 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2986
2987 /* set default work limits */
2988 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2989
2990 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2991 VLAN_HLEN;
2992 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2993
2994 spin_lock_init(&adapter->stats64_lock);
2995#ifdef CONFIG_PCI_IOV
2996 switch (hw->mac.type) {
2997 case e1000_82576:
2998 case e1000_i350:
2999 if (max_vfs > 7) {
3000 dev_warn(&pdev->dev,
3001 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 3002 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 3003 } else
3004 adapter->vfs_allocated_count = max_vfs;
3005 if (adapter->vfs_allocated_count)
3006 dev_warn(&pdev->dev,
3007 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3008 break;
3009 default:
3010 break;
3011 }
3012#endif /* CONFIG_PCI_IOV */
3013
cbfe360a
SA		 3014 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3015 adapter->flags |= IGB_FLAG_HAS_MSIX;
3016
ceee3450
TF		 3017 igb_probe_vfs(adapter);
3018
fa44f2f1 3019 igb_init_queue_configuration(adapter);
a99955fc 3020
1128c756 3021 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 3022 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3023 GFP_ATOMIC);
1128c756 3024
a6b623e0 3025 /* This call may decrease the number of queues */
53c7d064 3026 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3027 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3028 return -ENOMEM;
3029 }
3030
3031 /* Explicitly disable IRQ since the NIC can be in any state. */
3032 igb_irq_disable(adapter);
3033
f96a8a0b 3034 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3035 adapter->flags &= ~IGB_FLAG_DMAC;
3036
9d5c8243
AK		 3037 set_bit(__IGB_DOWN, &adapter->state);
3038 return 0;
3039}
3040
3041/**
b980ac18
JK		 3042 * igb_open - Called when a network interface is made active
3043 * @netdev: network interface device structure
9d5c8243 3044 *
b980ac18 3045 * Returns 0 on success, negative value on failure
9d5c8243 3046 *
b980ac18
JK		 3047 * The open entry point is called when a network interface is made
3048 * active by the system (IFF_UP). At this point all resources needed
3049 * for transmit and receive operations are allocated, the interrupt
3050 * handler is registered with the OS, the watchdog timer is started,
3051 * and the stack is notified that the interface is ready.
9d5c8243 3052 **/
749ab2cd 3053static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3054{
3055 struct igb_adapter *adapter = netdev_priv(netdev);
3056 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3057 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3058 int err;
3059 int i;
3060
3061 /* disallow open during test */
749ab2cd
YZ		 3062 if (test_bit(__IGB_TESTING, &adapter->state)) {
3063 WARN_ON(resuming);
9d5c8243 3064 return -EBUSY;
749ab2cd
YZ		 3065 }
3066
3067 if (!resuming)
3068 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3069
b168dfc5
JB		 3070 netif_carrier_off(netdev);
3071
9d5c8243
AK		 3072 /* allocate transmit descriptors */
3073 err = igb_setup_all_tx_resources(adapter);
3074 if (err)
3075 goto err_setup_tx;
3076
3077 /* allocate receive descriptors */
3078 err = igb_setup_all_rx_resources(adapter);
3079 if (err)
3080 goto err_setup_rx;
3081
88a268c1 3082 igb_power_up_link(adapter);
9d5c8243 3083
9d5c8243
AK		 3084 /* before we allocate an interrupt, we must be ready to handle it.
3085 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3086 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3087 * clean_rx handler before we do so.
3088 */
9d5c8243
AK		 3089 igb_configure(adapter);
3090
3091 err = igb_request_irq(adapter);
3092 if (err)
3093 goto err_req_irq;
3094
0c2cc02e
AD		 3095 /* Notify the stack of the actual queue counts. */
3096 err = netif_set_real_num_tx_queues(adapter->netdev,
3097 adapter->num_tx_queues);
3098 if (err)
3099 goto err_set_queues;
3100
3101 err = netif_set_real_num_rx_queues(adapter->netdev,
3102 adapter->num_rx_queues);
3103 if (err)
3104 goto err_set_queues;
3105
9d5c8243
AK		 3106 /* From here on the code is the same as igb_up() */
3107 clear_bit(__IGB_DOWN, &adapter->state);
3108
0d1ae7f4
AD		 3109 for (i = 0; i < adapter->num_q_vectors; i++)
3110 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3111
3112 /* Clear any pending interrupts. */
3113 rd32(E1000_ICR);
844290e5
PW		 3114
3115 igb_irq_enable(adapter);
3116
d4960307
AD		 3117 /* notify VFs that reset has been completed */
3118 if (adapter->vfs_allocated_count) {
3119 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3120
d4960307
AD		 3121 reg_data |= E1000_CTRL_EXT_PFRSTD;
3122 wr32(E1000_CTRL_EXT, reg_data);
3123 }
3124
d55b53ff
JK		 3125 netif_tx_start_all_queues(netdev);
3126
749ab2cd
YZ		 3127 if (!resuming)
3128 pm_runtime_put(&pdev->dev);
3129
25568a53
AD		 3130 /* start the watchdog. */
3131 hw->mac.get_link_status = 1;
3132 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3133
3134 return 0;
3135
0c2cc02e
AD		 3136err_set_queues:
3137 igb_free_irq(adapter);
9d5c8243
AK		 3138err_req_irq:
3139 igb_release_hw_control(adapter);
88a268c1 3140 igb_power_down_link(adapter);
9d5c8243
AK		 3141 igb_free_all_rx_resources(adapter);
3142err_setup_rx:
3143 igb_free_all_tx_resources(adapter);
3144err_setup_tx:
3145 igb_reset(adapter);
749ab2cd
YZ		 3146 if (!resuming)
3147 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3148
3149 return err;
3150}
3151
749ab2cd
YZ		 3152static int igb_open(struct net_device *netdev)
3153{
3154 return __igb_open(netdev, false);
3155}
3156
9d5c8243 3157/**
b980ac18
JK		 3158 * igb_close - Disables a network interface
3159 * @netdev: network interface device structure
9d5c8243 3160 *
b980ac18 3161 * Returns 0, this is not allowed to fail
9d5c8243 3162 *
b980ac18
JK		 3163 * The close entry point is called when an interface is de-activated
3164 * by the OS. The hardware is still under the driver's control, but
3165 * needs to be disabled. A global MAC reset is issued to stop the
3166 * hardware, and all transmit and receive resources are freed.
9d5c8243 3167 **/
749ab2cd 3168static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3169{
3170 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3171 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3172
3173 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3174
749ab2cd
YZ		 3175 if (!suspending)
3176 pm_runtime_get_sync(&pdev->dev);
3177
3178 igb_down(adapter);
9d5c8243
AK		 3179 igb_free_irq(adapter);
3180
3181 igb_free_all_tx_resources(adapter);
3182 igb_free_all_rx_resources(adapter);
3183
749ab2cd
YZ		 3184 if (!suspending)
3185 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3186 return 0;
3187}
3188
749ab2cd
YZ		 3189static int igb_close(struct net_device *netdev)
3190{
3191 return __igb_close(netdev, false);
3192}
3193
9d5c8243 3194/**
b980ac18
JK		 3195 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3196 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3197 *
b980ac18 3198 * Return 0 on success, negative on failure
9d5c8243 3199 **/
80785298 3200int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3201{
59d71989 3202 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3203 int size;
3204
06034649 3205 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3206
3207 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3208 if (!tx_ring->tx_buffer_info)
9d5c8243 3209 goto err;
9d5c8243
AK		 3210
3211 /* round up to nearest 4K */
85e8d004 3212 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3213 tx_ring->size = ALIGN(tx_ring->size, 4096);
3214
5536d210
AD		 3215 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3216 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3217 if (!tx_ring->desc)
3218 goto err;
3219
9d5c8243
AK		 3220 tx_ring->next_to_use = 0;
3221 tx_ring->next_to_clean = 0;
81c2fc22 3222
9d5c8243
AK		 3223 return 0;
3224
3225err:
06034649 3226 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3227 tx_ring->tx_buffer_info = NULL;
3228 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3229 return -ENOMEM;
3230}
3231
3232/**
b980ac18
JK		 3233 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3234 * (Descriptors) for all queues
3235 * @adapter: board private structure
9d5c8243 3236 *
b980ac18 3237 * Return 0 on success, negative on failure
9d5c8243
AK		 3238 **/
3239static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3240{
439705e1 3241 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3242 int i, err = 0;
3243
3244 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3245 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3246 if (err) {
439705e1 3247 dev_err(&pdev->dev,
9d5c8243
AK		 3248 "Allocation for Tx Queue %u failed\n", i);
3249 for (i--; i >= 0; i--)
3025a446 3250 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3251 break;
3252 }
3253 }
3254
3255 return err;
3256}
3257
3258/**
b980ac18
JK		 3259 * igb_setup_tctl - configure the transmit control registers
3260 * @adapter: Board private structure
9d5c8243 3261 **/
d7ee5b3a 3262void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3263{
9d5c8243
AK		 3264 struct e1000_hw *hw = &adapter->hw;
3265 u32 tctl;
9d5c8243 3266
85b430b4
AD		 3267 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3268 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3269
3270 /* Program the Transmit Control Register */
9d5c8243
AK		 3271 tctl = rd32(E1000_TCTL);
3272 tctl &= ~E1000_TCTL_CT;
3273 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3274 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3275
3276 igb_config_collision_dist(hw);
3277
9d5c8243
AK		 3278 /* Enable transmits */
3279 tctl |= E1000_TCTL_EN;
3280
3281 wr32(E1000_TCTL, tctl);
3282}
3283
85b430b4 3284/**
b980ac18
JK		 3285 * igb_configure_tx_ring - Configure transmit ring after Reset
3286 * @adapter: board private structure
3287 * @ring: tx ring to configure
85b430b4 3288 *
b980ac18 3289 * Configure a transmit ring after a reset.
85b430b4 3290 **/
d7ee5b3a 3291void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3292 struct igb_ring *ring)
85b430b4
AD		 3293{
3294 struct e1000_hw *hw = &adapter->hw;
a74420e0 3295 u32 txdctl = 0;
85b430b4
AD		 3296 u64 tdba = ring->dma;
3297 int reg_idx = ring->reg_idx;
3298
3299 /* disable the queue */
a74420e0 3300 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3301 wrfl();
3302 mdelay(10);
3303
3304 wr32(E1000_TDLEN(reg_idx),
b980ac18 3305 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3306 wr32(E1000_TDBAL(reg_idx),
b980ac18 3307 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3308 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3309
fce99e34 3310 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3311 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3312 writel(0, ring->tail);
85b430b4
AD		 3313
3314 txdctl |= IGB_TX_PTHRESH;
3315 txdctl |= IGB_TX_HTHRESH << 8;
3316 txdctl |= IGB_TX_WTHRESH << 16;
3317
3318 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3319 wr32(E1000_TXDCTL(reg_idx), txdctl);
3320}
3321
3322/**
b980ac18
JK		 3323 * igb_configure_tx - Configure transmit Unit after Reset
3324 * @adapter: board private structure
85b430b4 3325 *
b980ac18 3326 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3327 **/
3328static void igb_configure_tx(struct igb_adapter *adapter)
3329{
3330 int i;
3331
3332 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3333 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3334}
3335
9d5c8243 3336/**
b980ac18
JK		 3337 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3338 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3339 *
b980ac18 3340 * Returns 0 on success, negative on failure
9d5c8243 3341 **/
80785298 3342int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3343{
59d71989 3344 struct device *dev = rx_ring->dev;
f33005a6 3345 int size;
9d5c8243 3346
06034649 3347 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3348
3349 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3350 if (!rx_ring->rx_buffer_info)
9d5c8243 3351 goto err;
9d5c8243 3352
9d5c8243 3353 /* Round up to nearest 4K */
f33005a6 3354 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3355 rx_ring->size = ALIGN(rx_ring->size, 4096);
3356
5536d210
AD		 3357 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3358 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3359 if (!rx_ring->desc)
3360 goto err;
3361
cbc8e55f 3362 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3363 rx_ring->next_to_clean = 0;
3364 rx_ring->next_to_use = 0;
9d5c8243 3365
9d5c8243
AK		 3366 return 0;
3367
3368err:
06034649
AD		 3369 vfree(rx_ring->rx_buffer_info);
3370 rx_ring->rx_buffer_info = NULL;
f33005a6 3371 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3372 return -ENOMEM;
3373}
3374
3375/**
b980ac18
JK		 3376 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3377 * (Descriptors) for all queues
3378 * @adapter: board private structure
9d5c8243 3379 *
b980ac18 3380 * Return 0 on success, negative on failure
9d5c8243
AK		 3381 **/
3382static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3383{
439705e1 3384 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3385 int i, err = 0;
3386
3387 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3388 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3389 if (err) {
439705e1 3390 dev_err(&pdev->dev,
9d5c8243
AK		 3391 "Allocation for Rx Queue %u failed\n", i);
3392 for (i--; i >= 0; i--)
3025a446 3393 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3394 break;
3395 }
3396 }
3397
3398 return err;
3399}
3400
06cf2666 3401/**
b980ac18
JK		 3402 * igb_setup_mrqc - configure the multiple receive queue control registers
3403 * @adapter: Board private structure
06cf2666
AD		 3404 **/
3405static void igb_setup_mrqc(struct igb_adapter *adapter)
3406{
3407 struct e1000_hw *hw = &adapter->hw;
3408 u32 mrqc, rxcsum;
ed12cc9a 3409 u32 j, num_rx_queues;
eb31f849 3410 u32 rss_key[10];
06cf2666 3411
eb31f849 3412 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3413 for (j = 0; j < 10; j++)
eb31f849 3414 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3415
a99955fc 3416 num_rx_queues = adapter->rss_queues;
06cf2666 3417
797fd4be 3418 switch (hw->mac.type) {
797fd4be
AD		 3419 case e1000_82576:
3420 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3421 if (adapter->vfs_allocated_count)
06cf2666 3422 num_rx_queues = 2;
797fd4be
AD		 3423 break;
3424 default:
3425 break;
06cf2666
AD		 3426 }
3427
ed12cc9a
LMV		 3428 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3429 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3430 adapter->rss_indir_tbl[j] =
3431 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3432 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3433 }
ed12cc9a 3434 igb_write_rss_indir_tbl(adapter);
06cf2666 3435
b980ac18 3436 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3437 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3438 * offloads as they are enabled by default
3439 */
3440 rxcsum = rd32(E1000_RXCSUM);
3441 rxcsum |= E1000_RXCSUM_PCSD;
3442
3443 if (adapter->hw.mac.type >= e1000_82576)
3444 /* Enable Receive Checksum Offload for SCTP */
3445 rxcsum |= E1000_RXCSUM_CRCOFL;
3446
3447 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3448 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3449
039454a8
AA		 3450 /* Generate RSS hash based on packet types, TCP/UDP
3451 * port numbers and/or IPv4/v6 src and dst addresses
3452 */
f96a8a0b
CW		 3453 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3454 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3455 E1000_MRQC_RSS_FIELD_IPV6 |
3456 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3457 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3458
039454a8
AA		 3459 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3460 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3461 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3462 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3463
06cf2666
AD		 3464 /* If VMDq is enabled then we set the appropriate mode for that, else
3465 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3466 * if we are only using one queue
3467 */
06cf2666
AD		 3468 if (adapter->vfs_allocated_count) {
3469 if (hw->mac.type > e1000_82575) {
3470 /* Set the default pool for the PF's first queue */
3471 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3472
06cf2666
AD		 3473 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3474 E1000_VT_CTL_DISABLE_DEF_POOL);
3475 vtctl |= adapter->vfs_allocated_count <<
3476 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3477 wr32(E1000_VT_CTL, vtctl);
3478 }
a99955fc 3479 if (adapter->rss_queues > 1)
f96a8a0b 3480 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3481 else
f96a8a0b 3482 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3483 } else {
f96a8a0b
CW		 3484 if (hw->mac.type != e1000_i211)
3485 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3486 }
3487 igb_vmm_control(adapter);
3488
06cf2666
AD		 3489 wr32(E1000_MRQC, mrqc);
3490}
3491
9d5c8243 3492/**
b980ac18
JK		 3493 * igb_setup_rctl - configure the receive control registers
3494 * @adapter: Board private structure
9d5c8243 3495 **/
d7ee5b3a 3496void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3497{
3498 struct e1000_hw *hw = &adapter->hw;
3499 u32 rctl;
9d5c8243
AK		 3500
3501 rctl = rd32(E1000_RCTL);
3502
3503 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3504 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3505
69d728ba 3506 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3507 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3508
b980ac18 3509 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3510 * redirection as it did with e1000. Newer features require
3511 * that the HW strips the CRC.
73cd78f1 3512 */
87cb7e8c 3513 rctl |= E1000_RCTL_SECRC;
9d5c8243 3514
559e9c49 3515 /* disable store bad packets and clear size bits. */
ec54d7d6 3516 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3517
45693bcb 3518 /* enable LPE to allow for reception of jumbo frames */
6ec43fe6 3519 rctl |= E1000_RCTL_LPE;
9d5c8243 3520
952f72a8
AD		 3521 /* disable queue 0 to prevent tail write w/o re-config */
3522 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3523
e1739522
AD		 3524 /* Attention!!! For SR-IOV PF driver operations you must enable
3525 * queue drop for all VF and PF queues to prevent head of line blocking
3526 * if an un-trusted VF does not provide descriptors to hardware.
3527 */
3528 if (adapter->vfs_allocated_count) {
e1739522
AD		 3529 /* set all queue drop enable bits */
3530 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3531 }
3532
89eaefb6
BG		 3533 /* This is useful for sniffing bad packets. */
3534 if (adapter->netdev->features & NETIF_F_RXALL) {
3535 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3536 * in e1000e_set_rx_mode
3537 */
89eaefb6
BG		 3538 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3539 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3540 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3541
16903caa 3542 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
89eaefb6
BG		 3543 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3544 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3545 * and that breaks VLANs.
3546 */
3547 }
3548
9d5c8243
AK		 3549 wr32(E1000_RCTL, rctl);
3550}
3551
7d5753f0 3552static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3553 int vfn)
7d5753f0
AD		 3554{
3555 struct e1000_hw *hw = &adapter->hw;
3556 u32 vmolr;
3557
d3836f8e
AD		 3558 if (size > MAX_JUMBO_FRAME_SIZE)
3559 size = MAX_JUMBO_FRAME_SIZE;
7d5753f0
AD		 3560
3561 vmolr = rd32(E1000_VMOLR(vfn));
3562 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3563 vmolr |= size | E1000_VMOLR_LPE;
3564 wr32(E1000_VMOLR(vfn), vmolr);
3565
3566 return 0;
3567}
3568
8151d294
WM		 3569static inline void igb_set_vmolr(struct igb_adapter *adapter,
3570 int vfn, bool aupe)
7d5753f0
AD		 3571{
3572 struct e1000_hw *hw = &adapter->hw;
3573 u32 vmolr;
3574
b980ac18 3575 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3576 * we should exit and do nothing
3577 */
3578 if (hw->mac.type < e1000_82576)
3579 return;
3580
3581 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3582 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3583 if (hw->mac.type == e1000_i350) {
3584 u32 dvmolr;
3585
3586 dvmolr = rd32(E1000_DVMOLR(vfn));
3587 dvmolr |= E1000_DVMOLR_STRVLAN;
3588 wr32(E1000_DVMOLR(vfn), dvmolr);
3589 }
8151d294 3590 if (aupe)
b980ac18 3591 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3592 else
3593 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3594
3595 /* clear all bits that might not be set */
3596 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3597
a99955fc 3598 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3599 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3600 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3601 * multicast packets
3602 */
3603 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3604 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3605
3606 wr32(E1000_VMOLR(vfn), vmolr);
3607}
3608
85b430b4 3609/**
b980ac18
JK		 3610 * igb_configure_rx_ring - Configure a receive ring after Reset
3611 * @adapter: board private structure
3612 * @ring: receive ring to be configured
85b430b4 3613 *
b980ac18 3614 * Configure the Rx unit of the MAC after a reset.
85b430b4 3615 **/
d7ee5b3a 3616void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3617 struct igb_ring *ring)
85b430b4
AD		 3618{
3619 struct e1000_hw *hw = &adapter->hw;
3620 u64 rdba = ring->dma;
3621 int reg_idx = ring->reg_idx;
a74420e0 3622 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3623
3624 /* disable the queue */
a74420e0 3625 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3626
3627 /* Set DMA base address registers */
3628 wr32(E1000_RDBAL(reg_idx),
3629 rdba & 0x00000000ffffffffULL);
3630 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3631 wr32(E1000_RDLEN(reg_idx),
b980ac18 3632 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3633
3634 /* initialize head and tail */
fce99e34 3635 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3636 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3637 writel(0, ring->tail);
85b430b4 3638
952f72a8 3639 /* set descriptor configuration */
44390ca6 3640 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3641 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3642 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3643 if (hw->mac.type >= e1000_82580)
757b77e2 3644 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3645 /* Only set Drop Enable if we are supporting multiple queues */
3646 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3647 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3648
3649 wr32(E1000_SRRCTL(reg_idx), srrctl);
3650
7d5753f0 3651 /* set filtering for VMDQ pools */
8151d294 3652 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3653
85b430b4
AD		 3654 rxdctl |= IGB_RX_PTHRESH;
3655 rxdctl |= IGB_RX_HTHRESH << 8;
3656 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3657
3658 /* enable receive descriptor fetching */
3659 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3660 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3661}
3662
9d5c8243 3663/**
b980ac18
JK		 3664 * igb_configure_rx - Configure receive Unit after Reset
3665 * @adapter: board private structure
9d5c8243 3666 *
b980ac18 3667 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3668 **/
3669static void igb_configure_rx(struct igb_adapter *adapter)
3670{
9107584e 3671 int i;
9d5c8243 3672
68d480c4
AD		 3673 /* set UTA to appropriate mode */
3674 igb_set_uta(adapter);
3675
26ad9178
AD		 3676 /* set the correct pool for the PF default MAC address in entry 0 */
3677 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3678 adapter->vfs_allocated_count);
26ad9178 3679
06cf2666 3680 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3681 * the Base and Length of the Rx Descriptor Ring
3682 */
f9d40f6a
AD		 3683 for (i = 0; i < adapter->num_rx_queues; i++)
3684 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3685}
3686
3687/**
b980ac18
JK		 3688 * igb_free_tx_resources - Free Tx Resources per Queue
3689 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3690 *
b980ac18 3691 * Free all transmit software resources
9d5c8243 3692 **/
68fd9910 3693void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3694{
3b644cf6 3695 igb_clean_tx_ring(tx_ring);
9d5c8243 3696
06034649
AD		 3697 vfree(tx_ring->tx_buffer_info);
3698 tx_ring->tx_buffer_info = NULL;
9d5c8243 3699
439705e1
AD		 3700 /* if not set, then don't free */
3701 if (!tx_ring->desc)
3702 return;
3703
59d71989
AD		 3704 dma_free_coherent(tx_ring->dev, tx_ring->size,
3705 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3706
3707 tx_ring->desc = NULL;
3708}
3709
3710/**
b980ac18
JK		 3711 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3712 * @adapter: board private structure
9d5c8243 3713 *
b980ac18 3714 * Free all transmit software resources
9d5c8243
AK		 3715 **/
3716static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3717{
3718 int i;
3719
3720 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3721 if (adapter->tx_ring[i])
3722 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3723}
3724
ebe42d16
AD		 3725void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3726 struct igb_tx_buffer *tx_buffer)
3727{
3728 if (tx_buffer->skb) {
3729 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3730 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3731 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3732 dma_unmap_addr(tx_buffer, dma),
3733 dma_unmap_len(tx_buffer, len),
ebe42d16 3734 DMA_TO_DEVICE);
c9f14bf3 3735 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3736 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3737 dma_unmap_addr(tx_buffer, dma),
3738 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3739 DMA_TO_DEVICE);
3740 }
3741 tx_buffer->next_to_watch = NULL;
3742 tx_buffer->skb = NULL;
c9f14bf3 3743 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3744 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3745}
3746
3747/**
b980ac18
JK		 3748 * igb_clean_tx_ring - Free Tx Buffers
3749 * @tx_ring: ring to be cleaned
9d5c8243 3750 **/
3b644cf6 3751static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3752{
06034649 3753 struct igb_tx_buffer *buffer_info;
9d5c8243 3754 unsigned long size;
6ad4edfc 3755 u16 i;
9d5c8243 3756
06034649 3757 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3758 return;
3759 /* Free all the Tx ring sk_buffs */
3760
3761 for (i = 0; i < tx_ring->count; i++) {
06034649 3762 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3763 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3764 }
3765
dad8a3b3
JF		 3766 netdev_tx_reset_queue(txring_txq(tx_ring));
3767
06034649
AD		 3768 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3769 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3770
3771 /* Zero out the descriptor ring */
9d5c8243
AK		 3772 memset(tx_ring->desc, 0, tx_ring->size);
3773
3774 tx_ring->next_to_use = 0;
3775 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3776}
3777
3778/**
b980ac18
JK		 3779 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3780 * @adapter: board private structure
9d5c8243
AK		 3781 **/
3782static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3783{
3784 int i;
3785
3786 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3787 if (adapter->tx_ring[i])
3788 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3789}
3790
3791/**
b980ac18
JK		 3792 * igb_free_rx_resources - Free Rx Resources
3793 * @rx_ring: ring to clean the resources from
9d5c8243 3794 *
b980ac18 3795 * Free all receive software resources
9d5c8243 3796 **/
68fd9910 3797void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3798{
3b644cf6 3799 igb_clean_rx_ring(rx_ring);
9d5c8243 3800
06034649
AD		 3801 vfree(rx_ring->rx_buffer_info);
3802 rx_ring->rx_buffer_info = NULL;
9d5c8243 3803
439705e1
AD		 3804 /* if not set, then don't free */
3805 if (!rx_ring->desc)
3806 return;
3807
59d71989
AD		 3808 dma_free_coherent(rx_ring->dev, rx_ring->size,
3809 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3810
3811 rx_ring->desc = NULL;
3812}
3813
3814/**
b980ac18
JK		 3815 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3816 * @adapter: board private structure
9d5c8243 3817 *
b980ac18 3818 * Free all receive software resources
9d5c8243
AK		 3819 **/
3820static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3821{
3822 int i;
3823
3824 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3825 if (adapter->rx_ring[i])
3826 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3827}
3828
3829/**
b980ac18
JK		 3830 * igb_clean_rx_ring - Free Rx Buffers per Queue
3831 * @rx_ring: ring to free buffers from
9d5c8243 3832 **/
3b644cf6 3833static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3834{
9d5c8243 3835 unsigned long size;
c023cd88 3836 u16 i;
9d5c8243 3837
1a1c225b
AD		 3838 if (rx_ring->skb)
3839 dev_kfree_skb(rx_ring->skb);
3840 rx_ring->skb = NULL;
3841
06034649 3842 if (!rx_ring->rx_buffer_info)
9d5c8243 3843 return;
439705e1 3844
9d5c8243
AK		 3845 /* Free all the Rx ring sk_buffs */
3846 for (i = 0; i < rx_ring->count; i++) {
06034649 3847 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3848
cbc8e55f
AD		 3849 if (!buffer_info->page)
3850 continue;
3851
3852 dma_unmap_page(rx_ring->dev,
3853 buffer_info->dma,
3854 PAGE_SIZE,
3855 DMA_FROM_DEVICE);
3856 __free_page(buffer_info->page);
3857
1a1c225b 3858 buffer_info->page = NULL;
9d5c8243
AK		 3859 }
3860
06034649
AD		 3861 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3862 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3863
3864 /* Zero out the descriptor ring */
3865 memset(rx_ring->desc, 0, rx_ring->size);
3866
cbc8e55f 3867 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3868 rx_ring->next_to_clean = 0;
3869 rx_ring->next_to_use = 0;
9d5c8243
AK		 3870}
3871
3872/**
b980ac18
JK		 3873 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3874 * @adapter: board private structure
9d5c8243
AK		 3875 **/
3876static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3877{
3878 int i;
3879
3880 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3881 if (adapter->rx_ring[i])
3882 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3883}
3884
3885/**
b980ac18
JK		 3886 * igb_set_mac - Change the Ethernet Address of the NIC
3887 * @netdev: network interface device structure
3888 * @p: pointer to an address structure
9d5c8243 3889 *
b980ac18 3890 * Returns 0 on success, negative on failure
9d5c8243
AK		 3891 **/
3892static int igb_set_mac(struct net_device *netdev, void *p)
3893{
3894 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3895 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3896 struct sockaddr *addr = p;
3897
3898 if (!is_valid_ether_addr(addr->sa_data))
3899 return -EADDRNOTAVAIL;
3900
3901 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3902 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3903
26ad9178
AD		 3904 /* set the correct pool for the new PF MAC address in entry 0 */
3905 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3906 adapter->vfs_allocated_count);
e1739522 3907
9d5c8243
AK		 3908 return 0;
3909}
3910
3911/**
b980ac18
JK		 3912 * igb_write_mc_addr_list - write multicast addresses to MTA
3913 * @netdev: network interface device structure
9d5c8243 3914 *
b980ac18
JK		 3915 * Writes multicast address list to the MTA hash table.
3916 * Returns: -ENOMEM on failure
3917 * 0 on no addresses written
3918 * X on writing X addresses to MTA
9d5c8243 3919 **/
68d480c4 3920static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3921{
3922 struct igb_adapter *adapter = netdev_priv(netdev);
3923 struct e1000_hw *hw = &adapter->hw;
22bedad3 3924 struct netdev_hw_addr *ha;
68d480c4 3925 u8 *mta_list;
9d5c8243
AK		 3926 int i;
3927
4cd24eaf 3928 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3929 /* nothing to program, so clear mc list */
3930 igb_update_mc_addr_list(hw, NULL, 0);
3931 igb_restore_vf_multicasts(adapter);
3932 return 0;
3933 }
9d5c8243 3934
4cd24eaf 3935 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3936 if (!mta_list)
3937 return -ENOMEM;
ff41f8dc 3938
68d480c4 3939 /* The shared function expects a packed array of only addresses. */
48e2f183 3940 i = 0;
22bedad3
JP		 3941 netdev_for_each_mc_addr(ha, netdev)
3942 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3943
68d480c4
AD		 3944 igb_update_mc_addr_list(hw, mta_list, i);
3945 kfree(mta_list);
3946
4cd24eaf 3947 return netdev_mc_count(netdev);
68d480c4
AD		 3948}
3949
3950/**
b980ac18
JK		 3951 * igb_write_uc_addr_list - write unicast addresses to RAR table
3952 * @netdev: network interface device structure
68d480c4 3953 *
b980ac18
JK		 3954 * Writes unicast address list to the RAR table.
3955 * Returns: -ENOMEM on failure/insufficient address space
3956 * 0 on no addresses written
3957 * X on writing X addresses to the RAR table
68d480c4
AD		 3958 **/
3959static int igb_write_uc_addr_list(struct net_device *netdev)
3960{
3961 struct igb_adapter *adapter = netdev_priv(netdev);
3962 struct e1000_hw *hw = &adapter->hw;
3963 unsigned int vfn = adapter->vfs_allocated_count;
3964 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3965 int count = 0;
3966
3967 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3968 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3969 return -ENOMEM;
9d5c8243 3970
32e7bfc4 3971 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3972 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3973
3974 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3975 if (!rar_entries)
3976 break;
26ad9178 3977 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3978 rar_entries--,
3979 vfn);
68d480c4 3980 count++;
ff41f8dc
AD		 3981 }
3982 }
3983 /* write the addresses in reverse order to avoid write combining */
3984 for (; rar_entries > 0 ; rar_entries--) {
3985 wr32(E1000_RAH(rar_entries), 0);
3986 wr32(E1000_RAL(rar_entries), 0);
3987 }
3988 wrfl();
3989
68d480c4
AD		 3990 return count;
3991}
3992
16903caa
AD		 3993static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
3994{
3995 struct e1000_hw *hw = &adapter->hw;
3996 u32 i, pf_id;
3997
3998 switch (hw->mac.type) {
3999 case e1000_i210:
4000 case e1000_i211:
4001 case e1000_i350:
4002 /* VLAN filtering needed for VLAN prio filter */
4003 if (adapter->netdev->features & NETIF_F_NTUPLE)
4004 break;
4005 /* fall through */
4006 case e1000_82576:
4007 case e1000_82580:
4008 case e1000_i354:
4009 /* VLAN filtering needed for pool filtering */
4010 if (adapter->vfs_allocated_count)
4011 break;
4012 /* fall through */
4013 default:
4014 return 1;
4015 }
4016
4017 /* We are already in VLAN promisc, nothing to do */
4018 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4019 return 0;
4020
4021 if (!adapter->vfs_allocated_count)
4022 goto set_vfta;
4023
4024 /* Add PF to all active pools */
4025 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4026
4027 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4028 u32 vlvf = rd32(E1000_VLVF(i));
4029
4030 vlvf |= 1 << pf_id;
4031 wr32(E1000_VLVF(i), vlvf);
4032 }
4033
4034set_vfta:
4035 /* Set all bits in the VLAN filter table array */
4036 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4037 hw->mac.ops.write_vfta(hw, i, ~0U);
4038
4039 /* Set flag so we don't redo unnecessary work */
4040 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4041
4042 return 0;
4043}
4044
4045#define VFTA_BLOCK_SIZE 8
4046static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4047{
4048 struct e1000_hw *hw = &adapter->hw;
4049 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4050 u32 vid_start = vfta_offset * 32;
4051 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4052 u32 i, vid, word, bits, pf_id;
4053
4054 /* guarantee that we don't scrub out management VLAN */
4055 vid = adapter->mng_vlan_id;
4056 if (vid >= vid_start && vid < vid_end)
4057 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4058
4059 if (!adapter->vfs_allocated_count)
4060 goto set_vfta;
4061
4062 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4063
4064 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4065 u32 vlvf = rd32(E1000_VLVF(i));
4066
4067 /* pull VLAN ID from VLVF */
4068 vid = vlvf & VLAN_VID_MASK;
4069
4070 /* only concern ourselves with a certain range */
4071 if (vid < vid_start || vid >= vid_end)
4072 continue;
4073
4074 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4075 /* record VLAN ID in VFTA */
4076 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4077
4078 /* if PF is part of this then continue */
4079 if (test_bit(vid, adapter->active_vlans))
4080 continue;
4081 }
4082
4083 /* remove PF from the pool */
4084 bits = ~(1 << pf_id);
4085 bits &= rd32(E1000_VLVF(i));
4086 wr32(E1000_VLVF(i), bits);
4087 }
4088
4089set_vfta:
4090 /* extract values from active_vlans and write back to VFTA */
4091 for (i = VFTA_BLOCK_SIZE; i--;) {
4092 vid = (vfta_offset + i) * 32;
4093 word = vid / BITS_PER_LONG;
4094 bits = vid % BITS_PER_LONG;
4095
4096 vfta[i] |= adapter->active_vlans[word] >> bits;
4097
4098 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4099 }
4100}
4101
4102static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4103{
4104 u32 i;
4105
4106 /* We are not in VLAN promisc, nothing to do */
4107 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4108 return;
4109
4110 /* Set flag so we don't redo unnecessary work */
4111 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4112
4113 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4114 igb_scrub_vfta(adapter, i);
4115}
4116
68d480c4 4117/**
b980ac18
JK		 4118 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4119 * @netdev: network interface device structure
68d480c4 4120 *
b980ac18
JK		 4121 * The set_rx_mode entry point is called whenever the unicast or multicast
4122 * address lists or the network interface flags are updated. This routine is
4123 * responsible for configuring the hardware for proper unicast, multicast,
4124 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4125 **/
4126static void igb_set_rx_mode(struct net_device *netdev)
4127{
4128 struct igb_adapter *adapter = netdev_priv(netdev);
4129 struct e1000_hw *hw = &adapter->hw;
4130 unsigned int vfn = adapter->vfs_allocated_count;
16903caa 4131 u32 rctl = 0, vmolr = 0;
68d480c4
AD		 4132 int count;
4133
4134 /* Check for Promiscuous and All Multicast modes */
68d480c4 4135 if (netdev->flags & IFF_PROMISC) {
16903caa
AD		 4136 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
4137 vmolr |= E1000_VMOLR_ROPE | E1000_VMOLR_MPME;
68d480c4
AD		 4138 } else {
4139 if (netdev->flags & IFF_ALLMULTI) {
4140 rctl |= E1000_RCTL_MPE;
4141 vmolr |= E1000_VMOLR_MPME;
4142 } else {
b980ac18 4143 /* Write addresses to the MTA, if the attempt fails
25985edc 4144 * then we should just turn on promiscuous mode so
68d480c4
AD		 4145 * that we can at least receive multicast traffic
4146 */
4147 count = igb_write_mc_addr_list(netdev);
4148 if (count < 0) {
4149 rctl |= E1000_RCTL_MPE;
4150 vmolr |= E1000_VMOLR_MPME;
4151 } else if (count) {
4152 vmolr |= E1000_VMOLR_ROMPE;
4153 }
4154 }
268f9d33
AD		 4155 }
4156
4157 /* Write addresses to available RAR registers, if there is not
4158 * sufficient space to store all the addresses then enable
4159 * unicast promiscuous mode
4160 */
4161 count = igb_write_uc_addr_list(netdev);
4162 if (count < 0) {
4163 rctl |= E1000_RCTL_UPE;
4164 vmolr |= E1000_VMOLR_ROPE;
28fc06f5 4165 }
16903caa
AD		 4166
4167 /* enable VLAN filtering by default */
4168 rctl |= E1000_RCTL_VFE;
4169
4170 /* disable VLAN filtering for modes that require it */
4171 if ((netdev->flags & IFF_PROMISC) ||
4172 (netdev->features & NETIF_F_RXALL)) {
4173 /* if we fail to set all rules then just clear VFE */
4174 if (igb_vlan_promisc_enable(adapter))
4175 rctl &= ~E1000_RCTL_VFE;
4176 } else {
4177 igb_vlan_promisc_disable(adapter);
4178 }
4179
4180 /* update state of unicast, multicast, and VLAN filtering modes */
4181 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4182 E1000_RCTL_VFE);
68d480c4 4183 wr32(E1000_RCTL, rctl);
28fc06f5 4184
b980ac18 4185 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4186 * the VMOLR to enable the appropriate modes. Without this workaround
4187 * we will have issues with VLAN tag stripping not being done for frames
4188 * that are only arriving because we are the default pool
4189 */
f96a8a0b 4190 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4191 return;
9d5c8243 4192
68d480c4 4193 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4194 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
45693bcb
AD		 4195
4196 /* enable Rx jumbo frames, no need for restriction */
4197 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4198 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4199
68d480c4 4200 wr32(E1000_VMOLR(vfn), vmolr);
45693bcb
AD		 4201 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4202
28fc06f5 4203 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4204}
4205
13800469
GR		 4206static void igb_check_wvbr(struct igb_adapter *adapter)
4207{
4208 struct e1000_hw *hw = &adapter->hw;
4209 u32 wvbr = 0;
4210
4211 switch (hw->mac.type) {
4212 case e1000_82576:
4213 case e1000_i350:
81ad807b
CW		 4214 wvbr = rd32(E1000_WVBR);
4215 if (!wvbr)
13800469
GR		 4216 return;
4217 break;
4218 default:
4219 break;
4220 }
4221
4222 adapter->wvbr |= wvbr;
4223}
4224
4225#define IGB_STAGGERED_QUEUE_OFFSET 8
4226
4227static void igb_spoof_check(struct igb_adapter *adapter)
4228{
4229 int j;
4230
4231 if (!adapter->wvbr)
4232 return;
4233
9005df38 4234 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4235 if (adapter->wvbr & (1 << j) ||
4236 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4237 dev_warn(&adapter->pdev->dev,
4238 "Spoof event(s) detected on VF %d\n", j);
4239 adapter->wvbr &=
4240 ~((1 << j) |
4241 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4242 }
4243 }
4244}
4245
9d5c8243 4246/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4247 * the phy
4248 */
9d5c8243
AK		 4249static void igb_update_phy_info(unsigned long data)
4250{
4251 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4252 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4253}
4254
4d6b725e 4255/**
b980ac18
JK		 4256 * igb_has_link - check shared code for link and determine up/down
4257 * @adapter: pointer to driver private info
4d6b725e 4258 **/
3145535a 4259bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4260{
4261 struct e1000_hw *hw = &adapter->hw;
4262 bool link_active = false;
4d6b725e
AD		 4263
4264 /* get_link_status is set on LSC (link status) interrupt or
4265 * rx sequence error interrupt. get_link_status will stay
4266 * false until the e1000_check_for_link establishes link
4267 * for copper adapters ONLY
4268 */
4269 switch (hw->phy.media_type) {
4270 case e1000_media_type_copper:
e5c3370f
AA		 4271 if (!hw->mac.get_link_status)
4272 return true;
4d6b725e 4273 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4274 hw->mac.ops.check_for_link(hw);
4275 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4276 break;
4277 default:
4278 case e1000_media_type_unknown:
4279 break;
4280 }
4281
aa9b8cc4
AA		 4282 if (((hw->mac.type == e1000_i210) ||
4283 (hw->mac.type == e1000_i211)) &&
4284 (hw->phy.id == I210_I_PHY_ID)) {
4285 if (!netif_carrier_ok(adapter->netdev)) {
4286 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4287 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4288 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4289 adapter->link_check_timeout = jiffies;
4290 }
4291 }
4292
4d6b725e
AD		 4293 return link_active;
4294}
4295
563988dc
SA		 4296static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4297{
4298 bool ret = false;
4299 u32 ctrl_ext, thstat;
4300
f96a8a0b 4301 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4302 if (hw->mac.type == e1000_i350) {
4303 thstat = rd32(E1000_THSTAT);
4304 ctrl_ext = rd32(E1000_CTRL_EXT);
4305
4306 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4307 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4308 ret = !!(thstat & event);
563988dc
SA		 4309 }
4310
4311 return ret;
4312}
4313
1516f0a6
CW		 4314/**
4315 * igb_check_lvmmc - check for malformed packets received
4316 * and indicated in LVMMC register
4317 * @adapter: pointer to adapter
4318 **/
4319static void igb_check_lvmmc(struct igb_adapter *adapter)
4320{
4321 struct e1000_hw *hw = &adapter->hw;
4322 u32 lvmmc;
4323
4324 lvmmc = rd32(E1000_LVMMC);
4325 if (lvmmc) {
4326 if (unlikely(net_ratelimit())) {
4327 netdev_warn(adapter->netdev,
4328 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4329 lvmmc);
4330 }
4331 }
4332}
4333
9d5c8243 4334/**
b980ac18
JK		 4335 * igb_watchdog - Timer Call-back
4336 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4337 **/
4338static void igb_watchdog(unsigned long data)
4339{
4340 struct igb_adapter *adapter = (struct igb_adapter *)data;
4341 /* Do the rest outside of interrupt context */
4342 schedule_work(&adapter->watchdog_task);
4343}
4344
4345static void igb_watchdog_task(struct work_struct *work)
4346{
4347 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4348 struct igb_adapter,
4349 watchdog_task);
9d5c8243 4350 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4351 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4352 struct net_device *netdev = adapter->netdev;
563988dc 4353 u32 link;
7a6ea550 4354 int i;
56cec249 4355 u32 connsw;
9d5c8243 4356
4d6b725e 4357 link = igb_has_link(adapter);
aa9b8cc4
AA		 4358
4359 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4360 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4361 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4362 else
4363 link = false;
4364 }
4365
56cec249
CW		 4366 /* Force link down if we have fiber to swap to */
4367 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4368 if (hw->phy.media_type == e1000_media_type_copper) {
4369 connsw = rd32(E1000_CONNSW);
4370 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4371 link = 0;
4372 }
4373 }
9d5c8243 4374 if (link) {
2bdfc4e2
CW		 4375 /* Perform a reset if the media type changed. */
4376 if (hw->dev_spec._82575.media_changed) {
4377 hw->dev_spec._82575.media_changed = false;
4378 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4379 igb_reset(adapter);
4380 }
749ab2cd
YZ		 4381 /* Cancel scheduled suspend requests. */
4382 pm_runtime_resume(netdev->dev.parent);
4383
9d5c8243
AK		 4384 if (!netif_carrier_ok(netdev)) {
4385 u32 ctrl;
9005df38 4386
330a6d6a 4387 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4388 &adapter->link_speed,
4389 &adapter->link_duplex);
9d5c8243
AK		 4390
4391 ctrl = rd32(E1000_CTRL);
527d47c1 4392 /* Links status message must follow this format */
c75c4edf
CW		 4393 netdev_info(netdev,
4394 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4395 netdev->name,
4396 adapter->link_speed,
4397 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4398 "Full" : "Half",
4399 (ctrl & E1000_CTRL_TFCE) &&
4400 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4401 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4402 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4403
f4c01e96
CW		 4404 /* disable EEE if enabled */
4405 if ((adapter->flags & IGB_FLAG_EEE) &&
4406 (adapter->link_duplex == HALF_DUPLEX)) {
4407 dev_info(&adapter->pdev->dev,
4408 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4409 adapter->hw.dev_spec._82575.eee_disable = true;
4410 adapter->flags &= ~IGB_FLAG_EEE;
4411 }
4412
c0ba4778
KS		 4413 /* check if SmartSpeed worked */
4414 igb_check_downshift(hw);
4415 if (phy->speed_downgraded)
4416 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4417
563988dc 4418 /* check for thermal sensor event */
876d2d6f 4419 if (igb_thermal_sensor_event(hw,
d34a15ab 4420 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4421 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4422
d07f3e37 4423 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4424 adapter->tx_timeout_factor = 1;
4425 switch (adapter->link_speed) {
4426 case SPEED_10:
9d5c8243
AK		 4427 adapter->tx_timeout_factor = 14;
4428 break;
4429 case SPEED_100:
9d5c8243
AK		 4430 /* maybe add some timeout factor ? */
4431 break;
4432 }
4433
4434 netif_carrier_on(netdev);
9d5c8243 4435
4ae196df 4436 igb_ping_all_vfs(adapter);
17dc566c 4437 igb_check_vf_rate_limit(adapter);
4ae196df 4438
4b1a9877 4439 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4440 if (!test_bit(__IGB_DOWN, &adapter->state))
4441 mod_timer(&adapter->phy_info_timer,
4442 round_jiffies(jiffies + 2 * HZ));
4443 }
4444 } else {
4445 if (netif_carrier_ok(netdev)) {
4446 adapter->link_speed = 0;
4447 adapter->link_duplex = 0;
563988dc
SA		 4448
4449 /* check for thermal sensor event */
876d2d6f
JK		 4450 if (igb_thermal_sensor_event(hw,
4451 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4452 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4453 }
563988dc 4454
527d47c1 4455 /* Links status message must follow this format */
c75c4edf 4456 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4457 netdev->name);
9d5c8243 4458 netif_carrier_off(netdev);
4b1a9877 4459
4ae196df
AD		 4460 igb_ping_all_vfs(adapter);
4461
4b1a9877 4462 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4463 if (!test_bit(__IGB_DOWN, &adapter->state))
4464 mod_timer(&adapter->phy_info_timer,
4465 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4466
56cec249
CW		 4467 /* link is down, time to check for alternate media */
4468 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4469 igb_check_swap_media(adapter);
4470 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4471 schedule_work(&adapter->reset_task);
4472 /* return immediately */
4473 return;
4474 }
4475 }
749ab2cd
YZ		 4476 pm_schedule_suspend(netdev->dev.parent,
4477 MSEC_PER_SEC * 5);
56cec249
CW		 4478
4479 /* also check for alternate media here */
4480 } else if (!netif_carrier_ok(netdev) &&
4481 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4482 igb_check_swap_media(adapter);
4483 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4484 schedule_work(&adapter->reset_task);
4485 /* return immediately */
4486 return;
4487 }
9d5c8243
AK		 4488 }
4489 }
4490
12dcd86b
ED		 4491 spin_lock(&adapter->stats64_lock);
4492 igb_update_stats(adapter, &adapter->stats64);
4493 spin_unlock(&adapter->stats64_lock);
9d5c8243 4494
dbabb065 4495 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4496 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4497 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4498 /* We've lost link, so the controller stops DMA,
4499 * but we've got queued Tx work that's never going
4500 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4501 * (Do the reset outside of interrupt context).
4502 */
dbabb065
AD		 4503 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4504 adapter->tx_timeout_count++;
4505 schedule_work(&adapter->reset_task);
4506 /* return immediately since reset is imminent */
4507 return;
4508 }
9d5c8243 4509 }
9d5c8243 4510
dbabb065 4511 /* Force detection of hung controller every watchdog period */
6d095fa8 4512 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4513 }
f7ba205e 4514
b980ac18 4515 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4516 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4517 u32 eics = 0;
9005df38 4518
0d1ae7f4
AD		 4519 for (i = 0; i < adapter->num_q_vectors; i++)
4520 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4521 wr32(E1000_EICS, eics);
4522 } else {
4523 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4524 }
9d5c8243 4525
13800469 4526 igb_spoof_check(adapter);
fc580751 4527 igb_ptp_rx_hang(adapter);
13800469 4528
1516f0a6
CW		 4529 /* Check LVMMC register on i350/i354 only */
4530 if ((adapter->hw.mac.type == e1000_i350) ||
4531 (adapter->hw.mac.type == e1000_i354))
4532 igb_check_lvmmc(adapter);
4533
9d5c8243 4534 /* Reset the timer */
aa9b8cc4
AA		 4535 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4536 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4537 mod_timer(&adapter->watchdog_timer,
4538 round_jiffies(jiffies + HZ));
4539 else
4540 mod_timer(&adapter->watchdog_timer,
4541 round_jiffies(jiffies + 2 * HZ));
4542 }
9d5c8243
AK		 4543}
4544
4545enum latency_range {
4546 lowest_latency = 0,
4547 low_latency = 1,
4548 bulk_latency = 2,
4549 latency_invalid = 255
4550};
4551
6eb5a7f1 4552/**
b980ac18
JK		 4553 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4554 * @q_vector: pointer to q_vector
6eb5a7f1 4555 *
b980ac18
JK		 4556 * Stores a new ITR value based on strictly on packet size. This
4557 * algorithm is less sophisticated than that used in igb_update_itr,
4558 * due to the difficulty of synchronizing statistics across multiple
4559 * receive rings. The divisors and thresholds used by this function
4560 * were determined based on theoretical maximum wire speed and testing
4561 * data, in order to minimize response time while increasing bulk
4562 * throughput.
406d4965 4563 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4564 * NOTE: This function is called only when operating in a multiqueue
4565 * receive environment.
6eb5a7f1 4566 **/
047e0030 4567static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4568{
047e0030 4569 int new_val = q_vector->itr_val;
6eb5a7f1 4570 int avg_wire_size = 0;
047e0030 4571 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4572 unsigned int packets;
9d5c8243 4573
6eb5a7f1
AD		 4574 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4575 * ints/sec - ITR timer value of 120 ticks.
4576 */
4577 if (adapter->link_speed != SPEED_1000) {
0ba82994 4578 new_val = IGB_4K_ITR;
6eb5a7f1 4579 goto set_itr_val;
9d5c8243 4580 }
047e0030 4581
0ba82994
AD		 4582 packets = q_vector->rx.total_packets;
4583 if (packets)
4584 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4585
0ba82994
AD		 4586 packets = q_vector->tx.total_packets;
4587 if (packets)
4588 avg_wire_size = max_t(u32, avg_wire_size,
4589 q_vector->tx.total_bytes / packets);
047e0030
AD		 4590
4591 /* if avg_wire_size isn't set no work was done */
4592 if (!avg_wire_size)
4593 goto clear_counts;
9d5c8243 4594
6eb5a7f1
AD		 4595 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4596 avg_wire_size += 24;
4597
4598 /* Don't starve jumbo frames */
4599 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4600
6eb5a7f1
AD		 4601 /* Give a little boost to mid-size frames */
4602 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4603 new_val = avg_wire_size / 3;
4604 else
4605 new_val = avg_wire_size / 2;
9d5c8243 4606
0ba82994
AD		 4607 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4608 if (new_val < IGB_20K_ITR &&
4609 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4610 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4611 new_val = IGB_20K_ITR;
abe1c363 4612
6eb5a7f1 4613set_itr_val:
047e0030
AD		 4614 if (new_val != q_vector->itr_val) {
4615 q_vector->itr_val = new_val;
4616 q_vector->set_itr = 1;
9d5c8243 4617 }
6eb5a7f1 4618clear_counts:
0ba82994
AD		 4619 q_vector->rx.total_bytes = 0;
4620 q_vector->rx.total_packets = 0;
4621 q_vector->tx.total_bytes = 0;
4622 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4623}
4624
4625/**
b980ac18
JK		 4626 * igb_update_itr - update the dynamic ITR value based on statistics
4627 * @q_vector: pointer to q_vector
4628 * @ring_container: ring info to update the itr for
4629 *
4630 * Stores a new ITR value based on packets and byte
4631 * counts during the last interrupt. The advantage of per interrupt
4632 * computation is faster updates and more accurate ITR for the current
4633 * traffic pattern. Constants in this function were computed
4634 * based on theoretical maximum wire speed and thresholds were set based
4635 * on testing data as well as attempting to minimize response time
4636 * while increasing bulk throughput.
406d4965 4637 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4638 * NOTE: These calculations are only valid when operating in a single-
4639 * queue environment.
9d5c8243 4640 **/
0ba82994
AD		 4641static void igb_update_itr(struct igb_q_vector *q_vector,
4642 struct igb_ring_container *ring_container)
9d5c8243 4643{
0ba82994
AD		 4644 unsigned int packets = ring_container->total_packets;
4645 unsigned int bytes = ring_container->total_bytes;
4646 u8 itrval = ring_container->itr;
9d5c8243 4647
0ba82994 4648 /* no packets, exit with status unchanged */
9d5c8243 4649 if (packets == 0)
0ba82994 4650 return;
9d5c8243 4651
0ba82994 4652 switch (itrval) {
9d5c8243
AK		 4653 case lowest_latency:
4654 /* handle TSO and jumbo frames */
4655 if (bytes/packets > 8000)
0ba82994 4656 itrval = bulk_latency;
9d5c8243 4657 else if ((packets < 5) && (bytes > 512))
0ba82994 4658 itrval = low_latency;
9d5c8243
AK		 4659 break;
4660 case low_latency: /* 50 usec aka 20000 ints/s */
4661 if (bytes > 10000) {
4662 /* this if handles the TSO accounting */
d34a15ab 4663 if (bytes/packets > 8000)
0ba82994 4664 itrval = bulk_latency;
d34a15ab 4665 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4666 itrval = bulk_latency;
d34a15ab 4667 else if ((packets > 35))
0ba82994 4668 itrval = lowest_latency;
9d5c8243 4669 } else if (bytes/packets > 2000) {
0ba82994 4670 itrval = bulk_latency;
9d5c8243 4671 } else if (packets <= 2 && bytes < 512) {
0ba82994 4672 itrval = lowest_latency;
9d5c8243
AK		 4673 }
4674 break;
4675 case bulk_latency: /* 250 usec aka 4000 ints/s */
4676 if (bytes > 25000) {
4677 if (packets > 35)
0ba82994 4678 itrval = low_latency;
1e5c3d21 4679 } else if (bytes < 1500) {
0ba82994 4680 itrval = low_latency;
9d5c8243
AK		 4681 }
4682 break;
4683 }
4684
0ba82994
AD		 4685 /* clear work counters since we have the values we need */
4686 ring_container->total_bytes = 0;
4687 ring_container->total_packets = 0;
4688
4689 /* write updated itr to ring container */
4690 ring_container->itr = itrval;
9d5c8243
AK		 4691}
4692
0ba82994 4693static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4694{
0ba82994 4695 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4696 u32 new_itr = q_vector->itr_val;
0ba82994 4697 u8 current_itr = 0;
9d5c8243
AK		 4698
4699 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4700 if (adapter->link_speed != SPEED_1000) {
4701 current_itr = 0;
0ba82994 4702 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4703 goto set_itr_now;
4704 }
4705
0ba82994
AD		 4706 igb_update_itr(q_vector, &q_vector->tx);
4707 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4708
0ba82994 4709 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4710
6eb5a7f1 4711 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4712 if (current_itr == lowest_latency &&
4713 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4714 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4715 current_itr = low_latency;
4716
9d5c8243
AK		 4717 switch (current_itr) {
4718 /* counts and packets in update_itr are dependent on these numbers */
4719 case lowest_latency:
0ba82994 4720 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4721 break;
4722 case low_latency:
0ba82994 4723 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4724 break;
4725 case bulk_latency:
0ba82994 4726 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4727 break;
4728 default:
4729 break;
4730 }
4731
4732set_itr_now:
047e0030 4733 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4734 /* this attempts to bias the interrupt rate towards Bulk
4735 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4736 * increasing
4737 */
047e0030 4738 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4739 max((new_itr * q_vector->itr_val) /
4740 (new_itr + (q_vector->itr_val >> 2)),
4741 new_itr) : new_itr;
9d5c8243
AK		 4742 /* Don't write the value here; it resets the adapter's
4743 * internal timer, and causes us to delay far longer than
4744 * we should between interrupts. Instead, we write the ITR
4745 * value at the beginning of the next interrupt so the timing
4746 * ends up being correct.
4747 */
047e0030
AD		 4748 q_vector->itr_val = new_itr;
4749 q_vector->set_itr = 1;
9d5c8243 4750 }
9d5c8243
AK		 4751}
4752
c50b52a0
SH		 4753static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4754 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4755{
4756 struct e1000_adv_tx_context_desc *context_desc;
4757 u16 i = tx_ring->next_to_use;
4758
4759 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4760
4761 i++;
4762 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4763
4764 /* set bits to identify this as an advanced context descriptor */
4765 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4766
4767 /* For 82575, context index must be unique per ring. */
866cff06 4768 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4769 mss_l4len_idx |= tx_ring->reg_idx << 4;
4770
4771 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4772 context_desc->seqnum_seed = 0;
4773 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4774 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4775}
4776
7af40ad9
AD		 4777static int igb_tso(struct igb_ring *tx_ring,
4778 struct igb_tx_buffer *first,
4779 u8 *hdr_len)
9d5c8243 4780{
7af40ad9 4781 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4782 u32 vlan_macip_lens, type_tucmd;
4783 u32 mss_l4len_idx, l4len;
06c14e5a 4784 int err;
7d13a7d0 4785
ed6aa105
AD		 4786 if (skb->ip_summed != CHECKSUM_PARTIAL)
4787 return 0;
4788
7d13a7d0
AD		 4789 if (!skb_is_gso(skb))
4790 return 0;
9d5c8243 4791
06c14e5a
FR		 4792 err = skb_cow_head(skb, 0);
4793 if (err < 0)
4794 return err;
9d5c8243 4795
7d13a7d0
AD		 4796 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4797 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4798
7c4d16ff 4799 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4800 struct iphdr *iph = ip_hdr(skb);
4801 iph->tot_len = 0;
4802 iph->check = 0;
4803 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4804 iph->daddr, 0,
4805 IPPROTO_TCP,
4806 0);
7d13a7d0 4807 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4808 first->tx_flags |= IGB_TX_FLAGS_TSO |
4809 IGB_TX_FLAGS_CSUM |
4810 IGB_TX_FLAGS_IPV4;
8e1e8a47 4811 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4812 ipv6_hdr(skb)->payload_len = 0;
4813 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4814 &ipv6_hdr(skb)->daddr,
4815 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4816 first->tx_flags |= IGB_TX_FLAGS_TSO |
4817 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4818 }
4819
7af40ad9 4820 /* compute header lengths */
7d13a7d0
AD		 4821 l4len = tcp_hdrlen(skb);
4822 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4823
7af40ad9
AD		 4824 /* update gso size and bytecount with header size */
4825 first->gso_segs = skb_shinfo(skb)->gso_segs;
4826 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4827
9d5c8243 4828 /* MSS L4LEN IDX */
7d13a7d0
AD		 4829 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4830 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4831
7d13a7d0
AD		 4832 /* VLAN MACLEN IPLEN */
4833 vlan_macip_lens = skb_network_header_len(skb);
4834 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4835 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4836
7d13a7d0 4837 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4838
7d13a7d0 4839 return 1;
9d5c8243
AK		 4840}
4841
7af40ad9 4842static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4843{
7af40ad9 4844 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4845 u32 vlan_macip_lens = 0;
4846 u32 mss_l4len_idx = 0;
4847 u32 type_tucmd = 0;
9d5c8243 4848
7d13a7d0 4849 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4850 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4851 return;
7d13a7d0
AD		 4852 } else {
4853 u8 l4_hdr = 0;
9005df38 4854
7af40ad9 4855 switch (first->protocol) {
7c4d16ff 4856 case htons(ETH_P_IP):
7d13a7d0
AD		 4857 vlan_macip_lens |= skb_network_header_len(skb);
4858 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4859 l4_hdr = ip_hdr(skb)->protocol;
4860 break;
7c4d16ff 4861 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4862 vlan_macip_lens |= skb_network_header_len(skb);
4863 l4_hdr = ipv6_hdr(skb)->nexthdr;
4864 break;
4865 default:
4866 if (unlikely(net_ratelimit())) {
4867 dev_warn(tx_ring->dev,
b980ac18
JK		 4868 "partial checksum but proto=%x!\n",
4869 first->protocol);
fa4a7ef3 4870 }
7d13a7d0
AD		 4871 break;
4872 }
fa4a7ef3 4873
7d13a7d0
AD		 4874 switch (l4_hdr) {
4875 case IPPROTO_TCP:
4876 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4877 mss_l4len_idx = tcp_hdrlen(skb) <<
4878 E1000_ADVTXD_L4LEN_SHIFT;
4879 break;
4880 case IPPROTO_SCTP:
4881 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4882 mss_l4len_idx = sizeof(struct sctphdr) <<
4883 E1000_ADVTXD_L4LEN_SHIFT;
4884 break;
4885 case IPPROTO_UDP:
4886 mss_l4len_idx = sizeof(struct udphdr) <<
4887 E1000_ADVTXD_L4LEN_SHIFT;
4888 break;
4889 default:
4890 if (unlikely(net_ratelimit())) {
4891 dev_warn(tx_ring->dev,
b980ac18
JK		 4892 "partial checksum but l4 proto=%x!\n",
4893 l4_hdr);
44b0cda3 4894 }
7d13a7d0 4895 break;
9d5c8243 4896 }
7af40ad9
AD		 4897
4898 /* update TX checksum flag */
4899 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4900 }
9d5c8243 4901
7d13a7d0 4902 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4903 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4904
7d13a7d0 4905 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4906}
4907
1d9daf45
AD		 4908#define IGB_SET_FLAG(_input, _flag, _result) \
4909 ((_flag <= _result) ? \
4910 ((u32)(_input & _flag) * (_result / _flag)) : \
4911 ((u32)(_input & _flag) / (_flag / _result)))
4912
4913static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4914{
4915 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4916 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4917 E1000_ADVTXD_DCMD_DEXT |
4918 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4919
4920 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4921 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4922 (E1000_ADVTXD_DCMD_VLE));
4923
4924 /* set segmentation bits for TSO */
4925 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4926 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4927
4928 /* set timestamp bit if present */
1d9daf45
AD		 4929 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4930 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4931
1d9daf45
AD		 4932 /* insert frame checksum */
4933 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4934
4935 return cmd_type;
4936}
4937
7af40ad9
AD		 4938static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4939 union e1000_adv_tx_desc *tx_desc,
4940 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4941{
4942 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4943
1d9daf45
AD		 4944 /* 82575 requires a unique index per ring */
4945 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4946 olinfo_status |= tx_ring->reg_idx << 4;
4947
4948 /* insert L4 checksum */
1d9daf45
AD		 4949 olinfo_status |= IGB_SET_FLAG(tx_flags,
4950 IGB_TX_FLAGS_CSUM,
4951 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4952
1d9daf45
AD		 4953 /* insert IPv4 checksum */
4954 olinfo_status |= IGB_SET_FLAG(tx_flags,
4955 IGB_TX_FLAGS_IPV4,
4956 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4957
7af40ad9 4958 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4959}
4960
6f19e12f
DM		 4961static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4962{
4963 struct net_device *netdev = tx_ring->netdev;
4964
4965 netif_stop_subqueue(netdev, tx_ring->queue_index);
4966
4967 /* Herbert's original patch had:
4968 * smp_mb__after_netif_stop_queue();
4969 * but since that doesn't exist yet, just open code it.
4970 */
4971 smp_mb();
4972
4973 /* We need to check again in a case another CPU has just
4974 * made room available.
4975 */
4976 if (igb_desc_unused(tx_ring) < size)
4977 return -EBUSY;
4978
4979 /* A reprieve! */
4980 netif_wake_subqueue(netdev, tx_ring->queue_index);
4981
4982 u64_stats_update_begin(&tx_ring->tx_syncp2);
4983 tx_ring->tx_stats.restart_queue2++;
4984 u64_stats_update_end(&tx_ring->tx_syncp2);
4985
4986 return 0;
4987}
4988
4989static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4990{
4991 if (igb_desc_unused(tx_ring) >= size)
4992 return 0;
4993 return __igb_maybe_stop_tx(tx_ring, size);
4994}
4995
7af40ad9
AD		 4996static void igb_tx_map(struct igb_ring *tx_ring,
4997 struct igb_tx_buffer *first,
ebe42d16 4998 const u8 hdr_len)
9d5c8243 4999{
7af40ad9 5000 struct sk_buff *skb = first->skb;
c9f14bf3 5001 struct igb_tx_buffer *tx_buffer;
ebe42d16 5002 union e1000_adv_tx_desc *tx_desc;
80d0759e 5003 struct skb_frag_struct *frag;
ebe42d16 5004 dma_addr_t dma;
80d0759e 5005 unsigned int data_len, size;
7af40ad9 5006 u32 tx_flags = first->tx_flags;
1d9daf45 5007 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 5008 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 5009
5010 tx_desc = IGB_TX_DESC(tx_ring, i);
5011
80d0759e
AD		 5012 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5013
5014 size = skb_headlen(skb);
5015 data_len = skb->data_len;
ebe42d16
AD		 5016
5017 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 5018
80d0759e
AD		 5019 tx_buffer = first;
5020
5021 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5022 if (dma_mapping_error(tx_ring->dev, dma))
5023 goto dma_error;
5024
5025 /* record length, and DMA address */
5026 dma_unmap_len_set(tx_buffer, len, size);
5027 dma_unmap_addr_set(tx_buffer, dma, dma);
5028
5029 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 5030
ebe42d16
AD		 5031 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5032 tx_desc->read.cmd_type_len =
1d9daf45 5033 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 5034
5035 i++;
5036 tx_desc++;
5037 if (i == tx_ring->count) {
5038 tx_desc = IGB_TX_DESC(tx_ring, 0);
5039 i = 0;
5040 }
80d0759e 5041 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 5042
5043 dma += IGB_MAX_DATA_PER_TXD;
5044 size -= IGB_MAX_DATA_PER_TXD;
5045
ebe42d16
AD		 5046 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5047 }
5048
5049 if (likely(!data_len))
5050 break;
2bbfebe2 5051
1d9daf45 5052 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 5053
65689fef 5054 i++;
ebe42d16
AD		 5055 tx_desc++;
5056 if (i == tx_ring->count) {
5057 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 5058 i = 0;
ebe42d16 5059 }
80d0759e 5060 tx_desc->read.olinfo_status = 0;
65689fef 5061
9e903e08 5062 size = skb_frag_size(frag);
ebe42d16
AD		 5063 data_len -= size;
5064
5065 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 5066 size, DMA_TO_DEVICE);
6366ad33 5067
c9f14bf3 5068 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 5069 }
5070
ebe42d16 5071 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 5072 cmd_type |= size | IGB_TXD_DCMD;
5073 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 5074
80d0759e
AD		 5075 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5076
8542db05
AD		 5077 /* set the timestamp */
5078 first->time_stamp = jiffies;
5079
b980ac18 5080 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 5081 * are new descriptors to fetch. (Only applicable for weak-ordered
5082 * memory model archs, such as IA-64).
5083 *
5084 * We also need this memory barrier to make certain all of the
5085 * status bits have been updated before next_to_watch is written.
5086 */
5087 wmb();
5088
8542db05 5089 /* set next_to_watch value indicating a packet is present */
ebe42d16 5090 first->next_to_watch = tx_desc;
9d5c8243 5091
ebe42d16
AD		 5092 i++;
5093 if (i == tx_ring->count)
5094 i = 0;
6366ad33 5095
ebe42d16 5096 tx_ring->next_to_use = i;
6366ad33 5097
6f19e12f
DM		 5098 /* Make sure there is space in the ring for the next send. */
5099 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5100
5101 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 5102 writel(i, tx_ring->tail);
5103
5104 /* we need this if more than one processor can write to our tail
5105 * at a time, it synchronizes IO on IA64/Altix systems
5106 */
5107 mmiowb();
5108 }
ebe42d16
AD		 5109 return;
5110
5111dma_error:
5112 dev_err(tx_ring->dev, "TX DMA map failed\n");
5113
5114 /* clear dma mappings for failed tx_buffer_info map */
5115 for (;;) {
c9f14bf3
AD		 5116 tx_buffer = &tx_ring->tx_buffer_info[i];
5117 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5118 if (tx_buffer == first)
ebe42d16 5119 break;
a77ff709
NN		 5120 if (i == 0)
5121 i = tx_ring->count;
6366ad33 5122 i--;
6366ad33
AD		 5123 }
5124
9d5c8243 5125 tx_ring->next_to_use = i;
9d5c8243
AK		 5126}
5127
cd392f5c
AD		 5128netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5129 struct igb_ring *tx_ring)
9d5c8243 5130{
8542db05 5131 struct igb_tx_buffer *first;
ebe42d16 5132 int tso;
91d4ee33 5133 u32 tx_flags = 0;
2ee52ad4 5134 unsigned short f;
21ba6fe1 5135 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5136 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5137 u8 hdr_len = 0;
9d5c8243 5138
21ba6fe1
AD		 5139 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5140 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5141 * + 2 desc gap to keep tail from touching head,
9d5c8243 5142 * + 1 desc for context descriptor,
21ba6fe1
AD		 5143 * otherwise try next time
5144 */
2ee52ad4
AD		 5145 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5146 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5147
5148 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5149 /* this is a hard error */
9d5c8243
AK		 5150 return NETDEV_TX_BUSY;
5151 }
33af6bcc 5152
7af40ad9
AD		 5153 /* record the location of the first descriptor for this packet */
5154 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5155 first->skb = skb;
5156 first->bytecount = skb->len;
5157 first->gso_segs = 1;
5158
b646c22e
AD		 5159 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5160 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5161
ed4420a3
JK		 5162 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5163 &adapter->state)) {
b646c22e
AD		 5164 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5165 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5166
5167 adapter->ptp_tx_skb = skb_get(skb);
5168 adapter->ptp_tx_start = jiffies;
5169 if (adapter->hw.mac.type == e1000_82576)
5170 schedule_work(&adapter->ptp_tx_work);
5171 }
33af6bcc 5172 }
9d5c8243 5173
afc835d1
JK		 5174 skb_tx_timestamp(skb);
5175
df8a39de 5176 if (skb_vlan_tag_present(skb)) {
9d5c8243 5177 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5178 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5179 }
5180
7af40ad9
AD		 5181 /* record initial flags and protocol */
5182 first->tx_flags = tx_flags;
5183 first->protocol = protocol;
cdfd01fc 5184
7af40ad9
AD		 5185 tso = igb_tso(tx_ring, first, &hdr_len);
5186 if (tso < 0)
7d13a7d0 5187 goto out_drop;
7af40ad9
AD		 5188 else if (!tso)
5189 igb_tx_csum(tx_ring, first);
9d5c8243 5190
7af40ad9 5191 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5192
9d5c8243 5193 return NETDEV_TX_OK;
7d13a7d0
AD		 5194
5195out_drop:
7af40ad9
AD		 5196 igb_unmap_and_free_tx_resource(tx_ring, first);
5197
7d13a7d0 5198 return NETDEV_TX_OK;
9d5c8243
AK		 5199}
5200
0b725a2c
DM		 5201static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5202 struct sk_buff *skb)
1cc3bd87 5203{
0b725a2c
DM		 5204 unsigned int r_idx = skb->queue_mapping;
5205
1cc3bd87
AD		 5206 if (r_idx >= adapter->num_tx_queues)
5207 r_idx = r_idx % adapter->num_tx_queues;
5208
5209 return adapter->tx_ring[r_idx];
5210}
5211
cd392f5c
AD		 5212static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5213 struct net_device *netdev)
9d5c8243
AK		 5214{
5215 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3 5216
b980ac18 5217 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5218 * in order to meet this minimum size requirement.
5219 */
a94d9e22
AD		 5220 if (skb_put_padto(skb, 17))
5221 return NETDEV_TX_OK;
9d5c8243 5222
1cc3bd87 5223 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5224}
5225
5226/**
b980ac18
JK		 5227 * igb_tx_timeout - Respond to a Tx Hang
5228 * @netdev: network interface device structure
9d5c8243
AK		 5229 **/
5230static void igb_tx_timeout(struct net_device *netdev)
5231{
5232 struct igb_adapter *adapter = netdev_priv(netdev);
5233 struct e1000_hw *hw = &adapter->hw;
5234
5235 /* Do the reset outside of interrupt context */
5236 adapter->tx_timeout_count++;
f7ba205e 5237
06218a8d 5238 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5239 hw->dev_spec._82575.global_device_reset = true;
5240
9d5c8243 5241 schedule_work(&adapter->reset_task);
265de409
AD		 5242 wr32(E1000_EICS,
5243 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5244}
5245
5246static void igb_reset_task(struct work_struct *work)
5247{
5248 struct igb_adapter *adapter;
5249 adapter = container_of(work, struct igb_adapter, reset_task);
5250
c97ec42a
TI		 5251 igb_dump(adapter);
5252 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5253 igb_reinit_locked(adapter);
5254}
5255
5256/**
b980ac18
JK		 5257 * igb_get_stats64 - Get System Network Statistics
5258 * @netdev: network interface device structure
5259 * @stats: rtnl_link_stats64 pointer
9d5c8243 5260 **/
12dcd86b 5261static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5262 struct rtnl_link_stats64 *stats)
9d5c8243 5263{
12dcd86b
ED		 5264 struct igb_adapter *adapter = netdev_priv(netdev);
5265
5266 spin_lock(&adapter->stats64_lock);
5267 igb_update_stats(adapter, &adapter->stats64);
5268 memcpy(stats, &adapter->stats64, sizeof(*stats));
5269 spin_unlock(&adapter->stats64_lock);
5270
5271 return stats;
9d5c8243
AK		 5272}
5273
5274/**
b980ac18
JK		 5275 * igb_change_mtu - Change the Maximum Transfer Unit
5276 * @netdev: network interface device structure
5277 * @new_mtu: new value for maximum frame size
9d5c8243 5278 *
b980ac18 5279 * Returns 0 on success, negative on failure
9d5c8243
AK		 5280 **/
5281static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5282{
5283 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5284 struct pci_dev *pdev = adapter->pdev;
153285f9 5285 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5286
c809d227 5287 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5288 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5289 return -EINVAL;
5290 }
5291
153285f9 5292#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5293 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5294 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5295 return -EINVAL;
5296 }
5297
2ccd994c
AD		 5298 /* adjust max frame to be at least the size of a standard frame */
5299 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5300 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5301
9d5c8243 5302 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5303 usleep_range(1000, 2000);
73cd78f1 5304
9d5c8243
AK		 5305 /* igb_down has a dependency on max_frame_size */
5306 adapter->max_frame_size = max_frame;
559e9c49 5307
4c844851
AD		 5308 if (netif_running(netdev))
5309 igb_down(adapter);
9d5c8243 5310
090b1795 5311 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5312 netdev->mtu, new_mtu);
5313 netdev->mtu = new_mtu;
5314
5315 if (netif_running(netdev))
5316 igb_up(adapter);
5317 else
5318 igb_reset(adapter);
5319
5320 clear_bit(__IGB_RESETTING, &adapter->state);
5321
5322 return 0;
5323}
5324
5325/**
b980ac18
JK		 5326 * igb_update_stats - Update the board statistics counters
5327 * @adapter: board private structure
9d5c8243 5328 **/
12dcd86b
ED		 5329void igb_update_stats(struct igb_adapter *adapter,
5330 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5331{
5332 struct e1000_hw *hw = &adapter->hw;
5333 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5334 u32 reg, mpc;
3f9c0164
AD		 5335 int i;
5336 u64 bytes, packets;
12dcd86b
ED		 5337 unsigned int start;
5338 u64 _bytes, _packets;
9d5c8243 5339
b980ac18 5340 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5341 * connection is down.
5342 */
5343 if (adapter->link_speed == 0)
5344 return;
5345 if (pci_channel_offline(pdev))
5346 return;
5347
3f9c0164
AD		 5348 bytes = 0;
5349 packets = 0;
7f90128e
AA		 5350
5351 rcu_read_lock();
3f9c0164 5352 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5353 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5354 u32 rqdpc = rd32(E1000_RQDPC(i));
5355 if (hw->mac.type >= e1000_i210)
5356 wr32(E1000_RQDPC(i), 0);
12dcd86b 5357
ae1c07a6
AD		 5358 if (rqdpc) {
5359 ring->rx_stats.drops += rqdpc;
5360 net_stats->rx_fifo_errors += rqdpc;
5361 }
12dcd86b
ED		 5362
5363 do {
57a7744e 5364 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5365 _bytes = ring->rx_stats.bytes;
5366 _packets = ring->rx_stats.packets;
57a7744e 5367 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5368 bytes += _bytes;
5369 packets += _packets;
3f9c0164
AD		 5370 }
5371
128e45eb
AD		 5372 net_stats->rx_bytes = bytes;
5373 net_stats->rx_packets = packets;
3f9c0164
AD		 5374
5375 bytes = 0;
5376 packets = 0;
5377 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5378 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5379 do {
57a7744e 5380 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5381 _bytes = ring->tx_stats.bytes;
5382 _packets = ring->tx_stats.packets;
57a7744e 5383 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5384 bytes += _bytes;
5385 packets += _packets;
3f9c0164 5386 }
128e45eb
AD		 5387 net_stats->tx_bytes = bytes;
5388 net_stats->tx_packets = packets;
7f90128e 5389 rcu_read_unlock();
3f9c0164
AD		 5390
5391 /* read stats registers */
9d5c8243
AK		 5392 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5393 adapter->stats.gprc += rd32(E1000_GPRC);
5394 adapter->stats.gorc += rd32(E1000_GORCL);
5395 rd32(E1000_GORCH); /* clear GORCL */
5396 adapter->stats.bprc += rd32(E1000_BPRC);
5397 adapter->stats.mprc += rd32(E1000_MPRC);
5398 adapter->stats.roc += rd32(E1000_ROC);
5399
5400 adapter->stats.prc64 += rd32(E1000_PRC64);
5401 adapter->stats.prc127 += rd32(E1000_PRC127);
5402 adapter->stats.prc255 += rd32(E1000_PRC255);
5403 adapter->stats.prc511 += rd32(E1000_PRC511);
5404 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5405 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5406 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5407 adapter->stats.sec += rd32(E1000_SEC);
5408
fa3d9a6d
MW		 5409 mpc = rd32(E1000_MPC);
5410 adapter->stats.mpc += mpc;
5411 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5412 adapter->stats.scc += rd32(E1000_SCC);
5413 adapter->stats.ecol += rd32(E1000_ECOL);
5414 adapter->stats.mcc += rd32(E1000_MCC);
5415 adapter->stats.latecol += rd32(E1000_LATECOL);
5416 adapter->stats.dc += rd32(E1000_DC);
5417 adapter->stats.rlec += rd32(E1000_RLEC);
5418 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5419 adapter->stats.xontxc += rd32(E1000_XONTXC);
5420 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5421 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5422 adapter->stats.fcruc += rd32(E1000_FCRUC);
5423 adapter->stats.gptc += rd32(E1000_GPTC);
5424 adapter->stats.gotc += rd32(E1000_GOTCL);
5425 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5426 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5427 adapter->stats.ruc += rd32(E1000_RUC);
5428 adapter->stats.rfc += rd32(E1000_RFC);
5429 adapter->stats.rjc += rd32(E1000_RJC);
5430 adapter->stats.tor += rd32(E1000_TORH);
5431 adapter->stats.tot += rd32(E1000_TOTH);
5432 adapter->stats.tpr += rd32(E1000_TPR);
5433
5434 adapter->stats.ptc64 += rd32(E1000_PTC64);
5435 adapter->stats.ptc127 += rd32(E1000_PTC127);
5436 adapter->stats.ptc255 += rd32(E1000_PTC255);
5437 adapter->stats.ptc511 += rd32(E1000_PTC511);
5438 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5439 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5440
5441 adapter->stats.mptc += rd32(E1000_MPTC);
5442 adapter->stats.bptc += rd32(E1000_BPTC);
5443
2d0b0f69
NN		 5444 adapter->stats.tpt += rd32(E1000_TPT);
5445 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5446
5447 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5448 /* read internal phy specific stats */
5449 reg = rd32(E1000_CTRL_EXT);
5450 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5451 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5452
5453 /* this stat has invalid values on i210/i211 */
5454 if ((hw->mac.type != e1000_i210) &&
5455 (hw->mac.type != e1000_i211))
5456 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5457 }
5458
9d5c8243
AK		 5459 adapter->stats.tsctc += rd32(E1000_TSCTC);
5460 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5461
5462 adapter->stats.iac += rd32(E1000_IAC);
5463 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5464 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5465 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5466 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5467 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5468 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5469 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5470 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5471
5472 /* Fill out the OS statistics structure */
128e45eb
AD		 5473 net_stats->multicast = adapter->stats.mprc;
5474 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5475
5476 /* Rx Errors */
5477
5478 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5479 * our own version based on RUC and ROC
5480 */
128e45eb 5481 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5482 adapter->stats.crcerrs + adapter->stats.algnerrc +
5483 adapter->stats.ruc + adapter->stats.roc +
5484 adapter->stats.cexterr;
128e45eb
AD		 5485 net_stats->rx_length_errors = adapter->stats.ruc +
5486 adapter->stats.roc;
5487 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5488 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5489 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5490
5491 /* Tx Errors */
128e45eb
AD		 5492 net_stats->tx_errors = adapter->stats.ecol +
5493 adapter->stats.latecol;
5494 net_stats->tx_aborted_errors = adapter->stats.ecol;
5495 net_stats->tx_window_errors = adapter->stats.latecol;
5496 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5497
5498 /* Tx Dropped needs to be maintained elsewhere */
5499
9d5c8243
AK		 5500 /* Management Stats */
5501 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5502 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5503 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5504
5505 /* OS2BMC Stats */
5506 reg = rd32(E1000_MANC);
5507 if (reg & E1000_MANC_EN_BMC2OS) {
5508 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5509 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5510 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5511 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5512 }
9d5c8243
AK		 5513}
5514
61d7f75f
RC		 5515static void igb_tsync_interrupt(struct igb_adapter *adapter)
5516{
5517 struct e1000_hw *hw = &adapter->hw;
00c65578 5518 struct ptp_clock_event event;
40c9b079 5519 struct timespec64 ts;
720db4ff 5520 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5521
5522 if (tsicr & TSINTR_SYS_WRAP) {
5523 event.type = PTP_CLOCK_PPS;
5524 if (adapter->ptp_caps.pps)
5525 ptp_clock_event(adapter->ptp_clock, &event);
5526 else
5527 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5528 ack |= TSINTR_SYS_WRAP;
5529 }
61d7f75f
RC		 5530
5531 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5532 /* retrieve hardware timestamp */
5533 schedule_work(&adapter->ptp_tx_work);
00c65578 5534 ack |= E1000_TSICR_TXTS;
61d7f75f 5535 }
00c65578 5536
720db4ff
RC		 5537 if (tsicr & TSINTR_TT0) {
5538 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5539 ts = timespec64_add(adapter->perout[0].start,
5540 adapter->perout[0].period);
5541 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5542 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5543 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5544 tsauxc = rd32(E1000_TSAUXC);
5545 tsauxc |= TSAUXC_EN_TT0;
5546 wr32(E1000_TSAUXC, tsauxc);
5547 adapter->perout[0].start = ts;
5548 spin_unlock(&adapter->tmreg_lock);
5549 ack |= TSINTR_TT0;
5550 }
5551
5552 if (tsicr & TSINTR_TT1) {
5553 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5554 ts = timespec64_add(adapter->perout[1].start,
5555 adapter->perout[1].period);
720db4ff 5556 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5557 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5558 tsauxc = rd32(E1000_TSAUXC);
5559 tsauxc |= TSAUXC_EN_TT1;
5560 wr32(E1000_TSAUXC, tsauxc);
5561 adapter->perout[1].start = ts;
5562 spin_unlock(&adapter->tmreg_lock);
5563 ack |= TSINTR_TT1;
5564 }
5565
5566 if (tsicr & TSINTR_AUTT0) {
5567 nsec = rd32(E1000_AUXSTMPL0);
5568 sec = rd32(E1000_AUXSTMPH0);
5569 event.type = PTP_CLOCK_EXTTS;
5570 event.index = 0;
5571 event.timestamp = sec * 1000000000ULL + nsec;
5572 ptp_clock_event(adapter->ptp_clock, &event);
5573 ack |= TSINTR_AUTT0;
5574 }
5575
5576 if (tsicr & TSINTR_AUTT1) {
5577 nsec = rd32(E1000_AUXSTMPL1);
5578 sec = rd32(E1000_AUXSTMPH1);
5579 event.type = PTP_CLOCK_EXTTS;
5580 event.index = 1;
5581 event.timestamp = sec * 1000000000ULL + nsec;
5582 ptp_clock_event(adapter->ptp_clock, &event);
5583 ack |= TSINTR_AUTT1;
5584 }
5585
00c65578
RC		 5586 /* acknowledge the interrupts */
5587 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5588}
5589
9d5c8243
AK		 5590static irqreturn_t igb_msix_other(int irq, void *data)
5591{
047e0030 5592 struct igb_adapter *adapter = data;
9d5c8243 5593 struct e1000_hw *hw = &adapter->hw;
844290e5 5594 u32 icr = rd32(E1000_ICR);
844290e5 5595 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5596
7f081d40
AD		 5597 if (icr & E1000_ICR_DRSTA)
5598 schedule_work(&adapter->reset_task);
5599
047e0030 5600 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5601 /* HW is reporting DMA is out of sync */
5602 adapter->stats.doosync++;
13800469
GR		 5603 /* The DMA Out of Sync is also indication of a spoof event
5604 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5605 * see if it is really a spoof event.
5606 */
13800469 5607 igb_check_wvbr(adapter);
dda0e083 5608 }
eebbbdba 5609
4ae196df
AD		 5610 /* Check for a mailbox event */
5611 if (icr & E1000_ICR_VMMB)
5612 igb_msg_task(adapter);
5613
5614 if (icr & E1000_ICR_LSC) {
5615 hw->mac.get_link_status = 1;
5616 /* guard against interrupt when we're going down */
5617 if (!test_bit(__IGB_DOWN, &adapter->state))
5618 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5619 }
5620
61d7f75f
RC		 5621 if (icr & E1000_ICR_TS)
5622 igb_tsync_interrupt(adapter);
1f6e8178 5623
844290e5 5624 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5625
5626 return IRQ_HANDLED;
5627}
5628
047e0030 5629static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5630{
26b39276 5631 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5632 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5633
047e0030
AD		 5634 if (!q_vector->set_itr)
5635 return;
73cd78f1 5636
047e0030
AD		 5637 if (!itr_val)
5638 itr_val = 0x4;
661086df 5639
26b39276
AD		 5640 if (adapter->hw.mac.type == e1000_82575)
5641 itr_val |= itr_val << 16;
661086df 5642 else
0ba82994 5643 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5644
047e0030
AD		 5645 writel(itr_val, q_vector->itr_register);
5646 q_vector->set_itr = 0;
6eb5a7f1
AD		 5647}
5648
047e0030 5649static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5650{
047e0030 5651 struct igb_q_vector *q_vector = data;
9d5c8243 5652
047e0030
AD		 5653 /* Write the ITR value calculated from the previous interrupt. */
5654 igb_write_itr(q_vector);
9d5c8243 5655
047e0030 5656 napi_schedule(&q_vector->napi);
844290e5 5657
047e0030 5658 return IRQ_HANDLED;
fe4506b6
JC		 5659}
5660
421e02f0 5661#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5662static void igb_update_tx_dca(struct igb_adapter *adapter,
5663 struct igb_ring *tx_ring,
5664 int cpu)
5665{
5666 struct e1000_hw *hw = &adapter->hw;
5667 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5668
5669 if (hw->mac.type != e1000_82575)
5670 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5671
b980ac18 5672 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5673 * DCA is enabled. This is due to a known issue in some chipsets
5674 * which will cause the DCA tag to be cleared.
5675 */
5676 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5677 E1000_DCA_TXCTRL_DATA_RRO_EN |
5678 E1000_DCA_TXCTRL_DESC_DCA_EN;
5679
5680 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5681}
5682
5683static void igb_update_rx_dca(struct igb_adapter *adapter,
5684 struct igb_ring *rx_ring,
5685 int cpu)
5686{
5687 struct e1000_hw *hw = &adapter->hw;
5688 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5689
5690 if (hw->mac.type != e1000_82575)
5691 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5692
b980ac18 5693 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5694 * DCA is enabled. This is due to a known issue in some chipsets
5695 * which will cause the DCA tag to be cleared.
5696 */
5697 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5698 E1000_DCA_RXCTRL_DESC_DCA_EN;
5699
5700 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5701}
5702
047e0030 5703static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5704{
047e0030 5705 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5706 int cpu = get_cpu();
fe4506b6 5707
047e0030
AD		 5708 if (q_vector->cpu == cpu)
5709 goto out_no_update;
5710
6a05004a
AD		 5711 if (q_vector->tx.ring)
5712 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5713
5714 if (q_vector->rx.ring)
5715 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5716
047e0030
AD		 5717 q_vector->cpu = cpu;
5718out_no_update:
fe4506b6
JC		 5719 put_cpu();
5720}
5721
5722static void igb_setup_dca(struct igb_adapter *adapter)
5723{
7e0e99ef 5724 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5725 int i;
5726
7dfc16fa 5727 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5728 return;
5729
7e0e99ef
AD		 5730 /* Always use CB2 mode, difference is masked in the CB driver. */
5731 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5732
047e0030 5733 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5734 adapter->q_vector[i]->cpu = -1;
5735 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5736 }
5737}
5738
5739static int __igb_notify_dca(struct device *dev, void *data)
5740{
5741 struct net_device *netdev = dev_get_drvdata(dev);
5742 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5743 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5744 struct e1000_hw *hw = &adapter->hw;
5745 unsigned long event = *(unsigned long *)data;
5746
5747 switch (event) {
5748 case DCA_PROVIDER_ADD:
5749 /* if already enabled, don't do it again */
7dfc16fa 5750 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5751 break;
fe4506b6 5752 if (dca_add_requester(dev) == 0) {
bbd98fe4 5753 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5754 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5755 igb_setup_dca(adapter);
5756 break;
5757 }
5758 /* Fall Through since DCA is disabled. */
5759 case DCA_PROVIDER_REMOVE:
7dfc16fa 5760 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5761 /* without this a class_device is left
b980ac18
JK		 5762 * hanging around in the sysfs model
5763 */
fe4506b6 5764 dca_remove_requester(dev);
090b1795 5765 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5766 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5767 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5768 }
5769 break;
5770 }
bbd98fe4 5771
fe4506b6 5772 return 0;
9d5c8243
AK		 5773}
5774
fe4506b6 5775static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5776 void *p)
fe4506b6
JC		 5777{
5778 int ret_val;
5779
5780 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5781 __igb_notify_dca);
fe4506b6
JC		 5782
5783 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5784}
421e02f0 5785#endif /* CONFIG_IGB_DCA */
9d5c8243 5786
0224d663
GR		 5787#ifdef CONFIG_PCI_IOV
5788static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5789{
5790 unsigned char mac_addr[ETH_ALEN];
0224d663 5791
5ac6f91d 5792 eth_zero_addr(mac_addr);
0224d663
GR		 5793 igb_set_vf_mac(adapter, vf, mac_addr);
5794
70ea4783
LL		 5795 /* By default spoof check is enabled for all VFs */
5796 adapter->vf_data[vf].spoofchk_enabled = true;
5797
f557147c 5798 return 0;
0224d663
GR		 5799}
5800
0224d663 5801#endif
4ae196df
AD		 5802static void igb_ping_all_vfs(struct igb_adapter *adapter)
5803{
5804 struct e1000_hw *hw = &adapter->hw;
5805 u32 ping;
5806 int i;
5807
5808 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5809 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5810 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5811 ping |= E1000_VT_MSGTYPE_CTS;
5812 igb_write_mbx(hw, &ping, 1, i);
5813 }
5814}
5815
7d5753f0
AD		 5816static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5817{
5818 struct e1000_hw *hw = &adapter->hw;
5819 u32 vmolr = rd32(E1000_VMOLR(vf));
5820 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5821
d85b9004 5822 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5823 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5824 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5825
5826 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5827 vmolr |= E1000_VMOLR_MPME;
d85b9004 5828 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5829 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5830 } else {
b980ac18 5831 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5832 * flag we need to write the hashes to the MTA as this step
5833 * was previously skipped
5834 */
5835 if (vf_data->num_vf_mc_hashes > 30) {
5836 vmolr |= E1000_VMOLR_MPME;
5837 } else if (vf_data->num_vf_mc_hashes) {
5838 int j;
9005df38 5839
7d5753f0
AD		 5840 vmolr |= E1000_VMOLR_ROMPE;
5841 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5842 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5843 }
5844 }
5845
5846 wr32(E1000_VMOLR(vf), vmolr);
5847
5848 /* there are flags left unprocessed, likely not supported */
5849 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5850 return -EINVAL;
5851
5852 return 0;
7d5753f0
AD		 5853}
5854
4ae196df
AD		 5855static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5856 u32 *msgbuf, u32 vf)
5857{
5858 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5859 u16 *hash_list = (u16 *)&msgbuf[1];
5860 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5861 int i;
5862
7d5753f0 5863 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5864 * to this VF for later use to restore when the PF multi cast
5865 * list changes
5866 */
5867 vf_data->num_vf_mc_hashes = n;
5868
7d5753f0
AD		 5869 /* only up to 30 hash values supported */
5870 if (n > 30)
5871 n = 30;
5872
5873 /* store the hashes for later use */
4ae196df 5874 for (i = 0; i < n; i++)
a419aef8 5875 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5876
5877 /* Flush and reset the mta with the new values */
ff41f8dc 5878 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5879
5880 return 0;
5881}
5882
5883static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5884{
5885 struct e1000_hw *hw = &adapter->hw;
5886 struct vf_data_storage *vf_data;
5887 int i, j;
5888
5889 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5890 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5891
7d5753f0
AD		 5892 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5893
4ae196df 5894 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5895
5896 if ((vf_data->num_vf_mc_hashes > 30) ||
5897 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5898 vmolr |= E1000_VMOLR_MPME;
5899 } else if (vf_data->num_vf_mc_hashes) {
5900 vmolr |= E1000_VMOLR_ROMPE;
5901 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5902 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5903 }
5904 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5905 }
5906}
5907
5908static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5909{
5910 struct e1000_hw *hw = &adapter->hw;
16903caa 5911 u32 pool_mask, vlvf_mask, i;
4ae196df 5912
16903caa
AD		 5913 /* create mask for VF and other pools */
5914 pool_mask = E1000_VLVF_POOLSEL_MASK;
5915 vlvf_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5916
5917 /* drop PF from pool bits */
5918 pool_mask &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT +
5919 adapter->vfs_allocated_count));
4ae196df
AD		 5920
5921 /* Find the vlan filter for this id */
16903caa
AD		 5922 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
5923 u32 vlvf = rd32(E1000_VLVF(i));
5924 u32 vfta_mask, vid, vfta;
4ae196df
AD		 5925
5926 /* remove the vf from the pool */
16903caa
AD		 5927 if (!(vlvf & vlvf_mask))
5928 continue;
5929
5930 /* clear out bit from VLVF */
5931 vlvf ^= vlvf_mask;
5932
5933 /* if other pools are present, just remove ourselves */
5934 if (vlvf & pool_mask)
5935 goto update_vlvfb;
5936
5937 /* if PF is present, leave VFTA */
5938 if (vlvf & E1000_VLVF_POOLSEL_MASK)
5939 goto update_vlvf;
4ae196df 5940
16903caa
AD		 5941 vid = vlvf & E1000_VLVF_VLANID_MASK;
5942 vfta_mask = 1 << (vid % 32);
5943
5944 /* clear bit from VFTA */
5945 vfta = adapter->shadow_vfta[vid / 32];
5946 if (vfta & vfta_mask)
5947 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
5948update_vlvf:
5949 /* clear pool selection enable */
5950 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5951 vlvf &= E1000_VLVF_POOLSEL_MASK;
5952 else
5953 vlvf = 0;
5954update_vlvfb:
5955 /* clear pool bits */
5956 wr32(E1000_VLVF(i), vlvf);
4ae196df
AD		 5957 }
5958}
5959
16903caa 5960static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6f3dc319 5961{
16903caa
AD		 5962 u32 vlvf;
5963 int idx;
6f3dc319 5964
16903caa
AD		 5965 /* short cut the special case */
5966 if (vlan == 0)
5967 return 0;
5968
5969 /* Search for the VLAN id in the VLVF entries */
5970 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
5971 vlvf = rd32(E1000_VLVF(idx));
5972 if ((vlvf & VLAN_VID_MASK) == vlan)
6f3dc319
GR		 5973 break;
5974 }
5975
16903caa
AD		 5976 return idx;
5977}
5978
5979void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
5980{
5981 struct e1000_hw *hw = &adapter->hw;
5982 u32 bits, pf_id;
5983 int idx;
5984
5985 idx = igb_find_vlvf_entry(hw, vid);
5986 if (!idx)
5987 return;
6f3dc319 5988
16903caa
AD		 5989 /* See if any other pools are set for this VLAN filter
5990 * entry other than the PF.
5991 */
5992 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
5993 bits = ~(1 << pf_id) & E1000_VLVF_POOLSEL_MASK;
5994 bits &= rd32(E1000_VLVF(idx));
5995
5996 /* Disable the filter so this falls into the default pool. */
5997 if (!bits) {
5998 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5999 wr32(E1000_VLVF(idx), 1 << pf_id);
6000 else
6001 wr32(E1000_VLVF(idx), 0);
6002 }
6f3dc319
GR		 6003}
6004
a15d9259
AD		 6005static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6006 bool add, u32 vf)
4ae196df 6007{
a15d9259 6008 int pf_id = adapter->vfs_allocated_count;
6f3dc319 6009 struct e1000_hw *hw = &adapter->hw;
a15d9259 6010 int err;
4ae196df 6011
a15d9259
AD		 6012 /* If VLAN overlaps with one the PF is currently monitoring make
6013 * sure that we are able to allocate a VLVF entry. This may be
6014 * redundant but it guarantees PF will maintain visibility to
6015 * the VLAN.
6f3dc319 6016 */
16903caa 6017 if (add && test_bit(vid, adapter->active_vlans)) {
a15d9259
AD		 6018 err = igb_vfta_set(hw, vid, pf_id, true, false);
6019 if (err)
6020 return err;
6021 }
6f3dc319 6022
a15d9259 6023 err = igb_vfta_set(hw, vid, vf, add, false);
6f3dc319 6024
16903caa
AD		 6025 if (add && !err)
6026 return err;
6f3dc319 6027
16903caa
AD		 6028 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6029 * we may need to drop the PF pool bit in order to allow us to free
6030 * up the VLVF resources.
6f3dc319 6031 */
16903caa
AD		 6032 if (test_bit(vid, adapter->active_vlans) ||
6033 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6034 igb_update_pf_vlvf(adapter, vid);
6f3dc319 6035
6f3dc319 6036 return err;
4ae196df
AD		 6037}
6038
a15d9259 6039static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4ae196df 6040{
a15d9259
AD		 6041 struct e1000_hw *hw = &adapter->hw;
6042
6043 if (vid)
6044 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6045 else
6046 wr32(E1000_VMVIR(vf), 0);
6047}
6048
6049static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6050 u16 vlan, u8 qos)
6051{
6052 int err;
6053
6054 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6055 if (err)
6056 return err;
6057
6058 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6059 igb_set_vmolr(adapter, vf, !vlan);
6060
6061 /* revoke access to previous VLAN */
6062 if (vlan != adapter->vf_data[vf].pf_vlan)
6063 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6064 false, vf);
6065
6066 adapter->vf_data[vf].pf_vlan = vlan;
6067 adapter->vf_data[vf].pf_qos = qos;
6068 dev_info(&adapter->pdev->dev,
6069 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6070 if (test_bit(__IGB_DOWN, &adapter->state)) {
6071 dev_warn(&adapter->pdev->dev,
6072 "The VF VLAN has been set, but the PF device is not up.\n");
6073 dev_warn(&adapter->pdev->dev,
6074 "Bring the PF device up before attempting to use the VF device.\n");
6075 }
6076
6077 return err;
6078}
4ae196df 6079
a15d9259
AD		 6080static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6081{
6082 /* Restore tagless access via VLAN 0 */
6083 igb_set_vf_vlan(adapter, 0, true, vf);
6084
6085 igb_set_vmvir(adapter, 0, vf);
8151d294 6086 igb_set_vmolr(adapter, vf, true);
4ae196df 6087
a15d9259
AD		 6088 /* Remove any PF assigned VLAN */
6089 if (adapter->vf_data[vf].pf_vlan)
6090 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6091 false, vf);
6092
6093 adapter->vf_data[vf].pf_vlan = 0;
6094 adapter->vf_data[vf].pf_qos = 0;
6095
6096 return 0;
6097}
6098
6099static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6100 int vf, u16 vlan, u8 qos)
6101{
6102 struct igb_adapter *adapter = netdev_priv(netdev);
6103
6104 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6105 return -EINVAL;
6106
6107 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6108 igb_disable_port_vlan(adapter, vf);
6109}
6110
6111static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6112{
6113 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6114 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6115
6116 if (adapter->vf_data[vf].pf_vlan)
6117 return -1;
6118
6119 /* VLAN 0 is a special case, don't allow it to be removed */
6120 if (!vid && !add)
6121 return 0;
6122
6123 return igb_set_vf_vlan(adapter, vid, !!add, vf);
6124}
6125
6126static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6127{
6128 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6129
6130 /* clear flags - except flag that indicates PF has set the MAC */
6131 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6132 vf_data->last_nack = jiffies;
6133
4ae196df
AD		 6134 /* reset vlans for device */
6135 igb_clear_vf_vfta(adapter, vf);
a15d9259
AD		 6136 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6137 igb_set_vmvir(adapter, vf_data->pf_vlan |
6138 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6139 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
4ae196df
AD		 6140
6141 /* reset multicast table array for vf */
6142 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6143
6144 /* Flush and reset the mta with the new values */
ff41f8dc 6145 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6146}
6147
f2ca0dbe
AD		 6148static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6149{
6150 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6151
5ac6f91d 6152 /* clear mac address as we were hotplug removed/added */
8151d294 6153 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6154 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6155
6156 /* process remaining reset events */
6157 igb_vf_reset(adapter, vf);
6158}
6159
6160static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6161{
6162 struct e1000_hw *hw = &adapter->hw;
6163 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6164 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6165 u32 reg, msgbuf[3];
6166 u8 *addr = (u8 *)(&msgbuf[1]);
6167
6168 /* process all the same items cleared in a function level reset */
f2ca0dbe 6169 igb_vf_reset(adapter, vf);
4ae196df
AD		 6170
6171 /* set vf mac address */
26ad9178 6172 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6173
6174 /* enable transmit and receive for vf */
6175 reg = rd32(E1000_VFTE);
6176 wr32(E1000_VFTE, reg | (1 << vf));
6177 reg = rd32(E1000_VFRE);
6178 wr32(E1000_VFRE, reg | (1 << vf));
6179
8fa7e0f7 6180 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6181
6182 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6183 if (!is_zero_ether_addr(vf_mac)) {
6184 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6185 memcpy(addr, vf_mac, ETH_ALEN);
6186 } else {
6187 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6188 }
4ae196df
AD		 6189 igb_write_mbx(hw, msgbuf, 3, vf);
6190}
6191
6192static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6193{
b980ac18 6194 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6195 * starting at the second 32 bit word of the msg array
6196 */
f2ca0dbe
AD		 6197 unsigned char *addr = (char *)&msg[1];
6198 int err = -1;
4ae196df 6199
f2ca0dbe
AD		 6200 if (is_valid_ether_addr(addr))
6201 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6202
f2ca0dbe 6203 return err;
4ae196df
AD		 6204}
6205
6206static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6207{
6208 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6209 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6210 u32 msg = E1000_VT_MSGTYPE_NACK;
6211
6212 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6213 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6214 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6215 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6216 vf_data->last_nack = jiffies;
4ae196df
AD		 6217 }
6218}
6219
f2ca0dbe 6220static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6221{
f2ca0dbe
AD		 6222 struct pci_dev *pdev = adapter->pdev;
6223 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6224 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6225 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6226 s32 retval;
6227
f2ca0dbe 6228 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6229
fef45f4c
AD		 6230 if (retval) {
6231 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6232 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6233 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6234 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6235 return;
6236 goto out;
6237 }
4ae196df
AD		 6238
6239 /* this is a message we already processed, do nothing */
6240 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6241 return;
4ae196df 6242
b980ac18 6243 /* until the vf completes a reset it should not be
4ae196df
AD		 6244 * allowed to start any configuration.
6245 */
4ae196df
AD		 6246 if (msgbuf[0] == E1000_VF_RESET) {
6247 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6248 return;
4ae196df
AD		 6249 }
6250
f2ca0dbe 6251 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6252 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6253 return;
6254 retval = -1;
6255 goto out;
4ae196df
AD		 6256 }
6257
6258 switch ((msgbuf[0] & 0xFFFF)) {
6259 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6260 retval = -EINVAL;
6261 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6262 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6263 else
6264 dev_warn(&pdev->dev,
b980ac18
JK		 6265 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6266 vf);
4ae196df 6267 break;
7d5753f0
AD		 6268 case E1000_VF_SET_PROMISC:
6269 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6270 break;
4ae196df
AD		 6271 case E1000_VF_SET_MULTICAST:
6272 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6273 break;
6274 case E1000_VF_SET_LPE:
6275 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6276 break;
6277 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6278 retval = -1;
6279 if (vf_data->pf_vlan)
6280 dev_warn(&pdev->dev,
b980ac18
JK		 6281 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6282 vf);
8151d294 6283 else
a15d9259 6284 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
4ae196df
AD		 6285 break;
6286 default:
090b1795 6287 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6288 retval = -1;
6289 break;
6290 }
6291
fef45f4c
AD		 6292 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6293out:
4ae196df
AD		 6294 /* notify the VF of the results of what it sent us */
6295 if (retval)
6296 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6297 else
6298 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6299
4ae196df 6300 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6301}
4ae196df 6302
f2ca0dbe
AD		 6303static void igb_msg_task(struct igb_adapter *adapter)
6304{
6305 struct e1000_hw *hw = &adapter->hw;
6306 u32 vf;
6307
6308 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6309 /* process any reset requests */
6310 if (!igb_check_for_rst(hw, vf))
6311 igb_vf_reset_event(adapter, vf);
6312
6313 /* process any messages pending */
6314 if (!igb_check_for_msg(hw, vf))
6315 igb_rcv_msg_from_vf(adapter, vf);
6316
6317 /* process any acks */
6318 if (!igb_check_for_ack(hw, vf))
6319 igb_rcv_ack_from_vf(adapter, vf);
6320 }
4ae196df
AD		 6321}
6322
68d480c4
AD		 6323/**
6324 * igb_set_uta - Set unicast filter table address
6325 * @adapter: board private structure
6326 *
6327 * The unicast table address is a register array of 32-bit registers.
6328 * The table is meant to be used in a way similar to how the MTA is used
6329 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6330 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6331 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6332 **/
6333static void igb_set_uta(struct igb_adapter *adapter)
6334{
6335 struct e1000_hw *hw = &adapter->hw;
6336 int i;
6337
6338 /* The UTA table only exists on 82576 hardware and newer */
6339 if (hw->mac.type < e1000_82576)
6340 return;
6341
6342 /* we only need to do this if VMDq is enabled */
6343 if (!adapter->vfs_allocated_count)
6344 return;
6345
6346 for (i = 0; i < hw->mac.uta_reg_count; i++)
6347 array_wr32(E1000_UTA, i, ~0);
6348}
6349
9d5c8243 6350/**
b980ac18
JK		 6351 * igb_intr_msi - Interrupt Handler
6352 * @irq: interrupt number
6353 * @data: pointer to a network interface device structure
9d5c8243
AK		 6354 **/
6355static irqreturn_t igb_intr_msi(int irq, void *data)
6356{
047e0030
AD		 6357 struct igb_adapter *adapter = data;
6358 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6359 struct e1000_hw *hw = &adapter->hw;
6360 /* read ICR disables interrupts using IAM */
6361 u32 icr = rd32(E1000_ICR);
6362
047e0030 6363 igb_write_itr(q_vector);
9d5c8243 6364
7f081d40
AD		 6365 if (icr & E1000_ICR_DRSTA)
6366 schedule_work(&adapter->reset_task);
6367
047e0030 6368 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6369 /* HW is reporting DMA is out of sync */
6370 adapter->stats.doosync++;
6371 }
6372
9d5c8243
AK		 6373 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6374 hw->mac.get_link_status = 1;
6375 if (!test_bit(__IGB_DOWN, &adapter->state))
6376 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6377 }
6378
61d7f75f
RC		 6379 if (icr & E1000_ICR_TS)
6380 igb_tsync_interrupt(adapter);
1f6e8178 6381
047e0030 6382 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6383
6384 return IRQ_HANDLED;
6385}
6386
6387/**
b980ac18
JK		 6388 * igb_intr - Legacy Interrupt Handler
6389 * @irq: interrupt number
6390 * @data: pointer to a network interface device structure
9d5c8243
AK		 6391 **/
6392static irqreturn_t igb_intr(int irq, void *data)
6393{
047e0030
AD		 6394 struct igb_adapter *adapter = data;
6395 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6396 struct e1000_hw *hw = &adapter->hw;
6397 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6398 * need for the IMC write
6399 */
9d5c8243 6400 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6401
6402 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6403 * not set, then the adapter didn't send an interrupt
6404 */
9d5c8243
AK		 6405 if (!(icr & E1000_ICR_INT_ASSERTED))
6406 return IRQ_NONE;
6407
0ba82994
AD		 6408 igb_write_itr(q_vector);
6409
7f081d40
AD		 6410 if (icr & E1000_ICR_DRSTA)
6411 schedule_work(&adapter->reset_task);
6412
047e0030 6413 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6414 /* HW is reporting DMA is out of sync */
6415 adapter->stats.doosync++;
6416 }
6417
9d5c8243
AK		 6418 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6419 hw->mac.get_link_status = 1;
6420 /* guard against interrupt when we're going down */
6421 if (!test_bit(__IGB_DOWN, &adapter->state))
6422 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6423 }
6424
61d7f75f
RC		 6425 if (icr & E1000_ICR_TS)
6426 igb_tsync_interrupt(adapter);
1f6e8178 6427
047e0030 6428 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6429
6430 return IRQ_HANDLED;
6431}
6432
c50b52a0 6433static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6434{
047e0030 6435 struct igb_adapter *adapter = q_vector->adapter;
46544258 6436 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6437
0ba82994
AD		 6438 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6439 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6440 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6441 igb_set_itr(q_vector);
46544258 6442 else
047e0030 6443 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6444 }
6445
46544258 6446 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6447 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6448 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6449 else
6450 igb_irq_enable(adapter);
6451 }
9d5c8243
AK		 6452}
6453
46544258 6454/**
b980ac18
JK		 6455 * igb_poll - NAPI Rx polling callback
6456 * @napi: napi polling structure
6457 * @budget: count of how many packets we should handle
46544258
AD		 6458 **/
6459static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6460{
047e0030 6461 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6462 struct igb_q_vector,
6463 napi);
16eb8815 6464 bool clean_complete = true;
32b3e08f 6465 int work_done = 0;
9d5c8243 6466
421e02f0 6467#ifdef CONFIG_IGB_DCA
047e0030
AD		 6468 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6469 igb_update_dca(q_vector);
fe4506b6 6470#endif
0ba82994 6471 if (q_vector->tx.ring)
13fde97a 6472 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6473
32b3e08f
JB		 6474 if (q_vector->rx.ring) {
6475 int cleaned = igb_clean_rx_irq(q_vector, budget);
6476
6477 work_done += cleaned;
6478 clean_complete &= (cleaned < budget);
6479 }
047e0030 6480
16eb8815
AD		 6481 /* If all work not completed, return budget and keep polling */
6482 if (!clean_complete)
6483 return budget;
46544258 6484
9d5c8243 6485 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6486 napi_complete_done(napi, work_done);
16eb8815 6487 igb_ring_irq_enable(q_vector);
9d5c8243 6488
16eb8815 6489 return 0;
9d5c8243 6490}
6d8126f9 6491
9d5c8243 6492/**
b980ac18
JK		 6493 * igb_clean_tx_irq - Reclaim resources after transmit completes
6494 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6495 *
b980ac18 6496 * returns true if ring is completely cleaned
9d5c8243 6497 **/
047e0030 6498static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6499{
047e0030 6500 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6501 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6502 struct igb_tx_buffer *tx_buffer;
f4128785 6503 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6504 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6505 unsigned int budget = q_vector->tx.work_limit;
8542db05 6506 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6507
13fde97a
AD		 6508 if (test_bit(__IGB_DOWN, &adapter->state))
6509 return true;
0e014cb1 6510
06034649 6511 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6512 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6513 i -= tx_ring->count;
9d5c8243 6514
f4128785
AD		 6515 do {
6516 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6517
6518 /* if next_to_watch is not set then there is no work pending */
6519 if (!eop_desc)
6520 break;
13fde97a 6521
f4128785 6522 /* prevent any other reads prior to eop_desc */
70d289bc 6523 read_barrier_depends();
f4128785 6524
13fde97a
AD		 6525 /* if DD is not set pending work has not been completed */
6526 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6527 break;
6528
8542db05
AD		 6529 /* clear next_to_watch to prevent false hangs */
6530 tx_buffer->next_to_watch = NULL;
9d5c8243 6531
ebe42d16
AD		 6532 /* update the statistics for this packet */
6533 total_bytes += tx_buffer->bytecount;
6534 total_packets += tx_buffer->gso_segs;
13fde97a 6535
ebe42d16 6536 /* free the skb */
a81fb049 6537 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6538
ebe42d16
AD		 6539 /* unmap skb header data */
6540 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6541 dma_unmap_addr(tx_buffer, dma),
6542 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6543 DMA_TO_DEVICE);
6544
c9f14bf3
AD		 6545 /* clear tx_buffer data */
6546 tx_buffer->skb = NULL;
6547 dma_unmap_len_set(tx_buffer, len, 0);
6548
ebe42d16
AD		 6549 /* clear last DMA location and unmap remaining buffers */
6550 while (tx_desc != eop_desc) {
13fde97a
AD		 6551 tx_buffer++;
6552 tx_desc++;
9d5c8243 6553 i++;
8542db05
AD		 6554 if (unlikely(!i)) {
6555 i -= tx_ring->count;
06034649 6556 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6557 tx_desc = IGB_TX_DESC(tx_ring, 0);
6558 }
ebe42d16
AD		 6559
6560 /* unmap any remaining paged data */
c9f14bf3 6561 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6562 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6563 dma_unmap_addr(tx_buffer, dma),
6564 dma_unmap_len(tx_buffer, len),
ebe42d16 6565 DMA_TO_DEVICE);
c9f14bf3 6566 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6567 }
6568 }
6569
ebe42d16
AD		 6570 /* move us one more past the eop_desc for start of next pkt */
6571 tx_buffer++;
6572 tx_desc++;
6573 i++;
6574 if (unlikely(!i)) {
6575 i -= tx_ring->count;
6576 tx_buffer = tx_ring->tx_buffer_info;
6577 tx_desc = IGB_TX_DESC(tx_ring, 0);
6578 }
f4128785
AD		 6579
6580 /* issue prefetch for next Tx descriptor */
6581 prefetch(tx_desc);
6582
6583 /* update budget accounting */
6584 budget--;
6585 } while (likely(budget));
0e014cb1 6586
bdbc0631
ED		 6587 netdev_tx_completed_queue(txring_txq(tx_ring),
6588 total_packets, total_bytes);
8542db05 6589 i += tx_ring->count;
9d5c8243 6590 tx_ring->next_to_clean = i;
13fde97a
AD		 6591 u64_stats_update_begin(&tx_ring->tx_syncp);
6592 tx_ring->tx_stats.bytes += total_bytes;
6593 tx_ring->tx_stats.packets += total_packets;
6594 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6595 q_vector->tx.total_bytes += total_bytes;
6596 q_vector->tx.total_packets += total_packets;
9d5c8243 6597
6d095fa8 6598 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6599 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6600
9d5c8243 6601 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6602 * check with the clearing of time_stamp and movement of i
6603 */
6d095fa8 6604 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6605 if (tx_buffer->next_to_watch &&
8542db05 6606 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6607 (adapter->tx_timeout_factor * HZ)) &&
6608 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6609
9d5c8243 6610 /* detected Tx unit hang */
59d71989 6611 dev_err(tx_ring->dev,
9d5c8243 6612 "Detected Tx Unit Hang\n"
2d064c06 6613 " Tx Queue <%d>\n"
9d5c8243
AK		 6614 " TDH <%x>\n"
6615 " TDT <%x>\n"
6616 " next_to_use <%x>\n"
6617 " next_to_clean <%x>\n"
9d5c8243
AK		 6618 "buffer_info[next_to_clean]\n"
6619 " time_stamp <%lx>\n"
8542db05 6620 " next_to_watch <%p>\n"
9d5c8243
AK		 6621 " jiffies <%lx>\n"
6622 " desc.status <%x>\n",
2d064c06 6623 tx_ring->queue_index,
238ac817 6624 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6625 readl(tx_ring->tail),
9d5c8243
AK		 6626 tx_ring->next_to_use,
6627 tx_ring->next_to_clean,
8542db05 6628 tx_buffer->time_stamp,
f4128785 6629 tx_buffer->next_to_watch,
9d5c8243 6630 jiffies,
f4128785 6631 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6632 netif_stop_subqueue(tx_ring->netdev,
6633 tx_ring->queue_index);
6634
6635 /* we are about to reset, no point in enabling stuff */
6636 return true;
9d5c8243
AK		 6637 }
6638 }
13fde97a 6639
21ba6fe1 6640#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6641 if (unlikely(total_packets &&
b980ac18
JK		 6642 netif_carrier_ok(tx_ring->netdev) &&
6643 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6644 /* Make sure that anybody stopping the queue after this
6645 * sees the new next_to_clean.
6646 */
6647 smp_mb();
6648 if (__netif_subqueue_stopped(tx_ring->netdev,
6649 tx_ring->queue_index) &&
6650 !(test_bit(__IGB_DOWN, &adapter->state))) {
6651 netif_wake_subqueue(tx_ring->netdev,
6652 tx_ring->queue_index);
6653
6654 u64_stats_update_begin(&tx_ring->tx_syncp);
6655 tx_ring->tx_stats.restart_queue++;
6656 u64_stats_update_end(&tx_ring->tx_syncp);
6657 }
6658 }
6659
6660 return !!budget;
9d5c8243
AK		 6661}
6662
cbc8e55f 6663/**
b980ac18
JK		 6664 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6665 * @rx_ring: rx descriptor ring to store buffers on
6666 * @old_buff: donor buffer to have page reused
cbc8e55f 6667 *
b980ac18 6668 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6669 **/
6670static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6671 struct igb_rx_buffer *old_buff)
6672{
6673 struct igb_rx_buffer *new_buff;
6674 u16 nta = rx_ring->next_to_alloc;
6675
6676 new_buff = &rx_ring->rx_buffer_info[nta];
6677
6678 /* update, and store next to alloc */
6679 nta++;
6680 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6681
6682 /* transfer page from old buffer to new buffer */
a1f63473 6683 *new_buff = *old_buff;
cbc8e55f
AD		 6684
6685 /* sync the buffer for use by the device */
6686 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6687 old_buff->page_offset,
de78d1f9 6688 IGB_RX_BUFSZ,
cbc8e55f
AD		 6689 DMA_FROM_DEVICE);
6690}
6691
95dd44b4
AD		 6692static inline bool igb_page_is_reserved(struct page *page)
6693{
2f064f34 6694 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6695}
6696
74e238ea
AD		 6697static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6698 struct page *page,
6699 unsigned int truesize)
6700{
6701 /* avoid re-using remote pages */
95dd44b4 6702 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6703 return false;
6704
74e238ea
AD		 6705#if (PAGE_SIZE < 8192)
6706 /* if we are only owner of page we can reuse it */
6707 if (unlikely(page_count(page) != 1))
6708 return false;
6709
6710 /* flip page offset to other buffer */
6711 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6712#else
6713 /* move offset up to the next cache line */
6714 rx_buffer->page_offset += truesize;
6715
6716 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6717 return false;
74e238ea
AD		 6718#endif
6719
95dd44b4
AD		 6720 /* Even if we own the page, we are not allowed to use atomic_set()
6721 * This would break get_page_unless_zero() users.
6722 */
6723 atomic_inc(&page->_count);
6724
74e238ea
AD		 6725 return true;
6726}
6727
cbc8e55f 6728/**
b980ac18
JK		 6729 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6730 * @rx_ring: rx descriptor ring to transact packets on
6731 * @rx_buffer: buffer containing page to add
6732 * @rx_desc: descriptor containing length of buffer written by hardware
6733 * @skb: sk_buff to place the data into
cbc8e55f 6734 *
b980ac18
JK		 6735 * This function will add the data contained in rx_buffer->page to the skb.
6736 * This is done either through a direct copy if the data in the buffer is
6737 * less than the skb header size, otherwise it will just attach the page as
6738 * a frag to the skb.
cbc8e55f 6739 *
b980ac18
JK		 6740 * The function will then update the page offset if necessary and return
6741 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6742 **/
6743static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6744 struct igb_rx_buffer *rx_buffer,
6745 union e1000_adv_rx_desc *rx_desc,
6746 struct sk_buff *skb)
6747{
6748 struct page *page = rx_buffer->page;
f56e7bba 6749 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6750 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6751#if (PAGE_SIZE < 8192)
6752 unsigned int truesize = IGB_RX_BUFSZ;
6753#else
f56e7bba 6754 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6755#endif
f56e7bba 6756 unsigned int pull_len;
cbc8e55f 6757
f56e7bba
AD		 6758 if (unlikely(skb_is_nonlinear(skb)))
6759 goto add_tail_frag;
cbc8e55f 6760
f56e7bba
AD		 6761 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6762 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6763 va += IGB_TS_HDR_LEN;
6764 size -= IGB_TS_HDR_LEN;
6765 }
cbc8e55f 6766
f56e7bba 6767 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6768 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6769
95dd44b4
AD		 6770 /* page is not reserved, we can reuse buffer as-is */
6771 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6772 return true;
6773
6774 /* this page cannot be reused so discard it */
95dd44b4 6775 __free_page(page);
cbc8e55f
AD		 6776 return false;
6777 }
6778
f56e7bba
AD		 6779 /* we need the header to contain the greater of either ETH_HLEN or
6780 * 60 bytes if the skb->len is less than 60 for skb_pad.
6781 */
6782 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6783
6784 /* align pull length to size of long to optimize memcpy performance */
6785 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6786
6787 /* update all of the pointers */
6788 va += pull_len;
6789 size -= pull_len;
6790
6791add_tail_frag:
cbc8e55f 6792 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6793 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6794
74e238ea
AD		 6795 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6796}
cbc8e55f 6797
2e334eee
AD		 6798static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6799 union e1000_adv_rx_desc *rx_desc,
6800 struct sk_buff *skb)
6801{
6802 struct igb_rx_buffer *rx_buffer;
6803 struct page *page;
6804
6805 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6806 page = rx_buffer->page;
6807 prefetchw(page);
6808
6809 if (likely(!skb)) {
6810 void *page_addr = page_address(page) +
6811 rx_buffer->page_offset;
6812
6813 /* prefetch first cache line of first page */
6814 prefetch(page_addr);
6815#if L1_CACHE_BYTES < 128
6816 prefetch(page_addr + L1_CACHE_BYTES);
6817#endif
6818
6819 /* allocate a skb to store the frags */
67fd893e 6820 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6821 if (unlikely(!skb)) {
6822 rx_ring->rx_stats.alloc_failed++;
6823 return NULL;
6824 }
6825
b980ac18 6826 /* we will be copying header into skb->data in
2e334eee
AD		 6827 * pskb_may_pull so it is in our interest to prefetch
6828 * it now to avoid a possible cache miss
6829 */
6830 prefetchw(skb->data);
6831 }
6832
6833 /* we are reusing so sync this buffer for CPU use */
6834 dma_sync_single_range_for_cpu(rx_ring->dev,
6835 rx_buffer->dma,
6836 rx_buffer->page_offset,
de78d1f9 6837 IGB_RX_BUFSZ,
2e334eee
AD		 6838 DMA_FROM_DEVICE);
6839
6840 /* pull page into skb */
6841 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6842 /* hand second half of page back to the ring */
6843 igb_reuse_rx_page(rx_ring, rx_buffer);
6844 } else {
6845 /* we are not reusing the buffer so unmap it */
6846 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6847 PAGE_SIZE, DMA_FROM_DEVICE);
6848 }
6849
6850 /* clear contents of rx_buffer */
6851 rx_buffer->page = NULL;
6852
6853 return skb;
6854}
6855
cd392f5c 6856static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6857 union e1000_adv_rx_desc *rx_desc,
6858 struct sk_buff *skb)
9d5c8243 6859{
bc8acf2c 6860 skb_checksum_none_assert(skb);
9d5c8243 6861
294e7d78 6862 /* Ignore Checksum bit is set */
3ceb90fd 6863 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6864 return;
6865
6866 /* Rx checksum disabled via ethtool */
6867 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6868 return;
85ad76b2 6869
9d5c8243 6870 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6871 if (igb_test_staterr(rx_desc,
6872 E1000_RXDEXT_STATERR_TCPE |
6873 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6874 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6875 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6876 * packets, (aka let the stack check the crc32c)
6877 */
866cff06
AD		 6878 if (!((skb->len == 60) &&
6879 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6880 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6881 ring->rx_stats.csum_err++;
12dcd86b
ED		 6882 u64_stats_update_end(&ring->rx_syncp);
6883 }
9d5c8243 6884 /* let the stack verify checksum errors */
9d5c8243
AK		 6885 return;
6886 }
6887 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6888 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6889 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6890 skb->ip_summed = CHECKSUM_UNNECESSARY;
6891
3ceb90fd
AD		 6892 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6893 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6894}
6895
077887c3
AD		 6896static inline void igb_rx_hash(struct igb_ring *ring,
6897 union e1000_adv_rx_desc *rx_desc,
6898 struct sk_buff *skb)
6899{
6900 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6901 skb_set_hash(skb,
6902 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6903 PKT_HASH_TYPE_L3);
077887c3
AD		 6904}
6905
2e334eee 6906/**
b980ac18
JK		 6907 * igb_is_non_eop - process handling of non-EOP buffers
6908 * @rx_ring: Rx ring being processed
6909 * @rx_desc: Rx descriptor for current buffer
6910 * @skb: current socket buffer containing buffer in progress
2e334eee 6911 *
b980ac18
JK		 6912 * This function updates next to clean. If the buffer is an EOP buffer
6913 * this function exits returning false, otherwise it will place the
6914 * sk_buff in the next buffer to be chained and return true indicating
6915 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6916 **/
6917static bool igb_is_non_eop(struct igb_ring *rx_ring,
6918 union e1000_adv_rx_desc *rx_desc)
6919{
6920 u32 ntc = rx_ring->next_to_clean + 1;
6921
6922 /* fetch, update, and store next to clean */
6923 ntc = (ntc < rx_ring->count) ? ntc : 0;
6924 rx_ring->next_to_clean = ntc;
6925
6926 prefetch(IGB_RX_DESC(rx_ring, ntc));
6927
6928 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6929 return false;
6930
6931 return true;
6932}
6933
1a1c225b 6934/**
b980ac18
JK		 6935 * igb_cleanup_headers - Correct corrupted or empty headers
6936 * @rx_ring: rx descriptor ring packet is being transacted on
6937 * @rx_desc: pointer to the EOP Rx descriptor
6938 * @skb: pointer to current skb being fixed
1a1c225b 6939 *
b980ac18
JK		 6940 * Address the case where we are pulling data in on pages only
6941 * and as such no data is present in the skb header.
1a1c225b 6942 *
b980ac18
JK		 6943 * In addition if skb is not at least 60 bytes we need to pad it so that
6944 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6945 *
b980ac18 6946 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6947 **/
6948static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6949 union e1000_adv_rx_desc *rx_desc,
6950 struct sk_buff *skb)
6951{
1a1c225b
AD		 6952 if (unlikely((igb_test_staterr(rx_desc,
6953 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6954 struct net_device *netdev = rx_ring->netdev;
6955 if (!(netdev->features & NETIF_F_RXALL)) {
6956 dev_kfree_skb_any(skb);
6957 return true;
6958 }
6959 }
6960
a94d9e22
AD		 6961 /* if eth_skb_pad returns an error the skb was freed */
6962 if (eth_skb_pad(skb))
6963 return true;
1a1c225b
AD		 6964
6965 return false;
2d94d8ab
AD		 6966}
6967
db2ee5bd 6968/**
b980ac18
JK		 6969 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6970 * @rx_ring: rx descriptor ring packet is being transacted on
6971 * @rx_desc: pointer to the EOP Rx descriptor
6972 * @skb: pointer to current skb being populated
db2ee5bd 6973 *
b980ac18
JK		 6974 * This function checks the ring, descriptor, and packet information in
6975 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6976 * other fields within the skb.
db2ee5bd
AD		 6977 **/
6978static void igb_process_skb_fields(struct igb_ring *rx_ring,
6979 union e1000_adv_rx_desc *rx_desc,
6980 struct sk_buff *skb)
6981{
6982 struct net_device *dev = rx_ring->netdev;
6983
6984 igb_rx_hash(rx_ring, rx_desc, skb);
6985
6986 igb_rx_checksum(rx_ring, rx_desc, skb);
6987
5499a968
JK		 6988 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6989 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6990 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6991
f646968f 6992 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6993 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6994 u16 vid;
9005df38 6995
db2ee5bd
AD		 6996 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6997 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6998 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6999 else
7000 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7001
86a9bad3 7002 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 7003 }
7004
7005 skb_record_rx_queue(skb, rx_ring->queue_index);
7006
7007 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7008}
7009
32b3e08f 7010static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 7011{
0ba82994 7012 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 7013 struct sk_buff *skb = rx_ring->skb;
9d5c8243 7014 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 7015 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 7016
57ba34c9 7017 while (likely(total_packets < budget)) {
2e334eee 7018 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7019
2e334eee
AD		 7020 /* return some buffers to hardware, one at a time is too slow */
7021 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7022 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7023 cleaned_count = 0;
7024 }
bf36c1a0 7025
2e334eee 7026 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7027
124b74c1 7028 if (!rx_desc->wb.upper.status_error)
2e334eee 7029 break;
9d5c8243 7030
74e238ea
AD		 7031 /* This memory barrier is needed to keep us from reading
7032 * any other fields out of the rx_desc until we know the
124b74c1 7033 * descriptor has been written back
74e238ea 7034 */
124b74c1 7035 dma_rmb();
74e238ea 7036
2e334eee 7037 /* retrieve a buffer from the ring */
f9d40f6a 7038 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7039
2e334eee
AD		 7040 /* exit if we failed to retrieve a buffer */
7041 if (!skb)
7042 break;
1a1c225b 7043
2e334eee 7044 cleaned_count++;
1a1c225b 7045
2e334eee
AD		 7046 /* fetch next buffer in frame if non-eop */
7047 if (igb_is_non_eop(rx_ring, rx_desc))
7048 continue;
1a1c225b
AD		 7049
7050 /* verify the packet layout is correct */
7051 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7052 skb = NULL;
7053 continue;
9d5c8243 7054 }
9d5c8243 7055
db2ee5bd 7056 /* probably a little skewed due to removing CRC */
3ceb90fd 7057 total_bytes += skb->len;
3ceb90fd 7058
db2ee5bd
AD		 7059 /* populate checksum, timestamp, VLAN, and protocol */
7060 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7061
b2cb09b1 7062 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7063
1a1c225b
AD		 7064 /* reset skb pointer */
7065 skb = NULL;
7066
2e334eee
AD		 7067 /* update budget accounting */
7068 total_packets++;
57ba34c9 7069 }
bf36c1a0 7070
1a1c225b
AD		 7071 /* place incomplete frames back on ring for completion */
7072 rx_ring->skb = skb;
7073
12dcd86b 7074 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7075 rx_ring->rx_stats.packets += total_packets;
7076 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7077 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7078 q_vector->rx.total_packets += total_packets;
7079 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7080
7081 if (cleaned_count)
cd392f5c 7082 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7083
32b3e08f 7084 return total_packets;
9d5c8243
AK		 7085}
7086
c023cd88 7087static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7088 struct igb_rx_buffer *bi)
c023cd88
AD		 7089{
7090 struct page *page = bi->page;
cbc8e55f 7091 dma_addr_t dma;
c023cd88 7092
cbc8e55f
AD		 7093 /* since we are recycling buffers we should seldom need to alloc */
7094 if (likely(page))
c023cd88
AD		 7095 return true;
7096
cbc8e55f 7097 /* alloc new page for storage */
42b17f09 7098 page = dev_alloc_page();
cbc8e55f
AD		 7099 if (unlikely(!page)) {
7100 rx_ring->rx_stats.alloc_failed++;
7101 return false;
c023cd88
AD		 7102 }
7103
cbc8e55f
AD		 7104 /* map page for use */
7105 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7106
b980ac18 7107 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7108 * there isn't much point in holding memory we can't use
7109 */
1a1c225b 7110 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7111 __free_page(page);
7112
c023cd88
AD		 7113 rx_ring->rx_stats.alloc_failed++;
7114 return false;
7115 }
7116
1a1c225b 7117 bi->dma = dma;
cbc8e55f
AD		 7118 bi->page = page;
7119 bi->page_offset = 0;
1a1c225b 7120
c023cd88
AD		 7121 return true;
7122}
7123
9d5c8243 7124/**
b980ac18
JK		 7125 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7126 * @adapter: address of board private structure
9d5c8243 7127 **/
cd392f5c 7128void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7129{
9d5c8243 7130 union e1000_adv_rx_desc *rx_desc;
06034649 7131 struct igb_rx_buffer *bi;
c023cd88 7132 u16 i = rx_ring->next_to_use;
9d5c8243 7133
cbc8e55f
AD		 7134 /* nothing to do */
7135 if (!cleaned_count)
7136 return;
7137
60136906 7138 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7139 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7140 i -= rx_ring->count;
9d5c8243 7141
cbc8e55f 7142 do {
1a1c225b 7143 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7144 break;
9d5c8243 7145
b980ac18 7146 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7147 * because each write-back erases this info.
7148 */
f9d40f6a 7149 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7150
c023cd88
AD		 7151 rx_desc++;
7152 bi++;
9d5c8243 7153 i++;
c023cd88 7154 if (unlikely(!i)) {
60136906 7155 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7156 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7157 i -= rx_ring->count;
7158 }
7159
95dd44b4
AD		 7160 /* clear the status bits for the next_to_use descriptor */
7161 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7162
7163 cleaned_count--;
7164 } while (cleaned_count);
9d5c8243 7165
c023cd88
AD		 7166 i += rx_ring->count;
7167
9d5c8243 7168 if (rx_ring->next_to_use != i) {
cbc8e55f 7169 /* record the next descriptor to use */
9d5c8243 7170 rx_ring->next_to_use = i;
9d5c8243 7171
cbc8e55f
AD		 7172 /* update next to alloc since we have filled the ring */
7173 rx_ring->next_to_alloc = i;
7174
b980ac18 7175 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7176 * know there are new descriptors to fetch. (Only
7177 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7178 * such as IA-64).
7179 */
9d5c8243 7180 wmb();
fce99e34 7181 writel(i, rx_ring->tail);
9d5c8243
AK		 7182 }
7183}
7184
7185/**
7186 * igb_mii_ioctl -
7187 * @netdev:
7188 * @ifreq:
7189 * @cmd:
7190 **/
7191static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7192{
7193 struct igb_adapter *adapter = netdev_priv(netdev);
7194 struct mii_ioctl_data *data = if_mii(ifr);
7195
7196 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7197 return -EOPNOTSUPP;
7198
7199 switch (cmd) {
7200 case SIOCGMIIPHY:
7201 data->phy_id = adapter->hw.phy.addr;
7202 break;
7203 case SIOCGMIIREG:
f5f4cf08 7204 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7205 &data->val_out))
9d5c8243
AK		 7206 return -EIO;
7207 break;
7208 case SIOCSMIIREG:
7209 default:
7210 return -EOPNOTSUPP;
7211 }
7212 return 0;
7213}
7214
7215/**
7216 * igb_ioctl -
7217 * @netdev:
7218 * @ifreq:
7219 * @cmd:
7220 **/
7221static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7222{
7223 switch (cmd) {
7224 case SIOCGMIIPHY:
7225 case SIOCGMIIREG:
7226 case SIOCSMIIREG:
7227 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7228 case SIOCGHWTSTAMP:
7229 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7230 case SIOCSHWTSTAMP:
6ab5f7b2 7231 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7232 default:
7233 return -EOPNOTSUPP;
7234 }
7235}
7236
94826487
TF		 7237void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7238{
7239 struct igb_adapter *adapter = hw->back;
7240
7241 pci_read_config_word(adapter->pdev, reg, value);
7242}
7243
7244void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7245{
7246 struct igb_adapter *adapter = hw->back;
7247
7248 pci_write_config_word(adapter->pdev, reg, *value);
7249}
7250
009bc06e
AD		 7251s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7252{
7253 struct igb_adapter *adapter = hw->back;
009bc06e 7254
23d028cc 7255 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7256 return -E1000_ERR_CONFIG;
7257
009bc06e
AD		 7258 return 0;
7259}
7260
7261s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7262{
7263 struct igb_adapter *adapter = hw->back;
009bc06e 7264
23d028cc 7265 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7266 return -E1000_ERR_CONFIG;
7267
009bc06e
AD		 7268 return 0;
7269}
7270
c8f44aff 7271static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7272{
7273 struct igb_adapter *adapter = netdev_priv(netdev);
7274 struct e1000_hw *hw = &adapter->hw;
7275 u32 ctrl, rctl;
f646968f 7276 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7277
5faf030c 7278 if (enable) {
9d5c8243
AK		 7279 /* enable VLAN tag insert/strip */
7280 ctrl = rd32(E1000_CTRL);
7281 ctrl |= E1000_CTRL_VME;
7282 wr32(E1000_CTRL, ctrl);
7283
51466239 7284 /* Disable CFI check */
9d5c8243 7285 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7286 rctl &= ~E1000_RCTL_CFIEN;
7287 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7288 } else {
7289 /* disable VLAN tag insert/strip */
7290 ctrl = rd32(E1000_CTRL);
7291 ctrl &= ~E1000_CTRL_VME;
7292 wr32(E1000_CTRL, ctrl);
9d5c8243 7293 }
9d5c8243
AK		 7294}
7295
80d5c368
PM		 7296static int igb_vlan_rx_add_vid(struct net_device *netdev,
7297 __be16 proto, u16 vid)
9d5c8243
AK		 7298{
7299 struct igb_adapter *adapter = netdev_priv(netdev);
7300 struct e1000_hw *hw = &adapter->hw;
4ae196df 7301 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7302
51466239 7303 /* add the filter since PF can receive vlans w/o entry in vlvf */
16903caa
AD		 7304 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7305 igb_vfta_set(hw, vid, pf_id, true, !!vid);
7306
b2cb09b1 7307 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7308
7309 return 0;
9d5c8243
AK		 7310}
7311
80d5c368
PM		 7312static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7313 __be16 proto, u16 vid)
9d5c8243
AK		 7314{
7315 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 7316 int pf_id = adapter->vfs_allocated_count;
8b77c6b2 7317 struct e1000_hw *hw = &adapter->hw;
9d5c8243 7318
8b77c6b2 7319 /* remove VID from filter table */
16903caa
AD		 7320 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7321 igb_vfta_set(hw, vid, pf_id, false, true);
b2cb09b1
JP		 7322
7323 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7324
7325 return 0;
9d5c8243
AK		 7326}
7327
7328static void igb_restore_vlan(struct igb_adapter *adapter)
7329{
5982a556 7330 u16 vid = 1;
9d5c8243 7331
5faf030c 7332 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
5982a556 7333 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
5faf030c 7334
5982a556 7335 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7336 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7337}
7338
14ad2513 7339int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7340{
090b1795 7341 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7342 struct e1000_mac_info *mac = &adapter->hw.mac;
7343
7344 mac->autoneg = 0;
7345
14ad2513 7346 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7347 * for the switch() below to work
7348 */
14ad2513
DD		 7349 if ((spd & 1) || (dplx & ~1))
7350 goto err_inval;
7351
f502ef7d
AA		 7352 /* Fiber NIC's only allow 1000 gbps Full duplex
7353 * and 100Mbps Full duplex for 100baseFx sfp
7354 */
7355 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7356 switch (spd + dplx) {
7357 case SPEED_10 + DUPLEX_HALF:
7358 case SPEED_10 + DUPLEX_FULL:
7359 case SPEED_100 + DUPLEX_HALF:
7360 goto err_inval;
7361 default:
7362 break;
7363 }
7364 }
cd2638a8 7365
14ad2513 7366 switch (spd + dplx) {
9d5c8243
AK		 7367 case SPEED_10 + DUPLEX_HALF:
7368 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7369 break;
7370 case SPEED_10 + DUPLEX_FULL:
7371 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7372 break;
7373 case SPEED_100 + DUPLEX_HALF:
7374 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7375 break;
7376 case SPEED_100 + DUPLEX_FULL:
7377 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7378 break;
7379 case SPEED_1000 + DUPLEX_FULL:
7380 mac->autoneg = 1;
7381 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7382 break;
7383 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7384 default:
14ad2513 7385 goto err_inval;
9d5c8243 7386 }
8376dad0
JB		 7387
7388 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7389 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7390
9d5c8243 7391 return 0;
14ad2513
DD		 7392
7393err_inval:
7394 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7395 return -EINVAL;
9d5c8243
AK		 7396}
7397
749ab2cd
YZ		 7398static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7399 bool runtime)
9d5c8243
AK		 7400{
7401 struct net_device *netdev = pci_get_drvdata(pdev);
7402 struct igb_adapter *adapter = netdev_priv(netdev);
7403 struct e1000_hw *hw = &adapter->hw;
2d064c06 7404 u32 ctrl, rctl, status;
749ab2cd 7405 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7406#ifdef CONFIG_PM
7407 int retval = 0;
7408#endif
7409
7410 netif_device_detach(netdev);
7411
a88f10ec 7412 if (netif_running(netdev))
749ab2cd 7413 __igb_close(netdev, true);
a88f10ec 7414
047e0030 7415 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7416
7417#ifdef CONFIG_PM
7418 retval = pci_save_state(pdev);
7419 if (retval)
7420 return retval;
7421#endif
7422
7423 status = rd32(E1000_STATUS);
7424 if (status & E1000_STATUS_LU)
7425 wufc &= ~E1000_WUFC_LNKC;
7426
7427 if (wufc) {
7428 igb_setup_rctl(adapter);
ff41f8dc 7429 igb_set_rx_mode(netdev);
9d5c8243
AK		 7430
7431 /* turn on all-multi mode if wake on multicast is enabled */
7432 if (wufc & E1000_WUFC_MC) {
7433 rctl = rd32(E1000_RCTL);
7434 rctl |= E1000_RCTL_MPE;
7435 wr32(E1000_RCTL, rctl);
7436 }
7437
7438 ctrl = rd32(E1000_CTRL);
7439 /* advertise wake from D3Cold */
7440 #define E1000_CTRL_ADVD3WUC 0x00100000
7441 /* phy power management enable */
7442 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7443 ctrl |= E1000_CTRL_ADVD3WUC;
7444 wr32(E1000_CTRL, ctrl);
7445
9d5c8243 7446 /* Allow time for pending master requests to run */
330a6d6a 7447 igb_disable_pcie_master(hw);
9d5c8243
AK		 7448
7449 wr32(E1000_WUC, E1000_WUC_PME_EN);
7450 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7451 } else {
7452 wr32(E1000_WUC, 0);
7453 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7454 }
7455
3fe7c4c9
RW		 7456 *enable_wake = wufc || adapter->en_mng_pt;
7457 if (!*enable_wake)
88a268c1
NN		 7458 igb_power_down_link(adapter);
7459 else
7460 igb_power_up_link(adapter);
9d5c8243
AK		 7461
7462 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7463 * would have already happened in close and is redundant.
7464 */
9d5c8243
AK		 7465 igb_release_hw_control(adapter);
7466
7467 pci_disable_device(pdev);
7468
9d5c8243
AK		 7469 return 0;
7470}
7471
7472#ifdef CONFIG_PM
d9dd966d 7473#ifdef CONFIG_PM_SLEEP
749ab2cd 7474static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7475{
7476 int retval;
7477 bool wake;
749ab2cd 7478 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7479
749ab2cd 7480 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7481 if (retval)
7482 return retval;
7483
7484 if (wake) {
7485 pci_prepare_to_sleep(pdev);
7486 } else {
7487 pci_wake_from_d3(pdev, false);
7488 pci_set_power_state(pdev, PCI_D3hot);
7489 }
7490
7491 return 0;
7492}
d9dd966d 7493#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7494
749ab2cd 7495static int igb_resume(struct device *dev)
9d5c8243 7496{
749ab2cd 7497 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7498 struct net_device *netdev = pci_get_drvdata(pdev);
7499 struct igb_adapter *adapter = netdev_priv(netdev);
7500 struct e1000_hw *hw = &adapter->hw;
7501 u32 err;
7502
7503 pci_set_power_state(pdev, PCI_D0);
7504 pci_restore_state(pdev);
b94f2d77 7505 pci_save_state(pdev);
42bfd33a 7506
17a402a0
CW		 7507 if (!pci_device_is_present(pdev))
7508 return -ENODEV;
aed5dec3 7509 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7510 if (err) {
7511 dev_err(&pdev->dev,
7512 "igb: Cannot enable PCI device from suspend\n");
7513 return err;
7514 }
7515 pci_set_master(pdev);
7516
7517 pci_enable_wake(pdev, PCI_D3hot, 0);
7518 pci_enable_wake(pdev, PCI_D3cold, 0);
7519
53c7d064 7520 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec 7521 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3eb14ea8 7522 rtnl_unlock();
a88f10ec 7523 return -ENOMEM;
9d5c8243
AK		 7524 }
7525
9d5c8243 7526 igb_reset(adapter);
a8564f03
AD		 7527
7528 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7529 * driver.
7530 */
a8564f03
AD		 7531 igb_get_hw_control(adapter);
7532
9d5c8243
AK		 7533 wr32(E1000_WUS, ~0);
7534
749ab2cd 7535 if (netdev->flags & IFF_UP) {
0c2cc02e 7536 rtnl_lock();
749ab2cd 7537 err = __igb_open(netdev, true);
0c2cc02e 7538 rtnl_unlock();
a88f10ec
AD		 7539 if (err)
7540 return err;
7541 }
9d5c8243
AK		 7542
7543 netif_device_attach(netdev);
749ab2cd
YZ		 7544 return 0;
7545}
7546
749ab2cd
YZ		 7547static int igb_runtime_idle(struct device *dev)
7548{
7549 struct pci_dev *pdev = to_pci_dev(dev);
7550 struct net_device *netdev = pci_get_drvdata(pdev);
7551 struct igb_adapter *adapter = netdev_priv(netdev);
7552
7553 if (!igb_has_link(adapter))
7554 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7555
7556 return -EBUSY;
7557}
7558
7559static int igb_runtime_suspend(struct device *dev)
7560{
7561 struct pci_dev *pdev = to_pci_dev(dev);
7562 int retval;
7563 bool wake;
7564
7565 retval = __igb_shutdown(pdev, &wake, 1);
7566 if (retval)
7567 return retval;
7568
7569 if (wake) {
7570 pci_prepare_to_sleep(pdev);
7571 } else {
7572 pci_wake_from_d3(pdev, false);
7573 pci_set_power_state(pdev, PCI_D3hot);
7574 }
9d5c8243 7575
9d5c8243
AK		 7576 return 0;
7577}
749ab2cd
YZ		 7578
7579static int igb_runtime_resume(struct device *dev)
7580{
7581 return igb_resume(dev);
7582}
d61c81cb 7583#endif /* CONFIG_PM */
9d5c8243
AK		 7584
7585static void igb_shutdown(struct pci_dev *pdev)
7586{
3fe7c4c9
RW		 7587 bool wake;
7588
749ab2cd 7589 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7590
7591 if (system_state == SYSTEM_POWER_OFF) {
7592 pci_wake_from_d3(pdev, wake);
7593 pci_set_power_state(pdev, PCI_D3hot);
7594 }
9d5c8243
AK		 7595}
7596
fa44f2f1
GR		 7597#ifdef CONFIG_PCI_IOV
7598static int igb_sriov_reinit(struct pci_dev *dev)
7599{
7600 struct net_device *netdev = pci_get_drvdata(dev);
7601 struct igb_adapter *adapter = netdev_priv(netdev);
7602 struct pci_dev *pdev = adapter->pdev;
7603
7604 rtnl_lock();
7605
7606 if (netif_running(netdev))
7607 igb_close(netdev);
76252723
SA		 7608 else
7609 igb_reset(adapter);
fa44f2f1
GR		 7610
7611 igb_clear_interrupt_scheme(adapter);
7612
7613 igb_init_queue_configuration(adapter);
7614
7615 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7616 rtnl_unlock();
fa44f2f1
GR		 7617 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7618 return -ENOMEM;
7619 }
7620
7621 if (netif_running(netdev))
7622 igb_open(netdev);
7623
7624 rtnl_unlock();
7625
7626 return 0;
7627}
7628
7629static int igb_pci_disable_sriov(struct pci_dev *dev)
7630{
7631 int err = igb_disable_sriov(dev);
7632
7633 if (!err)
7634 err = igb_sriov_reinit(dev);
7635
7636 return err;
7637}
7638
7639static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7640{
7641 int err = igb_enable_sriov(dev, num_vfs);
7642
7643 if (err)
7644 goto out;
7645
7646 err = igb_sriov_reinit(dev);
7647 if (!err)
7648 return num_vfs;
7649
7650out:
7651 return err;
7652}
7653
7654#endif
7655static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7656{
7657#ifdef CONFIG_PCI_IOV
7658 if (num_vfs == 0)
7659 return igb_pci_disable_sriov(dev);
7660 else
7661 return igb_pci_enable_sriov(dev, num_vfs);
7662#endif
7663 return 0;
7664}
7665
9d5c8243 7666#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7667/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7668 * without having to re-enable interrupts. It's not called while
7669 * the interrupt routine is executing.
7670 */
7671static void igb_netpoll(struct net_device *netdev)
7672{
7673 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7674 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7675 struct igb_q_vector *q_vector;
9d5c8243 7676 int i;
9d5c8243 7677
047e0030 7678 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7679 q_vector = adapter->q_vector[i];
cd14ef54 7680 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7681 wr32(E1000_EIMC, q_vector->eims_value);
7682 else
7683 igb_irq_disable(adapter);
047e0030 7684 napi_schedule(&q_vector->napi);
eebbbdba 7685 }
9d5c8243
AK		 7686}
7687#endif /* CONFIG_NET_POLL_CONTROLLER */
7688
7689/**
b980ac18
JK		 7690 * igb_io_error_detected - called when PCI error is detected
7691 * @pdev: Pointer to PCI device
7692 * @state: The current pci connection state
9d5c8243 7693 *
b980ac18
JK		 7694 * This function is called after a PCI bus error affecting
7695 * this device has been detected.
7696 **/
9d5c8243
AK		 7697static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7698 pci_channel_state_t state)
7699{
7700 struct net_device *netdev = pci_get_drvdata(pdev);
7701 struct igb_adapter *adapter = netdev_priv(netdev);
7702
7703 netif_device_detach(netdev);
7704
59ed6eec
AD		 7705 if (state == pci_channel_io_perm_failure)
7706 return PCI_ERS_RESULT_DISCONNECT;
7707
9d5c8243
AK		 7708 if (netif_running(netdev))
7709 igb_down(adapter);
7710 pci_disable_device(pdev);
7711
7712 /* Request a slot slot reset. */
7713 return PCI_ERS_RESULT_NEED_RESET;
7714}
7715
7716/**
b980ac18
JK		 7717 * igb_io_slot_reset - called after the pci bus has been reset.
7718 * @pdev: Pointer to PCI device
9d5c8243 7719 *
b980ac18
JK		 7720 * Restart the card from scratch, as if from a cold-boot. Implementation
7721 * resembles the first-half of the igb_resume routine.
7722 **/
9d5c8243
AK		 7723static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7724{
7725 struct net_device *netdev = pci_get_drvdata(pdev);
7726 struct igb_adapter *adapter = netdev_priv(netdev);
7727 struct e1000_hw *hw = &adapter->hw;
40a914fa 7728 pci_ers_result_t result;
42bfd33a 7729 int err;
9d5c8243 7730
aed5dec3 7731 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7732 dev_err(&pdev->dev,
7733 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7734 result = PCI_ERS_RESULT_DISCONNECT;
7735 } else {
7736 pci_set_master(pdev);
7737 pci_restore_state(pdev);
b94f2d77 7738 pci_save_state(pdev);
9d5c8243 7739
40a914fa
AD		 7740 pci_enable_wake(pdev, PCI_D3hot, 0);
7741 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7742
40a914fa
AD		 7743 igb_reset(adapter);
7744 wr32(E1000_WUS, ~0);
7745 result = PCI_ERS_RESULT_RECOVERED;
7746 }
9d5c8243 7747
ea943d41
JK		 7748 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7749 if (err) {
b980ac18
JK		 7750 dev_err(&pdev->dev,
7751 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7752 err);
ea943d41
JK		 7753 /* non-fatal, continue */
7754 }
40a914fa
AD		 7755
7756 return result;
9d5c8243
AK		 7757}
7758
7759/**
b980ac18
JK		 7760 * igb_io_resume - called when traffic can start flowing again.
7761 * @pdev: Pointer to PCI device
9d5c8243 7762 *
b980ac18
JK		 7763 * This callback is called when the error recovery driver tells us that
7764 * its OK to resume normal operation. Implementation resembles the
7765 * second-half of the igb_resume routine.
9d5c8243
AK		 7766 */
7767static void igb_io_resume(struct pci_dev *pdev)
7768{
7769 struct net_device *netdev = pci_get_drvdata(pdev);
7770 struct igb_adapter *adapter = netdev_priv(netdev);
7771
9d5c8243
AK		 7772 if (netif_running(netdev)) {
7773 if (igb_up(adapter)) {
7774 dev_err(&pdev->dev, "igb_up failed after reset\n");
7775 return;
7776 }
7777 }
7778
7779 netif_device_attach(netdev);
7780
7781 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7782 * driver.
7783 */
9d5c8243 7784 igb_get_hw_control(adapter);
9d5c8243
AK		 7785}
7786
26ad9178 7787static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7788 u8 qsel)
26ad9178 7789{
26ad9178 7790 struct e1000_hw *hw = &adapter->hw;
c3278587 7791 u32 rar_low, rar_high;
26ad9178
AD		 7792
7793 /* HW expects these in little endian so we reverse the byte order
c3278587 7794 * from network order (big endian) to CPU endian
26ad9178 7795 */
c3278587
AD		 7796 rar_low = le32_to_cpup((__be32 *)(addr));
7797 rar_high = le16_to_cpup((__be16 *)(addr + 4));
26ad9178
AD		 7798
7799 /* Indicate to hardware the Address is Valid. */
7800 rar_high |= E1000_RAH_AV;
7801
7802 if (hw->mac.type == e1000_82575)
7803 rar_high |= E1000_RAH_POOL_1 * qsel;
7804 else
7805 rar_high |= E1000_RAH_POOL_1 << qsel;
7806
7807 wr32(E1000_RAL(index), rar_low);
7808 wrfl();
7809 wr32(E1000_RAH(index), rar_high);
7810 wrfl();
7811}
7812
4ae196df 7813static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7814 int vf, unsigned char *mac_addr)
4ae196df
AD		 7815{
7816 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7817 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7818 * towards the first, as a result a collision should not be possible
7819 */
ff41f8dc 7820 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7821
37680117 7822 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7823
26ad9178 7824 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7825
7826 return 0;
7827}
7828
8151d294
WM		 7829static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7830{
7831 struct igb_adapter *adapter = netdev_priv(netdev);
7832 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7833 return -EINVAL;
7834 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7835 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7836 dev_info(&adapter->pdev->dev,
7837 "Reload the VF driver to make this change effective.");
8151d294 7838 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7839 dev_warn(&adapter->pdev->dev,
7840 "The VF MAC address has been set, but the PF device is not up.\n");
7841 dev_warn(&adapter->pdev->dev,
7842 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7843 }
7844 return igb_set_vf_mac(adapter, vf, mac);
7845}
7846
17dc566c
LL		 7847static int igb_link_mbps(int internal_link_speed)
7848{
7849 switch (internal_link_speed) {
7850 case SPEED_100:
7851 return 100;
7852 case SPEED_1000:
7853 return 1000;
7854 default:
7855 return 0;
7856 }
7857}
7858
7859static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7860 int link_speed)
7861{
7862 int rf_dec, rf_int;
7863 u32 bcnrc_val;
7864
7865 if (tx_rate != 0) {
7866 /* Calculate the rate factor values to set */
7867 rf_int = link_speed / tx_rate;
7868 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7869 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7870 tx_rate;
17dc566c
LL		 7871
7872 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7873 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7874 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7875 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7876 } else {
7877 bcnrc_val = 0;
7878 }
7879
7880 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7881 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7882 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7883 */
7884 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7885 wr32(E1000_RTTBCNRC, bcnrc_val);
7886}
7887
7888static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7889{
7890 int actual_link_speed, i;
7891 bool reset_rate = false;
7892
7893 /* VF TX rate limit was not set or not supported */
7894 if ((adapter->vf_rate_link_speed == 0) ||
7895 (adapter->hw.mac.type != e1000_82576))
7896 return;
7897
7898 actual_link_speed = igb_link_mbps(adapter->link_speed);
7899 if (actual_link_speed != adapter->vf_rate_link_speed) {
7900 reset_rate = true;
7901 adapter->vf_rate_link_speed = 0;
7902 dev_info(&adapter->pdev->dev,
b980ac18 7903 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7904 }
7905
7906 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7907 if (reset_rate)
7908 adapter->vf_data[i].tx_rate = 0;
7909
7910 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7911 adapter->vf_data[i].tx_rate,
7912 actual_link_speed);
17dc566c
LL		 7913 }
7914}
7915
ed616689
SC		 7916static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7917 int min_tx_rate, int max_tx_rate)
8151d294 7918{
17dc566c
LL		 7919 struct igb_adapter *adapter = netdev_priv(netdev);
7920 struct e1000_hw *hw = &adapter->hw;
7921 int actual_link_speed;
7922
7923 if (hw->mac.type != e1000_82576)
7924 return -EOPNOTSUPP;
7925
ed616689
SC		 7926 if (min_tx_rate)
7927 return -EINVAL;
7928
17dc566c
LL		 7929 actual_link_speed = igb_link_mbps(adapter->link_speed);
7930 if ((vf >= adapter->vfs_allocated_count) ||
7931 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7932 (max_tx_rate < 0) ||
7933 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7934 return -EINVAL;
7935
7936 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7937 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7938 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7939
7940 return 0;
8151d294
WM		 7941}
7942
70ea4783
LL		 7943static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7944 bool setting)
7945{
7946 struct igb_adapter *adapter = netdev_priv(netdev);
7947 struct e1000_hw *hw = &adapter->hw;
7948 u32 reg_val, reg_offset;
7949
7950 if (!adapter->vfs_allocated_count)
7951 return -EOPNOTSUPP;
7952
7953 if (vf >= adapter->vfs_allocated_count)
7954 return -EINVAL;
7955
7956 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7957 reg_val = rd32(reg_offset);
7958 if (setting)
7959 reg_val |= ((1 << vf) |
7960 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7961 else
7962 reg_val &= ~((1 << vf) |
7963 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7964 wr32(reg_offset, reg_val);
7965
7966 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7967 return 0;
70ea4783
LL		 7968}
7969
8151d294
WM		 7970static int igb_ndo_get_vf_config(struct net_device *netdev,
7971 int vf, struct ifla_vf_info *ivi)
7972{
7973 struct igb_adapter *adapter = netdev_priv(netdev);
7974 if (vf >= adapter->vfs_allocated_count)
7975 return -EINVAL;
7976 ivi->vf = vf;
7977 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7978 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7979 ivi->min_tx_rate = 0;
8151d294
WM		 7980 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7981 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7982 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7983 return 0;
7984}
7985
4ae196df
AD		 7986static void igb_vmm_control(struct igb_adapter *adapter)
7987{
7988 struct e1000_hw *hw = &adapter->hw;
10d8e907 7989 u32 reg;
4ae196df 7990
52a1dd4d
AD		 7991 switch (hw->mac.type) {
7992 case e1000_82575:
f96a8a0b
CW		 7993 case e1000_i210:
7994 case e1000_i211:
ceb5f13b 7995 case e1000_i354:
52a1dd4d
AD		 7996 default:
7997 /* replication is not supported for 82575 */
4ae196df 7998 return;
52a1dd4d
AD		 7999 case e1000_82576:
8000 /* notify HW that the MAC is adding vlan tags */
8001 reg = rd32(E1000_DTXCTL);
8002 reg |= E1000_DTXCTL_VLAN_ADDED;
8003 wr32(E1000_DTXCTL, reg);
b26141d4 8004 /* Fall through */
52a1dd4d
AD		 8005 case e1000_82580:
8006 /* enable replication vlan tag stripping */
8007 reg = rd32(E1000_RPLOLR);
8008 reg |= E1000_RPLOLR_STRVLAN;
8009 wr32(E1000_RPLOLR, reg);
b26141d4 8010 /* Fall through */
d2ba2ed8
AD		 8011 case e1000_i350:
8012 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8013 break;
8014 }
10d8e907 8015
d4960307
AD		 8016 if (adapter->vfs_allocated_count) {
8017 igb_vmdq_set_loopback_pf(hw, true);
8018 igb_vmdq_set_replication_pf(hw, true);
13800469 8019 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8020 adapter->vfs_allocated_count);
d4960307
AD		 8021 } else {
8022 igb_vmdq_set_loopback_pf(hw, false);
8023 igb_vmdq_set_replication_pf(hw, false);
8024 }
4ae196df
AD		 8025}
8026
b6e0c419
CW		 8027static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8028{
8029 struct e1000_hw *hw = &adapter->hw;
8030 u32 dmac_thr;
8031 u16 hwm;
8032
8033 if (hw->mac.type > e1000_82580) {
8034 if (adapter->flags & IGB_FLAG_DMAC) {
8035 u32 reg;
8036
8037 /* force threshold to 0. */
8038 wr32(E1000_DMCTXTH, 0);
8039
b980ac18 8040 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8041 * than the Rx threshold. Set hwm to PBA - max frame
8042 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8043 */
45693bcb 8044 hwm = 64 * (pba - 6);
e8c626e9
MV		 8045 reg = rd32(E1000_FCRTC);
8046 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8047 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8048 & E1000_FCRTC_RTH_COAL_MASK);
8049 wr32(E1000_FCRTC, reg);
8050
b980ac18 8051 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8052 * frame size, capping it at PBA - 10KB.
8053 */
45693bcb 8054 dmac_thr = pba - 10;
b6e0c419
CW		 8055 reg = rd32(E1000_DMACR);
8056 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8057 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8058 & E1000_DMACR_DMACTHR_MASK);
8059
8060 /* transition to L0x or L1 if available..*/
8061 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8062
8063 /* watchdog timer= +-1000 usec in 32usec intervals */
8064 reg |= (1000 >> 5);
0c02dd98
MV		 8065
8066 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8067 if (hw->mac.type != e1000_i354)
8068 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8069
b6e0c419
CW		 8070 wr32(E1000_DMACR, reg);
8071
b980ac18 8072 /* no lower threshold to disable
b6e0c419
CW		 8073 * coalescing(smart fifb)-UTRESH=0
8074 */
8075 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8076
8077 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8078
8079 wr32(E1000_DMCTLX, reg);
8080
b980ac18 8081 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8082 * DMA coal
8083 */
8084 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8085 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8086
b980ac18 8087 /* make low power state decision controlled
b6e0c419
CW		 8088 * by DMA coal
8089 */
8090 reg = rd32(E1000_PCIEMISC);
8091 reg &= ~E1000_PCIEMISC_LX_DECISION;
8092 wr32(E1000_PCIEMISC, reg);
8093 } /* endif adapter->dmac is not disabled */
8094 } else if (hw->mac.type == e1000_82580) {
8095 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8096
b6e0c419
CW		 8097 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8098 wr32(E1000_DMACR, 0);
8099 }
8100}
8101
b980ac18
JK		 8102/**
8103 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8104 * @hw: pointer to hardware structure
8105 * @byte_offset: byte offset to read
8106 * @dev_addr: device address
8107 * @data: value read
8108 *
8109 * Performs byte read operation over I2C interface at
8110 * a specified device address.
b980ac18 8111 **/
441fc6fd 8112s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8113 u8 dev_addr, u8 *data)
441fc6fd
CW		 8114{
8115 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8116 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8117 s32 status;
8118 u16 swfw_mask = 0;
8119
8120 if (!this_client)
8121 return E1000_ERR_I2C;
8122
8123 swfw_mask = E1000_SWFW_PHY0_SM;
8124
23d87824 8125 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8126 return E1000_ERR_SWFW_SYNC;
8127
8128 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8129 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8130
8131 if (status < 0)
8132 return E1000_ERR_I2C;
8133 else {
8134 *data = status;
23d87824 8135 return 0;
441fc6fd
CW		 8136 }
8137}
8138
b980ac18
JK		 8139/**
8140 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8141 * @hw: pointer to hardware structure
8142 * @byte_offset: byte offset to write
8143 * @dev_addr: device address
8144 * @data: value to write
8145 *
8146 * Performs byte write operation over I2C interface at
8147 * a specified device address.
b980ac18 8148 **/
441fc6fd 8149s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8150 u8 dev_addr, u8 data)
441fc6fd
CW		 8151{
8152 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8153 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8154 s32 status;
8155 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8156
8157 if (!this_client)
8158 return E1000_ERR_I2C;
8159
23d87824 8160 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8161 return E1000_ERR_SWFW_SYNC;
8162 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8163 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8164
8165 if (status)
8166 return E1000_ERR_I2C;
8167 else
23d87824 8168 return 0;
441fc6fd
CW		 8169
8170}
907b7835
LMV		 8171
8172int igb_reinit_queues(struct igb_adapter *adapter)
8173{
8174 struct net_device *netdev = adapter->netdev;
8175 struct pci_dev *pdev = adapter->pdev;
8176 int err = 0;
8177
8178 if (netif_running(netdev))
8179 igb_close(netdev);
8180
02ef6e1d 8181 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8182
8183 if (igb_init_interrupt_scheme(adapter, true)) {
8184 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8185 return -ENOMEM;
8186 }
8187
8188 if (netif_running(netdev))
8189 err = igb_open(netdev);
8190
8191 return err;
8192}
9d5c8243 8193/* igb_main.c */
Linux kernel - Deliverables
This page took 1.668343 seconds and 5 git commands to generate.