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igb: Update MTU so that it is always at least a standard frame size
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
65#define BUILD 3
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
113 /* required last entry */
114 {0, }
115};
116
117MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
118
119void igb_reset(struct igb_adapter *);
120static int igb_setup_all_tx_resources(struct igb_adapter *);
121static int igb_setup_all_rx_resources(struct igb_adapter *);
122static void igb_free_all_tx_resources(struct igb_adapter *);
123static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 124static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 125static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 126static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 127static int igb_sw_init(struct igb_adapter *);
128static int igb_open(struct net_device *);
129static int igb_close(struct net_device *);
53c7d064 130static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 131static void igb_configure_tx(struct igb_adapter *);
132static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 133static void igb_clean_all_tx_rings(struct igb_adapter *);
134static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 135static void igb_clean_tx_ring(struct igb_ring *);
136static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 137static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 138static void igb_update_phy_info(unsigned long);
139static void igb_watchdog(unsigned long);
140static void igb_watchdog_task(struct work_struct *);
cd392f5c 141static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 142static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
143 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 144static int igb_change_mtu(struct net_device *, int);
145static int igb_set_mac(struct net_device *, void *);
68d480c4 146static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 147static irqreturn_t igb_intr(int irq, void *);
148static irqreturn_t igb_intr_msi(int irq, void *);
149static irqreturn_t igb_msix_other(int irq, void *);
047e0030 150static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 151#ifdef CONFIG_IGB_DCA
047e0030 152static void igb_update_dca(struct igb_q_vector *);
fe4506b6 153static void igb_setup_dca(struct igb_adapter *);
421e02f0 154#endif /* CONFIG_IGB_DCA */
661086df 155static int igb_poll(struct napi_struct *, int);
13fde97a 156static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 157static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 158static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
159static void igb_tx_timeout(struct net_device *);
160static void igb_reset_task(struct work_struct *);
c8f44aff 161static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 162static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
163static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 164static void igb_restore_vlan(struct igb_adapter *);
26ad9178 165static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 166static void igb_ping_all_vfs(struct igb_adapter *);
167static void igb_msg_task(struct igb_adapter *);
4ae196df 168static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 169static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 170static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 171static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
172static int igb_ndo_set_vf_vlan(struct net_device *netdev,
173 int vf, u16 vlan, u8 qos);
174static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 175static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
176 bool setting);
8151d294
WM		 177static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
178 struct ifla_vf_info *ivi);
17dc566c 179static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 180
181#ifdef CONFIG_PCI_IOV
0224d663 182static int igb_vf_configure(struct igb_adapter *adapter, int vf);
46a01698 183#endif
9d5c8243 184
9d5c8243 185#ifdef CONFIG_PM
d9dd966d 186#ifdef CONFIG_PM_SLEEP
749ab2cd 187static int igb_suspend(struct device *);
d9dd966d 188#endif
749ab2cd
YZ		 189static int igb_resume(struct device *);
190#ifdef CONFIG_PM_RUNTIME
191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
194#endif
195static const struct dev_pm_ops igb_pm_ops = {
196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
198 igb_runtime_idle)
199};
9d5c8243
AK		 200#endif
201static void igb_shutdown(struct pci_dev *);
fa44f2f1 202static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 203#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 204static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
205static struct notifier_block dca_notifier = {
206 .notifier_call = igb_notify_dca,
207 .next = NULL,
208 .priority = 0
209};
210#endif
9d5c8243
AK		 211#ifdef CONFIG_NET_POLL_CONTROLLER
212/* for netdump / net console */
213static void igb_netpoll(struct net_device *);
214#endif
37680117 215#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 216static unsigned int max_vfs = 0;
217module_param(max_vfs, uint, 0);
218MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
219 "per physical function");
220#endif /* CONFIG_PCI_IOV */
221
9d5c8243
AK		 222static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
223 pci_channel_state_t);
224static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
225static void igb_io_resume(struct pci_dev *);
226
3646f0e5 227static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 228 .error_detected = igb_io_error_detected,
229 .slot_reset = igb_io_slot_reset,
230 .resume = igb_io_resume,
231};
232
b6e0c419 233static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 234
235static struct pci_driver igb_driver = {
236 .name = igb_driver_name,
237 .id_table = igb_pci_tbl,
238 .probe = igb_probe,
9f9a12f8 239 .remove = igb_remove,
9d5c8243 240#ifdef CONFIG_PM
749ab2cd 241 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 242#endif
243 .shutdown = igb_shutdown,
fa44f2f1 244 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 245 .err_handler = &igb_err_handler
246};
247
248MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
249MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
250MODULE_LICENSE("GPL");
251MODULE_VERSION(DRV_VERSION);
252
b3f4d599 253#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
254static int debug = -1;
255module_param(debug, int, 0);
256MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
257
c97ec42a
TI		 258struct igb_reg_info {
259 u32 ofs;
260 char *name;
261};
262
263static const struct igb_reg_info igb_reg_info_tbl[] = {
264
265 /* General Registers */
266 {E1000_CTRL, "CTRL"},
267 {E1000_STATUS, "STATUS"},
268 {E1000_CTRL_EXT, "CTRL_EXT"},
269
270 /* Interrupt Registers */
271 {E1000_ICR, "ICR"},
272
273 /* RX Registers */
274 {E1000_RCTL, "RCTL"},
275 {E1000_RDLEN(0), "RDLEN"},
276 {E1000_RDH(0), "RDH"},
277 {E1000_RDT(0), "RDT"},
278 {E1000_RXDCTL(0), "RXDCTL"},
279 {E1000_RDBAL(0), "RDBAL"},
280 {E1000_RDBAH(0), "RDBAH"},
281
282 /* TX Registers */
283 {E1000_TCTL, "TCTL"},
284 {E1000_TDBAL(0), "TDBAL"},
285 {E1000_TDBAH(0), "TDBAH"},
286 {E1000_TDLEN(0), "TDLEN"},
287 {E1000_TDH(0), "TDH"},
288 {E1000_TDT(0), "TDT"},
289 {E1000_TXDCTL(0), "TXDCTL"},
290 {E1000_TDFH, "TDFH"},
291 {E1000_TDFT, "TDFT"},
292 {E1000_TDFHS, "TDFHS"},
293 {E1000_TDFPC, "TDFPC"},
294
295 /* List Terminator */
296 {}
297};
298
b980ac18 299/* igb_regdump - register printout routine */
c97ec42a
TI		 300static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
301{
302 int n = 0;
303 char rname[16];
304 u32 regs[8];
305
306 switch (reginfo->ofs) {
307 case E1000_RDLEN(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDLEN(n));
310 break;
311 case E1000_RDH(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDH(n));
314 break;
315 case E1000_RDT(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RDT(n));
318 break;
319 case E1000_RXDCTL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RXDCTL(n));
322 break;
323 case E1000_RDBAL(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAL(n));
326 break;
327 case E1000_RDBAH(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAH(n));
330 break;
331 case E1000_TDBAL(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_RDBAL(n));
334 break;
335 case E1000_TDBAH(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDBAH(n));
338 break;
339 case E1000_TDLEN(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDLEN(n));
342 break;
343 case E1000_TDH(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDH(n));
346 break;
347 case E1000_TDT(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TDT(n));
350 break;
351 case E1000_TXDCTL(0):
352 for (n = 0; n < 4; n++)
353 regs[n] = rd32(E1000_TXDCTL(n));
354 break;
355 default:
876d2d6f 356 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 357 return;
358 }
359
360 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 361 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
362 regs[2], regs[3]);
c97ec42a
TI		 363}
364
b980ac18 365/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 366static void igb_dump(struct igb_adapter *adapter)
367{
368 struct net_device *netdev = adapter->netdev;
369 struct e1000_hw *hw = &adapter->hw;
370 struct igb_reg_info *reginfo;
c97ec42a
TI		 371 struct igb_ring *tx_ring;
372 union e1000_adv_tx_desc *tx_desc;
373 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 374 struct igb_ring *rx_ring;
375 union e1000_adv_rx_desc *rx_desc;
376 u32 staterr;
6ad4edfc 377 u16 i, n;
c97ec42a
TI		 378
379 if (!netif_msg_hw(adapter))
380 return;
381
382 /* Print netdevice Info */
383 if (netdev) {
384 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 385 pr_info("Device Name state trans_start "
386 "last_rx\n");
387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
388 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 389 }
390
391 /* Print Registers */
392 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 393 pr_info(" Register Name Value\n");
c97ec42a
TI		 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
395 reginfo->name; reginfo++) {
396 igb_regdump(hw, reginfo);
397 }
398
399 /* Print TX Ring Summary */
400 if (!netdev || !netif_running(netdev))
401 goto exit;
402
403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 405 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 406 struct igb_tx_buffer *buffer_info;
c97ec42a 407 tx_ring = adapter->tx_ring[n];
06034649 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
410 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 411 (u64)dma_unmap_addr(buffer_info, dma),
412 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 413 buffer_info->next_to_watch,
414 (u64)buffer_info->time_stamp);
c97ec42a
TI		 415 }
416
417 /* Print TX Rings */
418 if (!netif_msg_tx_done(adapter))
419 goto rx_ring_summary;
420
421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
422
423 /* Transmit Descriptor Formats
424 *
425 * Advanced Transmit Descriptor
426 * +--------------------------------------------------------------+
427 * 0 | Buffer Address [63:0] |
428 * +--------------------------------------------------------------+
429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
430 * +--------------------------------------------------------------+
431 * 63 46 45 40 39 38 36 35 32 31 24 15 0
432 */
433
434 for (n = 0; n < adapter->num_tx_queues; n++) {
435 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 436 pr_info("------------------------------------\n");
437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
438 pr_info("------------------------------------\n");
439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
440 "[bi->dma ] leng ntw timestamp "
441 "bi->skb\n");
c97ec42a
TI		 442
443 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 444 const char *next_desc;
06034649 445 struct igb_tx_buffer *buffer_info;
60136906 446 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 447 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 448 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 449 if (i == tx_ring->next_to_use &&
450 i == tx_ring->next_to_clean)
451 next_desc = " NTC/U";
452 else if (i == tx_ring->next_to_use)
453 next_desc = " NTU";
454 else if (i == tx_ring->next_to_clean)
455 next_desc = " NTC";
456 else
457 next_desc = "";
458
459 pr_info("T [0x%03X] %016llX %016llX %016llX"
460 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 461 le64_to_cpu(u0->a),
462 le64_to_cpu(u0->b),
c9f14bf3
AD		 463 (u64)dma_unmap_addr(buffer_info, dma),
464 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 465 buffer_info->next_to_watch,
466 (u64)buffer_info->time_stamp,
876d2d6f 467 buffer_info->skb, next_desc);
c97ec42a 468
b669588a 469 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 470 print_hex_dump(KERN_INFO, "",
471 DUMP_PREFIX_ADDRESS,
b669588a 472 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 473 dma_unmap_len(buffer_info, len),
474 true);
c97ec42a
TI		 475 }
476 }
477
478 /* Print RX Rings Summary */
479rx_ring_summary:
480 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 481 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 482 for (n = 0; n < adapter->num_rx_queues; n++) {
483 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 484 pr_info(" %5d %5X %5X\n",
485 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 486 }
487
488 /* Print RX Rings */
489 if (!netif_msg_rx_status(adapter))
490 goto exit;
491
492 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
493
494 /* Advanced Receive Descriptor (Read) Format
495 * 63 1 0
496 * +-----------------------------------------------------+
497 * 0 | Packet Buffer Address [63:1] |A0/NSE|
498 * +----------------------------------------------+------+
499 * 8 | Header Buffer Address [63:1] | DD |
500 * +-----------------------------------------------------+
501 *
502 *
503 * Advanced Receive Descriptor (Write-Back) Format
504 *
505 * 63 48 47 32 31 30 21 20 17 16 4 3 0
506 * +------------------------------------------------------+
507 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
508 * | Checksum Ident | | | | Type | Type |
509 * +------------------------------------------------------+
510 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
511 * +------------------------------------------------------+
512 * 63 48 47 32 31 20 19 0
513 */
514
515 for (n = 0; n < adapter->num_rx_queues; n++) {
516 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 517 pr_info("------------------------------------\n");
518 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
519 pr_info("------------------------------------\n");
520 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
521 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
522 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
523 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 524
525 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 526 const char *next_desc;
06034649
AD		 527 struct igb_rx_buffer *buffer_info;
528 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 529 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 530 u0 = (struct my_u0 *)rx_desc;
531 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 532
533 if (i == rx_ring->next_to_use)
534 next_desc = " NTU";
535 else if (i == rx_ring->next_to_clean)
536 next_desc = " NTC";
537 else
538 next_desc = "";
539
c97ec42a
TI		 540 if (staterr & E1000_RXD_STAT_DD) {
541 /* Descriptor Done */
1a1c225b
AD		 542 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
543 "RWB", i,
c97ec42a
TI		 544 le64_to_cpu(u0->a),
545 le64_to_cpu(u0->b),
1a1c225b 546 next_desc);
c97ec42a 547 } else {
1a1c225b
AD		 548 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
549 "R ", i,
c97ec42a
TI		 550 le64_to_cpu(u0->a),
551 le64_to_cpu(u0->b),
552 (u64)buffer_info->dma,
1a1c225b 553 next_desc);
c97ec42a 554
b669588a 555 if (netif_msg_pktdata(adapter) &&
1a1c225b 556 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 557 print_hex_dump(KERN_INFO, "",
558 DUMP_PREFIX_ADDRESS,
559 16, 1,
b669588a
ET		 560 page_address(buffer_info->page) +
561 buffer_info->page_offset,
de78d1f9 562 IGB_RX_BUFSZ, true);
c97ec42a
TI		 563 }
564 }
c97ec42a
TI		 565 }
566 }
567
568exit:
569 return;
570}
571
b980ac18
JK		 572/**
573 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 574 * @hw: pointer to hardware structure
575 * @i2cctl: Current value of I2CCTL register
576 *
577 * Returns the I2C data bit value
b980ac18 578 **/
441fc6fd
CW		 579static int igb_get_i2c_data(void *data)
580{
581 struct igb_adapter *adapter = (struct igb_adapter *)data;
582 struct e1000_hw *hw = &adapter->hw;
583 s32 i2cctl = rd32(E1000_I2CPARAMS);
584
585 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
586}
587
b980ac18
JK		 588/**
589 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 590 * @data: pointer to hardware structure
591 * @state: I2C data value (0 or 1) to set
592 *
593 * Sets the I2C data bit
b980ac18 594 **/
441fc6fd
CW		 595static void igb_set_i2c_data(void *data, int state)
596{
597 struct igb_adapter *adapter = (struct igb_adapter *)data;
598 struct e1000_hw *hw = &adapter->hw;
599 s32 i2cctl = rd32(E1000_I2CPARAMS);
600
601 if (state)
602 i2cctl |= E1000_I2C_DATA_OUT;
603 else
604 i2cctl &= ~E1000_I2C_DATA_OUT;
605
606 i2cctl &= ~E1000_I2C_DATA_OE_N;
607 i2cctl |= E1000_I2C_CLK_OE_N;
608 wr32(E1000_I2CPARAMS, i2cctl);
609 wrfl();
610
611}
612
b980ac18
JK		 613/**
614 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 615 * @data: pointer to hardware structure
616 * @state: state to set clock
617 *
618 * Sets the I2C clock line to state
b980ac18 619 **/
441fc6fd
CW		 620static void igb_set_i2c_clk(void *data, int state)
621{
622 struct igb_adapter *adapter = (struct igb_adapter *)data;
623 struct e1000_hw *hw = &adapter->hw;
624 s32 i2cctl = rd32(E1000_I2CPARAMS);
625
626 if (state) {
627 i2cctl |= E1000_I2C_CLK_OUT;
628 i2cctl &= ~E1000_I2C_CLK_OE_N;
629 } else {
630 i2cctl &= ~E1000_I2C_CLK_OUT;
631 i2cctl &= ~E1000_I2C_CLK_OE_N;
632 }
633 wr32(E1000_I2CPARAMS, i2cctl);
634 wrfl();
635}
636
b980ac18
JK		 637/**
638 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 639 * @data: pointer to hardware structure
640 *
641 * Gets the I2C clock state
b980ac18 642 **/
441fc6fd
CW		 643static int igb_get_i2c_clk(void *data)
644{
645 struct igb_adapter *adapter = (struct igb_adapter *)data;
646 struct e1000_hw *hw = &adapter->hw;
647 s32 i2cctl = rd32(E1000_I2CPARAMS);
648
649 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
650}
651
652static const struct i2c_algo_bit_data igb_i2c_algo = {
653 .setsda = igb_set_i2c_data,
654 .setscl = igb_set_i2c_clk,
655 .getsda = igb_get_i2c_data,
656 .getscl = igb_get_i2c_clk,
657 .udelay = 5,
658 .timeout = 20,
659};
660
9d5c8243 661/**
b980ac18
JK		 662 * igb_get_hw_dev - return device
663 * @hw: pointer to hardware structure
664 *
665 * used by hardware layer to print debugging information
9d5c8243 666 **/
c041076a 667struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 668{
669 struct igb_adapter *adapter = hw->back;
c041076a 670 return adapter->netdev;
9d5c8243 671}
38c845c7 672
9d5c8243 673/**
b980ac18 674 * igb_init_module - Driver Registration Routine
9d5c8243 675 *
b980ac18
JK		 676 * igb_init_module is the first routine called when the driver is
677 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 678 **/
679static int __init igb_init_module(void)
680{
681 int ret;
876d2d6f 682 pr_info("%s - version %s\n",
9d5c8243
AK		 683 igb_driver_string, igb_driver_version);
684
876d2d6f 685 pr_info("%s\n", igb_copyright);
9d5c8243 686
421e02f0 687#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 688 dca_register_notify(&dca_notifier);
689#endif
bbd98fe4 690 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 691 return ret;
692}
693
694module_init(igb_init_module);
695
696/**
b980ac18 697 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 698 *
b980ac18
JK		 699 * igb_exit_module is called just before the driver is removed
700 * from memory.
9d5c8243
AK		 701 **/
702static void __exit igb_exit_module(void)
703{
421e02f0 704#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 705 dca_unregister_notify(&dca_notifier);
706#endif
9d5c8243
AK		 707 pci_unregister_driver(&igb_driver);
708}
709
710module_exit(igb_exit_module);
711
26bc19ec
AD		 712#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
713/**
b980ac18
JK		 714 * igb_cache_ring_register - Descriptor ring to register mapping
715 * @adapter: board private structure to initialize
26bc19ec 716 *
b980ac18
JK		 717 * Once we know the feature-set enabled for the device, we'll cache
718 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 719 **/
720static void igb_cache_ring_register(struct igb_adapter *adapter)
721{
ee1b9f06 722 int i = 0, j = 0;
047e0030 723 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 724
725 switch (adapter->hw.mac.type) {
726 case e1000_82576:
727 /* The queues are allocated for virtualization such that VF 0
728 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
729 * In order to avoid collision we start at the first free queue
730 * and continue consuming queues in the same sequence
731 */
ee1b9f06 732 if (adapter->vfs_allocated_count) {
a99955fc 733 for (; i < adapter->rss_queues; i++)
3025a446 734 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 735 Q_IDX_82576(i);
ee1b9f06 736 }
26bc19ec 737 case e1000_82575:
55cac248 738 case e1000_82580:
d2ba2ed8 739 case e1000_i350:
ceb5f13b 740 case e1000_i354:
f96a8a0b
CW		 741 case e1000_i210:
742 case e1000_i211:
26bc19ec 743 default:
ee1b9f06 744 for (; i < adapter->num_rx_queues; i++)
3025a446 745 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 746 for (; j < adapter->num_tx_queues; j++)
3025a446 747 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 748 break;
749 }
750}
751
4be000c8
AD		 752/**
753 * igb_write_ivar - configure ivar for given MSI-X vector
754 * @hw: pointer to the HW structure
755 * @msix_vector: vector number we are allocating to a given ring
756 * @index: row index of IVAR register to write within IVAR table
757 * @offset: column offset of in IVAR, should be multiple of 8
758 *
759 * This function is intended to handle the writing of the IVAR register
760 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
761 * each containing an cause allocation for an Rx and Tx ring, and a
762 * variable number of rows depending on the number of queues supported.
763 **/
764static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
765 int index, int offset)
766{
767 u32 ivar = array_rd32(E1000_IVAR0, index);
768
769 /* clear any bits that are currently set */
770 ivar &= ~((u32)0xFF << offset);
771
772 /* write vector and valid bit */
773 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
774
775 array_wr32(E1000_IVAR0, index, ivar);
776}
777
9d5c8243 778#define IGB_N0_QUEUE -1
047e0030 779static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 780{
047e0030 781 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 782 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 783 int rx_queue = IGB_N0_QUEUE;
784 int tx_queue = IGB_N0_QUEUE;
4be000c8 785 u32 msixbm = 0;
047e0030 786
0ba82994
AD		 787 if (q_vector->rx.ring)
788 rx_queue = q_vector->rx.ring->reg_idx;
789 if (q_vector->tx.ring)
790 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 791
792 switch (hw->mac.type) {
793 case e1000_82575:
9d5c8243 794 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 795 * bitmask for the EICR/EIMS/EIMC registers. To assign one
796 * or more queues to a vector, we write the appropriate bits
797 * into the MSIXBM register for that vector.
798 */
047e0030 799 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 800 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 801 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 802 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 803 if (!adapter->msix_entries && msix_vector == 0)
804 msixbm |= E1000_EIMS_OTHER;
9d5c8243 805 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 806 q_vector->eims_value = msixbm;
2d064c06
AD		 807 break;
808 case e1000_82576:
b980ac18 809 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 810 * with 8 rows. The ordering is column-major so we use the
811 * lower 3 bits as the row index, and the 4th bit as the
812 * column offset.
813 */
814 if (rx_queue > IGB_N0_QUEUE)
815 igb_write_ivar(hw, msix_vector,
816 rx_queue & 0x7,
817 (rx_queue & 0x8) << 1);
818 if (tx_queue > IGB_N0_QUEUE)
819 igb_write_ivar(hw, msix_vector,
820 tx_queue & 0x7,
821 ((tx_queue & 0x8) << 1) + 8);
047e0030 822 q_vector->eims_value = 1 << msix_vector;
2d064c06 823 break;
55cac248 824 case e1000_82580:
d2ba2ed8 825 case e1000_i350:
ceb5f13b 826 case e1000_i354:
f96a8a0b
CW		 827 case e1000_i210:
828 case e1000_i211:
b980ac18 829 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 830 * however instead of ordering column-major we have things
831 * ordered row-major. So we traverse the table by using
832 * bit 0 as the column offset, and the remaining bits as the
833 * row index.
834 */
835 if (rx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 rx_queue >> 1,
838 (rx_queue & 0x1) << 4);
839 if (tx_queue > IGB_N0_QUEUE)
840 igb_write_ivar(hw, msix_vector,
841 tx_queue >> 1,
842 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 843 q_vector->eims_value = 1 << msix_vector;
844 break;
2d064c06
AD		 845 default:
846 BUG();
847 break;
848 }
26b39276
AD		 849
850 /* add q_vector eims value to global eims_enable_mask */
851 adapter->eims_enable_mask |= q_vector->eims_value;
852
853 /* configure q_vector to set itr on first interrupt */
854 q_vector->set_itr = 1;
9d5c8243
AK		 855}
856
857/**
b980ac18
JK		 858 * igb_configure_msix - Configure MSI-X hardware
859 * @adapter: board private structure to initialize
9d5c8243 860 *
b980ac18
JK		 861 * igb_configure_msix sets up the hardware to properly
862 * generate MSI-X interrupts.
9d5c8243
AK		 863 **/
864static void igb_configure_msix(struct igb_adapter *adapter)
865{
866 u32 tmp;
867 int i, vector = 0;
868 struct e1000_hw *hw = &adapter->hw;
869
870 adapter->eims_enable_mask = 0;
9d5c8243
AK		 871
872 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 873 switch (hw->mac.type) {
874 case e1000_82575:
9d5c8243
AK		 875 tmp = rd32(E1000_CTRL_EXT);
876 /* enable MSI-X PBA support*/
877 tmp |= E1000_CTRL_EXT_PBA_CLR;
878
879 /* Auto-Mask interrupts upon ICR read. */
880 tmp |= E1000_CTRL_EXT_EIAME;
881 tmp |= E1000_CTRL_EXT_IRCA;
882
883 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 884
885 /* enable msix_other interrupt */
b980ac18 886 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 887 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 888
2d064c06
AD		 889 break;
890
891 case e1000_82576:
55cac248 892 case e1000_82580:
d2ba2ed8 893 case e1000_i350:
ceb5f13b 894 case e1000_i354:
f96a8a0b
CW		 895 case e1000_i210:
896 case e1000_i211:
047e0030 897 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 898 * won't stick. And it will take days to debug.
899 */
047e0030 900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 901 E1000_GPIE_PBA | E1000_GPIE_EIAME |
902 E1000_GPIE_NSICR);
047e0030
AD		 903
904 /* enable msix_other interrupt */
905 adapter->eims_other = 1 << vector;
2d064c06 906 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 907
047e0030 908 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 909 break;
910 default:
911 /* do nothing, since nothing else supports MSI-X */
912 break;
913 } /* switch (hw->mac.type) */
047e0030
AD		 914
915 adapter->eims_enable_mask |= adapter->eims_other;
916
26b39276
AD		 917 for (i = 0; i < adapter->num_q_vectors; i++)
918 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 919
9d5c8243
AK		 920 wrfl();
921}
922
923/**
b980ac18
JK		 924 * igb_request_msix - Initialize MSI-X interrupts
925 * @adapter: board private structure to initialize
9d5c8243 926 *
b980ac18
JK		 927 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
928 * kernel.
9d5c8243
AK		 929 **/
930static int igb_request_msix(struct igb_adapter *adapter)
931{
932 struct net_device *netdev = adapter->netdev;
047e0030 933 struct e1000_hw *hw = &adapter->hw;
52285b76 934 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 935
047e0030 936 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 937 igb_msix_other, 0, netdev->name, adapter);
047e0030 938 if (err)
52285b76 939 goto err_out;
047e0030
AD		 940
941 for (i = 0; i < adapter->num_q_vectors; i++) {
942 struct igb_q_vector *q_vector = adapter->q_vector[i];
943
52285b76
SA		 944 vector++;
945
047e0030
AD		 946 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
947
0ba82994 948 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 949 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 950 q_vector->rx.ring->queue_index);
951 else if (q_vector->tx.ring)
047e0030 952 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 953 q_vector->tx.ring->queue_index);
954 else if (q_vector->rx.ring)
047e0030 955 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 956 q_vector->rx.ring->queue_index);
9d5c8243 957 else
047e0030
AD		 958 sprintf(q_vector->name, "%s-unused", netdev->name);
959
9d5c8243 960 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 961 igb_msix_ring, 0, q_vector->name,
962 q_vector);
9d5c8243 963 if (err)
52285b76 964 goto err_free;
9d5c8243
AK		 965 }
966
9d5c8243
AK		 967 igb_configure_msix(adapter);
968 return 0;
52285b76
SA		 969
970err_free:
971 /* free already assigned IRQs */
972 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
973
974 vector--;
975 for (i = 0; i < vector; i++) {
976 free_irq(adapter->msix_entries[free_vector++].vector,
977 adapter->q_vector[i]);
978 }
979err_out:
9d5c8243
AK		 980 return err;
981}
982
983static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
984{
985 if (adapter->msix_entries) {
986 pci_disable_msix(adapter->pdev);
987 kfree(adapter->msix_entries);
988 adapter->msix_entries = NULL;
047e0030 989 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 990 pci_disable_msi(adapter->pdev);
047e0030 991 }
9d5c8243
AK		 992}
993
5536d210 994/**
b980ac18
JK		 995 * igb_free_q_vector - Free memory allocated for specific interrupt vector
996 * @adapter: board private structure to initialize
997 * @v_idx: Index of vector to be freed
5536d210 998 *
b980ac18
JK		 999 * This function frees the memory allocated to the q_vector. In addition if
1000 * NAPI is enabled it will delete any references to the NAPI struct prior
1001 * to freeing the q_vector.
5536d210
AD		 1002 **/
1003static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1004{
1005 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1006
1007 if (q_vector->tx.ring)
1008 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1009
1010 if (q_vector->rx.ring)
1011 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1012
1013 adapter->q_vector[v_idx] = NULL;
1014 netif_napi_del(&q_vector->napi);
1015
7f90128e 1016 /* igb_get_stats64() might access the rings on this vector,
5536d210
AD		 1017 * we must wait a grace period before freeing it.
1018 */
1019 kfree_rcu(q_vector, rcu);
1020}
1021
047e0030 1022/**
b980ac18
JK		 1023 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1024 * @adapter: board private structure to initialize
047e0030 1025 *
b980ac18
JK		 1026 * This function frees the memory allocated to the q_vectors. In addition if
1027 * NAPI is enabled it will delete any references to the NAPI struct prior
1028 * to freeing the q_vector.
047e0030
AD		 1029 **/
1030static void igb_free_q_vectors(struct igb_adapter *adapter)
1031{
5536d210
AD		 1032 int v_idx = adapter->num_q_vectors;
1033
1034 adapter->num_tx_queues = 0;
1035 adapter->num_rx_queues = 0;
047e0030 1036 adapter->num_q_vectors = 0;
5536d210
AD		 1037
1038 while (v_idx--)
1039 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1040}
1041
1042/**
b980ac18
JK		 1043 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1044 * @adapter: board private structure to initialize
047e0030 1045 *
b980ac18
JK		 1046 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1047 * MSI-X interrupts allocated.
047e0030
AD		 1048 */
1049static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1050{
047e0030
AD		 1051 igb_free_q_vectors(adapter);
1052 igb_reset_interrupt_capability(adapter);
1053}
9d5c8243
AK		 1054
1055/**
b980ac18
JK		 1056 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1057 * @adapter: board private structure to initialize
1058 * @msix: boolean value of MSIX capability
9d5c8243 1059 *
b980ac18
JK		 1060 * Attempt to configure interrupts using the best available
1061 * capabilities of the hardware and kernel.
9d5c8243 1062 **/
53c7d064 1063static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1064{
1065 int err;
1066 int numvecs, i;
1067
53c7d064
SA		 1068 if (!msix)
1069 goto msi_only;
1070
83b7180d 1071 /* Number of supported queues. */
a99955fc 1072 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1073 if (adapter->vfs_allocated_count)
1074 adapter->num_tx_queues = 1;
1075 else
1076 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1077
b980ac18 1078 /* start with one vector for every Rx queue */
047e0030
AD		 1079 numvecs = adapter->num_rx_queues;
1080
b980ac18 1081 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1082 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1083 numvecs += adapter->num_tx_queues;
047e0030
AD		 1084
1085 /* store the number of vectors reserved for queues */
1086 adapter->num_q_vectors = numvecs;
1087
1088 /* add 1 vector for link status interrupts */
1089 numvecs++;
9d5c8243
AK		 1090 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1091 GFP_KERNEL);
f96a8a0b 1092
9d5c8243
AK		 1093 if (!adapter->msix_entries)
1094 goto msi_only;
1095
1096 for (i = 0; i < numvecs; i++)
1097 adapter->msix_entries[i].entry = i;
1098
1099 err = pci_enable_msix(adapter->pdev,
1100 adapter->msix_entries,
1101 numvecs);
1102 if (err == 0)
0c2cc02e 1103 return;
9d5c8243
AK		 1104
1105 igb_reset_interrupt_capability(adapter);
1106
1107 /* If we can't do MSI-X, try MSI */
1108msi_only:
2a3abf6d
AD		 1109#ifdef CONFIG_PCI_IOV
1110 /* disable SR-IOV for non MSI-X configurations */
1111 if (adapter->vf_data) {
1112 struct e1000_hw *hw = &adapter->hw;
1113 /* disable iov and allow time for transactions to clear */
1114 pci_disable_sriov(adapter->pdev);
1115 msleep(500);
1116
1117 kfree(adapter->vf_data);
1118 adapter->vf_data = NULL;
1119 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1120 wrfl();
2a3abf6d
AD		 1121 msleep(100);
1122 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1123 }
1124#endif
4fc82adf 1125 adapter->vfs_allocated_count = 0;
a99955fc 1126 adapter->rss_queues = 1;
4fc82adf 1127 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1128 adapter->num_rx_queues = 1;
661086df 1129 adapter->num_tx_queues = 1;
047e0030 1130 adapter->num_q_vectors = 1;
9d5c8243 1131 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1132 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1133}
1134
5536d210
AD		 1135static void igb_add_ring(struct igb_ring *ring,
1136 struct igb_ring_container *head)
1137{
1138 head->ring = ring;
1139 head->count++;
1140}
1141
047e0030 1142/**
b980ac18
JK		 1143 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1144 * @adapter: board private structure to initialize
1145 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1146 * @v_idx: index of vector in adapter struct
1147 * @txr_count: total number of Tx rings to allocate
1148 * @txr_idx: index of first Tx ring to allocate
1149 * @rxr_count: total number of Rx rings to allocate
1150 * @rxr_idx: index of first Rx ring to allocate
047e0030 1151 *
b980ac18 1152 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1153 **/
5536d210
AD		 1154static int igb_alloc_q_vector(struct igb_adapter *adapter,
1155 int v_count, int v_idx,
1156 int txr_count, int txr_idx,
1157 int rxr_count, int rxr_idx)
047e0030
AD		 1158{
1159 struct igb_q_vector *q_vector;
5536d210
AD		 1160 struct igb_ring *ring;
1161 int ring_count, size;
047e0030 1162
5536d210
AD		 1163 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1164 if (txr_count > 1 || rxr_count > 1)
1165 return -ENOMEM;
1166
1167 ring_count = txr_count + rxr_count;
1168 size = sizeof(struct igb_q_vector) +
1169 (sizeof(struct igb_ring) * ring_count);
1170
1171 /* allocate q_vector and rings */
1172 q_vector = kzalloc(size, GFP_KERNEL);
1173 if (!q_vector)
1174 return -ENOMEM;
1175
1176 /* initialize NAPI */
1177 netif_napi_add(adapter->netdev, &q_vector->napi,
1178 igb_poll, 64);
1179
1180 /* tie q_vector and adapter together */
1181 adapter->q_vector[v_idx] = q_vector;
1182 q_vector->adapter = adapter;
1183
1184 /* initialize work limits */
1185 q_vector->tx.work_limit = adapter->tx_work_limit;
1186
1187 /* initialize ITR configuration */
1188 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1189 q_vector->itr_val = IGB_START_ITR;
1190
1191 /* initialize pointer to rings */
1192 ring = q_vector->ring;
1193
4e227667
AD		 1194 /* intialize ITR */
1195 if (rxr_count) {
1196 /* rx or rx/tx vector */
1197 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1198 q_vector->itr_val = adapter->rx_itr_setting;
1199 } else {
1200 /* tx only vector */
1201 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1202 q_vector->itr_val = adapter->tx_itr_setting;
1203 }
1204
5536d210
AD		 1205 if (txr_count) {
1206 /* assign generic ring traits */
1207 ring->dev = &adapter->pdev->dev;
1208 ring->netdev = adapter->netdev;
1209
1210 /* configure backlink on ring */
1211 ring->q_vector = q_vector;
1212
1213 /* update q_vector Tx values */
1214 igb_add_ring(ring, &q_vector->tx);
1215
1216 /* For 82575, context index must be unique per ring. */
1217 if (adapter->hw.mac.type == e1000_82575)
1218 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1219
1220 /* apply Tx specific ring traits */
1221 ring->count = adapter->tx_ring_count;
1222 ring->queue_index = txr_idx;
1223
1224 /* assign ring to adapter */
1225 adapter->tx_ring[txr_idx] = ring;
1226
1227 /* push pointer to next ring */
1228 ring++;
047e0030 1229 }
81c2fc22 1230
5536d210
AD		 1231 if (rxr_count) {
1232 /* assign generic ring traits */
1233 ring->dev = &adapter->pdev->dev;
1234 ring->netdev = adapter->netdev;
047e0030 1235
5536d210
AD		 1236 /* configure backlink on ring */
1237 ring->q_vector = q_vector;
047e0030 1238
5536d210
AD		 1239 /* update q_vector Rx values */
1240 igb_add_ring(ring, &q_vector->rx);
047e0030 1241
5536d210
AD		 1242 /* set flag indicating ring supports SCTP checksum offload */
1243 if (adapter->hw.mac.type >= e1000_82576)
1244 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1245
ceb5f13b
CW		 1246 /*
1247 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1248 * have the tag byte-swapped.
b980ac18 1249 */
5536d210
AD		 1250 if (adapter->hw.mac.type >= e1000_i350)
1251 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1252
5536d210
AD		 1253 /* apply Rx specific ring traits */
1254 ring->count = adapter->rx_ring_count;
1255 ring->queue_index = rxr_idx;
1256
1257 /* assign ring to adapter */
1258 adapter->rx_ring[rxr_idx] = ring;
1259 }
1260
1261 return 0;
047e0030
AD		 1262}
1263
5536d210 1264
047e0030 1265/**
b980ac18
JK		 1266 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1267 * @adapter: board private structure to initialize
047e0030 1268 *
b980ac18
JK		 1269 * We allocate one q_vector per queue interrupt. If allocation fails we
1270 * return -ENOMEM.
047e0030 1271 **/
5536d210 1272static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1273{
5536d210
AD		 1274 int q_vectors = adapter->num_q_vectors;
1275 int rxr_remaining = adapter->num_rx_queues;
1276 int txr_remaining = adapter->num_tx_queues;
1277 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1278 int err;
047e0030 1279
5536d210
AD		 1280 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1281 for (; rxr_remaining; v_idx++) {
1282 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1283 0, 0, 1, rxr_idx);
047e0030 1284
5536d210
AD		 1285 if (err)
1286 goto err_out;
1287
1288 /* update counts and index */
1289 rxr_remaining--;
1290 rxr_idx++;
047e0030 1291 }
047e0030 1292 }
5536d210
AD		 1293
1294 for (; v_idx < q_vectors; v_idx++) {
1295 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1296 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1297 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1298 tqpv, txr_idx, rqpv, rxr_idx);
1299
1300 if (err)
1301 goto err_out;
1302
1303 /* update counts and index */
1304 rxr_remaining -= rqpv;
1305 txr_remaining -= tqpv;
1306 rxr_idx++;
1307 txr_idx++;
1308 }
1309
047e0030 1310 return 0;
5536d210
AD		 1311
1312err_out:
1313 adapter->num_tx_queues = 0;
1314 adapter->num_rx_queues = 0;
1315 adapter->num_q_vectors = 0;
1316
1317 while (v_idx--)
1318 igb_free_q_vector(adapter, v_idx);
1319
1320 return -ENOMEM;
047e0030
AD		 1321}
1322
1323/**
b980ac18
JK		 1324 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1325 * @adapter: board private structure to initialize
1326 * @msix: boolean value of MSIX capability
047e0030 1327 *
b980ac18 1328 * This function initializes the interrupts and allocates all of the queues.
047e0030 1329 **/
53c7d064 1330static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1331{
1332 struct pci_dev *pdev = adapter->pdev;
1333 int err;
1334
53c7d064 1335 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1336
1337 err = igb_alloc_q_vectors(adapter);
1338 if (err) {
1339 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1340 goto err_alloc_q_vectors;
1341 }
1342
5536d210 1343 igb_cache_ring_register(adapter);
047e0030
AD		 1344
1345 return 0;
5536d210 1346
047e0030
AD		 1347err_alloc_q_vectors:
1348 igb_reset_interrupt_capability(adapter);
1349 return err;
1350}
1351
9d5c8243 1352/**
b980ac18
JK		 1353 * igb_request_irq - initialize interrupts
1354 * @adapter: board private structure to initialize
9d5c8243 1355 *
b980ac18
JK		 1356 * Attempts to configure interrupts using the best available
1357 * capabilities of the hardware and kernel.
9d5c8243
AK		 1358 **/
1359static int igb_request_irq(struct igb_adapter *adapter)
1360{
1361 struct net_device *netdev = adapter->netdev;
047e0030 1362 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1363 int err = 0;
1364
1365 if (adapter->msix_entries) {
1366 err = igb_request_msix(adapter);
844290e5 1367 if (!err)
9d5c8243 1368 goto request_done;
9d5c8243 1369 /* fall back to MSI */
5536d210
AD		 1370 igb_free_all_tx_resources(adapter);
1371 igb_free_all_rx_resources(adapter);
53c7d064 1372
047e0030 1373 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1374 err = igb_init_interrupt_scheme(adapter, false);
1375 if (err)
047e0030 1376 goto request_done;
53c7d064 1377
047e0030
AD		 1378 igb_setup_all_tx_resources(adapter);
1379 igb_setup_all_rx_resources(adapter);
53c7d064 1380 igb_configure(adapter);
9d5c8243 1381 }
844290e5 1382
c74d588e
AD		 1383 igb_assign_vector(adapter->q_vector[0], 0);
1384
7dfc16fa 1385 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1386 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1387 netdev->name, adapter);
9d5c8243
AK		 1388 if (!err)
1389 goto request_done;
047e0030 1390
9d5c8243
AK		 1391 /* fall back to legacy interrupts */
1392 igb_reset_interrupt_capability(adapter);
7dfc16fa 1393 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1394 }
1395
c74d588e 1396 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1397 netdev->name, adapter);
9d5c8243 1398
6cb5e577 1399 if (err)
c74d588e 1400 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1401 err);
9d5c8243
AK		 1402
1403request_done:
1404 return err;
1405}
1406
1407static void igb_free_irq(struct igb_adapter *adapter)
1408{
9d5c8243
AK		 1409 if (adapter->msix_entries) {
1410 int vector = 0, i;
1411
047e0030 1412 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1413
0d1ae7f4 1414 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1415 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1416 adapter->q_vector[i]);
047e0030
AD		 1417 } else {
1418 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1419 }
9d5c8243
AK		 1420}
1421
1422/**
b980ac18
JK		 1423 * igb_irq_disable - Mask off interrupt generation on the NIC
1424 * @adapter: board private structure
9d5c8243
AK		 1425 **/
1426static void igb_irq_disable(struct igb_adapter *adapter)
1427{
1428 struct e1000_hw *hw = &adapter->hw;
1429
b980ac18 1430 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1431 * mapped into these registers and so clearing the bits can cause
1432 * issues on the VF drivers so we only need to clear what we set
1433 */
9d5c8243 1434 if (adapter->msix_entries) {
2dfd1212
AD		 1435 u32 regval = rd32(E1000_EIAM);
1436 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1437 wr32(E1000_EIMC, adapter->eims_enable_mask);
1438 regval = rd32(E1000_EIAC);
1439 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1440 }
844290e5
PW		 1441
1442 wr32(E1000_IAM, 0);
9d5c8243
AK		 1443 wr32(E1000_IMC, ~0);
1444 wrfl();
81a61859
ET		 1445 if (adapter->msix_entries) {
1446 int i;
1447 for (i = 0; i < adapter->num_q_vectors; i++)
1448 synchronize_irq(adapter->msix_entries[i].vector);
1449 } else {
1450 synchronize_irq(adapter->pdev->irq);
1451 }
9d5c8243
AK		 1452}
1453
1454/**
b980ac18
JK		 1455 * igb_irq_enable - Enable default interrupt generation settings
1456 * @adapter: board private structure
9d5c8243
AK		 1457 **/
1458static void igb_irq_enable(struct igb_adapter *adapter)
1459{
1460 struct e1000_hw *hw = &adapter->hw;
1461
1462 if (adapter->msix_entries) {
06218a8d 1463 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1464 u32 regval = rd32(E1000_EIAC);
1465 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1466 regval = rd32(E1000_EIAM);
1467 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1468 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1469 if (adapter->vfs_allocated_count) {
4ae196df 1470 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1471 ims |= E1000_IMS_VMMB;
1472 }
1473 wr32(E1000_IMS, ims);
844290e5 1474 } else {
55cac248
AD		 1475 wr32(E1000_IMS, IMS_ENABLE_MASK |
1476 E1000_IMS_DRSTA);
1477 wr32(E1000_IAM, IMS_ENABLE_MASK |
1478 E1000_IMS_DRSTA);
844290e5 1479 }
9d5c8243
AK		 1480}
1481
1482static void igb_update_mng_vlan(struct igb_adapter *adapter)
1483{
51466239 1484 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1485 u16 vid = adapter->hw.mng_cookie.vlan_id;
1486 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1487
1488 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1489 /* add VID to filter table */
1490 igb_vfta_set(hw, vid, true);
1491 adapter->mng_vlan_id = vid;
1492 } else {
1493 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1494 }
1495
1496 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1497 (vid != old_vid) &&
b2cb09b1 1498 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1499 /* remove VID from filter table */
1500 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1501 }
1502}
1503
1504/**
b980ac18
JK		 1505 * igb_release_hw_control - release control of the h/w to f/w
1506 * @adapter: address of board private structure
9d5c8243 1507 *
b980ac18
JK		 1508 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1509 * For ASF and Pass Through versions of f/w this means that the
1510 * driver is no longer loaded.
9d5c8243
AK		 1511 **/
1512static void igb_release_hw_control(struct igb_adapter *adapter)
1513{
1514 struct e1000_hw *hw = &adapter->hw;
1515 u32 ctrl_ext;
1516
1517 /* Let firmware take over control of h/w */
1518 ctrl_ext = rd32(E1000_CTRL_EXT);
1519 wr32(E1000_CTRL_EXT,
1520 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1521}
1522
9d5c8243 1523/**
b980ac18
JK		 1524 * igb_get_hw_control - get control of the h/w from f/w
1525 * @adapter: address of board private structure
9d5c8243 1526 *
b980ac18
JK		 1527 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1528 * For ASF and Pass Through versions of f/w this means that
1529 * the driver is loaded.
9d5c8243
AK		 1530 **/
1531static void igb_get_hw_control(struct igb_adapter *adapter)
1532{
1533 struct e1000_hw *hw = &adapter->hw;
1534 u32 ctrl_ext;
1535
1536 /* Let firmware know the driver has taken over */
1537 ctrl_ext = rd32(E1000_CTRL_EXT);
1538 wr32(E1000_CTRL_EXT,
1539 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1540}
1541
9d5c8243 1542/**
b980ac18
JK		 1543 * igb_configure - configure the hardware for RX and TX
1544 * @adapter: private board structure
9d5c8243
AK		 1545 **/
1546static void igb_configure(struct igb_adapter *adapter)
1547{
1548 struct net_device *netdev = adapter->netdev;
1549 int i;
1550
1551 igb_get_hw_control(adapter);
ff41f8dc 1552 igb_set_rx_mode(netdev);
9d5c8243
AK		 1553
1554 igb_restore_vlan(adapter);
9d5c8243 1555
85b430b4 1556 igb_setup_tctl(adapter);
06cf2666 1557 igb_setup_mrqc(adapter);
9d5c8243 1558 igb_setup_rctl(adapter);
85b430b4
AD		 1559
1560 igb_configure_tx(adapter);
9d5c8243 1561 igb_configure_rx(adapter);
662d7205
AD		 1562
1563 igb_rx_fifo_flush_82575(&adapter->hw);
1564
c493ea45 1565 /* call igb_desc_unused which always leaves
9d5c8243 1566 * at least 1 descriptor unused to make sure
b980ac18
JK		 1567 * next_to_use != next_to_clean
1568 */
9d5c8243 1569 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1570 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1571 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1572 }
9d5c8243
AK		 1573}
1574
88a268c1 1575/**
b980ac18
JK		 1576 * igb_power_up_link - Power up the phy/serdes link
1577 * @adapter: address of board private structure
88a268c1
NN		 1578 **/
1579void igb_power_up_link(struct igb_adapter *adapter)
1580{
76886596
AA		 1581 igb_reset_phy(&adapter->hw);
1582
88a268c1
NN		 1583 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1584 igb_power_up_phy_copper(&adapter->hw);
1585 else
1586 igb_power_up_serdes_link_82575(&adapter->hw);
1587}
1588
1589/**
b980ac18
JK		 1590 * igb_power_down_link - Power down the phy/serdes link
1591 * @adapter: address of board private structure
88a268c1
NN		 1592 */
1593static void igb_power_down_link(struct igb_adapter *adapter)
1594{
1595 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1596 igb_power_down_phy_copper_82575(&adapter->hw);
1597 else
1598 igb_shutdown_serdes_link_82575(&adapter->hw);
1599}
9d5c8243
AK		 1600
1601/**
b980ac18
JK		 1602 * igb_up - Open the interface and prepare it to handle traffic
1603 * @adapter: board private structure
9d5c8243 1604 **/
9d5c8243
AK		 1605int igb_up(struct igb_adapter *adapter)
1606{
1607 struct e1000_hw *hw = &adapter->hw;
1608 int i;
1609
1610 /* hardware has been reset, we need to reload some things */
1611 igb_configure(adapter);
1612
1613 clear_bit(__IGB_DOWN, &adapter->state);
1614
0d1ae7f4
AD		 1615 for (i = 0; i < adapter->num_q_vectors; i++)
1616 napi_enable(&(adapter->q_vector[i]->napi));
1617
844290e5 1618 if (adapter->msix_entries)
9d5c8243 1619 igb_configure_msix(adapter);
feeb2721
AD		 1620 else
1621 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1622
1623 /* Clear any pending interrupts. */
1624 rd32(E1000_ICR);
1625 igb_irq_enable(adapter);
1626
d4960307
AD		 1627 /* notify VFs that reset has been completed */
1628 if (adapter->vfs_allocated_count) {
1629 u32 reg_data = rd32(E1000_CTRL_EXT);
1630 reg_data |= E1000_CTRL_EXT_PFRSTD;
1631 wr32(E1000_CTRL_EXT, reg_data);
1632 }
1633
4cb9be7a
JB		 1634 netif_tx_start_all_queues(adapter->netdev);
1635
25568a53
AD		 1636 /* start the watchdog. */
1637 hw->mac.get_link_status = 1;
1638 schedule_work(&adapter->watchdog_task);
1639
9d5c8243
AK		 1640 return 0;
1641}
1642
1643void igb_down(struct igb_adapter *adapter)
1644{
9d5c8243 1645 struct net_device *netdev = adapter->netdev;
330a6d6a 1646 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1647 u32 tctl, rctl;
1648 int i;
1649
1650 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1651 * reschedule our watchdog timer
1652 */
9d5c8243
AK		 1653 set_bit(__IGB_DOWN, &adapter->state);
1654
1655 /* disable receives in the hardware */
1656 rctl = rd32(E1000_RCTL);
1657 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1658 /* flush and sleep below */
1659
fd2ea0a7 1660 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1661
1662 /* disable transmits in the hardware */
1663 tctl = rd32(E1000_TCTL);
1664 tctl &= ~E1000_TCTL_EN;
1665 wr32(E1000_TCTL, tctl);
1666 /* flush both disables and wait for them to finish */
1667 wrfl();
1668 msleep(10);
1669
41f149a2
CW		 1670 igb_irq_disable(adapter);
1671
1672 for (i = 0; i < adapter->num_q_vectors; i++) {
1673 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1674 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1675 }
9d5c8243 1676
9d5c8243
AK		 1677
1678 del_timer_sync(&adapter->watchdog_timer);
1679 del_timer_sync(&adapter->phy_info_timer);
1680
9d5c8243 1681 netif_carrier_off(netdev);
04fe6358
AD		 1682
1683 /* record the stats before reset*/
12dcd86b
ED		 1684 spin_lock(&adapter->stats64_lock);
1685 igb_update_stats(adapter, &adapter->stats64);
1686 spin_unlock(&adapter->stats64_lock);
04fe6358 1687
9d5c8243
AK		 1688 adapter->link_speed = 0;
1689 adapter->link_duplex = 0;
1690
3023682e
JK		 1691 if (!pci_channel_offline(adapter->pdev))
1692 igb_reset(adapter);
9d5c8243
AK		 1693 igb_clean_all_tx_rings(adapter);
1694 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1695#ifdef CONFIG_IGB_DCA
1696
1697 /* since we reset the hardware DCA settings were cleared */
1698 igb_setup_dca(adapter);
1699#endif
9d5c8243
AK		 1700}
1701
1702void igb_reinit_locked(struct igb_adapter *adapter)
1703{
1704 WARN_ON(in_interrupt());
1705 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1706 msleep(1);
1707 igb_down(adapter);
1708 igb_up(adapter);
1709 clear_bit(__IGB_RESETTING, &adapter->state);
1710}
1711
1712void igb_reset(struct igb_adapter *adapter)
1713{
090b1795 1714 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1715 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1716 struct e1000_mac_info *mac = &hw->mac;
1717 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1718 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1719
1720 /* Repartition Pba for greater than 9k mtu
1721 * To take effect CTRL.RST is required.
1722 */
fa4dfae0 1723 switch (mac->type) {
d2ba2ed8 1724 case e1000_i350:
ceb5f13b 1725 case e1000_i354:
55cac248
AD		 1726 case e1000_82580:
1727 pba = rd32(E1000_RXPBS);
1728 pba = igb_rxpbs_adjust_82580(pba);
1729 break;
fa4dfae0 1730 case e1000_82576:
d249be54
AD		 1731 pba = rd32(E1000_RXPBS);
1732 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1733 break;
1734 case e1000_82575:
f96a8a0b
CW		 1735 case e1000_i210:
1736 case e1000_i211:
fa4dfae0
AD		 1737 default:
1738 pba = E1000_PBA_34K;
1739 break;
2d064c06 1740 }
9d5c8243 1741
2d064c06
AD		 1742 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1743 (mac->type < e1000_82576)) {
9d5c8243
AK		 1744 /* adjust PBA for jumbo frames */
1745 wr32(E1000_PBA, pba);
1746
1747 /* To maintain wire speed transmits, the Tx FIFO should be
1748 * large enough to accommodate two full transmit packets,
1749 * rounded up to the next 1KB and expressed in KB. Likewise,
1750 * the Rx FIFO should be large enough to accommodate at least
1751 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1752 * expressed in KB.
1753 */
9d5c8243
AK		 1754 pba = rd32(E1000_PBA);
1755 /* upper 16 bits has Tx packet buffer allocation size in KB */
1756 tx_space = pba >> 16;
1757 /* lower 16 bits has Rx packet buffer allocation size in KB */
1758 pba &= 0xffff;
b980ac18
JK		 1759 /* the Tx fifo also stores 16 bytes of information about the Tx
1760 * but don't include ethernet FCS because hardware appends it
1761 */
9d5c8243 1762 min_tx_space = (adapter->max_frame_size +
85e8d004 1763 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1764 ETH_FCS_LEN) * 2;
1765 min_tx_space = ALIGN(min_tx_space, 1024);
1766 min_tx_space >>= 10;
1767 /* software strips receive CRC, so leave room for it */
1768 min_rx_space = adapter->max_frame_size;
1769 min_rx_space = ALIGN(min_rx_space, 1024);
1770 min_rx_space >>= 10;
1771
1772 /* If current Tx allocation is less than the min Tx FIFO size,
1773 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1774 * allocation, take space away from current Rx allocation
1775 */
9d5c8243
AK		 1776 if (tx_space < min_tx_space &&
1777 ((min_tx_space - tx_space) < pba)) {
1778 pba = pba - (min_tx_space - tx_space);
1779
b980ac18
JK		 1780 /* if short on Rx space, Rx wins and must trump Tx
1781 * adjustment
1782 */
9d5c8243
AK		 1783 if (pba < min_rx_space)
1784 pba = min_rx_space;
1785 }
2d064c06 1786 wr32(E1000_PBA, pba);
9d5c8243 1787 }
9d5c8243
AK		 1788
1789 /* flow control settings */
1790 /* The high water mark must be low enough to fit one full frame
1791 * (or the size used for early receive) above it in the Rx FIFO.
1792 * Set it to the lower of:
1793 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1794 * - the full Rx FIFO size minus one full frame
1795 */
9d5c8243 1796 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1797 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1798
d48507fe 1799 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1800 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1801 fc->pause_time = 0xFFFF;
1802 fc->send_xon = 1;
0cce119a 1803 fc->current_mode = fc->requested_mode;
9d5c8243 1804
4ae196df
AD		 1805 /* disable receive for all VFs and wait one second */
1806 if (adapter->vfs_allocated_count) {
1807 int i;
1808 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1809 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1810
1811 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1812 igb_ping_all_vfs(adapter);
4ae196df
AD		 1813
1814 /* disable transmits and receives */
1815 wr32(E1000_VFRE, 0);
1816 wr32(E1000_VFTE, 0);
1817 }
1818
9d5c8243 1819 /* Allow time for pending master requests to run */
330a6d6a 1820 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1821 wr32(E1000_WUC, 0);
1822
330a6d6a 1823 if (hw->mac.ops.init_hw(hw))
090b1795 1824 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1825
b980ac18 1826 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1827 * control is off when forcing speed.
1828 */
1829 if (!hw->mac.autoneg)
1830 igb_force_mac_fc(hw);
1831
b6e0c419 1832 igb_init_dmac(adapter, pba);
e428893b
CW		 1833#ifdef CONFIG_IGB_HWMON
1834 /* Re-initialize the thermal sensor on i350 devices. */
1835 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1836 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1837 /* If present, re-initialize the external thermal sensor
1838 * interface.
1839 */
1840 if (adapter->ets)
1841 mac->ops.init_thermal_sensor_thresh(hw);
1842 }
1843 }
1844#endif
88a268c1
NN		 1845 if (!netif_running(adapter->netdev))
1846 igb_power_down_link(adapter);
1847
9d5c8243
AK		 1848 igb_update_mng_vlan(adapter);
1849
1850 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1851 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1852
1f6e8178
MV		 1853 /* Re-enable PTP, where applicable. */
1854 igb_ptp_reset(adapter);
1f6e8178 1855
330a6d6a 1856 igb_get_phy_info(hw);
9d5c8243
AK		 1857}
1858
c8f44aff
MM		 1859static netdev_features_t igb_fix_features(struct net_device *netdev,
1860 netdev_features_t features)
b2cb09b1 1861{
b980ac18
JK		 1862 /* Since there is no support for separate Rx/Tx vlan accel
1863 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1864 */
f646968f
PM		 1865 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1866 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1867 else
f646968f 1868 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1869
1870 return features;
1871}
1872
c8f44aff
MM		 1873static int igb_set_features(struct net_device *netdev,
1874 netdev_features_t features)
ac52caa3 1875{
c8f44aff 1876 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1877 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1878
f646968f 1879 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1880 igb_vlan_mode(netdev, features);
1881
89eaefb6
BG		 1882 if (!(changed & NETIF_F_RXALL))
1883 return 0;
1884
1885 netdev->features = features;
1886
1887 if (netif_running(netdev))
1888 igb_reinit_locked(adapter);
1889 else
1890 igb_reset(adapter);
1891
ac52caa3
MM		 1892 return 0;
1893}
1894
2e5c6922 1895static const struct net_device_ops igb_netdev_ops = {
559e9c49 1896 .ndo_open = igb_open,
2e5c6922 1897 .ndo_stop = igb_close,
cd392f5c 1898 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1899 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1900 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1901 .ndo_set_mac_address = igb_set_mac,
1902 .ndo_change_mtu = igb_change_mtu,
1903 .ndo_do_ioctl = igb_ioctl,
1904 .ndo_tx_timeout = igb_tx_timeout,
1905 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1906 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1907 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1908 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1909 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1910 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1911 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1912 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1913#ifdef CONFIG_NET_POLL_CONTROLLER
1914 .ndo_poll_controller = igb_netpoll,
1915#endif
b2cb09b1
JP		 1916 .ndo_fix_features = igb_fix_features,
1917 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1918};
1919
d67974f0
CW		 1920/**
1921 * igb_set_fw_version - Configure version string for ethtool
1922 * @adapter: adapter struct
d67974f0
CW		 1923 **/
1924void igb_set_fw_version(struct igb_adapter *adapter)
1925{
1926 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1927 struct e1000_fw_version fw;
1928
1929 igb_get_fw_version(hw, &fw);
1930
1931 switch (hw->mac.type) {
1932 case e1000_i211:
d67974f0 1933 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1934 "%2d.%2d-%d",
1935 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1936 break;
1937
1938 default:
1939 /* if option is rom valid, display its version too */
1940 if (fw.or_valid) {
1941 snprintf(adapter->fw_version,
1942 sizeof(adapter->fw_version),
1943 "%d.%d, 0x%08x, %d.%d.%d",
1944 fw.eep_major, fw.eep_minor, fw.etrack_id,
1945 fw.or_major, fw.or_build, fw.or_patch);
1946 /* no option rom */
1947 } else {
1948 snprintf(adapter->fw_version,
1949 sizeof(adapter->fw_version),
1950 "%d.%d, 0x%08x",
1951 fw.eep_major, fw.eep_minor, fw.etrack_id);
1952 }
1953 break;
d67974f0 1954 }
d67974f0
CW		 1955 return;
1956}
1957
b980ac18
JK		 1958/**
1959 * igb_init_i2c - Init I2C interface
441fc6fd 1960 * @adapter: pointer to adapter structure
b980ac18 1961 **/
441fc6fd
CW		 1962static s32 igb_init_i2c(struct igb_adapter *adapter)
1963{
1964 s32 status = E1000_SUCCESS;
1965
1966 /* I2C interface supported on i350 devices */
1967 if (adapter->hw.mac.type != e1000_i350)
1968 return E1000_SUCCESS;
1969
1970 /* Initialize the i2c bus which is controlled by the registers.
1971 * This bus will use the i2c_algo_bit structue that implements
1972 * the protocol through toggling of the 4 bits in the register.
1973 */
1974 adapter->i2c_adap.owner = THIS_MODULE;
1975 adapter->i2c_algo = igb_i2c_algo;
1976 adapter->i2c_algo.data = adapter;
1977 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1978 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1979 strlcpy(adapter->i2c_adap.name, "igb BB",
1980 sizeof(adapter->i2c_adap.name));
1981 status = i2c_bit_add_bus(&adapter->i2c_adap);
1982 return status;
1983}
1984
9d5c8243 1985/**
b980ac18
JK		 1986 * igb_probe - Device Initialization Routine
1987 * @pdev: PCI device information struct
1988 * @ent: entry in igb_pci_tbl
9d5c8243 1989 *
b980ac18 1990 * Returns 0 on success, negative on failure
9d5c8243 1991 *
b980ac18
JK		 1992 * igb_probe initializes an adapter identified by a pci_dev structure.
1993 * The OS initialization, configuring of the adapter private structure,
1994 * and a hardware reset occur.
9d5c8243 1995 **/
1dd06ae8 1996static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 1997{
1998 struct net_device *netdev;
1999 struct igb_adapter *adapter;
2000 struct e1000_hw *hw;
4337e993 2001 u16 eeprom_data = 0;
9835fd73 2002 s32 ret_val;
4337e993 2003 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 2004 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2005 unsigned long mmio_start, mmio_len;
2d6a5e95 2006 int err, pci_using_dac;
9835fd73 2007 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2008
bded64a7
AG		 2009 /* Catch broken hardware that put the wrong VF device ID in
2010 * the PCIe SR-IOV capability.
2011 */
2012 if (pdev->is_virtfn) {
2013 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2014 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2015 return -EINVAL;
2016 }
2017
aed5dec3 2018 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2019 if (err)
2020 return err;
2021
2022 pci_using_dac = 0;
59d71989 2023 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2024 if (!err) {
59d71989 2025 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 2026 if (!err)
2027 pci_using_dac = 1;
2028 } else {
59d71989 2029 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2030 if (err) {
b980ac18
JK		 2031 err = dma_set_coherent_mask(&pdev->dev,
2032 DMA_BIT_MASK(32));
9d5c8243 2033 if (err) {
b980ac18
JK		 2034 dev_err(&pdev->dev,
2035 "No usable DMA configuration, aborting\n");
9d5c8243
AK		 2036 goto err_dma;
2037 }
2038 }
2039 }
2040
aed5dec3 2041 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2042 IORESOURCE_MEM),
2043 igb_driver_name);
9d5c8243
AK		 2044 if (err)
2045 goto err_pci_reg;
2046
19d5afd4 2047 pci_enable_pcie_error_reporting(pdev);
40a914fa 2048
9d5c8243 2049 pci_set_master(pdev);
c682fc23 2050 pci_save_state(pdev);
9d5c8243
AK		 2051
2052 err = -ENOMEM;
1bfaf07b 2053 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2054 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2055 if (!netdev)
2056 goto err_alloc_etherdev;
2057
2058 SET_NETDEV_DEV(netdev, &pdev->dev);
2059
2060 pci_set_drvdata(pdev, netdev);
2061 adapter = netdev_priv(netdev);
2062 adapter->netdev = netdev;
2063 adapter->pdev = pdev;
2064 hw = &adapter->hw;
2065 hw->back = adapter;
b3f4d599 2066 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2067
2068 mmio_start = pci_resource_start(pdev, 0);
2069 mmio_len = pci_resource_len(pdev, 0);
2070
2071 err = -EIO;
28b0759c
AD		 2072 hw->hw_addr = ioremap(mmio_start, mmio_len);
2073 if (!hw->hw_addr)
9d5c8243
AK		 2074 goto err_ioremap;
2075
2e5c6922 2076 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2077 igb_set_ethtool_ops(netdev);
9d5c8243 2078 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2079
2080 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2081
2082 netdev->mem_start = mmio_start;
2083 netdev->mem_end = mmio_start + mmio_len;
2084
9d5c8243
AK		 2085 /* PCI config space info */
2086 hw->vendor_id = pdev->vendor;
2087 hw->device_id = pdev->device;
2088 hw->revision_id = pdev->revision;
2089 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2090 hw->subsystem_device_id = pdev->subsystem_device;
2091
9d5c8243
AK		 2092 /* Copy the default MAC, PHY and NVM function pointers */
2093 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2094 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2095 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2096 /* Initialize skew-specific constants */
2097 err = ei->get_invariants(hw);
2098 if (err)
450c87c8 2099 goto err_sw_init;
9d5c8243 2100
450c87c8 2101 /* setup the private structure */
9d5c8243
AK		 2102 err = igb_sw_init(adapter);
2103 if (err)
2104 goto err_sw_init;
2105
2106 igb_get_bus_info_pcie(hw);
2107
2108 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2109
2110 /* Copper options */
2111 if (hw->phy.media_type == e1000_media_type_copper) {
2112 hw->phy.mdix = AUTO_ALL_MODES;
2113 hw->phy.disable_polarity_correction = false;
2114 hw->phy.ms_type = e1000_ms_hw_default;
2115 }
2116
2117 if (igb_check_reset_block(hw))
2118 dev_info(&pdev->dev,
2119 "PHY reset is blocked due to SOL/IDER session.\n");
2120
b980ac18 2121 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2122 * set by igb_sw_init so we should use an or instead of an
2123 * assignment.
2124 */
2125 netdev->features |= NETIF_F_SG |
2126 NETIF_F_IP_CSUM |
2127 NETIF_F_IPV6_CSUM |
2128 NETIF_F_TSO |
2129 NETIF_F_TSO6 |
2130 NETIF_F_RXHASH |
2131 NETIF_F_RXCSUM |
f646968f
PM		 2132 NETIF_F_HW_VLAN_CTAG_RX |
2133 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2134
2135 /* copy netdev features into list of user selectable features */
2136 netdev->hw_features |= netdev->features;
89eaefb6 2137 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2138
2139 /* set this bit last since it cannot be part of hw_features */
f646968f 2140 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2141
2142 netdev->vlan_features |= NETIF_F_TSO |
2143 NETIF_F_TSO6 |
2144 NETIF_F_IP_CSUM |
2145 NETIF_F_IPV6_CSUM |
2146 NETIF_F_SG;
48f29ffc 2147
6b8f0922
BG		 2148 netdev->priv_flags |= IFF_SUPP_NOFCS;
2149
7b872a55 2150 if (pci_using_dac) {
9d5c8243 2151 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2152 netdev->vlan_features |= NETIF_F_HIGHDMA;
2153 }
9d5c8243 2154
ac52caa3
MM		 2155 if (hw->mac.type >= e1000_82576) {
2156 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2157 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2158 }
b9473560 2159
01789349
JP		 2160 netdev->priv_flags |= IFF_UNICAST_FLT;
2161
330a6d6a 2162 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2163
2164 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2165 * known good starting state
2166 */
9d5c8243
AK		 2167 hw->mac.ops.reset_hw(hw);
2168
b980ac18 2169 /* make sure the NVM is good , i211 parts have special NVM that
f96a8a0b
CW		 2170 * doesn't contain a checksum
2171 */
2172 if (hw->mac.type != e1000_i211) {
2173 if (hw->nvm.ops.validate(hw) < 0) {
2174 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2175 err = -EIO;
2176 goto err_eeprom;
2177 }
9d5c8243
AK		 2178 }
2179
2180 /* copy the MAC address out of the NVM */
2181 if (hw->mac.ops.read_mac_addr(hw))
2182 dev_err(&pdev->dev, "NVM Read Error\n");
2183
2184 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2185
aaeb6cdf 2186 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2187 dev_err(&pdev->dev, "Invalid MAC Address\n");
2188 err = -EIO;
2189 goto err_eeprom;
2190 }
2191
d67974f0
CW		 2192 /* get firmware version for ethtool -i */
2193 igb_set_fw_version(adapter);
2194
c061b18d 2195 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2196 (unsigned long) adapter);
c061b18d 2197 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2198 (unsigned long) adapter);
9d5c8243
AK		 2199
2200 INIT_WORK(&adapter->reset_task, igb_reset_task);
2201 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2202
450c87c8 2203 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2204 adapter->fc_autoneg = true;
2205 hw->mac.autoneg = true;
2206 hw->phy.autoneg_advertised = 0x2f;
2207
0cce119a
AD		 2208 hw->fc.requested_mode = e1000_fc_default;
2209 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2210
9d5c8243
AK		 2211 igb_validate_mdi_setting(hw);
2212
63d4a8f9 2213 /* By default, support wake on port A */
a2cf8b6c 2214 if (hw->bus.func == 0)
63d4a8f9
MV		 2215 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2216
2217 /* Check the NVM for wake support on non-port A ports */
2218 if (hw->mac.type >= e1000_82580)
55cac248 2219 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2220 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2221 &eeprom_data);
a2cf8b6c
AD		 2222 else if (hw->bus.func == 1)
2223 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2224
63d4a8f9
MV		 2225 if (eeprom_data & IGB_EEPROM_APME)
2226 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2227
2228 /* now that we have the eeprom settings, apply the special cases where
2229 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2230 * lan on a particular port
2231 */
9d5c8243
AK		 2232 switch (pdev->device) {
2233 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2234 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2235 break;
2236 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2237 case E1000_DEV_ID_82576_FIBER:
2238 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2239 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2240 * regardless of eeprom setting
2241 */
9d5c8243 2242 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2243 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2244 break;
c8ea5ea9 2245 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2246 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2247 /* if quad port adapter, disable WoL on all but port A */
2248 if (global_quad_port_a != 0)
63d4a8f9 2249 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2250 else
2251 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2252 /* Reset for multiple quad port adapters */
2253 if (++global_quad_port_a == 4)
2254 global_quad_port_a = 0;
2255 break;
63d4a8f9
MV		 2256 default:
2257 /* If the device can't wake, don't set software support */
2258 if (!device_can_wakeup(&adapter->pdev->dev))
2259 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2260 }
2261
2262 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2263 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2264 adapter->wol |= E1000_WUFC_MAG;
2265
2266 /* Some vendors want WoL disabled by default, but still supported */
2267 if ((hw->mac.type == e1000_i350) &&
2268 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2269 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2270 adapter->wol = 0;
2271 }
2272
2273 device_set_wakeup_enable(&adapter->pdev->dev,
2274 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2275
2276 /* reset the hardware with the new settings */
2277 igb_reset(adapter);
2278
441fc6fd
CW		 2279 /* Init the I2C interface */
2280 err = igb_init_i2c(adapter);
2281 if (err) {
2282 dev_err(&pdev->dev, "failed to init i2c interface\n");
2283 goto err_eeprom;
2284 }
2285
9d5c8243
AK		 2286 /* let the f/w know that the h/w is now under the control of the
2287 * driver. */
2288 igb_get_hw_control(adapter);
2289
9d5c8243
AK		 2290 strcpy(netdev->name, "eth%d");
2291 err = register_netdev(netdev);
2292 if (err)
2293 goto err_register;
2294
b168dfc5
JB		 2295 /* carrier off reporting is important to ethtool even BEFORE open */
2296 netif_carrier_off(netdev);
2297
421e02f0 2298#ifdef CONFIG_IGB_DCA
bbd98fe4 2299 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2300 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2301 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2302 igb_setup_dca(adapter);
2303 }
fe4506b6 2304
38c845c7 2305#endif
e428893b
CW		 2306#ifdef CONFIG_IGB_HWMON
2307 /* Initialize the thermal sensor on i350 devices. */
2308 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2309 u16 ets_word;
3c89f6d0 2310
b980ac18 2311 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2312 * external thermal sensor.
2313 */
2314 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2315 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2316 adapter->ets = true;
2317 else
2318 adapter->ets = false;
2319 if (igb_sysfs_init(adapter))
2320 dev_err(&pdev->dev,
2321 "failed to allocate sysfs resources\n");
2322 } else {
2323 adapter->ets = false;
2324 }
2325#endif
673b8b70 2326 /* do hw tstamp init after resetting */
7ebae817 2327 igb_ptp_init(adapter);
673b8b70 2328
9d5c8243 2329 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2330 /* print bus type/speed/width info, not applicable to i354 */
2331 if (hw->mac.type != e1000_i354) {
2332 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2333 netdev->name,
2334 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2335 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2336 "unknown"),
2337 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2338 "Width x4" :
2339 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2340 "Width x2" :
2341 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2342 "Width x1" : "unknown"), netdev->dev_addr);
2343 }
9d5c8243 2344
9835fd73
CW		 2345 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2346 if (ret_val)
2347 strcpy(part_str, "Unknown");
2348 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2349 dev_info(&pdev->dev,
2350 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2351 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2352 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2353 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2354 switch (hw->mac.type) {
2355 case e1000_i350:
f96a8a0b
CW		 2356 case e1000_i210:
2357 case e1000_i211:
09b068d4
CW		 2358 igb_set_eee_i350(hw);
2359 break;
ceb5f13b
CW		 2360 case e1000_i354:
2361 if (hw->phy.media_type == e1000_media_type_copper) {
2362 if ((rd32(E1000_CTRL_EXT) &
2363 E1000_CTRL_EXT_LINK_MODE_SGMII))
2364 igb_set_eee_i354(hw);
2365 }
2366 break;
09b068d4
CW		 2367 default:
2368 break;
2369 }
749ab2cd
YZ		 2370
2371 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2372 return 0;
2373
2374err_register:
2375 igb_release_hw_control(adapter);
441fc6fd 2376 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2377err_eeprom:
2378 if (!igb_check_reset_block(hw))
f5f4cf08 2379 igb_reset_phy(hw);
9d5c8243
AK		 2380
2381 if (hw->flash_address)
2382 iounmap(hw->flash_address);
9d5c8243 2383err_sw_init:
047e0030 2384 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2385 iounmap(hw->hw_addr);
2386err_ioremap:
2387 free_netdev(netdev);
2388err_alloc_etherdev:
559e9c49 2389 pci_release_selected_regions(pdev,
b980ac18 2390 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2391err_pci_reg:
2392err_dma:
2393 pci_disable_device(pdev);
2394 return err;
2395}
2396
fa44f2f1
GR		 2397#ifdef CONFIG_PCI_IOV
2398static int igb_disable_sriov(struct pci_dev *pdev)
2399{
2400 struct net_device *netdev = pci_get_drvdata(pdev);
2401 struct igb_adapter *adapter = netdev_priv(netdev);
2402 struct e1000_hw *hw = &adapter->hw;
2403
2404 /* reclaim resources allocated to VFs */
2405 if (adapter->vf_data) {
2406 /* disable iov and allow time for transactions to clear */
b09186d2 2407 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2408 dev_warn(&pdev->dev,
2409 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2410 return -EPERM;
2411 } else {
2412 pci_disable_sriov(pdev);
2413 msleep(500);
2414 }
2415
2416 kfree(adapter->vf_data);
2417 adapter->vf_data = NULL;
2418 adapter->vfs_allocated_count = 0;
2419 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2420 wrfl();
2421 msleep(100);
2422 dev_info(&pdev->dev, "IOV Disabled\n");
2423
2424 /* Re-enable DMA Coalescing flag since IOV is turned off */
2425 adapter->flags |= IGB_FLAG_DMAC;
2426 }
2427
2428 return 0;
2429}
2430
2431static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2432{
2433 struct net_device *netdev = pci_get_drvdata(pdev);
2434 struct igb_adapter *adapter = netdev_priv(netdev);
2435 int old_vfs = pci_num_vf(pdev);
2436 int err = 0;
2437 int i;
2438
50267196
MW		 2439 if (!adapter->msix_entries) {
2440 err = -EPERM;
2441 goto out;
2442 }
2443
fa44f2f1
GR		 2444 if (!num_vfs)
2445 goto out;
2446 else if (old_vfs && old_vfs == num_vfs)
2447 goto out;
2448 else if (old_vfs && old_vfs != num_vfs)
2449 err = igb_disable_sriov(pdev);
2450
2451 if (err)
2452 goto out;
2453
2454 if (num_vfs > 7) {
2455 err = -EPERM;
2456 goto out;
2457 }
2458
2459 adapter->vfs_allocated_count = num_vfs;
2460
2461 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2462 sizeof(struct vf_data_storage), GFP_KERNEL);
2463
2464 /* if allocation failed then we do not support SR-IOV */
2465 if (!adapter->vf_data) {
2466 adapter->vfs_allocated_count = 0;
2467 dev_err(&pdev->dev,
2468 "Unable to allocate memory for VF Data Storage\n");
2469 err = -ENOMEM;
2470 goto out;
2471 }
2472
2473 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2474 if (err)
2475 goto err_out;
2476
2477 dev_info(&pdev->dev, "%d VFs allocated\n",
2478 adapter->vfs_allocated_count);
2479 for (i = 0; i < adapter->vfs_allocated_count; i++)
2480 igb_vf_configure(adapter, i);
2481
2482 /* DMA Coalescing is not supported in IOV mode. */
2483 adapter->flags &= ~IGB_FLAG_DMAC;
2484 goto out;
2485
2486err_out:
2487 kfree(adapter->vf_data);
2488 adapter->vf_data = NULL;
2489 adapter->vfs_allocated_count = 0;
2490out:
2491 return err;
2492}
2493
2494#endif
b980ac18 2495/**
441fc6fd
CW		 2496 * igb_remove_i2c - Cleanup I2C interface
2497 * @adapter: pointer to adapter structure
b980ac18 2498 **/
441fc6fd
CW		 2499static void igb_remove_i2c(struct igb_adapter *adapter)
2500{
441fc6fd
CW		 2501 /* free the adapter bus structure */
2502 i2c_del_adapter(&adapter->i2c_adap);
2503}
2504
9d5c8243 2505/**
b980ac18
JK		 2506 * igb_remove - Device Removal Routine
2507 * @pdev: PCI device information struct
9d5c8243 2508 *
b980ac18
JK		 2509 * igb_remove is called by the PCI subsystem to alert the driver
2510 * that it should release a PCI device. The could be caused by a
2511 * Hot-Plug event, or because the driver is going to be removed from
2512 * memory.
9d5c8243 2513 **/
9f9a12f8 2514static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2515{
2516 struct net_device *netdev = pci_get_drvdata(pdev);
2517 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2518 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2519
749ab2cd 2520 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2521#ifdef CONFIG_IGB_HWMON
2522 igb_sysfs_exit(adapter);
2523#endif
441fc6fd 2524 igb_remove_i2c(adapter);
a79f4f88 2525 igb_ptp_stop(adapter);
b980ac18 2526 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2527 * disable watchdog from being rescheduled.
2528 */
9d5c8243
AK		 2529 set_bit(__IGB_DOWN, &adapter->state);
2530 del_timer_sync(&adapter->watchdog_timer);
2531 del_timer_sync(&adapter->phy_info_timer);
2532
760141a5
TH		 2533 cancel_work_sync(&adapter->reset_task);
2534 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2535
421e02f0 2536#ifdef CONFIG_IGB_DCA
7dfc16fa 2537 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2538 dev_info(&pdev->dev, "DCA disabled\n");
2539 dca_remove_requester(&pdev->dev);
7dfc16fa 2540 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2541 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2542 }
2543#endif
2544
9d5c8243 2545 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2546 * would have already happened in close and is redundant.
2547 */
9d5c8243
AK		 2548 igb_release_hw_control(adapter);
2549
2550 unregister_netdev(netdev);
2551
047e0030 2552 igb_clear_interrupt_scheme(adapter);
9d5c8243 2553
37680117 2554#ifdef CONFIG_PCI_IOV
fa44f2f1 2555 igb_disable_sriov(pdev);
37680117 2556#endif
559e9c49 2557
28b0759c
AD		 2558 iounmap(hw->hw_addr);
2559 if (hw->flash_address)
2560 iounmap(hw->flash_address);
559e9c49 2561 pci_release_selected_regions(pdev,
b980ac18 2562 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2563
1128c756 2564 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2565 free_netdev(netdev);
2566
19d5afd4 2567 pci_disable_pcie_error_reporting(pdev);
40a914fa 2568
9d5c8243
AK		 2569 pci_disable_device(pdev);
2570}
2571
a6b623e0 2572/**
b980ac18
JK		 2573 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2574 * @adapter: board private structure to initialize
a6b623e0 2575 *
b980ac18
JK		 2576 * This function initializes the vf specific data storage and then attempts to
2577 * allocate the VFs. The reason for ordering it this way is because it is much
2578 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2579 * the memory for the VFs.
a6b623e0 2580 **/
9f9a12f8 2581static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2582{
2583#ifdef CONFIG_PCI_IOV
2584 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2585 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2586
f96a8a0b
CW		 2587 /* Virtualization features not supported on i210 family. */
2588 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2589 return;
2590
fa44f2f1 2591 pci_sriov_set_totalvfs(pdev, 7);
d5e51a10 2592 igb_enable_sriov(pdev, max_vfs);
0224d663 2593
a6b623e0
AD		 2594#endif /* CONFIG_PCI_IOV */
2595}
2596
fa44f2f1 2597static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2598{
2599 struct e1000_hw *hw = &adapter->hw;
374a542d 2600 u32 max_rss_queues;
9d5c8243 2601
374a542d 2602 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2603 switch (hw->mac.type) {
374a542d
MV		 2604 case e1000_i211:
2605 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2606 break;
2607 case e1000_82575:
f96a8a0b 2608 case e1000_i210:
374a542d
MV		 2609 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2610 break;
2611 case e1000_i350:
2612 /* I350 cannot do RSS and SR-IOV at the same time */
2613 if (!!adapter->vfs_allocated_count) {
2614 max_rss_queues = 1;
2615 break;
2616 }
2617 /* fall through */
2618 case e1000_82576:
2619 if (!!adapter->vfs_allocated_count) {
2620 max_rss_queues = 2;
2621 break;
2622 }
2623 /* fall through */
2624 case e1000_82580:
ceb5f13b 2625 case e1000_i354:
374a542d
MV		 2626 default:
2627 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2628 break;
374a542d
MV		 2629 }
2630
2631 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2632
2633 /* Determine if we need to pair queues. */
2634 switch (hw->mac.type) {
2635 case e1000_82575:
f96a8a0b 2636 case e1000_i211:
374a542d 2637 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2638 break;
374a542d 2639 case e1000_82576:
b980ac18 2640 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2641 * should pair the queues in order to conserve interrupts due
2642 * to limited supply.
2643 */
2644 if ((adapter->rss_queues > 1) &&
2645 (adapter->vfs_allocated_count > 6))
2646 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2647 /* fall through */
2648 case e1000_82580:
2649 case e1000_i350:
ceb5f13b 2650 case e1000_i354:
374a542d 2651 case e1000_i210:
f96a8a0b 2652 default:
b980ac18 2653 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2654 * order to conserve interrupts due to limited supply.
2655 */
2656 if (adapter->rss_queues > (max_rss_queues / 2))
2657 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2658 break;
2659 }
fa44f2f1
GR		 2660}
2661
2662/**
b980ac18
JK		 2663 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2664 * @adapter: board private structure to initialize
fa44f2f1 2665 *
b980ac18
JK		 2666 * igb_sw_init initializes the Adapter private data structure.
2667 * Fields are initialized based on PCI device information and
2668 * OS network device settings (MTU size).
fa44f2f1
GR		 2669 **/
2670static int igb_sw_init(struct igb_adapter *adapter)
2671{
2672 struct e1000_hw *hw = &adapter->hw;
2673 struct net_device *netdev = adapter->netdev;
2674 struct pci_dev *pdev = adapter->pdev;
2675
2676 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2677
2678 /* set default ring sizes */
2679 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2680 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2681
2682 /* set default ITR values */
2683 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2684 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2685
2686 /* set default work limits */
2687 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2688
2689 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2690 VLAN_HLEN;
2691 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2692
2693 spin_lock_init(&adapter->stats64_lock);
2694#ifdef CONFIG_PCI_IOV
2695 switch (hw->mac.type) {
2696 case e1000_82576:
2697 case e1000_i350:
2698 if (max_vfs > 7) {
2699 dev_warn(&pdev->dev,
2700 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2701 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2702 } else
2703 adapter->vfs_allocated_count = max_vfs;
2704 if (adapter->vfs_allocated_count)
2705 dev_warn(&pdev->dev,
2706 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2707 break;
2708 default:
2709 break;
2710 }
2711#endif /* CONFIG_PCI_IOV */
2712
2713 igb_init_queue_configuration(adapter);
a99955fc 2714
1128c756 2715 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2716 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2717 GFP_ATOMIC);
1128c756 2718
a6b623e0 2719 /* This call may decrease the number of queues */
53c7d064 2720 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2721 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2722 return -ENOMEM;
2723 }
2724
a6b623e0
AD		 2725 igb_probe_vfs(adapter);
2726
9d5c8243
AK		 2727 /* Explicitly disable IRQ since the NIC can be in any state. */
2728 igb_irq_disable(adapter);
2729
f96a8a0b 2730 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2731 adapter->flags &= ~IGB_FLAG_DMAC;
2732
9d5c8243
AK		 2733 set_bit(__IGB_DOWN, &adapter->state);
2734 return 0;
2735}
2736
2737/**
b980ac18
JK		 2738 * igb_open - Called when a network interface is made active
2739 * @netdev: network interface device structure
9d5c8243 2740 *
b980ac18 2741 * Returns 0 on success, negative value on failure
9d5c8243 2742 *
b980ac18
JK		 2743 * The open entry point is called when a network interface is made
2744 * active by the system (IFF_UP). At this point all resources needed
2745 * for transmit and receive operations are allocated, the interrupt
2746 * handler is registered with the OS, the watchdog timer is started,
2747 * and the stack is notified that the interface is ready.
9d5c8243 2748 **/
749ab2cd 2749static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2750{
2751 struct igb_adapter *adapter = netdev_priv(netdev);
2752 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2753 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2754 int err;
2755 int i;
2756
2757 /* disallow open during test */
749ab2cd
YZ		 2758 if (test_bit(__IGB_TESTING, &adapter->state)) {
2759 WARN_ON(resuming);
9d5c8243 2760 return -EBUSY;
749ab2cd
YZ		 2761 }
2762
2763 if (!resuming)
2764 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2765
b168dfc5
JB		 2766 netif_carrier_off(netdev);
2767
9d5c8243
AK		 2768 /* allocate transmit descriptors */
2769 err = igb_setup_all_tx_resources(adapter);
2770 if (err)
2771 goto err_setup_tx;
2772
2773 /* allocate receive descriptors */
2774 err = igb_setup_all_rx_resources(adapter);
2775 if (err)
2776 goto err_setup_rx;
2777
88a268c1 2778 igb_power_up_link(adapter);
9d5c8243 2779
9d5c8243
AK		 2780 /* before we allocate an interrupt, we must be ready to handle it.
2781 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2782 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2783 * clean_rx handler before we do so.
2784 */
9d5c8243
AK		 2785 igb_configure(adapter);
2786
2787 err = igb_request_irq(adapter);
2788 if (err)
2789 goto err_req_irq;
2790
0c2cc02e
AD		 2791 /* Notify the stack of the actual queue counts. */
2792 err = netif_set_real_num_tx_queues(adapter->netdev,
2793 adapter->num_tx_queues);
2794 if (err)
2795 goto err_set_queues;
2796
2797 err = netif_set_real_num_rx_queues(adapter->netdev,
2798 adapter->num_rx_queues);
2799 if (err)
2800 goto err_set_queues;
2801
9d5c8243
AK		 2802 /* From here on the code is the same as igb_up() */
2803 clear_bit(__IGB_DOWN, &adapter->state);
2804
0d1ae7f4
AD		 2805 for (i = 0; i < adapter->num_q_vectors; i++)
2806 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2807
2808 /* Clear any pending interrupts. */
2809 rd32(E1000_ICR);
844290e5
PW		 2810
2811 igb_irq_enable(adapter);
2812
d4960307
AD		 2813 /* notify VFs that reset has been completed */
2814 if (adapter->vfs_allocated_count) {
2815 u32 reg_data = rd32(E1000_CTRL_EXT);
2816 reg_data |= E1000_CTRL_EXT_PFRSTD;
2817 wr32(E1000_CTRL_EXT, reg_data);
2818 }
2819
d55b53ff
JK		 2820 netif_tx_start_all_queues(netdev);
2821
749ab2cd
YZ		 2822 if (!resuming)
2823 pm_runtime_put(&pdev->dev);
2824
25568a53
AD		 2825 /* start the watchdog. */
2826 hw->mac.get_link_status = 1;
2827 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2828
2829 return 0;
2830
0c2cc02e
AD		 2831err_set_queues:
2832 igb_free_irq(adapter);
9d5c8243
AK		 2833err_req_irq:
2834 igb_release_hw_control(adapter);
88a268c1 2835 igb_power_down_link(adapter);
9d5c8243
AK		 2836 igb_free_all_rx_resources(adapter);
2837err_setup_rx:
2838 igb_free_all_tx_resources(adapter);
2839err_setup_tx:
2840 igb_reset(adapter);
749ab2cd
YZ		 2841 if (!resuming)
2842 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2843
2844 return err;
2845}
2846
749ab2cd
YZ		 2847static int igb_open(struct net_device *netdev)
2848{
2849 return __igb_open(netdev, false);
2850}
2851
9d5c8243 2852/**
b980ac18
JK		 2853 * igb_close - Disables a network interface
2854 * @netdev: network interface device structure
9d5c8243 2855 *
b980ac18 2856 * Returns 0, this is not allowed to fail
9d5c8243 2857 *
b980ac18
JK		 2858 * The close entry point is called when an interface is de-activated
2859 * by the OS. The hardware is still under the driver's control, but
2860 * needs to be disabled. A global MAC reset is issued to stop the
2861 * hardware, and all transmit and receive resources are freed.
9d5c8243 2862 **/
749ab2cd 2863static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2864{
2865 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2866 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2867
2868 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2869
749ab2cd
YZ		 2870 if (!suspending)
2871 pm_runtime_get_sync(&pdev->dev);
2872
2873 igb_down(adapter);
9d5c8243
AK		 2874 igb_free_irq(adapter);
2875
2876 igb_free_all_tx_resources(adapter);
2877 igb_free_all_rx_resources(adapter);
2878
749ab2cd
YZ		 2879 if (!suspending)
2880 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2881 return 0;
2882}
2883
749ab2cd
YZ		 2884static int igb_close(struct net_device *netdev)
2885{
2886 return __igb_close(netdev, false);
2887}
2888
9d5c8243 2889/**
b980ac18
JK		 2890 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2891 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2892 *
b980ac18 2893 * Return 0 on success, negative on failure
9d5c8243 2894 **/
80785298 2895int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2896{
59d71989 2897 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2898 int size;
2899
06034649 2900 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2901
2902 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2903 if (!tx_ring->tx_buffer_info)
9d5c8243 2904 goto err;
9d5c8243
AK		 2905
2906 /* round up to nearest 4K */
85e8d004 2907 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2908 tx_ring->size = ALIGN(tx_ring->size, 4096);
2909
5536d210
AD		 2910 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2911 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2912 if (!tx_ring->desc)
2913 goto err;
2914
9d5c8243
AK		 2915 tx_ring->next_to_use = 0;
2916 tx_ring->next_to_clean = 0;
81c2fc22 2917
9d5c8243
AK		 2918 return 0;
2919
2920err:
06034649 2921 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2922 tx_ring->tx_buffer_info = NULL;
2923 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2924 return -ENOMEM;
2925}
2926
2927/**
b980ac18
JK		 2928 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2929 * (Descriptors) for all queues
2930 * @adapter: board private structure
9d5c8243 2931 *
b980ac18 2932 * Return 0 on success, negative on failure
9d5c8243
AK		 2933 **/
2934static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2935{
439705e1 2936 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2937 int i, err = 0;
2938
2939 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2940 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2941 if (err) {
439705e1 2942 dev_err(&pdev->dev,
9d5c8243
AK		 2943 "Allocation for Tx Queue %u failed\n", i);
2944 for (i--; i >= 0; i--)
3025a446 2945 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2946 break;
2947 }
2948 }
2949
2950 return err;
2951}
2952
2953/**
b980ac18
JK		 2954 * igb_setup_tctl - configure the transmit control registers
2955 * @adapter: Board private structure
9d5c8243 2956 **/
d7ee5b3a 2957void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2958{
9d5c8243
AK		 2959 struct e1000_hw *hw = &adapter->hw;
2960 u32 tctl;
9d5c8243 2961
85b430b4
AD		 2962 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2963 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2964
2965 /* Program the Transmit Control Register */
9d5c8243
AK		 2966 tctl = rd32(E1000_TCTL);
2967 tctl &= ~E1000_TCTL_CT;
2968 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2969 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2970
2971 igb_config_collision_dist(hw);
2972
9d5c8243
AK		 2973 /* Enable transmits */
2974 tctl |= E1000_TCTL_EN;
2975
2976 wr32(E1000_TCTL, tctl);
2977}
2978
85b430b4 2979/**
b980ac18
JK		 2980 * igb_configure_tx_ring - Configure transmit ring after Reset
2981 * @adapter: board private structure
2982 * @ring: tx ring to configure
85b430b4 2983 *
b980ac18 2984 * Configure a transmit ring after a reset.
85b430b4 2985 **/
d7ee5b3a
AD		 2986void igb_configure_tx_ring(struct igb_adapter *adapter,
2987 struct igb_ring *ring)
85b430b4
AD		 2988{
2989 struct e1000_hw *hw = &adapter->hw;
a74420e0 2990 u32 txdctl = 0;
85b430b4
AD		 2991 u64 tdba = ring->dma;
2992 int reg_idx = ring->reg_idx;
2993
2994 /* disable the queue */
a74420e0 2995 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2996 wrfl();
2997 mdelay(10);
2998
2999 wr32(E1000_TDLEN(reg_idx),
b980ac18 3000 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3001 wr32(E1000_TDBAL(reg_idx),
b980ac18 3002 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3003 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3004
fce99e34 3005 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3006 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3007 writel(0, ring->tail);
85b430b4
AD		 3008
3009 txdctl |= IGB_TX_PTHRESH;
3010 txdctl |= IGB_TX_HTHRESH << 8;
3011 txdctl |= IGB_TX_WTHRESH << 16;
3012
3013 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3014 wr32(E1000_TXDCTL(reg_idx), txdctl);
3015}
3016
3017/**
b980ac18
JK		 3018 * igb_configure_tx - Configure transmit Unit after Reset
3019 * @adapter: board private structure
85b430b4 3020 *
b980ac18 3021 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3022 **/
3023static void igb_configure_tx(struct igb_adapter *adapter)
3024{
3025 int i;
3026
3027 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3028 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3029}
3030
9d5c8243 3031/**
b980ac18
JK		 3032 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3033 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3034 *
b980ac18 3035 * Returns 0 on success, negative on failure
9d5c8243 3036 **/
80785298 3037int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3038{
59d71989 3039 struct device *dev = rx_ring->dev;
f33005a6 3040 int size;
9d5c8243 3041
06034649 3042 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3043
3044 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3045 if (!rx_ring->rx_buffer_info)
9d5c8243 3046 goto err;
9d5c8243 3047
9d5c8243 3048 /* Round up to nearest 4K */
f33005a6 3049 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3050 rx_ring->size = ALIGN(rx_ring->size, 4096);
3051
5536d210
AD		 3052 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3053 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3054 if (!rx_ring->desc)
3055 goto err;
3056
cbc8e55f 3057 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3058 rx_ring->next_to_clean = 0;
3059 rx_ring->next_to_use = 0;
9d5c8243 3060
9d5c8243
AK		 3061 return 0;
3062
3063err:
06034649
AD		 3064 vfree(rx_ring->rx_buffer_info);
3065 rx_ring->rx_buffer_info = NULL;
f33005a6 3066 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3067 return -ENOMEM;
3068}
3069
3070/**
b980ac18
JK		 3071 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3072 * (Descriptors) for all queues
3073 * @adapter: board private structure
9d5c8243 3074 *
b980ac18 3075 * Return 0 on success, negative on failure
9d5c8243
AK		 3076 **/
3077static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3078{
439705e1 3079 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3080 int i, err = 0;
3081
3082 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3083 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3084 if (err) {
439705e1 3085 dev_err(&pdev->dev,
9d5c8243
AK		 3086 "Allocation for Rx Queue %u failed\n", i);
3087 for (i--; i >= 0; i--)
3025a446 3088 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3089 break;
3090 }
3091 }
3092
3093 return err;
3094}
3095
06cf2666 3096/**
b980ac18
JK		 3097 * igb_setup_mrqc - configure the multiple receive queue control registers
3098 * @adapter: Board private structure
06cf2666
AD		 3099 **/
3100static void igb_setup_mrqc(struct igb_adapter *adapter)
3101{
3102 struct e1000_hw *hw = &adapter->hw;
3103 u32 mrqc, rxcsum;
797fd4be 3104 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 3105 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3106 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3107 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3108 0xFA01ACBE };
06cf2666
AD		 3109
3110 /* Fill out hash function seeds */
a57fe23e
AD		 3111 for (j = 0; j < 10; j++)
3112 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3113
a99955fc 3114 num_rx_queues = adapter->rss_queues;
06cf2666 3115
797fd4be
AD		 3116 switch (hw->mac.type) {
3117 case e1000_82575:
3118 shift = 6;
3119 break;
3120 case e1000_82576:
3121 /* 82576 supports 2 RSS queues for SR-IOV */
3122 if (adapter->vfs_allocated_count) {
06cf2666
AD		 3123 shift = 3;
3124 num_rx_queues = 2;
06cf2666 3125 }
797fd4be
AD		 3126 break;
3127 default:
3128 break;
06cf2666
AD		 3129 }
3130
b980ac18 3131 /* Populate the indirection table 4 entries at a time. To do this
797fd4be
AD		 3132 * we are generating the results for n and n+2 and then interleaving
3133 * those with the results with n+1 and n+3.
3134 */
3135 for (j = 0; j < 32; j++) {
3136 /* first pass generates n and n+2 */
3137 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3138 u32 reta = (base & 0x07800780) >> (7 - shift);
3139
3140 /* second pass generates n+1 and n+3 */
3141 base += 0x00010001 * num_rx_queues;
3142 reta |= (base & 0x07800780) << (1 + shift);
3143
3144 wr32(E1000_RETA(j), reta);
06cf2666
AD		 3145 }
3146
b980ac18 3147 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3148 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3149 * offloads as they are enabled by default
3150 */
3151 rxcsum = rd32(E1000_RXCSUM);
3152 rxcsum |= E1000_RXCSUM_PCSD;
3153
3154 if (adapter->hw.mac.type >= e1000_82576)
3155 /* Enable Receive Checksum Offload for SCTP */
3156 rxcsum |= E1000_RXCSUM_CRCOFL;
3157
3158 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3159 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3160
039454a8
AA		 3161 /* Generate RSS hash based on packet types, TCP/UDP
3162 * port numbers and/or IPv4/v6 src and dst addresses
3163 */
f96a8a0b
CW		 3164 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3165 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3166 E1000_MRQC_RSS_FIELD_IPV6 |
3167 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3168 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3169
039454a8
AA		 3170 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3171 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3172 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3173 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3174
06cf2666
AD		 3175 /* If VMDq is enabled then we set the appropriate mode for that, else
3176 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3177 * if we are only using one queue
3178 */
06cf2666
AD		 3179 if (adapter->vfs_allocated_count) {
3180 if (hw->mac.type > e1000_82575) {
3181 /* Set the default pool for the PF's first queue */
3182 u32 vtctl = rd32(E1000_VT_CTL);
3183 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3184 E1000_VT_CTL_DISABLE_DEF_POOL);
3185 vtctl |= adapter->vfs_allocated_count <<
3186 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3187 wr32(E1000_VT_CTL, vtctl);
3188 }
a99955fc 3189 if (adapter->rss_queues > 1)
f96a8a0b 3190 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3191 else
f96a8a0b 3192 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3193 } else {
f96a8a0b
CW		 3194 if (hw->mac.type != e1000_i211)
3195 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3196 }
3197 igb_vmm_control(adapter);
3198
06cf2666
AD		 3199 wr32(E1000_MRQC, mrqc);
3200}
3201
9d5c8243 3202/**
b980ac18
JK		 3203 * igb_setup_rctl - configure the receive control registers
3204 * @adapter: Board private structure
9d5c8243 3205 **/
d7ee5b3a 3206void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3207{
3208 struct e1000_hw *hw = &adapter->hw;
3209 u32 rctl;
9d5c8243
AK		 3210
3211 rctl = rd32(E1000_RCTL);
3212
3213 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3214 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3215
69d728ba 3216 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3217 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3218
b980ac18 3219 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3220 * redirection as it did with e1000. Newer features require
3221 * that the HW strips the CRC.
73cd78f1 3222 */
87cb7e8c 3223 rctl |= E1000_RCTL_SECRC;
9d5c8243 3224
559e9c49 3225 /* disable store bad packets and clear size bits. */
ec54d7d6 3226 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3227
6ec43fe6
AD		 3228 /* enable LPE to prevent packets larger than max_frame_size */
3229 rctl |= E1000_RCTL_LPE;
9d5c8243 3230
952f72a8
AD		 3231 /* disable queue 0 to prevent tail write w/o re-config */
3232 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3233
e1739522
AD		 3234 /* Attention!!! For SR-IOV PF driver operations you must enable
3235 * queue drop for all VF and PF queues to prevent head of line blocking
3236 * if an un-trusted VF does not provide descriptors to hardware.
3237 */
3238 if (adapter->vfs_allocated_count) {
e1739522
AD		 3239 /* set all queue drop enable bits */
3240 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3241 }
3242
89eaefb6
BG		 3243 /* This is useful for sniffing bad packets. */
3244 if (adapter->netdev->features & NETIF_F_RXALL) {
3245 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3246 * in e1000e_set_rx_mode
3247 */
89eaefb6
BG		 3248 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3249 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3250 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3251
3252 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3253 E1000_RCTL_DPF | /* Allow filtered pause */
3254 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3255 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3256 * and that breaks VLANs.
3257 */
3258 }
3259
9d5c8243
AK		 3260 wr32(E1000_RCTL, rctl);
3261}
3262
7d5753f0
AD		 3263static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3264 int vfn)
3265{
3266 struct e1000_hw *hw = &adapter->hw;
3267 u32 vmolr;
3268
3269 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3270 * increase the size to support vlan tags
3271 */
7d5753f0
AD		 3272 if (vfn < adapter->vfs_allocated_count &&
3273 adapter->vf_data[vfn].vlans_enabled)
3274 size += VLAN_TAG_SIZE;
3275
3276 vmolr = rd32(E1000_VMOLR(vfn));
3277 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3278 vmolr |= size | E1000_VMOLR_LPE;
3279 wr32(E1000_VMOLR(vfn), vmolr);
3280
3281 return 0;
3282}
3283
e1739522 3284/**
b980ac18
JK		 3285 * igb_rlpml_set - set maximum receive packet size
3286 * @adapter: board private structure
e1739522 3287 *
b980ac18 3288 * Configure maximum receivable packet size.
e1739522
AD		 3289 **/
3290static void igb_rlpml_set(struct igb_adapter *adapter)
3291{
153285f9 3292 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3293 struct e1000_hw *hw = &adapter->hw;
3294 u16 pf_id = adapter->vfs_allocated_count;
3295
e1739522
AD		 3296 if (pf_id) {
3297 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3298 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3299 * to our max jumbo frame size, in case we need to enable
3300 * jumbo frames on one of the rings later.
3301 * This will not pass over-length frames into the default
3302 * queue because it's gated by the VMOLR.RLPML.
3303 */
7d5753f0 3304 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3305 }
3306
3307 wr32(E1000_RLPML, max_frame_size);
3308}
3309
8151d294
WM		 3310static inline void igb_set_vmolr(struct igb_adapter *adapter,
3311 int vfn, bool aupe)
7d5753f0
AD		 3312{
3313 struct e1000_hw *hw = &adapter->hw;
3314 u32 vmolr;
3315
b980ac18 3316 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3317 * we should exit and do nothing
3318 */
3319 if (hw->mac.type < e1000_82576)
3320 return;
3321
3322 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3323 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3324 if (aupe)
b980ac18 3325 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3326 else
3327 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3328
3329 /* clear all bits that might not be set */
3330 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3331
a99955fc 3332 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3333 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3334 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3335 * multicast packets
3336 */
3337 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3338 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3339
3340 wr32(E1000_VMOLR(vfn), vmolr);
3341}
3342
85b430b4 3343/**
b980ac18
JK		 3344 * igb_configure_rx_ring - Configure a receive ring after Reset
3345 * @adapter: board private structure
3346 * @ring: receive ring to be configured
85b430b4 3347 *
b980ac18 3348 * Configure the Rx unit of the MAC after a reset.
85b430b4 3349 **/
d7ee5b3a 3350void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3351 struct igb_ring *ring)
85b430b4
AD		 3352{
3353 struct e1000_hw *hw = &adapter->hw;
3354 u64 rdba = ring->dma;
3355 int reg_idx = ring->reg_idx;
a74420e0 3356 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3357
3358 /* disable the queue */
a74420e0 3359 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3360
3361 /* Set DMA base address registers */
3362 wr32(E1000_RDBAL(reg_idx),
3363 rdba & 0x00000000ffffffffULL);
3364 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3365 wr32(E1000_RDLEN(reg_idx),
b980ac18 3366 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3367
3368 /* initialize head and tail */
fce99e34 3369 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3370 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3371 writel(0, ring->tail);
85b430b4 3372
952f72a8 3373 /* set descriptor configuration */
44390ca6 3374 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3375 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3376 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3377 if (hw->mac.type >= e1000_82580)
757b77e2 3378 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3379 /* Only set Drop Enable if we are supporting multiple queues */
3380 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3381 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3382
3383 wr32(E1000_SRRCTL(reg_idx), srrctl);
3384
7d5753f0 3385 /* set filtering for VMDQ pools */
8151d294 3386 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3387
85b430b4
AD		 3388 rxdctl |= IGB_RX_PTHRESH;
3389 rxdctl |= IGB_RX_HTHRESH << 8;
3390 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3391
3392 /* enable receive descriptor fetching */
3393 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3394 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3395}
3396
9d5c8243 3397/**
b980ac18
JK		 3398 * igb_configure_rx - Configure receive Unit after Reset
3399 * @adapter: board private structure
9d5c8243 3400 *
b980ac18 3401 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3402 **/
3403static void igb_configure_rx(struct igb_adapter *adapter)
3404{
9107584e 3405 int i;
9d5c8243 3406
68d480c4
AD		 3407 /* set UTA to appropriate mode */
3408 igb_set_uta(adapter);
3409
26ad9178
AD		 3410 /* set the correct pool for the PF default MAC address in entry 0 */
3411 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3412 adapter->vfs_allocated_count);
26ad9178 3413
06cf2666 3414 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3415 * the Base and Length of the Rx Descriptor Ring
3416 */
f9d40f6a
AD		 3417 for (i = 0; i < adapter->num_rx_queues; i++)
3418 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3419}
3420
3421/**
b980ac18
JK		 3422 * igb_free_tx_resources - Free Tx Resources per Queue
3423 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3424 *
b980ac18 3425 * Free all transmit software resources
9d5c8243 3426 **/
68fd9910 3427void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3428{
3b644cf6 3429 igb_clean_tx_ring(tx_ring);
9d5c8243 3430
06034649
AD		 3431 vfree(tx_ring->tx_buffer_info);
3432 tx_ring->tx_buffer_info = NULL;
9d5c8243 3433
439705e1
AD		 3434 /* if not set, then don't free */
3435 if (!tx_ring->desc)
3436 return;
3437
59d71989
AD		 3438 dma_free_coherent(tx_ring->dev, tx_ring->size,
3439 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3440
3441 tx_ring->desc = NULL;
3442}
3443
3444/**
b980ac18
JK		 3445 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3446 * @adapter: board private structure
9d5c8243 3447 *
b980ac18 3448 * Free all transmit software resources
9d5c8243
AK		 3449 **/
3450static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3451{
3452 int i;
3453
3454 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3455 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3456}
3457
ebe42d16
AD		 3458void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3459 struct igb_tx_buffer *tx_buffer)
3460{
3461 if (tx_buffer->skb) {
3462 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3463 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3464 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3465 dma_unmap_addr(tx_buffer, dma),
3466 dma_unmap_len(tx_buffer, len),
ebe42d16 3467 DMA_TO_DEVICE);
c9f14bf3 3468 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3469 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3470 dma_unmap_addr(tx_buffer, dma),
3471 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3472 DMA_TO_DEVICE);
3473 }
3474 tx_buffer->next_to_watch = NULL;
3475 tx_buffer->skb = NULL;
c9f14bf3 3476 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3477 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3478}
3479
3480/**
b980ac18
JK		 3481 * igb_clean_tx_ring - Free Tx Buffers
3482 * @tx_ring: ring to be cleaned
9d5c8243 3483 **/
3b644cf6 3484static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3485{
06034649 3486 struct igb_tx_buffer *buffer_info;
9d5c8243 3487 unsigned long size;
6ad4edfc 3488 u16 i;
9d5c8243 3489
06034649 3490 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3491 return;
3492 /* Free all the Tx ring sk_buffs */
3493
3494 for (i = 0; i < tx_ring->count; i++) {
06034649 3495 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3496 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3497 }
3498
dad8a3b3
JF		 3499 netdev_tx_reset_queue(txring_txq(tx_ring));
3500
06034649
AD		 3501 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3502 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3503
3504 /* Zero out the descriptor ring */
9d5c8243
AK		 3505 memset(tx_ring->desc, 0, tx_ring->size);
3506
3507 tx_ring->next_to_use = 0;
3508 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3509}
3510
3511/**
b980ac18
JK		 3512 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3513 * @adapter: board private structure
9d5c8243
AK		 3514 **/
3515static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3516{
3517 int i;
3518
3519 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3520 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3521}
3522
3523/**
b980ac18
JK		 3524 * igb_free_rx_resources - Free Rx Resources
3525 * @rx_ring: ring to clean the resources from
9d5c8243 3526 *
b980ac18 3527 * Free all receive software resources
9d5c8243 3528 **/
68fd9910 3529void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3530{
3b644cf6 3531 igb_clean_rx_ring(rx_ring);
9d5c8243 3532
06034649
AD		 3533 vfree(rx_ring->rx_buffer_info);
3534 rx_ring->rx_buffer_info = NULL;
9d5c8243 3535
439705e1
AD		 3536 /* if not set, then don't free */
3537 if (!rx_ring->desc)
3538 return;
3539
59d71989
AD		 3540 dma_free_coherent(rx_ring->dev, rx_ring->size,
3541 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3542
3543 rx_ring->desc = NULL;
3544}
3545
3546/**
b980ac18
JK		 3547 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3548 * @adapter: board private structure
9d5c8243 3549 *
b980ac18 3550 * Free all receive software resources
9d5c8243
AK		 3551 **/
3552static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3553{
3554 int i;
3555
3556 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3557 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3558}
3559
3560/**
b980ac18
JK		 3561 * igb_clean_rx_ring - Free Rx Buffers per Queue
3562 * @rx_ring: ring to free buffers from
9d5c8243 3563 **/
3b644cf6 3564static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3565{
9d5c8243 3566 unsigned long size;
c023cd88 3567 u16 i;
9d5c8243 3568
1a1c225b
AD		 3569 if (rx_ring->skb)
3570 dev_kfree_skb(rx_ring->skb);
3571 rx_ring->skb = NULL;
3572
06034649 3573 if (!rx_ring->rx_buffer_info)
9d5c8243 3574 return;
439705e1 3575
9d5c8243
AK		 3576 /* Free all the Rx ring sk_buffs */
3577 for (i = 0; i < rx_ring->count; i++) {
06034649 3578 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3579
cbc8e55f
AD		 3580 if (!buffer_info->page)
3581 continue;
3582
3583 dma_unmap_page(rx_ring->dev,
3584 buffer_info->dma,
3585 PAGE_SIZE,
3586 DMA_FROM_DEVICE);
3587 __free_page(buffer_info->page);
3588
1a1c225b 3589 buffer_info->page = NULL;
9d5c8243
AK		 3590 }
3591
06034649
AD		 3592 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3593 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3594
3595 /* Zero out the descriptor ring */
3596 memset(rx_ring->desc, 0, rx_ring->size);
3597
cbc8e55f 3598 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3599 rx_ring->next_to_clean = 0;
3600 rx_ring->next_to_use = 0;
9d5c8243
AK		 3601}
3602
3603/**
b980ac18
JK		 3604 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3605 * @adapter: board private structure
9d5c8243
AK		 3606 **/
3607static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3608{
3609 int i;
3610
3611 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3612 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3613}
3614
3615/**
b980ac18
JK		 3616 * igb_set_mac - Change the Ethernet Address of the NIC
3617 * @netdev: network interface device structure
3618 * @p: pointer to an address structure
9d5c8243 3619 *
b980ac18 3620 * Returns 0 on success, negative on failure
9d5c8243
AK		 3621 **/
3622static int igb_set_mac(struct net_device *netdev, void *p)
3623{
3624 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3625 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3626 struct sockaddr *addr = p;
3627
3628 if (!is_valid_ether_addr(addr->sa_data))
3629 return -EADDRNOTAVAIL;
3630
3631 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3632 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3633
26ad9178
AD		 3634 /* set the correct pool for the new PF MAC address in entry 0 */
3635 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3636 adapter->vfs_allocated_count);
e1739522 3637
9d5c8243
AK		 3638 return 0;
3639}
3640
3641/**
b980ac18
JK		 3642 * igb_write_mc_addr_list - write multicast addresses to MTA
3643 * @netdev: network interface device structure
9d5c8243 3644 *
b980ac18
JK		 3645 * Writes multicast address list to the MTA hash table.
3646 * Returns: -ENOMEM on failure
3647 * 0 on no addresses written
3648 * X on writing X addresses to MTA
9d5c8243 3649 **/
68d480c4 3650static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3651{
3652 struct igb_adapter *adapter = netdev_priv(netdev);
3653 struct e1000_hw *hw = &adapter->hw;
22bedad3 3654 struct netdev_hw_addr *ha;
68d480c4 3655 u8 *mta_list;
9d5c8243
AK		 3656 int i;
3657
4cd24eaf 3658 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3659 /* nothing to program, so clear mc list */
3660 igb_update_mc_addr_list(hw, NULL, 0);
3661 igb_restore_vf_multicasts(adapter);
3662 return 0;
3663 }
9d5c8243 3664
4cd24eaf 3665 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3666 if (!mta_list)
3667 return -ENOMEM;
ff41f8dc 3668
68d480c4 3669 /* The shared function expects a packed array of only addresses. */
48e2f183 3670 i = 0;
22bedad3
JP		 3671 netdev_for_each_mc_addr(ha, netdev)
3672 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3673
68d480c4
AD		 3674 igb_update_mc_addr_list(hw, mta_list, i);
3675 kfree(mta_list);
3676
4cd24eaf 3677 return netdev_mc_count(netdev);
68d480c4
AD		 3678}
3679
3680/**
b980ac18
JK		 3681 * igb_write_uc_addr_list - write unicast addresses to RAR table
3682 * @netdev: network interface device structure
68d480c4 3683 *
b980ac18
JK		 3684 * Writes unicast address list to the RAR table.
3685 * Returns: -ENOMEM on failure/insufficient address space
3686 * 0 on no addresses written
3687 * X on writing X addresses to the RAR table
68d480c4
AD		 3688 **/
3689static int igb_write_uc_addr_list(struct net_device *netdev)
3690{
3691 struct igb_adapter *adapter = netdev_priv(netdev);
3692 struct e1000_hw *hw = &adapter->hw;
3693 unsigned int vfn = adapter->vfs_allocated_count;
3694 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3695 int count = 0;
3696
3697 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3698 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3699 return -ENOMEM;
9d5c8243 3700
32e7bfc4 3701 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3702 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3703
3704 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3705 if (!rar_entries)
3706 break;
26ad9178 3707 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3708 rar_entries--,
3709 vfn);
68d480c4 3710 count++;
ff41f8dc
AD		 3711 }
3712 }
3713 /* write the addresses in reverse order to avoid write combining */
3714 for (; rar_entries > 0 ; rar_entries--) {
3715 wr32(E1000_RAH(rar_entries), 0);
3716 wr32(E1000_RAL(rar_entries), 0);
3717 }
3718 wrfl();
3719
68d480c4
AD		 3720 return count;
3721}
3722
3723/**
b980ac18
JK		 3724 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3725 * @netdev: network interface device structure
68d480c4 3726 *
b980ac18
JK		 3727 * The set_rx_mode entry point is called whenever the unicast or multicast
3728 * address lists or the network interface flags are updated. This routine is
3729 * responsible for configuring the hardware for proper unicast, multicast,
3730 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3731 **/
3732static void igb_set_rx_mode(struct net_device *netdev)
3733{
3734 struct igb_adapter *adapter = netdev_priv(netdev);
3735 struct e1000_hw *hw = &adapter->hw;
3736 unsigned int vfn = adapter->vfs_allocated_count;
3737 u32 rctl, vmolr = 0;
3738 int count;
3739
3740 /* Check for Promiscuous and All Multicast modes */
3741 rctl = rd32(E1000_RCTL);
3742
3743 /* clear the effected bits */
3744 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3745
3746 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3747 /* retain VLAN HW filtering if in VT mode */
7e44892c 3748 if (adapter->vfs_allocated_count)
6f3dc319 3749 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3750 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3751 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3752 } else {
3753 if (netdev->flags & IFF_ALLMULTI) {
3754 rctl |= E1000_RCTL_MPE;
3755 vmolr |= E1000_VMOLR_MPME;
3756 } else {
b980ac18 3757 /* Write addresses to the MTA, if the attempt fails
25985edc 3758 * then we should just turn on promiscuous mode so
68d480c4
AD		 3759 * that we can at least receive multicast traffic
3760 */
3761 count = igb_write_mc_addr_list(netdev);
3762 if (count < 0) {
3763 rctl |= E1000_RCTL_MPE;
3764 vmolr |= E1000_VMOLR_MPME;
3765 } else if (count) {
3766 vmolr |= E1000_VMOLR_ROMPE;
3767 }
3768 }
b980ac18 3769 /* Write addresses to available RAR registers, if there is not
68d480c4 3770 * sufficient space to store all the addresses then enable
25985edc 3771 * unicast promiscuous mode
68d480c4
AD		 3772 */
3773 count = igb_write_uc_addr_list(netdev);
3774 if (count < 0) {
3775 rctl |= E1000_RCTL_UPE;
3776 vmolr |= E1000_VMOLR_ROPE;
3777 }
3778 rctl |= E1000_RCTL_VFE;
28fc06f5 3779 }
68d480c4 3780 wr32(E1000_RCTL, rctl);
28fc06f5 3781
b980ac18 3782 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3783 * the VMOLR to enable the appropriate modes. Without this workaround
3784 * we will have issues with VLAN tag stripping not being done for frames
3785 * that are only arriving because we are the default pool
3786 */
f96a8a0b 3787 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3788 return;
9d5c8243 3789
68d480c4 3790 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3791 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3792 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3793 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3794}
3795
13800469
GR		 3796static void igb_check_wvbr(struct igb_adapter *adapter)
3797{
3798 struct e1000_hw *hw = &adapter->hw;
3799 u32 wvbr = 0;
3800
3801 switch (hw->mac.type) {
3802 case e1000_82576:
3803 case e1000_i350:
3804 if (!(wvbr = rd32(E1000_WVBR)))
3805 return;
3806 break;
3807 default:
3808 break;
3809 }
3810
3811 adapter->wvbr |= wvbr;
3812}
3813
3814#define IGB_STAGGERED_QUEUE_OFFSET 8
3815
3816static void igb_spoof_check(struct igb_adapter *adapter)
3817{
3818 int j;
3819
3820 if (!adapter->wvbr)
3821 return;
3822
3823 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3824 if (adapter->wvbr & (1 << j) ||
3825 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3826 dev_warn(&adapter->pdev->dev,
3827 "Spoof event(s) detected on VF %d\n", j);
3828 adapter->wvbr &=
3829 ~((1 << j) |
3830 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3831 }
3832 }
3833}
3834
9d5c8243 3835/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3836 * the phy
3837 */
9d5c8243
AK		 3838static void igb_update_phy_info(unsigned long data)
3839{
3840 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3841 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3842}
3843
4d6b725e 3844/**
b980ac18
JK		 3845 * igb_has_link - check shared code for link and determine up/down
3846 * @adapter: pointer to driver private info
4d6b725e 3847 **/
3145535a 3848bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3849{
3850 struct e1000_hw *hw = &adapter->hw;
3851 bool link_active = false;
4d6b725e
AD		 3852
3853 /* get_link_status is set on LSC (link status) interrupt or
3854 * rx sequence error interrupt. get_link_status will stay
3855 * false until the e1000_check_for_link establishes link
3856 * for copper adapters ONLY
3857 */
3858 switch (hw->phy.media_type) {
3859 case e1000_media_type_copper:
e5c3370f
AA		 3860 if (!hw->mac.get_link_status)
3861 return true;
4d6b725e 3862 case e1000_media_type_internal_serdes:
e5c3370f
AA		 3863 hw->mac.ops.check_for_link(hw);
3864 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 3865 break;
3866 default:
3867 case e1000_media_type_unknown:
3868 break;
3869 }
3870
3871 return link_active;
3872}
3873
563988dc
SA		 3874static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3875{
3876 bool ret = false;
3877 u32 ctrl_ext, thstat;
3878
f96a8a0b 3879 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3880 if (hw->mac.type == e1000_i350) {
3881 thstat = rd32(E1000_THSTAT);
3882 ctrl_ext = rd32(E1000_CTRL_EXT);
3883
3884 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3885 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3886 ret = !!(thstat & event);
563988dc
SA		 3887 }
3888
3889 return ret;
3890}
3891
9d5c8243 3892/**
b980ac18
JK		 3893 * igb_watchdog - Timer Call-back
3894 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3895 **/
3896static void igb_watchdog(unsigned long data)
3897{
3898 struct igb_adapter *adapter = (struct igb_adapter *)data;
3899 /* Do the rest outside of interrupt context */
3900 schedule_work(&adapter->watchdog_task);
3901}
3902
3903static void igb_watchdog_task(struct work_struct *work)
3904{
3905 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3906 struct igb_adapter,
3907 watchdog_task);
9d5c8243 3908 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3909 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3910 struct net_device *netdev = adapter->netdev;
563988dc 3911 u32 link;
7a6ea550 3912 int i;
9d5c8243 3913
4d6b725e 3914 link = igb_has_link(adapter);
9d5c8243 3915 if (link) {
749ab2cd
YZ		 3916 /* Cancel scheduled suspend requests. */
3917 pm_runtime_resume(netdev->dev.parent);
3918
9d5c8243
AK		 3919 if (!netif_carrier_ok(netdev)) {
3920 u32 ctrl;
330a6d6a 3921 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3922 &adapter->link_speed,
3923 &adapter->link_duplex);
9d5c8243
AK		 3924
3925 ctrl = rd32(E1000_CTRL);
527d47c1 3926 /* Links status message must follow this format */
876d2d6f
JK		 3927 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3928 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3929 netdev->name,
3930 adapter->link_speed,
3931 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3932 "Full" : "Half",
3933 (ctrl & E1000_CTRL_TFCE) &&
3934 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3935 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3936 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3937
c0ba4778
KS		 3938 /* check if SmartSpeed worked */
3939 igb_check_downshift(hw);
3940 if (phy->speed_downgraded)
3941 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3942
563988dc 3943 /* check for thermal sensor event */
876d2d6f
JK		 3944 if (igb_thermal_sensor_event(hw,
3945 E1000_THSTAT_LINK_THROTTLE)) {
3946 netdev_info(netdev, "The network adapter link "
3947 "speed was downshifted because it "
3948 "overheated\n");
7ef5ed1c 3949 }
563988dc 3950
d07f3e37 3951 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3952 adapter->tx_timeout_factor = 1;
3953 switch (adapter->link_speed) {
3954 case SPEED_10:
9d5c8243
AK		 3955 adapter->tx_timeout_factor = 14;
3956 break;
3957 case SPEED_100:
9d5c8243
AK		 3958 /* maybe add some timeout factor ? */
3959 break;
3960 }
3961
3962 netif_carrier_on(netdev);
9d5c8243 3963
4ae196df 3964 igb_ping_all_vfs(adapter);
17dc566c 3965 igb_check_vf_rate_limit(adapter);
4ae196df 3966
4b1a9877 3967 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3968 if (!test_bit(__IGB_DOWN, &adapter->state))
3969 mod_timer(&adapter->phy_info_timer,
3970 round_jiffies(jiffies + 2 * HZ));
3971 }
3972 } else {
3973 if (netif_carrier_ok(netdev)) {
3974 adapter->link_speed = 0;
3975 adapter->link_duplex = 0;
563988dc
SA		 3976
3977 /* check for thermal sensor event */
876d2d6f
JK		 3978 if (igb_thermal_sensor_event(hw,
3979 E1000_THSTAT_PWR_DOWN)) {
3980 netdev_err(netdev, "The network adapter was "
3981 "stopped because it overheated\n");
7ef5ed1c 3982 }
563988dc 3983
527d47c1
AD		 3984 /* Links status message must follow this format */
3985 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3986 netdev->name);
9d5c8243 3987 netif_carrier_off(netdev);
4b1a9877 3988
4ae196df
AD		 3989 igb_ping_all_vfs(adapter);
3990
4b1a9877 3991 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3992 if (!test_bit(__IGB_DOWN, &adapter->state))
3993 mod_timer(&adapter->phy_info_timer,
3994 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3995
3996 pm_schedule_suspend(netdev->dev.parent,
3997 MSEC_PER_SEC * 5);
9d5c8243
AK		 3998 }
3999 }
4000
12dcd86b
ED		 4001 spin_lock(&adapter->stats64_lock);
4002 igb_update_stats(adapter, &adapter->stats64);
4003 spin_unlock(&adapter->stats64_lock);
9d5c8243 4004
dbabb065 4005 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4006 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4007 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4008 /* We've lost link, so the controller stops DMA,
4009 * but we've got queued Tx work that's never going
4010 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4011 * (Do the reset outside of interrupt context).
4012 */
dbabb065
AD		 4013 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4014 adapter->tx_timeout_count++;
4015 schedule_work(&adapter->reset_task);
4016 /* return immediately since reset is imminent */
4017 return;
4018 }
9d5c8243 4019 }
9d5c8243 4020
dbabb065 4021 /* Force detection of hung controller every watchdog period */
6d095fa8 4022 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4023 }
f7ba205e 4024
b980ac18 4025 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4026 if (adapter->msix_entries) {
047e0030 4027 u32 eics = 0;
0d1ae7f4
AD		 4028 for (i = 0; i < adapter->num_q_vectors; i++)
4029 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4030 wr32(E1000_EICS, eics);
4031 } else {
4032 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4033 }
9d5c8243 4034
13800469 4035 igb_spoof_check(adapter);
fc580751 4036 igb_ptp_rx_hang(adapter);
13800469 4037
9d5c8243
AK		 4038 /* Reset the timer */
4039 if (!test_bit(__IGB_DOWN, &adapter->state))
4040 mod_timer(&adapter->watchdog_timer,
4041 round_jiffies(jiffies + 2 * HZ));
4042}
4043
4044enum latency_range {
4045 lowest_latency = 0,
4046 low_latency = 1,
4047 bulk_latency = 2,
4048 latency_invalid = 255
4049};
4050
6eb5a7f1 4051/**
b980ac18
JK		 4052 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4053 * @q_vector: pointer to q_vector
6eb5a7f1 4054 *
b980ac18
JK		 4055 * Stores a new ITR value based on strictly on packet size. This
4056 * algorithm is less sophisticated than that used in igb_update_itr,
4057 * due to the difficulty of synchronizing statistics across multiple
4058 * receive rings. The divisors and thresholds used by this function
4059 * were determined based on theoretical maximum wire speed and testing
4060 * data, in order to minimize response time while increasing bulk
4061 * throughput.
4062 * This functionality is controlled by the InterruptThrottleRate module
4063 * parameter (see igb_param.c)
4064 * NOTE: This function is called only when operating in a multiqueue
4065 * receive environment.
6eb5a7f1 4066 **/
047e0030 4067static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4068{
047e0030 4069 int new_val = q_vector->itr_val;
6eb5a7f1 4070 int avg_wire_size = 0;
047e0030 4071 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4072 unsigned int packets;
9d5c8243 4073
6eb5a7f1
AD		 4074 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4075 * ints/sec - ITR timer value of 120 ticks.
4076 */
4077 if (adapter->link_speed != SPEED_1000) {
0ba82994 4078 new_val = IGB_4K_ITR;
6eb5a7f1 4079 goto set_itr_val;
9d5c8243 4080 }
047e0030 4081
0ba82994
AD		 4082 packets = q_vector->rx.total_packets;
4083 if (packets)
4084 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4085
0ba82994
AD		 4086 packets = q_vector->tx.total_packets;
4087 if (packets)
4088 avg_wire_size = max_t(u32, avg_wire_size,
4089 q_vector->tx.total_bytes / packets);
047e0030
AD		 4090
4091 /* if avg_wire_size isn't set no work was done */
4092 if (!avg_wire_size)
4093 goto clear_counts;
9d5c8243 4094
6eb5a7f1
AD		 4095 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4096 avg_wire_size += 24;
4097
4098 /* Don't starve jumbo frames */
4099 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4100
6eb5a7f1
AD		 4101 /* Give a little boost to mid-size frames */
4102 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4103 new_val = avg_wire_size / 3;
4104 else
4105 new_val = avg_wire_size / 2;
9d5c8243 4106
0ba82994
AD		 4107 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4108 if (new_val < IGB_20K_ITR &&
4109 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4110 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4111 new_val = IGB_20K_ITR;
abe1c363 4112
6eb5a7f1 4113set_itr_val:
047e0030
AD		 4114 if (new_val != q_vector->itr_val) {
4115 q_vector->itr_val = new_val;
4116 q_vector->set_itr = 1;
9d5c8243 4117 }
6eb5a7f1 4118clear_counts:
0ba82994
AD		 4119 q_vector->rx.total_bytes = 0;
4120 q_vector->rx.total_packets = 0;
4121 q_vector->tx.total_bytes = 0;
4122 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4123}
4124
4125/**
b980ac18
JK		 4126 * igb_update_itr - update the dynamic ITR value based on statistics
4127 * @q_vector: pointer to q_vector
4128 * @ring_container: ring info to update the itr for
4129 *
4130 * Stores a new ITR value based on packets and byte
4131 * counts during the last interrupt. The advantage of per interrupt
4132 * computation is faster updates and more accurate ITR for the current
4133 * traffic pattern. Constants in this function were computed
4134 * based on theoretical maximum wire speed and thresholds were set based
4135 * on testing data as well as attempting to minimize response time
4136 * while increasing bulk throughput.
4137 * this functionality is controlled by the InterruptThrottleRate module
4138 * parameter (see igb_param.c)
4139 * NOTE: These calculations are only valid when operating in a single-
4140 * queue environment.
9d5c8243 4141 **/
0ba82994
AD		 4142static void igb_update_itr(struct igb_q_vector *q_vector,
4143 struct igb_ring_container *ring_container)
9d5c8243 4144{
0ba82994
AD		 4145 unsigned int packets = ring_container->total_packets;
4146 unsigned int bytes = ring_container->total_bytes;
4147 u8 itrval = ring_container->itr;
9d5c8243 4148
0ba82994 4149 /* no packets, exit with status unchanged */
9d5c8243 4150 if (packets == 0)
0ba82994 4151 return;
9d5c8243 4152
0ba82994 4153 switch (itrval) {
9d5c8243
AK		 4154 case lowest_latency:
4155 /* handle TSO and jumbo frames */
4156 if (bytes/packets > 8000)
0ba82994 4157 itrval = bulk_latency;
9d5c8243 4158 else if ((packets < 5) && (bytes > 512))
0ba82994 4159 itrval = low_latency;
9d5c8243
AK		 4160 break;
4161 case low_latency: /* 50 usec aka 20000 ints/s */
4162 if (bytes > 10000) {
4163 /* this if handles the TSO accounting */
4164 if (bytes/packets > 8000) {
0ba82994 4165 itrval = bulk_latency;
9d5c8243 4166 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4167 itrval = bulk_latency;
9d5c8243 4168 } else if ((packets > 35)) {
0ba82994 4169 itrval = lowest_latency;
9d5c8243
AK		 4170 }
4171 } else if (bytes/packets > 2000) {
0ba82994 4172 itrval = bulk_latency;
9d5c8243 4173 } else if (packets <= 2 && bytes < 512) {
0ba82994 4174 itrval = lowest_latency;
9d5c8243
AK		 4175 }
4176 break;
4177 case bulk_latency: /* 250 usec aka 4000 ints/s */
4178 if (bytes > 25000) {
4179 if (packets > 35)
0ba82994 4180 itrval = low_latency;
1e5c3d21 4181 } else if (bytes < 1500) {
0ba82994 4182 itrval = low_latency;
9d5c8243
AK		 4183 }
4184 break;
4185 }
4186
0ba82994
AD		 4187 /* clear work counters since we have the values we need */
4188 ring_container->total_bytes = 0;
4189 ring_container->total_packets = 0;
4190
4191 /* write updated itr to ring container */
4192 ring_container->itr = itrval;
9d5c8243
AK		 4193}
4194
0ba82994 4195static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4196{
0ba82994 4197 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4198 u32 new_itr = q_vector->itr_val;
0ba82994 4199 u8 current_itr = 0;
9d5c8243
AK		 4200
4201 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4202 if (adapter->link_speed != SPEED_1000) {
4203 current_itr = 0;
0ba82994 4204 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4205 goto set_itr_now;
4206 }
4207
0ba82994
AD		 4208 igb_update_itr(q_vector, &q_vector->tx);
4209 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4210
0ba82994 4211 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4212
6eb5a7f1 4213 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4214 if (current_itr == lowest_latency &&
4215 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4216 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4217 current_itr = low_latency;
4218
9d5c8243
AK		 4219 switch (current_itr) {
4220 /* counts and packets in update_itr are dependent on these numbers */
4221 case lowest_latency:
0ba82994 4222 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4223 break;
4224 case low_latency:
0ba82994 4225 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4226 break;
4227 case bulk_latency:
0ba82994 4228 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4229 break;
4230 default:
4231 break;
4232 }
4233
4234set_itr_now:
047e0030 4235 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4236 /* this attempts to bias the interrupt rate towards Bulk
4237 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4238 * increasing
4239 */
047e0030 4240 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4241 max((new_itr * q_vector->itr_val) /
4242 (new_itr + (q_vector->itr_val >> 2)),
4243 new_itr) : new_itr;
9d5c8243
AK		 4244 /* Don't write the value here; it resets the adapter's
4245 * internal timer, and causes us to delay far longer than
4246 * we should between interrupts. Instead, we write the ITR
4247 * value at the beginning of the next interrupt so the timing
4248 * ends up being correct.
4249 */
047e0030
AD		 4250 q_vector->itr_val = new_itr;
4251 q_vector->set_itr = 1;
9d5c8243 4252 }
9d5c8243
AK		 4253}
4254
c50b52a0
SH		 4255static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4256 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4257{
4258 struct e1000_adv_tx_context_desc *context_desc;
4259 u16 i = tx_ring->next_to_use;
4260
4261 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4262
4263 i++;
4264 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4265
4266 /* set bits to identify this as an advanced context descriptor */
4267 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4268
4269 /* For 82575, context index must be unique per ring. */
866cff06 4270 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4271 mss_l4len_idx |= tx_ring->reg_idx << 4;
4272
4273 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4274 context_desc->seqnum_seed = 0;
4275 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4276 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4277}
4278
7af40ad9
AD		 4279static int igb_tso(struct igb_ring *tx_ring,
4280 struct igb_tx_buffer *first,
4281 u8 *hdr_len)
9d5c8243 4282{
7af40ad9 4283 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4284 u32 vlan_macip_lens, type_tucmd;
4285 u32 mss_l4len_idx, l4len;
4286
ed6aa105
AD		 4287 if (skb->ip_summed != CHECKSUM_PARTIAL)
4288 return 0;
4289
7d13a7d0
AD		 4290 if (!skb_is_gso(skb))
4291 return 0;
9d5c8243
AK		 4292
4293 if (skb_header_cloned(skb)) {
7af40ad9 4294 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4295 if (err)
4296 return err;
4297 }
4298
7d13a7d0
AD		 4299 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4300 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4301
7af40ad9 4302 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4303 struct iphdr *iph = ip_hdr(skb);
4304 iph->tot_len = 0;
4305 iph->check = 0;
4306 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4307 iph->daddr, 0,
4308 IPPROTO_TCP,
4309 0);
7d13a7d0 4310 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4311 first->tx_flags |= IGB_TX_FLAGS_TSO |
4312 IGB_TX_FLAGS_CSUM |
4313 IGB_TX_FLAGS_IPV4;
8e1e8a47 4314 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4315 ipv6_hdr(skb)->payload_len = 0;
4316 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4317 &ipv6_hdr(skb)->daddr,
4318 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4319 first->tx_flags |= IGB_TX_FLAGS_TSO |
4320 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4321 }
4322
7af40ad9 4323 /* compute header lengths */
7d13a7d0
AD		 4324 l4len = tcp_hdrlen(skb);
4325 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4326
7af40ad9
AD		 4327 /* update gso size and bytecount with header size */
4328 first->gso_segs = skb_shinfo(skb)->gso_segs;
4329 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4330
9d5c8243 4331 /* MSS L4LEN IDX */
7d13a7d0
AD		 4332 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4333 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4334
7d13a7d0
AD		 4335 /* VLAN MACLEN IPLEN */
4336 vlan_macip_lens = skb_network_header_len(skb);
4337 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4338 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4339
7d13a7d0 4340 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4341
7d13a7d0 4342 return 1;
9d5c8243
AK		 4343}
4344
7af40ad9 4345static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4346{
7af40ad9 4347 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4348 u32 vlan_macip_lens = 0;
4349 u32 mss_l4len_idx = 0;
4350 u32 type_tucmd = 0;
9d5c8243 4351
7d13a7d0 4352 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4353 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4354 return;
7d13a7d0
AD		 4355 } else {
4356 u8 l4_hdr = 0;
7af40ad9 4357 switch (first->protocol) {
7d13a7d0
AD		 4358 case __constant_htons(ETH_P_IP):
4359 vlan_macip_lens |= skb_network_header_len(skb);
4360 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4361 l4_hdr = ip_hdr(skb)->protocol;
4362 break;
4363 case __constant_htons(ETH_P_IPV6):
4364 vlan_macip_lens |= skb_network_header_len(skb);
4365 l4_hdr = ipv6_hdr(skb)->nexthdr;
4366 break;
4367 default:
4368 if (unlikely(net_ratelimit())) {
4369 dev_warn(tx_ring->dev,
b980ac18
JK		 4370 "partial checksum but proto=%x!\n",
4371 first->protocol);
fa4a7ef3 4372 }
7d13a7d0
AD		 4373 break;
4374 }
fa4a7ef3 4375
7d13a7d0
AD		 4376 switch (l4_hdr) {
4377 case IPPROTO_TCP:
4378 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4379 mss_l4len_idx = tcp_hdrlen(skb) <<
4380 E1000_ADVTXD_L4LEN_SHIFT;
4381 break;
4382 case IPPROTO_SCTP:
4383 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4384 mss_l4len_idx = sizeof(struct sctphdr) <<
4385 E1000_ADVTXD_L4LEN_SHIFT;
4386 break;
4387 case IPPROTO_UDP:
4388 mss_l4len_idx = sizeof(struct udphdr) <<
4389 E1000_ADVTXD_L4LEN_SHIFT;
4390 break;
4391 default:
4392 if (unlikely(net_ratelimit())) {
4393 dev_warn(tx_ring->dev,
b980ac18
JK		 4394 "partial checksum but l4 proto=%x!\n",
4395 l4_hdr);
44b0cda3 4396 }
7d13a7d0 4397 break;
9d5c8243 4398 }
7af40ad9
AD		 4399
4400 /* update TX checksum flag */
4401 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4402 }
9d5c8243 4403
7d13a7d0 4404 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4405 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4406
7d13a7d0 4407 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4408}
4409
1d9daf45
AD		 4410#define IGB_SET_FLAG(_input, _flag, _result) \
4411 ((_flag <= _result) ? \
4412 ((u32)(_input & _flag) * (_result / _flag)) : \
4413 ((u32)(_input & _flag) / (_flag / _result)))
4414
4415static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4416{
4417 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4418 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4419 E1000_ADVTXD_DCMD_DEXT |
4420 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4421
4422 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4423 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4424 (E1000_ADVTXD_DCMD_VLE));
4425
4426 /* set segmentation bits for TSO */
4427 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4428 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4429
4430 /* set timestamp bit if present */
1d9daf45
AD		 4431 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4432 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4433
1d9daf45
AD		 4434 /* insert frame checksum */
4435 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4436
4437 return cmd_type;
4438}
4439
7af40ad9
AD		 4440static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4441 union e1000_adv_tx_desc *tx_desc,
4442 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4443{
4444 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4445
1d9daf45
AD		 4446 /* 82575 requires a unique index per ring */
4447 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4448 olinfo_status |= tx_ring->reg_idx << 4;
4449
4450 /* insert L4 checksum */
1d9daf45
AD		 4451 olinfo_status |= IGB_SET_FLAG(tx_flags,
4452 IGB_TX_FLAGS_CSUM,
4453 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4454
1d9daf45
AD		 4455 /* insert IPv4 checksum */
4456 olinfo_status |= IGB_SET_FLAG(tx_flags,
4457 IGB_TX_FLAGS_IPV4,
4458 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4459
7af40ad9 4460 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4461}
4462
7af40ad9
AD		 4463static void igb_tx_map(struct igb_ring *tx_ring,
4464 struct igb_tx_buffer *first,
ebe42d16 4465 const u8 hdr_len)
9d5c8243 4466{
7af40ad9 4467 struct sk_buff *skb = first->skb;
c9f14bf3 4468 struct igb_tx_buffer *tx_buffer;
ebe42d16 4469 union e1000_adv_tx_desc *tx_desc;
80d0759e 4470 struct skb_frag_struct *frag;
ebe42d16 4471 dma_addr_t dma;
80d0759e 4472 unsigned int data_len, size;
7af40ad9 4473 u32 tx_flags = first->tx_flags;
1d9daf45 4474 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4475 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4476
4477 tx_desc = IGB_TX_DESC(tx_ring, i);
4478
80d0759e
AD		 4479 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4480
4481 size = skb_headlen(skb);
4482 data_len = skb->data_len;
ebe42d16
AD		 4483
4484 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4485
80d0759e
AD		 4486 tx_buffer = first;
4487
4488 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4489 if (dma_mapping_error(tx_ring->dev, dma))
4490 goto dma_error;
4491
4492 /* record length, and DMA address */
4493 dma_unmap_len_set(tx_buffer, len, size);
4494 dma_unmap_addr_set(tx_buffer, dma, dma);
4495
4496 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4497
ebe42d16
AD		 4498 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4499 tx_desc->read.cmd_type_len =
1d9daf45 4500 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4501
4502 i++;
4503 tx_desc++;
4504 if (i == tx_ring->count) {
4505 tx_desc = IGB_TX_DESC(tx_ring, 0);
4506 i = 0;
4507 }
80d0759e 4508 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4509
4510 dma += IGB_MAX_DATA_PER_TXD;
4511 size -= IGB_MAX_DATA_PER_TXD;
4512
ebe42d16
AD		 4513 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4514 }
4515
4516 if (likely(!data_len))
4517 break;
2bbfebe2 4518
1d9daf45 4519 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4520
65689fef 4521 i++;
ebe42d16
AD		 4522 tx_desc++;
4523 if (i == tx_ring->count) {
4524 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4525 i = 0;
ebe42d16 4526 }
80d0759e 4527 tx_desc->read.olinfo_status = 0;
65689fef 4528
9e903e08 4529 size = skb_frag_size(frag);
ebe42d16
AD		 4530 data_len -= size;
4531
4532 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4533 size, DMA_TO_DEVICE);
6366ad33 4534
c9f14bf3 4535 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4536 }
4537
ebe42d16 4538 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4539 cmd_type |= size | IGB_TXD_DCMD;
4540 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4541
80d0759e
AD		 4542 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4543
8542db05
AD		 4544 /* set the timestamp */
4545 first->time_stamp = jiffies;
4546
b980ac18 4547 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4548 * are new descriptors to fetch. (Only applicable for weak-ordered
4549 * memory model archs, such as IA-64).
4550 *
4551 * We also need this memory barrier to make certain all of the
4552 * status bits have been updated before next_to_watch is written.
4553 */
4554 wmb();
4555
8542db05 4556 /* set next_to_watch value indicating a packet is present */
ebe42d16 4557 first->next_to_watch = tx_desc;
9d5c8243 4558
ebe42d16
AD		 4559 i++;
4560 if (i == tx_ring->count)
4561 i = 0;
6366ad33 4562
ebe42d16 4563 tx_ring->next_to_use = i;
6366ad33 4564
ebe42d16 4565 writel(i, tx_ring->tail);
6366ad33 4566
ebe42d16 4567 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4568 * at a time, it synchronizes IO on IA64/Altix systems
4569 */
ebe42d16
AD		 4570 mmiowb();
4571
4572 return;
4573
4574dma_error:
4575 dev_err(tx_ring->dev, "TX DMA map failed\n");
4576
4577 /* clear dma mappings for failed tx_buffer_info map */
4578 for (;;) {
c9f14bf3
AD		 4579 tx_buffer = &tx_ring->tx_buffer_info[i];
4580 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4581 if (tx_buffer == first)
ebe42d16 4582 break;
a77ff709
NN		 4583 if (i == 0)
4584 i = tx_ring->count;
6366ad33 4585 i--;
6366ad33
AD		 4586 }
4587
9d5c8243 4588 tx_ring->next_to_use = i;
9d5c8243
AK		 4589}
4590
6ad4edfc 4591static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4592{
e694e964
AD		 4593 struct net_device *netdev = tx_ring->netdev;
4594
661086df 4595 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4596
9d5c8243
AK		 4597 /* Herbert's original patch had:
4598 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4599 * but since that doesn't exist yet, just open code it.
4600 */
9d5c8243
AK		 4601 smp_mb();
4602
4603 /* We need to check again in a case another CPU has just
b980ac18
JK		 4604 * made room available.
4605 */
c493ea45 4606 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4607 return -EBUSY;
4608
4609 /* A reprieve! */
661086df 4610 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4611
4612 u64_stats_update_begin(&tx_ring->tx_syncp2);
4613 tx_ring->tx_stats.restart_queue2++;
4614 u64_stats_update_end(&tx_ring->tx_syncp2);
4615
9d5c8243
AK		 4616 return 0;
4617}
4618
6ad4edfc 4619static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4620{
c493ea45 4621 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4622 return 0;
e694e964 4623 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4624}
4625
cd392f5c
AD		 4626netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4627 struct igb_ring *tx_ring)
9d5c8243 4628{
8542db05 4629 struct igb_tx_buffer *first;
ebe42d16 4630 int tso;
91d4ee33 4631 u32 tx_flags = 0;
21ba6fe1 4632 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4633 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4634 u8 hdr_len = 0;
9d5c8243 4635
21ba6fe1
AD		 4636 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4637 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4638 * + 2 desc gap to keep tail from touching head,
9d5c8243 4639 * + 1 desc for context descriptor,
21ba6fe1
AD		 4640 * otherwise try next time
4641 */
4642 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4643 unsigned short f;
4644 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4645 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4646 } else {
4647 count += skb_shinfo(skb)->nr_frags;
4648 }
4649
4650 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4651 /* this is a hard error */
9d5c8243
AK		 4652 return NETDEV_TX_BUSY;
4653 }
33af6bcc 4654
7af40ad9
AD		 4655 /* record the location of the first descriptor for this packet */
4656 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4657 first->skb = skb;
4658 first->bytecount = skb->len;
4659 first->gso_segs = 1;
4660
b66e2397
MV		 4661 skb_tx_timestamp(skb);
4662
b646c22e
AD		 4663 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4664 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4665
b646c22e
AD		 4666 if (!(adapter->ptp_tx_skb)) {
4667 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4668 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4669
4670 adapter->ptp_tx_skb = skb_get(skb);
4671 adapter->ptp_tx_start = jiffies;
4672 if (adapter->hw.mac.type == e1000_82576)
4673 schedule_work(&adapter->ptp_tx_work);
4674 }
33af6bcc 4675 }
9d5c8243 4676
eab6d18d 4677 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4678 tx_flags |= IGB_TX_FLAGS_VLAN;
4679 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4680 }
4681
7af40ad9
AD		 4682 /* record initial flags and protocol */
4683 first->tx_flags = tx_flags;
4684 first->protocol = protocol;
cdfd01fc 4685
7af40ad9
AD		 4686 tso = igb_tso(tx_ring, first, &hdr_len);
4687 if (tso < 0)
7d13a7d0 4688 goto out_drop;
7af40ad9
AD		 4689 else if (!tso)
4690 igb_tx_csum(tx_ring, first);
9d5c8243 4691
7af40ad9 4692 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4693
4694 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4695 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4696
9d5c8243 4697 return NETDEV_TX_OK;
7d13a7d0
AD		 4698
4699out_drop:
7af40ad9
AD		 4700 igb_unmap_and_free_tx_resource(tx_ring, first);
4701
7d13a7d0 4702 return NETDEV_TX_OK;
9d5c8243
AK		 4703}
4704
1cc3bd87
AD		 4705static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4706 struct sk_buff *skb)
4707{
4708 unsigned int r_idx = skb->queue_mapping;
4709
4710 if (r_idx >= adapter->num_tx_queues)
4711 r_idx = r_idx % adapter->num_tx_queues;
4712
4713 return adapter->tx_ring[r_idx];
4714}
4715
cd392f5c
AD		 4716static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4717 struct net_device *netdev)
9d5c8243
AK		 4718{
4719 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4720
4721 if (test_bit(__IGB_DOWN, &adapter->state)) {
4722 dev_kfree_skb_any(skb);
4723 return NETDEV_TX_OK;
4724 }
4725
4726 if (skb->len <= 0) {
4727 dev_kfree_skb_any(skb);
4728 return NETDEV_TX_OK;
4729 }
4730
b980ac18 4731 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4732 * in order to meet this minimum size requirement.
4733 */
ea5ceeab
TD		 4734 if (unlikely(skb->len < 17)) {
4735 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4736 return NETDEV_TX_OK;
4737 skb->len = 17;
ea5ceeab 4738 skb_set_tail_pointer(skb, 17);
1cc3bd87 4739 }
9d5c8243 4740
1cc3bd87 4741 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4742}
4743
4744/**
b980ac18
JK		 4745 * igb_tx_timeout - Respond to a Tx Hang
4746 * @netdev: network interface device structure
9d5c8243
AK		 4747 **/
4748static void igb_tx_timeout(struct net_device *netdev)
4749{
4750 struct igb_adapter *adapter = netdev_priv(netdev);
4751 struct e1000_hw *hw = &adapter->hw;
4752
4753 /* Do the reset outside of interrupt context */
4754 adapter->tx_timeout_count++;
f7ba205e 4755
06218a8d 4756 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4757 hw->dev_spec._82575.global_device_reset = true;
4758
9d5c8243 4759 schedule_work(&adapter->reset_task);
265de409
AD		 4760 wr32(E1000_EICS,
4761 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4762}
4763
4764static void igb_reset_task(struct work_struct *work)
4765{
4766 struct igb_adapter *adapter;
4767 adapter = container_of(work, struct igb_adapter, reset_task);
4768
c97ec42a
TI		 4769 igb_dump(adapter);
4770 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4771 igb_reinit_locked(adapter);
4772}
4773
4774/**
b980ac18
JK		 4775 * igb_get_stats64 - Get System Network Statistics
4776 * @netdev: network interface device structure
4777 * @stats: rtnl_link_stats64 pointer
9d5c8243 4778 **/
12dcd86b 4779static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4780 struct rtnl_link_stats64 *stats)
9d5c8243 4781{
12dcd86b
ED		 4782 struct igb_adapter *adapter = netdev_priv(netdev);
4783
4784 spin_lock(&adapter->stats64_lock);
4785 igb_update_stats(adapter, &adapter->stats64);
4786 memcpy(stats, &adapter->stats64, sizeof(*stats));
4787 spin_unlock(&adapter->stats64_lock);
4788
4789 return stats;
9d5c8243
AK		 4790}
4791
4792/**
b980ac18
JK		 4793 * igb_change_mtu - Change the Maximum Transfer Unit
4794 * @netdev: network interface device structure
4795 * @new_mtu: new value for maximum frame size
9d5c8243 4796 *
b980ac18 4797 * Returns 0 on success, negative on failure
9d5c8243
AK		 4798 **/
4799static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4800{
4801 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4802 struct pci_dev *pdev = adapter->pdev;
153285f9 4803 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4804
c809d227 4805 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4806 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4807 return -EINVAL;
4808 }
4809
153285f9 4810#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4811 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4812 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4813 return -EINVAL;
4814 }
4815
2ccd994c
AD		 4816 /* adjust max frame to be at least the size of a standard frame */
4817 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4818 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4819
9d5c8243
AK		 4820 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4821 msleep(1);
73cd78f1 4822
9d5c8243
AK		 4823 /* igb_down has a dependency on max_frame_size */
4824 adapter->max_frame_size = max_frame;
559e9c49 4825
4c844851
AD		 4826 if (netif_running(netdev))
4827 igb_down(adapter);
9d5c8243 4828
090b1795 4829 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4830 netdev->mtu, new_mtu);
4831 netdev->mtu = new_mtu;
4832
4833 if (netif_running(netdev))
4834 igb_up(adapter);
4835 else
4836 igb_reset(adapter);
4837
4838 clear_bit(__IGB_RESETTING, &adapter->state);
4839
4840 return 0;
4841}
4842
4843/**
b980ac18
JK		 4844 * igb_update_stats - Update the board statistics counters
4845 * @adapter: board private structure
9d5c8243 4846 **/
12dcd86b
ED		 4847void igb_update_stats(struct igb_adapter *adapter,
4848 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4849{
4850 struct e1000_hw *hw = &adapter->hw;
4851 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4852 u32 reg, mpc;
9d5c8243 4853 u16 phy_tmp;
3f9c0164
AD		 4854 int i;
4855 u64 bytes, packets;
12dcd86b
ED		 4856 unsigned int start;
4857 u64 _bytes, _packets;
9d5c8243
AK		 4858
4859#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4860
b980ac18 4861 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4862 * connection is down.
4863 */
4864 if (adapter->link_speed == 0)
4865 return;
4866 if (pci_channel_offline(pdev))
4867 return;
4868
3f9c0164
AD		 4869 bytes = 0;
4870 packets = 0;
7f90128e
AA		 4871
4872 rcu_read_lock();
3f9c0164 4873 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4874 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4875 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4876
ae1c07a6
AD		 4877 if (rqdpc) {
4878 ring->rx_stats.drops += rqdpc;
4879 net_stats->rx_fifo_errors += rqdpc;
4880 }
12dcd86b
ED		 4881
4882 do {
4883 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4884 _bytes = ring->rx_stats.bytes;
4885 _packets = ring->rx_stats.packets;
4886 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4887 bytes += _bytes;
4888 packets += _packets;
3f9c0164
AD		 4889 }
4890
128e45eb
AD		 4891 net_stats->rx_bytes = bytes;
4892 net_stats->rx_packets = packets;
3f9c0164
AD		 4893
4894 bytes = 0;
4895 packets = 0;
4896 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4897 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4898 do {
4899 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4900 _bytes = ring->tx_stats.bytes;
4901 _packets = ring->tx_stats.packets;
4902 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4903 bytes += _bytes;
4904 packets += _packets;
3f9c0164 4905 }
128e45eb
AD		 4906 net_stats->tx_bytes = bytes;
4907 net_stats->tx_packets = packets;
7f90128e 4908 rcu_read_unlock();
3f9c0164
AD		 4909
4910 /* read stats registers */
9d5c8243
AK		 4911 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4912 adapter->stats.gprc += rd32(E1000_GPRC);
4913 adapter->stats.gorc += rd32(E1000_GORCL);
4914 rd32(E1000_GORCH); /* clear GORCL */
4915 adapter->stats.bprc += rd32(E1000_BPRC);
4916 adapter->stats.mprc += rd32(E1000_MPRC);
4917 adapter->stats.roc += rd32(E1000_ROC);
4918
4919 adapter->stats.prc64 += rd32(E1000_PRC64);
4920 adapter->stats.prc127 += rd32(E1000_PRC127);
4921 adapter->stats.prc255 += rd32(E1000_PRC255);
4922 adapter->stats.prc511 += rd32(E1000_PRC511);
4923 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4924 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4925 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4926 adapter->stats.sec += rd32(E1000_SEC);
4927
fa3d9a6d
MW		 4928 mpc = rd32(E1000_MPC);
4929 adapter->stats.mpc += mpc;
4930 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4931 adapter->stats.scc += rd32(E1000_SCC);
4932 adapter->stats.ecol += rd32(E1000_ECOL);
4933 adapter->stats.mcc += rd32(E1000_MCC);
4934 adapter->stats.latecol += rd32(E1000_LATECOL);
4935 adapter->stats.dc += rd32(E1000_DC);
4936 adapter->stats.rlec += rd32(E1000_RLEC);
4937 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4938 adapter->stats.xontxc += rd32(E1000_XONTXC);
4939 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4940 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4941 adapter->stats.fcruc += rd32(E1000_FCRUC);
4942 adapter->stats.gptc += rd32(E1000_GPTC);
4943 adapter->stats.gotc += rd32(E1000_GOTCL);
4944 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4945 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4946 adapter->stats.ruc += rd32(E1000_RUC);
4947 adapter->stats.rfc += rd32(E1000_RFC);
4948 adapter->stats.rjc += rd32(E1000_RJC);
4949 adapter->stats.tor += rd32(E1000_TORH);
4950 adapter->stats.tot += rd32(E1000_TOTH);
4951 adapter->stats.tpr += rd32(E1000_TPR);
4952
4953 adapter->stats.ptc64 += rd32(E1000_PTC64);
4954 adapter->stats.ptc127 += rd32(E1000_PTC127);
4955 adapter->stats.ptc255 += rd32(E1000_PTC255);
4956 adapter->stats.ptc511 += rd32(E1000_PTC511);
4957 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4958 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4959
4960 adapter->stats.mptc += rd32(E1000_MPTC);
4961 adapter->stats.bptc += rd32(E1000_BPTC);
4962
2d0b0f69
NN		 4963 adapter->stats.tpt += rd32(E1000_TPT);
4964 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4965
4966 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4967 /* read internal phy specific stats */
4968 reg = rd32(E1000_CTRL_EXT);
4969 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4970 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4971
4972 /* this stat has invalid values on i210/i211 */
4973 if ((hw->mac.type != e1000_i210) &&
4974 (hw->mac.type != e1000_i211))
4975 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4976 }
4977
9d5c8243
AK		 4978 adapter->stats.tsctc += rd32(E1000_TSCTC);
4979 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4980
4981 adapter->stats.iac += rd32(E1000_IAC);
4982 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4983 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4984 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4985 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4986 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4987 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4988 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4989 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4990
4991 /* Fill out the OS statistics structure */
128e45eb
AD		 4992 net_stats->multicast = adapter->stats.mprc;
4993 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4994
4995 /* Rx Errors */
4996
4997 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 4998 * our own version based on RUC and ROC
4999 */
128e45eb 5000 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5001 adapter->stats.crcerrs + adapter->stats.algnerrc +
5002 adapter->stats.ruc + adapter->stats.roc +
5003 adapter->stats.cexterr;
128e45eb
AD		 5004 net_stats->rx_length_errors = adapter->stats.ruc +
5005 adapter->stats.roc;
5006 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5007 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5008 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5009
5010 /* Tx Errors */
128e45eb
AD		 5011 net_stats->tx_errors = adapter->stats.ecol +
5012 adapter->stats.latecol;
5013 net_stats->tx_aborted_errors = adapter->stats.ecol;
5014 net_stats->tx_window_errors = adapter->stats.latecol;
5015 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5016
5017 /* Tx Dropped needs to be maintained elsewhere */
5018
5019 /* Phy Stats */
5020 if (hw->phy.media_type == e1000_media_type_copper) {
5021 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5022 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5023 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5024 adapter->phy_stats.idle_errors += phy_tmp;
5025 }
5026 }
5027
5028 /* Management Stats */
5029 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5030 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5031 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5032
5033 /* OS2BMC Stats */
5034 reg = rd32(E1000_MANC);
5035 if (reg & E1000_MANC_EN_BMC2OS) {
5036 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5037 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5038 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5039 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5040 }
9d5c8243
AK		 5041}
5042
9d5c8243
AK		 5043static irqreturn_t igb_msix_other(int irq, void *data)
5044{
047e0030 5045 struct igb_adapter *adapter = data;
9d5c8243 5046 struct e1000_hw *hw = &adapter->hw;
844290e5 5047 u32 icr = rd32(E1000_ICR);
844290e5 5048 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5049
7f081d40
AD		 5050 if (icr & E1000_ICR_DRSTA)
5051 schedule_work(&adapter->reset_task);
5052
047e0030 5053 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5054 /* HW is reporting DMA is out of sync */
5055 adapter->stats.doosync++;
13800469
GR		 5056 /* The DMA Out of Sync is also indication of a spoof event
5057 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5058 * see if it is really a spoof event.
5059 */
13800469 5060 igb_check_wvbr(adapter);
dda0e083 5061 }
eebbbdba 5062
4ae196df
AD		 5063 /* Check for a mailbox event */
5064 if (icr & E1000_ICR_VMMB)
5065 igb_msg_task(adapter);
5066
5067 if (icr & E1000_ICR_LSC) {
5068 hw->mac.get_link_status = 1;
5069 /* guard against interrupt when we're going down */
5070 if (!test_bit(__IGB_DOWN, &adapter->state))
5071 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5072 }
5073
1f6e8178
MV		 5074 if (icr & E1000_ICR_TS) {
5075 u32 tsicr = rd32(E1000_TSICR);
5076
5077 if (tsicr & E1000_TSICR_TXTS) {
5078 /* acknowledge the interrupt */
5079 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5080 /* retrieve hardware timestamp */
5081 schedule_work(&adapter->ptp_tx_work);
5082 }
5083 }
1f6e8178 5084
844290e5 5085 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5086
5087 return IRQ_HANDLED;
5088}
5089
047e0030 5090static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5091{
26b39276 5092 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5093 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5094
047e0030
AD		 5095 if (!q_vector->set_itr)
5096 return;
73cd78f1 5097
047e0030
AD		 5098 if (!itr_val)
5099 itr_val = 0x4;
661086df 5100
26b39276
AD		 5101 if (adapter->hw.mac.type == e1000_82575)
5102 itr_val |= itr_val << 16;
661086df 5103 else
0ba82994 5104 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5105
047e0030
AD		 5106 writel(itr_val, q_vector->itr_register);
5107 q_vector->set_itr = 0;
6eb5a7f1
AD		 5108}
5109
047e0030 5110static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5111{
047e0030 5112 struct igb_q_vector *q_vector = data;
9d5c8243 5113
047e0030
AD		 5114 /* Write the ITR value calculated from the previous interrupt. */
5115 igb_write_itr(q_vector);
9d5c8243 5116
047e0030 5117 napi_schedule(&q_vector->napi);
844290e5 5118
047e0030 5119 return IRQ_HANDLED;
fe4506b6
JC		 5120}
5121
421e02f0 5122#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5123static void igb_update_tx_dca(struct igb_adapter *adapter,
5124 struct igb_ring *tx_ring,
5125 int cpu)
5126{
5127 struct e1000_hw *hw = &adapter->hw;
5128 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5129
5130 if (hw->mac.type != e1000_82575)
5131 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5132
b980ac18 5133 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5134 * DCA is enabled. This is due to a known issue in some chipsets
5135 * which will cause the DCA tag to be cleared.
5136 */
5137 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5138 E1000_DCA_TXCTRL_DATA_RRO_EN |
5139 E1000_DCA_TXCTRL_DESC_DCA_EN;
5140
5141 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5142}
5143
5144static void igb_update_rx_dca(struct igb_adapter *adapter,
5145 struct igb_ring *rx_ring,
5146 int cpu)
5147{
5148 struct e1000_hw *hw = &adapter->hw;
5149 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5150
5151 if (hw->mac.type != e1000_82575)
5152 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5153
b980ac18 5154 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5155 * DCA is enabled. This is due to a known issue in some chipsets
5156 * which will cause the DCA tag to be cleared.
5157 */
5158 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5159 E1000_DCA_RXCTRL_DESC_DCA_EN;
5160
5161 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5162}
5163
047e0030 5164static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5165{
047e0030 5166 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5167 int cpu = get_cpu();
fe4506b6 5168
047e0030
AD		 5169 if (q_vector->cpu == cpu)
5170 goto out_no_update;
5171
6a05004a
AD		 5172 if (q_vector->tx.ring)
5173 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5174
5175 if (q_vector->rx.ring)
5176 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5177
047e0030
AD		 5178 q_vector->cpu = cpu;
5179out_no_update:
fe4506b6
JC		 5180 put_cpu();
5181}
5182
5183static void igb_setup_dca(struct igb_adapter *adapter)
5184{
7e0e99ef 5185 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5186 int i;
5187
7dfc16fa 5188 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5189 return;
5190
7e0e99ef
AD		 5191 /* Always use CB2 mode, difference is masked in the CB driver. */
5192 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5193
047e0030 5194 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5195 adapter->q_vector[i]->cpu = -1;
5196 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5197 }
5198}
5199
5200static int __igb_notify_dca(struct device *dev, void *data)
5201{
5202 struct net_device *netdev = dev_get_drvdata(dev);
5203 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5204 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5205 struct e1000_hw *hw = &adapter->hw;
5206 unsigned long event = *(unsigned long *)data;
5207
5208 switch (event) {
5209 case DCA_PROVIDER_ADD:
5210 /* if already enabled, don't do it again */
7dfc16fa 5211 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5212 break;
fe4506b6 5213 if (dca_add_requester(dev) == 0) {
bbd98fe4 5214 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5215 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5216 igb_setup_dca(adapter);
5217 break;
5218 }
5219 /* Fall Through since DCA is disabled. */
5220 case DCA_PROVIDER_REMOVE:
7dfc16fa 5221 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5222 /* without this a class_device is left
b980ac18
JK		 5223 * hanging around in the sysfs model
5224 */
fe4506b6 5225 dca_remove_requester(dev);
090b1795 5226 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5227 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5228 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5229 }
5230 break;
5231 }
bbd98fe4 5232
fe4506b6 5233 return 0;
9d5c8243
AK		 5234}
5235
fe4506b6 5236static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5237 void *p)
fe4506b6
JC		 5238{
5239 int ret_val;
5240
5241 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5242 __igb_notify_dca);
fe4506b6
JC		 5243
5244 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5245}
421e02f0 5246#endif /* CONFIG_IGB_DCA */
9d5c8243 5247
0224d663
GR		 5248#ifdef CONFIG_PCI_IOV
5249static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5250{
5251 unsigned char mac_addr[ETH_ALEN];
0224d663 5252
5ac6f91d 5253 eth_zero_addr(mac_addr);
0224d663
GR		 5254 igb_set_vf_mac(adapter, vf, mac_addr);
5255
70ea4783
LL		 5256 /* By default spoof check is enabled for all VFs */
5257 adapter->vf_data[vf].spoofchk_enabled = true;
5258
f557147c 5259 return 0;
0224d663
GR		 5260}
5261
0224d663 5262#endif
4ae196df
AD		 5263static void igb_ping_all_vfs(struct igb_adapter *adapter)
5264{
5265 struct e1000_hw *hw = &adapter->hw;
5266 u32 ping;
5267 int i;
5268
5269 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5270 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5271 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5272 ping |= E1000_VT_MSGTYPE_CTS;
5273 igb_write_mbx(hw, &ping, 1, i);
5274 }
5275}
5276
7d5753f0
AD		 5277static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5278{
5279 struct e1000_hw *hw = &adapter->hw;
5280 u32 vmolr = rd32(E1000_VMOLR(vf));
5281 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5282
d85b9004 5283 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5284 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5285 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5286
5287 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5288 vmolr |= E1000_VMOLR_MPME;
d85b9004 5289 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5290 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5291 } else {
b980ac18 5292 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5293 * flag we need to write the hashes to the MTA as this step
5294 * was previously skipped
5295 */
5296 if (vf_data->num_vf_mc_hashes > 30) {
5297 vmolr |= E1000_VMOLR_MPME;
5298 } else if (vf_data->num_vf_mc_hashes) {
5299 int j;
5300 vmolr |= E1000_VMOLR_ROMPE;
5301 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5302 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5303 }
5304 }
5305
5306 wr32(E1000_VMOLR(vf), vmolr);
5307
5308 /* there are flags left unprocessed, likely not supported */
5309 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5310 return -EINVAL;
5311
5312 return 0;
7d5753f0
AD		 5313}
5314
4ae196df
AD		 5315static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5316 u32 *msgbuf, u32 vf)
5317{
5318 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5319 u16 *hash_list = (u16 *)&msgbuf[1];
5320 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5321 int i;
5322
7d5753f0 5323 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5324 * to this VF for later use to restore when the PF multi cast
5325 * list changes
5326 */
5327 vf_data->num_vf_mc_hashes = n;
5328
7d5753f0
AD		 5329 /* only up to 30 hash values supported */
5330 if (n > 30)
5331 n = 30;
5332
5333 /* store the hashes for later use */
4ae196df 5334 for (i = 0; i < n; i++)
a419aef8 5335 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5336
5337 /* Flush and reset the mta with the new values */
ff41f8dc 5338 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5339
5340 return 0;
5341}
5342
5343static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5344{
5345 struct e1000_hw *hw = &adapter->hw;
5346 struct vf_data_storage *vf_data;
5347 int i, j;
5348
5349 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5350 u32 vmolr = rd32(E1000_VMOLR(i));
5351 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5352
4ae196df 5353 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5354
5355 if ((vf_data->num_vf_mc_hashes > 30) ||
5356 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5357 vmolr |= E1000_VMOLR_MPME;
5358 } else if (vf_data->num_vf_mc_hashes) {
5359 vmolr |= E1000_VMOLR_ROMPE;
5360 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5361 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5362 }
5363 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5364 }
5365}
5366
5367static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5368{
5369 struct e1000_hw *hw = &adapter->hw;
5370 u32 pool_mask, reg, vid;
5371 int i;
5372
5373 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5374
5375 /* Find the vlan filter for this id */
5376 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5377 reg = rd32(E1000_VLVF(i));
5378
5379 /* remove the vf from the pool */
5380 reg &= ~pool_mask;
5381
5382 /* if pool is empty then remove entry from vfta */
5383 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5384 (reg & E1000_VLVF_VLANID_ENABLE)) {
5385 reg = 0;
5386 vid = reg & E1000_VLVF_VLANID_MASK;
5387 igb_vfta_set(hw, vid, false);
5388 }
5389
5390 wr32(E1000_VLVF(i), reg);
5391 }
ae641bdc
AD		 5392
5393 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5394}
5395
5396static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5397{
5398 struct e1000_hw *hw = &adapter->hw;
5399 u32 reg, i;
5400
51466239
AD		 5401 /* The vlvf table only exists on 82576 hardware and newer */
5402 if (hw->mac.type < e1000_82576)
5403 return -1;
5404
5405 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5406 if (!adapter->vfs_allocated_count)
5407 return -1;
5408
5409 /* Find the vlan filter for this id */
5410 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5411 reg = rd32(E1000_VLVF(i));
5412 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5413 vid == (reg & E1000_VLVF_VLANID_MASK))
5414 break;
5415 }
5416
5417 if (add) {
5418 if (i == E1000_VLVF_ARRAY_SIZE) {
5419 /* Did not find a matching VLAN ID entry that was
5420 * enabled. Search for a free filter entry, i.e.
5421 * one without the enable bit set
5422 */
5423 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5424 reg = rd32(E1000_VLVF(i));
5425 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5426 break;
5427 }
5428 }
5429 if (i < E1000_VLVF_ARRAY_SIZE) {
5430 /* Found an enabled/available entry */
5431 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5432
5433 /* if !enabled we need to set this up in vfta */
5434 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5435 /* add VID to filter table */
5436 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5437 reg |= E1000_VLVF_VLANID_ENABLE;
5438 }
cad6d05f
AD		 5439 reg &= ~E1000_VLVF_VLANID_MASK;
5440 reg |= vid;
4ae196df 5441 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5442
5443 /* do not modify RLPML for PF devices */
5444 if (vf >= adapter->vfs_allocated_count)
5445 return 0;
5446
5447 if (!adapter->vf_data[vf].vlans_enabled) {
5448 u32 size;
5449 reg = rd32(E1000_VMOLR(vf));
5450 size = reg & E1000_VMOLR_RLPML_MASK;
5451 size += 4;
5452 reg &= ~E1000_VMOLR_RLPML_MASK;
5453 reg |= size;
5454 wr32(E1000_VMOLR(vf), reg);
5455 }
ae641bdc 5456
51466239 5457 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5458 }
5459 } else {
5460 if (i < E1000_VLVF_ARRAY_SIZE) {
5461 /* remove vf from the pool */
5462 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5463 /* if pool is empty then remove entry from vfta */
5464 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5465 reg = 0;
5466 igb_vfta_set(hw, vid, false);
5467 }
5468 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5469
5470 /* do not modify RLPML for PF devices */
5471 if (vf >= adapter->vfs_allocated_count)
5472 return 0;
5473
5474 adapter->vf_data[vf].vlans_enabled--;
5475 if (!adapter->vf_data[vf].vlans_enabled) {
5476 u32 size;
5477 reg = rd32(E1000_VMOLR(vf));
5478 size = reg & E1000_VMOLR_RLPML_MASK;
5479 size -= 4;
5480 reg &= ~E1000_VMOLR_RLPML_MASK;
5481 reg |= size;
5482 wr32(E1000_VMOLR(vf), reg);
5483 }
4ae196df
AD		 5484 }
5485 }
8151d294
WM		 5486 return 0;
5487}
5488
5489static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5490{
5491 struct e1000_hw *hw = &adapter->hw;
5492
5493 if (vid)
5494 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5495 else
5496 wr32(E1000_VMVIR(vf), 0);
5497}
5498
5499static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5500 int vf, u16 vlan, u8 qos)
5501{
5502 int err = 0;
5503 struct igb_adapter *adapter = netdev_priv(netdev);
5504
5505 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5506 return -EINVAL;
5507 if (vlan || qos) {
5508 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5509 if (err)
5510 goto out;
5511 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5512 igb_set_vmolr(adapter, vf, !vlan);
5513 adapter->vf_data[vf].pf_vlan = vlan;
5514 adapter->vf_data[vf].pf_qos = qos;
5515 dev_info(&adapter->pdev->dev,
5516 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5517 if (test_bit(__IGB_DOWN, &adapter->state)) {
5518 dev_warn(&adapter->pdev->dev,
b980ac18 5519 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5520 dev_warn(&adapter->pdev->dev,
b980ac18 5521 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5522 }
5523 } else {
5524 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5525 false, vf);
8151d294
WM		 5526 igb_set_vmvir(adapter, vlan, vf);
5527 igb_set_vmolr(adapter, vf, true);
5528 adapter->vf_data[vf].pf_vlan = 0;
5529 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5530 }
8151d294 5531out:
b980ac18 5532 return err;
4ae196df
AD		 5533}
5534
6f3dc319
GR		 5535static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5536{
5537 struct e1000_hw *hw = &adapter->hw;
5538 int i;
5539 u32 reg;
5540
5541 /* Find the vlan filter for this id */
5542 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5543 reg = rd32(E1000_VLVF(i));
5544 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5545 vid == (reg & E1000_VLVF_VLANID_MASK))
5546 break;
5547 }
5548
5549 if (i >= E1000_VLVF_ARRAY_SIZE)
5550 i = -1;
5551
5552 return i;
5553}
5554
4ae196df
AD		 5555static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5556{
6f3dc319 5557 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5558 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5559 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5560 int err = 0;
4ae196df 5561
6f3dc319
GR		 5562 /* If in promiscuous mode we need to make sure the PF also has
5563 * the VLAN filter set.
5564 */
5565 if (add && (adapter->netdev->flags & IFF_PROMISC))
5566 err = igb_vlvf_set(adapter, vid, add,
5567 adapter->vfs_allocated_count);
5568 if (err)
5569 goto out;
5570
5571 err = igb_vlvf_set(adapter, vid, add, vf);
5572
5573 if (err)
5574 goto out;
5575
5576 /* Go through all the checks to see if the VLAN filter should
5577 * be wiped completely.
5578 */
5579 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5580 u32 vlvf, bits;
5581
5582 int regndx = igb_find_vlvf_entry(adapter, vid);
5583 if (regndx < 0)
5584 goto out;
5585 /* See if any other pools are set for this VLAN filter
5586 * entry other than the PF.
5587 */
5588 vlvf = bits = rd32(E1000_VLVF(regndx));
5589 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5590 adapter->vfs_allocated_count);
5591 /* If the filter was removed then ensure PF pool bit
5592 * is cleared if the PF only added itself to the pool
5593 * because the PF is in promiscuous mode.
5594 */
5595 if ((vlvf & VLAN_VID_MASK) == vid &&
5596 !test_bit(vid, adapter->active_vlans) &&
5597 !bits)
5598 igb_vlvf_set(adapter, vid, add,
5599 adapter->vfs_allocated_count);
5600 }
5601
5602out:
5603 return err;
4ae196df
AD		 5604}
5605
f2ca0dbe 5606static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5607{
8fa7e0f7
GR		 5608 /* clear flags - except flag that indicates PF has set the MAC */
5609 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5610 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5611
5612 /* reset offloads to defaults */
8151d294 5613 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5614
5615 /* reset vlans for device */
5616 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5617 if (adapter->vf_data[vf].pf_vlan)
5618 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5619 adapter->vf_data[vf].pf_vlan,
5620 adapter->vf_data[vf].pf_qos);
5621 else
5622 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5623
5624 /* reset multicast table array for vf */
5625 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5626
5627 /* Flush and reset the mta with the new values */
ff41f8dc 5628 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5629}
5630
f2ca0dbe
AD		 5631static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5632{
5633 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5634
5ac6f91d 5635 /* clear mac address as we were hotplug removed/added */
8151d294 5636 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5637 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5638
5639 /* process remaining reset events */
5640 igb_vf_reset(adapter, vf);
5641}
5642
5643static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5644{
5645 struct e1000_hw *hw = &adapter->hw;
5646 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5647 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5648 u32 reg, msgbuf[3];
5649 u8 *addr = (u8 *)(&msgbuf[1]);
5650
5651 /* process all the same items cleared in a function level reset */
f2ca0dbe 5652 igb_vf_reset(adapter, vf);
4ae196df
AD		 5653
5654 /* set vf mac address */
26ad9178 5655 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5656
5657 /* enable transmit and receive for vf */
5658 reg = rd32(E1000_VFTE);
5659 wr32(E1000_VFTE, reg | (1 << vf));
5660 reg = rd32(E1000_VFRE);
5661 wr32(E1000_VFRE, reg | (1 << vf));
5662
8fa7e0f7 5663 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5664
5665 /* reply to reset with ack and vf mac address */
5666 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5667 memcpy(addr, vf_mac, 6);
5668 igb_write_mbx(hw, msgbuf, 3, vf);
5669}
5670
5671static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5672{
b980ac18 5673 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5674 * starting at the second 32 bit word of the msg array
5675 */
f2ca0dbe
AD		 5676 unsigned char *addr = (char *)&msg[1];
5677 int err = -1;
4ae196df 5678
f2ca0dbe
AD		 5679 if (is_valid_ether_addr(addr))
5680 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5681
f2ca0dbe 5682 return err;
4ae196df
AD		 5683}
5684
5685static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5686{
5687 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5688 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5689 u32 msg = E1000_VT_MSGTYPE_NACK;
5690
5691 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5692 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5693 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5694 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5695 vf_data->last_nack = jiffies;
4ae196df
AD		 5696 }
5697}
5698
f2ca0dbe 5699static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5700{
f2ca0dbe
AD		 5701 struct pci_dev *pdev = adapter->pdev;
5702 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5703 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5704 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5705 s32 retval;
5706
f2ca0dbe 5707 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5708
fef45f4c
AD		 5709 if (retval) {
5710 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5711 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5712 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5713 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5714 return;
5715 goto out;
5716 }
4ae196df
AD		 5717
5718 /* this is a message we already processed, do nothing */
5719 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5720 return;
4ae196df 5721
b980ac18 5722 /* until the vf completes a reset it should not be
4ae196df
AD		 5723 * allowed to start any configuration.
5724 */
4ae196df
AD		 5725 if (msgbuf[0] == E1000_VF_RESET) {
5726 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5727 return;
4ae196df
AD		 5728 }
5729
f2ca0dbe 5730 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5731 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5732 return;
5733 retval = -1;
5734 goto out;
4ae196df
AD		 5735 }
5736
5737 switch ((msgbuf[0] & 0xFFFF)) {
5738 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5739 retval = -EINVAL;
5740 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5741 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5742 else
5743 dev_warn(&pdev->dev,
b980ac18
JK		 5744 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5745 vf);
4ae196df 5746 break;
7d5753f0
AD		 5747 case E1000_VF_SET_PROMISC:
5748 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5749 break;
4ae196df
AD		 5750 case E1000_VF_SET_MULTICAST:
5751 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5752 break;
5753 case E1000_VF_SET_LPE:
5754 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5755 break;
5756 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5757 retval = -1;
5758 if (vf_data->pf_vlan)
5759 dev_warn(&pdev->dev,
b980ac18
JK		 5760 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5761 vf);
8151d294
WM		 5762 else
5763 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5764 break;
5765 default:
090b1795 5766 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5767 retval = -1;
5768 break;
5769 }
5770
fef45f4c
AD		 5771 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5772out:
4ae196df
AD		 5773 /* notify the VF of the results of what it sent us */
5774 if (retval)
5775 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5776 else
5777 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5778
4ae196df 5779 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5780}
4ae196df 5781
f2ca0dbe
AD		 5782static void igb_msg_task(struct igb_adapter *adapter)
5783{
5784 struct e1000_hw *hw = &adapter->hw;
5785 u32 vf;
5786
5787 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5788 /* process any reset requests */
5789 if (!igb_check_for_rst(hw, vf))
5790 igb_vf_reset_event(adapter, vf);
5791
5792 /* process any messages pending */
5793 if (!igb_check_for_msg(hw, vf))
5794 igb_rcv_msg_from_vf(adapter, vf);
5795
5796 /* process any acks */
5797 if (!igb_check_for_ack(hw, vf))
5798 igb_rcv_ack_from_vf(adapter, vf);
5799 }
4ae196df
AD		 5800}
5801
68d480c4
AD		 5802/**
5803 * igb_set_uta - Set unicast filter table address
5804 * @adapter: board private structure
5805 *
5806 * The unicast table address is a register array of 32-bit registers.
5807 * The table is meant to be used in a way similar to how the MTA is used
5808 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5809 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5810 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5811 **/
5812static void igb_set_uta(struct igb_adapter *adapter)
5813{
5814 struct e1000_hw *hw = &adapter->hw;
5815 int i;
5816
5817 /* The UTA table only exists on 82576 hardware and newer */
5818 if (hw->mac.type < e1000_82576)
5819 return;
5820
5821 /* we only need to do this if VMDq is enabled */
5822 if (!adapter->vfs_allocated_count)
5823 return;
5824
5825 for (i = 0; i < hw->mac.uta_reg_count; i++)
5826 array_wr32(E1000_UTA, i, ~0);
5827}
5828
9d5c8243 5829/**
b980ac18
JK		 5830 * igb_intr_msi - Interrupt Handler
5831 * @irq: interrupt number
5832 * @data: pointer to a network interface device structure
9d5c8243
AK		 5833 **/
5834static irqreturn_t igb_intr_msi(int irq, void *data)
5835{
047e0030
AD		 5836 struct igb_adapter *adapter = data;
5837 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5838 struct e1000_hw *hw = &adapter->hw;
5839 /* read ICR disables interrupts using IAM */
5840 u32 icr = rd32(E1000_ICR);
5841
047e0030 5842 igb_write_itr(q_vector);
9d5c8243 5843
7f081d40
AD		 5844 if (icr & E1000_ICR_DRSTA)
5845 schedule_work(&adapter->reset_task);
5846
047e0030 5847 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5848 /* HW is reporting DMA is out of sync */
5849 adapter->stats.doosync++;
5850 }
5851
9d5c8243
AK		 5852 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5853 hw->mac.get_link_status = 1;
5854 if (!test_bit(__IGB_DOWN, &adapter->state))
5855 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5856 }
5857
1f6e8178
MV		 5858 if (icr & E1000_ICR_TS) {
5859 u32 tsicr = rd32(E1000_TSICR);
5860
5861 if (tsicr & E1000_TSICR_TXTS) {
5862 /* acknowledge the interrupt */
5863 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5864 /* retrieve hardware timestamp */
5865 schedule_work(&adapter->ptp_tx_work);
5866 }
5867 }
1f6e8178 5868
047e0030 5869 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5870
5871 return IRQ_HANDLED;
5872}
5873
5874/**
b980ac18
JK		 5875 * igb_intr - Legacy Interrupt Handler
5876 * @irq: interrupt number
5877 * @data: pointer to a network interface device structure
9d5c8243
AK		 5878 **/
5879static irqreturn_t igb_intr(int irq, void *data)
5880{
047e0030
AD		 5881 struct igb_adapter *adapter = data;
5882 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5883 struct e1000_hw *hw = &adapter->hw;
5884 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5885 * need for the IMC write
5886 */
9d5c8243 5887 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5888
5889 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5890 * not set, then the adapter didn't send an interrupt
5891 */
9d5c8243
AK		 5892 if (!(icr & E1000_ICR_INT_ASSERTED))
5893 return IRQ_NONE;
5894
0ba82994
AD		 5895 igb_write_itr(q_vector);
5896
7f081d40
AD		 5897 if (icr & E1000_ICR_DRSTA)
5898 schedule_work(&adapter->reset_task);
5899
047e0030 5900 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5901 /* HW is reporting DMA is out of sync */
5902 adapter->stats.doosync++;
5903 }
5904
9d5c8243
AK		 5905 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5906 hw->mac.get_link_status = 1;
5907 /* guard against interrupt when we're going down */
5908 if (!test_bit(__IGB_DOWN, &adapter->state))
5909 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5910 }
5911
1f6e8178
MV		 5912 if (icr & E1000_ICR_TS) {
5913 u32 tsicr = rd32(E1000_TSICR);
5914
5915 if (tsicr & E1000_TSICR_TXTS) {
5916 /* acknowledge the interrupt */
5917 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5918 /* retrieve hardware timestamp */
5919 schedule_work(&adapter->ptp_tx_work);
5920 }
5921 }
1f6e8178 5922
047e0030 5923 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5924
5925 return IRQ_HANDLED;
5926}
5927
c50b52a0 5928static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5929{
047e0030 5930 struct igb_adapter *adapter = q_vector->adapter;
46544258 5931 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5932
0ba82994
AD		 5933 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5934 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5935 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5936 igb_set_itr(q_vector);
46544258 5937 else
047e0030 5938 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5939 }
5940
46544258
AD		 5941 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5942 if (adapter->msix_entries)
047e0030 5943 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5944 else
5945 igb_irq_enable(adapter);
5946 }
9d5c8243
AK		 5947}
5948
46544258 5949/**
b980ac18
JK		 5950 * igb_poll - NAPI Rx polling callback
5951 * @napi: napi polling structure
5952 * @budget: count of how many packets we should handle
46544258
AD		 5953 **/
5954static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5955{
047e0030 5956 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 5957 struct igb_q_vector,
5958 napi);
16eb8815 5959 bool clean_complete = true;
9d5c8243 5960
421e02f0 5961#ifdef CONFIG_IGB_DCA
047e0030
AD		 5962 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5963 igb_update_dca(q_vector);
fe4506b6 5964#endif
0ba82994 5965 if (q_vector->tx.ring)
13fde97a 5966 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5967
0ba82994 5968 if (q_vector->rx.ring)
cd392f5c 5969 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5970
16eb8815
AD		 5971 /* If all work not completed, return budget and keep polling */
5972 if (!clean_complete)
5973 return budget;
46544258 5974
9d5c8243 5975 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5976 napi_complete(napi);
5977 igb_ring_irq_enable(q_vector);
9d5c8243 5978
16eb8815 5979 return 0;
9d5c8243 5980}
6d8126f9 5981
9d5c8243 5982/**
b980ac18
JK		 5983 * igb_clean_tx_irq - Reclaim resources after transmit completes
5984 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5985 *
b980ac18 5986 * returns true if ring is completely cleaned
9d5c8243 5987 **/
047e0030 5988static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5989{
047e0030 5990 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5991 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5992 struct igb_tx_buffer *tx_buffer;
f4128785 5993 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5994 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5995 unsigned int budget = q_vector->tx.work_limit;
8542db05 5996 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5997
13fde97a
AD		 5998 if (test_bit(__IGB_DOWN, &adapter->state))
5999 return true;
0e014cb1 6000
06034649 6001 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6002 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6003 i -= tx_ring->count;
9d5c8243 6004
f4128785
AD		 6005 do {
6006 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6007
6008 /* if next_to_watch is not set then there is no work pending */
6009 if (!eop_desc)
6010 break;
13fde97a 6011
f4128785 6012 /* prevent any other reads prior to eop_desc */
70d289bc 6013 read_barrier_depends();
f4128785 6014
13fde97a
AD		 6015 /* if DD is not set pending work has not been completed */
6016 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6017 break;
6018
8542db05
AD		 6019 /* clear next_to_watch to prevent false hangs */
6020 tx_buffer->next_to_watch = NULL;
9d5c8243 6021
ebe42d16
AD		 6022 /* update the statistics for this packet */
6023 total_bytes += tx_buffer->bytecount;
6024 total_packets += tx_buffer->gso_segs;
13fde97a 6025
ebe42d16
AD		 6026 /* free the skb */
6027 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6028
ebe42d16
AD		 6029 /* unmap skb header data */
6030 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6031 dma_unmap_addr(tx_buffer, dma),
6032 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6033 DMA_TO_DEVICE);
6034
c9f14bf3
AD		 6035 /* clear tx_buffer data */
6036 tx_buffer->skb = NULL;
6037 dma_unmap_len_set(tx_buffer, len, 0);
6038
ebe42d16
AD		 6039 /* clear last DMA location and unmap remaining buffers */
6040 while (tx_desc != eop_desc) {
13fde97a
AD		 6041 tx_buffer++;
6042 tx_desc++;
9d5c8243 6043 i++;
8542db05
AD		 6044 if (unlikely(!i)) {
6045 i -= tx_ring->count;
06034649 6046 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6047 tx_desc = IGB_TX_DESC(tx_ring, 0);
6048 }
ebe42d16
AD		 6049
6050 /* unmap any remaining paged data */
c9f14bf3 6051 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6052 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6053 dma_unmap_addr(tx_buffer, dma),
6054 dma_unmap_len(tx_buffer, len),
ebe42d16 6055 DMA_TO_DEVICE);
c9f14bf3 6056 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6057 }
6058 }
6059
ebe42d16
AD		 6060 /* move us one more past the eop_desc for start of next pkt */
6061 tx_buffer++;
6062 tx_desc++;
6063 i++;
6064 if (unlikely(!i)) {
6065 i -= tx_ring->count;
6066 tx_buffer = tx_ring->tx_buffer_info;
6067 tx_desc = IGB_TX_DESC(tx_ring, 0);
6068 }
f4128785
AD		 6069
6070 /* issue prefetch for next Tx descriptor */
6071 prefetch(tx_desc);
6072
6073 /* update budget accounting */
6074 budget--;
6075 } while (likely(budget));
0e014cb1 6076
bdbc0631
ED		 6077 netdev_tx_completed_queue(txring_txq(tx_ring),
6078 total_packets, total_bytes);
8542db05 6079 i += tx_ring->count;
9d5c8243 6080 tx_ring->next_to_clean = i;
13fde97a
AD		 6081 u64_stats_update_begin(&tx_ring->tx_syncp);
6082 tx_ring->tx_stats.bytes += total_bytes;
6083 tx_ring->tx_stats.packets += total_packets;
6084 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6085 q_vector->tx.total_bytes += total_bytes;
6086 q_vector->tx.total_packets += total_packets;
9d5c8243 6087
6d095fa8 6088 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6089 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6090
9d5c8243 6091 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6092 * check with the clearing of time_stamp and movement of i
6093 */
6d095fa8 6094 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6095 if (tx_buffer->next_to_watch &&
8542db05 6096 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6097 (adapter->tx_timeout_factor * HZ)) &&
6098 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6099
9d5c8243 6100 /* detected Tx unit hang */
59d71989 6101 dev_err(tx_ring->dev,
9d5c8243 6102 "Detected Tx Unit Hang\n"
2d064c06 6103 " Tx Queue <%d>\n"
9d5c8243
AK		 6104 " TDH <%x>\n"
6105 " TDT <%x>\n"
6106 " next_to_use <%x>\n"
6107 " next_to_clean <%x>\n"
9d5c8243
AK		 6108 "buffer_info[next_to_clean]\n"
6109 " time_stamp <%lx>\n"
8542db05 6110 " next_to_watch <%p>\n"
9d5c8243
AK		 6111 " jiffies <%lx>\n"
6112 " desc.status <%x>\n",
2d064c06 6113 tx_ring->queue_index,
238ac817 6114 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6115 readl(tx_ring->tail),
9d5c8243
AK		 6116 tx_ring->next_to_use,
6117 tx_ring->next_to_clean,
8542db05 6118 tx_buffer->time_stamp,
f4128785 6119 tx_buffer->next_to_watch,
9d5c8243 6120 jiffies,
f4128785 6121 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6122 netif_stop_subqueue(tx_ring->netdev,
6123 tx_ring->queue_index);
6124
6125 /* we are about to reset, no point in enabling stuff */
6126 return true;
9d5c8243
AK		 6127 }
6128 }
13fde97a 6129
21ba6fe1 6130#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6131 if (unlikely(total_packets &&
b980ac18
JK		 6132 netif_carrier_ok(tx_ring->netdev) &&
6133 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6134 /* Make sure that anybody stopping the queue after this
6135 * sees the new next_to_clean.
6136 */
6137 smp_mb();
6138 if (__netif_subqueue_stopped(tx_ring->netdev,
6139 tx_ring->queue_index) &&
6140 !(test_bit(__IGB_DOWN, &adapter->state))) {
6141 netif_wake_subqueue(tx_ring->netdev,
6142 tx_ring->queue_index);
6143
6144 u64_stats_update_begin(&tx_ring->tx_syncp);
6145 tx_ring->tx_stats.restart_queue++;
6146 u64_stats_update_end(&tx_ring->tx_syncp);
6147 }
6148 }
6149
6150 return !!budget;
9d5c8243
AK		 6151}
6152
cbc8e55f 6153/**
b980ac18
JK		 6154 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6155 * @rx_ring: rx descriptor ring to store buffers on
6156 * @old_buff: donor buffer to have page reused
cbc8e55f 6157 *
b980ac18 6158 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6159 **/
6160static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6161 struct igb_rx_buffer *old_buff)
6162{
6163 struct igb_rx_buffer *new_buff;
6164 u16 nta = rx_ring->next_to_alloc;
6165
6166 new_buff = &rx_ring->rx_buffer_info[nta];
6167
6168 /* update, and store next to alloc */
6169 nta++;
6170 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6171
6172 /* transfer page from old buffer to new buffer */
6173 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6174
6175 /* sync the buffer for use by the device */
6176 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6177 old_buff->page_offset,
de78d1f9 6178 IGB_RX_BUFSZ,
cbc8e55f
AD		 6179 DMA_FROM_DEVICE);
6180}
6181
74e238ea
AD		 6182static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6183 struct page *page,
6184 unsigned int truesize)
6185{
6186 /* avoid re-using remote pages */
6187 if (unlikely(page_to_nid(page) != numa_node_id()))
6188 return false;
6189
6190#if (PAGE_SIZE < 8192)
6191 /* if we are only owner of page we can reuse it */
6192 if (unlikely(page_count(page) != 1))
6193 return false;
6194
6195 /* flip page offset to other buffer */
6196 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6197
6198 /* since we are the only owner of the page and we need to
6199 * increment it, just set the value to 2 in order to avoid
6200 * an unnecessary locked operation
6201 */
6202 atomic_set(&page->_count, 2);
6203#else
6204 /* move offset up to the next cache line */
6205 rx_buffer->page_offset += truesize;
6206
6207 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6208 return false;
6209
6210 /* bump ref count on page before it is given to the stack */
6211 get_page(page);
6212#endif
6213
6214 return true;
6215}
6216
cbc8e55f 6217/**
b980ac18
JK		 6218 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6219 * @rx_ring: rx descriptor ring to transact packets on
6220 * @rx_buffer: buffer containing page to add
6221 * @rx_desc: descriptor containing length of buffer written by hardware
6222 * @skb: sk_buff to place the data into
cbc8e55f 6223 *
b980ac18
JK		 6224 * This function will add the data contained in rx_buffer->page to the skb.
6225 * This is done either through a direct copy if the data in the buffer is
6226 * less than the skb header size, otherwise it will just attach the page as
6227 * a frag to the skb.
cbc8e55f 6228 *
b980ac18
JK		 6229 * The function will then update the page offset if necessary and return
6230 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6231 **/
6232static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6233 struct igb_rx_buffer *rx_buffer,
6234 union e1000_adv_rx_desc *rx_desc,
6235 struct sk_buff *skb)
6236{
6237 struct page *page = rx_buffer->page;
6238 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6239#if (PAGE_SIZE < 8192)
6240 unsigned int truesize = IGB_RX_BUFSZ;
6241#else
6242 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6243#endif
cbc8e55f
AD		 6244
6245 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6246 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6247
cbc8e55f
AD		 6248 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6249 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6250 va += IGB_TS_HDR_LEN;
6251 size -= IGB_TS_HDR_LEN;
6252 }
6253
cbc8e55f
AD		 6254 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6255
6256 /* we can reuse buffer as-is, just make sure it is local */
6257 if (likely(page_to_nid(page) == numa_node_id()))
6258 return true;
6259
6260 /* this page cannot be reused so discard it */
6261 put_page(page);
6262 return false;
6263 }
6264
6265 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6266 rx_buffer->page_offset, size, truesize);
cbc8e55f 6267
74e238ea
AD		 6268 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6269}
cbc8e55f 6270
2e334eee
AD		 6271static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6272 union e1000_adv_rx_desc *rx_desc,
6273 struct sk_buff *skb)
6274{
6275 struct igb_rx_buffer *rx_buffer;
6276 struct page *page;
6277
6278 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6279
2e334eee
AD		 6280 page = rx_buffer->page;
6281 prefetchw(page);
6282
6283 if (likely(!skb)) {
6284 void *page_addr = page_address(page) +
6285 rx_buffer->page_offset;
6286
6287 /* prefetch first cache line of first page */
6288 prefetch(page_addr);
6289#if L1_CACHE_BYTES < 128
6290 prefetch(page_addr + L1_CACHE_BYTES);
6291#endif
6292
6293 /* allocate a skb to store the frags */
6294 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6295 IGB_RX_HDR_LEN);
6296 if (unlikely(!skb)) {
6297 rx_ring->rx_stats.alloc_failed++;
6298 return NULL;
6299 }
6300
b980ac18 6301 /* we will be copying header into skb->data in
2e334eee
AD		 6302 * pskb_may_pull so it is in our interest to prefetch
6303 * it now to avoid a possible cache miss
6304 */
6305 prefetchw(skb->data);
6306 }
6307
6308 /* we are reusing so sync this buffer for CPU use */
6309 dma_sync_single_range_for_cpu(rx_ring->dev,
6310 rx_buffer->dma,
6311 rx_buffer->page_offset,
de78d1f9 6312 IGB_RX_BUFSZ,
2e334eee
AD		 6313 DMA_FROM_DEVICE);
6314
6315 /* pull page into skb */
6316 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6317 /* hand second half of page back to the ring */
6318 igb_reuse_rx_page(rx_ring, rx_buffer);
6319 } else {
6320 /* we are not reusing the buffer so unmap it */
6321 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6322 PAGE_SIZE, DMA_FROM_DEVICE);
6323 }
6324
6325 /* clear contents of rx_buffer */
6326 rx_buffer->page = NULL;
6327
6328 return skb;
6329}
6330
cd392f5c 6331static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6332 union e1000_adv_rx_desc *rx_desc,
6333 struct sk_buff *skb)
9d5c8243 6334{
bc8acf2c 6335 skb_checksum_none_assert(skb);
9d5c8243 6336
294e7d78 6337 /* Ignore Checksum bit is set */
3ceb90fd 6338 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6339 return;
6340
6341 /* Rx checksum disabled via ethtool */
6342 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6343 return;
85ad76b2 6344
9d5c8243 6345 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6346 if (igb_test_staterr(rx_desc,
6347 E1000_RXDEXT_STATERR_TCPE |
6348 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6349 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6350 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6351 * packets, (aka let the stack check the crc32c)
6352 */
866cff06
AD		 6353 if (!((skb->len == 60) &&
6354 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6355 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6356 ring->rx_stats.csum_err++;
12dcd86b
ED		 6357 u64_stats_update_end(&ring->rx_syncp);
6358 }
9d5c8243 6359 /* let the stack verify checksum errors */
9d5c8243
AK		 6360 return;
6361 }
6362 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6363 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6364 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6365 skb->ip_summed = CHECKSUM_UNNECESSARY;
6366
3ceb90fd
AD		 6367 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6368 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6369}
6370
077887c3
AD		 6371static inline void igb_rx_hash(struct igb_ring *ring,
6372 union e1000_adv_rx_desc *rx_desc,
6373 struct sk_buff *skb)
6374{
6375 if (ring->netdev->features & NETIF_F_RXHASH)
6376 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6377}
6378
2e334eee 6379/**
b980ac18
JK		 6380 * igb_is_non_eop - process handling of non-EOP buffers
6381 * @rx_ring: Rx ring being processed
6382 * @rx_desc: Rx descriptor for current buffer
6383 * @skb: current socket buffer containing buffer in progress
2e334eee 6384 *
b980ac18
JK		 6385 * This function updates next to clean. If the buffer is an EOP buffer
6386 * this function exits returning false, otherwise it will place the
6387 * sk_buff in the next buffer to be chained and return true indicating
6388 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6389 **/
6390static bool igb_is_non_eop(struct igb_ring *rx_ring,
6391 union e1000_adv_rx_desc *rx_desc)
6392{
6393 u32 ntc = rx_ring->next_to_clean + 1;
6394
6395 /* fetch, update, and store next to clean */
6396 ntc = (ntc < rx_ring->count) ? ntc : 0;
6397 rx_ring->next_to_clean = ntc;
6398
6399 prefetch(IGB_RX_DESC(rx_ring, ntc));
6400
6401 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6402 return false;
6403
6404 return true;
6405}
6406
1a1c225b 6407/**
b980ac18
JK		 6408 * igb_get_headlen - determine size of header for LRO/GRO
6409 * @data: pointer to the start of the headers
6410 * @max_len: total length of section to find headers in
1a1c225b 6411 *
b980ac18
JK		 6412 * This function is meant to determine the length of headers that will
6413 * be recognized by hardware for LRO, and GRO offloads. The main
6414 * motivation of doing this is to only perform one pull for IPv4 TCP
6415 * packets so that we can do basic things like calculating the gso_size
6416 * based on the average data per packet.
1a1c225b
AD		 6417 **/
6418static unsigned int igb_get_headlen(unsigned char *data,
6419 unsigned int max_len)
6420{
6421 union {
6422 unsigned char *network;
6423 /* l2 headers */
6424 struct ethhdr *eth;
6425 struct vlan_hdr *vlan;
6426 /* l3 headers */
6427 struct iphdr *ipv4;
6428 struct ipv6hdr *ipv6;
6429 } hdr;
6430 __be16 protocol;
6431 u8 nexthdr = 0; /* default to not TCP */
6432 u8 hlen;
6433
6434 /* this should never happen, but better safe than sorry */
6435 if (max_len < ETH_HLEN)
6436 return max_len;
6437
6438 /* initialize network frame pointer */
6439 hdr.network = data;
6440
6441 /* set first protocol and move network header forward */
6442 protocol = hdr.eth->h_proto;
6443 hdr.network += ETH_HLEN;
6444
6445 /* handle any vlan tag if present */
6446 if (protocol == __constant_htons(ETH_P_8021Q)) {
6447 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6448 return max_len;
6449
6450 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6451 hdr.network += VLAN_HLEN;
6452 }
6453
6454 /* handle L3 protocols */
6455 if (protocol == __constant_htons(ETH_P_IP)) {
6456 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6457 return max_len;
6458
6459 /* access ihl as a u8 to avoid unaligned access on ia64 */
6460 hlen = (hdr.network[0] & 0x0F) << 2;
6461
6462 /* verify hlen meets minimum size requirements */
6463 if (hlen < sizeof(struct iphdr))
6464 return hdr.network - data;
6465
f2fb4ab2 6466 /* record next protocol if header is present */
b9555f66 6467 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6468 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6469 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6470 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6471 return max_len;
6472
6473 /* record next protocol */
6474 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6475 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6476 } else {
6477 return hdr.network - data;
6478 }
6479
f2fb4ab2
AD		 6480 /* relocate pointer to start of L4 header */
6481 hdr.network += hlen;
6482
1a1c225b
AD		 6483 /* finally sort out TCP */
6484 if (nexthdr == IPPROTO_TCP) {
6485 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6486 return max_len;
6487
6488 /* access doff as a u8 to avoid unaligned access on ia64 */
6489 hlen = (hdr.network[12] & 0xF0) >> 2;
6490
6491 /* verify hlen meets minimum size requirements */
6492 if (hlen < sizeof(struct tcphdr))
6493 return hdr.network - data;
6494
6495 hdr.network += hlen;
6496 } else if (nexthdr == IPPROTO_UDP) {
6497 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6498 return max_len;
6499
6500 hdr.network += sizeof(struct udphdr);
6501 }
6502
b980ac18 6503 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6504 * data section of the packet and will be the end of the header.
6505 * If not then it probably represents the end of the last recognized
6506 * header.
6507 */
6508 if ((hdr.network - data) < max_len)
6509 return hdr.network - data;
6510 else
6511 return max_len;
6512}
6513
6514/**
b980ac18
JK		 6515 * igb_pull_tail - igb specific version of skb_pull_tail
6516 * @rx_ring: rx descriptor ring packet is being transacted on
6517 * @rx_desc: pointer to the EOP Rx descriptor
6518 * @skb: pointer to current skb being adjusted
1a1c225b 6519 *
b980ac18
JK		 6520 * This function is an igb specific version of __pskb_pull_tail. The
6521 * main difference between this version and the original function is that
6522 * this function can make several assumptions about the state of things
6523 * that allow for significant optimizations versus the standard function.
6524 * As a result we can do things like drop a frag and maintain an accurate
6525 * truesize for the skb.
1a1c225b
AD		 6526 */
6527static void igb_pull_tail(struct igb_ring *rx_ring,
6528 union e1000_adv_rx_desc *rx_desc,
6529 struct sk_buff *skb)
2d94d8ab 6530{
1a1c225b
AD		 6531 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6532 unsigned char *va;
6533 unsigned int pull_len;
6534
b980ac18 6535 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6536 * working with pages allocated out of the lomem pool per
6537 * alloc_page(GFP_ATOMIC)
2d94d8ab 6538 */
1a1c225b
AD		 6539 va = skb_frag_address(frag);
6540
1a1c225b
AD		 6541 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6542 /* retrieve timestamp from buffer */
6543 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6544
6545 /* update pointers to remove timestamp header */
6546 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6547 frag->page_offset += IGB_TS_HDR_LEN;
6548 skb->data_len -= IGB_TS_HDR_LEN;
6549 skb->len -= IGB_TS_HDR_LEN;
6550
6551 /* move va to start of packet data */
6552 va += IGB_TS_HDR_LEN;
6553 }
6554
b980ac18 6555 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6556 * 60 bytes if the skb->len is less than 60 for skb_pad.
6557 */
6558 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6559
6560 /* align pull length to size of long to optimize memcpy performance */
6561 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6562
6563 /* update all of the pointers */
6564 skb_frag_size_sub(frag, pull_len);
6565 frag->page_offset += pull_len;
6566 skb->data_len -= pull_len;
6567 skb->tail += pull_len;
6568}
6569
6570/**
b980ac18
JK		 6571 * igb_cleanup_headers - Correct corrupted or empty headers
6572 * @rx_ring: rx descriptor ring packet is being transacted on
6573 * @rx_desc: pointer to the EOP Rx descriptor
6574 * @skb: pointer to current skb being fixed
1a1c225b 6575 *
b980ac18
JK		 6576 * Address the case where we are pulling data in on pages only
6577 * and as such no data is present in the skb header.
1a1c225b 6578 *
b980ac18
JK		 6579 * In addition if skb is not at least 60 bytes we need to pad it so that
6580 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6581 *
b980ac18 6582 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6583 **/
6584static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6585 union e1000_adv_rx_desc *rx_desc,
6586 struct sk_buff *skb)
6587{
1a1c225b
AD		 6588 if (unlikely((igb_test_staterr(rx_desc,
6589 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6590 struct net_device *netdev = rx_ring->netdev;
6591 if (!(netdev->features & NETIF_F_RXALL)) {
6592 dev_kfree_skb_any(skb);
6593 return true;
6594 }
6595 }
6596
6597 /* place header in linear portion of buffer */
6598 if (skb_is_nonlinear(skb))
6599 igb_pull_tail(rx_ring, rx_desc, skb);
6600
6601 /* if skb_pad returns an error the skb was freed */
6602 if (unlikely(skb->len < 60)) {
6603 int pad_len = 60 - skb->len;
6604
6605 if (skb_pad(skb, pad_len))
6606 return true;
6607 __skb_put(skb, pad_len);
6608 }
6609
6610 return false;
2d94d8ab
AD		 6611}
6612
db2ee5bd 6613/**
b980ac18
JK		 6614 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6615 * @rx_ring: rx descriptor ring packet is being transacted on
6616 * @rx_desc: pointer to the EOP Rx descriptor
6617 * @skb: pointer to current skb being populated
db2ee5bd 6618 *
b980ac18
JK		 6619 * This function checks the ring, descriptor, and packet information in
6620 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6621 * other fields within the skb.
db2ee5bd
AD		 6622 **/
6623static void igb_process_skb_fields(struct igb_ring *rx_ring,
6624 union e1000_adv_rx_desc *rx_desc,
6625 struct sk_buff *skb)
6626{
6627 struct net_device *dev = rx_ring->netdev;
6628
6629 igb_rx_hash(rx_ring, rx_desc, skb);
6630
6631 igb_rx_checksum(rx_ring, rx_desc, skb);
6632
20a48412 6633 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6634
f646968f 6635 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6636 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6637 u16 vid;
6638 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6639 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6640 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6641 else
6642 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6643
86a9bad3 6644 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6645 }
6646
6647 skb_record_rx_queue(skb, rx_ring->queue_index);
6648
6649 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6650}
6651
2e334eee 6652static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6653{
0ba82994 6654 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6655 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6656 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6657 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6658
2e334eee
AD		 6659 do {
6660 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6661
2e334eee
AD		 6662 /* return some buffers to hardware, one at a time is too slow */
6663 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6664 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6665 cleaned_count = 0;
6666 }
bf36c1a0 6667
2e334eee 6668 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6669
2e334eee
AD		 6670 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6671 break;
9d5c8243 6672
74e238ea
AD		 6673 /* This memory barrier is needed to keep us from reading
6674 * any other fields out of the rx_desc until we know the
6675 * RXD_STAT_DD bit is set
6676 */
6677 rmb();
6678
2e334eee 6679 /* retrieve a buffer from the ring */
f9d40f6a 6680 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6681
2e334eee
AD		 6682 /* exit if we failed to retrieve a buffer */
6683 if (!skb)
6684 break;
1a1c225b 6685
2e334eee 6686 cleaned_count++;
1a1c225b 6687
2e334eee
AD		 6688 /* fetch next buffer in frame if non-eop */
6689 if (igb_is_non_eop(rx_ring, rx_desc))
6690 continue;
1a1c225b
AD		 6691
6692 /* verify the packet layout is correct */
6693 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6694 skb = NULL;
6695 continue;
9d5c8243 6696 }
9d5c8243 6697
db2ee5bd 6698 /* probably a little skewed due to removing CRC */
3ceb90fd 6699 total_bytes += skb->len;
3ceb90fd 6700
db2ee5bd
AD		 6701 /* populate checksum, timestamp, VLAN, and protocol */
6702 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6703
b2cb09b1 6704 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6705
1a1c225b
AD		 6706 /* reset skb pointer */
6707 skb = NULL;
6708
2e334eee
AD		 6709 /* update budget accounting */
6710 total_packets++;
6711 } while (likely(total_packets < budget));
bf36c1a0 6712
1a1c225b
AD		 6713 /* place incomplete frames back on ring for completion */
6714 rx_ring->skb = skb;
6715
12dcd86b 6716 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6717 rx_ring->rx_stats.packets += total_packets;
6718 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6719 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6720 q_vector->rx.total_packets += total_packets;
6721 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6722
6723 if (cleaned_count)
cd392f5c 6724 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6725
2e334eee 6726 return (total_packets < budget);
9d5c8243
AK		 6727}
6728
c023cd88 6729static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6730 struct igb_rx_buffer *bi)
c023cd88
AD		 6731{
6732 struct page *page = bi->page;
cbc8e55f 6733 dma_addr_t dma;
c023cd88 6734
cbc8e55f
AD		 6735 /* since we are recycling buffers we should seldom need to alloc */
6736 if (likely(page))
c023cd88
AD		 6737 return true;
6738
cbc8e55f
AD		 6739 /* alloc new page for storage */
6740 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6741 if (unlikely(!page)) {
6742 rx_ring->rx_stats.alloc_failed++;
6743 return false;
c023cd88
AD		 6744 }
6745
cbc8e55f
AD		 6746 /* map page for use */
6747 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6748
b980ac18 6749 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6750 * there isn't much point in holding memory we can't use
6751 */
1a1c225b 6752 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6753 __free_page(page);
6754
c023cd88
AD		 6755 rx_ring->rx_stats.alloc_failed++;
6756 return false;
6757 }
6758
1a1c225b 6759 bi->dma = dma;
cbc8e55f
AD		 6760 bi->page = page;
6761 bi->page_offset = 0;
1a1c225b 6762
c023cd88
AD		 6763 return true;
6764}
6765
9d5c8243 6766/**
b980ac18
JK		 6767 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6768 * @adapter: address of board private structure
9d5c8243 6769 **/
cd392f5c 6770void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6771{
9d5c8243 6772 union e1000_adv_rx_desc *rx_desc;
06034649 6773 struct igb_rx_buffer *bi;
c023cd88 6774 u16 i = rx_ring->next_to_use;
9d5c8243 6775
cbc8e55f
AD		 6776 /* nothing to do */
6777 if (!cleaned_count)
6778 return;
6779
60136906 6780 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6781 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6782 i -= rx_ring->count;
9d5c8243 6783
cbc8e55f 6784 do {
1a1c225b 6785 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6786 break;
9d5c8243 6787
b980ac18 6788 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6789 * because each write-back erases this info.
6790 */
f9d40f6a 6791 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6792
c023cd88
AD		 6793 rx_desc++;
6794 bi++;
9d5c8243 6795 i++;
c023cd88 6796 if (unlikely(!i)) {
60136906 6797 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6798 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6799 i -= rx_ring->count;
6800 }
6801
6802 /* clear the hdr_addr for the next_to_use descriptor */
6803 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6804
6805 cleaned_count--;
6806 } while (cleaned_count);
9d5c8243 6807
c023cd88
AD		 6808 i += rx_ring->count;
6809
9d5c8243 6810 if (rx_ring->next_to_use != i) {
cbc8e55f 6811 /* record the next descriptor to use */
9d5c8243 6812 rx_ring->next_to_use = i;
9d5c8243 6813
cbc8e55f
AD		 6814 /* update next to alloc since we have filled the ring */
6815 rx_ring->next_to_alloc = i;
6816
b980ac18 6817 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6818 * know there are new descriptors to fetch. (Only
6819 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6820 * such as IA-64).
6821 */
9d5c8243 6822 wmb();
fce99e34 6823 writel(i, rx_ring->tail);
9d5c8243
AK		 6824 }
6825}
6826
6827/**
6828 * igb_mii_ioctl -
6829 * @netdev:
6830 * @ifreq:
6831 * @cmd:
6832 **/
6833static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6834{
6835 struct igb_adapter *adapter = netdev_priv(netdev);
6836 struct mii_ioctl_data *data = if_mii(ifr);
6837
6838 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6839 return -EOPNOTSUPP;
6840
6841 switch (cmd) {
6842 case SIOCGMIIPHY:
6843 data->phy_id = adapter->hw.phy.addr;
6844 break;
6845 case SIOCGMIIREG:
f5f4cf08
AD		 6846 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6847 &data->val_out))
9d5c8243
AK		 6848 return -EIO;
6849 break;
6850 case SIOCSMIIREG:
6851 default:
6852 return -EOPNOTSUPP;
6853 }
6854 return 0;
6855}
6856
6857/**
6858 * igb_ioctl -
6859 * @netdev:
6860 * @ifreq:
6861 * @cmd:
6862 **/
6863static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6864{
6865 switch (cmd) {
6866 case SIOCGMIIPHY:
6867 case SIOCGMIIREG:
6868 case SIOCSMIIREG:
6869 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6870 case SIOCSHWTSTAMP:
a79f4f88 6871 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6872 default:
6873 return -EOPNOTSUPP;
6874 }
6875}
6876
009bc06e
AD		 6877s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6878{
6879 struct igb_adapter *adapter = hw->back;
009bc06e 6880
23d028cc 6881 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6882 return -E1000_ERR_CONFIG;
6883
009bc06e
AD		 6884 return 0;
6885}
6886
6887s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6888{
6889 struct igb_adapter *adapter = hw->back;
009bc06e 6890
23d028cc 6891 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6892 return -E1000_ERR_CONFIG;
6893
009bc06e
AD		 6894 return 0;
6895}
6896
c8f44aff 6897static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6898{
6899 struct igb_adapter *adapter = netdev_priv(netdev);
6900 struct e1000_hw *hw = &adapter->hw;
6901 u32 ctrl, rctl;
f646968f 6902 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6903
5faf030c 6904 if (enable) {
9d5c8243
AK		 6905 /* enable VLAN tag insert/strip */
6906 ctrl = rd32(E1000_CTRL);
6907 ctrl |= E1000_CTRL_VME;
6908 wr32(E1000_CTRL, ctrl);
6909
51466239 6910 /* Disable CFI check */
9d5c8243 6911 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6912 rctl &= ~E1000_RCTL_CFIEN;
6913 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6914 } else {
6915 /* disable VLAN tag insert/strip */
6916 ctrl = rd32(E1000_CTRL);
6917 ctrl &= ~E1000_CTRL_VME;
6918 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6919 }
6920
e1739522 6921 igb_rlpml_set(adapter);
9d5c8243
AK		 6922}
6923
80d5c368
PM		 6924static int igb_vlan_rx_add_vid(struct net_device *netdev,
6925 __be16 proto, u16 vid)
9d5c8243
AK		 6926{
6927 struct igb_adapter *adapter = netdev_priv(netdev);
6928 struct e1000_hw *hw = &adapter->hw;
4ae196df 6929 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6930
51466239
AD		 6931 /* attempt to add filter to vlvf array */
6932 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6933
51466239
AD		 6934 /* add the filter since PF can receive vlans w/o entry in vlvf */
6935 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6936
6937 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6938
6939 return 0;
9d5c8243
AK		 6940}
6941
80d5c368
PM		 6942static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6943 __be16 proto, u16 vid)
9d5c8243
AK		 6944{
6945 struct igb_adapter *adapter = netdev_priv(netdev);
6946 struct e1000_hw *hw = &adapter->hw;
4ae196df 6947 int pf_id = adapter->vfs_allocated_count;
51466239 6948 s32 err;
9d5c8243 6949
51466239
AD		 6950 /* remove vlan from VLVF table array */
6951 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6952
51466239
AD		 6953 /* if vid was not present in VLVF just remove it from table */
6954 if (err)
4ae196df 6955 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6956
6957 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6958
6959 return 0;
9d5c8243
AK		 6960}
6961
6962static void igb_restore_vlan(struct igb_adapter *adapter)
6963{
b2cb09b1 6964 u16 vid;
9d5c8243 6965
5faf030c
AD		 6966 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6967
b2cb09b1 6968 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 6969 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 6970}
6971
14ad2513 6972int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6973{
090b1795 6974 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6975 struct e1000_mac_info *mac = &adapter->hw.mac;
6976
6977 mac->autoneg = 0;
6978
14ad2513 6979 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 6980 * for the switch() below to work
6981 */
14ad2513
DD		 6982 if ((spd & 1) || (dplx & ~1))
6983 goto err_inval;
6984
f502ef7d
AA		 6985 /* Fiber NIC's only allow 1000 gbps Full duplex
6986 * and 100Mbps Full duplex for 100baseFx sfp
6987 */
6988 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
6989 switch (spd + dplx) {
6990 case SPEED_10 + DUPLEX_HALF:
6991 case SPEED_10 + DUPLEX_FULL:
6992 case SPEED_100 + DUPLEX_HALF:
6993 goto err_inval;
6994 default:
6995 break;
6996 }
6997 }
cd2638a8 6998
14ad2513 6999 switch (spd + dplx) {
9d5c8243
AK		 7000 case SPEED_10 + DUPLEX_HALF:
7001 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7002 break;
7003 case SPEED_10 + DUPLEX_FULL:
7004 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7005 break;
7006 case SPEED_100 + DUPLEX_HALF:
7007 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7008 break;
7009 case SPEED_100 + DUPLEX_FULL:
7010 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7011 break;
7012 case SPEED_1000 + DUPLEX_FULL:
7013 mac->autoneg = 1;
7014 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7015 break;
7016 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7017 default:
14ad2513 7018 goto err_inval;
9d5c8243 7019 }
8376dad0
JB		 7020
7021 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7022 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7023
9d5c8243 7024 return 0;
14ad2513
DD		 7025
7026err_inval:
7027 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7028 return -EINVAL;
9d5c8243
AK		 7029}
7030
749ab2cd
YZ		 7031static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7032 bool runtime)
9d5c8243
AK		 7033{
7034 struct net_device *netdev = pci_get_drvdata(pdev);
7035 struct igb_adapter *adapter = netdev_priv(netdev);
7036 struct e1000_hw *hw = &adapter->hw;
2d064c06 7037 u32 ctrl, rctl, status;
749ab2cd 7038 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7039#ifdef CONFIG_PM
7040 int retval = 0;
7041#endif
7042
7043 netif_device_detach(netdev);
7044
a88f10ec 7045 if (netif_running(netdev))
749ab2cd 7046 __igb_close(netdev, true);
a88f10ec 7047
047e0030 7048 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7049
7050#ifdef CONFIG_PM
7051 retval = pci_save_state(pdev);
7052 if (retval)
7053 return retval;
7054#endif
7055
7056 status = rd32(E1000_STATUS);
7057 if (status & E1000_STATUS_LU)
7058 wufc &= ~E1000_WUFC_LNKC;
7059
7060 if (wufc) {
7061 igb_setup_rctl(adapter);
ff41f8dc 7062 igb_set_rx_mode(netdev);
9d5c8243
AK		 7063
7064 /* turn on all-multi mode if wake on multicast is enabled */
7065 if (wufc & E1000_WUFC_MC) {
7066 rctl = rd32(E1000_RCTL);
7067 rctl |= E1000_RCTL_MPE;
7068 wr32(E1000_RCTL, rctl);
7069 }
7070
7071 ctrl = rd32(E1000_CTRL);
7072 /* advertise wake from D3Cold */
7073 #define E1000_CTRL_ADVD3WUC 0x00100000
7074 /* phy power management enable */
7075 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7076 ctrl |= E1000_CTRL_ADVD3WUC;
7077 wr32(E1000_CTRL, ctrl);
7078
9d5c8243 7079 /* Allow time for pending master requests to run */
330a6d6a 7080 igb_disable_pcie_master(hw);
9d5c8243
AK		 7081
7082 wr32(E1000_WUC, E1000_WUC_PME_EN);
7083 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7084 } else {
7085 wr32(E1000_WUC, 0);
7086 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7087 }
7088
3fe7c4c9
RW		 7089 *enable_wake = wufc || adapter->en_mng_pt;
7090 if (!*enable_wake)
88a268c1
NN		 7091 igb_power_down_link(adapter);
7092 else
7093 igb_power_up_link(adapter);
9d5c8243
AK		 7094
7095 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7096 * would have already happened in close and is redundant.
7097 */
9d5c8243
AK		 7098 igb_release_hw_control(adapter);
7099
7100 pci_disable_device(pdev);
7101
9d5c8243
AK		 7102 return 0;
7103}
7104
7105#ifdef CONFIG_PM
d9dd966d 7106#ifdef CONFIG_PM_SLEEP
749ab2cd 7107static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7108{
7109 int retval;
7110 bool wake;
749ab2cd 7111 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7112
749ab2cd 7113 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7114 if (retval)
7115 return retval;
7116
7117 if (wake) {
7118 pci_prepare_to_sleep(pdev);
7119 } else {
7120 pci_wake_from_d3(pdev, false);
7121 pci_set_power_state(pdev, PCI_D3hot);
7122 }
7123
7124 return 0;
7125}
d9dd966d 7126#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7127
749ab2cd 7128static int igb_resume(struct device *dev)
9d5c8243 7129{
749ab2cd 7130 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7131 struct net_device *netdev = pci_get_drvdata(pdev);
7132 struct igb_adapter *adapter = netdev_priv(netdev);
7133 struct e1000_hw *hw = &adapter->hw;
7134 u32 err;
7135
7136 pci_set_power_state(pdev, PCI_D0);
7137 pci_restore_state(pdev);
b94f2d77 7138 pci_save_state(pdev);
42bfd33a 7139
aed5dec3 7140 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7141 if (err) {
7142 dev_err(&pdev->dev,
7143 "igb: Cannot enable PCI device from suspend\n");
7144 return err;
7145 }
7146 pci_set_master(pdev);
7147
7148 pci_enable_wake(pdev, PCI_D3hot, 0);
7149 pci_enable_wake(pdev, PCI_D3cold, 0);
7150
53c7d064 7151 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7152 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7153 return -ENOMEM;
9d5c8243
AK		 7154 }
7155
9d5c8243 7156 igb_reset(adapter);
a8564f03
AD		 7157
7158 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7159 * driver.
7160 */
a8564f03
AD		 7161 igb_get_hw_control(adapter);
7162
9d5c8243
AK		 7163 wr32(E1000_WUS, ~0);
7164
749ab2cd 7165 if (netdev->flags & IFF_UP) {
0c2cc02e 7166 rtnl_lock();
749ab2cd 7167 err = __igb_open(netdev, true);
0c2cc02e 7168 rtnl_unlock();
a88f10ec
AD		 7169 if (err)
7170 return err;
7171 }
9d5c8243
AK		 7172
7173 netif_device_attach(netdev);
749ab2cd
YZ		 7174 return 0;
7175}
7176
7177#ifdef CONFIG_PM_RUNTIME
7178static int igb_runtime_idle(struct device *dev)
7179{
7180 struct pci_dev *pdev = to_pci_dev(dev);
7181 struct net_device *netdev = pci_get_drvdata(pdev);
7182 struct igb_adapter *adapter = netdev_priv(netdev);
7183
7184 if (!igb_has_link(adapter))
7185 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7186
7187 return -EBUSY;
7188}
7189
7190static int igb_runtime_suspend(struct device *dev)
7191{
7192 struct pci_dev *pdev = to_pci_dev(dev);
7193 int retval;
7194 bool wake;
7195
7196 retval = __igb_shutdown(pdev, &wake, 1);
7197 if (retval)
7198 return retval;
7199
7200 if (wake) {
7201 pci_prepare_to_sleep(pdev);
7202 } else {
7203 pci_wake_from_d3(pdev, false);
7204 pci_set_power_state(pdev, PCI_D3hot);
7205 }
9d5c8243 7206
9d5c8243
AK		 7207 return 0;
7208}
749ab2cd
YZ		 7209
7210static int igb_runtime_resume(struct device *dev)
7211{
7212 return igb_resume(dev);
7213}
7214#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7215#endif
7216
7217static void igb_shutdown(struct pci_dev *pdev)
7218{
3fe7c4c9
RW		 7219 bool wake;
7220
749ab2cd 7221 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7222
7223 if (system_state == SYSTEM_POWER_OFF) {
7224 pci_wake_from_d3(pdev, wake);
7225 pci_set_power_state(pdev, PCI_D3hot);
7226 }
9d5c8243
AK		 7227}
7228
fa44f2f1
GR		 7229#ifdef CONFIG_PCI_IOV
7230static int igb_sriov_reinit(struct pci_dev *dev)
7231{
7232 struct net_device *netdev = pci_get_drvdata(dev);
7233 struct igb_adapter *adapter = netdev_priv(netdev);
7234 struct pci_dev *pdev = adapter->pdev;
7235
7236 rtnl_lock();
7237
7238 if (netif_running(netdev))
7239 igb_close(netdev);
7240
7241 igb_clear_interrupt_scheme(adapter);
7242
7243 igb_init_queue_configuration(adapter);
7244
7245 if (igb_init_interrupt_scheme(adapter, true)) {
7246 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7247 return -ENOMEM;
7248 }
7249
7250 if (netif_running(netdev))
7251 igb_open(netdev);
7252
7253 rtnl_unlock();
7254
7255 return 0;
7256}
7257
7258static int igb_pci_disable_sriov(struct pci_dev *dev)
7259{
7260 int err = igb_disable_sriov(dev);
7261
7262 if (!err)
7263 err = igb_sriov_reinit(dev);
7264
7265 return err;
7266}
7267
7268static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7269{
7270 int err = igb_enable_sriov(dev, num_vfs);
7271
7272 if (err)
7273 goto out;
7274
7275 err = igb_sriov_reinit(dev);
7276 if (!err)
7277 return num_vfs;
7278
7279out:
7280 return err;
7281}
7282
7283#endif
7284static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7285{
7286#ifdef CONFIG_PCI_IOV
7287 if (num_vfs == 0)
7288 return igb_pci_disable_sriov(dev);
7289 else
7290 return igb_pci_enable_sriov(dev, num_vfs);
7291#endif
7292 return 0;
7293}
7294
9d5c8243 7295#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7296/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7297 * without having to re-enable interrupts. It's not called while
7298 * the interrupt routine is executing.
7299 */
7300static void igb_netpoll(struct net_device *netdev)
7301{
7302 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7303 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7304 struct igb_q_vector *q_vector;
9d5c8243 7305 int i;
9d5c8243 7306
047e0030 7307 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7308 q_vector = adapter->q_vector[i];
7309 if (adapter->msix_entries)
7310 wr32(E1000_EIMC, q_vector->eims_value);
7311 else
7312 igb_irq_disable(adapter);
047e0030 7313 napi_schedule(&q_vector->napi);
eebbbdba 7314 }
9d5c8243
AK		 7315}
7316#endif /* CONFIG_NET_POLL_CONTROLLER */
7317
7318/**
b980ac18
JK		 7319 * igb_io_error_detected - called when PCI error is detected
7320 * @pdev: Pointer to PCI device
7321 * @state: The current pci connection state
9d5c8243 7322 *
b980ac18
JK		 7323 * This function is called after a PCI bus error affecting
7324 * this device has been detected.
7325 **/
9d5c8243
AK		 7326static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7327 pci_channel_state_t state)
7328{
7329 struct net_device *netdev = pci_get_drvdata(pdev);
7330 struct igb_adapter *adapter = netdev_priv(netdev);
7331
7332 netif_device_detach(netdev);
7333
59ed6eec
AD		 7334 if (state == pci_channel_io_perm_failure)
7335 return PCI_ERS_RESULT_DISCONNECT;
7336
9d5c8243
AK		 7337 if (netif_running(netdev))
7338 igb_down(adapter);
7339 pci_disable_device(pdev);
7340
7341 /* Request a slot slot reset. */
7342 return PCI_ERS_RESULT_NEED_RESET;
7343}
7344
7345/**
b980ac18
JK		 7346 * igb_io_slot_reset - called after the pci bus has been reset.
7347 * @pdev: Pointer to PCI device
9d5c8243 7348 *
b980ac18
JK		 7349 * Restart the card from scratch, as if from a cold-boot. Implementation
7350 * resembles the first-half of the igb_resume routine.
7351 **/
9d5c8243
AK		 7352static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7353{
7354 struct net_device *netdev = pci_get_drvdata(pdev);
7355 struct igb_adapter *adapter = netdev_priv(netdev);
7356 struct e1000_hw *hw = &adapter->hw;
40a914fa 7357 pci_ers_result_t result;
42bfd33a 7358 int err;
9d5c8243 7359
aed5dec3 7360 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7361 dev_err(&pdev->dev,
7362 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7363 result = PCI_ERS_RESULT_DISCONNECT;
7364 } else {
7365 pci_set_master(pdev);
7366 pci_restore_state(pdev);
b94f2d77 7367 pci_save_state(pdev);
9d5c8243 7368
40a914fa
AD		 7369 pci_enable_wake(pdev, PCI_D3hot, 0);
7370 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7371
40a914fa
AD		 7372 igb_reset(adapter);
7373 wr32(E1000_WUS, ~0);
7374 result = PCI_ERS_RESULT_RECOVERED;
7375 }
9d5c8243 7376
ea943d41
JK		 7377 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7378 if (err) {
b980ac18
JK		 7379 dev_err(&pdev->dev,
7380 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7381 err);
ea943d41
JK		 7382 /* non-fatal, continue */
7383 }
40a914fa
AD		 7384
7385 return result;
9d5c8243
AK		 7386}
7387
7388/**
b980ac18
JK		 7389 * igb_io_resume - called when traffic can start flowing again.
7390 * @pdev: Pointer to PCI device
9d5c8243 7391 *
b980ac18
JK		 7392 * This callback is called when the error recovery driver tells us that
7393 * its OK to resume normal operation. Implementation resembles the
7394 * second-half of the igb_resume routine.
9d5c8243
AK		 7395 */
7396static void igb_io_resume(struct pci_dev *pdev)
7397{
7398 struct net_device *netdev = pci_get_drvdata(pdev);
7399 struct igb_adapter *adapter = netdev_priv(netdev);
7400
9d5c8243
AK		 7401 if (netif_running(netdev)) {
7402 if (igb_up(adapter)) {
7403 dev_err(&pdev->dev, "igb_up failed after reset\n");
7404 return;
7405 }
7406 }
7407
7408 netif_device_attach(netdev);
7409
7410 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7411 * driver.
7412 */
9d5c8243 7413 igb_get_hw_control(adapter);
9d5c8243
AK		 7414}
7415
26ad9178 7416static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7417 u8 qsel)
26ad9178
AD		 7418{
7419 u32 rar_low, rar_high;
7420 struct e1000_hw *hw = &adapter->hw;
7421
7422 /* HW expects these in little endian so we reverse the byte order
7423 * from network order (big endian) to little endian
7424 */
7425 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7426 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7427 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7428
7429 /* Indicate to hardware the Address is Valid. */
7430 rar_high |= E1000_RAH_AV;
7431
7432 if (hw->mac.type == e1000_82575)
7433 rar_high |= E1000_RAH_POOL_1 * qsel;
7434 else
7435 rar_high |= E1000_RAH_POOL_1 << qsel;
7436
7437 wr32(E1000_RAL(index), rar_low);
7438 wrfl();
7439 wr32(E1000_RAH(index), rar_high);
7440 wrfl();
7441}
7442
4ae196df 7443static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7444 int vf, unsigned char *mac_addr)
4ae196df
AD		 7445{
7446 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7447 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7448 * towards the first, as a result a collision should not be possible
7449 */
ff41f8dc 7450 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7451
37680117 7452 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7453
26ad9178 7454 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7455
7456 return 0;
7457}
7458
8151d294
WM		 7459static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7460{
7461 struct igb_adapter *adapter = netdev_priv(netdev);
7462 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7463 return -EINVAL;
7464 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7465 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7466 dev_info(&adapter->pdev->dev,
7467 "Reload the VF driver to make this change effective.");
8151d294 7468 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7469 dev_warn(&adapter->pdev->dev,
7470 "The VF MAC address has been set, but the PF device is not up.\n");
7471 dev_warn(&adapter->pdev->dev,
7472 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7473 }
7474 return igb_set_vf_mac(adapter, vf, mac);
7475}
7476
17dc566c
LL		 7477static int igb_link_mbps(int internal_link_speed)
7478{
7479 switch (internal_link_speed) {
7480 case SPEED_100:
7481 return 100;
7482 case SPEED_1000:
7483 return 1000;
7484 default:
7485 return 0;
7486 }
7487}
7488
7489static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7490 int link_speed)
7491{
7492 int rf_dec, rf_int;
7493 u32 bcnrc_val;
7494
7495 if (tx_rate != 0) {
7496 /* Calculate the rate factor values to set */
7497 rf_int = link_speed / tx_rate;
7498 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7499 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7500 tx_rate;
17dc566c
LL		 7501
7502 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7503 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7504 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7505 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7506 } else {
7507 bcnrc_val = 0;
7508 }
7509
7510 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7511 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7512 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7513 */
7514 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7515 wr32(E1000_RTTBCNRC, bcnrc_val);
7516}
7517
7518static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7519{
7520 int actual_link_speed, i;
7521 bool reset_rate = false;
7522
7523 /* VF TX rate limit was not set or not supported */
7524 if ((adapter->vf_rate_link_speed == 0) ||
7525 (adapter->hw.mac.type != e1000_82576))
7526 return;
7527
7528 actual_link_speed = igb_link_mbps(adapter->link_speed);
7529 if (actual_link_speed != adapter->vf_rate_link_speed) {
7530 reset_rate = true;
7531 adapter->vf_rate_link_speed = 0;
7532 dev_info(&adapter->pdev->dev,
b980ac18 7533 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7534 }
7535
7536 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7537 if (reset_rate)
7538 adapter->vf_data[i].tx_rate = 0;
7539
7540 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7541 adapter->vf_data[i].tx_rate,
7542 actual_link_speed);
17dc566c
LL		 7543 }
7544}
7545
8151d294
WM		 7546static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7547{
17dc566c
LL		 7548 struct igb_adapter *adapter = netdev_priv(netdev);
7549 struct e1000_hw *hw = &adapter->hw;
7550 int actual_link_speed;
7551
7552 if (hw->mac.type != e1000_82576)
7553 return -EOPNOTSUPP;
7554
7555 actual_link_speed = igb_link_mbps(adapter->link_speed);
7556 if ((vf >= adapter->vfs_allocated_count) ||
7557 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7558 (tx_rate < 0) || (tx_rate > actual_link_speed))
7559 return -EINVAL;
7560
7561 adapter->vf_rate_link_speed = actual_link_speed;
7562 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7563 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7564
7565 return 0;
8151d294
WM		 7566}
7567
70ea4783
LL		 7568static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7569 bool setting)
7570{
7571 struct igb_adapter *adapter = netdev_priv(netdev);
7572 struct e1000_hw *hw = &adapter->hw;
7573 u32 reg_val, reg_offset;
7574
7575 if (!adapter->vfs_allocated_count)
7576 return -EOPNOTSUPP;
7577
7578 if (vf >= adapter->vfs_allocated_count)
7579 return -EINVAL;
7580
7581 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7582 reg_val = rd32(reg_offset);
7583 if (setting)
7584 reg_val |= ((1 << vf) |
7585 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7586 else
7587 reg_val &= ~((1 << vf) |
7588 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7589 wr32(reg_offset, reg_val);
7590
7591 adapter->vf_data[vf].spoofchk_enabled = setting;
7592 return E1000_SUCCESS;
7593}
7594
8151d294
WM		 7595static int igb_ndo_get_vf_config(struct net_device *netdev,
7596 int vf, struct ifla_vf_info *ivi)
7597{
7598 struct igb_adapter *adapter = netdev_priv(netdev);
7599 if (vf >= adapter->vfs_allocated_count)
7600 return -EINVAL;
7601 ivi->vf = vf;
7602 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7603 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7604 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7605 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7606 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7607 return 0;
7608}
7609
4ae196df
AD		 7610static void igb_vmm_control(struct igb_adapter *adapter)
7611{
7612 struct e1000_hw *hw = &adapter->hw;
10d8e907 7613 u32 reg;
4ae196df 7614
52a1dd4d
AD		 7615 switch (hw->mac.type) {
7616 case e1000_82575:
f96a8a0b
CW		 7617 case e1000_i210:
7618 case e1000_i211:
ceb5f13b 7619 case e1000_i354:
52a1dd4d
AD		 7620 default:
7621 /* replication is not supported for 82575 */
4ae196df 7622 return;
52a1dd4d
AD		 7623 case e1000_82576:
7624 /* notify HW that the MAC is adding vlan tags */
7625 reg = rd32(E1000_DTXCTL);
7626 reg |= E1000_DTXCTL_VLAN_ADDED;
7627 wr32(E1000_DTXCTL, reg);
7628 case e1000_82580:
7629 /* enable replication vlan tag stripping */
7630 reg = rd32(E1000_RPLOLR);
7631 reg |= E1000_RPLOLR_STRVLAN;
7632 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7633 case e1000_i350:
7634 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7635 break;
7636 }
10d8e907 7637
d4960307
AD		 7638 if (adapter->vfs_allocated_count) {
7639 igb_vmdq_set_loopback_pf(hw, true);
7640 igb_vmdq_set_replication_pf(hw, true);
13800469 7641 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7642 adapter->vfs_allocated_count);
d4960307
AD		 7643 } else {
7644 igb_vmdq_set_loopback_pf(hw, false);
7645 igb_vmdq_set_replication_pf(hw, false);
7646 }
4ae196df
AD		 7647}
7648
b6e0c419
CW		 7649static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7650{
7651 struct e1000_hw *hw = &adapter->hw;
7652 u32 dmac_thr;
7653 u16 hwm;
7654
7655 if (hw->mac.type > e1000_82580) {
7656 if (adapter->flags & IGB_FLAG_DMAC) {
7657 u32 reg;
7658
7659 /* force threshold to 0. */
7660 wr32(E1000_DMCTXTH, 0);
7661
b980ac18 7662 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7663 * than the Rx threshold. Set hwm to PBA - max frame
7664 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7665 */
e8c626e9
MV		 7666 hwm = 64 * pba - adapter->max_frame_size / 16;
7667 if (hwm < 64 * (pba - 6))
7668 hwm = 64 * (pba - 6);
7669 reg = rd32(E1000_FCRTC);
7670 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7671 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7672 & E1000_FCRTC_RTH_COAL_MASK);
7673 wr32(E1000_FCRTC, reg);
7674
b980ac18 7675 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7676 * frame size, capping it at PBA - 10KB.
7677 */
7678 dmac_thr = pba - adapter->max_frame_size / 512;
7679 if (dmac_thr < pba - 10)
7680 dmac_thr = pba - 10;
b6e0c419
CW		 7681 reg = rd32(E1000_DMACR);
7682 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7683 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7684 & E1000_DMACR_DMACTHR_MASK);
7685
7686 /* transition to L0x or L1 if available..*/
7687 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7688
7689 /* watchdog timer= +-1000 usec in 32usec intervals */
7690 reg |= (1000 >> 5);
0c02dd98
MV		 7691
7692 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7693 if (hw->mac.type != e1000_i354)
7694 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7695
b6e0c419
CW		 7696 wr32(E1000_DMACR, reg);
7697
b980ac18 7698 /* no lower threshold to disable
b6e0c419
CW		 7699 * coalescing(smart fifb)-UTRESH=0
7700 */
7701 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7702
7703 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7704
7705 wr32(E1000_DMCTLX, reg);
7706
b980ac18 7707 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7708 * DMA coal
7709 */
7710 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7711 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7712
b980ac18 7713 /* make low power state decision controlled
b6e0c419
CW		 7714 * by DMA coal
7715 */
7716 reg = rd32(E1000_PCIEMISC);
7717 reg &= ~E1000_PCIEMISC_LX_DECISION;
7718 wr32(E1000_PCIEMISC, reg);
7719 } /* endif adapter->dmac is not disabled */
7720 } else if (hw->mac.type == e1000_82580) {
7721 u32 reg = rd32(E1000_PCIEMISC);
7722 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7723 wr32(E1000_DMACR, 0);
7724 }
7725}
7726
b980ac18
JK		 7727/**
7728 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7729 * @hw: pointer to hardware structure
7730 * @byte_offset: byte offset to read
7731 * @dev_addr: device address
7732 * @data: value read
7733 *
7734 * Performs byte read operation over I2C interface at
7735 * a specified device address.
b980ac18 7736 **/
441fc6fd 7737s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7738 u8 dev_addr, u8 *data)
441fc6fd
CW		 7739{
7740 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7741 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7742 s32 status;
7743 u16 swfw_mask = 0;
7744
7745 if (!this_client)
7746 return E1000_ERR_I2C;
7747
7748 swfw_mask = E1000_SWFW_PHY0_SM;
7749
7750 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7751 != E1000_SUCCESS)
7752 return E1000_ERR_SWFW_SYNC;
7753
7754 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7755 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7756
7757 if (status < 0)
7758 return E1000_ERR_I2C;
7759 else {
7760 *data = status;
7761 return E1000_SUCCESS;
7762 }
7763}
7764
b980ac18
JK		 7765/**
7766 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7767 * @hw: pointer to hardware structure
7768 * @byte_offset: byte offset to write
7769 * @dev_addr: device address
7770 * @data: value to write
7771 *
7772 * Performs byte write operation over I2C interface at
7773 * a specified device address.
b980ac18 7774 **/
441fc6fd 7775s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7776 u8 dev_addr, u8 data)
441fc6fd
CW		 7777{
7778 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7779 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7780 s32 status;
7781 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7782
7783 if (!this_client)
7784 return E1000_ERR_I2C;
7785
7786 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7787 return E1000_ERR_SWFW_SYNC;
7788 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7789 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7790
7791 if (status)
7792 return E1000_ERR_I2C;
7793 else
7794 return E1000_SUCCESS;
7795
7796}
9d5c8243 7797/* igb_main.c */
Linux kernel - Deliverables
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