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Merge branch 'is_kdump_kernel'
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
bf22a6bd
TF		 60#define MIN 2
61#define BUILD 13
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
c1ebf46c 139static void igb_xmit_flush(struct net_device *netdev, u16 queue);
12dcd86b 140static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 141 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 142static int igb_change_mtu(struct net_device *, int);
143static int igb_set_mac(struct net_device *, void *);
68d480c4 144static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 145static irqreturn_t igb_intr(int irq, void *);
146static irqreturn_t igb_intr_msi(int irq, void *);
147static irqreturn_t igb_msix_other(int irq, void *);
047e0030 148static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 149#ifdef CONFIG_IGB_DCA
047e0030 150static void igb_update_dca(struct igb_q_vector *);
fe4506b6 151static void igb_setup_dca(struct igb_adapter *);
421e02f0 152#endif /* CONFIG_IGB_DCA */
661086df 153static int igb_poll(struct napi_struct *, int);
13fde97a 154static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 155static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 156static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
157static void igb_tx_timeout(struct net_device *);
158static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 159static void igb_vlan_mode(struct net_device *netdev,
160 netdev_features_t features);
80d5c368
PM		 161static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
162static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 163static void igb_restore_vlan(struct igb_adapter *);
26ad9178 164static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 165static void igb_ping_all_vfs(struct igb_adapter *);
166static void igb_msg_task(struct igb_adapter *);
4ae196df 167static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 168static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 169static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 170static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
171static int igb_ndo_set_vf_vlan(struct net_device *netdev,
172 int vf, u16 vlan, u8 qos);
ed616689 173static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 174static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
175 bool setting);
8151d294
WM		 176static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
177 struct ifla_vf_info *ivi);
17dc566c 178static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 179
180#ifdef CONFIG_PCI_IOV
0224d663 181static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 182static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 183#endif
9d5c8243 184
9d5c8243 185#ifdef CONFIG_PM
d9dd966d 186#ifdef CONFIG_PM_SLEEP
749ab2cd 187static int igb_suspend(struct device *);
d9dd966d 188#endif
749ab2cd
YZ		 189static int igb_resume(struct device *);
190#ifdef CONFIG_PM_RUNTIME
191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
194#endif
195static const struct dev_pm_ops igb_pm_ops = {
196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
198 igb_runtime_idle)
199};
9d5c8243
AK		 200#endif
201static void igb_shutdown(struct pci_dev *);
fa44f2f1 202static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 203#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 204static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
205static struct notifier_block dca_notifier = {
206 .notifier_call = igb_notify_dca,
207 .next = NULL,
208 .priority = 0
209};
210#endif
9d5c8243
AK		 211#ifdef CONFIG_NET_POLL_CONTROLLER
212/* for netdump / net console */
213static void igb_netpoll(struct net_device *);
214#endif
37680117 215#ifdef CONFIG_PCI_IOV
6dd6d2b7 216static unsigned int max_vfs;
2a3abf6d 217module_param(max_vfs, uint, 0);
c75c4edf 218MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 219#endif /* CONFIG_PCI_IOV */
220
9d5c8243
AK		 221static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
222 pci_channel_state_t);
223static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
224static void igb_io_resume(struct pci_dev *);
225
3646f0e5 226static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 227 .error_detected = igb_io_error_detected,
228 .slot_reset = igb_io_slot_reset,
229 .resume = igb_io_resume,
230};
231
b6e0c419 232static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 233
234static struct pci_driver igb_driver = {
235 .name = igb_driver_name,
236 .id_table = igb_pci_tbl,
237 .probe = igb_probe,
9f9a12f8 238 .remove = igb_remove,
9d5c8243 239#ifdef CONFIG_PM
749ab2cd 240 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 241#endif
242 .shutdown = igb_shutdown,
fa44f2f1 243 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 244 .err_handler = &igb_err_handler
245};
246
247MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
248MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
249MODULE_LICENSE("GPL");
250MODULE_VERSION(DRV_VERSION);
251
b3f4d599 252#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
253static int debug = -1;
254module_param(debug, int, 0);
255MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
256
c97ec42a
TI		 257struct igb_reg_info {
258 u32 ofs;
259 char *name;
260};
261
262static const struct igb_reg_info igb_reg_info_tbl[] = {
263
264 /* General Registers */
265 {E1000_CTRL, "CTRL"},
266 {E1000_STATUS, "STATUS"},
267 {E1000_CTRL_EXT, "CTRL_EXT"},
268
269 /* Interrupt Registers */
270 {E1000_ICR, "ICR"},
271
272 /* RX Registers */
273 {E1000_RCTL, "RCTL"},
274 {E1000_RDLEN(0), "RDLEN"},
275 {E1000_RDH(0), "RDH"},
276 {E1000_RDT(0), "RDT"},
277 {E1000_RXDCTL(0), "RXDCTL"},
278 {E1000_RDBAL(0), "RDBAL"},
279 {E1000_RDBAH(0), "RDBAH"},
280
281 /* TX Registers */
282 {E1000_TCTL, "TCTL"},
283 {E1000_TDBAL(0), "TDBAL"},
284 {E1000_TDBAH(0), "TDBAH"},
285 {E1000_TDLEN(0), "TDLEN"},
286 {E1000_TDH(0), "TDH"},
287 {E1000_TDT(0), "TDT"},
288 {E1000_TXDCTL(0), "TXDCTL"},
289 {E1000_TDFH, "TDFH"},
290 {E1000_TDFT, "TDFT"},
291 {E1000_TDFHS, "TDFHS"},
292 {E1000_TDFPC, "TDFPC"},
293
294 /* List Terminator */
295 {}
296};
297
b980ac18 298/* igb_regdump - register printout routine */
c97ec42a
TI		 299static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
300{
301 int n = 0;
302 char rname[16];
303 u32 regs[8];
304
305 switch (reginfo->ofs) {
306 case E1000_RDLEN(0):
307 for (n = 0; n < 4; n++)
308 regs[n] = rd32(E1000_RDLEN(n));
309 break;
310 case E1000_RDH(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDH(n));
313 break;
314 case E1000_RDT(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDT(n));
317 break;
318 case E1000_RXDCTL(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RXDCTL(n));
321 break;
322 case E1000_RDBAL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RDBAL(n));
325 break;
326 case E1000_RDBAH(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAH(n));
329 break;
330 case E1000_TDBAL(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAL(n));
333 break;
334 case E1000_TDBAH(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_TDBAH(n));
337 break;
338 case E1000_TDLEN(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDLEN(n));
341 break;
342 case E1000_TDH(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDH(n));
345 break;
346 case E1000_TDT(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDT(n));
349 break;
350 case E1000_TXDCTL(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TXDCTL(n));
353 break;
354 default:
876d2d6f 355 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 356 return;
357 }
358
359 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 360 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
361 regs[2], regs[3]);
c97ec42a
TI		 362}
363
b980ac18 364/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 365static void igb_dump(struct igb_adapter *adapter)
366{
367 struct net_device *netdev = adapter->netdev;
368 struct e1000_hw *hw = &adapter->hw;
369 struct igb_reg_info *reginfo;
c97ec42a
TI		 370 struct igb_ring *tx_ring;
371 union e1000_adv_tx_desc *tx_desc;
372 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 373 struct igb_ring *rx_ring;
374 union e1000_adv_rx_desc *rx_desc;
375 u32 staterr;
6ad4edfc 376 u16 i, n;
c97ec42a
TI		 377
378 if (!netif_msg_hw(adapter))
379 return;
380
381 /* Print netdevice Info */
382 if (netdev) {
383 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 384 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 385 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
386 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 387 }
388
389 /* Print Registers */
390 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 391 pr_info(" Register Name Value\n");
c97ec42a
TI		 392 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
393 reginfo->name; reginfo++) {
394 igb_regdump(hw, reginfo);
395 }
396
397 /* Print TX Ring Summary */
398 if (!netdev || !netif_running(netdev))
399 goto exit;
400
401 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 402 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 403 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 404 struct igb_tx_buffer *buffer_info;
c97ec42a 405 tx_ring = adapter->tx_ring[n];
06034649 406 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 407 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
408 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 409 (u64)dma_unmap_addr(buffer_info, dma),
410 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 411 buffer_info->next_to_watch,
412 (u64)buffer_info->time_stamp);
c97ec42a
TI		 413 }
414
415 /* Print TX Rings */
416 if (!netif_msg_tx_done(adapter))
417 goto rx_ring_summary;
418
419 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
420
421 /* Transmit Descriptor Formats
422 *
423 * Advanced Transmit Descriptor
424 * +--------------------------------------------------------------+
425 * 0 | Buffer Address [63:0] |
426 * +--------------------------------------------------------------+
427 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
428 * +--------------------------------------------------------------+
429 * 63 46 45 40 39 38 36 35 32 31 24 15 0
430 */
431
432 for (n = 0; n < adapter->num_tx_queues; n++) {
433 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 434 pr_info("------------------------------------\n");
435 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
436 pr_info("------------------------------------\n");
c75c4edf 437 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 440 const char *next_desc;
06034649 441 struct igb_tx_buffer *buffer_info;
60136906 442 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 443 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 444 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
c75c4edf
CW		 455 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
456 i, le64_to_cpu(u0->a),
c97ec42a 457 le64_to_cpu(u0->b),
c9f14bf3
AD		 458 (u64)dma_unmap_addr(buffer_info, dma),
459 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 460 buffer_info->next_to_watch,
461 (u64)buffer_info->time_stamp,
876d2d6f 462 buffer_info->skb, next_desc);
c97ec42a 463
b669588a 464 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 465 print_hex_dump(KERN_INFO, "",
466 DUMP_PREFIX_ADDRESS,
b669588a 467 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 468 dma_unmap_len(buffer_info, len),
469 true);
c97ec42a
TI		 470 }
471 }
472
473 /* Print RX Rings Summary */
474rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 476 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
c75c4edf
CW		 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
516 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 517
518 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 519 const char *next_desc;
06034649
AD		 520 struct igb_rx_buffer *buffer_info;
521 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 522 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 523 u0 = (struct my_u0 *)rx_desc;
524 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 525
526 if (i == rx_ring->next_to_use)
527 next_desc = " NTU";
528 else if (i == rx_ring->next_to_clean)
529 next_desc = " NTC";
530 else
531 next_desc = "";
532
c97ec42a
TI		 533 if (staterr & E1000_RXD_STAT_DD) {
534 /* Descriptor Done */
1a1c225b
AD		 535 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
536 "RWB", i,
c97ec42a
TI		 537 le64_to_cpu(u0->a),
538 le64_to_cpu(u0->b),
1a1c225b 539 next_desc);
c97ec42a 540 } else {
1a1c225b
AD		 541 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
542 "R ", i,
c97ec42a
TI		 543 le64_to_cpu(u0->a),
544 le64_to_cpu(u0->b),
545 (u64)buffer_info->dma,
1a1c225b 546 next_desc);
c97ec42a 547
b669588a 548 if (netif_msg_pktdata(adapter) &&
1a1c225b 549 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 550 print_hex_dump(KERN_INFO, "",
551 DUMP_PREFIX_ADDRESS,
552 16, 1,
b669588a
ET		 553 page_address(buffer_info->page) +
554 buffer_info->page_offset,
de78d1f9 555 IGB_RX_BUFSZ, true);
c97ec42a
TI		 556 }
557 }
c97ec42a
TI		 558 }
559 }
560
561exit:
562 return;
563}
564
b980ac18
JK		 565/**
566 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 567 * @hw: pointer to hardware structure
568 * @i2cctl: Current value of I2CCTL register
569 *
570 * Returns the I2C data bit value
b980ac18 571 **/
441fc6fd
CW		 572static int igb_get_i2c_data(void *data)
573{
574 struct igb_adapter *adapter = (struct igb_adapter *)data;
575 struct e1000_hw *hw = &adapter->hw;
576 s32 i2cctl = rd32(E1000_I2CPARAMS);
577
da1f1dfe 578 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 579}
580
b980ac18
JK		 581/**
582 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 583 * @data: pointer to hardware structure
584 * @state: I2C data value (0 or 1) to set
585 *
586 * Sets the I2C data bit
b980ac18 587 **/
441fc6fd
CW		 588static void igb_set_i2c_data(void *data, int state)
589{
590 struct igb_adapter *adapter = (struct igb_adapter *)data;
591 struct e1000_hw *hw = &adapter->hw;
592 s32 i2cctl = rd32(E1000_I2CPARAMS);
593
594 if (state)
595 i2cctl |= E1000_I2C_DATA_OUT;
596 else
597 i2cctl &= ~E1000_I2C_DATA_OUT;
598
599 i2cctl &= ~E1000_I2C_DATA_OE_N;
600 i2cctl |= E1000_I2C_CLK_OE_N;
601 wr32(E1000_I2CPARAMS, i2cctl);
602 wrfl();
603
604}
605
b980ac18
JK		 606/**
607 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 608 * @data: pointer to hardware structure
609 * @state: state to set clock
610 *
611 * Sets the I2C clock line to state
b980ac18 612 **/
441fc6fd
CW		 613static void igb_set_i2c_clk(void *data, int state)
614{
615 struct igb_adapter *adapter = (struct igb_adapter *)data;
616 struct e1000_hw *hw = &adapter->hw;
617 s32 i2cctl = rd32(E1000_I2CPARAMS);
618
619 if (state) {
620 i2cctl |= E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 } else {
623 i2cctl &= ~E1000_I2C_CLK_OUT;
624 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 }
626 wr32(E1000_I2CPARAMS, i2cctl);
627 wrfl();
628}
629
b980ac18
JK		 630/**
631 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 632 * @data: pointer to hardware structure
633 *
634 * Gets the I2C clock state
b980ac18 635 **/
441fc6fd
CW		 636static int igb_get_i2c_clk(void *data)
637{
638 struct igb_adapter *adapter = (struct igb_adapter *)data;
639 struct e1000_hw *hw = &adapter->hw;
640 s32 i2cctl = rd32(E1000_I2CPARAMS);
641
da1f1dfe 642 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 643}
644
645static const struct i2c_algo_bit_data igb_i2c_algo = {
646 .setsda = igb_set_i2c_data,
647 .setscl = igb_set_i2c_clk,
648 .getsda = igb_get_i2c_data,
649 .getscl = igb_get_i2c_clk,
650 .udelay = 5,
651 .timeout = 20,
652};
653
9d5c8243 654/**
b980ac18
JK		 655 * igb_get_hw_dev - return device
656 * @hw: pointer to hardware structure
657 *
658 * used by hardware layer to print debugging information
9d5c8243 659 **/
c041076a 660struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 661{
662 struct igb_adapter *adapter = hw->back;
c041076a 663 return adapter->netdev;
9d5c8243 664}
38c845c7 665
9d5c8243 666/**
b980ac18 667 * igb_init_module - Driver Registration Routine
9d5c8243 668 *
b980ac18
JK		 669 * igb_init_module is the first routine called when the driver is
670 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 671 **/
672static int __init igb_init_module(void)
673{
674 int ret;
9005df38 675
876d2d6f 676 pr_info("%s - version %s\n",
9d5c8243 677 igb_driver_string, igb_driver_version);
876d2d6f 678 pr_info("%s\n", igb_copyright);
9d5c8243 679
421e02f0 680#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 681 dca_register_notify(&dca_notifier);
682#endif
bbd98fe4 683 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 684 return ret;
685}
686
687module_init(igb_init_module);
688
689/**
b980ac18 690 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 691 *
b980ac18
JK		 692 * igb_exit_module is called just before the driver is removed
693 * from memory.
9d5c8243
AK		 694 **/
695static void __exit igb_exit_module(void)
696{
421e02f0 697#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 698 dca_unregister_notify(&dca_notifier);
699#endif
9d5c8243
AK		 700 pci_unregister_driver(&igb_driver);
701}
702
703module_exit(igb_exit_module);
704
26bc19ec
AD		 705#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706/**
b980ac18
JK		 707 * igb_cache_ring_register - Descriptor ring to register mapping
708 * @adapter: board private structure to initialize
26bc19ec 709 *
b980ac18
JK		 710 * Once we know the feature-set enabled for the device, we'll cache
711 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 712 **/
713static void igb_cache_ring_register(struct igb_adapter *adapter)
714{
ee1b9f06 715 int i = 0, j = 0;
047e0030 716 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 717
718 switch (adapter->hw.mac.type) {
719 case e1000_82576:
720 /* The queues are allocated for virtualization such that VF 0
721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
722 * In order to avoid collision we start at the first free queue
723 * and continue consuming queues in the same sequence
724 */
ee1b9f06 725 if (adapter->vfs_allocated_count) {
a99955fc 726 for (; i < adapter->rss_queues; i++)
3025a446 727 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 728 Q_IDX_82576(i);
ee1b9f06 729 }
b26141d4 730 /* Fall through */
26bc19ec 731 case e1000_82575:
55cac248 732 case e1000_82580:
d2ba2ed8 733 case e1000_i350:
ceb5f13b 734 case e1000_i354:
f96a8a0b
CW		 735 case e1000_i210:
736 case e1000_i211:
b26141d4 737 /* Fall through */
26bc19ec 738 default:
ee1b9f06 739 for (; i < adapter->num_rx_queues; i++)
3025a446 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 741 for (; j < adapter->num_tx_queues; j++)
3025a446 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 743 break;
744 }
745}
746
22a8b291
FT		 747u32 igb_rd32(struct e1000_hw *hw, u32 reg)
748{
749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
751 u32 value = 0;
752
753 if (E1000_REMOVED(hw_addr))
754 return ~value;
755
756 value = readl(&hw_addr[reg]);
757
758 /* reads should not return all F's */
759 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
760 struct net_device *netdev = igb->netdev;
761 hw->hw_addr = NULL;
762 netif_device_detach(netdev);
763 netdev_err(netdev, "PCIe link lost, device now detached\n");
764 }
765
766 return value;
767}
768
4be000c8
AD		 769/**
770 * igb_write_ivar - configure ivar for given MSI-X vector
771 * @hw: pointer to the HW structure
772 * @msix_vector: vector number we are allocating to a given ring
773 * @index: row index of IVAR register to write within IVAR table
774 * @offset: column offset of in IVAR, should be multiple of 8
775 *
776 * This function is intended to handle the writing of the IVAR register
777 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
778 * each containing an cause allocation for an Rx and Tx ring, and a
779 * variable number of rows depending on the number of queues supported.
780 **/
781static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
782 int index, int offset)
783{
784 u32 ivar = array_rd32(E1000_IVAR0, index);
785
786 /* clear any bits that are currently set */
787 ivar &= ~((u32)0xFF << offset);
788
789 /* write vector and valid bit */
790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
791
792 array_wr32(E1000_IVAR0, index, ivar);
793}
794
9d5c8243 795#define IGB_N0_QUEUE -1
047e0030 796static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 797{
047e0030 798 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 799 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 800 int rx_queue = IGB_N0_QUEUE;
801 int tx_queue = IGB_N0_QUEUE;
4be000c8 802 u32 msixbm = 0;
047e0030 803
0ba82994
AD		 804 if (q_vector->rx.ring)
805 rx_queue = q_vector->rx.ring->reg_idx;
806 if (q_vector->tx.ring)
807 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 808
809 switch (hw->mac.type) {
810 case e1000_82575:
9d5c8243 811 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one
813 * or more queues to a vector, we write the appropriate bits
814 * into the MSIXBM register for that vector.
815 */
047e0030 816 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 818 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 821 msixbm |= E1000_EIMS_OTHER;
9d5c8243 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 823 q_vector->eims_value = msixbm;
2d064c06
AD		 824 break;
825 case e1000_82576:
b980ac18 826 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 827 * with 8 rows. The ordering is column-major so we use the
828 * lower 3 bits as the row index, and the 4th bit as the
829 * column offset.
830 */
831 if (rx_queue > IGB_N0_QUEUE)
832 igb_write_ivar(hw, msix_vector,
833 rx_queue & 0x7,
834 (rx_queue & 0x8) << 1);
835 if (tx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 tx_queue & 0x7,
838 ((tx_queue & 0x8) << 1) + 8);
047e0030 839 q_vector->eims_value = 1 << msix_vector;
2d064c06 840 break;
55cac248 841 case e1000_82580:
d2ba2ed8 842 case e1000_i350:
ceb5f13b 843 case e1000_i354:
f96a8a0b
CW		 844 case e1000_i210:
845 case e1000_i211:
b980ac18 846 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 847 * however instead of ordering column-major we have things
848 * ordered row-major. So we traverse the table by using
849 * bit 0 as the column offset, and the remaining bits as the
850 * row index.
851 */
852 if (rx_queue > IGB_N0_QUEUE)
853 igb_write_ivar(hw, msix_vector,
854 rx_queue >> 1,
855 (rx_queue & 0x1) << 4);
856 if (tx_queue > IGB_N0_QUEUE)
857 igb_write_ivar(hw, msix_vector,
858 tx_queue >> 1,
859 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 860 q_vector->eims_value = 1 << msix_vector;
861 break;
2d064c06
AD		 862 default:
863 BUG();
864 break;
865 }
26b39276
AD		 866
867 /* add q_vector eims value to global eims_enable_mask */
868 adapter->eims_enable_mask |= q_vector->eims_value;
869
870 /* configure q_vector to set itr on first interrupt */
871 q_vector->set_itr = 1;
9d5c8243
AK		 872}
873
874/**
b980ac18
JK		 875 * igb_configure_msix - Configure MSI-X hardware
876 * @adapter: board private structure to initialize
9d5c8243 877 *
b980ac18
JK		 878 * igb_configure_msix sets up the hardware to properly
879 * generate MSI-X interrupts.
9d5c8243
AK		 880 **/
881static void igb_configure_msix(struct igb_adapter *adapter)
882{
883 u32 tmp;
884 int i, vector = 0;
885 struct e1000_hw *hw = &adapter->hw;
886
887 adapter->eims_enable_mask = 0;
9d5c8243
AK		 888
889 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 890 switch (hw->mac.type) {
891 case e1000_82575:
9d5c8243
AK		 892 tmp = rd32(E1000_CTRL_EXT);
893 /* enable MSI-X PBA support*/
894 tmp |= E1000_CTRL_EXT_PBA_CLR;
895
896 /* Auto-Mask interrupts upon ICR read. */
897 tmp |= E1000_CTRL_EXT_EIAME;
898 tmp |= E1000_CTRL_EXT_IRCA;
899
900 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 901
902 /* enable msix_other interrupt */
b980ac18 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 904 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 905
2d064c06
AD		 906 break;
907
908 case e1000_82576:
55cac248 909 case e1000_82580:
d2ba2ed8 910 case e1000_i350:
ceb5f13b 911 case e1000_i354:
f96a8a0b
CW		 912 case e1000_i210:
913 case e1000_i211:
047e0030 914 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 915 * won't stick. And it will take days to debug.
916 */
047e0030 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 918 E1000_GPIE_PBA | E1000_GPIE_EIAME |
919 E1000_GPIE_NSICR);
047e0030
AD		 920
921 /* enable msix_other interrupt */
922 adapter->eims_other = 1 << vector;
2d064c06 923 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 924
047e0030 925 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 926 break;
927 default:
928 /* do nothing, since nothing else supports MSI-X */
929 break;
930 } /* switch (hw->mac.type) */
047e0030
AD		 931
932 adapter->eims_enable_mask |= adapter->eims_other;
933
26b39276
AD		 934 for (i = 0; i < adapter->num_q_vectors; i++)
935 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 936
9d5c8243
AK		 937 wrfl();
938}
939
940/**
b980ac18
JK		 941 * igb_request_msix - Initialize MSI-X interrupts
942 * @adapter: board private structure to initialize
9d5c8243 943 *
b980ac18
JK		 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
945 * kernel.
9d5c8243
AK		 946 **/
947static int igb_request_msix(struct igb_adapter *adapter)
948{
949 struct net_device *netdev = adapter->netdev;
047e0030 950 struct e1000_hw *hw = &adapter->hw;
52285b76 951 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 952
047e0030 953 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 954 igb_msix_other, 0, netdev->name, adapter);
047e0030 955 if (err)
52285b76 956 goto err_out;
047e0030
AD		 957
958 for (i = 0; i < adapter->num_q_vectors; i++) {
959 struct igb_q_vector *q_vector = adapter->q_vector[i];
960
52285b76
SA		 961 vector++;
962
047e0030
AD		 963 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
964
0ba82994 965 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 966 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 967 q_vector->rx.ring->queue_index);
968 else if (q_vector->tx.ring)
047e0030 969 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 970 q_vector->tx.ring->queue_index);
971 else if (q_vector->rx.ring)
047e0030 972 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 973 q_vector->rx.ring->queue_index);
9d5c8243 974 else
047e0030
AD		 975 sprintf(q_vector->name, "%s-unused", netdev->name);
976
9d5c8243 977 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 978 igb_msix_ring, 0, q_vector->name,
979 q_vector);
9d5c8243 980 if (err)
52285b76 981 goto err_free;
9d5c8243
AK		 982 }
983
9d5c8243
AK		 984 igb_configure_msix(adapter);
985 return 0;
52285b76
SA		 986
987err_free:
988 /* free already assigned IRQs */
989 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
990
991 vector--;
992 for (i = 0; i < vector; i++) {
993 free_irq(adapter->msix_entries[free_vector++].vector,
994 adapter->q_vector[i]);
995 }
996err_out:
9d5c8243
AK		 997 return err;
998}
999
5536d210 1000/**
b980ac18
JK		 1001 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1002 * @adapter: board private structure to initialize
1003 * @v_idx: Index of vector to be freed
5536d210 1004 *
02ef6e1d 1005 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1006 **/
1007static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1008{
1009 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1010
02ef6e1d
CW		 1011 adapter->q_vector[v_idx] = NULL;
1012
1013 /* igb_get_stats64() might access the rings on this vector,
1014 * we must wait a grace period before freeing it.
1015 */
1016 kfree_rcu(q_vector, rcu);
1017}
1018
1019/**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
cb06d102
CP		 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
5536d210
AD		 1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
1041 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1042
5536d210
AD		 1043 netif_napi_del(&q_vector->napi);
1044
02ef6e1d
CW		 1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
cd14ef54 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1052 pci_disable_msix(adapter->pdev);
cd14ef54 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1054 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1058}
1059
047e0030 1060/**
b980ac18
JK		 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
047e0030 1063 *
b980ac18
JK		 1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
047e0030
AD		 1067 **/
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
5536d210
AD		 1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
047e0030 1074 adapter->num_q_vectors = 0;
5536d210 1075
02ef6e1d
CW		 1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
5536d210 1078 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1079 }
047e0030
AD		 1080}
1081
1082/**
b980ac18
JK		 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
047e0030 1085 *
b980ac18
JK		 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
047e0030
AD		 1088 */
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
047e0030
AD		 1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
9d5c8243
AK		 1094
1095/**
b980ac18
JK		 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
9d5c8243 1099 *
b980ac18
JK		 1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
9d5c8243 1102 **/
53c7d064 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1104{
1105 int err;
1106 int numvecs, i;
1107
53c7d064
SA		 1108 if (!msix)
1109 goto msi_only;
cd14ef54 1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1111
83b7180d 1112 /* Number of supported queues. */
a99955fc 1113 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1118
b980ac18 1119 /* start with one vector for every Rx queue */
047e0030
AD		 1120 numvecs = adapter->num_rx_queues;
1121
b980ac18 1122 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
047e0030
AD		 1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
9d5c8243
AK		 1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
479d02df
AG		 1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
0c2cc02e 1139 return;
9d5c8243
AK		 1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144msi_only:
b709323d 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1146#ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1157 wrfl();
2a3abf6d
AD		 1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
4fc82adf 1162 adapter->vfs_allocated_count = 0;
a99955fc 1163 adapter->rss_queues = 1;
4fc82adf 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1165 adapter->num_rx_queues = 1;
661086df 1166 adapter->num_tx_queues = 1;
047e0030 1167 adapter->num_q_vectors = 1;
9d5c8243 1168 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1169 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1170}
1171
5536d210
AD		 1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
047e0030 1179/**
b980ac18
JK		 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
047e0030 1188 *
b980ac18 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1190 **/
5536d210
AD		 1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
047e0030
AD		 1195{
1196 struct igb_q_vector *q_vector;
5536d210
AD		 1197 struct igb_ring *ring;
1198 int ring_count, size;
047e0030 1199
5536d210
AD		 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
02ef6e1d
CW		 1209 q_vector = adapter->q_vector[v_idx];
1210 if (!q_vector)
1211 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1212 if (!q_vector)
1213 return -ENOMEM;
1214
1215 /* initialize NAPI */
1216 netif_napi_add(adapter->netdev, &q_vector->napi,
1217 igb_poll, 64);
1218
1219 /* tie q_vector and adapter together */
1220 adapter->q_vector[v_idx] = q_vector;
1221 q_vector->adapter = adapter;
1222
1223 /* initialize work limits */
1224 q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226 /* initialize ITR configuration */
1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1228 q_vector->itr_val = IGB_START_ITR;
1229
1230 /* initialize pointer to rings */
1231 ring = q_vector->ring;
1232
4e227667
AD		 1233 /* intialize ITR */
1234 if (rxr_count) {
1235 /* rx or rx/tx vector */
1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237 q_vector->itr_val = adapter->rx_itr_setting;
1238 } else {
1239 /* tx only vector */
1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241 q_vector->itr_val = adapter->tx_itr_setting;
1242 }
1243
5536d210
AD		 1244 if (txr_count) {
1245 /* assign generic ring traits */
1246 ring->dev = &adapter->pdev->dev;
1247 ring->netdev = adapter->netdev;
1248
1249 /* configure backlink on ring */
1250 ring->q_vector = q_vector;
1251
1252 /* update q_vector Tx values */
1253 igb_add_ring(ring, &q_vector->tx);
1254
1255 /* For 82575, context index must be unique per ring. */
1256 if (adapter->hw.mac.type == e1000_82575)
1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259 /* apply Tx specific ring traits */
1260 ring->count = adapter->tx_ring_count;
1261 ring->queue_index = txr_idx;
1262
827da44c
JS		 1263 u64_stats_init(&ring->tx_syncp);
1264 u64_stats_init(&ring->tx_syncp2);
1265
5536d210
AD		 1266 /* assign ring to adapter */
1267 adapter->tx_ring[txr_idx] = ring;
1268
1269 /* push pointer to next ring */
1270 ring++;
047e0030 1271 }
81c2fc22 1272
5536d210
AD		 1273 if (rxr_count) {
1274 /* assign generic ring traits */
1275 ring->dev = &adapter->pdev->dev;
1276 ring->netdev = adapter->netdev;
047e0030 1277
5536d210
AD		 1278 /* configure backlink on ring */
1279 ring->q_vector = q_vector;
047e0030 1280
5536d210
AD		 1281 /* update q_vector Rx values */
1282 igb_add_ring(ring, &q_vector->rx);
047e0030 1283
5536d210
AD		 1284 /* set flag indicating ring supports SCTP checksum offload */
1285 if (adapter->hw.mac.type >= e1000_82576)
1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1287
e52c0f96 1288 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1289 * have the tag byte-swapped.
b980ac18 1290 */
5536d210
AD		 1291 if (adapter->hw.mac.type >= e1000_i350)
1292 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1293
5536d210
AD		 1294 /* apply Rx specific ring traits */
1295 ring->count = adapter->rx_ring_count;
1296 ring->queue_index = rxr_idx;
1297
827da44c
JS		 1298 u64_stats_init(&ring->rx_syncp);
1299
5536d210
AD		 1300 /* assign ring to adapter */
1301 adapter->rx_ring[rxr_idx] = ring;
1302 }
1303
1304 return 0;
047e0030
AD		 1305}
1306
5536d210 1307
047e0030 1308/**
b980ac18
JK		 1309 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1310 * @adapter: board private structure to initialize
047e0030 1311 *
b980ac18
JK		 1312 * We allocate one q_vector per queue interrupt. If allocation fails we
1313 * return -ENOMEM.
047e0030 1314 **/
5536d210 1315static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1316{
5536d210
AD		 1317 int q_vectors = adapter->num_q_vectors;
1318 int rxr_remaining = adapter->num_rx_queues;
1319 int txr_remaining = adapter->num_tx_queues;
1320 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1321 int err;
047e0030 1322
5536d210
AD		 1323 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1324 for (; rxr_remaining; v_idx++) {
1325 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1326 0, 0, 1, rxr_idx);
047e0030 1327
5536d210
AD		 1328 if (err)
1329 goto err_out;
1330
1331 /* update counts and index */
1332 rxr_remaining--;
1333 rxr_idx++;
047e0030 1334 }
047e0030 1335 }
5536d210
AD		 1336
1337 for (; v_idx < q_vectors; v_idx++) {
1338 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1339 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1340
5536d210
AD		 1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1342 tqpv, txr_idx, rqpv, rxr_idx);
1343
1344 if (err)
1345 goto err_out;
1346
1347 /* update counts and index */
1348 rxr_remaining -= rqpv;
1349 txr_remaining -= tqpv;
1350 rxr_idx++;
1351 txr_idx++;
1352 }
1353
047e0030 1354 return 0;
5536d210
AD		 1355
1356err_out:
1357 adapter->num_tx_queues = 0;
1358 adapter->num_rx_queues = 0;
1359 adapter->num_q_vectors = 0;
1360
1361 while (v_idx--)
1362 igb_free_q_vector(adapter, v_idx);
1363
1364 return -ENOMEM;
047e0030
AD		 1365}
1366
1367/**
b980ac18
JK		 1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1369 * @adapter: board private structure to initialize
1370 * @msix: boolean value of MSIX capability
047e0030 1371 *
b980ac18 1372 * This function initializes the interrupts and allocates all of the queues.
047e0030 1373 **/
53c7d064 1374static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1375{
1376 struct pci_dev *pdev = adapter->pdev;
1377 int err;
1378
53c7d064 1379 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1380
1381 err = igb_alloc_q_vectors(adapter);
1382 if (err) {
1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1384 goto err_alloc_q_vectors;
1385 }
1386
5536d210 1387 igb_cache_ring_register(adapter);
047e0030
AD		 1388
1389 return 0;
5536d210 1390
047e0030
AD		 1391err_alloc_q_vectors:
1392 igb_reset_interrupt_capability(adapter);
1393 return err;
1394}
1395
9d5c8243 1396/**
b980ac18
JK		 1397 * igb_request_irq - initialize interrupts
1398 * @adapter: board private structure to initialize
9d5c8243 1399 *
b980ac18
JK		 1400 * Attempts to configure interrupts using the best available
1401 * capabilities of the hardware and kernel.
9d5c8243
AK		 1402 **/
1403static int igb_request_irq(struct igb_adapter *adapter)
1404{
1405 struct net_device *netdev = adapter->netdev;
047e0030 1406 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1407 int err = 0;
1408
cd14ef54 1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1410 err = igb_request_msix(adapter);
844290e5 1411 if (!err)
9d5c8243 1412 goto request_done;
9d5c8243 1413 /* fall back to MSI */
5536d210
AD		 1414 igb_free_all_tx_resources(adapter);
1415 igb_free_all_rx_resources(adapter);
53c7d064 1416
047e0030 1417 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1418 err = igb_init_interrupt_scheme(adapter, false);
1419 if (err)
047e0030 1420 goto request_done;
53c7d064 1421
047e0030
AD		 1422 igb_setup_all_tx_resources(adapter);
1423 igb_setup_all_rx_resources(adapter);
53c7d064 1424 igb_configure(adapter);
9d5c8243 1425 }
844290e5 1426
c74d588e
AD		 1427 igb_assign_vector(adapter->q_vector[0], 0);
1428
7dfc16fa 1429 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1430 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1431 netdev->name, adapter);
9d5c8243
AK		 1432 if (!err)
1433 goto request_done;
047e0030 1434
9d5c8243
AK		 1435 /* fall back to legacy interrupts */
1436 igb_reset_interrupt_capability(adapter);
7dfc16fa 1437 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1438 }
1439
c74d588e 1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1441 netdev->name, adapter);
9d5c8243 1442
6cb5e577 1443 if (err)
c74d588e 1444 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1445 err);
9d5c8243
AK		 1446
1447request_done:
1448 return err;
1449}
1450
1451static void igb_free_irq(struct igb_adapter *adapter)
1452{
cd14ef54 1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1454 int vector = 0, i;
1455
047e0030 1456 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1457
0d1ae7f4 1458 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1459 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1460 adapter->q_vector[i]);
047e0030
AD		 1461 } else {
1462 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1463 }
9d5c8243
AK		 1464}
1465
1466/**
b980ac18
JK		 1467 * igb_irq_disable - Mask off interrupt generation on the NIC
1468 * @adapter: board private structure
9d5c8243
AK		 1469 **/
1470static void igb_irq_disable(struct igb_adapter *adapter)
1471{
1472 struct e1000_hw *hw = &adapter->hw;
1473
b980ac18 1474 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1475 * mapped into these registers and so clearing the bits can cause
1476 * issues on the VF drivers so we only need to clear what we set
1477 */
cd14ef54 1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1479 u32 regval = rd32(E1000_EIAM);
9005df38 1480
2dfd1212
AD		 1481 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1482 wr32(E1000_EIMC, adapter->eims_enable_mask);
1483 regval = rd32(E1000_EIAC);
1484 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1485 }
844290e5
PW		 1486
1487 wr32(E1000_IAM, 0);
9d5c8243
AK		 1488 wr32(E1000_IMC, ~0);
1489 wrfl();
cd14ef54 1490 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1491 int i;
9005df38 1492
81a61859
ET		 1493 for (i = 0; i < adapter->num_q_vectors; i++)
1494 synchronize_irq(adapter->msix_entries[i].vector);
1495 } else {
1496 synchronize_irq(adapter->pdev->irq);
1497 }
9d5c8243
AK		 1498}
1499
1500/**
b980ac18
JK		 1501 * igb_irq_enable - Enable default interrupt generation settings
1502 * @adapter: board private structure
9d5c8243
AK		 1503 **/
1504static void igb_irq_enable(struct igb_adapter *adapter)
1505{
1506 struct e1000_hw *hw = &adapter->hw;
1507
cd14ef54 1508 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1509 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1510 u32 regval = rd32(E1000_EIAC);
9005df38 1511
2dfd1212
AD		 1512 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1513 regval = rd32(E1000_EIAM);
1514 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1515 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1516 if (adapter->vfs_allocated_count) {
4ae196df 1517 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1518 ims |= E1000_IMS_VMMB;
1519 }
1520 wr32(E1000_IMS, ims);
844290e5 1521 } else {
55cac248
AD		 1522 wr32(E1000_IMS, IMS_ENABLE_MASK |
1523 E1000_IMS_DRSTA);
1524 wr32(E1000_IAM, IMS_ENABLE_MASK |
1525 E1000_IMS_DRSTA);
844290e5 1526 }
9d5c8243
AK		 1527}
1528
1529static void igb_update_mng_vlan(struct igb_adapter *adapter)
1530{
51466239 1531 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1532 u16 vid = adapter->hw.mng_cookie.vlan_id;
1533 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1534
1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1536 /* add VID to filter table */
1537 igb_vfta_set(hw, vid, true);
1538 adapter->mng_vlan_id = vid;
1539 } else {
1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1541 }
1542
1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1544 (vid != old_vid) &&
b2cb09b1 1545 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1546 /* remove VID from filter table */
1547 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1548 }
1549}
1550
1551/**
b980ac18
JK		 1552 * igb_release_hw_control - release control of the h/w to f/w
1553 * @adapter: address of board private structure
9d5c8243 1554 *
b980ac18
JK		 1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1556 * For ASF and Pass Through versions of f/w this means that the
1557 * driver is no longer loaded.
9d5c8243
AK		 1558 **/
1559static void igb_release_hw_control(struct igb_adapter *adapter)
1560{
1561 struct e1000_hw *hw = &adapter->hw;
1562 u32 ctrl_ext;
1563
1564 /* Let firmware take over control of h/w */
1565 ctrl_ext = rd32(E1000_CTRL_EXT);
1566 wr32(E1000_CTRL_EXT,
1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1568}
1569
9d5c8243 1570/**
b980ac18
JK		 1571 * igb_get_hw_control - get control of the h/w from f/w
1572 * @adapter: address of board private structure
9d5c8243 1573 *
b980ac18
JK		 1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1575 * For ASF and Pass Through versions of f/w this means that
1576 * the driver is loaded.
9d5c8243
AK		 1577 **/
1578static void igb_get_hw_control(struct igb_adapter *adapter)
1579{
1580 struct e1000_hw *hw = &adapter->hw;
1581 u32 ctrl_ext;
1582
1583 /* Let firmware know the driver has taken over */
1584 ctrl_ext = rd32(E1000_CTRL_EXT);
1585 wr32(E1000_CTRL_EXT,
1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1587}
1588
9d5c8243 1589/**
b980ac18
JK		 1590 * igb_configure - configure the hardware for RX and TX
1591 * @adapter: private board structure
9d5c8243
AK		 1592 **/
1593static void igb_configure(struct igb_adapter *adapter)
1594{
1595 struct net_device *netdev = adapter->netdev;
1596 int i;
1597
1598 igb_get_hw_control(adapter);
ff41f8dc 1599 igb_set_rx_mode(netdev);
9d5c8243
AK		 1600
1601 igb_restore_vlan(adapter);
9d5c8243 1602
85b430b4 1603 igb_setup_tctl(adapter);
06cf2666 1604 igb_setup_mrqc(adapter);
9d5c8243 1605 igb_setup_rctl(adapter);
85b430b4
AD		 1606
1607 igb_configure_tx(adapter);
9d5c8243 1608 igb_configure_rx(adapter);
662d7205
AD		 1609
1610 igb_rx_fifo_flush_82575(&adapter->hw);
1611
c493ea45 1612 /* call igb_desc_unused which always leaves
9d5c8243 1613 * at least 1 descriptor unused to make sure
b980ac18
JK		 1614 * next_to_use != next_to_clean
1615 */
9d5c8243 1616 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1617 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1618 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1619 }
9d5c8243
AK		 1620}
1621
88a268c1 1622/**
b980ac18
JK		 1623 * igb_power_up_link - Power up the phy/serdes link
1624 * @adapter: address of board private structure
88a268c1
NN		 1625 **/
1626void igb_power_up_link(struct igb_adapter *adapter)
1627{
76886596
AA		 1628 igb_reset_phy(&adapter->hw);
1629
88a268c1
NN		 1630 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1631 igb_power_up_phy_copper(&adapter->hw);
1632 else
1633 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1634
1635 igb_setup_link(&adapter->hw);
88a268c1
NN		 1636}
1637
1638/**
b980ac18
JK		 1639 * igb_power_down_link - Power down the phy/serdes link
1640 * @adapter: address of board private structure
88a268c1
NN		 1641 */
1642static void igb_power_down_link(struct igb_adapter *adapter)
1643{
1644 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1645 igb_power_down_phy_copper_82575(&adapter->hw);
1646 else
1647 igb_shutdown_serdes_link_82575(&adapter->hw);
1648}
9d5c8243 1649
56cec249
CW		 1650/**
1651 * Detect and switch function for Media Auto Sense
1652 * @adapter: address of the board private structure
1653 **/
1654static void igb_check_swap_media(struct igb_adapter *adapter)
1655{
1656 struct e1000_hw *hw = &adapter->hw;
1657 u32 ctrl_ext, connsw;
1658 bool swap_now = false;
1659
1660 ctrl_ext = rd32(E1000_CTRL_EXT);
1661 connsw = rd32(E1000_CONNSW);
1662
1663 /* need to live swap if current media is copper and we have fiber/serdes
1664 * to go to.
1665 */
1666
1667 if ((hw->phy.media_type == e1000_media_type_copper) &&
1668 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1669 swap_now = true;
1670 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1671 /* copper signal takes time to appear */
1672 if (adapter->copper_tries < 4) {
1673 adapter->copper_tries++;
1674 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1675 wr32(E1000_CONNSW, connsw);
1676 return;
1677 } else {
1678 adapter->copper_tries = 0;
1679 if ((connsw & E1000_CONNSW_PHYSD) &&
1680 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1681 swap_now = true;
1682 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1683 wr32(E1000_CONNSW, connsw);
1684 }
1685 }
1686 }
1687
1688 if (!swap_now)
1689 return;
1690
1691 switch (hw->phy.media_type) {
1692 case e1000_media_type_copper:
1693 netdev_info(adapter->netdev,
1694 "MAS: changing media to fiber/serdes\n");
1695 ctrl_ext |=
1696 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1697 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1698 adapter->copper_tries = 0;
1699 break;
1700 case e1000_media_type_internal_serdes:
1701 case e1000_media_type_fiber:
1702 netdev_info(adapter->netdev,
1703 "MAS: changing media to copper\n");
1704 ctrl_ext &=
1705 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1706 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1707 break;
1708 default:
1709 /* shouldn't get here during regular operation */
1710 netdev_err(adapter->netdev,
1711 "AMS: Invalid media type found, returning\n");
1712 break;
1713 }
1714 wr32(E1000_CTRL_EXT, ctrl_ext);
1715}
1716
9d5c8243 1717/**
b980ac18
JK		 1718 * igb_up - Open the interface and prepare it to handle traffic
1719 * @adapter: board private structure
9d5c8243 1720 **/
9d5c8243
AK		 1721int igb_up(struct igb_adapter *adapter)
1722{
1723 struct e1000_hw *hw = &adapter->hw;
1724 int i;
1725
1726 /* hardware has been reset, we need to reload some things */
1727 igb_configure(adapter);
1728
1729 clear_bit(__IGB_DOWN, &adapter->state);
1730
0d1ae7f4
AD		 1731 for (i = 0; i < adapter->num_q_vectors; i++)
1732 napi_enable(&(adapter->q_vector[i]->napi));
1733
cd14ef54 1734 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1735 igb_configure_msix(adapter);
feeb2721
AD		 1736 else
1737 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1738
1739 /* Clear any pending interrupts. */
1740 rd32(E1000_ICR);
1741 igb_irq_enable(adapter);
1742
d4960307
AD		 1743 /* notify VFs that reset has been completed */
1744 if (adapter->vfs_allocated_count) {
1745 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1746
d4960307
AD		 1747 reg_data |= E1000_CTRL_EXT_PFRSTD;
1748 wr32(E1000_CTRL_EXT, reg_data);
1749 }
1750
4cb9be7a
JB		 1751 netif_tx_start_all_queues(adapter->netdev);
1752
25568a53
AD		 1753 /* start the watchdog. */
1754 hw->mac.get_link_status = 1;
1755 schedule_work(&adapter->watchdog_task);
1756
f4c01e96
CW		 1757 if ((adapter->flags & IGB_FLAG_EEE) &&
1758 (!hw->dev_spec._82575.eee_disable))
1759 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1760
9d5c8243
AK		 1761 return 0;
1762}
1763
1764void igb_down(struct igb_adapter *adapter)
1765{
9d5c8243 1766 struct net_device *netdev = adapter->netdev;
330a6d6a 1767 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1768 u32 tctl, rctl;
1769 int i;
1770
1771 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1772 * reschedule our watchdog timer
1773 */
9d5c8243
AK		 1774 set_bit(__IGB_DOWN, &adapter->state);
1775
1776 /* disable receives in the hardware */
1777 rctl = rd32(E1000_RCTL);
1778 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1779 /* flush and sleep below */
1780
fd2ea0a7 1781 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1782
1783 /* disable transmits in the hardware */
1784 tctl = rd32(E1000_TCTL);
1785 tctl &= ~E1000_TCTL_EN;
1786 wr32(E1000_TCTL, tctl);
1787 /* flush both disables and wait for them to finish */
1788 wrfl();
0d451e79 1789 usleep_range(10000, 11000);
9d5c8243 1790
41f149a2
CW		 1791 igb_irq_disable(adapter);
1792
aa9b8cc4
AA		 1793 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1794
41f149a2
CW		 1795 for (i = 0; i < adapter->num_q_vectors; i++) {
1796 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1797 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1798 }
9d5c8243 1799
9d5c8243
AK		 1800
1801 del_timer_sync(&adapter->watchdog_timer);
1802 del_timer_sync(&adapter->phy_info_timer);
1803
9d5c8243 1804 netif_carrier_off(netdev);
04fe6358
AD		 1805
1806 /* record the stats before reset*/
12dcd86b
ED		 1807 spin_lock(&adapter->stats64_lock);
1808 igb_update_stats(adapter, &adapter->stats64);
1809 spin_unlock(&adapter->stats64_lock);
04fe6358 1810
9d5c8243
AK		 1811 adapter->link_speed = 0;
1812 adapter->link_duplex = 0;
1813
3023682e
JK		 1814 if (!pci_channel_offline(adapter->pdev))
1815 igb_reset(adapter);
9d5c8243
AK		 1816 igb_clean_all_tx_rings(adapter);
1817 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1818#ifdef CONFIG_IGB_DCA
1819
1820 /* since we reset the hardware DCA settings were cleared */
1821 igb_setup_dca(adapter);
1822#endif
9d5c8243
AK		 1823}
1824
1825void igb_reinit_locked(struct igb_adapter *adapter)
1826{
1827 WARN_ON(in_interrupt());
1828 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1829 usleep_range(1000, 2000);
9d5c8243
AK		 1830 igb_down(adapter);
1831 igb_up(adapter);
1832 clear_bit(__IGB_RESETTING, &adapter->state);
1833}
1834
56cec249
CW		 1835/** igb_enable_mas - Media Autosense re-enable after swap
1836 *
1837 * @adapter: adapter struct
1838 **/
1839static s32 igb_enable_mas(struct igb_adapter *adapter)
1840{
1841 struct e1000_hw *hw = &adapter->hw;
1842 u32 connsw;
1843 s32 ret_val = 0;
1844
1845 connsw = rd32(E1000_CONNSW);
1846 if (!(hw->phy.media_type == e1000_media_type_copper))
1847 return ret_val;
1848
1849 /* configure for SerDes media detect */
1850 if (!(connsw & E1000_CONNSW_SERDESD)) {
1851 connsw |= E1000_CONNSW_ENRGSRC;
1852 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1853 wr32(E1000_CONNSW, connsw);
1854 wrfl();
1855 } else if (connsw & E1000_CONNSW_SERDESD) {
1856 /* already SerDes, no need to enable anything */
1857 return ret_val;
1858 } else {
1859 netdev_info(adapter->netdev,
1860 "MAS: Unable to configure feature, disabling..\n");
1861 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1862 }
1863 return ret_val;
1864}
1865
9d5c8243
AK		 1866void igb_reset(struct igb_adapter *adapter)
1867{
090b1795 1868 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1869 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1870 struct e1000_mac_info *mac = &hw->mac;
1871 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1872 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1873
1874 /* Repartition Pba for greater than 9k mtu
1875 * To take effect CTRL.RST is required.
1876 */
fa4dfae0 1877 switch (mac->type) {
d2ba2ed8 1878 case e1000_i350:
ceb5f13b 1879 case e1000_i354:
55cac248
AD		 1880 case e1000_82580:
1881 pba = rd32(E1000_RXPBS);
1882 pba = igb_rxpbs_adjust_82580(pba);
1883 break;
fa4dfae0 1884 case e1000_82576:
d249be54
AD		 1885 pba = rd32(E1000_RXPBS);
1886 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1887 break;
1888 case e1000_82575:
f96a8a0b
CW		 1889 case e1000_i210:
1890 case e1000_i211:
fa4dfae0
AD		 1891 default:
1892 pba = E1000_PBA_34K;
1893 break;
2d064c06 1894 }
9d5c8243 1895
2d064c06
AD		 1896 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1897 (mac->type < e1000_82576)) {
9d5c8243
AK		 1898 /* adjust PBA for jumbo frames */
1899 wr32(E1000_PBA, pba);
1900
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1906 * expressed in KB.
1907 */
9d5c8243
AK		 1908 pba = rd32(E1000_PBA);
1909 /* upper 16 bits has Tx packet buffer allocation size in KB */
1910 tx_space = pba >> 16;
1911 /* lower 16 bits has Rx packet buffer allocation size in KB */
1912 pba &= 0xffff;
b980ac18
JK		 1913 /* the Tx fifo also stores 16 bytes of information about the Tx
1914 * but don't include ethernet FCS because hardware appends it
1915 */
9d5c8243 1916 min_tx_space = (adapter->max_frame_size +
85e8d004 1917 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1918 ETH_FCS_LEN) * 2;
1919 min_tx_space = ALIGN(min_tx_space, 1024);
1920 min_tx_space >>= 10;
1921 /* software strips receive CRC, so leave room for it */
1922 min_rx_space = adapter->max_frame_size;
1923 min_rx_space = ALIGN(min_rx_space, 1024);
1924 min_rx_space >>= 10;
1925
1926 /* If current Tx allocation is less than the min Tx FIFO size,
1927 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1928 * allocation, take space away from current Rx allocation
1929 */
9d5c8243
AK		 1930 if (tx_space < min_tx_space &&
1931 ((min_tx_space - tx_space) < pba)) {
1932 pba = pba - (min_tx_space - tx_space);
1933
b980ac18
JK		 1934 /* if short on Rx space, Rx wins and must trump Tx
1935 * adjustment
1936 */
9d5c8243
AK		 1937 if (pba < min_rx_space)
1938 pba = min_rx_space;
1939 }
2d064c06 1940 wr32(E1000_PBA, pba);
9d5c8243 1941 }
9d5c8243
AK		 1942
1943 /* flow control settings */
1944 /* The high water mark must be low enough to fit one full frame
1945 * (or the size used for early receive) above it in the Rx FIFO.
1946 * Set it to the lower of:
1947 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1948 * - the full Rx FIFO size minus one full frame
1949 */
9d5c8243 1950 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1951 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1952
d48507fe 1953 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1954 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1955 fc->pause_time = 0xFFFF;
1956 fc->send_xon = 1;
0cce119a 1957 fc->current_mode = fc->requested_mode;
9d5c8243 1958
4ae196df
AD		 1959 /* disable receive for all VFs and wait one second */
1960 if (adapter->vfs_allocated_count) {
1961 int i;
9005df38 1962
4ae196df 1963 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1964 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1965
1966 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1967 igb_ping_all_vfs(adapter);
4ae196df
AD		 1968
1969 /* disable transmits and receives */
1970 wr32(E1000_VFRE, 0);
1971 wr32(E1000_VFTE, 0);
1972 }
1973
9d5c8243 1974 /* Allow time for pending master requests to run */
330a6d6a 1975 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1976 wr32(E1000_WUC, 0);
1977
56cec249
CW		 1978 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1979 /* need to resetup here after media swap */
1980 adapter->ei.get_invariants(hw);
1981 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1982 }
1983 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1984 if (igb_enable_mas(adapter))
1985 dev_err(&pdev->dev,
1986 "Error enabling Media Auto Sense\n");
1987 }
330a6d6a 1988 if (hw->mac.ops.init_hw(hw))
090b1795 1989 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1990
b980ac18 1991 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1992 * control is off when forcing speed.
1993 */
1994 if (!hw->mac.autoneg)
1995 igb_force_mac_fc(hw);
1996
b6e0c419 1997 igb_init_dmac(adapter, pba);
e428893b
CW		 1998#ifdef CONFIG_IGB_HWMON
1999 /* Re-initialize the thermal sensor on i350 devices. */
2000 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2001 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2002 /* If present, re-initialize the external thermal sensor
2003 * interface.
2004 */
2005 if (adapter->ets)
2006 mac->ops.init_thermal_sensor_thresh(hw);
2007 }
2008 }
2009#endif
b936136d 2010 /* Re-establish EEE setting */
f4c01e96
CW		 2011 if (hw->phy.media_type == e1000_media_type_copper) {
2012 switch (mac->type) {
2013 case e1000_i350:
2014 case e1000_i210:
2015 case e1000_i211:
2016 igb_set_eee_i350(hw);
2017 break;
2018 case e1000_i354:
2019 igb_set_eee_i354(hw);
2020 break;
2021 default:
2022 break;
2023 }
2024 }
88a268c1
NN		 2025 if (!netif_running(adapter->netdev))
2026 igb_power_down_link(adapter);
2027
9d5c8243
AK		 2028 igb_update_mng_vlan(adapter);
2029
2030 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2031 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2032
1f6e8178
MV		 2033 /* Re-enable PTP, where applicable. */
2034 igb_ptp_reset(adapter);
1f6e8178 2035
330a6d6a 2036 igb_get_phy_info(hw);
9d5c8243
AK		 2037}
2038
c8f44aff
MM		 2039static netdev_features_t igb_fix_features(struct net_device *netdev,
2040 netdev_features_t features)
b2cb09b1 2041{
b980ac18
JK		 2042 /* Since there is no support for separate Rx/Tx vlan accel
2043 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2044 */
f646968f
PM		 2045 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2046 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2047 else
f646968f 2048 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2049
2050 return features;
2051}
2052
c8f44aff
MM		 2053static int igb_set_features(struct net_device *netdev,
2054 netdev_features_t features)
ac52caa3 2055{
c8f44aff 2056 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2057 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2058
f646968f 2059 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2060 igb_vlan_mode(netdev, features);
2061
89eaefb6
BG		 2062 if (!(changed & NETIF_F_RXALL))
2063 return 0;
2064
2065 netdev->features = features;
2066
2067 if (netif_running(netdev))
2068 igb_reinit_locked(adapter);
2069 else
2070 igb_reset(adapter);
2071
ac52caa3
MM		 2072 return 0;
2073}
2074
2e5c6922 2075static const struct net_device_ops igb_netdev_ops = {
559e9c49 2076 .ndo_open = igb_open,
2e5c6922 2077 .ndo_stop = igb_close,
cd392f5c 2078 .ndo_start_xmit = igb_xmit_frame,
c1ebf46c 2079 .ndo_xmit_flush = igb_xmit_flush,
12dcd86b 2080 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2081 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2082 .ndo_set_mac_address = igb_set_mac,
2083 .ndo_change_mtu = igb_change_mtu,
2084 .ndo_do_ioctl = igb_ioctl,
2085 .ndo_tx_timeout = igb_tx_timeout,
2086 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2087 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2088 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2089 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2090 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2091 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2092 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2093 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2094#ifdef CONFIG_NET_POLL_CONTROLLER
2095 .ndo_poll_controller = igb_netpoll,
2096#endif
b2cb09b1
JP		 2097 .ndo_fix_features = igb_fix_features,
2098 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2099};
2100
d67974f0
CW		 2101/**
2102 * igb_set_fw_version - Configure version string for ethtool
2103 * @adapter: adapter struct
d67974f0
CW		 2104 **/
2105void igb_set_fw_version(struct igb_adapter *adapter)
2106{
2107 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2108 struct e1000_fw_version fw;
2109
2110 igb_get_fw_version(hw, &fw);
2111
2112 switch (hw->mac.type) {
7dc98a62 2113 case e1000_i210:
0b1a6f2e 2114 case e1000_i211:
7dc98a62
CW		 2115 if (!(igb_get_flash_presence_i210(hw))) {
2116 snprintf(adapter->fw_version,
2117 sizeof(adapter->fw_version),
2118 "%2d.%2d-%d",
2119 fw.invm_major, fw.invm_minor,
2120 fw.invm_img_type);
2121 break;
2122 }
2123 /* fall through */
0b1a6f2e
CW		 2124 default:
2125 /* if option is rom valid, display its version too */
2126 if (fw.or_valid) {
2127 snprintf(adapter->fw_version,
2128 sizeof(adapter->fw_version),
2129 "%d.%d, 0x%08x, %d.%d.%d",
2130 fw.eep_major, fw.eep_minor, fw.etrack_id,
2131 fw.or_major, fw.or_build, fw.or_patch);
2132 /* no option rom */
7dc98a62 2133 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2134 snprintf(adapter->fw_version,
7dc98a62
CW		 2135 sizeof(adapter->fw_version),
2136 "%d.%d, 0x%08x",
2137 fw.eep_major, fw.eep_minor, fw.etrack_id);
2138 } else {
2139 snprintf(adapter->fw_version,
2140 sizeof(adapter->fw_version),
2141 "%d.%d.%d",
2142 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2143 }
2144 break;
d67974f0 2145 }
d67974f0
CW		 2146}
2147
56cec249
CW		 2148/**
2149 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2150 *
2151 * @adapter: adapter struct
2152 **/
2153static void igb_init_mas(struct igb_adapter *adapter)
2154{
2155 struct e1000_hw *hw = &adapter->hw;
2156 u16 eeprom_data;
2157
2158 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2159 switch (hw->bus.func) {
2160 case E1000_FUNC_0:
2161 if (eeprom_data & IGB_MAS_ENABLE_0) {
2162 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2163 netdev_info(adapter->netdev,
2164 "MAS: Enabling Media Autosense for port %d\n",
2165 hw->bus.func);
2166 }
2167 break;
2168 case E1000_FUNC_1:
2169 if (eeprom_data & IGB_MAS_ENABLE_1) {
2170 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2171 netdev_info(adapter->netdev,
2172 "MAS: Enabling Media Autosense for port %d\n",
2173 hw->bus.func);
2174 }
2175 break;
2176 case E1000_FUNC_2:
2177 if (eeprom_data & IGB_MAS_ENABLE_2) {
2178 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2179 netdev_info(adapter->netdev,
2180 "MAS: Enabling Media Autosense for port %d\n",
2181 hw->bus.func);
2182 }
2183 break;
2184 case E1000_FUNC_3:
2185 if (eeprom_data & IGB_MAS_ENABLE_3) {
2186 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2187 netdev_info(adapter->netdev,
2188 "MAS: Enabling Media Autosense for port %d\n",
2189 hw->bus.func);
2190 }
2191 break;
2192 default:
2193 /* Shouldn't get here */
2194 netdev_err(adapter->netdev,
2195 "MAS: Invalid port configuration, returning\n");
2196 break;
2197 }
2198}
2199
b980ac18
JK		 2200/**
2201 * igb_init_i2c - Init I2C interface
441fc6fd 2202 * @adapter: pointer to adapter structure
b980ac18 2203 **/
441fc6fd
CW		 2204static s32 igb_init_i2c(struct igb_adapter *adapter)
2205{
23d87824 2206 s32 status = 0;
441fc6fd
CW		 2207
2208 /* I2C interface supported on i350 devices */
2209 if (adapter->hw.mac.type != e1000_i350)
23d87824 2210 return 0;
441fc6fd
CW		 2211
2212 /* Initialize the i2c bus which is controlled by the registers.
2213 * This bus will use the i2c_algo_bit structue that implements
2214 * the protocol through toggling of the 4 bits in the register.
2215 */
2216 adapter->i2c_adap.owner = THIS_MODULE;
2217 adapter->i2c_algo = igb_i2c_algo;
2218 adapter->i2c_algo.data = adapter;
2219 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2220 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2221 strlcpy(adapter->i2c_adap.name, "igb BB",
2222 sizeof(adapter->i2c_adap.name));
2223 status = i2c_bit_add_bus(&adapter->i2c_adap);
2224 return status;
2225}
2226
9d5c8243 2227/**
b980ac18
JK		 2228 * igb_probe - Device Initialization Routine
2229 * @pdev: PCI device information struct
2230 * @ent: entry in igb_pci_tbl
9d5c8243 2231 *
b980ac18 2232 * Returns 0 on success, negative on failure
9d5c8243 2233 *
b980ac18
JK		 2234 * igb_probe initializes an adapter identified by a pci_dev structure.
2235 * The OS initialization, configuring of the adapter private structure,
2236 * and a hardware reset occur.
9d5c8243 2237 **/
1dd06ae8 2238static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2239{
2240 struct net_device *netdev;
2241 struct igb_adapter *adapter;
2242 struct e1000_hw *hw;
4337e993 2243 u16 eeprom_data = 0;
9835fd73 2244 s32 ret_val;
4337e993 2245 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2246 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2247 int err, pci_using_dac;
9835fd73 2248 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2249
bded64a7
AG		 2250 /* Catch broken hardware that put the wrong VF device ID in
2251 * the PCIe SR-IOV capability.
2252 */
2253 if (pdev->is_virtfn) {
2254 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2255 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2256 return -EINVAL;
2257 }
2258
aed5dec3 2259 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2260 if (err)
2261 return err;
2262
2263 pci_using_dac = 0;
dc4ff9bb 2264 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2265 if (!err) {
dc4ff9bb 2266 pci_using_dac = 1;
9d5c8243 2267 } else {
dc4ff9bb 2268 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2269 if (err) {
dc4ff9bb
RK		 2270 dev_err(&pdev->dev,
2271 "No usable DMA configuration, aborting\n");
2272 goto err_dma;
9d5c8243
AK		 2273 }
2274 }
2275
aed5dec3 2276 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2277 IORESOURCE_MEM),
2278 igb_driver_name);
9d5c8243
AK		 2279 if (err)
2280 goto err_pci_reg;
2281
19d5afd4 2282 pci_enable_pcie_error_reporting(pdev);
40a914fa 2283
9d5c8243 2284 pci_set_master(pdev);
c682fc23 2285 pci_save_state(pdev);
9d5c8243
AK		 2286
2287 err = -ENOMEM;
1bfaf07b 2288 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2289 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2290 if (!netdev)
2291 goto err_alloc_etherdev;
2292
2293 SET_NETDEV_DEV(netdev, &pdev->dev);
2294
2295 pci_set_drvdata(pdev, netdev);
2296 adapter = netdev_priv(netdev);
2297 adapter->netdev = netdev;
2298 adapter->pdev = pdev;
2299 hw = &adapter->hw;
2300 hw->back = adapter;
b3f4d599 2301 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2302
9d5c8243 2303 err = -EIO;
89dbefb2 2304 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2305 if (!hw->hw_addr)
9d5c8243
AK		 2306 goto err_ioremap;
2307
2e5c6922 2308 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2309 igb_set_ethtool_ops(netdev);
9d5c8243 2310 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2311
2312 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2313
89dbefb2
AS		 2314 netdev->mem_start = pci_resource_start(pdev, 0);
2315 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2316
9d5c8243
AK		 2317 /* PCI config space info */
2318 hw->vendor_id = pdev->vendor;
2319 hw->device_id = pdev->device;
2320 hw->revision_id = pdev->revision;
2321 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2322 hw->subsystem_device_id = pdev->subsystem_device;
2323
9d5c8243
AK		 2324 /* Copy the default MAC, PHY and NVM function pointers */
2325 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2326 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2327 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2328 /* Initialize skew-specific constants */
2329 err = ei->get_invariants(hw);
2330 if (err)
450c87c8 2331 goto err_sw_init;
9d5c8243 2332
450c87c8 2333 /* setup the private structure */
9d5c8243
AK		 2334 err = igb_sw_init(adapter);
2335 if (err)
2336 goto err_sw_init;
2337
2338 igb_get_bus_info_pcie(hw);
2339
2340 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2341
2342 /* Copper options */
2343 if (hw->phy.media_type == e1000_media_type_copper) {
2344 hw->phy.mdix = AUTO_ALL_MODES;
2345 hw->phy.disable_polarity_correction = false;
2346 hw->phy.ms_type = e1000_ms_hw_default;
2347 }
2348
2349 if (igb_check_reset_block(hw))
2350 dev_info(&pdev->dev,
2351 "PHY reset is blocked due to SOL/IDER session.\n");
2352
b980ac18 2353 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2354 * set by igb_sw_init so we should use an or instead of an
2355 * assignment.
2356 */
2357 netdev->features |= NETIF_F_SG |
2358 NETIF_F_IP_CSUM |
2359 NETIF_F_IPV6_CSUM |
2360 NETIF_F_TSO |
2361 NETIF_F_TSO6 |
2362 NETIF_F_RXHASH |
2363 NETIF_F_RXCSUM |
f646968f
PM		 2364 NETIF_F_HW_VLAN_CTAG_RX |
2365 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2366
2367 /* copy netdev features into list of user selectable features */
2368 netdev->hw_features |= netdev->features;
89eaefb6 2369 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2370
2371 /* set this bit last since it cannot be part of hw_features */
f646968f 2372 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2373
2374 netdev->vlan_features |= NETIF_F_TSO |
2375 NETIF_F_TSO6 |
2376 NETIF_F_IP_CSUM |
2377 NETIF_F_IPV6_CSUM |
2378 NETIF_F_SG;
48f29ffc 2379
6b8f0922
BG		 2380 netdev->priv_flags |= IFF_SUPP_NOFCS;
2381
7b872a55 2382 if (pci_using_dac) {
9d5c8243 2383 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2384 netdev->vlan_features |= NETIF_F_HIGHDMA;
2385 }
9d5c8243 2386
ac52caa3
MM		 2387 if (hw->mac.type >= e1000_82576) {
2388 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2389 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2390 }
b9473560 2391
01789349
JP		 2392 netdev->priv_flags |= IFF_UNICAST_FLT;
2393
330a6d6a 2394 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2395
2396 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2397 * known good starting state
2398 */
9d5c8243
AK		 2399 hw->mac.ops.reset_hw(hw);
2400
ef3a0092
CW		 2401 /* make sure the NVM is good , i211/i210 parts can have special NVM
2402 * that doesn't contain a checksum
f96a8a0b 2403 */
ef3a0092
CW		 2404 switch (hw->mac.type) {
2405 case e1000_i210:
2406 case e1000_i211:
2407 if (igb_get_flash_presence_i210(hw)) {
2408 if (hw->nvm.ops.validate(hw) < 0) {
2409 dev_err(&pdev->dev,
2410 "The NVM Checksum Is Not Valid\n");
2411 err = -EIO;
2412 goto err_eeprom;
2413 }
2414 }
2415 break;
2416 default:
f96a8a0b
CW		 2417 if (hw->nvm.ops.validate(hw) < 0) {
2418 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2419 err = -EIO;
2420 goto err_eeprom;
2421 }
ef3a0092 2422 break;
9d5c8243
AK		 2423 }
2424
2425 /* copy the MAC address out of the NVM */
2426 if (hw->mac.ops.read_mac_addr(hw))
2427 dev_err(&pdev->dev, "NVM Read Error\n");
2428
2429 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2430
aaeb6cdf 2431 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2432 dev_err(&pdev->dev, "Invalid MAC Address\n");
2433 err = -EIO;
2434 goto err_eeprom;
2435 }
2436
d67974f0
CW		 2437 /* get firmware version for ethtool -i */
2438 igb_set_fw_version(adapter);
2439
27dff8b2
TF		 2440 /* configure RXPBSIZE and TXPBSIZE */
2441 if (hw->mac.type == e1000_i210) {
2442 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2443 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2444 }
2445
c061b18d 2446 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2447 (unsigned long) adapter);
c061b18d 2448 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2449 (unsigned long) adapter);
9d5c8243
AK		 2450
2451 INIT_WORK(&adapter->reset_task, igb_reset_task);
2452 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2453
450c87c8 2454 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2455 adapter->fc_autoneg = true;
2456 hw->mac.autoneg = true;
2457 hw->phy.autoneg_advertised = 0x2f;
2458
0cce119a
AD		 2459 hw->fc.requested_mode = e1000_fc_default;
2460 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2461
9d5c8243
AK		 2462 igb_validate_mdi_setting(hw);
2463
63d4a8f9 2464 /* By default, support wake on port A */
a2cf8b6c 2465 if (hw->bus.func == 0)
63d4a8f9
MV		 2466 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2467
2468 /* Check the NVM for wake support on non-port A ports */
2469 if (hw->mac.type >= e1000_82580)
55cac248 2470 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2471 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2472 &eeprom_data);
a2cf8b6c
AD		 2473 else if (hw->bus.func == 1)
2474 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2475
63d4a8f9
MV		 2476 if (eeprom_data & IGB_EEPROM_APME)
2477 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2478
2479 /* now that we have the eeprom settings, apply the special cases where
2480 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2481 * lan on a particular port
2482 */
9d5c8243
AK		 2483 switch (pdev->device) {
2484 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2485 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2486 break;
2487 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2488 case E1000_DEV_ID_82576_FIBER:
2489 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2490 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2491 * regardless of eeprom setting
2492 */
9d5c8243 2493 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2494 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2495 break;
c8ea5ea9 2496 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2497 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2498 /* if quad port adapter, disable WoL on all but port A */
2499 if (global_quad_port_a != 0)
63d4a8f9 2500 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2501 else
2502 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2503 /* Reset for multiple quad port adapters */
2504 if (++global_quad_port_a == 4)
2505 global_quad_port_a = 0;
2506 break;
63d4a8f9
MV		 2507 default:
2508 /* If the device can't wake, don't set software support */
2509 if (!device_can_wakeup(&adapter->pdev->dev))
2510 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2511 }
2512
2513 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2514 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2515 adapter->wol |= E1000_WUFC_MAG;
2516
2517 /* Some vendors want WoL disabled by default, but still supported */
2518 if ((hw->mac.type == e1000_i350) &&
2519 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2520 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2521 adapter->wol = 0;
2522 }
2523
2524 device_set_wakeup_enable(&adapter->pdev->dev,
2525 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2526
2527 /* reset the hardware with the new settings */
2528 igb_reset(adapter);
2529
441fc6fd
CW		 2530 /* Init the I2C interface */
2531 err = igb_init_i2c(adapter);
2532 if (err) {
2533 dev_err(&pdev->dev, "failed to init i2c interface\n");
2534 goto err_eeprom;
2535 }
2536
9d5c8243 2537 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2538 * driver.
2539 */
9d5c8243
AK		 2540 igb_get_hw_control(adapter);
2541
9d5c8243
AK		 2542 strcpy(netdev->name, "eth%d");
2543 err = register_netdev(netdev);
2544 if (err)
2545 goto err_register;
2546
b168dfc5
JB		 2547 /* carrier off reporting is important to ethtool even BEFORE open */
2548 netif_carrier_off(netdev);
2549
421e02f0 2550#ifdef CONFIG_IGB_DCA
bbd98fe4 2551 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2552 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2553 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2554 igb_setup_dca(adapter);
2555 }
fe4506b6 2556
38c845c7 2557#endif
e428893b
CW		 2558#ifdef CONFIG_IGB_HWMON
2559 /* Initialize the thermal sensor on i350 devices. */
2560 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2561 u16 ets_word;
3c89f6d0 2562
b980ac18 2563 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2564 * external thermal sensor.
2565 */
2566 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2567 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2568 adapter->ets = true;
2569 else
2570 adapter->ets = false;
2571 if (igb_sysfs_init(adapter))
2572 dev_err(&pdev->dev,
2573 "failed to allocate sysfs resources\n");
2574 } else {
2575 adapter->ets = false;
2576 }
2577#endif
56cec249
CW		 2578 /* Check if Media Autosense is enabled */
2579 adapter->ei = *ei;
2580 if (hw->dev_spec._82575.mas_capable)
2581 igb_init_mas(adapter);
2582
673b8b70 2583 /* do hw tstamp init after resetting */
7ebae817 2584 igb_ptp_init(adapter);
673b8b70 2585
9d5c8243 2586 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2587 /* print bus type/speed/width info, not applicable to i354 */
2588 if (hw->mac.type != e1000_i354) {
2589 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2590 netdev->name,
2591 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2592 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2593 "unknown"),
2594 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2595 "Width x4" :
2596 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2597 "Width x2" :
2598 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2599 "Width x1" : "unknown"), netdev->dev_addr);
2600 }
9d5c8243 2601
53ea6c7e
TF		 2602 if ((hw->mac.type >= e1000_i210 ||
2603 igb_get_flash_presence_i210(hw))) {
2604 ret_val = igb_read_part_string(hw, part_str,
2605 E1000_PBANUM_LENGTH);
2606 } else {
2607 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2608 }
2609
9835fd73
CW		 2610 if (ret_val)
2611 strcpy(part_str, "Unknown");
2612 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2613 dev_info(&pdev->dev,
2614 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2615 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2616 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2617 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2618 if (hw->phy.media_type == e1000_media_type_copper) {
2619 switch (hw->mac.type) {
2620 case e1000_i350:
2621 case e1000_i210:
2622 case e1000_i211:
2623 /* Enable EEE for internal copper PHY devices */
2624 err = igb_set_eee_i350(hw);
2625 if ((!err) &&
2626 (!hw->dev_spec._82575.eee_disable)) {
2627 adapter->eee_advert =
2628 MDIO_EEE_100TX | MDIO_EEE_1000T;
2629 adapter->flags |= IGB_FLAG_EEE;
2630 }
2631 break;
2632 case e1000_i354:
ceb5f13b 2633 if ((rd32(E1000_CTRL_EXT) &
f4c01e96
CW		 2634 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2635 err = igb_set_eee_i354(hw);
2636 if ((!err) &&
2637 (!hw->dev_spec._82575.eee_disable)) {
2638 adapter->eee_advert =
2639 MDIO_EEE_100TX | MDIO_EEE_1000T;
2640 adapter->flags |= IGB_FLAG_EEE;
2641 }
2642 }
2643 break;
2644 default:
2645 break;
ceb5f13b 2646 }
09b068d4 2647 }
749ab2cd 2648 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2649 return 0;
2650
2651err_register:
2652 igb_release_hw_control(adapter);
441fc6fd 2653 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2654err_eeprom:
2655 if (!igb_check_reset_block(hw))
f5f4cf08 2656 igb_reset_phy(hw);
9d5c8243
AK		 2657
2658 if (hw->flash_address)
2659 iounmap(hw->flash_address);
9d5c8243 2660err_sw_init:
047e0030 2661 igb_clear_interrupt_scheme(adapter);
75009b3a 2662 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2663err_ioremap:
2664 free_netdev(netdev);
2665err_alloc_etherdev:
559e9c49 2666 pci_release_selected_regions(pdev,
b980ac18 2667 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2668err_pci_reg:
2669err_dma:
2670 pci_disable_device(pdev);
2671 return err;
2672}
2673
fa44f2f1 2674#ifdef CONFIG_PCI_IOV
781798a1 2675static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2676{
2677 struct net_device *netdev = pci_get_drvdata(pdev);
2678 struct igb_adapter *adapter = netdev_priv(netdev);
2679 struct e1000_hw *hw = &adapter->hw;
2680
2681 /* reclaim resources allocated to VFs */
2682 if (adapter->vf_data) {
2683 /* disable iov and allow time for transactions to clear */
b09186d2 2684 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2685 dev_warn(&pdev->dev,
2686 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2687 return -EPERM;
2688 } else {
2689 pci_disable_sriov(pdev);
2690 msleep(500);
2691 }
2692
2693 kfree(adapter->vf_data);
2694 adapter->vf_data = NULL;
2695 adapter->vfs_allocated_count = 0;
2696 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2697 wrfl();
2698 msleep(100);
2699 dev_info(&pdev->dev, "IOV Disabled\n");
2700
2701 /* Re-enable DMA Coalescing flag since IOV is turned off */
2702 adapter->flags |= IGB_FLAG_DMAC;
2703 }
2704
2705 return 0;
2706}
2707
2708static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2709{
2710 struct net_device *netdev = pci_get_drvdata(pdev);
2711 struct igb_adapter *adapter = netdev_priv(netdev);
2712 int old_vfs = pci_num_vf(pdev);
2713 int err = 0;
2714 int i;
2715
cd14ef54 2716 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2717 err = -EPERM;
2718 goto out;
2719 }
fa44f2f1
GR		 2720 if (!num_vfs)
2721 goto out;
fa44f2f1 2722
781798a1
SA		 2723 if (old_vfs) {
2724 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2725 old_vfs, max_vfs);
2726 adapter->vfs_allocated_count = old_vfs;
2727 } else
2728 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2729
2730 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2731 sizeof(struct vf_data_storage), GFP_KERNEL);
2732
2733 /* if allocation failed then we do not support SR-IOV */
2734 if (!adapter->vf_data) {
2735 adapter->vfs_allocated_count = 0;
2736 dev_err(&pdev->dev,
2737 "Unable to allocate memory for VF Data Storage\n");
2738 err = -ENOMEM;
2739 goto out;
2740 }
2741
781798a1
SA		 2742 /* only call pci_enable_sriov() if no VFs are allocated already */
2743 if (!old_vfs) {
2744 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2745 if (err)
2746 goto err_out;
2747 }
fa44f2f1
GR		 2748 dev_info(&pdev->dev, "%d VFs allocated\n",
2749 adapter->vfs_allocated_count);
2750 for (i = 0; i < adapter->vfs_allocated_count; i++)
2751 igb_vf_configure(adapter, i);
2752
2753 /* DMA Coalescing is not supported in IOV mode. */
2754 adapter->flags &= ~IGB_FLAG_DMAC;
2755 goto out;
2756
2757err_out:
2758 kfree(adapter->vf_data);
2759 adapter->vf_data = NULL;
2760 adapter->vfs_allocated_count = 0;
2761out:
2762 return err;
2763}
2764
2765#endif
b980ac18 2766/**
441fc6fd
CW		 2767 * igb_remove_i2c - Cleanup I2C interface
2768 * @adapter: pointer to adapter structure
b980ac18 2769 **/
441fc6fd
CW		 2770static void igb_remove_i2c(struct igb_adapter *adapter)
2771{
441fc6fd
CW		 2772 /* free the adapter bus structure */
2773 i2c_del_adapter(&adapter->i2c_adap);
2774}
2775
9d5c8243 2776/**
b980ac18
JK		 2777 * igb_remove - Device Removal Routine
2778 * @pdev: PCI device information struct
9d5c8243 2779 *
b980ac18
JK		 2780 * igb_remove is called by the PCI subsystem to alert the driver
2781 * that it should release a PCI device. The could be caused by a
2782 * Hot-Plug event, or because the driver is going to be removed from
2783 * memory.
9d5c8243 2784 **/
9f9a12f8 2785static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2786{
2787 struct net_device *netdev = pci_get_drvdata(pdev);
2788 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2789 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2790
749ab2cd 2791 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2792#ifdef CONFIG_IGB_HWMON
2793 igb_sysfs_exit(adapter);
2794#endif
441fc6fd 2795 igb_remove_i2c(adapter);
a79f4f88 2796 igb_ptp_stop(adapter);
b980ac18 2797 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2798 * disable watchdog from being rescheduled.
2799 */
9d5c8243
AK		 2800 set_bit(__IGB_DOWN, &adapter->state);
2801 del_timer_sync(&adapter->watchdog_timer);
2802 del_timer_sync(&adapter->phy_info_timer);
2803
760141a5
TH		 2804 cancel_work_sync(&adapter->reset_task);
2805 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2806
421e02f0 2807#ifdef CONFIG_IGB_DCA
7dfc16fa 2808 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2809 dev_info(&pdev->dev, "DCA disabled\n");
2810 dca_remove_requester(&pdev->dev);
7dfc16fa 2811 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2812 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2813 }
2814#endif
2815
9d5c8243 2816 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2817 * would have already happened in close and is redundant.
2818 */
9d5c8243
AK		 2819 igb_release_hw_control(adapter);
2820
2821 unregister_netdev(netdev);
2822
047e0030 2823 igb_clear_interrupt_scheme(adapter);
9d5c8243 2824
37680117 2825#ifdef CONFIG_PCI_IOV
fa44f2f1 2826 igb_disable_sriov(pdev);
37680117 2827#endif
559e9c49 2828
75009b3a 2829 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2830 if (hw->flash_address)
2831 iounmap(hw->flash_address);
559e9c49 2832 pci_release_selected_regions(pdev,
b980ac18 2833 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2834
1128c756 2835 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2836 free_netdev(netdev);
2837
19d5afd4 2838 pci_disable_pcie_error_reporting(pdev);
40a914fa 2839
9d5c8243
AK		 2840 pci_disable_device(pdev);
2841}
2842
a6b623e0 2843/**
b980ac18
JK		 2844 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2845 * @adapter: board private structure to initialize
a6b623e0 2846 *
b980ac18
JK		 2847 * This function initializes the vf specific data storage and then attempts to
2848 * allocate the VFs. The reason for ordering it this way is because it is much
2849 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2850 * the memory for the VFs.
a6b623e0 2851 **/
9f9a12f8 2852static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2853{
2854#ifdef CONFIG_PCI_IOV
2855 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2856 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2857
f96a8a0b
CW		 2858 /* Virtualization features not supported on i210 family. */
2859 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2860 return;
2861
fa44f2f1 2862 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2863 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2864
a6b623e0
AD		 2865#endif /* CONFIG_PCI_IOV */
2866}
2867
fa44f2f1 2868static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2869{
2870 struct e1000_hw *hw = &adapter->hw;
374a542d 2871 u32 max_rss_queues;
9d5c8243 2872
374a542d 2873 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2874 switch (hw->mac.type) {
374a542d
MV		 2875 case e1000_i211:
2876 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2877 break;
2878 case e1000_82575:
f96a8a0b 2879 case e1000_i210:
374a542d
MV		 2880 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2881 break;
2882 case e1000_i350:
2883 /* I350 cannot do RSS and SR-IOV at the same time */
2884 if (!!adapter->vfs_allocated_count) {
2885 max_rss_queues = 1;
2886 break;
2887 }
2888 /* fall through */
2889 case e1000_82576:
2890 if (!!adapter->vfs_allocated_count) {
2891 max_rss_queues = 2;
2892 break;
2893 }
2894 /* fall through */
2895 case e1000_82580:
ceb5f13b 2896 case e1000_i354:
374a542d
MV		 2897 default:
2898 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2899 break;
374a542d
MV		 2900 }
2901
2902 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2903
2904 /* Determine if we need to pair queues. */
2905 switch (hw->mac.type) {
2906 case e1000_82575:
f96a8a0b 2907 case e1000_i211:
374a542d 2908 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2909 break;
374a542d 2910 case e1000_82576:
b980ac18 2911 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2912 * should pair the queues in order to conserve interrupts due
2913 * to limited supply.
2914 */
2915 if ((adapter->rss_queues > 1) &&
2916 (adapter->vfs_allocated_count > 6))
2917 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2918 /* fall through */
2919 case e1000_82580:
2920 case e1000_i350:
ceb5f13b 2921 case e1000_i354:
374a542d 2922 case e1000_i210:
f96a8a0b 2923 default:
b980ac18 2924 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2925 * order to conserve interrupts due to limited supply.
2926 */
2927 if (adapter->rss_queues > (max_rss_queues / 2))
2928 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2929 break;
2930 }
fa44f2f1
GR		 2931}
2932
2933/**
b980ac18
JK		 2934 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2935 * @adapter: board private structure to initialize
fa44f2f1 2936 *
b980ac18
JK		 2937 * igb_sw_init initializes the Adapter private data structure.
2938 * Fields are initialized based on PCI device information and
2939 * OS network device settings (MTU size).
fa44f2f1
GR		 2940 **/
2941static int igb_sw_init(struct igb_adapter *adapter)
2942{
2943 struct e1000_hw *hw = &adapter->hw;
2944 struct net_device *netdev = adapter->netdev;
2945 struct pci_dev *pdev = adapter->pdev;
2946
2947 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2948
2949 /* set default ring sizes */
2950 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2951 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2952
2953 /* set default ITR values */
2954 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2955 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2956
2957 /* set default work limits */
2958 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2959
2960 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2961 VLAN_HLEN;
2962 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2963
2964 spin_lock_init(&adapter->stats64_lock);
2965#ifdef CONFIG_PCI_IOV
2966 switch (hw->mac.type) {
2967 case e1000_82576:
2968 case e1000_i350:
2969 if (max_vfs > 7) {
2970 dev_warn(&pdev->dev,
2971 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2972 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2973 } else
2974 adapter->vfs_allocated_count = max_vfs;
2975 if (adapter->vfs_allocated_count)
2976 dev_warn(&pdev->dev,
2977 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2978 break;
2979 default:
2980 break;
2981 }
2982#endif /* CONFIG_PCI_IOV */
2983
2984 igb_init_queue_configuration(adapter);
a99955fc 2985
1128c756 2986 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2987 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2988 GFP_ATOMIC);
1128c756 2989
a6b623e0 2990 /* This call may decrease the number of queues */
53c7d064 2991 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2992 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2993 return -ENOMEM;
2994 }
2995
a6b623e0
AD		 2996 igb_probe_vfs(adapter);
2997
9d5c8243
AK		 2998 /* Explicitly disable IRQ since the NIC can be in any state. */
2999 igb_irq_disable(adapter);
3000
f96a8a0b 3001 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3002 adapter->flags &= ~IGB_FLAG_DMAC;
3003
9d5c8243
AK		 3004 set_bit(__IGB_DOWN, &adapter->state);
3005 return 0;
3006}
3007
3008/**
b980ac18
JK		 3009 * igb_open - Called when a network interface is made active
3010 * @netdev: network interface device structure
9d5c8243 3011 *
b980ac18 3012 * Returns 0 on success, negative value on failure
9d5c8243 3013 *
b980ac18
JK		 3014 * The open entry point is called when a network interface is made
3015 * active by the system (IFF_UP). At this point all resources needed
3016 * for transmit and receive operations are allocated, the interrupt
3017 * handler is registered with the OS, the watchdog timer is started,
3018 * and the stack is notified that the interface is ready.
9d5c8243 3019 **/
749ab2cd 3020static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3021{
3022 struct igb_adapter *adapter = netdev_priv(netdev);
3023 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3024 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3025 int err;
3026 int i;
3027
3028 /* disallow open during test */
749ab2cd
YZ		 3029 if (test_bit(__IGB_TESTING, &adapter->state)) {
3030 WARN_ON(resuming);
9d5c8243 3031 return -EBUSY;
749ab2cd
YZ		 3032 }
3033
3034 if (!resuming)
3035 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3036
b168dfc5
JB		 3037 netif_carrier_off(netdev);
3038
9d5c8243
AK		 3039 /* allocate transmit descriptors */
3040 err = igb_setup_all_tx_resources(adapter);
3041 if (err)
3042 goto err_setup_tx;
3043
3044 /* allocate receive descriptors */
3045 err = igb_setup_all_rx_resources(adapter);
3046 if (err)
3047 goto err_setup_rx;
3048
88a268c1 3049 igb_power_up_link(adapter);
9d5c8243 3050
9d5c8243
AK		 3051 /* before we allocate an interrupt, we must be ready to handle it.
3052 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3053 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3054 * clean_rx handler before we do so.
3055 */
9d5c8243
AK		 3056 igb_configure(adapter);
3057
3058 err = igb_request_irq(adapter);
3059 if (err)
3060 goto err_req_irq;
3061
0c2cc02e
AD		 3062 /* Notify the stack of the actual queue counts. */
3063 err = netif_set_real_num_tx_queues(adapter->netdev,
3064 adapter->num_tx_queues);
3065 if (err)
3066 goto err_set_queues;
3067
3068 err = netif_set_real_num_rx_queues(adapter->netdev,
3069 adapter->num_rx_queues);
3070 if (err)
3071 goto err_set_queues;
3072
9d5c8243
AK		 3073 /* From here on the code is the same as igb_up() */
3074 clear_bit(__IGB_DOWN, &adapter->state);
3075
0d1ae7f4
AD		 3076 for (i = 0; i < adapter->num_q_vectors; i++)
3077 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3078
3079 /* Clear any pending interrupts. */
3080 rd32(E1000_ICR);
844290e5
PW		 3081
3082 igb_irq_enable(adapter);
3083
d4960307
AD		 3084 /* notify VFs that reset has been completed */
3085 if (adapter->vfs_allocated_count) {
3086 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3087
d4960307
AD		 3088 reg_data |= E1000_CTRL_EXT_PFRSTD;
3089 wr32(E1000_CTRL_EXT, reg_data);
3090 }
3091
d55b53ff
JK		 3092 netif_tx_start_all_queues(netdev);
3093
749ab2cd
YZ		 3094 if (!resuming)
3095 pm_runtime_put(&pdev->dev);
3096
25568a53
AD		 3097 /* start the watchdog. */
3098 hw->mac.get_link_status = 1;
3099 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3100
3101 return 0;
3102
0c2cc02e
AD		 3103err_set_queues:
3104 igb_free_irq(adapter);
9d5c8243
AK		 3105err_req_irq:
3106 igb_release_hw_control(adapter);
88a268c1 3107 igb_power_down_link(adapter);
9d5c8243
AK		 3108 igb_free_all_rx_resources(adapter);
3109err_setup_rx:
3110 igb_free_all_tx_resources(adapter);
3111err_setup_tx:
3112 igb_reset(adapter);
749ab2cd
YZ		 3113 if (!resuming)
3114 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3115
3116 return err;
3117}
3118
749ab2cd
YZ		 3119static int igb_open(struct net_device *netdev)
3120{
3121 return __igb_open(netdev, false);
3122}
3123
9d5c8243 3124/**
b980ac18
JK		 3125 * igb_close - Disables a network interface
3126 * @netdev: network interface device structure
9d5c8243 3127 *
b980ac18 3128 * Returns 0, this is not allowed to fail
9d5c8243 3129 *
b980ac18
JK		 3130 * The close entry point is called when an interface is de-activated
3131 * by the OS. The hardware is still under the driver's control, but
3132 * needs to be disabled. A global MAC reset is issued to stop the
3133 * hardware, and all transmit and receive resources are freed.
9d5c8243 3134 **/
749ab2cd 3135static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3136{
3137 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3138 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3139
3140 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3141
749ab2cd
YZ		 3142 if (!suspending)
3143 pm_runtime_get_sync(&pdev->dev);
3144
3145 igb_down(adapter);
9d5c8243
AK		 3146 igb_free_irq(adapter);
3147
3148 igb_free_all_tx_resources(adapter);
3149 igb_free_all_rx_resources(adapter);
3150
749ab2cd
YZ		 3151 if (!suspending)
3152 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3153 return 0;
3154}
3155
749ab2cd
YZ		 3156static int igb_close(struct net_device *netdev)
3157{
3158 return __igb_close(netdev, false);
3159}
3160
9d5c8243 3161/**
b980ac18
JK		 3162 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3163 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3164 *
b980ac18 3165 * Return 0 on success, negative on failure
9d5c8243 3166 **/
80785298 3167int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3168{
59d71989 3169 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3170 int size;
3171
06034649 3172 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3173
3174 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3175 if (!tx_ring->tx_buffer_info)
9d5c8243 3176 goto err;
9d5c8243
AK		 3177
3178 /* round up to nearest 4K */
85e8d004 3179 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3180 tx_ring->size = ALIGN(tx_ring->size, 4096);
3181
5536d210
AD		 3182 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3183 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3184 if (!tx_ring->desc)
3185 goto err;
3186
9d5c8243
AK		 3187 tx_ring->next_to_use = 0;
3188 tx_ring->next_to_clean = 0;
81c2fc22 3189
9d5c8243
AK		 3190 return 0;
3191
3192err:
06034649 3193 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3194 tx_ring->tx_buffer_info = NULL;
3195 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3196 return -ENOMEM;
3197}
3198
3199/**
b980ac18
JK		 3200 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3201 * (Descriptors) for all queues
3202 * @adapter: board private structure
9d5c8243 3203 *
b980ac18 3204 * Return 0 on success, negative on failure
9d5c8243
AK		 3205 **/
3206static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3207{
439705e1 3208 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3209 int i, err = 0;
3210
3211 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3212 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3213 if (err) {
439705e1 3214 dev_err(&pdev->dev,
9d5c8243
AK		 3215 "Allocation for Tx Queue %u failed\n", i);
3216 for (i--; i >= 0; i--)
3025a446 3217 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3218 break;
3219 }
3220 }
3221
3222 return err;
3223}
3224
3225/**
b980ac18
JK		 3226 * igb_setup_tctl - configure the transmit control registers
3227 * @adapter: Board private structure
9d5c8243 3228 **/
d7ee5b3a 3229void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3230{
9d5c8243
AK		 3231 struct e1000_hw *hw = &adapter->hw;
3232 u32 tctl;
9d5c8243 3233
85b430b4
AD		 3234 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3235 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3236
3237 /* Program the Transmit Control Register */
9d5c8243
AK		 3238 tctl = rd32(E1000_TCTL);
3239 tctl &= ~E1000_TCTL_CT;
3240 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3241 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3242
3243 igb_config_collision_dist(hw);
3244
9d5c8243
AK		 3245 /* Enable transmits */
3246 tctl |= E1000_TCTL_EN;
3247
3248 wr32(E1000_TCTL, tctl);
3249}
3250
85b430b4 3251/**
b980ac18
JK		 3252 * igb_configure_tx_ring - Configure transmit ring after Reset
3253 * @adapter: board private structure
3254 * @ring: tx ring to configure
85b430b4 3255 *
b980ac18 3256 * Configure a transmit ring after a reset.
85b430b4 3257 **/
d7ee5b3a 3258void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3259 struct igb_ring *ring)
85b430b4
AD		 3260{
3261 struct e1000_hw *hw = &adapter->hw;
a74420e0 3262 u32 txdctl = 0;
85b430b4
AD		 3263 u64 tdba = ring->dma;
3264 int reg_idx = ring->reg_idx;
3265
3266 /* disable the queue */
a74420e0 3267 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3268 wrfl();
3269 mdelay(10);
3270
3271 wr32(E1000_TDLEN(reg_idx),
b980ac18 3272 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3273 wr32(E1000_TDBAL(reg_idx),
b980ac18 3274 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3275 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3276
fce99e34 3277 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3278 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3279 writel(0, ring->tail);
85b430b4
AD		 3280
3281 txdctl |= IGB_TX_PTHRESH;
3282 txdctl |= IGB_TX_HTHRESH << 8;
3283 txdctl |= IGB_TX_WTHRESH << 16;
3284
3285 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3286 wr32(E1000_TXDCTL(reg_idx), txdctl);
3287}
3288
3289/**
b980ac18
JK		 3290 * igb_configure_tx - Configure transmit Unit after Reset
3291 * @adapter: board private structure
85b430b4 3292 *
b980ac18 3293 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3294 **/
3295static void igb_configure_tx(struct igb_adapter *adapter)
3296{
3297 int i;
3298
3299 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3300 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3301}
3302
9d5c8243 3303/**
b980ac18
JK		 3304 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3305 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3306 *
b980ac18 3307 * Returns 0 on success, negative on failure
9d5c8243 3308 **/
80785298 3309int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3310{
59d71989 3311 struct device *dev = rx_ring->dev;
f33005a6 3312 int size;
9d5c8243 3313
06034649 3314 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3315
3316 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3317 if (!rx_ring->rx_buffer_info)
9d5c8243 3318 goto err;
9d5c8243 3319
9d5c8243 3320 /* Round up to nearest 4K */
f33005a6 3321 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3322 rx_ring->size = ALIGN(rx_ring->size, 4096);
3323
5536d210
AD		 3324 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3325 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3326 if (!rx_ring->desc)
3327 goto err;
3328
cbc8e55f 3329 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3330 rx_ring->next_to_clean = 0;
3331 rx_ring->next_to_use = 0;
9d5c8243 3332
9d5c8243
AK		 3333 return 0;
3334
3335err:
06034649
AD		 3336 vfree(rx_ring->rx_buffer_info);
3337 rx_ring->rx_buffer_info = NULL;
f33005a6 3338 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3339 return -ENOMEM;
3340}
3341
3342/**
b980ac18
JK		 3343 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3344 * (Descriptors) for all queues
3345 * @adapter: board private structure
9d5c8243 3346 *
b980ac18 3347 * Return 0 on success, negative on failure
9d5c8243
AK		 3348 **/
3349static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3350{
439705e1 3351 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3352 int i, err = 0;
3353
3354 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3355 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3356 if (err) {
439705e1 3357 dev_err(&pdev->dev,
9d5c8243
AK		 3358 "Allocation for Rx Queue %u failed\n", i);
3359 for (i--; i >= 0; i--)
3025a446 3360 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3361 break;
3362 }
3363 }
3364
3365 return err;
3366}
3367
06cf2666 3368/**
b980ac18
JK		 3369 * igb_setup_mrqc - configure the multiple receive queue control registers
3370 * @adapter: Board private structure
06cf2666
AD		 3371 **/
3372static void igb_setup_mrqc(struct igb_adapter *adapter)
3373{
3374 struct e1000_hw *hw = &adapter->hw;
3375 u32 mrqc, rxcsum;
ed12cc9a 3376 u32 j, num_rx_queues;
a57fe23e
AD		 3377 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3378 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3379 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3380 0xFA01ACBE };
06cf2666
AD		 3381
3382 /* Fill out hash function seeds */
a57fe23e
AD		 3383 for (j = 0; j < 10; j++)
3384 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3385
a99955fc 3386 num_rx_queues = adapter->rss_queues;
06cf2666 3387
797fd4be 3388 switch (hw->mac.type) {
797fd4be
AD		 3389 case e1000_82576:
3390 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3391 if (adapter->vfs_allocated_count)
06cf2666 3392 num_rx_queues = 2;
797fd4be
AD		 3393 break;
3394 default:
3395 break;
06cf2666
AD		 3396 }
3397
ed12cc9a
LMV		 3398 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3399 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3400 adapter->rss_indir_tbl[j] =
3401 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3402 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3403 }
ed12cc9a 3404 igb_write_rss_indir_tbl(adapter);
06cf2666 3405
b980ac18 3406 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3407 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3408 * offloads as they are enabled by default
3409 */
3410 rxcsum = rd32(E1000_RXCSUM);
3411 rxcsum |= E1000_RXCSUM_PCSD;
3412
3413 if (adapter->hw.mac.type >= e1000_82576)
3414 /* Enable Receive Checksum Offload for SCTP */
3415 rxcsum |= E1000_RXCSUM_CRCOFL;
3416
3417 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3418 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3419
039454a8
AA		 3420 /* Generate RSS hash based on packet types, TCP/UDP
3421 * port numbers and/or IPv4/v6 src and dst addresses
3422 */
f96a8a0b
CW		 3423 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3424 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3425 E1000_MRQC_RSS_FIELD_IPV6 |
3426 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3427 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3428
039454a8
AA		 3429 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3430 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3431 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3432 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3433
06cf2666
AD		 3434 /* If VMDq is enabled then we set the appropriate mode for that, else
3435 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3436 * if we are only using one queue
3437 */
06cf2666
AD		 3438 if (adapter->vfs_allocated_count) {
3439 if (hw->mac.type > e1000_82575) {
3440 /* Set the default pool for the PF's first queue */
3441 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3442
06cf2666
AD		 3443 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3444 E1000_VT_CTL_DISABLE_DEF_POOL);
3445 vtctl |= adapter->vfs_allocated_count <<
3446 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3447 wr32(E1000_VT_CTL, vtctl);
3448 }
a99955fc 3449 if (adapter->rss_queues > 1)
f96a8a0b 3450 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3451 else
f96a8a0b 3452 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3453 } else {
f96a8a0b
CW		 3454 if (hw->mac.type != e1000_i211)
3455 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3456 }
3457 igb_vmm_control(adapter);
3458
06cf2666
AD		 3459 wr32(E1000_MRQC, mrqc);
3460}
3461
9d5c8243 3462/**
b980ac18
JK		 3463 * igb_setup_rctl - configure the receive control registers
3464 * @adapter: Board private structure
9d5c8243 3465 **/
d7ee5b3a 3466void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3467{
3468 struct e1000_hw *hw = &adapter->hw;
3469 u32 rctl;
9d5c8243
AK		 3470
3471 rctl = rd32(E1000_RCTL);
3472
3473 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3474 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3475
69d728ba 3476 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3477 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3478
b980ac18 3479 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3480 * redirection as it did with e1000. Newer features require
3481 * that the HW strips the CRC.
73cd78f1 3482 */
87cb7e8c 3483 rctl |= E1000_RCTL_SECRC;
9d5c8243 3484
559e9c49 3485 /* disable store bad packets and clear size bits. */
ec54d7d6 3486 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3487
6ec43fe6
AD		 3488 /* enable LPE to prevent packets larger than max_frame_size */
3489 rctl |= E1000_RCTL_LPE;
9d5c8243 3490
952f72a8
AD		 3491 /* disable queue 0 to prevent tail write w/o re-config */
3492 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3493
e1739522
AD		 3494 /* Attention!!! For SR-IOV PF driver operations you must enable
3495 * queue drop for all VF and PF queues to prevent head of line blocking
3496 * if an un-trusted VF does not provide descriptors to hardware.
3497 */
3498 if (adapter->vfs_allocated_count) {
e1739522
AD		 3499 /* set all queue drop enable bits */
3500 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3501 }
3502
89eaefb6
BG		 3503 /* This is useful for sniffing bad packets. */
3504 if (adapter->netdev->features & NETIF_F_RXALL) {
3505 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3506 * in e1000e_set_rx_mode
3507 */
89eaefb6
BG		 3508 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3509 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3510 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3511
3512 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3513 E1000_RCTL_DPF | /* Allow filtered pause */
3514 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3515 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3516 * and that breaks VLANs.
3517 */
3518 }
3519
9d5c8243
AK		 3520 wr32(E1000_RCTL, rctl);
3521}
3522
7d5753f0 3523static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3524 int vfn)
7d5753f0
AD		 3525{
3526 struct e1000_hw *hw = &adapter->hw;
3527 u32 vmolr;
3528
3529 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3530 * increase the size to support vlan tags
3531 */
7d5753f0
AD		 3532 if (vfn < adapter->vfs_allocated_count &&
3533 adapter->vf_data[vfn].vlans_enabled)
3534 size += VLAN_TAG_SIZE;
3535
3536 vmolr = rd32(E1000_VMOLR(vfn));
3537 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3538 vmolr |= size | E1000_VMOLR_LPE;
3539 wr32(E1000_VMOLR(vfn), vmolr);
3540
3541 return 0;
3542}
3543
e1739522 3544/**
b980ac18
JK		 3545 * igb_rlpml_set - set maximum receive packet size
3546 * @adapter: board private structure
e1739522 3547 *
b980ac18 3548 * Configure maximum receivable packet size.
e1739522
AD		 3549 **/
3550static void igb_rlpml_set(struct igb_adapter *adapter)
3551{
153285f9 3552 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3553 struct e1000_hw *hw = &adapter->hw;
3554 u16 pf_id = adapter->vfs_allocated_count;
3555
e1739522
AD		 3556 if (pf_id) {
3557 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3558 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3559 * to our max jumbo frame size, in case we need to enable
3560 * jumbo frames on one of the rings later.
3561 * This will not pass over-length frames into the default
3562 * queue because it's gated by the VMOLR.RLPML.
3563 */
7d5753f0 3564 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3565 }
3566
3567 wr32(E1000_RLPML, max_frame_size);
3568}
3569
8151d294
WM		 3570static inline void igb_set_vmolr(struct igb_adapter *adapter,
3571 int vfn, bool aupe)
7d5753f0
AD		 3572{
3573 struct e1000_hw *hw = &adapter->hw;
3574 u32 vmolr;
3575
b980ac18 3576 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3577 * we should exit and do nothing
3578 */
3579 if (hw->mac.type < e1000_82576)
3580 return;
3581
3582 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3583 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3584 if (hw->mac.type == e1000_i350) {
3585 u32 dvmolr;
3586
3587 dvmolr = rd32(E1000_DVMOLR(vfn));
3588 dvmolr |= E1000_DVMOLR_STRVLAN;
3589 wr32(E1000_DVMOLR(vfn), dvmolr);
3590 }
8151d294 3591 if (aupe)
b980ac18 3592 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3593 else
3594 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3595
3596 /* clear all bits that might not be set */
3597 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3598
a99955fc 3599 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3600 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3601 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3602 * multicast packets
3603 */
3604 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3605 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3606
3607 wr32(E1000_VMOLR(vfn), vmolr);
3608}
3609
85b430b4 3610/**
b980ac18
JK		 3611 * igb_configure_rx_ring - Configure a receive ring after Reset
3612 * @adapter: board private structure
3613 * @ring: receive ring to be configured
85b430b4 3614 *
b980ac18 3615 * Configure the Rx unit of the MAC after a reset.
85b430b4 3616 **/
d7ee5b3a 3617void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3618 struct igb_ring *ring)
85b430b4
AD		 3619{
3620 struct e1000_hw *hw = &adapter->hw;
3621 u64 rdba = ring->dma;
3622 int reg_idx = ring->reg_idx;
a74420e0 3623 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3624
3625 /* disable the queue */
a74420e0 3626 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3627
3628 /* Set DMA base address registers */
3629 wr32(E1000_RDBAL(reg_idx),
3630 rdba & 0x00000000ffffffffULL);
3631 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3632 wr32(E1000_RDLEN(reg_idx),
b980ac18 3633 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3634
3635 /* initialize head and tail */
fce99e34 3636 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3637 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3638 writel(0, ring->tail);
85b430b4 3639
952f72a8 3640 /* set descriptor configuration */
44390ca6 3641 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3642 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3643 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3644 if (hw->mac.type >= e1000_82580)
757b77e2 3645 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3646 /* Only set Drop Enable if we are supporting multiple queues */
3647 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3648 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3649
3650 wr32(E1000_SRRCTL(reg_idx), srrctl);
3651
7d5753f0 3652 /* set filtering for VMDQ pools */
8151d294 3653 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3654
85b430b4
AD		 3655 rxdctl |= IGB_RX_PTHRESH;
3656 rxdctl |= IGB_RX_HTHRESH << 8;
3657 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3658
3659 /* enable receive descriptor fetching */
3660 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3661 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3662}
3663
9d5c8243 3664/**
b980ac18
JK		 3665 * igb_configure_rx - Configure receive Unit after Reset
3666 * @adapter: board private structure
9d5c8243 3667 *
b980ac18 3668 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3669 **/
3670static void igb_configure_rx(struct igb_adapter *adapter)
3671{
9107584e 3672 int i;
9d5c8243 3673
68d480c4
AD		 3674 /* set UTA to appropriate mode */
3675 igb_set_uta(adapter);
3676
26ad9178
AD		 3677 /* set the correct pool for the PF default MAC address in entry 0 */
3678 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3679 adapter->vfs_allocated_count);
26ad9178 3680
06cf2666 3681 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3682 * the Base and Length of the Rx Descriptor Ring
3683 */
f9d40f6a
AD		 3684 for (i = 0; i < adapter->num_rx_queues; i++)
3685 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3686}
3687
3688/**
b980ac18
JK		 3689 * igb_free_tx_resources - Free Tx Resources per Queue
3690 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3691 *
b980ac18 3692 * Free all transmit software resources
9d5c8243 3693 **/
68fd9910 3694void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3695{
3b644cf6 3696 igb_clean_tx_ring(tx_ring);
9d5c8243 3697
06034649
AD		 3698 vfree(tx_ring->tx_buffer_info);
3699 tx_ring->tx_buffer_info = NULL;
9d5c8243 3700
439705e1
AD		 3701 /* if not set, then don't free */
3702 if (!tx_ring->desc)
3703 return;
3704
59d71989
AD		 3705 dma_free_coherent(tx_ring->dev, tx_ring->size,
3706 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3707
3708 tx_ring->desc = NULL;
3709}
3710
3711/**
b980ac18
JK		 3712 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3713 * @adapter: board private structure
9d5c8243 3714 *
b980ac18 3715 * Free all transmit software resources
9d5c8243
AK		 3716 **/
3717static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3718{
3719 int i;
3720
3721 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3722 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3723}
3724
ebe42d16
AD		 3725void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3726 struct igb_tx_buffer *tx_buffer)
3727{
3728 if (tx_buffer->skb) {
3729 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3730 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3731 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3732 dma_unmap_addr(tx_buffer, dma),
3733 dma_unmap_len(tx_buffer, len),
ebe42d16 3734 DMA_TO_DEVICE);
c9f14bf3 3735 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3736 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3737 dma_unmap_addr(tx_buffer, dma),
3738 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3739 DMA_TO_DEVICE);
3740 }
3741 tx_buffer->next_to_watch = NULL;
3742 tx_buffer->skb = NULL;
c9f14bf3 3743 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3744 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3745}
3746
3747/**
b980ac18
JK		 3748 * igb_clean_tx_ring - Free Tx Buffers
3749 * @tx_ring: ring to be cleaned
9d5c8243 3750 **/
3b644cf6 3751static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3752{
06034649 3753 struct igb_tx_buffer *buffer_info;
9d5c8243 3754 unsigned long size;
6ad4edfc 3755 u16 i;
9d5c8243 3756
06034649 3757 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3758 return;
3759 /* Free all the Tx ring sk_buffs */
3760
3761 for (i = 0; i < tx_ring->count; i++) {
06034649 3762 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3763 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3764 }
3765
dad8a3b3
JF		 3766 netdev_tx_reset_queue(txring_txq(tx_ring));
3767
06034649
AD		 3768 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3769 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3770
3771 /* Zero out the descriptor ring */
9d5c8243
AK		 3772 memset(tx_ring->desc, 0, tx_ring->size);
3773
3774 tx_ring->next_to_use = 0;
3775 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3776}
3777
3778/**
b980ac18
JK		 3779 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3780 * @adapter: board private structure
9d5c8243
AK		 3781 **/
3782static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3783{
3784 int i;
3785
3786 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3787 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3788}
3789
3790/**
b980ac18
JK		 3791 * igb_free_rx_resources - Free Rx Resources
3792 * @rx_ring: ring to clean the resources from
9d5c8243 3793 *
b980ac18 3794 * Free all receive software resources
9d5c8243 3795 **/
68fd9910 3796void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3797{
3b644cf6 3798 igb_clean_rx_ring(rx_ring);
9d5c8243 3799
06034649
AD		 3800 vfree(rx_ring->rx_buffer_info);
3801 rx_ring->rx_buffer_info = NULL;
9d5c8243 3802
439705e1
AD		 3803 /* if not set, then don't free */
3804 if (!rx_ring->desc)
3805 return;
3806
59d71989
AD		 3807 dma_free_coherent(rx_ring->dev, rx_ring->size,
3808 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3809
3810 rx_ring->desc = NULL;
3811}
3812
3813/**
b980ac18
JK		 3814 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3815 * @adapter: board private structure
9d5c8243 3816 *
b980ac18 3817 * Free all receive software resources
9d5c8243
AK		 3818 **/
3819static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3820{
3821 int i;
3822
3823 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3824 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3825}
3826
3827/**
b980ac18
JK		 3828 * igb_clean_rx_ring - Free Rx Buffers per Queue
3829 * @rx_ring: ring to free buffers from
9d5c8243 3830 **/
3b644cf6 3831static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3832{
9d5c8243 3833 unsigned long size;
c023cd88 3834 u16 i;
9d5c8243 3835
1a1c225b
AD		 3836 if (rx_ring->skb)
3837 dev_kfree_skb(rx_ring->skb);
3838 rx_ring->skb = NULL;
3839
06034649 3840 if (!rx_ring->rx_buffer_info)
9d5c8243 3841 return;
439705e1 3842
9d5c8243
AK		 3843 /* Free all the Rx ring sk_buffs */
3844 for (i = 0; i < rx_ring->count; i++) {
06034649 3845 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3846
cbc8e55f
AD		 3847 if (!buffer_info->page)
3848 continue;
3849
3850 dma_unmap_page(rx_ring->dev,
3851 buffer_info->dma,
3852 PAGE_SIZE,
3853 DMA_FROM_DEVICE);
3854 __free_page(buffer_info->page);
3855
1a1c225b 3856 buffer_info->page = NULL;
9d5c8243
AK		 3857 }
3858
06034649
AD		 3859 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3860 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3861
3862 /* Zero out the descriptor ring */
3863 memset(rx_ring->desc, 0, rx_ring->size);
3864
cbc8e55f 3865 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3866 rx_ring->next_to_clean = 0;
3867 rx_ring->next_to_use = 0;
9d5c8243
AK		 3868}
3869
3870/**
b980ac18
JK		 3871 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3872 * @adapter: board private structure
9d5c8243
AK		 3873 **/
3874static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3875{
3876 int i;
3877
3878 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3879 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3880}
3881
3882/**
b980ac18
JK		 3883 * igb_set_mac - Change the Ethernet Address of the NIC
3884 * @netdev: network interface device structure
3885 * @p: pointer to an address structure
9d5c8243 3886 *
b980ac18 3887 * Returns 0 on success, negative on failure
9d5c8243
AK		 3888 **/
3889static int igb_set_mac(struct net_device *netdev, void *p)
3890{
3891 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3892 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3893 struct sockaddr *addr = p;
3894
3895 if (!is_valid_ether_addr(addr->sa_data))
3896 return -EADDRNOTAVAIL;
3897
3898 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3899 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3900
26ad9178
AD		 3901 /* set the correct pool for the new PF MAC address in entry 0 */
3902 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3903 adapter->vfs_allocated_count);
e1739522 3904
9d5c8243
AK		 3905 return 0;
3906}
3907
3908/**
b980ac18
JK		 3909 * igb_write_mc_addr_list - write multicast addresses to MTA
3910 * @netdev: network interface device structure
9d5c8243 3911 *
b980ac18
JK		 3912 * Writes multicast address list to the MTA hash table.
3913 * Returns: -ENOMEM on failure
3914 * 0 on no addresses written
3915 * X on writing X addresses to MTA
9d5c8243 3916 **/
68d480c4 3917static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3918{
3919 struct igb_adapter *adapter = netdev_priv(netdev);
3920 struct e1000_hw *hw = &adapter->hw;
22bedad3 3921 struct netdev_hw_addr *ha;
68d480c4 3922 u8 *mta_list;
9d5c8243
AK		 3923 int i;
3924
4cd24eaf 3925 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3926 /* nothing to program, so clear mc list */
3927 igb_update_mc_addr_list(hw, NULL, 0);
3928 igb_restore_vf_multicasts(adapter);
3929 return 0;
3930 }
9d5c8243 3931
4cd24eaf 3932 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3933 if (!mta_list)
3934 return -ENOMEM;
ff41f8dc 3935
68d480c4 3936 /* The shared function expects a packed array of only addresses. */
48e2f183 3937 i = 0;
22bedad3
JP		 3938 netdev_for_each_mc_addr(ha, netdev)
3939 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3940
68d480c4
AD		 3941 igb_update_mc_addr_list(hw, mta_list, i);
3942 kfree(mta_list);
3943
4cd24eaf 3944 return netdev_mc_count(netdev);
68d480c4
AD		 3945}
3946
3947/**
b980ac18
JK		 3948 * igb_write_uc_addr_list - write unicast addresses to RAR table
3949 * @netdev: network interface device structure
68d480c4 3950 *
b980ac18
JK		 3951 * Writes unicast address list to the RAR table.
3952 * Returns: -ENOMEM on failure/insufficient address space
3953 * 0 on no addresses written
3954 * X on writing X addresses to the RAR table
68d480c4
AD		 3955 **/
3956static int igb_write_uc_addr_list(struct net_device *netdev)
3957{
3958 struct igb_adapter *adapter = netdev_priv(netdev);
3959 struct e1000_hw *hw = &adapter->hw;
3960 unsigned int vfn = adapter->vfs_allocated_count;
3961 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3962 int count = 0;
3963
3964 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3965 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3966 return -ENOMEM;
9d5c8243 3967
32e7bfc4 3968 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3969 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3970
3971 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3972 if (!rar_entries)
3973 break;
26ad9178 3974 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3975 rar_entries--,
3976 vfn);
68d480c4 3977 count++;
ff41f8dc
AD		 3978 }
3979 }
3980 /* write the addresses in reverse order to avoid write combining */
3981 for (; rar_entries > 0 ; rar_entries--) {
3982 wr32(E1000_RAH(rar_entries), 0);
3983 wr32(E1000_RAL(rar_entries), 0);
3984 }
3985 wrfl();
3986
68d480c4
AD		 3987 return count;
3988}
3989
3990/**
b980ac18
JK		 3991 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3992 * @netdev: network interface device structure
68d480c4 3993 *
b980ac18
JK		 3994 * The set_rx_mode entry point is called whenever the unicast or multicast
3995 * address lists or the network interface flags are updated. This routine is
3996 * responsible for configuring the hardware for proper unicast, multicast,
3997 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3998 **/
3999static void igb_set_rx_mode(struct net_device *netdev)
4000{
4001 struct igb_adapter *adapter = netdev_priv(netdev);
4002 struct e1000_hw *hw = &adapter->hw;
4003 unsigned int vfn = adapter->vfs_allocated_count;
4004 u32 rctl, vmolr = 0;
4005 int count;
4006
4007 /* Check for Promiscuous and All Multicast modes */
4008 rctl = rd32(E1000_RCTL);
4009
4010 /* clear the effected bits */
4011 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4012
4013 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4014 /* retain VLAN HW filtering if in VT mode */
7e44892c 4015 if (adapter->vfs_allocated_count)
6f3dc319 4016 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4017 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4018 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4019 } else {
4020 if (netdev->flags & IFF_ALLMULTI) {
4021 rctl |= E1000_RCTL_MPE;
4022 vmolr |= E1000_VMOLR_MPME;
4023 } else {
b980ac18 4024 /* Write addresses to the MTA, if the attempt fails
25985edc 4025 * then we should just turn on promiscuous mode so
68d480c4
AD		 4026 * that we can at least receive multicast traffic
4027 */
4028 count = igb_write_mc_addr_list(netdev);
4029 if (count < 0) {
4030 rctl |= E1000_RCTL_MPE;
4031 vmolr |= E1000_VMOLR_MPME;
4032 } else if (count) {
4033 vmolr |= E1000_VMOLR_ROMPE;
4034 }
4035 }
b980ac18 4036 /* Write addresses to available RAR registers, if there is not
68d480c4 4037 * sufficient space to store all the addresses then enable
25985edc 4038 * unicast promiscuous mode
68d480c4
AD		 4039 */
4040 count = igb_write_uc_addr_list(netdev);
4041 if (count < 0) {
4042 rctl |= E1000_RCTL_UPE;
4043 vmolr |= E1000_VMOLR_ROPE;
4044 }
4045 rctl |= E1000_RCTL_VFE;
28fc06f5 4046 }
68d480c4 4047 wr32(E1000_RCTL, rctl);
28fc06f5 4048
b980ac18 4049 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4050 * the VMOLR to enable the appropriate modes. Without this workaround
4051 * we will have issues with VLAN tag stripping not being done for frames
4052 * that are only arriving because we are the default pool
4053 */
f96a8a0b 4054 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4055 return;
9d5c8243 4056
68d480c4 4057 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4058 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4059 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4060 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4061}
4062
13800469
GR		 4063static void igb_check_wvbr(struct igb_adapter *adapter)
4064{
4065 struct e1000_hw *hw = &adapter->hw;
4066 u32 wvbr = 0;
4067
4068 switch (hw->mac.type) {
4069 case e1000_82576:
4070 case e1000_i350:
81ad807b
CW		 4071 wvbr = rd32(E1000_WVBR);
4072 if (!wvbr)
13800469
GR		 4073 return;
4074 break;
4075 default:
4076 break;
4077 }
4078
4079 adapter->wvbr |= wvbr;
4080}
4081
4082#define IGB_STAGGERED_QUEUE_OFFSET 8
4083
4084static void igb_spoof_check(struct igb_adapter *adapter)
4085{
4086 int j;
4087
4088 if (!adapter->wvbr)
4089 return;
4090
9005df38 4091 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4092 if (adapter->wvbr & (1 << j) ||
4093 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4094 dev_warn(&adapter->pdev->dev,
4095 "Spoof event(s) detected on VF %d\n", j);
4096 adapter->wvbr &=
4097 ~((1 << j) |
4098 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4099 }
4100 }
4101}
4102
9d5c8243 4103/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4104 * the phy
4105 */
9d5c8243
AK		 4106static void igb_update_phy_info(unsigned long data)
4107{
4108 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4109 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4110}
4111
4d6b725e 4112/**
b980ac18
JK		 4113 * igb_has_link - check shared code for link and determine up/down
4114 * @adapter: pointer to driver private info
4d6b725e 4115 **/
3145535a 4116bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4117{
4118 struct e1000_hw *hw = &adapter->hw;
4119 bool link_active = false;
4d6b725e
AD		 4120
4121 /* get_link_status is set on LSC (link status) interrupt or
4122 * rx sequence error interrupt. get_link_status will stay
4123 * false until the e1000_check_for_link establishes link
4124 * for copper adapters ONLY
4125 */
4126 switch (hw->phy.media_type) {
4127 case e1000_media_type_copper:
e5c3370f
AA		 4128 if (!hw->mac.get_link_status)
4129 return true;
4d6b725e 4130 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4131 hw->mac.ops.check_for_link(hw);
4132 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4133 break;
4134 default:
4135 case e1000_media_type_unknown:
4136 break;
4137 }
4138
aa9b8cc4
AA		 4139 if (((hw->mac.type == e1000_i210) ||
4140 (hw->mac.type == e1000_i211)) &&
4141 (hw->phy.id == I210_I_PHY_ID)) {
4142 if (!netif_carrier_ok(adapter->netdev)) {
4143 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4144 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4145 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4146 adapter->link_check_timeout = jiffies;
4147 }
4148 }
4149
4d6b725e
AD		 4150 return link_active;
4151}
4152
563988dc
SA		 4153static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4154{
4155 bool ret = false;
4156 u32 ctrl_ext, thstat;
4157
f96a8a0b 4158 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4159 if (hw->mac.type == e1000_i350) {
4160 thstat = rd32(E1000_THSTAT);
4161 ctrl_ext = rd32(E1000_CTRL_EXT);
4162
4163 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4164 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4165 ret = !!(thstat & event);
563988dc
SA		 4166 }
4167
4168 return ret;
4169}
4170
1516f0a6
CW		 4171/**
4172 * igb_check_lvmmc - check for malformed packets received
4173 * and indicated in LVMMC register
4174 * @adapter: pointer to adapter
4175 **/
4176static void igb_check_lvmmc(struct igb_adapter *adapter)
4177{
4178 struct e1000_hw *hw = &adapter->hw;
4179 u32 lvmmc;
4180
4181 lvmmc = rd32(E1000_LVMMC);
4182 if (lvmmc) {
4183 if (unlikely(net_ratelimit())) {
4184 netdev_warn(adapter->netdev,
4185 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4186 lvmmc);
4187 }
4188 }
4189}
4190
9d5c8243 4191/**
b980ac18
JK		 4192 * igb_watchdog - Timer Call-back
4193 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4194 **/
4195static void igb_watchdog(unsigned long data)
4196{
4197 struct igb_adapter *adapter = (struct igb_adapter *)data;
4198 /* Do the rest outside of interrupt context */
4199 schedule_work(&adapter->watchdog_task);
4200}
4201
4202static void igb_watchdog_task(struct work_struct *work)
4203{
4204 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4205 struct igb_adapter,
4206 watchdog_task);
9d5c8243 4207 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4208 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4209 struct net_device *netdev = adapter->netdev;
563988dc 4210 u32 link;
7a6ea550 4211 int i;
56cec249 4212 u32 connsw;
9d5c8243 4213
4d6b725e 4214 link = igb_has_link(adapter);
aa9b8cc4
AA		 4215
4216 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4217 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4218 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4219 else
4220 link = false;
4221 }
4222
56cec249
CW		 4223 /* Force link down if we have fiber to swap to */
4224 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4225 if (hw->phy.media_type == e1000_media_type_copper) {
4226 connsw = rd32(E1000_CONNSW);
4227 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4228 link = 0;
4229 }
4230 }
9d5c8243 4231 if (link) {
2bdfc4e2
CW		 4232 /* Perform a reset if the media type changed. */
4233 if (hw->dev_spec._82575.media_changed) {
4234 hw->dev_spec._82575.media_changed = false;
4235 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4236 igb_reset(adapter);
4237 }
749ab2cd
YZ		 4238 /* Cancel scheduled suspend requests. */
4239 pm_runtime_resume(netdev->dev.parent);
4240
9d5c8243
AK		 4241 if (!netif_carrier_ok(netdev)) {
4242 u32 ctrl;
9005df38 4243
330a6d6a 4244 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4245 &adapter->link_speed,
4246 &adapter->link_duplex);
9d5c8243
AK		 4247
4248 ctrl = rd32(E1000_CTRL);
527d47c1 4249 /* Links status message must follow this format */
c75c4edf
CW		 4250 netdev_info(netdev,
4251 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4252 netdev->name,
4253 adapter->link_speed,
4254 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4255 "Full" : "Half",
4256 (ctrl & E1000_CTRL_TFCE) &&
4257 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4258 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4259 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4260
f4c01e96
CW		 4261 /* disable EEE if enabled */
4262 if ((adapter->flags & IGB_FLAG_EEE) &&
4263 (adapter->link_duplex == HALF_DUPLEX)) {
4264 dev_info(&adapter->pdev->dev,
4265 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4266 adapter->hw.dev_spec._82575.eee_disable = true;
4267 adapter->flags &= ~IGB_FLAG_EEE;
4268 }
4269
c0ba4778
KS		 4270 /* check if SmartSpeed worked */
4271 igb_check_downshift(hw);
4272 if (phy->speed_downgraded)
4273 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4274
563988dc 4275 /* check for thermal sensor event */
876d2d6f 4276 if (igb_thermal_sensor_event(hw,
d34a15ab 4277 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4278 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4279
d07f3e37 4280 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4281 adapter->tx_timeout_factor = 1;
4282 switch (adapter->link_speed) {
4283 case SPEED_10:
9d5c8243
AK		 4284 adapter->tx_timeout_factor = 14;
4285 break;
4286 case SPEED_100:
9d5c8243
AK		 4287 /* maybe add some timeout factor ? */
4288 break;
4289 }
4290
4291 netif_carrier_on(netdev);
9d5c8243 4292
4ae196df 4293 igb_ping_all_vfs(adapter);
17dc566c 4294 igb_check_vf_rate_limit(adapter);
4ae196df 4295
4b1a9877 4296 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4297 if (!test_bit(__IGB_DOWN, &adapter->state))
4298 mod_timer(&adapter->phy_info_timer,
4299 round_jiffies(jiffies + 2 * HZ));
4300 }
4301 } else {
4302 if (netif_carrier_ok(netdev)) {
4303 adapter->link_speed = 0;
4304 adapter->link_duplex = 0;
563988dc
SA		 4305
4306 /* check for thermal sensor event */
876d2d6f
JK		 4307 if (igb_thermal_sensor_event(hw,
4308 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4309 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4310 }
563988dc 4311
527d47c1 4312 /* Links status message must follow this format */
c75c4edf 4313 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4314 netdev->name);
9d5c8243 4315 netif_carrier_off(netdev);
4b1a9877 4316
4ae196df
AD		 4317 igb_ping_all_vfs(adapter);
4318
4b1a9877 4319 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4320 if (!test_bit(__IGB_DOWN, &adapter->state))
4321 mod_timer(&adapter->phy_info_timer,
4322 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4323
56cec249
CW		 4324 /* link is down, time to check for alternate media */
4325 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4326 igb_check_swap_media(adapter);
4327 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4328 schedule_work(&adapter->reset_task);
4329 /* return immediately */
4330 return;
4331 }
4332 }
749ab2cd
YZ		 4333 pm_schedule_suspend(netdev->dev.parent,
4334 MSEC_PER_SEC * 5);
56cec249
CW		 4335
4336 /* also check for alternate media here */
4337 } else if (!netif_carrier_ok(netdev) &&
4338 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4339 igb_check_swap_media(adapter);
4340 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4341 schedule_work(&adapter->reset_task);
4342 /* return immediately */
4343 return;
4344 }
9d5c8243
AK		 4345 }
4346 }
4347
12dcd86b
ED		 4348 spin_lock(&adapter->stats64_lock);
4349 igb_update_stats(adapter, &adapter->stats64);
4350 spin_unlock(&adapter->stats64_lock);
9d5c8243 4351
dbabb065 4352 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4353 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4354 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4355 /* We've lost link, so the controller stops DMA,
4356 * but we've got queued Tx work that's never going
4357 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4358 * (Do the reset outside of interrupt context).
4359 */
dbabb065
AD		 4360 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4361 adapter->tx_timeout_count++;
4362 schedule_work(&adapter->reset_task);
4363 /* return immediately since reset is imminent */
4364 return;
4365 }
9d5c8243 4366 }
9d5c8243 4367
dbabb065 4368 /* Force detection of hung controller every watchdog period */
6d095fa8 4369 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4370 }
f7ba205e 4371
b980ac18 4372 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4373 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4374 u32 eics = 0;
9005df38 4375
0d1ae7f4
AD		 4376 for (i = 0; i < adapter->num_q_vectors; i++)
4377 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4378 wr32(E1000_EICS, eics);
4379 } else {
4380 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4381 }
9d5c8243 4382
13800469 4383 igb_spoof_check(adapter);
fc580751 4384 igb_ptp_rx_hang(adapter);
13800469 4385
1516f0a6
CW		 4386 /* Check LVMMC register on i350/i354 only */
4387 if ((adapter->hw.mac.type == e1000_i350) ||
4388 (adapter->hw.mac.type == e1000_i354))
4389 igb_check_lvmmc(adapter);
4390
9d5c8243 4391 /* Reset the timer */
aa9b8cc4
AA		 4392 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4393 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4394 mod_timer(&adapter->watchdog_timer,
4395 round_jiffies(jiffies + HZ));
4396 else
4397 mod_timer(&adapter->watchdog_timer,
4398 round_jiffies(jiffies + 2 * HZ));
4399 }
9d5c8243
AK		 4400}
4401
4402enum latency_range {
4403 lowest_latency = 0,
4404 low_latency = 1,
4405 bulk_latency = 2,
4406 latency_invalid = 255
4407};
4408
6eb5a7f1 4409/**
b980ac18
JK		 4410 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4411 * @q_vector: pointer to q_vector
6eb5a7f1 4412 *
b980ac18
JK		 4413 * Stores a new ITR value based on strictly on packet size. This
4414 * algorithm is less sophisticated than that used in igb_update_itr,
4415 * due to the difficulty of synchronizing statistics across multiple
4416 * receive rings. The divisors and thresholds used by this function
4417 * were determined based on theoretical maximum wire speed and testing
4418 * data, in order to minimize response time while increasing bulk
4419 * throughput.
406d4965 4420 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4421 * NOTE: This function is called only when operating in a multiqueue
4422 * receive environment.
6eb5a7f1 4423 **/
047e0030 4424static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4425{
047e0030 4426 int new_val = q_vector->itr_val;
6eb5a7f1 4427 int avg_wire_size = 0;
047e0030 4428 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4429 unsigned int packets;
9d5c8243 4430
6eb5a7f1
AD		 4431 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4432 * ints/sec - ITR timer value of 120 ticks.
4433 */
4434 if (adapter->link_speed != SPEED_1000) {
0ba82994 4435 new_val = IGB_4K_ITR;
6eb5a7f1 4436 goto set_itr_val;
9d5c8243 4437 }
047e0030 4438
0ba82994
AD		 4439 packets = q_vector->rx.total_packets;
4440 if (packets)
4441 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4442
0ba82994
AD		 4443 packets = q_vector->tx.total_packets;
4444 if (packets)
4445 avg_wire_size = max_t(u32, avg_wire_size,
4446 q_vector->tx.total_bytes / packets);
047e0030
AD		 4447
4448 /* if avg_wire_size isn't set no work was done */
4449 if (!avg_wire_size)
4450 goto clear_counts;
9d5c8243 4451
6eb5a7f1
AD		 4452 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4453 avg_wire_size += 24;
4454
4455 /* Don't starve jumbo frames */
4456 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4457
6eb5a7f1
AD		 4458 /* Give a little boost to mid-size frames */
4459 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4460 new_val = avg_wire_size / 3;
4461 else
4462 new_val = avg_wire_size / 2;
9d5c8243 4463
0ba82994
AD		 4464 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4465 if (new_val < IGB_20K_ITR &&
4466 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4467 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4468 new_val = IGB_20K_ITR;
abe1c363 4469
6eb5a7f1 4470set_itr_val:
047e0030
AD		 4471 if (new_val != q_vector->itr_val) {
4472 q_vector->itr_val = new_val;
4473 q_vector->set_itr = 1;
9d5c8243 4474 }
6eb5a7f1 4475clear_counts:
0ba82994
AD		 4476 q_vector->rx.total_bytes = 0;
4477 q_vector->rx.total_packets = 0;
4478 q_vector->tx.total_bytes = 0;
4479 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4480}
4481
4482/**
b980ac18
JK		 4483 * igb_update_itr - update the dynamic ITR value based on statistics
4484 * @q_vector: pointer to q_vector
4485 * @ring_container: ring info to update the itr for
4486 *
4487 * Stores a new ITR value based on packets and byte
4488 * counts during the last interrupt. The advantage of per interrupt
4489 * computation is faster updates and more accurate ITR for the current
4490 * traffic pattern. Constants in this function were computed
4491 * based on theoretical maximum wire speed and thresholds were set based
4492 * on testing data as well as attempting to minimize response time
4493 * while increasing bulk throughput.
406d4965 4494 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4495 * NOTE: These calculations are only valid when operating in a single-
4496 * queue environment.
9d5c8243 4497 **/
0ba82994
AD		 4498static void igb_update_itr(struct igb_q_vector *q_vector,
4499 struct igb_ring_container *ring_container)
9d5c8243 4500{
0ba82994
AD		 4501 unsigned int packets = ring_container->total_packets;
4502 unsigned int bytes = ring_container->total_bytes;
4503 u8 itrval = ring_container->itr;
9d5c8243 4504
0ba82994 4505 /* no packets, exit with status unchanged */
9d5c8243 4506 if (packets == 0)
0ba82994 4507 return;
9d5c8243 4508
0ba82994 4509 switch (itrval) {
9d5c8243
AK		 4510 case lowest_latency:
4511 /* handle TSO and jumbo frames */
4512 if (bytes/packets > 8000)
0ba82994 4513 itrval = bulk_latency;
9d5c8243 4514 else if ((packets < 5) && (bytes > 512))
0ba82994 4515 itrval = low_latency;
9d5c8243
AK		 4516 break;
4517 case low_latency: /* 50 usec aka 20000 ints/s */
4518 if (bytes > 10000) {
4519 /* this if handles the TSO accounting */
d34a15ab 4520 if (bytes/packets > 8000)
0ba82994 4521 itrval = bulk_latency;
d34a15ab 4522 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4523 itrval = bulk_latency;
d34a15ab 4524 else if ((packets > 35))
0ba82994 4525 itrval = lowest_latency;
9d5c8243 4526 } else if (bytes/packets > 2000) {
0ba82994 4527 itrval = bulk_latency;
9d5c8243 4528 } else if (packets <= 2 && bytes < 512) {
0ba82994 4529 itrval = lowest_latency;
9d5c8243
AK		 4530 }
4531 break;
4532 case bulk_latency: /* 250 usec aka 4000 ints/s */
4533 if (bytes > 25000) {
4534 if (packets > 35)
0ba82994 4535 itrval = low_latency;
1e5c3d21 4536 } else if (bytes < 1500) {
0ba82994 4537 itrval = low_latency;
9d5c8243
AK		 4538 }
4539 break;
4540 }
4541
0ba82994
AD		 4542 /* clear work counters since we have the values we need */
4543 ring_container->total_bytes = 0;
4544 ring_container->total_packets = 0;
4545
4546 /* write updated itr to ring container */
4547 ring_container->itr = itrval;
9d5c8243
AK		 4548}
4549
0ba82994 4550static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4551{
0ba82994 4552 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4553 u32 new_itr = q_vector->itr_val;
0ba82994 4554 u8 current_itr = 0;
9d5c8243
AK		 4555
4556 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4557 if (adapter->link_speed != SPEED_1000) {
4558 current_itr = 0;
0ba82994 4559 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4560 goto set_itr_now;
4561 }
4562
0ba82994
AD		 4563 igb_update_itr(q_vector, &q_vector->tx);
4564 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4565
0ba82994 4566 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4567
6eb5a7f1 4568 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4569 if (current_itr == lowest_latency &&
4570 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4571 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4572 current_itr = low_latency;
4573
9d5c8243
AK		 4574 switch (current_itr) {
4575 /* counts and packets in update_itr are dependent on these numbers */
4576 case lowest_latency:
0ba82994 4577 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4578 break;
4579 case low_latency:
0ba82994 4580 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4581 break;
4582 case bulk_latency:
0ba82994 4583 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4584 break;
4585 default:
4586 break;
4587 }
4588
4589set_itr_now:
047e0030 4590 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4591 /* this attempts to bias the interrupt rate towards Bulk
4592 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4593 * increasing
4594 */
047e0030 4595 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4596 max((new_itr * q_vector->itr_val) /
4597 (new_itr + (q_vector->itr_val >> 2)),
4598 new_itr) : new_itr;
9d5c8243
AK		 4599 /* Don't write the value here; it resets the adapter's
4600 * internal timer, and causes us to delay far longer than
4601 * we should between interrupts. Instead, we write the ITR
4602 * value at the beginning of the next interrupt so the timing
4603 * ends up being correct.
4604 */
047e0030
AD		 4605 q_vector->itr_val = new_itr;
4606 q_vector->set_itr = 1;
9d5c8243 4607 }
9d5c8243
AK		 4608}
4609
c50b52a0
SH		 4610static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4611 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4612{
4613 struct e1000_adv_tx_context_desc *context_desc;
4614 u16 i = tx_ring->next_to_use;
4615
4616 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4617
4618 i++;
4619 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4620
4621 /* set bits to identify this as an advanced context descriptor */
4622 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4623
4624 /* For 82575, context index must be unique per ring. */
866cff06 4625 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4626 mss_l4len_idx |= tx_ring->reg_idx << 4;
4627
4628 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4629 context_desc->seqnum_seed = 0;
4630 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4631 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4632}
4633
7af40ad9
AD		 4634static int igb_tso(struct igb_ring *tx_ring,
4635 struct igb_tx_buffer *first,
4636 u8 *hdr_len)
9d5c8243 4637{
7af40ad9 4638 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4639 u32 vlan_macip_lens, type_tucmd;
4640 u32 mss_l4len_idx, l4len;
06c14e5a 4641 int err;
7d13a7d0 4642
ed6aa105
AD		 4643 if (skb->ip_summed != CHECKSUM_PARTIAL)
4644 return 0;
4645
7d13a7d0
AD		 4646 if (!skb_is_gso(skb))
4647 return 0;
9d5c8243 4648
06c14e5a
FR		 4649 err = skb_cow_head(skb, 0);
4650 if (err < 0)
4651 return err;
9d5c8243 4652
7d13a7d0
AD		 4653 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4654 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4655
7c4d16ff 4656 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4657 struct iphdr *iph = ip_hdr(skb);
4658 iph->tot_len = 0;
4659 iph->check = 0;
4660 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4661 iph->daddr, 0,
4662 IPPROTO_TCP,
4663 0);
7d13a7d0 4664 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4665 first->tx_flags |= IGB_TX_FLAGS_TSO |
4666 IGB_TX_FLAGS_CSUM |
4667 IGB_TX_FLAGS_IPV4;
8e1e8a47 4668 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4669 ipv6_hdr(skb)->payload_len = 0;
4670 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4671 &ipv6_hdr(skb)->daddr,
4672 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4673 first->tx_flags |= IGB_TX_FLAGS_TSO |
4674 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4675 }
4676
7af40ad9 4677 /* compute header lengths */
7d13a7d0
AD		 4678 l4len = tcp_hdrlen(skb);
4679 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4680
7af40ad9
AD		 4681 /* update gso size and bytecount with header size */
4682 first->gso_segs = skb_shinfo(skb)->gso_segs;
4683 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4684
9d5c8243 4685 /* MSS L4LEN IDX */
7d13a7d0
AD		 4686 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4687 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4688
7d13a7d0
AD		 4689 /* VLAN MACLEN IPLEN */
4690 vlan_macip_lens = skb_network_header_len(skb);
4691 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4692 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4693
7d13a7d0 4694 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4695
7d13a7d0 4696 return 1;
9d5c8243
AK		 4697}
4698
7af40ad9 4699static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4700{
7af40ad9 4701 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4702 u32 vlan_macip_lens = 0;
4703 u32 mss_l4len_idx = 0;
4704 u32 type_tucmd = 0;
9d5c8243 4705
7d13a7d0 4706 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4707 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4708 return;
7d13a7d0
AD		 4709 } else {
4710 u8 l4_hdr = 0;
9005df38 4711
7af40ad9 4712 switch (first->protocol) {
7c4d16ff 4713 case htons(ETH_P_IP):
7d13a7d0
AD		 4714 vlan_macip_lens |= skb_network_header_len(skb);
4715 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4716 l4_hdr = ip_hdr(skb)->protocol;
4717 break;
7c4d16ff 4718 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4719 vlan_macip_lens |= skb_network_header_len(skb);
4720 l4_hdr = ipv6_hdr(skb)->nexthdr;
4721 break;
4722 default:
4723 if (unlikely(net_ratelimit())) {
4724 dev_warn(tx_ring->dev,
b980ac18
JK		 4725 "partial checksum but proto=%x!\n",
4726 first->protocol);
fa4a7ef3 4727 }
7d13a7d0
AD		 4728 break;
4729 }
fa4a7ef3 4730
7d13a7d0
AD		 4731 switch (l4_hdr) {
4732 case IPPROTO_TCP:
4733 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4734 mss_l4len_idx = tcp_hdrlen(skb) <<
4735 E1000_ADVTXD_L4LEN_SHIFT;
4736 break;
4737 case IPPROTO_SCTP:
4738 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4739 mss_l4len_idx = sizeof(struct sctphdr) <<
4740 E1000_ADVTXD_L4LEN_SHIFT;
4741 break;
4742 case IPPROTO_UDP:
4743 mss_l4len_idx = sizeof(struct udphdr) <<
4744 E1000_ADVTXD_L4LEN_SHIFT;
4745 break;
4746 default:
4747 if (unlikely(net_ratelimit())) {
4748 dev_warn(tx_ring->dev,
b980ac18
JK		 4749 "partial checksum but l4 proto=%x!\n",
4750 l4_hdr);
44b0cda3 4751 }
7d13a7d0 4752 break;
9d5c8243 4753 }
7af40ad9
AD		 4754
4755 /* update TX checksum flag */
4756 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4757 }
9d5c8243 4758
7d13a7d0 4759 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4760 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4761
7d13a7d0 4762 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4763}
4764
1d9daf45
AD		 4765#define IGB_SET_FLAG(_input, _flag, _result) \
4766 ((_flag <= _result) ? \
4767 ((u32)(_input & _flag) * (_result / _flag)) : \
4768 ((u32)(_input & _flag) / (_flag / _result)))
4769
4770static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4771{
4772 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4773 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4774 E1000_ADVTXD_DCMD_DEXT |
4775 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4776
4777 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4778 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4779 (E1000_ADVTXD_DCMD_VLE));
4780
4781 /* set segmentation bits for TSO */
4782 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4783 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4784
4785 /* set timestamp bit if present */
1d9daf45
AD		 4786 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4787 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4788
1d9daf45
AD		 4789 /* insert frame checksum */
4790 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4791
4792 return cmd_type;
4793}
4794
7af40ad9
AD		 4795static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4796 union e1000_adv_tx_desc *tx_desc,
4797 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4798{
4799 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4800
1d9daf45
AD		 4801 /* 82575 requires a unique index per ring */
4802 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4803 olinfo_status |= tx_ring->reg_idx << 4;
4804
4805 /* insert L4 checksum */
1d9daf45
AD		 4806 olinfo_status |= IGB_SET_FLAG(tx_flags,
4807 IGB_TX_FLAGS_CSUM,
4808 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4809
1d9daf45
AD		 4810 /* insert IPv4 checksum */
4811 olinfo_status |= IGB_SET_FLAG(tx_flags,
4812 IGB_TX_FLAGS_IPV4,
4813 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4814
7af40ad9 4815 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4816}
4817
7af40ad9
AD		 4818static void igb_tx_map(struct igb_ring *tx_ring,
4819 struct igb_tx_buffer *first,
ebe42d16 4820 const u8 hdr_len)
9d5c8243 4821{
7af40ad9 4822 struct sk_buff *skb = first->skb;
c9f14bf3 4823 struct igb_tx_buffer *tx_buffer;
ebe42d16 4824 union e1000_adv_tx_desc *tx_desc;
80d0759e 4825 struct skb_frag_struct *frag;
ebe42d16 4826 dma_addr_t dma;
80d0759e 4827 unsigned int data_len, size;
7af40ad9 4828 u32 tx_flags = first->tx_flags;
1d9daf45 4829 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4830 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4831
4832 tx_desc = IGB_TX_DESC(tx_ring, i);
4833
80d0759e
AD		 4834 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4835
4836 size = skb_headlen(skb);
4837 data_len = skb->data_len;
ebe42d16
AD		 4838
4839 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4840
80d0759e
AD		 4841 tx_buffer = first;
4842
4843 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4844 if (dma_mapping_error(tx_ring->dev, dma))
4845 goto dma_error;
4846
4847 /* record length, and DMA address */
4848 dma_unmap_len_set(tx_buffer, len, size);
4849 dma_unmap_addr_set(tx_buffer, dma, dma);
4850
4851 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4852
ebe42d16
AD		 4853 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4854 tx_desc->read.cmd_type_len =
1d9daf45 4855 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4856
4857 i++;
4858 tx_desc++;
4859 if (i == tx_ring->count) {
4860 tx_desc = IGB_TX_DESC(tx_ring, 0);
4861 i = 0;
4862 }
80d0759e 4863 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4864
4865 dma += IGB_MAX_DATA_PER_TXD;
4866 size -= IGB_MAX_DATA_PER_TXD;
4867
ebe42d16
AD		 4868 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4869 }
4870
4871 if (likely(!data_len))
4872 break;
2bbfebe2 4873
1d9daf45 4874 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4875
65689fef 4876 i++;
ebe42d16
AD		 4877 tx_desc++;
4878 if (i == tx_ring->count) {
4879 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4880 i = 0;
ebe42d16 4881 }
80d0759e 4882 tx_desc->read.olinfo_status = 0;
65689fef 4883
9e903e08 4884 size = skb_frag_size(frag);
ebe42d16
AD		 4885 data_len -= size;
4886
4887 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4888 size, DMA_TO_DEVICE);
6366ad33 4889
c9f14bf3 4890 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4891 }
4892
ebe42d16 4893 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4894 cmd_type |= size | IGB_TXD_DCMD;
4895 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4896
80d0759e
AD		 4897 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4898
8542db05
AD		 4899 /* set the timestamp */
4900 first->time_stamp = jiffies;
4901
b980ac18 4902 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4903 * are new descriptors to fetch. (Only applicable for weak-ordered
4904 * memory model archs, such as IA-64).
4905 *
4906 * We also need this memory barrier to make certain all of the
4907 * status bits have been updated before next_to_watch is written.
4908 */
4909 wmb();
4910
8542db05 4911 /* set next_to_watch value indicating a packet is present */
ebe42d16 4912 first->next_to_watch = tx_desc;
9d5c8243 4913
ebe42d16
AD		 4914 i++;
4915 if (i == tx_ring->count)
4916 i = 0;
6366ad33 4917
ebe42d16 4918 tx_ring->next_to_use = i;
6366ad33 4919
ebe42d16
AD		 4920 return;
4921
4922dma_error:
4923 dev_err(tx_ring->dev, "TX DMA map failed\n");
4924
4925 /* clear dma mappings for failed tx_buffer_info map */
4926 for (;;) {
c9f14bf3
AD		 4927 tx_buffer = &tx_ring->tx_buffer_info[i];
4928 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4929 if (tx_buffer == first)
ebe42d16 4930 break;
a77ff709
NN		 4931 if (i == 0)
4932 i = tx_ring->count;
6366ad33 4933 i--;
6366ad33
AD		 4934 }
4935
9d5c8243 4936 tx_ring->next_to_use = i;
9d5c8243
AK		 4937}
4938
6ad4edfc 4939static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4940{
e694e964
AD		 4941 struct net_device *netdev = tx_ring->netdev;
4942
661086df 4943 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4944
9d5c8243
AK		 4945 /* Herbert's original patch had:
4946 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4947 * but since that doesn't exist yet, just open code it.
4948 */
9d5c8243
AK		 4949 smp_mb();
4950
4951 /* We need to check again in a case another CPU has just
b980ac18
JK		 4952 * made room available.
4953 */
c493ea45 4954 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4955 return -EBUSY;
4956
4957 /* A reprieve! */
661086df 4958 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4959
4960 u64_stats_update_begin(&tx_ring->tx_syncp2);
4961 tx_ring->tx_stats.restart_queue2++;
4962 u64_stats_update_end(&tx_ring->tx_syncp2);
4963
9d5c8243
AK		 4964 return 0;
4965}
4966
6ad4edfc 4967static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4968{
c493ea45 4969 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4970 return 0;
e694e964 4971 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4972}
4973
cd392f5c
AD		 4974netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4975 struct igb_ring *tx_ring)
9d5c8243 4976{
8542db05 4977 struct igb_tx_buffer *first;
ebe42d16 4978 int tso;
91d4ee33 4979 u32 tx_flags = 0;
21ba6fe1 4980 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4981 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4982 u8 hdr_len = 0;
9d5c8243 4983
21ba6fe1
AD		 4984 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4985 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4986 * + 2 desc gap to keep tail from touching head,
9d5c8243 4987 * + 1 desc for context descriptor,
21ba6fe1
AD		 4988 * otherwise try next time
4989 */
4990 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4991 unsigned short f;
9005df38 4992
21ba6fe1
AD		 4993 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4994 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4995 } else {
4996 count += skb_shinfo(skb)->nr_frags;
4997 }
4998
4999 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5000 /* this is a hard error */
9d5c8243
AK		 5001 return NETDEV_TX_BUSY;
5002 }
33af6bcc 5003
7af40ad9
AD		 5004 /* record the location of the first descriptor for this packet */
5005 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5006 first->skb = skb;
5007 first->bytecount = skb->len;
5008 first->gso_segs = 1;
5009
b646c22e
AD		 5010 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5011 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5012
ed4420a3
JK		 5013 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5014 &adapter->state)) {
b646c22e
AD		 5015 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5016 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5017
5018 adapter->ptp_tx_skb = skb_get(skb);
5019 adapter->ptp_tx_start = jiffies;
5020 if (adapter->hw.mac.type == e1000_82576)
5021 schedule_work(&adapter->ptp_tx_work);
5022 }
33af6bcc 5023 }
9d5c8243 5024
afc835d1
JK		 5025 skb_tx_timestamp(skb);
5026
eab6d18d 5027 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 5028 tx_flags |= IGB_TX_FLAGS_VLAN;
5029 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5030 }
5031
7af40ad9
AD		 5032 /* record initial flags and protocol */
5033 first->tx_flags = tx_flags;
5034 first->protocol = protocol;
cdfd01fc 5035
7af40ad9
AD		 5036 tso = igb_tso(tx_ring, first, &hdr_len);
5037 if (tso < 0)
7d13a7d0 5038 goto out_drop;
7af40ad9
AD		 5039 else if (!tso)
5040 igb_tx_csum(tx_ring, first);
9d5c8243 5041
7af40ad9 5042 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 5043
5044 /* Make sure there is space in the ring for the next send. */
21ba6fe1 5045 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 5046
9d5c8243 5047 return NETDEV_TX_OK;
7d13a7d0
AD		 5048
5049out_drop:
7af40ad9
AD		 5050 igb_unmap_and_free_tx_resource(tx_ring, first);
5051
7d13a7d0 5052 return NETDEV_TX_OK;
9d5c8243
AK		 5053}
5054
c1ebf46c 5055static struct igb_ring *__igb_tx_queue_mapping(struct igb_adapter *adapter, unsigned int r_idx)
1cc3bd87 5056{
1cc3bd87
AD		 5057 if (r_idx >= adapter->num_tx_queues)
5058 r_idx = r_idx % adapter->num_tx_queues;
5059
5060 return adapter->tx_ring[r_idx];
5061}
5062
c1ebf46c
DM		 5063static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5064 struct sk_buff *skb)
5065{
5066 return __igb_tx_queue_mapping(adapter, skb->queue_mapping);
5067}
5068
cd392f5c
AD		 5069static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5070 struct net_device *netdev)
9d5c8243
AK		 5071{
5072 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5073
5074 if (test_bit(__IGB_DOWN, &adapter->state)) {
5075 dev_kfree_skb_any(skb);
5076 return NETDEV_TX_OK;
5077 }
5078
5079 if (skb->len <= 0) {
5080 dev_kfree_skb_any(skb);
5081 return NETDEV_TX_OK;
5082 }
5083
b980ac18 5084 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5085 * in order to meet this minimum size requirement.
5086 */
ea5ceeab
TD		 5087 if (unlikely(skb->len < 17)) {
5088 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 5089 return NETDEV_TX_OK;
5090 skb->len = 17;
ea5ceeab 5091 skb_set_tail_pointer(skb, 17);
1cc3bd87 5092 }
9d5c8243 5093
1cc3bd87 5094 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5095}
5096
c1ebf46c
DM		 5097static void igb_xmit_flush(struct net_device *netdev, u16 queue)
5098{
5099 struct igb_adapter *adapter = netdev_priv(netdev);
5100 struct igb_ring *tx_ring;
5101
5102 tx_ring = __igb_tx_queue_mapping(adapter, queue);
5103
5104 writel(tx_ring->next_to_use, tx_ring->tail);
5105
5106 /* we need this if more than one processor can write to our tail
5107 * at a time, it synchronizes IO on IA64/Altix systems
5108 */
5109 mmiowb();
5110}
5111
9d5c8243 5112/**
b980ac18
JK		 5113 * igb_tx_timeout - Respond to a Tx Hang
5114 * @netdev: network interface device structure
9d5c8243
AK		 5115 **/
5116static void igb_tx_timeout(struct net_device *netdev)
5117{
5118 struct igb_adapter *adapter = netdev_priv(netdev);
5119 struct e1000_hw *hw = &adapter->hw;
5120
5121 /* Do the reset outside of interrupt context */
5122 adapter->tx_timeout_count++;
f7ba205e 5123
06218a8d 5124 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5125 hw->dev_spec._82575.global_device_reset = true;
5126
9d5c8243 5127 schedule_work(&adapter->reset_task);
265de409
AD		 5128 wr32(E1000_EICS,
5129 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5130}
5131
5132static void igb_reset_task(struct work_struct *work)
5133{
5134 struct igb_adapter *adapter;
5135 adapter = container_of(work, struct igb_adapter, reset_task);
5136
c97ec42a
TI		 5137 igb_dump(adapter);
5138 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5139 igb_reinit_locked(adapter);
5140}
5141
5142/**
b980ac18
JK		 5143 * igb_get_stats64 - Get System Network Statistics
5144 * @netdev: network interface device structure
5145 * @stats: rtnl_link_stats64 pointer
9d5c8243 5146 **/
12dcd86b 5147static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5148 struct rtnl_link_stats64 *stats)
9d5c8243 5149{
12dcd86b
ED		 5150 struct igb_adapter *adapter = netdev_priv(netdev);
5151
5152 spin_lock(&adapter->stats64_lock);
5153 igb_update_stats(adapter, &adapter->stats64);
5154 memcpy(stats, &adapter->stats64, sizeof(*stats));
5155 spin_unlock(&adapter->stats64_lock);
5156
5157 return stats;
9d5c8243
AK		 5158}
5159
5160/**
b980ac18
JK		 5161 * igb_change_mtu - Change the Maximum Transfer Unit
5162 * @netdev: network interface device structure
5163 * @new_mtu: new value for maximum frame size
9d5c8243 5164 *
b980ac18 5165 * Returns 0 on success, negative on failure
9d5c8243
AK		 5166 **/
5167static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5168{
5169 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5170 struct pci_dev *pdev = adapter->pdev;
153285f9 5171 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5172
c809d227 5173 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5174 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5175 return -EINVAL;
5176 }
5177
153285f9 5178#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5179 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5180 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5181 return -EINVAL;
5182 }
5183
2ccd994c
AD		 5184 /* adjust max frame to be at least the size of a standard frame */
5185 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5186 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5187
9d5c8243 5188 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5189 usleep_range(1000, 2000);
73cd78f1 5190
9d5c8243
AK		 5191 /* igb_down has a dependency on max_frame_size */
5192 adapter->max_frame_size = max_frame;
559e9c49 5193
4c844851
AD		 5194 if (netif_running(netdev))
5195 igb_down(adapter);
9d5c8243 5196
090b1795 5197 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5198 netdev->mtu, new_mtu);
5199 netdev->mtu = new_mtu;
5200
5201 if (netif_running(netdev))
5202 igb_up(adapter);
5203 else
5204 igb_reset(adapter);
5205
5206 clear_bit(__IGB_RESETTING, &adapter->state);
5207
5208 return 0;
5209}
5210
5211/**
b980ac18
JK		 5212 * igb_update_stats - Update the board statistics counters
5213 * @adapter: board private structure
9d5c8243 5214 **/
12dcd86b
ED		 5215void igb_update_stats(struct igb_adapter *adapter,
5216 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5217{
5218 struct e1000_hw *hw = &adapter->hw;
5219 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5220 u32 reg, mpc;
9d5c8243 5221 u16 phy_tmp;
3f9c0164
AD		 5222 int i;
5223 u64 bytes, packets;
12dcd86b
ED		 5224 unsigned int start;
5225 u64 _bytes, _packets;
9d5c8243
AK		 5226
5227#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
5228
b980ac18 5229 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5230 * connection is down.
5231 */
5232 if (adapter->link_speed == 0)
5233 return;
5234 if (pci_channel_offline(pdev))
5235 return;
5236
3f9c0164
AD		 5237 bytes = 0;
5238 packets = 0;
7f90128e
AA		 5239
5240 rcu_read_lock();
3f9c0164 5241 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5242 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5243 u32 rqdpc = rd32(E1000_RQDPC(i));
5244 if (hw->mac.type >= e1000_i210)
5245 wr32(E1000_RQDPC(i), 0);
12dcd86b 5246
ae1c07a6
AD		 5247 if (rqdpc) {
5248 ring->rx_stats.drops += rqdpc;
5249 net_stats->rx_fifo_errors += rqdpc;
5250 }
12dcd86b
ED		 5251
5252 do {
57a7744e 5253 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5254 _bytes = ring->rx_stats.bytes;
5255 _packets = ring->rx_stats.packets;
57a7744e 5256 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5257 bytes += _bytes;
5258 packets += _packets;
3f9c0164
AD		 5259 }
5260
128e45eb
AD		 5261 net_stats->rx_bytes = bytes;
5262 net_stats->rx_packets = packets;
3f9c0164
AD		 5263
5264 bytes = 0;
5265 packets = 0;
5266 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5267 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5268 do {
57a7744e 5269 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5270 _bytes = ring->tx_stats.bytes;
5271 _packets = ring->tx_stats.packets;
57a7744e 5272 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5273 bytes += _bytes;
5274 packets += _packets;
3f9c0164 5275 }
128e45eb
AD		 5276 net_stats->tx_bytes = bytes;
5277 net_stats->tx_packets = packets;
7f90128e 5278 rcu_read_unlock();
3f9c0164
AD		 5279
5280 /* read stats registers */
9d5c8243
AK		 5281 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5282 adapter->stats.gprc += rd32(E1000_GPRC);
5283 adapter->stats.gorc += rd32(E1000_GORCL);
5284 rd32(E1000_GORCH); /* clear GORCL */
5285 adapter->stats.bprc += rd32(E1000_BPRC);
5286 adapter->stats.mprc += rd32(E1000_MPRC);
5287 adapter->stats.roc += rd32(E1000_ROC);
5288
5289 adapter->stats.prc64 += rd32(E1000_PRC64);
5290 adapter->stats.prc127 += rd32(E1000_PRC127);
5291 adapter->stats.prc255 += rd32(E1000_PRC255);
5292 adapter->stats.prc511 += rd32(E1000_PRC511);
5293 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5294 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5295 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5296 adapter->stats.sec += rd32(E1000_SEC);
5297
fa3d9a6d
MW		 5298 mpc = rd32(E1000_MPC);
5299 adapter->stats.mpc += mpc;
5300 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5301 adapter->stats.scc += rd32(E1000_SCC);
5302 adapter->stats.ecol += rd32(E1000_ECOL);
5303 adapter->stats.mcc += rd32(E1000_MCC);
5304 adapter->stats.latecol += rd32(E1000_LATECOL);
5305 adapter->stats.dc += rd32(E1000_DC);
5306 adapter->stats.rlec += rd32(E1000_RLEC);
5307 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5308 adapter->stats.xontxc += rd32(E1000_XONTXC);
5309 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5310 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5311 adapter->stats.fcruc += rd32(E1000_FCRUC);
5312 adapter->stats.gptc += rd32(E1000_GPTC);
5313 adapter->stats.gotc += rd32(E1000_GOTCL);
5314 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5315 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5316 adapter->stats.ruc += rd32(E1000_RUC);
5317 adapter->stats.rfc += rd32(E1000_RFC);
5318 adapter->stats.rjc += rd32(E1000_RJC);
5319 adapter->stats.tor += rd32(E1000_TORH);
5320 adapter->stats.tot += rd32(E1000_TOTH);
5321 adapter->stats.tpr += rd32(E1000_TPR);
5322
5323 adapter->stats.ptc64 += rd32(E1000_PTC64);
5324 adapter->stats.ptc127 += rd32(E1000_PTC127);
5325 adapter->stats.ptc255 += rd32(E1000_PTC255);
5326 adapter->stats.ptc511 += rd32(E1000_PTC511);
5327 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5328 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5329
5330 adapter->stats.mptc += rd32(E1000_MPTC);
5331 adapter->stats.bptc += rd32(E1000_BPTC);
5332
2d0b0f69
NN		 5333 adapter->stats.tpt += rd32(E1000_TPT);
5334 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5335
5336 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5337 /* read internal phy specific stats */
5338 reg = rd32(E1000_CTRL_EXT);
5339 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5340 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5341
5342 /* this stat has invalid values on i210/i211 */
5343 if ((hw->mac.type != e1000_i210) &&
5344 (hw->mac.type != e1000_i211))
5345 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5346 }
5347
9d5c8243
AK		 5348 adapter->stats.tsctc += rd32(E1000_TSCTC);
5349 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5350
5351 adapter->stats.iac += rd32(E1000_IAC);
5352 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5353 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5354 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5355 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5356 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5357 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5358 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5359 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5360
5361 /* Fill out the OS statistics structure */
128e45eb
AD		 5362 net_stats->multicast = adapter->stats.mprc;
5363 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5364
5365 /* Rx Errors */
5366
5367 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5368 * our own version based on RUC and ROC
5369 */
128e45eb 5370 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5371 adapter->stats.crcerrs + adapter->stats.algnerrc +
5372 adapter->stats.ruc + adapter->stats.roc +
5373 adapter->stats.cexterr;
128e45eb
AD		 5374 net_stats->rx_length_errors = adapter->stats.ruc +
5375 adapter->stats.roc;
5376 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5377 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5378 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5379
5380 /* Tx Errors */
128e45eb
AD		 5381 net_stats->tx_errors = adapter->stats.ecol +
5382 adapter->stats.latecol;
5383 net_stats->tx_aborted_errors = adapter->stats.ecol;
5384 net_stats->tx_window_errors = adapter->stats.latecol;
5385 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5386
5387 /* Tx Dropped needs to be maintained elsewhere */
5388
5389 /* Phy Stats */
5390 if (hw->phy.media_type == e1000_media_type_copper) {
5391 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5392 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5393 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5394 adapter->phy_stats.idle_errors += phy_tmp;
5395 }
5396 }
5397
5398 /* Management Stats */
5399 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5400 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5401 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5402
5403 /* OS2BMC Stats */
5404 reg = rd32(E1000_MANC);
5405 if (reg & E1000_MANC_EN_BMC2OS) {
5406 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5407 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5408 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5409 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5410 }
9d5c8243
AK		 5411}
5412
9d5c8243
AK		 5413static irqreturn_t igb_msix_other(int irq, void *data)
5414{
047e0030 5415 struct igb_adapter *adapter = data;
9d5c8243 5416 struct e1000_hw *hw = &adapter->hw;
844290e5 5417 u32 icr = rd32(E1000_ICR);
844290e5 5418 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5419
7f081d40
AD		 5420 if (icr & E1000_ICR_DRSTA)
5421 schedule_work(&adapter->reset_task);
5422
047e0030 5423 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5424 /* HW is reporting DMA is out of sync */
5425 adapter->stats.doosync++;
13800469
GR		 5426 /* The DMA Out of Sync is also indication of a spoof event
5427 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5428 * see if it is really a spoof event.
5429 */
13800469 5430 igb_check_wvbr(adapter);
dda0e083 5431 }
eebbbdba 5432
4ae196df
AD		 5433 /* Check for a mailbox event */
5434 if (icr & E1000_ICR_VMMB)
5435 igb_msg_task(adapter);
5436
5437 if (icr & E1000_ICR_LSC) {
5438 hw->mac.get_link_status = 1;
5439 /* guard against interrupt when we're going down */
5440 if (!test_bit(__IGB_DOWN, &adapter->state))
5441 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5442 }
5443
1f6e8178
MV		 5444 if (icr & E1000_ICR_TS) {
5445 u32 tsicr = rd32(E1000_TSICR);
5446
5447 if (tsicr & E1000_TSICR_TXTS) {
5448 /* acknowledge the interrupt */
5449 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5450 /* retrieve hardware timestamp */
5451 schedule_work(&adapter->ptp_tx_work);
5452 }
5453 }
1f6e8178 5454
844290e5 5455 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5456
5457 return IRQ_HANDLED;
5458}
5459
047e0030 5460static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5461{
26b39276 5462 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5463 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5464
047e0030
AD		 5465 if (!q_vector->set_itr)
5466 return;
73cd78f1 5467
047e0030
AD		 5468 if (!itr_val)
5469 itr_val = 0x4;
661086df 5470
26b39276
AD		 5471 if (adapter->hw.mac.type == e1000_82575)
5472 itr_val |= itr_val << 16;
661086df 5473 else
0ba82994 5474 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5475
047e0030
AD		 5476 writel(itr_val, q_vector->itr_register);
5477 q_vector->set_itr = 0;
6eb5a7f1
AD		 5478}
5479
047e0030 5480static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5481{
047e0030 5482 struct igb_q_vector *q_vector = data;
9d5c8243 5483
047e0030
AD		 5484 /* Write the ITR value calculated from the previous interrupt. */
5485 igb_write_itr(q_vector);
9d5c8243 5486
047e0030 5487 napi_schedule(&q_vector->napi);
844290e5 5488
047e0030 5489 return IRQ_HANDLED;
fe4506b6
JC		 5490}
5491
421e02f0 5492#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5493static void igb_update_tx_dca(struct igb_adapter *adapter,
5494 struct igb_ring *tx_ring,
5495 int cpu)
5496{
5497 struct e1000_hw *hw = &adapter->hw;
5498 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5499
5500 if (hw->mac.type != e1000_82575)
5501 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5502
b980ac18 5503 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5504 * DCA is enabled. This is due to a known issue in some chipsets
5505 * which will cause the DCA tag to be cleared.
5506 */
5507 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5508 E1000_DCA_TXCTRL_DATA_RRO_EN |
5509 E1000_DCA_TXCTRL_DESC_DCA_EN;
5510
5511 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5512}
5513
5514static void igb_update_rx_dca(struct igb_adapter *adapter,
5515 struct igb_ring *rx_ring,
5516 int cpu)
5517{
5518 struct e1000_hw *hw = &adapter->hw;
5519 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5520
5521 if (hw->mac.type != e1000_82575)
5522 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5523
b980ac18 5524 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5525 * DCA is enabled. This is due to a known issue in some chipsets
5526 * which will cause the DCA tag to be cleared.
5527 */
5528 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5529 E1000_DCA_RXCTRL_DESC_DCA_EN;
5530
5531 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5532}
5533
047e0030 5534static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5535{
047e0030 5536 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5537 int cpu = get_cpu();
fe4506b6 5538
047e0030
AD		 5539 if (q_vector->cpu == cpu)
5540 goto out_no_update;
5541
6a05004a
AD		 5542 if (q_vector->tx.ring)
5543 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5544
5545 if (q_vector->rx.ring)
5546 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5547
047e0030
AD		 5548 q_vector->cpu = cpu;
5549out_no_update:
fe4506b6
JC		 5550 put_cpu();
5551}
5552
5553static void igb_setup_dca(struct igb_adapter *adapter)
5554{
7e0e99ef 5555 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5556 int i;
5557
7dfc16fa 5558 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5559 return;
5560
7e0e99ef
AD		 5561 /* Always use CB2 mode, difference is masked in the CB driver. */
5562 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5563
047e0030 5564 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5565 adapter->q_vector[i]->cpu = -1;
5566 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5567 }
5568}
5569
5570static int __igb_notify_dca(struct device *dev, void *data)
5571{
5572 struct net_device *netdev = dev_get_drvdata(dev);
5573 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5574 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5575 struct e1000_hw *hw = &adapter->hw;
5576 unsigned long event = *(unsigned long *)data;
5577
5578 switch (event) {
5579 case DCA_PROVIDER_ADD:
5580 /* if already enabled, don't do it again */
7dfc16fa 5581 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5582 break;
fe4506b6 5583 if (dca_add_requester(dev) == 0) {
bbd98fe4 5584 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5585 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5586 igb_setup_dca(adapter);
5587 break;
5588 }
5589 /* Fall Through since DCA is disabled. */
5590 case DCA_PROVIDER_REMOVE:
7dfc16fa 5591 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5592 /* without this a class_device is left
b980ac18
JK		 5593 * hanging around in the sysfs model
5594 */
fe4506b6 5595 dca_remove_requester(dev);
090b1795 5596 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5597 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5598 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5599 }
5600 break;
5601 }
bbd98fe4 5602
fe4506b6 5603 return 0;
9d5c8243
AK		 5604}
5605
fe4506b6 5606static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5607 void *p)
fe4506b6
JC		 5608{
5609 int ret_val;
5610
5611 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5612 __igb_notify_dca);
fe4506b6
JC		 5613
5614 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5615}
421e02f0 5616#endif /* CONFIG_IGB_DCA */
9d5c8243 5617
0224d663
GR		 5618#ifdef CONFIG_PCI_IOV
5619static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5620{
5621 unsigned char mac_addr[ETH_ALEN];
0224d663 5622
5ac6f91d 5623 eth_zero_addr(mac_addr);
0224d663
GR		 5624 igb_set_vf_mac(adapter, vf, mac_addr);
5625
70ea4783
LL		 5626 /* By default spoof check is enabled for all VFs */
5627 adapter->vf_data[vf].spoofchk_enabled = true;
5628
f557147c 5629 return 0;
0224d663
GR		 5630}
5631
0224d663 5632#endif
4ae196df
AD		 5633static void igb_ping_all_vfs(struct igb_adapter *adapter)
5634{
5635 struct e1000_hw *hw = &adapter->hw;
5636 u32 ping;
5637 int i;
5638
5639 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5640 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5641 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5642 ping |= E1000_VT_MSGTYPE_CTS;
5643 igb_write_mbx(hw, &ping, 1, i);
5644 }
5645}
5646
7d5753f0
AD		 5647static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5648{
5649 struct e1000_hw *hw = &adapter->hw;
5650 u32 vmolr = rd32(E1000_VMOLR(vf));
5651 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5652
d85b9004 5653 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5654 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5655 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5656
5657 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5658 vmolr |= E1000_VMOLR_MPME;
d85b9004 5659 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5660 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5661 } else {
b980ac18 5662 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5663 * flag we need to write the hashes to the MTA as this step
5664 * was previously skipped
5665 */
5666 if (vf_data->num_vf_mc_hashes > 30) {
5667 vmolr |= E1000_VMOLR_MPME;
5668 } else if (vf_data->num_vf_mc_hashes) {
5669 int j;
9005df38 5670
7d5753f0
AD		 5671 vmolr |= E1000_VMOLR_ROMPE;
5672 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5673 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5674 }
5675 }
5676
5677 wr32(E1000_VMOLR(vf), vmolr);
5678
5679 /* there are flags left unprocessed, likely not supported */
5680 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5681 return -EINVAL;
5682
5683 return 0;
7d5753f0
AD		 5684}
5685
4ae196df
AD		 5686static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5687 u32 *msgbuf, u32 vf)
5688{
5689 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5690 u16 *hash_list = (u16 *)&msgbuf[1];
5691 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5692 int i;
5693
7d5753f0 5694 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5695 * to this VF for later use to restore when the PF multi cast
5696 * list changes
5697 */
5698 vf_data->num_vf_mc_hashes = n;
5699
7d5753f0
AD		 5700 /* only up to 30 hash values supported */
5701 if (n > 30)
5702 n = 30;
5703
5704 /* store the hashes for later use */
4ae196df 5705 for (i = 0; i < n; i++)
a419aef8 5706 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5707
5708 /* Flush and reset the mta with the new values */
ff41f8dc 5709 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5710
5711 return 0;
5712}
5713
5714static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5715{
5716 struct e1000_hw *hw = &adapter->hw;
5717 struct vf_data_storage *vf_data;
5718 int i, j;
5719
5720 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5721 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5722
7d5753f0
AD		 5723 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5724
4ae196df 5725 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5726
5727 if ((vf_data->num_vf_mc_hashes > 30) ||
5728 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5729 vmolr |= E1000_VMOLR_MPME;
5730 } else if (vf_data->num_vf_mc_hashes) {
5731 vmolr |= E1000_VMOLR_ROMPE;
5732 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5733 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5734 }
5735 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5736 }
5737}
5738
5739static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5740{
5741 struct e1000_hw *hw = &adapter->hw;
5742 u32 pool_mask, reg, vid;
5743 int i;
5744
5745 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5746
5747 /* Find the vlan filter for this id */
5748 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5749 reg = rd32(E1000_VLVF(i));
5750
5751 /* remove the vf from the pool */
5752 reg &= ~pool_mask;
5753
5754 /* if pool is empty then remove entry from vfta */
5755 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5756 (reg & E1000_VLVF_VLANID_ENABLE)) {
5757 reg = 0;
5758 vid = reg & E1000_VLVF_VLANID_MASK;
5759 igb_vfta_set(hw, vid, false);
5760 }
5761
5762 wr32(E1000_VLVF(i), reg);
5763 }
ae641bdc
AD		 5764
5765 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5766}
5767
5768static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5769{
5770 struct e1000_hw *hw = &adapter->hw;
5771 u32 reg, i;
5772
51466239
AD		 5773 /* The vlvf table only exists on 82576 hardware and newer */
5774 if (hw->mac.type < e1000_82576)
5775 return -1;
5776
5777 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5778 if (!adapter->vfs_allocated_count)
5779 return -1;
5780
5781 /* Find the vlan filter for this id */
5782 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5783 reg = rd32(E1000_VLVF(i));
5784 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5785 vid == (reg & E1000_VLVF_VLANID_MASK))
5786 break;
5787 }
5788
5789 if (add) {
5790 if (i == E1000_VLVF_ARRAY_SIZE) {
5791 /* Did not find a matching VLAN ID entry that was
5792 * enabled. Search for a free filter entry, i.e.
5793 * one without the enable bit set
5794 */
5795 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5796 reg = rd32(E1000_VLVF(i));
5797 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5798 break;
5799 }
5800 }
5801 if (i < E1000_VLVF_ARRAY_SIZE) {
5802 /* Found an enabled/available entry */
5803 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5804
5805 /* if !enabled we need to set this up in vfta */
5806 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5807 /* add VID to filter table */
5808 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5809 reg |= E1000_VLVF_VLANID_ENABLE;
5810 }
cad6d05f
AD		 5811 reg &= ~E1000_VLVF_VLANID_MASK;
5812 reg |= vid;
4ae196df 5813 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5814
5815 /* do not modify RLPML for PF devices */
5816 if (vf >= adapter->vfs_allocated_count)
5817 return 0;
5818
5819 if (!adapter->vf_data[vf].vlans_enabled) {
5820 u32 size;
9005df38 5821
ae641bdc
AD		 5822 reg = rd32(E1000_VMOLR(vf));
5823 size = reg & E1000_VMOLR_RLPML_MASK;
5824 size += 4;
5825 reg &= ~E1000_VMOLR_RLPML_MASK;
5826 reg |= size;
5827 wr32(E1000_VMOLR(vf), reg);
5828 }
ae641bdc 5829
51466239 5830 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5831 }
5832 } else {
5833 if (i < E1000_VLVF_ARRAY_SIZE) {
5834 /* remove vf from the pool */
5835 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5836 /* if pool is empty then remove entry from vfta */
5837 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5838 reg = 0;
5839 igb_vfta_set(hw, vid, false);
5840 }
5841 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5842
5843 /* do not modify RLPML for PF devices */
5844 if (vf >= adapter->vfs_allocated_count)
5845 return 0;
5846
5847 adapter->vf_data[vf].vlans_enabled--;
5848 if (!adapter->vf_data[vf].vlans_enabled) {
5849 u32 size;
9005df38 5850
ae641bdc
AD		 5851 reg = rd32(E1000_VMOLR(vf));
5852 size = reg & E1000_VMOLR_RLPML_MASK;
5853 size -= 4;
5854 reg &= ~E1000_VMOLR_RLPML_MASK;
5855 reg |= size;
5856 wr32(E1000_VMOLR(vf), reg);
5857 }
4ae196df
AD		 5858 }
5859 }
8151d294
WM		 5860 return 0;
5861}
5862
5863static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5864{
5865 struct e1000_hw *hw = &adapter->hw;
5866
5867 if (vid)
5868 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5869 else
5870 wr32(E1000_VMVIR(vf), 0);
5871}
5872
5873static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5874 int vf, u16 vlan, u8 qos)
5875{
5876 int err = 0;
5877 struct igb_adapter *adapter = netdev_priv(netdev);
5878
5879 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5880 return -EINVAL;
5881 if (vlan || qos) {
5882 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5883 if (err)
5884 goto out;
5885 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5886 igb_set_vmolr(adapter, vf, !vlan);
5887 adapter->vf_data[vf].pf_vlan = vlan;
5888 adapter->vf_data[vf].pf_qos = qos;
5889 dev_info(&adapter->pdev->dev,
5890 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5891 if (test_bit(__IGB_DOWN, &adapter->state)) {
5892 dev_warn(&adapter->pdev->dev,
b980ac18 5893 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5894 dev_warn(&adapter->pdev->dev,
b980ac18 5895 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5896 }
5897 } else {
5898 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5899 false, vf);
8151d294
WM		 5900 igb_set_vmvir(adapter, vlan, vf);
5901 igb_set_vmolr(adapter, vf, true);
5902 adapter->vf_data[vf].pf_vlan = 0;
5903 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5904 }
8151d294 5905out:
b980ac18 5906 return err;
4ae196df
AD		 5907}
5908
6f3dc319
GR		 5909static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5910{
5911 struct e1000_hw *hw = &adapter->hw;
5912 int i;
5913 u32 reg;
5914
5915 /* Find the vlan filter for this id */
5916 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5917 reg = rd32(E1000_VLVF(i));
5918 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5919 vid == (reg & E1000_VLVF_VLANID_MASK))
5920 break;
5921 }
5922
5923 if (i >= E1000_VLVF_ARRAY_SIZE)
5924 i = -1;
5925
5926 return i;
5927}
5928
4ae196df
AD		 5929static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5930{
6f3dc319 5931 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5932 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5933 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5934 int err = 0;
4ae196df 5935
6f3dc319
GR		 5936 /* If in promiscuous mode we need to make sure the PF also has
5937 * the VLAN filter set.
5938 */
5939 if (add && (adapter->netdev->flags & IFF_PROMISC))
5940 err = igb_vlvf_set(adapter, vid, add,
5941 adapter->vfs_allocated_count);
5942 if (err)
5943 goto out;
5944
5945 err = igb_vlvf_set(adapter, vid, add, vf);
5946
5947 if (err)
5948 goto out;
5949
5950 /* Go through all the checks to see if the VLAN filter should
5951 * be wiped completely.
5952 */
5953 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5954 u32 vlvf, bits;
6f3dc319 5955 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 5956
6f3dc319
GR		 5957 if (regndx < 0)
5958 goto out;
5959 /* See if any other pools are set for this VLAN filter
5960 * entry other than the PF.
5961 */
5962 vlvf = bits = rd32(E1000_VLVF(regndx));
5963 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5964 adapter->vfs_allocated_count);
5965 /* If the filter was removed then ensure PF pool bit
5966 * is cleared if the PF only added itself to the pool
5967 * because the PF is in promiscuous mode.
5968 */
5969 if ((vlvf & VLAN_VID_MASK) == vid &&
5970 !test_bit(vid, adapter->active_vlans) &&
5971 !bits)
5972 igb_vlvf_set(adapter, vid, add,
5973 adapter->vfs_allocated_count);
5974 }
5975
5976out:
5977 return err;
4ae196df
AD		 5978}
5979
f2ca0dbe 5980static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5981{
8fa7e0f7
GR		 5982 /* clear flags - except flag that indicates PF has set the MAC */
5983 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5984 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5985
5986 /* reset offloads to defaults */
8151d294 5987 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5988
5989 /* reset vlans for device */
5990 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5991 if (adapter->vf_data[vf].pf_vlan)
5992 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5993 adapter->vf_data[vf].pf_vlan,
5994 adapter->vf_data[vf].pf_qos);
5995 else
5996 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5997
5998 /* reset multicast table array for vf */
5999 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6000
6001 /* Flush and reset the mta with the new values */
ff41f8dc 6002 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6003}
6004
f2ca0dbe
AD		 6005static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6006{
6007 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6008
5ac6f91d 6009 /* clear mac address as we were hotplug removed/added */
8151d294 6010 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6011 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6012
6013 /* process remaining reset events */
6014 igb_vf_reset(adapter, vf);
6015}
6016
6017static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6018{
6019 struct e1000_hw *hw = &adapter->hw;
6020 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6021 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6022 u32 reg, msgbuf[3];
6023 u8 *addr = (u8 *)(&msgbuf[1]);
6024
6025 /* process all the same items cleared in a function level reset */
f2ca0dbe 6026 igb_vf_reset(adapter, vf);
4ae196df
AD		 6027
6028 /* set vf mac address */
26ad9178 6029 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6030
6031 /* enable transmit and receive for vf */
6032 reg = rd32(E1000_VFTE);
6033 wr32(E1000_VFTE, reg | (1 << vf));
6034 reg = rd32(E1000_VFRE);
6035 wr32(E1000_VFRE, reg | (1 << vf));
6036
8fa7e0f7 6037 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6038
6039 /* reply to reset with ack and vf mac address */
6040 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 6041 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 6042 igb_write_mbx(hw, msgbuf, 3, vf);
6043}
6044
6045static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6046{
b980ac18 6047 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6048 * starting at the second 32 bit word of the msg array
6049 */
f2ca0dbe
AD		 6050 unsigned char *addr = (char *)&msg[1];
6051 int err = -1;
4ae196df 6052
f2ca0dbe
AD		 6053 if (is_valid_ether_addr(addr))
6054 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6055
f2ca0dbe 6056 return err;
4ae196df
AD		 6057}
6058
6059static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6060{
6061 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6062 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6063 u32 msg = E1000_VT_MSGTYPE_NACK;
6064
6065 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6066 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6067 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6068 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6069 vf_data->last_nack = jiffies;
4ae196df
AD		 6070 }
6071}
6072
f2ca0dbe 6073static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6074{
f2ca0dbe
AD		 6075 struct pci_dev *pdev = adapter->pdev;
6076 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6077 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6078 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6079 s32 retval;
6080
f2ca0dbe 6081 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6082
fef45f4c
AD		 6083 if (retval) {
6084 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6085 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6086 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6087 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6088 return;
6089 goto out;
6090 }
4ae196df
AD		 6091
6092 /* this is a message we already processed, do nothing */
6093 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6094 return;
4ae196df 6095
b980ac18 6096 /* until the vf completes a reset it should not be
4ae196df
AD		 6097 * allowed to start any configuration.
6098 */
4ae196df
AD		 6099 if (msgbuf[0] == E1000_VF_RESET) {
6100 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6101 return;
4ae196df
AD		 6102 }
6103
f2ca0dbe 6104 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6105 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6106 return;
6107 retval = -1;
6108 goto out;
4ae196df
AD		 6109 }
6110
6111 switch ((msgbuf[0] & 0xFFFF)) {
6112 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6113 retval = -EINVAL;
6114 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6115 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6116 else
6117 dev_warn(&pdev->dev,
b980ac18
JK		 6118 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6119 vf);
4ae196df 6120 break;
7d5753f0
AD		 6121 case E1000_VF_SET_PROMISC:
6122 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6123 break;
4ae196df
AD		 6124 case E1000_VF_SET_MULTICAST:
6125 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6126 break;
6127 case E1000_VF_SET_LPE:
6128 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6129 break;
6130 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6131 retval = -1;
6132 if (vf_data->pf_vlan)
6133 dev_warn(&pdev->dev,
b980ac18
JK		 6134 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6135 vf);
8151d294
WM		 6136 else
6137 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6138 break;
6139 default:
090b1795 6140 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6141 retval = -1;
6142 break;
6143 }
6144
fef45f4c
AD		 6145 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6146out:
4ae196df
AD		 6147 /* notify the VF of the results of what it sent us */
6148 if (retval)
6149 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6150 else
6151 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6152
4ae196df 6153 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6154}
4ae196df 6155
f2ca0dbe
AD		 6156static void igb_msg_task(struct igb_adapter *adapter)
6157{
6158 struct e1000_hw *hw = &adapter->hw;
6159 u32 vf;
6160
6161 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6162 /* process any reset requests */
6163 if (!igb_check_for_rst(hw, vf))
6164 igb_vf_reset_event(adapter, vf);
6165
6166 /* process any messages pending */
6167 if (!igb_check_for_msg(hw, vf))
6168 igb_rcv_msg_from_vf(adapter, vf);
6169
6170 /* process any acks */
6171 if (!igb_check_for_ack(hw, vf))
6172 igb_rcv_ack_from_vf(adapter, vf);
6173 }
4ae196df
AD		 6174}
6175
68d480c4
AD		 6176/**
6177 * igb_set_uta - Set unicast filter table address
6178 * @adapter: board private structure
6179 *
6180 * The unicast table address is a register array of 32-bit registers.
6181 * The table is meant to be used in a way similar to how the MTA is used
6182 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6183 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6184 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6185 **/
6186static void igb_set_uta(struct igb_adapter *adapter)
6187{
6188 struct e1000_hw *hw = &adapter->hw;
6189 int i;
6190
6191 /* The UTA table only exists on 82576 hardware and newer */
6192 if (hw->mac.type < e1000_82576)
6193 return;
6194
6195 /* we only need to do this if VMDq is enabled */
6196 if (!adapter->vfs_allocated_count)
6197 return;
6198
6199 for (i = 0; i < hw->mac.uta_reg_count; i++)
6200 array_wr32(E1000_UTA, i, ~0);
6201}
6202
9d5c8243 6203/**
b980ac18
JK		 6204 * igb_intr_msi - Interrupt Handler
6205 * @irq: interrupt number
6206 * @data: pointer to a network interface device structure
9d5c8243
AK		 6207 **/
6208static irqreturn_t igb_intr_msi(int irq, void *data)
6209{
047e0030
AD		 6210 struct igb_adapter *adapter = data;
6211 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6212 struct e1000_hw *hw = &adapter->hw;
6213 /* read ICR disables interrupts using IAM */
6214 u32 icr = rd32(E1000_ICR);
6215
047e0030 6216 igb_write_itr(q_vector);
9d5c8243 6217
7f081d40
AD		 6218 if (icr & E1000_ICR_DRSTA)
6219 schedule_work(&adapter->reset_task);
6220
047e0030 6221 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6222 /* HW is reporting DMA is out of sync */
6223 adapter->stats.doosync++;
6224 }
6225
9d5c8243
AK		 6226 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6227 hw->mac.get_link_status = 1;
6228 if (!test_bit(__IGB_DOWN, &adapter->state))
6229 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6230 }
6231
1f6e8178
MV		 6232 if (icr & E1000_ICR_TS) {
6233 u32 tsicr = rd32(E1000_TSICR);
6234
6235 if (tsicr & E1000_TSICR_TXTS) {
6236 /* acknowledge the interrupt */
6237 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6238 /* retrieve hardware timestamp */
6239 schedule_work(&adapter->ptp_tx_work);
6240 }
6241 }
1f6e8178 6242
047e0030 6243 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6244
6245 return IRQ_HANDLED;
6246}
6247
6248/**
b980ac18
JK		 6249 * igb_intr - Legacy Interrupt Handler
6250 * @irq: interrupt number
6251 * @data: pointer to a network interface device structure
9d5c8243
AK		 6252 **/
6253static irqreturn_t igb_intr(int irq, void *data)
6254{
047e0030
AD		 6255 struct igb_adapter *adapter = data;
6256 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6257 struct e1000_hw *hw = &adapter->hw;
6258 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6259 * need for the IMC write
6260 */
9d5c8243 6261 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6262
6263 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6264 * not set, then the adapter didn't send an interrupt
6265 */
9d5c8243
AK		 6266 if (!(icr & E1000_ICR_INT_ASSERTED))
6267 return IRQ_NONE;
6268
0ba82994
AD		 6269 igb_write_itr(q_vector);
6270
7f081d40
AD		 6271 if (icr & E1000_ICR_DRSTA)
6272 schedule_work(&adapter->reset_task);
6273
047e0030 6274 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6275 /* HW is reporting DMA is out of sync */
6276 adapter->stats.doosync++;
6277 }
6278
9d5c8243
AK		 6279 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6280 hw->mac.get_link_status = 1;
6281 /* guard against interrupt when we're going down */
6282 if (!test_bit(__IGB_DOWN, &adapter->state))
6283 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6284 }
6285
1f6e8178
MV		 6286 if (icr & E1000_ICR_TS) {
6287 u32 tsicr = rd32(E1000_TSICR);
6288
6289 if (tsicr & E1000_TSICR_TXTS) {
6290 /* acknowledge the interrupt */
6291 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6292 /* retrieve hardware timestamp */
6293 schedule_work(&adapter->ptp_tx_work);
6294 }
6295 }
1f6e8178 6296
047e0030 6297 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6298
6299 return IRQ_HANDLED;
6300}
6301
c50b52a0 6302static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6303{
047e0030 6304 struct igb_adapter *adapter = q_vector->adapter;
46544258 6305 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6306
0ba82994
AD		 6307 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6308 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6309 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6310 igb_set_itr(q_vector);
46544258 6311 else
047e0030 6312 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6313 }
6314
46544258 6315 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6316 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6317 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6318 else
6319 igb_irq_enable(adapter);
6320 }
9d5c8243
AK		 6321}
6322
46544258 6323/**
b980ac18
JK		 6324 * igb_poll - NAPI Rx polling callback
6325 * @napi: napi polling structure
6326 * @budget: count of how many packets we should handle
46544258
AD		 6327 **/
6328static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6329{
047e0030 6330 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6331 struct igb_q_vector,
6332 napi);
16eb8815 6333 bool clean_complete = true;
9d5c8243 6334
421e02f0 6335#ifdef CONFIG_IGB_DCA
047e0030
AD		 6336 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6337 igb_update_dca(q_vector);
fe4506b6 6338#endif
0ba82994 6339 if (q_vector->tx.ring)
13fde97a 6340 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6341
0ba82994 6342 if (q_vector->rx.ring)
cd392f5c 6343 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6344
16eb8815
AD		 6345 /* If all work not completed, return budget and keep polling */
6346 if (!clean_complete)
6347 return budget;
46544258 6348
9d5c8243 6349 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6350 napi_complete(napi);
6351 igb_ring_irq_enable(q_vector);
9d5c8243 6352
16eb8815 6353 return 0;
9d5c8243 6354}
6d8126f9 6355
9d5c8243 6356/**
b980ac18
JK		 6357 * igb_clean_tx_irq - Reclaim resources after transmit completes
6358 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6359 *
b980ac18 6360 * returns true if ring is completely cleaned
9d5c8243 6361 **/
047e0030 6362static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6363{
047e0030 6364 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6365 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6366 struct igb_tx_buffer *tx_buffer;
f4128785 6367 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6368 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6369 unsigned int budget = q_vector->tx.work_limit;
8542db05 6370 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6371
13fde97a
AD		 6372 if (test_bit(__IGB_DOWN, &adapter->state))
6373 return true;
0e014cb1 6374
06034649 6375 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6376 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6377 i -= tx_ring->count;
9d5c8243 6378
f4128785
AD		 6379 do {
6380 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6381
6382 /* if next_to_watch is not set then there is no work pending */
6383 if (!eop_desc)
6384 break;
13fde97a 6385
f4128785 6386 /* prevent any other reads prior to eop_desc */
70d289bc 6387 read_barrier_depends();
f4128785 6388
13fde97a
AD		 6389 /* if DD is not set pending work has not been completed */
6390 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6391 break;
6392
8542db05
AD		 6393 /* clear next_to_watch to prevent false hangs */
6394 tx_buffer->next_to_watch = NULL;
9d5c8243 6395
ebe42d16
AD		 6396 /* update the statistics for this packet */
6397 total_bytes += tx_buffer->bytecount;
6398 total_packets += tx_buffer->gso_segs;
13fde97a 6399
ebe42d16
AD		 6400 /* free the skb */
6401 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6402
ebe42d16
AD		 6403 /* unmap skb header data */
6404 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6405 dma_unmap_addr(tx_buffer, dma),
6406 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6407 DMA_TO_DEVICE);
6408
c9f14bf3
AD		 6409 /* clear tx_buffer data */
6410 tx_buffer->skb = NULL;
6411 dma_unmap_len_set(tx_buffer, len, 0);
6412
ebe42d16
AD		 6413 /* clear last DMA location and unmap remaining buffers */
6414 while (tx_desc != eop_desc) {
13fde97a
AD		 6415 tx_buffer++;
6416 tx_desc++;
9d5c8243 6417 i++;
8542db05
AD		 6418 if (unlikely(!i)) {
6419 i -= tx_ring->count;
06034649 6420 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6421 tx_desc = IGB_TX_DESC(tx_ring, 0);
6422 }
ebe42d16
AD		 6423
6424 /* unmap any remaining paged data */
c9f14bf3 6425 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6426 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6427 dma_unmap_addr(tx_buffer, dma),
6428 dma_unmap_len(tx_buffer, len),
ebe42d16 6429 DMA_TO_DEVICE);
c9f14bf3 6430 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6431 }
6432 }
6433
ebe42d16
AD		 6434 /* move us one more past the eop_desc for start of next pkt */
6435 tx_buffer++;
6436 tx_desc++;
6437 i++;
6438 if (unlikely(!i)) {
6439 i -= tx_ring->count;
6440 tx_buffer = tx_ring->tx_buffer_info;
6441 tx_desc = IGB_TX_DESC(tx_ring, 0);
6442 }
f4128785
AD		 6443
6444 /* issue prefetch for next Tx descriptor */
6445 prefetch(tx_desc);
6446
6447 /* update budget accounting */
6448 budget--;
6449 } while (likely(budget));
0e014cb1 6450
bdbc0631
ED		 6451 netdev_tx_completed_queue(txring_txq(tx_ring),
6452 total_packets, total_bytes);
8542db05 6453 i += tx_ring->count;
9d5c8243 6454 tx_ring->next_to_clean = i;
13fde97a
AD		 6455 u64_stats_update_begin(&tx_ring->tx_syncp);
6456 tx_ring->tx_stats.bytes += total_bytes;
6457 tx_ring->tx_stats.packets += total_packets;
6458 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6459 q_vector->tx.total_bytes += total_bytes;
6460 q_vector->tx.total_packets += total_packets;
9d5c8243 6461
6d095fa8 6462 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6463 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6464
9d5c8243 6465 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6466 * check with the clearing of time_stamp and movement of i
6467 */
6d095fa8 6468 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6469 if (tx_buffer->next_to_watch &&
8542db05 6470 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6471 (adapter->tx_timeout_factor * HZ)) &&
6472 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6473
9d5c8243 6474 /* detected Tx unit hang */
59d71989 6475 dev_err(tx_ring->dev,
9d5c8243 6476 "Detected Tx Unit Hang\n"
2d064c06 6477 " Tx Queue <%d>\n"
9d5c8243
AK		 6478 " TDH <%x>\n"
6479 " TDT <%x>\n"
6480 " next_to_use <%x>\n"
6481 " next_to_clean <%x>\n"
9d5c8243
AK		 6482 "buffer_info[next_to_clean]\n"
6483 " time_stamp <%lx>\n"
8542db05 6484 " next_to_watch <%p>\n"
9d5c8243
AK		 6485 " jiffies <%lx>\n"
6486 " desc.status <%x>\n",
2d064c06 6487 tx_ring->queue_index,
238ac817 6488 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6489 readl(tx_ring->tail),
9d5c8243
AK		 6490 tx_ring->next_to_use,
6491 tx_ring->next_to_clean,
8542db05 6492 tx_buffer->time_stamp,
f4128785 6493 tx_buffer->next_to_watch,
9d5c8243 6494 jiffies,
f4128785 6495 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6496 netif_stop_subqueue(tx_ring->netdev,
6497 tx_ring->queue_index);
6498
6499 /* we are about to reset, no point in enabling stuff */
6500 return true;
9d5c8243
AK		 6501 }
6502 }
13fde97a 6503
21ba6fe1 6504#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6505 if (unlikely(total_packets &&
b980ac18
JK		 6506 netif_carrier_ok(tx_ring->netdev) &&
6507 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6508 /* Make sure that anybody stopping the queue after this
6509 * sees the new next_to_clean.
6510 */
6511 smp_mb();
6512 if (__netif_subqueue_stopped(tx_ring->netdev,
6513 tx_ring->queue_index) &&
6514 !(test_bit(__IGB_DOWN, &adapter->state))) {
6515 netif_wake_subqueue(tx_ring->netdev,
6516 tx_ring->queue_index);
6517
6518 u64_stats_update_begin(&tx_ring->tx_syncp);
6519 tx_ring->tx_stats.restart_queue++;
6520 u64_stats_update_end(&tx_ring->tx_syncp);
6521 }
6522 }
6523
6524 return !!budget;
9d5c8243
AK		 6525}
6526
cbc8e55f 6527/**
b980ac18
JK		 6528 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6529 * @rx_ring: rx descriptor ring to store buffers on
6530 * @old_buff: donor buffer to have page reused
cbc8e55f 6531 *
b980ac18 6532 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6533 **/
6534static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6535 struct igb_rx_buffer *old_buff)
6536{
6537 struct igb_rx_buffer *new_buff;
6538 u16 nta = rx_ring->next_to_alloc;
6539
6540 new_buff = &rx_ring->rx_buffer_info[nta];
6541
6542 /* update, and store next to alloc */
6543 nta++;
6544 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6545
6546 /* transfer page from old buffer to new buffer */
a1f63473 6547 *new_buff = *old_buff;
cbc8e55f
AD		 6548
6549 /* sync the buffer for use by the device */
6550 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6551 old_buff->page_offset,
de78d1f9 6552 IGB_RX_BUFSZ,
cbc8e55f
AD		 6553 DMA_FROM_DEVICE);
6554}
6555
74e238ea
AD		 6556static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6557 struct page *page,
6558 unsigned int truesize)
6559{
6560 /* avoid re-using remote pages */
6561 if (unlikely(page_to_nid(page) != numa_node_id()))
6562 return false;
6563
6564#if (PAGE_SIZE < 8192)
6565 /* if we are only owner of page we can reuse it */
6566 if (unlikely(page_count(page) != 1))
6567 return false;
6568
6569 /* flip page offset to other buffer */
6570 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6571
6572 /* since we are the only owner of the page and we need to
6573 * increment it, just set the value to 2 in order to avoid
6574 * an unnecessary locked operation
6575 */
6576 atomic_set(&page->_count, 2);
6577#else
6578 /* move offset up to the next cache line */
6579 rx_buffer->page_offset += truesize;
6580
6581 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6582 return false;
6583
6584 /* bump ref count on page before it is given to the stack */
6585 get_page(page);
6586#endif
6587
6588 return true;
6589}
6590
cbc8e55f 6591/**
b980ac18
JK		 6592 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6593 * @rx_ring: rx descriptor ring to transact packets on
6594 * @rx_buffer: buffer containing page to add
6595 * @rx_desc: descriptor containing length of buffer written by hardware
6596 * @skb: sk_buff to place the data into
cbc8e55f 6597 *
b980ac18
JK		 6598 * This function will add the data contained in rx_buffer->page to the skb.
6599 * This is done either through a direct copy if the data in the buffer is
6600 * less than the skb header size, otherwise it will just attach the page as
6601 * a frag to the skb.
cbc8e55f 6602 *
b980ac18
JK		 6603 * The function will then update the page offset if necessary and return
6604 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6605 **/
6606static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6607 struct igb_rx_buffer *rx_buffer,
6608 union e1000_adv_rx_desc *rx_desc,
6609 struct sk_buff *skb)
6610{
6611 struct page *page = rx_buffer->page;
6612 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6613#if (PAGE_SIZE < 8192)
6614 unsigned int truesize = IGB_RX_BUFSZ;
6615#else
6616 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6617#endif
cbc8e55f
AD		 6618
6619 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6620 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6621
cbc8e55f
AD		 6622 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6623 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6624 va += IGB_TS_HDR_LEN;
6625 size -= IGB_TS_HDR_LEN;
6626 }
6627
cbc8e55f
AD		 6628 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6629
6630 /* we can reuse buffer as-is, just make sure it is local */
6631 if (likely(page_to_nid(page) == numa_node_id()))
6632 return true;
6633
6634 /* this page cannot be reused so discard it */
6635 put_page(page);
6636 return false;
6637 }
6638
6639 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6640 rx_buffer->page_offset, size, truesize);
cbc8e55f 6641
74e238ea
AD		 6642 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6643}
cbc8e55f 6644
2e334eee
AD		 6645static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6646 union e1000_adv_rx_desc *rx_desc,
6647 struct sk_buff *skb)
6648{
6649 struct igb_rx_buffer *rx_buffer;
6650 struct page *page;
6651
6652 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6653
2e334eee
AD		 6654 page = rx_buffer->page;
6655 prefetchw(page);
6656
6657 if (likely(!skb)) {
6658 void *page_addr = page_address(page) +
6659 rx_buffer->page_offset;
6660
6661 /* prefetch first cache line of first page */
6662 prefetch(page_addr);
6663#if L1_CACHE_BYTES < 128
6664 prefetch(page_addr + L1_CACHE_BYTES);
6665#endif
6666
6667 /* allocate a skb to store the frags */
6668 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6669 IGB_RX_HDR_LEN);
6670 if (unlikely(!skb)) {
6671 rx_ring->rx_stats.alloc_failed++;
6672 return NULL;
6673 }
6674
b980ac18 6675 /* we will be copying header into skb->data in
2e334eee
AD		 6676 * pskb_may_pull so it is in our interest to prefetch
6677 * it now to avoid a possible cache miss
6678 */
6679 prefetchw(skb->data);
6680 }
6681
6682 /* we are reusing so sync this buffer for CPU use */
6683 dma_sync_single_range_for_cpu(rx_ring->dev,
6684 rx_buffer->dma,
6685 rx_buffer->page_offset,
de78d1f9 6686 IGB_RX_BUFSZ,
2e334eee
AD		 6687 DMA_FROM_DEVICE);
6688
6689 /* pull page into skb */
6690 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6691 /* hand second half of page back to the ring */
6692 igb_reuse_rx_page(rx_ring, rx_buffer);
6693 } else {
6694 /* we are not reusing the buffer so unmap it */
6695 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6696 PAGE_SIZE, DMA_FROM_DEVICE);
6697 }
6698
6699 /* clear contents of rx_buffer */
6700 rx_buffer->page = NULL;
6701
6702 return skb;
6703}
6704
cd392f5c 6705static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6706 union e1000_adv_rx_desc *rx_desc,
6707 struct sk_buff *skb)
9d5c8243 6708{
bc8acf2c 6709 skb_checksum_none_assert(skb);
9d5c8243 6710
294e7d78 6711 /* Ignore Checksum bit is set */
3ceb90fd 6712 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6713 return;
6714
6715 /* Rx checksum disabled via ethtool */
6716 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6717 return;
85ad76b2 6718
9d5c8243 6719 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6720 if (igb_test_staterr(rx_desc,
6721 E1000_RXDEXT_STATERR_TCPE |
6722 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6723 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6724 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6725 * packets, (aka let the stack check the crc32c)
6726 */
866cff06
AD		 6727 if (!((skb->len == 60) &&
6728 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6729 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6730 ring->rx_stats.csum_err++;
12dcd86b
ED		 6731 u64_stats_update_end(&ring->rx_syncp);
6732 }
9d5c8243 6733 /* let the stack verify checksum errors */
9d5c8243
AK		 6734 return;
6735 }
6736 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6737 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6738 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6739 skb->ip_summed = CHECKSUM_UNNECESSARY;
6740
3ceb90fd
AD		 6741 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6742 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6743}
6744
077887c3
AD		 6745static inline void igb_rx_hash(struct igb_ring *ring,
6746 union e1000_adv_rx_desc *rx_desc,
6747 struct sk_buff *skb)
6748{
6749 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6750 skb_set_hash(skb,
6751 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6752 PKT_HASH_TYPE_L3);
077887c3
AD		 6753}
6754
2e334eee 6755/**
b980ac18
JK		 6756 * igb_is_non_eop - process handling of non-EOP buffers
6757 * @rx_ring: Rx ring being processed
6758 * @rx_desc: Rx descriptor for current buffer
6759 * @skb: current socket buffer containing buffer in progress
2e334eee 6760 *
b980ac18
JK		 6761 * This function updates next to clean. If the buffer is an EOP buffer
6762 * this function exits returning false, otherwise it will place the
6763 * sk_buff in the next buffer to be chained and return true indicating
6764 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6765 **/
6766static bool igb_is_non_eop(struct igb_ring *rx_ring,
6767 union e1000_adv_rx_desc *rx_desc)
6768{
6769 u32 ntc = rx_ring->next_to_clean + 1;
6770
6771 /* fetch, update, and store next to clean */
6772 ntc = (ntc < rx_ring->count) ? ntc : 0;
6773 rx_ring->next_to_clean = ntc;
6774
6775 prefetch(IGB_RX_DESC(rx_ring, ntc));
6776
6777 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6778 return false;
6779
6780 return true;
6781}
6782
1a1c225b 6783/**
b980ac18
JK		 6784 * igb_get_headlen - determine size of header for LRO/GRO
6785 * @data: pointer to the start of the headers
6786 * @max_len: total length of section to find headers in
1a1c225b 6787 *
b980ac18
JK		 6788 * This function is meant to determine the length of headers that will
6789 * be recognized by hardware for LRO, and GRO offloads. The main
6790 * motivation of doing this is to only perform one pull for IPv4 TCP
6791 * packets so that we can do basic things like calculating the gso_size
6792 * based on the average data per packet.
1a1c225b
AD		 6793 **/
6794static unsigned int igb_get_headlen(unsigned char *data,
6795 unsigned int max_len)
6796{
6797 union {
6798 unsigned char *network;
6799 /* l2 headers */
6800 struct ethhdr *eth;
6801 struct vlan_hdr *vlan;
6802 /* l3 headers */
6803 struct iphdr *ipv4;
6804 struct ipv6hdr *ipv6;
6805 } hdr;
6806 __be16 protocol;
6807 u8 nexthdr = 0; /* default to not TCP */
6808 u8 hlen;
6809
6810 /* this should never happen, but better safe than sorry */
6811 if (max_len < ETH_HLEN)
6812 return max_len;
6813
6814 /* initialize network frame pointer */
6815 hdr.network = data;
6816
6817 /* set first protocol and move network header forward */
6818 protocol = hdr.eth->h_proto;
6819 hdr.network += ETH_HLEN;
6820
6821 /* handle any vlan tag if present */
7c4d16ff 6822 if (protocol == htons(ETH_P_8021Q)) {
1a1c225b
AD		 6823 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6824 return max_len;
6825
6826 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6827 hdr.network += VLAN_HLEN;
6828 }
6829
6830 /* handle L3 protocols */
7c4d16ff 6831 if (protocol == htons(ETH_P_IP)) {
1a1c225b
AD		 6832 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6833 return max_len;
6834
6835 /* access ihl as a u8 to avoid unaligned access on ia64 */
6836 hlen = (hdr.network[0] & 0x0F) << 2;
6837
6838 /* verify hlen meets minimum size requirements */
6839 if (hlen < sizeof(struct iphdr))
6840 return hdr.network - data;
6841
f2fb4ab2 6842 /* record next protocol if header is present */
b9555f66 6843 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6844 nexthdr = hdr.ipv4->protocol;
7c4d16ff 6845 } else if (protocol == htons(ETH_P_IPV6)) {
1a1c225b
AD		 6846 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6847 return max_len;
6848
6849 /* record next protocol */
6850 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6851 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6852 } else {
6853 return hdr.network - data;
6854 }
6855
f2fb4ab2
AD		 6856 /* relocate pointer to start of L4 header */
6857 hdr.network += hlen;
6858
1a1c225b
AD		 6859 /* finally sort out TCP */
6860 if (nexthdr == IPPROTO_TCP) {
6861 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6862 return max_len;
6863
6864 /* access doff as a u8 to avoid unaligned access on ia64 */
6865 hlen = (hdr.network[12] & 0xF0) >> 2;
6866
6867 /* verify hlen meets minimum size requirements */
6868 if (hlen < sizeof(struct tcphdr))
6869 return hdr.network - data;
6870
6871 hdr.network += hlen;
6872 } else if (nexthdr == IPPROTO_UDP) {
6873 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6874 return max_len;
6875
6876 hdr.network += sizeof(struct udphdr);
6877 }
6878
b980ac18 6879 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6880 * data section of the packet and will be the end of the header.
6881 * If not then it probably represents the end of the last recognized
6882 * header.
6883 */
6884 if ((hdr.network - data) < max_len)
6885 return hdr.network - data;
6886 else
6887 return max_len;
6888}
6889
6890/**
b980ac18
JK		 6891 * igb_pull_tail - igb specific version of skb_pull_tail
6892 * @rx_ring: rx descriptor ring packet is being transacted on
6893 * @rx_desc: pointer to the EOP Rx descriptor
6894 * @skb: pointer to current skb being adjusted
1a1c225b 6895 *
b980ac18
JK		 6896 * This function is an igb specific version of __pskb_pull_tail. The
6897 * main difference between this version and the original function is that
6898 * this function can make several assumptions about the state of things
6899 * that allow for significant optimizations versus the standard function.
6900 * As a result we can do things like drop a frag and maintain an accurate
6901 * truesize for the skb.
1a1c225b
AD		 6902 */
6903static void igb_pull_tail(struct igb_ring *rx_ring,
6904 union e1000_adv_rx_desc *rx_desc,
6905 struct sk_buff *skb)
2d94d8ab 6906{
1a1c225b
AD		 6907 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6908 unsigned char *va;
6909 unsigned int pull_len;
6910
b980ac18 6911 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6912 * working with pages allocated out of the lomem pool per
6913 * alloc_page(GFP_ATOMIC)
2d94d8ab 6914 */
1a1c225b
AD		 6915 va = skb_frag_address(frag);
6916
1a1c225b
AD		 6917 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6918 /* retrieve timestamp from buffer */
6919 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6920
6921 /* update pointers to remove timestamp header */
6922 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6923 frag->page_offset += IGB_TS_HDR_LEN;
6924 skb->data_len -= IGB_TS_HDR_LEN;
6925 skb->len -= IGB_TS_HDR_LEN;
6926
6927 /* move va to start of packet data */
6928 va += IGB_TS_HDR_LEN;
6929 }
6930
b980ac18 6931 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6932 * 60 bytes if the skb->len is less than 60 for skb_pad.
6933 */
6934 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6935
6936 /* align pull length to size of long to optimize memcpy performance */
6937 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6938
6939 /* update all of the pointers */
6940 skb_frag_size_sub(frag, pull_len);
6941 frag->page_offset += pull_len;
6942 skb->data_len -= pull_len;
6943 skb->tail += pull_len;
6944}
6945
6946/**
b980ac18
JK		 6947 * igb_cleanup_headers - Correct corrupted or empty headers
6948 * @rx_ring: rx descriptor ring packet is being transacted on
6949 * @rx_desc: pointer to the EOP Rx descriptor
6950 * @skb: pointer to current skb being fixed
1a1c225b 6951 *
b980ac18
JK		 6952 * Address the case where we are pulling data in on pages only
6953 * and as such no data is present in the skb header.
1a1c225b 6954 *
b980ac18
JK		 6955 * In addition if skb is not at least 60 bytes we need to pad it so that
6956 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6957 *
b980ac18 6958 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6959 **/
6960static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6961 union e1000_adv_rx_desc *rx_desc,
6962 struct sk_buff *skb)
6963{
1a1c225b
AD		 6964 if (unlikely((igb_test_staterr(rx_desc,
6965 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6966 struct net_device *netdev = rx_ring->netdev;
6967 if (!(netdev->features & NETIF_F_RXALL)) {
6968 dev_kfree_skb_any(skb);
6969 return true;
6970 }
6971 }
6972
6973 /* place header in linear portion of buffer */
6974 if (skb_is_nonlinear(skb))
6975 igb_pull_tail(rx_ring, rx_desc, skb);
6976
6977 /* if skb_pad returns an error the skb was freed */
6978 if (unlikely(skb->len < 60)) {
6979 int pad_len = 60 - skb->len;
6980
6981 if (skb_pad(skb, pad_len))
6982 return true;
6983 __skb_put(skb, pad_len);
6984 }
6985
6986 return false;
2d94d8ab
AD		 6987}
6988
db2ee5bd 6989/**
b980ac18
JK		 6990 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6991 * @rx_ring: rx descriptor ring packet is being transacted on
6992 * @rx_desc: pointer to the EOP Rx descriptor
6993 * @skb: pointer to current skb being populated
db2ee5bd 6994 *
b980ac18
JK		 6995 * This function checks the ring, descriptor, and packet information in
6996 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6997 * other fields within the skb.
db2ee5bd
AD		 6998 **/
6999static void igb_process_skb_fields(struct igb_ring *rx_ring,
7000 union e1000_adv_rx_desc *rx_desc,
7001 struct sk_buff *skb)
7002{
7003 struct net_device *dev = rx_ring->netdev;
7004
7005 igb_rx_hash(rx_ring, rx_desc, skb);
7006
7007 igb_rx_checksum(rx_ring, rx_desc, skb);
7008
5499a968
JK		 7009 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7010 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7011 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 7012
f646968f 7013 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 7014 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7015 u16 vid;
9005df38 7016
db2ee5bd
AD		 7017 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7018 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7019 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7020 else
7021 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7022
86a9bad3 7023 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 7024 }
7025
7026 skb_record_rx_queue(skb, rx_ring->queue_index);
7027
7028 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7029}
7030
2e334eee 7031static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 7032{
0ba82994 7033 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 7034 struct sk_buff *skb = rx_ring->skb;
9d5c8243 7035 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 7036 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 7037
57ba34c9 7038 while (likely(total_packets < budget)) {
2e334eee 7039 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7040
2e334eee
AD		 7041 /* return some buffers to hardware, one at a time is too slow */
7042 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7043 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7044 cleaned_count = 0;
7045 }
bf36c1a0 7046
2e334eee 7047 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7048
2e334eee
AD		 7049 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
7050 break;
9d5c8243 7051
74e238ea
AD		 7052 /* This memory barrier is needed to keep us from reading
7053 * any other fields out of the rx_desc until we know the
7054 * RXD_STAT_DD bit is set
7055 */
7056 rmb();
7057
2e334eee 7058 /* retrieve a buffer from the ring */
f9d40f6a 7059 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7060
2e334eee
AD		 7061 /* exit if we failed to retrieve a buffer */
7062 if (!skb)
7063 break;
1a1c225b 7064
2e334eee 7065 cleaned_count++;
1a1c225b 7066
2e334eee
AD		 7067 /* fetch next buffer in frame if non-eop */
7068 if (igb_is_non_eop(rx_ring, rx_desc))
7069 continue;
1a1c225b
AD		 7070
7071 /* verify the packet layout is correct */
7072 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7073 skb = NULL;
7074 continue;
9d5c8243 7075 }
9d5c8243 7076
db2ee5bd 7077 /* probably a little skewed due to removing CRC */
3ceb90fd 7078 total_bytes += skb->len;
3ceb90fd 7079
db2ee5bd
AD		 7080 /* populate checksum, timestamp, VLAN, and protocol */
7081 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7082
b2cb09b1 7083 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7084
1a1c225b
AD		 7085 /* reset skb pointer */
7086 skb = NULL;
7087
2e334eee
AD		 7088 /* update budget accounting */
7089 total_packets++;
57ba34c9 7090 }
bf36c1a0 7091
1a1c225b
AD		 7092 /* place incomplete frames back on ring for completion */
7093 rx_ring->skb = skb;
7094
12dcd86b 7095 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7096 rx_ring->rx_stats.packets += total_packets;
7097 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7098 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7099 q_vector->rx.total_packets += total_packets;
7100 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7101
7102 if (cleaned_count)
cd392f5c 7103 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7104
da1f1dfe 7105 return total_packets < budget;
9d5c8243
AK		 7106}
7107
c023cd88 7108static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7109 struct igb_rx_buffer *bi)
c023cd88
AD		 7110{
7111 struct page *page = bi->page;
cbc8e55f 7112 dma_addr_t dma;
c023cd88 7113
cbc8e55f
AD		 7114 /* since we are recycling buffers we should seldom need to alloc */
7115 if (likely(page))
c023cd88
AD		 7116 return true;
7117
cbc8e55f
AD		 7118 /* alloc new page for storage */
7119 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
7120 if (unlikely(!page)) {
7121 rx_ring->rx_stats.alloc_failed++;
7122 return false;
c023cd88
AD		 7123 }
7124
cbc8e55f
AD		 7125 /* map page for use */
7126 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7127
b980ac18 7128 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7129 * there isn't much point in holding memory we can't use
7130 */
1a1c225b 7131 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7132 __free_page(page);
7133
c023cd88
AD		 7134 rx_ring->rx_stats.alloc_failed++;
7135 return false;
7136 }
7137
1a1c225b 7138 bi->dma = dma;
cbc8e55f
AD		 7139 bi->page = page;
7140 bi->page_offset = 0;
1a1c225b 7141
c023cd88
AD		 7142 return true;
7143}
7144
9d5c8243 7145/**
b980ac18
JK		 7146 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7147 * @adapter: address of board private structure
9d5c8243 7148 **/
cd392f5c 7149void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7150{
9d5c8243 7151 union e1000_adv_rx_desc *rx_desc;
06034649 7152 struct igb_rx_buffer *bi;
c023cd88 7153 u16 i = rx_ring->next_to_use;
9d5c8243 7154
cbc8e55f
AD		 7155 /* nothing to do */
7156 if (!cleaned_count)
7157 return;
7158
60136906 7159 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7160 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7161 i -= rx_ring->count;
9d5c8243 7162
cbc8e55f 7163 do {
1a1c225b 7164 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7165 break;
9d5c8243 7166
b980ac18 7167 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7168 * because each write-back erases this info.
7169 */
f9d40f6a 7170 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7171
c023cd88
AD		 7172 rx_desc++;
7173 bi++;
9d5c8243 7174 i++;
c023cd88 7175 if (unlikely(!i)) {
60136906 7176 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7177 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7178 i -= rx_ring->count;
7179 }
7180
7181 /* clear the hdr_addr for the next_to_use descriptor */
7182 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7183
7184 cleaned_count--;
7185 } while (cleaned_count);
9d5c8243 7186
c023cd88
AD		 7187 i += rx_ring->count;
7188
9d5c8243 7189 if (rx_ring->next_to_use != i) {
cbc8e55f 7190 /* record the next descriptor to use */
9d5c8243 7191 rx_ring->next_to_use = i;
9d5c8243 7192
cbc8e55f
AD		 7193 /* update next to alloc since we have filled the ring */
7194 rx_ring->next_to_alloc = i;
7195
b980ac18 7196 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7197 * know there are new descriptors to fetch. (Only
7198 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7199 * such as IA-64).
7200 */
9d5c8243 7201 wmb();
fce99e34 7202 writel(i, rx_ring->tail);
9d5c8243
AK		 7203 }
7204}
7205
7206/**
7207 * igb_mii_ioctl -
7208 * @netdev:
7209 * @ifreq:
7210 * @cmd:
7211 **/
7212static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7213{
7214 struct igb_adapter *adapter = netdev_priv(netdev);
7215 struct mii_ioctl_data *data = if_mii(ifr);
7216
7217 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7218 return -EOPNOTSUPP;
7219
7220 switch (cmd) {
7221 case SIOCGMIIPHY:
7222 data->phy_id = adapter->hw.phy.addr;
7223 break;
7224 case SIOCGMIIREG:
f5f4cf08 7225 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7226 &data->val_out))
9d5c8243
AK		 7227 return -EIO;
7228 break;
7229 case SIOCSMIIREG:
7230 default:
7231 return -EOPNOTSUPP;
7232 }
7233 return 0;
7234}
7235
7236/**
7237 * igb_ioctl -
7238 * @netdev:
7239 * @ifreq:
7240 * @cmd:
7241 **/
7242static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7243{
7244 switch (cmd) {
7245 case SIOCGMIIPHY:
7246 case SIOCGMIIREG:
7247 case SIOCSMIIREG:
7248 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7249 case SIOCGHWTSTAMP:
7250 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7251 case SIOCSHWTSTAMP:
6ab5f7b2 7252 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7253 default:
7254 return -EOPNOTSUPP;
7255 }
7256}
7257
94826487
TF		 7258void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7259{
7260 struct igb_adapter *adapter = hw->back;
7261
7262 pci_read_config_word(adapter->pdev, reg, value);
7263}
7264
7265void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7266{
7267 struct igb_adapter *adapter = hw->back;
7268
7269 pci_write_config_word(adapter->pdev, reg, *value);
7270}
7271
009bc06e
AD		 7272s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7273{
7274 struct igb_adapter *adapter = hw->back;
009bc06e 7275
23d028cc 7276 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7277 return -E1000_ERR_CONFIG;
7278
009bc06e
AD		 7279 return 0;
7280}
7281
7282s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7283{
7284 struct igb_adapter *adapter = hw->back;
009bc06e 7285
23d028cc 7286 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7287 return -E1000_ERR_CONFIG;
7288
009bc06e
AD		 7289 return 0;
7290}
7291
c8f44aff 7292static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7293{
7294 struct igb_adapter *adapter = netdev_priv(netdev);
7295 struct e1000_hw *hw = &adapter->hw;
7296 u32 ctrl, rctl;
f646968f 7297 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7298
5faf030c 7299 if (enable) {
9d5c8243
AK		 7300 /* enable VLAN tag insert/strip */
7301 ctrl = rd32(E1000_CTRL);
7302 ctrl |= E1000_CTRL_VME;
7303 wr32(E1000_CTRL, ctrl);
7304
51466239 7305 /* Disable CFI check */
9d5c8243 7306 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7307 rctl &= ~E1000_RCTL_CFIEN;
7308 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7309 } else {
7310 /* disable VLAN tag insert/strip */
7311 ctrl = rd32(E1000_CTRL);
7312 ctrl &= ~E1000_CTRL_VME;
7313 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7314 }
7315
e1739522 7316 igb_rlpml_set(adapter);
9d5c8243
AK		 7317}
7318
80d5c368
PM		 7319static int igb_vlan_rx_add_vid(struct net_device *netdev,
7320 __be16 proto, u16 vid)
9d5c8243
AK		 7321{
7322 struct igb_adapter *adapter = netdev_priv(netdev);
7323 struct e1000_hw *hw = &adapter->hw;
4ae196df 7324 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7325
51466239
AD		 7326 /* attempt to add filter to vlvf array */
7327 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7328
51466239
AD		 7329 /* add the filter since PF can receive vlans w/o entry in vlvf */
7330 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7331
7332 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7333
7334 return 0;
9d5c8243
AK		 7335}
7336
80d5c368
PM		 7337static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7338 __be16 proto, u16 vid)
9d5c8243
AK		 7339{
7340 struct igb_adapter *adapter = netdev_priv(netdev);
7341 struct e1000_hw *hw = &adapter->hw;
4ae196df 7342 int pf_id = adapter->vfs_allocated_count;
51466239 7343 s32 err;
9d5c8243 7344
51466239
AD		 7345 /* remove vlan from VLVF table array */
7346 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7347
51466239
AD		 7348 /* if vid was not present in VLVF just remove it from table */
7349 if (err)
4ae196df 7350 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7351
7352 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7353
7354 return 0;
9d5c8243
AK		 7355}
7356
7357static void igb_restore_vlan(struct igb_adapter *adapter)
7358{
b2cb09b1 7359 u16 vid;
9d5c8243 7360
5faf030c
AD		 7361 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7362
b2cb09b1 7363 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7364 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7365}
7366
14ad2513 7367int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7368{
090b1795 7369 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7370 struct e1000_mac_info *mac = &adapter->hw.mac;
7371
7372 mac->autoneg = 0;
7373
14ad2513 7374 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7375 * for the switch() below to work
7376 */
14ad2513
DD		 7377 if ((spd & 1) || (dplx & ~1))
7378 goto err_inval;
7379
f502ef7d
AA		 7380 /* Fiber NIC's only allow 1000 gbps Full duplex
7381 * and 100Mbps Full duplex for 100baseFx sfp
7382 */
7383 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7384 switch (spd + dplx) {
7385 case SPEED_10 + DUPLEX_HALF:
7386 case SPEED_10 + DUPLEX_FULL:
7387 case SPEED_100 + DUPLEX_HALF:
7388 goto err_inval;
7389 default:
7390 break;
7391 }
7392 }
cd2638a8 7393
14ad2513 7394 switch (spd + dplx) {
9d5c8243
AK		 7395 case SPEED_10 + DUPLEX_HALF:
7396 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7397 break;
7398 case SPEED_10 + DUPLEX_FULL:
7399 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7400 break;
7401 case SPEED_100 + DUPLEX_HALF:
7402 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7403 break;
7404 case SPEED_100 + DUPLEX_FULL:
7405 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7406 break;
7407 case SPEED_1000 + DUPLEX_FULL:
7408 mac->autoneg = 1;
7409 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7410 break;
7411 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7412 default:
14ad2513 7413 goto err_inval;
9d5c8243 7414 }
8376dad0
JB		 7415
7416 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7417 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7418
9d5c8243 7419 return 0;
14ad2513
DD		 7420
7421err_inval:
7422 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7423 return -EINVAL;
9d5c8243
AK		 7424}
7425
749ab2cd
YZ		 7426static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7427 bool runtime)
9d5c8243
AK		 7428{
7429 struct net_device *netdev = pci_get_drvdata(pdev);
7430 struct igb_adapter *adapter = netdev_priv(netdev);
7431 struct e1000_hw *hw = &adapter->hw;
2d064c06 7432 u32 ctrl, rctl, status;
749ab2cd 7433 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7434#ifdef CONFIG_PM
7435 int retval = 0;
7436#endif
7437
7438 netif_device_detach(netdev);
7439
a88f10ec 7440 if (netif_running(netdev))
749ab2cd 7441 __igb_close(netdev, true);
a88f10ec 7442
047e0030 7443 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7444
7445#ifdef CONFIG_PM
7446 retval = pci_save_state(pdev);
7447 if (retval)
7448 return retval;
7449#endif
7450
7451 status = rd32(E1000_STATUS);
7452 if (status & E1000_STATUS_LU)
7453 wufc &= ~E1000_WUFC_LNKC;
7454
7455 if (wufc) {
7456 igb_setup_rctl(adapter);
ff41f8dc 7457 igb_set_rx_mode(netdev);
9d5c8243
AK		 7458
7459 /* turn on all-multi mode if wake on multicast is enabled */
7460 if (wufc & E1000_WUFC_MC) {
7461 rctl = rd32(E1000_RCTL);
7462 rctl |= E1000_RCTL_MPE;
7463 wr32(E1000_RCTL, rctl);
7464 }
7465
7466 ctrl = rd32(E1000_CTRL);
7467 /* advertise wake from D3Cold */
7468 #define E1000_CTRL_ADVD3WUC 0x00100000
7469 /* phy power management enable */
7470 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7471 ctrl |= E1000_CTRL_ADVD3WUC;
7472 wr32(E1000_CTRL, ctrl);
7473
9d5c8243 7474 /* Allow time for pending master requests to run */
330a6d6a 7475 igb_disable_pcie_master(hw);
9d5c8243
AK		 7476
7477 wr32(E1000_WUC, E1000_WUC_PME_EN);
7478 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7479 } else {
7480 wr32(E1000_WUC, 0);
7481 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7482 }
7483
3fe7c4c9
RW		 7484 *enable_wake = wufc || adapter->en_mng_pt;
7485 if (!*enable_wake)
88a268c1
NN		 7486 igb_power_down_link(adapter);
7487 else
7488 igb_power_up_link(adapter);
9d5c8243
AK		 7489
7490 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7491 * would have already happened in close and is redundant.
7492 */
9d5c8243
AK		 7493 igb_release_hw_control(adapter);
7494
7495 pci_disable_device(pdev);
7496
9d5c8243
AK		 7497 return 0;
7498}
7499
7500#ifdef CONFIG_PM
d9dd966d 7501#ifdef CONFIG_PM_SLEEP
749ab2cd 7502static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7503{
7504 int retval;
7505 bool wake;
749ab2cd 7506 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7507
749ab2cd 7508 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7509 if (retval)
7510 return retval;
7511
7512 if (wake) {
7513 pci_prepare_to_sleep(pdev);
7514 } else {
7515 pci_wake_from_d3(pdev, false);
7516 pci_set_power_state(pdev, PCI_D3hot);
7517 }
7518
7519 return 0;
7520}
d9dd966d 7521#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7522
749ab2cd 7523static int igb_resume(struct device *dev)
9d5c8243 7524{
749ab2cd 7525 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7526 struct net_device *netdev = pci_get_drvdata(pdev);
7527 struct igb_adapter *adapter = netdev_priv(netdev);
7528 struct e1000_hw *hw = &adapter->hw;
7529 u32 err;
7530
7531 pci_set_power_state(pdev, PCI_D0);
7532 pci_restore_state(pdev);
b94f2d77 7533 pci_save_state(pdev);
42bfd33a 7534
aed5dec3 7535 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7536 if (err) {
7537 dev_err(&pdev->dev,
7538 "igb: Cannot enable PCI device from suspend\n");
7539 return err;
7540 }
7541 pci_set_master(pdev);
7542
7543 pci_enable_wake(pdev, PCI_D3hot, 0);
7544 pci_enable_wake(pdev, PCI_D3cold, 0);
7545
53c7d064 7546 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7547 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7548 return -ENOMEM;
9d5c8243
AK		 7549 }
7550
9d5c8243 7551 igb_reset(adapter);
a8564f03
AD		 7552
7553 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7554 * driver.
7555 */
a8564f03
AD		 7556 igb_get_hw_control(adapter);
7557
9d5c8243
AK		 7558 wr32(E1000_WUS, ~0);
7559
749ab2cd 7560 if (netdev->flags & IFF_UP) {
0c2cc02e 7561 rtnl_lock();
749ab2cd 7562 err = __igb_open(netdev, true);
0c2cc02e 7563 rtnl_unlock();
a88f10ec
AD		 7564 if (err)
7565 return err;
7566 }
9d5c8243
AK		 7567
7568 netif_device_attach(netdev);
749ab2cd
YZ		 7569 return 0;
7570}
7571
7572#ifdef CONFIG_PM_RUNTIME
7573static int igb_runtime_idle(struct device *dev)
7574{
7575 struct pci_dev *pdev = to_pci_dev(dev);
7576 struct net_device *netdev = pci_get_drvdata(pdev);
7577 struct igb_adapter *adapter = netdev_priv(netdev);
7578
7579 if (!igb_has_link(adapter))
7580 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7581
7582 return -EBUSY;
7583}
7584
7585static int igb_runtime_suspend(struct device *dev)
7586{
7587 struct pci_dev *pdev = to_pci_dev(dev);
7588 int retval;
7589 bool wake;
7590
7591 retval = __igb_shutdown(pdev, &wake, 1);
7592 if (retval)
7593 return retval;
7594
7595 if (wake) {
7596 pci_prepare_to_sleep(pdev);
7597 } else {
7598 pci_wake_from_d3(pdev, false);
7599 pci_set_power_state(pdev, PCI_D3hot);
7600 }
9d5c8243 7601
9d5c8243
AK		 7602 return 0;
7603}
749ab2cd
YZ		 7604
7605static int igb_runtime_resume(struct device *dev)
7606{
7607 return igb_resume(dev);
7608}
7609#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7610#endif
7611
7612static void igb_shutdown(struct pci_dev *pdev)
7613{
3fe7c4c9
RW		 7614 bool wake;
7615
749ab2cd 7616 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7617
7618 if (system_state == SYSTEM_POWER_OFF) {
7619 pci_wake_from_d3(pdev, wake);
7620 pci_set_power_state(pdev, PCI_D3hot);
7621 }
9d5c8243
AK		 7622}
7623
fa44f2f1
GR		 7624#ifdef CONFIG_PCI_IOV
7625static int igb_sriov_reinit(struct pci_dev *dev)
7626{
7627 struct net_device *netdev = pci_get_drvdata(dev);
7628 struct igb_adapter *adapter = netdev_priv(netdev);
7629 struct pci_dev *pdev = adapter->pdev;
7630
7631 rtnl_lock();
7632
7633 if (netif_running(netdev))
7634 igb_close(netdev);
76252723
SA		 7635 else
7636 igb_reset(adapter);
fa44f2f1
GR		 7637
7638 igb_clear_interrupt_scheme(adapter);
7639
7640 igb_init_queue_configuration(adapter);
7641
7642 if (igb_init_interrupt_scheme(adapter, true)) {
7643 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7644 return -ENOMEM;
7645 }
7646
7647 if (netif_running(netdev))
7648 igb_open(netdev);
7649
7650 rtnl_unlock();
7651
7652 return 0;
7653}
7654
7655static int igb_pci_disable_sriov(struct pci_dev *dev)
7656{
7657 int err = igb_disable_sriov(dev);
7658
7659 if (!err)
7660 err = igb_sriov_reinit(dev);
7661
7662 return err;
7663}
7664
7665static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7666{
7667 int err = igb_enable_sriov(dev, num_vfs);
7668
7669 if (err)
7670 goto out;
7671
7672 err = igb_sriov_reinit(dev);
7673 if (!err)
7674 return num_vfs;
7675
7676out:
7677 return err;
7678}
7679
7680#endif
7681static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7682{
7683#ifdef CONFIG_PCI_IOV
7684 if (num_vfs == 0)
7685 return igb_pci_disable_sriov(dev);
7686 else
7687 return igb_pci_enable_sriov(dev, num_vfs);
7688#endif
7689 return 0;
7690}
7691
9d5c8243 7692#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7693/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7694 * without having to re-enable interrupts. It's not called while
7695 * the interrupt routine is executing.
7696 */
7697static void igb_netpoll(struct net_device *netdev)
7698{
7699 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7700 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7701 struct igb_q_vector *q_vector;
9d5c8243 7702 int i;
9d5c8243 7703
047e0030 7704 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7705 q_vector = adapter->q_vector[i];
cd14ef54 7706 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7707 wr32(E1000_EIMC, q_vector->eims_value);
7708 else
7709 igb_irq_disable(adapter);
047e0030 7710 napi_schedule(&q_vector->napi);
eebbbdba 7711 }
9d5c8243
AK		 7712}
7713#endif /* CONFIG_NET_POLL_CONTROLLER */
7714
7715/**
b980ac18
JK		 7716 * igb_io_error_detected - called when PCI error is detected
7717 * @pdev: Pointer to PCI device
7718 * @state: The current pci connection state
9d5c8243 7719 *
b980ac18
JK		 7720 * This function is called after a PCI bus error affecting
7721 * this device has been detected.
7722 **/
9d5c8243
AK		 7723static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7724 pci_channel_state_t state)
7725{
7726 struct net_device *netdev = pci_get_drvdata(pdev);
7727 struct igb_adapter *adapter = netdev_priv(netdev);
7728
7729 netif_device_detach(netdev);
7730
59ed6eec
AD		 7731 if (state == pci_channel_io_perm_failure)
7732 return PCI_ERS_RESULT_DISCONNECT;
7733
9d5c8243
AK		 7734 if (netif_running(netdev))
7735 igb_down(adapter);
7736 pci_disable_device(pdev);
7737
7738 /* Request a slot slot reset. */
7739 return PCI_ERS_RESULT_NEED_RESET;
7740}
7741
7742/**
b980ac18
JK		 7743 * igb_io_slot_reset - called after the pci bus has been reset.
7744 * @pdev: Pointer to PCI device
9d5c8243 7745 *
b980ac18
JK		 7746 * Restart the card from scratch, as if from a cold-boot. Implementation
7747 * resembles the first-half of the igb_resume routine.
7748 **/
9d5c8243
AK		 7749static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7750{
7751 struct net_device *netdev = pci_get_drvdata(pdev);
7752 struct igb_adapter *adapter = netdev_priv(netdev);
7753 struct e1000_hw *hw = &adapter->hw;
40a914fa 7754 pci_ers_result_t result;
42bfd33a 7755 int err;
9d5c8243 7756
aed5dec3 7757 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7758 dev_err(&pdev->dev,
7759 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7760 result = PCI_ERS_RESULT_DISCONNECT;
7761 } else {
7762 pci_set_master(pdev);
7763 pci_restore_state(pdev);
b94f2d77 7764 pci_save_state(pdev);
9d5c8243 7765
40a914fa
AD		 7766 pci_enable_wake(pdev, PCI_D3hot, 0);
7767 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7768
40a914fa
AD		 7769 igb_reset(adapter);
7770 wr32(E1000_WUS, ~0);
7771 result = PCI_ERS_RESULT_RECOVERED;
7772 }
9d5c8243 7773
ea943d41
JK		 7774 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7775 if (err) {
b980ac18
JK		 7776 dev_err(&pdev->dev,
7777 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7778 err);
ea943d41
JK		 7779 /* non-fatal, continue */
7780 }
40a914fa
AD		 7781
7782 return result;
9d5c8243
AK		 7783}
7784
7785/**
b980ac18
JK		 7786 * igb_io_resume - called when traffic can start flowing again.
7787 * @pdev: Pointer to PCI device
9d5c8243 7788 *
b980ac18
JK		 7789 * This callback is called when the error recovery driver tells us that
7790 * its OK to resume normal operation. Implementation resembles the
7791 * second-half of the igb_resume routine.
9d5c8243
AK		 7792 */
7793static void igb_io_resume(struct pci_dev *pdev)
7794{
7795 struct net_device *netdev = pci_get_drvdata(pdev);
7796 struct igb_adapter *adapter = netdev_priv(netdev);
7797
9d5c8243
AK		 7798 if (netif_running(netdev)) {
7799 if (igb_up(adapter)) {
7800 dev_err(&pdev->dev, "igb_up failed after reset\n");
7801 return;
7802 }
7803 }
7804
7805 netif_device_attach(netdev);
7806
7807 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7808 * driver.
7809 */
9d5c8243 7810 igb_get_hw_control(adapter);
9d5c8243
AK		 7811}
7812
26ad9178 7813static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7814 u8 qsel)
26ad9178
AD		 7815{
7816 u32 rar_low, rar_high;
7817 struct e1000_hw *hw = &adapter->hw;
7818
7819 /* HW expects these in little endian so we reverse the byte order
7820 * from network order (big endian) to little endian
7821 */
7822 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7823 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7824 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7825
7826 /* Indicate to hardware the Address is Valid. */
7827 rar_high |= E1000_RAH_AV;
7828
7829 if (hw->mac.type == e1000_82575)
7830 rar_high |= E1000_RAH_POOL_1 * qsel;
7831 else
7832 rar_high |= E1000_RAH_POOL_1 << qsel;
7833
7834 wr32(E1000_RAL(index), rar_low);
7835 wrfl();
7836 wr32(E1000_RAH(index), rar_high);
7837 wrfl();
7838}
7839
4ae196df 7840static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7841 int vf, unsigned char *mac_addr)
4ae196df
AD		 7842{
7843 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7844 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7845 * towards the first, as a result a collision should not be possible
7846 */
ff41f8dc 7847 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7848
37680117 7849 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7850
26ad9178 7851 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7852
7853 return 0;
7854}
7855
8151d294
WM		 7856static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7857{
7858 struct igb_adapter *adapter = netdev_priv(netdev);
7859 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7860 return -EINVAL;
7861 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7862 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7863 dev_info(&adapter->pdev->dev,
7864 "Reload the VF driver to make this change effective.");
8151d294 7865 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7866 dev_warn(&adapter->pdev->dev,
7867 "The VF MAC address has been set, but the PF device is not up.\n");
7868 dev_warn(&adapter->pdev->dev,
7869 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7870 }
7871 return igb_set_vf_mac(adapter, vf, mac);
7872}
7873
17dc566c
LL		 7874static int igb_link_mbps(int internal_link_speed)
7875{
7876 switch (internal_link_speed) {
7877 case SPEED_100:
7878 return 100;
7879 case SPEED_1000:
7880 return 1000;
7881 default:
7882 return 0;
7883 }
7884}
7885
7886static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7887 int link_speed)
7888{
7889 int rf_dec, rf_int;
7890 u32 bcnrc_val;
7891
7892 if (tx_rate != 0) {
7893 /* Calculate the rate factor values to set */
7894 rf_int = link_speed / tx_rate;
7895 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7896 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7897 tx_rate;
17dc566c
LL		 7898
7899 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7900 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7901 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7902 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7903 } else {
7904 bcnrc_val = 0;
7905 }
7906
7907 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7908 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7909 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7910 */
7911 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7912 wr32(E1000_RTTBCNRC, bcnrc_val);
7913}
7914
7915static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7916{
7917 int actual_link_speed, i;
7918 bool reset_rate = false;
7919
7920 /* VF TX rate limit was not set or not supported */
7921 if ((adapter->vf_rate_link_speed == 0) ||
7922 (adapter->hw.mac.type != e1000_82576))
7923 return;
7924
7925 actual_link_speed = igb_link_mbps(adapter->link_speed);
7926 if (actual_link_speed != adapter->vf_rate_link_speed) {
7927 reset_rate = true;
7928 adapter->vf_rate_link_speed = 0;
7929 dev_info(&adapter->pdev->dev,
b980ac18 7930 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7931 }
7932
7933 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7934 if (reset_rate)
7935 adapter->vf_data[i].tx_rate = 0;
7936
7937 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7938 adapter->vf_data[i].tx_rate,
7939 actual_link_speed);
17dc566c
LL		 7940 }
7941}
7942
ed616689
SC		 7943static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7944 int min_tx_rate, int max_tx_rate)
8151d294 7945{
17dc566c
LL		 7946 struct igb_adapter *adapter = netdev_priv(netdev);
7947 struct e1000_hw *hw = &adapter->hw;
7948 int actual_link_speed;
7949
7950 if (hw->mac.type != e1000_82576)
7951 return -EOPNOTSUPP;
7952
ed616689
SC		 7953 if (min_tx_rate)
7954 return -EINVAL;
7955
17dc566c
LL		 7956 actual_link_speed = igb_link_mbps(adapter->link_speed);
7957 if ((vf >= adapter->vfs_allocated_count) ||
7958 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7959 (max_tx_rate < 0) ||
7960 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7961 return -EINVAL;
7962
7963 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7964 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7965 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7966
7967 return 0;
8151d294
WM		 7968}
7969
70ea4783
LL		 7970static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7971 bool setting)
7972{
7973 struct igb_adapter *adapter = netdev_priv(netdev);
7974 struct e1000_hw *hw = &adapter->hw;
7975 u32 reg_val, reg_offset;
7976
7977 if (!adapter->vfs_allocated_count)
7978 return -EOPNOTSUPP;
7979
7980 if (vf >= adapter->vfs_allocated_count)
7981 return -EINVAL;
7982
7983 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7984 reg_val = rd32(reg_offset);
7985 if (setting)
7986 reg_val |= ((1 << vf) |
7987 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7988 else
7989 reg_val &= ~((1 << vf) |
7990 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7991 wr32(reg_offset, reg_val);
7992
7993 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7994 return 0;
70ea4783
LL		 7995}
7996
8151d294
WM		 7997static int igb_ndo_get_vf_config(struct net_device *netdev,
7998 int vf, struct ifla_vf_info *ivi)
7999{
8000 struct igb_adapter *adapter = netdev_priv(netdev);
8001 if (vf >= adapter->vfs_allocated_count)
8002 return -EINVAL;
8003 ivi->vf = vf;
8004 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 8005 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8006 ivi->min_tx_rate = 0;
8151d294
WM		 8007 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8008 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 8009 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 8010 return 0;
8011}
8012
4ae196df
AD		 8013static void igb_vmm_control(struct igb_adapter *adapter)
8014{
8015 struct e1000_hw *hw = &adapter->hw;
10d8e907 8016 u32 reg;
4ae196df 8017
52a1dd4d
AD		 8018 switch (hw->mac.type) {
8019 case e1000_82575:
f96a8a0b
CW		 8020 case e1000_i210:
8021 case e1000_i211:
ceb5f13b 8022 case e1000_i354:
52a1dd4d
AD		 8023 default:
8024 /* replication is not supported for 82575 */
4ae196df 8025 return;
52a1dd4d
AD		 8026 case e1000_82576:
8027 /* notify HW that the MAC is adding vlan tags */
8028 reg = rd32(E1000_DTXCTL);
8029 reg |= E1000_DTXCTL_VLAN_ADDED;
8030 wr32(E1000_DTXCTL, reg);
b26141d4 8031 /* Fall through */
52a1dd4d
AD		 8032 case e1000_82580:
8033 /* enable replication vlan tag stripping */
8034 reg = rd32(E1000_RPLOLR);
8035 reg |= E1000_RPLOLR_STRVLAN;
8036 wr32(E1000_RPLOLR, reg);
b26141d4 8037 /* Fall through */
d2ba2ed8
AD		 8038 case e1000_i350:
8039 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8040 break;
8041 }
10d8e907 8042
d4960307
AD		 8043 if (adapter->vfs_allocated_count) {
8044 igb_vmdq_set_loopback_pf(hw, true);
8045 igb_vmdq_set_replication_pf(hw, true);
13800469 8046 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8047 adapter->vfs_allocated_count);
d4960307
AD		 8048 } else {
8049 igb_vmdq_set_loopback_pf(hw, false);
8050 igb_vmdq_set_replication_pf(hw, false);
8051 }
4ae196df
AD		 8052}
8053
b6e0c419
CW		 8054static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8055{
8056 struct e1000_hw *hw = &adapter->hw;
8057 u32 dmac_thr;
8058 u16 hwm;
8059
8060 if (hw->mac.type > e1000_82580) {
8061 if (adapter->flags & IGB_FLAG_DMAC) {
8062 u32 reg;
8063
8064 /* force threshold to 0. */
8065 wr32(E1000_DMCTXTH, 0);
8066
b980ac18 8067 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8068 * than the Rx threshold. Set hwm to PBA - max frame
8069 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8070 */
e8c626e9
MV		 8071 hwm = 64 * pba - adapter->max_frame_size / 16;
8072 if (hwm < 64 * (pba - 6))
8073 hwm = 64 * (pba - 6);
8074 reg = rd32(E1000_FCRTC);
8075 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8076 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8077 & E1000_FCRTC_RTH_COAL_MASK);
8078 wr32(E1000_FCRTC, reg);
8079
b980ac18 8080 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8081 * frame size, capping it at PBA - 10KB.
8082 */
8083 dmac_thr = pba - adapter->max_frame_size / 512;
8084 if (dmac_thr < pba - 10)
8085 dmac_thr = pba - 10;
b6e0c419
CW		 8086 reg = rd32(E1000_DMACR);
8087 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8088 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8089 & E1000_DMACR_DMACTHR_MASK);
8090
8091 /* transition to L0x or L1 if available..*/
8092 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8093
8094 /* watchdog timer= +-1000 usec in 32usec intervals */
8095 reg |= (1000 >> 5);
0c02dd98
MV		 8096
8097 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8098 if (hw->mac.type != e1000_i354)
8099 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8100
b6e0c419
CW		 8101 wr32(E1000_DMACR, reg);
8102
b980ac18 8103 /* no lower threshold to disable
b6e0c419
CW		 8104 * coalescing(smart fifb)-UTRESH=0
8105 */
8106 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8107
8108 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8109
8110 wr32(E1000_DMCTLX, reg);
8111
b980ac18 8112 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8113 * DMA coal
8114 */
8115 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8116 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8117
b980ac18 8118 /* make low power state decision controlled
b6e0c419
CW		 8119 * by DMA coal
8120 */
8121 reg = rd32(E1000_PCIEMISC);
8122 reg &= ~E1000_PCIEMISC_LX_DECISION;
8123 wr32(E1000_PCIEMISC, reg);
8124 } /* endif adapter->dmac is not disabled */
8125 } else if (hw->mac.type == e1000_82580) {
8126 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8127
b6e0c419
CW		 8128 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8129 wr32(E1000_DMACR, 0);
8130 }
8131}
8132
b980ac18
JK		 8133/**
8134 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8135 * @hw: pointer to hardware structure
8136 * @byte_offset: byte offset to read
8137 * @dev_addr: device address
8138 * @data: value read
8139 *
8140 * Performs byte read operation over I2C interface at
8141 * a specified device address.
b980ac18 8142 **/
441fc6fd 8143s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8144 u8 dev_addr, u8 *data)
441fc6fd
CW		 8145{
8146 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8147 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8148 s32 status;
8149 u16 swfw_mask = 0;
8150
8151 if (!this_client)
8152 return E1000_ERR_I2C;
8153
8154 swfw_mask = E1000_SWFW_PHY0_SM;
8155
23d87824 8156 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8157 return E1000_ERR_SWFW_SYNC;
8158
8159 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8160 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8161
8162 if (status < 0)
8163 return E1000_ERR_I2C;
8164 else {
8165 *data = status;
23d87824 8166 return 0;
441fc6fd
CW		 8167 }
8168}
8169
b980ac18
JK		 8170/**
8171 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8172 * @hw: pointer to hardware structure
8173 * @byte_offset: byte offset to write
8174 * @dev_addr: device address
8175 * @data: value to write
8176 *
8177 * Performs byte write operation over I2C interface at
8178 * a specified device address.
b980ac18 8179 **/
441fc6fd 8180s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8181 u8 dev_addr, u8 data)
441fc6fd
CW		 8182{
8183 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8184 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8185 s32 status;
8186 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8187
8188 if (!this_client)
8189 return E1000_ERR_I2C;
8190
23d87824 8191 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8192 return E1000_ERR_SWFW_SYNC;
8193 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8194 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8195
8196 if (status)
8197 return E1000_ERR_I2C;
8198 else
23d87824 8199 return 0;
441fc6fd
CW		 8200
8201}
907b7835
LMV		 8202
8203int igb_reinit_queues(struct igb_adapter *adapter)
8204{
8205 struct net_device *netdev = adapter->netdev;
8206 struct pci_dev *pdev = adapter->pdev;
8207 int err = 0;
8208
8209 if (netif_running(netdev))
8210 igb_close(netdev);
8211
02ef6e1d 8212 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8213
8214 if (igb_init_interrupt_scheme(adapter, true)) {
8215 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8216 return -ENOMEM;
8217 }
8218
8219 if (netif_running(netdev))
8220 err = igb_open(netdev);
8221
8222 return err;
8223}
9d5c8243 8224/* igb_main.c */
Linux kernel - Deliverables
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