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igb: release already assigned MSI-X interrupts if setup fails
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
6e861326 4 Copyright(c) 2007-2012 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
9d5c8243
AK		 60#include "igb.h"
61
200e5fd5
CW		 62#define MAJ 4
63#define MIN 0
3db73804 64#define BUILD 17
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
6e861326 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
9d5c8243 72
9d5c8243
AK		 73static const struct e1000_info *igb_info_tbl[] = {
74 [board_82575] = &e1000_82575_info,
75};
76
a3aa1884 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
f96a8a0b
CW		 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
d2ba2ed8
AD		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
108 /* required last entry */
109 {0, }
110};
111
112MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
113
114void igb_reset(struct igb_adapter *);
115static int igb_setup_all_tx_resources(struct igb_adapter *);
116static int igb_setup_all_rx_resources(struct igb_adapter *);
117static void igb_free_all_tx_resources(struct igb_adapter *);
118static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 119static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 120static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 121static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 122static int igb_sw_init(struct igb_adapter *);
123static int igb_open(struct net_device *);
124static int igb_close(struct net_device *);
53c7d064 125static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 126static void igb_configure_tx(struct igb_adapter *);
127static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 128static void igb_clean_all_tx_rings(struct igb_adapter *);
129static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 130static void igb_clean_tx_ring(struct igb_ring *);
131static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 132static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 133static void igb_update_phy_info(unsigned long);
134static void igb_watchdog(unsigned long);
135static void igb_watchdog_task(struct work_struct *);
cd392f5c 136static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 137static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
138 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 139static int igb_change_mtu(struct net_device *, int);
140static int igb_set_mac(struct net_device *, void *);
68d480c4 141static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 142static irqreturn_t igb_intr(int irq, void *);
143static irqreturn_t igb_intr_msi(int irq, void *);
144static irqreturn_t igb_msix_other(int irq, void *);
047e0030 145static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 146#ifdef CONFIG_IGB_DCA
047e0030 147static void igb_update_dca(struct igb_q_vector *);
fe4506b6 148static void igb_setup_dca(struct igb_adapter *);
421e02f0 149#endif /* CONFIG_IGB_DCA */
661086df 150static int igb_poll(struct napi_struct *, int);
13fde97a 151static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 152static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 153static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
154static void igb_tx_timeout(struct net_device *);
155static void igb_reset_task(struct work_struct *);
c8f44aff 156static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
8e586137
JP		 157static int igb_vlan_rx_add_vid(struct net_device *, u16);
158static int igb_vlan_rx_kill_vid(struct net_device *, u16);
9d5c8243 159static void igb_restore_vlan(struct igb_adapter *);
26ad9178 160static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 161static void igb_ping_all_vfs(struct igb_adapter *);
162static void igb_msg_task(struct igb_adapter *);
4ae196df 163static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 164static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 165static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 166static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
167static int igb_ndo_set_vf_vlan(struct net_device *netdev,
168 int vf, u16 vlan, u8 qos);
169static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
170static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
171 struct ifla_vf_info *ivi);
17dc566c 172static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 173
174#ifdef CONFIG_PCI_IOV
0224d663 175static int igb_vf_configure(struct igb_adapter *adapter, int vf);
f557147c 176static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
46a01698 177#endif
9d5c8243 178
9d5c8243 179#ifdef CONFIG_PM
d9dd966d 180#ifdef CONFIG_PM_SLEEP
749ab2cd 181static int igb_suspend(struct device *);
d9dd966d 182#endif
749ab2cd
YZ		 183static int igb_resume(struct device *);
184#ifdef CONFIG_PM_RUNTIME
185static int igb_runtime_suspend(struct device *dev);
186static int igb_runtime_resume(struct device *dev);
187static int igb_runtime_idle(struct device *dev);
188#endif
189static const struct dev_pm_ops igb_pm_ops = {
190 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
191 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
192 igb_runtime_idle)
193};
9d5c8243
AK		 194#endif
195static void igb_shutdown(struct pci_dev *);
421e02f0 196#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 197static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
198static struct notifier_block dca_notifier = {
199 .notifier_call = igb_notify_dca,
200 .next = NULL,
201 .priority = 0
202};
203#endif
9d5c8243
AK		 204#ifdef CONFIG_NET_POLL_CONTROLLER
205/* for netdump / net console */
206static void igb_netpoll(struct net_device *);
207#endif
37680117 208#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 209static unsigned int max_vfs = 0;
210module_param(max_vfs, uint, 0);
211MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
212 "per physical function");
213#endif /* CONFIG_PCI_IOV */
214
9d5c8243
AK		 215static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
216 pci_channel_state_t);
217static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
218static void igb_io_resume(struct pci_dev *);
219
3646f0e5 220static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 221 .error_detected = igb_io_error_detected,
222 .slot_reset = igb_io_slot_reset,
223 .resume = igb_io_resume,
224};
225
b6e0c419 226static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 227
228static struct pci_driver igb_driver = {
229 .name = igb_driver_name,
230 .id_table = igb_pci_tbl,
231 .probe = igb_probe,
9f9a12f8 232 .remove = igb_remove,
9d5c8243 233#ifdef CONFIG_PM
749ab2cd 234 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 235#endif
236 .shutdown = igb_shutdown,
237 .err_handler = &igb_err_handler
238};
239
240MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
241MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
242MODULE_LICENSE("GPL");
243MODULE_VERSION(DRV_VERSION);
244
b3f4d599 245#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
246static int debug = -1;
247module_param(debug, int, 0);
248MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
249
c97ec42a
TI		 250struct igb_reg_info {
251 u32 ofs;
252 char *name;
253};
254
255static const struct igb_reg_info igb_reg_info_tbl[] = {
256
257 /* General Registers */
258 {E1000_CTRL, "CTRL"},
259 {E1000_STATUS, "STATUS"},
260 {E1000_CTRL_EXT, "CTRL_EXT"},
261
262 /* Interrupt Registers */
263 {E1000_ICR, "ICR"},
264
265 /* RX Registers */
266 {E1000_RCTL, "RCTL"},
267 {E1000_RDLEN(0), "RDLEN"},
268 {E1000_RDH(0), "RDH"},
269 {E1000_RDT(0), "RDT"},
270 {E1000_RXDCTL(0), "RXDCTL"},
271 {E1000_RDBAL(0), "RDBAL"},
272 {E1000_RDBAH(0), "RDBAH"},
273
274 /* TX Registers */
275 {E1000_TCTL, "TCTL"},
276 {E1000_TDBAL(0), "TDBAL"},
277 {E1000_TDBAH(0), "TDBAH"},
278 {E1000_TDLEN(0), "TDLEN"},
279 {E1000_TDH(0), "TDH"},
280 {E1000_TDT(0), "TDT"},
281 {E1000_TXDCTL(0), "TXDCTL"},
282 {E1000_TDFH, "TDFH"},
283 {E1000_TDFT, "TDFT"},
284 {E1000_TDFHS, "TDFHS"},
285 {E1000_TDFPC, "TDFPC"},
286
287 /* List Terminator */
288 {}
289};
290
291/*
292 * igb_regdump - register printout routine
293 */
294static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
295{
296 int n = 0;
297 char rname[16];
298 u32 regs[8];
299
300 switch (reginfo->ofs) {
301 case E1000_RDLEN(0):
302 for (n = 0; n < 4; n++)
303 regs[n] = rd32(E1000_RDLEN(n));
304 break;
305 case E1000_RDH(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDH(n));
308 break;
309 case E1000_RDT(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDT(n));
312 break;
313 case E1000_RXDCTL(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RXDCTL(n));
316 break;
317 case E1000_RDBAL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDBAL(n));
320 break;
321 case E1000_RDBAH(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAH(n));
324 break;
325 case E1000_TDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_TDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_TDBAH(n));
332 break;
333 case E1000_TDLEN(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDLEN(n));
336 break;
337 case E1000_TDH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDH(n));
340 break;
341 case E1000_TDT(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDT(n));
344 break;
345 case E1000_TXDCTL(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TXDCTL(n));
348 break;
349 default:
876d2d6f 350 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 351 return;
352 }
353
354 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 355 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
356 regs[2], regs[3]);
c97ec42a
TI		 357}
358
359/*
360 * igb_dump - Print registers, tx-rings and rx-rings
361 */
362static void igb_dump(struct igb_adapter *adapter)
363{
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
c97ec42a
TI		 367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
6ad4edfc 373 u16 i, n;
c97ec42a
TI		 374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 381 pr_info("Device Name state trans_start "
382 "last_rx\n");
383 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
384 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 385 }
386
387 /* Print Registers */
388 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 389 pr_info(" Register Name Value\n");
c97ec42a
TI		 390 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
391 reginfo->name; reginfo++) {
392 igb_regdump(hw, reginfo);
393 }
394
395 /* Print TX Ring Summary */
396 if (!netdev || !netif_running(netdev))
397 goto exit;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 400 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 401 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 402 struct igb_tx_buffer *buffer_info;
c97ec42a 403 tx_ring = adapter->tx_ring[n];
06034649 404 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 405 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
406 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 407 (u64)dma_unmap_addr(buffer_info, dma),
408 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 409 buffer_info->next_to_watch,
410 (u64)buffer_info->time_stamp);
c97ec42a
TI		 411 }
412
413 /* Print TX Rings */
414 if (!netif_msg_tx_done(adapter))
415 goto rx_ring_summary;
416
417 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
418
419 /* Transmit Descriptor Formats
420 *
421 * Advanced Transmit Descriptor
422 * +--------------------------------------------------------------+
423 * 0 | Buffer Address [63:0] |
424 * +--------------------------------------------------------------+
425 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
426 * +--------------------------------------------------------------+
427 * 63 46 45 40 39 38 36 35 32 31 24 15 0
428 */
429
430 for (n = 0; n < adapter->num_tx_queues; n++) {
431 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 432 pr_info("------------------------------------\n");
433 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
434 pr_info("------------------------------------\n");
435 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
436 "[bi->dma ] leng ntw timestamp "
437 "bi->skb\n");
c97ec42a
TI		 438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 440 const char *next_desc;
06034649 441 struct igb_tx_buffer *buffer_info;
60136906 442 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 443 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 444 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
455 pr_info("T [0x%03X] %016llX %016llX %016llX"
456 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
c9f14bf3
AD		 459 (u64)dma_unmap_addr(buffer_info, dma),
460 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 461 buffer_info->next_to_watch,
462 (u64)buffer_info->time_stamp,
876d2d6f 463 buffer_info->skb, next_desc);
c97ec42a 464
b669588a 465 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 466 print_hex_dump(KERN_INFO, "",
467 DUMP_PREFIX_ADDRESS,
b669588a 468 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 469 dma_unmap_len(buffer_info, len),
470 true);
c97ec42a
TI		 471 }
472 }
473
474 /* Print RX Rings Summary */
475rx_ring_summary:
476 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 477 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 478 for (n = 0; n < adapter->num_rx_queues; n++) {
479 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 480 pr_info(" %5d %5X %5X\n",
481 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 482 }
483
484 /* Print RX Rings */
485 if (!netif_msg_rx_status(adapter))
486 goto exit;
487
488 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
489
490 /* Advanced Receive Descriptor (Read) Format
491 * 63 1 0
492 * +-----------------------------------------------------+
493 * 0 | Packet Buffer Address [63:1] |A0/NSE|
494 * +----------------------------------------------+------+
495 * 8 | Header Buffer Address [63:1] | DD |
496 * +-----------------------------------------------------+
497 *
498 *
499 * Advanced Receive Descriptor (Write-Back) Format
500 *
501 * 63 48 47 32 31 30 21 20 17 16 4 3 0
502 * +------------------------------------------------------+
503 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
504 * | Checksum Ident | | | | Type | Type |
505 * +------------------------------------------------------+
506 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
507 * +------------------------------------------------------+
508 * 63 48 47 32 31 20 19 0
509 */
510
511 for (n = 0; n < adapter->num_rx_queues; n++) {
512 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 513 pr_info("------------------------------------\n");
514 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
515 pr_info("------------------------------------\n");
516 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
517 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
519 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 520
521 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 522 const char *next_desc;
06034649
AD		 523 struct igb_rx_buffer *buffer_info;
524 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 525 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 526 u0 = (struct my_u0 *)rx_desc;
527 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 528
529 if (i == rx_ring->next_to_use)
530 next_desc = " NTU";
531 else if (i == rx_ring->next_to_clean)
532 next_desc = " NTC";
533 else
534 next_desc = "";
535
c97ec42a
TI		 536 if (staterr & E1000_RXD_STAT_DD) {
537 /* Descriptor Done */
1a1c225b
AD		 538 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
539 "RWB", i,
c97ec42a
TI		 540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
1a1c225b 542 next_desc);
c97ec42a 543 } else {
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
545 "R ", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
548 (u64)buffer_info->dma,
1a1c225b 549 next_desc);
c97ec42a 550
b669588a 551 if (netif_msg_pktdata(adapter) &&
1a1c225b 552 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 553 print_hex_dump(KERN_INFO, "",
554 DUMP_PREFIX_ADDRESS,
555 16, 1,
b669588a
ET		 556 page_address(buffer_info->page) +
557 buffer_info->page_offset,
de78d1f9 558 IGB_RX_BUFSZ, true);
c97ec42a
TI		 559 }
560 }
c97ec42a
TI		 561 }
562 }
563
564exit:
565 return;
566}
567
9d5c8243 568/**
c041076a 569 * igb_get_hw_dev - return device
9d5c8243
AK		 570 * used by hardware layer to print debugging information
571 **/
c041076a 572struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 573{
574 struct igb_adapter *adapter = hw->back;
c041076a 575 return adapter->netdev;
9d5c8243 576}
38c845c7 577
9d5c8243
AK		 578/**
579 * igb_init_module - Driver Registration Routine
580 *
581 * igb_init_module is the first routine called when the driver is
582 * loaded. All it does is register with the PCI subsystem.
583 **/
584static int __init igb_init_module(void)
585{
586 int ret;
876d2d6f 587 pr_info("%s - version %s\n",
9d5c8243
AK		 588 igb_driver_string, igb_driver_version);
589
876d2d6f 590 pr_info("%s\n", igb_copyright);
9d5c8243 591
421e02f0 592#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 593 dca_register_notify(&dca_notifier);
594#endif
bbd98fe4 595 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 596 return ret;
597}
598
599module_init(igb_init_module);
600
601/**
602 * igb_exit_module - Driver Exit Cleanup Routine
603 *
604 * igb_exit_module is called just before the driver is removed
605 * from memory.
606 **/
607static void __exit igb_exit_module(void)
608{
421e02f0 609#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 610 dca_unregister_notify(&dca_notifier);
611#endif
9d5c8243
AK		 612 pci_unregister_driver(&igb_driver);
613}
614
615module_exit(igb_exit_module);
616
26bc19ec
AD		 617#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
618/**
619 * igb_cache_ring_register - Descriptor ring to register mapping
620 * @adapter: board private structure to initialize
621 *
622 * Once we know the feature-set enabled for the device, we'll cache
623 * the register offset the descriptor ring is assigned to.
624 **/
625static void igb_cache_ring_register(struct igb_adapter *adapter)
626{
ee1b9f06 627 int i = 0, j = 0;
047e0030 628 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 629
630 switch (adapter->hw.mac.type) {
631 case e1000_82576:
632 /* The queues are allocated for virtualization such that VF 0
633 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
634 * In order to avoid collision we start at the first free queue
635 * and continue consuming queues in the same sequence
636 */
ee1b9f06 637 if (adapter->vfs_allocated_count) {
a99955fc 638 for (; i < adapter->rss_queues; i++)
3025a446
AD		 639 adapter->rx_ring[i]->reg_idx = rbase_offset +
640 Q_IDX_82576(i);
ee1b9f06 641 }
26bc19ec 642 case e1000_82575:
55cac248 643 case e1000_82580:
d2ba2ed8 644 case e1000_i350:
f96a8a0b
CW		 645 case e1000_i210:
646 case e1000_i211:
26bc19ec 647 default:
ee1b9f06 648 for (; i < adapter->num_rx_queues; i++)
3025a446 649 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 650 for (; j < adapter->num_tx_queues; j++)
3025a446 651 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 652 break;
653 }
654}
655
4be000c8
AD		 656/**
657 * igb_write_ivar - configure ivar for given MSI-X vector
658 * @hw: pointer to the HW structure
659 * @msix_vector: vector number we are allocating to a given ring
660 * @index: row index of IVAR register to write within IVAR table
661 * @offset: column offset of in IVAR, should be multiple of 8
662 *
663 * This function is intended to handle the writing of the IVAR register
664 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
665 * each containing an cause allocation for an Rx and Tx ring, and a
666 * variable number of rows depending on the number of queues supported.
667 **/
668static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
669 int index, int offset)
670{
671 u32 ivar = array_rd32(E1000_IVAR0, index);
672
673 /* clear any bits that are currently set */
674 ivar &= ~((u32)0xFF << offset);
675
676 /* write vector and valid bit */
677 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
678
679 array_wr32(E1000_IVAR0, index, ivar);
680}
681
9d5c8243 682#define IGB_N0_QUEUE -1
047e0030 683static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 684{
047e0030 685 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 686 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 687 int rx_queue = IGB_N0_QUEUE;
688 int tx_queue = IGB_N0_QUEUE;
4be000c8 689 u32 msixbm = 0;
047e0030 690
0ba82994
AD		 691 if (q_vector->rx.ring)
692 rx_queue = q_vector->rx.ring->reg_idx;
693 if (q_vector->tx.ring)
694 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 695
696 switch (hw->mac.type) {
697 case e1000_82575:
9d5c8243
AK		 698 /* The 82575 assigns vectors using a bitmask, which matches the
699 bitmask for the EICR/EIMS/EIMC registers. To assign one
700 or more queues to a vector, we write the appropriate bits
701 into the MSIXBM register for that vector. */
047e0030 702 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 703 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 704 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 705 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 706 if (!adapter->msix_entries && msix_vector == 0)
707 msixbm |= E1000_EIMS_OTHER;
9d5c8243 708 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 709 q_vector->eims_value = msixbm;
2d064c06
AD		 710 break;
711 case e1000_82576:
4be000c8
AD		 712 /*
713 * 82576 uses a table that essentially consists of 2 columns
714 * with 8 rows. The ordering is column-major so we use the
715 * lower 3 bits as the row index, and the 4th bit as the
716 * column offset.
717 */
718 if (rx_queue > IGB_N0_QUEUE)
719 igb_write_ivar(hw, msix_vector,
720 rx_queue & 0x7,
721 (rx_queue & 0x8) << 1);
722 if (tx_queue > IGB_N0_QUEUE)
723 igb_write_ivar(hw, msix_vector,
724 tx_queue & 0x7,
725 ((tx_queue & 0x8) << 1) + 8);
047e0030 726 q_vector->eims_value = 1 << msix_vector;
2d064c06 727 break;
55cac248 728 case e1000_82580:
d2ba2ed8 729 case e1000_i350:
f96a8a0b
CW		 730 case e1000_i210:
731 case e1000_i211:
4be000c8
AD		 732 /*
733 * On 82580 and newer adapters the scheme is similar to 82576
734 * however instead of ordering column-major we have things
735 * ordered row-major. So we traverse the table by using
736 * bit 0 as the column offset, and the remaining bits as the
737 * row index.
738 */
739 if (rx_queue > IGB_N0_QUEUE)
740 igb_write_ivar(hw, msix_vector,
741 rx_queue >> 1,
742 (rx_queue & 0x1) << 4);
743 if (tx_queue > IGB_N0_QUEUE)
744 igb_write_ivar(hw, msix_vector,
745 tx_queue >> 1,
746 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 747 q_vector->eims_value = 1 << msix_vector;
748 break;
2d064c06
AD		 749 default:
750 BUG();
751 break;
752 }
26b39276
AD		 753
754 /* add q_vector eims value to global eims_enable_mask */
755 adapter->eims_enable_mask |= q_vector->eims_value;
756
757 /* configure q_vector to set itr on first interrupt */
758 q_vector->set_itr = 1;
9d5c8243
AK		 759}
760
761/**
762 * igb_configure_msix - Configure MSI-X hardware
763 *
764 * igb_configure_msix sets up the hardware to properly
765 * generate MSI-X interrupts.
766 **/
767static void igb_configure_msix(struct igb_adapter *adapter)
768{
769 u32 tmp;
770 int i, vector = 0;
771 struct e1000_hw *hw = &adapter->hw;
772
773 adapter->eims_enable_mask = 0;
9d5c8243
AK		 774
775 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 776 switch (hw->mac.type) {
777 case e1000_82575:
9d5c8243
AK		 778 tmp = rd32(E1000_CTRL_EXT);
779 /* enable MSI-X PBA support*/
780 tmp |= E1000_CTRL_EXT_PBA_CLR;
781
782 /* Auto-Mask interrupts upon ICR read. */
783 tmp |= E1000_CTRL_EXT_EIAME;
784 tmp |= E1000_CTRL_EXT_IRCA;
785
786 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 787
788 /* enable msix_other interrupt */
789 array_wr32(E1000_MSIXBM(0), vector++,
790 E1000_EIMS_OTHER);
844290e5 791 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 792
2d064c06
AD		 793 break;
794
795 case e1000_82576:
55cac248 796 case e1000_82580:
d2ba2ed8 797 case e1000_i350:
f96a8a0b
CW		 798 case e1000_i210:
799 case e1000_i211:
047e0030
AD		 800 /* Turn on MSI-X capability first, or our settings
801 * won't stick. And it will take days to debug. */
802 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
803 E1000_GPIE_PBA | E1000_GPIE_EIAME |
804 E1000_GPIE_NSICR);
805
806 /* enable msix_other interrupt */
807 adapter->eims_other = 1 << vector;
2d064c06 808 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 809
047e0030 810 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 811 break;
812 default:
813 /* do nothing, since nothing else supports MSI-X */
814 break;
815 } /* switch (hw->mac.type) */
047e0030
AD		 816
817 adapter->eims_enable_mask |= adapter->eims_other;
818
26b39276
AD		 819 for (i = 0; i < adapter->num_q_vectors; i++)
820 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 821
9d5c8243
AK		 822 wrfl();
823}
824
825/**
826 * igb_request_msix - Initialize MSI-X interrupts
827 *
828 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
829 * kernel.
830 **/
831static int igb_request_msix(struct igb_adapter *adapter)
832{
833 struct net_device *netdev = adapter->netdev;
047e0030 834 struct e1000_hw *hw = &adapter->hw;
52285b76 835 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 836
047e0030 837 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 838 igb_msix_other, 0, netdev->name, adapter);
047e0030 839 if (err)
52285b76 840 goto err_out;
047e0030
AD		 841
842 for (i = 0; i < adapter->num_q_vectors; i++) {
843 struct igb_q_vector *q_vector = adapter->q_vector[i];
844
52285b76
SA		 845 vector++;
846
047e0030
AD		 847 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
848
0ba82994 849 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 850 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 851 q_vector->rx.ring->queue_index);
852 else if (q_vector->tx.ring)
047e0030 853 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 854 q_vector->tx.ring->queue_index);
855 else if (q_vector->rx.ring)
047e0030 856 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 857 q_vector->rx.ring->queue_index);
9d5c8243 858 else
047e0030
AD		 859 sprintf(q_vector->name, "%s-unused", netdev->name);
860
9d5c8243 861 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 862 igb_msix_ring, 0, q_vector->name,
047e0030 863 q_vector);
9d5c8243 864 if (err)
52285b76 865 goto err_free;
9d5c8243
AK		 866 }
867
9d5c8243
AK		 868 igb_configure_msix(adapter);
869 return 0;
52285b76
SA		 870
871err_free:
872 /* free already assigned IRQs */
873 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
874
875 vector--;
876 for (i = 0; i < vector; i++) {
877 free_irq(adapter->msix_entries[free_vector++].vector,
878 adapter->q_vector[i]);
879 }
880err_out:
9d5c8243
AK		 881 return err;
882}
883
884static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
885{
886 if (adapter->msix_entries) {
887 pci_disable_msix(adapter->pdev);
888 kfree(adapter->msix_entries);
889 adapter->msix_entries = NULL;
047e0030 890 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 891 pci_disable_msi(adapter->pdev);
047e0030 892 }
9d5c8243
AK		 893}
894
5536d210
AD		 895/**
896 * igb_free_q_vector - Free memory allocated for specific interrupt vector
897 * @adapter: board private structure to initialize
898 * @v_idx: Index of vector to be freed
899 *
900 * This function frees the memory allocated to the q_vector. In addition if
901 * NAPI is enabled it will delete any references to the NAPI struct prior
902 * to freeing the q_vector.
903 **/
904static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
905{
906 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
907
908 if (q_vector->tx.ring)
909 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
910
911 if (q_vector->rx.ring)
912 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
913
914 adapter->q_vector[v_idx] = NULL;
915 netif_napi_del(&q_vector->napi);
916
917 /*
918 * ixgbe_get_stats64() might access the rings on this vector,
919 * we must wait a grace period before freeing it.
920 */
921 kfree_rcu(q_vector, rcu);
922}
923
047e0030
AD		 924/**
925 * igb_free_q_vectors - Free memory allocated for interrupt vectors
926 * @adapter: board private structure to initialize
927 *
928 * This function frees the memory allocated to the q_vectors. In addition if
929 * NAPI is enabled it will delete any references to the NAPI struct prior
930 * to freeing the q_vector.
931 **/
932static void igb_free_q_vectors(struct igb_adapter *adapter)
933{
5536d210
AD		 934 int v_idx = adapter->num_q_vectors;
935
936 adapter->num_tx_queues = 0;
937 adapter->num_rx_queues = 0;
047e0030 938 adapter->num_q_vectors = 0;
5536d210
AD		 939
940 while (v_idx--)
941 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 942}
943
944/**
945 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
946 *
947 * This function resets the device so that it has 0 rx queues, tx queues, and
948 * MSI-X interrupts allocated.
949 */
950static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
951{
047e0030
AD		 952 igb_free_q_vectors(adapter);
953 igb_reset_interrupt_capability(adapter);
954}
9d5c8243
AK		 955
956/**
957 * igb_set_interrupt_capability - set MSI or MSI-X if supported
958 *
959 * Attempt to configure interrupts using the best available
960 * capabilities of the hardware and kernel.
961 **/
53c7d064 962static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 963{
964 int err;
965 int numvecs, i;
966
53c7d064
SA		 967 if (!msix)
968 goto msi_only;
969
83b7180d 970 /* Number of supported queues. */
a99955fc 971 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 972 if (adapter->vfs_allocated_count)
973 adapter->num_tx_queues = 1;
974 else
975 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 976
047e0030
AD		 977 /* start with one vector for every rx queue */
978 numvecs = adapter->num_rx_queues;
979
3ad2f3fb 980 /* if tx handler is separate add 1 for every tx queue */
a99955fc
AD		 981 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
982 numvecs += adapter->num_tx_queues;
047e0030
AD		 983
984 /* store the number of vectors reserved for queues */
985 adapter->num_q_vectors = numvecs;
986
987 /* add 1 vector for link status interrupts */
988 numvecs++;
9d5c8243
AK		 989 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
990 GFP_KERNEL);
f96a8a0b 991
9d5c8243
AK		 992 if (!adapter->msix_entries)
993 goto msi_only;
994
995 for (i = 0; i < numvecs; i++)
996 adapter->msix_entries[i].entry = i;
997
998 err = pci_enable_msix(adapter->pdev,
999 adapter->msix_entries,
1000 numvecs);
1001 if (err == 0)
0c2cc02e 1002 return;
9d5c8243
AK		 1003
1004 igb_reset_interrupt_capability(adapter);
1005
1006 /* If we can't do MSI-X, try MSI */
1007msi_only:
2a3abf6d
AD		 1008#ifdef CONFIG_PCI_IOV
1009 /* disable SR-IOV for non MSI-X configurations */
1010 if (adapter->vf_data) {
1011 struct e1000_hw *hw = &adapter->hw;
1012 /* disable iov and allow time for transactions to clear */
1013 pci_disable_sriov(adapter->pdev);
1014 msleep(500);
1015
1016 kfree(adapter->vf_data);
1017 adapter->vf_data = NULL;
1018 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1019 wrfl();
2a3abf6d
AD		 1020 msleep(100);
1021 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1022 }
1023#endif
4fc82adf 1024 adapter->vfs_allocated_count = 0;
a99955fc 1025 adapter->rss_queues = 1;
4fc82adf 1026 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1027 adapter->num_rx_queues = 1;
661086df 1028 adapter->num_tx_queues = 1;
047e0030 1029 adapter->num_q_vectors = 1;
9d5c8243 1030 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1031 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1032}
1033
5536d210
AD		 1034static void igb_add_ring(struct igb_ring *ring,
1035 struct igb_ring_container *head)
1036{
1037 head->ring = ring;
1038 head->count++;
1039}
1040
047e0030 1041/**
5536d210 1042 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
047e0030 1043 * @adapter: board private structure to initialize
5536d210
AD		 1044 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1045 * @v_idx: index of vector in adapter struct
1046 * @txr_count: total number of Tx rings to allocate
1047 * @txr_idx: index of first Tx ring to allocate
1048 * @rxr_count: total number of Rx rings to allocate
1049 * @rxr_idx: index of first Rx ring to allocate
047e0030 1050 *
5536d210 1051 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1052 **/
5536d210
AD		 1053static int igb_alloc_q_vector(struct igb_adapter *adapter,
1054 int v_count, int v_idx,
1055 int txr_count, int txr_idx,
1056 int rxr_count, int rxr_idx)
047e0030
AD		 1057{
1058 struct igb_q_vector *q_vector;
5536d210
AD		 1059 struct igb_ring *ring;
1060 int ring_count, size;
047e0030 1061
5536d210
AD		 1062 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1063 if (txr_count > 1 || rxr_count > 1)
1064 return -ENOMEM;
1065
1066 ring_count = txr_count + rxr_count;
1067 size = sizeof(struct igb_q_vector) +
1068 (sizeof(struct igb_ring) * ring_count);
1069
1070 /* allocate q_vector and rings */
1071 q_vector = kzalloc(size, GFP_KERNEL);
1072 if (!q_vector)
1073 return -ENOMEM;
1074
1075 /* initialize NAPI */
1076 netif_napi_add(adapter->netdev, &q_vector->napi,
1077 igb_poll, 64);
1078
1079 /* tie q_vector and adapter together */
1080 adapter->q_vector[v_idx] = q_vector;
1081 q_vector->adapter = adapter;
1082
1083 /* initialize work limits */
1084 q_vector->tx.work_limit = adapter->tx_work_limit;
1085
1086 /* initialize ITR configuration */
1087 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1088 q_vector->itr_val = IGB_START_ITR;
1089
1090 /* initialize pointer to rings */
1091 ring = q_vector->ring;
1092
1093 if (txr_count) {
1094 /* assign generic ring traits */
1095 ring->dev = &adapter->pdev->dev;
1096 ring->netdev = adapter->netdev;
1097
1098 /* configure backlink on ring */
1099 ring->q_vector = q_vector;
1100
1101 /* update q_vector Tx values */
1102 igb_add_ring(ring, &q_vector->tx);
1103
1104 /* For 82575, context index must be unique per ring. */
1105 if (adapter->hw.mac.type == e1000_82575)
1106 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1107
1108 /* apply Tx specific ring traits */
1109 ring->count = adapter->tx_ring_count;
1110 ring->queue_index = txr_idx;
1111
1112 /* assign ring to adapter */
1113 adapter->tx_ring[txr_idx] = ring;
1114
1115 /* push pointer to next ring */
1116 ring++;
047e0030 1117 }
81c2fc22 1118
5536d210
AD		 1119 if (rxr_count) {
1120 /* assign generic ring traits */
1121 ring->dev = &adapter->pdev->dev;
1122 ring->netdev = adapter->netdev;
047e0030 1123
5536d210
AD		 1124 /* configure backlink on ring */
1125 ring->q_vector = q_vector;
047e0030 1126
5536d210
AD		 1127 /* update q_vector Rx values */
1128 igb_add_ring(ring, &q_vector->rx);
047e0030 1129
5536d210
AD		 1130 /* set flag indicating ring supports SCTP checksum offload */
1131 if (adapter->hw.mac.type >= e1000_82576)
1132 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1133
5536d210
AD		 1134 /*
1135 * On i350, i210, and i211, loopback VLAN packets
1136 * have the tag byte-swapped.
1137 * */
1138 if (adapter->hw.mac.type >= e1000_i350)
1139 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1140
5536d210
AD		 1141 /* apply Rx specific ring traits */
1142 ring->count = adapter->rx_ring_count;
1143 ring->queue_index = rxr_idx;
1144
1145 /* assign ring to adapter */
1146 adapter->rx_ring[rxr_idx] = ring;
1147 }
1148
1149 return 0;
047e0030
AD		 1150}
1151
5536d210 1152
047e0030 1153/**
5536d210
AD		 1154 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1155 * @adapter: board private structure to initialize
047e0030 1156 *
5536d210
AD		 1157 * We allocate one q_vector per queue interrupt. If allocation fails we
1158 * return -ENOMEM.
047e0030 1159 **/
5536d210 1160static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1161{
5536d210
AD		 1162 int q_vectors = adapter->num_q_vectors;
1163 int rxr_remaining = adapter->num_rx_queues;
1164 int txr_remaining = adapter->num_tx_queues;
1165 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1166 int err;
047e0030 1167
5536d210
AD		 1168 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1169 for (; rxr_remaining; v_idx++) {
1170 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1171 0, 0, 1, rxr_idx);
047e0030 1172
5536d210
AD		 1173 if (err)
1174 goto err_out;
1175
1176 /* update counts and index */
1177 rxr_remaining--;
1178 rxr_idx++;
047e0030 1179 }
047e0030 1180 }
5536d210
AD		 1181
1182 for (; v_idx < q_vectors; v_idx++) {
1183 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1184 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1185 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1186 tqpv, txr_idx, rqpv, rxr_idx);
1187
1188 if (err)
1189 goto err_out;
1190
1191 /* update counts and index */
1192 rxr_remaining -= rqpv;
1193 txr_remaining -= tqpv;
1194 rxr_idx++;
1195 txr_idx++;
1196 }
1197
047e0030 1198 return 0;
5536d210
AD		 1199
1200err_out:
1201 adapter->num_tx_queues = 0;
1202 adapter->num_rx_queues = 0;
1203 adapter->num_q_vectors = 0;
1204
1205 while (v_idx--)
1206 igb_free_q_vector(adapter, v_idx);
1207
1208 return -ENOMEM;
047e0030
AD		 1209}
1210
1211/**
1212 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1213 *
1214 * This function initializes the interrupts and allocates all of the queues.
1215 **/
53c7d064 1216static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1217{
1218 struct pci_dev *pdev = adapter->pdev;
1219 int err;
1220
53c7d064 1221 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1222
1223 err = igb_alloc_q_vectors(adapter);
1224 if (err) {
1225 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1226 goto err_alloc_q_vectors;
1227 }
1228
5536d210 1229 igb_cache_ring_register(adapter);
047e0030
AD		 1230
1231 return 0;
5536d210 1232
047e0030
AD		 1233err_alloc_q_vectors:
1234 igb_reset_interrupt_capability(adapter);
1235 return err;
1236}
1237
9d5c8243
AK		 1238/**
1239 * igb_request_irq - initialize interrupts
1240 *
1241 * Attempts to configure interrupts using the best available
1242 * capabilities of the hardware and kernel.
1243 **/
1244static int igb_request_irq(struct igb_adapter *adapter)
1245{
1246 struct net_device *netdev = adapter->netdev;
047e0030 1247 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1248 int err = 0;
1249
1250 if (adapter->msix_entries) {
1251 err = igb_request_msix(adapter);
844290e5 1252 if (!err)
9d5c8243 1253 goto request_done;
9d5c8243 1254 /* fall back to MSI */
5536d210
AD		 1255 igb_free_all_tx_resources(adapter);
1256 igb_free_all_rx_resources(adapter);
53c7d064 1257
047e0030 1258 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1259 err = igb_init_interrupt_scheme(adapter, false);
1260 if (err)
047e0030 1261 goto request_done;
53c7d064 1262
047e0030
AD		 1263 igb_setup_all_tx_resources(adapter);
1264 igb_setup_all_rx_resources(adapter);
53c7d064 1265 igb_configure(adapter);
9d5c8243 1266 }
844290e5 1267
c74d588e
AD		 1268 igb_assign_vector(adapter->q_vector[0], 0);
1269
7dfc16fa 1270 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1271 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1272 netdev->name, adapter);
9d5c8243
AK		 1273 if (!err)
1274 goto request_done;
047e0030 1275
9d5c8243
AK		 1276 /* fall back to legacy interrupts */
1277 igb_reset_interrupt_capability(adapter);
7dfc16fa 1278 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1279 }
1280
c74d588e 1281 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1282 netdev->name, adapter);
9d5c8243 1283
6cb5e577 1284 if (err)
c74d588e 1285 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1286 err);
9d5c8243
AK		 1287
1288request_done:
1289 return err;
1290}
1291
1292static void igb_free_irq(struct igb_adapter *adapter)
1293{
9d5c8243
AK		 1294 if (adapter->msix_entries) {
1295 int vector = 0, i;
1296
047e0030 1297 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1298
0d1ae7f4 1299 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1300 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1301 adapter->q_vector[i]);
047e0030
AD		 1302 } else {
1303 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1304 }
9d5c8243
AK		 1305}
1306
1307/**
1308 * igb_irq_disable - Mask off interrupt generation on the NIC
1309 * @adapter: board private structure
1310 **/
1311static void igb_irq_disable(struct igb_adapter *adapter)
1312{
1313 struct e1000_hw *hw = &adapter->hw;
1314
25568a53
AD		 1315 /*
1316 * we need to be careful when disabling interrupts. The VFs are also
1317 * mapped into these registers and so clearing the bits can cause
1318 * issues on the VF drivers so we only need to clear what we set
1319 */
9d5c8243 1320 if (adapter->msix_entries) {
2dfd1212
AD		 1321 u32 regval = rd32(E1000_EIAM);
1322 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1323 wr32(E1000_EIMC, adapter->eims_enable_mask);
1324 regval = rd32(E1000_EIAC);
1325 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1326 }
844290e5
PW		 1327
1328 wr32(E1000_IAM, 0);
9d5c8243
AK		 1329 wr32(E1000_IMC, ~0);
1330 wrfl();
81a61859
ET		 1331 if (adapter->msix_entries) {
1332 int i;
1333 for (i = 0; i < adapter->num_q_vectors; i++)
1334 synchronize_irq(adapter->msix_entries[i].vector);
1335 } else {
1336 synchronize_irq(adapter->pdev->irq);
1337 }
9d5c8243
AK		 1338}
1339
1340/**
1341 * igb_irq_enable - Enable default interrupt generation settings
1342 * @adapter: board private structure
1343 **/
1344static void igb_irq_enable(struct igb_adapter *adapter)
1345{
1346 struct e1000_hw *hw = &adapter->hw;
1347
1348 if (adapter->msix_entries) {
06218a8d 1349 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1350 u32 regval = rd32(E1000_EIAC);
1351 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1352 regval = rd32(E1000_EIAM);
1353 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1354 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1355 if (adapter->vfs_allocated_count) {
4ae196df 1356 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1357 ims |= E1000_IMS_VMMB;
1358 }
1359 wr32(E1000_IMS, ims);
844290e5 1360 } else {
55cac248
AD		 1361 wr32(E1000_IMS, IMS_ENABLE_MASK |
1362 E1000_IMS_DRSTA);
1363 wr32(E1000_IAM, IMS_ENABLE_MASK |
1364 E1000_IMS_DRSTA);
844290e5 1365 }
9d5c8243
AK		 1366}
1367
1368static void igb_update_mng_vlan(struct igb_adapter *adapter)
1369{
51466239 1370 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1371 u16 vid = adapter->hw.mng_cookie.vlan_id;
1372 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1373
1374 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1375 /* add VID to filter table */
1376 igb_vfta_set(hw, vid, true);
1377 adapter->mng_vlan_id = vid;
1378 } else {
1379 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1380 }
1381
1382 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1383 (vid != old_vid) &&
b2cb09b1 1384 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1385 /* remove VID from filter table */
1386 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1387 }
1388}
1389
1390/**
1391 * igb_release_hw_control - release control of the h/w to f/w
1392 * @adapter: address of board private structure
1393 *
1394 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1395 * For ASF and Pass Through versions of f/w this means that the
1396 * driver is no longer loaded.
1397 *
1398 **/
1399static void igb_release_hw_control(struct igb_adapter *adapter)
1400{
1401 struct e1000_hw *hw = &adapter->hw;
1402 u32 ctrl_ext;
1403
1404 /* Let firmware take over control of h/w */
1405 ctrl_ext = rd32(E1000_CTRL_EXT);
1406 wr32(E1000_CTRL_EXT,
1407 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1408}
1409
9d5c8243
AK		 1410/**
1411 * igb_get_hw_control - get control of the h/w from f/w
1412 * @adapter: address of board private structure
1413 *
1414 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1415 * For ASF and Pass Through versions of f/w this means that
1416 * the driver is loaded.
1417 *
1418 **/
1419static void igb_get_hw_control(struct igb_adapter *adapter)
1420{
1421 struct e1000_hw *hw = &adapter->hw;
1422 u32 ctrl_ext;
1423
1424 /* Let firmware know the driver has taken over */
1425 ctrl_ext = rd32(E1000_CTRL_EXT);
1426 wr32(E1000_CTRL_EXT,
1427 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1428}
1429
9d5c8243
AK		 1430/**
1431 * igb_configure - configure the hardware for RX and TX
1432 * @adapter: private board structure
1433 **/
1434static void igb_configure(struct igb_adapter *adapter)
1435{
1436 struct net_device *netdev = adapter->netdev;
1437 int i;
1438
1439 igb_get_hw_control(adapter);
ff41f8dc 1440 igb_set_rx_mode(netdev);
9d5c8243
AK		 1441
1442 igb_restore_vlan(adapter);
9d5c8243 1443
85b430b4 1444 igb_setup_tctl(adapter);
06cf2666 1445 igb_setup_mrqc(adapter);
9d5c8243 1446 igb_setup_rctl(adapter);
85b430b4
AD		 1447
1448 igb_configure_tx(adapter);
9d5c8243 1449 igb_configure_rx(adapter);
662d7205
AD		 1450
1451 igb_rx_fifo_flush_82575(&adapter->hw);
1452
c493ea45 1453 /* call igb_desc_unused which always leaves
9d5c8243
AK		 1454 * at least 1 descriptor unused to make sure
1455 * next_to_use != next_to_clean */
1456 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1457 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1458 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1459 }
9d5c8243
AK		 1460}
1461
88a268c1
NN		 1462/**
1463 * igb_power_up_link - Power up the phy/serdes link
1464 * @adapter: address of board private structure
1465 **/
1466void igb_power_up_link(struct igb_adapter *adapter)
1467{
76886596
AA		 1468 igb_reset_phy(&adapter->hw);
1469
88a268c1
NN		 1470 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1471 igb_power_up_phy_copper(&adapter->hw);
1472 else
1473 igb_power_up_serdes_link_82575(&adapter->hw);
1474}
1475
1476/**
1477 * igb_power_down_link - Power down the phy/serdes link
1478 * @adapter: address of board private structure
1479 */
1480static void igb_power_down_link(struct igb_adapter *adapter)
1481{
1482 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1483 igb_power_down_phy_copper_82575(&adapter->hw);
1484 else
1485 igb_shutdown_serdes_link_82575(&adapter->hw);
1486}
9d5c8243
AK		 1487
1488/**
1489 * igb_up - Open the interface and prepare it to handle traffic
1490 * @adapter: board private structure
1491 **/
9d5c8243
AK		 1492int igb_up(struct igb_adapter *adapter)
1493{
1494 struct e1000_hw *hw = &adapter->hw;
1495 int i;
1496
1497 /* hardware has been reset, we need to reload some things */
1498 igb_configure(adapter);
1499
1500 clear_bit(__IGB_DOWN, &adapter->state);
1501
0d1ae7f4
AD		 1502 for (i = 0; i < adapter->num_q_vectors; i++)
1503 napi_enable(&(adapter->q_vector[i]->napi));
1504
844290e5 1505 if (adapter->msix_entries)
9d5c8243 1506 igb_configure_msix(adapter);
feeb2721
AD		 1507 else
1508 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1509
1510 /* Clear any pending interrupts. */
1511 rd32(E1000_ICR);
1512 igb_irq_enable(adapter);
1513
d4960307
AD		 1514 /* notify VFs that reset has been completed */
1515 if (adapter->vfs_allocated_count) {
1516 u32 reg_data = rd32(E1000_CTRL_EXT);
1517 reg_data |= E1000_CTRL_EXT_PFRSTD;
1518 wr32(E1000_CTRL_EXT, reg_data);
1519 }
1520
4cb9be7a
JB		 1521 netif_tx_start_all_queues(adapter->netdev);
1522
25568a53
AD		 1523 /* start the watchdog. */
1524 hw->mac.get_link_status = 1;
1525 schedule_work(&adapter->watchdog_task);
1526
9d5c8243
AK		 1527 return 0;
1528}
1529
1530void igb_down(struct igb_adapter *adapter)
1531{
9d5c8243 1532 struct net_device *netdev = adapter->netdev;
330a6d6a 1533 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1534 u32 tctl, rctl;
1535 int i;
1536
1537 /* signal that we're down so the interrupt handler does not
1538 * reschedule our watchdog timer */
1539 set_bit(__IGB_DOWN, &adapter->state);
1540
1541 /* disable receives in the hardware */
1542 rctl = rd32(E1000_RCTL);
1543 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1544 /* flush and sleep below */
1545
fd2ea0a7 1546 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1547
1548 /* disable transmits in the hardware */
1549 tctl = rd32(E1000_TCTL);
1550 tctl &= ~E1000_TCTL_EN;
1551 wr32(E1000_TCTL, tctl);
1552 /* flush both disables and wait for them to finish */
1553 wrfl();
1554 msleep(10);
1555
0d1ae7f4
AD		 1556 for (i = 0; i < adapter->num_q_vectors; i++)
1557 napi_disable(&(adapter->q_vector[i]->napi));
9d5c8243 1558
9d5c8243
AK		 1559 igb_irq_disable(adapter);
1560
1561 del_timer_sync(&adapter->watchdog_timer);
1562 del_timer_sync(&adapter->phy_info_timer);
1563
9d5c8243 1564 netif_carrier_off(netdev);
04fe6358
AD		 1565
1566 /* record the stats before reset*/
12dcd86b
ED		 1567 spin_lock(&adapter->stats64_lock);
1568 igb_update_stats(adapter, &adapter->stats64);
1569 spin_unlock(&adapter->stats64_lock);
04fe6358 1570
9d5c8243
AK		 1571 adapter->link_speed = 0;
1572 adapter->link_duplex = 0;
1573
3023682e
JK		 1574 if (!pci_channel_offline(adapter->pdev))
1575 igb_reset(adapter);
9d5c8243
AK		 1576 igb_clean_all_tx_rings(adapter);
1577 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1578#ifdef CONFIG_IGB_DCA
1579
1580 /* since we reset the hardware DCA settings were cleared */
1581 igb_setup_dca(adapter);
1582#endif
9d5c8243
AK		 1583}
1584
1585void igb_reinit_locked(struct igb_adapter *adapter)
1586{
1587 WARN_ON(in_interrupt());
1588 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1589 msleep(1);
1590 igb_down(adapter);
1591 igb_up(adapter);
1592 clear_bit(__IGB_RESETTING, &adapter->state);
1593}
1594
1595void igb_reset(struct igb_adapter *adapter)
1596{
090b1795 1597 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1598 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1599 struct e1000_mac_info *mac = &hw->mac;
1600 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1601 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1602
1603 /* Repartition Pba for greater than 9k mtu
1604 * To take effect CTRL.RST is required.
1605 */
fa4dfae0 1606 switch (mac->type) {
d2ba2ed8 1607 case e1000_i350:
55cac248
AD		 1608 case e1000_82580:
1609 pba = rd32(E1000_RXPBS);
1610 pba = igb_rxpbs_adjust_82580(pba);
1611 break;
fa4dfae0 1612 case e1000_82576:
d249be54
AD		 1613 pba = rd32(E1000_RXPBS);
1614 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1615 break;
1616 case e1000_82575:
f96a8a0b
CW		 1617 case e1000_i210:
1618 case e1000_i211:
fa4dfae0
AD		 1619 default:
1620 pba = E1000_PBA_34K;
1621 break;
2d064c06 1622 }
9d5c8243 1623
2d064c06
AD		 1624 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1625 (mac->type < e1000_82576)) {
9d5c8243
AK		 1626 /* adjust PBA for jumbo frames */
1627 wr32(E1000_PBA, pba);
1628
1629 /* To maintain wire speed transmits, the Tx FIFO should be
1630 * large enough to accommodate two full transmit packets,
1631 * rounded up to the next 1KB and expressed in KB. Likewise,
1632 * the Rx FIFO should be large enough to accommodate at least
1633 * one full receive packet and is similarly rounded up and
1634 * expressed in KB. */
1635 pba = rd32(E1000_PBA);
1636 /* upper 16 bits has Tx packet buffer allocation size in KB */
1637 tx_space = pba >> 16;
1638 /* lower 16 bits has Rx packet buffer allocation size in KB */
1639 pba &= 0xffff;
1640 /* the tx fifo also stores 16 bytes of information about the tx
1641 * but don't include ethernet FCS because hardware appends it */
1642 min_tx_space = (adapter->max_frame_size +
85e8d004 1643 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1644 ETH_FCS_LEN) * 2;
1645 min_tx_space = ALIGN(min_tx_space, 1024);
1646 min_tx_space >>= 10;
1647 /* software strips receive CRC, so leave room for it */
1648 min_rx_space = adapter->max_frame_size;
1649 min_rx_space = ALIGN(min_rx_space, 1024);
1650 min_rx_space >>= 10;
1651
1652 /* If current Tx allocation is less than the min Tx FIFO size,
1653 * and the min Tx FIFO size is less than the current Rx FIFO
1654 * allocation, take space away from current Rx allocation */
1655 if (tx_space < min_tx_space &&
1656 ((min_tx_space - tx_space) < pba)) {
1657 pba = pba - (min_tx_space - tx_space);
1658
1659 /* if short on rx space, rx wins and must trump tx
1660 * adjustment */
1661 if (pba < min_rx_space)
1662 pba = min_rx_space;
1663 }
2d064c06 1664 wr32(E1000_PBA, pba);
9d5c8243 1665 }
9d5c8243
AK		 1666
1667 /* flow control settings */
1668 /* The high water mark must be low enough to fit one full frame
1669 * (or the size used for early receive) above it in the Rx FIFO.
1670 * Set it to the lower of:
1671 * - 90% of the Rx FIFO size, or
1672 * - the full Rx FIFO size minus one full frame */
1673 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1674 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1675
d48507fe 1676 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1677 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1678 fc->pause_time = 0xFFFF;
1679 fc->send_xon = 1;
0cce119a 1680 fc->current_mode = fc->requested_mode;
9d5c8243 1681
4ae196df
AD		 1682 /* disable receive for all VFs and wait one second */
1683 if (adapter->vfs_allocated_count) {
1684 int i;
1685 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1686 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1687
1688 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1689 igb_ping_all_vfs(adapter);
4ae196df
AD		 1690
1691 /* disable transmits and receives */
1692 wr32(E1000_VFRE, 0);
1693 wr32(E1000_VFTE, 0);
1694 }
1695
9d5c8243 1696 /* Allow time for pending master requests to run */
330a6d6a 1697 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1698 wr32(E1000_WUC, 0);
1699
330a6d6a 1700 if (hw->mac.ops.init_hw(hw))
090b1795 1701 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1702
a27416bb
MV		 1703 /*
1704 * Flow control settings reset on hardware reset, so guarantee flow
1705 * control is off when forcing speed.
1706 */
1707 if (!hw->mac.autoneg)
1708 igb_force_mac_fc(hw);
1709
b6e0c419 1710 igb_init_dmac(adapter, pba);
88a268c1
NN		 1711 if (!netif_running(adapter->netdev))
1712 igb_power_down_link(adapter);
1713
9d5c8243
AK		 1714 igb_update_mng_vlan(adapter);
1715
1716 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1717 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1718
1f6e8178
MV		 1719 /* Re-enable PTP, where applicable. */
1720 igb_ptp_reset(adapter);
1f6e8178 1721
330a6d6a 1722 igb_get_phy_info(hw);
9d5c8243
AK		 1723}
1724
c8f44aff
MM		 1725static netdev_features_t igb_fix_features(struct net_device *netdev,
1726 netdev_features_t features)
b2cb09b1
JP		 1727{
1728 /*
1729 * Since there is no support for separate rx/tx vlan accel
1730 * enable/disable make sure tx flag is always in same state as rx.
1731 */
1732 if (features & NETIF_F_HW_VLAN_RX)
1733 features |= NETIF_F_HW_VLAN_TX;
1734 else
1735 features &= ~NETIF_F_HW_VLAN_TX;
1736
1737 return features;
1738}
1739
c8f44aff
MM		 1740static int igb_set_features(struct net_device *netdev,
1741 netdev_features_t features)
ac52caa3 1742{
c8f44aff 1743 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1744 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1745
b2cb09b1
JP		 1746 if (changed & NETIF_F_HW_VLAN_RX)
1747 igb_vlan_mode(netdev, features);
1748
89eaefb6
BG		 1749 if (!(changed & NETIF_F_RXALL))
1750 return 0;
1751
1752 netdev->features = features;
1753
1754 if (netif_running(netdev))
1755 igb_reinit_locked(adapter);
1756 else
1757 igb_reset(adapter);
1758
ac52caa3
MM		 1759 return 0;
1760}
1761
2e5c6922 1762static const struct net_device_ops igb_netdev_ops = {
559e9c49 1763 .ndo_open = igb_open,
2e5c6922 1764 .ndo_stop = igb_close,
cd392f5c 1765 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1766 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1767 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1768 .ndo_set_mac_address = igb_set_mac,
1769 .ndo_change_mtu = igb_change_mtu,
1770 .ndo_do_ioctl = igb_ioctl,
1771 .ndo_tx_timeout = igb_tx_timeout,
1772 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1773 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1774 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1775 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1776 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1777 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
1778 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1779#ifdef CONFIG_NET_POLL_CONTROLLER
1780 .ndo_poll_controller = igb_netpoll,
1781#endif
b2cb09b1
JP		 1782 .ndo_fix_features = igb_fix_features,
1783 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1784};
1785
d67974f0
CW		 1786/**
1787 * igb_set_fw_version - Configure version string for ethtool
1788 * @adapter: adapter struct
1789 *
1790 **/
1791void igb_set_fw_version(struct igb_adapter *adapter)
1792{
1793 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1794 struct e1000_fw_version fw;
1795
1796 igb_get_fw_version(hw, &fw);
1797
1798 switch (hw->mac.type) {
1799 case e1000_i211:
d67974f0 1800 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
0b1a6f2e
CW		 1801 "%2d.%2d-%d",
1802 fw.invm_major, fw.invm_minor, fw.invm_img_type);
1803 break;
1804
1805 default:
1806 /* if option is rom valid, display its version too */
1807 if (fw.or_valid) {
1808 snprintf(adapter->fw_version,
1809 sizeof(adapter->fw_version),
1810 "%d.%d, 0x%08x, %d.%d.%d",
1811 fw.eep_major, fw.eep_minor, fw.etrack_id,
1812 fw.or_major, fw.or_build, fw.or_patch);
1813 /* no option rom */
1814 } else {
1815 snprintf(adapter->fw_version,
1816 sizeof(adapter->fw_version),
1817 "%d.%d, 0x%08x",
1818 fw.eep_major, fw.eep_minor, fw.etrack_id);
1819 }
1820 break;
d67974f0 1821 }
d67974f0
CW		 1822 return;
1823}
1824
9d5c8243
AK		 1825/**
1826 * igb_probe - Device Initialization Routine
1827 * @pdev: PCI device information struct
1828 * @ent: entry in igb_pci_tbl
1829 *
1830 * Returns 0 on success, negative on failure
1831 *
1832 * igb_probe initializes an adapter identified by a pci_dev structure.
1833 * The OS initialization, configuring of the adapter private structure,
1834 * and a hardware reset occur.
1835 **/
9f9a12f8 1836static int igb_probe(struct pci_dev *pdev,
9d5c8243
AK		 1837 const struct pci_device_id *ent)
1838{
1839 struct net_device *netdev;
1840 struct igb_adapter *adapter;
1841 struct e1000_hw *hw;
4337e993 1842 u16 eeprom_data = 0;
9835fd73 1843 s32 ret_val;
4337e993 1844 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 1845 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1846 unsigned long mmio_start, mmio_len;
2d6a5e95 1847 int err, pci_using_dac;
9835fd73 1848 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 1849
bded64a7
AG		 1850 /* Catch broken hardware that put the wrong VF device ID in
1851 * the PCIe SR-IOV capability.
1852 */
1853 if (pdev->is_virtfn) {
1854 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 1855 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 1856 return -EINVAL;
1857 }
1858
aed5dec3 1859 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 1860 if (err)
1861 return err;
1862
1863 pci_using_dac = 0;
59d71989 1864 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 1865 if (!err) {
59d71989 1866 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 1867 if (!err)
1868 pci_using_dac = 1;
1869 } else {
59d71989 1870 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 1871 if (err) {
59d71989 1872 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243
AK		 1873 if (err) {
1874 dev_err(&pdev->dev, "No usable DMA "
1875 "configuration, aborting\n");
1876 goto err_dma;
1877 }
1878 }
1879 }
1880
aed5dec3
AD		 1881 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1882 IORESOURCE_MEM),
1883 igb_driver_name);
9d5c8243
AK		 1884 if (err)
1885 goto err_pci_reg;
1886
19d5afd4 1887 pci_enable_pcie_error_reporting(pdev);
40a914fa 1888
9d5c8243 1889 pci_set_master(pdev);
c682fc23 1890 pci_save_state(pdev);
9d5c8243
AK		 1891
1892 err = -ENOMEM;
1bfaf07b 1893 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 1894 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 1895 if (!netdev)
1896 goto err_alloc_etherdev;
1897
1898 SET_NETDEV_DEV(netdev, &pdev->dev);
1899
1900 pci_set_drvdata(pdev, netdev);
1901 adapter = netdev_priv(netdev);
1902 adapter->netdev = netdev;
1903 adapter->pdev = pdev;
1904 hw = &adapter->hw;
1905 hw->back = adapter;
b3f4d599 1906 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 1907
1908 mmio_start = pci_resource_start(pdev, 0);
1909 mmio_len = pci_resource_len(pdev, 0);
1910
1911 err = -EIO;
28b0759c
AD		 1912 hw->hw_addr = ioremap(mmio_start, mmio_len);
1913 if (!hw->hw_addr)
9d5c8243
AK		 1914 goto err_ioremap;
1915
2e5c6922 1916 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 1917 igb_set_ethtool_ops(netdev);
9d5c8243 1918 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 1919
1920 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1921
1922 netdev->mem_start = mmio_start;
1923 netdev->mem_end = mmio_start + mmio_len;
1924
9d5c8243
AK		 1925 /* PCI config space info */
1926 hw->vendor_id = pdev->vendor;
1927 hw->device_id = pdev->device;
1928 hw->revision_id = pdev->revision;
1929 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1930 hw->subsystem_device_id = pdev->subsystem_device;
1931
9d5c8243
AK		 1932 /* Copy the default MAC, PHY and NVM function pointers */
1933 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1934 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1935 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1936 /* Initialize skew-specific constants */
1937 err = ei->get_invariants(hw);
1938 if (err)
450c87c8 1939 goto err_sw_init;
9d5c8243 1940
450c87c8 1941 /* setup the private structure */
9d5c8243
AK		 1942 err = igb_sw_init(adapter);
1943 if (err)
1944 goto err_sw_init;
1945
1946 igb_get_bus_info_pcie(hw);
1947
1948 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 1949
1950 /* Copper options */
1951 if (hw->phy.media_type == e1000_media_type_copper) {
1952 hw->phy.mdix = AUTO_ALL_MODES;
1953 hw->phy.disable_polarity_correction = false;
1954 hw->phy.ms_type = e1000_ms_hw_default;
1955 }
1956
1957 if (igb_check_reset_block(hw))
1958 dev_info(&pdev->dev,
1959 "PHY reset is blocked due to SOL/IDER session.\n");
1960
077887c3
AD		 1961 /*
1962 * features is initialized to 0 in allocation, it might have bits
1963 * set by igb_sw_init so we should use an or instead of an
1964 * assignment.
1965 */
1966 netdev->features |= NETIF_F_SG |
1967 NETIF_F_IP_CSUM |
1968 NETIF_F_IPV6_CSUM |
1969 NETIF_F_TSO |
1970 NETIF_F_TSO6 |
1971 NETIF_F_RXHASH |
1972 NETIF_F_RXCSUM |
1973 NETIF_F_HW_VLAN_RX |
1974 NETIF_F_HW_VLAN_TX;
1975
1976 /* copy netdev features into list of user selectable features */
1977 netdev->hw_features |= netdev->features;
89eaefb6 1978 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 1979
1980 /* set this bit last since it cannot be part of hw_features */
1981 netdev->features |= NETIF_F_HW_VLAN_FILTER;
1982
1983 netdev->vlan_features |= NETIF_F_TSO |
1984 NETIF_F_TSO6 |
1985 NETIF_F_IP_CSUM |
1986 NETIF_F_IPV6_CSUM |
1987 NETIF_F_SG;
48f29ffc 1988
6b8f0922
BG		 1989 netdev->priv_flags |= IFF_SUPP_NOFCS;
1990
7b872a55 1991 if (pci_using_dac) {
9d5c8243 1992 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 1993 netdev->vlan_features |= NETIF_F_HIGHDMA;
1994 }
9d5c8243 1995
ac52caa3
MM		 1996 if (hw->mac.type >= e1000_82576) {
1997 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 1998 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 1999 }
b9473560 2000
01789349
JP		 2001 netdev->priv_flags |= IFF_UNICAST_FLT;
2002
330a6d6a 2003 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2004
2005 /* before reading the NVM, reset the controller to put the device in a
2006 * known good starting state */
2007 hw->mac.ops.reset_hw(hw);
2008
f96a8a0b
CW		 2009 /*
2010 * make sure the NVM is good , i211 parts have special NVM that
2011 * doesn't contain a checksum
2012 */
2013 if (hw->mac.type != e1000_i211) {
2014 if (hw->nvm.ops.validate(hw) < 0) {
2015 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2016 err = -EIO;
2017 goto err_eeprom;
2018 }
9d5c8243
AK		 2019 }
2020
2021 /* copy the MAC address out of the NVM */
2022 if (hw->mac.ops.read_mac_addr(hw))
2023 dev_err(&pdev->dev, "NVM Read Error\n");
2024
2025 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2026 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
2027
2028 if (!is_valid_ether_addr(netdev->perm_addr)) {
2029 dev_err(&pdev->dev, "Invalid MAC Address\n");
2030 err = -EIO;
2031 goto err_eeprom;
2032 }
2033
d67974f0
CW		 2034 /* get firmware version for ethtool -i */
2035 igb_set_fw_version(adapter);
2036
c061b18d 2037 setup_timer(&adapter->watchdog_timer, igb_watchdog,
0e340485 2038 (unsigned long) adapter);
c061b18d 2039 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
0e340485 2040 (unsigned long) adapter);
9d5c8243
AK		 2041
2042 INIT_WORK(&adapter->reset_task, igb_reset_task);
2043 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2044
450c87c8 2045 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2046 adapter->fc_autoneg = true;
2047 hw->mac.autoneg = true;
2048 hw->phy.autoneg_advertised = 0x2f;
2049
0cce119a
AD		 2050 hw->fc.requested_mode = e1000_fc_default;
2051 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2052
9d5c8243
AK		 2053 igb_validate_mdi_setting(hw);
2054
63d4a8f9 2055 /* By default, support wake on port A */
a2cf8b6c 2056 if (hw->bus.func == 0)
63d4a8f9
MV		 2057 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2058
2059 /* Check the NVM for wake support on non-port A ports */
2060 if (hw->mac.type >= e1000_82580)
55cac248
AD		 2061 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2062 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2063 &eeprom_data);
a2cf8b6c
AD		 2064 else if (hw->bus.func == 1)
2065 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2066
63d4a8f9
MV		 2067 if (eeprom_data & IGB_EEPROM_APME)
2068 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2069
2070 /* now that we have the eeprom settings, apply the special cases where
2071 * the eeprom may be wrong or the board simply won't support wake on
2072 * lan on a particular port */
2073 switch (pdev->device) {
2074 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2075 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2076 break;
2077 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2078 case E1000_DEV_ID_82576_FIBER:
2079 case E1000_DEV_ID_82576_SERDES:
9d5c8243
AK		 2080 /* Wake events only supported on port A for dual fiber
2081 * regardless of eeprom setting */
2082 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2083 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2084 break;
c8ea5ea9 2085 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2086 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2087 /* if quad port adapter, disable WoL on all but port A */
2088 if (global_quad_port_a != 0)
63d4a8f9 2089 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2090 else
2091 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2092 /* Reset for multiple quad port adapters */
2093 if (++global_quad_port_a == 4)
2094 global_quad_port_a = 0;
2095 break;
63d4a8f9
MV		 2096 default:
2097 /* If the device can't wake, don't set software support */
2098 if (!device_can_wakeup(&adapter->pdev->dev))
2099 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2100 }
2101
2102 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2103 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2104 adapter->wol |= E1000_WUFC_MAG;
2105
2106 /* Some vendors want WoL disabled by default, but still supported */
2107 if ((hw->mac.type == e1000_i350) &&
2108 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2109 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2110 adapter->wol = 0;
2111 }
2112
2113 device_set_wakeup_enable(&adapter->pdev->dev,
2114 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2115
2116 /* reset the hardware with the new settings */
2117 igb_reset(adapter);
2118
2119 /* let the f/w know that the h/w is now under the control of the
2120 * driver. */
2121 igb_get_hw_control(adapter);
2122
9d5c8243
AK		 2123 strcpy(netdev->name, "eth%d");
2124 err = register_netdev(netdev);
2125 if (err)
2126 goto err_register;
2127
b168dfc5
JB		 2128 /* carrier off reporting is important to ethtool even BEFORE open */
2129 netif_carrier_off(netdev);
2130
421e02f0 2131#ifdef CONFIG_IGB_DCA
bbd98fe4 2132 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2133 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2134 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2135 igb_setup_dca(adapter);
2136 }
fe4506b6 2137
38c845c7 2138#endif
3c89f6d0 2139
673b8b70 2140 /* do hw tstamp init after resetting */
7ebae817 2141 igb_ptp_init(adapter);
673b8b70 2142
9d5c8243
AK		 2143 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2144 /* print bus type/speed/width info */
7c510e4b 2145 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
9d5c8243 2146 netdev->name,
559e9c49 2147 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
ff846f52 2148 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
559e9c49 2149 "unknown"),
59c3de89
AD		 2150 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2151 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2152 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2153 "unknown"),
7c510e4b 2154 netdev->dev_addr);
9d5c8243 2155
9835fd73
CW		 2156 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2157 if (ret_val)
2158 strcpy(part_str, "Unknown");
2159 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2160 dev_info(&pdev->dev,
2161 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2162 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2163 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2164 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2165 switch (hw->mac.type) {
2166 case e1000_i350:
f96a8a0b
CW		 2167 case e1000_i210:
2168 case e1000_i211:
09b068d4
CW		 2169 igb_set_eee_i350(hw);
2170 break;
2171 default:
2172 break;
2173 }
749ab2cd
YZ		 2174
2175 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2176 return 0;
2177
2178err_register:
2179 igb_release_hw_control(adapter);
2180err_eeprom:
2181 if (!igb_check_reset_block(hw))
f5f4cf08 2182 igb_reset_phy(hw);
9d5c8243
AK		 2183
2184 if (hw->flash_address)
2185 iounmap(hw->flash_address);
9d5c8243 2186err_sw_init:
047e0030 2187 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2188 iounmap(hw->hw_addr);
2189err_ioremap:
2190 free_netdev(netdev);
2191err_alloc_etherdev:
559e9c49
AD		 2192 pci_release_selected_regions(pdev,
2193 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2194err_pci_reg:
2195err_dma:
2196 pci_disable_device(pdev);
2197 return err;
2198}
2199
2200/**
2201 * igb_remove - Device Removal Routine
2202 * @pdev: PCI device information struct
2203 *
2204 * igb_remove is called by the PCI subsystem to alert the driver
2205 * that it should release a PCI device. The could be caused by a
2206 * Hot-Plug event, or because the driver is going to be removed from
2207 * memory.
2208 **/
9f9a12f8 2209static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2210{
2211 struct net_device *netdev = pci_get_drvdata(pdev);
2212 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2213 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2214
749ab2cd 2215 pm_runtime_get_noresume(&pdev->dev);
a79f4f88 2216 igb_ptp_stop(adapter);
749ab2cd 2217
760141a5
TH		 2218 /*
2219 * The watchdog timer may be rescheduled, so explicitly
2220 * disable watchdog from being rescheduled.
2221 */
9d5c8243
AK		 2222 set_bit(__IGB_DOWN, &adapter->state);
2223 del_timer_sync(&adapter->watchdog_timer);
2224 del_timer_sync(&adapter->phy_info_timer);
2225
760141a5
TH		 2226 cancel_work_sync(&adapter->reset_task);
2227 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2228
421e02f0 2229#ifdef CONFIG_IGB_DCA
7dfc16fa 2230 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2231 dev_info(&pdev->dev, "DCA disabled\n");
2232 dca_remove_requester(&pdev->dev);
7dfc16fa 2233 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2234 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2235 }
2236#endif
2237
9d5c8243
AK		 2238 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2239 * would have already happened in close and is redundant. */
2240 igb_release_hw_control(adapter);
2241
2242 unregister_netdev(netdev);
2243
047e0030 2244 igb_clear_interrupt_scheme(adapter);
9d5c8243 2245
37680117
AD		 2246#ifdef CONFIG_PCI_IOV
2247 /* reclaim resources allocated to VFs */
2248 if (adapter->vf_data) {
2249 /* disable iov and allow time for transactions to clear */
f557147c
SA		 2250 if (igb_vfs_are_assigned(adapter)) {
2251 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2252 } else {
0224d663
GR		 2253 pci_disable_sriov(pdev);
2254 msleep(500);
0224d663 2255 }
37680117
AD		 2256
2257 kfree(adapter->vf_data);
2258 adapter->vf_data = NULL;
2259 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 2260 wrfl();
37680117
AD		 2261 msleep(100);
2262 dev_info(&pdev->dev, "IOV Disabled\n");
2263 }
2264#endif
559e9c49 2265
28b0759c
AD		 2266 iounmap(hw->hw_addr);
2267 if (hw->flash_address)
2268 iounmap(hw->flash_address);
559e9c49
AD		 2269 pci_release_selected_regions(pdev,
2270 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2271
1128c756 2272 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2273 free_netdev(netdev);
2274
19d5afd4 2275 pci_disable_pcie_error_reporting(pdev);
40a914fa 2276
9d5c8243
AK		 2277 pci_disable_device(pdev);
2278}
2279
a6b623e0
AD		 2280/**
2281 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2282 * @adapter: board private structure to initialize
2283 *
2284 * This function initializes the vf specific data storage and then attempts to
2285 * allocate the VFs. The reason for ordering it this way is because it is much
2286 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2287 * the memory for the VFs.
2288 **/
9f9a12f8 2289static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2290{
2291#ifdef CONFIG_PCI_IOV
2292 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2293 struct e1000_hw *hw = &adapter->hw;
f557147c 2294 int old_vfs = pci_num_vf(adapter->pdev);
0224d663 2295 int i;
a6b623e0 2296
f96a8a0b
CW		 2297 /* Virtualization features not supported on i210 family. */
2298 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2299 return;
2300
0224d663
GR		 2301 if (old_vfs) {
2302 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2303 "max_vfs setting of %d\n", old_vfs, max_vfs);
2304 adapter->vfs_allocated_count = old_vfs;
a6b623e0
AD		 2305 }
2306
0224d663
GR		 2307 if (!adapter->vfs_allocated_count)
2308 return;
2309
2310 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2311 sizeof(struct vf_data_storage), GFP_KERNEL);
f96a8a0b 2312
0224d663
GR		 2313 /* if allocation failed then we do not support SR-IOV */
2314 if (!adapter->vf_data) {
a6b623e0 2315 adapter->vfs_allocated_count = 0;
0224d663
GR		 2316 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2317 "Data Storage\n");
2318 goto out;
a6b623e0 2319 }
0224d663
GR		 2320
2321 if (!old_vfs) {
2322 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2323 goto err_out;
2324 }
2325 dev_info(&pdev->dev, "%d VFs allocated\n",
2326 adapter->vfs_allocated_count);
2327 for (i = 0; i < adapter->vfs_allocated_count; i++)
2328 igb_vf_configure(adapter, i);
2329
2330 /* DMA Coalescing is not supported in IOV mode. */
2331 adapter->flags &= ~IGB_FLAG_DMAC;
2332 goto out;
2333err_out:
2334 kfree(adapter->vf_data);
2335 adapter->vf_data = NULL;
2336 adapter->vfs_allocated_count = 0;
2337out:
2338 return;
a6b623e0
AD		 2339#endif /* CONFIG_PCI_IOV */
2340}
2341
9d5c8243
AK		 2342/**
2343 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2344 * @adapter: board private structure to initialize
2345 *
2346 * igb_sw_init initializes the Adapter private data structure.
2347 * Fields are initialized based on PCI device information and
2348 * OS network device settings (MTU size).
2349 **/
9f9a12f8 2350static int igb_sw_init(struct igb_adapter *adapter)
9d5c8243
AK		 2351{
2352 struct e1000_hw *hw = &adapter->hw;
2353 struct net_device *netdev = adapter->netdev;
2354 struct pci_dev *pdev = adapter->pdev;
374a542d 2355 u32 max_rss_queues;
9d5c8243
AK		 2356
2357 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2358
13fde97a 2359 /* set default ring sizes */
68fd9910
AD		 2360 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2361 adapter->rx_ring_count = IGB_DEFAULT_RXD;
13fde97a
AD		 2362
2363 /* set default ITR values */
4fc82adf
AD		 2364 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2365 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2366
13fde97a
AD		 2367 /* set default work limits */
2368 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2369
153285f9
AD		 2370 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2371 VLAN_HLEN;
9d5c8243
AK		 2372 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2373
12dcd86b 2374 spin_lock_init(&adapter->stats64_lock);
a6b623e0 2375#ifdef CONFIG_PCI_IOV
6b78bb1d
CW		 2376 switch (hw->mac.type) {
2377 case e1000_82576:
2378 case e1000_i350:
9b082d73
SA		 2379 if (max_vfs > 7) {
2380 dev_warn(&pdev->dev,
2381 "Maximum of 7 VFs per PF, using max\n");
2382 adapter->vfs_allocated_count = 7;
2383 } else
2384 adapter->vfs_allocated_count = max_vfs;
6b78bb1d
CW		 2385 break;
2386 default:
2387 break;
2388 }
a6b623e0 2389#endif /* CONFIG_PCI_IOV */
374a542d
MV		 2390
2391 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2392 switch (hw->mac.type) {
374a542d
MV		 2393 case e1000_i211:
2394 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2395 break;
2396 case e1000_82575:
f96a8a0b 2397 case e1000_i210:
374a542d
MV		 2398 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2399 break;
2400 case e1000_i350:
2401 /* I350 cannot do RSS and SR-IOV at the same time */
2402 if (!!adapter->vfs_allocated_count) {
2403 max_rss_queues = 1;
2404 break;
2405 }
2406 /* fall through */
2407 case e1000_82576:
2408 if (!!adapter->vfs_allocated_count) {
2409 max_rss_queues = 2;
2410 break;
2411 }
2412 /* fall through */
2413 case e1000_82580:
2414 default:
2415 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2416 break;
374a542d
MV		 2417 }
2418
2419 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2420
2421 /* Determine if we need to pair queues. */
2422 switch (hw->mac.type) {
2423 case e1000_82575:
f96a8a0b 2424 case e1000_i211:
374a542d 2425 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2426 break;
374a542d
MV		 2427 case e1000_82576:
2428 /*
2429 * If VFs are going to be allocated with RSS queues then we
2430 * should pair the queues in order to conserve interrupts due
2431 * to limited supply.
2432 */
2433 if ((adapter->rss_queues > 1) &&
2434 (adapter->vfs_allocated_count > 6))
2435 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2436 /* fall through */
2437 case e1000_82580:
2438 case e1000_i350:
2439 case e1000_i210:
f96a8a0b 2440 default:
374a542d
MV		 2441 /*
2442 * If rss_queues > half of max_rss_queues, pair the queues in
2443 * order to conserve interrupts due to limited supply.
2444 */
2445 if (adapter->rss_queues > (max_rss_queues / 2))
2446 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2447 break;
2448 }
a99955fc 2449
1128c756
CW		 2450 /* Setup and initialize a copy of the hw vlan table array */
2451 adapter->shadow_vfta = kzalloc(sizeof(u32) *
2452 E1000_VLAN_FILTER_TBL_SIZE,
2453 GFP_ATOMIC);
2454
a6b623e0 2455 /* This call may decrease the number of queues */
53c7d064 2456 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2457 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2458 return -ENOMEM;
2459 }
2460
a6b623e0
AD		 2461 igb_probe_vfs(adapter);
2462
9d5c8243
AK		 2463 /* Explicitly disable IRQ since the NIC can be in any state. */
2464 igb_irq_disable(adapter);
2465
f96a8a0b 2466 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2467 adapter->flags &= ~IGB_FLAG_DMAC;
2468
9d5c8243
AK		 2469 set_bit(__IGB_DOWN, &adapter->state);
2470 return 0;
2471}
2472
2473/**
2474 * igb_open - Called when a network interface is made active
2475 * @netdev: network interface device structure
2476 *
2477 * Returns 0 on success, negative value on failure
2478 *
2479 * The open entry point is called when a network interface is made
2480 * active by the system (IFF_UP). At this point all resources needed
2481 * for transmit and receive operations are allocated, the interrupt
2482 * handler is registered with the OS, the watchdog timer is started,
2483 * and the stack is notified that the interface is ready.
2484 **/
749ab2cd 2485static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2486{
2487 struct igb_adapter *adapter = netdev_priv(netdev);
2488 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2489 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2490 int err;
2491 int i;
2492
2493 /* disallow open during test */
749ab2cd
YZ		 2494 if (test_bit(__IGB_TESTING, &adapter->state)) {
2495 WARN_ON(resuming);
9d5c8243 2496 return -EBUSY;
749ab2cd
YZ		 2497 }
2498
2499 if (!resuming)
2500 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2501
b168dfc5
JB		 2502 netif_carrier_off(netdev);
2503
9d5c8243
AK		 2504 /* allocate transmit descriptors */
2505 err = igb_setup_all_tx_resources(adapter);
2506 if (err)
2507 goto err_setup_tx;
2508
2509 /* allocate receive descriptors */
2510 err = igb_setup_all_rx_resources(adapter);
2511 if (err)
2512 goto err_setup_rx;
2513
88a268c1 2514 igb_power_up_link(adapter);
9d5c8243 2515
9d5c8243
AK		 2516 /* before we allocate an interrupt, we must be ready to handle it.
2517 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2518 * as soon as we call pci_request_irq, so we have to setup our
2519 * clean_rx handler before we do so. */
2520 igb_configure(adapter);
2521
2522 err = igb_request_irq(adapter);
2523 if (err)
2524 goto err_req_irq;
2525
0c2cc02e
AD		 2526 /* Notify the stack of the actual queue counts. */
2527 err = netif_set_real_num_tx_queues(adapter->netdev,
2528 adapter->num_tx_queues);
2529 if (err)
2530 goto err_set_queues;
2531
2532 err = netif_set_real_num_rx_queues(adapter->netdev,
2533 adapter->num_rx_queues);
2534 if (err)
2535 goto err_set_queues;
2536
9d5c8243
AK		 2537 /* From here on the code is the same as igb_up() */
2538 clear_bit(__IGB_DOWN, &adapter->state);
2539
0d1ae7f4
AD		 2540 for (i = 0; i < adapter->num_q_vectors; i++)
2541 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2542
2543 /* Clear any pending interrupts. */
2544 rd32(E1000_ICR);
844290e5
PW		 2545
2546 igb_irq_enable(adapter);
2547
d4960307
AD		 2548 /* notify VFs that reset has been completed */
2549 if (adapter->vfs_allocated_count) {
2550 u32 reg_data = rd32(E1000_CTRL_EXT);
2551 reg_data |= E1000_CTRL_EXT_PFRSTD;
2552 wr32(E1000_CTRL_EXT, reg_data);
2553 }
2554
d55b53ff
JK		 2555 netif_tx_start_all_queues(netdev);
2556
749ab2cd
YZ		 2557 if (!resuming)
2558 pm_runtime_put(&pdev->dev);
2559
25568a53
AD		 2560 /* start the watchdog. */
2561 hw->mac.get_link_status = 1;
2562 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2563
2564 return 0;
2565
0c2cc02e
AD		 2566err_set_queues:
2567 igb_free_irq(adapter);
9d5c8243
AK		 2568err_req_irq:
2569 igb_release_hw_control(adapter);
88a268c1 2570 igb_power_down_link(adapter);
9d5c8243
AK		 2571 igb_free_all_rx_resources(adapter);
2572err_setup_rx:
2573 igb_free_all_tx_resources(adapter);
2574err_setup_tx:
2575 igb_reset(adapter);
749ab2cd
YZ		 2576 if (!resuming)
2577 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2578
2579 return err;
2580}
2581
749ab2cd
YZ		 2582static int igb_open(struct net_device *netdev)
2583{
2584 return __igb_open(netdev, false);
2585}
2586
9d5c8243
AK		 2587/**
2588 * igb_close - Disables a network interface
2589 * @netdev: network interface device structure
2590 *
2591 * Returns 0, this is not allowed to fail
2592 *
2593 * The close entry point is called when an interface is de-activated
2594 * by the OS. The hardware is still under the driver's control, but
2595 * needs to be disabled. A global MAC reset is issued to stop the
2596 * hardware, and all transmit and receive resources are freed.
2597 **/
749ab2cd 2598static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2599{
2600 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2601 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2602
2603 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2604
749ab2cd
YZ		 2605 if (!suspending)
2606 pm_runtime_get_sync(&pdev->dev);
2607
2608 igb_down(adapter);
9d5c8243
AK		 2609 igb_free_irq(adapter);
2610
2611 igb_free_all_tx_resources(adapter);
2612 igb_free_all_rx_resources(adapter);
2613
749ab2cd
YZ		 2614 if (!suspending)
2615 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2616 return 0;
2617}
2618
749ab2cd
YZ		 2619static int igb_close(struct net_device *netdev)
2620{
2621 return __igb_close(netdev, false);
2622}
2623
9d5c8243
AK		 2624/**
2625 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
9d5c8243
AK		 2626 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2627 *
2628 * Return 0 on success, negative on failure
2629 **/
80785298 2630int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2631{
59d71989 2632 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2633 int size;
2634
06034649 2635 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2636
2637 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2638 if (!tx_ring->tx_buffer_info)
9d5c8243 2639 goto err;
9d5c8243
AK		 2640
2641 /* round up to nearest 4K */
85e8d004 2642 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2643 tx_ring->size = ALIGN(tx_ring->size, 4096);
2644
5536d210
AD		 2645 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2646 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2647 if (!tx_ring->desc)
2648 goto err;
2649
9d5c8243
AK		 2650 tx_ring->next_to_use = 0;
2651 tx_ring->next_to_clean = 0;
81c2fc22 2652
9d5c8243
AK		 2653 return 0;
2654
2655err:
06034649 2656 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2657 tx_ring->tx_buffer_info = NULL;
2658 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2659 return -ENOMEM;
2660}
2661
2662/**
2663 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2664 * (Descriptors) for all queues
2665 * @adapter: board private structure
2666 *
2667 * Return 0 on success, negative on failure
2668 **/
2669static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2670{
439705e1 2671 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2672 int i, err = 0;
2673
2674 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2675 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2676 if (err) {
439705e1 2677 dev_err(&pdev->dev,
9d5c8243
AK		 2678 "Allocation for Tx Queue %u failed\n", i);
2679 for (i--; i >= 0; i--)
3025a446 2680 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2681 break;
2682 }
2683 }
2684
2685 return err;
2686}
2687
2688/**
85b430b4
AD		 2689 * igb_setup_tctl - configure the transmit control registers
2690 * @adapter: Board private structure
9d5c8243 2691 **/
d7ee5b3a 2692void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2693{
9d5c8243
AK		 2694 struct e1000_hw *hw = &adapter->hw;
2695 u32 tctl;
9d5c8243 2696
85b430b4
AD		 2697 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2698 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2699
2700 /* Program the Transmit Control Register */
9d5c8243
AK		 2701 tctl = rd32(E1000_TCTL);
2702 tctl &= ~E1000_TCTL_CT;
2703 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2704 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2705
2706 igb_config_collision_dist(hw);
2707
9d5c8243
AK		 2708 /* Enable transmits */
2709 tctl |= E1000_TCTL_EN;
2710
2711 wr32(E1000_TCTL, tctl);
2712}
2713
85b430b4
AD		 2714/**
2715 * igb_configure_tx_ring - Configure transmit ring after Reset
2716 * @adapter: board private structure
2717 * @ring: tx ring to configure
2718 *
2719 * Configure a transmit ring after a reset.
2720 **/
d7ee5b3a
AD		 2721void igb_configure_tx_ring(struct igb_adapter *adapter,
2722 struct igb_ring *ring)
85b430b4
AD		 2723{
2724 struct e1000_hw *hw = &adapter->hw;
a74420e0 2725 u32 txdctl = 0;
85b430b4
AD		 2726 u64 tdba = ring->dma;
2727 int reg_idx = ring->reg_idx;
2728
2729 /* disable the queue */
a74420e0 2730 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 2731 wrfl();
2732 mdelay(10);
2733
2734 wr32(E1000_TDLEN(reg_idx),
2735 ring->count * sizeof(union e1000_adv_tx_desc));
2736 wr32(E1000_TDBAL(reg_idx),
2737 tdba & 0x00000000ffffffffULL);
2738 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2739
fce99e34 2740 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 2741 wr32(E1000_TDH(reg_idx), 0);
fce99e34 2742 writel(0, ring->tail);
85b430b4
AD		 2743
2744 txdctl |= IGB_TX_PTHRESH;
2745 txdctl |= IGB_TX_HTHRESH << 8;
2746 txdctl |= IGB_TX_WTHRESH << 16;
2747
2748 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2749 wr32(E1000_TXDCTL(reg_idx), txdctl);
2750}
2751
2752/**
2753 * igb_configure_tx - Configure transmit Unit after Reset
2754 * @adapter: board private structure
2755 *
2756 * Configure the Tx unit of the MAC after a reset.
2757 **/
2758static void igb_configure_tx(struct igb_adapter *adapter)
2759{
2760 int i;
2761
2762 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 2763 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 2764}
2765
9d5c8243
AK		 2766/**
2767 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
9d5c8243
AK		 2768 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2769 *
2770 * Returns 0 on success, negative on failure
2771 **/
80785298 2772int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 2773{
59d71989 2774 struct device *dev = rx_ring->dev;
f33005a6 2775 int size;
9d5c8243 2776
06034649 2777 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 2778
2779 rx_ring->rx_buffer_info = vzalloc(size);
06034649 2780 if (!rx_ring->rx_buffer_info)
9d5c8243 2781 goto err;
9d5c8243 2782
9d5c8243 2783 /* Round up to nearest 4K */
f33005a6 2784 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 2785 rx_ring->size = ALIGN(rx_ring->size, 4096);
2786
5536d210
AD		 2787 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2788 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2789 if (!rx_ring->desc)
2790 goto err;
2791
cbc8e55f 2792 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 2793 rx_ring->next_to_clean = 0;
2794 rx_ring->next_to_use = 0;
9d5c8243 2795
9d5c8243
AK		 2796 return 0;
2797
2798err:
06034649
AD		 2799 vfree(rx_ring->rx_buffer_info);
2800 rx_ring->rx_buffer_info = NULL;
f33005a6 2801 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 2802 return -ENOMEM;
2803}
2804
2805/**
2806 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2807 * (Descriptors) for all queues
2808 * @adapter: board private structure
2809 *
2810 * Return 0 on success, negative on failure
2811 **/
2812static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2813{
439705e1 2814 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2815 int i, err = 0;
2816
2817 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 2818 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 2819 if (err) {
439705e1 2820 dev_err(&pdev->dev,
9d5c8243
AK		 2821 "Allocation for Rx Queue %u failed\n", i);
2822 for (i--; i >= 0; i--)
3025a446 2823 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 2824 break;
2825 }
2826 }
2827
2828 return err;
2829}
2830
06cf2666
AD		 2831/**
2832 * igb_setup_mrqc - configure the multiple receive queue control registers
2833 * @adapter: Board private structure
2834 **/
2835static void igb_setup_mrqc(struct igb_adapter *adapter)
2836{
2837 struct e1000_hw *hw = &adapter->hw;
2838 u32 mrqc, rxcsum;
797fd4be 2839 u32 j, num_rx_queues, shift = 0;
a57fe23e
AD		 2840 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2841 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2842 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2843 0xFA01ACBE };
06cf2666
AD		 2844
2845 /* Fill out hash function seeds */
a57fe23e
AD		 2846 for (j = 0; j < 10; j++)
2847 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 2848
a99955fc 2849 num_rx_queues = adapter->rss_queues;
06cf2666 2850
797fd4be
AD		 2851 switch (hw->mac.type) {
2852 case e1000_82575:
2853 shift = 6;
2854 break;
2855 case e1000_82576:
2856 /* 82576 supports 2 RSS queues for SR-IOV */
2857 if (adapter->vfs_allocated_count) {
06cf2666
AD		 2858 shift = 3;
2859 num_rx_queues = 2;
06cf2666 2860 }
797fd4be
AD		 2861 break;
2862 default:
2863 break;
06cf2666
AD		 2864 }
2865
797fd4be
AD		 2866 /*
2867 * Populate the indirection table 4 entries at a time. To do this
2868 * we are generating the results for n and n+2 and then interleaving
2869 * those with the results with n+1 and n+3.
2870 */
2871 for (j = 0; j < 32; j++) {
2872 /* first pass generates n and n+2 */
2873 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2874 u32 reta = (base & 0x07800780) >> (7 - shift);
2875
2876 /* second pass generates n+1 and n+3 */
2877 base += 0x00010001 * num_rx_queues;
2878 reta |= (base & 0x07800780) << (1 + shift);
2879
2880 wr32(E1000_RETA(j), reta);
06cf2666
AD		 2881 }
2882
2883 /*
2884 * Disable raw packet checksumming so that RSS hash is placed in
2885 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
2886 * offloads as they are enabled by default
2887 */
2888 rxcsum = rd32(E1000_RXCSUM);
2889 rxcsum |= E1000_RXCSUM_PCSD;
2890
2891 if (adapter->hw.mac.type >= e1000_82576)
2892 /* Enable Receive Checksum Offload for SCTP */
2893 rxcsum |= E1000_RXCSUM_CRCOFL;
2894
2895 /* Don't need to set TUOFL or IPOFL, they default to 1 */
2896 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 2897
039454a8
AA		 2898 /* Generate RSS hash based on packet types, TCP/UDP
2899 * port numbers and/or IPv4/v6 src and dst addresses
2900 */
f96a8a0b
CW		 2901 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2902 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2903 E1000_MRQC_RSS_FIELD_IPV6 |
2904 E1000_MRQC_RSS_FIELD_IPV6_TCP |
2905 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 2906
039454a8
AA		 2907 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2908 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2909 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2910 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2911
06cf2666
AD		 2912 /* If VMDq is enabled then we set the appropriate mode for that, else
2913 * we default to RSS so that an RSS hash is calculated per packet even
2914 * if we are only using one queue */
2915 if (adapter->vfs_allocated_count) {
2916 if (hw->mac.type > e1000_82575) {
2917 /* Set the default pool for the PF's first queue */
2918 u32 vtctl = rd32(E1000_VT_CTL);
2919 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2920 E1000_VT_CTL_DISABLE_DEF_POOL);
2921 vtctl |= adapter->vfs_allocated_count <<
2922 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2923 wr32(E1000_VT_CTL, vtctl);
2924 }
a99955fc 2925 if (adapter->rss_queues > 1)
f96a8a0b 2926 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 2927 else
f96a8a0b 2928 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 2929 } else {
f96a8a0b
CW		 2930 if (hw->mac.type != e1000_i211)
2931 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 2932 }
2933 igb_vmm_control(adapter);
2934
06cf2666
AD		 2935 wr32(E1000_MRQC, mrqc);
2936}
2937
9d5c8243
AK		 2938/**
2939 * igb_setup_rctl - configure the receive control registers
2940 * @adapter: Board private structure
2941 **/
d7ee5b3a 2942void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 2943{
2944 struct e1000_hw *hw = &adapter->hw;
2945 u32 rctl;
9d5c8243
AK		 2946
2947 rctl = rd32(E1000_RCTL);
2948
2949 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 2950 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 2951
69d728ba 2952 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 2953 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 2954
87cb7e8c
AK		 2955 /*
2956 * enable stripping of CRC. It's unlikely this will break BMC
2957 * redirection as it did with e1000. Newer features require
2958 * that the HW strips the CRC.
73cd78f1 2959 */
87cb7e8c 2960 rctl |= E1000_RCTL_SECRC;
9d5c8243 2961
559e9c49 2962 /* disable store bad packets and clear size bits. */
ec54d7d6 2963 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 2964
6ec43fe6
AD		 2965 /* enable LPE to prevent packets larger than max_frame_size */
2966 rctl |= E1000_RCTL_LPE;
9d5c8243 2967
952f72a8
AD		 2968 /* disable queue 0 to prevent tail write w/o re-config */
2969 wr32(E1000_RXDCTL(0), 0);
9d5c8243 2970
e1739522
AD		 2971 /* Attention!!! For SR-IOV PF driver operations you must enable
2972 * queue drop for all VF and PF queues to prevent head of line blocking
2973 * if an un-trusted VF does not provide descriptors to hardware.
2974 */
2975 if (adapter->vfs_allocated_count) {
e1739522
AD		 2976 /* set all queue drop enable bits */
2977 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 2978 }
2979
89eaefb6
BG		 2980 /* This is useful for sniffing bad packets. */
2981 if (adapter->netdev->features & NETIF_F_RXALL) {
2982 /* UPE and MPE will be handled by normal PROMISC logic
2983 * in e1000e_set_rx_mode */
2984 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2985 E1000_RCTL_BAM | /* RX All Bcast Pkts */
2986 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2987
2988 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2989 E1000_RCTL_DPF | /* Allow filtered pause */
2990 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2991 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2992 * and that breaks VLANs.
2993 */
2994 }
2995
9d5c8243
AK		 2996 wr32(E1000_RCTL, rctl);
2997}
2998
7d5753f0
AD		 2999static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3000 int vfn)
3001{
3002 struct e1000_hw *hw = &adapter->hw;
3003 u32 vmolr;
3004
3005 /* if it isn't the PF check to see if VFs are enabled and
3006 * increase the size to support vlan tags */
3007 if (vfn < adapter->vfs_allocated_count &&
3008 adapter->vf_data[vfn].vlans_enabled)
3009 size += VLAN_TAG_SIZE;
3010
3011 vmolr = rd32(E1000_VMOLR(vfn));
3012 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3013 vmolr |= size | E1000_VMOLR_LPE;
3014 wr32(E1000_VMOLR(vfn), vmolr);
3015
3016 return 0;
3017}
3018
e1739522
AD		 3019/**
3020 * igb_rlpml_set - set maximum receive packet size
3021 * @adapter: board private structure
3022 *
3023 * Configure maximum receivable packet size.
3024 **/
3025static void igb_rlpml_set(struct igb_adapter *adapter)
3026{
153285f9 3027 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3028 struct e1000_hw *hw = &adapter->hw;
3029 u16 pf_id = adapter->vfs_allocated_count;
3030
e1739522
AD		 3031 if (pf_id) {
3032 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
153285f9
AD		 3033 /*
3034 * If we're in VMDQ or SR-IOV mode, then set global RLPML
3035 * to our max jumbo frame size, in case we need to enable
3036 * jumbo frames on one of the rings later.
3037 * This will not pass over-length frames into the default
3038 * queue because it's gated by the VMOLR.RLPML.
3039 */
7d5753f0 3040 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3041 }
3042
3043 wr32(E1000_RLPML, max_frame_size);
3044}
3045
8151d294
WM		 3046static inline void igb_set_vmolr(struct igb_adapter *adapter,
3047 int vfn, bool aupe)
7d5753f0
AD		 3048{
3049 struct e1000_hw *hw = &adapter->hw;
3050 u32 vmolr;
3051
3052 /*
3053 * This register exists only on 82576 and newer so if we are older then
3054 * we should exit and do nothing
3055 */
3056 if (hw->mac.type < e1000_82576)
3057 return;
3058
3059 vmolr = rd32(E1000_VMOLR(vfn));
8151d294
WM		 3060 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
3061 if (aupe)
3062 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
3063 else
3064 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3065
3066 /* clear all bits that might not be set */
3067 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3068
a99955fc 3069 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0
AD		 3070 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3071 /*
3072 * for VMDq only allow the VFs and pool 0 to accept broadcast and
3073 * multicast packets
3074 */
3075 if (vfn <= adapter->vfs_allocated_count)
3076 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
3077
3078 wr32(E1000_VMOLR(vfn), vmolr);
3079}
3080
85b430b4
AD		 3081/**
3082 * igb_configure_rx_ring - Configure a receive ring after Reset
3083 * @adapter: board private structure
3084 * @ring: receive ring to be configured
3085 *
3086 * Configure the Rx unit of the MAC after a reset.
3087 **/
d7ee5b3a
AD		 3088void igb_configure_rx_ring(struct igb_adapter *adapter,
3089 struct igb_ring *ring)
85b430b4
AD		 3090{
3091 struct e1000_hw *hw = &adapter->hw;
3092 u64 rdba = ring->dma;
3093 int reg_idx = ring->reg_idx;
a74420e0 3094 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3095
3096 /* disable the queue */
a74420e0 3097 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3098
3099 /* Set DMA base address registers */
3100 wr32(E1000_RDBAL(reg_idx),
3101 rdba & 0x00000000ffffffffULL);
3102 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3103 wr32(E1000_RDLEN(reg_idx),
3104 ring->count * sizeof(union e1000_adv_rx_desc));
3105
3106 /* initialize head and tail */
fce99e34 3107 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3108 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3109 writel(0, ring->tail);
85b430b4 3110
952f72a8 3111 /* set descriptor configuration */
44390ca6 3112 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3113 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3114 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3115 if (hw->mac.type >= e1000_82580)
757b77e2 3116 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3117 /* Only set Drop Enable if we are supporting multiple queues */
3118 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3119 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3120
3121 wr32(E1000_SRRCTL(reg_idx), srrctl);
3122
7d5753f0 3123 /* set filtering for VMDQ pools */
8151d294 3124 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3125
85b430b4
AD		 3126 rxdctl |= IGB_RX_PTHRESH;
3127 rxdctl |= IGB_RX_HTHRESH << 8;
3128 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3129
3130 /* enable receive descriptor fetching */
3131 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3132 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3133}
3134
9d5c8243
AK		 3135/**
3136 * igb_configure_rx - Configure receive Unit after Reset
3137 * @adapter: board private structure
3138 *
3139 * Configure the Rx unit of the MAC after a reset.
3140 **/
3141static void igb_configure_rx(struct igb_adapter *adapter)
3142{
9107584e 3143 int i;
9d5c8243 3144
68d480c4
AD		 3145 /* set UTA to appropriate mode */
3146 igb_set_uta(adapter);
3147
26ad9178
AD		 3148 /* set the correct pool for the PF default MAC address in entry 0 */
3149 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3150 adapter->vfs_allocated_count);
3151
06cf2666
AD		 3152 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3153 * the Base and Length of the Rx Descriptor Ring */
3154 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3155 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3156}
3157
3158/**
3159 * igb_free_tx_resources - Free Tx Resources per Queue
9d5c8243
AK		 3160 * @tx_ring: Tx descriptor ring for a specific queue
3161 *
3162 * Free all transmit software resources
3163 **/
68fd9910 3164void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3165{
3b644cf6 3166 igb_clean_tx_ring(tx_ring);
9d5c8243 3167
06034649
AD		 3168 vfree(tx_ring->tx_buffer_info);
3169 tx_ring->tx_buffer_info = NULL;
9d5c8243 3170
439705e1
AD		 3171 /* if not set, then don't free */
3172 if (!tx_ring->desc)
3173 return;
3174
59d71989
AD		 3175 dma_free_coherent(tx_ring->dev, tx_ring->size,
3176 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3177
3178 tx_ring->desc = NULL;
3179}
3180
3181/**
3182 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3183 * @adapter: board private structure
3184 *
3185 * Free all transmit software resources
3186 **/
3187static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3188{
3189 int i;
3190
3191 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3192 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3193}
3194
ebe42d16
AD		 3195void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3196 struct igb_tx_buffer *tx_buffer)
3197{
3198 if (tx_buffer->skb) {
3199 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3200 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3201 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3202 dma_unmap_addr(tx_buffer, dma),
3203 dma_unmap_len(tx_buffer, len),
ebe42d16 3204 DMA_TO_DEVICE);
c9f14bf3 3205 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3206 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3207 dma_unmap_addr(tx_buffer, dma),
3208 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3209 DMA_TO_DEVICE);
3210 }
3211 tx_buffer->next_to_watch = NULL;
3212 tx_buffer->skb = NULL;
c9f14bf3 3213 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3214 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3215}
3216
3217/**
3218 * igb_clean_tx_ring - Free Tx Buffers
9d5c8243
AK		 3219 * @tx_ring: ring to be cleaned
3220 **/
3b644cf6 3221static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3222{
06034649 3223 struct igb_tx_buffer *buffer_info;
9d5c8243 3224 unsigned long size;
6ad4edfc 3225 u16 i;
9d5c8243 3226
06034649 3227 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3228 return;
3229 /* Free all the Tx ring sk_buffs */
3230
3231 for (i = 0; i < tx_ring->count; i++) {
06034649 3232 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3233 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3234 }
3235
dad8a3b3
JF		 3236 netdev_tx_reset_queue(txring_txq(tx_ring));
3237
06034649
AD		 3238 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3239 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3240
3241 /* Zero out the descriptor ring */
9d5c8243
AK		 3242 memset(tx_ring->desc, 0, tx_ring->size);
3243
3244 tx_ring->next_to_use = 0;
3245 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3246}
3247
3248/**
3249 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3250 * @adapter: board private structure
3251 **/
3252static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3253{
3254 int i;
3255
3256 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3257 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3258}
3259
3260/**
3261 * igb_free_rx_resources - Free Rx Resources
9d5c8243
AK		 3262 * @rx_ring: ring to clean the resources from
3263 *
3264 * Free all receive software resources
3265 **/
68fd9910 3266void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3267{
3b644cf6 3268 igb_clean_rx_ring(rx_ring);
9d5c8243 3269
06034649
AD		 3270 vfree(rx_ring->rx_buffer_info);
3271 rx_ring->rx_buffer_info = NULL;
9d5c8243 3272
439705e1
AD		 3273 /* if not set, then don't free */
3274 if (!rx_ring->desc)
3275 return;
3276
59d71989
AD		 3277 dma_free_coherent(rx_ring->dev, rx_ring->size,
3278 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3279
3280 rx_ring->desc = NULL;
3281}
3282
3283/**
3284 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3285 * @adapter: board private structure
3286 *
3287 * Free all receive software resources
3288 **/
3289static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3290{
3291 int i;
3292
3293 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3294 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3295}
3296
3297/**
3298 * igb_clean_rx_ring - Free Rx Buffers per Queue
9d5c8243
AK		 3299 * @rx_ring: ring to free buffers from
3300 **/
3b644cf6 3301static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3302{
9d5c8243 3303 unsigned long size;
c023cd88 3304 u16 i;
9d5c8243 3305
1a1c225b
AD		 3306 if (rx_ring->skb)
3307 dev_kfree_skb(rx_ring->skb);
3308 rx_ring->skb = NULL;
3309
06034649 3310 if (!rx_ring->rx_buffer_info)
9d5c8243 3311 return;
439705e1 3312
9d5c8243
AK		 3313 /* Free all the Rx ring sk_buffs */
3314 for (i = 0; i < rx_ring->count; i++) {
06034649 3315 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3316
cbc8e55f
AD		 3317 if (!buffer_info->page)
3318 continue;
3319
3320 dma_unmap_page(rx_ring->dev,
3321 buffer_info->dma,
3322 PAGE_SIZE,
3323 DMA_FROM_DEVICE);
3324 __free_page(buffer_info->page);
3325
1a1c225b 3326 buffer_info->page = NULL;
9d5c8243
AK		 3327 }
3328
06034649
AD		 3329 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3330 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3331
3332 /* Zero out the descriptor ring */
3333 memset(rx_ring->desc, 0, rx_ring->size);
3334
cbc8e55f 3335 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3336 rx_ring->next_to_clean = 0;
3337 rx_ring->next_to_use = 0;
9d5c8243
AK		 3338}
3339
3340/**
3341 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3342 * @adapter: board private structure
3343 **/
3344static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3345{
3346 int i;
3347
3348 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3349 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3350}
3351
3352/**
3353 * igb_set_mac - Change the Ethernet Address of the NIC
3354 * @netdev: network interface device structure
3355 * @p: pointer to an address structure
3356 *
3357 * Returns 0 on success, negative on failure
3358 **/
3359static int igb_set_mac(struct net_device *netdev, void *p)
3360{
3361 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3362 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3363 struct sockaddr *addr = p;
3364
3365 if (!is_valid_ether_addr(addr->sa_data))
3366 return -EADDRNOTAVAIL;
3367
3368 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3369 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3370
26ad9178
AD		 3371 /* set the correct pool for the new PF MAC address in entry 0 */
3372 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3373 adapter->vfs_allocated_count);
e1739522 3374
9d5c8243
AK		 3375 return 0;
3376}
3377
3378/**
68d480c4 3379 * igb_write_mc_addr_list - write multicast addresses to MTA
9d5c8243
AK		 3380 * @netdev: network interface device structure
3381 *
68d480c4
AD		 3382 * Writes multicast address list to the MTA hash table.
3383 * Returns: -ENOMEM on failure
3384 * 0 on no addresses written
3385 * X on writing X addresses to MTA
9d5c8243 3386 **/
68d480c4 3387static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3388{
3389 struct igb_adapter *adapter = netdev_priv(netdev);
3390 struct e1000_hw *hw = &adapter->hw;
22bedad3 3391 struct netdev_hw_addr *ha;
68d480c4 3392 u8 *mta_list;
9d5c8243
AK		 3393 int i;
3394
4cd24eaf 3395 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3396 /* nothing to program, so clear mc list */
3397 igb_update_mc_addr_list(hw, NULL, 0);
3398 igb_restore_vf_multicasts(adapter);
3399 return 0;
3400 }
9d5c8243 3401
4cd24eaf 3402 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3403 if (!mta_list)
3404 return -ENOMEM;
ff41f8dc 3405
68d480c4 3406 /* The shared function expects a packed array of only addresses. */
48e2f183 3407 i = 0;
22bedad3
JP		 3408 netdev_for_each_mc_addr(ha, netdev)
3409 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3410
68d480c4
AD		 3411 igb_update_mc_addr_list(hw, mta_list, i);
3412 kfree(mta_list);
3413
4cd24eaf 3414 return netdev_mc_count(netdev);
68d480c4
AD		 3415}
3416
3417/**
3418 * igb_write_uc_addr_list - write unicast addresses to RAR table
3419 * @netdev: network interface device structure
3420 *
3421 * Writes unicast address list to the RAR table.
3422 * Returns: -ENOMEM on failure/insufficient address space
3423 * 0 on no addresses written
3424 * X on writing X addresses to the RAR table
3425 **/
3426static int igb_write_uc_addr_list(struct net_device *netdev)
3427{
3428 struct igb_adapter *adapter = netdev_priv(netdev);
3429 struct e1000_hw *hw = &adapter->hw;
3430 unsigned int vfn = adapter->vfs_allocated_count;
3431 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3432 int count = 0;
3433
3434 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3435 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3436 return -ENOMEM;
9d5c8243 3437
32e7bfc4 3438 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3439 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3440
3441 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3442 if (!rar_entries)
3443 break;
26ad9178
AD		 3444 igb_rar_set_qsel(adapter, ha->addr,
3445 rar_entries--,
68d480c4
AD		 3446 vfn);
3447 count++;
ff41f8dc
AD		 3448 }
3449 }
3450 /* write the addresses in reverse order to avoid write combining */
3451 for (; rar_entries > 0 ; rar_entries--) {
3452 wr32(E1000_RAH(rar_entries), 0);
3453 wr32(E1000_RAL(rar_entries), 0);
3454 }
3455 wrfl();
3456
68d480c4
AD		 3457 return count;
3458}
3459
3460/**
3461 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3462 * @netdev: network interface device structure
3463 *
3464 * The set_rx_mode entry point is called whenever the unicast or multicast
3465 * address lists or the network interface flags are updated. This routine is
3466 * responsible for configuring the hardware for proper unicast, multicast,
3467 * promiscuous mode, and all-multi behavior.
3468 **/
3469static void igb_set_rx_mode(struct net_device *netdev)
3470{
3471 struct igb_adapter *adapter = netdev_priv(netdev);
3472 struct e1000_hw *hw = &adapter->hw;
3473 unsigned int vfn = adapter->vfs_allocated_count;
3474 u32 rctl, vmolr = 0;
3475 int count;
3476
3477 /* Check for Promiscuous and All Multicast modes */
3478 rctl = rd32(E1000_RCTL);
3479
3480 /* clear the effected bits */
3481 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3482
3483 if (netdev->flags & IFF_PROMISC) {
3484 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3485 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3486 } else {
3487 if (netdev->flags & IFF_ALLMULTI) {
3488 rctl |= E1000_RCTL_MPE;
3489 vmolr |= E1000_VMOLR_MPME;
3490 } else {
3491 /*
3492 * Write addresses to the MTA, if the attempt fails
25985edc 3493 * then we should just turn on promiscuous mode so
68d480c4
AD		 3494 * that we can at least receive multicast traffic
3495 */
3496 count = igb_write_mc_addr_list(netdev);
3497 if (count < 0) {
3498 rctl |= E1000_RCTL_MPE;
3499 vmolr |= E1000_VMOLR_MPME;
3500 } else if (count) {
3501 vmolr |= E1000_VMOLR_ROMPE;
3502 }
3503 }
3504 /*
3505 * Write addresses to available RAR registers, if there is not
3506 * sufficient space to store all the addresses then enable
25985edc 3507 * unicast promiscuous mode
68d480c4
AD		 3508 */
3509 count = igb_write_uc_addr_list(netdev);
3510 if (count < 0) {
3511 rctl |= E1000_RCTL_UPE;
3512 vmolr |= E1000_VMOLR_ROPE;
3513 }
3514 rctl |= E1000_RCTL_VFE;
28fc06f5 3515 }
68d480c4 3516 wr32(E1000_RCTL, rctl);
28fc06f5 3517
68d480c4
AD		 3518 /*
3519 * In order to support SR-IOV and eventually VMDq it is necessary to set
3520 * the VMOLR to enable the appropriate modes. Without this workaround
3521 * we will have issues with VLAN tag stripping not being done for frames
3522 * that are only arriving because we are the default pool
3523 */
f96a8a0b 3524 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3525 return;
9d5c8243 3526
68d480c4
AD		 3527 vmolr |= rd32(E1000_VMOLR(vfn)) &
3528 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3529 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3530 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3531}
3532
13800469
GR		 3533static void igb_check_wvbr(struct igb_adapter *adapter)
3534{
3535 struct e1000_hw *hw = &adapter->hw;
3536 u32 wvbr = 0;
3537
3538 switch (hw->mac.type) {
3539 case e1000_82576:
3540 case e1000_i350:
3541 if (!(wvbr = rd32(E1000_WVBR)))
3542 return;
3543 break;
3544 default:
3545 break;
3546 }
3547
3548 adapter->wvbr |= wvbr;
3549}
3550
3551#define IGB_STAGGERED_QUEUE_OFFSET 8
3552
3553static void igb_spoof_check(struct igb_adapter *adapter)
3554{
3555 int j;
3556
3557 if (!adapter->wvbr)
3558 return;
3559
3560 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3561 if (adapter->wvbr & (1 << j) ||
3562 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3563 dev_warn(&adapter->pdev->dev,
3564 "Spoof event(s) detected on VF %d\n", j);
3565 adapter->wvbr &=
3566 ~((1 << j) |
3567 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3568 }
3569 }
3570}
3571
9d5c8243
AK		 3572/* Need to wait a few seconds after link up to get diagnostic information from
3573 * the phy */
3574static void igb_update_phy_info(unsigned long data)
3575{
3576 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3577 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3578}
3579
4d6b725e
AD		 3580/**
3581 * igb_has_link - check shared code for link and determine up/down
3582 * @adapter: pointer to driver private info
3583 **/
3145535a 3584bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3585{
3586 struct e1000_hw *hw = &adapter->hw;
3587 bool link_active = false;
3588 s32 ret_val = 0;
3589
3590 /* get_link_status is set on LSC (link status) interrupt or
3591 * rx sequence error interrupt. get_link_status will stay
3592 * false until the e1000_check_for_link establishes link
3593 * for copper adapters ONLY
3594 */
3595 switch (hw->phy.media_type) {
3596 case e1000_media_type_copper:
3597 if (hw->mac.get_link_status) {
3598 ret_val = hw->mac.ops.check_for_link(hw);
3599 link_active = !hw->mac.get_link_status;
3600 } else {
3601 link_active = true;
3602 }
3603 break;
4d6b725e
AD		 3604 case e1000_media_type_internal_serdes:
3605 ret_val = hw->mac.ops.check_for_link(hw);
3606 link_active = hw->mac.serdes_has_link;
3607 break;
3608 default:
3609 case e1000_media_type_unknown:
3610 break;
3611 }
3612
3613 return link_active;
3614}
3615
563988dc
SA		 3616static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3617{
3618 bool ret = false;
3619 u32 ctrl_ext, thstat;
3620
f96a8a0b 3621 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3622 if (hw->mac.type == e1000_i350) {
3623 thstat = rd32(E1000_THSTAT);
3624 ctrl_ext = rd32(E1000_CTRL_EXT);
3625
3626 if ((hw->phy.media_type == e1000_media_type_copper) &&
3627 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3628 ret = !!(thstat & event);
3629 }
3630 }
3631
3632 return ret;
3633}
3634
9d5c8243
AK		 3635/**
3636 * igb_watchdog - Timer Call-back
3637 * @data: pointer to adapter cast into an unsigned long
3638 **/
3639static void igb_watchdog(unsigned long data)
3640{
3641 struct igb_adapter *adapter = (struct igb_adapter *)data;
3642 /* Do the rest outside of interrupt context */
3643 schedule_work(&adapter->watchdog_task);
3644}
3645
3646static void igb_watchdog_task(struct work_struct *work)
3647{
3648 struct igb_adapter *adapter = container_of(work,
559e9c49
AD		 3649 struct igb_adapter,
3650 watchdog_task);
9d5c8243 3651 struct e1000_hw *hw = &adapter->hw;
9d5c8243 3652 struct net_device *netdev = adapter->netdev;
563988dc 3653 u32 link;
7a6ea550 3654 int i;
9d5c8243 3655
4d6b725e 3656 link = igb_has_link(adapter);
9d5c8243 3657 if (link) {
749ab2cd
YZ		 3658 /* Cancel scheduled suspend requests. */
3659 pm_runtime_resume(netdev->dev.parent);
3660
9d5c8243
AK		 3661 if (!netif_carrier_ok(netdev)) {
3662 u32 ctrl;
330a6d6a
AD		 3663 hw->mac.ops.get_speed_and_duplex(hw,
3664 &adapter->link_speed,
3665 &adapter->link_duplex);
9d5c8243
AK		 3666
3667 ctrl = rd32(E1000_CTRL);
527d47c1 3668 /* Links status message must follow this format */
876d2d6f
JK		 3669 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3670 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3671 netdev->name,
3672 adapter->link_speed,
3673 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3674 "Full" : "Half",
3675 (ctrl & E1000_CTRL_TFCE) &&
3676 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3677 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3678 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3679
563988dc 3680 /* check for thermal sensor event */
876d2d6f
JK		 3681 if (igb_thermal_sensor_event(hw,
3682 E1000_THSTAT_LINK_THROTTLE)) {
3683 netdev_info(netdev, "The network adapter link "
3684 "speed was downshifted because it "
3685 "overheated\n");
7ef5ed1c 3686 }
563988dc 3687
d07f3e37 3688 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3689 adapter->tx_timeout_factor = 1;
3690 switch (adapter->link_speed) {
3691 case SPEED_10:
9d5c8243
AK		 3692 adapter->tx_timeout_factor = 14;
3693 break;
3694 case SPEED_100:
9d5c8243
AK		 3695 /* maybe add some timeout factor ? */
3696 break;
3697 }
3698
3699 netif_carrier_on(netdev);
9d5c8243 3700
4ae196df 3701 igb_ping_all_vfs(adapter);
17dc566c 3702 igb_check_vf_rate_limit(adapter);
4ae196df 3703
4b1a9877 3704 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3705 if (!test_bit(__IGB_DOWN, &adapter->state))
3706 mod_timer(&adapter->phy_info_timer,
3707 round_jiffies(jiffies + 2 * HZ));
3708 }
3709 } else {
3710 if (netif_carrier_ok(netdev)) {
3711 adapter->link_speed = 0;
3712 adapter->link_duplex = 0;
563988dc
SA		 3713
3714 /* check for thermal sensor event */
876d2d6f
JK		 3715 if (igb_thermal_sensor_event(hw,
3716 E1000_THSTAT_PWR_DOWN)) {
3717 netdev_err(netdev, "The network adapter was "
3718 "stopped because it overheated\n");
7ef5ed1c 3719 }
563988dc 3720
527d47c1
AD		 3721 /* Links status message must follow this format */
3722 printk(KERN_INFO "igb: %s NIC Link is Down\n",
3723 netdev->name);
9d5c8243 3724 netif_carrier_off(netdev);
4b1a9877 3725
4ae196df
AD		 3726 igb_ping_all_vfs(adapter);
3727
4b1a9877 3728 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3729 if (!test_bit(__IGB_DOWN, &adapter->state))
3730 mod_timer(&adapter->phy_info_timer,
3731 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 3732
3733 pm_schedule_suspend(netdev->dev.parent,
3734 MSEC_PER_SEC * 5);
9d5c8243
AK		 3735 }
3736 }
3737
12dcd86b
ED		 3738 spin_lock(&adapter->stats64_lock);
3739 igb_update_stats(adapter, &adapter->stats64);
3740 spin_unlock(&adapter->stats64_lock);
9d5c8243 3741
dbabb065 3742 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3743 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 3744 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 3745 /* We've lost link, so the controller stops DMA,
3746 * but we've got queued Tx work that's never going
3747 * to get done, so reset controller to flush Tx.
3748 * (Do the reset outside of interrupt context). */
dbabb065
AD		 3749 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3750 adapter->tx_timeout_count++;
3751 schedule_work(&adapter->reset_task);
3752 /* return immediately since reset is imminent */
3753 return;
3754 }
9d5c8243 3755 }
9d5c8243 3756
dbabb065 3757 /* Force detection of hung controller every watchdog period */
6d095fa8 3758 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 3759 }
f7ba205e 3760
9d5c8243 3761 /* Cause software interrupt to ensure rx ring is cleaned */
7a6ea550 3762 if (adapter->msix_entries) {
047e0030 3763 u32 eics = 0;
0d1ae7f4
AD		 3764 for (i = 0; i < adapter->num_q_vectors; i++)
3765 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 3766 wr32(E1000_EICS, eics);
3767 } else {
3768 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3769 }
9d5c8243 3770
13800469
GR		 3771 igb_spoof_check(adapter);
3772
9d5c8243
AK		 3773 /* Reset the timer */
3774 if (!test_bit(__IGB_DOWN, &adapter->state))
3775 mod_timer(&adapter->watchdog_timer,
3776 round_jiffies(jiffies + 2 * HZ));
3777}
3778
3779enum latency_range {
3780 lowest_latency = 0,
3781 low_latency = 1,
3782 bulk_latency = 2,
3783 latency_invalid = 255
3784};
3785
6eb5a7f1
AD		 3786/**
3787 * igb_update_ring_itr - update the dynamic ITR value based on packet size
3788 *
3789 * Stores a new ITR value based on strictly on packet size. This
3790 * algorithm is less sophisticated than that used in igb_update_itr,
3791 * due to the difficulty of synchronizing statistics across multiple
eef35c2d 3792 * receive rings. The divisors and thresholds used by this function
6eb5a7f1
AD		 3793 * were determined based on theoretical maximum wire speed and testing
3794 * data, in order to minimize response time while increasing bulk
3795 * throughput.
3796 * This functionality is controlled by the InterruptThrottleRate module
3797 * parameter (see igb_param.c)
3798 * NOTE: This function is called only when operating in a multiqueue
3799 * receive environment.
047e0030 3800 * @q_vector: pointer to q_vector
6eb5a7f1 3801 **/
047e0030 3802static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 3803{
047e0030 3804 int new_val = q_vector->itr_val;
6eb5a7f1 3805 int avg_wire_size = 0;
047e0030 3806 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 3807 unsigned int packets;
9d5c8243 3808
6eb5a7f1
AD		 3809 /* For non-gigabit speeds, just fix the interrupt rate at 4000
3810 * ints/sec - ITR timer value of 120 ticks.
3811 */
3812 if (adapter->link_speed != SPEED_1000) {
0ba82994 3813 new_val = IGB_4K_ITR;
6eb5a7f1 3814 goto set_itr_val;
9d5c8243 3815 }
047e0030 3816
0ba82994
AD		 3817 packets = q_vector->rx.total_packets;
3818 if (packets)
3819 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 3820
0ba82994
AD		 3821 packets = q_vector->tx.total_packets;
3822 if (packets)
3823 avg_wire_size = max_t(u32, avg_wire_size,
3824 q_vector->tx.total_bytes / packets);
047e0030
AD		 3825
3826 /* if avg_wire_size isn't set no work was done */
3827 if (!avg_wire_size)
3828 goto clear_counts;
9d5c8243 3829
6eb5a7f1
AD		 3830 /* Add 24 bytes to size to account for CRC, preamble, and gap */
3831 avg_wire_size += 24;
3832
3833 /* Don't starve jumbo frames */
3834 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 3835
6eb5a7f1
AD		 3836 /* Give a little boost to mid-size frames */
3837 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3838 new_val = avg_wire_size / 3;
3839 else
3840 new_val = avg_wire_size / 2;
9d5c8243 3841
0ba82994
AD		 3842 /* conservative mode (itr 3) eliminates the lowest_latency setting */
3843 if (new_val < IGB_20K_ITR &&
3844 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3845 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3846 new_val = IGB_20K_ITR;
abe1c363 3847
6eb5a7f1 3848set_itr_val:
047e0030
AD		 3849 if (new_val != q_vector->itr_val) {
3850 q_vector->itr_val = new_val;
3851 q_vector->set_itr = 1;
9d5c8243 3852 }
6eb5a7f1 3853clear_counts:
0ba82994
AD		 3854 q_vector->rx.total_bytes = 0;
3855 q_vector->rx.total_packets = 0;
3856 q_vector->tx.total_bytes = 0;
3857 q_vector->tx.total_packets = 0;
9d5c8243
AK		 3858}
3859
3860/**
3861 * igb_update_itr - update the dynamic ITR value based on statistics
3862 * Stores a new ITR value based on packets and byte
3863 * counts during the last interrupt. The advantage of per interrupt
3864 * computation is faster updates and more accurate ITR for the current
3865 * traffic pattern. Constants in this function were computed
3866 * based on theoretical maximum wire speed and thresholds were set based
3867 * on testing data as well as attempting to minimize response time
3868 * while increasing bulk throughput.
3869 * this functionality is controlled by the InterruptThrottleRate module
3870 * parameter (see igb_param.c)
3871 * NOTE: These calculations are only valid when operating in a single-
3872 * queue environment.
0ba82994
AD		 3873 * @q_vector: pointer to q_vector
3874 * @ring_container: ring info to update the itr for
9d5c8243 3875 **/
0ba82994
AD		 3876static void igb_update_itr(struct igb_q_vector *q_vector,
3877 struct igb_ring_container *ring_container)
9d5c8243 3878{
0ba82994
AD		 3879 unsigned int packets = ring_container->total_packets;
3880 unsigned int bytes = ring_container->total_bytes;
3881 u8 itrval = ring_container->itr;
9d5c8243 3882
0ba82994 3883 /* no packets, exit with status unchanged */
9d5c8243 3884 if (packets == 0)
0ba82994 3885 return;
9d5c8243 3886
0ba82994 3887 switch (itrval) {
9d5c8243
AK		 3888 case lowest_latency:
3889 /* handle TSO and jumbo frames */
3890 if (bytes/packets > 8000)
0ba82994 3891 itrval = bulk_latency;
9d5c8243 3892 else if ((packets < 5) && (bytes > 512))
0ba82994 3893 itrval = low_latency;
9d5c8243
AK		 3894 break;
3895 case low_latency: /* 50 usec aka 20000 ints/s */
3896 if (bytes > 10000) {
3897 /* this if handles the TSO accounting */
3898 if (bytes/packets > 8000) {
0ba82994 3899 itrval = bulk_latency;
9d5c8243 3900 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 3901 itrval = bulk_latency;
9d5c8243 3902 } else if ((packets > 35)) {
0ba82994 3903 itrval = lowest_latency;
9d5c8243
AK		 3904 }
3905 } else if (bytes/packets > 2000) {
0ba82994 3906 itrval = bulk_latency;
9d5c8243 3907 } else if (packets <= 2 && bytes < 512) {
0ba82994 3908 itrval = lowest_latency;
9d5c8243
AK		 3909 }
3910 break;
3911 case bulk_latency: /* 250 usec aka 4000 ints/s */
3912 if (bytes > 25000) {
3913 if (packets > 35)
0ba82994 3914 itrval = low_latency;
1e5c3d21 3915 } else if (bytes < 1500) {
0ba82994 3916 itrval = low_latency;
9d5c8243
AK		 3917 }
3918 break;
3919 }
3920
0ba82994
AD		 3921 /* clear work counters since we have the values we need */
3922 ring_container->total_bytes = 0;
3923 ring_container->total_packets = 0;
3924
3925 /* write updated itr to ring container */
3926 ring_container->itr = itrval;
9d5c8243
AK		 3927}
3928
0ba82994 3929static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 3930{
0ba82994 3931 struct igb_adapter *adapter = q_vector->adapter;
047e0030 3932 u32 new_itr = q_vector->itr_val;
0ba82994 3933 u8 current_itr = 0;
9d5c8243
AK		 3934
3935 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3936 if (adapter->link_speed != SPEED_1000) {
3937 current_itr = 0;
0ba82994 3938 new_itr = IGB_4K_ITR;
9d5c8243
AK		 3939 goto set_itr_now;
3940 }
3941
0ba82994
AD		 3942 igb_update_itr(q_vector, &q_vector->tx);
3943 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 3944
0ba82994 3945 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 3946
6eb5a7f1 3947 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 3948 if (current_itr == lowest_latency &&
3949 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3950 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 3951 current_itr = low_latency;
3952
9d5c8243
AK		 3953 switch (current_itr) {
3954 /* counts and packets in update_itr are dependent on these numbers */
3955 case lowest_latency:
0ba82994 3956 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 3957 break;
3958 case low_latency:
0ba82994 3959 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 3960 break;
3961 case bulk_latency:
0ba82994 3962 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 3963 break;
3964 default:
3965 break;
3966 }
3967
3968set_itr_now:
047e0030 3969 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 3970 /* this attempts to bias the interrupt rate towards Bulk
3971 * by adding intermediate steps when interrupt rate is
3972 * increasing */
047e0030
AD		 3973 new_itr = new_itr > q_vector->itr_val ?
3974 max((new_itr * q_vector->itr_val) /
3975 (new_itr + (q_vector->itr_val >> 2)),
0ba82994 3976 new_itr) :
9d5c8243
AK		 3977 new_itr;
3978 /* Don't write the value here; it resets the adapter's
3979 * internal timer, and causes us to delay far longer than
3980 * we should between interrupts. Instead, we write the ITR
3981 * value at the beginning of the next interrupt so the timing
3982 * ends up being correct.
3983 */
047e0030
AD		 3984 q_vector->itr_val = new_itr;
3985 q_vector->set_itr = 1;
9d5c8243 3986 }
9d5c8243
AK		 3987}
3988
c50b52a0
SH		 3989static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3990 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 3991{
3992 struct e1000_adv_tx_context_desc *context_desc;
3993 u16 i = tx_ring->next_to_use;
3994
3995 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3996
3997 i++;
3998 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3999
4000 /* set bits to identify this as an advanced context descriptor */
4001 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4002
4003 /* For 82575, context index must be unique per ring. */
866cff06 4004 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4005 mss_l4len_idx |= tx_ring->reg_idx << 4;
4006
4007 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4008 context_desc->seqnum_seed = 0;
4009 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4010 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4011}
4012
7af40ad9
AD		 4013static int igb_tso(struct igb_ring *tx_ring,
4014 struct igb_tx_buffer *first,
4015 u8 *hdr_len)
9d5c8243 4016{
7af40ad9 4017 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4018 u32 vlan_macip_lens, type_tucmd;
4019 u32 mss_l4len_idx, l4len;
4020
ed6aa105
AD		 4021 if (skb->ip_summed != CHECKSUM_PARTIAL)
4022 return 0;
4023
7d13a7d0
AD		 4024 if (!skb_is_gso(skb))
4025 return 0;
9d5c8243
AK		 4026
4027 if (skb_header_cloned(skb)) {
7af40ad9 4028 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4029 if (err)
4030 return err;
4031 }
4032
7d13a7d0
AD		 4033 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4034 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4035
7af40ad9 4036 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4037 struct iphdr *iph = ip_hdr(skb);
4038 iph->tot_len = 0;
4039 iph->check = 0;
4040 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4041 iph->daddr, 0,
4042 IPPROTO_TCP,
4043 0);
7d13a7d0 4044 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4045 first->tx_flags |= IGB_TX_FLAGS_TSO |
4046 IGB_TX_FLAGS_CSUM |
4047 IGB_TX_FLAGS_IPV4;
8e1e8a47 4048 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4049 ipv6_hdr(skb)->payload_len = 0;
4050 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4051 &ipv6_hdr(skb)->daddr,
4052 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4053 first->tx_flags |= IGB_TX_FLAGS_TSO |
4054 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4055 }
4056
7af40ad9 4057 /* compute header lengths */
7d13a7d0
AD		 4058 l4len = tcp_hdrlen(skb);
4059 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4060
7af40ad9
AD		 4061 /* update gso size and bytecount with header size */
4062 first->gso_segs = skb_shinfo(skb)->gso_segs;
4063 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4064
9d5c8243 4065 /* MSS L4LEN IDX */
7d13a7d0
AD		 4066 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4067 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4068
7d13a7d0
AD		 4069 /* VLAN MACLEN IPLEN */
4070 vlan_macip_lens = skb_network_header_len(skb);
4071 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4072 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4073
7d13a7d0 4074 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4075
7d13a7d0 4076 return 1;
9d5c8243
AK		 4077}
4078
7af40ad9 4079static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4080{
7af40ad9 4081 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4082 u32 vlan_macip_lens = 0;
4083 u32 mss_l4len_idx = 0;
4084 u32 type_tucmd = 0;
9d5c8243 4085
7d13a7d0 4086 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4087 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4088 return;
7d13a7d0
AD		 4089 } else {
4090 u8 l4_hdr = 0;
7af40ad9 4091 switch (first->protocol) {
7d13a7d0
AD		 4092 case __constant_htons(ETH_P_IP):
4093 vlan_macip_lens |= skb_network_header_len(skb);
4094 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4095 l4_hdr = ip_hdr(skb)->protocol;
4096 break;
4097 case __constant_htons(ETH_P_IPV6):
4098 vlan_macip_lens |= skb_network_header_len(skb);
4099 l4_hdr = ipv6_hdr(skb)->nexthdr;
4100 break;
4101 default:
4102 if (unlikely(net_ratelimit())) {
4103 dev_warn(tx_ring->dev,
4104 "partial checksum but proto=%x!\n",
7af40ad9 4105 first->protocol);
fa4a7ef3 4106 }
7d13a7d0
AD		 4107 break;
4108 }
fa4a7ef3 4109
7d13a7d0
AD		 4110 switch (l4_hdr) {
4111 case IPPROTO_TCP:
4112 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4113 mss_l4len_idx = tcp_hdrlen(skb) <<
4114 E1000_ADVTXD_L4LEN_SHIFT;
4115 break;
4116 case IPPROTO_SCTP:
4117 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4118 mss_l4len_idx = sizeof(struct sctphdr) <<
4119 E1000_ADVTXD_L4LEN_SHIFT;
4120 break;
4121 case IPPROTO_UDP:
4122 mss_l4len_idx = sizeof(struct udphdr) <<
4123 E1000_ADVTXD_L4LEN_SHIFT;
4124 break;
4125 default:
4126 if (unlikely(net_ratelimit())) {
4127 dev_warn(tx_ring->dev,
4128 "partial checksum but l4 proto=%x!\n",
4129 l4_hdr);
44b0cda3 4130 }
7d13a7d0 4131 break;
9d5c8243 4132 }
7af40ad9
AD		 4133
4134 /* update TX checksum flag */
4135 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4136 }
9d5c8243 4137
7d13a7d0 4138 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4139 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4140
7d13a7d0 4141 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4142}
4143
1d9daf45
AD		 4144#define IGB_SET_FLAG(_input, _flag, _result) \
4145 ((_flag <= _result) ? \
4146 ((u32)(_input & _flag) * (_result / _flag)) : \
4147 ((u32)(_input & _flag) / (_flag / _result)))
4148
4149static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4150{
4151 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4152 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4153 E1000_ADVTXD_DCMD_DEXT |
4154 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4155
4156 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4157 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4158 (E1000_ADVTXD_DCMD_VLE));
4159
4160 /* set segmentation bits for TSO */
4161 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4162 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4163
4164 /* set timestamp bit if present */
1d9daf45
AD		 4165 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4166 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4167
1d9daf45
AD		 4168 /* insert frame checksum */
4169 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4170
4171 return cmd_type;
4172}
4173
7af40ad9
AD		 4174static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4175 union e1000_adv_tx_desc *tx_desc,
4176 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4177{
4178 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4179
1d9daf45
AD		 4180 /* 82575 requires a unique index per ring */
4181 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4182 olinfo_status |= tx_ring->reg_idx << 4;
4183
4184 /* insert L4 checksum */
1d9daf45
AD		 4185 olinfo_status |= IGB_SET_FLAG(tx_flags,
4186 IGB_TX_FLAGS_CSUM,
4187 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4188
1d9daf45
AD		 4189 /* insert IPv4 checksum */
4190 olinfo_status |= IGB_SET_FLAG(tx_flags,
4191 IGB_TX_FLAGS_IPV4,
4192 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4193
7af40ad9 4194 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4195}
4196
ebe42d16
AD		 4197/*
4198 * The largest size we can write to the descriptor is 65535. In order to
4199 * maintain a power of two alignment we have to limit ourselves to 32K.
4200 */
4201#define IGB_MAX_TXD_PWR 15
7af40ad9 4202#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
9d5c8243 4203
7af40ad9
AD		 4204static void igb_tx_map(struct igb_ring *tx_ring,
4205 struct igb_tx_buffer *first,
ebe42d16 4206 const u8 hdr_len)
9d5c8243 4207{
7af40ad9 4208 struct sk_buff *skb = first->skb;
c9f14bf3 4209 struct igb_tx_buffer *tx_buffer;
ebe42d16 4210 union e1000_adv_tx_desc *tx_desc;
80d0759e 4211 struct skb_frag_struct *frag;
ebe42d16 4212 dma_addr_t dma;
80d0759e 4213 unsigned int data_len, size;
7af40ad9 4214 u32 tx_flags = first->tx_flags;
1d9daf45 4215 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4216 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4217
4218 tx_desc = IGB_TX_DESC(tx_ring, i);
4219
80d0759e
AD		 4220 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4221
4222 size = skb_headlen(skb);
4223 data_len = skb->data_len;
ebe42d16
AD		 4224
4225 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4226
80d0759e
AD		 4227 tx_buffer = first;
4228
4229 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4230 if (dma_mapping_error(tx_ring->dev, dma))
4231 goto dma_error;
4232
4233 /* record length, and DMA address */
4234 dma_unmap_len_set(tx_buffer, len, size);
4235 dma_unmap_addr_set(tx_buffer, dma, dma);
4236
4237 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4238
ebe42d16
AD		 4239 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4240 tx_desc->read.cmd_type_len =
1d9daf45 4241 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4242
4243 i++;
4244 tx_desc++;
4245 if (i == tx_ring->count) {
4246 tx_desc = IGB_TX_DESC(tx_ring, 0);
4247 i = 0;
4248 }
80d0759e 4249 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4250
4251 dma += IGB_MAX_DATA_PER_TXD;
4252 size -= IGB_MAX_DATA_PER_TXD;
4253
ebe42d16
AD		 4254 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4255 }
4256
4257 if (likely(!data_len))
4258 break;
2bbfebe2 4259
1d9daf45 4260 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4261
65689fef 4262 i++;
ebe42d16
AD		 4263 tx_desc++;
4264 if (i == tx_ring->count) {
4265 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4266 i = 0;
ebe42d16 4267 }
80d0759e 4268 tx_desc->read.olinfo_status = 0;
65689fef 4269
9e903e08 4270 size = skb_frag_size(frag);
ebe42d16
AD		 4271 data_len -= size;
4272
4273 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4274 size, DMA_TO_DEVICE);
6366ad33 4275
c9f14bf3 4276 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4277 }
4278
ebe42d16 4279 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4280 cmd_type |= size | IGB_TXD_DCMD;
4281 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4282
80d0759e
AD		 4283 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4284
8542db05
AD		 4285 /* set the timestamp */
4286 first->time_stamp = jiffies;
4287
ebe42d16
AD		 4288 /*
4289 * Force memory writes to complete before letting h/w know there
4290 * are new descriptors to fetch. (Only applicable for weak-ordered
4291 * memory model archs, such as IA-64).
4292 *
4293 * We also need this memory barrier to make certain all of the
4294 * status bits have been updated before next_to_watch is written.
4295 */
4296 wmb();
4297
8542db05 4298 /* set next_to_watch value indicating a packet is present */
ebe42d16 4299 first->next_to_watch = tx_desc;
9d5c8243 4300
ebe42d16
AD		 4301 i++;
4302 if (i == tx_ring->count)
4303 i = 0;
6366ad33 4304
ebe42d16 4305 tx_ring->next_to_use = i;
6366ad33 4306
ebe42d16 4307 writel(i, tx_ring->tail);
6366ad33 4308
ebe42d16
AD		 4309 /* we need this if more than one processor can write to our tail
4310 * at a time, it syncronizes IO on IA64/Altix systems */
4311 mmiowb();
4312
4313 return;
4314
4315dma_error:
4316 dev_err(tx_ring->dev, "TX DMA map failed\n");
4317
4318 /* clear dma mappings for failed tx_buffer_info map */
4319 for (;;) {
c9f14bf3
AD		 4320 tx_buffer = &tx_ring->tx_buffer_info[i];
4321 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4322 if (tx_buffer == first)
ebe42d16 4323 break;
a77ff709
NN		 4324 if (i == 0)
4325 i = tx_ring->count;
6366ad33 4326 i--;
6366ad33
AD		 4327 }
4328
9d5c8243 4329 tx_ring->next_to_use = i;
9d5c8243
AK		 4330}
4331
6ad4edfc 4332static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4333{
e694e964
AD		 4334 struct net_device *netdev = tx_ring->netdev;
4335
661086df 4336 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4337
9d5c8243
AK		 4338 /* Herbert's original patch had:
4339 * smp_mb__after_netif_stop_queue();
4340 * but since that doesn't exist yet, just open code it. */
4341 smp_mb();
4342
4343 /* We need to check again in a case another CPU has just
4344 * made room available. */
c493ea45 4345 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4346 return -EBUSY;
4347
4348 /* A reprieve! */
661086df 4349 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4350
4351 u64_stats_update_begin(&tx_ring->tx_syncp2);
4352 tx_ring->tx_stats.restart_queue2++;
4353 u64_stats_update_end(&tx_ring->tx_syncp2);
4354
9d5c8243
AK		 4355 return 0;
4356}
4357
6ad4edfc 4358static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4359{
c493ea45 4360 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4361 return 0;
e694e964 4362 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4363}
4364
cd392f5c
AD		 4365netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4366 struct igb_ring *tx_ring)
9d5c8243 4367{
1f6e8178 4368 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
8542db05 4369 struct igb_tx_buffer *first;
ebe42d16 4370 int tso;
91d4ee33 4371 u32 tx_flags = 0;
31f6adbb 4372 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4373 u8 hdr_len = 0;
9d5c8243 4374
9d5c8243
AK		 4375 /* need: 1 descriptor per page,
4376 * + 2 desc gap to keep tail from touching head,
4377 * + 1 desc for skb->data,
4378 * + 1 desc for context descriptor,
4379 * otherwise try next time */
e694e964 4380 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
9d5c8243 4381 /* this is a hard error */
9d5c8243
AK		 4382 return NETDEV_TX_BUSY;
4383 }
33af6bcc 4384
7af40ad9
AD		 4385 /* record the location of the first descriptor for this packet */
4386 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4387 first->skb = skb;
4388 first->bytecount = skb->len;
4389 first->gso_segs = 1;
4390
1f6e8178
MV		 4391 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4392 !(adapter->ptp_tx_skb))) {
2244d07b 4393 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
33af6bcc 4394 tx_flags |= IGB_TX_FLAGS_TSTAMP;
1f6e8178
MV		 4395
4396 adapter->ptp_tx_skb = skb_get(skb);
4397 if (adapter->hw.mac.type == e1000_82576)
4398 schedule_work(&adapter->ptp_tx_work);
33af6bcc 4399 }
9d5c8243 4400
eab6d18d 4401 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4402 tx_flags |= IGB_TX_FLAGS_VLAN;
4403 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4404 }
4405
7af40ad9
AD		 4406 /* record initial flags and protocol */
4407 first->tx_flags = tx_flags;
4408 first->protocol = protocol;
cdfd01fc 4409
7af40ad9
AD		 4410 tso = igb_tso(tx_ring, first, &hdr_len);
4411 if (tso < 0)
7d13a7d0 4412 goto out_drop;
7af40ad9
AD		 4413 else if (!tso)
4414 igb_tx_csum(tx_ring, first);
9d5c8243 4415
7af40ad9 4416 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4417
4418 /* Make sure there is space in the ring for the next send. */
e694e964 4419 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
85ad76b2 4420
9d5c8243 4421 return NETDEV_TX_OK;
7d13a7d0
AD		 4422
4423out_drop:
7af40ad9
AD		 4424 igb_unmap_and_free_tx_resource(tx_ring, first);
4425
7d13a7d0 4426 return NETDEV_TX_OK;
9d5c8243
AK		 4427}
4428
1cc3bd87
AD		 4429static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4430 struct sk_buff *skb)
4431{
4432 unsigned int r_idx = skb->queue_mapping;
4433
4434 if (r_idx >= adapter->num_tx_queues)
4435 r_idx = r_idx % adapter->num_tx_queues;
4436
4437 return adapter->tx_ring[r_idx];
4438}
4439
cd392f5c
AD		 4440static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4441 struct net_device *netdev)
9d5c8243
AK		 4442{
4443 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4444
4445 if (test_bit(__IGB_DOWN, &adapter->state)) {
4446 dev_kfree_skb_any(skb);
4447 return NETDEV_TX_OK;
4448 }
4449
4450 if (skb->len <= 0) {
4451 dev_kfree_skb_any(skb);
4452 return NETDEV_TX_OK;
4453 }
4454
1cc3bd87
AD		 4455 /*
4456 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4457 * in order to meet this minimum size requirement.
4458 */
ea5ceeab
TD		 4459 if (unlikely(skb->len < 17)) {
4460 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4461 return NETDEV_TX_OK;
4462 skb->len = 17;
ea5ceeab 4463 skb_set_tail_pointer(skb, 17);
1cc3bd87 4464 }
9d5c8243 4465
1cc3bd87 4466 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4467}
4468
4469/**
4470 * igb_tx_timeout - Respond to a Tx Hang
4471 * @netdev: network interface device structure
4472 **/
4473static void igb_tx_timeout(struct net_device *netdev)
4474{
4475 struct igb_adapter *adapter = netdev_priv(netdev);
4476 struct e1000_hw *hw = &adapter->hw;
4477
4478 /* Do the reset outside of interrupt context */
4479 adapter->tx_timeout_count++;
f7ba205e 4480
06218a8d 4481 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4482 hw->dev_spec._82575.global_device_reset = true;
4483
9d5c8243 4484 schedule_work(&adapter->reset_task);
265de409
AD		 4485 wr32(E1000_EICS,
4486 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4487}
4488
4489static void igb_reset_task(struct work_struct *work)
4490{
4491 struct igb_adapter *adapter;
4492 adapter = container_of(work, struct igb_adapter, reset_task);
4493
c97ec42a
TI		 4494 igb_dump(adapter);
4495 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4496 igb_reinit_locked(adapter);
4497}
4498
4499/**
12dcd86b 4500 * igb_get_stats64 - Get System Network Statistics
9d5c8243 4501 * @netdev: network interface device structure
12dcd86b 4502 * @stats: rtnl_link_stats64 pointer
9d5c8243 4503 *
9d5c8243 4504 **/
12dcd86b
ED		 4505static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4506 struct rtnl_link_stats64 *stats)
9d5c8243 4507{
12dcd86b
ED		 4508 struct igb_adapter *adapter = netdev_priv(netdev);
4509
4510 spin_lock(&adapter->stats64_lock);
4511 igb_update_stats(adapter, &adapter->stats64);
4512 memcpy(stats, &adapter->stats64, sizeof(*stats));
4513 spin_unlock(&adapter->stats64_lock);
4514
4515 return stats;
9d5c8243
AK		 4516}
4517
4518/**
4519 * igb_change_mtu - Change the Maximum Transfer Unit
4520 * @netdev: network interface device structure
4521 * @new_mtu: new value for maximum frame size
4522 *
4523 * Returns 0 on success, negative on failure
4524 **/
4525static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4526{
4527 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4528 struct pci_dev *pdev = adapter->pdev;
153285f9 4529 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4530
c809d227 4531 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4532 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4533 return -EINVAL;
4534 }
4535
153285f9 4536#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4537 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4538 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4539 return -EINVAL;
4540 }
4541
4542 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4543 msleep(1);
73cd78f1 4544
9d5c8243
AK		 4545 /* igb_down has a dependency on max_frame_size */
4546 adapter->max_frame_size = max_frame;
559e9c49 4547
4c844851
AD		 4548 if (netif_running(netdev))
4549 igb_down(adapter);
9d5c8243 4550
090b1795 4551 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4552 netdev->mtu, new_mtu);
4553 netdev->mtu = new_mtu;
4554
4555 if (netif_running(netdev))
4556 igb_up(adapter);
4557 else
4558 igb_reset(adapter);
4559
4560 clear_bit(__IGB_RESETTING, &adapter->state);
4561
4562 return 0;
4563}
4564
4565/**
4566 * igb_update_stats - Update the board statistics counters
4567 * @adapter: board private structure
4568 **/
4569
12dcd86b
ED		 4570void igb_update_stats(struct igb_adapter *adapter,
4571 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4572{
4573 struct e1000_hw *hw = &adapter->hw;
4574 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4575 u32 reg, mpc;
9d5c8243 4576 u16 phy_tmp;
3f9c0164
AD		 4577 int i;
4578 u64 bytes, packets;
12dcd86b
ED		 4579 unsigned int start;
4580 u64 _bytes, _packets;
9d5c8243
AK		 4581
4582#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4583
4584 /*
4585 * Prevent stats update while adapter is being reset, or if the pci
4586 * connection is down.
4587 */
4588 if (adapter->link_speed == 0)
4589 return;
4590 if (pci_channel_offline(pdev))
4591 return;
4592
3f9c0164
AD		 4593 bytes = 0;
4594 packets = 0;
4595 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4596 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4597 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4598
ae1c07a6
AD		 4599 if (rqdpc) {
4600 ring->rx_stats.drops += rqdpc;
4601 net_stats->rx_fifo_errors += rqdpc;
4602 }
12dcd86b
ED		 4603
4604 do {
4605 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4606 _bytes = ring->rx_stats.bytes;
4607 _packets = ring->rx_stats.packets;
4608 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4609 bytes += _bytes;
4610 packets += _packets;
3f9c0164
AD		 4611 }
4612
128e45eb
AD		 4613 net_stats->rx_bytes = bytes;
4614 net_stats->rx_packets = packets;
3f9c0164
AD		 4615
4616 bytes = 0;
4617 packets = 0;
4618 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4619 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4620 do {
4621 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4622 _bytes = ring->tx_stats.bytes;
4623 _packets = ring->tx_stats.packets;
4624 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4625 bytes += _bytes;
4626 packets += _packets;
3f9c0164 4627 }
128e45eb
AD		 4628 net_stats->tx_bytes = bytes;
4629 net_stats->tx_packets = packets;
3f9c0164
AD		 4630
4631 /* read stats registers */
9d5c8243
AK		 4632 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4633 adapter->stats.gprc += rd32(E1000_GPRC);
4634 adapter->stats.gorc += rd32(E1000_GORCL);
4635 rd32(E1000_GORCH); /* clear GORCL */
4636 adapter->stats.bprc += rd32(E1000_BPRC);
4637 adapter->stats.mprc += rd32(E1000_MPRC);
4638 adapter->stats.roc += rd32(E1000_ROC);
4639
4640 adapter->stats.prc64 += rd32(E1000_PRC64);
4641 adapter->stats.prc127 += rd32(E1000_PRC127);
4642 adapter->stats.prc255 += rd32(E1000_PRC255);
4643 adapter->stats.prc511 += rd32(E1000_PRC511);
4644 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4645 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4646 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4647 adapter->stats.sec += rd32(E1000_SEC);
4648
fa3d9a6d
MW		 4649 mpc = rd32(E1000_MPC);
4650 adapter->stats.mpc += mpc;
4651 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4652 adapter->stats.scc += rd32(E1000_SCC);
4653 adapter->stats.ecol += rd32(E1000_ECOL);
4654 adapter->stats.mcc += rd32(E1000_MCC);
4655 adapter->stats.latecol += rd32(E1000_LATECOL);
4656 adapter->stats.dc += rd32(E1000_DC);
4657 adapter->stats.rlec += rd32(E1000_RLEC);
4658 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4659 adapter->stats.xontxc += rd32(E1000_XONTXC);
4660 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4661 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4662 adapter->stats.fcruc += rd32(E1000_FCRUC);
4663 adapter->stats.gptc += rd32(E1000_GPTC);
4664 adapter->stats.gotc += rd32(E1000_GOTCL);
4665 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4666 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4667 adapter->stats.ruc += rd32(E1000_RUC);
4668 adapter->stats.rfc += rd32(E1000_RFC);
4669 adapter->stats.rjc += rd32(E1000_RJC);
4670 adapter->stats.tor += rd32(E1000_TORH);
4671 adapter->stats.tot += rd32(E1000_TOTH);
4672 adapter->stats.tpr += rd32(E1000_TPR);
4673
4674 adapter->stats.ptc64 += rd32(E1000_PTC64);
4675 adapter->stats.ptc127 += rd32(E1000_PTC127);
4676 adapter->stats.ptc255 += rd32(E1000_PTC255);
4677 adapter->stats.ptc511 += rd32(E1000_PTC511);
4678 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4679 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4680
4681 adapter->stats.mptc += rd32(E1000_MPTC);
4682 adapter->stats.bptc += rd32(E1000_BPTC);
4683
2d0b0f69
NN		 4684 adapter->stats.tpt += rd32(E1000_TPT);
4685 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4686
4687 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4688 /* read internal phy specific stats */
4689 reg = rd32(E1000_CTRL_EXT);
4690 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4691 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4692
4693 /* this stat has invalid values on i210/i211 */
4694 if ((hw->mac.type != e1000_i210) &&
4695 (hw->mac.type != e1000_i211))
4696 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4697 }
4698
9d5c8243
AK		 4699 adapter->stats.tsctc += rd32(E1000_TSCTC);
4700 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4701
4702 adapter->stats.iac += rd32(E1000_IAC);
4703 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4704 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4705 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4706 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4707 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4708 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4709 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4710 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4711
4712 /* Fill out the OS statistics structure */
128e45eb
AD		 4713 net_stats->multicast = adapter->stats.mprc;
4714 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 4715
4716 /* Rx Errors */
4717
4718 /* RLEC on some newer hardware can be incorrect so build
8c0ab70a 4719 * our own version based on RUC and ROC */
128e45eb 4720 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 4721 adapter->stats.crcerrs + adapter->stats.algnerrc +
4722 adapter->stats.ruc + adapter->stats.roc +
4723 adapter->stats.cexterr;
128e45eb
AD		 4724 net_stats->rx_length_errors = adapter->stats.ruc +
4725 adapter->stats.roc;
4726 net_stats->rx_crc_errors = adapter->stats.crcerrs;
4727 net_stats->rx_frame_errors = adapter->stats.algnerrc;
4728 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 4729
4730 /* Tx Errors */
128e45eb
AD		 4731 net_stats->tx_errors = adapter->stats.ecol +
4732 adapter->stats.latecol;
4733 net_stats->tx_aborted_errors = adapter->stats.ecol;
4734 net_stats->tx_window_errors = adapter->stats.latecol;
4735 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 4736
4737 /* Tx Dropped needs to be maintained elsewhere */
4738
4739 /* Phy Stats */
4740 if (hw->phy.media_type == e1000_media_type_copper) {
4741 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 4742 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 4743 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4744 adapter->phy_stats.idle_errors += phy_tmp;
4745 }
4746 }
4747
4748 /* Management Stats */
4749 adapter->stats.mgptc += rd32(E1000_MGTPTC);
4750 adapter->stats.mgprc += rd32(E1000_MGTPRC);
4751 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 4752
4753 /* OS2BMC Stats */
4754 reg = rd32(E1000_MANC);
4755 if (reg & E1000_MANC_EN_BMC2OS) {
4756 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4757 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4758 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4759 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4760 }
9d5c8243
AK		 4761}
4762
9d5c8243
AK		 4763static irqreturn_t igb_msix_other(int irq, void *data)
4764{
047e0030 4765 struct igb_adapter *adapter = data;
9d5c8243 4766 struct e1000_hw *hw = &adapter->hw;
844290e5 4767 u32 icr = rd32(E1000_ICR);
844290e5 4768 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 4769
7f081d40
AD		 4770 if (icr & E1000_ICR_DRSTA)
4771 schedule_work(&adapter->reset_task);
4772
047e0030 4773 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 4774 /* HW is reporting DMA is out of sync */
4775 adapter->stats.doosync++;
13800469
GR		 4776 /* The DMA Out of Sync is also indication of a spoof event
4777 * in IOV mode. Check the Wrong VM Behavior register to
4778 * see if it is really a spoof event. */
4779 igb_check_wvbr(adapter);
dda0e083 4780 }
eebbbdba 4781
4ae196df
AD		 4782 /* Check for a mailbox event */
4783 if (icr & E1000_ICR_VMMB)
4784 igb_msg_task(adapter);
4785
4786 if (icr & E1000_ICR_LSC) {
4787 hw->mac.get_link_status = 1;
4788 /* guard against interrupt when we're going down */
4789 if (!test_bit(__IGB_DOWN, &adapter->state))
4790 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4791 }
4792
1f6e8178
MV		 4793 if (icr & E1000_ICR_TS) {
4794 u32 tsicr = rd32(E1000_TSICR);
4795
4796 if (tsicr & E1000_TSICR_TXTS) {
4797 /* acknowledge the interrupt */
4798 wr32(E1000_TSICR, E1000_TSICR_TXTS);
4799 /* retrieve hardware timestamp */
4800 schedule_work(&adapter->ptp_tx_work);
4801 }
4802 }
1f6e8178 4803
844290e5 4804 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 4805
4806 return IRQ_HANDLED;
4807}
4808
047e0030 4809static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 4810{
26b39276 4811 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4812 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 4813
047e0030
AD		 4814 if (!q_vector->set_itr)
4815 return;
73cd78f1 4816
047e0030
AD		 4817 if (!itr_val)
4818 itr_val = 0x4;
661086df 4819
26b39276
AD		 4820 if (adapter->hw.mac.type == e1000_82575)
4821 itr_val |= itr_val << 16;
661086df 4822 else
0ba82994 4823 itr_val |= E1000_EITR_CNT_IGNR;
661086df 4824
047e0030
AD		 4825 writel(itr_val, q_vector->itr_register);
4826 q_vector->set_itr = 0;
6eb5a7f1
AD		 4827}
4828
047e0030 4829static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 4830{
047e0030 4831 struct igb_q_vector *q_vector = data;
9d5c8243 4832
047e0030
AD		 4833 /* Write the ITR value calculated from the previous interrupt. */
4834 igb_write_itr(q_vector);
9d5c8243 4835
047e0030 4836 napi_schedule(&q_vector->napi);
844290e5 4837
047e0030 4838 return IRQ_HANDLED;
fe4506b6
JC		 4839}
4840
421e02f0 4841#ifdef CONFIG_IGB_DCA
6a05004a
AD		 4842static void igb_update_tx_dca(struct igb_adapter *adapter,
4843 struct igb_ring *tx_ring,
4844 int cpu)
4845{
4846 struct e1000_hw *hw = &adapter->hw;
4847 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4848
4849 if (hw->mac.type != e1000_82575)
4850 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4851
4852 /*
4853 * We can enable relaxed ordering for reads, but not writes when
4854 * DCA is enabled. This is due to a known issue in some chipsets
4855 * which will cause the DCA tag to be cleared.
4856 */
4857 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4858 E1000_DCA_TXCTRL_DATA_RRO_EN |
4859 E1000_DCA_TXCTRL_DESC_DCA_EN;
4860
4861 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4862}
4863
4864static void igb_update_rx_dca(struct igb_adapter *adapter,
4865 struct igb_ring *rx_ring,
4866 int cpu)
4867{
4868 struct e1000_hw *hw = &adapter->hw;
4869 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4870
4871 if (hw->mac.type != e1000_82575)
4872 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4873
4874 /*
4875 * We can enable relaxed ordering for reads, but not writes when
4876 * DCA is enabled. This is due to a known issue in some chipsets
4877 * which will cause the DCA tag to be cleared.
4878 */
4879 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4880 E1000_DCA_RXCTRL_DESC_DCA_EN;
4881
4882 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4883}
4884
047e0030 4885static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 4886{
047e0030 4887 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 4888 int cpu = get_cpu();
fe4506b6 4889
047e0030
AD		 4890 if (q_vector->cpu == cpu)
4891 goto out_no_update;
4892
6a05004a
AD		 4893 if (q_vector->tx.ring)
4894 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4895
4896 if (q_vector->rx.ring)
4897 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4898
047e0030
AD		 4899 q_vector->cpu = cpu;
4900out_no_update:
fe4506b6
JC		 4901 put_cpu();
4902}
4903
4904static void igb_setup_dca(struct igb_adapter *adapter)
4905{
7e0e99ef 4906 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 4907 int i;
4908
7dfc16fa 4909 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 4910 return;
4911
7e0e99ef
AD		 4912 /* Always use CB2 mode, difference is masked in the CB driver. */
4913 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4914
047e0030 4915 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 4916 adapter->q_vector[i]->cpu = -1;
4917 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 4918 }
4919}
4920
4921static int __igb_notify_dca(struct device *dev, void *data)
4922{
4923 struct net_device *netdev = dev_get_drvdata(dev);
4924 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4925 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 4926 struct e1000_hw *hw = &adapter->hw;
4927 unsigned long event = *(unsigned long *)data;
4928
4929 switch (event) {
4930 case DCA_PROVIDER_ADD:
4931 /* if already enabled, don't do it again */
7dfc16fa 4932 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 4933 break;
fe4506b6 4934 if (dca_add_requester(dev) == 0) {
bbd98fe4 4935 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 4936 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 4937 igb_setup_dca(adapter);
4938 break;
4939 }
4940 /* Fall Through since DCA is disabled. */
4941 case DCA_PROVIDER_REMOVE:
7dfc16fa 4942 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 4943 /* without this a class_device is left
047e0030 4944 * hanging around in the sysfs model */
fe4506b6 4945 dca_remove_requester(dev);
090b1795 4946 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 4947 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 4948 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 4949 }
4950 break;
4951 }
bbd98fe4 4952
fe4506b6 4953 return 0;
9d5c8243
AK		 4954}
4955
fe4506b6
JC		 4956static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4957 void *p)
4958{
4959 int ret_val;
4960
4961 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4962 __igb_notify_dca);
4963
4964 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4965}
421e02f0 4966#endif /* CONFIG_IGB_DCA */
9d5c8243 4967
0224d663
GR		 4968#ifdef CONFIG_PCI_IOV
4969static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4970{
4971 unsigned char mac_addr[ETH_ALEN];
0224d663 4972
7efd26d0 4973 eth_random_addr(mac_addr);
0224d663
GR		 4974 igb_set_vf_mac(adapter, vf, mac_addr);
4975
f557147c 4976 return 0;
0224d663
GR		 4977}
4978
f557147c 4979static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
0224d663 4980{
0224d663 4981 struct pci_dev *pdev = adapter->pdev;
f557147c
SA		 4982 struct pci_dev *vfdev;
4983 int dev_id;
0224d663
GR		 4984
4985 switch (adapter->hw.mac.type) {
4986 case e1000_82576:
f557147c 4987 dev_id = IGB_82576_VF_DEV_ID;
0224d663
GR		 4988 break;
4989 case e1000_i350:
f557147c 4990 dev_id = IGB_I350_VF_DEV_ID;
0224d663
GR		 4991 break;
4992 default:
f557147c 4993 return false;
0224d663
GR		 4994 }
4995
f557147c
SA		 4996 /* loop through all the VFs to see if we own any that are assigned */
4997 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
4998 while (vfdev) {
4999 /* if we don't own it we don't care */
5000 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5001 /* if it is assigned we cannot release it */
5002 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
0224d663
GR		 5003 return true;
5004 }
f557147c
SA		 5005
5006 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
0224d663 5007 }
f557147c 5008
0224d663
GR		 5009 return false;
5010}
5011
5012#endif
4ae196df
AD		 5013static void igb_ping_all_vfs(struct igb_adapter *adapter)
5014{
5015 struct e1000_hw *hw = &adapter->hw;
5016 u32 ping;
5017 int i;
5018
5019 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5020 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5021 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5022 ping |= E1000_VT_MSGTYPE_CTS;
5023 igb_write_mbx(hw, &ping, 1, i);
5024 }
5025}
5026
7d5753f0
AD		 5027static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5028{
5029 struct e1000_hw *hw = &adapter->hw;
5030 u32 vmolr = rd32(E1000_VMOLR(vf));
5031 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5032
d85b9004 5033 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
7d5753f0
AD		 5034 IGB_VF_FLAG_MULTI_PROMISC);
5035 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5036
5037 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5038 vmolr |= E1000_VMOLR_MPME;
d85b9004 5039 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5040 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5041 } else {
5042 /*
5043 * if we have hashes and we are clearing a multicast promisc
5044 * flag we need to write the hashes to the MTA as this step
5045 * was previously skipped
5046 */
5047 if (vf_data->num_vf_mc_hashes > 30) {
5048 vmolr |= E1000_VMOLR_MPME;
5049 } else if (vf_data->num_vf_mc_hashes) {
5050 int j;
5051 vmolr |= E1000_VMOLR_ROMPE;
5052 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5053 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5054 }
5055 }
5056
5057 wr32(E1000_VMOLR(vf), vmolr);
5058
5059 /* there are flags left unprocessed, likely not supported */
5060 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5061 return -EINVAL;
5062
5063 return 0;
5064
5065}
5066
4ae196df
AD		 5067static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5068 u32 *msgbuf, u32 vf)
5069{
5070 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5071 u16 *hash_list = (u16 *)&msgbuf[1];
5072 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5073 int i;
5074
7d5753f0 5075 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5076 * to this VF for later use to restore when the PF multi cast
5077 * list changes
5078 */
5079 vf_data->num_vf_mc_hashes = n;
5080
7d5753f0
AD		 5081 /* only up to 30 hash values supported */
5082 if (n > 30)
5083 n = 30;
5084
5085 /* store the hashes for later use */
4ae196df 5086 for (i = 0; i < n; i++)
a419aef8 5087 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5088
5089 /* Flush and reset the mta with the new values */
ff41f8dc 5090 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5091
5092 return 0;
5093}
5094
5095static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5096{
5097 struct e1000_hw *hw = &adapter->hw;
5098 struct vf_data_storage *vf_data;
5099 int i, j;
5100
5101 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5102 u32 vmolr = rd32(E1000_VMOLR(i));
5103 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5104
4ae196df 5105 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5106
5107 if ((vf_data->num_vf_mc_hashes > 30) ||
5108 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5109 vmolr |= E1000_VMOLR_MPME;
5110 } else if (vf_data->num_vf_mc_hashes) {
5111 vmolr |= E1000_VMOLR_ROMPE;
5112 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5113 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5114 }
5115 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5116 }
5117}
5118
5119static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5120{
5121 struct e1000_hw *hw = &adapter->hw;
5122 u32 pool_mask, reg, vid;
5123 int i;
5124
5125 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5126
5127 /* Find the vlan filter for this id */
5128 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5129 reg = rd32(E1000_VLVF(i));
5130
5131 /* remove the vf from the pool */
5132 reg &= ~pool_mask;
5133
5134 /* if pool is empty then remove entry from vfta */
5135 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5136 (reg & E1000_VLVF_VLANID_ENABLE)) {
5137 reg = 0;
5138 vid = reg & E1000_VLVF_VLANID_MASK;
5139 igb_vfta_set(hw, vid, false);
5140 }
5141
5142 wr32(E1000_VLVF(i), reg);
5143 }
ae641bdc
AD		 5144
5145 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5146}
5147
5148static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5149{
5150 struct e1000_hw *hw = &adapter->hw;
5151 u32 reg, i;
5152
51466239
AD		 5153 /* The vlvf table only exists on 82576 hardware and newer */
5154 if (hw->mac.type < e1000_82576)
5155 return -1;
5156
5157 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5158 if (!adapter->vfs_allocated_count)
5159 return -1;
5160
5161 /* Find the vlan filter for this id */
5162 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5163 reg = rd32(E1000_VLVF(i));
5164 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5165 vid == (reg & E1000_VLVF_VLANID_MASK))
5166 break;
5167 }
5168
5169 if (add) {
5170 if (i == E1000_VLVF_ARRAY_SIZE) {
5171 /* Did not find a matching VLAN ID entry that was
5172 * enabled. Search for a free filter entry, i.e.
5173 * one without the enable bit set
5174 */
5175 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5176 reg = rd32(E1000_VLVF(i));
5177 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5178 break;
5179 }
5180 }
5181 if (i < E1000_VLVF_ARRAY_SIZE) {
5182 /* Found an enabled/available entry */
5183 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5184
5185 /* if !enabled we need to set this up in vfta */
5186 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5187 /* add VID to filter table */
5188 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5189 reg |= E1000_VLVF_VLANID_ENABLE;
5190 }
cad6d05f
AD		 5191 reg &= ~E1000_VLVF_VLANID_MASK;
5192 reg |= vid;
4ae196df 5193 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5194
5195 /* do not modify RLPML for PF devices */
5196 if (vf >= adapter->vfs_allocated_count)
5197 return 0;
5198
5199 if (!adapter->vf_data[vf].vlans_enabled) {
5200 u32 size;
5201 reg = rd32(E1000_VMOLR(vf));
5202 size = reg & E1000_VMOLR_RLPML_MASK;
5203 size += 4;
5204 reg &= ~E1000_VMOLR_RLPML_MASK;
5205 reg |= size;
5206 wr32(E1000_VMOLR(vf), reg);
5207 }
ae641bdc 5208
51466239 5209 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5210 }
5211 } else {
5212 if (i < E1000_VLVF_ARRAY_SIZE) {
5213 /* remove vf from the pool */
5214 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5215 /* if pool is empty then remove entry from vfta */
5216 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5217 reg = 0;
5218 igb_vfta_set(hw, vid, false);
5219 }
5220 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5221
5222 /* do not modify RLPML for PF devices */
5223 if (vf >= adapter->vfs_allocated_count)
5224 return 0;
5225
5226 adapter->vf_data[vf].vlans_enabled--;
5227 if (!adapter->vf_data[vf].vlans_enabled) {
5228 u32 size;
5229 reg = rd32(E1000_VMOLR(vf));
5230 size = reg & E1000_VMOLR_RLPML_MASK;
5231 size -= 4;
5232 reg &= ~E1000_VMOLR_RLPML_MASK;
5233 reg |= size;
5234 wr32(E1000_VMOLR(vf), reg);
5235 }
4ae196df
AD		 5236 }
5237 }
8151d294
WM		 5238 return 0;
5239}
5240
5241static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5242{
5243 struct e1000_hw *hw = &adapter->hw;
5244
5245 if (vid)
5246 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5247 else
5248 wr32(E1000_VMVIR(vf), 0);
5249}
5250
5251static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5252 int vf, u16 vlan, u8 qos)
5253{
5254 int err = 0;
5255 struct igb_adapter *adapter = netdev_priv(netdev);
5256
5257 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5258 return -EINVAL;
5259 if (vlan || qos) {
5260 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5261 if (err)
5262 goto out;
5263 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5264 igb_set_vmolr(adapter, vf, !vlan);
5265 adapter->vf_data[vf].pf_vlan = vlan;
5266 adapter->vf_data[vf].pf_qos = qos;
5267 dev_info(&adapter->pdev->dev,
5268 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5269 if (test_bit(__IGB_DOWN, &adapter->state)) {
5270 dev_warn(&adapter->pdev->dev,
5271 "The VF VLAN has been set,"
5272 " but the PF device is not up.\n");
5273 dev_warn(&adapter->pdev->dev,
5274 "Bring the PF device up before"
5275 " attempting to use the VF device.\n");
5276 }
5277 } else {
5278 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5279 false, vf);
5280 igb_set_vmvir(adapter, vlan, vf);
5281 igb_set_vmolr(adapter, vf, true);
5282 adapter->vf_data[vf].pf_vlan = 0;
5283 adapter->vf_data[vf].pf_qos = 0;
5284 }
5285out:
5286 return err;
4ae196df
AD		 5287}
5288
5289static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5290{
5291 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5292 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5293
5294 return igb_vlvf_set(adapter, vid, add, vf);
5295}
5296
f2ca0dbe 5297static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5298{
8fa7e0f7
GR		 5299 /* clear flags - except flag that indicates PF has set the MAC */
5300 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5301 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5302
5303 /* reset offloads to defaults */
8151d294 5304 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5305
5306 /* reset vlans for device */
5307 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5308 if (adapter->vf_data[vf].pf_vlan)
5309 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5310 adapter->vf_data[vf].pf_vlan,
5311 adapter->vf_data[vf].pf_qos);
5312 else
5313 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5314
5315 /* reset multicast table array for vf */
5316 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5317
5318 /* Flush and reset the mta with the new values */
ff41f8dc 5319 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5320}
5321
f2ca0dbe
AD		 5322static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5323{
5324 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5325
5326 /* generate a new mac address as we were hotplug removed/added */
8151d294 5327 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7efd26d0 5328 eth_random_addr(vf_mac);
f2ca0dbe
AD		 5329
5330 /* process remaining reset events */
5331 igb_vf_reset(adapter, vf);
5332}
5333
5334static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5335{
5336 struct e1000_hw *hw = &adapter->hw;
5337 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5338 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5339 u32 reg, msgbuf[3];
5340 u8 *addr = (u8 *)(&msgbuf[1]);
5341
5342 /* process all the same items cleared in a function level reset */
f2ca0dbe 5343 igb_vf_reset(adapter, vf);
4ae196df
AD		 5344
5345 /* set vf mac address */
26ad9178 5346 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5347
5348 /* enable transmit and receive for vf */
5349 reg = rd32(E1000_VFTE);
5350 wr32(E1000_VFTE, reg | (1 << vf));
5351 reg = rd32(E1000_VFRE);
5352 wr32(E1000_VFRE, reg | (1 << vf));
5353
8fa7e0f7 5354 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5355
5356 /* reply to reset with ack and vf mac address */
5357 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5358 memcpy(addr, vf_mac, 6);
5359 igb_write_mbx(hw, msgbuf, 3, vf);
5360}
5361
5362static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5363{
de42edde
GR		 5364 /*
5365 * The VF MAC Address is stored in a packed array of bytes
5366 * starting at the second 32 bit word of the msg array
5367 */
f2ca0dbe
AD		 5368 unsigned char *addr = (char *)&msg[1];
5369 int err = -1;
4ae196df 5370
f2ca0dbe
AD		 5371 if (is_valid_ether_addr(addr))
5372 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5373
f2ca0dbe 5374 return err;
4ae196df
AD		 5375}
5376
5377static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5378{
5379 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5380 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5381 u32 msg = E1000_VT_MSGTYPE_NACK;
5382
5383 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5384 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5385 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5386 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5387 vf_data->last_nack = jiffies;
4ae196df
AD		 5388 }
5389}
5390
f2ca0dbe 5391static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5392{
f2ca0dbe
AD		 5393 struct pci_dev *pdev = adapter->pdev;
5394 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5395 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5396 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5397 s32 retval;
5398
f2ca0dbe 5399 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5400
fef45f4c
AD		 5401 if (retval) {
5402 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5403 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5404 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5405 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5406 return;
5407 goto out;
5408 }
4ae196df
AD		 5409
5410 /* this is a message we already processed, do nothing */
5411 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5412 return;
4ae196df
AD		 5413
5414 /*
5415 * until the vf completes a reset it should not be
5416 * allowed to start any configuration.
5417 */
5418
5419 if (msgbuf[0] == E1000_VF_RESET) {
5420 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5421 return;
4ae196df
AD		 5422 }
5423
f2ca0dbe 5424 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5425 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5426 return;
5427 retval = -1;
5428 goto out;
4ae196df
AD		 5429 }
5430
5431 switch ((msgbuf[0] & 0xFFFF)) {
5432 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5433 retval = -EINVAL;
5434 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5435 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5436 else
5437 dev_warn(&pdev->dev,
5438 "VF %d attempted to override administratively "
5439 "set MAC address\nReload the VF driver to "
5440 "resume operations\n", vf);
4ae196df 5441 break;
7d5753f0
AD		 5442 case E1000_VF_SET_PROMISC:
5443 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5444 break;
4ae196df
AD		 5445 case E1000_VF_SET_MULTICAST:
5446 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5447 break;
5448 case E1000_VF_SET_LPE:
5449 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5450 break;
5451 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5452 retval = -1;
5453 if (vf_data->pf_vlan)
5454 dev_warn(&pdev->dev,
5455 "VF %d attempted to override administratively "
5456 "set VLAN tag\nReload the VF driver to "
5457 "resume operations\n", vf);
8151d294
WM		 5458 else
5459 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5460 break;
5461 default:
090b1795 5462 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5463 retval = -1;
5464 break;
5465 }
5466
fef45f4c
AD		 5467 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5468out:
4ae196df
AD		 5469 /* notify the VF of the results of what it sent us */
5470 if (retval)
5471 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5472 else
5473 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5474
4ae196df 5475 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5476}
4ae196df 5477
f2ca0dbe
AD		 5478static void igb_msg_task(struct igb_adapter *adapter)
5479{
5480 struct e1000_hw *hw = &adapter->hw;
5481 u32 vf;
5482
5483 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5484 /* process any reset requests */
5485 if (!igb_check_for_rst(hw, vf))
5486 igb_vf_reset_event(adapter, vf);
5487
5488 /* process any messages pending */
5489 if (!igb_check_for_msg(hw, vf))
5490 igb_rcv_msg_from_vf(adapter, vf);
5491
5492 /* process any acks */
5493 if (!igb_check_for_ack(hw, vf))
5494 igb_rcv_ack_from_vf(adapter, vf);
5495 }
4ae196df
AD		 5496}
5497
68d480c4
AD		 5498/**
5499 * igb_set_uta - Set unicast filter table address
5500 * @adapter: board private structure
5501 *
5502 * The unicast table address is a register array of 32-bit registers.
5503 * The table is meant to be used in a way similar to how the MTA is used
5504 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5505 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5506 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5507 **/
5508static void igb_set_uta(struct igb_adapter *adapter)
5509{
5510 struct e1000_hw *hw = &adapter->hw;
5511 int i;
5512
5513 /* The UTA table only exists on 82576 hardware and newer */
5514 if (hw->mac.type < e1000_82576)
5515 return;
5516
5517 /* we only need to do this if VMDq is enabled */
5518 if (!adapter->vfs_allocated_count)
5519 return;
5520
5521 for (i = 0; i < hw->mac.uta_reg_count; i++)
5522 array_wr32(E1000_UTA, i, ~0);
5523}
5524
9d5c8243
AK		 5525/**
5526 * igb_intr_msi - Interrupt Handler
5527 * @irq: interrupt number
5528 * @data: pointer to a network interface device structure
5529 **/
5530static irqreturn_t igb_intr_msi(int irq, void *data)
5531{
047e0030
AD		 5532 struct igb_adapter *adapter = data;
5533 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5534 struct e1000_hw *hw = &adapter->hw;
5535 /* read ICR disables interrupts using IAM */
5536 u32 icr = rd32(E1000_ICR);
5537
047e0030 5538 igb_write_itr(q_vector);
9d5c8243 5539
7f081d40
AD		 5540 if (icr & E1000_ICR_DRSTA)
5541 schedule_work(&adapter->reset_task);
5542
047e0030 5543 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5544 /* HW is reporting DMA is out of sync */
5545 adapter->stats.doosync++;
5546 }
5547
9d5c8243
AK		 5548 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5549 hw->mac.get_link_status = 1;
5550 if (!test_bit(__IGB_DOWN, &adapter->state))
5551 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5552 }
5553
1f6e8178
MV		 5554 if (icr & E1000_ICR_TS) {
5555 u32 tsicr = rd32(E1000_TSICR);
5556
5557 if (tsicr & E1000_TSICR_TXTS) {
5558 /* acknowledge the interrupt */
5559 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5560 /* retrieve hardware timestamp */
5561 schedule_work(&adapter->ptp_tx_work);
5562 }
5563 }
1f6e8178 5564
047e0030 5565 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5566
5567 return IRQ_HANDLED;
5568}
5569
5570/**
4a3c6433 5571 * igb_intr - Legacy Interrupt Handler
9d5c8243
AK		 5572 * @irq: interrupt number
5573 * @data: pointer to a network interface device structure
5574 **/
5575static irqreturn_t igb_intr(int irq, void *data)
5576{
047e0030
AD		 5577 struct igb_adapter *adapter = data;
5578 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5579 struct e1000_hw *hw = &adapter->hw;
5580 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
5581 * need for the IMC write */
5582 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5583
5584 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5585 * not set, then the adapter didn't send an interrupt */
5586 if (!(icr & E1000_ICR_INT_ASSERTED))
5587 return IRQ_NONE;
5588
0ba82994
AD		 5589 igb_write_itr(q_vector);
5590
7f081d40
AD		 5591 if (icr & E1000_ICR_DRSTA)
5592 schedule_work(&adapter->reset_task);
5593
047e0030 5594 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5595 /* HW is reporting DMA is out of sync */
5596 adapter->stats.doosync++;
5597 }
5598
9d5c8243
AK		 5599 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5600 hw->mac.get_link_status = 1;
5601 /* guard against interrupt when we're going down */
5602 if (!test_bit(__IGB_DOWN, &adapter->state))
5603 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5604 }
5605
1f6e8178
MV		 5606 if (icr & E1000_ICR_TS) {
5607 u32 tsicr = rd32(E1000_TSICR);
5608
5609 if (tsicr & E1000_TSICR_TXTS) {
5610 /* acknowledge the interrupt */
5611 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5612 /* retrieve hardware timestamp */
5613 schedule_work(&adapter->ptp_tx_work);
5614 }
5615 }
1f6e8178 5616
047e0030 5617 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5618
5619 return IRQ_HANDLED;
5620}
5621
c50b52a0 5622static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5623{
047e0030 5624 struct igb_adapter *adapter = q_vector->adapter;
46544258 5625 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5626
0ba82994
AD		 5627 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5628 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5629 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5630 igb_set_itr(q_vector);
46544258 5631 else
047e0030 5632 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5633 }
5634
46544258
AD		 5635 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5636 if (adapter->msix_entries)
047e0030 5637 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5638 else
5639 igb_irq_enable(adapter);
5640 }
9d5c8243
AK		 5641}
5642
46544258
AD		 5643/**
5644 * igb_poll - NAPI Rx polling callback
5645 * @napi: napi polling structure
5646 * @budget: count of how many packets we should handle
5647 **/
5648static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5649{
047e0030
AD		 5650 struct igb_q_vector *q_vector = container_of(napi,
5651 struct igb_q_vector,
5652 napi);
16eb8815 5653 bool clean_complete = true;
9d5c8243 5654
421e02f0 5655#ifdef CONFIG_IGB_DCA
047e0030
AD		 5656 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5657 igb_update_dca(q_vector);
fe4506b6 5658#endif
0ba82994 5659 if (q_vector->tx.ring)
13fde97a 5660 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5661
0ba82994 5662 if (q_vector->rx.ring)
cd392f5c 5663 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5664
16eb8815
AD		 5665 /* If all work not completed, return budget and keep polling */
5666 if (!clean_complete)
5667 return budget;
46544258 5668
9d5c8243 5669 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5670 napi_complete(napi);
5671 igb_ring_irq_enable(q_vector);
9d5c8243 5672
16eb8815 5673 return 0;
9d5c8243 5674}
6d8126f9 5675
9d5c8243
AK		 5676/**
5677 * igb_clean_tx_irq - Reclaim resources after transmit completes
047e0030 5678 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 5679 *
9d5c8243
AK		 5680 * returns true if ring is completely cleaned
5681 **/
047e0030 5682static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 5683{
047e0030 5684 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 5685 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 5686 struct igb_tx_buffer *tx_buffer;
f4128785 5687 union e1000_adv_tx_desc *tx_desc;
9d5c8243 5688 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 5689 unsigned int budget = q_vector->tx.work_limit;
8542db05 5690 unsigned int i = tx_ring->next_to_clean;
9d5c8243 5691
13fde97a
AD		 5692 if (test_bit(__IGB_DOWN, &adapter->state))
5693 return true;
0e014cb1 5694
06034649 5695 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 5696 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 5697 i -= tx_ring->count;
9d5c8243 5698
f4128785
AD		 5699 do {
5700 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 5701
5702 /* if next_to_watch is not set then there is no work pending */
5703 if (!eop_desc)
5704 break;
13fde97a 5705
f4128785
AD		 5706 /* prevent any other reads prior to eop_desc */
5707 rmb();
5708
13fde97a
AD		 5709 /* if DD is not set pending work has not been completed */
5710 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5711 break;
5712
8542db05
AD		 5713 /* clear next_to_watch to prevent false hangs */
5714 tx_buffer->next_to_watch = NULL;
9d5c8243 5715
ebe42d16
AD		 5716 /* update the statistics for this packet */
5717 total_bytes += tx_buffer->bytecount;
5718 total_packets += tx_buffer->gso_segs;
13fde97a 5719
ebe42d16
AD		 5720 /* free the skb */
5721 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 5722
ebe42d16
AD		 5723 /* unmap skb header data */
5724 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 5725 dma_unmap_addr(tx_buffer, dma),
5726 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 5727 DMA_TO_DEVICE);
5728
c9f14bf3
AD		 5729 /* clear tx_buffer data */
5730 tx_buffer->skb = NULL;
5731 dma_unmap_len_set(tx_buffer, len, 0);
5732
ebe42d16
AD		 5733 /* clear last DMA location and unmap remaining buffers */
5734 while (tx_desc != eop_desc) {
13fde97a
AD		 5735 tx_buffer++;
5736 tx_desc++;
9d5c8243 5737 i++;
8542db05
AD		 5738 if (unlikely(!i)) {
5739 i -= tx_ring->count;
06034649 5740 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 5741 tx_desc = IGB_TX_DESC(tx_ring, 0);
5742 }
ebe42d16
AD		 5743
5744 /* unmap any remaining paged data */
c9f14bf3 5745 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 5746 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 5747 dma_unmap_addr(tx_buffer, dma),
5748 dma_unmap_len(tx_buffer, len),
ebe42d16 5749 DMA_TO_DEVICE);
c9f14bf3 5750 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 5751 }
5752 }
5753
ebe42d16
AD		 5754 /* move us one more past the eop_desc for start of next pkt */
5755 tx_buffer++;
5756 tx_desc++;
5757 i++;
5758 if (unlikely(!i)) {
5759 i -= tx_ring->count;
5760 tx_buffer = tx_ring->tx_buffer_info;
5761 tx_desc = IGB_TX_DESC(tx_ring, 0);
5762 }
f4128785
AD		 5763
5764 /* issue prefetch for next Tx descriptor */
5765 prefetch(tx_desc);
5766
5767 /* update budget accounting */
5768 budget--;
5769 } while (likely(budget));
0e014cb1 5770
bdbc0631
ED		 5771 netdev_tx_completed_queue(txring_txq(tx_ring),
5772 total_packets, total_bytes);
8542db05 5773 i += tx_ring->count;
9d5c8243 5774 tx_ring->next_to_clean = i;
13fde97a
AD		 5775 u64_stats_update_begin(&tx_ring->tx_syncp);
5776 tx_ring->tx_stats.bytes += total_bytes;
5777 tx_ring->tx_stats.packets += total_packets;
5778 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 5779 q_vector->tx.total_bytes += total_bytes;
5780 q_vector->tx.total_packets += total_packets;
9d5c8243 5781
6d095fa8 5782 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 5783 struct e1000_hw *hw = &adapter->hw;
12dcd86b 5784
9d5c8243
AK		 5785 /* Detect a transmit hang in hardware, this serializes the
5786 * check with the clearing of time_stamp and movement of i */
6d095fa8 5787 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 5788 if (tx_buffer->next_to_watch &&
8542db05 5789 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 5790 (adapter->tx_timeout_factor * HZ)) &&
5791 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 5792
9d5c8243 5793 /* detected Tx unit hang */
59d71989 5794 dev_err(tx_ring->dev,
9d5c8243 5795 "Detected Tx Unit Hang\n"
2d064c06 5796 " Tx Queue <%d>\n"
9d5c8243
AK		 5797 " TDH <%x>\n"
5798 " TDT <%x>\n"
5799 " next_to_use <%x>\n"
5800 " next_to_clean <%x>\n"
9d5c8243
AK		 5801 "buffer_info[next_to_clean]\n"
5802 " time_stamp <%lx>\n"
8542db05 5803 " next_to_watch <%p>\n"
9d5c8243
AK		 5804 " jiffies <%lx>\n"
5805 " desc.status <%x>\n",
2d064c06 5806 tx_ring->queue_index,
238ac817 5807 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 5808 readl(tx_ring->tail),
9d5c8243
AK		 5809 tx_ring->next_to_use,
5810 tx_ring->next_to_clean,
8542db05 5811 tx_buffer->time_stamp,
f4128785 5812 tx_buffer->next_to_watch,
9d5c8243 5813 jiffies,
f4128785 5814 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 5815 netif_stop_subqueue(tx_ring->netdev,
5816 tx_ring->queue_index);
5817
5818 /* we are about to reset, no point in enabling stuff */
5819 return true;
9d5c8243
AK		 5820 }
5821 }
13fde97a
AD		 5822
5823 if (unlikely(total_packets &&
5824 netif_carrier_ok(tx_ring->netdev) &&
5825 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5826 /* Make sure that anybody stopping the queue after this
5827 * sees the new next_to_clean.
5828 */
5829 smp_mb();
5830 if (__netif_subqueue_stopped(tx_ring->netdev,
5831 tx_ring->queue_index) &&
5832 !(test_bit(__IGB_DOWN, &adapter->state))) {
5833 netif_wake_subqueue(tx_ring->netdev,
5834 tx_ring->queue_index);
5835
5836 u64_stats_update_begin(&tx_ring->tx_syncp);
5837 tx_ring->tx_stats.restart_queue++;
5838 u64_stats_update_end(&tx_ring->tx_syncp);
5839 }
5840 }
5841
5842 return !!budget;
9d5c8243
AK		 5843}
5844
cbc8e55f
AD		 5845/**
5846 * igb_reuse_rx_page - page flip buffer and store it back on the ring
5847 * @rx_ring: rx descriptor ring to store buffers on
5848 * @old_buff: donor buffer to have page reused
5849 *
5850 * Synchronizes page for reuse by the adapter
5851 **/
5852static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5853 struct igb_rx_buffer *old_buff)
5854{
5855 struct igb_rx_buffer *new_buff;
5856 u16 nta = rx_ring->next_to_alloc;
5857
5858 new_buff = &rx_ring->rx_buffer_info[nta];
5859
5860 /* update, and store next to alloc */
5861 nta++;
5862 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5863
5864 /* transfer page from old buffer to new buffer */
5865 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5866
5867 /* sync the buffer for use by the device */
5868 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5869 old_buff->page_offset,
de78d1f9 5870 IGB_RX_BUFSZ,
cbc8e55f
AD		 5871 DMA_FROM_DEVICE);
5872}
5873
5874/**
5875 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5876 * @rx_ring: rx descriptor ring to transact packets on
5877 * @rx_buffer: buffer containing page to add
5878 * @rx_desc: descriptor containing length of buffer written by hardware
5879 * @skb: sk_buff to place the data into
5880 *
5881 * This function will add the data contained in rx_buffer->page to the skb.
5882 * This is done either through a direct copy if the data in the buffer is
5883 * less than the skb header size, otherwise it will just attach the page as
5884 * a frag to the skb.
5885 *
5886 * The function will then update the page offset if necessary and return
5887 * true if the buffer can be reused by the adapter.
5888 **/
5889static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5890 struct igb_rx_buffer *rx_buffer,
5891 union e1000_adv_rx_desc *rx_desc,
5892 struct sk_buff *skb)
5893{
5894 struct page *page = rx_buffer->page;
5895 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5896
5897 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5898 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5899
cbc8e55f
AD		 5900 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5901 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5902 va += IGB_TS_HDR_LEN;
5903 size -= IGB_TS_HDR_LEN;
5904 }
5905
cbc8e55f
AD		 5906 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5907
5908 /* we can reuse buffer as-is, just make sure it is local */
5909 if (likely(page_to_nid(page) == numa_node_id()))
5910 return true;
5911
5912 /* this page cannot be reused so discard it */
5913 put_page(page);
5914 return false;
5915 }
5916
5917 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
de78d1f9 5918 rx_buffer->page_offset, size, IGB_RX_BUFSZ);
cbc8e55f
AD		 5919
5920 /* avoid re-using remote pages */
5921 if (unlikely(page_to_nid(page) != numa_node_id()))
5922 return false;
5923
de78d1f9 5924#if (PAGE_SIZE < 8192)
cbc8e55f
AD		 5925 /* if we are only owner of page we can reuse it */
5926 if (unlikely(page_count(page) != 1))
5927 return false;
5928
5929 /* flip page offset to other buffer */
de78d1f9 5930 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
cbc8e55f
AD		 5931
5932 /*
5933 * since we are the only owner of the page and we need to
5934 * increment it, just set the value to 2 in order to avoid
5935 * an unnecessary locked operation
5936 */
5937 atomic_set(&page->_count, 2);
de78d1f9
AD		 5938#else
5939 /* move offset up to the next cache line */
5940 rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5941
5942 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5943 return false;
5944
5945 /* bump ref count on page before it is given to the stack */
5946 get_page(page);
5947#endif
cbc8e55f
AD		 5948
5949 return true;
5950}
5951
2e334eee
AD		 5952static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
5953 union e1000_adv_rx_desc *rx_desc,
5954 struct sk_buff *skb)
5955{
5956 struct igb_rx_buffer *rx_buffer;
5957 struct page *page;
5958
5959 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
5960
5961 /*
5962 * This memory barrier is needed to keep us from reading
5963 * any other fields out of the rx_desc until we know the
5964 * RXD_STAT_DD bit is set
5965 */
5966 rmb();
5967
5968 page = rx_buffer->page;
5969 prefetchw(page);
5970
5971 if (likely(!skb)) {
5972 void *page_addr = page_address(page) +
5973 rx_buffer->page_offset;
5974
5975 /* prefetch first cache line of first page */
5976 prefetch(page_addr);
5977#if L1_CACHE_BYTES < 128
5978 prefetch(page_addr + L1_CACHE_BYTES);
5979#endif
5980
5981 /* allocate a skb to store the frags */
5982 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5983 IGB_RX_HDR_LEN);
5984 if (unlikely(!skb)) {
5985 rx_ring->rx_stats.alloc_failed++;
5986 return NULL;
5987 }
5988
5989 /*
5990 * we will be copying header into skb->data in
5991 * pskb_may_pull so it is in our interest to prefetch
5992 * it now to avoid a possible cache miss
5993 */
5994 prefetchw(skb->data);
5995 }
5996
5997 /* we are reusing so sync this buffer for CPU use */
5998 dma_sync_single_range_for_cpu(rx_ring->dev,
5999 rx_buffer->dma,
6000 rx_buffer->page_offset,
de78d1f9 6001 IGB_RX_BUFSZ,
2e334eee
AD		 6002 DMA_FROM_DEVICE);
6003
6004 /* pull page into skb */
6005 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6006 /* hand second half of page back to the ring */
6007 igb_reuse_rx_page(rx_ring, rx_buffer);
6008 } else {
6009 /* we are not reusing the buffer so unmap it */
6010 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6011 PAGE_SIZE, DMA_FROM_DEVICE);
6012 }
6013
6014 /* clear contents of rx_buffer */
6015 rx_buffer->page = NULL;
6016
6017 return skb;
6018}
6019
cd392f5c 6020static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6021 union e1000_adv_rx_desc *rx_desc,
6022 struct sk_buff *skb)
9d5c8243 6023{
bc8acf2c 6024 skb_checksum_none_assert(skb);
9d5c8243 6025
294e7d78 6026 /* Ignore Checksum bit is set */
3ceb90fd 6027 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6028 return;
6029
6030 /* Rx checksum disabled via ethtool */
6031 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6032 return;
85ad76b2 6033
9d5c8243 6034 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6035 if (igb_test_staterr(rx_desc,
6036 E1000_RXDEXT_STATERR_TCPE |
6037 E1000_RXDEXT_STATERR_IPE)) {
b9473560
JB		 6038 /*
6039 * work around errata with sctp packets where the TCPE aka
6040 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6041 * packets, (aka let the stack check the crc32c)
6042 */
866cff06
AD		 6043 if (!((skb->len == 60) &&
6044 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6045 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6046 ring->rx_stats.csum_err++;
12dcd86b
ED		 6047 u64_stats_update_end(&ring->rx_syncp);
6048 }
9d5c8243 6049 /* let the stack verify checksum errors */
9d5c8243
AK		 6050 return;
6051 }
6052 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6053 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6054 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6055 skb->ip_summed = CHECKSUM_UNNECESSARY;
6056
3ceb90fd
AD		 6057 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6058 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6059}
6060
077887c3
AD		 6061static inline void igb_rx_hash(struct igb_ring *ring,
6062 union e1000_adv_rx_desc *rx_desc,
6063 struct sk_buff *skb)
6064{
6065 if (ring->netdev->features & NETIF_F_RXHASH)
6066 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6067}
6068
2e334eee
AD		 6069/**
6070 * igb_is_non_eop - process handling of non-EOP buffers
6071 * @rx_ring: Rx ring being processed
6072 * @rx_desc: Rx descriptor for current buffer
6073 * @skb: current socket buffer containing buffer in progress
6074 *
6075 * This function updates next to clean. If the buffer is an EOP buffer
6076 * this function exits returning false, otherwise it will place the
6077 * sk_buff in the next buffer to be chained and return true indicating
6078 * that this is in fact a non-EOP buffer.
6079 **/
6080static bool igb_is_non_eop(struct igb_ring *rx_ring,
6081 union e1000_adv_rx_desc *rx_desc)
6082{
6083 u32 ntc = rx_ring->next_to_clean + 1;
6084
6085 /* fetch, update, and store next to clean */
6086 ntc = (ntc < rx_ring->count) ? ntc : 0;
6087 rx_ring->next_to_clean = ntc;
6088
6089 prefetch(IGB_RX_DESC(rx_ring, ntc));
6090
6091 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6092 return false;
6093
6094 return true;
6095}
6096
1a1c225b
AD		 6097/**
6098 * igb_get_headlen - determine size of header for LRO/GRO
6099 * @data: pointer to the start of the headers
6100 * @max_len: total length of section to find headers in
6101 *
6102 * This function is meant to determine the length of headers that will
6103 * be recognized by hardware for LRO, and GRO offloads. The main
6104 * motivation of doing this is to only perform one pull for IPv4 TCP
6105 * packets so that we can do basic things like calculating the gso_size
6106 * based on the average data per packet.
6107 **/
6108static unsigned int igb_get_headlen(unsigned char *data,
6109 unsigned int max_len)
6110{
6111 union {
6112 unsigned char *network;
6113 /* l2 headers */
6114 struct ethhdr *eth;
6115 struct vlan_hdr *vlan;
6116 /* l3 headers */
6117 struct iphdr *ipv4;
6118 struct ipv6hdr *ipv6;
6119 } hdr;
6120 __be16 protocol;
6121 u8 nexthdr = 0; /* default to not TCP */
6122 u8 hlen;
6123
6124 /* this should never happen, but better safe than sorry */
6125 if (max_len < ETH_HLEN)
6126 return max_len;
6127
6128 /* initialize network frame pointer */
6129 hdr.network = data;
6130
6131 /* set first protocol and move network header forward */
6132 protocol = hdr.eth->h_proto;
6133 hdr.network += ETH_HLEN;
6134
6135 /* handle any vlan tag if present */
6136 if (protocol == __constant_htons(ETH_P_8021Q)) {
6137 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6138 return max_len;
6139
6140 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6141 hdr.network += VLAN_HLEN;
6142 }
6143
6144 /* handle L3 protocols */
6145 if (protocol == __constant_htons(ETH_P_IP)) {
6146 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6147 return max_len;
6148
6149 /* access ihl as a u8 to avoid unaligned access on ia64 */
6150 hlen = (hdr.network[0] & 0x0F) << 2;
6151
6152 /* verify hlen meets minimum size requirements */
6153 if (hlen < sizeof(struct iphdr))
6154 return hdr.network - data;
6155
f2fb4ab2
AD		 6156 /* record next protocol if header is present */
6157 if (!hdr.ipv4->frag_off)
6158 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6159 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6160 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6161 return max_len;
6162
6163 /* record next protocol */
6164 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6165 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6166 } else {
6167 return hdr.network - data;
6168 }
6169
f2fb4ab2
AD		 6170 /* relocate pointer to start of L4 header */
6171 hdr.network += hlen;
6172
1a1c225b
AD		 6173 /* finally sort out TCP */
6174 if (nexthdr == IPPROTO_TCP) {
6175 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6176 return max_len;
6177
6178 /* access doff as a u8 to avoid unaligned access on ia64 */
6179 hlen = (hdr.network[12] & 0xF0) >> 2;
6180
6181 /* verify hlen meets minimum size requirements */
6182 if (hlen < sizeof(struct tcphdr))
6183 return hdr.network - data;
6184
6185 hdr.network += hlen;
6186 } else if (nexthdr == IPPROTO_UDP) {
6187 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6188 return max_len;
6189
6190 hdr.network += sizeof(struct udphdr);
6191 }
6192
6193 /*
6194 * If everything has gone correctly hdr.network should be the
6195 * data section of the packet and will be the end of the header.
6196 * If not then it probably represents the end of the last recognized
6197 * header.
6198 */
6199 if ((hdr.network - data) < max_len)
6200 return hdr.network - data;
6201 else
6202 return max_len;
6203}
6204
6205/**
6206 * igb_pull_tail - igb specific version of skb_pull_tail
6207 * @rx_ring: rx descriptor ring packet is being transacted on
cbc8e55f 6208 * @rx_desc: pointer to the EOP Rx descriptor
1a1c225b
AD		 6209 * @skb: pointer to current skb being adjusted
6210 *
6211 * This function is an igb specific version of __pskb_pull_tail. The
6212 * main difference between this version and the original function is that
6213 * this function can make several assumptions about the state of things
6214 * that allow for significant optimizations versus the standard function.
6215 * As a result we can do things like drop a frag and maintain an accurate
6216 * truesize for the skb.
6217 */
6218static void igb_pull_tail(struct igb_ring *rx_ring,
6219 union e1000_adv_rx_desc *rx_desc,
6220 struct sk_buff *skb)
2d94d8ab 6221{
1a1c225b
AD		 6222 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6223 unsigned char *va;
6224 unsigned int pull_len;
6225
6226 /*
6227 * it is valid to use page_address instead of kmap since we are
6228 * working with pages allocated out of the lomem pool per
6229 * alloc_page(GFP_ATOMIC)
2d94d8ab 6230 */
1a1c225b
AD		 6231 va = skb_frag_address(frag);
6232
1a1c225b
AD		 6233 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6234 /* retrieve timestamp from buffer */
6235 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6236
6237 /* update pointers to remove timestamp header */
6238 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6239 frag->page_offset += IGB_TS_HDR_LEN;
6240 skb->data_len -= IGB_TS_HDR_LEN;
6241 skb->len -= IGB_TS_HDR_LEN;
6242
6243 /* move va to start of packet data */
6244 va += IGB_TS_HDR_LEN;
6245 }
6246
1a1c225b
AD		 6247 /*
6248 * we need the header to contain the greater of either ETH_HLEN or
6249 * 60 bytes if the skb->len is less than 60 for skb_pad.
6250 */
6251 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6252
6253 /* align pull length to size of long to optimize memcpy performance */
6254 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6255
6256 /* update all of the pointers */
6257 skb_frag_size_sub(frag, pull_len);
6258 frag->page_offset += pull_len;
6259 skb->data_len -= pull_len;
6260 skb->tail += pull_len;
6261}
6262
6263/**
6264 * igb_cleanup_headers - Correct corrupted or empty headers
6265 * @rx_ring: rx descriptor ring packet is being transacted on
6266 * @rx_desc: pointer to the EOP Rx descriptor
6267 * @skb: pointer to current skb being fixed
6268 *
6269 * Address the case where we are pulling data in on pages only
6270 * and as such no data is present in the skb header.
6271 *
6272 * In addition if skb is not at least 60 bytes we need to pad it so that
6273 * it is large enough to qualify as a valid Ethernet frame.
6274 *
6275 * Returns true if an error was encountered and skb was freed.
6276 **/
6277static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6278 union e1000_adv_rx_desc *rx_desc,
6279 struct sk_buff *skb)
6280{
6281
6282 if (unlikely((igb_test_staterr(rx_desc,
6283 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6284 struct net_device *netdev = rx_ring->netdev;
6285 if (!(netdev->features & NETIF_F_RXALL)) {
6286 dev_kfree_skb_any(skb);
6287 return true;
6288 }
6289 }
6290
6291 /* place header in linear portion of buffer */
6292 if (skb_is_nonlinear(skb))
6293 igb_pull_tail(rx_ring, rx_desc, skb);
6294
6295 /* if skb_pad returns an error the skb was freed */
6296 if (unlikely(skb->len < 60)) {
6297 int pad_len = 60 - skb->len;
6298
6299 if (skb_pad(skb, pad_len))
6300 return true;
6301 __skb_put(skb, pad_len);
6302 }
6303
6304 return false;
2d94d8ab
AD		 6305}
6306
db2ee5bd
AD		 6307/**
6308 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6309 * @rx_ring: rx descriptor ring packet is being transacted on
6310 * @rx_desc: pointer to the EOP Rx descriptor
6311 * @skb: pointer to current skb being populated
6312 *
6313 * This function checks the ring, descriptor, and packet information in
6314 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6315 * other fields within the skb.
6316 **/
6317static void igb_process_skb_fields(struct igb_ring *rx_ring,
6318 union e1000_adv_rx_desc *rx_desc,
6319 struct sk_buff *skb)
6320{
6321 struct net_device *dev = rx_ring->netdev;
6322
6323 igb_rx_hash(rx_ring, rx_desc, skb);
6324
6325 igb_rx_checksum(rx_ring, rx_desc, skb);
6326
db2ee5bd 6327 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
db2ee5bd
AD		 6328
6329 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6330 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6331 u16 vid;
6332 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6333 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6334 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6335 else
6336 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6337
6338 __vlan_hwaccel_put_tag(skb, vid);
6339 }
6340
6341 skb_record_rx_queue(skb, rx_ring->queue_index);
6342
6343 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6344}
6345
2e334eee 6346static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6347{
0ba82994 6348 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6349 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6350 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6351 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6352
2e334eee
AD		 6353 do {
6354 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6355
2e334eee
AD		 6356 /* return some buffers to hardware, one at a time is too slow */
6357 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6358 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6359 cleaned_count = 0;
6360 }
bf36c1a0 6361
2e334eee 6362 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6363
2e334eee
AD		 6364 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6365 break;
9d5c8243 6366
2e334eee
AD		 6367 /* retrieve a buffer from the ring */
6368 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6369
2e334eee
AD		 6370 /* exit if we failed to retrieve a buffer */
6371 if (!skb)
6372 break;
1a1c225b 6373
2e334eee 6374 cleaned_count++;
1a1c225b 6375
2e334eee
AD		 6376 /* fetch next buffer in frame if non-eop */
6377 if (igb_is_non_eop(rx_ring, rx_desc))
6378 continue;
1a1c225b
AD		 6379
6380 /* verify the packet layout is correct */
6381 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6382 skb = NULL;
6383 continue;
9d5c8243 6384 }
9d5c8243 6385
db2ee5bd 6386 /* probably a little skewed due to removing CRC */
3ceb90fd 6387 total_bytes += skb->len;
3ceb90fd 6388
db2ee5bd
AD		 6389 /* populate checksum, timestamp, VLAN, and protocol */
6390 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6391
b2cb09b1 6392 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6393
1a1c225b
AD		 6394 /* reset skb pointer */
6395 skb = NULL;
6396
2e334eee
AD		 6397 /* update budget accounting */
6398 total_packets++;
6399 } while (likely(total_packets < budget));
bf36c1a0 6400
1a1c225b
AD		 6401 /* place incomplete frames back on ring for completion */
6402 rx_ring->skb = skb;
6403
12dcd86b 6404 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6405 rx_ring->rx_stats.packets += total_packets;
6406 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6407 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6408 q_vector->rx.total_packets += total_packets;
6409 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6410
6411 if (cleaned_count)
cd392f5c 6412 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6413
2e334eee 6414 return (total_packets < budget);
9d5c8243
AK		 6415}
6416
c023cd88 6417static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6418 struct igb_rx_buffer *bi)
c023cd88
AD		 6419{
6420 struct page *page = bi->page;
cbc8e55f 6421 dma_addr_t dma;
c023cd88 6422
cbc8e55f
AD		 6423 /* since we are recycling buffers we should seldom need to alloc */
6424 if (likely(page))
c023cd88
AD		 6425 return true;
6426
cbc8e55f
AD		 6427 /* alloc new page for storage */
6428 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6429 if (unlikely(!page)) {
6430 rx_ring->rx_stats.alloc_failed++;
6431 return false;
c023cd88
AD		 6432 }
6433
cbc8e55f
AD		 6434 /* map page for use */
6435 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6436
cbc8e55f
AD		 6437 /*
6438 * if mapping failed free memory back to system since
6439 * there isn't much point in holding memory we can't use
6440 */
1a1c225b 6441 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6442 __free_page(page);
6443
c023cd88
AD		 6444 rx_ring->rx_stats.alloc_failed++;
6445 return false;
6446 }
6447
1a1c225b 6448 bi->dma = dma;
cbc8e55f
AD		 6449 bi->page = page;
6450 bi->page_offset = 0;
1a1c225b 6451
c023cd88
AD		 6452 return true;
6453}
6454
9d5c8243 6455/**
cd392f5c 6456 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
9d5c8243
AK		 6457 * @adapter: address of board private structure
6458 **/
cd392f5c 6459void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6460{
9d5c8243 6461 union e1000_adv_rx_desc *rx_desc;
06034649 6462 struct igb_rx_buffer *bi;
c023cd88 6463 u16 i = rx_ring->next_to_use;
9d5c8243 6464
cbc8e55f
AD		 6465 /* nothing to do */
6466 if (!cleaned_count)
6467 return;
6468
60136906 6469 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6470 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6471 i -= rx_ring->count;
9d5c8243 6472
cbc8e55f 6473 do {
1a1c225b 6474 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6475 break;
9d5c8243 6476
cbc8e55f
AD		 6477 /*
6478 * Refresh the desc even if buffer_addrs didn't change
6479 * because each write-back erases this info.
6480 */
6481 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6482
c023cd88
AD		 6483 rx_desc++;
6484 bi++;
9d5c8243 6485 i++;
c023cd88 6486 if (unlikely(!i)) {
60136906 6487 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6488 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6489 i -= rx_ring->count;
6490 }
6491
6492 /* clear the hdr_addr for the next_to_use descriptor */
6493 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6494
6495 cleaned_count--;
6496 } while (cleaned_count);
9d5c8243 6497
c023cd88
AD		 6498 i += rx_ring->count;
6499
9d5c8243 6500 if (rx_ring->next_to_use != i) {
cbc8e55f 6501 /* record the next descriptor to use */
9d5c8243 6502 rx_ring->next_to_use = i;
9d5c8243 6503
cbc8e55f
AD		 6504 /* update next to alloc since we have filled the ring */
6505 rx_ring->next_to_alloc = i;
6506
6507 /*
6508 * Force memory writes to complete before letting h/w
9d5c8243
AK		 6509 * know there are new descriptors to fetch. (Only
6510 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6511 * such as IA-64).
6512 */
9d5c8243 6513 wmb();
fce99e34 6514 writel(i, rx_ring->tail);
9d5c8243
AK		 6515 }
6516}
6517
6518/**
6519 * igb_mii_ioctl -
6520 * @netdev:
6521 * @ifreq:
6522 * @cmd:
6523 **/
6524static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6525{
6526 struct igb_adapter *adapter = netdev_priv(netdev);
6527 struct mii_ioctl_data *data = if_mii(ifr);
6528
6529 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6530 return -EOPNOTSUPP;
6531
6532 switch (cmd) {
6533 case SIOCGMIIPHY:
6534 data->phy_id = adapter->hw.phy.addr;
6535 break;
6536 case SIOCGMIIREG:
f5f4cf08
AD		 6537 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6538 &data->val_out))
9d5c8243
AK		 6539 return -EIO;
6540 break;
6541 case SIOCSMIIREG:
6542 default:
6543 return -EOPNOTSUPP;
6544 }
6545 return 0;
6546}
6547
6548/**
6549 * igb_ioctl -
6550 * @netdev:
6551 * @ifreq:
6552 * @cmd:
6553 **/
6554static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6555{
6556 switch (cmd) {
6557 case SIOCGMIIPHY:
6558 case SIOCGMIIREG:
6559 case SIOCSMIIREG:
6560 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6561 case SIOCSHWTSTAMP:
a79f4f88 6562 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6563 default:
6564 return -EOPNOTSUPP;
6565 }
6566}
6567
009bc06e
AD		 6568s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6569{
6570 struct igb_adapter *adapter = hw->back;
009bc06e 6571
23d028cc 6572 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6573 return -E1000_ERR_CONFIG;
6574
009bc06e
AD		 6575 return 0;
6576}
6577
6578s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6579{
6580 struct igb_adapter *adapter = hw->back;
009bc06e 6581
23d028cc 6582 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6583 return -E1000_ERR_CONFIG;
6584
009bc06e
AD		 6585 return 0;
6586}
6587
c8f44aff 6588static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6589{
6590 struct igb_adapter *adapter = netdev_priv(netdev);
6591 struct e1000_hw *hw = &adapter->hw;
6592 u32 ctrl, rctl;
5faf030c 6593 bool enable = !!(features & NETIF_F_HW_VLAN_RX);
9d5c8243 6594
5faf030c 6595 if (enable) {
9d5c8243
AK		 6596 /* enable VLAN tag insert/strip */
6597 ctrl = rd32(E1000_CTRL);
6598 ctrl |= E1000_CTRL_VME;
6599 wr32(E1000_CTRL, ctrl);
6600
51466239 6601 /* Disable CFI check */
9d5c8243 6602 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6603 rctl &= ~E1000_RCTL_CFIEN;
6604 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6605 } else {
6606 /* disable VLAN tag insert/strip */
6607 ctrl = rd32(E1000_CTRL);
6608 ctrl &= ~E1000_CTRL_VME;
6609 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6610 }
6611
e1739522 6612 igb_rlpml_set(adapter);
9d5c8243
AK		 6613}
6614
8e586137 6615static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6616{
6617 struct igb_adapter *adapter = netdev_priv(netdev);
6618 struct e1000_hw *hw = &adapter->hw;
4ae196df 6619 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6620
51466239
AD		 6621 /* attempt to add filter to vlvf array */
6622 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6623
51466239
AD		 6624 /* add the filter since PF can receive vlans w/o entry in vlvf */
6625 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6626
6627 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6628
6629 return 0;
9d5c8243
AK		 6630}
6631
8e586137 6632static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
9d5c8243
AK		 6633{
6634 struct igb_adapter *adapter = netdev_priv(netdev);
6635 struct e1000_hw *hw = &adapter->hw;
4ae196df 6636 int pf_id = adapter->vfs_allocated_count;
51466239 6637 s32 err;
9d5c8243 6638
51466239
AD		 6639 /* remove vlan from VLVF table array */
6640 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6641
51466239
AD		 6642 /* if vid was not present in VLVF just remove it from table */
6643 if (err)
4ae196df 6644 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6645
6646 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6647
6648 return 0;
9d5c8243
AK		 6649}
6650
6651static void igb_restore_vlan(struct igb_adapter *adapter)
6652{
b2cb09b1 6653 u16 vid;
9d5c8243 6654
5faf030c
AD		 6655 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6656
b2cb09b1
JP		 6657 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6658 igb_vlan_rx_add_vid(adapter->netdev, vid);
9d5c8243
AK		 6659}
6660
14ad2513 6661int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6662{
090b1795 6663 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6664 struct e1000_mac_info *mac = &adapter->hw.mac;
6665
6666 mac->autoneg = 0;
6667
14ad2513
DD		 6668 /* Make sure dplx is at most 1 bit and lsb of speed is not set
6669 * for the switch() below to work */
6670 if ((spd & 1) || (dplx & ~1))
6671 goto err_inval;
6672
cd2638a8
CW		 6673 /* Fiber NIC's only allow 1000 Gbps Full duplex */
6674 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
14ad2513
DD		 6675 spd != SPEED_1000 &&
6676 dplx != DUPLEX_FULL)
6677 goto err_inval;
cd2638a8 6678
14ad2513 6679 switch (spd + dplx) {
9d5c8243
AK		 6680 case SPEED_10 + DUPLEX_HALF:
6681 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6682 break;
6683 case SPEED_10 + DUPLEX_FULL:
6684 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6685 break;
6686 case SPEED_100 + DUPLEX_HALF:
6687 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6688 break;
6689 case SPEED_100 + DUPLEX_FULL:
6690 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6691 break;
6692 case SPEED_1000 + DUPLEX_FULL:
6693 mac->autoneg = 1;
6694 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6695 break;
6696 case SPEED_1000 + DUPLEX_HALF: /* not supported */
6697 default:
14ad2513 6698 goto err_inval;
9d5c8243 6699 }
8376dad0
JB		 6700
6701 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6702 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6703
9d5c8243 6704 return 0;
14ad2513
DD		 6705
6706err_inval:
6707 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6708 return -EINVAL;
9d5c8243
AK		 6709}
6710
749ab2cd
YZ		 6711static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6712 bool runtime)
9d5c8243
AK		 6713{
6714 struct net_device *netdev = pci_get_drvdata(pdev);
6715 struct igb_adapter *adapter = netdev_priv(netdev);
6716 struct e1000_hw *hw = &adapter->hw;
2d064c06 6717 u32 ctrl, rctl, status;
749ab2cd 6718 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 6719#ifdef CONFIG_PM
6720 int retval = 0;
6721#endif
6722
6723 netif_device_detach(netdev);
6724
a88f10ec 6725 if (netif_running(netdev))
749ab2cd 6726 __igb_close(netdev, true);
a88f10ec 6727
047e0030 6728 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 6729
6730#ifdef CONFIG_PM
6731 retval = pci_save_state(pdev);
6732 if (retval)
6733 return retval;
6734#endif
6735
6736 status = rd32(E1000_STATUS);
6737 if (status & E1000_STATUS_LU)
6738 wufc &= ~E1000_WUFC_LNKC;
6739
6740 if (wufc) {
6741 igb_setup_rctl(adapter);
ff41f8dc 6742 igb_set_rx_mode(netdev);
9d5c8243
AK		 6743
6744 /* turn on all-multi mode if wake on multicast is enabled */
6745 if (wufc & E1000_WUFC_MC) {
6746 rctl = rd32(E1000_RCTL);
6747 rctl |= E1000_RCTL_MPE;
6748 wr32(E1000_RCTL, rctl);
6749 }
6750
6751 ctrl = rd32(E1000_CTRL);
6752 /* advertise wake from D3Cold */
6753 #define E1000_CTRL_ADVD3WUC 0x00100000
6754 /* phy power management enable */
6755 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6756 ctrl |= E1000_CTRL_ADVD3WUC;
6757 wr32(E1000_CTRL, ctrl);
6758
9d5c8243 6759 /* Allow time for pending master requests to run */
330a6d6a 6760 igb_disable_pcie_master(hw);
9d5c8243
AK		 6761
6762 wr32(E1000_WUC, E1000_WUC_PME_EN);
6763 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 6764 } else {
6765 wr32(E1000_WUC, 0);
6766 wr32(E1000_WUFC, 0);
9d5c8243
AK		 6767 }
6768
3fe7c4c9
RW		 6769 *enable_wake = wufc || adapter->en_mng_pt;
6770 if (!*enable_wake)
88a268c1
NN		 6771 igb_power_down_link(adapter);
6772 else
6773 igb_power_up_link(adapter);
9d5c8243
AK		 6774
6775 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6776 * would have already happened in close and is redundant. */
6777 igb_release_hw_control(adapter);
6778
6779 pci_disable_device(pdev);
6780
9d5c8243
AK		 6781 return 0;
6782}
6783
6784#ifdef CONFIG_PM
d9dd966d 6785#ifdef CONFIG_PM_SLEEP
749ab2cd 6786static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 6787{
6788 int retval;
6789 bool wake;
749ab2cd 6790 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 6791
749ab2cd 6792 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6793 if (retval)
6794 return retval;
6795
6796 if (wake) {
6797 pci_prepare_to_sleep(pdev);
6798 } else {
6799 pci_wake_from_d3(pdev, false);
6800 pci_set_power_state(pdev, PCI_D3hot);
6801 }
6802
6803 return 0;
6804}
d9dd966d 6805#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 6806
749ab2cd 6807static int igb_resume(struct device *dev)
9d5c8243 6808{
749ab2cd 6809 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 6810 struct net_device *netdev = pci_get_drvdata(pdev);
6811 struct igb_adapter *adapter = netdev_priv(netdev);
6812 struct e1000_hw *hw = &adapter->hw;
6813 u32 err;
6814
6815 pci_set_power_state(pdev, PCI_D0);
6816 pci_restore_state(pdev);
b94f2d77 6817 pci_save_state(pdev);
42bfd33a 6818
aed5dec3 6819 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 6820 if (err) {
6821 dev_err(&pdev->dev,
6822 "igb: Cannot enable PCI device from suspend\n");
6823 return err;
6824 }
6825 pci_set_master(pdev);
6826
6827 pci_enable_wake(pdev, PCI_D3hot, 0);
6828 pci_enable_wake(pdev, PCI_D3cold, 0);
6829
53c7d064 6830 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 6831 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6832 return -ENOMEM;
9d5c8243
AK		 6833 }
6834
9d5c8243 6835 igb_reset(adapter);
a8564f03
AD		 6836
6837 /* let the f/w know that the h/w is now under the control of the
6838 * driver. */
6839 igb_get_hw_control(adapter);
6840
9d5c8243
AK		 6841 wr32(E1000_WUS, ~0);
6842
749ab2cd 6843 if (netdev->flags & IFF_UP) {
0c2cc02e 6844 rtnl_lock();
749ab2cd 6845 err = __igb_open(netdev, true);
0c2cc02e 6846 rtnl_unlock();
a88f10ec
AD		 6847 if (err)
6848 return err;
6849 }
9d5c8243
AK		 6850
6851 netif_device_attach(netdev);
749ab2cd
YZ		 6852 return 0;
6853}
6854
6855#ifdef CONFIG_PM_RUNTIME
6856static int igb_runtime_idle(struct device *dev)
6857{
6858 struct pci_dev *pdev = to_pci_dev(dev);
6859 struct net_device *netdev = pci_get_drvdata(pdev);
6860 struct igb_adapter *adapter = netdev_priv(netdev);
6861
6862 if (!igb_has_link(adapter))
6863 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6864
6865 return -EBUSY;
6866}
6867
6868static int igb_runtime_suspend(struct device *dev)
6869{
6870 struct pci_dev *pdev = to_pci_dev(dev);
6871 int retval;
6872 bool wake;
6873
6874 retval = __igb_shutdown(pdev, &wake, 1);
6875 if (retval)
6876 return retval;
6877
6878 if (wake) {
6879 pci_prepare_to_sleep(pdev);
6880 } else {
6881 pci_wake_from_d3(pdev, false);
6882 pci_set_power_state(pdev, PCI_D3hot);
6883 }
9d5c8243 6884
9d5c8243
AK		 6885 return 0;
6886}
749ab2cd
YZ		 6887
6888static int igb_runtime_resume(struct device *dev)
6889{
6890 return igb_resume(dev);
6891}
6892#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 6893#endif
6894
6895static void igb_shutdown(struct pci_dev *pdev)
6896{
3fe7c4c9
RW		 6897 bool wake;
6898
749ab2cd 6899 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 6900
6901 if (system_state == SYSTEM_POWER_OFF) {
6902 pci_wake_from_d3(pdev, wake);
6903 pci_set_power_state(pdev, PCI_D3hot);
6904 }
9d5c8243
AK		 6905}
6906
6907#ifdef CONFIG_NET_POLL_CONTROLLER
6908/*
6909 * Polling 'interrupt' - used by things like netconsole to send skbs
6910 * without having to re-enable interrupts. It's not called while
6911 * the interrupt routine is executing.
6912 */
6913static void igb_netpoll(struct net_device *netdev)
6914{
6915 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 6916 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 6917 struct igb_q_vector *q_vector;
9d5c8243 6918 int i;
9d5c8243 6919
047e0030 6920 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 6921 q_vector = adapter->q_vector[i];
6922 if (adapter->msix_entries)
6923 wr32(E1000_EIMC, q_vector->eims_value);
6924 else
6925 igb_irq_disable(adapter);
047e0030 6926 napi_schedule(&q_vector->napi);
eebbbdba 6927 }
9d5c8243
AK		 6928}
6929#endif /* CONFIG_NET_POLL_CONTROLLER */
6930
6931/**
6932 * igb_io_error_detected - called when PCI error is detected
6933 * @pdev: Pointer to PCI device
6934 * @state: The current pci connection state
6935 *
6936 * This function is called after a PCI bus error affecting
6937 * this device has been detected.
6938 */
6939static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6940 pci_channel_state_t state)
6941{
6942 struct net_device *netdev = pci_get_drvdata(pdev);
6943 struct igb_adapter *adapter = netdev_priv(netdev);
6944
6945 netif_device_detach(netdev);
6946
59ed6eec
AD		 6947 if (state == pci_channel_io_perm_failure)
6948 return PCI_ERS_RESULT_DISCONNECT;
6949
9d5c8243
AK		 6950 if (netif_running(netdev))
6951 igb_down(adapter);
6952 pci_disable_device(pdev);
6953
6954 /* Request a slot slot reset. */
6955 return PCI_ERS_RESULT_NEED_RESET;
6956}
6957
6958/**
6959 * igb_io_slot_reset - called after the pci bus has been reset.
6960 * @pdev: Pointer to PCI device
6961 *
6962 * Restart the card from scratch, as if from a cold-boot. Implementation
6963 * resembles the first-half of the igb_resume routine.
6964 */
6965static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6966{
6967 struct net_device *netdev = pci_get_drvdata(pdev);
6968 struct igb_adapter *adapter = netdev_priv(netdev);
6969 struct e1000_hw *hw = &adapter->hw;
40a914fa 6970 pci_ers_result_t result;
42bfd33a 6971 int err;
9d5c8243 6972
aed5dec3 6973 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 6974 dev_err(&pdev->dev,
6975 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 6976 result = PCI_ERS_RESULT_DISCONNECT;
6977 } else {
6978 pci_set_master(pdev);
6979 pci_restore_state(pdev);
b94f2d77 6980 pci_save_state(pdev);
9d5c8243 6981
40a914fa
AD		 6982 pci_enable_wake(pdev, PCI_D3hot, 0);
6983 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 6984
40a914fa
AD		 6985 igb_reset(adapter);
6986 wr32(E1000_WUS, ~0);
6987 result = PCI_ERS_RESULT_RECOVERED;
6988 }
9d5c8243 6989
ea943d41
JK		 6990 err = pci_cleanup_aer_uncorrect_error_status(pdev);
6991 if (err) {
6992 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6993 "failed 0x%0x\n", err);
6994 /* non-fatal, continue */
6995 }
40a914fa
AD		 6996
6997 return result;
9d5c8243
AK		 6998}
6999
7000/**
7001 * igb_io_resume - called when traffic can start flowing again.
7002 * @pdev: Pointer to PCI device
7003 *
7004 * This callback is called when the error recovery driver tells us that
7005 * its OK to resume normal operation. Implementation resembles the
7006 * second-half of the igb_resume routine.
7007 */
7008static void igb_io_resume(struct pci_dev *pdev)
7009{
7010 struct net_device *netdev = pci_get_drvdata(pdev);
7011 struct igb_adapter *adapter = netdev_priv(netdev);
7012
9d5c8243
AK		 7013 if (netif_running(netdev)) {
7014 if (igb_up(adapter)) {
7015 dev_err(&pdev->dev, "igb_up failed after reset\n");
7016 return;
7017 }
7018 }
7019
7020 netif_device_attach(netdev);
7021
7022 /* let the f/w know that the h/w is now under the control of the
7023 * driver. */
7024 igb_get_hw_control(adapter);
9d5c8243
AK		 7025}
7026
26ad9178
AD		 7027static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7028 u8 qsel)
7029{
7030 u32 rar_low, rar_high;
7031 struct e1000_hw *hw = &adapter->hw;
7032
7033 /* HW expects these in little endian so we reverse the byte order
7034 * from network order (big endian) to little endian
7035 */
7036 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7037 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7038 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7039
7040 /* Indicate to hardware the Address is Valid. */
7041 rar_high |= E1000_RAH_AV;
7042
7043 if (hw->mac.type == e1000_82575)
7044 rar_high |= E1000_RAH_POOL_1 * qsel;
7045 else
7046 rar_high |= E1000_RAH_POOL_1 << qsel;
7047
7048 wr32(E1000_RAL(index), rar_low);
7049 wrfl();
7050 wr32(E1000_RAH(index), rar_high);
7051 wrfl();
7052}
7053
4ae196df
AD		 7054static int igb_set_vf_mac(struct igb_adapter *adapter,
7055 int vf, unsigned char *mac_addr)
7056{
7057 struct e1000_hw *hw = &adapter->hw;
ff41f8dc
AD		 7058 /* VF MAC addresses start at end of receive addresses and moves
7059 * torwards the first, as a result a collision should not be possible */
7060 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7061
37680117 7062 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7063
26ad9178 7064 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7065
7066 return 0;
7067}
7068
8151d294
WM		 7069static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7070{
7071 struct igb_adapter *adapter = netdev_priv(netdev);
7072 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7073 return -EINVAL;
7074 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7075 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7076 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7077 " change effective.");
7078 if (test_bit(__IGB_DOWN, &adapter->state)) {
7079 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7080 " but the PF device is not up.\n");
7081 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7082 " attempting to use the VF device.\n");
7083 }
7084 return igb_set_vf_mac(adapter, vf, mac);
7085}
7086
17dc566c
LL		 7087static int igb_link_mbps(int internal_link_speed)
7088{
7089 switch (internal_link_speed) {
7090 case SPEED_100:
7091 return 100;
7092 case SPEED_1000:
7093 return 1000;
7094 default:
7095 return 0;
7096 }
7097}
7098
7099static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7100 int link_speed)
7101{
7102 int rf_dec, rf_int;
7103 u32 bcnrc_val;
7104
7105 if (tx_rate != 0) {
7106 /* Calculate the rate factor values to set */
7107 rf_int = link_speed / tx_rate;
7108 rf_dec = (link_speed - (rf_int * tx_rate));
7109 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7110
7111 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7112 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7113 E1000_RTTBCNRC_RF_INT_MASK);
7114 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7115 } else {
7116 bcnrc_val = 0;
7117 }
7118
7119 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
f00b0da7
LL		 7120 /*
7121 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7122 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7123 */
7124 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7125 wr32(E1000_RTTBCNRC, bcnrc_val);
7126}
7127
7128static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7129{
7130 int actual_link_speed, i;
7131 bool reset_rate = false;
7132
7133 /* VF TX rate limit was not set or not supported */
7134 if ((adapter->vf_rate_link_speed == 0) ||
7135 (adapter->hw.mac.type != e1000_82576))
7136 return;
7137
7138 actual_link_speed = igb_link_mbps(adapter->link_speed);
7139 if (actual_link_speed != adapter->vf_rate_link_speed) {
7140 reset_rate = true;
7141 adapter->vf_rate_link_speed = 0;
7142 dev_info(&adapter->pdev->dev,
7143 "Link speed has been changed. VF Transmit "
7144 "rate is disabled\n");
7145 }
7146
7147 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7148 if (reset_rate)
7149 adapter->vf_data[i].tx_rate = 0;
7150
7151 igb_set_vf_rate_limit(&adapter->hw, i,
7152 adapter->vf_data[i].tx_rate,
7153 actual_link_speed);
7154 }
7155}
7156
8151d294
WM		 7157static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7158{
17dc566c
LL		 7159 struct igb_adapter *adapter = netdev_priv(netdev);
7160 struct e1000_hw *hw = &adapter->hw;
7161 int actual_link_speed;
7162
7163 if (hw->mac.type != e1000_82576)
7164 return -EOPNOTSUPP;
7165
7166 actual_link_speed = igb_link_mbps(adapter->link_speed);
7167 if ((vf >= adapter->vfs_allocated_count) ||
7168 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7169 (tx_rate < 0) || (tx_rate > actual_link_speed))
7170 return -EINVAL;
7171
7172 adapter->vf_rate_link_speed = actual_link_speed;
7173 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7174 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7175
7176 return 0;
8151d294
WM		 7177}
7178
7179static int igb_ndo_get_vf_config(struct net_device *netdev,
7180 int vf, struct ifla_vf_info *ivi)
7181{
7182 struct igb_adapter *adapter = netdev_priv(netdev);
7183 if (vf >= adapter->vfs_allocated_count)
7184 return -EINVAL;
7185 ivi->vf = vf;
7186 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7187 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7188 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7189 ivi->qos = adapter->vf_data[vf].pf_qos;
7190 return 0;
7191}
7192
4ae196df
AD		 7193static void igb_vmm_control(struct igb_adapter *adapter)
7194{
7195 struct e1000_hw *hw = &adapter->hw;
10d8e907 7196 u32 reg;
4ae196df 7197
52a1dd4d
AD		 7198 switch (hw->mac.type) {
7199 case e1000_82575:
f96a8a0b
CW		 7200 case e1000_i210:
7201 case e1000_i211:
52a1dd4d
AD		 7202 default:
7203 /* replication is not supported for 82575 */
4ae196df 7204 return;
52a1dd4d
AD		 7205 case e1000_82576:
7206 /* notify HW that the MAC is adding vlan tags */
7207 reg = rd32(E1000_DTXCTL);
7208 reg |= E1000_DTXCTL_VLAN_ADDED;
7209 wr32(E1000_DTXCTL, reg);
7210 case e1000_82580:
7211 /* enable replication vlan tag stripping */
7212 reg = rd32(E1000_RPLOLR);
7213 reg |= E1000_RPLOLR_STRVLAN;
7214 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7215 case e1000_i350:
7216 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7217 break;
7218 }
10d8e907 7219
d4960307
AD		 7220 if (adapter->vfs_allocated_count) {
7221 igb_vmdq_set_loopback_pf(hw, true);
7222 igb_vmdq_set_replication_pf(hw, true);
13800469
GR		 7223 igb_vmdq_set_anti_spoofing_pf(hw, true,
7224 adapter->vfs_allocated_count);
d4960307
AD		 7225 } else {
7226 igb_vmdq_set_loopback_pf(hw, false);
7227 igb_vmdq_set_replication_pf(hw, false);
7228 }
4ae196df
AD		 7229}
7230
b6e0c419
CW		 7231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7232{
7233 struct e1000_hw *hw = &adapter->hw;
7234 u32 dmac_thr;
7235 u16 hwm;
7236
7237 if (hw->mac.type > e1000_82580) {
7238 if (adapter->flags & IGB_FLAG_DMAC) {
7239 u32 reg;
7240
7241 /* force threshold to 0. */
7242 wr32(E1000_DMCTXTH, 0);
7243
7244 /*
e8c626e9
MV		 7245 * DMA Coalescing high water mark needs to be greater
7246 * than the Rx threshold. Set hwm to PBA - max frame
7247 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7248 */
e8c626e9
MV		 7249 hwm = 64 * pba - adapter->max_frame_size / 16;
7250 if (hwm < 64 * (pba - 6))
7251 hwm = 64 * (pba - 6);
7252 reg = rd32(E1000_FCRTC);
7253 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7254 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7255 & E1000_FCRTC_RTH_COAL_MASK);
7256 wr32(E1000_FCRTC, reg);
7257
7258 /*
7259 * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7260 * frame size, capping it at PBA - 10KB.
7261 */
7262 dmac_thr = pba - adapter->max_frame_size / 512;
7263 if (dmac_thr < pba - 10)
7264 dmac_thr = pba - 10;
b6e0c419
CW		 7265 reg = rd32(E1000_DMACR);
7266 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7267 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7268 & E1000_DMACR_DMACTHR_MASK);
7269
7270 /* transition to L0x or L1 if available..*/
7271 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7272
7273 /* watchdog timer= +-1000 usec in 32usec intervals */
7274 reg |= (1000 >> 5);
0c02dd98
MV		 7275
7276 /* Disable BMC-to-OS Watchdog Enable */
7277 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
b6e0c419
CW		 7278 wr32(E1000_DMACR, reg);
7279
7280 /*
7281 * no lower threshold to disable
7282 * coalescing(smart fifb)-UTRESH=0
7283 */
7284 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7285
7286 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7287
7288 wr32(E1000_DMCTLX, reg);
7289
7290 /*
7291 * free space in tx packet buffer to wake from
7292 * DMA coal
7293 */
7294 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7295 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7296
7297 /*
7298 * make low power state decision controlled
7299 * by DMA coal
7300 */
7301 reg = rd32(E1000_PCIEMISC);
7302 reg &= ~E1000_PCIEMISC_LX_DECISION;
7303 wr32(E1000_PCIEMISC, reg);
7304 } /* endif adapter->dmac is not disabled */
7305 } else if (hw->mac.type == e1000_82580) {
7306 u32 reg = rd32(E1000_PCIEMISC);
7307 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7308 wr32(E1000_DMACR, 0);
7309 }
7310}
7311
9d5c8243 7312/* igb_main.c */
Linux kernel - Deliverables
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