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igb: Don't look for a PBA in the iNVM when flashless
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
65#define BUILD 3
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 126static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 128static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
53c7d064 132static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 139static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
cd392f5c 143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
68d480c4 148static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
047e0030 152static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 153#ifdef CONFIG_IGB_DCA
047e0030 154static void igb_update_dca(struct igb_q_vector *);
fe4506b6 155static void igb_setup_dca(struct igb_adapter *);
421e02f0 156#endif /* CONFIG_IGB_DCA */
661086df 157static int igb_poll(struct napi_struct *, int);
13fde97a 158static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
c8f44aff 163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 166static void igb_restore_vlan(struct igb_adapter *);
26ad9178 167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
4ae196df 170static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
8151d294
WM		 179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
17dc566c 181static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd
YZ		 191static int igb_resume(struct device *);
192#ifdef CONFIG_PM_RUNTIME
193static int igb_runtime_suspend(struct device *dev);
194static int igb_runtime_resume(struct device *dev);
195static int igb_runtime_idle(struct device *dev);
196#endif
197static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201};
9d5c8243
AK		 202#endif
203static void igb_shutdown(struct pci_dev *);
fa44f2f1 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 205#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211};
212#endif
9d5c8243
AK		 213#ifdef CONFIG_NET_POLL_CONTROLLER
214/* for netdump / net console */
215static void igb_netpoll(struct net_device *);
216#endif
37680117 217#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 218static unsigned int max_vfs = 0;
219module_param(max_vfs, uint, 0);
220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
221 "per physical function");
222#endif /* CONFIG_PCI_IOV */
223
9d5c8243
AK		 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227static void igb_io_resume(struct pci_dev *);
228
3646f0e5 229static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233};
234
b6e0c419 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 236
237static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
9f9a12f8 241 .remove = igb_remove,
9d5c8243 242#ifdef CONFIG_PM
749ab2cd 243 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 244#endif
245 .shutdown = igb_shutdown,
fa44f2f1 246 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 247 .err_handler = &igb_err_handler
248};
249
250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252MODULE_LICENSE("GPL");
253MODULE_VERSION(DRV_VERSION);
254
b3f4d599 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256static int debug = -1;
257module_param(debug, int, 0);
258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
c97ec42a
TI		 260struct igb_reg_info {
261 u32 ofs;
262 char *name;
263};
264
265static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299};
300
b980ac18 301/* igb_regdump - register printout routine */
c97ec42a
TI		 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303{
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
876d2d6f 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
c97ec42a
TI		 365}
366
b980ac18 367/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 368static void igb_dump(struct igb_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
c97ec42a
TI		 373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
6ad4edfc 379 u16 i, n;
c97ec42a
TI		 380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 387 pr_info("Device Name state trans_start "
388 "last_rx\n");
389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
390 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 391 }
392
393 /* Print Registers */
394 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 395 pr_info(" Register Name Value\n");
c97ec42a
TI		 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
397 reginfo->name; reginfo++) {
398 igb_regdump(hw, reginfo);
399 }
400
401 /* Print TX Ring Summary */
402 if (!netdev || !netif_running(netdev))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 407 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 408 struct igb_tx_buffer *buffer_info;
c97ec42a 409 tx_ring = adapter->tx_ring[n];
06034649 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
412 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 413 (u64)dma_unmap_addr(buffer_info, dma),
414 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 415 buffer_info->next_to_watch,
416 (u64)buffer_info->time_stamp);
c97ec42a
TI		 417 }
418
419 /* Print TX Rings */
420 if (!netif_msg_tx_done(adapter))
421 goto rx_ring_summary;
422
423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
424
425 /* Transmit Descriptor Formats
426 *
427 * Advanced Transmit Descriptor
428 * +--------------------------------------------------------------+
429 * 0 | Buffer Address [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
432 * +--------------------------------------------------------------+
433 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
442 "[bi->dma ] leng ntw timestamp "
443 "bi->skb\n");
c97ec42a
TI		 444
445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 446 const char *next_desc;
06034649 447 struct igb_tx_buffer *buffer_info;
60136906 448 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 449 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 450 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 451 if (i == tx_ring->next_to_use &&
452 i == tx_ring->next_to_clean)
453 next_desc = " NTC/U";
454 else if (i == tx_ring->next_to_use)
455 next_desc = " NTU";
456 else if (i == tx_ring->next_to_clean)
457 next_desc = " NTC";
458 else
459 next_desc = "";
460
461 pr_info("T [0x%03X] %016llX %016llX %016llX"
462 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
c9f14bf3
AD		 465 (u64)dma_unmap_addr(buffer_info, dma),
466 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 467 buffer_info->next_to_watch,
468 (u64)buffer_info->time_stamp,
876d2d6f 469 buffer_info->skb, next_desc);
c97ec42a 470
b669588a 471 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS,
b669588a 474 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 475 dma_unmap_len(buffer_info, len),
476 true);
c97ec42a
TI		 477 }
478 }
479
480 /* Print RX Rings Summary */
481rx_ring_summary:
482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 483 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 486 pr_info(" %5d %5X %5X\n",
487 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 488 }
489
490 /* Print RX Rings */
491 if (!netif_msg_rx_status(adapter))
492 goto exit;
493
494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
495
496 /* Advanced Receive Descriptor (Read) Format
497 * 63 1 0
498 * +-----------------------------------------------------+
499 * 0 | Packet Buffer Address [63:1] |A0/NSE|
500 * +----------------------------------------------+------+
501 * 8 | Header Buffer Address [63:1] | DD |
502 * +-----------------------------------------------------+
503 *
504 *
505 * Advanced Receive Descriptor (Write-Back) Format
506 *
507 * 63 48 47 32 31 30 21 20 17 16 4 3 0
508 * +------------------------------------------------------+
509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
510 * | Checksum Ident | | | | Type | Type |
511 * +------------------------------------------------------+
512 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
513 * +------------------------------------------------------+
514 * 63 48 47 32 31 20 19 0
515 */
516
517 for (n = 0; n < adapter->num_rx_queues; n++) {
518 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 519 pr_info("------------------------------------\n");
520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 526
527 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 528 const char *next_desc;
06034649
AD		 529 struct igb_rx_buffer *buffer_info;
530 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 531 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 532 u0 = (struct my_u0 *)rx_desc;
533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 534
535 if (i == rx_ring->next_to_use)
536 next_desc = " NTU";
537 else if (i == rx_ring->next_to_clean)
538 next_desc = " NTC";
539 else
540 next_desc = "";
541
c97ec42a
TI		 542 if (staterr & E1000_RXD_STAT_DD) {
543 /* Descriptor Done */
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
545 "RWB", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
1a1c225b 548 next_desc);
c97ec42a 549 } else {
1a1c225b
AD		 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
551 "R ", i,
c97ec42a
TI		 552 le64_to_cpu(u0->a),
553 le64_to_cpu(u0->b),
554 (u64)buffer_info->dma,
1a1c225b 555 next_desc);
c97ec42a 556
b669588a 557 if (netif_msg_pktdata(adapter) &&
1a1c225b 558 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 559 print_hex_dump(KERN_INFO, "",
560 DUMP_PREFIX_ADDRESS,
561 16, 1,
b669588a
ET		 562 page_address(buffer_info->page) +
563 buffer_info->page_offset,
de78d1f9 564 IGB_RX_BUFSZ, true);
c97ec42a
TI		 565 }
566 }
c97ec42a
TI		 567 }
568 }
569
570exit:
571 return;
572}
573
b980ac18
JK		 574/**
575 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 576 * @hw: pointer to hardware structure
577 * @i2cctl: Current value of I2CCTL register
578 *
579 * Returns the I2C data bit value
b980ac18 580 **/
441fc6fd
CW		 581static int igb_get_i2c_data(void *data)
582{
583 struct igb_adapter *adapter = (struct igb_adapter *)data;
584 struct e1000_hw *hw = &adapter->hw;
585 s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
588}
589
b980ac18
JK		 590/**
591 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 592 * @data: pointer to hardware structure
593 * @state: I2C data value (0 or 1) to set
594 *
595 * Sets the I2C data bit
b980ac18 596 **/
441fc6fd
CW		 597static void igb_set_i2c_data(void *data, int state)
598{
599 struct igb_adapter *adapter = (struct igb_adapter *)data;
600 struct e1000_hw *hw = &adapter->hw;
601 s32 i2cctl = rd32(E1000_I2CPARAMS);
602
603 if (state)
604 i2cctl |= E1000_I2C_DATA_OUT;
605 else
606 i2cctl &= ~E1000_I2C_DATA_OUT;
607
608 i2cctl &= ~E1000_I2C_DATA_OE_N;
609 i2cctl |= E1000_I2C_CLK_OE_N;
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612
613}
614
b980ac18
JK		 615/**
616 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 617 * @data: pointer to hardware structure
618 * @state: state to set clock
619 *
620 * Sets the I2C clock line to state
b980ac18 621 **/
441fc6fd
CW		 622static void igb_set_i2c_clk(void *data, int state)
623{
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 if (state) {
629 i2cctl |= E1000_I2C_CLK_OUT;
630 i2cctl &= ~E1000_I2C_CLK_OE_N;
631 } else {
632 i2cctl &= ~E1000_I2C_CLK_OUT;
633 i2cctl &= ~E1000_I2C_CLK_OE_N;
634 }
635 wr32(E1000_I2CPARAMS, i2cctl);
636 wrfl();
637}
638
b980ac18
JK		 639/**
640 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 641 * @data: pointer to hardware structure
642 *
643 * Gets the I2C clock state
b980ac18 644 **/
441fc6fd
CW		 645static int igb_get_i2c_clk(void *data)
646{
647 struct igb_adapter *adapter = (struct igb_adapter *)data;
648 struct e1000_hw *hw = &adapter->hw;
649 s32 i2cctl = rd32(E1000_I2CPARAMS);
650
651 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
652}
653
654static const struct i2c_algo_bit_data igb_i2c_algo = {
655 .setsda = igb_set_i2c_data,
656 .setscl = igb_set_i2c_clk,
657 .getsda = igb_get_i2c_data,
658 .getscl = igb_get_i2c_clk,
659 .udelay = 5,
660 .timeout = 20,
661};
662
9d5c8243 663/**
b980ac18
JK		 664 * igb_get_hw_dev - return device
665 * @hw: pointer to hardware structure
666 *
667 * used by hardware layer to print debugging information
9d5c8243 668 **/
c041076a 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 670{
671 struct igb_adapter *adapter = hw->back;
c041076a 672 return adapter->netdev;
9d5c8243 673}
38c845c7 674
9d5c8243 675/**
b980ac18 676 * igb_init_module - Driver Registration Routine
9d5c8243 677 *
b980ac18
JK		 678 * igb_init_module is the first routine called when the driver is
679 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 680 **/
681static int __init igb_init_module(void)
682{
683 int ret;
876d2d6f 684 pr_info("%s - version %s\n",
9d5c8243
AK		 685 igb_driver_string, igb_driver_version);
686
876d2d6f 687 pr_info("%s\n", igb_copyright);
9d5c8243 688
421e02f0 689#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 690 dca_register_notify(&dca_notifier);
691#endif
bbd98fe4 692 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 693 return ret;
694}
695
696module_init(igb_init_module);
697
698/**
b980ac18 699 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 700 *
b980ac18
JK		 701 * igb_exit_module is called just before the driver is removed
702 * from memory.
9d5c8243
AK		 703 **/
704static void __exit igb_exit_module(void)
705{
421e02f0 706#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 707 dca_unregister_notify(&dca_notifier);
708#endif
9d5c8243
AK		 709 pci_unregister_driver(&igb_driver);
710}
711
712module_exit(igb_exit_module);
713
26bc19ec
AD		 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
715/**
b980ac18
JK		 716 * igb_cache_ring_register - Descriptor ring to register mapping
717 * @adapter: board private structure to initialize
26bc19ec 718 *
b980ac18
JK		 719 * Once we know the feature-set enabled for the device, we'll cache
720 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 721 **/
722static void igb_cache_ring_register(struct igb_adapter *adapter)
723{
ee1b9f06 724 int i = 0, j = 0;
047e0030 725 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 726
727 switch (adapter->hw.mac.type) {
728 case e1000_82576:
729 /* The queues are allocated for virtualization such that VF 0
730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
731 * In order to avoid collision we start at the first free queue
732 * and continue consuming queues in the same sequence
733 */
ee1b9f06 734 if (adapter->vfs_allocated_count) {
a99955fc 735 for (; i < adapter->rss_queues; i++)
3025a446 736 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 737 Q_IDX_82576(i);
ee1b9f06 738 }
26bc19ec 739 case e1000_82575:
55cac248 740 case e1000_82580:
d2ba2ed8 741 case e1000_i350:
ceb5f13b 742 case e1000_i354:
f96a8a0b
CW		 743 case e1000_i210:
744 case e1000_i211:
26bc19ec 745 default:
ee1b9f06 746 for (; i < adapter->num_rx_queues; i++)
3025a446 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 748 for (; j < adapter->num_tx_queues; j++)
3025a446 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 750 break;
751 }
752}
753
4be000c8
AD		 754/**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768{
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778}
779
9d5c8243 780#define IGB_N0_QUEUE -1
047e0030 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 782{
047e0030 783 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 784 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
4be000c8 787 u32 msixbm = 0;
047e0030 788
0ba82994
AD		 789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 793
794 switch (hw->mac.type) {
795 case e1000_82575:
9d5c8243 796 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
047e0030 801 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 803 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 805 if (!adapter->msix_entries && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
9d5c8243 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 808 q_vector->eims_value = msixbm;
2d064c06
AD		 809 break;
810 case e1000_82576:
b980ac18 811 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
047e0030 824 q_vector->eims_value = 1 << msix_vector;
2d064c06 825 break;
55cac248 826 case e1000_82580:
d2ba2ed8 827 case e1000_i350:
ceb5f13b 828 case e1000_i354:
f96a8a0b
CW		 829 case e1000_i210:
830 case e1000_i211:
b980ac18 831 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 845 q_vector->eims_value = 1 << msix_vector;
846 break;
2d064c06
AD		 847 default:
848 BUG();
849 break;
850 }
26b39276
AD		 851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
9d5c8243
AK		 857}
858
859/**
b980ac18
JK		 860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
9d5c8243 862 *
b980ac18
JK		 863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
9d5c8243
AK		 865 **/
866static void igb_configure_msix(struct igb_adapter *adapter)
867{
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
9d5c8243
AK		 873
874 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 875 switch (hw->mac.type) {
876 case e1000_82575:
9d5c8243
AK		 877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 886
887 /* enable msix_other interrupt */
b980ac18 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 889 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 890
2d064c06
AD		 891 break;
892
893 case e1000_82576:
55cac248 894 case e1000_82580:
d2ba2ed8 895 case e1000_i350:
ceb5f13b 896 case e1000_i354:
f96a8a0b
CW		 897 case e1000_i210:
898 case e1000_i211:
047e0030 899 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 900 * won't stick. And it will take days to debug.
901 */
047e0030 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
047e0030
AD		 905
906 /* enable msix_other interrupt */
907 adapter->eims_other = 1 << vector;
2d064c06 908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 909
047e0030 910 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
047e0030
AD		 916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
26b39276
AD		 919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 921
9d5c8243
AK		 922 wrfl();
923}
924
925/**
b980ac18
JK		 926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
9d5c8243 928 *
b980ac18
JK		 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
9d5c8243
AK		 931 **/
932static int igb_request_msix(struct igb_adapter *adapter)
933{
934 struct net_device *netdev = adapter->netdev;
047e0030 935 struct e1000_hw *hw = &adapter->hw;
52285b76 936 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 937
047e0030 938 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 939 igb_msix_other, 0, netdev->name, adapter);
047e0030 940 if (err)
52285b76 941 goto err_out;
047e0030
AD		 942
943 for (i = 0; i < adapter->num_q_vectors; i++) {
944 struct igb_q_vector *q_vector = adapter->q_vector[i];
945
52285b76
SA		 946 vector++;
947
047e0030
AD		 948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
949
0ba82994 950 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 952 q_vector->rx.ring->queue_index);
953 else if (q_vector->tx.ring)
047e0030 954 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 955 q_vector->tx.ring->queue_index);
956 else if (q_vector->rx.ring)
047e0030 957 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 958 q_vector->rx.ring->queue_index);
9d5c8243 959 else
047e0030
AD		 960 sprintf(q_vector->name, "%s-unused", netdev->name);
961
9d5c8243 962 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 963 igb_msix_ring, 0, q_vector->name,
964 q_vector);
9d5c8243 965 if (err)
52285b76 966 goto err_free;
9d5c8243
AK		 967 }
968
9d5c8243
AK		 969 igb_configure_msix(adapter);
970 return 0;
52285b76
SA		 971
972err_free:
973 /* free already assigned IRQs */
974 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
975
976 vector--;
977 for (i = 0; i < vector; i++) {
978 free_irq(adapter->msix_entries[free_vector++].vector,
979 adapter->q_vector[i]);
980 }
981err_out:
9d5c8243
AK		 982 return err;
983}
984
985static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
986{
987 if (adapter->msix_entries) {
988 pci_disable_msix(adapter->pdev);
989 kfree(adapter->msix_entries);
990 adapter->msix_entries = NULL;
047e0030 991 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 992 pci_disable_msi(adapter->pdev);
047e0030 993 }
9d5c8243
AK		 994}
995
5536d210 996/**
b980ac18
JK		 997 * igb_free_q_vector - Free memory allocated for specific interrupt vector
998 * @adapter: board private structure to initialize
999 * @v_idx: Index of vector to be freed
5536d210 1000 *
b980ac18
JK		 1001 * This function frees the memory allocated to the q_vector. In addition if
1002 * NAPI is enabled it will delete any references to the NAPI struct prior
1003 * to freeing the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 if (q_vector->tx.ring)
1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1011
1012 if (q_vector->rx.ring)
1013 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1014
1015 adapter->q_vector[v_idx] = NULL;
1016 netif_napi_del(&q_vector->napi);
1017
7f90128e 1018 /* igb_get_stats64() might access the rings on this vector,
5536d210
AD		 1019 * we must wait a grace period before freeing it.
1020 */
1021 kfree_rcu(q_vector, rcu);
1022}
1023
047e0030 1024/**
b980ac18
JK		 1025 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1026 * @adapter: board private structure to initialize
047e0030 1027 *
b980ac18
JK		 1028 * This function frees the memory allocated to the q_vectors. In addition if
1029 * NAPI is enabled it will delete any references to the NAPI struct prior
1030 * to freeing the q_vector.
047e0030
AD		 1031 **/
1032static void igb_free_q_vectors(struct igb_adapter *adapter)
1033{
5536d210
AD		 1034 int v_idx = adapter->num_q_vectors;
1035
1036 adapter->num_tx_queues = 0;
1037 adapter->num_rx_queues = 0;
047e0030 1038 adapter->num_q_vectors = 0;
5536d210
AD		 1039
1040 while (v_idx--)
1041 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1042}
1043
1044/**
b980ac18
JK		 1045 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1046 * @adapter: board private structure to initialize
047e0030 1047 *
b980ac18
JK		 1048 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1049 * MSI-X interrupts allocated.
047e0030
AD		 1050 */
1051static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1052{
047e0030
AD		 1053 igb_free_q_vectors(adapter);
1054 igb_reset_interrupt_capability(adapter);
1055}
9d5c8243
AK		 1056
1057/**
b980ac18
JK		 1058 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1059 * @adapter: board private structure to initialize
1060 * @msix: boolean value of MSIX capability
9d5c8243 1061 *
b980ac18
JK		 1062 * Attempt to configure interrupts using the best available
1063 * capabilities of the hardware and kernel.
9d5c8243 1064 **/
53c7d064 1065static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1066{
1067 int err;
1068 int numvecs, i;
1069
53c7d064
SA		 1070 if (!msix)
1071 goto msi_only;
1072
83b7180d 1073 /* Number of supported queues. */
a99955fc 1074 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1075 if (adapter->vfs_allocated_count)
1076 adapter->num_tx_queues = 1;
1077 else
1078 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1079
b980ac18 1080 /* start with one vector for every Rx queue */
047e0030
AD		 1081 numvecs = adapter->num_rx_queues;
1082
b980ac18 1083 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1084 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1085 numvecs += adapter->num_tx_queues;
047e0030
AD		 1086
1087 /* store the number of vectors reserved for queues */
1088 adapter->num_q_vectors = numvecs;
1089
1090 /* add 1 vector for link status interrupts */
1091 numvecs++;
9d5c8243
AK		 1092 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1093 GFP_KERNEL);
f96a8a0b 1094
9d5c8243
AK		 1095 if (!adapter->msix_entries)
1096 goto msi_only;
1097
1098 for (i = 0; i < numvecs; i++)
1099 adapter->msix_entries[i].entry = i;
1100
1101 err = pci_enable_msix(adapter->pdev,
1102 adapter->msix_entries,
1103 numvecs);
1104 if (err == 0)
0c2cc02e 1105 return;
9d5c8243
AK		 1106
1107 igb_reset_interrupt_capability(adapter);
1108
1109 /* If we can't do MSI-X, try MSI */
1110msi_only:
2a3abf6d
AD		 1111#ifdef CONFIG_PCI_IOV
1112 /* disable SR-IOV for non MSI-X configurations */
1113 if (adapter->vf_data) {
1114 struct e1000_hw *hw = &adapter->hw;
1115 /* disable iov and allow time for transactions to clear */
1116 pci_disable_sriov(adapter->pdev);
1117 msleep(500);
1118
1119 kfree(adapter->vf_data);
1120 adapter->vf_data = NULL;
1121 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1122 wrfl();
2a3abf6d
AD		 1123 msleep(100);
1124 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1125 }
1126#endif
4fc82adf 1127 adapter->vfs_allocated_count = 0;
a99955fc 1128 adapter->rss_queues = 1;
4fc82adf 1129 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1130 adapter->num_rx_queues = 1;
661086df 1131 adapter->num_tx_queues = 1;
047e0030 1132 adapter->num_q_vectors = 1;
9d5c8243 1133 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1134 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1135}
1136
5536d210
AD		 1137static void igb_add_ring(struct igb_ring *ring,
1138 struct igb_ring_container *head)
1139{
1140 head->ring = ring;
1141 head->count++;
1142}
1143
047e0030 1144/**
b980ac18
JK		 1145 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1146 * @adapter: board private structure to initialize
1147 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1148 * @v_idx: index of vector in adapter struct
1149 * @txr_count: total number of Tx rings to allocate
1150 * @txr_idx: index of first Tx ring to allocate
1151 * @rxr_count: total number of Rx rings to allocate
1152 * @rxr_idx: index of first Rx ring to allocate
047e0030 1153 *
b980ac18 1154 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1155 **/
5536d210
AD		 1156static int igb_alloc_q_vector(struct igb_adapter *adapter,
1157 int v_count, int v_idx,
1158 int txr_count, int txr_idx,
1159 int rxr_count, int rxr_idx)
047e0030
AD		 1160{
1161 struct igb_q_vector *q_vector;
5536d210
AD		 1162 struct igb_ring *ring;
1163 int ring_count, size;
047e0030 1164
5536d210
AD		 1165 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1166 if (txr_count > 1 || rxr_count > 1)
1167 return -ENOMEM;
1168
1169 ring_count = txr_count + rxr_count;
1170 size = sizeof(struct igb_q_vector) +
1171 (sizeof(struct igb_ring) * ring_count);
1172
1173 /* allocate q_vector and rings */
1174 q_vector = kzalloc(size, GFP_KERNEL);
1175 if (!q_vector)
1176 return -ENOMEM;
1177
1178 /* initialize NAPI */
1179 netif_napi_add(adapter->netdev, &q_vector->napi,
1180 igb_poll, 64);
1181
1182 /* tie q_vector and adapter together */
1183 adapter->q_vector[v_idx] = q_vector;
1184 q_vector->adapter = adapter;
1185
1186 /* initialize work limits */
1187 q_vector->tx.work_limit = adapter->tx_work_limit;
1188
1189 /* initialize ITR configuration */
1190 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1191 q_vector->itr_val = IGB_START_ITR;
1192
1193 /* initialize pointer to rings */
1194 ring = q_vector->ring;
1195
4e227667
AD		 1196 /* intialize ITR */
1197 if (rxr_count) {
1198 /* rx or rx/tx vector */
1199 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1200 q_vector->itr_val = adapter->rx_itr_setting;
1201 } else {
1202 /* tx only vector */
1203 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1204 q_vector->itr_val = adapter->tx_itr_setting;
1205 }
1206
5536d210
AD		 1207 if (txr_count) {
1208 /* assign generic ring traits */
1209 ring->dev = &adapter->pdev->dev;
1210 ring->netdev = adapter->netdev;
1211
1212 /* configure backlink on ring */
1213 ring->q_vector = q_vector;
1214
1215 /* update q_vector Tx values */
1216 igb_add_ring(ring, &q_vector->tx);
1217
1218 /* For 82575, context index must be unique per ring. */
1219 if (adapter->hw.mac.type == e1000_82575)
1220 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1221
1222 /* apply Tx specific ring traits */
1223 ring->count = adapter->tx_ring_count;
1224 ring->queue_index = txr_idx;
1225
1226 /* assign ring to adapter */
1227 adapter->tx_ring[txr_idx] = ring;
1228
1229 /* push pointer to next ring */
1230 ring++;
047e0030 1231 }
81c2fc22 1232
5536d210
AD		 1233 if (rxr_count) {
1234 /* assign generic ring traits */
1235 ring->dev = &adapter->pdev->dev;
1236 ring->netdev = adapter->netdev;
047e0030 1237
5536d210
AD		 1238 /* configure backlink on ring */
1239 ring->q_vector = q_vector;
047e0030 1240
5536d210
AD		 1241 /* update q_vector Rx values */
1242 igb_add_ring(ring, &q_vector->rx);
047e0030 1243
5536d210
AD		 1244 /* set flag indicating ring supports SCTP checksum offload */
1245 if (adapter->hw.mac.type >= e1000_82576)
1246 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1247
ceb5f13b
CW		 1248 /*
1249 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1250 * have the tag byte-swapped.
b980ac18 1251 */
5536d210
AD		 1252 if (adapter->hw.mac.type >= e1000_i350)
1253 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1254
5536d210
AD		 1255 /* apply Rx specific ring traits */
1256 ring->count = adapter->rx_ring_count;
1257 ring->queue_index = rxr_idx;
1258
1259 /* assign ring to adapter */
1260 adapter->rx_ring[rxr_idx] = ring;
1261 }
1262
1263 return 0;
047e0030
AD		 1264}
1265
5536d210 1266
047e0030 1267/**
b980ac18
JK		 1268 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1269 * @adapter: board private structure to initialize
047e0030 1270 *
b980ac18
JK		 1271 * We allocate one q_vector per queue interrupt. If allocation fails we
1272 * return -ENOMEM.
047e0030 1273 **/
5536d210 1274static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1275{
5536d210
AD		 1276 int q_vectors = adapter->num_q_vectors;
1277 int rxr_remaining = adapter->num_rx_queues;
1278 int txr_remaining = adapter->num_tx_queues;
1279 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1280 int err;
047e0030 1281
5536d210
AD		 1282 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1283 for (; rxr_remaining; v_idx++) {
1284 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1285 0, 0, 1, rxr_idx);
047e0030 1286
5536d210
AD		 1287 if (err)
1288 goto err_out;
1289
1290 /* update counts and index */
1291 rxr_remaining--;
1292 rxr_idx++;
047e0030 1293 }
047e0030 1294 }
5536d210
AD		 1295
1296 for (; v_idx < q_vectors; v_idx++) {
1297 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1298 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1299 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1300 tqpv, txr_idx, rqpv, rxr_idx);
1301
1302 if (err)
1303 goto err_out;
1304
1305 /* update counts and index */
1306 rxr_remaining -= rqpv;
1307 txr_remaining -= tqpv;
1308 rxr_idx++;
1309 txr_idx++;
1310 }
1311
047e0030 1312 return 0;
5536d210
AD		 1313
1314err_out:
1315 adapter->num_tx_queues = 0;
1316 adapter->num_rx_queues = 0;
1317 adapter->num_q_vectors = 0;
1318
1319 while (v_idx--)
1320 igb_free_q_vector(adapter, v_idx);
1321
1322 return -ENOMEM;
047e0030
AD		 1323}
1324
1325/**
b980ac18
JK		 1326 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1327 * @adapter: board private structure to initialize
1328 * @msix: boolean value of MSIX capability
047e0030 1329 *
b980ac18 1330 * This function initializes the interrupts and allocates all of the queues.
047e0030 1331 **/
53c7d064 1332static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1333{
1334 struct pci_dev *pdev = adapter->pdev;
1335 int err;
1336
53c7d064 1337 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1338
1339 err = igb_alloc_q_vectors(adapter);
1340 if (err) {
1341 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1342 goto err_alloc_q_vectors;
1343 }
1344
5536d210 1345 igb_cache_ring_register(adapter);
047e0030
AD		 1346
1347 return 0;
5536d210 1348
047e0030
AD		 1349err_alloc_q_vectors:
1350 igb_reset_interrupt_capability(adapter);
1351 return err;
1352}
1353
9d5c8243 1354/**
b980ac18
JK		 1355 * igb_request_irq - initialize interrupts
1356 * @adapter: board private structure to initialize
9d5c8243 1357 *
b980ac18
JK		 1358 * Attempts to configure interrupts using the best available
1359 * capabilities of the hardware and kernel.
9d5c8243
AK		 1360 **/
1361static int igb_request_irq(struct igb_adapter *adapter)
1362{
1363 struct net_device *netdev = adapter->netdev;
047e0030 1364 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1365 int err = 0;
1366
1367 if (adapter->msix_entries) {
1368 err = igb_request_msix(adapter);
844290e5 1369 if (!err)
9d5c8243 1370 goto request_done;
9d5c8243 1371 /* fall back to MSI */
5536d210
AD		 1372 igb_free_all_tx_resources(adapter);
1373 igb_free_all_rx_resources(adapter);
53c7d064 1374
047e0030 1375 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1376 err = igb_init_interrupt_scheme(adapter, false);
1377 if (err)
047e0030 1378 goto request_done;
53c7d064 1379
047e0030
AD		 1380 igb_setup_all_tx_resources(adapter);
1381 igb_setup_all_rx_resources(adapter);
53c7d064 1382 igb_configure(adapter);
9d5c8243 1383 }
844290e5 1384
c74d588e
AD		 1385 igb_assign_vector(adapter->q_vector[0], 0);
1386
7dfc16fa 1387 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1388 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1389 netdev->name, adapter);
9d5c8243
AK		 1390 if (!err)
1391 goto request_done;
047e0030 1392
9d5c8243
AK		 1393 /* fall back to legacy interrupts */
1394 igb_reset_interrupt_capability(adapter);
7dfc16fa 1395 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1396 }
1397
c74d588e 1398 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1399 netdev->name, adapter);
9d5c8243 1400
6cb5e577 1401 if (err)
c74d588e 1402 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1403 err);
9d5c8243
AK		 1404
1405request_done:
1406 return err;
1407}
1408
1409static void igb_free_irq(struct igb_adapter *adapter)
1410{
9d5c8243
AK		 1411 if (adapter->msix_entries) {
1412 int vector = 0, i;
1413
047e0030 1414 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1415
0d1ae7f4 1416 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1417 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1418 adapter->q_vector[i]);
047e0030
AD		 1419 } else {
1420 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1421 }
9d5c8243
AK		 1422}
1423
1424/**
b980ac18
JK		 1425 * igb_irq_disable - Mask off interrupt generation on the NIC
1426 * @adapter: board private structure
9d5c8243
AK		 1427 **/
1428static void igb_irq_disable(struct igb_adapter *adapter)
1429{
1430 struct e1000_hw *hw = &adapter->hw;
1431
b980ac18 1432 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1433 * mapped into these registers and so clearing the bits can cause
1434 * issues on the VF drivers so we only need to clear what we set
1435 */
9d5c8243 1436 if (adapter->msix_entries) {
2dfd1212
AD		 1437 u32 regval = rd32(E1000_EIAM);
1438 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1439 wr32(E1000_EIMC, adapter->eims_enable_mask);
1440 regval = rd32(E1000_EIAC);
1441 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1442 }
844290e5
PW		 1443
1444 wr32(E1000_IAM, 0);
9d5c8243
AK		 1445 wr32(E1000_IMC, ~0);
1446 wrfl();
81a61859
ET		 1447 if (adapter->msix_entries) {
1448 int i;
1449 for (i = 0; i < adapter->num_q_vectors; i++)
1450 synchronize_irq(adapter->msix_entries[i].vector);
1451 } else {
1452 synchronize_irq(adapter->pdev->irq);
1453 }
9d5c8243
AK		 1454}
1455
1456/**
b980ac18
JK		 1457 * igb_irq_enable - Enable default interrupt generation settings
1458 * @adapter: board private structure
9d5c8243
AK		 1459 **/
1460static void igb_irq_enable(struct igb_adapter *adapter)
1461{
1462 struct e1000_hw *hw = &adapter->hw;
1463
1464 if (adapter->msix_entries) {
06218a8d 1465 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1466 u32 regval = rd32(E1000_EIAC);
1467 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1468 regval = rd32(E1000_EIAM);
1469 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1470 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1471 if (adapter->vfs_allocated_count) {
4ae196df 1472 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1473 ims |= E1000_IMS_VMMB;
1474 }
1475 wr32(E1000_IMS, ims);
844290e5 1476 } else {
55cac248
AD		 1477 wr32(E1000_IMS, IMS_ENABLE_MASK |
1478 E1000_IMS_DRSTA);
1479 wr32(E1000_IAM, IMS_ENABLE_MASK |
1480 E1000_IMS_DRSTA);
844290e5 1481 }
9d5c8243
AK		 1482}
1483
1484static void igb_update_mng_vlan(struct igb_adapter *adapter)
1485{
51466239 1486 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1487 u16 vid = adapter->hw.mng_cookie.vlan_id;
1488 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1489
1490 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1491 /* add VID to filter table */
1492 igb_vfta_set(hw, vid, true);
1493 adapter->mng_vlan_id = vid;
1494 } else {
1495 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1496 }
1497
1498 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1499 (vid != old_vid) &&
b2cb09b1 1500 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1501 /* remove VID from filter table */
1502 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1503 }
1504}
1505
1506/**
b980ac18
JK		 1507 * igb_release_hw_control - release control of the h/w to f/w
1508 * @adapter: address of board private structure
9d5c8243 1509 *
b980ac18
JK		 1510 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1511 * For ASF and Pass Through versions of f/w this means that the
1512 * driver is no longer loaded.
9d5c8243
AK		 1513 **/
1514static void igb_release_hw_control(struct igb_adapter *adapter)
1515{
1516 struct e1000_hw *hw = &adapter->hw;
1517 u32 ctrl_ext;
1518
1519 /* Let firmware take over control of h/w */
1520 ctrl_ext = rd32(E1000_CTRL_EXT);
1521 wr32(E1000_CTRL_EXT,
1522 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1523}
1524
9d5c8243 1525/**
b980ac18
JK		 1526 * igb_get_hw_control - get control of the h/w from f/w
1527 * @adapter: address of board private structure
9d5c8243 1528 *
b980ac18
JK		 1529 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1530 * For ASF and Pass Through versions of f/w this means that
1531 * the driver is loaded.
9d5c8243
AK		 1532 **/
1533static void igb_get_hw_control(struct igb_adapter *adapter)
1534{
1535 struct e1000_hw *hw = &adapter->hw;
1536 u32 ctrl_ext;
1537
1538 /* Let firmware know the driver has taken over */
1539 ctrl_ext = rd32(E1000_CTRL_EXT);
1540 wr32(E1000_CTRL_EXT,
1541 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1542}
1543
9d5c8243 1544/**
b980ac18
JK		 1545 * igb_configure - configure the hardware for RX and TX
1546 * @adapter: private board structure
9d5c8243
AK		 1547 **/
1548static void igb_configure(struct igb_adapter *adapter)
1549{
1550 struct net_device *netdev = adapter->netdev;
1551 int i;
1552
1553 igb_get_hw_control(adapter);
ff41f8dc 1554 igb_set_rx_mode(netdev);
9d5c8243
AK		 1555
1556 igb_restore_vlan(adapter);
9d5c8243 1557
85b430b4 1558 igb_setup_tctl(adapter);
06cf2666 1559 igb_setup_mrqc(adapter);
9d5c8243 1560 igb_setup_rctl(adapter);
85b430b4
AD		 1561
1562 igb_configure_tx(adapter);
9d5c8243 1563 igb_configure_rx(adapter);
662d7205
AD		 1564
1565 igb_rx_fifo_flush_82575(&adapter->hw);
1566
c493ea45 1567 /* call igb_desc_unused which always leaves
9d5c8243 1568 * at least 1 descriptor unused to make sure
b980ac18
JK		 1569 * next_to_use != next_to_clean
1570 */
9d5c8243 1571 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1572 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1573 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1574 }
9d5c8243
AK		 1575}
1576
88a268c1 1577/**
b980ac18
JK		 1578 * igb_power_up_link - Power up the phy/serdes link
1579 * @adapter: address of board private structure
88a268c1
NN		 1580 **/
1581void igb_power_up_link(struct igb_adapter *adapter)
1582{
76886596
AA		 1583 igb_reset_phy(&adapter->hw);
1584
88a268c1
NN		 1585 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1586 igb_power_up_phy_copper(&adapter->hw);
1587 else
1588 igb_power_up_serdes_link_82575(&adapter->hw);
1589}
1590
1591/**
b980ac18
JK		 1592 * igb_power_down_link - Power down the phy/serdes link
1593 * @adapter: address of board private structure
88a268c1
NN		 1594 */
1595static void igb_power_down_link(struct igb_adapter *adapter)
1596{
1597 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1598 igb_power_down_phy_copper_82575(&adapter->hw);
1599 else
1600 igb_shutdown_serdes_link_82575(&adapter->hw);
1601}
9d5c8243
AK		 1602
1603/**
b980ac18
JK		 1604 * igb_up - Open the interface and prepare it to handle traffic
1605 * @adapter: board private structure
9d5c8243 1606 **/
9d5c8243
AK		 1607int igb_up(struct igb_adapter *adapter)
1608{
1609 struct e1000_hw *hw = &adapter->hw;
1610 int i;
1611
1612 /* hardware has been reset, we need to reload some things */
1613 igb_configure(adapter);
1614
1615 clear_bit(__IGB_DOWN, &adapter->state);
1616
0d1ae7f4
AD		 1617 for (i = 0; i < adapter->num_q_vectors; i++)
1618 napi_enable(&(adapter->q_vector[i]->napi));
1619
844290e5 1620 if (adapter->msix_entries)
9d5c8243 1621 igb_configure_msix(adapter);
feeb2721
AD		 1622 else
1623 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1624
1625 /* Clear any pending interrupts. */
1626 rd32(E1000_ICR);
1627 igb_irq_enable(adapter);
1628
d4960307
AD		 1629 /* notify VFs that reset has been completed */
1630 if (adapter->vfs_allocated_count) {
1631 u32 reg_data = rd32(E1000_CTRL_EXT);
1632 reg_data |= E1000_CTRL_EXT_PFRSTD;
1633 wr32(E1000_CTRL_EXT, reg_data);
1634 }
1635
4cb9be7a
JB		 1636 netif_tx_start_all_queues(adapter->netdev);
1637
25568a53
AD		 1638 /* start the watchdog. */
1639 hw->mac.get_link_status = 1;
1640 schedule_work(&adapter->watchdog_task);
1641
9d5c8243
AK		 1642 return 0;
1643}
1644
1645void igb_down(struct igb_adapter *adapter)
1646{
9d5c8243 1647 struct net_device *netdev = adapter->netdev;
330a6d6a 1648 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1649 u32 tctl, rctl;
1650 int i;
1651
1652 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1653 * reschedule our watchdog timer
1654 */
9d5c8243
AK		 1655 set_bit(__IGB_DOWN, &adapter->state);
1656
1657 /* disable receives in the hardware */
1658 rctl = rd32(E1000_RCTL);
1659 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1660 /* flush and sleep below */
1661
fd2ea0a7 1662 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1663
1664 /* disable transmits in the hardware */
1665 tctl = rd32(E1000_TCTL);
1666 tctl &= ~E1000_TCTL_EN;
1667 wr32(E1000_TCTL, tctl);
1668 /* flush both disables and wait for them to finish */
1669 wrfl();
1670 msleep(10);
1671
41f149a2
CW		 1672 igb_irq_disable(adapter);
1673
1674 for (i = 0; i < adapter->num_q_vectors; i++) {
1675 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1676 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1677 }
9d5c8243 1678
9d5c8243
AK		 1679
1680 del_timer_sync(&adapter->watchdog_timer);
1681 del_timer_sync(&adapter->phy_info_timer);
1682
9d5c8243 1683 netif_carrier_off(netdev);
04fe6358
AD		 1684
1685 /* record the stats before reset*/
12dcd86b
ED		 1686 spin_lock(&adapter->stats64_lock);
1687 igb_update_stats(adapter, &adapter->stats64);
1688 spin_unlock(&adapter->stats64_lock);
04fe6358 1689
9d5c8243
AK		 1690 adapter->link_speed = 0;
1691 adapter->link_duplex = 0;
1692
3023682e
JK		 1693 if (!pci_channel_offline(adapter->pdev))
1694 igb_reset(adapter);
9d5c8243
AK		 1695 igb_clean_all_tx_rings(adapter);
1696 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1697#ifdef CONFIG_IGB_DCA
1698
1699 /* since we reset the hardware DCA settings were cleared */
1700 igb_setup_dca(adapter);
1701#endif
9d5c8243
AK		 1702}
1703
1704void igb_reinit_locked(struct igb_adapter *adapter)
1705{
1706 WARN_ON(in_interrupt());
1707 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1708 msleep(1);
1709 igb_down(adapter);
1710 igb_up(adapter);
1711 clear_bit(__IGB_RESETTING, &adapter->state);
1712}
1713
1714void igb_reset(struct igb_adapter *adapter)
1715{
090b1795 1716 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1717 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1718 struct e1000_mac_info *mac = &hw->mac;
1719 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1720 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1721
1722 /* Repartition Pba for greater than 9k mtu
1723 * To take effect CTRL.RST is required.
1724 */
fa4dfae0 1725 switch (mac->type) {
d2ba2ed8 1726 case e1000_i350:
ceb5f13b 1727 case e1000_i354:
55cac248
AD		 1728 case e1000_82580:
1729 pba = rd32(E1000_RXPBS);
1730 pba = igb_rxpbs_adjust_82580(pba);
1731 break;
fa4dfae0 1732 case e1000_82576:
d249be54
AD		 1733 pba = rd32(E1000_RXPBS);
1734 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1735 break;
1736 case e1000_82575:
f96a8a0b
CW		 1737 case e1000_i210:
1738 case e1000_i211:
fa4dfae0
AD		 1739 default:
1740 pba = E1000_PBA_34K;
1741 break;
2d064c06 1742 }
9d5c8243 1743
2d064c06
AD		 1744 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1745 (mac->type < e1000_82576)) {
9d5c8243
AK		 1746 /* adjust PBA for jumbo frames */
1747 wr32(E1000_PBA, pba);
1748
1749 /* To maintain wire speed transmits, the Tx FIFO should be
1750 * large enough to accommodate two full transmit packets,
1751 * rounded up to the next 1KB and expressed in KB. Likewise,
1752 * the Rx FIFO should be large enough to accommodate at least
1753 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1754 * expressed in KB.
1755 */
9d5c8243
AK		 1756 pba = rd32(E1000_PBA);
1757 /* upper 16 bits has Tx packet buffer allocation size in KB */
1758 tx_space = pba >> 16;
1759 /* lower 16 bits has Rx packet buffer allocation size in KB */
1760 pba &= 0xffff;
b980ac18
JK		 1761 /* the Tx fifo also stores 16 bytes of information about the Tx
1762 * but don't include ethernet FCS because hardware appends it
1763 */
9d5c8243 1764 min_tx_space = (adapter->max_frame_size +
85e8d004 1765 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1766 ETH_FCS_LEN) * 2;
1767 min_tx_space = ALIGN(min_tx_space, 1024);
1768 min_tx_space >>= 10;
1769 /* software strips receive CRC, so leave room for it */
1770 min_rx_space = adapter->max_frame_size;
1771 min_rx_space = ALIGN(min_rx_space, 1024);
1772 min_rx_space >>= 10;
1773
1774 /* If current Tx allocation is less than the min Tx FIFO size,
1775 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1776 * allocation, take space away from current Rx allocation
1777 */
9d5c8243
AK		 1778 if (tx_space < min_tx_space &&
1779 ((min_tx_space - tx_space) < pba)) {
1780 pba = pba - (min_tx_space - tx_space);
1781
b980ac18
JK		 1782 /* if short on Rx space, Rx wins and must trump Tx
1783 * adjustment
1784 */
9d5c8243
AK		 1785 if (pba < min_rx_space)
1786 pba = min_rx_space;
1787 }
2d064c06 1788 wr32(E1000_PBA, pba);
9d5c8243 1789 }
9d5c8243
AK		 1790
1791 /* flow control settings */
1792 /* The high water mark must be low enough to fit one full frame
1793 * (or the size used for early receive) above it in the Rx FIFO.
1794 * Set it to the lower of:
1795 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1796 * - the full Rx FIFO size minus one full frame
1797 */
9d5c8243 1798 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1799 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1800
d48507fe 1801 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1802 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1803 fc->pause_time = 0xFFFF;
1804 fc->send_xon = 1;
0cce119a 1805 fc->current_mode = fc->requested_mode;
9d5c8243 1806
4ae196df
AD		 1807 /* disable receive for all VFs and wait one second */
1808 if (adapter->vfs_allocated_count) {
1809 int i;
1810 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1811 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1812
1813 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1814 igb_ping_all_vfs(adapter);
4ae196df
AD		 1815
1816 /* disable transmits and receives */
1817 wr32(E1000_VFRE, 0);
1818 wr32(E1000_VFTE, 0);
1819 }
1820
9d5c8243 1821 /* Allow time for pending master requests to run */
330a6d6a 1822 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1823 wr32(E1000_WUC, 0);
1824
330a6d6a 1825 if (hw->mac.ops.init_hw(hw))
090b1795 1826 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1827
b980ac18 1828 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1829 * control is off when forcing speed.
1830 */
1831 if (!hw->mac.autoneg)
1832 igb_force_mac_fc(hw);
1833
b6e0c419 1834 igb_init_dmac(adapter, pba);
e428893b
CW		 1835#ifdef CONFIG_IGB_HWMON
1836 /* Re-initialize the thermal sensor on i350 devices. */
1837 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1838 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1839 /* If present, re-initialize the external thermal sensor
1840 * interface.
1841 */
1842 if (adapter->ets)
1843 mac->ops.init_thermal_sensor_thresh(hw);
1844 }
1845 }
1846#endif
88a268c1
NN		 1847 if (!netif_running(adapter->netdev))
1848 igb_power_down_link(adapter);
1849
9d5c8243
AK		 1850 igb_update_mng_vlan(adapter);
1851
1852 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1853 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1854
1f6e8178
MV		 1855 /* Re-enable PTP, where applicable. */
1856 igb_ptp_reset(adapter);
1f6e8178 1857
330a6d6a 1858 igb_get_phy_info(hw);
9d5c8243
AK		 1859}
1860
c8f44aff
MM		 1861static netdev_features_t igb_fix_features(struct net_device *netdev,
1862 netdev_features_t features)
b2cb09b1 1863{
b980ac18
JK		 1864 /* Since there is no support for separate Rx/Tx vlan accel
1865 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1866 */
f646968f
PM		 1867 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1868 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1869 else
f646968f 1870 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1871
1872 return features;
1873}
1874
c8f44aff
MM		 1875static int igb_set_features(struct net_device *netdev,
1876 netdev_features_t features)
ac52caa3 1877{
c8f44aff 1878 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1879 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1880
f646968f 1881 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1882 igb_vlan_mode(netdev, features);
1883
89eaefb6
BG		 1884 if (!(changed & NETIF_F_RXALL))
1885 return 0;
1886
1887 netdev->features = features;
1888
1889 if (netif_running(netdev))
1890 igb_reinit_locked(adapter);
1891 else
1892 igb_reset(adapter);
1893
ac52caa3
MM		 1894 return 0;
1895}
1896
2e5c6922 1897static const struct net_device_ops igb_netdev_ops = {
559e9c49 1898 .ndo_open = igb_open,
2e5c6922 1899 .ndo_stop = igb_close,
cd392f5c 1900 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1901 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1902 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1903 .ndo_set_mac_address = igb_set_mac,
1904 .ndo_change_mtu = igb_change_mtu,
1905 .ndo_do_ioctl = igb_ioctl,
1906 .ndo_tx_timeout = igb_tx_timeout,
1907 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1908 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1909 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1910 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1911 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1912 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1913 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1914 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1915#ifdef CONFIG_NET_POLL_CONTROLLER
1916 .ndo_poll_controller = igb_netpoll,
1917#endif
b2cb09b1
JP		 1918 .ndo_fix_features = igb_fix_features,
1919 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1920};
1921
d67974f0
CW		 1922/**
1923 * igb_set_fw_version - Configure version string for ethtool
1924 * @adapter: adapter struct
d67974f0
CW		 1925 **/
1926void igb_set_fw_version(struct igb_adapter *adapter)
1927{
1928 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1929 struct e1000_fw_version fw;
1930
1931 igb_get_fw_version(hw, &fw);
1932
1933 switch (hw->mac.type) {
7dc98a62 1934 case e1000_i210:
0b1a6f2e 1935 case e1000_i211:
7dc98a62
CW		 1936 if (!(igb_get_flash_presence_i210(hw))) {
1937 snprintf(adapter->fw_version,
1938 sizeof(adapter->fw_version),
1939 "%2d.%2d-%d",
1940 fw.invm_major, fw.invm_minor,
1941 fw.invm_img_type);
1942 break;
1943 }
1944 /* fall through */
0b1a6f2e
CW		 1945 default:
1946 /* if option is rom valid, display its version too */
1947 if (fw.or_valid) {
1948 snprintf(adapter->fw_version,
1949 sizeof(adapter->fw_version),
1950 "%d.%d, 0x%08x, %d.%d.%d",
1951 fw.eep_major, fw.eep_minor, fw.etrack_id,
1952 fw.or_major, fw.or_build, fw.or_patch);
1953 /* no option rom */
7dc98a62 1954 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 1955 snprintf(adapter->fw_version,
7dc98a62
CW		 1956 sizeof(adapter->fw_version),
1957 "%d.%d, 0x%08x",
1958 fw.eep_major, fw.eep_minor, fw.etrack_id);
1959 } else {
1960 snprintf(adapter->fw_version,
1961 sizeof(adapter->fw_version),
1962 "%d.%d.%d",
1963 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 1964 }
1965 break;
d67974f0 1966 }
d67974f0
CW		 1967 return;
1968}
1969
b980ac18
JK		 1970/**
1971 * igb_init_i2c - Init I2C interface
441fc6fd 1972 * @adapter: pointer to adapter structure
b980ac18 1973 **/
441fc6fd
CW		 1974static s32 igb_init_i2c(struct igb_adapter *adapter)
1975{
1976 s32 status = E1000_SUCCESS;
1977
1978 /* I2C interface supported on i350 devices */
1979 if (adapter->hw.mac.type != e1000_i350)
1980 return E1000_SUCCESS;
1981
1982 /* Initialize the i2c bus which is controlled by the registers.
1983 * This bus will use the i2c_algo_bit structue that implements
1984 * the protocol through toggling of the 4 bits in the register.
1985 */
1986 adapter->i2c_adap.owner = THIS_MODULE;
1987 adapter->i2c_algo = igb_i2c_algo;
1988 adapter->i2c_algo.data = adapter;
1989 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1990 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1991 strlcpy(adapter->i2c_adap.name, "igb BB",
1992 sizeof(adapter->i2c_adap.name));
1993 status = i2c_bit_add_bus(&adapter->i2c_adap);
1994 return status;
1995}
1996
9d5c8243 1997/**
b980ac18
JK		 1998 * igb_probe - Device Initialization Routine
1999 * @pdev: PCI device information struct
2000 * @ent: entry in igb_pci_tbl
9d5c8243 2001 *
b980ac18 2002 * Returns 0 on success, negative on failure
9d5c8243 2003 *
b980ac18
JK		 2004 * igb_probe initializes an adapter identified by a pci_dev structure.
2005 * The OS initialization, configuring of the adapter private structure,
2006 * and a hardware reset occur.
9d5c8243 2007 **/
1dd06ae8 2008static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2009{
2010 struct net_device *netdev;
2011 struct igb_adapter *adapter;
2012 struct e1000_hw *hw;
4337e993 2013 u16 eeprom_data = 0;
9835fd73 2014 s32 ret_val;
4337e993 2015 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 2016 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2017 unsigned long mmio_start, mmio_len;
2d6a5e95 2018 int err, pci_using_dac;
9835fd73 2019 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2020
bded64a7
AG		 2021 /* Catch broken hardware that put the wrong VF device ID in
2022 * the PCIe SR-IOV capability.
2023 */
2024 if (pdev->is_virtfn) {
2025 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2026 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2027 return -EINVAL;
2028 }
2029
aed5dec3 2030 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2031 if (err)
2032 return err;
2033
2034 pci_using_dac = 0;
59d71989 2035 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2036 if (!err) {
59d71989 2037 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 2038 if (!err)
2039 pci_using_dac = 1;
2040 } else {
59d71989 2041 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2042 if (err) {
b980ac18
JK		 2043 err = dma_set_coherent_mask(&pdev->dev,
2044 DMA_BIT_MASK(32));
9d5c8243 2045 if (err) {
b980ac18
JK		 2046 dev_err(&pdev->dev,
2047 "No usable DMA configuration, aborting\n");
9d5c8243
AK		 2048 goto err_dma;
2049 }
2050 }
2051 }
2052
aed5dec3 2053 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2054 IORESOURCE_MEM),
2055 igb_driver_name);
9d5c8243
AK		 2056 if (err)
2057 goto err_pci_reg;
2058
19d5afd4 2059 pci_enable_pcie_error_reporting(pdev);
40a914fa 2060
9d5c8243 2061 pci_set_master(pdev);
c682fc23 2062 pci_save_state(pdev);
9d5c8243
AK		 2063
2064 err = -ENOMEM;
1bfaf07b 2065 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2066 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2067 if (!netdev)
2068 goto err_alloc_etherdev;
2069
2070 SET_NETDEV_DEV(netdev, &pdev->dev);
2071
2072 pci_set_drvdata(pdev, netdev);
2073 adapter = netdev_priv(netdev);
2074 adapter->netdev = netdev;
2075 adapter->pdev = pdev;
2076 hw = &adapter->hw;
2077 hw->back = adapter;
b3f4d599 2078 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2079
2080 mmio_start = pci_resource_start(pdev, 0);
2081 mmio_len = pci_resource_len(pdev, 0);
2082
2083 err = -EIO;
28b0759c
AD		 2084 hw->hw_addr = ioremap(mmio_start, mmio_len);
2085 if (!hw->hw_addr)
9d5c8243
AK		 2086 goto err_ioremap;
2087
2e5c6922 2088 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2089 igb_set_ethtool_ops(netdev);
9d5c8243 2090 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2091
2092 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2093
2094 netdev->mem_start = mmio_start;
2095 netdev->mem_end = mmio_start + mmio_len;
2096
9d5c8243
AK		 2097 /* PCI config space info */
2098 hw->vendor_id = pdev->vendor;
2099 hw->device_id = pdev->device;
2100 hw->revision_id = pdev->revision;
2101 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2102 hw->subsystem_device_id = pdev->subsystem_device;
2103
9d5c8243
AK		 2104 /* Copy the default MAC, PHY and NVM function pointers */
2105 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2106 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2107 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2108 /* Initialize skew-specific constants */
2109 err = ei->get_invariants(hw);
2110 if (err)
450c87c8 2111 goto err_sw_init;
9d5c8243 2112
450c87c8 2113 /* setup the private structure */
9d5c8243
AK		 2114 err = igb_sw_init(adapter);
2115 if (err)
2116 goto err_sw_init;
2117
2118 igb_get_bus_info_pcie(hw);
2119
2120 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2121
2122 /* Copper options */
2123 if (hw->phy.media_type == e1000_media_type_copper) {
2124 hw->phy.mdix = AUTO_ALL_MODES;
2125 hw->phy.disable_polarity_correction = false;
2126 hw->phy.ms_type = e1000_ms_hw_default;
2127 }
2128
2129 if (igb_check_reset_block(hw))
2130 dev_info(&pdev->dev,
2131 "PHY reset is blocked due to SOL/IDER session.\n");
2132
b980ac18 2133 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2134 * set by igb_sw_init so we should use an or instead of an
2135 * assignment.
2136 */
2137 netdev->features |= NETIF_F_SG |
2138 NETIF_F_IP_CSUM |
2139 NETIF_F_IPV6_CSUM |
2140 NETIF_F_TSO |
2141 NETIF_F_TSO6 |
2142 NETIF_F_RXHASH |
2143 NETIF_F_RXCSUM |
f646968f
PM		 2144 NETIF_F_HW_VLAN_CTAG_RX |
2145 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2146
2147 /* copy netdev features into list of user selectable features */
2148 netdev->hw_features |= netdev->features;
89eaefb6 2149 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2150
2151 /* set this bit last since it cannot be part of hw_features */
f646968f 2152 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2153
2154 netdev->vlan_features |= NETIF_F_TSO |
2155 NETIF_F_TSO6 |
2156 NETIF_F_IP_CSUM |
2157 NETIF_F_IPV6_CSUM |
2158 NETIF_F_SG;
48f29ffc 2159
6b8f0922
BG		 2160 netdev->priv_flags |= IFF_SUPP_NOFCS;
2161
7b872a55 2162 if (pci_using_dac) {
9d5c8243 2163 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2164 netdev->vlan_features |= NETIF_F_HIGHDMA;
2165 }
9d5c8243 2166
ac52caa3
MM		 2167 if (hw->mac.type >= e1000_82576) {
2168 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2169 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2170 }
b9473560 2171
01789349
JP		 2172 netdev->priv_flags |= IFF_UNICAST_FLT;
2173
330a6d6a 2174 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2175
2176 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2177 * known good starting state
2178 */
9d5c8243
AK		 2179 hw->mac.ops.reset_hw(hw);
2180
ef3a0092
CW		 2181 /* make sure the NVM is good , i211/i210 parts can have special NVM
2182 * that doesn't contain a checksum
f96a8a0b 2183 */
ef3a0092
CW		 2184 switch (hw->mac.type) {
2185 case e1000_i210:
2186 case e1000_i211:
2187 if (igb_get_flash_presence_i210(hw)) {
2188 if (hw->nvm.ops.validate(hw) < 0) {
2189 dev_err(&pdev->dev,
2190 "The NVM Checksum Is Not Valid\n");
2191 err = -EIO;
2192 goto err_eeprom;
2193 }
2194 }
2195 break;
2196 default:
f96a8a0b
CW		 2197 if (hw->nvm.ops.validate(hw) < 0) {
2198 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2199 err = -EIO;
2200 goto err_eeprom;
2201 }
ef3a0092 2202 break;
9d5c8243
AK		 2203 }
2204
2205 /* copy the MAC address out of the NVM */
2206 if (hw->mac.ops.read_mac_addr(hw))
2207 dev_err(&pdev->dev, "NVM Read Error\n");
2208
2209 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2210
aaeb6cdf 2211 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2212 dev_err(&pdev->dev, "Invalid MAC Address\n");
2213 err = -EIO;
2214 goto err_eeprom;
2215 }
2216
d67974f0
CW		 2217 /* get firmware version for ethtool -i */
2218 igb_set_fw_version(adapter);
2219
c061b18d 2220 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2221 (unsigned long) adapter);
c061b18d 2222 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2223 (unsigned long) adapter);
9d5c8243
AK		 2224
2225 INIT_WORK(&adapter->reset_task, igb_reset_task);
2226 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2227
450c87c8 2228 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2229 adapter->fc_autoneg = true;
2230 hw->mac.autoneg = true;
2231 hw->phy.autoneg_advertised = 0x2f;
2232
0cce119a
AD		 2233 hw->fc.requested_mode = e1000_fc_default;
2234 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2235
9d5c8243
AK		 2236 igb_validate_mdi_setting(hw);
2237
63d4a8f9 2238 /* By default, support wake on port A */
a2cf8b6c 2239 if (hw->bus.func == 0)
63d4a8f9
MV		 2240 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2241
2242 /* Check the NVM for wake support on non-port A ports */
2243 if (hw->mac.type >= e1000_82580)
55cac248 2244 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2245 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2246 &eeprom_data);
a2cf8b6c
AD		 2247 else if (hw->bus.func == 1)
2248 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2249
63d4a8f9
MV		 2250 if (eeprom_data & IGB_EEPROM_APME)
2251 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2252
2253 /* now that we have the eeprom settings, apply the special cases where
2254 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2255 * lan on a particular port
2256 */
9d5c8243
AK		 2257 switch (pdev->device) {
2258 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2259 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2260 break;
2261 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2262 case E1000_DEV_ID_82576_FIBER:
2263 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2264 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2265 * regardless of eeprom setting
2266 */
9d5c8243 2267 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2268 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2269 break;
c8ea5ea9 2270 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2271 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2272 /* if quad port adapter, disable WoL on all but port A */
2273 if (global_quad_port_a != 0)
63d4a8f9 2274 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2275 else
2276 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2277 /* Reset for multiple quad port adapters */
2278 if (++global_quad_port_a == 4)
2279 global_quad_port_a = 0;
2280 break;
63d4a8f9
MV		 2281 default:
2282 /* If the device can't wake, don't set software support */
2283 if (!device_can_wakeup(&adapter->pdev->dev))
2284 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2285 }
2286
2287 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2288 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2289 adapter->wol |= E1000_WUFC_MAG;
2290
2291 /* Some vendors want WoL disabled by default, but still supported */
2292 if ((hw->mac.type == e1000_i350) &&
2293 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2294 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2295 adapter->wol = 0;
2296 }
2297
2298 device_set_wakeup_enable(&adapter->pdev->dev,
2299 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2300
2301 /* reset the hardware with the new settings */
2302 igb_reset(adapter);
2303
441fc6fd
CW		 2304 /* Init the I2C interface */
2305 err = igb_init_i2c(adapter);
2306 if (err) {
2307 dev_err(&pdev->dev, "failed to init i2c interface\n");
2308 goto err_eeprom;
2309 }
2310
9d5c8243
AK		 2311 /* let the f/w know that the h/w is now under the control of the
2312 * driver. */
2313 igb_get_hw_control(adapter);
2314
9d5c8243
AK		 2315 strcpy(netdev->name, "eth%d");
2316 err = register_netdev(netdev);
2317 if (err)
2318 goto err_register;
2319
b168dfc5
JB		 2320 /* carrier off reporting is important to ethtool even BEFORE open */
2321 netif_carrier_off(netdev);
2322
421e02f0 2323#ifdef CONFIG_IGB_DCA
bbd98fe4 2324 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2325 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2326 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2327 igb_setup_dca(adapter);
2328 }
fe4506b6 2329
38c845c7 2330#endif
e428893b
CW		 2331#ifdef CONFIG_IGB_HWMON
2332 /* Initialize the thermal sensor on i350 devices. */
2333 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2334 u16 ets_word;
3c89f6d0 2335
b980ac18 2336 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2337 * external thermal sensor.
2338 */
2339 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2340 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2341 adapter->ets = true;
2342 else
2343 adapter->ets = false;
2344 if (igb_sysfs_init(adapter))
2345 dev_err(&pdev->dev,
2346 "failed to allocate sysfs resources\n");
2347 } else {
2348 adapter->ets = false;
2349 }
2350#endif
673b8b70 2351 /* do hw tstamp init after resetting */
7ebae817 2352 igb_ptp_init(adapter);
673b8b70 2353
9d5c8243 2354 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2355 /* print bus type/speed/width info, not applicable to i354 */
2356 if (hw->mac.type != e1000_i354) {
2357 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2358 netdev->name,
2359 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2360 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2361 "unknown"),
2362 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2363 "Width x4" :
2364 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2365 "Width x2" :
2366 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2367 "Width x1" : "unknown"), netdev->dev_addr);
2368 }
9d5c8243 2369
53ea6c7e
TF		 2370 if ((hw->mac.type >= e1000_i210 ||
2371 igb_get_flash_presence_i210(hw))) {
2372 ret_val = igb_read_part_string(hw, part_str,
2373 E1000_PBANUM_LENGTH);
2374 } else {
2375 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2376 }
2377
9835fd73
CW		 2378 if (ret_val)
2379 strcpy(part_str, "Unknown");
2380 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2381 dev_info(&pdev->dev,
2382 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2383 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2384 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2385 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2386 switch (hw->mac.type) {
2387 case e1000_i350:
f96a8a0b
CW		 2388 case e1000_i210:
2389 case e1000_i211:
09b068d4
CW		 2390 igb_set_eee_i350(hw);
2391 break;
ceb5f13b
CW		 2392 case e1000_i354:
2393 if (hw->phy.media_type == e1000_media_type_copper) {
2394 if ((rd32(E1000_CTRL_EXT) &
2395 E1000_CTRL_EXT_LINK_MODE_SGMII))
2396 igb_set_eee_i354(hw);
2397 }
2398 break;
09b068d4
CW		 2399 default:
2400 break;
2401 }
749ab2cd
YZ		 2402
2403 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2404 return 0;
2405
2406err_register:
2407 igb_release_hw_control(adapter);
441fc6fd 2408 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2409err_eeprom:
2410 if (!igb_check_reset_block(hw))
f5f4cf08 2411 igb_reset_phy(hw);
9d5c8243
AK		 2412
2413 if (hw->flash_address)
2414 iounmap(hw->flash_address);
9d5c8243 2415err_sw_init:
047e0030 2416 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2417 iounmap(hw->hw_addr);
2418err_ioremap:
2419 free_netdev(netdev);
2420err_alloc_etherdev:
559e9c49 2421 pci_release_selected_regions(pdev,
b980ac18 2422 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2423err_pci_reg:
2424err_dma:
2425 pci_disable_device(pdev);
2426 return err;
2427}
2428
fa44f2f1
GR		 2429#ifdef CONFIG_PCI_IOV
2430static int igb_disable_sriov(struct pci_dev *pdev)
2431{
2432 struct net_device *netdev = pci_get_drvdata(pdev);
2433 struct igb_adapter *adapter = netdev_priv(netdev);
2434 struct e1000_hw *hw = &adapter->hw;
2435
2436 /* reclaim resources allocated to VFs */
2437 if (adapter->vf_data) {
2438 /* disable iov and allow time for transactions to clear */
b09186d2 2439 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2440 dev_warn(&pdev->dev,
2441 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2442 return -EPERM;
2443 } else {
2444 pci_disable_sriov(pdev);
2445 msleep(500);
2446 }
2447
2448 kfree(adapter->vf_data);
2449 adapter->vf_data = NULL;
2450 adapter->vfs_allocated_count = 0;
2451 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2452 wrfl();
2453 msleep(100);
2454 dev_info(&pdev->dev, "IOV Disabled\n");
2455
2456 /* Re-enable DMA Coalescing flag since IOV is turned off */
2457 adapter->flags |= IGB_FLAG_DMAC;
2458 }
2459
2460 return 0;
2461}
2462
2463static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2464{
2465 struct net_device *netdev = pci_get_drvdata(pdev);
2466 struct igb_adapter *adapter = netdev_priv(netdev);
2467 int old_vfs = pci_num_vf(pdev);
2468 int err = 0;
2469 int i;
2470
50267196
MW		 2471 if (!adapter->msix_entries) {
2472 err = -EPERM;
2473 goto out;
2474 }
2475
fa44f2f1
GR		 2476 if (!num_vfs)
2477 goto out;
2478 else if (old_vfs && old_vfs == num_vfs)
2479 goto out;
2480 else if (old_vfs && old_vfs != num_vfs)
2481 err = igb_disable_sriov(pdev);
2482
2483 if (err)
2484 goto out;
2485
2486 if (num_vfs > 7) {
2487 err = -EPERM;
2488 goto out;
2489 }
2490
2491 adapter->vfs_allocated_count = num_vfs;
2492
2493 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2494 sizeof(struct vf_data_storage), GFP_KERNEL);
2495
2496 /* if allocation failed then we do not support SR-IOV */
2497 if (!adapter->vf_data) {
2498 adapter->vfs_allocated_count = 0;
2499 dev_err(&pdev->dev,
2500 "Unable to allocate memory for VF Data Storage\n");
2501 err = -ENOMEM;
2502 goto out;
2503 }
2504
2505 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2506 if (err)
2507 goto err_out;
2508
2509 dev_info(&pdev->dev, "%d VFs allocated\n",
2510 adapter->vfs_allocated_count);
2511 for (i = 0; i < adapter->vfs_allocated_count; i++)
2512 igb_vf_configure(adapter, i);
2513
2514 /* DMA Coalescing is not supported in IOV mode. */
2515 adapter->flags &= ~IGB_FLAG_DMAC;
2516 goto out;
2517
2518err_out:
2519 kfree(adapter->vf_data);
2520 adapter->vf_data = NULL;
2521 adapter->vfs_allocated_count = 0;
2522out:
2523 return err;
2524}
2525
2526#endif
b980ac18 2527/**
441fc6fd
CW		 2528 * igb_remove_i2c - Cleanup I2C interface
2529 * @adapter: pointer to adapter structure
b980ac18 2530 **/
441fc6fd
CW		 2531static void igb_remove_i2c(struct igb_adapter *adapter)
2532{
441fc6fd
CW		 2533 /* free the adapter bus structure */
2534 i2c_del_adapter(&adapter->i2c_adap);
2535}
2536
9d5c8243 2537/**
b980ac18
JK		 2538 * igb_remove - Device Removal Routine
2539 * @pdev: PCI device information struct
9d5c8243 2540 *
b980ac18
JK		 2541 * igb_remove is called by the PCI subsystem to alert the driver
2542 * that it should release a PCI device. The could be caused by a
2543 * Hot-Plug event, or because the driver is going to be removed from
2544 * memory.
9d5c8243 2545 **/
9f9a12f8 2546static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2547{
2548 struct net_device *netdev = pci_get_drvdata(pdev);
2549 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2550 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2551
749ab2cd 2552 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2553#ifdef CONFIG_IGB_HWMON
2554 igb_sysfs_exit(adapter);
2555#endif
441fc6fd 2556 igb_remove_i2c(adapter);
a79f4f88 2557 igb_ptp_stop(adapter);
b980ac18 2558 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2559 * disable watchdog from being rescheduled.
2560 */
9d5c8243
AK		 2561 set_bit(__IGB_DOWN, &adapter->state);
2562 del_timer_sync(&adapter->watchdog_timer);
2563 del_timer_sync(&adapter->phy_info_timer);
2564
760141a5
TH		 2565 cancel_work_sync(&adapter->reset_task);
2566 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2567
421e02f0 2568#ifdef CONFIG_IGB_DCA
7dfc16fa 2569 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2570 dev_info(&pdev->dev, "DCA disabled\n");
2571 dca_remove_requester(&pdev->dev);
7dfc16fa 2572 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2573 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2574 }
2575#endif
2576
9d5c8243 2577 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2578 * would have already happened in close and is redundant.
2579 */
9d5c8243
AK		 2580 igb_release_hw_control(adapter);
2581
2582 unregister_netdev(netdev);
2583
047e0030 2584 igb_clear_interrupt_scheme(adapter);
9d5c8243 2585
37680117 2586#ifdef CONFIG_PCI_IOV
fa44f2f1 2587 igb_disable_sriov(pdev);
37680117 2588#endif
559e9c49 2589
28b0759c
AD		 2590 iounmap(hw->hw_addr);
2591 if (hw->flash_address)
2592 iounmap(hw->flash_address);
559e9c49 2593 pci_release_selected_regions(pdev,
b980ac18 2594 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2595
1128c756 2596 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2597 free_netdev(netdev);
2598
19d5afd4 2599 pci_disable_pcie_error_reporting(pdev);
40a914fa 2600
9d5c8243
AK		 2601 pci_disable_device(pdev);
2602}
2603
a6b623e0 2604/**
b980ac18
JK		 2605 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2606 * @adapter: board private structure to initialize
a6b623e0 2607 *
b980ac18
JK		 2608 * This function initializes the vf specific data storage and then attempts to
2609 * allocate the VFs. The reason for ordering it this way is because it is much
2610 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2611 * the memory for the VFs.
a6b623e0 2612 **/
9f9a12f8 2613static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2614{
2615#ifdef CONFIG_PCI_IOV
2616 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2617 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2618
f96a8a0b
CW		 2619 /* Virtualization features not supported on i210 family. */
2620 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2621 return;
2622
fa44f2f1 2623 pci_sriov_set_totalvfs(pdev, 7);
d5e51a10 2624 igb_enable_sriov(pdev, max_vfs);
0224d663 2625
a6b623e0
AD		 2626#endif /* CONFIG_PCI_IOV */
2627}
2628
fa44f2f1 2629static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2630{
2631 struct e1000_hw *hw = &adapter->hw;
374a542d 2632 u32 max_rss_queues;
9d5c8243 2633
374a542d 2634 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2635 switch (hw->mac.type) {
374a542d
MV		 2636 case e1000_i211:
2637 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2638 break;
2639 case e1000_82575:
f96a8a0b 2640 case e1000_i210:
374a542d
MV		 2641 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2642 break;
2643 case e1000_i350:
2644 /* I350 cannot do RSS and SR-IOV at the same time */
2645 if (!!adapter->vfs_allocated_count) {
2646 max_rss_queues = 1;
2647 break;
2648 }
2649 /* fall through */
2650 case e1000_82576:
2651 if (!!adapter->vfs_allocated_count) {
2652 max_rss_queues = 2;
2653 break;
2654 }
2655 /* fall through */
2656 case e1000_82580:
ceb5f13b 2657 case e1000_i354:
374a542d
MV		 2658 default:
2659 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2660 break;
374a542d
MV		 2661 }
2662
2663 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2664
2665 /* Determine if we need to pair queues. */
2666 switch (hw->mac.type) {
2667 case e1000_82575:
f96a8a0b 2668 case e1000_i211:
374a542d 2669 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2670 break;
374a542d 2671 case e1000_82576:
b980ac18 2672 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2673 * should pair the queues in order to conserve interrupts due
2674 * to limited supply.
2675 */
2676 if ((adapter->rss_queues > 1) &&
2677 (adapter->vfs_allocated_count > 6))
2678 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2679 /* fall through */
2680 case e1000_82580:
2681 case e1000_i350:
ceb5f13b 2682 case e1000_i354:
374a542d 2683 case e1000_i210:
f96a8a0b 2684 default:
b980ac18 2685 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2686 * order to conserve interrupts due to limited supply.
2687 */
2688 if (adapter->rss_queues > (max_rss_queues / 2))
2689 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2690 break;
2691 }
fa44f2f1
GR		 2692}
2693
2694/**
b980ac18
JK		 2695 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2696 * @adapter: board private structure to initialize
fa44f2f1 2697 *
b980ac18
JK		 2698 * igb_sw_init initializes the Adapter private data structure.
2699 * Fields are initialized based on PCI device information and
2700 * OS network device settings (MTU size).
fa44f2f1
GR		 2701 **/
2702static int igb_sw_init(struct igb_adapter *adapter)
2703{
2704 struct e1000_hw *hw = &adapter->hw;
2705 struct net_device *netdev = adapter->netdev;
2706 struct pci_dev *pdev = adapter->pdev;
2707
2708 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2709
2710 /* set default ring sizes */
2711 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2712 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2713
2714 /* set default ITR values */
2715 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2716 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2717
2718 /* set default work limits */
2719 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2720
2721 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2722 VLAN_HLEN;
2723 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2724
2725 spin_lock_init(&adapter->stats64_lock);
2726#ifdef CONFIG_PCI_IOV
2727 switch (hw->mac.type) {
2728 case e1000_82576:
2729 case e1000_i350:
2730 if (max_vfs > 7) {
2731 dev_warn(&pdev->dev,
2732 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2733 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2734 } else
2735 adapter->vfs_allocated_count = max_vfs;
2736 if (adapter->vfs_allocated_count)
2737 dev_warn(&pdev->dev,
2738 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2739 break;
2740 default:
2741 break;
2742 }
2743#endif /* CONFIG_PCI_IOV */
2744
2745 igb_init_queue_configuration(adapter);
a99955fc 2746
1128c756 2747 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2748 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2749 GFP_ATOMIC);
1128c756 2750
a6b623e0 2751 /* This call may decrease the number of queues */
53c7d064 2752 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2753 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2754 return -ENOMEM;
2755 }
2756
a6b623e0
AD		 2757 igb_probe_vfs(adapter);
2758
9d5c8243
AK		 2759 /* Explicitly disable IRQ since the NIC can be in any state. */
2760 igb_irq_disable(adapter);
2761
f96a8a0b 2762 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2763 adapter->flags &= ~IGB_FLAG_DMAC;
2764
9d5c8243
AK		 2765 set_bit(__IGB_DOWN, &adapter->state);
2766 return 0;
2767}
2768
2769/**
b980ac18
JK		 2770 * igb_open - Called when a network interface is made active
2771 * @netdev: network interface device structure
9d5c8243 2772 *
b980ac18 2773 * Returns 0 on success, negative value on failure
9d5c8243 2774 *
b980ac18
JK		 2775 * The open entry point is called when a network interface is made
2776 * active by the system (IFF_UP). At this point all resources needed
2777 * for transmit and receive operations are allocated, the interrupt
2778 * handler is registered with the OS, the watchdog timer is started,
2779 * and the stack is notified that the interface is ready.
9d5c8243 2780 **/
749ab2cd 2781static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2782{
2783 struct igb_adapter *adapter = netdev_priv(netdev);
2784 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2785 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2786 int err;
2787 int i;
2788
2789 /* disallow open during test */
749ab2cd
YZ		 2790 if (test_bit(__IGB_TESTING, &adapter->state)) {
2791 WARN_ON(resuming);
9d5c8243 2792 return -EBUSY;
749ab2cd
YZ		 2793 }
2794
2795 if (!resuming)
2796 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2797
b168dfc5
JB		 2798 netif_carrier_off(netdev);
2799
9d5c8243
AK		 2800 /* allocate transmit descriptors */
2801 err = igb_setup_all_tx_resources(adapter);
2802 if (err)
2803 goto err_setup_tx;
2804
2805 /* allocate receive descriptors */
2806 err = igb_setup_all_rx_resources(adapter);
2807 if (err)
2808 goto err_setup_rx;
2809
88a268c1 2810 igb_power_up_link(adapter);
9d5c8243 2811
9d5c8243
AK		 2812 /* before we allocate an interrupt, we must be ready to handle it.
2813 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2814 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2815 * clean_rx handler before we do so.
2816 */
9d5c8243
AK		 2817 igb_configure(adapter);
2818
2819 err = igb_request_irq(adapter);
2820 if (err)
2821 goto err_req_irq;
2822
0c2cc02e
AD		 2823 /* Notify the stack of the actual queue counts. */
2824 err = netif_set_real_num_tx_queues(adapter->netdev,
2825 adapter->num_tx_queues);
2826 if (err)
2827 goto err_set_queues;
2828
2829 err = netif_set_real_num_rx_queues(adapter->netdev,
2830 adapter->num_rx_queues);
2831 if (err)
2832 goto err_set_queues;
2833
9d5c8243
AK		 2834 /* From here on the code is the same as igb_up() */
2835 clear_bit(__IGB_DOWN, &adapter->state);
2836
0d1ae7f4
AD		 2837 for (i = 0; i < adapter->num_q_vectors; i++)
2838 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2839
2840 /* Clear any pending interrupts. */
2841 rd32(E1000_ICR);
844290e5
PW		 2842
2843 igb_irq_enable(adapter);
2844
d4960307
AD		 2845 /* notify VFs that reset has been completed */
2846 if (adapter->vfs_allocated_count) {
2847 u32 reg_data = rd32(E1000_CTRL_EXT);
2848 reg_data |= E1000_CTRL_EXT_PFRSTD;
2849 wr32(E1000_CTRL_EXT, reg_data);
2850 }
2851
d55b53ff
JK		 2852 netif_tx_start_all_queues(netdev);
2853
749ab2cd
YZ		 2854 if (!resuming)
2855 pm_runtime_put(&pdev->dev);
2856
25568a53
AD		 2857 /* start the watchdog. */
2858 hw->mac.get_link_status = 1;
2859 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2860
2861 return 0;
2862
0c2cc02e
AD		 2863err_set_queues:
2864 igb_free_irq(adapter);
9d5c8243
AK		 2865err_req_irq:
2866 igb_release_hw_control(adapter);
88a268c1 2867 igb_power_down_link(adapter);
9d5c8243
AK		 2868 igb_free_all_rx_resources(adapter);
2869err_setup_rx:
2870 igb_free_all_tx_resources(adapter);
2871err_setup_tx:
2872 igb_reset(adapter);
749ab2cd
YZ		 2873 if (!resuming)
2874 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2875
2876 return err;
2877}
2878
749ab2cd
YZ		 2879static int igb_open(struct net_device *netdev)
2880{
2881 return __igb_open(netdev, false);
2882}
2883
9d5c8243 2884/**
b980ac18
JK		 2885 * igb_close - Disables a network interface
2886 * @netdev: network interface device structure
9d5c8243 2887 *
b980ac18 2888 * Returns 0, this is not allowed to fail
9d5c8243 2889 *
b980ac18
JK		 2890 * The close entry point is called when an interface is de-activated
2891 * by the OS. The hardware is still under the driver's control, but
2892 * needs to be disabled. A global MAC reset is issued to stop the
2893 * hardware, and all transmit and receive resources are freed.
9d5c8243 2894 **/
749ab2cd 2895static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2896{
2897 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2898 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2899
2900 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2901
749ab2cd
YZ		 2902 if (!suspending)
2903 pm_runtime_get_sync(&pdev->dev);
2904
2905 igb_down(adapter);
9d5c8243
AK		 2906 igb_free_irq(adapter);
2907
2908 igb_free_all_tx_resources(adapter);
2909 igb_free_all_rx_resources(adapter);
2910
749ab2cd
YZ		 2911 if (!suspending)
2912 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2913 return 0;
2914}
2915
749ab2cd
YZ		 2916static int igb_close(struct net_device *netdev)
2917{
2918 return __igb_close(netdev, false);
2919}
2920
9d5c8243 2921/**
b980ac18
JK		 2922 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2923 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2924 *
b980ac18 2925 * Return 0 on success, negative on failure
9d5c8243 2926 **/
80785298 2927int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2928{
59d71989 2929 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2930 int size;
2931
06034649 2932 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2933
2934 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2935 if (!tx_ring->tx_buffer_info)
9d5c8243 2936 goto err;
9d5c8243
AK		 2937
2938 /* round up to nearest 4K */
85e8d004 2939 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2940 tx_ring->size = ALIGN(tx_ring->size, 4096);
2941
5536d210
AD		 2942 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2943 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2944 if (!tx_ring->desc)
2945 goto err;
2946
9d5c8243
AK		 2947 tx_ring->next_to_use = 0;
2948 tx_ring->next_to_clean = 0;
81c2fc22 2949
9d5c8243
AK		 2950 return 0;
2951
2952err:
06034649 2953 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2954 tx_ring->tx_buffer_info = NULL;
2955 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2956 return -ENOMEM;
2957}
2958
2959/**
b980ac18
JK		 2960 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2961 * (Descriptors) for all queues
2962 * @adapter: board private structure
9d5c8243 2963 *
b980ac18 2964 * Return 0 on success, negative on failure
9d5c8243
AK		 2965 **/
2966static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2967{
439705e1 2968 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2969 int i, err = 0;
2970
2971 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2972 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2973 if (err) {
439705e1 2974 dev_err(&pdev->dev,
9d5c8243
AK		 2975 "Allocation for Tx Queue %u failed\n", i);
2976 for (i--; i >= 0; i--)
3025a446 2977 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2978 break;
2979 }
2980 }
2981
2982 return err;
2983}
2984
2985/**
b980ac18
JK		 2986 * igb_setup_tctl - configure the transmit control registers
2987 * @adapter: Board private structure
9d5c8243 2988 **/
d7ee5b3a 2989void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2990{
9d5c8243
AK		 2991 struct e1000_hw *hw = &adapter->hw;
2992 u32 tctl;
9d5c8243 2993
85b430b4
AD		 2994 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2995 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2996
2997 /* Program the Transmit Control Register */
9d5c8243
AK		 2998 tctl = rd32(E1000_TCTL);
2999 tctl &= ~E1000_TCTL_CT;
3000 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3001 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3002
3003 igb_config_collision_dist(hw);
3004
9d5c8243
AK		 3005 /* Enable transmits */
3006 tctl |= E1000_TCTL_EN;
3007
3008 wr32(E1000_TCTL, tctl);
3009}
3010
85b430b4 3011/**
b980ac18
JK		 3012 * igb_configure_tx_ring - Configure transmit ring after Reset
3013 * @adapter: board private structure
3014 * @ring: tx ring to configure
85b430b4 3015 *
b980ac18 3016 * Configure a transmit ring after a reset.
85b430b4 3017 **/
d7ee5b3a
AD		 3018void igb_configure_tx_ring(struct igb_adapter *adapter,
3019 struct igb_ring *ring)
85b430b4
AD		 3020{
3021 struct e1000_hw *hw = &adapter->hw;
a74420e0 3022 u32 txdctl = 0;
85b430b4
AD		 3023 u64 tdba = ring->dma;
3024 int reg_idx = ring->reg_idx;
3025
3026 /* disable the queue */
a74420e0 3027 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3028 wrfl();
3029 mdelay(10);
3030
3031 wr32(E1000_TDLEN(reg_idx),
b980ac18 3032 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3033 wr32(E1000_TDBAL(reg_idx),
b980ac18 3034 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3035 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3036
fce99e34 3037 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3038 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3039 writel(0, ring->tail);
85b430b4
AD		 3040
3041 txdctl |= IGB_TX_PTHRESH;
3042 txdctl |= IGB_TX_HTHRESH << 8;
3043 txdctl |= IGB_TX_WTHRESH << 16;
3044
3045 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3046 wr32(E1000_TXDCTL(reg_idx), txdctl);
3047}
3048
3049/**
b980ac18
JK		 3050 * igb_configure_tx - Configure transmit Unit after Reset
3051 * @adapter: board private structure
85b430b4 3052 *
b980ac18 3053 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3054 **/
3055static void igb_configure_tx(struct igb_adapter *adapter)
3056{
3057 int i;
3058
3059 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3060 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3061}
3062
9d5c8243 3063/**
b980ac18
JK		 3064 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3065 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3066 *
b980ac18 3067 * Returns 0 on success, negative on failure
9d5c8243 3068 **/
80785298 3069int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3070{
59d71989 3071 struct device *dev = rx_ring->dev;
f33005a6 3072 int size;
9d5c8243 3073
06034649 3074 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3075
3076 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3077 if (!rx_ring->rx_buffer_info)
9d5c8243 3078 goto err;
9d5c8243 3079
9d5c8243 3080 /* Round up to nearest 4K */
f33005a6 3081 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3082 rx_ring->size = ALIGN(rx_ring->size, 4096);
3083
5536d210
AD		 3084 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3085 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3086 if (!rx_ring->desc)
3087 goto err;
3088
cbc8e55f 3089 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3090 rx_ring->next_to_clean = 0;
3091 rx_ring->next_to_use = 0;
9d5c8243 3092
9d5c8243
AK		 3093 return 0;
3094
3095err:
06034649
AD		 3096 vfree(rx_ring->rx_buffer_info);
3097 rx_ring->rx_buffer_info = NULL;
f33005a6 3098 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3099 return -ENOMEM;
3100}
3101
3102/**
b980ac18
JK		 3103 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3104 * (Descriptors) for all queues
3105 * @adapter: board private structure
9d5c8243 3106 *
b980ac18 3107 * Return 0 on success, negative on failure
9d5c8243
AK		 3108 **/
3109static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3110{
439705e1 3111 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3112 int i, err = 0;
3113
3114 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3115 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3116 if (err) {
439705e1 3117 dev_err(&pdev->dev,
9d5c8243
AK		 3118 "Allocation for Rx Queue %u failed\n", i);
3119 for (i--; i >= 0; i--)
3025a446 3120 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3121 break;
3122 }
3123 }
3124
3125 return err;
3126}
3127
06cf2666 3128/**
b980ac18
JK		 3129 * igb_setup_mrqc - configure the multiple receive queue control registers
3130 * @adapter: Board private structure
06cf2666
AD		 3131 **/
3132static void igb_setup_mrqc(struct igb_adapter *adapter)
3133{
3134 struct e1000_hw *hw = &adapter->hw;
3135 u32 mrqc, rxcsum;
ed12cc9a 3136 u32 j, num_rx_queues;
a57fe23e
AD		 3137 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3138 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3139 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3140 0xFA01ACBE };
06cf2666
AD		 3141
3142 /* Fill out hash function seeds */
a57fe23e
AD		 3143 for (j = 0; j < 10; j++)
3144 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3145
a99955fc 3146 num_rx_queues = adapter->rss_queues;
06cf2666 3147
797fd4be 3148 switch (hw->mac.type) {
797fd4be
AD		 3149 case e1000_82576:
3150 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3151 if (adapter->vfs_allocated_count)
06cf2666 3152 num_rx_queues = 2;
797fd4be
AD		 3153 break;
3154 default:
3155 break;
06cf2666
AD		 3156 }
3157
ed12cc9a
LMV		 3158 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3159 for (j = 0; j < IGB_RETA_SIZE; j++)
3160 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3161 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3162 }
ed12cc9a 3163 igb_write_rss_indir_tbl(adapter);
06cf2666 3164
b980ac18 3165 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3166 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3167 * offloads as they are enabled by default
3168 */
3169 rxcsum = rd32(E1000_RXCSUM);
3170 rxcsum |= E1000_RXCSUM_PCSD;
3171
3172 if (adapter->hw.mac.type >= e1000_82576)
3173 /* Enable Receive Checksum Offload for SCTP */
3174 rxcsum |= E1000_RXCSUM_CRCOFL;
3175
3176 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3177 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3178
039454a8
AA		 3179 /* Generate RSS hash based on packet types, TCP/UDP
3180 * port numbers and/or IPv4/v6 src and dst addresses
3181 */
f96a8a0b
CW		 3182 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3183 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3184 E1000_MRQC_RSS_FIELD_IPV6 |
3185 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3186 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3187
039454a8
AA		 3188 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3189 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3190 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3191 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3192
06cf2666
AD		 3193 /* If VMDq is enabled then we set the appropriate mode for that, else
3194 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3195 * if we are only using one queue
3196 */
06cf2666
AD		 3197 if (adapter->vfs_allocated_count) {
3198 if (hw->mac.type > e1000_82575) {
3199 /* Set the default pool for the PF's first queue */
3200 u32 vtctl = rd32(E1000_VT_CTL);
3201 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3202 E1000_VT_CTL_DISABLE_DEF_POOL);
3203 vtctl |= adapter->vfs_allocated_count <<
3204 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3205 wr32(E1000_VT_CTL, vtctl);
3206 }
a99955fc 3207 if (adapter->rss_queues > 1)
f96a8a0b 3208 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3209 else
f96a8a0b 3210 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3211 } else {
f96a8a0b
CW		 3212 if (hw->mac.type != e1000_i211)
3213 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3214 }
3215 igb_vmm_control(adapter);
3216
06cf2666
AD		 3217 wr32(E1000_MRQC, mrqc);
3218}
3219
9d5c8243 3220/**
b980ac18
JK		 3221 * igb_setup_rctl - configure the receive control registers
3222 * @adapter: Board private structure
9d5c8243 3223 **/
d7ee5b3a 3224void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3225{
3226 struct e1000_hw *hw = &adapter->hw;
3227 u32 rctl;
9d5c8243
AK		 3228
3229 rctl = rd32(E1000_RCTL);
3230
3231 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3232 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3233
69d728ba 3234 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3235 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3236
b980ac18 3237 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3238 * redirection as it did with e1000. Newer features require
3239 * that the HW strips the CRC.
73cd78f1 3240 */
87cb7e8c 3241 rctl |= E1000_RCTL_SECRC;
9d5c8243 3242
559e9c49 3243 /* disable store bad packets and clear size bits. */
ec54d7d6 3244 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3245
6ec43fe6
AD		 3246 /* enable LPE to prevent packets larger than max_frame_size */
3247 rctl |= E1000_RCTL_LPE;
9d5c8243 3248
952f72a8
AD		 3249 /* disable queue 0 to prevent tail write w/o re-config */
3250 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3251
e1739522
AD		 3252 /* Attention!!! For SR-IOV PF driver operations you must enable
3253 * queue drop for all VF and PF queues to prevent head of line blocking
3254 * if an un-trusted VF does not provide descriptors to hardware.
3255 */
3256 if (adapter->vfs_allocated_count) {
e1739522
AD		 3257 /* set all queue drop enable bits */
3258 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3259 }
3260
89eaefb6
BG		 3261 /* This is useful for sniffing bad packets. */
3262 if (adapter->netdev->features & NETIF_F_RXALL) {
3263 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3264 * in e1000e_set_rx_mode
3265 */
89eaefb6
BG		 3266 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3267 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3268 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3269
3270 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3271 E1000_RCTL_DPF | /* Allow filtered pause */
3272 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3273 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3274 * and that breaks VLANs.
3275 */
3276 }
3277
9d5c8243
AK		 3278 wr32(E1000_RCTL, rctl);
3279}
3280
7d5753f0
AD		 3281static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3282 int vfn)
3283{
3284 struct e1000_hw *hw = &adapter->hw;
3285 u32 vmolr;
3286
3287 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3288 * increase the size to support vlan tags
3289 */
7d5753f0
AD		 3290 if (vfn < adapter->vfs_allocated_count &&
3291 adapter->vf_data[vfn].vlans_enabled)
3292 size += VLAN_TAG_SIZE;
3293
3294 vmolr = rd32(E1000_VMOLR(vfn));
3295 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3296 vmolr |= size | E1000_VMOLR_LPE;
3297 wr32(E1000_VMOLR(vfn), vmolr);
3298
3299 return 0;
3300}
3301
e1739522 3302/**
b980ac18
JK		 3303 * igb_rlpml_set - set maximum receive packet size
3304 * @adapter: board private structure
e1739522 3305 *
b980ac18 3306 * Configure maximum receivable packet size.
e1739522
AD		 3307 **/
3308static void igb_rlpml_set(struct igb_adapter *adapter)
3309{
153285f9 3310 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3311 struct e1000_hw *hw = &adapter->hw;
3312 u16 pf_id = adapter->vfs_allocated_count;
3313
e1739522
AD		 3314 if (pf_id) {
3315 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3316 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3317 * to our max jumbo frame size, in case we need to enable
3318 * jumbo frames on one of the rings later.
3319 * This will not pass over-length frames into the default
3320 * queue because it's gated by the VMOLR.RLPML.
3321 */
7d5753f0 3322 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3323 }
3324
3325 wr32(E1000_RLPML, max_frame_size);
3326}
3327
8151d294
WM		 3328static inline void igb_set_vmolr(struct igb_adapter *adapter,
3329 int vfn, bool aupe)
7d5753f0
AD		 3330{
3331 struct e1000_hw *hw = &adapter->hw;
3332 u32 vmolr;
3333
b980ac18 3334 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3335 * we should exit and do nothing
3336 */
3337 if (hw->mac.type < e1000_82576)
3338 return;
3339
3340 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3341 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3342 if (aupe)
b980ac18 3343 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3344 else
3345 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3346
3347 /* clear all bits that might not be set */
3348 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3349
a99955fc 3350 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3351 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3352 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3353 * multicast packets
3354 */
3355 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3356 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3357
3358 wr32(E1000_VMOLR(vfn), vmolr);
3359}
3360
85b430b4 3361/**
b980ac18
JK		 3362 * igb_configure_rx_ring - Configure a receive ring after Reset
3363 * @adapter: board private structure
3364 * @ring: receive ring to be configured
85b430b4 3365 *
b980ac18 3366 * Configure the Rx unit of the MAC after a reset.
85b430b4 3367 **/
d7ee5b3a 3368void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3369 struct igb_ring *ring)
85b430b4
AD		 3370{
3371 struct e1000_hw *hw = &adapter->hw;
3372 u64 rdba = ring->dma;
3373 int reg_idx = ring->reg_idx;
a74420e0 3374 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3375
3376 /* disable the queue */
a74420e0 3377 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3378
3379 /* Set DMA base address registers */
3380 wr32(E1000_RDBAL(reg_idx),
3381 rdba & 0x00000000ffffffffULL);
3382 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3383 wr32(E1000_RDLEN(reg_idx),
b980ac18 3384 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3385
3386 /* initialize head and tail */
fce99e34 3387 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3388 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3389 writel(0, ring->tail);
85b430b4 3390
952f72a8 3391 /* set descriptor configuration */
44390ca6 3392 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3393 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3394 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3395 if (hw->mac.type >= e1000_82580)
757b77e2 3396 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3397 /* Only set Drop Enable if we are supporting multiple queues */
3398 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3399 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3400
3401 wr32(E1000_SRRCTL(reg_idx), srrctl);
3402
7d5753f0 3403 /* set filtering for VMDQ pools */
8151d294 3404 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3405
85b430b4
AD		 3406 rxdctl |= IGB_RX_PTHRESH;
3407 rxdctl |= IGB_RX_HTHRESH << 8;
3408 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3409
3410 /* enable receive descriptor fetching */
3411 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3412 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3413}
3414
9d5c8243 3415/**
b980ac18
JK		 3416 * igb_configure_rx - Configure receive Unit after Reset
3417 * @adapter: board private structure
9d5c8243 3418 *
b980ac18 3419 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3420 **/
3421static void igb_configure_rx(struct igb_adapter *adapter)
3422{
9107584e 3423 int i;
9d5c8243 3424
68d480c4
AD		 3425 /* set UTA to appropriate mode */
3426 igb_set_uta(adapter);
3427
26ad9178
AD		 3428 /* set the correct pool for the PF default MAC address in entry 0 */
3429 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3430 adapter->vfs_allocated_count);
26ad9178 3431
06cf2666 3432 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3433 * the Base and Length of the Rx Descriptor Ring
3434 */
f9d40f6a
AD		 3435 for (i = 0; i < adapter->num_rx_queues; i++)
3436 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3437}
3438
3439/**
b980ac18
JK		 3440 * igb_free_tx_resources - Free Tx Resources per Queue
3441 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3442 *
b980ac18 3443 * Free all transmit software resources
9d5c8243 3444 **/
68fd9910 3445void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3446{
3b644cf6 3447 igb_clean_tx_ring(tx_ring);
9d5c8243 3448
06034649
AD		 3449 vfree(tx_ring->tx_buffer_info);
3450 tx_ring->tx_buffer_info = NULL;
9d5c8243 3451
439705e1
AD		 3452 /* if not set, then don't free */
3453 if (!tx_ring->desc)
3454 return;
3455
59d71989
AD		 3456 dma_free_coherent(tx_ring->dev, tx_ring->size,
3457 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3458
3459 tx_ring->desc = NULL;
3460}
3461
3462/**
b980ac18
JK		 3463 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3464 * @adapter: board private structure
9d5c8243 3465 *
b980ac18 3466 * Free all transmit software resources
9d5c8243
AK		 3467 **/
3468static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3469{
3470 int i;
3471
3472 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3473 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3474}
3475
ebe42d16
AD		 3476void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3477 struct igb_tx_buffer *tx_buffer)
3478{
3479 if (tx_buffer->skb) {
3480 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3481 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3482 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3483 dma_unmap_addr(tx_buffer, dma),
3484 dma_unmap_len(tx_buffer, len),
ebe42d16 3485 DMA_TO_DEVICE);
c9f14bf3 3486 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3487 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3488 dma_unmap_addr(tx_buffer, dma),
3489 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3490 DMA_TO_DEVICE);
3491 }
3492 tx_buffer->next_to_watch = NULL;
3493 tx_buffer->skb = NULL;
c9f14bf3 3494 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3495 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3496}
3497
3498/**
b980ac18
JK		 3499 * igb_clean_tx_ring - Free Tx Buffers
3500 * @tx_ring: ring to be cleaned
9d5c8243 3501 **/
3b644cf6 3502static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3503{
06034649 3504 struct igb_tx_buffer *buffer_info;
9d5c8243 3505 unsigned long size;
6ad4edfc 3506 u16 i;
9d5c8243 3507
06034649 3508 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3509 return;
3510 /* Free all the Tx ring sk_buffs */
3511
3512 for (i = 0; i < tx_ring->count; i++) {
06034649 3513 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3514 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3515 }
3516
dad8a3b3
JF		 3517 netdev_tx_reset_queue(txring_txq(tx_ring));
3518
06034649
AD		 3519 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3520 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3521
3522 /* Zero out the descriptor ring */
9d5c8243
AK		 3523 memset(tx_ring->desc, 0, tx_ring->size);
3524
3525 tx_ring->next_to_use = 0;
3526 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3527}
3528
3529/**
b980ac18
JK		 3530 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3531 * @adapter: board private structure
9d5c8243
AK		 3532 **/
3533static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3534{
3535 int i;
3536
3537 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3538 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3539}
3540
3541/**
b980ac18
JK		 3542 * igb_free_rx_resources - Free Rx Resources
3543 * @rx_ring: ring to clean the resources from
9d5c8243 3544 *
b980ac18 3545 * Free all receive software resources
9d5c8243 3546 **/
68fd9910 3547void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3548{
3b644cf6 3549 igb_clean_rx_ring(rx_ring);
9d5c8243 3550
06034649
AD		 3551 vfree(rx_ring->rx_buffer_info);
3552 rx_ring->rx_buffer_info = NULL;
9d5c8243 3553
439705e1
AD		 3554 /* if not set, then don't free */
3555 if (!rx_ring->desc)
3556 return;
3557
59d71989
AD		 3558 dma_free_coherent(rx_ring->dev, rx_ring->size,
3559 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3560
3561 rx_ring->desc = NULL;
3562}
3563
3564/**
b980ac18
JK		 3565 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3566 * @adapter: board private structure
9d5c8243 3567 *
b980ac18 3568 * Free all receive software resources
9d5c8243
AK		 3569 **/
3570static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3571{
3572 int i;
3573
3574 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3575 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3576}
3577
3578/**
b980ac18
JK		 3579 * igb_clean_rx_ring - Free Rx Buffers per Queue
3580 * @rx_ring: ring to free buffers from
9d5c8243 3581 **/
3b644cf6 3582static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3583{
9d5c8243 3584 unsigned long size;
c023cd88 3585 u16 i;
9d5c8243 3586
1a1c225b
AD		 3587 if (rx_ring->skb)
3588 dev_kfree_skb(rx_ring->skb);
3589 rx_ring->skb = NULL;
3590
06034649 3591 if (!rx_ring->rx_buffer_info)
9d5c8243 3592 return;
439705e1 3593
9d5c8243
AK		 3594 /* Free all the Rx ring sk_buffs */
3595 for (i = 0; i < rx_ring->count; i++) {
06034649 3596 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3597
cbc8e55f
AD		 3598 if (!buffer_info->page)
3599 continue;
3600
3601 dma_unmap_page(rx_ring->dev,
3602 buffer_info->dma,
3603 PAGE_SIZE,
3604 DMA_FROM_DEVICE);
3605 __free_page(buffer_info->page);
3606
1a1c225b 3607 buffer_info->page = NULL;
9d5c8243
AK		 3608 }
3609
06034649
AD		 3610 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3611 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3612
3613 /* Zero out the descriptor ring */
3614 memset(rx_ring->desc, 0, rx_ring->size);
3615
cbc8e55f 3616 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3617 rx_ring->next_to_clean = 0;
3618 rx_ring->next_to_use = 0;
9d5c8243
AK		 3619}
3620
3621/**
b980ac18
JK		 3622 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3623 * @adapter: board private structure
9d5c8243
AK		 3624 **/
3625static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3626{
3627 int i;
3628
3629 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3630 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3631}
3632
3633/**
b980ac18
JK		 3634 * igb_set_mac - Change the Ethernet Address of the NIC
3635 * @netdev: network interface device structure
3636 * @p: pointer to an address structure
9d5c8243 3637 *
b980ac18 3638 * Returns 0 on success, negative on failure
9d5c8243
AK		 3639 **/
3640static int igb_set_mac(struct net_device *netdev, void *p)
3641{
3642 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3643 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3644 struct sockaddr *addr = p;
3645
3646 if (!is_valid_ether_addr(addr->sa_data))
3647 return -EADDRNOTAVAIL;
3648
3649 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3650 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3651
26ad9178
AD		 3652 /* set the correct pool for the new PF MAC address in entry 0 */
3653 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3654 adapter->vfs_allocated_count);
e1739522 3655
9d5c8243
AK		 3656 return 0;
3657}
3658
3659/**
b980ac18
JK		 3660 * igb_write_mc_addr_list - write multicast addresses to MTA
3661 * @netdev: network interface device structure
9d5c8243 3662 *
b980ac18
JK		 3663 * Writes multicast address list to the MTA hash table.
3664 * Returns: -ENOMEM on failure
3665 * 0 on no addresses written
3666 * X on writing X addresses to MTA
9d5c8243 3667 **/
68d480c4 3668static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3669{
3670 struct igb_adapter *adapter = netdev_priv(netdev);
3671 struct e1000_hw *hw = &adapter->hw;
22bedad3 3672 struct netdev_hw_addr *ha;
68d480c4 3673 u8 *mta_list;
9d5c8243
AK		 3674 int i;
3675
4cd24eaf 3676 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3677 /* nothing to program, so clear mc list */
3678 igb_update_mc_addr_list(hw, NULL, 0);
3679 igb_restore_vf_multicasts(adapter);
3680 return 0;
3681 }
9d5c8243 3682
4cd24eaf 3683 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3684 if (!mta_list)
3685 return -ENOMEM;
ff41f8dc 3686
68d480c4 3687 /* The shared function expects a packed array of only addresses. */
48e2f183 3688 i = 0;
22bedad3
JP		 3689 netdev_for_each_mc_addr(ha, netdev)
3690 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3691
68d480c4
AD		 3692 igb_update_mc_addr_list(hw, mta_list, i);
3693 kfree(mta_list);
3694
4cd24eaf 3695 return netdev_mc_count(netdev);
68d480c4
AD		 3696}
3697
3698/**
b980ac18
JK		 3699 * igb_write_uc_addr_list - write unicast addresses to RAR table
3700 * @netdev: network interface device structure
68d480c4 3701 *
b980ac18
JK		 3702 * Writes unicast address list to the RAR table.
3703 * Returns: -ENOMEM on failure/insufficient address space
3704 * 0 on no addresses written
3705 * X on writing X addresses to the RAR table
68d480c4
AD		 3706 **/
3707static int igb_write_uc_addr_list(struct net_device *netdev)
3708{
3709 struct igb_adapter *adapter = netdev_priv(netdev);
3710 struct e1000_hw *hw = &adapter->hw;
3711 unsigned int vfn = adapter->vfs_allocated_count;
3712 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3713 int count = 0;
3714
3715 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3716 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3717 return -ENOMEM;
9d5c8243 3718
32e7bfc4 3719 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3720 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3721
3722 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3723 if (!rar_entries)
3724 break;
26ad9178 3725 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3726 rar_entries--,
3727 vfn);
68d480c4 3728 count++;
ff41f8dc
AD		 3729 }
3730 }
3731 /* write the addresses in reverse order to avoid write combining */
3732 for (; rar_entries > 0 ; rar_entries--) {
3733 wr32(E1000_RAH(rar_entries), 0);
3734 wr32(E1000_RAL(rar_entries), 0);
3735 }
3736 wrfl();
3737
68d480c4
AD		 3738 return count;
3739}
3740
3741/**
b980ac18
JK		 3742 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3743 * @netdev: network interface device structure
68d480c4 3744 *
b980ac18
JK		 3745 * The set_rx_mode entry point is called whenever the unicast or multicast
3746 * address lists or the network interface flags are updated. This routine is
3747 * responsible for configuring the hardware for proper unicast, multicast,
3748 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3749 **/
3750static void igb_set_rx_mode(struct net_device *netdev)
3751{
3752 struct igb_adapter *adapter = netdev_priv(netdev);
3753 struct e1000_hw *hw = &adapter->hw;
3754 unsigned int vfn = adapter->vfs_allocated_count;
3755 u32 rctl, vmolr = 0;
3756 int count;
3757
3758 /* Check for Promiscuous and All Multicast modes */
3759 rctl = rd32(E1000_RCTL);
3760
3761 /* clear the effected bits */
3762 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3763
3764 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3765 /* retain VLAN HW filtering if in VT mode */
7e44892c 3766 if (adapter->vfs_allocated_count)
6f3dc319 3767 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3768 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3769 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3770 } else {
3771 if (netdev->flags & IFF_ALLMULTI) {
3772 rctl |= E1000_RCTL_MPE;
3773 vmolr |= E1000_VMOLR_MPME;
3774 } else {
b980ac18 3775 /* Write addresses to the MTA, if the attempt fails
25985edc 3776 * then we should just turn on promiscuous mode so
68d480c4
AD		 3777 * that we can at least receive multicast traffic
3778 */
3779 count = igb_write_mc_addr_list(netdev);
3780 if (count < 0) {
3781 rctl |= E1000_RCTL_MPE;
3782 vmolr |= E1000_VMOLR_MPME;
3783 } else if (count) {
3784 vmolr |= E1000_VMOLR_ROMPE;
3785 }
3786 }
b980ac18 3787 /* Write addresses to available RAR registers, if there is not
68d480c4 3788 * sufficient space to store all the addresses then enable
25985edc 3789 * unicast promiscuous mode
68d480c4
AD		 3790 */
3791 count = igb_write_uc_addr_list(netdev);
3792 if (count < 0) {
3793 rctl |= E1000_RCTL_UPE;
3794 vmolr |= E1000_VMOLR_ROPE;
3795 }
3796 rctl |= E1000_RCTL_VFE;
28fc06f5 3797 }
68d480c4 3798 wr32(E1000_RCTL, rctl);
28fc06f5 3799
b980ac18 3800 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3801 * the VMOLR to enable the appropriate modes. Without this workaround
3802 * we will have issues with VLAN tag stripping not being done for frames
3803 * that are only arriving because we are the default pool
3804 */
f96a8a0b 3805 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3806 return;
9d5c8243 3807
68d480c4 3808 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3809 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3810 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3811 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3812}
3813
13800469
GR		 3814static void igb_check_wvbr(struct igb_adapter *adapter)
3815{
3816 struct e1000_hw *hw = &adapter->hw;
3817 u32 wvbr = 0;
3818
3819 switch (hw->mac.type) {
3820 case e1000_82576:
3821 case e1000_i350:
3822 if (!(wvbr = rd32(E1000_WVBR)))
3823 return;
3824 break;
3825 default:
3826 break;
3827 }
3828
3829 adapter->wvbr |= wvbr;
3830}
3831
3832#define IGB_STAGGERED_QUEUE_OFFSET 8
3833
3834static void igb_spoof_check(struct igb_adapter *adapter)
3835{
3836 int j;
3837
3838 if (!adapter->wvbr)
3839 return;
3840
3841 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3842 if (adapter->wvbr & (1 << j) ||
3843 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3844 dev_warn(&adapter->pdev->dev,
3845 "Spoof event(s) detected on VF %d\n", j);
3846 adapter->wvbr &=
3847 ~((1 << j) |
3848 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3849 }
3850 }
3851}
3852
9d5c8243 3853/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3854 * the phy
3855 */
9d5c8243
AK		 3856static void igb_update_phy_info(unsigned long data)
3857{
3858 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3859 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3860}
3861
4d6b725e 3862/**
b980ac18
JK		 3863 * igb_has_link - check shared code for link and determine up/down
3864 * @adapter: pointer to driver private info
4d6b725e 3865 **/
3145535a 3866bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3867{
3868 struct e1000_hw *hw = &adapter->hw;
3869 bool link_active = false;
4d6b725e
AD		 3870
3871 /* get_link_status is set on LSC (link status) interrupt or
3872 * rx sequence error interrupt. get_link_status will stay
3873 * false until the e1000_check_for_link establishes link
3874 * for copper adapters ONLY
3875 */
3876 switch (hw->phy.media_type) {
3877 case e1000_media_type_copper:
e5c3370f
AA		 3878 if (!hw->mac.get_link_status)
3879 return true;
4d6b725e 3880 case e1000_media_type_internal_serdes:
e5c3370f
AA		 3881 hw->mac.ops.check_for_link(hw);
3882 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 3883 break;
3884 default:
3885 case e1000_media_type_unknown:
3886 break;
3887 }
3888
3889 return link_active;
3890}
3891
563988dc
SA		 3892static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3893{
3894 bool ret = false;
3895 u32 ctrl_ext, thstat;
3896
f96a8a0b 3897 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3898 if (hw->mac.type == e1000_i350) {
3899 thstat = rd32(E1000_THSTAT);
3900 ctrl_ext = rd32(E1000_CTRL_EXT);
3901
3902 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3903 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3904 ret = !!(thstat & event);
563988dc
SA		 3905 }
3906
3907 return ret;
3908}
3909
9d5c8243 3910/**
b980ac18
JK		 3911 * igb_watchdog - Timer Call-back
3912 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3913 **/
3914static void igb_watchdog(unsigned long data)
3915{
3916 struct igb_adapter *adapter = (struct igb_adapter *)data;
3917 /* Do the rest outside of interrupt context */
3918 schedule_work(&adapter->watchdog_task);
3919}
3920
3921static void igb_watchdog_task(struct work_struct *work)
3922{
3923 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3924 struct igb_adapter,
3925 watchdog_task);
9d5c8243 3926 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3927 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3928 struct net_device *netdev = adapter->netdev;
563988dc 3929 u32 link;
7a6ea550 3930 int i;
9d5c8243 3931
4d6b725e 3932 link = igb_has_link(adapter);
9d5c8243 3933 if (link) {
749ab2cd
YZ		 3934 /* Cancel scheduled suspend requests. */
3935 pm_runtime_resume(netdev->dev.parent);
3936
9d5c8243
AK		 3937 if (!netif_carrier_ok(netdev)) {
3938 u32 ctrl;
330a6d6a 3939 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3940 &adapter->link_speed,
3941 &adapter->link_duplex);
9d5c8243
AK		 3942
3943 ctrl = rd32(E1000_CTRL);
527d47c1 3944 /* Links status message must follow this format */
876d2d6f
JK		 3945 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3946 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3947 netdev->name,
3948 adapter->link_speed,
3949 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3950 "Full" : "Half",
3951 (ctrl & E1000_CTRL_TFCE) &&
3952 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3953 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3954 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3955
c0ba4778
KS		 3956 /* check if SmartSpeed worked */
3957 igb_check_downshift(hw);
3958 if (phy->speed_downgraded)
3959 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3960
563988dc 3961 /* check for thermal sensor event */
876d2d6f
JK		 3962 if (igb_thermal_sensor_event(hw,
3963 E1000_THSTAT_LINK_THROTTLE)) {
3964 netdev_info(netdev, "The network adapter link "
3965 "speed was downshifted because it "
3966 "overheated\n");
7ef5ed1c 3967 }
563988dc 3968
d07f3e37 3969 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3970 adapter->tx_timeout_factor = 1;
3971 switch (adapter->link_speed) {
3972 case SPEED_10:
9d5c8243
AK		 3973 adapter->tx_timeout_factor = 14;
3974 break;
3975 case SPEED_100:
9d5c8243
AK		 3976 /* maybe add some timeout factor ? */
3977 break;
3978 }
3979
3980 netif_carrier_on(netdev);
9d5c8243 3981
4ae196df 3982 igb_ping_all_vfs(adapter);
17dc566c 3983 igb_check_vf_rate_limit(adapter);
4ae196df 3984
4b1a9877 3985 /* link state has changed, schedule phy info update */
9d5c8243
AK		 3986 if (!test_bit(__IGB_DOWN, &adapter->state))
3987 mod_timer(&adapter->phy_info_timer,
3988 round_jiffies(jiffies + 2 * HZ));
3989 }
3990 } else {
3991 if (netif_carrier_ok(netdev)) {
3992 adapter->link_speed = 0;
3993 adapter->link_duplex = 0;
563988dc
SA		 3994
3995 /* check for thermal sensor event */
876d2d6f
JK		 3996 if (igb_thermal_sensor_event(hw,
3997 E1000_THSTAT_PWR_DOWN)) {
3998 netdev_err(netdev, "The network adapter was "
3999 "stopped because it overheated\n");
7ef5ed1c 4000 }
563988dc 4001
527d47c1
AD		 4002 /* Links status message must follow this format */
4003 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4004 netdev->name);
9d5c8243 4005 netif_carrier_off(netdev);
4b1a9877 4006
4ae196df
AD		 4007 igb_ping_all_vfs(adapter);
4008
4b1a9877 4009 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4010 if (!test_bit(__IGB_DOWN, &adapter->state))
4011 mod_timer(&adapter->phy_info_timer,
4012 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 4013
4014 pm_schedule_suspend(netdev->dev.parent,
4015 MSEC_PER_SEC * 5);
9d5c8243
AK		 4016 }
4017 }
4018
12dcd86b
ED		 4019 spin_lock(&adapter->stats64_lock);
4020 igb_update_stats(adapter, &adapter->stats64);
4021 spin_unlock(&adapter->stats64_lock);
9d5c8243 4022
dbabb065 4023 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4024 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4025 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4026 /* We've lost link, so the controller stops DMA,
4027 * but we've got queued Tx work that's never going
4028 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4029 * (Do the reset outside of interrupt context).
4030 */
dbabb065
AD		 4031 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4032 adapter->tx_timeout_count++;
4033 schedule_work(&adapter->reset_task);
4034 /* return immediately since reset is imminent */
4035 return;
4036 }
9d5c8243 4037 }
9d5c8243 4038
dbabb065 4039 /* Force detection of hung controller every watchdog period */
6d095fa8 4040 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4041 }
f7ba205e 4042
b980ac18 4043 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4044 if (adapter->msix_entries) {
047e0030 4045 u32 eics = 0;
0d1ae7f4
AD		 4046 for (i = 0; i < adapter->num_q_vectors; i++)
4047 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4048 wr32(E1000_EICS, eics);
4049 } else {
4050 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4051 }
9d5c8243 4052
13800469 4053 igb_spoof_check(adapter);
fc580751 4054 igb_ptp_rx_hang(adapter);
13800469 4055
9d5c8243
AK		 4056 /* Reset the timer */
4057 if (!test_bit(__IGB_DOWN, &adapter->state))
4058 mod_timer(&adapter->watchdog_timer,
4059 round_jiffies(jiffies + 2 * HZ));
4060}
4061
4062enum latency_range {
4063 lowest_latency = 0,
4064 low_latency = 1,
4065 bulk_latency = 2,
4066 latency_invalid = 255
4067};
4068
6eb5a7f1 4069/**
b980ac18
JK		 4070 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4071 * @q_vector: pointer to q_vector
6eb5a7f1 4072 *
b980ac18
JK		 4073 * Stores a new ITR value based on strictly on packet size. This
4074 * algorithm is less sophisticated than that used in igb_update_itr,
4075 * due to the difficulty of synchronizing statistics across multiple
4076 * receive rings. The divisors and thresholds used by this function
4077 * were determined based on theoretical maximum wire speed and testing
4078 * data, in order to minimize response time while increasing bulk
4079 * throughput.
4080 * This functionality is controlled by the InterruptThrottleRate module
4081 * parameter (see igb_param.c)
4082 * NOTE: This function is called only when operating in a multiqueue
4083 * receive environment.
6eb5a7f1 4084 **/
047e0030 4085static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4086{
047e0030 4087 int new_val = q_vector->itr_val;
6eb5a7f1 4088 int avg_wire_size = 0;
047e0030 4089 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4090 unsigned int packets;
9d5c8243 4091
6eb5a7f1
AD		 4092 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4093 * ints/sec - ITR timer value of 120 ticks.
4094 */
4095 if (adapter->link_speed != SPEED_1000) {
0ba82994 4096 new_val = IGB_4K_ITR;
6eb5a7f1 4097 goto set_itr_val;
9d5c8243 4098 }
047e0030 4099
0ba82994
AD		 4100 packets = q_vector->rx.total_packets;
4101 if (packets)
4102 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4103
0ba82994
AD		 4104 packets = q_vector->tx.total_packets;
4105 if (packets)
4106 avg_wire_size = max_t(u32, avg_wire_size,
4107 q_vector->tx.total_bytes / packets);
047e0030
AD		 4108
4109 /* if avg_wire_size isn't set no work was done */
4110 if (!avg_wire_size)
4111 goto clear_counts;
9d5c8243 4112
6eb5a7f1
AD		 4113 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4114 avg_wire_size += 24;
4115
4116 /* Don't starve jumbo frames */
4117 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4118
6eb5a7f1
AD		 4119 /* Give a little boost to mid-size frames */
4120 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4121 new_val = avg_wire_size / 3;
4122 else
4123 new_val = avg_wire_size / 2;
9d5c8243 4124
0ba82994
AD		 4125 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4126 if (new_val < IGB_20K_ITR &&
4127 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4128 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4129 new_val = IGB_20K_ITR;
abe1c363 4130
6eb5a7f1 4131set_itr_val:
047e0030
AD		 4132 if (new_val != q_vector->itr_val) {
4133 q_vector->itr_val = new_val;
4134 q_vector->set_itr = 1;
9d5c8243 4135 }
6eb5a7f1 4136clear_counts:
0ba82994
AD		 4137 q_vector->rx.total_bytes = 0;
4138 q_vector->rx.total_packets = 0;
4139 q_vector->tx.total_bytes = 0;
4140 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4141}
4142
4143/**
b980ac18
JK		 4144 * igb_update_itr - update the dynamic ITR value based on statistics
4145 * @q_vector: pointer to q_vector
4146 * @ring_container: ring info to update the itr for
4147 *
4148 * Stores a new ITR value based on packets and byte
4149 * counts during the last interrupt. The advantage of per interrupt
4150 * computation is faster updates and more accurate ITR for the current
4151 * traffic pattern. Constants in this function were computed
4152 * based on theoretical maximum wire speed and thresholds were set based
4153 * on testing data as well as attempting to minimize response time
4154 * while increasing bulk throughput.
4155 * this functionality is controlled by the InterruptThrottleRate module
4156 * parameter (see igb_param.c)
4157 * NOTE: These calculations are only valid when operating in a single-
4158 * queue environment.
9d5c8243 4159 **/
0ba82994
AD		 4160static void igb_update_itr(struct igb_q_vector *q_vector,
4161 struct igb_ring_container *ring_container)
9d5c8243 4162{
0ba82994
AD		 4163 unsigned int packets = ring_container->total_packets;
4164 unsigned int bytes = ring_container->total_bytes;
4165 u8 itrval = ring_container->itr;
9d5c8243 4166
0ba82994 4167 /* no packets, exit with status unchanged */
9d5c8243 4168 if (packets == 0)
0ba82994 4169 return;
9d5c8243 4170
0ba82994 4171 switch (itrval) {
9d5c8243
AK		 4172 case lowest_latency:
4173 /* handle TSO and jumbo frames */
4174 if (bytes/packets > 8000)
0ba82994 4175 itrval = bulk_latency;
9d5c8243 4176 else if ((packets < 5) && (bytes > 512))
0ba82994 4177 itrval = low_latency;
9d5c8243
AK		 4178 break;
4179 case low_latency: /* 50 usec aka 20000 ints/s */
4180 if (bytes > 10000) {
4181 /* this if handles the TSO accounting */
4182 if (bytes/packets > 8000) {
0ba82994 4183 itrval = bulk_latency;
9d5c8243 4184 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4185 itrval = bulk_latency;
9d5c8243 4186 } else if ((packets > 35)) {
0ba82994 4187 itrval = lowest_latency;
9d5c8243
AK		 4188 }
4189 } else if (bytes/packets > 2000) {
0ba82994 4190 itrval = bulk_latency;
9d5c8243 4191 } else if (packets <= 2 && bytes < 512) {
0ba82994 4192 itrval = lowest_latency;
9d5c8243
AK		 4193 }
4194 break;
4195 case bulk_latency: /* 250 usec aka 4000 ints/s */
4196 if (bytes > 25000) {
4197 if (packets > 35)
0ba82994 4198 itrval = low_latency;
1e5c3d21 4199 } else if (bytes < 1500) {
0ba82994 4200 itrval = low_latency;
9d5c8243
AK		 4201 }
4202 break;
4203 }
4204
0ba82994
AD		 4205 /* clear work counters since we have the values we need */
4206 ring_container->total_bytes = 0;
4207 ring_container->total_packets = 0;
4208
4209 /* write updated itr to ring container */
4210 ring_container->itr = itrval;
9d5c8243
AK		 4211}
4212
0ba82994 4213static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4214{
0ba82994 4215 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4216 u32 new_itr = q_vector->itr_val;
0ba82994 4217 u8 current_itr = 0;
9d5c8243
AK		 4218
4219 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4220 if (adapter->link_speed != SPEED_1000) {
4221 current_itr = 0;
0ba82994 4222 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4223 goto set_itr_now;
4224 }
4225
0ba82994
AD		 4226 igb_update_itr(q_vector, &q_vector->tx);
4227 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4228
0ba82994 4229 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4230
6eb5a7f1 4231 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4232 if (current_itr == lowest_latency &&
4233 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4234 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4235 current_itr = low_latency;
4236
9d5c8243
AK		 4237 switch (current_itr) {
4238 /* counts and packets in update_itr are dependent on these numbers */
4239 case lowest_latency:
0ba82994 4240 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4241 break;
4242 case low_latency:
0ba82994 4243 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4244 break;
4245 case bulk_latency:
0ba82994 4246 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4247 break;
4248 default:
4249 break;
4250 }
4251
4252set_itr_now:
047e0030 4253 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4254 /* this attempts to bias the interrupt rate towards Bulk
4255 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4256 * increasing
4257 */
047e0030 4258 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4259 max((new_itr * q_vector->itr_val) /
4260 (new_itr + (q_vector->itr_val >> 2)),
4261 new_itr) : new_itr;
9d5c8243
AK		 4262 /* Don't write the value here; it resets the adapter's
4263 * internal timer, and causes us to delay far longer than
4264 * we should between interrupts. Instead, we write the ITR
4265 * value at the beginning of the next interrupt so the timing
4266 * ends up being correct.
4267 */
047e0030
AD		 4268 q_vector->itr_val = new_itr;
4269 q_vector->set_itr = 1;
9d5c8243 4270 }
9d5c8243
AK		 4271}
4272
c50b52a0
SH		 4273static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4274 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4275{
4276 struct e1000_adv_tx_context_desc *context_desc;
4277 u16 i = tx_ring->next_to_use;
4278
4279 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4280
4281 i++;
4282 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4283
4284 /* set bits to identify this as an advanced context descriptor */
4285 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4286
4287 /* For 82575, context index must be unique per ring. */
866cff06 4288 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4289 mss_l4len_idx |= tx_ring->reg_idx << 4;
4290
4291 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4292 context_desc->seqnum_seed = 0;
4293 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4294 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4295}
4296
7af40ad9
AD		 4297static int igb_tso(struct igb_ring *tx_ring,
4298 struct igb_tx_buffer *first,
4299 u8 *hdr_len)
9d5c8243 4300{
7af40ad9 4301 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4302 u32 vlan_macip_lens, type_tucmd;
4303 u32 mss_l4len_idx, l4len;
4304
ed6aa105
AD		 4305 if (skb->ip_summed != CHECKSUM_PARTIAL)
4306 return 0;
4307
7d13a7d0
AD		 4308 if (!skb_is_gso(skb))
4309 return 0;
9d5c8243
AK		 4310
4311 if (skb_header_cloned(skb)) {
7af40ad9 4312 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4313 if (err)
4314 return err;
4315 }
4316
7d13a7d0
AD		 4317 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4318 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4319
7af40ad9 4320 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4321 struct iphdr *iph = ip_hdr(skb);
4322 iph->tot_len = 0;
4323 iph->check = 0;
4324 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4325 iph->daddr, 0,
4326 IPPROTO_TCP,
4327 0);
7d13a7d0 4328 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4329 first->tx_flags |= IGB_TX_FLAGS_TSO |
4330 IGB_TX_FLAGS_CSUM |
4331 IGB_TX_FLAGS_IPV4;
8e1e8a47 4332 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4333 ipv6_hdr(skb)->payload_len = 0;
4334 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4335 &ipv6_hdr(skb)->daddr,
4336 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4337 first->tx_flags |= IGB_TX_FLAGS_TSO |
4338 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4339 }
4340
7af40ad9 4341 /* compute header lengths */
7d13a7d0
AD		 4342 l4len = tcp_hdrlen(skb);
4343 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4344
7af40ad9
AD		 4345 /* update gso size and bytecount with header size */
4346 first->gso_segs = skb_shinfo(skb)->gso_segs;
4347 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4348
9d5c8243 4349 /* MSS L4LEN IDX */
7d13a7d0
AD		 4350 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4351 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4352
7d13a7d0
AD		 4353 /* VLAN MACLEN IPLEN */
4354 vlan_macip_lens = skb_network_header_len(skb);
4355 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4356 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4357
7d13a7d0 4358 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4359
7d13a7d0 4360 return 1;
9d5c8243
AK		 4361}
4362
7af40ad9 4363static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4364{
7af40ad9 4365 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4366 u32 vlan_macip_lens = 0;
4367 u32 mss_l4len_idx = 0;
4368 u32 type_tucmd = 0;
9d5c8243 4369
7d13a7d0 4370 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4371 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4372 return;
7d13a7d0
AD		 4373 } else {
4374 u8 l4_hdr = 0;
7af40ad9 4375 switch (first->protocol) {
7d13a7d0
AD		 4376 case __constant_htons(ETH_P_IP):
4377 vlan_macip_lens |= skb_network_header_len(skb);
4378 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4379 l4_hdr = ip_hdr(skb)->protocol;
4380 break;
4381 case __constant_htons(ETH_P_IPV6):
4382 vlan_macip_lens |= skb_network_header_len(skb);
4383 l4_hdr = ipv6_hdr(skb)->nexthdr;
4384 break;
4385 default:
4386 if (unlikely(net_ratelimit())) {
4387 dev_warn(tx_ring->dev,
b980ac18
JK		 4388 "partial checksum but proto=%x!\n",
4389 first->protocol);
fa4a7ef3 4390 }
7d13a7d0
AD		 4391 break;
4392 }
fa4a7ef3 4393
7d13a7d0
AD		 4394 switch (l4_hdr) {
4395 case IPPROTO_TCP:
4396 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4397 mss_l4len_idx = tcp_hdrlen(skb) <<
4398 E1000_ADVTXD_L4LEN_SHIFT;
4399 break;
4400 case IPPROTO_SCTP:
4401 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4402 mss_l4len_idx = sizeof(struct sctphdr) <<
4403 E1000_ADVTXD_L4LEN_SHIFT;
4404 break;
4405 case IPPROTO_UDP:
4406 mss_l4len_idx = sizeof(struct udphdr) <<
4407 E1000_ADVTXD_L4LEN_SHIFT;
4408 break;
4409 default:
4410 if (unlikely(net_ratelimit())) {
4411 dev_warn(tx_ring->dev,
b980ac18
JK		 4412 "partial checksum but l4 proto=%x!\n",
4413 l4_hdr);
44b0cda3 4414 }
7d13a7d0 4415 break;
9d5c8243 4416 }
7af40ad9
AD		 4417
4418 /* update TX checksum flag */
4419 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4420 }
9d5c8243 4421
7d13a7d0 4422 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4423 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4424
7d13a7d0 4425 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4426}
4427
1d9daf45
AD		 4428#define IGB_SET_FLAG(_input, _flag, _result) \
4429 ((_flag <= _result) ? \
4430 ((u32)(_input & _flag) * (_result / _flag)) : \
4431 ((u32)(_input & _flag) / (_flag / _result)))
4432
4433static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4434{
4435 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4436 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4437 E1000_ADVTXD_DCMD_DEXT |
4438 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4439
4440 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4441 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4442 (E1000_ADVTXD_DCMD_VLE));
4443
4444 /* set segmentation bits for TSO */
4445 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4446 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4447
4448 /* set timestamp bit if present */
1d9daf45
AD		 4449 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4450 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4451
1d9daf45
AD		 4452 /* insert frame checksum */
4453 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4454
4455 return cmd_type;
4456}
4457
7af40ad9
AD		 4458static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4459 union e1000_adv_tx_desc *tx_desc,
4460 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4461{
4462 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4463
1d9daf45
AD		 4464 /* 82575 requires a unique index per ring */
4465 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4466 olinfo_status |= tx_ring->reg_idx << 4;
4467
4468 /* insert L4 checksum */
1d9daf45
AD		 4469 olinfo_status |= IGB_SET_FLAG(tx_flags,
4470 IGB_TX_FLAGS_CSUM,
4471 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4472
1d9daf45
AD		 4473 /* insert IPv4 checksum */
4474 olinfo_status |= IGB_SET_FLAG(tx_flags,
4475 IGB_TX_FLAGS_IPV4,
4476 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4477
7af40ad9 4478 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4479}
4480
7af40ad9
AD		 4481static void igb_tx_map(struct igb_ring *tx_ring,
4482 struct igb_tx_buffer *first,
ebe42d16 4483 const u8 hdr_len)
9d5c8243 4484{
7af40ad9 4485 struct sk_buff *skb = first->skb;
c9f14bf3 4486 struct igb_tx_buffer *tx_buffer;
ebe42d16 4487 union e1000_adv_tx_desc *tx_desc;
80d0759e 4488 struct skb_frag_struct *frag;
ebe42d16 4489 dma_addr_t dma;
80d0759e 4490 unsigned int data_len, size;
7af40ad9 4491 u32 tx_flags = first->tx_flags;
1d9daf45 4492 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4493 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4494
4495 tx_desc = IGB_TX_DESC(tx_ring, i);
4496
80d0759e
AD		 4497 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4498
4499 size = skb_headlen(skb);
4500 data_len = skb->data_len;
ebe42d16
AD		 4501
4502 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4503
80d0759e
AD		 4504 tx_buffer = first;
4505
4506 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4507 if (dma_mapping_error(tx_ring->dev, dma))
4508 goto dma_error;
4509
4510 /* record length, and DMA address */
4511 dma_unmap_len_set(tx_buffer, len, size);
4512 dma_unmap_addr_set(tx_buffer, dma, dma);
4513
4514 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4515
ebe42d16
AD		 4516 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4517 tx_desc->read.cmd_type_len =
1d9daf45 4518 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4519
4520 i++;
4521 tx_desc++;
4522 if (i == tx_ring->count) {
4523 tx_desc = IGB_TX_DESC(tx_ring, 0);
4524 i = 0;
4525 }
80d0759e 4526 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4527
4528 dma += IGB_MAX_DATA_PER_TXD;
4529 size -= IGB_MAX_DATA_PER_TXD;
4530
ebe42d16
AD		 4531 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4532 }
4533
4534 if (likely(!data_len))
4535 break;
2bbfebe2 4536
1d9daf45 4537 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4538
65689fef 4539 i++;
ebe42d16
AD		 4540 tx_desc++;
4541 if (i == tx_ring->count) {
4542 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4543 i = 0;
ebe42d16 4544 }
80d0759e 4545 tx_desc->read.olinfo_status = 0;
65689fef 4546
9e903e08 4547 size = skb_frag_size(frag);
ebe42d16
AD		 4548 data_len -= size;
4549
4550 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4551 size, DMA_TO_DEVICE);
6366ad33 4552
c9f14bf3 4553 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4554 }
4555
ebe42d16 4556 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4557 cmd_type |= size | IGB_TXD_DCMD;
4558 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4559
80d0759e
AD		 4560 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4561
8542db05
AD		 4562 /* set the timestamp */
4563 first->time_stamp = jiffies;
4564
b980ac18 4565 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4566 * are new descriptors to fetch. (Only applicable for weak-ordered
4567 * memory model archs, such as IA-64).
4568 *
4569 * We also need this memory barrier to make certain all of the
4570 * status bits have been updated before next_to_watch is written.
4571 */
4572 wmb();
4573
8542db05 4574 /* set next_to_watch value indicating a packet is present */
ebe42d16 4575 first->next_to_watch = tx_desc;
9d5c8243 4576
ebe42d16
AD		 4577 i++;
4578 if (i == tx_ring->count)
4579 i = 0;
6366ad33 4580
ebe42d16 4581 tx_ring->next_to_use = i;
6366ad33 4582
ebe42d16 4583 writel(i, tx_ring->tail);
6366ad33 4584
ebe42d16 4585 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4586 * at a time, it synchronizes IO on IA64/Altix systems
4587 */
ebe42d16
AD		 4588 mmiowb();
4589
4590 return;
4591
4592dma_error:
4593 dev_err(tx_ring->dev, "TX DMA map failed\n");
4594
4595 /* clear dma mappings for failed tx_buffer_info map */
4596 for (;;) {
c9f14bf3
AD		 4597 tx_buffer = &tx_ring->tx_buffer_info[i];
4598 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4599 if (tx_buffer == first)
ebe42d16 4600 break;
a77ff709
NN		 4601 if (i == 0)
4602 i = tx_ring->count;
6366ad33 4603 i--;
6366ad33
AD		 4604 }
4605
9d5c8243 4606 tx_ring->next_to_use = i;
9d5c8243
AK		 4607}
4608
6ad4edfc 4609static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4610{
e694e964
AD		 4611 struct net_device *netdev = tx_ring->netdev;
4612
661086df 4613 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4614
9d5c8243
AK		 4615 /* Herbert's original patch had:
4616 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4617 * but since that doesn't exist yet, just open code it.
4618 */
9d5c8243
AK		 4619 smp_mb();
4620
4621 /* We need to check again in a case another CPU has just
b980ac18
JK		 4622 * made room available.
4623 */
c493ea45 4624 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4625 return -EBUSY;
4626
4627 /* A reprieve! */
661086df 4628 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4629
4630 u64_stats_update_begin(&tx_ring->tx_syncp2);
4631 tx_ring->tx_stats.restart_queue2++;
4632 u64_stats_update_end(&tx_ring->tx_syncp2);
4633
9d5c8243
AK		 4634 return 0;
4635}
4636
6ad4edfc 4637static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4638{
c493ea45 4639 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4640 return 0;
e694e964 4641 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4642}
4643
cd392f5c
AD		 4644netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4645 struct igb_ring *tx_ring)
9d5c8243 4646{
8542db05 4647 struct igb_tx_buffer *first;
ebe42d16 4648 int tso;
91d4ee33 4649 u32 tx_flags = 0;
21ba6fe1 4650 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4651 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4652 u8 hdr_len = 0;
9d5c8243 4653
21ba6fe1
AD		 4654 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4655 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4656 * + 2 desc gap to keep tail from touching head,
9d5c8243 4657 * + 1 desc for context descriptor,
21ba6fe1
AD		 4658 * otherwise try next time
4659 */
4660 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4661 unsigned short f;
4662 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4663 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4664 } else {
4665 count += skb_shinfo(skb)->nr_frags;
4666 }
4667
4668 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4669 /* this is a hard error */
9d5c8243
AK		 4670 return NETDEV_TX_BUSY;
4671 }
33af6bcc 4672
7af40ad9
AD		 4673 /* record the location of the first descriptor for this packet */
4674 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4675 first->skb = skb;
4676 first->bytecount = skb->len;
4677 first->gso_segs = 1;
4678
b66e2397
MV		 4679 skb_tx_timestamp(skb);
4680
b646c22e
AD		 4681 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4682 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4683
b646c22e
AD		 4684 if (!(adapter->ptp_tx_skb)) {
4685 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4686 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4687
4688 adapter->ptp_tx_skb = skb_get(skb);
4689 adapter->ptp_tx_start = jiffies;
4690 if (adapter->hw.mac.type == e1000_82576)
4691 schedule_work(&adapter->ptp_tx_work);
4692 }
33af6bcc 4693 }
9d5c8243 4694
eab6d18d 4695 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4696 tx_flags |= IGB_TX_FLAGS_VLAN;
4697 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4698 }
4699
7af40ad9
AD		 4700 /* record initial flags and protocol */
4701 first->tx_flags = tx_flags;
4702 first->protocol = protocol;
cdfd01fc 4703
7af40ad9
AD		 4704 tso = igb_tso(tx_ring, first, &hdr_len);
4705 if (tso < 0)
7d13a7d0 4706 goto out_drop;
7af40ad9
AD		 4707 else if (!tso)
4708 igb_tx_csum(tx_ring, first);
9d5c8243 4709
7af40ad9 4710 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4711
4712 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4713 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4714
9d5c8243 4715 return NETDEV_TX_OK;
7d13a7d0
AD		 4716
4717out_drop:
7af40ad9
AD		 4718 igb_unmap_and_free_tx_resource(tx_ring, first);
4719
7d13a7d0 4720 return NETDEV_TX_OK;
9d5c8243
AK		 4721}
4722
1cc3bd87
AD		 4723static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4724 struct sk_buff *skb)
4725{
4726 unsigned int r_idx = skb->queue_mapping;
4727
4728 if (r_idx >= adapter->num_tx_queues)
4729 r_idx = r_idx % adapter->num_tx_queues;
4730
4731 return adapter->tx_ring[r_idx];
4732}
4733
cd392f5c
AD		 4734static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4735 struct net_device *netdev)
9d5c8243
AK		 4736{
4737 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4738
4739 if (test_bit(__IGB_DOWN, &adapter->state)) {
4740 dev_kfree_skb_any(skb);
4741 return NETDEV_TX_OK;
4742 }
4743
4744 if (skb->len <= 0) {
4745 dev_kfree_skb_any(skb);
4746 return NETDEV_TX_OK;
4747 }
4748
b980ac18 4749 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4750 * in order to meet this minimum size requirement.
4751 */
ea5ceeab
TD		 4752 if (unlikely(skb->len < 17)) {
4753 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4754 return NETDEV_TX_OK;
4755 skb->len = 17;
ea5ceeab 4756 skb_set_tail_pointer(skb, 17);
1cc3bd87 4757 }
9d5c8243 4758
1cc3bd87 4759 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4760}
4761
4762/**
b980ac18
JK		 4763 * igb_tx_timeout - Respond to a Tx Hang
4764 * @netdev: network interface device structure
9d5c8243
AK		 4765 **/
4766static void igb_tx_timeout(struct net_device *netdev)
4767{
4768 struct igb_adapter *adapter = netdev_priv(netdev);
4769 struct e1000_hw *hw = &adapter->hw;
4770
4771 /* Do the reset outside of interrupt context */
4772 adapter->tx_timeout_count++;
f7ba205e 4773
06218a8d 4774 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4775 hw->dev_spec._82575.global_device_reset = true;
4776
9d5c8243 4777 schedule_work(&adapter->reset_task);
265de409
AD		 4778 wr32(E1000_EICS,
4779 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4780}
4781
4782static void igb_reset_task(struct work_struct *work)
4783{
4784 struct igb_adapter *adapter;
4785 adapter = container_of(work, struct igb_adapter, reset_task);
4786
c97ec42a
TI		 4787 igb_dump(adapter);
4788 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4789 igb_reinit_locked(adapter);
4790}
4791
4792/**
b980ac18
JK		 4793 * igb_get_stats64 - Get System Network Statistics
4794 * @netdev: network interface device structure
4795 * @stats: rtnl_link_stats64 pointer
9d5c8243 4796 **/
12dcd86b 4797static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4798 struct rtnl_link_stats64 *stats)
9d5c8243 4799{
12dcd86b
ED		 4800 struct igb_adapter *adapter = netdev_priv(netdev);
4801
4802 spin_lock(&adapter->stats64_lock);
4803 igb_update_stats(adapter, &adapter->stats64);
4804 memcpy(stats, &adapter->stats64, sizeof(*stats));
4805 spin_unlock(&adapter->stats64_lock);
4806
4807 return stats;
9d5c8243
AK		 4808}
4809
4810/**
b980ac18
JK		 4811 * igb_change_mtu - Change the Maximum Transfer Unit
4812 * @netdev: network interface device structure
4813 * @new_mtu: new value for maximum frame size
9d5c8243 4814 *
b980ac18 4815 * Returns 0 on success, negative on failure
9d5c8243
AK		 4816 **/
4817static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4818{
4819 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4820 struct pci_dev *pdev = adapter->pdev;
153285f9 4821 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4822
c809d227 4823 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4824 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4825 return -EINVAL;
4826 }
4827
153285f9 4828#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4829 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4830 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4831 return -EINVAL;
4832 }
4833
2ccd994c
AD		 4834 /* adjust max frame to be at least the size of a standard frame */
4835 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4836 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4837
9d5c8243
AK		 4838 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4839 msleep(1);
73cd78f1 4840
9d5c8243
AK		 4841 /* igb_down has a dependency on max_frame_size */
4842 adapter->max_frame_size = max_frame;
559e9c49 4843
4c844851
AD		 4844 if (netif_running(netdev))
4845 igb_down(adapter);
9d5c8243 4846
090b1795 4847 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4848 netdev->mtu, new_mtu);
4849 netdev->mtu = new_mtu;
4850
4851 if (netif_running(netdev))
4852 igb_up(adapter);
4853 else
4854 igb_reset(adapter);
4855
4856 clear_bit(__IGB_RESETTING, &adapter->state);
4857
4858 return 0;
4859}
4860
4861/**
b980ac18
JK		 4862 * igb_update_stats - Update the board statistics counters
4863 * @adapter: board private structure
9d5c8243 4864 **/
12dcd86b
ED		 4865void igb_update_stats(struct igb_adapter *adapter,
4866 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4867{
4868 struct e1000_hw *hw = &adapter->hw;
4869 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4870 u32 reg, mpc;
9d5c8243 4871 u16 phy_tmp;
3f9c0164
AD		 4872 int i;
4873 u64 bytes, packets;
12dcd86b
ED		 4874 unsigned int start;
4875 u64 _bytes, _packets;
9d5c8243
AK		 4876
4877#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4878
b980ac18 4879 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4880 * connection is down.
4881 */
4882 if (adapter->link_speed == 0)
4883 return;
4884 if (pci_channel_offline(pdev))
4885 return;
4886
3f9c0164
AD		 4887 bytes = 0;
4888 packets = 0;
7f90128e
AA		 4889
4890 rcu_read_lock();
3f9c0164 4891 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4892 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4893 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4894
ae1c07a6
AD		 4895 if (rqdpc) {
4896 ring->rx_stats.drops += rqdpc;
4897 net_stats->rx_fifo_errors += rqdpc;
4898 }
12dcd86b
ED		 4899
4900 do {
4901 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4902 _bytes = ring->rx_stats.bytes;
4903 _packets = ring->rx_stats.packets;
4904 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4905 bytes += _bytes;
4906 packets += _packets;
3f9c0164
AD		 4907 }
4908
128e45eb
AD		 4909 net_stats->rx_bytes = bytes;
4910 net_stats->rx_packets = packets;
3f9c0164
AD		 4911
4912 bytes = 0;
4913 packets = 0;
4914 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4915 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4916 do {
4917 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4918 _bytes = ring->tx_stats.bytes;
4919 _packets = ring->tx_stats.packets;
4920 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4921 bytes += _bytes;
4922 packets += _packets;
3f9c0164 4923 }
128e45eb
AD		 4924 net_stats->tx_bytes = bytes;
4925 net_stats->tx_packets = packets;
7f90128e 4926 rcu_read_unlock();
3f9c0164
AD		 4927
4928 /* read stats registers */
9d5c8243
AK		 4929 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4930 adapter->stats.gprc += rd32(E1000_GPRC);
4931 adapter->stats.gorc += rd32(E1000_GORCL);
4932 rd32(E1000_GORCH); /* clear GORCL */
4933 adapter->stats.bprc += rd32(E1000_BPRC);
4934 adapter->stats.mprc += rd32(E1000_MPRC);
4935 adapter->stats.roc += rd32(E1000_ROC);
4936
4937 adapter->stats.prc64 += rd32(E1000_PRC64);
4938 adapter->stats.prc127 += rd32(E1000_PRC127);
4939 adapter->stats.prc255 += rd32(E1000_PRC255);
4940 adapter->stats.prc511 += rd32(E1000_PRC511);
4941 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4942 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4943 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4944 adapter->stats.sec += rd32(E1000_SEC);
4945
fa3d9a6d
MW		 4946 mpc = rd32(E1000_MPC);
4947 adapter->stats.mpc += mpc;
4948 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4949 adapter->stats.scc += rd32(E1000_SCC);
4950 adapter->stats.ecol += rd32(E1000_ECOL);
4951 adapter->stats.mcc += rd32(E1000_MCC);
4952 adapter->stats.latecol += rd32(E1000_LATECOL);
4953 adapter->stats.dc += rd32(E1000_DC);
4954 adapter->stats.rlec += rd32(E1000_RLEC);
4955 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4956 adapter->stats.xontxc += rd32(E1000_XONTXC);
4957 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4958 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4959 adapter->stats.fcruc += rd32(E1000_FCRUC);
4960 adapter->stats.gptc += rd32(E1000_GPTC);
4961 adapter->stats.gotc += rd32(E1000_GOTCL);
4962 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4963 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4964 adapter->stats.ruc += rd32(E1000_RUC);
4965 adapter->stats.rfc += rd32(E1000_RFC);
4966 adapter->stats.rjc += rd32(E1000_RJC);
4967 adapter->stats.tor += rd32(E1000_TORH);
4968 adapter->stats.tot += rd32(E1000_TOTH);
4969 adapter->stats.tpr += rd32(E1000_TPR);
4970
4971 adapter->stats.ptc64 += rd32(E1000_PTC64);
4972 adapter->stats.ptc127 += rd32(E1000_PTC127);
4973 adapter->stats.ptc255 += rd32(E1000_PTC255);
4974 adapter->stats.ptc511 += rd32(E1000_PTC511);
4975 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4976 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4977
4978 adapter->stats.mptc += rd32(E1000_MPTC);
4979 adapter->stats.bptc += rd32(E1000_BPTC);
4980
2d0b0f69
NN		 4981 adapter->stats.tpt += rd32(E1000_TPT);
4982 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 4983
4984 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 4985 /* read internal phy specific stats */
4986 reg = rd32(E1000_CTRL_EXT);
4987 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4988 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 4989
4990 /* this stat has invalid values on i210/i211 */
4991 if ((hw->mac.type != e1000_i210) &&
4992 (hw->mac.type != e1000_i211))
4993 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 4994 }
4995
9d5c8243
AK		 4996 adapter->stats.tsctc += rd32(E1000_TSCTC);
4997 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4998
4999 adapter->stats.iac += rd32(E1000_IAC);
5000 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5001 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5002 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5003 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5004 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5005 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5006 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5007 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5008
5009 /* Fill out the OS statistics structure */
128e45eb
AD		 5010 net_stats->multicast = adapter->stats.mprc;
5011 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5012
5013 /* Rx Errors */
5014
5015 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5016 * our own version based on RUC and ROC
5017 */
128e45eb 5018 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5019 adapter->stats.crcerrs + adapter->stats.algnerrc +
5020 adapter->stats.ruc + adapter->stats.roc +
5021 adapter->stats.cexterr;
128e45eb
AD		 5022 net_stats->rx_length_errors = adapter->stats.ruc +
5023 adapter->stats.roc;
5024 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5025 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5026 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5027
5028 /* Tx Errors */
128e45eb
AD		 5029 net_stats->tx_errors = adapter->stats.ecol +
5030 adapter->stats.latecol;
5031 net_stats->tx_aborted_errors = adapter->stats.ecol;
5032 net_stats->tx_window_errors = adapter->stats.latecol;
5033 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5034
5035 /* Tx Dropped needs to be maintained elsewhere */
5036
5037 /* Phy Stats */
5038 if (hw->phy.media_type == e1000_media_type_copper) {
5039 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5040 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5041 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5042 adapter->phy_stats.idle_errors += phy_tmp;
5043 }
5044 }
5045
5046 /* Management Stats */
5047 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5048 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5049 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5050
5051 /* OS2BMC Stats */
5052 reg = rd32(E1000_MANC);
5053 if (reg & E1000_MANC_EN_BMC2OS) {
5054 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5055 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5056 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5057 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5058 }
9d5c8243
AK		 5059}
5060
9d5c8243
AK		 5061static irqreturn_t igb_msix_other(int irq, void *data)
5062{
047e0030 5063 struct igb_adapter *adapter = data;
9d5c8243 5064 struct e1000_hw *hw = &adapter->hw;
844290e5 5065 u32 icr = rd32(E1000_ICR);
844290e5 5066 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5067
7f081d40
AD		 5068 if (icr & E1000_ICR_DRSTA)
5069 schedule_work(&adapter->reset_task);
5070
047e0030 5071 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5072 /* HW is reporting DMA is out of sync */
5073 adapter->stats.doosync++;
13800469
GR		 5074 /* The DMA Out of Sync is also indication of a spoof event
5075 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5076 * see if it is really a spoof event.
5077 */
13800469 5078 igb_check_wvbr(adapter);
dda0e083 5079 }
eebbbdba 5080
4ae196df
AD		 5081 /* Check for a mailbox event */
5082 if (icr & E1000_ICR_VMMB)
5083 igb_msg_task(adapter);
5084
5085 if (icr & E1000_ICR_LSC) {
5086 hw->mac.get_link_status = 1;
5087 /* guard against interrupt when we're going down */
5088 if (!test_bit(__IGB_DOWN, &adapter->state))
5089 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5090 }
5091
1f6e8178
MV		 5092 if (icr & E1000_ICR_TS) {
5093 u32 tsicr = rd32(E1000_TSICR);
5094
5095 if (tsicr & E1000_TSICR_TXTS) {
5096 /* acknowledge the interrupt */
5097 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5098 /* retrieve hardware timestamp */
5099 schedule_work(&adapter->ptp_tx_work);
5100 }
5101 }
1f6e8178 5102
844290e5 5103 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5104
5105 return IRQ_HANDLED;
5106}
5107
047e0030 5108static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5109{
26b39276 5110 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5111 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5112
047e0030
AD		 5113 if (!q_vector->set_itr)
5114 return;
73cd78f1 5115
047e0030
AD		 5116 if (!itr_val)
5117 itr_val = 0x4;
661086df 5118
26b39276
AD		 5119 if (adapter->hw.mac.type == e1000_82575)
5120 itr_val |= itr_val << 16;
661086df 5121 else
0ba82994 5122 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5123
047e0030
AD		 5124 writel(itr_val, q_vector->itr_register);
5125 q_vector->set_itr = 0;
6eb5a7f1
AD		 5126}
5127
047e0030 5128static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5129{
047e0030 5130 struct igb_q_vector *q_vector = data;
9d5c8243 5131
047e0030
AD		 5132 /* Write the ITR value calculated from the previous interrupt. */
5133 igb_write_itr(q_vector);
9d5c8243 5134
047e0030 5135 napi_schedule(&q_vector->napi);
844290e5 5136
047e0030 5137 return IRQ_HANDLED;
fe4506b6
JC		 5138}
5139
421e02f0 5140#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5141static void igb_update_tx_dca(struct igb_adapter *adapter,
5142 struct igb_ring *tx_ring,
5143 int cpu)
5144{
5145 struct e1000_hw *hw = &adapter->hw;
5146 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5147
5148 if (hw->mac.type != e1000_82575)
5149 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5150
b980ac18 5151 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5152 * DCA is enabled. This is due to a known issue in some chipsets
5153 * which will cause the DCA tag to be cleared.
5154 */
5155 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5156 E1000_DCA_TXCTRL_DATA_RRO_EN |
5157 E1000_DCA_TXCTRL_DESC_DCA_EN;
5158
5159 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5160}
5161
5162static void igb_update_rx_dca(struct igb_adapter *adapter,
5163 struct igb_ring *rx_ring,
5164 int cpu)
5165{
5166 struct e1000_hw *hw = &adapter->hw;
5167 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5168
5169 if (hw->mac.type != e1000_82575)
5170 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5171
b980ac18 5172 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5173 * DCA is enabled. This is due to a known issue in some chipsets
5174 * which will cause the DCA tag to be cleared.
5175 */
5176 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5177 E1000_DCA_RXCTRL_DESC_DCA_EN;
5178
5179 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5180}
5181
047e0030 5182static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5183{
047e0030 5184 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5185 int cpu = get_cpu();
fe4506b6 5186
047e0030
AD		 5187 if (q_vector->cpu == cpu)
5188 goto out_no_update;
5189
6a05004a
AD		 5190 if (q_vector->tx.ring)
5191 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5192
5193 if (q_vector->rx.ring)
5194 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5195
047e0030
AD		 5196 q_vector->cpu = cpu;
5197out_no_update:
fe4506b6
JC		 5198 put_cpu();
5199}
5200
5201static void igb_setup_dca(struct igb_adapter *adapter)
5202{
7e0e99ef 5203 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5204 int i;
5205
7dfc16fa 5206 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5207 return;
5208
7e0e99ef
AD		 5209 /* Always use CB2 mode, difference is masked in the CB driver. */
5210 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5211
047e0030 5212 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5213 adapter->q_vector[i]->cpu = -1;
5214 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5215 }
5216}
5217
5218static int __igb_notify_dca(struct device *dev, void *data)
5219{
5220 struct net_device *netdev = dev_get_drvdata(dev);
5221 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5222 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5223 struct e1000_hw *hw = &adapter->hw;
5224 unsigned long event = *(unsigned long *)data;
5225
5226 switch (event) {
5227 case DCA_PROVIDER_ADD:
5228 /* if already enabled, don't do it again */
7dfc16fa 5229 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5230 break;
fe4506b6 5231 if (dca_add_requester(dev) == 0) {
bbd98fe4 5232 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5233 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5234 igb_setup_dca(adapter);
5235 break;
5236 }
5237 /* Fall Through since DCA is disabled. */
5238 case DCA_PROVIDER_REMOVE:
7dfc16fa 5239 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5240 /* without this a class_device is left
b980ac18
JK		 5241 * hanging around in the sysfs model
5242 */
fe4506b6 5243 dca_remove_requester(dev);
090b1795 5244 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5245 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5246 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5247 }
5248 break;
5249 }
bbd98fe4 5250
fe4506b6 5251 return 0;
9d5c8243
AK		 5252}
5253
fe4506b6 5254static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5255 void *p)
fe4506b6
JC		 5256{
5257 int ret_val;
5258
5259 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5260 __igb_notify_dca);
fe4506b6
JC		 5261
5262 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5263}
421e02f0 5264#endif /* CONFIG_IGB_DCA */
9d5c8243 5265
0224d663
GR		 5266#ifdef CONFIG_PCI_IOV
5267static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5268{
5269 unsigned char mac_addr[ETH_ALEN];
0224d663 5270
5ac6f91d 5271 eth_zero_addr(mac_addr);
0224d663
GR		 5272 igb_set_vf_mac(adapter, vf, mac_addr);
5273
70ea4783
LL		 5274 /* By default spoof check is enabled for all VFs */
5275 adapter->vf_data[vf].spoofchk_enabled = true;
5276
f557147c 5277 return 0;
0224d663
GR		 5278}
5279
0224d663 5280#endif
4ae196df
AD		 5281static void igb_ping_all_vfs(struct igb_adapter *adapter)
5282{
5283 struct e1000_hw *hw = &adapter->hw;
5284 u32 ping;
5285 int i;
5286
5287 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5288 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5289 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5290 ping |= E1000_VT_MSGTYPE_CTS;
5291 igb_write_mbx(hw, &ping, 1, i);
5292 }
5293}
5294
7d5753f0
AD		 5295static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5296{
5297 struct e1000_hw *hw = &adapter->hw;
5298 u32 vmolr = rd32(E1000_VMOLR(vf));
5299 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5300
d85b9004 5301 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5302 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5303 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5304
5305 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5306 vmolr |= E1000_VMOLR_MPME;
d85b9004 5307 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5308 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5309 } else {
b980ac18 5310 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5311 * flag we need to write the hashes to the MTA as this step
5312 * was previously skipped
5313 */
5314 if (vf_data->num_vf_mc_hashes > 30) {
5315 vmolr |= E1000_VMOLR_MPME;
5316 } else if (vf_data->num_vf_mc_hashes) {
5317 int j;
5318 vmolr |= E1000_VMOLR_ROMPE;
5319 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5320 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5321 }
5322 }
5323
5324 wr32(E1000_VMOLR(vf), vmolr);
5325
5326 /* there are flags left unprocessed, likely not supported */
5327 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5328 return -EINVAL;
5329
5330 return 0;
7d5753f0
AD		 5331}
5332
4ae196df
AD		 5333static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5334 u32 *msgbuf, u32 vf)
5335{
5336 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5337 u16 *hash_list = (u16 *)&msgbuf[1];
5338 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5339 int i;
5340
7d5753f0 5341 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5342 * to this VF for later use to restore when the PF multi cast
5343 * list changes
5344 */
5345 vf_data->num_vf_mc_hashes = n;
5346
7d5753f0
AD		 5347 /* only up to 30 hash values supported */
5348 if (n > 30)
5349 n = 30;
5350
5351 /* store the hashes for later use */
4ae196df 5352 for (i = 0; i < n; i++)
a419aef8 5353 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5354
5355 /* Flush and reset the mta with the new values */
ff41f8dc 5356 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5357
5358 return 0;
5359}
5360
5361static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5362{
5363 struct e1000_hw *hw = &adapter->hw;
5364 struct vf_data_storage *vf_data;
5365 int i, j;
5366
5367 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5368 u32 vmolr = rd32(E1000_VMOLR(i));
5369 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5370
4ae196df 5371 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5372
5373 if ((vf_data->num_vf_mc_hashes > 30) ||
5374 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5375 vmolr |= E1000_VMOLR_MPME;
5376 } else if (vf_data->num_vf_mc_hashes) {
5377 vmolr |= E1000_VMOLR_ROMPE;
5378 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5379 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5380 }
5381 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5382 }
5383}
5384
5385static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5386{
5387 struct e1000_hw *hw = &adapter->hw;
5388 u32 pool_mask, reg, vid;
5389 int i;
5390
5391 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5392
5393 /* Find the vlan filter for this id */
5394 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5395 reg = rd32(E1000_VLVF(i));
5396
5397 /* remove the vf from the pool */
5398 reg &= ~pool_mask;
5399
5400 /* if pool is empty then remove entry from vfta */
5401 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5402 (reg & E1000_VLVF_VLANID_ENABLE)) {
5403 reg = 0;
5404 vid = reg & E1000_VLVF_VLANID_MASK;
5405 igb_vfta_set(hw, vid, false);
5406 }
5407
5408 wr32(E1000_VLVF(i), reg);
5409 }
ae641bdc
AD		 5410
5411 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5412}
5413
5414static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5415{
5416 struct e1000_hw *hw = &adapter->hw;
5417 u32 reg, i;
5418
51466239
AD		 5419 /* The vlvf table only exists on 82576 hardware and newer */
5420 if (hw->mac.type < e1000_82576)
5421 return -1;
5422
5423 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5424 if (!adapter->vfs_allocated_count)
5425 return -1;
5426
5427 /* Find the vlan filter for this id */
5428 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5429 reg = rd32(E1000_VLVF(i));
5430 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5431 vid == (reg & E1000_VLVF_VLANID_MASK))
5432 break;
5433 }
5434
5435 if (add) {
5436 if (i == E1000_VLVF_ARRAY_SIZE) {
5437 /* Did not find a matching VLAN ID entry that was
5438 * enabled. Search for a free filter entry, i.e.
5439 * one without the enable bit set
5440 */
5441 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5442 reg = rd32(E1000_VLVF(i));
5443 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5444 break;
5445 }
5446 }
5447 if (i < E1000_VLVF_ARRAY_SIZE) {
5448 /* Found an enabled/available entry */
5449 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5450
5451 /* if !enabled we need to set this up in vfta */
5452 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5453 /* add VID to filter table */
5454 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5455 reg |= E1000_VLVF_VLANID_ENABLE;
5456 }
cad6d05f
AD		 5457 reg &= ~E1000_VLVF_VLANID_MASK;
5458 reg |= vid;
4ae196df 5459 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5460
5461 /* do not modify RLPML for PF devices */
5462 if (vf >= adapter->vfs_allocated_count)
5463 return 0;
5464
5465 if (!adapter->vf_data[vf].vlans_enabled) {
5466 u32 size;
5467 reg = rd32(E1000_VMOLR(vf));
5468 size = reg & E1000_VMOLR_RLPML_MASK;
5469 size += 4;
5470 reg &= ~E1000_VMOLR_RLPML_MASK;
5471 reg |= size;
5472 wr32(E1000_VMOLR(vf), reg);
5473 }
ae641bdc 5474
51466239 5475 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5476 }
5477 } else {
5478 if (i < E1000_VLVF_ARRAY_SIZE) {
5479 /* remove vf from the pool */
5480 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5481 /* if pool is empty then remove entry from vfta */
5482 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5483 reg = 0;
5484 igb_vfta_set(hw, vid, false);
5485 }
5486 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5487
5488 /* do not modify RLPML for PF devices */
5489 if (vf >= adapter->vfs_allocated_count)
5490 return 0;
5491
5492 adapter->vf_data[vf].vlans_enabled--;
5493 if (!adapter->vf_data[vf].vlans_enabled) {
5494 u32 size;
5495 reg = rd32(E1000_VMOLR(vf));
5496 size = reg & E1000_VMOLR_RLPML_MASK;
5497 size -= 4;
5498 reg &= ~E1000_VMOLR_RLPML_MASK;
5499 reg |= size;
5500 wr32(E1000_VMOLR(vf), reg);
5501 }
4ae196df
AD		 5502 }
5503 }
8151d294
WM		 5504 return 0;
5505}
5506
5507static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5508{
5509 struct e1000_hw *hw = &adapter->hw;
5510
5511 if (vid)
5512 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5513 else
5514 wr32(E1000_VMVIR(vf), 0);
5515}
5516
5517static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5518 int vf, u16 vlan, u8 qos)
5519{
5520 int err = 0;
5521 struct igb_adapter *adapter = netdev_priv(netdev);
5522
5523 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5524 return -EINVAL;
5525 if (vlan || qos) {
5526 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5527 if (err)
5528 goto out;
5529 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5530 igb_set_vmolr(adapter, vf, !vlan);
5531 adapter->vf_data[vf].pf_vlan = vlan;
5532 adapter->vf_data[vf].pf_qos = qos;
5533 dev_info(&adapter->pdev->dev,
5534 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5535 if (test_bit(__IGB_DOWN, &adapter->state)) {
5536 dev_warn(&adapter->pdev->dev,
b980ac18 5537 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5538 dev_warn(&adapter->pdev->dev,
b980ac18 5539 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5540 }
5541 } else {
5542 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5543 false, vf);
8151d294
WM		 5544 igb_set_vmvir(adapter, vlan, vf);
5545 igb_set_vmolr(adapter, vf, true);
5546 adapter->vf_data[vf].pf_vlan = 0;
5547 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5548 }
8151d294 5549out:
b980ac18 5550 return err;
4ae196df
AD		 5551}
5552
6f3dc319
GR		 5553static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5554{
5555 struct e1000_hw *hw = &adapter->hw;
5556 int i;
5557 u32 reg;
5558
5559 /* Find the vlan filter for this id */
5560 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5561 reg = rd32(E1000_VLVF(i));
5562 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5563 vid == (reg & E1000_VLVF_VLANID_MASK))
5564 break;
5565 }
5566
5567 if (i >= E1000_VLVF_ARRAY_SIZE)
5568 i = -1;
5569
5570 return i;
5571}
5572
4ae196df
AD		 5573static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5574{
6f3dc319 5575 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5576 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5577 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5578 int err = 0;
4ae196df 5579
6f3dc319
GR		 5580 /* If in promiscuous mode we need to make sure the PF also has
5581 * the VLAN filter set.
5582 */
5583 if (add && (adapter->netdev->flags & IFF_PROMISC))
5584 err = igb_vlvf_set(adapter, vid, add,
5585 adapter->vfs_allocated_count);
5586 if (err)
5587 goto out;
5588
5589 err = igb_vlvf_set(adapter, vid, add, vf);
5590
5591 if (err)
5592 goto out;
5593
5594 /* Go through all the checks to see if the VLAN filter should
5595 * be wiped completely.
5596 */
5597 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5598 u32 vlvf, bits;
5599
5600 int regndx = igb_find_vlvf_entry(adapter, vid);
5601 if (regndx < 0)
5602 goto out;
5603 /* See if any other pools are set for this VLAN filter
5604 * entry other than the PF.
5605 */
5606 vlvf = bits = rd32(E1000_VLVF(regndx));
5607 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5608 adapter->vfs_allocated_count);
5609 /* If the filter was removed then ensure PF pool bit
5610 * is cleared if the PF only added itself to the pool
5611 * because the PF is in promiscuous mode.
5612 */
5613 if ((vlvf & VLAN_VID_MASK) == vid &&
5614 !test_bit(vid, adapter->active_vlans) &&
5615 !bits)
5616 igb_vlvf_set(adapter, vid, add,
5617 adapter->vfs_allocated_count);
5618 }
5619
5620out:
5621 return err;
4ae196df
AD		 5622}
5623
f2ca0dbe 5624static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5625{
8fa7e0f7
GR		 5626 /* clear flags - except flag that indicates PF has set the MAC */
5627 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5628 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5629
5630 /* reset offloads to defaults */
8151d294 5631 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5632
5633 /* reset vlans for device */
5634 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5635 if (adapter->vf_data[vf].pf_vlan)
5636 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5637 adapter->vf_data[vf].pf_vlan,
5638 adapter->vf_data[vf].pf_qos);
5639 else
5640 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5641
5642 /* reset multicast table array for vf */
5643 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5644
5645 /* Flush and reset the mta with the new values */
ff41f8dc 5646 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5647}
5648
f2ca0dbe
AD		 5649static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5650{
5651 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5652
5ac6f91d 5653 /* clear mac address as we were hotplug removed/added */
8151d294 5654 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5655 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5656
5657 /* process remaining reset events */
5658 igb_vf_reset(adapter, vf);
5659}
5660
5661static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5662{
5663 struct e1000_hw *hw = &adapter->hw;
5664 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5665 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5666 u32 reg, msgbuf[3];
5667 u8 *addr = (u8 *)(&msgbuf[1]);
5668
5669 /* process all the same items cleared in a function level reset */
f2ca0dbe 5670 igb_vf_reset(adapter, vf);
4ae196df
AD		 5671
5672 /* set vf mac address */
26ad9178 5673 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5674
5675 /* enable transmit and receive for vf */
5676 reg = rd32(E1000_VFTE);
5677 wr32(E1000_VFTE, reg | (1 << vf));
5678 reg = rd32(E1000_VFRE);
5679 wr32(E1000_VFRE, reg | (1 << vf));
5680
8fa7e0f7 5681 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5682
5683 /* reply to reset with ack and vf mac address */
5684 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5685 memcpy(addr, vf_mac, 6);
5686 igb_write_mbx(hw, msgbuf, 3, vf);
5687}
5688
5689static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5690{
b980ac18 5691 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5692 * starting at the second 32 bit word of the msg array
5693 */
f2ca0dbe
AD		 5694 unsigned char *addr = (char *)&msg[1];
5695 int err = -1;
4ae196df 5696
f2ca0dbe
AD		 5697 if (is_valid_ether_addr(addr))
5698 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5699
f2ca0dbe 5700 return err;
4ae196df
AD		 5701}
5702
5703static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5704{
5705 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5706 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5707 u32 msg = E1000_VT_MSGTYPE_NACK;
5708
5709 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5710 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5711 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5712 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5713 vf_data->last_nack = jiffies;
4ae196df
AD		 5714 }
5715}
5716
f2ca0dbe 5717static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5718{
f2ca0dbe
AD		 5719 struct pci_dev *pdev = adapter->pdev;
5720 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5721 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5722 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5723 s32 retval;
5724
f2ca0dbe 5725 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5726
fef45f4c
AD		 5727 if (retval) {
5728 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5729 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5730 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5731 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5732 return;
5733 goto out;
5734 }
4ae196df
AD		 5735
5736 /* this is a message we already processed, do nothing */
5737 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5738 return;
4ae196df 5739
b980ac18 5740 /* until the vf completes a reset it should not be
4ae196df
AD		 5741 * allowed to start any configuration.
5742 */
4ae196df
AD		 5743 if (msgbuf[0] == E1000_VF_RESET) {
5744 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5745 return;
4ae196df
AD		 5746 }
5747
f2ca0dbe 5748 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5749 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5750 return;
5751 retval = -1;
5752 goto out;
4ae196df
AD		 5753 }
5754
5755 switch ((msgbuf[0] & 0xFFFF)) {
5756 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5757 retval = -EINVAL;
5758 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5759 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5760 else
5761 dev_warn(&pdev->dev,
b980ac18
JK		 5762 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5763 vf);
4ae196df 5764 break;
7d5753f0
AD		 5765 case E1000_VF_SET_PROMISC:
5766 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5767 break;
4ae196df
AD		 5768 case E1000_VF_SET_MULTICAST:
5769 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5770 break;
5771 case E1000_VF_SET_LPE:
5772 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5773 break;
5774 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5775 retval = -1;
5776 if (vf_data->pf_vlan)
5777 dev_warn(&pdev->dev,
b980ac18
JK		 5778 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5779 vf);
8151d294
WM		 5780 else
5781 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5782 break;
5783 default:
090b1795 5784 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5785 retval = -1;
5786 break;
5787 }
5788
fef45f4c
AD		 5789 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5790out:
4ae196df
AD		 5791 /* notify the VF of the results of what it sent us */
5792 if (retval)
5793 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5794 else
5795 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5796
4ae196df 5797 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5798}
4ae196df 5799
f2ca0dbe
AD		 5800static void igb_msg_task(struct igb_adapter *adapter)
5801{
5802 struct e1000_hw *hw = &adapter->hw;
5803 u32 vf;
5804
5805 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5806 /* process any reset requests */
5807 if (!igb_check_for_rst(hw, vf))
5808 igb_vf_reset_event(adapter, vf);
5809
5810 /* process any messages pending */
5811 if (!igb_check_for_msg(hw, vf))
5812 igb_rcv_msg_from_vf(adapter, vf);
5813
5814 /* process any acks */
5815 if (!igb_check_for_ack(hw, vf))
5816 igb_rcv_ack_from_vf(adapter, vf);
5817 }
4ae196df
AD		 5818}
5819
68d480c4
AD		 5820/**
5821 * igb_set_uta - Set unicast filter table address
5822 * @adapter: board private structure
5823 *
5824 * The unicast table address is a register array of 32-bit registers.
5825 * The table is meant to be used in a way similar to how the MTA is used
5826 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5827 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5828 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5829 **/
5830static void igb_set_uta(struct igb_adapter *adapter)
5831{
5832 struct e1000_hw *hw = &adapter->hw;
5833 int i;
5834
5835 /* The UTA table only exists on 82576 hardware and newer */
5836 if (hw->mac.type < e1000_82576)
5837 return;
5838
5839 /* we only need to do this if VMDq is enabled */
5840 if (!adapter->vfs_allocated_count)
5841 return;
5842
5843 for (i = 0; i < hw->mac.uta_reg_count; i++)
5844 array_wr32(E1000_UTA, i, ~0);
5845}
5846
9d5c8243 5847/**
b980ac18
JK		 5848 * igb_intr_msi - Interrupt Handler
5849 * @irq: interrupt number
5850 * @data: pointer to a network interface device structure
9d5c8243
AK		 5851 **/
5852static irqreturn_t igb_intr_msi(int irq, void *data)
5853{
047e0030
AD		 5854 struct igb_adapter *adapter = data;
5855 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5856 struct e1000_hw *hw = &adapter->hw;
5857 /* read ICR disables interrupts using IAM */
5858 u32 icr = rd32(E1000_ICR);
5859
047e0030 5860 igb_write_itr(q_vector);
9d5c8243 5861
7f081d40
AD		 5862 if (icr & E1000_ICR_DRSTA)
5863 schedule_work(&adapter->reset_task);
5864
047e0030 5865 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5866 /* HW is reporting DMA is out of sync */
5867 adapter->stats.doosync++;
5868 }
5869
9d5c8243
AK		 5870 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5871 hw->mac.get_link_status = 1;
5872 if (!test_bit(__IGB_DOWN, &adapter->state))
5873 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5874 }
5875
1f6e8178
MV		 5876 if (icr & E1000_ICR_TS) {
5877 u32 tsicr = rd32(E1000_TSICR);
5878
5879 if (tsicr & E1000_TSICR_TXTS) {
5880 /* acknowledge the interrupt */
5881 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5882 /* retrieve hardware timestamp */
5883 schedule_work(&adapter->ptp_tx_work);
5884 }
5885 }
1f6e8178 5886
047e0030 5887 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5888
5889 return IRQ_HANDLED;
5890}
5891
5892/**
b980ac18
JK		 5893 * igb_intr - Legacy Interrupt Handler
5894 * @irq: interrupt number
5895 * @data: pointer to a network interface device structure
9d5c8243
AK		 5896 **/
5897static irqreturn_t igb_intr(int irq, void *data)
5898{
047e0030
AD		 5899 struct igb_adapter *adapter = data;
5900 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5901 struct e1000_hw *hw = &adapter->hw;
5902 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5903 * need for the IMC write
5904 */
9d5c8243 5905 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5906
5907 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5908 * not set, then the adapter didn't send an interrupt
5909 */
9d5c8243
AK		 5910 if (!(icr & E1000_ICR_INT_ASSERTED))
5911 return IRQ_NONE;
5912
0ba82994
AD		 5913 igb_write_itr(q_vector);
5914
7f081d40
AD		 5915 if (icr & E1000_ICR_DRSTA)
5916 schedule_work(&adapter->reset_task);
5917
047e0030 5918 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5919 /* HW is reporting DMA is out of sync */
5920 adapter->stats.doosync++;
5921 }
5922
9d5c8243
AK		 5923 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5924 hw->mac.get_link_status = 1;
5925 /* guard against interrupt when we're going down */
5926 if (!test_bit(__IGB_DOWN, &adapter->state))
5927 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5928 }
5929
1f6e8178
MV		 5930 if (icr & E1000_ICR_TS) {
5931 u32 tsicr = rd32(E1000_TSICR);
5932
5933 if (tsicr & E1000_TSICR_TXTS) {
5934 /* acknowledge the interrupt */
5935 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5936 /* retrieve hardware timestamp */
5937 schedule_work(&adapter->ptp_tx_work);
5938 }
5939 }
1f6e8178 5940
047e0030 5941 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5942
5943 return IRQ_HANDLED;
5944}
5945
c50b52a0 5946static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5947{
047e0030 5948 struct igb_adapter *adapter = q_vector->adapter;
46544258 5949 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5950
0ba82994
AD		 5951 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5952 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5953 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5954 igb_set_itr(q_vector);
46544258 5955 else
047e0030 5956 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5957 }
5958
46544258
AD		 5959 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5960 if (adapter->msix_entries)
047e0030 5961 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5962 else
5963 igb_irq_enable(adapter);
5964 }
9d5c8243
AK		 5965}
5966
46544258 5967/**
b980ac18
JK		 5968 * igb_poll - NAPI Rx polling callback
5969 * @napi: napi polling structure
5970 * @budget: count of how many packets we should handle
46544258
AD		 5971 **/
5972static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5973{
047e0030 5974 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 5975 struct igb_q_vector,
5976 napi);
16eb8815 5977 bool clean_complete = true;
9d5c8243 5978
421e02f0 5979#ifdef CONFIG_IGB_DCA
047e0030
AD		 5980 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5981 igb_update_dca(q_vector);
fe4506b6 5982#endif
0ba82994 5983 if (q_vector->tx.ring)
13fde97a 5984 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 5985
0ba82994 5986 if (q_vector->rx.ring)
cd392f5c 5987 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 5988
16eb8815
AD		 5989 /* If all work not completed, return budget and keep polling */
5990 if (!clean_complete)
5991 return budget;
46544258 5992
9d5c8243 5993 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 5994 napi_complete(napi);
5995 igb_ring_irq_enable(q_vector);
9d5c8243 5996
16eb8815 5997 return 0;
9d5c8243 5998}
6d8126f9 5999
9d5c8243 6000/**
b980ac18
JK		 6001 * igb_clean_tx_irq - Reclaim resources after transmit completes
6002 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6003 *
b980ac18 6004 * returns true if ring is completely cleaned
9d5c8243 6005 **/
047e0030 6006static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6007{
047e0030 6008 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6009 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6010 struct igb_tx_buffer *tx_buffer;
f4128785 6011 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6012 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6013 unsigned int budget = q_vector->tx.work_limit;
8542db05 6014 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6015
13fde97a
AD		 6016 if (test_bit(__IGB_DOWN, &adapter->state))
6017 return true;
0e014cb1 6018
06034649 6019 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6020 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6021 i -= tx_ring->count;
9d5c8243 6022
f4128785
AD		 6023 do {
6024 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6025
6026 /* if next_to_watch is not set then there is no work pending */
6027 if (!eop_desc)
6028 break;
13fde97a 6029
f4128785 6030 /* prevent any other reads prior to eop_desc */
70d289bc 6031 read_barrier_depends();
f4128785 6032
13fde97a
AD		 6033 /* if DD is not set pending work has not been completed */
6034 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6035 break;
6036
8542db05
AD		 6037 /* clear next_to_watch to prevent false hangs */
6038 tx_buffer->next_to_watch = NULL;
9d5c8243 6039
ebe42d16
AD		 6040 /* update the statistics for this packet */
6041 total_bytes += tx_buffer->bytecount;
6042 total_packets += tx_buffer->gso_segs;
13fde97a 6043
ebe42d16
AD		 6044 /* free the skb */
6045 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6046
ebe42d16
AD		 6047 /* unmap skb header data */
6048 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6049 dma_unmap_addr(tx_buffer, dma),
6050 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6051 DMA_TO_DEVICE);
6052
c9f14bf3
AD		 6053 /* clear tx_buffer data */
6054 tx_buffer->skb = NULL;
6055 dma_unmap_len_set(tx_buffer, len, 0);
6056
ebe42d16
AD		 6057 /* clear last DMA location and unmap remaining buffers */
6058 while (tx_desc != eop_desc) {
13fde97a
AD		 6059 tx_buffer++;
6060 tx_desc++;
9d5c8243 6061 i++;
8542db05
AD		 6062 if (unlikely(!i)) {
6063 i -= tx_ring->count;
06034649 6064 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6065 tx_desc = IGB_TX_DESC(tx_ring, 0);
6066 }
ebe42d16
AD		 6067
6068 /* unmap any remaining paged data */
c9f14bf3 6069 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6070 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6071 dma_unmap_addr(tx_buffer, dma),
6072 dma_unmap_len(tx_buffer, len),
ebe42d16 6073 DMA_TO_DEVICE);
c9f14bf3 6074 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6075 }
6076 }
6077
ebe42d16
AD		 6078 /* move us one more past the eop_desc for start of next pkt */
6079 tx_buffer++;
6080 tx_desc++;
6081 i++;
6082 if (unlikely(!i)) {
6083 i -= tx_ring->count;
6084 tx_buffer = tx_ring->tx_buffer_info;
6085 tx_desc = IGB_TX_DESC(tx_ring, 0);
6086 }
f4128785
AD		 6087
6088 /* issue prefetch for next Tx descriptor */
6089 prefetch(tx_desc);
6090
6091 /* update budget accounting */
6092 budget--;
6093 } while (likely(budget));
0e014cb1 6094
bdbc0631
ED		 6095 netdev_tx_completed_queue(txring_txq(tx_ring),
6096 total_packets, total_bytes);
8542db05 6097 i += tx_ring->count;
9d5c8243 6098 tx_ring->next_to_clean = i;
13fde97a
AD		 6099 u64_stats_update_begin(&tx_ring->tx_syncp);
6100 tx_ring->tx_stats.bytes += total_bytes;
6101 tx_ring->tx_stats.packets += total_packets;
6102 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6103 q_vector->tx.total_bytes += total_bytes;
6104 q_vector->tx.total_packets += total_packets;
9d5c8243 6105
6d095fa8 6106 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6107 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6108
9d5c8243 6109 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6110 * check with the clearing of time_stamp and movement of i
6111 */
6d095fa8 6112 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6113 if (tx_buffer->next_to_watch &&
8542db05 6114 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6115 (adapter->tx_timeout_factor * HZ)) &&
6116 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6117
9d5c8243 6118 /* detected Tx unit hang */
59d71989 6119 dev_err(tx_ring->dev,
9d5c8243 6120 "Detected Tx Unit Hang\n"
2d064c06 6121 " Tx Queue <%d>\n"
9d5c8243
AK		 6122 " TDH <%x>\n"
6123 " TDT <%x>\n"
6124 " next_to_use <%x>\n"
6125 " next_to_clean <%x>\n"
9d5c8243
AK		 6126 "buffer_info[next_to_clean]\n"
6127 " time_stamp <%lx>\n"
8542db05 6128 " next_to_watch <%p>\n"
9d5c8243
AK		 6129 " jiffies <%lx>\n"
6130 " desc.status <%x>\n",
2d064c06 6131 tx_ring->queue_index,
238ac817 6132 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6133 readl(tx_ring->tail),
9d5c8243
AK		 6134 tx_ring->next_to_use,
6135 tx_ring->next_to_clean,
8542db05 6136 tx_buffer->time_stamp,
f4128785 6137 tx_buffer->next_to_watch,
9d5c8243 6138 jiffies,
f4128785 6139 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6140 netif_stop_subqueue(tx_ring->netdev,
6141 tx_ring->queue_index);
6142
6143 /* we are about to reset, no point in enabling stuff */
6144 return true;
9d5c8243
AK		 6145 }
6146 }
13fde97a 6147
21ba6fe1 6148#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6149 if (unlikely(total_packets &&
b980ac18
JK		 6150 netif_carrier_ok(tx_ring->netdev) &&
6151 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6152 /* Make sure that anybody stopping the queue after this
6153 * sees the new next_to_clean.
6154 */
6155 smp_mb();
6156 if (__netif_subqueue_stopped(tx_ring->netdev,
6157 tx_ring->queue_index) &&
6158 !(test_bit(__IGB_DOWN, &adapter->state))) {
6159 netif_wake_subqueue(tx_ring->netdev,
6160 tx_ring->queue_index);
6161
6162 u64_stats_update_begin(&tx_ring->tx_syncp);
6163 tx_ring->tx_stats.restart_queue++;
6164 u64_stats_update_end(&tx_ring->tx_syncp);
6165 }
6166 }
6167
6168 return !!budget;
9d5c8243
AK		 6169}
6170
cbc8e55f 6171/**
b980ac18
JK		 6172 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6173 * @rx_ring: rx descriptor ring to store buffers on
6174 * @old_buff: donor buffer to have page reused
cbc8e55f 6175 *
b980ac18 6176 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6177 **/
6178static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6179 struct igb_rx_buffer *old_buff)
6180{
6181 struct igb_rx_buffer *new_buff;
6182 u16 nta = rx_ring->next_to_alloc;
6183
6184 new_buff = &rx_ring->rx_buffer_info[nta];
6185
6186 /* update, and store next to alloc */
6187 nta++;
6188 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6189
6190 /* transfer page from old buffer to new buffer */
6191 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6192
6193 /* sync the buffer for use by the device */
6194 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6195 old_buff->page_offset,
de78d1f9 6196 IGB_RX_BUFSZ,
cbc8e55f
AD		 6197 DMA_FROM_DEVICE);
6198}
6199
74e238ea
AD		 6200static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6201 struct page *page,
6202 unsigned int truesize)
6203{
6204 /* avoid re-using remote pages */
6205 if (unlikely(page_to_nid(page) != numa_node_id()))
6206 return false;
6207
6208#if (PAGE_SIZE < 8192)
6209 /* if we are only owner of page we can reuse it */
6210 if (unlikely(page_count(page) != 1))
6211 return false;
6212
6213 /* flip page offset to other buffer */
6214 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6215
6216 /* since we are the only owner of the page and we need to
6217 * increment it, just set the value to 2 in order to avoid
6218 * an unnecessary locked operation
6219 */
6220 atomic_set(&page->_count, 2);
6221#else
6222 /* move offset up to the next cache line */
6223 rx_buffer->page_offset += truesize;
6224
6225 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6226 return false;
6227
6228 /* bump ref count on page before it is given to the stack */
6229 get_page(page);
6230#endif
6231
6232 return true;
6233}
6234
cbc8e55f 6235/**
b980ac18
JK		 6236 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6237 * @rx_ring: rx descriptor ring to transact packets on
6238 * @rx_buffer: buffer containing page to add
6239 * @rx_desc: descriptor containing length of buffer written by hardware
6240 * @skb: sk_buff to place the data into
cbc8e55f 6241 *
b980ac18
JK		 6242 * This function will add the data contained in rx_buffer->page to the skb.
6243 * This is done either through a direct copy if the data in the buffer is
6244 * less than the skb header size, otherwise it will just attach the page as
6245 * a frag to the skb.
cbc8e55f 6246 *
b980ac18
JK		 6247 * The function will then update the page offset if necessary and return
6248 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6249 **/
6250static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6251 struct igb_rx_buffer *rx_buffer,
6252 union e1000_adv_rx_desc *rx_desc,
6253 struct sk_buff *skb)
6254{
6255 struct page *page = rx_buffer->page;
6256 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6257#if (PAGE_SIZE < 8192)
6258 unsigned int truesize = IGB_RX_BUFSZ;
6259#else
6260 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6261#endif
cbc8e55f
AD		 6262
6263 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6264 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6265
cbc8e55f
AD		 6266 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6267 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6268 va += IGB_TS_HDR_LEN;
6269 size -= IGB_TS_HDR_LEN;
6270 }
6271
cbc8e55f
AD		 6272 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6273
6274 /* we can reuse buffer as-is, just make sure it is local */
6275 if (likely(page_to_nid(page) == numa_node_id()))
6276 return true;
6277
6278 /* this page cannot be reused so discard it */
6279 put_page(page);
6280 return false;
6281 }
6282
6283 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6284 rx_buffer->page_offset, size, truesize);
cbc8e55f 6285
74e238ea
AD		 6286 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6287}
cbc8e55f 6288
2e334eee
AD		 6289static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6290 union e1000_adv_rx_desc *rx_desc,
6291 struct sk_buff *skb)
6292{
6293 struct igb_rx_buffer *rx_buffer;
6294 struct page *page;
6295
6296 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6297
2e334eee
AD		 6298 page = rx_buffer->page;
6299 prefetchw(page);
6300
6301 if (likely(!skb)) {
6302 void *page_addr = page_address(page) +
6303 rx_buffer->page_offset;
6304
6305 /* prefetch first cache line of first page */
6306 prefetch(page_addr);
6307#if L1_CACHE_BYTES < 128
6308 prefetch(page_addr + L1_CACHE_BYTES);
6309#endif
6310
6311 /* allocate a skb to store the frags */
6312 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6313 IGB_RX_HDR_LEN);
6314 if (unlikely(!skb)) {
6315 rx_ring->rx_stats.alloc_failed++;
6316 return NULL;
6317 }
6318
b980ac18 6319 /* we will be copying header into skb->data in
2e334eee
AD		 6320 * pskb_may_pull so it is in our interest to prefetch
6321 * it now to avoid a possible cache miss
6322 */
6323 prefetchw(skb->data);
6324 }
6325
6326 /* we are reusing so sync this buffer for CPU use */
6327 dma_sync_single_range_for_cpu(rx_ring->dev,
6328 rx_buffer->dma,
6329 rx_buffer->page_offset,
de78d1f9 6330 IGB_RX_BUFSZ,
2e334eee
AD		 6331 DMA_FROM_DEVICE);
6332
6333 /* pull page into skb */
6334 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6335 /* hand second half of page back to the ring */
6336 igb_reuse_rx_page(rx_ring, rx_buffer);
6337 } else {
6338 /* we are not reusing the buffer so unmap it */
6339 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6340 PAGE_SIZE, DMA_FROM_DEVICE);
6341 }
6342
6343 /* clear contents of rx_buffer */
6344 rx_buffer->page = NULL;
6345
6346 return skb;
6347}
6348
cd392f5c 6349static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6350 union e1000_adv_rx_desc *rx_desc,
6351 struct sk_buff *skb)
9d5c8243 6352{
bc8acf2c 6353 skb_checksum_none_assert(skb);
9d5c8243 6354
294e7d78 6355 /* Ignore Checksum bit is set */
3ceb90fd 6356 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6357 return;
6358
6359 /* Rx checksum disabled via ethtool */
6360 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6361 return;
85ad76b2 6362
9d5c8243 6363 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6364 if (igb_test_staterr(rx_desc,
6365 E1000_RXDEXT_STATERR_TCPE |
6366 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6367 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6368 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6369 * packets, (aka let the stack check the crc32c)
6370 */
866cff06
AD		 6371 if (!((skb->len == 60) &&
6372 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6373 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6374 ring->rx_stats.csum_err++;
12dcd86b
ED		 6375 u64_stats_update_end(&ring->rx_syncp);
6376 }
9d5c8243 6377 /* let the stack verify checksum errors */
9d5c8243
AK		 6378 return;
6379 }
6380 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6381 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6382 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6383 skb->ip_summed = CHECKSUM_UNNECESSARY;
6384
3ceb90fd
AD		 6385 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6386 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6387}
6388
077887c3
AD		 6389static inline void igb_rx_hash(struct igb_ring *ring,
6390 union e1000_adv_rx_desc *rx_desc,
6391 struct sk_buff *skb)
6392{
6393 if (ring->netdev->features & NETIF_F_RXHASH)
6394 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6395}
6396
2e334eee 6397/**
b980ac18
JK		 6398 * igb_is_non_eop - process handling of non-EOP buffers
6399 * @rx_ring: Rx ring being processed
6400 * @rx_desc: Rx descriptor for current buffer
6401 * @skb: current socket buffer containing buffer in progress
2e334eee 6402 *
b980ac18
JK		 6403 * This function updates next to clean. If the buffer is an EOP buffer
6404 * this function exits returning false, otherwise it will place the
6405 * sk_buff in the next buffer to be chained and return true indicating
6406 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6407 **/
6408static bool igb_is_non_eop(struct igb_ring *rx_ring,
6409 union e1000_adv_rx_desc *rx_desc)
6410{
6411 u32 ntc = rx_ring->next_to_clean + 1;
6412
6413 /* fetch, update, and store next to clean */
6414 ntc = (ntc < rx_ring->count) ? ntc : 0;
6415 rx_ring->next_to_clean = ntc;
6416
6417 prefetch(IGB_RX_DESC(rx_ring, ntc));
6418
6419 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6420 return false;
6421
6422 return true;
6423}
6424
1a1c225b 6425/**
b980ac18
JK		 6426 * igb_get_headlen - determine size of header for LRO/GRO
6427 * @data: pointer to the start of the headers
6428 * @max_len: total length of section to find headers in
1a1c225b 6429 *
b980ac18
JK		 6430 * This function is meant to determine the length of headers that will
6431 * be recognized by hardware for LRO, and GRO offloads. The main
6432 * motivation of doing this is to only perform one pull for IPv4 TCP
6433 * packets so that we can do basic things like calculating the gso_size
6434 * based on the average data per packet.
1a1c225b
AD		 6435 **/
6436static unsigned int igb_get_headlen(unsigned char *data,
6437 unsigned int max_len)
6438{
6439 union {
6440 unsigned char *network;
6441 /* l2 headers */
6442 struct ethhdr *eth;
6443 struct vlan_hdr *vlan;
6444 /* l3 headers */
6445 struct iphdr *ipv4;
6446 struct ipv6hdr *ipv6;
6447 } hdr;
6448 __be16 protocol;
6449 u8 nexthdr = 0; /* default to not TCP */
6450 u8 hlen;
6451
6452 /* this should never happen, but better safe than sorry */
6453 if (max_len < ETH_HLEN)
6454 return max_len;
6455
6456 /* initialize network frame pointer */
6457 hdr.network = data;
6458
6459 /* set first protocol and move network header forward */
6460 protocol = hdr.eth->h_proto;
6461 hdr.network += ETH_HLEN;
6462
6463 /* handle any vlan tag if present */
6464 if (protocol == __constant_htons(ETH_P_8021Q)) {
6465 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6466 return max_len;
6467
6468 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6469 hdr.network += VLAN_HLEN;
6470 }
6471
6472 /* handle L3 protocols */
6473 if (protocol == __constant_htons(ETH_P_IP)) {
6474 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6475 return max_len;
6476
6477 /* access ihl as a u8 to avoid unaligned access on ia64 */
6478 hlen = (hdr.network[0] & 0x0F) << 2;
6479
6480 /* verify hlen meets minimum size requirements */
6481 if (hlen < sizeof(struct iphdr))
6482 return hdr.network - data;
6483
f2fb4ab2 6484 /* record next protocol if header is present */
b9555f66 6485 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6486 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6487 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6488 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6489 return max_len;
6490
6491 /* record next protocol */
6492 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6493 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6494 } else {
6495 return hdr.network - data;
6496 }
6497
f2fb4ab2
AD		 6498 /* relocate pointer to start of L4 header */
6499 hdr.network += hlen;
6500
1a1c225b
AD		 6501 /* finally sort out TCP */
6502 if (nexthdr == IPPROTO_TCP) {
6503 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6504 return max_len;
6505
6506 /* access doff as a u8 to avoid unaligned access on ia64 */
6507 hlen = (hdr.network[12] & 0xF0) >> 2;
6508
6509 /* verify hlen meets minimum size requirements */
6510 if (hlen < sizeof(struct tcphdr))
6511 return hdr.network - data;
6512
6513 hdr.network += hlen;
6514 } else if (nexthdr == IPPROTO_UDP) {
6515 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6516 return max_len;
6517
6518 hdr.network += sizeof(struct udphdr);
6519 }
6520
b980ac18 6521 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6522 * data section of the packet and will be the end of the header.
6523 * If not then it probably represents the end of the last recognized
6524 * header.
6525 */
6526 if ((hdr.network - data) < max_len)
6527 return hdr.network - data;
6528 else
6529 return max_len;
6530}
6531
6532/**
b980ac18
JK		 6533 * igb_pull_tail - igb specific version of skb_pull_tail
6534 * @rx_ring: rx descriptor ring packet is being transacted on
6535 * @rx_desc: pointer to the EOP Rx descriptor
6536 * @skb: pointer to current skb being adjusted
1a1c225b 6537 *
b980ac18
JK		 6538 * This function is an igb specific version of __pskb_pull_tail. The
6539 * main difference between this version and the original function is that
6540 * this function can make several assumptions about the state of things
6541 * that allow for significant optimizations versus the standard function.
6542 * As a result we can do things like drop a frag and maintain an accurate
6543 * truesize for the skb.
1a1c225b
AD		 6544 */
6545static void igb_pull_tail(struct igb_ring *rx_ring,
6546 union e1000_adv_rx_desc *rx_desc,
6547 struct sk_buff *skb)
2d94d8ab 6548{
1a1c225b
AD		 6549 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6550 unsigned char *va;
6551 unsigned int pull_len;
6552
b980ac18 6553 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6554 * working with pages allocated out of the lomem pool per
6555 * alloc_page(GFP_ATOMIC)
2d94d8ab 6556 */
1a1c225b
AD		 6557 va = skb_frag_address(frag);
6558
1a1c225b
AD		 6559 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6560 /* retrieve timestamp from buffer */
6561 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6562
6563 /* update pointers to remove timestamp header */
6564 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6565 frag->page_offset += IGB_TS_HDR_LEN;
6566 skb->data_len -= IGB_TS_HDR_LEN;
6567 skb->len -= IGB_TS_HDR_LEN;
6568
6569 /* move va to start of packet data */
6570 va += IGB_TS_HDR_LEN;
6571 }
6572
b980ac18 6573 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6574 * 60 bytes if the skb->len is less than 60 for skb_pad.
6575 */
6576 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6577
6578 /* align pull length to size of long to optimize memcpy performance */
6579 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6580
6581 /* update all of the pointers */
6582 skb_frag_size_sub(frag, pull_len);
6583 frag->page_offset += pull_len;
6584 skb->data_len -= pull_len;
6585 skb->tail += pull_len;
6586}
6587
6588/**
b980ac18
JK		 6589 * igb_cleanup_headers - Correct corrupted or empty headers
6590 * @rx_ring: rx descriptor ring packet is being transacted on
6591 * @rx_desc: pointer to the EOP Rx descriptor
6592 * @skb: pointer to current skb being fixed
1a1c225b 6593 *
b980ac18
JK		 6594 * Address the case where we are pulling data in on pages only
6595 * and as such no data is present in the skb header.
1a1c225b 6596 *
b980ac18
JK		 6597 * In addition if skb is not at least 60 bytes we need to pad it so that
6598 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6599 *
b980ac18 6600 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6601 **/
6602static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6603 union e1000_adv_rx_desc *rx_desc,
6604 struct sk_buff *skb)
6605{
1a1c225b
AD		 6606 if (unlikely((igb_test_staterr(rx_desc,
6607 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6608 struct net_device *netdev = rx_ring->netdev;
6609 if (!(netdev->features & NETIF_F_RXALL)) {
6610 dev_kfree_skb_any(skb);
6611 return true;
6612 }
6613 }
6614
6615 /* place header in linear portion of buffer */
6616 if (skb_is_nonlinear(skb))
6617 igb_pull_tail(rx_ring, rx_desc, skb);
6618
6619 /* if skb_pad returns an error the skb was freed */
6620 if (unlikely(skb->len < 60)) {
6621 int pad_len = 60 - skb->len;
6622
6623 if (skb_pad(skb, pad_len))
6624 return true;
6625 __skb_put(skb, pad_len);
6626 }
6627
6628 return false;
2d94d8ab
AD		 6629}
6630
db2ee5bd 6631/**
b980ac18
JK		 6632 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6633 * @rx_ring: rx descriptor ring packet is being transacted on
6634 * @rx_desc: pointer to the EOP Rx descriptor
6635 * @skb: pointer to current skb being populated
db2ee5bd 6636 *
b980ac18
JK		 6637 * This function checks the ring, descriptor, and packet information in
6638 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6639 * other fields within the skb.
db2ee5bd
AD		 6640 **/
6641static void igb_process_skb_fields(struct igb_ring *rx_ring,
6642 union e1000_adv_rx_desc *rx_desc,
6643 struct sk_buff *skb)
6644{
6645 struct net_device *dev = rx_ring->netdev;
6646
6647 igb_rx_hash(rx_ring, rx_desc, skb);
6648
6649 igb_rx_checksum(rx_ring, rx_desc, skb);
6650
20a48412 6651 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6652
f646968f 6653 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6654 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6655 u16 vid;
6656 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6657 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6658 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6659 else
6660 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6661
86a9bad3 6662 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6663 }
6664
6665 skb_record_rx_queue(skb, rx_ring->queue_index);
6666
6667 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6668}
6669
2e334eee 6670static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6671{
0ba82994 6672 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6673 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6674 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6675 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6676
2e334eee
AD		 6677 do {
6678 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6679
2e334eee
AD		 6680 /* return some buffers to hardware, one at a time is too slow */
6681 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6682 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6683 cleaned_count = 0;
6684 }
bf36c1a0 6685
2e334eee 6686 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6687
2e334eee
AD		 6688 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6689 break;
9d5c8243 6690
74e238ea
AD		 6691 /* This memory barrier is needed to keep us from reading
6692 * any other fields out of the rx_desc until we know the
6693 * RXD_STAT_DD bit is set
6694 */
6695 rmb();
6696
2e334eee 6697 /* retrieve a buffer from the ring */
f9d40f6a 6698 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6699
2e334eee
AD		 6700 /* exit if we failed to retrieve a buffer */
6701 if (!skb)
6702 break;
1a1c225b 6703
2e334eee 6704 cleaned_count++;
1a1c225b 6705
2e334eee
AD		 6706 /* fetch next buffer in frame if non-eop */
6707 if (igb_is_non_eop(rx_ring, rx_desc))
6708 continue;
1a1c225b
AD		 6709
6710 /* verify the packet layout is correct */
6711 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6712 skb = NULL;
6713 continue;
9d5c8243 6714 }
9d5c8243 6715
db2ee5bd 6716 /* probably a little skewed due to removing CRC */
3ceb90fd 6717 total_bytes += skb->len;
3ceb90fd 6718
db2ee5bd
AD		 6719 /* populate checksum, timestamp, VLAN, and protocol */
6720 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6721
b2cb09b1 6722 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6723
1a1c225b
AD		 6724 /* reset skb pointer */
6725 skb = NULL;
6726
2e334eee
AD		 6727 /* update budget accounting */
6728 total_packets++;
6729 } while (likely(total_packets < budget));
bf36c1a0 6730
1a1c225b
AD		 6731 /* place incomplete frames back on ring for completion */
6732 rx_ring->skb = skb;
6733
12dcd86b 6734 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6735 rx_ring->rx_stats.packets += total_packets;
6736 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6737 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6738 q_vector->rx.total_packets += total_packets;
6739 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6740
6741 if (cleaned_count)
cd392f5c 6742 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6743
2e334eee 6744 return (total_packets < budget);
9d5c8243
AK		 6745}
6746
c023cd88 6747static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6748 struct igb_rx_buffer *bi)
c023cd88
AD		 6749{
6750 struct page *page = bi->page;
cbc8e55f 6751 dma_addr_t dma;
c023cd88 6752
cbc8e55f
AD		 6753 /* since we are recycling buffers we should seldom need to alloc */
6754 if (likely(page))
c023cd88
AD		 6755 return true;
6756
cbc8e55f
AD		 6757 /* alloc new page for storage */
6758 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6759 if (unlikely(!page)) {
6760 rx_ring->rx_stats.alloc_failed++;
6761 return false;
c023cd88
AD		 6762 }
6763
cbc8e55f
AD		 6764 /* map page for use */
6765 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6766
b980ac18 6767 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6768 * there isn't much point in holding memory we can't use
6769 */
1a1c225b 6770 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6771 __free_page(page);
6772
c023cd88
AD		 6773 rx_ring->rx_stats.alloc_failed++;
6774 return false;
6775 }
6776
1a1c225b 6777 bi->dma = dma;
cbc8e55f
AD		 6778 bi->page = page;
6779 bi->page_offset = 0;
1a1c225b 6780
c023cd88
AD		 6781 return true;
6782}
6783
9d5c8243 6784/**
b980ac18
JK		 6785 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6786 * @adapter: address of board private structure
9d5c8243 6787 **/
cd392f5c 6788void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6789{
9d5c8243 6790 union e1000_adv_rx_desc *rx_desc;
06034649 6791 struct igb_rx_buffer *bi;
c023cd88 6792 u16 i = rx_ring->next_to_use;
9d5c8243 6793
cbc8e55f
AD		 6794 /* nothing to do */
6795 if (!cleaned_count)
6796 return;
6797
60136906 6798 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6799 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6800 i -= rx_ring->count;
9d5c8243 6801
cbc8e55f 6802 do {
1a1c225b 6803 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6804 break;
9d5c8243 6805
b980ac18 6806 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6807 * because each write-back erases this info.
6808 */
f9d40f6a 6809 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6810
c023cd88
AD		 6811 rx_desc++;
6812 bi++;
9d5c8243 6813 i++;
c023cd88 6814 if (unlikely(!i)) {
60136906 6815 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6816 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6817 i -= rx_ring->count;
6818 }
6819
6820 /* clear the hdr_addr for the next_to_use descriptor */
6821 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6822
6823 cleaned_count--;
6824 } while (cleaned_count);
9d5c8243 6825
c023cd88
AD		 6826 i += rx_ring->count;
6827
9d5c8243 6828 if (rx_ring->next_to_use != i) {
cbc8e55f 6829 /* record the next descriptor to use */
9d5c8243 6830 rx_ring->next_to_use = i;
9d5c8243 6831
cbc8e55f
AD		 6832 /* update next to alloc since we have filled the ring */
6833 rx_ring->next_to_alloc = i;
6834
b980ac18 6835 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6836 * know there are new descriptors to fetch. (Only
6837 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6838 * such as IA-64).
6839 */
9d5c8243 6840 wmb();
fce99e34 6841 writel(i, rx_ring->tail);
9d5c8243
AK		 6842 }
6843}
6844
6845/**
6846 * igb_mii_ioctl -
6847 * @netdev:
6848 * @ifreq:
6849 * @cmd:
6850 **/
6851static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6852{
6853 struct igb_adapter *adapter = netdev_priv(netdev);
6854 struct mii_ioctl_data *data = if_mii(ifr);
6855
6856 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6857 return -EOPNOTSUPP;
6858
6859 switch (cmd) {
6860 case SIOCGMIIPHY:
6861 data->phy_id = adapter->hw.phy.addr;
6862 break;
6863 case SIOCGMIIREG:
f5f4cf08
AD		 6864 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6865 &data->val_out))
9d5c8243
AK		 6866 return -EIO;
6867 break;
6868 case SIOCSMIIREG:
6869 default:
6870 return -EOPNOTSUPP;
6871 }
6872 return 0;
6873}
6874
6875/**
6876 * igb_ioctl -
6877 * @netdev:
6878 * @ifreq:
6879 * @cmd:
6880 **/
6881static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6882{
6883 switch (cmd) {
6884 case SIOCGMIIPHY:
6885 case SIOCGMIIREG:
6886 case SIOCSMIIREG:
6887 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6888 case SIOCSHWTSTAMP:
a79f4f88 6889 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6890 default:
6891 return -EOPNOTSUPP;
6892 }
6893}
6894
009bc06e
AD		 6895s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6896{
6897 struct igb_adapter *adapter = hw->back;
009bc06e 6898
23d028cc 6899 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6900 return -E1000_ERR_CONFIG;
6901
009bc06e
AD		 6902 return 0;
6903}
6904
6905s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6906{
6907 struct igb_adapter *adapter = hw->back;
009bc06e 6908
23d028cc 6909 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6910 return -E1000_ERR_CONFIG;
6911
009bc06e
AD		 6912 return 0;
6913}
6914
c8f44aff 6915static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6916{
6917 struct igb_adapter *adapter = netdev_priv(netdev);
6918 struct e1000_hw *hw = &adapter->hw;
6919 u32 ctrl, rctl;
f646968f 6920 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6921
5faf030c 6922 if (enable) {
9d5c8243
AK		 6923 /* enable VLAN tag insert/strip */
6924 ctrl = rd32(E1000_CTRL);
6925 ctrl |= E1000_CTRL_VME;
6926 wr32(E1000_CTRL, ctrl);
6927
51466239 6928 /* Disable CFI check */
9d5c8243 6929 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6930 rctl &= ~E1000_RCTL_CFIEN;
6931 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6932 } else {
6933 /* disable VLAN tag insert/strip */
6934 ctrl = rd32(E1000_CTRL);
6935 ctrl &= ~E1000_CTRL_VME;
6936 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6937 }
6938
e1739522 6939 igb_rlpml_set(adapter);
9d5c8243
AK		 6940}
6941
80d5c368
PM		 6942static int igb_vlan_rx_add_vid(struct net_device *netdev,
6943 __be16 proto, u16 vid)
9d5c8243
AK		 6944{
6945 struct igb_adapter *adapter = netdev_priv(netdev);
6946 struct e1000_hw *hw = &adapter->hw;
4ae196df 6947 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6948
51466239
AD		 6949 /* attempt to add filter to vlvf array */
6950 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6951
51466239
AD		 6952 /* add the filter since PF can receive vlans w/o entry in vlvf */
6953 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6954
6955 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6956
6957 return 0;
9d5c8243
AK		 6958}
6959
80d5c368
PM		 6960static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6961 __be16 proto, u16 vid)
9d5c8243
AK		 6962{
6963 struct igb_adapter *adapter = netdev_priv(netdev);
6964 struct e1000_hw *hw = &adapter->hw;
4ae196df 6965 int pf_id = adapter->vfs_allocated_count;
51466239 6966 s32 err;
9d5c8243 6967
51466239
AD		 6968 /* remove vlan from VLVF table array */
6969 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6970
51466239
AD		 6971 /* if vid was not present in VLVF just remove it from table */
6972 if (err)
4ae196df 6973 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6974
6975 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6976
6977 return 0;
9d5c8243
AK		 6978}
6979
6980static void igb_restore_vlan(struct igb_adapter *adapter)
6981{
b2cb09b1 6982 u16 vid;
9d5c8243 6983
5faf030c
AD		 6984 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6985
b2cb09b1 6986 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 6987 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 6988}
6989
14ad2513 6990int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 6991{
090b1795 6992 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 6993 struct e1000_mac_info *mac = &adapter->hw.mac;
6994
6995 mac->autoneg = 0;
6996
14ad2513 6997 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 6998 * for the switch() below to work
6999 */
14ad2513
DD		 7000 if ((spd & 1) || (dplx & ~1))
7001 goto err_inval;
7002
f502ef7d
AA		 7003 /* Fiber NIC's only allow 1000 gbps Full duplex
7004 * and 100Mbps Full duplex for 100baseFx sfp
7005 */
7006 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7007 switch (spd + dplx) {
7008 case SPEED_10 + DUPLEX_HALF:
7009 case SPEED_10 + DUPLEX_FULL:
7010 case SPEED_100 + DUPLEX_HALF:
7011 goto err_inval;
7012 default:
7013 break;
7014 }
7015 }
cd2638a8 7016
14ad2513 7017 switch (spd + dplx) {
9d5c8243
AK		 7018 case SPEED_10 + DUPLEX_HALF:
7019 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7020 break;
7021 case SPEED_10 + DUPLEX_FULL:
7022 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7023 break;
7024 case SPEED_100 + DUPLEX_HALF:
7025 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7026 break;
7027 case SPEED_100 + DUPLEX_FULL:
7028 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7029 break;
7030 case SPEED_1000 + DUPLEX_FULL:
7031 mac->autoneg = 1;
7032 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7033 break;
7034 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7035 default:
14ad2513 7036 goto err_inval;
9d5c8243 7037 }
8376dad0
JB		 7038
7039 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7040 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7041
9d5c8243 7042 return 0;
14ad2513
DD		 7043
7044err_inval:
7045 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7046 return -EINVAL;
9d5c8243
AK		 7047}
7048
749ab2cd
YZ		 7049static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7050 bool runtime)
9d5c8243
AK		 7051{
7052 struct net_device *netdev = pci_get_drvdata(pdev);
7053 struct igb_adapter *adapter = netdev_priv(netdev);
7054 struct e1000_hw *hw = &adapter->hw;
2d064c06 7055 u32 ctrl, rctl, status;
749ab2cd 7056 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7057#ifdef CONFIG_PM
7058 int retval = 0;
7059#endif
7060
7061 netif_device_detach(netdev);
7062
a88f10ec 7063 if (netif_running(netdev))
749ab2cd 7064 __igb_close(netdev, true);
a88f10ec 7065
047e0030 7066 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7067
7068#ifdef CONFIG_PM
7069 retval = pci_save_state(pdev);
7070 if (retval)
7071 return retval;
7072#endif
7073
7074 status = rd32(E1000_STATUS);
7075 if (status & E1000_STATUS_LU)
7076 wufc &= ~E1000_WUFC_LNKC;
7077
7078 if (wufc) {
7079 igb_setup_rctl(adapter);
ff41f8dc 7080 igb_set_rx_mode(netdev);
9d5c8243
AK		 7081
7082 /* turn on all-multi mode if wake on multicast is enabled */
7083 if (wufc & E1000_WUFC_MC) {
7084 rctl = rd32(E1000_RCTL);
7085 rctl |= E1000_RCTL_MPE;
7086 wr32(E1000_RCTL, rctl);
7087 }
7088
7089 ctrl = rd32(E1000_CTRL);
7090 /* advertise wake from D3Cold */
7091 #define E1000_CTRL_ADVD3WUC 0x00100000
7092 /* phy power management enable */
7093 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7094 ctrl |= E1000_CTRL_ADVD3WUC;
7095 wr32(E1000_CTRL, ctrl);
7096
9d5c8243 7097 /* Allow time for pending master requests to run */
330a6d6a 7098 igb_disable_pcie_master(hw);
9d5c8243
AK		 7099
7100 wr32(E1000_WUC, E1000_WUC_PME_EN);
7101 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7102 } else {
7103 wr32(E1000_WUC, 0);
7104 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7105 }
7106
3fe7c4c9
RW		 7107 *enable_wake = wufc || adapter->en_mng_pt;
7108 if (!*enable_wake)
88a268c1
NN		 7109 igb_power_down_link(adapter);
7110 else
7111 igb_power_up_link(adapter);
9d5c8243
AK		 7112
7113 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7114 * would have already happened in close and is redundant.
7115 */
9d5c8243
AK		 7116 igb_release_hw_control(adapter);
7117
7118 pci_disable_device(pdev);
7119
9d5c8243
AK		 7120 return 0;
7121}
7122
7123#ifdef CONFIG_PM
d9dd966d 7124#ifdef CONFIG_PM_SLEEP
749ab2cd 7125static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7126{
7127 int retval;
7128 bool wake;
749ab2cd 7129 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7130
749ab2cd 7131 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7132 if (retval)
7133 return retval;
7134
7135 if (wake) {
7136 pci_prepare_to_sleep(pdev);
7137 } else {
7138 pci_wake_from_d3(pdev, false);
7139 pci_set_power_state(pdev, PCI_D3hot);
7140 }
7141
7142 return 0;
7143}
d9dd966d 7144#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7145
749ab2cd 7146static int igb_resume(struct device *dev)
9d5c8243 7147{
749ab2cd 7148 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7149 struct net_device *netdev = pci_get_drvdata(pdev);
7150 struct igb_adapter *adapter = netdev_priv(netdev);
7151 struct e1000_hw *hw = &adapter->hw;
7152 u32 err;
7153
7154 pci_set_power_state(pdev, PCI_D0);
7155 pci_restore_state(pdev);
b94f2d77 7156 pci_save_state(pdev);
42bfd33a 7157
aed5dec3 7158 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7159 if (err) {
7160 dev_err(&pdev->dev,
7161 "igb: Cannot enable PCI device from suspend\n");
7162 return err;
7163 }
7164 pci_set_master(pdev);
7165
7166 pci_enable_wake(pdev, PCI_D3hot, 0);
7167 pci_enable_wake(pdev, PCI_D3cold, 0);
7168
53c7d064 7169 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7170 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7171 return -ENOMEM;
9d5c8243
AK		 7172 }
7173
9d5c8243 7174 igb_reset(adapter);
a8564f03
AD		 7175
7176 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7177 * driver.
7178 */
a8564f03
AD		 7179 igb_get_hw_control(adapter);
7180
9d5c8243
AK		 7181 wr32(E1000_WUS, ~0);
7182
749ab2cd 7183 if (netdev->flags & IFF_UP) {
0c2cc02e 7184 rtnl_lock();
749ab2cd 7185 err = __igb_open(netdev, true);
0c2cc02e 7186 rtnl_unlock();
a88f10ec
AD		 7187 if (err)
7188 return err;
7189 }
9d5c8243
AK		 7190
7191 netif_device_attach(netdev);
749ab2cd
YZ		 7192 return 0;
7193}
7194
7195#ifdef CONFIG_PM_RUNTIME
7196static int igb_runtime_idle(struct device *dev)
7197{
7198 struct pci_dev *pdev = to_pci_dev(dev);
7199 struct net_device *netdev = pci_get_drvdata(pdev);
7200 struct igb_adapter *adapter = netdev_priv(netdev);
7201
7202 if (!igb_has_link(adapter))
7203 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7204
7205 return -EBUSY;
7206}
7207
7208static int igb_runtime_suspend(struct device *dev)
7209{
7210 struct pci_dev *pdev = to_pci_dev(dev);
7211 int retval;
7212 bool wake;
7213
7214 retval = __igb_shutdown(pdev, &wake, 1);
7215 if (retval)
7216 return retval;
7217
7218 if (wake) {
7219 pci_prepare_to_sleep(pdev);
7220 } else {
7221 pci_wake_from_d3(pdev, false);
7222 pci_set_power_state(pdev, PCI_D3hot);
7223 }
9d5c8243 7224
9d5c8243
AK		 7225 return 0;
7226}
749ab2cd
YZ		 7227
7228static int igb_runtime_resume(struct device *dev)
7229{
7230 return igb_resume(dev);
7231}
7232#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7233#endif
7234
7235static void igb_shutdown(struct pci_dev *pdev)
7236{
3fe7c4c9
RW		 7237 bool wake;
7238
749ab2cd 7239 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7240
7241 if (system_state == SYSTEM_POWER_OFF) {
7242 pci_wake_from_d3(pdev, wake);
7243 pci_set_power_state(pdev, PCI_D3hot);
7244 }
9d5c8243
AK		 7245}
7246
fa44f2f1
GR		 7247#ifdef CONFIG_PCI_IOV
7248static int igb_sriov_reinit(struct pci_dev *dev)
7249{
7250 struct net_device *netdev = pci_get_drvdata(dev);
7251 struct igb_adapter *adapter = netdev_priv(netdev);
7252 struct pci_dev *pdev = adapter->pdev;
7253
7254 rtnl_lock();
7255
7256 if (netif_running(netdev))
7257 igb_close(netdev);
7258
7259 igb_clear_interrupt_scheme(adapter);
7260
7261 igb_init_queue_configuration(adapter);
7262
7263 if (igb_init_interrupt_scheme(adapter, true)) {
7264 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7265 return -ENOMEM;
7266 }
7267
7268 if (netif_running(netdev))
7269 igb_open(netdev);
7270
7271 rtnl_unlock();
7272
7273 return 0;
7274}
7275
7276static int igb_pci_disable_sriov(struct pci_dev *dev)
7277{
7278 int err = igb_disable_sriov(dev);
7279
7280 if (!err)
7281 err = igb_sriov_reinit(dev);
7282
7283 return err;
7284}
7285
7286static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7287{
7288 int err = igb_enable_sriov(dev, num_vfs);
7289
7290 if (err)
7291 goto out;
7292
7293 err = igb_sriov_reinit(dev);
7294 if (!err)
7295 return num_vfs;
7296
7297out:
7298 return err;
7299}
7300
7301#endif
7302static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7303{
7304#ifdef CONFIG_PCI_IOV
7305 if (num_vfs == 0)
7306 return igb_pci_disable_sriov(dev);
7307 else
7308 return igb_pci_enable_sriov(dev, num_vfs);
7309#endif
7310 return 0;
7311}
7312
9d5c8243 7313#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7314/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7315 * without having to re-enable interrupts. It's not called while
7316 * the interrupt routine is executing.
7317 */
7318static void igb_netpoll(struct net_device *netdev)
7319{
7320 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7321 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7322 struct igb_q_vector *q_vector;
9d5c8243 7323 int i;
9d5c8243 7324
047e0030 7325 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7326 q_vector = adapter->q_vector[i];
7327 if (adapter->msix_entries)
7328 wr32(E1000_EIMC, q_vector->eims_value);
7329 else
7330 igb_irq_disable(adapter);
047e0030 7331 napi_schedule(&q_vector->napi);
eebbbdba 7332 }
9d5c8243
AK		 7333}
7334#endif /* CONFIG_NET_POLL_CONTROLLER */
7335
7336/**
b980ac18
JK		 7337 * igb_io_error_detected - called when PCI error is detected
7338 * @pdev: Pointer to PCI device
7339 * @state: The current pci connection state
9d5c8243 7340 *
b980ac18
JK		 7341 * This function is called after a PCI bus error affecting
7342 * this device has been detected.
7343 **/
9d5c8243
AK		 7344static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7345 pci_channel_state_t state)
7346{
7347 struct net_device *netdev = pci_get_drvdata(pdev);
7348 struct igb_adapter *adapter = netdev_priv(netdev);
7349
7350 netif_device_detach(netdev);
7351
59ed6eec
AD		 7352 if (state == pci_channel_io_perm_failure)
7353 return PCI_ERS_RESULT_DISCONNECT;
7354
9d5c8243
AK		 7355 if (netif_running(netdev))
7356 igb_down(adapter);
7357 pci_disable_device(pdev);
7358
7359 /* Request a slot slot reset. */
7360 return PCI_ERS_RESULT_NEED_RESET;
7361}
7362
7363/**
b980ac18
JK		 7364 * igb_io_slot_reset - called after the pci bus has been reset.
7365 * @pdev: Pointer to PCI device
9d5c8243 7366 *
b980ac18
JK		 7367 * Restart the card from scratch, as if from a cold-boot. Implementation
7368 * resembles the first-half of the igb_resume routine.
7369 **/
9d5c8243
AK		 7370static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7371{
7372 struct net_device *netdev = pci_get_drvdata(pdev);
7373 struct igb_adapter *adapter = netdev_priv(netdev);
7374 struct e1000_hw *hw = &adapter->hw;
40a914fa 7375 pci_ers_result_t result;
42bfd33a 7376 int err;
9d5c8243 7377
aed5dec3 7378 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7379 dev_err(&pdev->dev,
7380 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7381 result = PCI_ERS_RESULT_DISCONNECT;
7382 } else {
7383 pci_set_master(pdev);
7384 pci_restore_state(pdev);
b94f2d77 7385 pci_save_state(pdev);
9d5c8243 7386
40a914fa
AD		 7387 pci_enable_wake(pdev, PCI_D3hot, 0);
7388 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7389
40a914fa
AD		 7390 igb_reset(adapter);
7391 wr32(E1000_WUS, ~0);
7392 result = PCI_ERS_RESULT_RECOVERED;
7393 }
9d5c8243 7394
ea943d41
JK		 7395 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7396 if (err) {
b980ac18
JK		 7397 dev_err(&pdev->dev,
7398 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7399 err);
ea943d41
JK		 7400 /* non-fatal, continue */
7401 }
40a914fa
AD		 7402
7403 return result;
9d5c8243
AK		 7404}
7405
7406/**
b980ac18
JK		 7407 * igb_io_resume - called when traffic can start flowing again.
7408 * @pdev: Pointer to PCI device
9d5c8243 7409 *
b980ac18
JK		 7410 * This callback is called when the error recovery driver tells us that
7411 * its OK to resume normal operation. Implementation resembles the
7412 * second-half of the igb_resume routine.
9d5c8243
AK		 7413 */
7414static void igb_io_resume(struct pci_dev *pdev)
7415{
7416 struct net_device *netdev = pci_get_drvdata(pdev);
7417 struct igb_adapter *adapter = netdev_priv(netdev);
7418
9d5c8243
AK		 7419 if (netif_running(netdev)) {
7420 if (igb_up(adapter)) {
7421 dev_err(&pdev->dev, "igb_up failed after reset\n");
7422 return;
7423 }
7424 }
7425
7426 netif_device_attach(netdev);
7427
7428 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7429 * driver.
7430 */
9d5c8243 7431 igb_get_hw_control(adapter);
9d5c8243
AK		 7432}
7433
26ad9178 7434static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7435 u8 qsel)
26ad9178
AD		 7436{
7437 u32 rar_low, rar_high;
7438 struct e1000_hw *hw = &adapter->hw;
7439
7440 /* HW expects these in little endian so we reverse the byte order
7441 * from network order (big endian) to little endian
7442 */
7443 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7444 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7445 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7446
7447 /* Indicate to hardware the Address is Valid. */
7448 rar_high |= E1000_RAH_AV;
7449
7450 if (hw->mac.type == e1000_82575)
7451 rar_high |= E1000_RAH_POOL_1 * qsel;
7452 else
7453 rar_high |= E1000_RAH_POOL_1 << qsel;
7454
7455 wr32(E1000_RAL(index), rar_low);
7456 wrfl();
7457 wr32(E1000_RAH(index), rar_high);
7458 wrfl();
7459}
7460
4ae196df 7461static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7462 int vf, unsigned char *mac_addr)
4ae196df
AD		 7463{
7464 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7465 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7466 * towards the first, as a result a collision should not be possible
7467 */
ff41f8dc 7468 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7469
37680117 7470 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7471
26ad9178 7472 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7473
7474 return 0;
7475}
7476
8151d294
WM		 7477static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7478{
7479 struct igb_adapter *adapter = netdev_priv(netdev);
7480 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7481 return -EINVAL;
7482 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7483 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7484 dev_info(&adapter->pdev->dev,
7485 "Reload the VF driver to make this change effective.");
8151d294 7486 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7487 dev_warn(&adapter->pdev->dev,
7488 "The VF MAC address has been set, but the PF device is not up.\n");
7489 dev_warn(&adapter->pdev->dev,
7490 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7491 }
7492 return igb_set_vf_mac(adapter, vf, mac);
7493}
7494
17dc566c
LL		 7495static int igb_link_mbps(int internal_link_speed)
7496{
7497 switch (internal_link_speed) {
7498 case SPEED_100:
7499 return 100;
7500 case SPEED_1000:
7501 return 1000;
7502 default:
7503 return 0;
7504 }
7505}
7506
7507static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7508 int link_speed)
7509{
7510 int rf_dec, rf_int;
7511 u32 bcnrc_val;
7512
7513 if (tx_rate != 0) {
7514 /* Calculate the rate factor values to set */
7515 rf_int = link_speed / tx_rate;
7516 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7517 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7518 tx_rate;
17dc566c
LL		 7519
7520 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7521 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7522 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7523 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7524 } else {
7525 bcnrc_val = 0;
7526 }
7527
7528 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7529 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7530 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7531 */
7532 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7533 wr32(E1000_RTTBCNRC, bcnrc_val);
7534}
7535
7536static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7537{
7538 int actual_link_speed, i;
7539 bool reset_rate = false;
7540
7541 /* VF TX rate limit was not set or not supported */
7542 if ((adapter->vf_rate_link_speed == 0) ||
7543 (adapter->hw.mac.type != e1000_82576))
7544 return;
7545
7546 actual_link_speed = igb_link_mbps(adapter->link_speed);
7547 if (actual_link_speed != adapter->vf_rate_link_speed) {
7548 reset_rate = true;
7549 adapter->vf_rate_link_speed = 0;
7550 dev_info(&adapter->pdev->dev,
b980ac18 7551 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7552 }
7553
7554 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7555 if (reset_rate)
7556 adapter->vf_data[i].tx_rate = 0;
7557
7558 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7559 adapter->vf_data[i].tx_rate,
7560 actual_link_speed);
17dc566c
LL		 7561 }
7562}
7563
8151d294
WM		 7564static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7565{
17dc566c
LL		 7566 struct igb_adapter *adapter = netdev_priv(netdev);
7567 struct e1000_hw *hw = &adapter->hw;
7568 int actual_link_speed;
7569
7570 if (hw->mac.type != e1000_82576)
7571 return -EOPNOTSUPP;
7572
7573 actual_link_speed = igb_link_mbps(adapter->link_speed);
7574 if ((vf >= adapter->vfs_allocated_count) ||
7575 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7576 (tx_rate < 0) || (tx_rate > actual_link_speed))
7577 return -EINVAL;
7578
7579 adapter->vf_rate_link_speed = actual_link_speed;
7580 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7581 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7582
7583 return 0;
8151d294
WM		 7584}
7585
70ea4783
LL		 7586static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7587 bool setting)
7588{
7589 struct igb_adapter *adapter = netdev_priv(netdev);
7590 struct e1000_hw *hw = &adapter->hw;
7591 u32 reg_val, reg_offset;
7592
7593 if (!adapter->vfs_allocated_count)
7594 return -EOPNOTSUPP;
7595
7596 if (vf >= adapter->vfs_allocated_count)
7597 return -EINVAL;
7598
7599 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7600 reg_val = rd32(reg_offset);
7601 if (setting)
7602 reg_val |= ((1 << vf) |
7603 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7604 else
7605 reg_val &= ~((1 << vf) |
7606 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7607 wr32(reg_offset, reg_val);
7608
7609 adapter->vf_data[vf].spoofchk_enabled = setting;
7610 return E1000_SUCCESS;
7611}
7612
8151d294
WM		 7613static int igb_ndo_get_vf_config(struct net_device *netdev,
7614 int vf, struct ifla_vf_info *ivi)
7615{
7616 struct igb_adapter *adapter = netdev_priv(netdev);
7617 if (vf >= adapter->vfs_allocated_count)
7618 return -EINVAL;
7619 ivi->vf = vf;
7620 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7621 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7622 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7623 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7624 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7625 return 0;
7626}
7627
4ae196df
AD		 7628static void igb_vmm_control(struct igb_adapter *adapter)
7629{
7630 struct e1000_hw *hw = &adapter->hw;
10d8e907 7631 u32 reg;
4ae196df 7632
52a1dd4d
AD		 7633 switch (hw->mac.type) {
7634 case e1000_82575:
f96a8a0b
CW		 7635 case e1000_i210:
7636 case e1000_i211:
ceb5f13b 7637 case e1000_i354:
52a1dd4d
AD		 7638 default:
7639 /* replication is not supported for 82575 */
4ae196df 7640 return;
52a1dd4d
AD		 7641 case e1000_82576:
7642 /* notify HW that the MAC is adding vlan tags */
7643 reg = rd32(E1000_DTXCTL);
7644 reg |= E1000_DTXCTL_VLAN_ADDED;
7645 wr32(E1000_DTXCTL, reg);
7646 case e1000_82580:
7647 /* enable replication vlan tag stripping */
7648 reg = rd32(E1000_RPLOLR);
7649 reg |= E1000_RPLOLR_STRVLAN;
7650 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7651 case e1000_i350:
7652 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7653 break;
7654 }
10d8e907 7655
d4960307
AD		 7656 if (adapter->vfs_allocated_count) {
7657 igb_vmdq_set_loopback_pf(hw, true);
7658 igb_vmdq_set_replication_pf(hw, true);
13800469 7659 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7660 adapter->vfs_allocated_count);
d4960307
AD		 7661 } else {
7662 igb_vmdq_set_loopback_pf(hw, false);
7663 igb_vmdq_set_replication_pf(hw, false);
7664 }
4ae196df
AD		 7665}
7666
b6e0c419
CW		 7667static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7668{
7669 struct e1000_hw *hw = &adapter->hw;
7670 u32 dmac_thr;
7671 u16 hwm;
7672
7673 if (hw->mac.type > e1000_82580) {
7674 if (adapter->flags & IGB_FLAG_DMAC) {
7675 u32 reg;
7676
7677 /* force threshold to 0. */
7678 wr32(E1000_DMCTXTH, 0);
7679
b980ac18 7680 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7681 * than the Rx threshold. Set hwm to PBA - max frame
7682 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7683 */
e8c626e9
MV		 7684 hwm = 64 * pba - adapter->max_frame_size / 16;
7685 if (hwm < 64 * (pba - 6))
7686 hwm = 64 * (pba - 6);
7687 reg = rd32(E1000_FCRTC);
7688 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7689 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7690 & E1000_FCRTC_RTH_COAL_MASK);
7691 wr32(E1000_FCRTC, reg);
7692
b980ac18 7693 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7694 * frame size, capping it at PBA - 10KB.
7695 */
7696 dmac_thr = pba - adapter->max_frame_size / 512;
7697 if (dmac_thr < pba - 10)
7698 dmac_thr = pba - 10;
b6e0c419
CW		 7699 reg = rd32(E1000_DMACR);
7700 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7701 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7702 & E1000_DMACR_DMACTHR_MASK);
7703
7704 /* transition to L0x or L1 if available..*/
7705 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7706
7707 /* watchdog timer= +-1000 usec in 32usec intervals */
7708 reg |= (1000 >> 5);
0c02dd98
MV		 7709
7710 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7711 if (hw->mac.type != e1000_i354)
7712 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7713
b6e0c419
CW		 7714 wr32(E1000_DMACR, reg);
7715
b980ac18 7716 /* no lower threshold to disable
b6e0c419
CW		 7717 * coalescing(smart fifb)-UTRESH=0
7718 */
7719 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7720
7721 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7722
7723 wr32(E1000_DMCTLX, reg);
7724
b980ac18 7725 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7726 * DMA coal
7727 */
7728 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7729 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7730
b980ac18 7731 /* make low power state decision controlled
b6e0c419
CW		 7732 * by DMA coal
7733 */
7734 reg = rd32(E1000_PCIEMISC);
7735 reg &= ~E1000_PCIEMISC_LX_DECISION;
7736 wr32(E1000_PCIEMISC, reg);
7737 } /* endif adapter->dmac is not disabled */
7738 } else if (hw->mac.type == e1000_82580) {
7739 u32 reg = rd32(E1000_PCIEMISC);
7740 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7741 wr32(E1000_DMACR, 0);
7742 }
7743}
7744
b980ac18
JK		 7745/**
7746 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7747 * @hw: pointer to hardware structure
7748 * @byte_offset: byte offset to read
7749 * @dev_addr: device address
7750 * @data: value read
7751 *
7752 * Performs byte read operation over I2C interface at
7753 * a specified device address.
b980ac18 7754 **/
441fc6fd 7755s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7756 u8 dev_addr, u8 *data)
441fc6fd
CW		 7757{
7758 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7759 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7760 s32 status;
7761 u16 swfw_mask = 0;
7762
7763 if (!this_client)
7764 return E1000_ERR_I2C;
7765
7766 swfw_mask = E1000_SWFW_PHY0_SM;
7767
7768 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7769 != E1000_SUCCESS)
7770 return E1000_ERR_SWFW_SYNC;
7771
7772 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7773 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7774
7775 if (status < 0)
7776 return E1000_ERR_I2C;
7777 else {
7778 *data = status;
7779 return E1000_SUCCESS;
7780 }
7781}
7782
b980ac18
JK		 7783/**
7784 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7785 * @hw: pointer to hardware structure
7786 * @byte_offset: byte offset to write
7787 * @dev_addr: device address
7788 * @data: value to write
7789 *
7790 * Performs byte write operation over I2C interface at
7791 * a specified device address.
b980ac18 7792 **/
441fc6fd 7793s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7794 u8 dev_addr, u8 data)
441fc6fd
CW		 7795{
7796 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7797 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7798 s32 status;
7799 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7800
7801 if (!this_client)
7802 return E1000_ERR_I2C;
7803
7804 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7805 return E1000_ERR_SWFW_SYNC;
7806 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7807 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7808
7809 if (status)
7810 return E1000_ERR_I2C;
7811 else
7812 return E1000_SUCCESS;
7813
7814}
9d5c8243 7815/* igb_main.c */
Linux kernel - Deliverables
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