projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
igb: Always enable VLAN 0 even if 8021q is not loaded
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
6fb46902
TF		 60#define MIN 3
61#define BUILD 0
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
32b3e08f 154static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 184#endif
9d5c8243 185
9d5c8243 186#ifdef CONFIG_PM
d9dd966d 187#ifdef CONFIG_PM_SLEEP
749ab2cd 188static int igb_suspend(struct device *);
d9dd966d 189#endif
749ab2cd 190static int igb_resume(struct device *);
749ab2cd
YZ		 191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
52285b76 949 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 950
047e0030 951 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 952 igb_msix_other, 0, netdev->name, adapter);
047e0030 953 if (err)
52285b76 954 goto err_out;
047e0030
AD		 955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
52285b76
SA		 959 vector++;
960
7b06a690 961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 962
0ba82994 963 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
047e0030 967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
047e0030 970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 971 q_vector->rx.ring->queue_index);
9d5c8243 972 else
047e0030
AD		 973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
9d5c8243 975 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
9d5c8243 978 if (err)
52285b76 979 goto err_free;
9d5c8243
AK		 980 }
981
9d5c8243
AK		 982 igb_configure_msix(adapter);
983 return 0;
52285b76
SA		 984
985err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994err_out:
9d5c8243
AK		 995 return err;
996}
997
5536d210 998/**
b980ac18
JK		 999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
5536d210 1002 *
02ef6e1d 1003 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
02ef6e1d
CW		 1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
17a402a0
CW		 1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
cb06d102
CP		 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
5536d210
AD		 1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
2439fc4d 1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1041
5536d210
AD		 1042 netif_napi_del(&q_vector->napi);
1043
02ef6e1d
CW		 1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
cd14ef54 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1051 pci_disable_msix(adapter->pdev);
cd14ef54 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1053 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1057}
1058
047e0030 1059/**
b980ac18
JK		 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
047e0030 1062 *
b980ac18
JK		 1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
047e0030
AD		 1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
5536d210
AD		 1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
047e0030 1073 adapter->num_q_vectors = 0;
5536d210 1074
02ef6e1d
CW		 1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
5536d210 1077 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1078 }
047e0030
AD		 1079}
1080
1081/**
b980ac18
JK		 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
047e0030 1084 *
b980ac18
JK		 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
047e0030
AD		 1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
047e0030
AD		 1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
9d5c8243
AK		 1093
1094/**
b980ac18
JK		 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
9d5c8243 1098 *
b980ac18
JK		 1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
9d5c8243 1101 **/
53c7d064 1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1103{
1104 int err;
1105 int numvecs, i;
1106
53c7d064
SA		 1107 if (!msix)
1108 goto msi_only;
cd14ef54 1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1110
83b7180d 1111 /* Number of supported queues. */
a99955fc 1112 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1117
b980ac18 1118 /* start with one vector for every Rx queue */
047e0030
AD		 1119 numvecs = adapter->num_rx_queues;
1120
b980ac18 1121 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
047e0030
AD		 1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
9d5c8243
AK		 1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
479d02df
AG		 1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
0c2cc02e 1138 return;
9d5c8243
AK		 1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
b709323d 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1156 wrfl();
2a3abf6d
AD		 1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
4fc82adf 1161 adapter->vfs_allocated_count = 0;
a99955fc 1162 adapter->rss_queues = 1;
4fc82adf 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1164 adapter->num_rx_queues = 1;
661086df 1165 adapter->num_tx_queues = 1;
047e0030 1166 adapter->num_q_vectors = 1;
9d5c8243 1167 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1168 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1169}
1170
5536d210
AD		 1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
047e0030 1178/**
b980ac18
JK		 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
047e0030 1187 *
b980ac18 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1189 **/
5536d210
AD		 1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
047e0030
AD		 1194{
1195 struct igb_q_vector *q_vector;
5536d210
AD		 1196 struct igb_ring *ring;
1197 int ring_count, size;
047e0030 1198
5536d210
AD		 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
02ef6e1d 1208 q_vector = adapter->q_vector[v_idx];
72ddef05 1209 if (!q_vector) {
02ef6e1d 1210 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
c0a06ee1 1215 memset(q_vector, 0, size);
72ddef05 1216 }
5536d210
AD		 1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
7b06a690 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
4e227667
AD		 1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
5536d210
AD		 1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
827da44c
JS		 1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
5536d210
AD		 1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
047e0030 1276 }
81c2fc22 1277
5536d210
AD		 1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
047e0030 1282
5536d210
AD		 1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
047e0030 1285
5536d210
AD		 1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
047e0030 1288
5536d210
AD		 1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1292
e52c0f96 1293 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1294 * have the tag byte-swapped.
b980ac18 1295 */
5536d210
AD		 1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1298
5536d210
AD		 1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
827da44c
JS		 1303 u64_stats_init(&ring->rx_syncp);
1304
5536d210
AD		 1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
047e0030
AD		 1310}
1311
5536d210 1312
047e0030 1313/**
b980ac18
JK		 1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
047e0030 1316 *
b980ac18
JK		 1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
047e0030 1319 **/
5536d210 1320static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1321{
5536d210
AD		 1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
047e0030 1327
5536d210
AD		 1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
047e0030 1332
5536d210
AD		 1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
047e0030 1339 }
047e0030 1340 }
5536d210
AD		 1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1345
5536d210
AD		 1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
047e0030 1359 return 0;
5536d210
AD		 1360
1361err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
047e0030
AD		 1370}
1371
1372/**
b980ac18
JK		 1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
047e0030 1376 *
b980ac18 1377 * This function initializes the interrupts and allocates all of the queues.
047e0030 1378 **/
53c7d064 1379static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1380{
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
53c7d064 1384 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
5536d210 1392 igb_cache_ring_register(adapter);
047e0030
AD		 1393
1394 return 0;
5536d210 1395
047e0030
AD		 1396err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399}
1400
9d5c8243 1401/**
b980ac18
JK		 1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
9d5c8243 1404 *
b980ac18
JK		 1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
9d5c8243
AK		 1407 **/
1408static int igb_request_irq(struct igb_adapter *adapter)
1409{
1410 struct net_device *netdev = adapter->netdev;
047e0030 1411 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1412 int err = 0;
1413
cd14ef54 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1415 err = igb_request_msix(adapter);
844290e5 1416 if (!err)
9d5c8243 1417 goto request_done;
9d5c8243 1418 /* fall back to MSI */
5536d210
AD		 1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
53c7d064 1421
047e0030 1422 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
047e0030 1425 goto request_done;
53c7d064 1426
047e0030
AD		 1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
53c7d064 1429 igb_configure(adapter);
9d5c8243 1430 }
844290e5 1431
c74d588e
AD		 1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
7dfc16fa 1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1436 netdev->name, adapter);
9d5c8243
AK		 1437 if (!err)
1438 goto request_done;
047e0030 1439
9d5c8243
AK		 1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
7dfc16fa 1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1443 }
1444
c74d588e 1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1446 netdev->name, adapter);
9d5c8243 1447
6cb5e577 1448 if (err)
c74d588e 1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1450 err);
9d5c8243
AK		 1451
1452request_done:
1453 return err;
1454}
1455
1456static void igb_free_irq(struct igb_adapter *adapter)
1457{
cd14ef54 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1459 int vector = 0, i;
1460
047e0030 1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1462
0d1ae7f4 1463 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1464 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1465 adapter->q_vector[i]);
047e0030
AD		 1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1468 }
9d5c8243
AK		 1469}
1470
1471/**
b980ac18
JK		 1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
9d5c8243
AK		 1474 **/
1475static void igb_irq_disable(struct igb_adapter *adapter)
1476{
1477 struct e1000_hw *hw = &adapter->hw;
1478
b980ac18 1479 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
cd14ef54 1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1484 u32 regval = rd32(E1000_EIAM);
9005df38 1485
2dfd1212
AD		 1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1490 }
844290e5
PW		 1491
1492 wr32(E1000_IAM, 0);
9d5c8243
AK		 1493 wr32(E1000_IMC, ~0);
1494 wrfl();
cd14ef54 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1496 int i;
9005df38 1497
81a61859
ET		 1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
9d5c8243
AK		 1503}
1504
1505/**
b980ac18
JK		 1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
9d5c8243
AK		 1508 **/
1509static void igb_irq_enable(struct igb_adapter *adapter)
1510{
1511 struct e1000_hw *hw = &adapter->hw;
1512
cd14ef54 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1515 u32 regval = rd32(E1000_EIAC);
9005df38 1516
2dfd1212
AD		 1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1521 if (adapter->vfs_allocated_count) {
4ae196df 1522 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
844290e5 1526 } else {
55cac248
AD		 1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
844290e5 1531 }
9d5c8243
AK		 1532}
1533
1534static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535{
51466239 1536 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1537 u16 vid = adapter->hw.mng_cookie.vlan_id;
1538 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1539
1540 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1541 /* add VID to filter table */
1542 igb_vfta_set(hw, vid, true);
1543 adapter->mng_vlan_id = vid;
1544 } else {
1545 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1546 }
1547
1548 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1549 (vid != old_vid) &&
b2cb09b1 1550 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1551 /* remove VID from filter table */
1552 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1553 }
1554}
1555
1556/**
b980ac18
JK		 1557 * igb_release_hw_control - release control of the h/w to f/w
1558 * @adapter: address of board private structure
9d5c8243 1559 *
b980ac18
JK		 1560 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1561 * For ASF and Pass Through versions of f/w this means that the
1562 * driver is no longer loaded.
9d5c8243
AK		 1563 **/
1564static void igb_release_hw_control(struct igb_adapter *adapter)
1565{
1566 struct e1000_hw *hw = &adapter->hw;
1567 u32 ctrl_ext;
1568
1569 /* Let firmware take over control of h/w */
1570 ctrl_ext = rd32(E1000_CTRL_EXT);
1571 wr32(E1000_CTRL_EXT,
1572 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1573}
1574
9d5c8243 1575/**
b980ac18
JK		 1576 * igb_get_hw_control - get control of the h/w from f/w
1577 * @adapter: address of board private structure
9d5c8243 1578 *
b980ac18
JK		 1579 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1580 * For ASF and Pass Through versions of f/w this means that
1581 * the driver is loaded.
9d5c8243
AK		 1582 **/
1583static void igb_get_hw_control(struct igb_adapter *adapter)
1584{
1585 struct e1000_hw *hw = &adapter->hw;
1586 u32 ctrl_ext;
1587
1588 /* Let firmware know the driver has taken over */
1589 ctrl_ext = rd32(E1000_CTRL_EXT);
1590 wr32(E1000_CTRL_EXT,
1591 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1592}
1593
9d5c8243 1594/**
b980ac18
JK		 1595 * igb_configure - configure the hardware for RX and TX
1596 * @adapter: private board structure
9d5c8243
AK		 1597 **/
1598static void igb_configure(struct igb_adapter *adapter)
1599{
1600 struct net_device *netdev = adapter->netdev;
1601 int i;
1602
1603 igb_get_hw_control(adapter);
ff41f8dc 1604 igb_set_rx_mode(netdev);
9d5c8243
AK		 1605
1606 igb_restore_vlan(adapter);
9d5c8243 1607
85b430b4 1608 igb_setup_tctl(adapter);
06cf2666 1609 igb_setup_mrqc(adapter);
9d5c8243 1610 igb_setup_rctl(adapter);
85b430b4
AD		 1611
1612 igb_configure_tx(adapter);
9d5c8243 1613 igb_configure_rx(adapter);
662d7205
AD		 1614
1615 igb_rx_fifo_flush_82575(&adapter->hw);
1616
c493ea45 1617 /* call igb_desc_unused which always leaves
9d5c8243 1618 * at least 1 descriptor unused to make sure
b980ac18
JK		 1619 * next_to_use != next_to_clean
1620 */
9d5c8243 1621 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1622 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1623 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1624 }
9d5c8243
AK		 1625}
1626
88a268c1 1627/**
b980ac18
JK		 1628 * igb_power_up_link - Power up the phy/serdes link
1629 * @adapter: address of board private structure
88a268c1
NN		 1630 **/
1631void igb_power_up_link(struct igb_adapter *adapter)
1632{
76886596
AA		 1633 igb_reset_phy(&adapter->hw);
1634
88a268c1
NN		 1635 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1636 igb_power_up_phy_copper(&adapter->hw);
1637 else
1638 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1639
1640 igb_setup_link(&adapter->hw);
88a268c1
NN		 1641}
1642
1643/**
b980ac18
JK		 1644 * igb_power_down_link - Power down the phy/serdes link
1645 * @adapter: address of board private structure
88a268c1
NN		 1646 */
1647static void igb_power_down_link(struct igb_adapter *adapter)
1648{
1649 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1650 igb_power_down_phy_copper_82575(&adapter->hw);
1651 else
1652 igb_shutdown_serdes_link_82575(&adapter->hw);
1653}
9d5c8243 1654
56cec249
CW		 1655/**
1656 * Detect and switch function for Media Auto Sense
1657 * @adapter: address of the board private structure
1658 **/
1659static void igb_check_swap_media(struct igb_adapter *adapter)
1660{
1661 struct e1000_hw *hw = &adapter->hw;
1662 u32 ctrl_ext, connsw;
1663 bool swap_now = false;
1664
1665 ctrl_ext = rd32(E1000_CTRL_EXT);
1666 connsw = rd32(E1000_CONNSW);
1667
1668 /* need to live swap if current media is copper and we have fiber/serdes
1669 * to go to.
1670 */
1671
1672 if ((hw->phy.media_type == e1000_media_type_copper) &&
1673 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1674 swap_now = true;
1675 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1676 /* copper signal takes time to appear */
1677 if (adapter->copper_tries < 4) {
1678 adapter->copper_tries++;
1679 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1680 wr32(E1000_CONNSW, connsw);
1681 return;
1682 } else {
1683 adapter->copper_tries = 0;
1684 if ((connsw & E1000_CONNSW_PHYSD) &&
1685 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1686 swap_now = true;
1687 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1688 wr32(E1000_CONNSW, connsw);
1689 }
1690 }
1691 }
1692
1693 if (!swap_now)
1694 return;
1695
1696 switch (hw->phy.media_type) {
1697 case e1000_media_type_copper:
1698 netdev_info(adapter->netdev,
1699 "MAS: changing media to fiber/serdes\n");
1700 ctrl_ext |=
1701 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1702 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1703 adapter->copper_tries = 0;
1704 break;
1705 case e1000_media_type_internal_serdes:
1706 case e1000_media_type_fiber:
1707 netdev_info(adapter->netdev,
1708 "MAS: changing media to copper\n");
1709 ctrl_ext &=
1710 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1711 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1712 break;
1713 default:
1714 /* shouldn't get here during regular operation */
1715 netdev_err(adapter->netdev,
1716 "AMS: Invalid media type found, returning\n");
1717 break;
1718 }
1719 wr32(E1000_CTRL_EXT, ctrl_ext);
1720}
1721
9d5c8243 1722/**
b980ac18
JK		 1723 * igb_up - Open the interface and prepare it to handle traffic
1724 * @adapter: board private structure
9d5c8243 1725 **/
9d5c8243
AK		 1726int igb_up(struct igb_adapter *adapter)
1727{
1728 struct e1000_hw *hw = &adapter->hw;
1729 int i;
1730
1731 /* hardware has been reset, we need to reload some things */
1732 igb_configure(adapter);
1733
1734 clear_bit(__IGB_DOWN, &adapter->state);
1735
0d1ae7f4
AD		 1736 for (i = 0; i < adapter->num_q_vectors; i++)
1737 napi_enable(&(adapter->q_vector[i]->napi));
1738
cd14ef54 1739 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1740 igb_configure_msix(adapter);
feeb2721
AD		 1741 else
1742 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1743
1744 /* Clear any pending interrupts. */
1745 rd32(E1000_ICR);
1746 igb_irq_enable(adapter);
1747
d4960307
AD		 1748 /* notify VFs that reset has been completed */
1749 if (adapter->vfs_allocated_count) {
1750 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1751
d4960307
AD		 1752 reg_data |= E1000_CTRL_EXT_PFRSTD;
1753 wr32(E1000_CTRL_EXT, reg_data);
1754 }
1755
4cb9be7a
JB		 1756 netif_tx_start_all_queues(adapter->netdev);
1757
25568a53
AD		 1758 /* start the watchdog. */
1759 hw->mac.get_link_status = 1;
1760 schedule_work(&adapter->watchdog_task);
1761
f4c01e96
CW		 1762 if ((adapter->flags & IGB_FLAG_EEE) &&
1763 (!hw->dev_spec._82575.eee_disable))
1764 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1765
9d5c8243
AK		 1766 return 0;
1767}
1768
1769void igb_down(struct igb_adapter *adapter)
1770{
9d5c8243 1771 struct net_device *netdev = adapter->netdev;
330a6d6a 1772 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1773 u32 tctl, rctl;
1774 int i;
1775
1776 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1777 * reschedule our watchdog timer
1778 */
9d5c8243
AK		 1779 set_bit(__IGB_DOWN, &adapter->state);
1780
1781 /* disable receives in the hardware */
1782 rctl = rd32(E1000_RCTL);
1783 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1784 /* flush and sleep below */
1785
f28ea083 1786 netif_carrier_off(netdev);
fd2ea0a7 1787 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1788
1789 /* disable transmits in the hardware */
1790 tctl = rd32(E1000_TCTL);
1791 tctl &= ~E1000_TCTL_EN;
1792 wr32(E1000_TCTL, tctl);
1793 /* flush both disables and wait for them to finish */
1794 wrfl();
0d451e79 1795 usleep_range(10000, 11000);
9d5c8243 1796
41f149a2
CW		 1797 igb_irq_disable(adapter);
1798
aa9b8cc4
AA		 1799 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1800
41f149a2 1801 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1802 if (adapter->q_vector[i]) {
1803 napi_synchronize(&adapter->q_vector[i]->napi);
1804 napi_disable(&adapter->q_vector[i]->napi);
1805 }
41f149a2 1806 }
9d5c8243 1807
9d5c8243
AK		 1808 del_timer_sync(&adapter->watchdog_timer);
1809 del_timer_sync(&adapter->phy_info_timer);
1810
04fe6358 1811 /* record the stats before reset*/
12dcd86b
ED		 1812 spin_lock(&adapter->stats64_lock);
1813 igb_update_stats(adapter, &adapter->stats64);
1814 spin_unlock(&adapter->stats64_lock);
04fe6358 1815
9d5c8243
AK		 1816 adapter->link_speed = 0;
1817 adapter->link_duplex = 0;
1818
3023682e
JK		 1819 if (!pci_channel_offline(adapter->pdev))
1820 igb_reset(adapter);
9d5c8243
AK		 1821 igb_clean_all_tx_rings(adapter);
1822 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1823#ifdef CONFIG_IGB_DCA
1824
1825 /* since we reset the hardware DCA settings were cleared */
1826 igb_setup_dca(adapter);
1827#endif
9d5c8243
AK		 1828}
1829
1830void igb_reinit_locked(struct igb_adapter *adapter)
1831{
1832 WARN_ON(in_interrupt());
1833 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1834 usleep_range(1000, 2000);
9d5c8243
AK		 1835 igb_down(adapter);
1836 igb_up(adapter);
1837 clear_bit(__IGB_RESETTING, &adapter->state);
1838}
1839
56cec249
CW		 1840/** igb_enable_mas - Media Autosense re-enable after swap
1841 *
1842 * @adapter: adapter struct
1843 **/
8cfb879d 1844static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1845{
1846 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1847 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1848
1849 /* configure for SerDes media detect */
8cfb879d
TF		 1850 if ((hw->phy.media_type == e1000_media_type_copper) &&
1851 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1852 connsw |= E1000_CONNSW_ENRGSRC;
1853 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1854 wr32(E1000_CONNSW, connsw);
1855 wrfl();
56cec249 1856 }
56cec249
CW		 1857}
1858
9d5c8243
AK		 1859void igb_reset(struct igb_adapter *adapter)
1860{
090b1795 1861 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1862 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1863 struct e1000_mac_info *mac = &hw->mac;
1864 struct e1000_fc_info *fc = &hw->fc;
45693bcb 1865 u32 pba, hwm;
9d5c8243
AK		 1866
1867 /* Repartition Pba for greater than 9k mtu
1868 * To take effect CTRL.RST is required.
1869 */
fa4dfae0 1870 switch (mac->type) {
d2ba2ed8 1871 case e1000_i350:
ceb5f13b 1872 case e1000_i354:
55cac248
AD		 1873 case e1000_82580:
1874 pba = rd32(E1000_RXPBS);
1875 pba = igb_rxpbs_adjust_82580(pba);
1876 break;
fa4dfae0 1877 case e1000_82576:
d249be54
AD		 1878 pba = rd32(E1000_RXPBS);
1879 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1880 break;
1881 case e1000_82575:
f96a8a0b
CW		 1882 case e1000_i210:
1883 case e1000_i211:
fa4dfae0
AD		 1884 default:
1885 pba = E1000_PBA_34K;
1886 break;
2d064c06 1887 }
9d5c8243 1888
45693bcb
AD		 1889 if (mac->type == e1000_82575) {
1890 u32 min_rx_space, min_tx_space, needed_tx_space;
1891
1892 /* write Rx PBA so that hardware can report correct Tx PBA */
9d5c8243
AK		 1893 wr32(E1000_PBA, pba);
1894
1895 /* To maintain wire speed transmits, the Tx FIFO should be
1896 * large enough to accommodate two full transmit packets,
1897 * rounded up to the next 1KB and expressed in KB. Likewise,
1898 * the Rx FIFO should be large enough to accommodate at least
1899 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1900 * expressed in KB.
1901 */
45693bcb
AD		 1902 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1903
1904 /* The Tx FIFO also stores 16 bytes of information about the Tx
1905 * but don't include Ethernet FCS because hardware appends it.
1906 * We only need to round down to the nearest 512 byte block
1907 * count since the value we care about is 2 frames, not 1.
b980ac18 1908 */
45693bcb
AD		 1909 min_tx_space = adapter->max_frame_size;
1910 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1911 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1912
1913 /* upper 16 bits has Tx packet buffer allocation size in KB */
1914 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
9d5c8243
AK		 1915
1916 /* If current Tx allocation is less than the min Tx FIFO size,
1917 * and the min Tx FIFO size is less than the current Rx FIFO
45693bcb 1918 * allocation, take space away from current Rx allocation.
b980ac18 1919 */
45693bcb
AD		 1920 if (needed_tx_space < pba) {
1921 pba -= needed_tx_space;
9d5c8243 1922
b980ac18
JK		 1923 /* if short on Rx space, Rx wins and must trump Tx
1924 * adjustment
1925 */
9d5c8243
AK		 1926 if (pba < min_rx_space)
1927 pba = min_rx_space;
1928 }
45693bcb
AD		 1929
1930 /* adjust PBA for jumbo frames */
2d064c06 1931 wr32(E1000_PBA, pba);
9d5c8243 1932 }
9d5c8243 1933
45693bcb
AD		 1934 /* flow control settings
1935 * The high water mark must be low enough to fit one full frame
1936 * after transmitting the pause frame. As such we must have enough
1937 * space to allow for us to complete our current transmit and then
1938 * receive the frame that is in progress from the link partner.
1939 * Set it to:
1940 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
b980ac18 1941 */
45693bcb 1942 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
9d5c8243 1943
d48507fe 1944 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1945 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1946 fc->pause_time = 0xFFFF;
1947 fc->send_xon = 1;
0cce119a 1948 fc->current_mode = fc->requested_mode;
9d5c8243 1949
4ae196df
AD		 1950 /* disable receive for all VFs and wait one second */
1951 if (adapter->vfs_allocated_count) {
1952 int i;
9005df38 1953
4ae196df 1954 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1955 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1956
1957 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1958 igb_ping_all_vfs(adapter);
4ae196df
AD		 1959
1960 /* disable transmits and receives */
1961 wr32(E1000_VFRE, 0);
1962 wr32(E1000_VFTE, 0);
1963 }
1964
9d5c8243 1965 /* Allow time for pending master requests to run */
330a6d6a 1966 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1967 wr32(E1000_WUC, 0);
1968
56cec249
CW		 1969 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1970 /* need to resetup here after media swap */
1971 adapter->ei.get_invariants(hw);
1972 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1973 }
8cfb879d
TF		 1974 if ((mac->type == e1000_82575) &&
1975 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1976 igb_enable_mas(adapter);
56cec249 1977 }
330a6d6a 1978 if (hw->mac.ops.init_hw(hw))
090b1795 1979 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1980
b980ac18 1981 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1982 * control is off when forcing speed.
1983 */
1984 if (!hw->mac.autoneg)
1985 igb_force_mac_fc(hw);
1986
b6e0c419 1987 igb_init_dmac(adapter, pba);
e428893b
CW		 1988#ifdef CONFIG_IGB_HWMON
1989 /* Re-initialize the thermal sensor on i350 devices. */
1990 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1991 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1992 /* If present, re-initialize the external thermal sensor
1993 * interface.
1994 */
1995 if (adapter->ets)
1996 mac->ops.init_thermal_sensor_thresh(hw);
1997 }
1998 }
1999#endif
b936136d 2000 /* Re-establish EEE setting */
f4c01e96
CW		 2001 if (hw->phy.media_type == e1000_media_type_copper) {
2002 switch (mac->type) {
2003 case e1000_i350:
2004 case e1000_i210:
2005 case e1000_i211:
c4c112f1 2006 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2007 break;
2008 case e1000_i354:
c4c112f1 2009 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2010 break;
2011 default:
2012 break;
2013 }
2014 }
88a268c1
NN		 2015 if (!netif_running(adapter->netdev))
2016 igb_power_down_link(adapter);
2017
9d5c8243
AK		 2018 igb_update_mng_vlan(adapter);
2019
2020 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2021 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2022
1f6e8178
MV		 2023 /* Re-enable PTP, where applicable. */
2024 igb_ptp_reset(adapter);
1f6e8178 2025
330a6d6a 2026 igb_get_phy_info(hw);
9d5c8243
AK		 2027}
2028
c8f44aff
MM		 2029static netdev_features_t igb_fix_features(struct net_device *netdev,
2030 netdev_features_t features)
b2cb09b1 2031{
b980ac18
JK		 2032 /* Since there is no support for separate Rx/Tx vlan accel
2033 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2034 */
f646968f
PM		 2035 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2036 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2037 else
f646968f 2038 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2039
2040 return features;
2041}
2042
c8f44aff
MM		 2043static int igb_set_features(struct net_device *netdev,
2044 netdev_features_t features)
ac52caa3 2045{
c8f44aff 2046 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2047 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2048
f646968f 2049 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2050 igb_vlan_mode(netdev, features);
2051
89eaefb6
BG		 2052 if (!(changed & NETIF_F_RXALL))
2053 return 0;
2054
2055 netdev->features = features;
2056
2057 if (netif_running(netdev))
2058 igb_reinit_locked(adapter);
2059 else
2060 igb_reset(adapter);
2061
ac52caa3
MM		 2062 return 0;
2063}
2064
2e5c6922 2065static const struct net_device_ops igb_netdev_ops = {
559e9c49 2066 .ndo_open = igb_open,
2e5c6922 2067 .ndo_stop = igb_close,
cd392f5c 2068 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2069 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2070 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2071 .ndo_set_mac_address = igb_set_mac,
2072 .ndo_change_mtu = igb_change_mtu,
2073 .ndo_do_ioctl = igb_ioctl,
2074 .ndo_tx_timeout = igb_tx_timeout,
2075 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2076 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2077 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2078 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2079 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2080 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2081 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2082 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2083#ifdef CONFIG_NET_POLL_CONTROLLER
2084 .ndo_poll_controller = igb_netpoll,
2085#endif
b2cb09b1
JP		 2086 .ndo_fix_features = igb_fix_features,
2087 .ndo_set_features = igb_set_features,
1abbc98a 2088 .ndo_features_check = passthru_features_check,
2e5c6922
SH		 2089};
2090
d67974f0
CW		 2091/**
2092 * igb_set_fw_version - Configure version string for ethtool
2093 * @adapter: adapter struct
d67974f0
CW		 2094 **/
2095void igb_set_fw_version(struct igb_adapter *adapter)
2096{
2097 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2098 struct e1000_fw_version fw;
2099
2100 igb_get_fw_version(hw, &fw);
2101
2102 switch (hw->mac.type) {
7dc98a62 2103 case e1000_i210:
0b1a6f2e 2104 case e1000_i211:
7dc98a62
CW		 2105 if (!(igb_get_flash_presence_i210(hw))) {
2106 snprintf(adapter->fw_version,
2107 sizeof(adapter->fw_version),
2108 "%2d.%2d-%d",
2109 fw.invm_major, fw.invm_minor,
2110 fw.invm_img_type);
2111 break;
2112 }
2113 /* fall through */
0b1a6f2e
CW		 2114 default:
2115 /* if option is rom valid, display its version too */
2116 if (fw.or_valid) {
2117 snprintf(adapter->fw_version,
2118 sizeof(adapter->fw_version),
2119 "%d.%d, 0x%08x, %d.%d.%d",
2120 fw.eep_major, fw.eep_minor, fw.etrack_id,
2121 fw.or_major, fw.or_build, fw.or_patch);
2122 /* no option rom */
7dc98a62 2123 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2124 snprintf(adapter->fw_version,
7dc98a62
CW		 2125 sizeof(adapter->fw_version),
2126 "%d.%d, 0x%08x",
2127 fw.eep_major, fw.eep_minor, fw.etrack_id);
2128 } else {
2129 snprintf(adapter->fw_version,
2130 sizeof(adapter->fw_version),
2131 "%d.%d.%d",
2132 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2133 }
2134 break;
d67974f0 2135 }
d67974f0
CW		 2136}
2137
56cec249
CW		 2138/**
2139 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2140 *
2141 * @adapter: adapter struct
2142 **/
2143static void igb_init_mas(struct igb_adapter *adapter)
2144{
2145 struct e1000_hw *hw = &adapter->hw;
2146 u16 eeprom_data;
2147
2148 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2149 switch (hw->bus.func) {
2150 case E1000_FUNC_0:
2151 if (eeprom_data & IGB_MAS_ENABLE_0) {
2152 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2153 netdev_info(adapter->netdev,
2154 "MAS: Enabling Media Autosense for port %d\n",
2155 hw->bus.func);
2156 }
2157 break;
2158 case E1000_FUNC_1:
2159 if (eeprom_data & IGB_MAS_ENABLE_1) {
2160 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2161 netdev_info(adapter->netdev,
2162 "MAS: Enabling Media Autosense for port %d\n",
2163 hw->bus.func);
2164 }
2165 break;
2166 case E1000_FUNC_2:
2167 if (eeprom_data & IGB_MAS_ENABLE_2) {
2168 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2169 netdev_info(adapter->netdev,
2170 "MAS: Enabling Media Autosense for port %d\n",
2171 hw->bus.func);
2172 }
2173 break;
2174 case E1000_FUNC_3:
2175 if (eeprom_data & IGB_MAS_ENABLE_3) {
2176 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2177 netdev_info(adapter->netdev,
2178 "MAS: Enabling Media Autosense for port %d\n",
2179 hw->bus.func);
2180 }
2181 break;
2182 default:
2183 /* Shouldn't get here */
2184 netdev_err(adapter->netdev,
2185 "MAS: Invalid port configuration, returning\n");
2186 break;
2187 }
2188}
2189
b980ac18
JK		 2190/**
2191 * igb_init_i2c - Init I2C interface
441fc6fd 2192 * @adapter: pointer to adapter structure
b980ac18 2193 **/
441fc6fd
CW		 2194static s32 igb_init_i2c(struct igb_adapter *adapter)
2195{
23d87824 2196 s32 status = 0;
441fc6fd
CW		 2197
2198 /* I2C interface supported on i350 devices */
2199 if (adapter->hw.mac.type != e1000_i350)
23d87824 2200 return 0;
441fc6fd
CW		 2201
2202 /* Initialize the i2c bus which is controlled by the registers.
2203 * This bus will use the i2c_algo_bit structue that implements
2204 * the protocol through toggling of the 4 bits in the register.
2205 */
2206 adapter->i2c_adap.owner = THIS_MODULE;
2207 adapter->i2c_algo = igb_i2c_algo;
2208 adapter->i2c_algo.data = adapter;
2209 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2210 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2211 strlcpy(adapter->i2c_adap.name, "igb BB",
2212 sizeof(adapter->i2c_adap.name));
2213 status = i2c_bit_add_bus(&adapter->i2c_adap);
2214 return status;
2215}
2216
9d5c8243 2217/**
b980ac18
JK		 2218 * igb_probe - Device Initialization Routine
2219 * @pdev: PCI device information struct
2220 * @ent: entry in igb_pci_tbl
9d5c8243 2221 *
b980ac18 2222 * Returns 0 on success, negative on failure
9d5c8243 2223 *
b980ac18
JK		 2224 * igb_probe initializes an adapter identified by a pci_dev structure.
2225 * The OS initialization, configuring of the adapter private structure,
2226 * and a hardware reset occur.
9d5c8243 2227 **/
1dd06ae8 2228static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2229{
2230 struct net_device *netdev;
2231 struct igb_adapter *adapter;
2232 struct e1000_hw *hw;
4337e993 2233 u16 eeprom_data = 0;
9835fd73 2234 s32 ret_val;
4337e993 2235 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2236 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2237 int err, pci_using_dac;
9835fd73 2238 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2239
bded64a7
AG		 2240 /* Catch broken hardware that put the wrong VF device ID in
2241 * the PCIe SR-IOV capability.
2242 */
2243 if (pdev->is_virtfn) {
2244 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2245 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2246 return -EINVAL;
2247 }
2248
aed5dec3 2249 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2250 if (err)
2251 return err;
2252
2253 pci_using_dac = 0;
dc4ff9bb 2254 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2255 if (!err) {
dc4ff9bb 2256 pci_using_dac = 1;
9d5c8243 2257 } else {
dc4ff9bb 2258 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2259 if (err) {
dc4ff9bb
RK		 2260 dev_err(&pdev->dev,
2261 "No usable DMA configuration, aborting\n");
2262 goto err_dma;
9d5c8243
AK		 2263 }
2264 }
2265
aed5dec3 2266 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2267 IORESOURCE_MEM),
2268 igb_driver_name);
9d5c8243
AK		 2269 if (err)
2270 goto err_pci_reg;
2271
19d5afd4 2272 pci_enable_pcie_error_reporting(pdev);
40a914fa 2273
9d5c8243 2274 pci_set_master(pdev);
c682fc23 2275 pci_save_state(pdev);
9d5c8243
AK		 2276
2277 err = -ENOMEM;
1bfaf07b 2278 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2279 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2280 if (!netdev)
2281 goto err_alloc_etherdev;
2282
2283 SET_NETDEV_DEV(netdev, &pdev->dev);
2284
2285 pci_set_drvdata(pdev, netdev);
2286 adapter = netdev_priv(netdev);
2287 adapter->netdev = netdev;
2288 adapter->pdev = pdev;
2289 hw = &adapter->hw;
2290 hw->back = adapter;
b3f4d599 2291 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2292
9d5c8243 2293 err = -EIO;
73bf8048
JW		 2294 adapter->io_addr = pci_iomap(pdev, 0, 0);
2295 if (!adapter->io_addr)
9d5c8243 2296 goto err_ioremap;
73bf8048
JW		 2297 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2298 hw->hw_addr = adapter->io_addr;
9d5c8243 2299
2e5c6922 2300 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2301 igb_set_ethtool_ops(netdev);
9d5c8243 2302 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2303
2304 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2305
89dbefb2
AS		 2306 netdev->mem_start = pci_resource_start(pdev, 0);
2307 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2308
9d5c8243
AK		 2309 /* PCI config space info */
2310 hw->vendor_id = pdev->vendor;
2311 hw->device_id = pdev->device;
2312 hw->revision_id = pdev->revision;
2313 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2314 hw->subsystem_device_id = pdev->subsystem_device;
2315
9d5c8243
AK		 2316 /* Copy the default MAC, PHY and NVM function pointers */
2317 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2318 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2319 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2320 /* Initialize skew-specific constants */
2321 err = ei->get_invariants(hw);
2322 if (err)
450c87c8 2323 goto err_sw_init;
9d5c8243 2324
450c87c8 2325 /* setup the private structure */
9d5c8243
AK		 2326 err = igb_sw_init(adapter);
2327 if (err)
2328 goto err_sw_init;
2329
2330 igb_get_bus_info_pcie(hw);
2331
2332 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2333
2334 /* Copper options */
2335 if (hw->phy.media_type == e1000_media_type_copper) {
2336 hw->phy.mdix = AUTO_ALL_MODES;
2337 hw->phy.disable_polarity_correction = false;
2338 hw->phy.ms_type = e1000_ms_hw_default;
2339 }
2340
2341 if (igb_check_reset_block(hw))
2342 dev_info(&pdev->dev,
2343 "PHY reset is blocked due to SOL/IDER session.\n");
2344
b980ac18 2345 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2346 * set by igb_sw_init so we should use an or instead of an
2347 * assignment.
2348 */
2349 netdev->features |= NETIF_F_SG |
2350 NETIF_F_IP_CSUM |
2351 NETIF_F_IPV6_CSUM |
2352 NETIF_F_TSO |
2353 NETIF_F_TSO6 |
2354 NETIF_F_RXHASH |
2355 NETIF_F_RXCSUM |
f646968f
PM		 2356 NETIF_F_HW_VLAN_CTAG_RX |
2357 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2358
2359 /* copy netdev features into list of user selectable features */
2360 netdev->hw_features |= netdev->features;
89eaefb6 2361 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2362
2363 /* set this bit last since it cannot be part of hw_features */
f646968f 2364 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2365
2366 netdev->vlan_features |= NETIF_F_TSO |
2367 NETIF_F_TSO6 |
2368 NETIF_F_IP_CSUM |
2369 NETIF_F_IPV6_CSUM |
2370 NETIF_F_SG;
48f29ffc 2371
6b8f0922
BG		 2372 netdev->priv_flags |= IFF_SUPP_NOFCS;
2373
7b872a55 2374 if (pci_using_dac) {
9d5c8243 2375 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2376 netdev->vlan_features |= NETIF_F_HIGHDMA;
2377 }
9d5c8243 2378
ac52caa3 2379 if (hw->mac.type >= e1000_82576) {
53692b1d
TH		 2380 netdev->hw_features |= NETIF_F_SCTP_CRC;
2381 netdev->features |= NETIF_F_SCTP_CRC;
ac52caa3 2382 }
b9473560 2383
01789349
JP		 2384 netdev->priv_flags |= IFF_UNICAST_FLT;
2385
330a6d6a 2386 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2387
2388 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2389 * known good starting state
2390 */
9d5c8243
AK		 2391 hw->mac.ops.reset_hw(hw);
2392
ef3a0092
CW		 2393 /* make sure the NVM is good , i211/i210 parts can have special NVM
2394 * that doesn't contain a checksum
f96a8a0b 2395 */
ef3a0092
CW		 2396 switch (hw->mac.type) {
2397 case e1000_i210:
2398 case e1000_i211:
2399 if (igb_get_flash_presence_i210(hw)) {
2400 if (hw->nvm.ops.validate(hw) < 0) {
2401 dev_err(&pdev->dev,
2402 "The NVM Checksum Is Not Valid\n");
2403 err = -EIO;
2404 goto err_eeprom;
2405 }
2406 }
2407 break;
2408 default:
f96a8a0b
CW		 2409 if (hw->nvm.ops.validate(hw) < 0) {
2410 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2411 err = -EIO;
2412 goto err_eeprom;
2413 }
ef3a0092 2414 break;
9d5c8243
AK		 2415 }
2416
2417 /* copy the MAC address out of the NVM */
2418 if (hw->mac.ops.read_mac_addr(hw))
2419 dev_err(&pdev->dev, "NVM Read Error\n");
2420
2421 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2422
aaeb6cdf 2423 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2424 dev_err(&pdev->dev, "Invalid MAC Address\n");
2425 err = -EIO;
2426 goto err_eeprom;
2427 }
2428
d67974f0
CW		 2429 /* get firmware version for ethtool -i */
2430 igb_set_fw_version(adapter);
2431
27dff8b2
TF		 2432 /* configure RXPBSIZE and TXPBSIZE */
2433 if (hw->mac.type == e1000_i210) {
2434 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2435 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2436 }
2437
c061b18d 2438 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2439 (unsigned long) adapter);
c061b18d 2440 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2441 (unsigned long) adapter);
9d5c8243
AK		 2442
2443 INIT_WORK(&adapter->reset_task, igb_reset_task);
2444 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2445
450c87c8 2446 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2447 adapter->fc_autoneg = true;
2448 hw->mac.autoneg = true;
2449 hw->phy.autoneg_advertised = 0x2f;
2450
0cce119a
AD		 2451 hw->fc.requested_mode = e1000_fc_default;
2452 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2453
9d5c8243
AK		 2454 igb_validate_mdi_setting(hw);
2455
63d4a8f9 2456 /* By default, support wake on port A */
a2cf8b6c 2457 if (hw->bus.func == 0)
63d4a8f9
MV		 2458 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2459
2460 /* Check the NVM for wake support on non-port A ports */
2461 if (hw->mac.type >= e1000_82580)
55cac248 2462 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2463 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2464 &eeprom_data);
a2cf8b6c
AD		 2465 else if (hw->bus.func == 1)
2466 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2467
63d4a8f9
MV		 2468 if (eeprom_data & IGB_EEPROM_APME)
2469 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2470
2471 /* now that we have the eeprom settings, apply the special cases where
2472 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2473 * lan on a particular port
2474 */
9d5c8243
AK		 2475 switch (pdev->device) {
2476 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2477 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2478 break;
2479 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2480 case E1000_DEV_ID_82576_FIBER:
2481 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2482 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2483 * regardless of eeprom setting
2484 */
9d5c8243 2485 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2486 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2487 break;
c8ea5ea9 2488 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2489 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2490 /* if quad port adapter, disable WoL on all but port A */
2491 if (global_quad_port_a != 0)
63d4a8f9 2492 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2493 else
2494 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2495 /* Reset for multiple quad port adapters */
2496 if (++global_quad_port_a == 4)
2497 global_quad_port_a = 0;
2498 break;
63d4a8f9
MV		 2499 default:
2500 /* If the device can't wake, don't set software support */
2501 if (!device_can_wakeup(&adapter->pdev->dev))
2502 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2503 }
2504
2505 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2506 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2507 adapter->wol |= E1000_WUFC_MAG;
2508
2509 /* Some vendors want WoL disabled by default, but still supported */
2510 if ((hw->mac.type == e1000_i350) &&
2511 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2512 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2513 adapter->wol = 0;
2514 }
2515
2516 device_set_wakeup_enable(&adapter->pdev->dev,
2517 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2518
2519 /* reset the hardware with the new settings */
2520 igb_reset(adapter);
2521
441fc6fd
CW		 2522 /* Init the I2C interface */
2523 err = igb_init_i2c(adapter);
2524 if (err) {
2525 dev_err(&pdev->dev, "failed to init i2c interface\n");
2526 goto err_eeprom;
2527 }
2528
9d5c8243 2529 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2530 * driver.
2531 */
9d5c8243
AK		 2532 igb_get_hw_control(adapter);
2533
9d5c8243
AK		 2534 strcpy(netdev->name, "eth%d");
2535 err = register_netdev(netdev);
2536 if (err)
2537 goto err_register;
2538
b168dfc5
JB		 2539 /* carrier off reporting is important to ethtool even BEFORE open */
2540 netif_carrier_off(netdev);
2541
421e02f0 2542#ifdef CONFIG_IGB_DCA
bbd98fe4 2543 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2544 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2545 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2546 igb_setup_dca(adapter);
2547 }
fe4506b6 2548
38c845c7 2549#endif
e428893b
CW		 2550#ifdef CONFIG_IGB_HWMON
2551 /* Initialize the thermal sensor on i350 devices. */
2552 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2553 u16 ets_word;
3c89f6d0 2554
b980ac18 2555 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2556 * external thermal sensor.
2557 */
2558 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2559 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2560 adapter->ets = true;
2561 else
2562 adapter->ets = false;
2563 if (igb_sysfs_init(adapter))
2564 dev_err(&pdev->dev,
2565 "failed to allocate sysfs resources\n");
2566 } else {
2567 adapter->ets = false;
2568 }
2569#endif
56cec249
CW		 2570 /* Check if Media Autosense is enabled */
2571 adapter->ei = *ei;
2572 if (hw->dev_spec._82575.mas_capable)
2573 igb_init_mas(adapter);
2574
673b8b70 2575 /* do hw tstamp init after resetting */
7ebae817 2576 igb_ptp_init(adapter);
673b8b70 2577
9d5c8243 2578 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2579 /* print bus type/speed/width info, not applicable to i354 */
2580 if (hw->mac.type != e1000_i354) {
2581 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2582 netdev->name,
2583 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2584 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2585 "unknown"),
2586 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2587 "Width x4" :
2588 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2589 "Width x2" :
2590 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2591 "Width x1" : "unknown"), netdev->dev_addr);
2592 }
9d5c8243 2593
53ea6c7e
TF		 2594 if ((hw->mac.type >= e1000_i210 ||
2595 igb_get_flash_presence_i210(hw))) {
2596 ret_val = igb_read_part_string(hw, part_str,
2597 E1000_PBANUM_LENGTH);
2598 } else {
2599 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2600 }
2601
9835fd73
CW		 2602 if (ret_val)
2603 strcpy(part_str, "Unknown");
2604 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2605 dev_info(&pdev->dev,
2606 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2607 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2608 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2609 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2610 if (hw->phy.media_type == e1000_media_type_copper) {
2611 switch (hw->mac.type) {
2612 case e1000_i350:
2613 case e1000_i210:
2614 case e1000_i211:
2615 /* Enable EEE for internal copper PHY devices */
c4c112f1 2616 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2617 if ((!err) &&
2618 (!hw->dev_spec._82575.eee_disable)) {
2619 adapter->eee_advert =
2620 MDIO_EEE_100TX | MDIO_EEE_1000T;
2621 adapter->flags |= IGB_FLAG_EEE;
2622 }
2623 break;
2624 case e1000_i354:
ceb5f13b 2625 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2626 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2627 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2628 if ((!err) &&
2629 (!hw->dev_spec._82575.eee_disable)) {
2630 adapter->eee_advert =
2631 MDIO_EEE_100TX | MDIO_EEE_1000T;
2632 adapter->flags |= IGB_FLAG_EEE;
2633 }
2634 }
2635 break;
2636 default:
2637 break;
ceb5f13b 2638 }
09b068d4 2639 }
749ab2cd 2640 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2641 return 0;
2642
2643err_register:
2644 igb_release_hw_control(adapter);
441fc6fd 2645 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2646err_eeprom:
2647 if (!igb_check_reset_block(hw))
f5f4cf08 2648 igb_reset_phy(hw);
9d5c8243
AK		 2649
2650 if (hw->flash_address)
2651 iounmap(hw->flash_address);
9d5c8243 2652err_sw_init:
42ad1a03 2653 kfree(adapter->shadow_vfta);
047e0030 2654 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2655#ifdef CONFIG_PCI_IOV
2656 igb_disable_sriov(pdev);
2657#endif
73bf8048 2658 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2659err_ioremap:
2660 free_netdev(netdev);
2661err_alloc_etherdev:
559e9c49 2662 pci_release_selected_regions(pdev,
b980ac18 2663 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2664err_pci_reg:
2665err_dma:
2666 pci_disable_device(pdev);
2667 return err;
2668}
2669
fa44f2f1 2670#ifdef CONFIG_PCI_IOV
781798a1 2671static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2672{
2673 struct net_device *netdev = pci_get_drvdata(pdev);
2674 struct igb_adapter *adapter = netdev_priv(netdev);
2675 struct e1000_hw *hw = &adapter->hw;
2676
2677 /* reclaim resources allocated to VFs */
2678 if (adapter->vf_data) {
2679 /* disable iov and allow time for transactions to clear */
b09186d2 2680 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2681 dev_warn(&pdev->dev,
2682 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2683 return -EPERM;
2684 } else {
2685 pci_disable_sriov(pdev);
2686 msleep(500);
2687 }
2688
2689 kfree(adapter->vf_data);
2690 adapter->vf_data = NULL;
2691 adapter->vfs_allocated_count = 0;
2692 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2693 wrfl();
2694 msleep(100);
2695 dev_info(&pdev->dev, "IOV Disabled\n");
2696
2697 /* Re-enable DMA Coalescing flag since IOV is turned off */
2698 adapter->flags |= IGB_FLAG_DMAC;
2699 }
2700
2701 return 0;
2702}
2703
2704static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2705{
2706 struct net_device *netdev = pci_get_drvdata(pdev);
2707 struct igb_adapter *adapter = netdev_priv(netdev);
2708 int old_vfs = pci_num_vf(pdev);
2709 int err = 0;
2710 int i;
2711
cd14ef54 2712 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2713 err = -EPERM;
2714 goto out;
2715 }
fa44f2f1
GR		 2716 if (!num_vfs)
2717 goto out;
fa44f2f1 2718
781798a1
SA		 2719 if (old_vfs) {
2720 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2721 old_vfs, max_vfs);
2722 adapter->vfs_allocated_count = old_vfs;
2723 } else
2724 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2725
2726 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2727 sizeof(struct vf_data_storage), GFP_KERNEL);
2728
2729 /* if allocation failed then we do not support SR-IOV */
2730 if (!adapter->vf_data) {
2731 adapter->vfs_allocated_count = 0;
2732 dev_err(&pdev->dev,
2733 "Unable to allocate memory for VF Data Storage\n");
2734 err = -ENOMEM;
2735 goto out;
2736 }
2737
781798a1
SA		 2738 /* only call pci_enable_sriov() if no VFs are allocated already */
2739 if (!old_vfs) {
2740 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2741 if (err)
2742 goto err_out;
2743 }
fa44f2f1
GR		 2744 dev_info(&pdev->dev, "%d VFs allocated\n",
2745 adapter->vfs_allocated_count);
2746 for (i = 0; i < adapter->vfs_allocated_count; i++)
2747 igb_vf_configure(adapter, i);
2748
2749 /* DMA Coalescing is not supported in IOV mode. */
2750 adapter->flags &= ~IGB_FLAG_DMAC;
2751 goto out;
2752
2753err_out:
2754 kfree(adapter->vf_data);
2755 adapter->vf_data = NULL;
2756 adapter->vfs_allocated_count = 0;
2757out:
2758 return err;
2759}
2760
2761#endif
b980ac18 2762/**
441fc6fd
CW		 2763 * igb_remove_i2c - Cleanup I2C interface
2764 * @adapter: pointer to adapter structure
b980ac18 2765 **/
441fc6fd
CW		 2766static void igb_remove_i2c(struct igb_adapter *adapter)
2767{
441fc6fd
CW		 2768 /* free the adapter bus structure */
2769 i2c_del_adapter(&adapter->i2c_adap);
2770}
2771
9d5c8243 2772/**
b980ac18
JK		 2773 * igb_remove - Device Removal Routine
2774 * @pdev: PCI device information struct
9d5c8243 2775 *
b980ac18
JK		 2776 * igb_remove is called by the PCI subsystem to alert the driver
2777 * that it should release a PCI device. The could be caused by a
2778 * Hot-Plug event, or because the driver is going to be removed from
2779 * memory.
9d5c8243 2780 **/
9f9a12f8 2781static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2782{
2783 struct net_device *netdev = pci_get_drvdata(pdev);
2784 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2785 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2786
749ab2cd 2787 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2788#ifdef CONFIG_IGB_HWMON
2789 igb_sysfs_exit(adapter);
2790#endif
441fc6fd 2791 igb_remove_i2c(adapter);
a79f4f88 2792 igb_ptp_stop(adapter);
b980ac18 2793 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2794 * disable watchdog from being rescheduled.
2795 */
9d5c8243
AK		 2796 set_bit(__IGB_DOWN, &adapter->state);
2797 del_timer_sync(&adapter->watchdog_timer);
2798 del_timer_sync(&adapter->phy_info_timer);
2799
760141a5
TH		 2800 cancel_work_sync(&adapter->reset_task);
2801 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2802
421e02f0 2803#ifdef CONFIG_IGB_DCA
7dfc16fa 2804 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2805 dev_info(&pdev->dev, "DCA disabled\n");
2806 dca_remove_requester(&pdev->dev);
7dfc16fa 2807 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2808 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2809 }
2810#endif
2811
9d5c8243 2812 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2813 * would have already happened in close and is redundant.
2814 */
9d5c8243
AK		 2815 igb_release_hw_control(adapter);
2816
37680117 2817#ifdef CONFIG_PCI_IOV
fa44f2f1 2818 igb_disable_sriov(pdev);
37680117 2819#endif
559e9c49 2820
c23d92b8
AW		 2821 unregister_netdev(netdev);
2822
2823 igb_clear_interrupt_scheme(adapter);
2824
73bf8048 2825 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2826 if (hw->flash_address)
2827 iounmap(hw->flash_address);
559e9c49 2828 pci_release_selected_regions(pdev,
b980ac18 2829 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2830
1128c756 2831 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2832 free_netdev(netdev);
2833
19d5afd4 2834 pci_disable_pcie_error_reporting(pdev);
40a914fa 2835
9d5c8243
AK		 2836 pci_disable_device(pdev);
2837}
2838
a6b623e0 2839/**
b980ac18
JK		 2840 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2841 * @adapter: board private structure to initialize
a6b623e0 2842 *
b980ac18
JK		 2843 * This function initializes the vf specific data storage and then attempts to
2844 * allocate the VFs. The reason for ordering it this way is because it is much
2845 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2846 * the memory for the VFs.
a6b623e0 2847 **/
9f9a12f8 2848static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2849{
2850#ifdef CONFIG_PCI_IOV
2851 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2852 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2853
f96a8a0b
CW		 2854 /* Virtualization features not supported on i210 family. */
2855 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2856 return;
2857
be06998f
JB		 2858 /* Of the below we really only want the effect of getting
2859 * IGB_FLAG_HAS_MSIX set (if available), without which
2860 * igb_enable_sriov() has no effect.
2861 */
2862 igb_set_interrupt_capability(adapter, true);
2863 igb_reset_interrupt_capability(adapter);
2864
fa44f2f1 2865 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2866 igb_enable_sriov(pdev, max_vfs);
0224d663 2867
a6b623e0
AD		 2868#endif /* CONFIG_PCI_IOV */
2869}
2870
fa44f2f1 2871static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2872{
2873 struct e1000_hw *hw = &adapter->hw;
374a542d 2874 u32 max_rss_queues;
9d5c8243 2875
374a542d 2876 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2877 switch (hw->mac.type) {
374a542d
MV		 2878 case e1000_i211:
2879 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2880 break;
2881 case e1000_82575:
f96a8a0b 2882 case e1000_i210:
374a542d
MV		 2883 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2884 break;
2885 case e1000_i350:
2886 /* I350 cannot do RSS and SR-IOV at the same time */
2887 if (!!adapter->vfs_allocated_count) {
2888 max_rss_queues = 1;
2889 break;
2890 }
2891 /* fall through */
2892 case e1000_82576:
2893 if (!!adapter->vfs_allocated_count) {
2894 max_rss_queues = 2;
2895 break;
2896 }
2897 /* fall through */
2898 case e1000_82580:
ceb5f13b 2899 case e1000_i354:
374a542d
MV		 2900 default:
2901 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2902 break;
374a542d
MV		 2903 }
2904
2905 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2906
72ddef05
SS		 2907 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2908}
2909
2910void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2911 const u32 max_rss_queues)
2912{
2913 struct e1000_hw *hw = &adapter->hw;
2914
374a542d
MV		 2915 /* Determine if we need to pair queues. */
2916 switch (hw->mac.type) {
2917 case e1000_82575:
f96a8a0b 2918 case e1000_i211:
374a542d 2919 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2920 break;
374a542d 2921 case e1000_82576:
374a542d
MV		 2922 case e1000_82580:
2923 case e1000_i350:
ceb5f13b 2924 case e1000_i354:
374a542d 2925 case e1000_i210:
f96a8a0b 2926 default:
b980ac18 2927 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2928 * order to conserve interrupts due to limited supply.
2929 */
2930 if (adapter->rss_queues > (max_rss_queues / 2))
2931 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
37a5d163
SS		 2932 else
2933 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2934 break;
2935 }
fa44f2f1
GR		 2936}
2937
2938/**
b980ac18
JK		 2939 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2940 * @adapter: board private structure to initialize
fa44f2f1 2941 *
b980ac18
JK		 2942 * igb_sw_init initializes the Adapter private data structure.
2943 * Fields are initialized based on PCI device information and
2944 * OS network device settings (MTU size).
fa44f2f1
GR		 2945 **/
2946static int igb_sw_init(struct igb_adapter *adapter)
2947{
2948 struct e1000_hw *hw = &adapter->hw;
2949 struct net_device *netdev = adapter->netdev;
2950 struct pci_dev *pdev = adapter->pdev;
2951
2952 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2953
2954 /* set default ring sizes */
2955 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2956 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2957
2958 /* set default ITR values */
2959 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2960 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2961
2962 /* set default work limits */
2963 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2964
2965 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2966 VLAN_HLEN;
2967 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2968
2969 spin_lock_init(&adapter->stats64_lock);
2970#ifdef CONFIG_PCI_IOV
2971 switch (hw->mac.type) {
2972 case e1000_82576:
2973 case e1000_i350:
2974 if (max_vfs > 7) {
2975 dev_warn(&pdev->dev,
2976 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2977 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2978 } else
2979 adapter->vfs_allocated_count = max_vfs;
2980 if (adapter->vfs_allocated_count)
2981 dev_warn(&pdev->dev,
2982 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2983 break;
2984 default:
2985 break;
2986 }
2987#endif /* CONFIG_PCI_IOV */
2988
cbfe360a
SA		 2989 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
2990 adapter->flags |= IGB_FLAG_HAS_MSIX;
2991
ceee3450
TF		 2992 igb_probe_vfs(adapter);
2993
fa44f2f1 2994 igb_init_queue_configuration(adapter);
a99955fc 2995
1128c756 2996 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2997 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2998 GFP_ATOMIC);
1128c756 2999
a6b623e0 3000 /* This call may decrease the number of queues */
53c7d064 3001 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3002 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3003 return -ENOMEM;
3004 }
3005
3006 /* Explicitly disable IRQ since the NIC can be in any state. */
3007 igb_irq_disable(adapter);
3008
f96a8a0b 3009 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3010 adapter->flags &= ~IGB_FLAG_DMAC;
3011
9d5c8243
AK		 3012 set_bit(__IGB_DOWN, &adapter->state);
3013 return 0;
3014}
3015
3016/**
b980ac18
JK		 3017 * igb_open - Called when a network interface is made active
3018 * @netdev: network interface device structure
9d5c8243 3019 *
b980ac18 3020 * Returns 0 on success, negative value on failure
9d5c8243 3021 *
b980ac18
JK		 3022 * The open entry point is called when a network interface is made
3023 * active by the system (IFF_UP). At this point all resources needed
3024 * for transmit and receive operations are allocated, the interrupt
3025 * handler is registered with the OS, the watchdog timer is started,
3026 * and the stack is notified that the interface is ready.
9d5c8243 3027 **/
749ab2cd 3028static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3029{
3030 struct igb_adapter *adapter = netdev_priv(netdev);
3031 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3032 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3033 int err;
3034 int i;
3035
3036 /* disallow open during test */
749ab2cd
YZ		 3037 if (test_bit(__IGB_TESTING, &adapter->state)) {
3038 WARN_ON(resuming);
9d5c8243 3039 return -EBUSY;
749ab2cd
YZ		 3040 }
3041
3042 if (!resuming)
3043 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3044
b168dfc5
JB		 3045 netif_carrier_off(netdev);
3046
9d5c8243
AK		 3047 /* allocate transmit descriptors */
3048 err = igb_setup_all_tx_resources(adapter);
3049 if (err)
3050 goto err_setup_tx;
3051
3052 /* allocate receive descriptors */
3053 err = igb_setup_all_rx_resources(adapter);
3054 if (err)
3055 goto err_setup_rx;
3056
88a268c1 3057 igb_power_up_link(adapter);
9d5c8243 3058
9d5c8243
AK		 3059 /* before we allocate an interrupt, we must be ready to handle it.
3060 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3061 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3062 * clean_rx handler before we do so.
3063 */
9d5c8243
AK		 3064 igb_configure(adapter);
3065
3066 err = igb_request_irq(adapter);
3067 if (err)
3068 goto err_req_irq;
3069
0c2cc02e
AD		 3070 /* Notify the stack of the actual queue counts. */
3071 err = netif_set_real_num_tx_queues(adapter->netdev,
3072 adapter->num_tx_queues);
3073 if (err)
3074 goto err_set_queues;
3075
3076 err = netif_set_real_num_rx_queues(adapter->netdev,
3077 adapter->num_rx_queues);
3078 if (err)
3079 goto err_set_queues;
3080
9d5c8243
AK		 3081 /* From here on the code is the same as igb_up() */
3082 clear_bit(__IGB_DOWN, &adapter->state);
3083
0d1ae7f4
AD		 3084 for (i = 0; i < adapter->num_q_vectors; i++)
3085 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3086
3087 /* Clear any pending interrupts. */
3088 rd32(E1000_ICR);
844290e5
PW		 3089
3090 igb_irq_enable(adapter);
3091
d4960307
AD		 3092 /* notify VFs that reset has been completed */
3093 if (adapter->vfs_allocated_count) {
3094 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3095
d4960307
AD		 3096 reg_data |= E1000_CTRL_EXT_PFRSTD;
3097 wr32(E1000_CTRL_EXT, reg_data);
3098 }
3099
d55b53ff
JK		 3100 netif_tx_start_all_queues(netdev);
3101
749ab2cd
YZ		 3102 if (!resuming)
3103 pm_runtime_put(&pdev->dev);
3104
25568a53
AD		 3105 /* start the watchdog. */
3106 hw->mac.get_link_status = 1;
3107 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3108
3109 return 0;
3110
0c2cc02e
AD		 3111err_set_queues:
3112 igb_free_irq(adapter);
9d5c8243
AK		 3113err_req_irq:
3114 igb_release_hw_control(adapter);
88a268c1 3115 igb_power_down_link(adapter);
9d5c8243
AK		 3116 igb_free_all_rx_resources(adapter);
3117err_setup_rx:
3118 igb_free_all_tx_resources(adapter);
3119err_setup_tx:
3120 igb_reset(adapter);
749ab2cd
YZ		 3121 if (!resuming)
3122 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3123
3124 return err;
3125}
3126
749ab2cd
YZ		 3127static int igb_open(struct net_device *netdev)
3128{
3129 return __igb_open(netdev, false);
3130}
3131
9d5c8243 3132/**
b980ac18
JK		 3133 * igb_close - Disables a network interface
3134 * @netdev: network interface device structure
9d5c8243 3135 *
b980ac18 3136 * Returns 0, this is not allowed to fail
9d5c8243 3137 *
b980ac18
JK		 3138 * The close entry point is called when an interface is de-activated
3139 * by the OS. The hardware is still under the driver's control, but
3140 * needs to be disabled. A global MAC reset is issued to stop the
3141 * hardware, and all transmit and receive resources are freed.
9d5c8243 3142 **/
749ab2cd 3143static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3144{
3145 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3146 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3147
3148 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3149
749ab2cd
YZ		 3150 if (!suspending)
3151 pm_runtime_get_sync(&pdev->dev);
3152
3153 igb_down(adapter);
9d5c8243
AK		 3154 igb_free_irq(adapter);
3155
3156 igb_free_all_tx_resources(adapter);
3157 igb_free_all_rx_resources(adapter);
3158
749ab2cd
YZ		 3159 if (!suspending)
3160 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3161 return 0;
3162}
3163
749ab2cd
YZ		 3164static int igb_close(struct net_device *netdev)
3165{
3166 return __igb_close(netdev, false);
3167}
3168
9d5c8243 3169/**
b980ac18
JK		 3170 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3171 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3172 *
b980ac18 3173 * Return 0 on success, negative on failure
9d5c8243 3174 **/
80785298 3175int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3176{
59d71989 3177 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3178 int size;
3179
06034649 3180 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3181
3182 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3183 if (!tx_ring->tx_buffer_info)
9d5c8243 3184 goto err;
9d5c8243
AK		 3185
3186 /* round up to nearest 4K */
85e8d004 3187 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3188 tx_ring->size = ALIGN(tx_ring->size, 4096);
3189
5536d210
AD		 3190 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3191 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3192 if (!tx_ring->desc)
3193 goto err;
3194
9d5c8243
AK		 3195 tx_ring->next_to_use = 0;
3196 tx_ring->next_to_clean = 0;
81c2fc22 3197
9d5c8243
AK		 3198 return 0;
3199
3200err:
06034649 3201 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3202 tx_ring->tx_buffer_info = NULL;
3203 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3204 return -ENOMEM;
3205}
3206
3207/**
b980ac18
JK		 3208 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3209 * (Descriptors) for all queues
3210 * @adapter: board private structure
9d5c8243 3211 *
b980ac18 3212 * Return 0 on success, negative on failure
9d5c8243
AK		 3213 **/
3214static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3215{
439705e1 3216 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3217 int i, err = 0;
3218
3219 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3220 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3221 if (err) {
439705e1 3222 dev_err(&pdev->dev,
9d5c8243
AK		 3223 "Allocation for Tx Queue %u failed\n", i);
3224 for (i--; i >= 0; i--)
3025a446 3225 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3226 break;
3227 }
3228 }
3229
3230 return err;
3231}
3232
3233/**
b980ac18
JK		 3234 * igb_setup_tctl - configure the transmit control registers
3235 * @adapter: Board private structure
9d5c8243 3236 **/
d7ee5b3a 3237void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3238{
9d5c8243
AK		 3239 struct e1000_hw *hw = &adapter->hw;
3240 u32 tctl;
9d5c8243 3241
85b430b4
AD		 3242 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3243 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3244
3245 /* Program the Transmit Control Register */
9d5c8243
AK		 3246 tctl = rd32(E1000_TCTL);
3247 tctl &= ~E1000_TCTL_CT;
3248 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3249 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3250
3251 igb_config_collision_dist(hw);
3252
9d5c8243
AK		 3253 /* Enable transmits */
3254 tctl |= E1000_TCTL_EN;
3255
3256 wr32(E1000_TCTL, tctl);
3257}
3258
85b430b4 3259/**
b980ac18
JK		 3260 * igb_configure_tx_ring - Configure transmit ring after Reset
3261 * @adapter: board private structure
3262 * @ring: tx ring to configure
85b430b4 3263 *
b980ac18 3264 * Configure a transmit ring after a reset.
85b430b4 3265 **/
d7ee5b3a 3266void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3267 struct igb_ring *ring)
85b430b4
AD		 3268{
3269 struct e1000_hw *hw = &adapter->hw;
a74420e0 3270 u32 txdctl = 0;
85b430b4
AD		 3271 u64 tdba = ring->dma;
3272 int reg_idx = ring->reg_idx;
3273
3274 /* disable the queue */
a74420e0 3275 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3276 wrfl();
3277 mdelay(10);
3278
3279 wr32(E1000_TDLEN(reg_idx),
b980ac18 3280 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3281 wr32(E1000_TDBAL(reg_idx),
b980ac18 3282 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3283 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3284
fce99e34 3285 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3286 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3287 writel(0, ring->tail);
85b430b4
AD		 3288
3289 txdctl |= IGB_TX_PTHRESH;
3290 txdctl |= IGB_TX_HTHRESH << 8;
3291 txdctl |= IGB_TX_WTHRESH << 16;
3292
3293 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3294 wr32(E1000_TXDCTL(reg_idx), txdctl);
3295}
3296
3297/**
b980ac18
JK		 3298 * igb_configure_tx - Configure transmit Unit after Reset
3299 * @adapter: board private structure
85b430b4 3300 *
b980ac18 3301 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3302 **/
3303static void igb_configure_tx(struct igb_adapter *adapter)
3304{
3305 int i;
3306
3307 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3308 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3309}
3310
9d5c8243 3311/**
b980ac18
JK		 3312 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3313 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3314 *
b980ac18 3315 * Returns 0 on success, negative on failure
9d5c8243 3316 **/
80785298 3317int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3318{
59d71989 3319 struct device *dev = rx_ring->dev;
f33005a6 3320 int size;
9d5c8243 3321
06034649 3322 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3323
3324 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3325 if (!rx_ring->rx_buffer_info)
9d5c8243 3326 goto err;
9d5c8243 3327
9d5c8243 3328 /* Round up to nearest 4K */
f33005a6 3329 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3330 rx_ring->size = ALIGN(rx_ring->size, 4096);
3331
5536d210
AD		 3332 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3333 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3334 if (!rx_ring->desc)
3335 goto err;
3336
cbc8e55f 3337 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3338 rx_ring->next_to_clean = 0;
3339 rx_ring->next_to_use = 0;
9d5c8243 3340
9d5c8243
AK		 3341 return 0;
3342
3343err:
06034649
AD		 3344 vfree(rx_ring->rx_buffer_info);
3345 rx_ring->rx_buffer_info = NULL;
f33005a6 3346 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3347 return -ENOMEM;
3348}
3349
3350/**
b980ac18
JK		 3351 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3352 * (Descriptors) for all queues
3353 * @adapter: board private structure
9d5c8243 3354 *
b980ac18 3355 * Return 0 on success, negative on failure
9d5c8243
AK		 3356 **/
3357static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3358{
439705e1 3359 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3360 int i, err = 0;
3361
3362 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3363 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3364 if (err) {
439705e1 3365 dev_err(&pdev->dev,
9d5c8243
AK		 3366 "Allocation for Rx Queue %u failed\n", i);
3367 for (i--; i >= 0; i--)
3025a446 3368 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3369 break;
3370 }
3371 }
3372
3373 return err;
3374}
3375
06cf2666 3376/**
b980ac18
JK		 3377 * igb_setup_mrqc - configure the multiple receive queue control registers
3378 * @adapter: Board private structure
06cf2666
AD		 3379 **/
3380static void igb_setup_mrqc(struct igb_adapter *adapter)
3381{
3382 struct e1000_hw *hw = &adapter->hw;
3383 u32 mrqc, rxcsum;
ed12cc9a 3384 u32 j, num_rx_queues;
eb31f849 3385 u32 rss_key[10];
06cf2666 3386
eb31f849 3387 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3388 for (j = 0; j < 10; j++)
eb31f849 3389 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3390
a99955fc 3391 num_rx_queues = adapter->rss_queues;
06cf2666 3392
797fd4be 3393 switch (hw->mac.type) {
797fd4be
AD		 3394 case e1000_82576:
3395 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3396 if (adapter->vfs_allocated_count)
06cf2666 3397 num_rx_queues = 2;
797fd4be
AD		 3398 break;
3399 default:
3400 break;
06cf2666
AD		 3401 }
3402
ed12cc9a
LMV		 3403 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3404 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3405 adapter->rss_indir_tbl[j] =
3406 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3407 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3408 }
ed12cc9a 3409 igb_write_rss_indir_tbl(adapter);
06cf2666 3410
b980ac18 3411 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3412 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3413 * offloads as they are enabled by default
3414 */
3415 rxcsum = rd32(E1000_RXCSUM);
3416 rxcsum |= E1000_RXCSUM_PCSD;
3417
3418 if (adapter->hw.mac.type >= e1000_82576)
3419 /* Enable Receive Checksum Offload for SCTP */
3420 rxcsum |= E1000_RXCSUM_CRCOFL;
3421
3422 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3423 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3424
039454a8
AA		 3425 /* Generate RSS hash based on packet types, TCP/UDP
3426 * port numbers and/or IPv4/v6 src and dst addresses
3427 */
f96a8a0b
CW		 3428 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3429 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3430 E1000_MRQC_RSS_FIELD_IPV6 |
3431 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3432 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3433
039454a8
AA		 3434 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3435 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3436 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3437 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3438
06cf2666
AD		 3439 /* If VMDq is enabled then we set the appropriate mode for that, else
3440 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3441 * if we are only using one queue
3442 */
06cf2666
AD		 3443 if (adapter->vfs_allocated_count) {
3444 if (hw->mac.type > e1000_82575) {
3445 /* Set the default pool for the PF's first queue */
3446 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3447
06cf2666
AD		 3448 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3449 E1000_VT_CTL_DISABLE_DEF_POOL);
3450 vtctl |= adapter->vfs_allocated_count <<
3451 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3452 wr32(E1000_VT_CTL, vtctl);
3453 }
a99955fc 3454 if (adapter->rss_queues > 1)
f96a8a0b 3455 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3456 else
f96a8a0b 3457 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3458 } else {
f96a8a0b
CW		 3459 if (hw->mac.type != e1000_i211)
3460 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3461 }
3462 igb_vmm_control(adapter);
3463
06cf2666
AD		 3464 wr32(E1000_MRQC, mrqc);
3465}
3466
9d5c8243 3467/**
b980ac18
JK		 3468 * igb_setup_rctl - configure the receive control registers
3469 * @adapter: Board private structure
9d5c8243 3470 **/
d7ee5b3a 3471void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3472{
3473 struct e1000_hw *hw = &adapter->hw;
3474 u32 rctl;
9d5c8243
AK		 3475
3476 rctl = rd32(E1000_RCTL);
3477
3478 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3479 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3480
69d728ba 3481 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3482 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3483
b980ac18 3484 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3485 * redirection as it did with e1000. Newer features require
3486 * that the HW strips the CRC.
73cd78f1 3487 */
87cb7e8c 3488 rctl |= E1000_RCTL_SECRC;
9d5c8243 3489
559e9c49 3490 /* disable store bad packets and clear size bits. */
ec54d7d6 3491 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3492
45693bcb 3493 /* enable LPE to allow for reception of jumbo frames */
6ec43fe6 3494 rctl |= E1000_RCTL_LPE;
9d5c8243 3495
952f72a8
AD		 3496 /* disable queue 0 to prevent tail write w/o re-config */
3497 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3498
e1739522
AD		 3499 /* Attention!!! For SR-IOV PF driver operations you must enable
3500 * queue drop for all VF and PF queues to prevent head of line blocking
3501 * if an un-trusted VF does not provide descriptors to hardware.
3502 */
3503 if (adapter->vfs_allocated_count) {
e1739522
AD		 3504 /* set all queue drop enable bits */
3505 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3506 }
3507
89eaefb6
BG		 3508 /* This is useful for sniffing bad packets. */
3509 if (adapter->netdev->features & NETIF_F_RXALL) {
3510 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3511 * in e1000e_set_rx_mode
3512 */
89eaefb6
BG		 3513 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3514 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3515 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3516
3517 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3518 E1000_RCTL_DPF | /* Allow filtered pause */
3519 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3520 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3521 * and that breaks VLANs.
3522 */
3523 }
3524
9d5c8243
AK		 3525 wr32(E1000_RCTL, rctl);
3526}
3527
7d5753f0 3528static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3529 int vfn)
7d5753f0
AD		 3530{
3531 struct e1000_hw *hw = &adapter->hw;
3532 u32 vmolr;
3533
d3836f8e
AD		 3534 if (size > MAX_JUMBO_FRAME_SIZE)
3535 size = MAX_JUMBO_FRAME_SIZE;
7d5753f0
AD		 3536
3537 vmolr = rd32(E1000_VMOLR(vfn));
3538 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3539 vmolr |= size | E1000_VMOLR_LPE;
3540 wr32(E1000_VMOLR(vfn), vmolr);
3541
3542 return 0;
3543}
3544
8151d294
WM		 3545static inline void igb_set_vmolr(struct igb_adapter *adapter,
3546 int vfn, bool aupe)
7d5753f0
AD		 3547{
3548 struct e1000_hw *hw = &adapter->hw;
3549 u32 vmolr;
3550
b980ac18 3551 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3552 * we should exit and do nothing
3553 */
3554 if (hw->mac.type < e1000_82576)
3555 return;
3556
3557 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3558 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3559 if (hw->mac.type == e1000_i350) {
3560 u32 dvmolr;
3561
3562 dvmolr = rd32(E1000_DVMOLR(vfn));
3563 dvmolr |= E1000_DVMOLR_STRVLAN;
3564 wr32(E1000_DVMOLR(vfn), dvmolr);
3565 }
8151d294 3566 if (aupe)
b980ac18 3567 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3568 else
3569 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3570
3571 /* clear all bits that might not be set */
3572 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3573
a99955fc 3574 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3575 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3576 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3577 * multicast packets
3578 */
3579 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3580 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3581
3582 wr32(E1000_VMOLR(vfn), vmolr);
3583}
3584
85b430b4 3585/**
b980ac18
JK		 3586 * igb_configure_rx_ring - Configure a receive ring after Reset
3587 * @adapter: board private structure
3588 * @ring: receive ring to be configured
85b430b4 3589 *
b980ac18 3590 * Configure the Rx unit of the MAC after a reset.
85b430b4 3591 **/
d7ee5b3a 3592void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3593 struct igb_ring *ring)
85b430b4
AD		 3594{
3595 struct e1000_hw *hw = &adapter->hw;
3596 u64 rdba = ring->dma;
3597 int reg_idx = ring->reg_idx;
a74420e0 3598 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3599
3600 /* disable the queue */
a74420e0 3601 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3602
3603 /* Set DMA base address registers */
3604 wr32(E1000_RDBAL(reg_idx),
3605 rdba & 0x00000000ffffffffULL);
3606 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3607 wr32(E1000_RDLEN(reg_idx),
b980ac18 3608 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3609
3610 /* initialize head and tail */
fce99e34 3611 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3612 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3613 writel(0, ring->tail);
85b430b4 3614
952f72a8 3615 /* set descriptor configuration */
44390ca6 3616 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3617 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3618 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3619 if (hw->mac.type >= e1000_82580)
757b77e2 3620 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3621 /* Only set Drop Enable if we are supporting multiple queues */
3622 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3623 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3624
3625 wr32(E1000_SRRCTL(reg_idx), srrctl);
3626
7d5753f0 3627 /* set filtering for VMDQ pools */
8151d294 3628 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3629
85b430b4
AD		 3630 rxdctl |= IGB_RX_PTHRESH;
3631 rxdctl |= IGB_RX_HTHRESH << 8;
3632 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3633
3634 /* enable receive descriptor fetching */
3635 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3636 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3637}
3638
9d5c8243 3639/**
b980ac18
JK		 3640 * igb_configure_rx - Configure receive Unit after Reset
3641 * @adapter: board private structure
9d5c8243 3642 *
b980ac18 3643 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3644 **/
3645static void igb_configure_rx(struct igb_adapter *adapter)
3646{
9107584e 3647 int i;
9d5c8243 3648
68d480c4
AD		 3649 /* set UTA to appropriate mode */
3650 igb_set_uta(adapter);
3651
26ad9178
AD		 3652 /* set the correct pool for the PF default MAC address in entry 0 */
3653 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3654 adapter->vfs_allocated_count);
26ad9178 3655
06cf2666 3656 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3657 * the Base and Length of the Rx Descriptor Ring
3658 */
f9d40f6a
AD		 3659 for (i = 0; i < adapter->num_rx_queues; i++)
3660 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3661}
3662
3663/**
b980ac18
JK		 3664 * igb_free_tx_resources - Free Tx Resources per Queue
3665 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3666 *
b980ac18 3667 * Free all transmit software resources
9d5c8243 3668 **/
68fd9910 3669void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3670{
3b644cf6 3671 igb_clean_tx_ring(tx_ring);
9d5c8243 3672
06034649
AD		 3673 vfree(tx_ring->tx_buffer_info);
3674 tx_ring->tx_buffer_info = NULL;
9d5c8243 3675
439705e1
AD		 3676 /* if not set, then don't free */
3677 if (!tx_ring->desc)
3678 return;
3679
59d71989
AD		 3680 dma_free_coherent(tx_ring->dev, tx_ring->size,
3681 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3682
3683 tx_ring->desc = NULL;
3684}
3685
3686/**
b980ac18
JK		 3687 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3688 * @adapter: board private structure
9d5c8243 3689 *
b980ac18 3690 * Free all transmit software resources
9d5c8243
AK		 3691 **/
3692static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3693{
3694 int i;
3695
3696 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3697 if (adapter->tx_ring[i])
3698 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3699}
3700
ebe42d16
AD		 3701void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3702 struct igb_tx_buffer *tx_buffer)
3703{
3704 if (tx_buffer->skb) {
3705 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3706 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3707 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3708 dma_unmap_addr(tx_buffer, dma),
3709 dma_unmap_len(tx_buffer, len),
ebe42d16 3710 DMA_TO_DEVICE);
c9f14bf3 3711 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3712 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3713 dma_unmap_addr(tx_buffer, dma),
3714 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3715 DMA_TO_DEVICE);
3716 }
3717 tx_buffer->next_to_watch = NULL;
3718 tx_buffer->skb = NULL;
c9f14bf3 3719 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3720 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3721}
3722
3723/**
b980ac18
JK		 3724 * igb_clean_tx_ring - Free Tx Buffers
3725 * @tx_ring: ring to be cleaned
9d5c8243 3726 **/
3b644cf6 3727static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3728{
06034649 3729 struct igb_tx_buffer *buffer_info;
9d5c8243 3730 unsigned long size;
6ad4edfc 3731 u16 i;
9d5c8243 3732
06034649 3733 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3734 return;
3735 /* Free all the Tx ring sk_buffs */
3736
3737 for (i = 0; i < tx_ring->count; i++) {
06034649 3738 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3739 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3740 }
3741
dad8a3b3
JF		 3742 netdev_tx_reset_queue(txring_txq(tx_ring));
3743
06034649
AD		 3744 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3745 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3746
3747 /* Zero out the descriptor ring */
9d5c8243
AK		 3748 memset(tx_ring->desc, 0, tx_ring->size);
3749
3750 tx_ring->next_to_use = 0;
3751 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3752}
3753
3754/**
b980ac18
JK		 3755 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3756 * @adapter: board private structure
9d5c8243
AK		 3757 **/
3758static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3759{
3760 int i;
3761
3762 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3763 if (adapter->tx_ring[i])
3764 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3765}
3766
3767/**
b980ac18
JK		 3768 * igb_free_rx_resources - Free Rx Resources
3769 * @rx_ring: ring to clean the resources from
9d5c8243 3770 *
b980ac18 3771 * Free all receive software resources
9d5c8243 3772 **/
68fd9910 3773void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3774{
3b644cf6 3775 igb_clean_rx_ring(rx_ring);
9d5c8243 3776
06034649
AD		 3777 vfree(rx_ring->rx_buffer_info);
3778 rx_ring->rx_buffer_info = NULL;
9d5c8243 3779
439705e1
AD		 3780 /* if not set, then don't free */
3781 if (!rx_ring->desc)
3782 return;
3783
59d71989
AD		 3784 dma_free_coherent(rx_ring->dev, rx_ring->size,
3785 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3786
3787 rx_ring->desc = NULL;
3788}
3789
3790/**
b980ac18
JK		 3791 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3792 * @adapter: board private structure
9d5c8243 3793 *
b980ac18 3794 * Free all receive software resources
9d5c8243
AK		 3795 **/
3796static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3797{
3798 int i;
3799
3800 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3801 if (adapter->rx_ring[i])
3802 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3803}
3804
3805/**
b980ac18
JK		 3806 * igb_clean_rx_ring - Free Rx Buffers per Queue
3807 * @rx_ring: ring to free buffers from
9d5c8243 3808 **/
3b644cf6 3809static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3810{
9d5c8243 3811 unsigned long size;
c023cd88 3812 u16 i;
9d5c8243 3813
1a1c225b
AD		 3814 if (rx_ring->skb)
3815 dev_kfree_skb(rx_ring->skb);
3816 rx_ring->skb = NULL;
3817
06034649 3818 if (!rx_ring->rx_buffer_info)
9d5c8243 3819 return;
439705e1 3820
9d5c8243
AK		 3821 /* Free all the Rx ring sk_buffs */
3822 for (i = 0; i < rx_ring->count; i++) {
06034649 3823 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3824
cbc8e55f
AD		 3825 if (!buffer_info->page)
3826 continue;
3827
3828 dma_unmap_page(rx_ring->dev,
3829 buffer_info->dma,
3830 PAGE_SIZE,
3831 DMA_FROM_DEVICE);
3832 __free_page(buffer_info->page);
3833
1a1c225b 3834 buffer_info->page = NULL;
9d5c8243
AK		 3835 }
3836
06034649
AD		 3837 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3838 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3839
3840 /* Zero out the descriptor ring */
3841 memset(rx_ring->desc, 0, rx_ring->size);
3842
cbc8e55f 3843 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3844 rx_ring->next_to_clean = 0;
3845 rx_ring->next_to_use = 0;
9d5c8243
AK		 3846}
3847
3848/**
b980ac18
JK		 3849 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3850 * @adapter: board private structure
9d5c8243
AK		 3851 **/
3852static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3853{
3854 int i;
3855
3856 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3857 if (adapter->rx_ring[i])
3858 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3859}
3860
3861/**
b980ac18
JK		 3862 * igb_set_mac - Change the Ethernet Address of the NIC
3863 * @netdev: network interface device structure
3864 * @p: pointer to an address structure
9d5c8243 3865 *
b980ac18 3866 * Returns 0 on success, negative on failure
9d5c8243
AK		 3867 **/
3868static int igb_set_mac(struct net_device *netdev, void *p)
3869{
3870 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3871 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3872 struct sockaddr *addr = p;
3873
3874 if (!is_valid_ether_addr(addr->sa_data))
3875 return -EADDRNOTAVAIL;
3876
3877 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3878 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3879
26ad9178
AD		 3880 /* set the correct pool for the new PF MAC address in entry 0 */
3881 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3882 adapter->vfs_allocated_count);
e1739522 3883
9d5c8243
AK		 3884 return 0;
3885}
3886
3887/**
b980ac18
JK		 3888 * igb_write_mc_addr_list - write multicast addresses to MTA
3889 * @netdev: network interface device structure
9d5c8243 3890 *
b980ac18
JK		 3891 * Writes multicast address list to the MTA hash table.
3892 * Returns: -ENOMEM on failure
3893 * 0 on no addresses written
3894 * X on writing X addresses to MTA
9d5c8243 3895 **/
68d480c4 3896static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3897{
3898 struct igb_adapter *adapter = netdev_priv(netdev);
3899 struct e1000_hw *hw = &adapter->hw;
22bedad3 3900 struct netdev_hw_addr *ha;
68d480c4 3901 u8 *mta_list;
9d5c8243
AK		 3902 int i;
3903
4cd24eaf 3904 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3905 /* nothing to program, so clear mc list */
3906 igb_update_mc_addr_list(hw, NULL, 0);
3907 igb_restore_vf_multicasts(adapter);
3908 return 0;
3909 }
9d5c8243 3910
4cd24eaf 3911 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3912 if (!mta_list)
3913 return -ENOMEM;
ff41f8dc 3914
68d480c4 3915 /* The shared function expects a packed array of only addresses. */
48e2f183 3916 i = 0;
22bedad3
JP		 3917 netdev_for_each_mc_addr(ha, netdev)
3918 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3919
68d480c4
AD		 3920 igb_update_mc_addr_list(hw, mta_list, i);
3921 kfree(mta_list);
3922
4cd24eaf 3923 return netdev_mc_count(netdev);
68d480c4
AD		 3924}
3925
3926/**
b980ac18
JK		 3927 * igb_write_uc_addr_list - write unicast addresses to RAR table
3928 * @netdev: network interface device structure
68d480c4 3929 *
b980ac18
JK		 3930 * Writes unicast address list to the RAR table.
3931 * Returns: -ENOMEM on failure/insufficient address space
3932 * 0 on no addresses written
3933 * X on writing X addresses to the RAR table
68d480c4
AD		 3934 **/
3935static int igb_write_uc_addr_list(struct net_device *netdev)
3936{
3937 struct igb_adapter *adapter = netdev_priv(netdev);
3938 struct e1000_hw *hw = &adapter->hw;
3939 unsigned int vfn = adapter->vfs_allocated_count;
3940 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3941 int count = 0;
3942
3943 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3944 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3945 return -ENOMEM;
9d5c8243 3946
32e7bfc4 3947 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3948 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3949
3950 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3951 if (!rar_entries)
3952 break;
26ad9178 3953 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3954 rar_entries--,
3955 vfn);
68d480c4 3956 count++;
ff41f8dc
AD		 3957 }
3958 }
3959 /* write the addresses in reverse order to avoid write combining */
3960 for (; rar_entries > 0 ; rar_entries--) {
3961 wr32(E1000_RAH(rar_entries), 0);
3962 wr32(E1000_RAL(rar_entries), 0);
3963 }
3964 wrfl();
3965
68d480c4
AD		 3966 return count;
3967}
3968
3969/**
b980ac18
JK		 3970 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3971 * @netdev: network interface device structure
68d480c4 3972 *
b980ac18
JK		 3973 * The set_rx_mode entry point is called whenever the unicast or multicast
3974 * address lists or the network interface flags are updated. This routine is
3975 * responsible for configuring the hardware for proper unicast, multicast,
3976 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3977 **/
3978static void igb_set_rx_mode(struct net_device *netdev)
3979{
3980 struct igb_adapter *adapter = netdev_priv(netdev);
3981 struct e1000_hw *hw = &adapter->hw;
3982 unsigned int vfn = adapter->vfs_allocated_count;
3983 u32 rctl, vmolr = 0;
3984 int count;
3985
3986 /* Check for Promiscuous and All Multicast modes */
3987 rctl = rd32(E1000_RCTL);
3988
3989 /* clear the effected bits */
3990 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3991
3992 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3993 /* retain VLAN HW filtering if in VT mode */
7e44892c 3994 if (adapter->vfs_allocated_count)
6f3dc319 3995 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3996 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3997 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3998 } else {
3999 if (netdev->flags & IFF_ALLMULTI) {
4000 rctl |= E1000_RCTL_MPE;
4001 vmolr |= E1000_VMOLR_MPME;
4002 } else {
b980ac18 4003 /* Write addresses to the MTA, if the attempt fails
25985edc 4004 * then we should just turn on promiscuous mode so
68d480c4
AD		 4005 * that we can at least receive multicast traffic
4006 */
4007 count = igb_write_mc_addr_list(netdev);
4008 if (count < 0) {
4009 rctl |= E1000_RCTL_MPE;
4010 vmolr |= E1000_VMOLR_MPME;
4011 } else if (count) {
4012 vmolr |= E1000_VMOLR_ROMPE;
4013 }
4014 }
b980ac18 4015 /* Write addresses to available RAR registers, if there is not
68d480c4 4016 * sufficient space to store all the addresses then enable
25985edc 4017 * unicast promiscuous mode
68d480c4
AD		 4018 */
4019 count = igb_write_uc_addr_list(netdev);
4020 if (count < 0) {
4021 rctl |= E1000_RCTL_UPE;
4022 vmolr |= E1000_VMOLR_ROPE;
4023 }
4024 rctl |= E1000_RCTL_VFE;
28fc06f5 4025 }
68d480c4 4026 wr32(E1000_RCTL, rctl);
28fc06f5 4027
b980ac18 4028 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4029 * the VMOLR to enable the appropriate modes. Without this workaround
4030 * we will have issues with VLAN tag stripping not being done for frames
4031 * that are only arriving because we are the default pool
4032 */
f96a8a0b 4033 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4034 return;
9d5c8243 4035
68d480c4 4036 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4037 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
45693bcb
AD		 4038
4039 /* enable Rx jumbo frames, no need for restriction */
4040 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4041 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4042
68d480c4 4043 wr32(E1000_VMOLR(vfn), vmolr);
45693bcb
AD		 4044 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4045
28fc06f5 4046 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4047}
4048
13800469
GR		 4049static void igb_check_wvbr(struct igb_adapter *adapter)
4050{
4051 struct e1000_hw *hw = &adapter->hw;
4052 u32 wvbr = 0;
4053
4054 switch (hw->mac.type) {
4055 case e1000_82576:
4056 case e1000_i350:
81ad807b
CW		 4057 wvbr = rd32(E1000_WVBR);
4058 if (!wvbr)
13800469
GR		 4059 return;
4060 break;
4061 default:
4062 break;
4063 }
4064
4065 adapter->wvbr |= wvbr;
4066}
4067
4068#define IGB_STAGGERED_QUEUE_OFFSET 8
4069
4070static void igb_spoof_check(struct igb_adapter *adapter)
4071{
4072 int j;
4073
4074 if (!adapter->wvbr)
4075 return;
4076
9005df38 4077 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4078 if (adapter->wvbr & (1 << j) ||
4079 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4080 dev_warn(&adapter->pdev->dev,
4081 "Spoof event(s) detected on VF %d\n", j);
4082 adapter->wvbr &=
4083 ~((1 << j) |
4084 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4085 }
4086 }
4087}
4088
9d5c8243 4089/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4090 * the phy
4091 */
9d5c8243
AK		 4092static void igb_update_phy_info(unsigned long data)
4093{
4094 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4095 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4096}
4097
4d6b725e 4098/**
b980ac18
JK		 4099 * igb_has_link - check shared code for link and determine up/down
4100 * @adapter: pointer to driver private info
4d6b725e 4101 **/
3145535a 4102bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4103{
4104 struct e1000_hw *hw = &adapter->hw;
4105 bool link_active = false;
4d6b725e
AD		 4106
4107 /* get_link_status is set on LSC (link status) interrupt or
4108 * rx sequence error interrupt. get_link_status will stay
4109 * false until the e1000_check_for_link establishes link
4110 * for copper adapters ONLY
4111 */
4112 switch (hw->phy.media_type) {
4113 case e1000_media_type_copper:
e5c3370f
AA		 4114 if (!hw->mac.get_link_status)
4115 return true;
4d6b725e 4116 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4117 hw->mac.ops.check_for_link(hw);
4118 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4119 break;
4120 default:
4121 case e1000_media_type_unknown:
4122 break;
4123 }
4124
aa9b8cc4
AA		 4125 if (((hw->mac.type == e1000_i210) ||
4126 (hw->mac.type == e1000_i211)) &&
4127 (hw->phy.id == I210_I_PHY_ID)) {
4128 if (!netif_carrier_ok(adapter->netdev)) {
4129 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4130 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4131 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4132 adapter->link_check_timeout = jiffies;
4133 }
4134 }
4135
4d6b725e
AD		 4136 return link_active;
4137}
4138
563988dc
SA		 4139static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4140{
4141 bool ret = false;
4142 u32 ctrl_ext, thstat;
4143
f96a8a0b 4144 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4145 if (hw->mac.type == e1000_i350) {
4146 thstat = rd32(E1000_THSTAT);
4147 ctrl_ext = rd32(E1000_CTRL_EXT);
4148
4149 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4150 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4151 ret = !!(thstat & event);
563988dc
SA		 4152 }
4153
4154 return ret;
4155}
4156
1516f0a6
CW		 4157/**
4158 * igb_check_lvmmc - check for malformed packets received
4159 * and indicated in LVMMC register
4160 * @adapter: pointer to adapter
4161 **/
4162static void igb_check_lvmmc(struct igb_adapter *adapter)
4163{
4164 struct e1000_hw *hw = &adapter->hw;
4165 u32 lvmmc;
4166
4167 lvmmc = rd32(E1000_LVMMC);
4168 if (lvmmc) {
4169 if (unlikely(net_ratelimit())) {
4170 netdev_warn(adapter->netdev,
4171 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4172 lvmmc);
4173 }
4174 }
4175}
4176
9d5c8243 4177/**
b980ac18
JK		 4178 * igb_watchdog - Timer Call-back
4179 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4180 **/
4181static void igb_watchdog(unsigned long data)
4182{
4183 struct igb_adapter *adapter = (struct igb_adapter *)data;
4184 /* Do the rest outside of interrupt context */
4185 schedule_work(&adapter->watchdog_task);
4186}
4187
4188static void igb_watchdog_task(struct work_struct *work)
4189{
4190 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4191 struct igb_adapter,
4192 watchdog_task);
9d5c8243 4193 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4194 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4195 struct net_device *netdev = adapter->netdev;
563988dc 4196 u32 link;
7a6ea550 4197 int i;
56cec249 4198 u32 connsw;
9d5c8243 4199
4d6b725e 4200 link = igb_has_link(adapter);
aa9b8cc4
AA		 4201
4202 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4203 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4204 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4205 else
4206 link = false;
4207 }
4208
56cec249
CW		 4209 /* Force link down if we have fiber to swap to */
4210 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4211 if (hw->phy.media_type == e1000_media_type_copper) {
4212 connsw = rd32(E1000_CONNSW);
4213 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4214 link = 0;
4215 }
4216 }
9d5c8243 4217 if (link) {
2bdfc4e2
CW		 4218 /* Perform a reset if the media type changed. */
4219 if (hw->dev_spec._82575.media_changed) {
4220 hw->dev_spec._82575.media_changed = false;
4221 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4222 igb_reset(adapter);
4223 }
749ab2cd
YZ		 4224 /* Cancel scheduled suspend requests. */
4225 pm_runtime_resume(netdev->dev.parent);
4226
9d5c8243
AK		 4227 if (!netif_carrier_ok(netdev)) {
4228 u32 ctrl;
9005df38 4229
330a6d6a 4230 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4231 &adapter->link_speed,
4232 &adapter->link_duplex);
9d5c8243
AK		 4233
4234 ctrl = rd32(E1000_CTRL);
527d47c1 4235 /* Links status message must follow this format */
c75c4edf
CW		 4236 netdev_info(netdev,
4237 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4238 netdev->name,
4239 adapter->link_speed,
4240 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4241 "Full" : "Half",
4242 (ctrl & E1000_CTRL_TFCE) &&
4243 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4244 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4245 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4246
f4c01e96
CW		 4247 /* disable EEE if enabled */
4248 if ((adapter->flags & IGB_FLAG_EEE) &&
4249 (adapter->link_duplex == HALF_DUPLEX)) {
4250 dev_info(&adapter->pdev->dev,
4251 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4252 adapter->hw.dev_spec._82575.eee_disable = true;
4253 adapter->flags &= ~IGB_FLAG_EEE;
4254 }
4255
c0ba4778
KS		 4256 /* check if SmartSpeed worked */
4257 igb_check_downshift(hw);
4258 if (phy->speed_downgraded)
4259 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4260
563988dc 4261 /* check for thermal sensor event */
876d2d6f 4262 if (igb_thermal_sensor_event(hw,
d34a15ab 4263 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4264 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4265
d07f3e37 4266 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4267 adapter->tx_timeout_factor = 1;
4268 switch (adapter->link_speed) {
4269 case SPEED_10:
9d5c8243
AK		 4270 adapter->tx_timeout_factor = 14;
4271 break;
4272 case SPEED_100:
9d5c8243
AK		 4273 /* maybe add some timeout factor ? */
4274 break;
4275 }
4276
4277 netif_carrier_on(netdev);
9d5c8243 4278
4ae196df 4279 igb_ping_all_vfs(adapter);
17dc566c 4280 igb_check_vf_rate_limit(adapter);
4ae196df 4281
4b1a9877 4282 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4283 if (!test_bit(__IGB_DOWN, &adapter->state))
4284 mod_timer(&adapter->phy_info_timer,
4285 round_jiffies(jiffies + 2 * HZ));
4286 }
4287 } else {
4288 if (netif_carrier_ok(netdev)) {
4289 adapter->link_speed = 0;
4290 adapter->link_duplex = 0;
563988dc
SA		 4291
4292 /* check for thermal sensor event */
876d2d6f
JK		 4293 if (igb_thermal_sensor_event(hw,
4294 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4295 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4296 }
563988dc 4297
527d47c1 4298 /* Links status message must follow this format */
c75c4edf 4299 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4300 netdev->name);
9d5c8243 4301 netif_carrier_off(netdev);
4b1a9877 4302
4ae196df
AD		 4303 igb_ping_all_vfs(adapter);
4304
4b1a9877 4305 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4306 if (!test_bit(__IGB_DOWN, &adapter->state))
4307 mod_timer(&adapter->phy_info_timer,
4308 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4309
56cec249
CW		 4310 /* link is down, time to check for alternate media */
4311 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4312 igb_check_swap_media(adapter);
4313 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4314 schedule_work(&adapter->reset_task);
4315 /* return immediately */
4316 return;
4317 }
4318 }
749ab2cd
YZ		 4319 pm_schedule_suspend(netdev->dev.parent,
4320 MSEC_PER_SEC * 5);
56cec249
CW		 4321
4322 /* also check for alternate media here */
4323 } else if (!netif_carrier_ok(netdev) &&
4324 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4325 igb_check_swap_media(adapter);
4326 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4327 schedule_work(&adapter->reset_task);
4328 /* return immediately */
4329 return;
4330 }
9d5c8243
AK		 4331 }
4332 }
4333
12dcd86b
ED		 4334 spin_lock(&adapter->stats64_lock);
4335 igb_update_stats(adapter, &adapter->stats64);
4336 spin_unlock(&adapter->stats64_lock);
9d5c8243 4337
dbabb065 4338 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4339 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4340 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4341 /* We've lost link, so the controller stops DMA,
4342 * but we've got queued Tx work that's never going
4343 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4344 * (Do the reset outside of interrupt context).
4345 */
dbabb065
AD		 4346 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4347 adapter->tx_timeout_count++;
4348 schedule_work(&adapter->reset_task);
4349 /* return immediately since reset is imminent */
4350 return;
4351 }
9d5c8243 4352 }
9d5c8243 4353
dbabb065 4354 /* Force detection of hung controller every watchdog period */
6d095fa8 4355 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4356 }
f7ba205e 4357
b980ac18 4358 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4359 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4360 u32 eics = 0;
9005df38 4361
0d1ae7f4
AD		 4362 for (i = 0; i < adapter->num_q_vectors; i++)
4363 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4364 wr32(E1000_EICS, eics);
4365 } else {
4366 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4367 }
9d5c8243 4368
13800469 4369 igb_spoof_check(adapter);
fc580751 4370 igb_ptp_rx_hang(adapter);
13800469 4371
1516f0a6
CW		 4372 /* Check LVMMC register on i350/i354 only */
4373 if ((adapter->hw.mac.type == e1000_i350) ||
4374 (adapter->hw.mac.type == e1000_i354))
4375 igb_check_lvmmc(adapter);
4376
9d5c8243 4377 /* Reset the timer */
aa9b8cc4
AA		 4378 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4379 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4380 mod_timer(&adapter->watchdog_timer,
4381 round_jiffies(jiffies + HZ));
4382 else
4383 mod_timer(&adapter->watchdog_timer,
4384 round_jiffies(jiffies + 2 * HZ));
4385 }
9d5c8243
AK		 4386}
4387
4388enum latency_range {
4389 lowest_latency = 0,
4390 low_latency = 1,
4391 bulk_latency = 2,
4392 latency_invalid = 255
4393};
4394
6eb5a7f1 4395/**
b980ac18
JK		 4396 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4397 * @q_vector: pointer to q_vector
6eb5a7f1 4398 *
b980ac18
JK		 4399 * Stores a new ITR value based on strictly on packet size. This
4400 * algorithm is less sophisticated than that used in igb_update_itr,
4401 * due to the difficulty of synchronizing statistics across multiple
4402 * receive rings. The divisors and thresholds used by this function
4403 * were determined based on theoretical maximum wire speed and testing
4404 * data, in order to minimize response time while increasing bulk
4405 * throughput.
406d4965 4406 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4407 * NOTE: This function is called only when operating in a multiqueue
4408 * receive environment.
6eb5a7f1 4409 **/
047e0030 4410static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4411{
047e0030 4412 int new_val = q_vector->itr_val;
6eb5a7f1 4413 int avg_wire_size = 0;
047e0030 4414 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4415 unsigned int packets;
9d5c8243 4416
6eb5a7f1
AD		 4417 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4418 * ints/sec - ITR timer value of 120 ticks.
4419 */
4420 if (adapter->link_speed != SPEED_1000) {
0ba82994 4421 new_val = IGB_4K_ITR;
6eb5a7f1 4422 goto set_itr_val;
9d5c8243 4423 }
047e0030 4424
0ba82994
AD		 4425 packets = q_vector->rx.total_packets;
4426 if (packets)
4427 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4428
0ba82994
AD		 4429 packets = q_vector->tx.total_packets;
4430 if (packets)
4431 avg_wire_size = max_t(u32, avg_wire_size,
4432 q_vector->tx.total_bytes / packets);
047e0030
AD		 4433
4434 /* if avg_wire_size isn't set no work was done */
4435 if (!avg_wire_size)
4436 goto clear_counts;
9d5c8243 4437
6eb5a7f1
AD		 4438 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4439 avg_wire_size += 24;
4440
4441 /* Don't starve jumbo frames */
4442 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4443
6eb5a7f1
AD		 4444 /* Give a little boost to mid-size frames */
4445 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4446 new_val = avg_wire_size / 3;
4447 else
4448 new_val = avg_wire_size / 2;
9d5c8243 4449
0ba82994
AD		 4450 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4451 if (new_val < IGB_20K_ITR &&
4452 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4453 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4454 new_val = IGB_20K_ITR;
abe1c363 4455
6eb5a7f1 4456set_itr_val:
047e0030
AD		 4457 if (new_val != q_vector->itr_val) {
4458 q_vector->itr_val = new_val;
4459 q_vector->set_itr = 1;
9d5c8243 4460 }
6eb5a7f1 4461clear_counts:
0ba82994
AD		 4462 q_vector->rx.total_bytes = 0;
4463 q_vector->rx.total_packets = 0;
4464 q_vector->tx.total_bytes = 0;
4465 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4466}
4467
4468/**
b980ac18
JK		 4469 * igb_update_itr - update the dynamic ITR value based on statistics
4470 * @q_vector: pointer to q_vector
4471 * @ring_container: ring info to update the itr for
4472 *
4473 * Stores a new ITR value based on packets and byte
4474 * counts during the last interrupt. The advantage of per interrupt
4475 * computation is faster updates and more accurate ITR for the current
4476 * traffic pattern. Constants in this function were computed
4477 * based on theoretical maximum wire speed and thresholds were set based
4478 * on testing data as well as attempting to minimize response time
4479 * while increasing bulk throughput.
406d4965 4480 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4481 * NOTE: These calculations are only valid when operating in a single-
4482 * queue environment.
9d5c8243 4483 **/
0ba82994
AD		 4484static void igb_update_itr(struct igb_q_vector *q_vector,
4485 struct igb_ring_container *ring_container)
9d5c8243 4486{
0ba82994
AD		 4487 unsigned int packets = ring_container->total_packets;
4488 unsigned int bytes = ring_container->total_bytes;
4489 u8 itrval = ring_container->itr;
9d5c8243 4490
0ba82994 4491 /* no packets, exit with status unchanged */
9d5c8243 4492 if (packets == 0)
0ba82994 4493 return;
9d5c8243 4494
0ba82994 4495 switch (itrval) {
9d5c8243
AK		 4496 case lowest_latency:
4497 /* handle TSO and jumbo frames */
4498 if (bytes/packets > 8000)
0ba82994 4499 itrval = bulk_latency;
9d5c8243 4500 else if ((packets < 5) && (bytes > 512))
0ba82994 4501 itrval = low_latency;
9d5c8243
AK		 4502 break;
4503 case low_latency: /* 50 usec aka 20000 ints/s */
4504 if (bytes > 10000) {
4505 /* this if handles the TSO accounting */
d34a15ab 4506 if (bytes/packets > 8000)
0ba82994 4507 itrval = bulk_latency;
d34a15ab 4508 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4509 itrval = bulk_latency;
d34a15ab 4510 else if ((packets > 35))
0ba82994 4511 itrval = lowest_latency;
9d5c8243 4512 } else if (bytes/packets > 2000) {
0ba82994 4513 itrval = bulk_latency;
9d5c8243 4514 } else if (packets <= 2 && bytes < 512) {
0ba82994 4515 itrval = lowest_latency;
9d5c8243
AK		 4516 }
4517 break;
4518 case bulk_latency: /* 250 usec aka 4000 ints/s */
4519 if (bytes > 25000) {
4520 if (packets > 35)
0ba82994 4521 itrval = low_latency;
1e5c3d21 4522 } else if (bytes < 1500) {
0ba82994 4523 itrval = low_latency;
9d5c8243
AK		 4524 }
4525 break;
4526 }
4527
0ba82994
AD		 4528 /* clear work counters since we have the values we need */
4529 ring_container->total_bytes = 0;
4530 ring_container->total_packets = 0;
4531
4532 /* write updated itr to ring container */
4533 ring_container->itr = itrval;
9d5c8243
AK		 4534}
4535
0ba82994 4536static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4537{
0ba82994 4538 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4539 u32 new_itr = q_vector->itr_val;
0ba82994 4540 u8 current_itr = 0;
9d5c8243
AK		 4541
4542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4543 if (adapter->link_speed != SPEED_1000) {
4544 current_itr = 0;
0ba82994 4545 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4546 goto set_itr_now;
4547 }
4548
0ba82994
AD		 4549 igb_update_itr(q_vector, &q_vector->tx);
4550 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4551
0ba82994 4552 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4553
6eb5a7f1 4554 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4555 if (current_itr == lowest_latency &&
4556 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4557 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4558 current_itr = low_latency;
4559
9d5c8243
AK		 4560 switch (current_itr) {
4561 /* counts and packets in update_itr are dependent on these numbers */
4562 case lowest_latency:
0ba82994 4563 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4564 break;
4565 case low_latency:
0ba82994 4566 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4567 break;
4568 case bulk_latency:
0ba82994 4569 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4570 break;
4571 default:
4572 break;
4573 }
4574
4575set_itr_now:
047e0030 4576 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4577 /* this attempts to bias the interrupt rate towards Bulk
4578 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4579 * increasing
4580 */
047e0030 4581 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4582 max((new_itr * q_vector->itr_val) /
4583 (new_itr + (q_vector->itr_val >> 2)),
4584 new_itr) : new_itr;
9d5c8243
AK		 4585 /* Don't write the value here; it resets the adapter's
4586 * internal timer, and causes us to delay far longer than
4587 * we should between interrupts. Instead, we write the ITR
4588 * value at the beginning of the next interrupt so the timing
4589 * ends up being correct.
4590 */
047e0030
AD		 4591 q_vector->itr_val = new_itr;
4592 q_vector->set_itr = 1;
9d5c8243 4593 }
9d5c8243
AK		 4594}
4595
c50b52a0
SH		 4596static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4597 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4598{
4599 struct e1000_adv_tx_context_desc *context_desc;
4600 u16 i = tx_ring->next_to_use;
4601
4602 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4603
4604 i++;
4605 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4606
4607 /* set bits to identify this as an advanced context descriptor */
4608 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4609
4610 /* For 82575, context index must be unique per ring. */
866cff06 4611 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4612 mss_l4len_idx |= tx_ring->reg_idx << 4;
4613
4614 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4615 context_desc->seqnum_seed = 0;
4616 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4617 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4618}
4619
7af40ad9
AD		 4620static int igb_tso(struct igb_ring *tx_ring,
4621 struct igb_tx_buffer *first,
4622 u8 *hdr_len)
9d5c8243 4623{
7af40ad9 4624 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4625 u32 vlan_macip_lens, type_tucmd;
4626 u32 mss_l4len_idx, l4len;
06c14e5a 4627 int err;
7d13a7d0 4628
ed6aa105
AD		 4629 if (skb->ip_summed != CHECKSUM_PARTIAL)
4630 return 0;
4631
7d13a7d0
AD		 4632 if (!skb_is_gso(skb))
4633 return 0;
9d5c8243 4634
06c14e5a
FR		 4635 err = skb_cow_head(skb, 0);
4636 if (err < 0)
4637 return err;
9d5c8243 4638
7d13a7d0
AD		 4639 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4640 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4641
7c4d16ff 4642 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4643 struct iphdr *iph = ip_hdr(skb);
4644 iph->tot_len = 0;
4645 iph->check = 0;
4646 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4647 iph->daddr, 0,
4648 IPPROTO_TCP,
4649 0);
7d13a7d0 4650 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4651 first->tx_flags |= IGB_TX_FLAGS_TSO |
4652 IGB_TX_FLAGS_CSUM |
4653 IGB_TX_FLAGS_IPV4;
8e1e8a47 4654 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4655 ipv6_hdr(skb)->payload_len = 0;
4656 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4657 &ipv6_hdr(skb)->daddr,
4658 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4659 first->tx_flags |= IGB_TX_FLAGS_TSO |
4660 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4661 }
4662
7af40ad9 4663 /* compute header lengths */
7d13a7d0
AD		 4664 l4len = tcp_hdrlen(skb);
4665 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4666
7af40ad9
AD		 4667 /* update gso size and bytecount with header size */
4668 first->gso_segs = skb_shinfo(skb)->gso_segs;
4669 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4670
9d5c8243 4671 /* MSS L4LEN IDX */
7d13a7d0
AD		 4672 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4673 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4674
7d13a7d0
AD		 4675 /* VLAN MACLEN IPLEN */
4676 vlan_macip_lens = skb_network_header_len(skb);
4677 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4678 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4679
7d13a7d0 4680 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4681
7d13a7d0 4682 return 1;
9d5c8243
AK		 4683}
4684
7af40ad9 4685static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4686{
7af40ad9 4687 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4688 u32 vlan_macip_lens = 0;
4689 u32 mss_l4len_idx = 0;
4690 u32 type_tucmd = 0;
9d5c8243 4691
7d13a7d0 4692 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4693 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4694 return;
7d13a7d0
AD		 4695 } else {
4696 u8 l4_hdr = 0;
9005df38 4697
7af40ad9 4698 switch (first->protocol) {
7c4d16ff 4699 case htons(ETH_P_IP):
7d13a7d0
AD		 4700 vlan_macip_lens |= skb_network_header_len(skb);
4701 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4702 l4_hdr = ip_hdr(skb)->protocol;
4703 break;
7c4d16ff 4704 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4705 vlan_macip_lens |= skb_network_header_len(skb);
4706 l4_hdr = ipv6_hdr(skb)->nexthdr;
4707 break;
4708 default:
4709 if (unlikely(net_ratelimit())) {
4710 dev_warn(tx_ring->dev,
b980ac18
JK		 4711 "partial checksum but proto=%x!\n",
4712 first->protocol);
fa4a7ef3 4713 }
7d13a7d0
AD		 4714 break;
4715 }
fa4a7ef3 4716
7d13a7d0
AD		 4717 switch (l4_hdr) {
4718 case IPPROTO_TCP:
4719 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4720 mss_l4len_idx = tcp_hdrlen(skb) <<
4721 E1000_ADVTXD_L4LEN_SHIFT;
4722 break;
4723 case IPPROTO_SCTP:
4724 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4725 mss_l4len_idx = sizeof(struct sctphdr) <<
4726 E1000_ADVTXD_L4LEN_SHIFT;
4727 break;
4728 case IPPROTO_UDP:
4729 mss_l4len_idx = sizeof(struct udphdr) <<
4730 E1000_ADVTXD_L4LEN_SHIFT;
4731 break;
4732 default:
4733 if (unlikely(net_ratelimit())) {
4734 dev_warn(tx_ring->dev,
b980ac18
JK		 4735 "partial checksum but l4 proto=%x!\n",
4736 l4_hdr);
44b0cda3 4737 }
7d13a7d0 4738 break;
9d5c8243 4739 }
7af40ad9
AD		 4740
4741 /* update TX checksum flag */
4742 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4743 }
9d5c8243 4744
7d13a7d0 4745 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4746 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4747
7d13a7d0 4748 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4749}
4750
1d9daf45
AD		 4751#define IGB_SET_FLAG(_input, _flag, _result) \
4752 ((_flag <= _result) ? \
4753 ((u32)(_input & _flag) * (_result / _flag)) : \
4754 ((u32)(_input & _flag) / (_flag / _result)))
4755
4756static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4757{
4758 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4759 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4760 E1000_ADVTXD_DCMD_DEXT |
4761 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4762
4763 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4764 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4765 (E1000_ADVTXD_DCMD_VLE));
4766
4767 /* set segmentation bits for TSO */
4768 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4769 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4770
4771 /* set timestamp bit if present */
1d9daf45
AD		 4772 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4773 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4774
1d9daf45
AD		 4775 /* insert frame checksum */
4776 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4777
4778 return cmd_type;
4779}
4780
7af40ad9
AD		 4781static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4782 union e1000_adv_tx_desc *tx_desc,
4783 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4784{
4785 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4786
1d9daf45
AD		 4787 /* 82575 requires a unique index per ring */
4788 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4789 olinfo_status |= tx_ring->reg_idx << 4;
4790
4791 /* insert L4 checksum */
1d9daf45
AD		 4792 olinfo_status |= IGB_SET_FLAG(tx_flags,
4793 IGB_TX_FLAGS_CSUM,
4794 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4795
1d9daf45
AD		 4796 /* insert IPv4 checksum */
4797 olinfo_status |= IGB_SET_FLAG(tx_flags,
4798 IGB_TX_FLAGS_IPV4,
4799 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4800
7af40ad9 4801 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4802}
4803
6f19e12f
DM		 4804static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4805{
4806 struct net_device *netdev = tx_ring->netdev;
4807
4808 netif_stop_subqueue(netdev, tx_ring->queue_index);
4809
4810 /* Herbert's original patch had:
4811 * smp_mb__after_netif_stop_queue();
4812 * but since that doesn't exist yet, just open code it.
4813 */
4814 smp_mb();
4815
4816 /* We need to check again in a case another CPU has just
4817 * made room available.
4818 */
4819 if (igb_desc_unused(tx_ring) < size)
4820 return -EBUSY;
4821
4822 /* A reprieve! */
4823 netif_wake_subqueue(netdev, tx_ring->queue_index);
4824
4825 u64_stats_update_begin(&tx_ring->tx_syncp2);
4826 tx_ring->tx_stats.restart_queue2++;
4827 u64_stats_update_end(&tx_ring->tx_syncp2);
4828
4829 return 0;
4830}
4831
4832static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4833{
4834 if (igb_desc_unused(tx_ring) >= size)
4835 return 0;
4836 return __igb_maybe_stop_tx(tx_ring, size);
4837}
4838
7af40ad9
AD		 4839static void igb_tx_map(struct igb_ring *tx_ring,
4840 struct igb_tx_buffer *first,
ebe42d16 4841 const u8 hdr_len)
9d5c8243 4842{
7af40ad9 4843 struct sk_buff *skb = first->skb;
c9f14bf3 4844 struct igb_tx_buffer *tx_buffer;
ebe42d16 4845 union e1000_adv_tx_desc *tx_desc;
80d0759e 4846 struct skb_frag_struct *frag;
ebe42d16 4847 dma_addr_t dma;
80d0759e 4848 unsigned int data_len, size;
7af40ad9 4849 u32 tx_flags = first->tx_flags;
1d9daf45 4850 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4851 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4852
4853 tx_desc = IGB_TX_DESC(tx_ring, i);
4854
80d0759e
AD		 4855 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4856
4857 size = skb_headlen(skb);
4858 data_len = skb->data_len;
ebe42d16
AD		 4859
4860 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4861
80d0759e
AD		 4862 tx_buffer = first;
4863
4864 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4865 if (dma_mapping_error(tx_ring->dev, dma))
4866 goto dma_error;
4867
4868 /* record length, and DMA address */
4869 dma_unmap_len_set(tx_buffer, len, size);
4870 dma_unmap_addr_set(tx_buffer, dma, dma);
4871
4872 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4873
ebe42d16
AD		 4874 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4875 tx_desc->read.cmd_type_len =
1d9daf45 4876 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4877
4878 i++;
4879 tx_desc++;
4880 if (i == tx_ring->count) {
4881 tx_desc = IGB_TX_DESC(tx_ring, 0);
4882 i = 0;
4883 }
80d0759e 4884 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4885
4886 dma += IGB_MAX_DATA_PER_TXD;
4887 size -= IGB_MAX_DATA_PER_TXD;
4888
ebe42d16
AD		 4889 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4890 }
4891
4892 if (likely(!data_len))
4893 break;
2bbfebe2 4894
1d9daf45 4895 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4896
65689fef 4897 i++;
ebe42d16
AD		 4898 tx_desc++;
4899 if (i == tx_ring->count) {
4900 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4901 i = 0;
ebe42d16 4902 }
80d0759e 4903 tx_desc->read.olinfo_status = 0;
65689fef 4904
9e903e08 4905 size = skb_frag_size(frag);
ebe42d16
AD		 4906 data_len -= size;
4907
4908 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4909 size, DMA_TO_DEVICE);
6366ad33 4910
c9f14bf3 4911 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4912 }
4913
ebe42d16 4914 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4915 cmd_type |= size | IGB_TXD_DCMD;
4916 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4917
80d0759e
AD		 4918 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4919
8542db05
AD		 4920 /* set the timestamp */
4921 first->time_stamp = jiffies;
4922
b980ac18 4923 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4924 * are new descriptors to fetch. (Only applicable for weak-ordered
4925 * memory model archs, such as IA-64).
4926 *
4927 * We also need this memory barrier to make certain all of the
4928 * status bits have been updated before next_to_watch is written.
4929 */
4930 wmb();
4931
8542db05 4932 /* set next_to_watch value indicating a packet is present */
ebe42d16 4933 first->next_to_watch = tx_desc;
9d5c8243 4934
ebe42d16
AD		 4935 i++;
4936 if (i == tx_ring->count)
4937 i = 0;
6366ad33 4938
ebe42d16 4939 tx_ring->next_to_use = i;
6366ad33 4940
6f19e12f
DM		 4941 /* Make sure there is space in the ring for the next send. */
4942 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4943
4944 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 4945 writel(i, tx_ring->tail);
4946
4947 /* we need this if more than one processor can write to our tail
4948 * at a time, it synchronizes IO on IA64/Altix systems
4949 */
4950 mmiowb();
4951 }
ebe42d16
AD		 4952 return;
4953
4954dma_error:
4955 dev_err(tx_ring->dev, "TX DMA map failed\n");
4956
4957 /* clear dma mappings for failed tx_buffer_info map */
4958 for (;;) {
c9f14bf3
AD		 4959 tx_buffer = &tx_ring->tx_buffer_info[i];
4960 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4961 if (tx_buffer == first)
ebe42d16 4962 break;
a77ff709
NN		 4963 if (i == 0)
4964 i = tx_ring->count;
6366ad33 4965 i--;
6366ad33
AD		 4966 }
4967
9d5c8243 4968 tx_ring->next_to_use = i;
9d5c8243
AK		 4969}
4970
cd392f5c
AD		 4971netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4972 struct igb_ring *tx_ring)
9d5c8243 4973{
8542db05 4974 struct igb_tx_buffer *first;
ebe42d16 4975 int tso;
91d4ee33 4976 u32 tx_flags = 0;
2ee52ad4 4977 unsigned short f;
21ba6fe1 4978 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4979 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4980 u8 hdr_len = 0;
9d5c8243 4981
21ba6fe1
AD		 4982 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4983 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4984 * + 2 desc gap to keep tail from touching head,
9d5c8243 4985 * + 1 desc for context descriptor,
21ba6fe1
AD		 4986 * otherwise try next time
4987 */
2ee52ad4
AD		 4988 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4989 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 4990
4991 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4992 /* this is a hard error */
9d5c8243
AK		 4993 return NETDEV_TX_BUSY;
4994 }
33af6bcc 4995
7af40ad9
AD		 4996 /* record the location of the first descriptor for this packet */
4997 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4998 first->skb = skb;
4999 first->bytecount = skb->len;
5000 first->gso_segs = 1;
5001
b646c22e
AD		 5002 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5003 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5004
ed4420a3
JK		 5005 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5006 &adapter->state)) {
b646c22e
AD		 5007 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5008 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5009
5010 adapter->ptp_tx_skb = skb_get(skb);
5011 adapter->ptp_tx_start = jiffies;
5012 if (adapter->hw.mac.type == e1000_82576)
5013 schedule_work(&adapter->ptp_tx_work);
5014 }
33af6bcc 5015 }
9d5c8243 5016
afc835d1
JK		 5017 skb_tx_timestamp(skb);
5018
df8a39de 5019 if (skb_vlan_tag_present(skb)) {
9d5c8243 5020 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5021 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5022 }
5023
7af40ad9
AD		 5024 /* record initial flags and protocol */
5025 first->tx_flags = tx_flags;
5026 first->protocol = protocol;
cdfd01fc 5027
7af40ad9
AD		 5028 tso = igb_tso(tx_ring, first, &hdr_len);
5029 if (tso < 0)
7d13a7d0 5030 goto out_drop;
7af40ad9
AD		 5031 else if (!tso)
5032 igb_tx_csum(tx_ring, first);
9d5c8243 5033
7af40ad9 5034 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5035
9d5c8243 5036 return NETDEV_TX_OK;
7d13a7d0
AD		 5037
5038out_drop:
7af40ad9
AD		 5039 igb_unmap_and_free_tx_resource(tx_ring, first);
5040
7d13a7d0 5041 return NETDEV_TX_OK;
9d5c8243
AK		 5042}
5043
0b725a2c
DM		 5044static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5045 struct sk_buff *skb)
1cc3bd87 5046{
0b725a2c
DM		 5047 unsigned int r_idx = skb->queue_mapping;
5048
1cc3bd87
AD		 5049 if (r_idx >= adapter->num_tx_queues)
5050 r_idx = r_idx % adapter->num_tx_queues;
5051
5052 return adapter->tx_ring[r_idx];
5053}
5054
cd392f5c
AD		 5055static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5056 struct net_device *netdev)
9d5c8243
AK		 5057{
5058 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5059
5060 if (test_bit(__IGB_DOWN, &adapter->state)) {
5061 dev_kfree_skb_any(skb);
5062 return NETDEV_TX_OK;
5063 }
5064
5065 if (skb->len <= 0) {
5066 dev_kfree_skb_any(skb);
5067 return NETDEV_TX_OK;
5068 }
5069
b980ac18 5070 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5071 * in order to meet this minimum size requirement.
5072 */
a94d9e22
AD		 5073 if (skb_put_padto(skb, 17))
5074 return NETDEV_TX_OK;
9d5c8243 5075
1cc3bd87 5076 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5077}
5078
5079/**
b980ac18
JK		 5080 * igb_tx_timeout - Respond to a Tx Hang
5081 * @netdev: network interface device structure
9d5c8243
AK		 5082 **/
5083static void igb_tx_timeout(struct net_device *netdev)
5084{
5085 struct igb_adapter *adapter = netdev_priv(netdev);
5086 struct e1000_hw *hw = &adapter->hw;
5087
5088 /* Do the reset outside of interrupt context */
5089 adapter->tx_timeout_count++;
f7ba205e 5090
06218a8d 5091 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5092 hw->dev_spec._82575.global_device_reset = true;
5093
9d5c8243 5094 schedule_work(&adapter->reset_task);
265de409
AD		 5095 wr32(E1000_EICS,
5096 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5097}
5098
5099static void igb_reset_task(struct work_struct *work)
5100{
5101 struct igb_adapter *adapter;
5102 adapter = container_of(work, struct igb_adapter, reset_task);
5103
c97ec42a
TI		 5104 igb_dump(adapter);
5105 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5106 igb_reinit_locked(adapter);
5107}
5108
5109/**
b980ac18
JK		 5110 * igb_get_stats64 - Get System Network Statistics
5111 * @netdev: network interface device structure
5112 * @stats: rtnl_link_stats64 pointer
9d5c8243 5113 **/
12dcd86b 5114static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5115 struct rtnl_link_stats64 *stats)
9d5c8243 5116{
12dcd86b
ED		 5117 struct igb_adapter *adapter = netdev_priv(netdev);
5118
5119 spin_lock(&adapter->stats64_lock);
5120 igb_update_stats(adapter, &adapter->stats64);
5121 memcpy(stats, &adapter->stats64, sizeof(*stats));
5122 spin_unlock(&adapter->stats64_lock);
5123
5124 return stats;
9d5c8243
AK		 5125}
5126
5127/**
b980ac18
JK		 5128 * igb_change_mtu - Change the Maximum Transfer Unit
5129 * @netdev: network interface device structure
5130 * @new_mtu: new value for maximum frame size
9d5c8243 5131 *
b980ac18 5132 * Returns 0 on success, negative on failure
9d5c8243
AK		 5133 **/
5134static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5135{
5136 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5137 struct pci_dev *pdev = adapter->pdev;
153285f9 5138 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5139
c809d227 5140 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5141 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5142 return -EINVAL;
5143 }
5144
153285f9 5145#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5146 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5147 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5148 return -EINVAL;
5149 }
5150
2ccd994c
AD		 5151 /* adjust max frame to be at least the size of a standard frame */
5152 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5153 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5154
9d5c8243 5155 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5156 usleep_range(1000, 2000);
73cd78f1 5157
9d5c8243
AK		 5158 /* igb_down has a dependency on max_frame_size */
5159 adapter->max_frame_size = max_frame;
559e9c49 5160
4c844851
AD		 5161 if (netif_running(netdev))
5162 igb_down(adapter);
9d5c8243 5163
090b1795 5164 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5165 netdev->mtu, new_mtu);
5166 netdev->mtu = new_mtu;
5167
5168 if (netif_running(netdev))
5169 igb_up(adapter);
5170 else
5171 igb_reset(adapter);
5172
5173 clear_bit(__IGB_RESETTING, &adapter->state);
5174
5175 return 0;
5176}
5177
5178/**
b980ac18
JK		 5179 * igb_update_stats - Update the board statistics counters
5180 * @adapter: board private structure
9d5c8243 5181 **/
12dcd86b
ED		 5182void igb_update_stats(struct igb_adapter *adapter,
5183 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5184{
5185 struct e1000_hw *hw = &adapter->hw;
5186 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5187 u32 reg, mpc;
3f9c0164
AD		 5188 int i;
5189 u64 bytes, packets;
12dcd86b
ED		 5190 unsigned int start;
5191 u64 _bytes, _packets;
9d5c8243 5192
b980ac18 5193 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5194 * connection is down.
5195 */
5196 if (adapter->link_speed == 0)
5197 return;
5198 if (pci_channel_offline(pdev))
5199 return;
5200
3f9c0164
AD		 5201 bytes = 0;
5202 packets = 0;
7f90128e
AA		 5203
5204 rcu_read_lock();
3f9c0164 5205 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5206 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5207 u32 rqdpc = rd32(E1000_RQDPC(i));
5208 if (hw->mac.type >= e1000_i210)
5209 wr32(E1000_RQDPC(i), 0);
12dcd86b 5210
ae1c07a6
AD		 5211 if (rqdpc) {
5212 ring->rx_stats.drops += rqdpc;
5213 net_stats->rx_fifo_errors += rqdpc;
5214 }
12dcd86b
ED		 5215
5216 do {
57a7744e 5217 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5218 _bytes = ring->rx_stats.bytes;
5219 _packets = ring->rx_stats.packets;
57a7744e 5220 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5221 bytes += _bytes;
5222 packets += _packets;
3f9c0164
AD		 5223 }
5224
128e45eb
AD		 5225 net_stats->rx_bytes = bytes;
5226 net_stats->rx_packets = packets;
3f9c0164
AD		 5227
5228 bytes = 0;
5229 packets = 0;
5230 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5231 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5232 do {
57a7744e 5233 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5234 _bytes = ring->tx_stats.bytes;
5235 _packets = ring->tx_stats.packets;
57a7744e 5236 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5237 bytes += _bytes;
5238 packets += _packets;
3f9c0164 5239 }
128e45eb
AD		 5240 net_stats->tx_bytes = bytes;
5241 net_stats->tx_packets = packets;
7f90128e 5242 rcu_read_unlock();
3f9c0164
AD		 5243
5244 /* read stats registers */
9d5c8243
AK		 5245 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5246 adapter->stats.gprc += rd32(E1000_GPRC);
5247 adapter->stats.gorc += rd32(E1000_GORCL);
5248 rd32(E1000_GORCH); /* clear GORCL */
5249 adapter->stats.bprc += rd32(E1000_BPRC);
5250 adapter->stats.mprc += rd32(E1000_MPRC);
5251 adapter->stats.roc += rd32(E1000_ROC);
5252
5253 adapter->stats.prc64 += rd32(E1000_PRC64);
5254 adapter->stats.prc127 += rd32(E1000_PRC127);
5255 adapter->stats.prc255 += rd32(E1000_PRC255);
5256 adapter->stats.prc511 += rd32(E1000_PRC511);
5257 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5258 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5259 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5260 adapter->stats.sec += rd32(E1000_SEC);
5261
fa3d9a6d
MW		 5262 mpc = rd32(E1000_MPC);
5263 adapter->stats.mpc += mpc;
5264 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5265 adapter->stats.scc += rd32(E1000_SCC);
5266 adapter->stats.ecol += rd32(E1000_ECOL);
5267 adapter->stats.mcc += rd32(E1000_MCC);
5268 adapter->stats.latecol += rd32(E1000_LATECOL);
5269 adapter->stats.dc += rd32(E1000_DC);
5270 adapter->stats.rlec += rd32(E1000_RLEC);
5271 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5272 adapter->stats.xontxc += rd32(E1000_XONTXC);
5273 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5274 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5275 adapter->stats.fcruc += rd32(E1000_FCRUC);
5276 adapter->stats.gptc += rd32(E1000_GPTC);
5277 adapter->stats.gotc += rd32(E1000_GOTCL);
5278 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5279 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5280 adapter->stats.ruc += rd32(E1000_RUC);
5281 adapter->stats.rfc += rd32(E1000_RFC);
5282 adapter->stats.rjc += rd32(E1000_RJC);
5283 adapter->stats.tor += rd32(E1000_TORH);
5284 adapter->stats.tot += rd32(E1000_TOTH);
5285 adapter->stats.tpr += rd32(E1000_TPR);
5286
5287 adapter->stats.ptc64 += rd32(E1000_PTC64);
5288 adapter->stats.ptc127 += rd32(E1000_PTC127);
5289 adapter->stats.ptc255 += rd32(E1000_PTC255);
5290 adapter->stats.ptc511 += rd32(E1000_PTC511);
5291 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5292 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5293
5294 adapter->stats.mptc += rd32(E1000_MPTC);
5295 adapter->stats.bptc += rd32(E1000_BPTC);
5296
2d0b0f69
NN		 5297 adapter->stats.tpt += rd32(E1000_TPT);
5298 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5299
5300 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5301 /* read internal phy specific stats */
5302 reg = rd32(E1000_CTRL_EXT);
5303 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5304 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5305
5306 /* this stat has invalid values on i210/i211 */
5307 if ((hw->mac.type != e1000_i210) &&
5308 (hw->mac.type != e1000_i211))
5309 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5310 }
5311
9d5c8243
AK		 5312 adapter->stats.tsctc += rd32(E1000_TSCTC);
5313 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5314
5315 adapter->stats.iac += rd32(E1000_IAC);
5316 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5317 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5318 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5319 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5320 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5321 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5322 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5323 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5324
5325 /* Fill out the OS statistics structure */
128e45eb
AD		 5326 net_stats->multicast = adapter->stats.mprc;
5327 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5328
5329 /* Rx Errors */
5330
5331 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5332 * our own version based on RUC and ROC
5333 */
128e45eb 5334 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5335 adapter->stats.crcerrs + adapter->stats.algnerrc +
5336 adapter->stats.ruc + adapter->stats.roc +
5337 adapter->stats.cexterr;
128e45eb
AD		 5338 net_stats->rx_length_errors = adapter->stats.ruc +
5339 adapter->stats.roc;
5340 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5341 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5342 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5343
5344 /* Tx Errors */
128e45eb
AD		 5345 net_stats->tx_errors = adapter->stats.ecol +
5346 adapter->stats.latecol;
5347 net_stats->tx_aborted_errors = adapter->stats.ecol;
5348 net_stats->tx_window_errors = adapter->stats.latecol;
5349 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5350
5351 /* Tx Dropped needs to be maintained elsewhere */
5352
9d5c8243
AK		 5353 /* Management Stats */
5354 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5355 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5356 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5357
5358 /* OS2BMC Stats */
5359 reg = rd32(E1000_MANC);
5360 if (reg & E1000_MANC_EN_BMC2OS) {
5361 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5362 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5363 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5364 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5365 }
9d5c8243
AK		 5366}
5367
61d7f75f
RC		 5368static void igb_tsync_interrupt(struct igb_adapter *adapter)
5369{
5370 struct e1000_hw *hw = &adapter->hw;
00c65578 5371 struct ptp_clock_event event;
40c9b079 5372 struct timespec64 ts;
720db4ff 5373 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5374
5375 if (tsicr & TSINTR_SYS_WRAP) {
5376 event.type = PTP_CLOCK_PPS;
5377 if (adapter->ptp_caps.pps)
5378 ptp_clock_event(adapter->ptp_clock, &event);
5379 else
5380 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5381 ack |= TSINTR_SYS_WRAP;
5382 }
61d7f75f
RC		 5383
5384 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5385 /* retrieve hardware timestamp */
5386 schedule_work(&adapter->ptp_tx_work);
00c65578 5387 ack |= E1000_TSICR_TXTS;
61d7f75f 5388 }
00c65578 5389
720db4ff
RC		 5390 if (tsicr & TSINTR_TT0) {
5391 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5392 ts = timespec64_add(adapter->perout[0].start,
5393 adapter->perout[0].period);
5394 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5395 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5396 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5397 tsauxc = rd32(E1000_TSAUXC);
5398 tsauxc |= TSAUXC_EN_TT0;
5399 wr32(E1000_TSAUXC, tsauxc);
5400 adapter->perout[0].start = ts;
5401 spin_unlock(&adapter->tmreg_lock);
5402 ack |= TSINTR_TT0;
5403 }
5404
5405 if (tsicr & TSINTR_TT1) {
5406 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5407 ts = timespec64_add(adapter->perout[1].start,
5408 adapter->perout[1].period);
720db4ff 5409 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5410 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5411 tsauxc = rd32(E1000_TSAUXC);
5412 tsauxc |= TSAUXC_EN_TT1;
5413 wr32(E1000_TSAUXC, tsauxc);
5414 adapter->perout[1].start = ts;
5415 spin_unlock(&adapter->tmreg_lock);
5416 ack |= TSINTR_TT1;
5417 }
5418
5419 if (tsicr & TSINTR_AUTT0) {
5420 nsec = rd32(E1000_AUXSTMPL0);
5421 sec = rd32(E1000_AUXSTMPH0);
5422 event.type = PTP_CLOCK_EXTTS;
5423 event.index = 0;
5424 event.timestamp = sec * 1000000000ULL + nsec;
5425 ptp_clock_event(adapter->ptp_clock, &event);
5426 ack |= TSINTR_AUTT0;
5427 }
5428
5429 if (tsicr & TSINTR_AUTT1) {
5430 nsec = rd32(E1000_AUXSTMPL1);
5431 sec = rd32(E1000_AUXSTMPH1);
5432 event.type = PTP_CLOCK_EXTTS;
5433 event.index = 1;
5434 event.timestamp = sec * 1000000000ULL + nsec;
5435 ptp_clock_event(adapter->ptp_clock, &event);
5436 ack |= TSINTR_AUTT1;
5437 }
5438
00c65578
RC		 5439 /* acknowledge the interrupts */
5440 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5441}
5442
9d5c8243
AK		 5443static irqreturn_t igb_msix_other(int irq, void *data)
5444{
047e0030 5445 struct igb_adapter *adapter = data;
9d5c8243 5446 struct e1000_hw *hw = &adapter->hw;
844290e5 5447 u32 icr = rd32(E1000_ICR);
844290e5 5448 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5449
7f081d40
AD		 5450 if (icr & E1000_ICR_DRSTA)
5451 schedule_work(&adapter->reset_task);
5452
047e0030 5453 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5454 /* HW is reporting DMA is out of sync */
5455 adapter->stats.doosync++;
13800469
GR		 5456 /* The DMA Out of Sync is also indication of a spoof event
5457 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5458 * see if it is really a spoof event.
5459 */
13800469 5460 igb_check_wvbr(adapter);
dda0e083 5461 }
eebbbdba 5462
4ae196df
AD		 5463 /* Check for a mailbox event */
5464 if (icr & E1000_ICR_VMMB)
5465 igb_msg_task(adapter);
5466
5467 if (icr & E1000_ICR_LSC) {
5468 hw->mac.get_link_status = 1;
5469 /* guard against interrupt when we're going down */
5470 if (!test_bit(__IGB_DOWN, &adapter->state))
5471 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5472 }
5473
61d7f75f
RC		 5474 if (icr & E1000_ICR_TS)
5475 igb_tsync_interrupt(adapter);
1f6e8178 5476
844290e5 5477 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5478
5479 return IRQ_HANDLED;
5480}
5481
047e0030 5482static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5483{
26b39276 5484 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5485 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5486
047e0030
AD		 5487 if (!q_vector->set_itr)
5488 return;
73cd78f1 5489
047e0030
AD		 5490 if (!itr_val)
5491 itr_val = 0x4;
661086df 5492
26b39276
AD		 5493 if (adapter->hw.mac.type == e1000_82575)
5494 itr_val |= itr_val << 16;
661086df 5495 else
0ba82994 5496 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5497
047e0030
AD		 5498 writel(itr_val, q_vector->itr_register);
5499 q_vector->set_itr = 0;
6eb5a7f1
AD		 5500}
5501
047e0030 5502static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5503{
047e0030 5504 struct igb_q_vector *q_vector = data;
9d5c8243 5505
047e0030
AD		 5506 /* Write the ITR value calculated from the previous interrupt. */
5507 igb_write_itr(q_vector);
9d5c8243 5508
047e0030 5509 napi_schedule(&q_vector->napi);
844290e5 5510
047e0030 5511 return IRQ_HANDLED;
fe4506b6
JC		 5512}
5513
421e02f0 5514#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5515static void igb_update_tx_dca(struct igb_adapter *adapter,
5516 struct igb_ring *tx_ring,
5517 int cpu)
5518{
5519 struct e1000_hw *hw = &adapter->hw;
5520 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5521
5522 if (hw->mac.type != e1000_82575)
5523 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5524
b980ac18 5525 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5526 * DCA is enabled. This is due to a known issue in some chipsets
5527 * which will cause the DCA tag to be cleared.
5528 */
5529 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5530 E1000_DCA_TXCTRL_DATA_RRO_EN |
5531 E1000_DCA_TXCTRL_DESC_DCA_EN;
5532
5533 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5534}
5535
5536static void igb_update_rx_dca(struct igb_adapter *adapter,
5537 struct igb_ring *rx_ring,
5538 int cpu)
5539{
5540 struct e1000_hw *hw = &adapter->hw;
5541 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5542
5543 if (hw->mac.type != e1000_82575)
5544 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5545
b980ac18 5546 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5547 * DCA is enabled. This is due to a known issue in some chipsets
5548 * which will cause the DCA tag to be cleared.
5549 */
5550 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5551 E1000_DCA_RXCTRL_DESC_DCA_EN;
5552
5553 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5554}
5555
047e0030 5556static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5557{
047e0030 5558 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5559 int cpu = get_cpu();
fe4506b6 5560
047e0030
AD		 5561 if (q_vector->cpu == cpu)
5562 goto out_no_update;
5563
6a05004a
AD		 5564 if (q_vector->tx.ring)
5565 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5566
5567 if (q_vector->rx.ring)
5568 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5569
047e0030
AD		 5570 q_vector->cpu = cpu;
5571out_no_update:
fe4506b6
JC		 5572 put_cpu();
5573}
5574
5575static void igb_setup_dca(struct igb_adapter *adapter)
5576{
7e0e99ef 5577 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5578 int i;
5579
7dfc16fa 5580 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5581 return;
5582
7e0e99ef
AD		 5583 /* Always use CB2 mode, difference is masked in the CB driver. */
5584 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5585
047e0030 5586 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5587 adapter->q_vector[i]->cpu = -1;
5588 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5589 }
5590}
5591
5592static int __igb_notify_dca(struct device *dev, void *data)
5593{
5594 struct net_device *netdev = dev_get_drvdata(dev);
5595 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5596 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5597 struct e1000_hw *hw = &adapter->hw;
5598 unsigned long event = *(unsigned long *)data;
5599
5600 switch (event) {
5601 case DCA_PROVIDER_ADD:
5602 /* if already enabled, don't do it again */
7dfc16fa 5603 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5604 break;
fe4506b6 5605 if (dca_add_requester(dev) == 0) {
bbd98fe4 5606 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5607 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5608 igb_setup_dca(adapter);
5609 break;
5610 }
5611 /* Fall Through since DCA is disabled. */
5612 case DCA_PROVIDER_REMOVE:
7dfc16fa 5613 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5614 /* without this a class_device is left
b980ac18
JK		 5615 * hanging around in the sysfs model
5616 */
fe4506b6 5617 dca_remove_requester(dev);
090b1795 5618 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5619 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5620 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5621 }
5622 break;
5623 }
bbd98fe4 5624
fe4506b6 5625 return 0;
9d5c8243
AK		 5626}
5627
fe4506b6 5628static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5629 void *p)
fe4506b6
JC		 5630{
5631 int ret_val;
5632
5633 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5634 __igb_notify_dca);
fe4506b6
JC		 5635
5636 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5637}
421e02f0 5638#endif /* CONFIG_IGB_DCA */
9d5c8243 5639
0224d663
GR		 5640#ifdef CONFIG_PCI_IOV
5641static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5642{
5643 unsigned char mac_addr[ETH_ALEN];
0224d663 5644
5ac6f91d 5645 eth_zero_addr(mac_addr);
0224d663
GR		 5646 igb_set_vf_mac(adapter, vf, mac_addr);
5647
70ea4783
LL		 5648 /* By default spoof check is enabled for all VFs */
5649 adapter->vf_data[vf].spoofchk_enabled = true;
5650
f557147c 5651 return 0;
0224d663
GR		 5652}
5653
0224d663 5654#endif
4ae196df
AD		 5655static void igb_ping_all_vfs(struct igb_adapter *adapter)
5656{
5657 struct e1000_hw *hw = &adapter->hw;
5658 u32 ping;
5659 int i;
5660
5661 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5662 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5663 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5664 ping |= E1000_VT_MSGTYPE_CTS;
5665 igb_write_mbx(hw, &ping, 1, i);
5666 }
5667}
5668
7d5753f0
AD		 5669static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5670{
5671 struct e1000_hw *hw = &adapter->hw;
5672 u32 vmolr = rd32(E1000_VMOLR(vf));
5673 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5674
d85b9004 5675 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5676 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5677 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5678
5679 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5680 vmolr |= E1000_VMOLR_MPME;
d85b9004 5681 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5682 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5683 } else {
b980ac18 5684 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5685 * flag we need to write the hashes to the MTA as this step
5686 * was previously skipped
5687 */
5688 if (vf_data->num_vf_mc_hashes > 30) {
5689 vmolr |= E1000_VMOLR_MPME;
5690 } else if (vf_data->num_vf_mc_hashes) {
5691 int j;
9005df38 5692
7d5753f0
AD		 5693 vmolr |= E1000_VMOLR_ROMPE;
5694 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5695 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5696 }
5697 }
5698
5699 wr32(E1000_VMOLR(vf), vmolr);
5700
5701 /* there are flags left unprocessed, likely not supported */
5702 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5703 return -EINVAL;
5704
5705 return 0;
7d5753f0
AD		 5706}
5707
4ae196df
AD		 5708static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5709 u32 *msgbuf, u32 vf)
5710{
5711 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5712 u16 *hash_list = (u16 *)&msgbuf[1];
5713 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5714 int i;
5715
7d5753f0 5716 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5717 * to this VF for later use to restore when the PF multi cast
5718 * list changes
5719 */
5720 vf_data->num_vf_mc_hashes = n;
5721
7d5753f0
AD		 5722 /* only up to 30 hash values supported */
5723 if (n > 30)
5724 n = 30;
5725
5726 /* store the hashes for later use */
4ae196df 5727 for (i = 0; i < n; i++)
a419aef8 5728 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5729
5730 /* Flush and reset the mta with the new values */
ff41f8dc 5731 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5732
5733 return 0;
5734}
5735
5736static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5737{
5738 struct e1000_hw *hw = &adapter->hw;
5739 struct vf_data_storage *vf_data;
5740 int i, j;
5741
5742 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5743 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5744
7d5753f0
AD		 5745 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5746
4ae196df 5747 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5748
5749 if ((vf_data->num_vf_mc_hashes > 30) ||
5750 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5751 vmolr |= E1000_VMOLR_MPME;
5752 } else if (vf_data->num_vf_mc_hashes) {
5753 vmolr |= E1000_VMOLR_ROMPE;
5754 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5755 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5756 }
5757 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5758 }
5759}
5760
5761static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5762{
5763 struct e1000_hw *hw = &adapter->hw;
5764 u32 pool_mask, reg, vid;
5765 int i;
5766
5767 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5768
5769 /* Find the vlan filter for this id */
5770 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5771 reg = rd32(E1000_VLVF(i));
5772
5773 /* remove the vf from the pool */
5774 reg &= ~pool_mask;
5775
5776 /* if pool is empty then remove entry from vfta */
5777 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5778 (reg & E1000_VLVF_VLANID_ENABLE)) {
5779 reg = 0;
5780 vid = reg & E1000_VLVF_VLANID_MASK;
5781 igb_vfta_set(hw, vid, false);
5782 }
5783
5784 wr32(E1000_VLVF(i), reg);
5785 }
5786}
5787
5788static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5789{
5790 struct e1000_hw *hw = &adapter->hw;
5791 u32 reg, i;
5792
51466239
AD		 5793 /* The vlvf table only exists on 82576 hardware and newer */
5794 if (hw->mac.type < e1000_82576)
5795 return -1;
5796
5797 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5798 if (!adapter->vfs_allocated_count)
5799 return -1;
5800
5801 /* Find the vlan filter for this id */
5802 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5803 reg = rd32(E1000_VLVF(i));
5804 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5805 vid == (reg & E1000_VLVF_VLANID_MASK))
5806 break;
5807 }
5808
5809 if (add) {
5810 if (i == E1000_VLVF_ARRAY_SIZE) {
5811 /* Did not find a matching VLAN ID entry that was
5812 * enabled. Search for a free filter entry, i.e.
5813 * one without the enable bit set
5814 */
5815 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5816 reg = rd32(E1000_VLVF(i));
5817 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5818 break;
5819 }
5820 }
5821 if (i < E1000_VLVF_ARRAY_SIZE) {
5822 /* Found an enabled/available entry */
5823 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5824
5825 /* if !enabled we need to set this up in vfta */
5826 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5827 /* add VID to filter table */
5828 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5829 reg |= E1000_VLVF_VLANID_ENABLE;
5830 }
cad6d05f
AD		 5831 reg &= ~E1000_VLVF_VLANID_MASK;
5832 reg |= vid;
4ae196df 5833 wr32(E1000_VLVF(i), reg);
4ae196df
AD		 5834 }
5835 } else {
5836 if (i < E1000_VLVF_ARRAY_SIZE) {
5837 /* remove vf from the pool */
5838 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5839 /* if pool is empty then remove entry from vfta */
5840 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5841 reg = 0;
5842 igb_vfta_set(hw, vid, false);
5843 }
5844 wr32(E1000_VLVF(i), reg);
4ae196df
AD		 5845 }
5846 }
8151d294
WM		 5847 return 0;
5848}
5849
5850static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5851{
5852 struct e1000_hw *hw = &adapter->hw;
5853
5854 if (vid)
5855 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5856 else
5857 wr32(E1000_VMVIR(vf), 0);
5858}
5859
5860static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5861 int vf, u16 vlan, u8 qos)
5862{
5863 int err = 0;
5864 struct igb_adapter *adapter = netdev_priv(netdev);
5865
5866 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5867 return -EINVAL;
5868 if (vlan || qos) {
5869 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5870 if (err)
5871 goto out;
5872 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5873 igb_set_vmolr(adapter, vf, !vlan);
5874 adapter->vf_data[vf].pf_vlan = vlan;
5875 adapter->vf_data[vf].pf_qos = qos;
5876 dev_info(&adapter->pdev->dev,
5877 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5878 if (test_bit(__IGB_DOWN, &adapter->state)) {
5879 dev_warn(&adapter->pdev->dev,
b980ac18 5880 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5881 dev_warn(&adapter->pdev->dev,
b980ac18 5882 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5883 }
5884 } else {
5885 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5886 false, vf);
8151d294
WM		 5887 igb_set_vmvir(adapter, vlan, vf);
5888 igb_set_vmolr(adapter, vf, true);
5889 adapter->vf_data[vf].pf_vlan = 0;
5890 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5891 }
8151d294 5892out:
b980ac18 5893 return err;
4ae196df
AD		 5894}
5895
6f3dc319
GR		 5896static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5897{
5898 struct e1000_hw *hw = &adapter->hw;
5899 int i;
5900 u32 reg;
5901
5902 /* Find the vlan filter for this id */
5903 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5904 reg = rd32(E1000_VLVF(i));
5905 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5906 vid == (reg & E1000_VLVF_VLANID_MASK))
5907 break;
5908 }
5909
5910 if (i >= E1000_VLVF_ARRAY_SIZE)
5911 i = -1;
5912
5913 return i;
5914}
5915
4ae196df
AD		 5916static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5917{
6f3dc319 5918 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5919 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5920 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5921 int err = 0;
4ae196df 5922
6f3dc319
GR		 5923 /* If in promiscuous mode we need to make sure the PF also has
5924 * the VLAN filter set.
5925 */
5926 if (add && (adapter->netdev->flags & IFF_PROMISC))
5927 err = igb_vlvf_set(adapter, vid, add,
5928 adapter->vfs_allocated_count);
5929 if (err)
5930 goto out;
5931
5932 err = igb_vlvf_set(adapter, vid, add, vf);
5933
5934 if (err)
5935 goto out;
5936
5937 /* Go through all the checks to see if the VLAN filter should
5938 * be wiped completely.
5939 */
5940 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5941 u32 vlvf, bits;
6f3dc319 5942 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 5943
6f3dc319
GR		 5944 if (regndx < 0)
5945 goto out;
5946 /* See if any other pools are set for this VLAN filter
5947 * entry other than the PF.
5948 */
5949 vlvf = bits = rd32(E1000_VLVF(regndx));
5950 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5951 adapter->vfs_allocated_count);
5952 /* If the filter was removed then ensure PF pool bit
5953 * is cleared if the PF only added itself to the pool
5954 * because the PF is in promiscuous mode.
5955 */
5956 if ((vlvf & VLAN_VID_MASK) == vid &&
5957 !test_bit(vid, adapter->active_vlans) &&
5958 !bits)
5959 igb_vlvf_set(adapter, vid, add,
5960 adapter->vfs_allocated_count);
5961 }
5962
5963out:
5964 return err;
4ae196df
AD		 5965}
5966
f2ca0dbe 5967static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5968{
8fa7e0f7
GR		 5969 /* clear flags - except flag that indicates PF has set the MAC */
5970 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5971 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5972
5973 /* reset offloads to defaults */
8151d294 5974 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5975
5976 /* reset vlans for device */
5977 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5978 if (adapter->vf_data[vf].pf_vlan)
5979 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5980 adapter->vf_data[vf].pf_vlan,
5981 adapter->vf_data[vf].pf_qos);
5982 else
5983 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5984
5985 /* reset multicast table array for vf */
5986 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5987
5988 /* Flush and reset the mta with the new values */
ff41f8dc 5989 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5990}
5991
f2ca0dbe
AD		 5992static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5993{
5994 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5995
5ac6f91d 5996 /* clear mac address as we were hotplug removed/added */
8151d294 5997 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5998 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5999
6000 /* process remaining reset events */
6001 igb_vf_reset(adapter, vf);
6002}
6003
6004static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6005{
6006 struct e1000_hw *hw = &adapter->hw;
6007 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6008 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6009 u32 reg, msgbuf[3];
6010 u8 *addr = (u8 *)(&msgbuf[1]);
6011
6012 /* process all the same items cleared in a function level reset */
f2ca0dbe 6013 igb_vf_reset(adapter, vf);
4ae196df
AD		 6014
6015 /* set vf mac address */
26ad9178 6016 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6017
6018 /* enable transmit and receive for vf */
6019 reg = rd32(E1000_VFTE);
6020 wr32(E1000_VFTE, reg | (1 << vf));
6021 reg = rd32(E1000_VFRE);
6022 wr32(E1000_VFRE, reg | (1 << vf));
6023
8fa7e0f7 6024 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6025
6026 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6027 if (!is_zero_ether_addr(vf_mac)) {
6028 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6029 memcpy(addr, vf_mac, ETH_ALEN);
6030 } else {
6031 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6032 }
4ae196df
AD		 6033 igb_write_mbx(hw, msgbuf, 3, vf);
6034}
6035
6036static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6037{
b980ac18 6038 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6039 * starting at the second 32 bit word of the msg array
6040 */
f2ca0dbe
AD		 6041 unsigned char *addr = (char *)&msg[1];
6042 int err = -1;
4ae196df 6043
f2ca0dbe
AD		 6044 if (is_valid_ether_addr(addr))
6045 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6046
f2ca0dbe 6047 return err;
4ae196df
AD		 6048}
6049
6050static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6051{
6052 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6053 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6054 u32 msg = E1000_VT_MSGTYPE_NACK;
6055
6056 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6057 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6058 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6059 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6060 vf_data->last_nack = jiffies;
4ae196df
AD		 6061 }
6062}
6063
f2ca0dbe 6064static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6065{
f2ca0dbe
AD		 6066 struct pci_dev *pdev = adapter->pdev;
6067 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6068 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6069 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6070 s32 retval;
6071
f2ca0dbe 6072 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6073
fef45f4c
AD		 6074 if (retval) {
6075 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6076 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6077 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6078 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6079 return;
6080 goto out;
6081 }
4ae196df
AD		 6082
6083 /* this is a message we already processed, do nothing */
6084 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6085 return;
4ae196df 6086
b980ac18 6087 /* until the vf completes a reset it should not be
4ae196df
AD		 6088 * allowed to start any configuration.
6089 */
4ae196df
AD		 6090 if (msgbuf[0] == E1000_VF_RESET) {
6091 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6092 return;
4ae196df
AD		 6093 }
6094
f2ca0dbe 6095 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6096 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6097 return;
6098 retval = -1;
6099 goto out;
4ae196df
AD		 6100 }
6101
6102 switch ((msgbuf[0] & 0xFFFF)) {
6103 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6104 retval = -EINVAL;
6105 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6106 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6107 else
6108 dev_warn(&pdev->dev,
b980ac18
JK		 6109 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6110 vf);
4ae196df 6111 break;
7d5753f0
AD		 6112 case E1000_VF_SET_PROMISC:
6113 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6114 break;
4ae196df
AD		 6115 case E1000_VF_SET_MULTICAST:
6116 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6117 break;
6118 case E1000_VF_SET_LPE:
6119 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6120 break;
6121 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6122 retval = -1;
6123 if (vf_data->pf_vlan)
6124 dev_warn(&pdev->dev,
b980ac18
JK		 6125 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6126 vf);
8151d294
WM		 6127 else
6128 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6129 break;
6130 default:
090b1795 6131 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6132 retval = -1;
6133 break;
6134 }
6135
fef45f4c
AD		 6136 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6137out:
4ae196df
AD		 6138 /* notify the VF of the results of what it sent us */
6139 if (retval)
6140 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6141 else
6142 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6143
4ae196df 6144 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6145}
4ae196df 6146
f2ca0dbe
AD		 6147static void igb_msg_task(struct igb_adapter *adapter)
6148{
6149 struct e1000_hw *hw = &adapter->hw;
6150 u32 vf;
6151
6152 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6153 /* process any reset requests */
6154 if (!igb_check_for_rst(hw, vf))
6155 igb_vf_reset_event(adapter, vf);
6156
6157 /* process any messages pending */
6158 if (!igb_check_for_msg(hw, vf))
6159 igb_rcv_msg_from_vf(adapter, vf);
6160
6161 /* process any acks */
6162 if (!igb_check_for_ack(hw, vf))
6163 igb_rcv_ack_from_vf(adapter, vf);
6164 }
4ae196df
AD		 6165}
6166
68d480c4
AD		 6167/**
6168 * igb_set_uta - Set unicast filter table address
6169 * @adapter: board private structure
6170 *
6171 * The unicast table address is a register array of 32-bit registers.
6172 * The table is meant to be used in a way similar to how the MTA is used
6173 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6174 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6175 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6176 **/
6177static void igb_set_uta(struct igb_adapter *adapter)
6178{
6179 struct e1000_hw *hw = &adapter->hw;
6180 int i;
6181
6182 /* The UTA table only exists on 82576 hardware and newer */
6183 if (hw->mac.type < e1000_82576)
6184 return;
6185
6186 /* we only need to do this if VMDq is enabled */
6187 if (!adapter->vfs_allocated_count)
6188 return;
6189
6190 for (i = 0; i < hw->mac.uta_reg_count; i++)
6191 array_wr32(E1000_UTA, i, ~0);
6192}
6193
9d5c8243 6194/**
b980ac18
JK		 6195 * igb_intr_msi - Interrupt Handler
6196 * @irq: interrupt number
6197 * @data: pointer to a network interface device structure
9d5c8243
AK		 6198 **/
6199static irqreturn_t igb_intr_msi(int irq, void *data)
6200{
047e0030
AD		 6201 struct igb_adapter *adapter = data;
6202 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6203 struct e1000_hw *hw = &adapter->hw;
6204 /* read ICR disables interrupts using IAM */
6205 u32 icr = rd32(E1000_ICR);
6206
047e0030 6207 igb_write_itr(q_vector);
9d5c8243 6208
7f081d40
AD		 6209 if (icr & E1000_ICR_DRSTA)
6210 schedule_work(&adapter->reset_task);
6211
047e0030 6212 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6213 /* HW is reporting DMA is out of sync */
6214 adapter->stats.doosync++;
6215 }
6216
9d5c8243
AK		 6217 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6218 hw->mac.get_link_status = 1;
6219 if (!test_bit(__IGB_DOWN, &adapter->state))
6220 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6221 }
6222
61d7f75f
RC		 6223 if (icr & E1000_ICR_TS)
6224 igb_tsync_interrupt(adapter);
1f6e8178 6225
047e0030 6226 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6227
6228 return IRQ_HANDLED;
6229}
6230
6231/**
b980ac18
JK		 6232 * igb_intr - Legacy Interrupt Handler
6233 * @irq: interrupt number
6234 * @data: pointer to a network interface device structure
9d5c8243
AK		 6235 **/
6236static irqreturn_t igb_intr(int irq, void *data)
6237{
047e0030
AD		 6238 struct igb_adapter *adapter = data;
6239 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6240 struct e1000_hw *hw = &adapter->hw;
6241 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6242 * need for the IMC write
6243 */
9d5c8243 6244 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6245
6246 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6247 * not set, then the adapter didn't send an interrupt
6248 */
9d5c8243
AK		 6249 if (!(icr & E1000_ICR_INT_ASSERTED))
6250 return IRQ_NONE;
6251
0ba82994
AD		 6252 igb_write_itr(q_vector);
6253
7f081d40
AD		 6254 if (icr & E1000_ICR_DRSTA)
6255 schedule_work(&adapter->reset_task);
6256
047e0030 6257 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6258 /* HW is reporting DMA is out of sync */
6259 adapter->stats.doosync++;
6260 }
6261
9d5c8243
AK		 6262 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6263 hw->mac.get_link_status = 1;
6264 /* guard against interrupt when we're going down */
6265 if (!test_bit(__IGB_DOWN, &adapter->state))
6266 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6267 }
6268
61d7f75f
RC		 6269 if (icr & E1000_ICR_TS)
6270 igb_tsync_interrupt(adapter);
1f6e8178 6271
047e0030 6272 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6273
6274 return IRQ_HANDLED;
6275}
6276
c50b52a0 6277static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6278{
047e0030 6279 struct igb_adapter *adapter = q_vector->adapter;
46544258 6280 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6281
0ba82994
AD		 6282 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6283 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6284 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6285 igb_set_itr(q_vector);
46544258 6286 else
047e0030 6287 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6288 }
6289
46544258 6290 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6291 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6292 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6293 else
6294 igb_irq_enable(adapter);
6295 }
9d5c8243
AK		 6296}
6297
46544258 6298/**
b980ac18
JK		 6299 * igb_poll - NAPI Rx polling callback
6300 * @napi: napi polling structure
6301 * @budget: count of how many packets we should handle
46544258
AD		 6302 **/
6303static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6304{
047e0030 6305 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6306 struct igb_q_vector,
6307 napi);
16eb8815 6308 bool clean_complete = true;
32b3e08f 6309 int work_done = 0;
9d5c8243 6310
421e02f0 6311#ifdef CONFIG_IGB_DCA
047e0030
AD		 6312 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6313 igb_update_dca(q_vector);
fe4506b6 6314#endif
0ba82994 6315 if (q_vector->tx.ring)
13fde97a 6316 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6317
32b3e08f
JB		 6318 if (q_vector->rx.ring) {
6319 int cleaned = igb_clean_rx_irq(q_vector, budget);
6320
6321 work_done += cleaned;
6322 clean_complete &= (cleaned < budget);
6323 }
047e0030 6324
16eb8815
AD		 6325 /* If all work not completed, return budget and keep polling */
6326 if (!clean_complete)
6327 return budget;
46544258 6328
9d5c8243 6329 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6330 napi_complete_done(napi, work_done);
16eb8815 6331 igb_ring_irq_enable(q_vector);
9d5c8243 6332
16eb8815 6333 return 0;
9d5c8243 6334}
6d8126f9 6335
9d5c8243 6336/**
b980ac18
JK		 6337 * igb_clean_tx_irq - Reclaim resources after transmit completes
6338 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6339 *
b980ac18 6340 * returns true if ring is completely cleaned
9d5c8243 6341 **/
047e0030 6342static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6343{
047e0030 6344 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6345 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6346 struct igb_tx_buffer *tx_buffer;
f4128785 6347 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6348 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6349 unsigned int budget = q_vector->tx.work_limit;
8542db05 6350 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6351
13fde97a
AD		 6352 if (test_bit(__IGB_DOWN, &adapter->state))
6353 return true;
0e014cb1 6354
06034649 6355 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6356 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6357 i -= tx_ring->count;
9d5c8243 6358
f4128785
AD		 6359 do {
6360 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6361
6362 /* if next_to_watch is not set then there is no work pending */
6363 if (!eop_desc)
6364 break;
13fde97a 6365
f4128785 6366 /* prevent any other reads prior to eop_desc */
70d289bc 6367 read_barrier_depends();
f4128785 6368
13fde97a
AD		 6369 /* if DD is not set pending work has not been completed */
6370 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6371 break;
6372
8542db05
AD		 6373 /* clear next_to_watch to prevent false hangs */
6374 tx_buffer->next_to_watch = NULL;
9d5c8243 6375
ebe42d16
AD		 6376 /* update the statistics for this packet */
6377 total_bytes += tx_buffer->bytecount;
6378 total_packets += tx_buffer->gso_segs;
13fde97a 6379
ebe42d16 6380 /* free the skb */
a81fb049 6381 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6382
ebe42d16
AD		 6383 /* unmap skb header data */
6384 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6385 dma_unmap_addr(tx_buffer, dma),
6386 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6387 DMA_TO_DEVICE);
6388
c9f14bf3
AD		 6389 /* clear tx_buffer data */
6390 tx_buffer->skb = NULL;
6391 dma_unmap_len_set(tx_buffer, len, 0);
6392
ebe42d16
AD		 6393 /* clear last DMA location and unmap remaining buffers */
6394 while (tx_desc != eop_desc) {
13fde97a
AD		 6395 tx_buffer++;
6396 tx_desc++;
9d5c8243 6397 i++;
8542db05
AD		 6398 if (unlikely(!i)) {
6399 i -= tx_ring->count;
06034649 6400 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6401 tx_desc = IGB_TX_DESC(tx_ring, 0);
6402 }
ebe42d16
AD		 6403
6404 /* unmap any remaining paged data */
c9f14bf3 6405 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6406 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6407 dma_unmap_addr(tx_buffer, dma),
6408 dma_unmap_len(tx_buffer, len),
ebe42d16 6409 DMA_TO_DEVICE);
c9f14bf3 6410 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6411 }
6412 }
6413
ebe42d16
AD		 6414 /* move us one more past the eop_desc for start of next pkt */
6415 tx_buffer++;
6416 tx_desc++;
6417 i++;
6418 if (unlikely(!i)) {
6419 i -= tx_ring->count;
6420 tx_buffer = tx_ring->tx_buffer_info;
6421 tx_desc = IGB_TX_DESC(tx_ring, 0);
6422 }
f4128785
AD		 6423
6424 /* issue prefetch for next Tx descriptor */
6425 prefetch(tx_desc);
6426
6427 /* update budget accounting */
6428 budget--;
6429 } while (likely(budget));
0e014cb1 6430
bdbc0631
ED		 6431 netdev_tx_completed_queue(txring_txq(tx_ring),
6432 total_packets, total_bytes);
8542db05 6433 i += tx_ring->count;
9d5c8243 6434 tx_ring->next_to_clean = i;
13fde97a
AD		 6435 u64_stats_update_begin(&tx_ring->tx_syncp);
6436 tx_ring->tx_stats.bytes += total_bytes;
6437 tx_ring->tx_stats.packets += total_packets;
6438 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6439 q_vector->tx.total_bytes += total_bytes;
6440 q_vector->tx.total_packets += total_packets;
9d5c8243 6441
6d095fa8 6442 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6443 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6444
9d5c8243 6445 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6446 * check with the clearing of time_stamp and movement of i
6447 */
6d095fa8 6448 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6449 if (tx_buffer->next_to_watch &&
8542db05 6450 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6451 (adapter->tx_timeout_factor * HZ)) &&
6452 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6453
9d5c8243 6454 /* detected Tx unit hang */
59d71989 6455 dev_err(tx_ring->dev,
9d5c8243 6456 "Detected Tx Unit Hang\n"
2d064c06 6457 " Tx Queue <%d>\n"
9d5c8243
AK		 6458 " TDH <%x>\n"
6459 " TDT <%x>\n"
6460 " next_to_use <%x>\n"
6461 " next_to_clean <%x>\n"
9d5c8243
AK		 6462 "buffer_info[next_to_clean]\n"
6463 " time_stamp <%lx>\n"
8542db05 6464 " next_to_watch <%p>\n"
9d5c8243
AK		 6465 " jiffies <%lx>\n"
6466 " desc.status <%x>\n",
2d064c06 6467 tx_ring->queue_index,
238ac817 6468 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6469 readl(tx_ring->tail),
9d5c8243
AK		 6470 tx_ring->next_to_use,
6471 tx_ring->next_to_clean,
8542db05 6472 tx_buffer->time_stamp,
f4128785 6473 tx_buffer->next_to_watch,
9d5c8243 6474 jiffies,
f4128785 6475 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6476 netif_stop_subqueue(tx_ring->netdev,
6477 tx_ring->queue_index);
6478
6479 /* we are about to reset, no point in enabling stuff */
6480 return true;
9d5c8243
AK		 6481 }
6482 }
13fde97a 6483
21ba6fe1 6484#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6485 if (unlikely(total_packets &&
b980ac18
JK		 6486 netif_carrier_ok(tx_ring->netdev) &&
6487 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6488 /* Make sure that anybody stopping the queue after this
6489 * sees the new next_to_clean.
6490 */
6491 smp_mb();
6492 if (__netif_subqueue_stopped(tx_ring->netdev,
6493 tx_ring->queue_index) &&
6494 !(test_bit(__IGB_DOWN, &adapter->state))) {
6495 netif_wake_subqueue(tx_ring->netdev,
6496 tx_ring->queue_index);
6497
6498 u64_stats_update_begin(&tx_ring->tx_syncp);
6499 tx_ring->tx_stats.restart_queue++;
6500 u64_stats_update_end(&tx_ring->tx_syncp);
6501 }
6502 }
6503
6504 return !!budget;
9d5c8243
AK		 6505}
6506
cbc8e55f 6507/**
b980ac18
JK		 6508 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6509 * @rx_ring: rx descriptor ring to store buffers on
6510 * @old_buff: donor buffer to have page reused
cbc8e55f 6511 *
b980ac18 6512 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6513 **/
6514static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6515 struct igb_rx_buffer *old_buff)
6516{
6517 struct igb_rx_buffer *new_buff;
6518 u16 nta = rx_ring->next_to_alloc;
6519
6520 new_buff = &rx_ring->rx_buffer_info[nta];
6521
6522 /* update, and store next to alloc */
6523 nta++;
6524 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6525
6526 /* transfer page from old buffer to new buffer */
a1f63473 6527 *new_buff = *old_buff;
cbc8e55f
AD		 6528
6529 /* sync the buffer for use by the device */
6530 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6531 old_buff->page_offset,
de78d1f9 6532 IGB_RX_BUFSZ,
cbc8e55f
AD		 6533 DMA_FROM_DEVICE);
6534}
6535
95dd44b4
AD		 6536static inline bool igb_page_is_reserved(struct page *page)
6537{
2f064f34 6538 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6539}
6540
74e238ea
AD		 6541static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6542 struct page *page,
6543 unsigned int truesize)
6544{
6545 /* avoid re-using remote pages */
95dd44b4 6546 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6547 return false;
6548
74e238ea
AD		 6549#if (PAGE_SIZE < 8192)
6550 /* if we are only owner of page we can reuse it */
6551 if (unlikely(page_count(page) != 1))
6552 return false;
6553
6554 /* flip page offset to other buffer */
6555 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6556#else
6557 /* move offset up to the next cache line */
6558 rx_buffer->page_offset += truesize;
6559
6560 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6561 return false;
74e238ea
AD		 6562#endif
6563
95dd44b4
AD		 6564 /* Even if we own the page, we are not allowed to use atomic_set()
6565 * This would break get_page_unless_zero() users.
6566 */
6567 atomic_inc(&page->_count);
6568
74e238ea
AD		 6569 return true;
6570}
6571
cbc8e55f 6572/**
b980ac18
JK		 6573 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6574 * @rx_ring: rx descriptor ring to transact packets on
6575 * @rx_buffer: buffer containing page to add
6576 * @rx_desc: descriptor containing length of buffer written by hardware
6577 * @skb: sk_buff to place the data into
cbc8e55f 6578 *
b980ac18
JK		 6579 * This function will add the data contained in rx_buffer->page to the skb.
6580 * This is done either through a direct copy if the data in the buffer is
6581 * less than the skb header size, otherwise it will just attach the page as
6582 * a frag to the skb.
cbc8e55f 6583 *
b980ac18
JK		 6584 * The function will then update the page offset if necessary and return
6585 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6586 **/
6587static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6588 struct igb_rx_buffer *rx_buffer,
6589 union e1000_adv_rx_desc *rx_desc,
6590 struct sk_buff *skb)
6591{
6592 struct page *page = rx_buffer->page;
f56e7bba 6593 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6594 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6595#if (PAGE_SIZE < 8192)
6596 unsigned int truesize = IGB_RX_BUFSZ;
6597#else
f56e7bba 6598 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6599#endif
f56e7bba 6600 unsigned int pull_len;
cbc8e55f 6601
f56e7bba
AD		 6602 if (unlikely(skb_is_nonlinear(skb)))
6603 goto add_tail_frag;
cbc8e55f 6604
f56e7bba
AD		 6605 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6606 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6607 va += IGB_TS_HDR_LEN;
6608 size -= IGB_TS_HDR_LEN;
6609 }
cbc8e55f 6610
f56e7bba 6611 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6612 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6613
95dd44b4
AD		 6614 /* page is not reserved, we can reuse buffer as-is */
6615 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6616 return true;
6617
6618 /* this page cannot be reused so discard it */
95dd44b4 6619 __free_page(page);
cbc8e55f
AD		 6620 return false;
6621 }
6622
f56e7bba
AD		 6623 /* we need the header to contain the greater of either ETH_HLEN or
6624 * 60 bytes if the skb->len is less than 60 for skb_pad.
6625 */
6626 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6627
6628 /* align pull length to size of long to optimize memcpy performance */
6629 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6630
6631 /* update all of the pointers */
6632 va += pull_len;
6633 size -= pull_len;
6634
6635add_tail_frag:
cbc8e55f 6636 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6637 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6638
74e238ea
AD		 6639 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6640}
cbc8e55f 6641
2e334eee
AD		 6642static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6643 union e1000_adv_rx_desc *rx_desc,
6644 struct sk_buff *skb)
6645{
6646 struct igb_rx_buffer *rx_buffer;
6647 struct page *page;
6648
6649 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6650 page = rx_buffer->page;
6651 prefetchw(page);
6652
6653 if (likely(!skb)) {
6654 void *page_addr = page_address(page) +
6655 rx_buffer->page_offset;
6656
6657 /* prefetch first cache line of first page */
6658 prefetch(page_addr);
6659#if L1_CACHE_BYTES < 128
6660 prefetch(page_addr + L1_CACHE_BYTES);
6661#endif
6662
6663 /* allocate a skb to store the frags */
67fd893e 6664 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6665 if (unlikely(!skb)) {
6666 rx_ring->rx_stats.alloc_failed++;
6667 return NULL;
6668 }
6669
b980ac18 6670 /* we will be copying header into skb->data in
2e334eee
AD		 6671 * pskb_may_pull so it is in our interest to prefetch
6672 * it now to avoid a possible cache miss
6673 */
6674 prefetchw(skb->data);
6675 }
6676
6677 /* we are reusing so sync this buffer for CPU use */
6678 dma_sync_single_range_for_cpu(rx_ring->dev,
6679 rx_buffer->dma,
6680 rx_buffer->page_offset,
de78d1f9 6681 IGB_RX_BUFSZ,
2e334eee
AD		 6682 DMA_FROM_DEVICE);
6683
6684 /* pull page into skb */
6685 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6686 /* hand second half of page back to the ring */
6687 igb_reuse_rx_page(rx_ring, rx_buffer);
6688 } else {
6689 /* we are not reusing the buffer so unmap it */
6690 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6691 PAGE_SIZE, DMA_FROM_DEVICE);
6692 }
6693
6694 /* clear contents of rx_buffer */
6695 rx_buffer->page = NULL;
6696
6697 return skb;
6698}
6699
cd392f5c 6700static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6701 union e1000_adv_rx_desc *rx_desc,
6702 struct sk_buff *skb)
9d5c8243 6703{
bc8acf2c 6704 skb_checksum_none_assert(skb);
9d5c8243 6705
294e7d78 6706 /* Ignore Checksum bit is set */
3ceb90fd 6707 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6708 return;
6709
6710 /* Rx checksum disabled via ethtool */
6711 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6712 return;
85ad76b2 6713
9d5c8243 6714 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6715 if (igb_test_staterr(rx_desc,
6716 E1000_RXDEXT_STATERR_TCPE |
6717 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6718 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6719 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6720 * packets, (aka let the stack check the crc32c)
6721 */
866cff06
AD		 6722 if (!((skb->len == 60) &&
6723 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6724 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6725 ring->rx_stats.csum_err++;
12dcd86b
ED		 6726 u64_stats_update_end(&ring->rx_syncp);
6727 }
9d5c8243 6728 /* let the stack verify checksum errors */
9d5c8243
AK		 6729 return;
6730 }
6731 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6732 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6733 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6734 skb->ip_summed = CHECKSUM_UNNECESSARY;
6735
3ceb90fd
AD		 6736 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6737 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6738}
6739
077887c3
AD		 6740static inline void igb_rx_hash(struct igb_ring *ring,
6741 union e1000_adv_rx_desc *rx_desc,
6742 struct sk_buff *skb)
6743{
6744 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6745 skb_set_hash(skb,
6746 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6747 PKT_HASH_TYPE_L3);
077887c3
AD		 6748}
6749
2e334eee 6750/**
b980ac18
JK		 6751 * igb_is_non_eop - process handling of non-EOP buffers
6752 * @rx_ring: Rx ring being processed
6753 * @rx_desc: Rx descriptor for current buffer
6754 * @skb: current socket buffer containing buffer in progress
2e334eee 6755 *
b980ac18
JK		 6756 * This function updates next to clean. If the buffer is an EOP buffer
6757 * this function exits returning false, otherwise it will place the
6758 * sk_buff in the next buffer to be chained and return true indicating
6759 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6760 **/
6761static bool igb_is_non_eop(struct igb_ring *rx_ring,
6762 union e1000_adv_rx_desc *rx_desc)
6763{
6764 u32 ntc = rx_ring->next_to_clean + 1;
6765
6766 /* fetch, update, and store next to clean */
6767 ntc = (ntc < rx_ring->count) ? ntc : 0;
6768 rx_ring->next_to_clean = ntc;
6769
6770 prefetch(IGB_RX_DESC(rx_ring, ntc));
6771
6772 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6773 return false;
6774
6775 return true;
6776}
6777
1a1c225b 6778/**
b980ac18
JK		 6779 * igb_cleanup_headers - Correct corrupted or empty headers
6780 * @rx_ring: rx descriptor ring packet is being transacted on
6781 * @rx_desc: pointer to the EOP Rx descriptor
6782 * @skb: pointer to current skb being fixed
1a1c225b 6783 *
b980ac18
JK		 6784 * Address the case where we are pulling data in on pages only
6785 * and as such no data is present in the skb header.
1a1c225b 6786 *
b980ac18
JK		 6787 * In addition if skb is not at least 60 bytes we need to pad it so that
6788 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6789 *
b980ac18 6790 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6791 **/
6792static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6793 union e1000_adv_rx_desc *rx_desc,
6794 struct sk_buff *skb)
6795{
1a1c225b
AD		 6796 if (unlikely((igb_test_staterr(rx_desc,
6797 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6798 struct net_device *netdev = rx_ring->netdev;
6799 if (!(netdev->features & NETIF_F_RXALL)) {
6800 dev_kfree_skb_any(skb);
6801 return true;
6802 }
6803 }
6804
a94d9e22
AD		 6805 /* if eth_skb_pad returns an error the skb was freed */
6806 if (eth_skb_pad(skb))
6807 return true;
1a1c225b
AD		 6808
6809 return false;
2d94d8ab
AD		 6810}
6811
db2ee5bd 6812/**
b980ac18
JK		 6813 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6814 * @rx_ring: rx descriptor ring packet is being transacted on
6815 * @rx_desc: pointer to the EOP Rx descriptor
6816 * @skb: pointer to current skb being populated
db2ee5bd 6817 *
b980ac18
JK		 6818 * This function checks the ring, descriptor, and packet information in
6819 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6820 * other fields within the skb.
db2ee5bd
AD		 6821 **/
6822static void igb_process_skb_fields(struct igb_ring *rx_ring,
6823 union e1000_adv_rx_desc *rx_desc,
6824 struct sk_buff *skb)
6825{
6826 struct net_device *dev = rx_ring->netdev;
6827
6828 igb_rx_hash(rx_ring, rx_desc, skb);
6829
6830 igb_rx_checksum(rx_ring, rx_desc, skb);
6831
5499a968
JK		 6832 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6833 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6834 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6835
f646968f 6836 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6837 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6838 u16 vid;
9005df38 6839
db2ee5bd
AD		 6840 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6841 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6842 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6843 else
6844 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6845
86a9bad3 6846 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6847 }
6848
6849 skb_record_rx_queue(skb, rx_ring->queue_index);
6850
6851 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6852}
6853
32b3e08f 6854static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6855{
0ba82994 6856 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6857 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6858 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6859 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6860
57ba34c9 6861 while (likely(total_packets < budget)) {
2e334eee 6862 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6863
2e334eee
AD		 6864 /* return some buffers to hardware, one at a time is too slow */
6865 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6866 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6867 cleaned_count = 0;
6868 }
bf36c1a0 6869
2e334eee 6870 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6871
124b74c1 6872 if (!rx_desc->wb.upper.status_error)
2e334eee 6873 break;
9d5c8243 6874
74e238ea
AD		 6875 /* This memory barrier is needed to keep us from reading
6876 * any other fields out of the rx_desc until we know the
124b74c1 6877 * descriptor has been written back
74e238ea 6878 */
124b74c1 6879 dma_rmb();
74e238ea 6880
2e334eee 6881 /* retrieve a buffer from the ring */
f9d40f6a 6882 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6883
2e334eee
AD		 6884 /* exit if we failed to retrieve a buffer */
6885 if (!skb)
6886 break;
1a1c225b 6887
2e334eee 6888 cleaned_count++;
1a1c225b 6889
2e334eee
AD		 6890 /* fetch next buffer in frame if non-eop */
6891 if (igb_is_non_eop(rx_ring, rx_desc))
6892 continue;
1a1c225b
AD		 6893
6894 /* verify the packet layout is correct */
6895 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6896 skb = NULL;
6897 continue;
9d5c8243 6898 }
9d5c8243 6899
db2ee5bd 6900 /* probably a little skewed due to removing CRC */
3ceb90fd 6901 total_bytes += skb->len;
3ceb90fd 6902
db2ee5bd
AD		 6903 /* populate checksum, timestamp, VLAN, and protocol */
6904 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6905
b2cb09b1 6906 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6907
1a1c225b
AD		 6908 /* reset skb pointer */
6909 skb = NULL;
6910
2e334eee
AD		 6911 /* update budget accounting */
6912 total_packets++;
57ba34c9 6913 }
bf36c1a0 6914
1a1c225b
AD		 6915 /* place incomplete frames back on ring for completion */
6916 rx_ring->skb = skb;
6917
12dcd86b 6918 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6919 rx_ring->rx_stats.packets += total_packets;
6920 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6921 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6922 q_vector->rx.total_packets += total_packets;
6923 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6924
6925 if (cleaned_count)
cd392f5c 6926 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6927
32b3e08f 6928 return total_packets;
9d5c8243
AK		 6929}
6930
c023cd88 6931static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6932 struct igb_rx_buffer *bi)
c023cd88
AD		 6933{
6934 struct page *page = bi->page;
cbc8e55f 6935 dma_addr_t dma;
c023cd88 6936
cbc8e55f
AD		 6937 /* since we are recycling buffers we should seldom need to alloc */
6938 if (likely(page))
c023cd88
AD		 6939 return true;
6940
cbc8e55f 6941 /* alloc new page for storage */
42b17f09 6942 page = dev_alloc_page();
cbc8e55f
AD		 6943 if (unlikely(!page)) {
6944 rx_ring->rx_stats.alloc_failed++;
6945 return false;
c023cd88
AD		 6946 }
6947
cbc8e55f
AD		 6948 /* map page for use */
6949 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6950
b980ac18 6951 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6952 * there isn't much point in holding memory we can't use
6953 */
1a1c225b 6954 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6955 __free_page(page);
6956
c023cd88
AD		 6957 rx_ring->rx_stats.alloc_failed++;
6958 return false;
6959 }
6960
1a1c225b 6961 bi->dma = dma;
cbc8e55f
AD		 6962 bi->page = page;
6963 bi->page_offset = 0;
1a1c225b 6964
c023cd88
AD		 6965 return true;
6966}
6967
9d5c8243 6968/**
b980ac18
JK		 6969 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6970 * @adapter: address of board private structure
9d5c8243 6971 **/
cd392f5c 6972void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6973{
9d5c8243 6974 union e1000_adv_rx_desc *rx_desc;
06034649 6975 struct igb_rx_buffer *bi;
c023cd88 6976 u16 i = rx_ring->next_to_use;
9d5c8243 6977
cbc8e55f
AD		 6978 /* nothing to do */
6979 if (!cleaned_count)
6980 return;
6981
60136906 6982 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6983 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6984 i -= rx_ring->count;
9d5c8243 6985
cbc8e55f 6986 do {
1a1c225b 6987 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6988 break;
9d5c8243 6989
b980ac18 6990 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6991 * because each write-back erases this info.
6992 */
f9d40f6a 6993 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6994
c023cd88
AD		 6995 rx_desc++;
6996 bi++;
9d5c8243 6997 i++;
c023cd88 6998 if (unlikely(!i)) {
60136906 6999 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7000 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7001 i -= rx_ring->count;
7002 }
7003
95dd44b4
AD		 7004 /* clear the status bits for the next_to_use descriptor */
7005 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7006
7007 cleaned_count--;
7008 } while (cleaned_count);
9d5c8243 7009
c023cd88
AD		 7010 i += rx_ring->count;
7011
9d5c8243 7012 if (rx_ring->next_to_use != i) {
cbc8e55f 7013 /* record the next descriptor to use */
9d5c8243 7014 rx_ring->next_to_use = i;
9d5c8243 7015
cbc8e55f
AD		 7016 /* update next to alloc since we have filled the ring */
7017 rx_ring->next_to_alloc = i;
7018
b980ac18 7019 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7020 * know there are new descriptors to fetch. (Only
7021 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7022 * such as IA-64).
7023 */
9d5c8243 7024 wmb();
fce99e34 7025 writel(i, rx_ring->tail);
9d5c8243
AK		 7026 }
7027}
7028
7029/**
7030 * igb_mii_ioctl -
7031 * @netdev:
7032 * @ifreq:
7033 * @cmd:
7034 **/
7035static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7036{
7037 struct igb_adapter *adapter = netdev_priv(netdev);
7038 struct mii_ioctl_data *data = if_mii(ifr);
7039
7040 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7041 return -EOPNOTSUPP;
7042
7043 switch (cmd) {
7044 case SIOCGMIIPHY:
7045 data->phy_id = adapter->hw.phy.addr;
7046 break;
7047 case SIOCGMIIREG:
f5f4cf08 7048 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7049 &data->val_out))
9d5c8243
AK		 7050 return -EIO;
7051 break;
7052 case SIOCSMIIREG:
7053 default:
7054 return -EOPNOTSUPP;
7055 }
7056 return 0;
7057}
7058
7059/**
7060 * igb_ioctl -
7061 * @netdev:
7062 * @ifreq:
7063 * @cmd:
7064 **/
7065static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7066{
7067 switch (cmd) {
7068 case SIOCGMIIPHY:
7069 case SIOCGMIIREG:
7070 case SIOCSMIIREG:
7071 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7072 case SIOCGHWTSTAMP:
7073 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7074 case SIOCSHWTSTAMP:
6ab5f7b2 7075 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7076 default:
7077 return -EOPNOTSUPP;
7078 }
7079}
7080
94826487
TF		 7081void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7082{
7083 struct igb_adapter *adapter = hw->back;
7084
7085 pci_read_config_word(adapter->pdev, reg, value);
7086}
7087
7088void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7089{
7090 struct igb_adapter *adapter = hw->back;
7091
7092 pci_write_config_word(adapter->pdev, reg, *value);
7093}
7094
009bc06e
AD		 7095s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7096{
7097 struct igb_adapter *adapter = hw->back;
009bc06e 7098
23d028cc 7099 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7100 return -E1000_ERR_CONFIG;
7101
009bc06e
AD		 7102 return 0;
7103}
7104
7105s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7106{
7107 struct igb_adapter *adapter = hw->back;
009bc06e 7108
23d028cc 7109 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7110 return -E1000_ERR_CONFIG;
7111
009bc06e
AD		 7112 return 0;
7113}
7114
c8f44aff 7115static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7116{
7117 struct igb_adapter *adapter = netdev_priv(netdev);
7118 struct e1000_hw *hw = &adapter->hw;
7119 u32 ctrl, rctl;
f646968f 7120 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7121
5faf030c 7122 if (enable) {
9d5c8243
AK		 7123 /* enable VLAN tag insert/strip */
7124 ctrl = rd32(E1000_CTRL);
7125 ctrl |= E1000_CTRL_VME;
7126 wr32(E1000_CTRL, ctrl);
7127
51466239 7128 /* Disable CFI check */
9d5c8243 7129 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7130 rctl &= ~E1000_RCTL_CFIEN;
7131 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7132 } else {
7133 /* disable VLAN tag insert/strip */
7134 ctrl = rd32(E1000_CTRL);
7135 ctrl &= ~E1000_CTRL_VME;
7136 wr32(E1000_CTRL, ctrl);
9d5c8243 7137 }
9d5c8243
AK		 7138}
7139
80d5c368
PM		 7140static int igb_vlan_rx_add_vid(struct net_device *netdev,
7141 __be16 proto, u16 vid)
9d5c8243
AK		 7142{
7143 struct igb_adapter *adapter = netdev_priv(netdev);
7144 struct e1000_hw *hw = &adapter->hw;
4ae196df 7145 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7146
51466239
AD		 7147 /* attempt to add filter to vlvf array */
7148 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7149
51466239
AD		 7150 /* add the filter since PF can receive vlans w/o entry in vlvf */
7151 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7152
7153 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7154
7155 return 0;
9d5c8243
AK		 7156}
7157
80d5c368
PM		 7158static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7159 __be16 proto, u16 vid)
9d5c8243
AK		 7160{
7161 struct igb_adapter *adapter = netdev_priv(netdev);
7162 struct e1000_hw *hw = &adapter->hw;
4ae196df 7163 int pf_id = adapter->vfs_allocated_count;
51466239 7164 s32 err;
9d5c8243 7165
51466239
AD		 7166 /* remove vlan from VLVF table array */
7167 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7168
51466239
AD		 7169 /* if vid was not present in VLVF just remove it from table */
7170 if (err)
4ae196df 7171 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7172
7173 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7174
7175 return 0;
9d5c8243
AK		 7176}
7177
7178static void igb_restore_vlan(struct igb_adapter *adapter)
7179{
5982a556 7180 u16 vid = 1;
9d5c8243 7181
5faf030c 7182 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
5982a556 7183 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
5faf030c 7184
5982a556 7185 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7186 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7187}
7188
14ad2513 7189int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7190{
090b1795 7191 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7192 struct e1000_mac_info *mac = &adapter->hw.mac;
7193
7194 mac->autoneg = 0;
7195
14ad2513 7196 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7197 * for the switch() below to work
7198 */
14ad2513
DD		 7199 if ((spd & 1) || (dplx & ~1))
7200 goto err_inval;
7201
f502ef7d
AA		 7202 /* Fiber NIC's only allow 1000 gbps Full duplex
7203 * and 100Mbps Full duplex for 100baseFx sfp
7204 */
7205 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7206 switch (spd + dplx) {
7207 case SPEED_10 + DUPLEX_HALF:
7208 case SPEED_10 + DUPLEX_FULL:
7209 case SPEED_100 + DUPLEX_HALF:
7210 goto err_inval;
7211 default:
7212 break;
7213 }
7214 }
cd2638a8 7215
14ad2513 7216 switch (spd + dplx) {
9d5c8243
AK		 7217 case SPEED_10 + DUPLEX_HALF:
7218 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7219 break;
7220 case SPEED_10 + DUPLEX_FULL:
7221 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7222 break;
7223 case SPEED_100 + DUPLEX_HALF:
7224 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7225 break;
7226 case SPEED_100 + DUPLEX_FULL:
7227 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7228 break;
7229 case SPEED_1000 + DUPLEX_FULL:
7230 mac->autoneg = 1;
7231 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7232 break;
7233 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7234 default:
14ad2513 7235 goto err_inval;
9d5c8243 7236 }
8376dad0
JB		 7237
7238 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7239 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7240
9d5c8243 7241 return 0;
14ad2513
DD		 7242
7243err_inval:
7244 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7245 return -EINVAL;
9d5c8243
AK		 7246}
7247
749ab2cd
YZ		 7248static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7249 bool runtime)
9d5c8243
AK		 7250{
7251 struct net_device *netdev = pci_get_drvdata(pdev);
7252 struct igb_adapter *adapter = netdev_priv(netdev);
7253 struct e1000_hw *hw = &adapter->hw;
2d064c06 7254 u32 ctrl, rctl, status;
749ab2cd 7255 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7256#ifdef CONFIG_PM
7257 int retval = 0;
7258#endif
7259
7260 netif_device_detach(netdev);
7261
a88f10ec 7262 if (netif_running(netdev))
749ab2cd 7263 __igb_close(netdev, true);
a88f10ec 7264
047e0030 7265 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7266
7267#ifdef CONFIG_PM
7268 retval = pci_save_state(pdev);
7269 if (retval)
7270 return retval;
7271#endif
7272
7273 status = rd32(E1000_STATUS);
7274 if (status & E1000_STATUS_LU)
7275 wufc &= ~E1000_WUFC_LNKC;
7276
7277 if (wufc) {
7278 igb_setup_rctl(adapter);
ff41f8dc 7279 igb_set_rx_mode(netdev);
9d5c8243
AK		 7280
7281 /* turn on all-multi mode if wake on multicast is enabled */
7282 if (wufc & E1000_WUFC_MC) {
7283 rctl = rd32(E1000_RCTL);
7284 rctl |= E1000_RCTL_MPE;
7285 wr32(E1000_RCTL, rctl);
7286 }
7287
7288 ctrl = rd32(E1000_CTRL);
7289 /* advertise wake from D3Cold */
7290 #define E1000_CTRL_ADVD3WUC 0x00100000
7291 /* phy power management enable */
7292 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7293 ctrl |= E1000_CTRL_ADVD3WUC;
7294 wr32(E1000_CTRL, ctrl);
7295
9d5c8243 7296 /* Allow time for pending master requests to run */
330a6d6a 7297 igb_disable_pcie_master(hw);
9d5c8243
AK		 7298
7299 wr32(E1000_WUC, E1000_WUC_PME_EN);
7300 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7301 } else {
7302 wr32(E1000_WUC, 0);
7303 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7304 }
7305
3fe7c4c9
RW		 7306 *enable_wake = wufc || adapter->en_mng_pt;
7307 if (!*enable_wake)
88a268c1
NN		 7308 igb_power_down_link(adapter);
7309 else
7310 igb_power_up_link(adapter);
9d5c8243
AK		 7311
7312 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7313 * would have already happened in close and is redundant.
7314 */
9d5c8243
AK		 7315 igb_release_hw_control(adapter);
7316
7317 pci_disable_device(pdev);
7318
9d5c8243
AK		 7319 return 0;
7320}
7321
7322#ifdef CONFIG_PM
d9dd966d 7323#ifdef CONFIG_PM_SLEEP
749ab2cd 7324static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7325{
7326 int retval;
7327 bool wake;
749ab2cd 7328 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7329
749ab2cd 7330 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7331 if (retval)
7332 return retval;
7333
7334 if (wake) {
7335 pci_prepare_to_sleep(pdev);
7336 } else {
7337 pci_wake_from_d3(pdev, false);
7338 pci_set_power_state(pdev, PCI_D3hot);
7339 }
7340
7341 return 0;
7342}
d9dd966d 7343#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7344
749ab2cd 7345static int igb_resume(struct device *dev)
9d5c8243 7346{
749ab2cd 7347 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7348 struct net_device *netdev = pci_get_drvdata(pdev);
7349 struct igb_adapter *adapter = netdev_priv(netdev);
7350 struct e1000_hw *hw = &adapter->hw;
7351 u32 err;
7352
7353 pci_set_power_state(pdev, PCI_D0);
7354 pci_restore_state(pdev);
b94f2d77 7355 pci_save_state(pdev);
42bfd33a 7356
17a402a0
CW		 7357 if (!pci_device_is_present(pdev))
7358 return -ENODEV;
aed5dec3 7359 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7360 if (err) {
7361 dev_err(&pdev->dev,
7362 "igb: Cannot enable PCI device from suspend\n");
7363 return err;
7364 }
7365 pci_set_master(pdev);
7366
7367 pci_enable_wake(pdev, PCI_D3hot, 0);
7368 pci_enable_wake(pdev, PCI_D3cold, 0);
7369
53c7d064 7370 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec 7371 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3eb14ea8 7372 rtnl_unlock();
a88f10ec 7373 return -ENOMEM;
9d5c8243
AK		 7374 }
7375
9d5c8243 7376 igb_reset(adapter);
a8564f03
AD		 7377
7378 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7379 * driver.
7380 */
a8564f03
AD		 7381 igb_get_hw_control(adapter);
7382
9d5c8243
AK		 7383 wr32(E1000_WUS, ~0);
7384
749ab2cd 7385 if (netdev->flags & IFF_UP) {
0c2cc02e 7386 rtnl_lock();
749ab2cd 7387 err = __igb_open(netdev, true);
0c2cc02e 7388 rtnl_unlock();
a88f10ec
AD		 7389 if (err)
7390 return err;
7391 }
9d5c8243
AK		 7392
7393 netif_device_attach(netdev);
749ab2cd
YZ		 7394 return 0;
7395}
7396
749ab2cd
YZ		 7397static int igb_runtime_idle(struct device *dev)
7398{
7399 struct pci_dev *pdev = to_pci_dev(dev);
7400 struct net_device *netdev = pci_get_drvdata(pdev);
7401 struct igb_adapter *adapter = netdev_priv(netdev);
7402
7403 if (!igb_has_link(adapter))
7404 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7405
7406 return -EBUSY;
7407}
7408
7409static int igb_runtime_suspend(struct device *dev)
7410{
7411 struct pci_dev *pdev = to_pci_dev(dev);
7412 int retval;
7413 bool wake;
7414
7415 retval = __igb_shutdown(pdev, &wake, 1);
7416 if (retval)
7417 return retval;
7418
7419 if (wake) {
7420 pci_prepare_to_sleep(pdev);
7421 } else {
7422 pci_wake_from_d3(pdev, false);
7423 pci_set_power_state(pdev, PCI_D3hot);
7424 }
9d5c8243 7425
9d5c8243
AK		 7426 return 0;
7427}
749ab2cd
YZ		 7428
7429static int igb_runtime_resume(struct device *dev)
7430{
7431 return igb_resume(dev);
7432}
d61c81cb 7433#endif /* CONFIG_PM */
9d5c8243
AK		 7434
7435static void igb_shutdown(struct pci_dev *pdev)
7436{
3fe7c4c9
RW		 7437 bool wake;
7438
749ab2cd 7439 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7440
7441 if (system_state == SYSTEM_POWER_OFF) {
7442 pci_wake_from_d3(pdev, wake);
7443 pci_set_power_state(pdev, PCI_D3hot);
7444 }
9d5c8243
AK		 7445}
7446
fa44f2f1
GR		 7447#ifdef CONFIG_PCI_IOV
7448static int igb_sriov_reinit(struct pci_dev *dev)
7449{
7450 struct net_device *netdev = pci_get_drvdata(dev);
7451 struct igb_adapter *adapter = netdev_priv(netdev);
7452 struct pci_dev *pdev = adapter->pdev;
7453
7454 rtnl_lock();
7455
7456 if (netif_running(netdev))
7457 igb_close(netdev);
76252723
SA		 7458 else
7459 igb_reset(adapter);
fa44f2f1
GR		 7460
7461 igb_clear_interrupt_scheme(adapter);
7462
7463 igb_init_queue_configuration(adapter);
7464
7465 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7466 rtnl_unlock();
fa44f2f1
GR		 7467 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7468 return -ENOMEM;
7469 }
7470
7471 if (netif_running(netdev))
7472 igb_open(netdev);
7473
7474 rtnl_unlock();
7475
7476 return 0;
7477}
7478
7479static int igb_pci_disable_sriov(struct pci_dev *dev)
7480{
7481 int err = igb_disable_sriov(dev);
7482
7483 if (!err)
7484 err = igb_sriov_reinit(dev);
7485
7486 return err;
7487}
7488
7489static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7490{
7491 int err = igb_enable_sriov(dev, num_vfs);
7492
7493 if (err)
7494 goto out;
7495
7496 err = igb_sriov_reinit(dev);
7497 if (!err)
7498 return num_vfs;
7499
7500out:
7501 return err;
7502}
7503
7504#endif
7505static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7506{
7507#ifdef CONFIG_PCI_IOV
7508 if (num_vfs == 0)
7509 return igb_pci_disable_sriov(dev);
7510 else
7511 return igb_pci_enable_sriov(dev, num_vfs);
7512#endif
7513 return 0;
7514}
7515
9d5c8243 7516#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7517/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7518 * without having to re-enable interrupts. It's not called while
7519 * the interrupt routine is executing.
7520 */
7521static void igb_netpoll(struct net_device *netdev)
7522{
7523 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7524 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7525 struct igb_q_vector *q_vector;
9d5c8243 7526 int i;
9d5c8243 7527
047e0030 7528 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7529 q_vector = adapter->q_vector[i];
cd14ef54 7530 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7531 wr32(E1000_EIMC, q_vector->eims_value);
7532 else
7533 igb_irq_disable(adapter);
047e0030 7534 napi_schedule(&q_vector->napi);
eebbbdba 7535 }
9d5c8243
AK		 7536}
7537#endif /* CONFIG_NET_POLL_CONTROLLER */
7538
7539/**
b980ac18
JK		 7540 * igb_io_error_detected - called when PCI error is detected
7541 * @pdev: Pointer to PCI device
7542 * @state: The current pci connection state
9d5c8243 7543 *
b980ac18
JK		 7544 * This function is called after a PCI bus error affecting
7545 * this device has been detected.
7546 **/
9d5c8243
AK		 7547static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7548 pci_channel_state_t state)
7549{
7550 struct net_device *netdev = pci_get_drvdata(pdev);
7551 struct igb_adapter *adapter = netdev_priv(netdev);
7552
7553 netif_device_detach(netdev);
7554
59ed6eec
AD		 7555 if (state == pci_channel_io_perm_failure)
7556 return PCI_ERS_RESULT_DISCONNECT;
7557
9d5c8243
AK		 7558 if (netif_running(netdev))
7559 igb_down(adapter);
7560 pci_disable_device(pdev);
7561
7562 /* Request a slot slot reset. */
7563 return PCI_ERS_RESULT_NEED_RESET;
7564}
7565
7566/**
b980ac18
JK		 7567 * igb_io_slot_reset - called after the pci bus has been reset.
7568 * @pdev: Pointer to PCI device
9d5c8243 7569 *
b980ac18
JK		 7570 * Restart the card from scratch, as if from a cold-boot. Implementation
7571 * resembles the first-half of the igb_resume routine.
7572 **/
9d5c8243
AK		 7573static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7574{
7575 struct net_device *netdev = pci_get_drvdata(pdev);
7576 struct igb_adapter *adapter = netdev_priv(netdev);
7577 struct e1000_hw *hw = &adapter->hw;
40a914fa 7578 pci_ers_result_t result;
42bfd33a 7579 int err;
9d5c8243 7580
aed5dec3 7581 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7582 dev_err(&pdev->dev,
7583 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7584 result = PCI_ERS_RESULT_DISCONNECT;
7585 } else {
7586 pci_set_master(pdev);
7587 pci_restore_state(pdev);
b94f2d77 7588 pci_save_state(pdev);
9d5c8243 7589
40a914fa
AD		 7590 pci_enable_wake(pdev, PCI_D3hot, 0);
7591 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7592
40a914fa
AD		 7593 igb_reset(adapter);
7594 wr32(E1000_WUS, ~0);
7595 result = PCI_ERS_RESULT_RECOVERED;
7596 }
9d5c8243 7597
ea943d41
JK		 7598 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7599 if (err) {
b980ac18
JK		 7600 dev_err(&pdev->dev,
7601 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7602 err);
ea943d41
JK		 7603 /* non-fatal, continue */
7604 }
40a914fa
AD		 7605
7606 return result;
9d5c8243
AK		 7607}
7608
7609/**
b980ac18
JK		 7610 * igb_io_resume - called when traffic can start flowing again.
7611 * @pdev: Pointer to PCI device
9d5c8243 7612 *
b980ac18
JK		 7613 * This callback is called when the error recovery driver tells us that
7614 * its OK to resume normal operation. Implementation resembles the
7615 * second-half of the igb_resume routine.
9d5c8243
AK		 7616 */
7617static void igb_io_resume(struct pci_dev *pdev)
7618{
7619 struct net_device *netdev = pci_get_drvdata(pdev);
7620 struct igb_adapter *adapter = netdev_priv(netdev);
7621
9d5c8243
AK		 7622 if (netif_running(netdev)) {
7623 if (igb_up(adapter)) {
7624 dev_err(&pdev->dev, "igb_up failed after reset\n");
7625 return;
7626 }
7627 }
7628
7629 netif_device_attach(netdev);
7630
7631 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7632 * driver.
7633 */
9d5c8243 7634 igb_get_hw_control(adapter);
9d5c8243
AK		 7635}
7636
26ad9178 7637static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7638 u8 qsel)
26ad9178 7639{
26ad9178 7640 struct e1000_hw *hw = &adapter->hw;
c3278587 7641 u32 rar_low, rar_high;
26ad9178
AD		 7642
7643 /* HW expects these in little endian so we reverse the byte order
c3278587 7644 * from network order (big endian) to CPU endian
26ad9178 7645 */
c3278587
AD		 7646 rar_low = le32_to_cpup((__be32 *)(addr));
7647 rar_high = le16_to_cpup((__be16 *)(addr + 4));
26ad9178
AD		 7648
7649 /* Indicate to hardware the Address is Valid. */
7650 rar_high |= E1000_RAH_AV;
7651
7652 if (hw->mac.type == e1000_82575)
7653 rar_high |= E1000_RAH_POOL_1 * qsel;
7654 else
7655 rar_high |= E1000_RAH_POOL_1 << qsel;
7656
7657 wr32(E1000_RAL(index), rar_low);
7658 wrfl();
7659 wr32(E1000_RAH(index), rar_high);
7660 wrfl();
7661}
7662
4ae196df 7663static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7664 int vf, unsigned char *mac_addr)
4ae196df
AD		 7665{
7666 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7667 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7668 * towards the first, as a result a collision should not be possible
7669 */
ff41f8dc 7670 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7671
37680117 7672 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7673
26ad9178 7674 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7675
7676 return 0;
7677}
7678
8151d294
WM		 7679static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7680{
7681 struct igb_adapter *adapter = netdev_priv(netdev);
7682 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7683 return -EINVAL;
7684 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7685 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7686 dev_info(&adapter->pdev->dev,
7687 "Reload the VF driver to make this change effective.");
8151d294 7688 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7689 dev_warn(&adapter->pdev->dev,
7690 "The VF MAC address has been set, but the PF device is not up.\n");
7691 dev_warn(&adapter->pdev->dev,
7692 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7693 }
7694 return igb_set_vf_mac(adapter, vf, mac);
7695}
7696
17dc566c
LL		 7697static int igb_link_mbps(int internal_link_speed)
7698{
7699 switch (internal_link_speed) {
7700 case SPEED_100:
7701 return 100;
7702 case SPEED_1000:
7703 return 1000;
7704 default:
7705 return 0;
7706 }
7707}
7708
7709static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7710 int link_speed)
7711{
7712 int rf_dec, rf_int;
7713 u32 bcnrc_val;
7714
7715 if (tx_rate != 0) {
7716 /* Calculate the rate factor values to set */
7717 rf_int = link_speed / tx_rate;
7718 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7719 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7720 tx_rate;
17dc566c
LL		 7721
7722 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7723 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7724 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7725 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7726 } else {
7727 bcnrc_val = 0;
7728 }
7729
7730 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7731 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7732 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7733 */
7734 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7735 wr32(E1000_RTTBCNRC, bcnrc_val);
7736}
7737
7738static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7739{
7740 int actual_link_speed, i;
7741 bool reset_rate = false;
7742
7743 /* VF TX rate limit was not set or not supported */
7744 if ((adapter->vf_rate_link_speed == 0) ||
7745 (adapter->hw.mac.type != e1000_82576))
7746 return;
7747
7748 actual_link_speed = igb_link_mbps(adapter->link_speed);
7749 if (actual_link_speed != adapter->vf_rate_link_speed) {
7750 reset_rate = true;
7751 adapter->vf_rate_link_speed = 0;
7752 dev_info(&adapter->pdev->dev,
b980ac18 7753 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7754 }
7755
7756 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7757 if (reset_rate)
7758 adapter->vf_data[i].tx_rate = 0;
7759
7760 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7761 adapter->vf_data[i].tx_rate,
7762 actual_link_speed);
17dc566c
LL		 7763 }
7764}
7765
ed616689
SC		 7766static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7767 int min_tx_rate, int max_tx_rate)
8151d294 7768{
17dc566c
LL		 7769 struct igb_adapter *adapter = netdev_priv(netdev);
7770 struct e1000_hw *hw = &adapter->hw;
7771 int actual_link_speed;
7772
7773 if (hw->mac.type != e1000_82576)
7774 return -EOPNOTSUPP;
7775
ed616689
SC		 7776 if (min_tx_rate)
7777 return -EINVAL;
7778
17dc566c
LL		 7779 actual_link_speed = igb_link_mbps(adapter->link_speed);
7780 if ((vf >= adapter->vfs_allocated_count) ||
7781 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7782 (max_tx_rate < 0) ||
7783 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7784 return -EINVAL;
7785
7786 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7787 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7788 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7789
7790 return 0;
8151d294
WM		 7791}
7792
70ea4783
LL		 7793static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7794 bool setting)
7795{
7796 struct igb_adapter *adapter = netdev_priv(netdev);
7797 struct e1000_hw *hw = &adapter->hw;
7798 u32 reg_val, reg_offset;
7799
7800 if (!adapter->vfs_allocated_count)
7801 return -EOPNOTSUPP;
7802
7803 if (vf >= adapter->vfs_allocated_count)
7804 return -EINVAL;
7805
7806 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7807 reg_val = rd32(reg_offset);
7808 if (setting)
7809 reg_val |= ((1 << vf) |
7810 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7811 else
7812 reg_val &= ~((1 << vf) |
7813 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7814 wr32(reg_offset, reg_val);
7815
7816 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7817 return 0;
70ea4783
LL		 7818}
7819
8151d294
WM		 7820static int igb_ndo_get_vf_config(struct net_device *netdev,
7821 int vf, struct ifla_vf_info *ivi)
7822{
7823 struct igb_adapter *adapter = netdev_priv(netdev);
7824 if (vf >= adapter->vfs_allocated_count)
7825 return -EINVAL;
7826 ivi->vf = vf;
7827 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7828 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7829 ivi->min_tx_rate = 0;
8151d294
WM		 7830 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7831 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7832 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7833 return 0;
7834}
7835
4ae196df
AD		 7836static void igb_vmm_control(struct igb_adapter *adapter)
7837{
7838 struct e1000_hw *hw = &adapter->hw;
10d8e907 7839 u32 reg;
4ae196df 7840
52a1dd4d
AD		 7841 switch (hw->mac.type) {
7842 case e1000_82575:
f96a8a0b
CW		 7843 case e1000_i210:
7844 case e1000_i211:
ceb5f13b 7845 case e1000_i354:
52a1dd4d
AD		 7846 default:
7847 /* replication is not supported for 82575 */
4ae196df 7848 return;
52a1dd4d
AD		 7849 case e1000_82576:
7850 /* notify HW that the MAC is adding vlan tags */
7851 reg = rd32(E1000_DTXCTL);
7852 reg |= E1000_DTXCTL_VLAN_ADDED;
7853 wr32(E1000_DTXCTL, reg);
b26141d4 7854 /* Fall through */
52a1dd4d
AD		 7855 case e1000_82580:
7856 /* enable replication vlan tag stripping */
7857 reg = rd32(E1000_RPLOLR);
7858 reg |= E1000_RPLOLR_STRVLAN;
7859 wr32(E1000_RPLOLR, reg);
b26141d4 7860 /* Fall through */
d2ba2ed8
AD		 7861 case e1000_i350:
7862 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7863 break;
7864 }
10d8e907 7865
d4960307
AD		 7866 if (adapter->vfs_allocated_count) {
7867 igb_vmdq_set_loopback_pf(hw, true);
7868 igb_vmdq_set_replication_pf(hw, true);
13800469 7869 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7870 adapter->vfs_allocated_count);
d4960307
AD		 7871 } else {
7872 igb_vmdq_set_loopback_pf(hw, false);
7873 igb_vmdq_set_replication_pf(hw, false);
7874 }
4ae196df
AD		 7875}
7876
b6e0c419
CW		 7877static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7878{
7879 struct e1000_hw *hw = &adapter->hw;
7880 u32 dmac_thr;
7881 u16 hwm;
7882
7883 if (hw->mac.type > e1000_82580) {
7884 if (adapter->flags & IGB_FLAG_DMAC) {
7885 u32 reg;
7886
7887 /* force threshold to 0. */
7888 wr32(E1000_DMCTXTH, 0);
7889
b980ac18 7890 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7891 * than the Rx threshold. Set hwm to PBA - max frame
7892 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7893 */
45693bcb 7894 hwm = 64 * (pba - 6);
e8c626e9
MV		 7895 reg = rd32(E1000_FCRTC);
7896 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7897 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7898 & E1000_FCRTC_RTH_COAL_MASK);
7899 wr32(E1000_FCRTC, reg);
7900
b980ac18 7901 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7902 * frame size, capping it at PBA - 10KB.
7903 */
45693bcb 7904 dmac_thr = pba - 10;
b6e0c419
CW		 7905 reg = rd32(E1000_DMACR);
7906 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7907 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7908 & E1000_DMACR_DMACTHR_MASK);
7909
7910 /* transition to L0x or L1 if available..*/
7911 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7912
7913 /* watchdog timer= +-1000 usec in 32usec intervals */
7914 reg |= (1000 >> 5);
0c02dd98
MV		 7915
7916 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7917 if (hw->mac.type != e1000_i354)
7918 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7919
b6e0c419
CW		 7920 wr32(E1000_DMACR, reg);
7921
b980ac18 7922 /* no lower threshold to disable
b6e0c419
CW		 7923 * coalescing(smart fifb)-UTRESH=0
7924 */
7925 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7926
7927 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7928
7929 wr32(E1000_DMCTLX, reg);
7930
b980ac18 7931 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7932 * DMA coal
7933 */
7934 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7935 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7936
b980ac18 7937 /* make low power state decision controlled
b6e0c419
CW		 7938 * by DMA coal
7939 */
7940 reg = rd32(E1000_PCIEMISC);
7941 reg &= ~E1000_PCIEMISC_LX_DECISION;
7942 wr32(E1000_PCIEMISC, reg);
7943 } /* endif adapter->dmac is not disabled */
7944 } else if (hw->mac.type == e1000_82580) {
7945 u32 reg = rd32(E1000_PCIEMISC);
9005df38 7946
b6e0c419
CW		 7947 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7948 wr32(E1000_DMACR, 0);
7949 }
7950}
7951
b980ac18
JK		 7952/**
7953 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7954 * @hw: pointer to hardware structure
7955 * @byte_offset: byte offset to read
7956 * @dev_addr: device address
7957 * @data: value read
7958 *
7959 * Performs byte read operation over I2C interface at
7960 * a specified device address.
b980ac18 7961 **/
441fc6fd 7962s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7963 u8 dev_addr, u8 *data)
441fc6fd
CW		 7964{
7965 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7966 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7967 s32 status;
7968 u16 swfw_mask = 0;
7969
7970 if (!this_client)
7971 return E1000_ERR_I2C;
7972
7973 swfw_mask = E1000_SWFW_PHY0_SM;
7974
23d87824 7975 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 7976 return E1000_ERR_SWFW_SYNC;
7977
7978 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7979 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7980
7981 if (status < 0)
7982 return E1000_ERR_I2C;
7983 else {
7984 *data = status;
23d87824 7985 return 0;
441fc6fd
CW		 7986 }
7987}
7988
b980ac18
JK		 7989/**
7990 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7991 * @hw: pointer to hardware structure
7992 * @byte_offset: byte offset to write
7993 * @dev_addr: device address
7994 * @data: value to write
7995 *
7996 * Performs byte write operation over I2C interface at
7997 * a specified device address.
b980ac18 7998 **/
441fc6fd 7999s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8000 u8 dev_addr, u8 data)
441fc6fd
CW		 8001{
8002 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8003 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8004 s32 status;
8005 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8006
8007 if (!this_client)
8008 return E1000_ERR_I2C;
8009
23d87824 8010 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8011 return E1000_ERR_SWFW_SYNC;
8012 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8013 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8014
8015 if (status)
8016 return E1000_ERR_I2C;
8017 else
23d87824 8018 return 0;
441fc6fd
CW		 8019
8020}
907b7835
LMV		 8021
8022int igb_reinit_queues(struct igb_adapter *adapter)
8023{
8024 struct net_device *netdev = adapter->netdev;
8025 struct pci_dev *pdev = adapter->pdev;
8026 int err = 0;
8027
8028 if (netif_running(netdev))
8029 igb_close(netdev);
8030
02ef6e1d 8031 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8032
8033 if (igb_init_interrupt_scheme(adapter, true)) {
8034 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8035 return -ENOMEM;
8036 }
8037
8038 if (netif_running(netdev))
8039 err = igb_open(netdev);
8040
8041 return err;
8042}
9d5c8243 8043/* igb_main.c */
Linux kernel - Deliverables
This page took 1.670332 seconds and 5 git commands to generate.