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ixgbe: Focus config of head, tail ntc, and ntu all into a single function
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
66f40b8a 65#define BUILD 5
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 126static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 128static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
53c7d064 132static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 139static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
cd392f5c 143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
68d480c4 148static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
047e0030 152static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 153#ifdef CONFIG_IGB_DCA
047e0030 154static void igb_update_dca(struct igb_q_vector *);
fe4506b6 155static void igb_setup_dca(struct igb_adapter *);
421e02f0 156#endif /* CONFIG_IGB_DCA */
661086df 157static int igb_poll(struct napi_struct *, int);
13fde97a 158static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
c8f44aff 163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 166static void igb_restore_vlan(struct igb_adapter *);
26ad9178 167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
4ae196df 170static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
8151d294
WM		 179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
17dc566c 181static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 185static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 186#endif
9d5c8243 187
9d5c8243 188#ifdef CONFIG_PM
d9dd966d 189#ifdef CONFIG_PM_SLEEP
749ab2cd 190static int igb_suspend(struct device *);
d9dd966d 191#endif
749ab2cd
YZ		 192static int igb_resume(struct device *);
193#ifdef CONFIG_PM_RUNTIME
194static int igb_runtime_suspend(struct device *dev);
195static int igb_runtime_resume(struct device *dev);
196static int igb_runtime_idle(struct device *dev);
197#endif
198static const struct dev_pm_ops igb_pm_ops = {
199 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
200 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
201 igb_runtime_idle)
202};
9d5c8243
AK		 203#endif
204static void igb_shutdown(struct pci_dev *);
fa44f2f1 205static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
208static struct notifier_block dca_notifier = {
209 .notifier_call = igb_notify_dca,
210 .next = NULL,
211 .priority = 0
212};
213#endif
9d5c8243
AK		 214#ifdef CONFIG_NET_POLL_CONTROLLER
215/* for netdump / net console */
216static void igb_netpoll(struct net_device *);
217#endif
37680117 218#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 219static unsigned int max_vfs = 0;
220module_param(max_vfs, uint, 0);
221MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
222 "per physical function");
223#endif /* CONFIG_PCI_IOV */
224
9d5c8243
AK		 225static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
226 pci_channel_state_t);
227static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
228static void igb_io_resume(struct pci_dev *);
229
3646f0e5 230static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 231 .error_detected = igb_io_error_detected,
232 .slot_reset = igb_io_slot_reset,
233 .resume = igb_io_resume,
234};
235
b6e0c419 236static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 237
238static struct pci_driver igb_driver = {
239 .name = igb_driver_name,
240 .id_table = igb_pci_tbl,
241 .probe = igb_probe,
9f9a12f8 242 .remove = igb_remove,
9d5c8243 243#ifdef CONFIG_PM
749ab2cd 244 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 245#endif
246 .shutdown = igb_shutdown,
fa44f2f1 247 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 248 .err_handler = &igb_err_handler
249};
250
251MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
252MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
253MODULE_LICENSE("GPL");
254MODULE_VERSION(DRV_VERSION);
255
b3f4d599 256#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
257static int debug = -1;
258module_param(debug, int, 0);
259MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
260
c97ec42a
TI		 261struct igb_reg_info {
262 u32 ofs;
263 char *name;
264};
265
266static const struct igb_reg_info igb_reg_info_tbl[] = {
267
268 /* General Registers */
269 {E1000_CTRL, "CTRL"},
270 {E1000_STATUS, "STATUS"},
271 {E1000_CTRL_EXT, "CTRL_EXT"},
272
273 /* Interrupt Registers */
274 {E1000_ICR, "ICR"},
275
276 /* RX Registers */
277 {E1000_RCTL, "RCTL"},
278 {E1000_RDLEN(0), "RDLEN"},
279 {E1000_RDH(0), "RDH"},
280 {E1000_RDT(0), "RDT"},
281 {E1000_RXDCTL(0), "RXDCTL"},
282 {E1000_RDBAL(0), "RDBAL"},
283 {E1000_RDBAH(0), "RDBAH"},
284
285 /* TX Registers */
286 {E1000_TCTL, "TCTL"},
287 {E1000_TDBAL(0), "TDBAL"},
288 {E1000_TDBAH(0), "TDBAH"},
289 {E1000_TDLEN(0), "TDLEN"},
290 {E1000_TDH(0), "TDH"},
291 {E1000_TDT(0), "TDT"},
292 {E1000_TXDCTL(0), "TXDCTL"},
293 {E1000_TDFH, "TDFH"},
294 {E1000_TDFT, "TDFT"},
295 {E1000_TDFHS, "TDFHS"},
296 {E1000_TDFPC, "TDFPC"},
297
298 /* List Terminator */
299 {}
300};
301
b980ac18 302/* igb_regdump - register printout routine */
c97ec42a
TI		 303static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
304{
305 int n = 0;
306 char rname[16];
307 u32 regs[8];
308
309 switch (reginfo->ofs) {
310 case E1000_RDLEN(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDLEN(n));
313 break;
314 case E1000_RDH(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDH(n));
317 break;
318 case E1000_RDT(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RDT(n));
321 break;
322 case E1000_RXDCTL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RXDCTL(n));
325 break;
326 case E1000_RDBAL(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAL(n));
329 break;
330 case E1000_RDBAH(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAH(n));
333 break;
334 case E1000_TDBAL(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_RDBAL(n));
337 break;
338 case E1000_TDBAH(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDBAH(n));
341 break;
342 case E1000_TDLEN(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDLEN(n));
345 break;
346 case E1000_TDH(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDH(n));
349 break;
350 case E1000_TDT(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TDT(n));
353 break;
354 case E1000_TXDCTL(0):
355 for (n = 0; n < 4; n++)
356 regs[n] = rd32(E1000_TXDCTL(n));
357 break;
358 default:
876d2d6f 359 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 360 return;
361 }
362
363 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 364 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
365 regs[2], regs[3]);
c97ec42a
TI		 366}
367
b980ac18 368/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 369static void igb_dump(struct igb_adapter *adapter)
370{
371 struct net_device *netdev = adapter->netdev;
372 struct e1000_hw *hw = &adapter->hw;
373 struct igb_reg_info *reginfo;
c97ec42a
TI		 374 struct igb_ring *tx_ring;
375 union e1000_adv_tx_desc *tx_desc;
376 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 377 struct igb_ring *rx_ring;
378 union e1000_adv_rx_desc *rx_desc;
379 u32 staterr;
6ad4edfc 380 u16 i, n;
c97ec42a
TI		 381
382 if (!netif_msg_hw(adapter))
383 return;
384
385 /* Print netdevice Info */
386 if (netdev) {
387 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 388 pr_info("Device Name state trans_start "
389 "last_rx\n");
390 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
391 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 392 }
393
394 /* Print Registers */
395 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 396 pr_info(" Register Name Value\n");
c97ec42a
TI		 397 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
398 reginfo->name; reginfo++) {
399 igb_regdump(hw, reginfo);
400 }
401
402 /* Print TX Ring Summary */
403 if (!netdev || !netif_running(netdev))
404 goto exit;
405
406 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 407 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 408 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 409 struct igb_tx_buffer *buffer_info;
c97ec42a 410 tx_ring = adapter->tx_ring[n];
06034649 411 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 412 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
413 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 414 (u64)dma_unmap_addr(buffer_info, dma),
415 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 416 buffer_info->next_to_watch,
417 (u64)buffer_info->time_stamp);
c97ec42a
TI		 418 }
419
420 /* Print TX Rings */
421 if (!netif_msg_tx_done(adapter))
422 goto rx_ring_summary;
423
424 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
425
426 /* Transmit Descriptor Formats
427 *
428 * Advanced Transmit Descriptor
429 * +--------------------------------------------------------------+
430 * 0 | Buffer Address [63:0] |
431 * +--------------------------------------------------------------+
432 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
433 * +--------------------------------------------------------------+
434 * 63 46 45 40 39 38 36 35 32 31 24 15 0
435 */
436
437 for (n = 0; n < adapter->num_tx_queues; n++) {
438 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 439 pr_info("------------------------------------\n");
440 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
441 pr_info("------------------------------------\n");
442 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
443 "[bi->dma ] leng ntw timestamp "
444 "bi->skb\n");
c97ec42a
TI		 445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 447 const char *next_desc;
06034649 448 struct igb_tx_buffer *buffer_info;
60136906 449 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 450 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 451 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 452 if (i == tx_ring->next_to_use &&
453 i == tx_ring->next_to_clean)
454 next_desc = " NTC/U";
455 else if (i == tx_ring->next_to_use)
456 next_desc = " NTU";
457 else if (i == tx_ring->next_to_clean)
458 next_desc = " NTC";
459 else
460 next_desc = "";
461
462 pr_info("T [0x%03X] %016llX %016llX %016llX"
463 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 464 le64_to_cpu(u0->a),
465 le64_to_cpu(u0->b),
c9f14bf3
AD		 466 (u64)dma_unmap_addr(buffer_info, dma),
467 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 468 buffer_info->next_to_watch,
469 (u64)buffer_info->time_stamp,
876d2d6f 470 buffer_info->skb, next_desc);
c97ec42a 471
b669588a 472 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 473 print_hex_dump(KERN_INFO, "",
474 DUMP_PREFIX_ADDRESS,
b669588a 475 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 476 dma_unmap_len(buffer_info, len),
477 true);
c97ec42a
TI		 478 }
479 }
480
481 /* Print RX Rings Summary */
482rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 484 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 487 pr_info(" %5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
497 /* Advanced Receive Descriptor (Read) Format
498 * 63 1 0
499 * +-----------------------------------------------------+
500 * 0 | Packet Buffer Address [63:1] |A0/NSE|
501 * +----------------------------------------------+------+
502 * 8 | Header Buffer Address [63:1] | DD |
503 * +-----------------------------------------------------+
504 *
505 *
506 * Advanced Receive Descriptor (Write-Back) Format
507 *
508 * 63 48 47 32 31 30 21 20 17 16 4 3 0
509 * +------------------------------------------------------+
510 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
511 * | Checksum Ident | | | | Type | Type |
512 * +------------------------------------------------------+
513 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
514 * +------------------------------------------------------+
515 * 63 48 47 32 31 20 19 0
516 */
517
518 for (n = 0; n < adapter->num_rx_queues; n++) {
519 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 520 pr_info("------------------------------------\n");
521 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
522 pr_info("------------------------------------\n");
523 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
524 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
525 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
526 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 527
528 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 529 const char *next_desc;
06034649
AD		 530 struct igb_rx_buffer *buffer_info;
531 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 532 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 533 u0 = (struct my_u0 *)rx_desc;
534 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 535
536 if (i == rx_ring->next_to_use)
537 next_desc = " NTU";
538 else if (i == rx_ring->next_to_clean)
539 next_desc = " NTC";
540 else
541 next_desc = "";
542
c97ec42a
TI		 543 if (staterr & E1000_RXD_STAT_DD) {
544 /* Descriptor Done */
1a1c225b
AD		 545 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
546 "RWB", i,
c97ec42a
TI		 547 le64_to_cpu(u0->a),
548 le64_to_cpu(u0->b),
1a1c225b 549 next_desc);
c97ec42a 550 } else {
1a1c225b
AD		 551 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
552 "R ", i,
c97ec42a
TI		 553 le64_to_cpu(u0->a),
554 le64_to_cpu(u0->b),
555 (u64)buffer_info->dma,
1a1c225b 556 next_desc);
c97ec42a 557
b669588a 558 if (netif_msg_pktdata(adapter) &&
1a1c225b 559 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 560 print_hex_dump(KERN_INFO, "",
561 DUMP_PREFIX_ADDRESS,
562 16, 1,
b669588a
ET		 563 page_address(buffer_info->page) +
564 buffer_info->page_offset,
de78d1f9 565 IGB_RX_BUFSZ, true);
c97ec42a
TI		 566 }
567 }
c97ec42a
TI		 568 }
569 }
570
571exit:
572 return;
573}
574
b980ac18
JK		 575/**
576 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 577 * @hw: pointer to hardware structure
578 * @i2cctl: Current value of I2CCTL register
579 *
580 * Returns the I2C data bit value
b980ac18 581 **/
441fc6fd
CW		 582static int igb_get_i2c_data(void *data)
583{
584 struct igb_adapter *adapter = (struct igb_adapter *)data;
585 struct e1000_hw *hw = &adapter->hw;
586 s32 i2cctl = rd32(E1000_I2CPARAMS);
587
588 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
589}
590
b980ac18
JK		 591/**
592 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 593 * @data: pointer to hardware structure
594 * @state: I2C data value (0 or 1) to set
595 *
596 * Sets the I2C data bit
b980ac18 597 **/
441fc6fd
CW		 598static void igb_set_i2c_data(void *data, int state)
599{
600 struct igb_adapter *adapter = (struct igb_adapter *)data;
601 struct e1000_hw *hw = &adapter->hw;
602 s32 i2cctl = rd32(E1000_I2CPARAMS);
603
604 if (state)
605 i2cctl |= E1000_I2C_DATA_OUT;
606 else
607 i2cctl &= ~E1000_I2C_DATA_OUT;
608
609 i2cctl &= ~E1000_I2C_DATA_OE_N;
610 i2cctl |= E1000_I2C_CLK_OE_N;
611 wr32(E1000_I2CPARAMS, i2cctl);
612 wrfl();
613
614}
615
b980ac18
JK		 616/**
617 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 618 * @data: pointer to hardware structure
619 * @state: state to set clock
620 *
621 * Sets the I2C clock line to state
b980ac18 622 **/
441fc6fd
CW		 623static void igb_set_i2c_clk(void *data, int state)
624{
625 struct igb_adapter *adapter = (struct igb_adapter *)data;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 i2cctl = rd32(E1000_I2CPARAMS);
628
629 if (state) {
630 i2cctl |= E1000_I2C_CLK_OUT;
631 i2cctl &= ~E1000_I2C_CLK_OE_N;
632 } else {
633 i2cctl &= ~E1000_I2C_CLK_OUT;
634 i2cctl &= ~E1000_I2C_CLK_OE_N;
635 }
636 wr32(E1000_I2CPARAMS, i2cctl);
637 wrfl();
638}
639
b980ac18
JK		 640/**
641 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 642 * @data: pointer to hardware structure
643 *
644 * Gets the I2C clock state
b980ac18 645 **/
441fc6fd
CW		 646static int igb_get_i2c_clk(void *data)
647{
648 struct igb_adapter *adapter = (struct igb_adapter *)data;
649 struct e1000_hw *hw = &adapter->hw;
650 s32 i2cctl = rd32(E1000_I2CPARAMS);
651
652 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
653}
654
655static const struct i2c_algo_bit_data igb_i2c_algo = {
656 .setsda = igb_set_i2c_data,
657 .setscl = igb_set_i2c_clk,
658 .getsda = igb_get_i2c_data,
659 .getscl = igb_get_i2c_clk,
660 .udelay = 5,
661 .timeout = 20,
662};
663
9d5c8243 664/**
b980ac18
JK		 665 * igb_get_hw_dev - return device
666 * @hw: pointer to hardware structure
667 *
668 * used by hardware layer to print debugging information
9d5c8243 669 **/
c041076a 670struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 671{
672 struct igb_adapter *adapter = hw->back;
c041076a 673 return adapter->netdev;
9d5c8243 674}
38c845c7 675
9d5c8243 676/**
b980ac18 677 * igb_init_module - Driver Registration Routine
9d5c8243 678 *
b980ac18
JK		 679 * igb_init_module is the first routine called when the driver is
680 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 681 **/
682static int __init igb_init_module(void)
683{
684 int ret;
876d2d6f 685 pr_info("%s - version %s\n",
9d5c8243
AK		 686 igb_driver_string, igb_driver_version);
687
876d2d6f 688 pr_info("%s\n", igb_copyright);
9d5c8243 689
421e02f0 690#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 691 dca_register_notify(&dca_notifier);
692#endif
bbd98fe4 693 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 694 return ret;
695}
696
697module_init(igb_init_module);
698
699/**
b980ac18 700 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 701 *
b980ac18
JK		 702 * igb_exit_module is called just before the driver is removed
703 * from memory.
9d5c8243
AK		 704 **/
705static void __exit igb_exit_module(void)
706{
421e02f0 707#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 708 dca_unregister_notify(&dca_notifier);
709#endif
9d5c8243
AK		 710 pci_unregister_driver(&igb_driver);
711}
712
713module_exit(igb_exit_module);
714
26bc19ec
AD		 715#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
716/**
b980ac18
JK		 717 * igb_cache_ring_register - Descriptor ring to register mapping
718 * @adapter: board private structure to initialize
26bc19ec 719 *
b980ac18
JK		 720 * Once we know the feature-set enabled for the device, we'll cache
721 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 722 **/
723static void igb_cache_ring_register(struct igb_adapter *adapter)
724{
ee1b9f06 725 int i = 0, j = 0;
047e0030 726 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 727
728 switch (adapter->hw.mac.type) {
729 case e1000_82576:
730 /* The queues are allocated for virtualization such that VF 0
731 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
732 * In order to avoid collision we start at the first free queue
733 * and continue consuming queues in the same sequence
734 */
ee1b9f06 735 if (adapter->vfs_allocated_count) {
a99955fc 736 for (; i < adapter->rss_queues; i++)
3025a446 737 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 738 Q_IDX_82576(i);
ee1b9f06 739 }
26bc19ec 740 case e1000_82575:
55cac248 741 case e1000_82580:
d2ba2ed8 742 case e1000_i350:
ceb5f13b 743 case e1000_i354:
f96a8a0b
CW		 744 case e1000_i210:
745 case e1000_i211:
26bc19ec 746 default:
ee1b9f06 747 for (; i < adapter->num_rx_queues; i++)
3025a446 748 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 749 for (; j < adapter->num_tx_queues; j++)
3025a446 750 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 751 break;
752 }
753}
754
4be000c8
AD		 755/**
756 * igb_write_ivar - configure ivar for given MSI-X vector
757 * @hw: pointer to the HW structure
758 * @msix_vector: vector number we are allocating to a given ring
759 * @index: row index of IVAR register to write within IVAR table
760 * @offset: column offset of in IVAR, should be multiple of 8
761 *
762 * This function is intended to handle the writing of the IVAR register
763 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
764 * each containing an cause allocation for an Rx and Tx ring, and a
765 * variable number of rows depending on the number of queues supported.
766 **/
767static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
768 int index, int offset)
769{
770 u32 ivar = array_rd32(E1000_IVAR0, index);
771
772 /* clear any bits that are currently set */
773 ivar &= ~((u32)0xFF << offset);
774
775 /* write vector and valid bit */
776 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
777
778 array_wr32(E1000_IVAR0, index, ivar);
779}
780
9d5c8243 781#define IGB_N0_QUEUE -1
047e0030 782static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 783{
047e0030 784 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 785 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 786 int rx_queue = IGB_N0_QUEUE;
787 int tx_queue = IGB_N0_QUEUE;
4be000c8 788 u32 msixbm = 0;
047e0030 789
0ba82994
AD		 790 if (q_vector->rx.ring)
791 rx_queue = q_vector->rx.ring->reg_idx;
792 if (q_vector->tx.ring)
793 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 794
795 switch (hw->mac.type) {
796 case e1000_82575:
9d5c8243 797 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 798 * bitmask for the EICR/EIMS/EIMC registers. To assign one
799 * or more queues to a vector, we write the appropriate bits
800 * into the MSIXBM register for that vector.
801 */
047e0030 802 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 803 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 804 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 805 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 806 if (!adapter->msix_entries && msix_vector == 0)
807 msixbm |= E1000_EIMS_OTHER;
9d5c8243 808 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 809 q_vector->eims_value = msixbm;
2d064c06
AD		 810 break;
811 case e1000_82576:
b980ac18 812 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 813 * with 8 rows. The ordering is column-major so we use the
814 * lower 3 bits as the row index, and the 4th bit as the
815 * column offset.
816 */
817 if (rx_queue > IGB_N0_QUEUE)
818 igb_write_ivar(hw, msix_vector,
819 rx_queue & 0x7,
820 (rx_queue & 0x8) << 1);
821 if (tx_queue > IGB_N0_QUEUE)
822 igb_write_ivar(hw, msix_vector,
823 tx_queue & 0x7,
824 ((tx_queue & 0x8) << 1) + 8);
047e0030 825 q_vector->eims_value = 1 << msix_vector;
2d064c06 826 break;
55cac248 827 case e1000_82580:
d2ba2ed8 828 case e1000_i350:
ceb5f13b 829 case e1000_i354:
f96a8a0b
CW		 830 case e1000_i210:
831 case e1000_i211:
b980ac18 832 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 833 * however instead of ordering column-major we have things
834 * ordered row-major. So we traverse the table by using
835 * bit 0 as the column offset, and the remaining bits as the
836 * row index.
837 */
838 if (rx_queue > IGB_N0_QUEUE)
839 igb_write_ivar(hw, msix_vector,
840 rx_queue >> 1,
841 (rx_queue & 0x1) << 4);
842 if (tx_queue > IGB_N0_QUEUE)
843 igb_write_ivar(hw, msix_vector,
844 tx_queue >> 1,
845 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 846 q_vector->eims_value = 1 << msix_vector;
847 break;
2d064c06
AD		 848 default:
849 BUG();
850 break;
851 }
26b39276
AD		 852
853 /* add q_vector eims value to global eims_enable_mask */
854 adapter->eims_enable_mask |= q_vector->eims_value;
855
856 /* configure q_vector to set itr on first interrupt */
857 q_vector->set_itr = 1;
9d5c8243
AK		 858}
859
860/**
b980ac18
JK		 861 * igb_configure_msix - Configure MSI-X hardware
862 * @adapter: board private structure to initialize
9d5c8243 863 *
b980ac18
JK		 864 * igb_configure_msix sets up the hardware to properly
865 * generate MSI-X interrupts.
9d5c8243
AK		 866 **/
867static void igb_configure_msix(struct igb_adapter *adapter)
868{
869 u32 tmp;
870 int i, vector = 0;
871 struct e1000_hw *hw = &adapter->hw;
872
873 adapter->eims_enable_mask = 0;
9d5c8243
AK		 874
875 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 876 switch (hw->mac.type) {
877 case e1000_82575:
9d5c8243
AK		 878 tmp = rd32(E1000_CTRL_EXT);
879 /* enable MSI-X PBA support*/
880 tmp |= E1000_CTRL_EXT_PBA_CLR;
881
882 /* Auto-Mask interrupts upon ICR read. */
883 tmp |= E1000_CTRL_EXT_EIAME;
884 tmp |= E1000_CTRL_EXT_IRCA;
885
886 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 887
888 /* enable msix_other interrupt */
b980ac18 889 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 890 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 891
2d064c06
AD		 892 break;
893
894 case e1000_82576:
55cac248 895 case e1000_82580:
d2ba2ed8 896 case e1000_i350:
ceb5f13b 897 case e1000_i354:
f96a8a0b
CW		 898 case e1000_i210:
899 case e1000_i211:
047e0030 900 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 901 * won't stick. And it will take days to debug.
902 */
047e0030 903 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 904 E1000_GPIE_PBA | E1000_GPIE_EIAME |
905 E1000_GPIE_NSICR);
047e0030
AD		 906
907 /* enable msix_other interrupt */
908 adapter->eims_other = 1 << vector;
2d064c06 909 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 910
047e0030 911 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 912 break;
913 default:
914 /* do nothing, since nothing else supports MSI-X */
915 break;
916 } /* switch (hw->mac.type) */
047e0030
AD		 917
918 adapter->eims_enable_mask |= adapter->eims_other;
919
26b39276
AD		 920 for (i = 0; i < adapter->num_q_vectors; i++)
921 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 922
9d5c8243
AK		 923 wrfl();
924}
925
926/**
b980ac18
JK		 927 * igb_request_msix - Initialize MSI-X interrupts
928 * @adapter: board private structure to initialize
9d5c8243 929 *
b980ac18
JK		 930 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
931 * kernel.
9d5c8243
AK		 932 **/
933static int igb_request_msix(struct igb_adapter *adapter)
934{
935 struct net_device *netdev = adapter->netdev;
047e0030 936 struct e1000_hw *hw = &adapter->hw;
52285b76 937 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 938
047e0030 939 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 940 igb_msix_other, 0, netdev->name, adapter);
047e0030 941 if (err)
52285b76 942 goto err_out;
047e0030
AD		 943
944 for (i = 0; i < adapter->num_q_vectors; i++) {
945 struct igb_q_vector *q_vector = adapter->q_vector[i];
946
52285b76
SA		 947 vector++;
948
047e0030
AD		 949 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
950
0ba82994 951 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 952 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 953 q_vector->rx.ring->queue_index);
954 else if (q_vector->tx.ring)
047e0030 955 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 956 q_vector->tx.ring->queue_index);
957 else if (q_vector->rx.ring)
047e0030 958 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 959 q_vector->rx.ring->queue_index);
9d5c8243 960 else
047e0030
AD		 961 sprintf(q_vector->name, "%s-unused", netdev->name);
962
9d5c8243 963 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 964 igb_msix_ring, 0, q_vector->name,
965 q_vector);
9d5c8243 966 if (err)
52285b76 967 goto err_free;
9d5c8243
AK		 968 }
969
9d5c8243
AK		 970 igb_configure_msix(adapter);
971 return 0;
52285b76
SA		 972
973err_free:
974 /* free already assigned IRQs */
975 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
976
977 vector--;
978 for (i = 0; i < vector; i++) {
979 free_irq(adapter->msix_entries[free_vector++].vector,
980 adapter->q_vector[i]);
981 }
982err_out:
9d5c8243
AK		 983 return err;
984}
985
986static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
987{
988 if (adapter->msix_entries) {
989 pci_disable_msix(adapter->pdev);
990 kfree(adapter->msix_entries);
991 adapter->msix_entries = NULL;
047e0030 992 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 993 pci_disable_msi(adapter->pdev);
047e0030 994 }
9d5c8243
AK		 995}
996
5536d210 997/**
b980ac18
JK		 998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
5536d210 1001 *
b980ac18
JK		 1002 * This function frees the memory allocated to the q_vector. In addition if
1003 * NAPI is enabled it will delete any references to the NAPI struct prior
1004 * to freeing the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
1010 if (q_vector->tx.ring)
1011 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1012
1013 if (q_vector->rx.ring)
1014 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1015
1016 adapter->q_vector[v_idx] = NULL;
1017 netif_napi_del(&q_vector->napi);
1018
7f90128e 1019 /* igb_get_stats64() might access the rings on this vector,
5536d210
AD		 1020 * we must wait a grace period before freeing it.
1021 */
1022 kfree_rcu(q_vector, rcu);
1023}
1024
047e0030 1025/**
b980ac18
JK		 1026 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1027 * @adapter: board private structure to initialize
047e0030 1028 *
b980ac18
JK		 1029 * This function frees the memory allocated to the q_vectors. In addition if
1030 * NAPI is enabled it will delete any references to the NAPI struct prior
1031 * to freeing the q_vector.
047e0030
AD		 1032 **/
1033static void igb_free_q_vectors(struct igb_adapter *adapter)
1034{
5536d210
AD		 1035 int v_idx = adapter->num_q_vectors;
1036
1037 adapter->num_tx_queues = 0;
1038 adapter->num_rx_queues = 0;
047e0030 1039 adapter->num_q_vectors = 0;
5536d210
AD		 1040
1041 while (v_idx--)
1042 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1043}
1044
1045/**
b980ac18
JK		 1046 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1047 * @adapter: board private structure to initialize
047e0030 1048 *
b980ac18
JK		 1049 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1050 * MSI-X interrupts allocated.
047e0030
AD		 1051 */
1052static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1053{
047e0030
AD		 1054 igb_free_q_vectors(adapter);
1055 igb_reset_interrupt_capability(adapter);
1056}
9d5c8243
AK		 1057
1058/**
b980ac18
JK		 1059 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1060 * @adapter: board private structure to initialize
1061 * @msix: boolean value of MSIX capability
9d5c8243 1062 *
b980ac18
JK		 1063 * Attempt to configure interrupts using the best available
1064 * capabilities of the hardware and kernel.
9d5c8243 1065 **/
53c7d064 1066static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1067{
1068 int err;
1069 int numvecs, i;
1070
53c7d064
SA		 1071 if (!msix)
1072 goto msi_only;
1073
83b7180d 1074 /* Number of supported queues. */
a99955fc 1075 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1076 if (adapter->vfs_allocated_count)
1077 adapter->num_tx_queues = 1;
1078 else
1079 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1080
b980ac18 1081 /* start with one vector for every Rx queue */
047e0030
AD		 1082 numvecs = adapter->num_rx_queues;
1083
b980ac18 1084 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1085 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1086 numvecs += adapter->num_tx_queues;
047e0030
AD		 1087
1088 /* store the number of vectors reserved for queues */
1089 adapter->num_q_vectors = numvecs;
1090
1091 /* add 1 vector for link status interrupts */
1092 numvecs++;
9d5c8243
AK		 1093 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1094 GFP_KERNEL);
f96a8a0b 1095
9d5c8243
AK		 1096 if (!adapter->msix_entries)
1097 goto msi_only;
1098
1099 for (i = 0; i < numvecs; i++)
1100 adapter->msix_entries[i].entry = i;
1101
1102 err = pci_enable_msix(adapter->pdev,
1103 adapter->msix_entries,
1104 numvecs);
1105 if (err == 0)
0c2cc02e 1106 return;
9d5c8243
AK		 1107
1108 igb_reset_interrupt_capability(adapter);
1109
1110 /* If we can't do MSI-X, try MSI */
1111msi_only:
2a3abf6d
AD		 1112#ifdef CONFIG_PCI_IOV
1113 /* disable SR-IOV for non MSI-X configurations */
1114 if (adapter->vf_data) {
1115 struct e1000_hw *hw = &adapter->hw;
1116 /* disable iov and allow time for transactions to clear */
1117 pci_disable_sriov(adapter->pdev);
1118 msleep(500);
1119
1120 kfree(adapter->vf_data);
1121 adapter->vf_data = NULL;
1122 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1123 wrfl();
2a3abf6d
AD		 1124 msleep(100);
1125 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1126 }
1127#endif
4fc82adf 1128 adapter->vfs_allocated_count = 0;
a99955fc 1129 adapter->rss_queues = 1;
4fc82adf 1130 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1131 adapter->num_rx_queues = 1;
661086df 1132 adapter->num_tx_queues = 1;
047e0030 1133 adapter->num_q_vectors = 1;
9d5c8243 1134 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1135 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1136}
1137
5536d210
AD		 1138static void igb_add_ring(struct igb_ring *ring,
1139 struct igb_ring_container *head)
1140{
1141 head->ring = ring;
1142 head->count++;
1143}
1144
047e0030 1145/**
b980ac18
JK		 1146 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1147 * @adapter: board private structure to initialize
1148 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1149 * @v_idx: index of vector in adapter struct
1150 * @txr_count: total number of Tx rings to allocate
1151 * @txr_idx: index of first Tx ring to allocate
1152 * @rxr_count: total number of Rx rings to allocate
1153 * @rxr_idx: index of first Rx ring to allocate
047e0030 1154 *
b980ac18 1155 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1156 **/
5536d210
AD		 1157static int igb_alloc_q_vector(struct igb_adapter *adapter,
1158 int v_count, int v_idx,
1159 int txr_count, int txr_idx,
1160 int rxr_count, int rxr_idx)
047e0030
AD		 1161{
1162 struct igb_q_vector *q_vector;
5536d210
AD		 1163 struct igb_ring *ring;
1164 int ring_count, size;
047e0030 1165
5536d210
AD		 1166 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1167 if (txr_count > 1 || rxr_count > 1)
1168 return -ENOMEM;
1169
1170 ring_count = txr_count + rxr_count;
1171 size = sizeof(struct igb_q_vector) +
1172 (sizeof(struct igb_ring) * ring_count);
1173
1174 /* allocate q_vector and rings */
1175 q_vector = kzalloc(size, GFP_KERNEL);
1176 if (!q_vector)
1177 return -ENOMEM;
1178
1179 /* initialize NAPI */
1180 netif_napi_add(adapter->netdev, &q_vector->napi,
1181 igb_poll, 64);
1182
1183 /* tie q_vector and adapter together */
1184 adapter->q_vector[v_idx] = q_vector;
1185 q_vector->adapter = adapter;
1186
1187 /* initialize work limits */
1188 q_vector->tx.work_limit = adapter->tx_work_limit;
1189
1190 /* initialize ITR configuration */
1191 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1192 q_vector->itr_val = IGB_START_ITR;
1193
1194 /* initialize pointer to rings */
1195 ring = q_vector->ring;
1196
4e227667
AD		 1197 /* intialize ITR */
1198 if (rxr_count) {
1199 /* rx or rx/tx vector */
1200 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1201 q_vector->itr_val = adapter->rx_itr_setting;
1202 } else {
1203 /* tx only vector */
1204 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1205 q_vector->itr_val = adapter->tx_itr_setting;
1206 }
1207
5536d210
AD		 1208 if (txr_count) {
1209 /* assign generic ring traits */
1210 ring->dev = &adapter->pdev->dev;
1211 ring->netdev = adapter->netdev;
1212
1213 /* configure backlink on ring */
1214 ring->q_vector = q_vector;
1215
1216 /* update q_vector Tx values */
1217 igb_add_ring(ring, &q_vector->tx);
1218
1219 /* For 82575, context index must be unique per ring. */
1220 if (adapter->hw.mac.type == e1000_82575)
1221 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1222
1223 /* apply Tx specific ring traits */
1224 ring->count = adapter->tx_ring_count;
1225 ring->queue_index = txr_idx;
1226
827da44c
JS		 1227 u64_stats_init(&ring->tx_syncp);
1228 u64_stats_init(&ring->tx_syncp2);
1229
5536d210
AD		 1230 /* assign ring to adapter */
1231 adapter->tx_ring[txr_idx] = ring;
1232
1233 /* push pointer to next ring */
1234 ring++;
047e0030 1235 }
81c2fc22 1236
5536d210
AD		 1237 if (rxr_count) {
1238 /* assign generic ring traits */
1239 ring->dev = &adapter->pdev->dev;
1240 ring->netdev = adapter->netdev;
047e0030 1241
5536d210
AD		 1242 /* configure backlink on ring */
1243 ring->q_vector = q_vector;
047e0030 1244
5536d210
AD		 1245 /* update q_vector Rx values */
1246 igb_add_ring(ring, &q_vector->rx);
047e0030 1247
5536d210
AD		 1248 /* set flag indicating ring supports SCTP checksum offload */
1249 if (adapter->hw.mac.type >= e1000_82576)
1250 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1251
ceb5f13b
CW		 1252 /*
1253 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1254 * have the tag byte-swapped.
b980ac18 1255 */
5536d210
AD		 1256 if (adapter->hw.mac.type >= e1000_i350)
1257 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1258
5536d210
AD		 1259 /* apply Rx specific ring traits */
1260 ring->count = adapter->rx_ring_count;
1261 ring->queue_index = rxr_idx;
1262
827da44c
JS		 1263 u64_stats_init(&ring->rx_syncp);
1264
5536d210
AD		 1265 /* assign ring to adapter */
1266 adapter->rx_ring[rxr_idx] = ring;
1267 }
1268
1269 return 0;
047e0030
AD		 1270}
1271
5536d210 1272
047e0030 1273/**
b980ac18
JK		 1274 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1275 * @adapter: board private structure to initialize
047e0030 1276 *
b980ac18
JK		 1277 * We allocate one q_vector per queue interrupt. If allocation fails we
1278 * return -ENOMEM.
047e0030 1279 **/
5536d210 1280static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1281{
5536d210
AD		 1282 int q_vectors = adapter->num_q_vectors;
1283 int rxr_remaining = adapter->num_rx_queues;
1284 int txr_remaining = adapter->num_tx_queues;
1285 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1286 int err;
047e0030 1287
5536d210
AD		 1288 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1289 for (; rxr_remaining; v_idx++) {
1290 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1291 0, 0, 1, rxr_idx);
047e0030 1292
5536d210
AD		 1293 if (err)
1294 goto err_out;
1295
1296 /* update counts and index */
1297 rxr_remaining--;
1298 rxr_idx++;
047e0030 1299 }
047e0030 1300 }
5536d210
AD		 1301
1302 for (; v_idx < q_vectors; v_idx++) {
1303 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1304 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1305 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1306 tqpv, txr_idx, rqpv, rxr_idx);
1307
1308 if (err)
1309 goto err_out;
1310
1311 /* update counts and index */
1312 rxr_remaining -= rqpv;
1313 txr_remaining -= tqpv;
1314 rxr_idx++;
1315 txr_idx++;
1316 }
1317
047e0030 1318 return 0;
5536d210
AD		 1319
1320err_out:
1321 adapter->num_tx_queues = 0;
1322 adapter->num_rx_queues = 0;
1323 adapter->num_q_vectors = 0;
1324
1325 while (v_idx--)
1326 igb_free_q_vector(adapter, v_idx);
1327
1328 return -ENOMEM;
047e0030
AD		 1329}
1330
1331/**
b980ac18
JK		 1332 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1333 * @adapter: board private structure to initialize
1334 * @msix: boolean value of MSIX capability
047e0030 1335 *
b980ac18 1336 * This function initializes the interrupts and allocates all of the queues.
047e0030 1337 **/
53c7d064 1338static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1339{
1340 struct pci_dev *pdev = adapter->pdev;
1341 int err;
1342
53c7d064 1343 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1344
1345 err = igb_alloc_q_vectors(adapter);
1346 if (err) {
1347 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1348 goto err_alloc_q_vectors;
1349 }
1350
5536d210 1351 igb_cache_ring_register(adapter);
047e0030
AD		 1352
1353 return 0;
5536d210 1354
047e0030
AD		 1355err_alloc_q_vectors:
1356 igb_reset_interrupt_capability(adapter);
1357 return err;
1358}
1359
9d5c8243 1360/**
b980ac18
JK		 1361 * igb_request_irq - initialize interrupts
1362 * @adapter: board private structure to initialize
9d5c8243 1363 *
b980ac18
JK		 1364 * Attempts to configure interrupts using the best available
1365 * capabilities of the hardware and kernel.
9d5c8243
AK		 1366 **/
1367static int igb_request_irq(struct igb_adapter *adapter)
1368{
1369 struct net_device *netdev = adapter->netdev;
047e0030 1370 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1371 int err = 0;
1372
1373 if (adapter->msix_entries) {
1374 err = igb_request_msix(adapter);
844290e5 1375 if (!err)
9d5c8243 1376 goto request_done;
9d5c8243 1377 /* fall back to MSI */
5536d210
AD		 1378 igb_free_all_tx_resources(adapter);
1379 igb_free_all_rx_resources(adapter);
53c7d064 1380
047e0030 1381 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1382 err = igb_init_interrupt_scheme(adapter, false);
1383 if (err)
047e0030 1384 goto request_done;
53c7d064 1385
047e0030
AD		 1386 igb_setup_all_tx_resources(adapter);
1387 igb_setup_all_rx_resources(adapter);
53c7d064 1388 igb_configure(adapter);
9d5c8243 1389 }
844290e5 1390
c74d588e
AD		 1391 igb_assign_vector(adapter->q_vector[0], 0);
1392
7dfc16fa 1393 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1394 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1395 netdev->name, adapter);
9d5c8243
AK		 1396 if (!err)
1397 goto request_done;
047e0030 1398
9d5c8243
AK		 1399 /* fall back to legacy interrupts */
1400 igb_reset_interrupt_capability(adapter);
7dfc16fa 1401 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1402 }
1403
c74d588e 1404 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1405 netdev->name, adapter);
9d5c8243 1406
6cb5e577 1407 if (err)
c74d588e 1408 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1409 err);
9d5c8243
AK		 1410
1411request_done:
1412 return err;
1413}
1414
1415static void igb_free_irq(struct igb_adapter *adapter)
1416{
9d5c8243
AK		 1417 if (adapter->msix_entries) {
1418 int vector = 0, i;
1419
047e0030 1420 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1421
0d1ae7f4 1422 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1423 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1424 adapter->q_vector[i]);
047e0030
AD		 1425 } else {
1426 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1427 }
9d5c8243
AK		 1428}
1429
1430/**
b980ac18
JK		 1431 * igb_irq_disable - Mask off interrupt generation on the NIC
1432 * @adapter: board private structure
9d5c8243
AK		 1433 **/
1434static void igb_irq_disable(struct igb_adapter *adapter)
1435{
1436 struct e1000_hw *hw = &adapter->hw;
1437
b980ac18 1438 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1439 * mapped into these registers and so clearing the bits can cause
1440 * issues on the VF drivers so we only need to clear what we set
1441 */
9d5c8243 1442 if (adapter->msix_entries) {
2dfd1212
AD		 1443 u32 regval = rd32(E1000_EIAM);
1444 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1445 wr32(E1000_EIMC, adapter->eims_enable_mask);
1446 regval = rd32(E1000_EIAC);
1447 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1448 }
844290e5
PW		 1449
1450 wr32(E1000_IAM, 0);
9d5c8243
AK		 1451 wr32(E1000_IMC, ~0);
1452 wrfl();
81a61859
ET		 1453 if (adapter->msix_entries) {
1454 int i;
1455 for (i = 0; i < adapter->num_q_vectors; i++)
1456 synchronize_irq(adapter->msix_entries[i].vector);
1457 } else {
1458 synchronize_irq(adapter->pdev->irq);
1459 }
9d5c8243
AK		 1460}
1461
1462/**
b980ac18
JK		 1463 * igb_irq_enable - Enable default interrupt generation settings
1464 * @adapter: board private structure
9d5c8243
AK		 1465 **/
1466static void igb_irq_enable(struct igb_adapter *adapter)
1467{
1468 struct e1000_hw *hw = &adapter->hw;
1469
1470 if (adapter->msix_entries) {
06218a8d 1471 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1472 u32 regval = rd32(E1000_EIAC);
1473 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1474 regval = rd32(E1000_EIAM);
1475 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1476 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1477 if (adapter->vfs_allocated_count) {
4ae196df 1478 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1479 ims |= E1000_IMS_VMMB;
1480 }
1481 wr32(E1000_IMS, ims);
844290e5 1482 } else {
55cac248
AD		 1483 wr32(E1000_IMS, IMS_ENABLE_MASK |
1484 E1000_IMS_DRSTA);
1485 wr32(E1000_IAM, IMS_ENABLE_MASK |
1486 E1000_IMS_DRSTA);
844290e5 1487 }
9d5c8243
AK		 1488}
1489
1490static void igb_update_mng_vlan(struct igb_adapter *adapter)
1491{
51466239 1492 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1493 u16 vid = adapter->hw.mng_cookie.vlan_id;
1494 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1495
1496 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1497 /* add VID to filter table */
1498 igb_vfta_set(hw, vid, true);
1499 adapter->mng_vlan_id = vid;
1500 } else {
1501 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1502 }
1503
1504 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1505 (vid != old_vid) &&
b2cb09b1 1506 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1507 /* remove VID from filter table */
1508 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1509 }
1510}
1511
1512/**
b980ac18
JK		 1513 * igb_release_hw_control - release control of the h/w to f/w
1514 * @adapter: address of board private structure
9d5c8243 1515 *
b980ac18
JK		 1516 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1517 * For ASF and Pass Through versions of f/w this means that the
1518 * driver is no longer loaded.
9d5c8243
AK		 1519 **/
1520static void igb_release_hw_control(struct igb_adapter *adapter)
1521{
1522 struct e1000_hw *hw = &adapter->hw;
1523 u32 ctrl_ext;
1524
1525 /* Let firmware take over control of h/w */
1526 ctrl_ext = rd32(E1000_CTRL_EXT);
1527 wr32(E1000_CTRL_EXT,
1528 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1529}
1530
9d5c8243 1531/**
b980ac18
JK		 1532 * igb_get_hw_control - get control of the h/w from f/w
1533 * @adapter: address of board private structure
9d5c8243 1534 *
b980ac18
JK		 1535 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1536 * For ASF and Pass Through versions of f/w this means that
1537 * the driver is loaded.
9d5c8243
AK		 1538 **/
1539static void igb_get_hw_control(struct igb_adapter *adapter)
1540{
1541 struct e1000_hw *hw = &adapter->hw;
1542 u32 ctrl_ext;
1543
1544 /* Let firmware know the driver has taken over */
1545 ctrl_ext = rd32(E1000_CTRL_EXT);
1546 wr32(E1000_CTRL_EXT,
1547 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1548}
1549
9d5c8243 1550/**
b980ac18
JK		 1551 * igb_configure - configure the hardware for RX and TX
1552 * @adapter: private board structure
9d5c8243
AK		 1553 **/
1554static void igb_configure(struct igb_adapter *adapter)
1555{
1556 struct net_device *netdev = adapter->netdev;
1557 int i;
1558
1559 igb_get_hw_control(adapter);
ff41f8dc 1560 igb_set_rx_mode(netdev);
9d5c8243
AK		 1561
1562 igb_restore_vlan(adapter);
9d5c8243 1563
85b430b4 1564 igb_setup_tctl(adapter);
06cf2666 1565 igb_setup_mrqc(adapter);
9d5c8243 1566 igb_setup_rctl(adapter);
85b430b4
AD		 1567
1568 igb_configure_tx(adapter);
9d5c8243 1569 igb_configure_rx(adapter);
662d7205
AD		 1570
1571 igb_rx_fifo_flush_82575(&adapter->hw);
1572
c493ea45 1573 /* call igb_desc_unused which always leaves
9d5c8243 1574 * at least 1 descriptor unused to make sure
b980ac18
JK		 1575 * next_to_use != next_to_clean
1576 */
9d5c8243 1577 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1578 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1579 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1580 }
9d5c8243
AK		 1581}
1582
88a268c1 1583/**
b980ac18
JK		 1584 * igb_power_up_link - Power up the phy/serdes link
1585 * @adapter: address of board private structure
88a268c1
NN		 1586 **/
1587void igb_power_up_link(struct igb_adapter *adapter)
1588{
76886596
AA		 1589 igb_reset_phy(&adapter->hw);
1590
88a268c1
NN		 1591 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1592 igb_power_up_phy_copper(&adapter->hw);
1593 else
1594 igb_power_up_serdes_link_82575(&adapter->hw);
1595}
1596
1597/**
b980ac18
JK		 1598 * igb_power_down_link - Power down the phy/serdes link
1599 * @adapter: address of board private structure
88a268c1
NN		 1600 */
1601static void igb_power_down_link(struct igb_adapter *adapter)
1602{
1603 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1604 igb_power_down_phy_copper_82575(&adapter->hw);
1605 else
1606 igb_shutdown_serdes_link_82575(&adapter->hw);
1607}
9d5c8243
AK		 1608
1609/**
b980ac18
JK		 1610 * igb_up - Open the interface and prepare it to handle traffic
1611 * @adapter: board private structure
9d5c8243 1612 **/
9d5c8243
AK		 1613int igb_up(struct igb_adapter *adapter)
1614{
1615 struct e1000_hw *hw = &adapter->hw;
1616 int i;
1617
1618 /* hardware has been reset, we need to reload some things */
1619 igb_configure(adapter);
1620
1621 clear_bit(__IGB_DOWN, &adapter->state);
1622
0d1ae7f4
AD		 1623 for (i = 0; i < adapter->num_q_vectors; i++)
1624 napi_enable(&(adapter->q_vector[i]->napi));
1625
844290e5 1626 if (adapter->msix_entries)
9d5c8243 1627 igb_configure_msix(adapter);
feeb2721
AD		 1628 else
1629 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1630
1631 /* Clear any pending interrupts. */
1632 rd32(E1000_ICR);
1633 igb_irq_enable(adapter);
1634
d4960307
AD		 1635 /* notify VFs that reset has been completed */
1636 if (adapter->vfs_allocated_count) {
1637 u32 reg_data = rd32(E1000_CTRL_EXT);
1638 reg_data |= E1000_CTRL_EXT_PFRSTD;
1639 wr32(E1000_CTRL_EXT, reg_data);
1640 }
1641
4cb9be7a
JB		 1642 netif_tx_start_all_queues(adapter->netdev);
1643
25568a53
AD		 1644 /* start the watchdog. */
1645 hw->mac.get_link_status = 1;
1646 schedule_work(&adapter->watchdog_task);
1647
9d5c8243
AK		 1648 return 0;
1649}
1650
1651void igb_down(struct igb_adapter *adapter)
1652{
9d5c8243 1653 struct net_device *netdev = adapter->netdev;
330a6d6a 1654 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1655 u32 tctl, rctl;
1656 int i;
1657
1658 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1659 * reschedule our watchdog timer
1660 */
9d5c8243
AK		 1661 set_bit(__IGB_DOWN, &adapter->state);
1662
1663 /* disable receives in the hardware */
1664 rctl = rd32(E1000_RCTL);
1665 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1666 /* flush and sleep below */
1667
fd2ea0a7 1668 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1669
1670 /* disable transmits in the hardware */
1671 tctl = rd32(E1000_TCTL);
1672 tctl &= ~E1000_TCTL_EN;
1673 wr32(E1000_TCTL, tctl);
1674 /* flush both disables and wait for them to finish */
1675 wrfl();
1676 msleep(10);
1677
41f149a2
CW		 1678 igb_irq_disable(adapter);
1679
aa9b8cc4
AA		 1680 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1681
41f149a2
CW		 1682 for (i = 0; i < adapter->num_q_vectors; i++) {
1683 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1684 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1685 }
9d5c8243 1686
9d5c8243
AK		 1687
1688 del_timer_sync(&adapter->watchdog_timer);
1689 del_timer_sync(&adapter->phy_info_timer);
1690
9d5c8243 1691 netif_carrier_off(netdev);
04fe6358
AD		 1692
1693 /* record the stats before reset*/
12dcd86b
ED		 1694 spin_lock(&adapter->stats64_lock);
1695 igb_update_stats(adapter, &adapter->stats64);
1696 spin_unlock(&adapter->stats64_lock);
04fe6358 1697
9d5c8243
AK		 1698 adapter->link_speed = 0;
1699 adapter->link_duplex = 0;
1700
3023682e
JK		 1701 if (!pci_channel_offline(adapter->pdev))
1702 igb_reset(adapter);
9d5c8243
AK		 1703 igb_clean_all_tx_rings(adapter);
1704 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1705#ifdef CONFIG_IGB_DCA
1706
1707 /* since we reset the hardware DCA settings were cleared */
1708 igb_setup_dca(adapter);
1709#endif
9d5c8243
AK		 1710}
1711
1712void igb_reinit_locked(struct igb_adapter *adapter)
1713{
1714 WARN_ON(in_interrupt());
1715 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1716 msleep(1);
1717 igb_down(adapter);
1718 igb_up(adapter);
1719 clear_bit(__IGB_RESETTING, &adapter->state);
1720}
1721
1722void igb_reset(struct igb_adapter *adapter)
1723{
090b1795 1724 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1725 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1726 struct e1000_mac_info *mac = &hw->mac;
1727 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1728 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1729
1730 /* Repartition Pba for greater than 9k mtu
1731 * To take effect CTRL.RST is required.
1732 */
fa4dfae0 1733 switch (mac->type) {
d2ba2ed8 1734 case e1000_i350:
ceb5f13b 1735 case e1000_i354:
55cac248
AD		 1736 case e1000_82580:
1737 pba = rd32(E1000_RXPBS);
1738 pba = igb_rxpbs_adjust_82580(pba);
1739 break;
fa4dfae0 1740 case e1000_82576:
d249be54
AD		 1741 pba = rd32(E1000_RXPBS);
1742 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1743 break;
1744 case e1000_82575:
f96a8a0b
CW		 1745 case e1000_i210:
1746 case e1000_i211:
fa4dfae0
AD		 1747 default:
1748 pba = E1000_PBA_34K;
1749 break;
2d064c06 1750 }
9d5c8243 1751
2d064c06
AD		 1752 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1753 (mac->type < e1000_82576)) {
9d5c8243
AK		 1754 /* adjust PBA for jumbo frames */
1755 wr32(E1000_PBA, pba);
1756
1757 /* To maintain wire speed transmits, the Tx FIFO should be
1758 * large enough to accommodate two full transmit packets,
1759 * rounded up to the next 1KB and expressed in KB. Likewise,
1760 * the Rx FIFO should be large enough to accommodate at least
1761 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1762 * expressed in KB.
1763 */
9d5c8243
AK		 1764 pba = rd32(E1000_PBA);
1765 /* upper 16 bits has Tx packet buffer allocation size in KB */
1766 tx_space = pba >> 16;
1767 /* lower 16 bits has Rx packet buffer allocation size in KB */
1768 pba &= 0xffff;
b980ac18
JK		 1769 /* the Tx fifo also stores 16 bytes of information about the Tx
1770 * but don't include ethernet FCS because hardware appends it
1771 */
9d5c8243 1772 min_tx_space = (adapter->max_frame_size +
85e8d004 1773 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1774 ETH_FCS_LEN) * 2;
1775 min_tx_space = ALIGN(min_tx_space, 1024);
1776 min_tx_space >>= 10;
1777 /* software strips receive CRC, so leave room for it */
1778 min_rx_space = adapter->max_frame_size;
1779 min_rx_space = ALIGN(min_rx_space, 1024);
1780 min_rx_space >>= 10;
1781
1782 /* If current Tx allocation is less than the min Tx FIFO size,
1783 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1784 * allocation, take space away from current Rx allocation
1785 */
9d5c8243
AK		 1786 if (tx_space < min_tx_space &&
1787 ((min_tx_space - tx_space) < pba)) {
1788 pba = pba - (min_tx_space - tx_space);
1789
b980ac18
JK		 1790 /* if short on Rx space, Rx wins and must trump Tx
1791 * adjustment
1792 */
9d5c8243
AK		 1793 if (pba < min_rx_space)
1794 pba = min_rx_space;
1795 }
2d064c06 1796 wr32(E1000_PBA, pba);
9d5c8243 1797 }
9d5c8243
AK		 1798
1799 /* flow control settings */
1800 /* The high water mark must be low enough to fit one full frame
1801 * (or the size used for early receive) above it in the Rx FIFO.
1802 * Set it to the lower of:
1803 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1804 * - the full Rx FIFO size minus one full frame
1805 */
9d5c8243 1806 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1807 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1808
d48507fe 1809 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1810 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1811 fc->pause_time = 0xFFFF;
1812 fc->send_xon = 1;
0cce119a 1813 fc->current_mode = fc->requested_mode;
9d5c8243 1814
4ae196df
AD		 1815 /* disable receive for all VFs and wait one second */
1816 if (adapter->vfs_allocated_count) {
1817 int i;
1818 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1819 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1820
1821 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1822 igb_ping_all_vfs(adapter);
4ae196df
AD		 1823
1824 /* disable transmits and receives */
1825 wr32(E1000_VFRE, 0);
1826 wr32(E1000_VFTE, 0);
1827 }
1828
9d5c8243 1829 /* Allow time for pending master requests to run */
330a6d6a 1830 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1831 wr32(E1000_WUC, 0);
1832
330a6d6a 1833 if (hw->mac.ops.init_hw(hw))
090b1795 1834 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1835
b980ac18 1836 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1837 * control is off when forcing speed.
1838 */
1839 if (!hw->mac.autoneg)
1840 igb_force_mac_fc(hw);
1841
b6e0c419 1842 igb_init_dmac(adapter, pba);
e428893b
CW		 1843#ifdef CONFIG_IGB_HWMON
1844 /* Re-initialize the thermal sensor on i350 devices. */
1845 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1846 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1847 /* If present, re-initialize the external thermal sensor
1848 * interface.
1849 */
1850 if (adapter->ets)
1851 mac->ops.init_thermal_sensor_thresh(hw);
1852 }
1853 }
1854#endif
88a268c1
NN		 1855 if (!netif_running(adapter->netdev))
1856 igb_power_down_link(adapter);
1857
9d5c8243
AK		 1858 igb_update_mng_vlan(adapter);
1859
1860 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1861 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1862
1f6e8178
MV		 1863 /* Re-enable PTP, where applicable. */
1864 igb_ptp_reset(adapter);
1f6e8178 1865
330a6d6a 1866 igb_get_phy_info(hw);
9d5c8243
AK		 1867}
1868
c8f44aff
MM		 1869static netdev_features_t igb_fix_features(struct net_device *netdev,
1870 netdev_features_t features)
b2cb09b1 1871{
b980ac18
JK		 1872 /* Since there is no support for separate Rx/Tx vlan accel
1873 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1874 */
f646968f
PM		 1875 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1876 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1877 else
f646968f 1878 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1879
1880 return features;
1881}
1882
c8f44aff
MM		 1883static int igb_set_features(struct net_device *netdev,
1884 netdev_features_t features)
ac52caa3 1885{
c8f44aff 1886 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1887 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1888
f646968f 1889 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1890 igb_vlan_mode(netdev, features);
1891
89eaefb6
BG		 1892 if (!(changed & NETIF_F_RXALL))
1893 return 0;
1894
1895 netdev->features = features;
1896
1897 if (netif_running(netdev))
1898 igb_reinit_locked(adapter);
1899 else
1900 igb_reset(adapter);
1901
ac52caa3
MM		 1902 return 0;
1903}
1904
2e5c6922 1905static const struct net_device_ops igb_netdev_ops = {
559e9c49 1906 .ndo_open = igb_open,
2e5c6922 1907 .ndo_stop = igb_close,
cd392f5c 1908 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1909 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1910 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1911 .ndo_set_mac_address = igb_set_mac,
1912 .ndo_change_mtu = igb_change_mtu,
1913 .ndo_do_ioctl = igb_ioctl,
1914 .ndo_tx_timeout = igb_tx_timeout,
1915 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1916 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1917 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1918 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1919 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1920 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1921 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1922 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1923#ifdef CONFIG_NET_POLL_CONTROLLER
1924 .ndo_poll_controller = igb_netpoll,
1925#endif
b2cb09b1
JP		 1926 .ndo_fix_features = igb_fix_features,
1927 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1928};
1929
d67974f0
CW		 1930/**
1931 * igb_set_fw_version - Configure version string for ethtool
1932 * @adapter: adapter struct
d67974f0
CW		 1933 **/
1934void igb_set_fw_version(struct igb_adapter *adapter)
1935{
1936 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1937 struct e1000_fw_version fw;
1938
1939 igb_get_fw_version(hw, &fw);
1940
1941 switch (hw->mac.type) {
7dc98a62 1942 case e1000_i210:
0b1a6f2e 1943 case e1000_i211:
7dc98a62
CW		 1944 if (!(igb_get_flash_presence_i210(hw))) {
1945 snprintf(adapter->fw_version,
1946 sizeof(adapter->fw_version),
1947 "%2d.%2d-%d",
1948 fw.invm_major, fw.invm_minor,
1949 fw.invm_img_type);
1950 break;
1951 }
1952 /* fall through */
0b1a6f2e
CW		 1953 default:
1954 /* if option is rom valid, display its version too */
1955 if (fw.or_valid) {
1956 snprintf(adapter->fw_version,
1957 sizeof(adapter->fw_version),
1958 "%d.%d, 0x%08x, %d.%d.%d",
1959 fw.eep_major, fw.eep_minor, fw.etrack_id,
1960 fw.or_major, fw.or_build, fw.or_patch);
1961 /* no option rom */
7dc98a62 1962 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 1963 snprintf(adapter->fw_version,
7dc98a62
CW		 1964 sizeof(adapter->fw_version),
1965 "%d.%d, 0x%08x",
1966 fw.eep_major, fw.eep_minor, fw.etrack_id);
1967 } else {
1968 snprintf(adapter->fw_version,
1969 sizeof(adapter->fw_version),
1970 "%d.%d.%d",
1971 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 1972 }
1973 break;
d67974f0 1974 }
d67974f0
CW		 1975 return;
1976}
1977
b980ac18
JK		 1978/**
1979 * igb_init_i2c - Init I2C interface
441fc6fd 1980 * @adapter: pointer to adapter structure
b980ac18 1981 **/
441fc6fd
CW		 1982static s32 igb_init_i2c(struct igb_adapter *adapter)
1983{
1984 s32 status = E1000_SUCCESS;
1985
1986 /* I2C interface supported on i350 devices */
1987 if (adapter->hw.mac.type != e1000_i350)
1988 return E1000_SUCCESS;
1989
1990 /* Initialize the i2c bus which is controlled by the registers.
1991 * This bus will use the i2c_algo_bit structue that implements
1992 * the protocol through toggling of the 4 bits in the register.
1993 */
1994 adapter->i2c_adap.owner = THIS_MODULE;
1995 adapter->i2c_algo = igb_i2c_algo;
1996 adapter->i2c_algo.data = adapter;
1997 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1998 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1999 strlcpy(adapter->i2c_adap.name, "igb BB",
2000 sizeof(adapter->i2c_adap.name));
2001 status = i2c_bit_add_bus(&adapter->i2c_adap);
2002 return status;
2003}
2004
9d5c8243 2005/**
b980ac18
JK		 2006 * igb_probe - Device Initialization Routine
2007 * @pdev: PCI device information struct
2008 * @ent: entry in igb_pci_tbl
9d5c8243 2009 *
b980ac18 2010 * Returns 0 on success, negative on failure
9d5c8243 2011 *
b980ac18
JK		 2012 * igb_probe initializes an adapter identified by a pci_dev structure.
2013 * The OS initialization, configuring of the adapter private structure,
2014 * and a hardware reset occur.
9d5c8243 2015 **/
1dd06ae8 2016static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2017{
2018 struct net_device *netdev;
2019 struct igb_adapter *adapter;
2020 struct e1000_hw *hw;
4337e993 2021 u16 eeprom_data = 0;
9835fd73 2022 s32 ret_val;
4337e993 2023 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 2024 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2025 unsigned long mmio_start, mmio_len;
2d6a5e95 2026 int err, pci_using_dac;
9835fd73 2027 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2028
bded64a7
AG		 2029 /* Catch broken hardware that put the wrong VF device ID in
2030 * the PCIe SR-IOV capability.
2031 */
2032 if (pdev->is_virtfn) {
2033 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2034 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2035 return -EINVAL;
2036 }
2037
aed5dec3 2038 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2039 if (err)
2040 return err;
2041
2042 pci_using_dac = 0;
dc4ff9bb 2043 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2044 if (!err) {
dc4ff9bb 2045 pci_using_dac = 1;
9d5c8243 2046 } else {
dc4ff9bb 2047 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2048 if (err) {
dc4ff9bb
RK		 2049 dev_err(&pdev->dev,
2050 "No usable DMA configuration, aborting\n");
2051 goto err_dma;
9d5c8243
AK		 2052 }
2053 }
2054
aed5dec3 2055 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2056 IORESOURCE_MEM),
2057 igb_driver_name);
9d5c8243
AK		 2058 if (err)
2059 goto err_pci_reg;
2060
19d5afd4 2061 pci_enable_pcie_error_reporting(pdev);
40a914fa 2062
9d5c8243 2063 pci_set_master(pdev);
c682fc23 2064 pci_save_state(pdev);
9d5c8243
AK		 2065
2066 err = -ENOMEM;
1bfaf07b 2067 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2068 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2069 if (!netdev)
2070 goto err_alloc_etherdev;
2071
2072 SET_NETDEV_DEV(netdev, &pdev->dev);
2073
2074 pci_set_drvdata(pdev, netdev);
2075 adapter = netdev_priv(netdev);
2076 adapter->netdev = netdev;
2077 adapter->pdev = pdev;
2078 hw = &adapter->hw;
2079 hw->back = adapter;
b3f4d599 2080 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2081
2082 mmio_start = pci_resource_start(pdev, 0);
2083 mmio_len = pci_resource_len(pdev, 0);
2084
2085 err = -EIO;
28b0759c
AD		 2086 hw->hw_addr = ioremap(mmio_start, mmio_len);
2087 if (!hw->hw_addr)
9d5c8243
AK		 2088 goto err_ioremap;
2089
2e5c6922 2090 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2091 igb_set_ethtool_ops(netdev);
9d5c8243 2092 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2093
2094 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2095
2096 netdev->mem_start = mmio_start;
2097 netdev->mem_end = mmio_start + mmio_len;
2098
9d5c8243
AK		 2099 /* PCI config space info */
2100 hw->vendor_id = pdev->vendor;
2101 hw->device_id = pdev->device;
2102 hw->revision_id = pdev->revision;
2103 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2104 hw->subsystem_device_id = pdev->subsystem_device;
2105
9d5c8243
AK		 2106 /* Copy the default MAC, PHY and NVM function pointers */
2107 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2108 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2109 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2110 /* Initialize skew-specific constants */
2111 err = ei->get_invariants(hw);
2112 if (err)
450c87c8 2113 goto err_sw_init;
9d5c8243 2114
450c87c8 2115 /* setup the private structure */
9d5c8243
AK		 2116 err = igb_sw_init(adapter);
2117 if (err)
2118 goto err_sw_init;
2119
2120 igb_get_bus_info_pcie(hw);
2121
2122 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2123
2124 /* Copper options */
2125 if (hw->phy.media_type == e1000_media_type_copper) {
2126 hw->phy.mdix = AUTO_ALL_MODES;
2127 hw->phy.disable_polarity_correction = false;
2128 hw->phy.ms_type = e1000_ms_hw_default;
2129 }
2130
2131 if (igb_check_reset_block(hw))
2132 dev_info(&pdev->dev,
2133 "PHY reset is blocked due to SOL/IDER session.\n");
2134
b980ac18 2135 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2136 * set by igb_sw_init so we should use an or instead of an
2137 * assignment.
2138 */
2139 netdev->features |= NETIF_F_SG |
2140 NETIF_F_IP_CSUM |
2141 NETIF_F_IPV6_CSUM |
2142 NETIF_F_TSO |
2143 NETIF_F_TSO6 |
2144 NETIF_F_RXHASH |
2145 NETIF_F_RXCSUM |
f646968f
PM		 2146 NETIF_F_HW_VLAN_CTAG_RX |
2147 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2148
2149 /* copy netdev features into list of user selectable features */
2150 netdev->hw_features |= netdev->features;
89eaefb6 2151 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2152
2153 /* set this bit last since it cannot be part of hw_features */
f646968f 2154 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2155
2156 netdev->vlan_features |= NETIF_F_TSO |
2157 NETIF_F_TSO6 |
2158 NETIF_F_IP_CSUM |
2159 NETIF_F_IPV6_CSUM |
2160 NETIF_F_SG;
48f29ffc 2161
6b8f0922
BG		 2162 netdev->priv_flags |= IFF_SUPP_NOFCS;
2163
7b872a55 2164 if (pci_using_dac) {
9d5c8243 2165 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2166 netdev->vlan_features |= NETIF_F_HIGHDMA;
2167 }
9d5c8243 2168
ac52caa3
MM		 2169 if (hw->mac.type >= e1000_82576) {
2170 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2171 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2172 }
b9473560 2173
01789349
JP		 2174 netdev->priv_flags |= IFF_UNICAST_FLT;
2175
330a6d6a 2176 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2177
2178 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2179 * known good starting state
2180 */
9d5c8243
AK		 2181 hw->mac.ops.reset_hw(hw);
2182
ef3a0092
CW		 2183 /* make sure the NVM is good , i211/i210 parts can have special NVM
2184 * that doesn't contain a checksum
f96a8a0b 2185 */
ef3a0092
CW		 2186 switch (hw->mac.type) {
2187 case e1000_i210:
2188 case e1000_i211:
2189 if (igb_get_flash_presence_i210(hw)) {
2190 if (hw->nvm.ops.validate(hw) < 0) {
2191 dev_err(&pdev->dev,
2192 "The NVM Checksum Is Not Valid\n");
2193 err = -EIO;
2194 goto err_eeprom;
2195 }
2196 }
2197 break;
2198 default:
f96a8a0b
CW		 2199 if (hw->nvm.ops.validate(hw) < 0) {
2200 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2201 err = -EIO;
2202 goto err_eeprom;
2203 }
ef3a0092 2204 break;
9d5c8243
AK		 2205 }
2206
2207 /* copy the MAC address out of the NVM */
2208 if (hw->mac.ops.read_mac_addr(hw))
2209 dev_err(&pdev->dev, "NVM Read Error\n");
2210
2211 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2212
aaeb6cdf 2213 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2214 dev_err(&pdev->dev, "Invalid MAC Address\n");
2215 err = -EIO;
2216 goto err_eeprom;
2217 }
2218
d67974f0
CW		 2219 /* get firmware version for ethtool -i */
2220 igb_set_fw_version(adapter);
2221
c061b18d 2222 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2223 (unsigned long) adapter);
c061b18d 2224 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2225 (unsigned long) adapter);
9d5c8243
AK		 2226
2227 INIT_WORK(&adapter->reset_task, igb_reset_task);
2228 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2229
450c87c8 2230 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2231 adapter->fc_autoneg = true;
2232 hw->mac.autoneg = true;
2233 hw->phy.autoneg_advertised = 0x2f;
2234
0cce119a
AD		 2235 hw->fc.requested_mode = e1000_fc_default;
2236 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2237
9d5c8243
AK		 2238 igb_validate_mdi_setting(hw);
2239
63d4a8f9 2240 /* By default, support wake on port A */
a2cf8b6c 2241 if (hw->bus.func == 0)
63d4a8f9
MV		 2242 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2243
2244 /* Check the NVM for wake support on non-port A ports */
2245 if (hw->mac.type >= e1000_82580)
55cac248 2246 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2247 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2248 &eeprom_data);
a2cf8b6c
AD		 2249 else if (hw->bus.func == 1)
2250 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2251
63d4a8f9
MV		 2252 if (eeprom_data & IGB_EEPROM_APME)
2253 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2254
2255 /* now that we have the eeprom settings, apply the special cases where
2256 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2257 * lan on a particular port
2258 */
9d5c8243
AK		 2259 switch (pdev->device) {
2260 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2261 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2262 break;
2263 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2264 case E1000_DEV_ID_82576_FIBER:
2265 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2266 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2267 * regardless of eeprom setting
2268 */
9d5c8243 2269 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2270 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2271 break;
c8ea5ea9 2272 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2273 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2274 /* if quad port adapter, disable WoL on all but port A */
2275 if (global_quad_port_a != 0)
63d4a8f9 2276 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2277 else
2278 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2279 /* Reset for multiple quad port adapters */
2280 if (++global_quad_port_a == 4)
2281 global_quad_port_a = 0;
2282 break;
63d4a8f9
MV		 2283 default:
2284 /* If the device can't wake, don't set software support */
2285 if (!device_can_wakeup(&adapter->pdev->dev))
2286 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2287 }
2288
2289 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2290 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2291 adapter->wol |= E1000_WUFC_MAG;
2292
2293 /* Some vendors want WoL disabled by default, but still supported */
2294 if ((hw->mac.type == e1000_i350) &&
2295 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2296 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2297 adapter->wol = 0;
2298 }
2299
2300 device_set_wakeup_enable(&adapter->pdev->dev,
2301 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2302
2303 /* reset the hardware with the new settings */
2304 igb_reset(adapter);
2305
441fc6fd
CW		 2306 /* Init the I2C interface */
2307 err = igb_init_i2c(adapter);
2308 if (err) {
2309 dev_err(&pdev->dev, "failed to init i2c interface\n");
2310 goto err_eeprom;
2311 }
2312
9d5c8243
AK		 2313 /* let the f/w know that the h/w is now under the control of the
2314 * driver. */
2315 igb_get_hw_control(adapter);
2316
9d5c8243
AK		 2317 strcpy(netdev->name, "eth%d");
2318 err = register_netdev(netdev);
2319 if (err)
2320 goto err_register;
2321
b168dfc5
JB		 2322 /* carrier off reporting is important to ethtool even BEFORE open */
2323 netif_carrier_off(netdev);
2324
421e02f0 2325#ifdef CONFIG_IGB_DCA
bbd98fe4 2326 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2327 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2328 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2329 igb_setup_dca(adapter);
2330 }
fe4506b6 2331
38c845c7 2332#endif
e428893b
CW		 2333#ifdef CONFIG_IGB_HWMON
2334 /* Initialize the thermal sensor on i350 devices. */
2335 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2336 u16 ets_word;
3c89f6d0 2337
b980ac18 2338 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2339 * external thermal sensor.
2340 */
2341 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2342 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2343 adapter->ets = true;
2344 else
2345 adapter->ets = false;
2346 if (igb_sysfs_init(adapter))
2347 dev_err(&pdev->dev,
2348 "failed to allocate sysfs resources\n");
2349 } else {
2350 adapter->ets = false;
2351 }
2352#endif
673b8b70 2353 /* do hw tstamp init after resetting */
7ebae817 2354 igb_ptp_init(adapter);
673b8b70 2355
9d5c8243 2356 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2357 /* print bus type/speed/width info, not applicable to i354 */
2358 if (hw->mac.type != e1000_i354) {
2359 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2360 netdev->name,
2361 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2362 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2363 "unknown"),
2364 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2365 "Width x4" :
2366 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2367 "Width x2" :
2368 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2369 "Width x1" : "unknown"), netdev->dev_addr);
2370 }
9d5c8243 2371
53ea6c7e
TF		 2372 if ((hw->mac.type >= e1000_i210 ||
2373 igb_get_flash_presence_i210(hw))) {
2374 ret_val = igb_read_part_string(hw, part_str,
2375 E1000_PBANUM_LENGTH);
2376 } else {
2377 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2378 }
2379
9835fd73
CW		 2380 if (ret_val)
2381 strcpy(part_str, "Unknown");
2382 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2383 dev_info(&pdev->dev,
2384 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2385 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2386 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2387 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2388 switch (hw->mac.type) {
2389 case e1000_i350:
f96a8a0b
CW		 2390 case e1000_i210:
2391 case e1000_i211:
09b068d4
CW		 2392 igb_set_eee_i350(hw);
2393 break;
ceb5f13b
CW		 2394 case e1000_i354:
2395 if (hw->phy.media_type == e1000_media_type_copper) {
2396 if ((rd32(E1000_CTRL_EXT) &
2397 E1000_CTRL_EXT_LINK_MODE_SGMII))
2398 igb_set_eee_i354(hw);
2399 }
2400 break;
09b068d4
CW		 2401 default:
2402 break;
2403 }
749ab2cd
YZ		 2404
2405 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2406 return 0;
2407
2408err_register:
2409 igb_release_hw_control(adapter);
441fc6fd 2410 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2411err_eeprom:
2412 if (!igb_check_reset_block(hw))
f5f4cf08 2413 igb_reset_phy(hw);
9d5c8243
AK		 2414
2415 if (hw->flash_address)
2416 iounmap(hw->flash_address);
9d5c8243 2417err_sw_init:
047e0030 2418 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2419 iounmap(hw->hw_addr);
2420err_ioremap:
2421 free_netdev(netdev);
2422err_alloc_etherdev:
559e9c49 2423 pci_release_selected_regions(pdev,
b980ac18 2424 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2425err_pci_reg:
2426err_dma:
2427 pci_disable_device(pdev);
2428 return err;
2429}
2430
fa44f2f1 2431#ifdef CONFIG_PCI_IOV
781798a1 2432static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2433{
2434 struct net_device *netdev = pci_get_drvdata(pdev);
2435 struct igb_adapter *adapter = netdev_priv(netdev);
2436 struct e1000_hw *hw = &adapter->hw;
2437
2438 /* reclaim resources allocated to VFs */
2439 if (adapter->vf_data) {
2440 /* disable iov and allow time for transactions to clear */
b09186d2 2441 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2442 dev_warn(&pdev->dev,
2443 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2444 return -EPERM;
2445 } else {
2446 pci_disable_sriov(pdev);
2447 msleep(500);
2448 }
2449
2450 kfree(adapter->vf_data);
2451 adapter->vf_data = NULL;
2452 adapter->vfs_allocated_count = 0;
2453 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2454 wrfl();
2455 msleep(100);
2456 dev_info(&pdev->dev, "IOV Disabled\n");
2457
2458 /* Re-enable DMA Coalescing flag since IOV is turned off */
2459 adapter->flags |= IGB_FLAG_DMAC;
2460 }
2461
2462 return 0;
2463}
2464
2465static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2466{
2467 struct net_device *netdev = pci_get_drvdata(pdev);
2468 struct igb_adapter *adapter = netdev_priv(netdev);
2469 int old_vfs = pci_num_vf(pdev);
2470 int err = 0;
2471 int i;
2472
781798a1 2473 if (!adapter->msix_entries || num_vfs > 7) {
50267196
MW		 2474 err = -EPERM;
2475 goto out;
2476 }
fa44f2f1
GR		 2477 if (!num_vfs)
2478 goto out;
fa44f2f1 2479
781798a1
SA		 2480 if (old_vfs) {
2481 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2482 old_vfs, max_vfs);
2483 adapter->vfs_allocated_count = old_vfs;
2484 } else
2485 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2486
2487 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2488 sizeof(struct vf_data_storage), GFP_KERNEL);
2489
2490 /* if allocation failed then we do not support SR-IOV */
2491 if (!adapter->vf_data) {
2492 adapter->vfs_allocated_count = 0;
2493 dev_err(&pdev->dev,
2494 "Unable to allocate memory for VF Data Storage\n");
2495 err = -ENOMEM;
2496 goto out;
2497 }
2498
781798a1
SA		 2499 /* only call pci_enable_sriov() if no VFs are allocated already */
2500 if (!old_vfs) {
2501 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2502 if (err)
2503 goto err_out;
2504 }
fa44f2f1
GR		 2505 dev_info(&pdev->dev, "%d VFs allocated\n",
2506 adapter->vfs_allocated_count);
2507 for (i = 0; i < adapter->vfs_allocated_count; i++)
2508 igb_vf_configure(adapter, i);
2509
2510 /* DMA Coalescing is not supported in IOV mode. */
2511 adapter->flags &= ~IGB_FLAG_DMAC;
2512 goto out;
2513
2514err_out:
2515 kfree(adapter->vf_data);
2516 adapter->vf_data = NULL;
2517 adapter->vfs_allocated_count = 0;
2518out:
2519 return err;
2520}
2521
2522#endif
b980ac18 2523/**
441fc6fd
CW		 2524 * igb_remove_i2c - Cleanup I2C interface
2525 * @adapter: pointer to adapter structure
b980ac18 2526 **/
441fc6fd
CW		 2527static void igb_remove_i2c(struct igb_adapter *adapter)
2528{
441fc6fd
CW		 2529 /* free the adapter bus structure */
2530 i2c_del_adapter(&adapter->i2c_adap);
2531}
2532
9d5c8243 2533/**
b980ac18
JK		 2534 * igb_remove - Device Removal Routine
2535 * @pdev: PCI device information struct
9d5c8243 2536 *
b980ac18
JK		 2537 * igb_remove is called by the PCI subsystem to alert the driver
2538 * that it should release a PCI device. The could be caused by a
2539 * Hot-Plug event, or because the driver is going to be removed from
2540 * memory.
9d5c8243 2541 **/
9f9a12f8 2542static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2543{
2544 struct net_device *netdev = pci_get_drvdata(pdev);
2545 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2546 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2547
749ab2cd 2548 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2549#ifdef CONFIG_IGB_HWMON
2550 igb_sysfs_exit(adapter);
2551#endif
441fc6fd 2552 igb_remove_i2c(adapter);
a79f4f88 2553 igb_ptp_stop(adapter);
b980ac18 2554 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2555 * disable watchdog from being rescheduled.
2556 */
9d5c8243
AK		 2557 set_bit(__IGB_DOWN, &adapter->state);
2558 del_timer_sync(&adapter->watchdog_timer);
2559 del_timer_sync(&adapter->phy_info_timer);
2560
760141a5
TH		 2561 cancel_work_sync(&adapter->reset_task);
2562 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2563
421e02f0 2564#ifdef CONFIG_IGB_DCA
7dfc16fa 2565 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2566 dev_info(&pdev->dev, "DCA disabled\n");
2567 dca_remove_requester(&pdev->dev);
7dfc16fa 2568 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2569 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2570 }
2571#endif
2572
9d5c8243 2573 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2574 * would have already happened in close and is redundant.
2575 */
9d5c8243
AK		 2576 igb_release_hw_control(adapter);
2577
2578 unregister_netdev(netdev);
2579
047e0030 2580 igb_clear_interrupt_scheme(adapter);
9d5c8243 2581
37680117 2582#ifdef CONFIG_PCI_IOV
fa44f2f1 2583 igb_disable_sriov(pdev);
37680117 2584#endif
559e9c49 2585
28b0759c
AD		 2586 iounmap(hw->hw_addr);
2587 if (hw->flash_address)
2588 iounmap(hw->flash_address);
559e9c49 2589 pci_release_selected_regions(pdev,
b980ac18 2590 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2591
1128c756 2592 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2593 free_netdev(netdev);
2594
19d5afd4 2595 pci_disable_pcie_error_reporting(pdev);
40a914fa 2596
9d5c8243
AK		 2597 pci_disable_device(pdev);
2598}
2599
a6b623e0 2600/**
b980ac18
JK		 2601 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2602 * @adapter: board private structure to initialize
a6b623e0 2603 *
b980ac18
JK		 2604 * This function initializes the vf specific data storage and then attempts to
2605 * allocate the VFs. The reason for ordering it this way is because it is much
2606 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2607 * the memory for the VFs.
a6b623e0 2608 **/
9f9a12f8 2609static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2610{
2611#ifdef CONFIG_PCI_IOV
2612 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2613 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2614
f96a8a0b
CW		 2615 /* Virtualization features not supported on i210 family. */
2616 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2617 return;
2618
fa44f2f1 2619 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2620 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2621
a6b623e0
AD		 2622#endif /* CONFIG_PCI_IOV */
2623}
2624
fa44f2f1 2625static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2626{
2627 struct e1000_hw *hw = &adapter->hw;
374a542d 2628 u32 max_rss_queues;
9d5c8243 2629
374a542d 2630 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2631 switch (hw->mac.type) {
374a542d
MV		 2632 case e1000_i211:
2633 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2634 break;
2635 case e1000_82575:
f96a8a0b 2636 case e1000_i210:
374a542d
MV		 2637 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2638 break;
2639 case e1000_i350:
2640 /* I350 cannot do RSS and SR-IOV at the same time */
2641 if (!!adapter->vfs_allocated_count) {
2642 max_rss_queues = 1;
2643 break;
2644 }
2645 /* fall through */
2646 case e1000_82576:
2647 if (!!adapter->vfs_allocated_count) {
2648 max_rss_queues = 2;
2649 break;
2650 }
2651 /* fall through */
2652 case e1000_82580:
ceb5f13b 2653 case e1000_i354:
374a542d
MV		 2654 default:
2655 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2656 break;
374a542d
MV		 2657 }
2658
2659 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2660
2661 /* Determine if we need to pair queues. */
2662 switch (hw->mac.type) {
2663 case e1000_82575:
f96a8a0b 2664 case e1000_i211:
374a542d 2665 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2666 break;
374a542d 2667 case e1000_82576:
b980ac18 2668 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2669 * should pair the queues in order to conserve interrupts due
2670 * to limited supply.
2671 */
2672 if ((adapter->rss_queues > 1) &&
2673 (adapter->vfs_allocated_count > 6))
2674 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2675 /* fall through */
2676 case e1000_82580:
2677 case e1000_i350:
ceb5f13b 2678 case e1000_i354:
374a542d 2679 case e1000_i210:
f96a8a0b 2680 default:
b980ac18 2681 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2682 * order to conserve interrupts due to limited supply.
2683 */
2684 if (adapter->rss_queues > (max_rss_queues / 2))
2685 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2686 break;
2687 }
fa44f2f1
GR		 2688}
2689
2690/**
b980ac18
JK		 2691 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2692 * @adapter: board private structure to initialize
fa44f2f1 2693 *
b980ac18
JK		 2694 * igb_sw_init initializes the Adapter private data structure.
2695 * Fields are initialized based on PCI device information and
2696 * OS network device settings (MTU size).
fa44f2f1
GR		 2697 **/
2698static int igb_sw_init(struct igb_adapter *adapter)
2699{
2700 struct e1000_hw *hw = &adapter->hw;
2701 struct net_device *netdev = adapter->netdev;
2702 struct pci_dev *pdev = adapter->pdev;
2703
2704 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2705
2706 /* set default ring sizes */
2707 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2708 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2709
2710 /* set default ITR values */
2711 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2712 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2713
2714 /* set default work limits */
2715 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2716
2717 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2718 VLAN_HLEN;
2719 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2720
2721 spin_lock_init(&adapter->stats64_lock);
2722#ifdef CONFIG_PCI_IOV
2723 switch (hw->mac.type) {
2724 case e1000_82576:
2725 case e1000_i350:
2726 if (max_vfs > 7) {
2727 dev_warn(&pdev->dev,
2728 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2729 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2730 } else
2731 adapter->vfs_allocated_count = max_vfs;
2732 if (adapter->vfs_allocated_count)
2733 dev_warn(&pdev->dev,
2734 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2735 break;
2736 default:
2737 break;
2738 }
2739#endif /* CONFIG_PCI_IOV */
2740
2741 igb_init_queue_configuration(adapter);
a99955fc 2742
1128c756 2743 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2744 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2745 GFP_ATOMIC);
1128c756 2746
a6b623e0 2747 /* This call may decrease the number of queues */
53c7d064 2748 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2749 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2750 return -ENOMEM;
2751 }
2752
a6b623e0
AD		 2753 igb_probe_vfs(adapter);
2754
9d5c8243
AK		 2755 /* Explicitly disable IRQ since the NIC can be in any state. */
2756 igb_irq_disable(adapter);
2757
f96a8a0b 2758 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2759 adapter->flags &= ~IGB_FLAG_DMAC;
2760
9d5c8243
AK		 2761 set_bit(__IGB_DOWN, &adapter->state);
2762 return 0;
2763}
2764
2765/**
b980ac18
JK		 2766 * igb_open - Called when a network interface is made active
2767 * @netdev: network interface device structure
9d5c8243 2768 *
b980ac18 2769 * Returns 0 on success, negative value on failure
9d5c8243 2770 *
b980ac18
JK		 2771 * The open entry point is called when a network interface is made
2772 * active by the system (IFF_UP). At this point all resources needed
2773 * for transmit and receive operations are allocated, the interrupt
2774 * handler is registered with the OS, the watchdog timer is started,
2775 * and the stack is notified that the interface is ready.
9d5c8243 2776 **/
749ab2cd 2777static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2778{
2779 struct igb_adapter *adapter = netdev_priv(netdev);
2780 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2781 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2782 int err;
2783 int i;
2784
2785 /* disallow open during test */
749ab2cd
YZ		 2786 if (test_bit(__IGB_TESTING, &adapter->state)) {
2787 WARN_ON(resuming);
9d5c8243 2788 return -EBUSY;
749ab2cd
YZ		 2789 }
2790
2791 if (!resuming)
2792 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2793
b168dfc5
JB		 2794 netif_carrier_off(netdev);
2795
9d5c8243
AK		 2796 /* allocate transmit descriptors */
2797 err = igb_setup_all_tx_resources(adapter);
2798 if (err)
2799 goto err_setup_tx;
2800
2801 /* allocate receive descriptors */
2802 err = igb_setup_all_rx_resources(adapter);
2803 if (err)
2804 goto err_setup_rx;
2805
88a268c1 2806 igb_power_up_link(adapter);
9d5c8243 2807
9d5c8243
AK		 2808 /* before we allocate an interrupt, we must be ready to handle it.
2809 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2810 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2811 * clean_rx handler before we do so.
2812 */
9d5c8243
AK		 2813 igb_configure(adapter);
2814
2815 err = igb_request_irq(adapter);
2816 if (err)
2817 goto err_req_irq;
2818
0c2cc02e
AD		 2819 /* Notify the stack of the actual queue counts. */
2820 err = netif_set_real_num_tx_queues(adapter->netdev,
2821 adapter->num_tx_queues);
2822 if (err)
2823 goto err_set_queues;
2824
2825 err = netif_set_real_num_rx_queues(adapter->netdev,
2826 adapter->num_rx_queues);
2827 if (err)
2828 goto err_set_queues;
2829
9d5c8243
AK		 2830 /* From here on the code is the same as igb_up() */
2831 clear_bit(__IGB_DOWN, &adapter->state);
2832
0d1ae7f4
AD		 2833 for (i = 0; i < adapter->num_q_vectors; i++)
2834 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2835
2836 /* Clear any pending interrupts. */
2837 rd32(E1000_ICR);
844290e5
PW		 2838
2839 igb_irq_enable(adapter);
2840
d4960307
AD		 2841 /* notify VFs that reset has been completed */
2842 if (adapter->vfs_allocated_count) {
2843 u32 reg_data = rd32(E1000_CTRL_EXT);
2844 reg_data |= E1000_CTRL_EXT_PFRSTD;
2845 wr32(E1000_CTRL_EXT, reg_data);
2846 }
2847
d55b53ff
JK		 2848 netif_tx_start_all_queues(netdev);
2849
749ab2cd
YZ		 2850 if (!resuming)
2851 pm_runtime_put(&pdev->dev);
2852
25568a53
AD		 2853 /* start the watchdog. */
2854 hw->mac.get_link_status = 1;
2855 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2856
2857 return 0;
2858
0c2cc02e
AD		 2859err_set_queues:
2860 igb_free_irq(adapter);
9d5c8243
AK		 2861err_req_irq:
2862 igb_release_hw_control(adapter);
88a268c1 2863 igb_power_down_link(adapter);
9d5c8243
AK		 2864 igb_free_all_rx_resources(adapter);
2865err_setup_rx:
2866 igb_free_all_tx_resources(adapter);
2867err_setup_tx:
2868 igb_reset(adapter);
749ab2cd
YZ		 2869 if (!resuming)
2870 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2871
2872 return err;
2873}
2874
749ab2cd
YZ		 2875static int igb_open(struct net_device *netdev)
2876{
2877 return __igb_open(netdev, false);
2878}
2879
9d5c8243 2880/**
b980ac18
JK		 2881 * igb_close - Disables a network interface
2882 * @netdev: network interface device structure
9d5c8243 2883 *
b980ac18 2884 * Returns 0, this is not allowed to fail
9d5c8243 2885 *
b980ac18
JK		 2886 * The close entry point is called when an interface is de-activated
2887 * by the OS. The hardware is still under the driver's control, but
2888 * needs to be disabled. A global MAC reset is issued to stop the
2889 * hardware, and all transmit and receive resources are freed.
9d5c8243 2890 **/
749ab2cd 2891static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2892{
2893 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2894 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2895
2896 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2897
749ab2cd
YZ		 2898 if (!suspending)
2899 pm_runtime_get_sync(&pdev->dev);
2900
2901 igb_down(adapter);
9d5c8243
AK		 2902 igb_free_irq(adapter);
2903
2904 igb_free_all_tx_resources(adapter);
2905 igb_free_all_rx_resources(adapter);
2906
749ab2cd
YZ		 2907 if (!suspending)
2908 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2909 return 0;
2910}
2911
749ab2cd
YZ		 2912static int igb_close(struct net_device *netdev)
2913{
2914 return __igb_close(netdev, false);
2915}
2916
9d5c8243 2917/**
b980ac18
JK		 2918 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2919 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2920 *
b980ac18 2921 * Return 0 on success, negative on failure
9d5c8243 2922 **/
80785298 2923int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2924{
59d71989 2925 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2926 int size;
2927
06034649 2928 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2929
2930 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2931 if (!tx_ring->tx_buffer_info)
9d5c8243 2932 goto err;
9d5c8243
AK		 2933
2934 /* round up to nearest 4K */
85e8d004 2935 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2936 tx_ring->size = ALIGN(tx_ring->size, 4096);
2937
5536d210
AD		 2938 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2939 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2940 if (!tx_ring->desc)
2941 goto err;
2942
9d5c8243
AK		 2943 tx_ring->next_to_use = 0;
2944 tx_ring->next_to_clean = 0;
81c2fc22 2945
9d5c8243
AK		 2946 return 0;
2947
2948err:
06034649 2949 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2950 tx_ring->tx_buffer_info = NULL;
2951 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2952 return -ENOMEM;
2953}
2954
2955/**
b980ac18
JK		 2956 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2957 * (Descriptors) for all queues
2958 * @adapter: board private structure
9d5c8243 2959 *
b980ac18 2960 * Return 0 on success, negative on failure
9d5c8243
AK		 2961 **/
2962static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2963{
439705e1 2964 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2965 int i, err = 0;
2966
2967 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2968 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2969 if (err) {
439705e1 2970 dev_err(&pdev->dev,
9d5c8243
AK		 2971 "Allocation for Tx Queue %u failed\n", i);
2972 for (i--; i >= 0; i--)
3025a446 2973 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2974 break;
2975 }
2976 }
2977
2978 return err;
2979}
2980
2981/**
b980ac18
JK		 2982 * igb_setup_tctl - configure the transmit control registers
2983 * @adapter: Board private structure
9d5c8243 2984 **/
d7ee5b3a 2985void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2986{
9d5c8243
AK		 2987 struct e1000_hw *hw = &adapter->hw;
2988 u32 tctl;
9d5c8243 2989
85b430b4
AD		 2990 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2991 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2992
2993 /* Program the Transmit Control Register */
9d5c8243
AK		 2994 tctl = rd32(E1000_TCTL);
2995 tctl &= ~E1000_TCTL_CT;
2996 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2997 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2998
2999 igb_config_collision_dist(hw);
3000
9d5c8243
AK		 3001 /* Enable transmits */
3002 tctl |= E1000_TCTL_EN;
3003
3004 wr32(E1000_TCTL, tctl);
3005}
3006
85b430b4 3007/**
b980ac18
JK		 3008 * igb_configure_tx_ring - Configure transmit ring after Reset
3009 * @adapter: board private structure
3010 * @ring: tx ring to configure
85b430b4 3011 *
b980ac18 3012 * Configure a transmit ring after a reset.
85b430b4 3013 **/
d7ee5b3a
AD		 3014void igb_configure_tx_ring(struct igb_adapter *adapter,
3015 struct igb_ring *ring)
85b430b4
AD		 3016{
3017 struct e1000_hw *hw = &adapter->hw;
a74420e0 3018 u32 txdctl = 0;
85b430b4
AD		 3019 u64 tdba = ring->dma;
3020 int reg_idx = ring->reg_idx;
3021
3022 /* disable the queue */
a74420e0 3023 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3024 wrfl();
3025 mdelay(10);
3026
3027 wr32(E1000_TDLEN(reg_idx),
b980ac18 3028 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3029 wr32(E1000_TDBAL(reg_idx),
b980ac18 3030 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3031 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3032
fce99e34 3033 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3034 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3035 writel(0, ring->tail);
85b430b4
AD		 3036
3037 txdctl |= IGB_TX_PTHRESH;
3038 txdctl |= IGB_TX_HTHRESH << 8;
3039 txdctl |= IGB_TX_WTHRESH << 16;
3040
3041 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3042 wr32(E1000_TXDCTL(reg_idx), txdctl);
3043}
3044
3045/**
b980ac18
JK		 3046 * igb_configure_tx - Configure transmit Unit after Reset
3047 * @adapter: board private structure
85b430b4 3048 *
b980ac18 3049 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3050 **/
3051static void igb_configure_tx(struct igb_adapter *adapter)
3052{
3053 int i;
3054
3055 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3056 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3057}
3058
9d5c8243 3059/**
b980ac18
JK		 3060 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3061 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3062 *
b980ac18 3063 * Returns 0 on success, negative on failure
9d5c8243 3064 **/
80785298 3065int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3066{
59d71989 3067 struct device *dev = rx_ring->dev;
f33005a6 3068 int size;
9d5c8243 3069
06034649 3070 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3071
3072 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3073 if (!rx_ring->rx_buffer_info)
9d5c8243 3074 goto err;
9d5c8243 3075
9d5c8243 3076 /* Round up to nearest 4K */
f33005a6 3077 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3078 rx_ring->size = ALIGN(rx_ring->size, 4096);
3079
5536d210
AD		 3080 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3081 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3082 if (!rx_ring->desc)
3083 goto err;
3084
cbc8e55f 3085 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3086 rx_ring->next_to_clean = 0;
3087 rx_ring->next_to_use = 0;
9d5c8243 3088
9d5c8243
AK		 3089 return 0;
3090
3091err:
06034649
AD		 3092 vfree(rx_ring->rx_buffer_info);
3093 rx_ring->rx_buffer_info = NULL;
f33005a6 3094 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3095 return -ENOMEM;
3096}
3097
3098/**
b980ac18
JK		 3099 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3100 * (Descriptors) for all queues
3101 * @adapter: board private structure
9d5c8243 3102 *
b980ac18 3103 * Return 0 on success, negative on failure
9d5c8243
AK		 3104 **/
3105static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3106{
439705e1 3107 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3108 int i, err = 0;
3109
3110 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3111 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3112 if (err) {
439705e1 3113 dev_err(&pdev->dev,
9d5c8243
AK		 3114 "Allocation for Rx Queue %u failed\n", i);
3115 for (i--; i >= 0; i--)
3025a446 3116 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3117 break;
3118 }
3119 }
3120
3121 return err;
3122}
3123
06cf2666 3124/**
b980ac18
JK		 3125 * igb_setup_mrqc - configure the multiple receive queue control registers
3126 * @adapter: Board private structure
06cf2666
AD		 3127 **/
3128static void igb_setup_mrqc(struct igb_adapter *adapter)
3129{
3130 struct e1000_hw *hw = &adapter->hw;
3131 u32 mrqc, rxcsum;
ed12cc9a 3132 u32 j, num_rx_queues;
a57fe23e
AD		 3133 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3134 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3135 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3136 0xFA01ACBE };
06cf2666
AD		 3137
3138 /* Fill out hash function seeds */
a57fe23e
AD		 3139 for (j = 0; j < 10; j++)
3140 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3141
a99955fc 3142 num_rx_queues = adapter->rss_queues;
06cf2666 3143
797fd4be 3144 switch (hw->mac.type) {
797fd4be
AD		 3145 case e1000_82576:
3146 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3147 if (adapter->vfs_allocated_count)
06cf2666 3148 num_rx_queues = 2;
797fd4be
AD		 3149 break;
3150 default:
3151 break;
06cf2666
AD		 3152 }
3153
ed12cc9a
LMV		 3154 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3155 for (j = 0; j < IGB_RETA_SIZE; j++)
3156 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3157 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3158 }
ed12cc9a 3159 igb_write_rss_indir_tbl(adapter);
06cf2666 3160
b980ac18 3161 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3162 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3163 * offloads as they are enabled by default
3164 */
3165 rxcsum = rd32(E1000_RXCSUM);
3166 rxcsum |= E1000_RXCSUM_PCSD;
3167
3168 if (adapter->hw.mac.type >= e1000_82576)
3169 /* Enable Receive Checksum Offload for SCTP */
3170 rxcsum |= E1000_RXCSUM_CRCOFL;
3171
3172 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3173 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3174
039454a8
AA		 3175 /* Generate RSS hash based on packet types, TCP/UDP
3176 * port numbers and/or IPv4/v6 src and dst addresses
3177 */
f96a8a0b
CW		 3178 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3179 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3180 E1000_MRQC_RSS_FIELD_IPV6 |
3181 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3182 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3183
039454a8
AA		 3184 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3185 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3186 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3187 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3188
06cf2666
AD		 3189 /* If VMDq is enabled then we set the appropriate mode for that, else
3190 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3191 * if we are only using one queue
3192 */
06cf2666
AD		 3193 if (adapter->vfs_allocated_count) {
3194 if (hw->mac.type > e1000_82575) {
3195 /* Set the default pool for the PF's first queue */
3196 u32 vtctl = rd32(E1000_VT_CTL);
3197 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3198 E1000_VT_CTL_DISABLE_DEF_POOL);
3199 vtctl |= adapter->vfs_allocated_count <<
3200 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3201 wr32(E1000_VT_CTL, vtctl);
3202 }
a99955fc 3203 if (adapter->rss_queues > 1)
f96a8a0b 3204 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3205 else
f96a8a0b 3206 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3207 } else {
f96a8a0b
CW		 3208 if (hw->mac.type != e1000_i211)
3209 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3210 }
3211 igb_vmm_control(adapter);
3212
06cf2666
AD		 3213 wr32(E1000_MRQC, mrqc);
3214}
3215
9d5c8243 3216/**
b980ac18
JK		 3217 * igb_setup_rctl - configure the receive control registers
3218 * @adapter: Board private structure
9d5c8243 3219 **/
d7ee5b3a 3220void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3221{
3222 struct e1000_hw *hw = &adapter->hw;
3223 u32 rctl;
9d5c8243
AK		 3224
3225 rctl = rd32(E1000_RCTL);
3226
3227 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3228 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3229
69d728ba 3230 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3231 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3232
b980ac18 3233 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3234 * redirection as it did with e1000. Newer features require
3235 * that the HW strips the CRC.
73cd78f1 3236 */
87cb7e8c 3237 rctl |= E1000_RCTL_SECRC;
9d5c8243 3238
559e9c49 3239 /* disable store bad packets and clear size bits. */
ec54d7d6 3240 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3241
6ec43fe6
AD		 3242 /* enable LPE to prevent packets larger than max_frame_size */
3243 rctl |= E1000_RCTL_LPE;
9d5c8243 3244
952f72a8
AD		 3245 /* disable queue 0 to prevent tail write w/o re-config */
3246 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3247
e1739522
AD		 3248 /* Attention!!! For SR-IOV PF driver operations you must enable
3249 * queue drop for all VF and PF queues to prevent head of line blocking
3250 * if an un-trusted VF does not provide descriptors to hardware.
3251 */
3252 if (adapter->vfs_allocated_count) {
e1739522
AD		 3253 /* set all queue drop enable bits */
3254 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3255 }
3256
89eaefb6
BG		 3257 /* This is useful for sniffing bad packets. */
3258 if (adapter->netdev->features & NETIF_F_RXALL) {
3259 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3260 * in e1000e_set_rx_mode
3261 */
89eaefb6
BG		 3262 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3263 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3264 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3265
3266 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3267 E1000_RCTL_DPF | /* Allow filtered pause */
3268 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3269 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3270 * and that breaks VLANs.
3271 */
3272 }
3273
9d5c8243
AK		 3274 wr32(E1000_RCTL, rctl);
3275}
3276
7d5753f0
AD		 3277static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3278 int vfn)
3279{
3280 struct e1000_hw *hw = &adapter->hw;
3281 u32 vmolr;
3282
3283 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3284 * increase the size to support vlan tags
3285 */
7d5753f0
AD		 3286 if (vfn < adapter->vfs_allocated_count &&
3287 adapter->vf_data[vfn].vlans_enabled)
3288 size += VLAN_TAG_SIZE;
3289
3290 vmolr = rd32(E1000_VMOLR(vfn));
3291 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3292 vmolr |= size | E1000_VMOLR_LPE;
3293 wr32(E1000_VMOLR(vfn), vmolr);
3294
3295 return 0;
3296}
3297
e1739522 3298/**
b980ac18
JK		 3299 * igb_rlpml_set - set maximum receive packet size
3300 * @adapter: board private structure
e1739522 3301 *
b980ac18 3302 * Configure maximum receivable packet size.
e1739522
AD		 3303 **/
3304static void igb_rlpml_set(struct igb_adapter *adapter)
3305{
153285f9 3306 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3307 struct e1000_hw *hw = &adapter->hw;
3308 u16 pf_id = adapter->vfs_allocated_count;
3309
e1739522
AD		 3310 if (pf_id) {
3311 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3312 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3313 * to our max jumbo frame size, in case we need to enable
3314 * jumbo frames on one of the rings later.
3315 * This will not pass over-length frames into the default
3316 * queue because it's gated by the VMOLR.RLPML.
3317 */
7d5753f0 3318 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3319 }
3320
3321 wr32(E1000_RLPML, max_frame_size);
3322}
3323
8151d294
WM		 3324static inline void igb_set_vmolr(struct igb_adapter *adapter,
3325 int vfn, bool aupe)
7d5753f0
AD		 3326{
3327 struct e1000_hw *hw = &adapter->hw;
3328 u32 vmolr;
3329
b980ac18 3330 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3331 * we should exit and do nothing
3332 */
3333 if (hw->mac.type < e1000_82576)
3334 return;
3335
3336 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3337 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3338 if (aupe)
b980ac18 3339 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3340 else
3341 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3342
3343 /* clear all bits that might not be set */
3344 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3345
a99955fc 3346 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3347 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3348 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3349 * multicast packets
3350 */
3351 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3352 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3353
3354 wr32(E1000_VMOLR(vfn), vmolr);
3355}
3356
85b430b4 3357/**
b980ac18
JK		 3358 * igb_configure_rx_ring - Configure a receive ring after Reset
3359 * @adapter: board private structure
3360 * @ring: receive ring to be configured
85b430b4 3361 *
b980ac18 3362 * Configure the Rx unit of the MAC after a reset.
85b430b4 3363 **/
d7ee5b3a 3364void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3365 struct igb_ring *ring)
85b430b4
AD		 3366{
3367 struct e1000_hw *hw = &adapter->hw;
3368 u64 rdba = ring->dma;
3369 int reg_idx = ring->reg_idx;
a74420e0 3370 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3371
3372 /* disable the queue */
a74420e0 3373 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3374
3375 /* Set DMA base address registers */
3376 wr32(E1000_RDBAL(reg_idx),
3377 rdba & 0x00000000ffffffffULL);
3378 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3379 wr32(E1000_RDLEN(reg_idx),
b980ac18 3380 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3381
3382 /* initialize head and tail */
fce99e34 3383 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3384 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3385 writel(0, ring->tail);
85b430b4 3386
952f72a8 3387 /* set descriptor configuration */
44390ca6 3388 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3389 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3390 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3391 if (hw->mac.type >= e1000_82580)
757b77e2 3392 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3393 /* Only set Drop Enable if we are supporting multiple queues */
3394 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3395 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3396
3397 wr32(E1000_SRRCTL(reg_idx), srrctl);
3398
7d5753f0 3399 /* set filtering for VMDQ pools */
8151d294 3400 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3401
85b430b4
AD		 3402 rxdctl |= IGB_RX_PTHRESH;
3403 rxdctl |= IGB_RX_HTHRESH << 8;
3404 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3405
3406 /* enable receive descriptor fetching */
3407 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3408 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3409}
3410
9d5c8243 3411/**
b980ac18
JK		 3412 * igb_configure_rx - Configure receive Unit after Reset
3413 * @adapter: board private structure
9d5c8243 3414 *
b980ac18 3415 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3416 **/
3417static void igb_configure_rx(struct igb_adapter *adapter)
3418{
9107584e 3419 int i;
9d5c8243 3420
68d480c4
AD		 3421 /* set UTA to appropriate mode */
3422 igb_set_uta(adapter);
3423
26ad9178
AD		 3424 /* set the correct pool for the PF default MAC address in entry 0 */
3425 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3426 adapter->vfs_allocated_count);
26ad9178 3427
06cf2666 3428 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3429 * the Base and Length of the Rx Descriptor Ring
3430 */
f9d40f6a
AD		 3431 for (i = 0; i < adapter->num_rx_queues; i++)
3432 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3433}
3434
3435/**
b980ac18
JK		 3436 * igb_free_tx_resources - Free Tx Resources per Queue
3437 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3438 *
b980ac18 3439 * Free all transmit software resources
9d5c8243 3440 **/
68fd9910 3441void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3442{
3b644cf6 3443 igb_clean_tx_ring(tx_ring);
9d5c8243 3444
06034649
AD		 3445 vfree(tx_ring->tx_buffer_info);
3446 tx_ring->tx_buffer_info = NULL;
9d5c8243 3447
439705e1
AD		 3448 /* if not set, then don't free */
3449 if (!tx_ring->desc)
3450 return;
3451
59d71989
AD		 3452 dma_free_coherent(tx_ring->dev, tx_ring->size,
3453 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3454
3455 tx_ring->desc = NULL;
3456}
3457
3458/**
b980ac18
JK		 3459 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3460 * @adapter: board private structure
9d5c8243 3461 *
b980ac18 3462 * Free all transmit software resources
9d5c8243
AK		 3463 **/
3464static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3465{
3466 int i;
3467
3468 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3469 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3470}
3471
ebe42d16
AD		 3472void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3473 struct igb_tx_buffer *tx_buffer)
3474{
3475 if (tx_buffer->skb) {
3476 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3477 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3478 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3479 dma_unmap_addr(tx_buffer, dma),
3480 dma_unmap_len(tx_buffer, len),
ebe42d16 3481 DMA_TO_DEVICE);
c9f14bf3 3482 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3483 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3484 dma_unmap_addr(tx_buffer, dma),
3485 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3486 DMA_TO_DEVICE);
3487 }
3488 tx_buffer->next_to_watch = NULL;
3489 tx_buffer->skb = NULL;
c9f14bf3 3490 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3491 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3492}
3493
3494/**
b980ac18
JK		 3495 * igb_clean_tx_ring - Free Tx Buffers
3496 * @tx_ring: ring to be cleaned
9d5c8243 3497 **/
3b644cf6 3498static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3499{
06034649 3500 struct igb_tx_buffer *buffer_info;
9d5c8243 3501 unsigned long size;
6ad4edfc 3502 u16 i;
9d5c8243 3503
06034649 3504 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3505 return;
3506 /* Free all the Tx ring sk_buffs */
3507
3508 for (i = 0; i < tx_ring->count; i++) {
06034649 3509 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3510 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3511 }
3512
dad8a3b3
JF		 3513 netdev_tx_reset_queue(txring_txq(tx_ring));
3514
06034649
AD		 3515 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3516 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3517
3518 /* Zero out the descriptor ring */
9d5c8243
AK		 3519 memset(tx_ring->desc, 0, tx_ring->size);
3520
3521 tx_ring->next_to_use = 0;
3522 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3523}
3524
3525/**
b980ac18
JK		 3526 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3527 * @adapter: board private structure
9d5c8243
AK		 3528 **/
3529static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3530{
3531 int i;
3532
3533 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3534 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3535}
3536
3537/**
b980ac18
JK		 3538 * igb_free_rx_resources - Free Rx Resources
3539 * @rx_ring: ring to clean the resources from
9d5c8243 3540 *
b980ac18 3541 * Free all receive software resources
9d5c8243 3542 **/
68fd9910 3543void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3544{
3b644cf6 3545 igb_clean_rx_ring(rx_ring);
9d5c8243 3546
06034649
AD		 3547 vfree(rx_ring->rx_buffer_info);
3548 rx_ring->rx_buffer_info = NULL;
9d5c8243 3549
439705e1
AD		 3550 /* if not set, then don't free */
3551 if (!rx_ring->desc)
3552 return;
3553
59d71989
AD		 3554 dma_free_coherent(rx_ring->dev, rx_ring->size,
3555 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3556
3557 rx_ring->desc = NULL;
3558}
3559
3560/**
b980ac18
JK		 3561 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3562 * @adapter: board private structure
9d5c8243 3563 *
b980ac18 3564 * Free all receive software resources
9d5c8243
AK		 3565 **/
3566static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3567{
3568 int i;
3569
3570 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3571 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3572}
3573
3574/**
b980ac18
JK		 3575 * igb_clean_rx_ring - Free Rx Buffers per Queue
3576 * @rx_ring: ring to free buffers from
9d5c8243 3577 **/
3b644cf6 3578static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3579{
9d5c8243 3580 unsigned long size;
c023cd88 3581 u16 i;
9d5c8243 3582
1a1c225b
AD		 3583 if (rx_ring->skb)
3584 dev_kfree_skb(rx_ring->skb);
3585 rx_ring->skb = NULL;
3586
06034649 3587 if (!rx_ring->rx_buffer_info)
9d5c8243 3588 return;
439705e1 3589
9d5c8243
AK		 3590 /* Free all the Rx ring sk_buffs */
3591 for (i = 0; i < rx_ring->count; i++) {
06034649 3592 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3593
cbc8e55f
AD		 3594 if (!buffer_info->page)
3595 continue;
3596
3597 dma_unmap_page(rx_ring->dev,
3598 buffer_info->dma,
3599 PAGE_SIZE,
3600 DMA_FROM_DEVICE);
3601 __free_page(buffer_info->page);
3602
1a1c225b 3603 buffer_info->page = NULL;
9d5c8243
AK		 3604 }
3605
06034649
AD		 3606 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3607 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3608
3609 /* Zero out the descriptor ring */
3610 memset(rx_ring->desc, 0, rx_ring->size);
3611
cbc8e55f 3612 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3613 rx_ring->next_to_clean = 0;
3614 rx_ring->next_to_use = 0;
9d5c8243
AK		 3615}
3616
3617/**
b980ac18
JK		 3618 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3619 * @adapter: board private structure
9d5c8243
AK		 3620 **/
3621static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3622{
3623 int i;
3624
3625 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3626 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3627}
3628
3629/**
b980ac18
JK		 3630 * igb_set_mac - Change the Ethernet Address of the NIC
3631 * @netdev: network interface device structure
3632 * @p: pointer to an address structure
9d5c8243 3633 *
b980ac18 3634 * Returns 0 on success, negative on failure
9d5c8243
AK		 3635 **/
3636static int igb_set_mac(struct net_device *netdev, void *p)
3637{
3638 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3639 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3640 struct sockaddr *addr = p;
3641
3642 if (!is_valid_ether_addr(addr->sa_data))
3643 return -EADDRNOTAVAIL;
3644
3645 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3646 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3647
26ad9178
AD		 3648 /* set the correct pool for the new PF MAC address in entry 0 */
3649 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3650 adapter->vfs_allocated_count);
e1739522 3651
9d5c8243
AK		 3652 return 0;
3653}
3654
3655/**
b980ac18
JK		 3656 * igb_write_mc_addr_list - write multicast addresses to MTA
3657 * @netdev: network interface device structure
9d5c8243 3658 *
b980ac18
JK		 3659 * Writes multicast address list to the MTA hash table.
3660 * Returns: -ENOMEM on failure
3661 * 0 on no addresses written
3662 * X on writing X addresses to MTA
9d5c8243 3663 **/
68d480c4 3664static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3665{
3666 struct igb_adapter *adapter = netdev_priv(netdev);
3667 struct e1000_hw *hw = &adapter->hw;
22bedad3 3668 struct netdev_hw_addr *ha;
68d480c4 3669 u8 *mta_list;
9d5c8243
AK		 3670 int i;
3671
4cd24eaf 3672 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3673 /* nothing to program, so clear mc list */
3674 igb_update_mc_addr_list(hw, NULL, 0);
3675 igb_restore_vf_multicasts(adapter);
3676 return 0;
3677 }
9d5c8243 3678
4cd24eaf 3679 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3680 if (!mta_list)
3681 return -ENOMEM;
ff41f8dc 3682
68d480c4 3683 /* The shared function expects a packed array of only addresses. */
48e2f183 3684 i = 0;
22bedad3
JP		 3685 netdev_for_each_mc_addr(ha, netdev)
3686 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3687
68d480c4
AD		 3688 igb_update_mc_addr_list(hw, mta_list, i);
3689 kfree(mta_list);
3690
4cd24eaf 3691 return netdev_mc_count(netdev);
68d480c4
AD		 3692}
3693
3694/**
b980ac18
JK		 3695 * igb_write_uc_addr_list - write unicast addresses to RAR table
3696 * @netdev: network interface device structure
68d480c4 3697 *
b980ac18
JK		 3698 * Writes unicast address list to the RAR table.
3699 * Returns: -ENOMEM on failure/insufficient address space
3700 * 0 on no addresses written
3701 * X on writing X addresses to the RAR table
68d480c4
AD		 3702 **/
3703static int igb_write_uc_addr_list(struct net_device *netdev)
3704{
3705 struct igb_adapter *adapter = netdev_priv(netdev);
3706 struct e1000_hw *hw = &adapter->hw;
3707 unsigned int vfn = adapter->vfs_allocated_count;
3708 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3709 int count = 0;
3710
3711 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3712 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3713 return -ENOMEM;
9d5c8243 3714
32e7bfc4 3715 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3716 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3717
3718 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3719 if (!rar_entries)
3720 break;
26ad9178 3721 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3722 rar_entries--,
3723 vfn);
68d480c4 3724 count++;
ff41f8dc
AD		 3725 }
3726 }
3727 /* write the addresses in reverse order to avoid write combining */
3728 for (; rar_entries > 0 ; rar_entries--) {
3729 wr32(E1000_RAH(rar_entries), 0);
3730 wr32(E1000_RAL(rar_entries), 0);
3731 }
3732 wrfl();
3733
68d480c4
AD		 3734 return count;
3735}
3736
3737/**
b980ac18
JK		 3738 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3739 * @netdev: network interface device structure
68d480c4 3740 *
b980ac18
JK		 3741 * The set_rx_mode entry point is called whenever the unicast or multicast
3742 * address lists or the network interface flags are updated. This routine is
3743 * responsible for configuring the hardware for proper unicast, multicast,
3744 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3745 **/
3746static void igb_set_rx_mode(struct net_device *netdev)
3747{
3748 struct igb_adapter *adapter = netdev_priv(netdev);
3749 struct e1000_hw *hw = &adapter->hw;
3750 unsigned int vfn = adapter->vfs_allocated_count;
3751 u32 rctl, vmolr = 0;
3752 int count;
3753
3754 /* Check for Promiscuous and All Multicast modes */
3755 rctl = rd32(E1000_RCTL);
3756
3757 /* clear the effected bits */
3758 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3759
3760 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3761 /* retain VLAN HW filtering if in VT mode */
7e44892c 3762 if (adapter->vfs_allocated_count)
6f3dc319 3763 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3764 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3765 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3766 } else {
3767 if (netdev->flags & IFF_ALLMULTI) {
3768 rctl |= E1000_RCTL_MPE;
3769 vmolr |= E1000_VMOLR_MPME;
3770 } else {
b980ac18 3771 /* Write addresses to the MTA, if the attempt fails
25985edc 3772 * then we should just turn on promiscuous mode so
68d480c4
AD		 3773 * that we can at least receive multicast traffic
3774 */
3775 count = igb_write_mc_addr_list(netdev);
3776 if (count < 0) {
3777 rctl |= E1000_RCTL_MPE;
3778 vmolr |= E1000_VMOLR_MPME;
3779 } else if (count) {
3780 vmolr |= E1000_VMOLR_ROMPE;
3781 }
3782 }
b980ac18 3783 /* Write addresses to available RAR registers, if there is not
68d480c4 3784 * sufficient space to store all the addresses then enable
25985edc 3785 * unicast promiscuous mode
68d480c4
AD		 3786 */
3787 count = igb_write_uc_addr_list(netdev);
3788 if (count < 0) {
3789 rctl |= E1000_RCTL_UPE;
3790 vmolr |= E1000_VMOLR_ROPE;
3791 }
3792 rctl |= E1000_RCTL_VFE;
28fc06f5 3793 }
68d480c4 3794 wr32(E1000_RCTL, rctl);
28fc06f5 3795
b980ac18 3796 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3797 * the VMOLR to enable the appropriate modes. Without this workaround
3798 * we will have issues with VLAN tag stripping not being done for frames
3799 * that are only arriving because we are the default pool
3800 */
f96a8a0b 3801 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3802 return;
9d5c8243 3803
68d480c4 3804 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3805 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3806 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3807 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3808}
3809
13800469
GR		 3810static void igb_check_wvbr(struct igb_adapter *adapter)
3811{
3812 struct e1000_hw *hw = &adapter->hw;
3813 u32 wvbr = 0;
3814
3815 switch (hw->mac.type) {
3816 case e1000_82576:
3817 case e1000_i350:
3818 if (!(wvbr = rd32(E1000_WVBR)))
3819 return;
3820 break;
3821 default:
3822 break;
3823 }
3824
3825 adapter->wvbr |= wvbr;
3826}
3827
3828#define IGB_STAGGERED_QUEUE_OFFSET 8
3829
3830static void igb_spoof_check(struct igb_adapter *adapter)
3831{
3832 int j;
3833
3834 if (!adapter->wvbr)
3835 return;
3836
3837 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3838 if (adapter->wvbr & (1 << j) ||
3839 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3840 dev_warn(&adapter->pdev->dev,
3841 "Spoof event(s) detected on VF %d\n", j);
3842 adapter->wvbr &=
3843 ~((1 << j) |
3844 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3845 }
3846 }
3847}
3848
9d5c8243 3849/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3850 * the phy
3851 */
9d5c8243
AK		 3852static void igb_update_phy_info(unsigned long data)
3853{
3854 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3855 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3856}
3857
4d6b725e 3858/**
b980ac18
JK		 3859 * igb_has_link - check shared code for link and determine up/down
3860 * @adapter: pointer to driver private info
4d6b725e 3861 **/
3145535a 3862bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3863{
3864 struct e1000_hw *hw = &adapter->hw;
3865 bool link_active = false;
4d6b725e
AD		 3866
3867 /* get_link_status is set on LSC (link status) interrupt or
3868 * rx sequence error interrupt. get_link_status will stay
3869 * false until the e1000_check_for_link establishes link
3870 * for copper adapters ONLY
3871 */
3872 switch (hw->phy.media_type) {
3873 case e1000_media_type_copper:
e5c3370f
AA		 3874 if (!hw->mac.get_link_status)
3875 return true;
4d6b725e 3876 case e1000_media_type_internal_serdes:
e5c3370f
AA		 3877 hw->mac.ops.check_for_link(hw);
3878 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 3879 break;
3880 default:
3881 case e1000_media_type_unknown:
3882 break;
3883 }
3884
aa9b8cc4
AA		 3885 if (((hw->mac.type == e1000_i210) ||
3886 (hw->mac.type == e1000_i211)) &&
3887 (hw->phy.id == I210_I_PHY_ID)) {
3888 if (!netif_carrier_ok(adapter->netdev)) {
3889 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3890 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
3891 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
3892 adapter->link_check_timeout = jiffies;
3893 }
3894 }
3895
4d6b725e
AD		 3896 return link_active;
3897}
3898
563988dc
SA		 3899static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3900{
3901 bool ret = false;
3902 u32 ctrl_ext, thstat;
3903
f96a8a0b 3904 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3905 if (hw->mac.type == e1000_i350) {
3906 thstat = rd32(E1000_THSTAT);
3907 ctrl_ext = rd32(E1000_CTRL_EXT);
3908
3909 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3910 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3911 ret = !!(thstat & event);
563988dc
SA		 3912 }
3913
3914 return ret;
3915}
3916
9d5c8243 3917/**
b980ac18
JK		 3918 * igb_watchdog - Timer Call-back
3919 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3920 **/
3921static void igb_watchdog(unsigned long data)
3922{
3923 struct igb_adapter *adapter = (struct igb_adapter *)data;
3924 /* Do the rest outside of interrupt context */
3925 schedule_work(&adapter->watchdog_task);
3926}
3927
3928static void igb_watchdog_task(struct work_struct *work)
3929{
3930 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3931 struct igb_adapter,
3932 watchdog_task);
9d5c8243 3933 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3934 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3935 struct net_device *netdev = adapter->netdev;
563988dc 3936 u32 link;
7a6ea550 3937 int i;
9d5c8243 3938
4d6b725e 3939 link = igb_has_link(adapter);
aa9b8cc4
AA		 3940
3941 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
3942 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
3943 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3944 else
3945 link = false;
3946 }
3947
9d5c8243 3948 if (link) {
749ab2cd
YZ		 3949 /* Cancel scheduled suspend requests. */
3950 pm_runtime_resume(netdev->dev.parent);
3951
9d5c8243
AK		 3952 if (!netif_carrier_ok(netdev)) {
3953 u32 ctrl;
330a6d6a 3954 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3955 &adapter->link_speed,
3956 &adapter->link_duplex);
9d5c8243
AK		 3957
3958 ctrl = rd32(E1000_CTRL);
527d47c1 3959 /* Links status message must follow this format */
876d2d6f
JK		 3960 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3961 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3962 netdev->name,
3963 adapter->link_speed,
3964 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3965 "Full" : "Half",
3966 (ctrl & E1000_CTRL_TFCE) &&
3967 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3968 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3969 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3970
c0ba4778
KS		 3971 /* check if SmartSpeed worked */
3972 igb_check_downshift(hw);
3973 if (phy->speed_downgraded)
3974 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3975
563988dc 3976 /* check for thermal sensor event */
876d2d6f
JK		 3977 if (igb_thermal_sensor_event(hw,
3978 E1000_THSTAT_LINK_THROTTLE)) {
3979 netdev_info(netdev, "The network adapter link "
3980 "speed was downshifted because it "
3981 "overheated\n");
7ef5ed1c 3982 }
563988dc 3983
d07f3e37 3984 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3985 adapter->tx_timeout_factor = 1;
3986 switch (adapter->link_speed) {
3987 case SPEED_10:
9d5c8243
AK		 3988 adapter->tx_timeout_factor = 14;
3989 break;
3990 case SPEED_100:
9d5c8243
AK		 3991 /* maybe add some timeout factor ? */
3992 break;
3993 }
3994
3995 netif_carrier_on(netdev);
9d5c8243 3996
4ae196df 3997 igb_ping_all_vfs(adapter);
17dc566c 3998 igb_check_vf_rate_limit(adapter);
4ae196df 3999
4b1a9877 4000 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4001 if (!test_bit(__IGB_DOWN, &adapter->state))
4002 mod_timer(&adapter->phy_info_timer,
4003 round_jiffies(jiffies + 2 * HZ));
4004 }
4005 } else {
4006 if (netif_carrier_ok(netdev)) {
4007 adapter->link_speed = 0;
4008 adapter->link_duplex = 0;
563988dc
SA		 4009
4010 /* check for thermal sensor event */
876d2d6f
JK		 4011 if (igb_thermal_sensor_event(hw,
4012 E1000_THSTAT_PWR_DOWN)) {
4013 netdev_err(netdev, "The network adapter was "
4014 "stopped because it overheated\n");
7ef5ed1c 4015 }
563988dc 4016
527d47c1
AD		 4017 /* Links status message must follow this format */
4018 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4019 netdev->name);
9d5c8243 4020 netif_carrier_off(netdev);
4b1a9877 4021
4ae196df
AD		 4022 igb_ping_all_vfs(adapter);
4023
4b1a9877 4024 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4025 if (!test_bit(__IGB_DOWN, &adapter->state))
4026 mod_timer(&adapter->phy_info_timer,
4027 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 4028
4029 pm_schedule_suspend(netdev->dev.parent,
4030 MSEC_PER_SEC * 5);
9d5c8243
AK		 4031 }
4032 }
4033
12dcd86b
ED		 4034 spin_lock(&adapter->stats64_lock);
4035 igb_update_stats(adapter, &adapter->stats64);
4036 spin_unlock(&adapter->stats64_lock);
9d5c8243 4037
dbabb065 4038 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4039 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4040 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4041 /* We've lost link, so the controller stops DMA,
4042 * but we've got queued Tx work that's never going
4043 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4044 * (Do the reset outside of interrupt context).
4045 */
dbabb065
AD		 4046 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4047 adapter->tx_timeout_count++;
4048 schedule_work(&adapter->reset_task);
4049 /* return immediately since reset is imminent */
4050 return;
4051 }
9d5c8243 4052 }
9d5c8243 4053
dbabb065 4054 /* Force detection of hung controller every watchdog period */
6d095fa8 4055 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4056 }
f7ba205e 4057
b980ac18 4058 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4059 if (adapter->msix_entries) {
047e0030 4060 u32 eics = 0;
0d1ae7f4
AD		 4061 for (i = 0; i < adapter->num_q_vectors; i++)
4062 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4063 wr32(E1000_EICS, eics);
4064 } else {
4065 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4066 }
9d5c8243 4067
13800469 4068 igb_spoof_check(adapter);
fc580751 4069 igb_ptp_rx_hang(adapter);
13800469 4070
9d5c8243 4071 /* Reset the timer */
aa9b8cc4
AA		 4072 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4073 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4074 mod_timer(&adapter->watchdog_timer,
4075 round_jiffies(jiffies + HZ));
4076 else
4077 mod_timer(&adapter->watchdog_timer,
4078 round_jiffies(jiffies + 2 * HZ));
4079 }
9d5c8243
AK		 4080}
4081
4082enum latency_range {
4083 lowest_latency = 0,
4084 low_latency = 1,
4085 bulk_latency = 2,
4086 latency_invalid = 255
4087};
4088
6eb5a7f1 4089/**
b980ac18
JK		 4090 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4091 * @q_vector: pointer to q_vector
6eb5a7f1 4092 *
b980ac18
JK		 4093 * Stores a new ITR value based on strictly on packet size. This
4094 * algorithm is less sophisticated than that used in igb_update_itr,
4095 * due to the difficulty of synchronizing statistics across multiple
4096 * receive rings. The divisors and thresholds used by this function
4097 * were determined based on theoretical maximum wire speed and testing
4098 * data, in order to minimize response time while increasing bulk
4099 * throughput.
4100 * This functionality is controlled by the InterruptThrottleRate module
4101 * parameter (see igb_param.c)
4102 * NOTE: This function is called only when operating in a multiqueue
4103 * receive environment.
6eb5a7f1 4104 **/
047e0030 4105static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4106{
047e0030 4107 int new_val = q_vector->itr_val;
6eb5a7f1 4108 int avg_wire_size = 0;
047e0030 4109 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4110 unsigned int packets;
9d5c8243 4111
6eb5a7f1
AD		 4112 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4113 * ints/sec - ITR timer value of 120 ticks.
4114 */
4115 if (adapter->link_speed != SPEED_1000) {
0ba82994 4116 new_val = IGB_4K_ITR;
6eb5a7f1 4117 goto set_itr_val;
9d5c8243 4118 }
047e0030 4119
0ba82994
AD		 4120 packets = q_vector->rx.total_packets;
4121 if (packets)
4122 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4123
0ba82994
AD		 4124 packets = q_vector->tx.total_packets;
4125 if (packets)
4126 avg_wire_size = max_t(u32, avg_wire_size,
4127 q_vector->tx.total_bytes / packets);
047e0030
AD		 4128
4129 /* if avg_wire_size isn't set no work was done */
4130 if (!avg_wire_size)
4131 goto clear_counts;
9d5c8243 4132
6eb5a7f1
AD		 4133 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4134 avg_wire_size += 24;
4135
4136 /* Don't starve jumbo frames */
4137 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4138
6eb5a7f1
AD		 4139 /* Give a little boost to mid-size frames */
4140 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4141 new_val = avg_wire_size / 3;
4142 else
4143 new_val = avg_wire_size / 2;
9d5c8243 4144
0ba82994
AD		 4145 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4146 if (new_val < IGB_20K_ITR &&
4147 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4148 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4149 new_val = IGB_20K_ITR;
abe1c363 4150
6eb5a7f1 4151set_itr_val:
047e0030
AD		 4152 if (new_val != q_vector->itr_val) {
4153 q_vector->itr_val = new_val;
4154 q_vector->set_itr = 1;
9d5c8243 4155 }
6eb5a7f1 4156clear_counts:
0ba82994
AD		 4157 q_vector->rx.total_bytes = 0;
4158 q_vector->rx.total_packets = 0;
4159 q_vector->tx.total_bytes = 0;
4160 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4161}
4162
4163/**
b980ac18
JK		 4164 * igb_update_itr - update the dynamic ITR value based on statistics
4165 * @q_vector: pointer to q_vector
4166 * @ring_container: ring info to update the itr for
4167 *
4168 * Stores a new ITR value based on packets and byte
4169 * counts during the last interrupt. The advantage of per interrupt
4170 * computation is faster updates and more accurate ITR for the current
4171 * traffic pattern. Constants in this function were computed
4172 * based on theoretical maximum wire speed and thresholds were set based
4173 * on testing data as well as attempting to minimize response time
4174 * while increasing bulk throughput.
4175 * this functionality is controlled by the InterruptThrottleRate module
4176 * parameter (see igb_param.c)
4177 * NOTE: These calculations are only valid when operating in a single-
4178 * queue environment.
9d5c8243 4179 **/
0ba82994
AD		 4180static void igb_update_itr(struct igb_q_vector *q_vector,
4181 struct igb_ring_container *ring_container)
9d5c8243 4182{
0ba82994
AD		 4183 unsigned int packets = ring_container->total_packets;
4184 unsigned int bytes = ring_container->total_bytes;
4185 u8 itrval = ring_container->itr;
9d5c8243 4186
0ba82994 4187 /* no packets, exit with status unchanged */
9d5c8243 4188 if (packets == 0)
0ba82994 4189 return;
9d5c8243 4190
0ba82994 4191 switch (itrval) {
9d5c8243
AK		 4192 case lowest_latency:
4193 /* handle TSO and jumbo frames */
4194 if (bytes/packets > 8000)
0ba82994 4195 itrval = bulk_latency;
9d5c8243 4196 else if ((packets < 5) && (bytes > 512))
0ba82994 4197 itrval = low_latency;
9d5c8243
AK		 4198 break;
4199 case low_latency: /* 50 usec aka 20000 ints/s */
4200 if (bytes > 10000) {
4201 /* this if handles the TSO accounting */
4202 if (bytes/packets > 8000) {
0ba82994 4203 itrval = bulk_latency;
9d5c8243 4204 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4205 itrval = bulk_latency;
9d5c8243 4206 } else if ((packets > 35)) {
0ba82994 4207 itrval = lowest_latency;
9d5c8243
AK		 4208 }
4209 } else if (bytes/packets > 2000) {
0ba82994 4210 itrval = bulk_latency;
9d5c8243 4211 } else if (packets <= 2 && bytes < 512) {
0ba82994 4212 itrval = lowest_latency;
9d5c8243
AK		 4213 }
4214 break;
4215 case bulk_latency: /* 250 usec aka 4000 ints/s */
4216 if (bytes > 25000) {
4217 if (packets > 35)
0ba82994 4218 itrval = low_latency;
1e5c3d21 4219 } else if (bytes < 1500) {
0ba82994 4220 itrval = low_latency;
9d5c8243
AK		 4221 }
4222 break;
4223 }
4224
0ba82994
AD		 4225 /* clear work counters since we have the values we need */
4226 ring_container->total_bytes = 0;
4227 ring_container->total_packets = 0;
4228
4229 /* write updated itr to ring container */
4230 ring_container->itr = itrval;
9d5c8243
AK		 4231}
4232
0ba82994 4233static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4234{
0ba82994 4235 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4236 u32 new_itr = q_vector->itr_val;
0ba82994 4237 u8 current_itr = 0;
9d5c8243
AK		 4238
4239 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4240 if (adapter->link_speed != SPEED_1000) {
4241 current_itr = 0;
0ba82994 4242 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4243 goto set_itr_now;
4244 }
4245
0ba82994
AD		 4246 igb_update_itr(q_vector, &q_vector->tx);
4247 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4248
0ba82994 4249 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4250
6eb5a7f1 4251 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4252 if (current_itr == lowest_latency &&
4253 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4254 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4255 current_itr = low_latency;
4256
9d5c8243
AK		 4257 switch (current_itr) {
4258 /* counts and packets in update_itr are dependent on these numbers */
4259 case lowest_latency:
0ba82994 4260 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4261 break;
4262 case low_latency:
0ba82994 4263 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4264 break;
4265 case bulk_latency:
0ba82994 4266 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4267 break;
4268 default:
4269 break;
4270 }
4271
4272set_itr_now:
047e0030 4273 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4274 /* this attempts to bias the interrupt rate towards Bulk
4275 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4276 * increasing
4277 */
047e0030 4278 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4279 max((new_itr * q_vector->itr_val) /
4280 (new_itr + (q_vector->itr_val >> 2)),
4281 new_itr) : new_itr;
9d5c8243
AK		 4282 /* Don't write the value here; it resets the adapter's
4283 * internal timer, and causes us to delay far longer than
4284 * we should between interrupts. Instead, we write the ITR
4285 * value at the beginning of the next interrupt so the timing
4286 * ends up being correct.
4287 */
047e0030
AD		 4288 q_vector->itr_val = new_itr;
4289 q_vector->set_itr = 1;
9d5c8243 4290 }
9d5c8243
AK		 4291}
4292
c50b52a0
SH		 4293static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4294 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4295{
4296 struct e1000_adv_tx_context_desc *context_desc;
4297 u16 i = tx_ring->next_to_use;
4298
4299 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4300
4301 i++;
4302 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4303
4304 /* set bits to identify this as an advanced context descriptor */
4305 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4306
4307 /* For 82575, context index must be unique per ring. */
866cff06 4308 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4309 mss_l4len_idx |= tx_ring->reg_idx << 4;
4310
4311 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4312 context_desc->seqnum_seed = 0;
4313 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4314 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4315}
4316
7af40ad9
AD		 4317static int igb_tso(struct igb_ring *tx_ring,
4318 struct igb_tx_buffer *first,
4319 u8 *hdr_len)
9d5c8243 4320{
7af40ad9 4321 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4322 u32 vlan_macip_lens, type_tucmd;
4323 u32 mss_l4len_idx, l4len;
4324
ed6aa105
AD		 4325 if (skb->ip_summed != CHECKSUM_PARTIAL)
4326 return 0;
4327
7d13a7d0
AD		 4328 if (!skb_is_gso(skb))
4329 return 0;
9d5c8243
AK		 4330
4331 if (skb_header_cloned(skb)) {
7af40ad9 4332 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4333 if (err)
4334 return err;
4335 }
4336
7d13a7d0
AD		 4337 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4338 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4339
7af40ad9 4340 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4341 struct iphdr *iph = ip_hdr(skb);
4342 iph->tot_len = 0;
4343 iph->check = 0;
4344 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4345 iph->daddr, 0,
4346 IPPROTO_TCP,
4347 0);
7d13a7d0 4348 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4349 first->tx_flags |= IGB_TX_FLAGS_TSO |
4350 IGB_TX_FLAGS_CSUM |
4351 IGB_TX_FLAGS_IPV4;
8e1e8a47 4352 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4353 ipv6_hdr(skb)->payload_len = 0;
4354 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4355 &ipv6_hdr(skb)->daddr,
4356 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4357 first->tx_flags |= IGB_TX_FLAGS_TSO |
4358 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4359 }
4360
7af40ad9 4361 /* compute header lengths */
7d13a7d0
AD		 4362 l4len = tcp_hdrlen(skb);
4363 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4364
7af40ad9
AD		 4365 /* update gso size and bytecount with header size */
4366 first->gso_segs = skb_shinfo(skb)->gso_segs;
4367 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4368
9d5c8243 4369 /* MSS L4LEN IDX */
7d13a7d0
AD		 4370 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4371 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4372
7d13a7d0
AD		 4373 /* VLAN MACLEN IPLEN */
4374 vlan_macip_lens = skb_network_header_len(skb);
4375 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4376 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4377
7d13a7d0 4378 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4379
7d13a7d0 4380 return 1;
9d5c8243
AK		 4381}
4382
7af40ad9 4383static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4384{
7af40ad9 4385 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4386 u32 vlan_macip_lens = 0;
4387 u32 mss_l4len_idx = 0;
4388 u32 type_tucmd = 0;
9d5c8243 4389
7d13a7d0 4390 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4391 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4392 return;
7d13a7d0
AD		 4393 } else {
4394 u8 l4_hdr = 0;
7af40ad9 4395 switch (first->protocol) {
7d13a7d0
AD		 4396 case __constant_htons(ETH_P_IP):
4397 vlan_macip_lens |= skb_network_header_len(skb);
4398 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4399 l4_hdr = ip_hdr(skb)->protocol;
4400 break;
4401 case __constant_htons(ETH_P_IPV6):
4402 vlan_macip_lens |= skb_network_header_len(skb);
4403 l4_hdr = ipv6_hdr(skb)->nexthdr;
4404 break;
4405 default:
4406 if (unlikely(net_ratelimit())) {
4407 dev_warn(tx_ring->dev,
b980ac18
JK		 4408 "partial checksum but proto=%x!\n",
4409 first->protocol);
fa4a7ef3 4410 }
7d13a7d0
AD		 4411 break;
4412 }
fa4a7ef3 4413
7d13a7d0
AD		 4414 switch (l4_hdr) {
4415 case IPPROTO_TCP:
4416 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4417 mss_l4len_idx = tcp_hdrlen(skb) <<
4418 E1000_ADVTXD_L4LEN_SHIFT;
4419 break;
4420 case IPPROTO_SCTP:
4421 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4422 mss_l4len_idx = sizeof(struct sctphdr) <<
4423 E1000_ADVTXD_L4LEN_SHIFT;
4424 break;
4425 case IPPROTO_UDP:
4426 mss_l4len_idx = sizeof(struct udphdr) <<
4427 E1000_ADVTXD_L4LEN_SHIFT;
4428 break;
4429 default:
4430 if (unlikely(net_ratelimit())) {
4431 dev_warn(tx_ring->dev,
b980ac18
JK		 4432 "partial checksum but l4 proto=%x!\n",
4433 l4_hdr);
44b0cda3 4434 }
7d13a7d0 4435 break;
9d5c8243 4436 }
7af40ad9
AD		 4437
4438 /* update TX checksum flag */
4439 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4440 }
9d5c8243 4441
7d13a7d0 4442 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4443 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4444
7d13a7d0 4445 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4446}
4447
1d9daf45
AD		 4448#define IGB_SET_FLAG(_input, _flag, _result) \
4449 ((_flag <= _result) ? \
4450 ((u32)(_input & _flag) * (_result / _flag)) : \
4451 ((u32)(_input & _flag) / (_flag / _result)))
4452
4453static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4454{
4455 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4456 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4457 E1000_ADVTXD_DCMD_DEXT |
4458 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4459
4460 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4461 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4462 (E1000_ADVTXD_DCMD_VLE));
4463
4464 /* set segmentation bits for TSO */
4465 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4466 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4467
4468 /* set timestamp bit if present */
1d9daf45
AD		 4469 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4470 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4471
1d9daf45
AD		 4472 /* insert frame checksum */
4473 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4474
4475 return cmd_type;
4476}
4477
7af40ad9
AD		 4478static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4479 union e1000_adv_tx_desc *tx_desc,
4480 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4481{
4482 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4483
1d9daf45
AD		 4484 /* 82575 requires a unique index per ring */
4485 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4486 olinfo_status |= tx_ring->reg_idx << 4;
4487
4488 /* insert L4 checksum */
1d9daf45
AD		 4489 olinfo_status |= IGB_SET_FLAG(tx_flags,
4490 IGB_TX_FLAGS_CSUM,
4491 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4492
1d9daf45
AD		 4493 /* insert IPv4 checksum */
4494 olinfo_status |= IGB_SET_FLAG(tx_flags,
4495 IGB_TX_FLAGS_IPV4,
4496 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4497
7af40ad9 4498 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4499}
4500
7af40ad9
AD		 4501static void igb_tx_map(struct igb_ring *tx_ring,
4502 struct igb_tx_buffer *first,
ebe42d16 4503 const u8 hdr_len)
9d5c8243 4504{
7af40ad9 4505 struct sk_buff *skb = first->skb;
c9f14bf3 4506 struct igb_tx_buffer *tx_buffer;
ebe42d16 4507 union e1000_adv_tx_desc *tx_desc;
80d0759e 4508 struct skb_frag_struct *frag;
ebe42d16 4509 dma_addr_t dma;
80d0759e 4510 unsigned int data_len, size;
7af40ad9 4511 u32 tx_flags = first->tx_flags;
1d9daf45 4512 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4513 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4514
4515 tx_desc = IGB_TX_DESC(tx_ring, i);
4516
80d0759e
AD		 4517 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4518
4519 size = skb_headlen(skb);
4520 data_len = skb->data_len;
ebe42d16
AD		 4521
4522 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4523
80d0759e
AD		 4524 tx_buffer = first;
4525
4526 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4527 if (dma_mapping_error(tx_ring->dev, dma))
4528 goto dma_error;
4529
4530 /* record length, and DMA address */
4531 dma_unmap_len_set(tx_buffer, len, size);
4532 dma_unmap_addr_set(tx_buffer, dma, dma);
4533
4534 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4535
ebe42d16
AD		 4536 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4537 tx_desc->read.cmd_type_len =
1d9daf45 4538 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4539
4540 i++;
4541 tx_desc++;
4542 if (i == tx_ring->count) {
4543 tx_desc = IGB_TX_DESC(tx_ring, 0);
4544 i = 0;
4545 }
80d0759e 4546 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4547
4548 dma += IGB_MAX_DATA_PER_TXD;
4549 size -= IGB_MAX_DATA_PER_TXD;
4550
ebe42d16
AD		 4551 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4552 }
4553
4554 if (likely(!data_len))
4555 break;
2bbfebe2 4556
1d9daf45 4557 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4558
65689fef 4559 i++;
ebe42d16
AD		 4560 tx_desc++;
4561 if (i == tx_ring->count) {
4562 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4563 i = 0;
ebe42d16 4564 }
80d0759e 4565 tx_desc->read.olinfo_status = 0;
65689fef 4566
9e903e08 4567 size = skb_frag_size(frag);
ebe42d16
AD		 4568 data_len -= size;
4569
4570 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4571 size, DMA_TO_DEVICE);
6366ad33 4572
c9f14bf3 4573 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4574 }
4575
ebe42d16 4576 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4577 cmd_type |= size | IGB_TXD_DCMD;
4578 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4579
80d0759e
AD		 4580 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4581
8542db05
AD		 4582 /* set the timestamp */
4583 first->time_stamp = jiffies;
4584
b980ac18 4585 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4586 * are new descriptors to fetch. (Only applicable for weak-ordered
4587 * memory model archs, such as IA-64).
4588 *
4589 * We also need this memory barrier to make certain all of the
4590 * status bits have been updated before next_to_watch is written.
4591 */
4592 wmb();
4593
8542db05 4594 /* set next_to_watch value indicating a packet is present */
ebe42d16 4595 first->next_to_watch = tx_desc;
9d5c8243 4596
ebe42d16
AD		 4597 i++;
4598 if (i == tx_ring->count)
4599 i = 0;
6366ad33 4600
ebe42d16 4601 tx_ring->next_to_use = i;
6366ad33 4602
ebe42d16 4603 writel(i, tx_ring->tail);
6366ad33 4604
ebe42d16 4605 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4606 * at a time, it synchronizes IO on IA64/Altix systems
4607 */
ebe42d16
AD		 4608 mmiowb();
4609
4610 return;
4611
4612dma_error:
4613 dev_err(tx_ring->dev, "TX DMA map failed\n");
4614
4615 /* clear dma mappings for failed tx_buffer_info map */
4616 for (;;) {
c9f14bf3
AD		 4617 tx_buffer = &tx_ring->tx_buffer_info[i];
4618 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4619 if (tx_buffer == first)
ebe42d16 4620 break;
a77ff709
NN		 4621 if (i == 0)
4622 i = tx_ring->count;
6366ad33 4623 i--;
6366ad33
AD		 4624 }
4625
9d5c8243 4626 tx_ring->next_to_use = i;
9d5c8243
AK		 4627}
4628
6ad4edfc 4629static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4630{
e694e964
AD		 4631 struct net_device *netdev = tx_ring->netdev;
4632
661086df 4633 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4634
9d5c8243
AK		 4635 /* Herbert's original patch had:
4636 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4637 * but since that doesn't exist yet, just open code it.
4638 */
9d5c8243
AK		 4639 smp_mb();
4640
4641 /* We need to check again in a case another CPU has just
b980ac18
JK		 4642 * made room available.
4643 */
c493ea45 4644 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4645 return -EBUSY;
4646
4647 /* A reprieve! */
661086df 4648 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4649
4650 u64_stats_update_begin(&tx_ring->tx_syncp2);
4651 tx_ring->tx_stats.restart_queue2++;
4652 u64_stats_update_end(&tx_ring->tx_syncp2);
4653
9d5c8243
AK		 4654 return 0;
4655}
4656
6ad4edfc 4657static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4658{
c493ea45 4659 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4660 return 0;
e694e964 4661 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4662}
4663
cd392f5c
AD		 4664netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4665 struct igb_ring *tx_ring)
9d5c8243 4666{
8542db05 4667 struct igb_tx_buffer *first;
ebe42d16 4668 int tso;
91d4ee33 4669 u32 tx_flags = 0;
21ba6fe1 4670 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4671 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4672 u8 hdr_len = 0;
9d5c8243 4673
21ba6fe1
AD		 4674 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4675 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4676 * + 2 desc gap to keep tail from touching head,
9d5c8243 4677 * + 1 desc for context descriptor,
21ba6fe1
AD		 4678 * otherwise try next time
4679 */
4680 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4681 unsigned short f;
4682 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4683 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4684 } else {
4685 count += skb_shinfo(skb)->nr_frags;
4686 }
4687
4688 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4689 /* this is a hard error */
9d5c8243
AK		 4690 return NETDEV_TX_BUSY;
4691 }
33af6bcc 4692
7af40ad9
AD		 4693 /* record the location of the first descriptor for this packet */
4694 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4695 first->skb = skb;
4696 first->bytecount = skb->len;
4697 first->gso_segs = 1;
4698
b66e2397
MV		 4699 skb_tx_timestamp(skb);
4700
b646c22e
AD		 4701 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4702 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4703
b646c22e
AD		 4704 if (!(adapter->ptp_tx_skb)) {
4705 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4706 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4707
4708 adapter->ptp_tx_skb = skb_get(skb);
4709 adapter->ptp_tx_start = jiffies;
4710 if (adapter->hw.mac.type == e1000_82576)
4711 schedule_work(&adapter->ptp_tx_work);
4712 }
33af6bcc 4713 }
9d5c8243 4714
eab6d18d 4715 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4716 tx_flags |= IGB_TX_FLAGS_VLAN;
4717 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4718 }
4719
7af40ad9
AD		 4720 /* record initial flags and protocol */
4721 first->tx_flags = tx_flags;
4722 first->protocol = protocol;
cdfd01fc 4723
7af40ad9
AD		 4724 tso = igb_tso(tx_ring, first, &hdr_len);
4725 if (tso < 0)
7d13a7d0 4726 goto out_drop;
7af40ad9
AD		 4727 else if (!tso)
4728 igb_tx_csum(tx_ring, first);
9d5c8243 4729
7af40ad9 4730 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4731
4732 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4733 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4734
9d5c8243 4735 return NETDEV_TX_OK;
7d13a7d0
AD		 4736
4737out_drop:
7af40ad9
AD		 4738 igb_unmap_and_free_tx_resource(tx_ring, first);
4739
7d13a7d0 4740 return NETDEV_TX_OK;
9d5c8243
AK		 4741}
4742
1cc3bd87
AD		 4743static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4744 struct sk_buff *skb)
4745{
4746 unsigned int r_idx = skb->queue_mapping;
4747
4748 if (r_idx >= adapter->num_tx_queues)
4749 r_idx = r_idx % adapter->num_tx_queues;
4750
4751 return adapter->tx_ring[r_idx];
4752}
4753
cd392f5c
AD		 4754static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4755 struct net_device *netdev)
9d5c8243
AK		 4756{
4757 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4758
4759 if (test_bit(__IGB_DOWN, &adapter->state)) {
4760 dev_kfree_skb_any(skb);
4761 return NETDEV_TX_OK;
4762 }
4763
4764 if (skb->len <= 0) {
4765 dev_kfree_skb_any(skb);
4766 return NETDEV_TX_OK;
4767 }
4768
b980ac18 4769 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4770 * in order to meet this minimum size requirement.
4771 */
ea5ceeab
TD		 4772 if (unlikely(skb->len < 17)) {
4773 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4774 return NETDEV_TX_OK;
4775 skb->len = 17;
ea5ceeab 4776 skb_set_tail_pointer(skb, 17);
1cc3bd87 4777 }
9d5c8243 4778
1cc3bd87 4779 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4780}
4781
4782/**
b980ac18
JK		 4783 * igb_tx_timeout - Respond to a Tx Hang
4784 * @netdev: network interface device structure
9d5c8243
AK		 4785 **/
4786static void igb_tx_timeout(struct net_device *netdev)
4787{
4788 struct igb_adapter *adapter = netdev_priv(netdev);
4789 struct e1000_hw *hw = &adapter->hw;
4790
4791 /* Do the reset outside of interrupt context */
4792 adapter->tx_timeout_count++;
f7ba205e 4793
06218a8d 4794 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4795 hw->dev_spec._82575.global_device_reset = true;
4796
9d5c8243 4797 schedule_work(&adapter->reset_task);
265de409
AD		 4798 wr32(E1000_EICS,
4799 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4800}
4801
4802static void igb_reset_task(struct work_struct *work)
4803{
4804 struct igb_adapter *adapter;
4805 adapter = container_of(work, struct igb_adapter, reset_task);
4806
c97ec42a
TI		 4807 igb_dump(adapter);
4808 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4809 igb_reinit_locked(adapter);
4810}
4811
4812/**
b980ac18
JK		 4813 * igb_get_stats64 - Get System Network Statistics
4814 * @netdev: network interface device structure
4815 * @stats: rtnl_link_stats64 pointer
9d5c8243 4816 **/
12dcd86b 4817static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4818 struct rtnl_link_stats64 *stats)
9d5c8243 4819{
12dcd86b
ED		 4820 struct igb_adapter *adapter = netdev_priv(netdev);
4821
4822 spin_lock(&adapter->stats64_lock);
4823 igb_update_stats(adapter, &adapter->stats64);
4824 memcpy(stats, &adapter->stats64, sizeof(*stats));
4825 spin_unlock(&adapter->stats64_lock);
4826
4827 return stats;
9d5c8243
AK		 4828}
4829
4830/**
b980ac18
JK		 4831 * igb_change_mtu - Change the Maximum Transfer Unit
4832 * @netdev: network interface device structure
4833 * @new_mtu: new value for maximum frame size
9d5c8243 4834 *
b980ac18 4835 * Returns 0 on success, negative on failure
9d5c8243
AK		 4836 **/
4837static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4838{
4839 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4840 struct pci_dev *pdev = adapter->pdev;
153285f9 4841 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4842
c809d227 4843 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4844 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4845 return -EINVAL;
4846 }
4847
153285f9 4848#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4849 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4850 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4851 return -EINVAL;
4852 }
4853
2ccd994c
AD		 4854 /* adjust max frame to be at least the size of a standard frame */
4855 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4856 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4857
9d5c8243
AK		 4858 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4859 msleep(1);
73cd78f1 4860
9d5c8243
AK		 4861 /* igb_down has a dependency on max_frame_size */
4862 adapter->max_frame_size = max_frame;
559e9c49 4863
4c844851
AD		 4864 if (netif_running(netdev))
4865 igb_down(adapter);
9d5c8243 4866
090b1795 4867 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4868 netdev->mtu, new_mtu);
4869 netdev->mtu = new_mtu;
4870
4871 if (netif_running(netdev))
4872 igb_up(adapter);
4873 else
4874 igb_reset(adapter);
4875
4876 clear_bit(__IGB_RESETTING, &adapter->state);
4877
4878 return 0;
4879}
4880
4881/**
b980ac18
JK		 4882 * igb_update_stats - Update the board statistics counters
4883 * @adapter: board private structure
9d5c8243 4884 **/
12dcd86b
ED		 4885void igb_update_stats(struct igb_adapter *adapter,
4886 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4887{
4888 struct e1000_hw *hw = &adapter->hw;
4889 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4890 u32 reg, mpc;
9d5c8243 4891 u16 phy_tmp;
3f9c0164
AD		 4892 int i;
4893 u64 bytes, packets;
12dcd86b
ED		 4894 unsigned int start;
4895 u64 _bytes, _packets;
9d5c8243
AK		 4896
4897#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4898
b980ac18 4899 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4900 * connection is down.
4901 */
4902 if (adapter->link_speed == 0)
4903 return;
4904 if (pci_channel_offline(pdev))
4905 return;
4906
3f9c0164
AD		 4907 bytes = 0;
4908 packets = 0;
7f90128e
AA		 4909
4910 rcu_read_lock();
3f9c0164 4911 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4912 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4913 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4914
ae1c07a6
AD		 4915 if (rqdpc) {
4916 ring->rx_stats.drops += rqdpc;
4917 net_stats->rx_fifo_errors += rqdpc;
4918 }
12dcd86b
ED		 4919
4920 do {
4921 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4922 _bytes = ring->rx_stats.bytes;
4923 _packets = ring->rx_stats.packets;
4924 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4925 bytes += _bytes;
4926 packets += _packets;
3f9c0164
AD		 4927 }
4928
128e45eb
AD		 4929 net_stats->rx_bytes = bytes;
4930 net_stats->rx_packets = packets;
3f9c0164
AD		 4931
4932 bytes = 0;
4933 packets = 0;
4934 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4935 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4936 do {
4937 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4938 _bytes = ring->tx_stats.bytes;
4939 _packets = ring->tx_stats.packets;
4940 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4941 bytes += _bytes;
4942 packets += _packets;
3f9c0164 4943 }
128e45eb
AD		 4944 net_stats->tx_bytes = bytes;
4945 net_stats->tx_packets = packets;
7f90128e 4946 rcu_read_unlock();
3f9c0164
AD		 4947
4948 /* read stats registers */
9d5c8243
AK		 4949 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4950 adapter->stats.gprc += rd32(E1000_GPRC);
4951 adapter->stats.gorc += rd32(E1000_GORCL);
4952 rd32(E1000_GORCH); /* clear GORCL */
4953 adapter->stats.bprc += rd32(E1000_BPRC);
4954 adapter->stats.mprc += rd32(E1000_MPRC);
4955 adapter->stats.roc += rd32(E1000_ROC);
4956
4957 adapter->stats.prc64 += rd32(E1000_PRC64);
4958 adapter->stats.prc127 += rd32(E1000_PRC127);
4959 adapter->stats.prc255 += rd32(E1000_PRC255);
4960 adapter->stats.prc511 += rd32(E1000_PRC511);
4961 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4962 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4963 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4964 adapter->stats.sec += rd32(E1000_SEC);
4965
fa3d9a6d
MW		 4966 mpc = rd32(E1000_MPC);
4967 adapter->stats.mpc += mpc;
4968 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4969 adapter->stats.scc += rd32(E1000_SCC);
4970 adapter->stats.ecol += rd32(E1000_ECOL);
4971 adapter->stats.mcc += rd32(E1000_MCC);
4972 adapter->stats.latecol += rd32(E1000_LATECOL);
4973 adapter->stats.dc += rd32(E1000_DC);
4974 adapter->stats.rlec += rd32(E1000_RLEC);
4975 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4976 adapter->stats.xontxc += rd32(E1000_XONTXC);
4977 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4978 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4979 adapter->stats.fcruc += rd32(E1000_FCRUC);
4980 adapter->stats.gptc += rd32(E1000_GPTC);
4981 adapter->stats.gotc += rd32(E1000_GOTCL);
4982 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4983 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4984 adapter->stats.ruc += rd32(E1000_RUC);
4985 adapter->stats.rfc += rd32(E1000_RFC);
4986 adapter->stats.rjc += rd32(E1000_RJC);
4987 adapter->stats.tor += rd32(E1000_TORH);
4988 adapter->stats.tot += rd32(E1000_TOTH);
4989 adapter->stats.tpr += rd32(E1000_TPR);
4990
4991 adapter->stats.ptc64 += rd32(E1000_PTC64);
4992 adapter->stats.ptc127 += rd32(E1000_PTC127);
4993 adapter->stats.ptc255 += rd32(E1000_PTC255);
4994 adapter->stats.ptc511 += rd32(E1000_PTC511);
4995 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4996 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4997
4998 adapter->stats.mptc += rd32(E1000_MPTC);
4999 adapter->stats.bptc += rd32(E1000_BPTC);
5000
2d0b0f69
NN		 5001 adapter->stats.tpt += rd32(E1000_TPT);
5002 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5003
5004 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5005 /* read internal phy specific stats */
5006 reg = rd32(E1000_CTRL_EXT);
5007 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5008 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5009
5010 /* this stat has invalid values on i210/i211 */
5011 if ((hw->mac.type != e1000_i210) &&
5012 (hw->mac.type != e1000_i211))
5013 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5014 }
5015
9d5c8243
AK		 5016 adapter->stats.tsctc += rd32(E1000_TSCTC);
5017 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5018
5019 adapter->stats.iac += rd32(E1000_IAC);
5020 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5021 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5022 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5023 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5024 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5025 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5026 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5027 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5028
5029 /* Fill out the OS statistics structure */
128e45eb
AD		 5030 net_stats->multicast = adapter->stats.mprc;
5031 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5032
5033 /* Rx Errors */
5034
5035 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5036 * our own version based on RUC and ROC
5037 */
128e45eb 5038 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5039 adapter->stats.crcerrs + adapter->stats.algnerrc +
5040 adapter->stats.ruc + adapter->stats.roc +
5041 adapter->stats.cexterr;
128e45eb
AD		 5042 net_stats->rx_length_errors = adapter->stats.ruc +
5043 adapter->stats.roc;
5044 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5045 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5046 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5047
5048 /* Tx Errors */
128e45eb
AD		 5049 net_stats->tx_errors = adapter->stats.ecol +
5050 adapter->stats.latecol;
5051 net_stats->tx_aborted_errors = adapter->stats.ecol;
5052 net_stats->tx_window_errors = adapter->stats.latecol;
5053 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5054
5055 /* Tx Dropped needs to be maintained elsewhere */
5056
5057 /* Phy Stats */
5058 if (hw->phy.media_type == e1000_media_type_copper) {
5059 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5060 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5061 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5062 adapter->phy_stats.idle_errors += phy_tmp;
5063 }
5064 }
5065
5066 /* Management Stats */
5067 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5068 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5069 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5070
5071 /* OS2BMC Stats */
5072 reg = rd32(E1000_MANC);
5073 if (reg & E1000_MANC_EN_BMC2OS) {
5074 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5075 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5076 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5077 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5078 }
9d5c8243
AK		 5079}
5080
9d5c8243
AK		 5081static irqreturn_t igb_msix_other(int irq, void *data)
5082{
047e0030 5083 struct igb_adapter *adapter = data;
9d5c8243 5084 struct e1000_hw *hw = &adapter->hw;
844290e5 5085 u32 icr = rd32(E1000_ICR);
844290e5 5086 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5087
7f081d40
AD		 5088 if (icr & E1000_ICR_DRSTA)
5089 schedule_work(&adapter->reset_task);
5090
047e0030 5091 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5092 /* HW is reporting DMA is out of sync */
5093 adapter->stats.doosync++;
13800469
GR		 5094 /* The DMA Out of Sync is also indication of a spoof event
5095 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5096 * see if it is really a spoof event.
5097 */
13800469 5098 igb_check_wvbr(adapter);
dda0e083 5099 }
eebbbdba 5100
4ae196df
AD		 5101 /* Check for a mailbox event */
5102 if (icr & E1000_ICR_VMMB)
5103 igb_msg_task(adapter);
5104
5105 if (icr & E1000_ICR_LSC) {
5106 hw->mac.get_link_status = 1;
5107 /* guard against interrupt when we're going down */
5108 if (!test_bit(__IGB_DOWN, &adapter->state))
5109 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5110 }
5111
1f6e8178
MV		 5112 if (icr & E1000_ICR_TS) {
5113 u32 tsicr = rd32(E1000_TSICR);
5114
5115 if (tsicr & E1000_TSICR_TXTS) {
5116 /* acknowledge the interrupt */
5117 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5118 /* retrieve hardware timestamp */
5119 schedule_work(&adapter->ptp_tx_work);
5120 }
5121 }
1f6e8178 5122
844290e5 5123 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5124
5125 return IRQ_HANDLED;
5126}
5127
047e0030 5128static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5129{
26b39276 5130 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5131 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5132
047e0030
AD		 5133 if (!q_vector->set_itr)
5134 return;
73cd78f1 5135
047e0030
AD		 5136 if (!itr_val)
5137 itr_val = 0x4;
661086df 5138
26b39276
AD		 5139 if (adapter->hw.mac.type == e1000_82575)
5140 itr_val |= itr_val << 16;
661086df 5141 else
0ba82994 5142 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5143
047e0030
AD		 5144 writel(itr_val, q_vector->itr_register);
5145 q_vector->set_itr = 0;
6eb5a7f1
AD		 5146}
5147
047e0030 5148static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5149{
047e0030 5150 struct igb_q_vector *q_vector = data;
9d5c8243 5151
047e0030
AD		 5152 /* Write the ITR value calculated from the previous interrupt. */
5153 igb_write_itr(q_vector);
9d5c8243 5154
047e0030 5155 napi_schedule(&q_vector->napi);
844290e5 5156
047e0030 5157 return IRQ_HANDLED;
fe4506b6
JC		 5158}
5159
421e02f0 5160#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5161static void igb_update_tx_dca(struct igb_adapter *adapter,
5162 struct igb_ring *tx_ring,
5163 int cpu)
5164{
5165 struct e1000_hw *hw = &adapter->hw;
5166 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5167
5168 if (hw->mac.type != e1000_82575)
5169 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5170
b980ac18 5171 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5172 * DCA is enabled. This is due to a known issue in some chipsets
5173 * which will cause the DCA tag to be cleared.
5174 */
5175 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5176 E1000_DCA_TXCTRL_DATA_RRO_EN |
5177 E1000_DCA_TXCTRL_DESC_DCA_EN;
5178
5179 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5180}
5181
5182static void igb_update_rx_dca(struct igb_adapter *adapter,
5183 struct igb_ring *rx_ring,
5184 int cpu)
5185{
5186 struct e1000_hw *hw = &adapter->hw;
5187 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5188
5189 if (hw->mac.type != e1000_82575)
5190 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5191
b980ac18 5192 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5193 * DCA is enabled. This is due to a known issue in some chipsets
5194 * which will cause the DCA tag to be cleared.
5195 */
5196 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5197 E1000_DCA_RXCTRL_DESC_DCA_EN;
5198
5199 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5200}
5201
047e0030 5202static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5203{
047e0030 5204 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5205 int cpu = get_cpu();
fe4506b6 5206
047e0030
AD		 5207 if (q_vector->cpu == cpu)
5208 goto out_no_update;
5209
6a05004a
AD		 5210 if (q_vector->tx.ring)
5211 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5212
5213 if (q_vector->rx.ring)
5214 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5215
047e0030
AD		 5216 q_vector->cpu = cpu;
5217out_no_update:
fe4506b6
JC		 5218 put_cpu();
5219}
5220
5221static void igb_setup_dca(struct igb_adapter *adapter)
5222{
7e0e99ef 5223 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5224 int i;
5225
7dfc16fa 5226 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5227 return;
5228
7e0e99ef
AD		 5229 /* Always use CB2 mode, difference is masked in the CB driver. */
5230 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5231
047e0030 5232 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5233 adapter->q_vector[i]->cpu = -1;
5234 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5235 }
5236}
5237
5238static int __igb_notify_dca(struct device *dev, void *data)
5239{
5240 struct net_device *netdev = dev_get_drvdata(dev);
5241 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5242 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5243 struct e1000_hw *hw = &adapter->hw;
5244 unsigned long event = *(unsigned long *)data;
5245
5246 switch (event) {
5247 case DCA_PROVIDER_ADD:
5248 /* if already enabled, don't do it again */
7dfc16fa 5249 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5250 break;
fe4506b6 5251 if (dca_add_requester(dev) == 0) {
bbd98fe4 5252 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5253 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5254 igb_setup_dca(adapter);
5255 break;
5256 }
5257 /* Fall Through since DCA is disabled. */
5258 case DCA_PROVIDER_REMOVE:
7dfc16fa 5259 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5260 /* without this a class_device is left
b980ac18
JK		 5261 * hanging around in the sysfs model
5262 */
fe4506b6 5263 dca_remove_requester(dev);
090b1795 5264 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5265 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5266 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5267 }
5268 break;
5269 }
bbd98fe4 5270
fe4506b6 5271 return 0;
9d5c8243
AK		 5272}
5273
fe4506b6 5274static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5275 void *p)
fe4506b6
JC		 5276{
5277 int ret_val;
5278
5279 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5280 __igb_notify_dca);
fe4506b6
JC		 5281
5282 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5283}
421e02f0 5284#endif /* CONFIG_IGB_DCA */
9d5c8243 5285
0224d663
GR		 5286#ifdef CONFIG_PCI_IOV
5287static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5288{
5289 unsigned char mac_addr[ETH_ALEN];
0224d663 5290
5ac6f91d 5291 eth_zero_addr(mac_addr);
0224d663
GR		 5292 igb_set_vf_mac(adapter, vf, mac_addr);
5293
70ea4783
LL		 5294 /* By default spoof check is enabled for all VFs */
5295 adapter->vf_data[vf].spoofchk_enabled = true;
5296
f557147c 5297 return 0;
0224d663
GR		 5298}
5299
0224d663 5300#endif
4ae196df
AD		 5301static void igb_ping_all_vfs(struct igb_adapter *adapter)
5302{
5303 struct e1000_hw *hw = &adapter->hw;
5304 u32 ping;
5305 int i;
5306
5307 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5308 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5309 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5310 ping |= E1000_VT_MSGTYPE_CTS;
5311 igb_write_mbx(hw, &ping, 1, i);
5312 }
5313}
5314
7d5753f0
AD		 5315static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5316{
5317 struct e1000_hw *hw = &adapter->hw;
5318 u32 vmolr = rd32(E1000_VMOLR(vf));
5319 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5320
d85b9004 5321 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5322 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5323 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5324
5325 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5326 vmolr |= E1000_VMOLR_MPME;
d85b9004 5327 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5328 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5329 } else {
b980ac18 5330 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5331 * flag we need to write the hashes to the MTA as this step
5332 * was previously skipped
5333 */
5334 if (vf_data->num_vf_mc_hashes > 30) {
5335 vmolr |= E1000_VMOLR_MPME;
5336 } else if (vf_data->num_vf_mc_hashes) {
5337 int j;
5338 vmolr |= E1000_VMOLR_ROMPE;
5339 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5340 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5341 }
5342 }
5343
5344 wr32(E1000_VMOLR(vf), vmolr);
5345
5346 /* there are flags left unprocessed, likely not supported */
5347 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5348 return -EINVAL;
5349
5350 return 0;
7d5753f0
AD		 5351}
5352
4ae196df
AD		 5353static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5354 u32 *msgbuf, u32 vf)
5355{
5356 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5357 u16 *hash_list = (u16 *)&msgbuf[1];
5358 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5359 int i;
5360
7d5753f0 5361 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5362 * to this VF for later use to restore when the PF multi cast
5363 * list changes
5364 */
5365 vf_data->num_vf_mc_hashes = n;
5366
7d5753f0
AD		 5367 /* only up to 30 hash values supported */
5368 if (n > 30)
5369 n = 30;
5370
5371 /* store the hashes for later use */
4ae196df 5372 for (i = 0; i < n; i++)
a419aef8 5373 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5374
5375 /* Flush and reset the mta with the new values */
ff41f8dc 5376 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5377
5378 return 0;
5379}
5380
5381static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5382{
5383 struct e1000_hw *hw = &adapter->hw;
5384 struct vf_data_storage *vf_data;
5385 int i, j;
5386
5387 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5388 u32 vmolr = rd32(E1000_VMOLR(i));
5389 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5390
4ae196df 5391 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5392
5393 if ((vf_data->num_vf_mc_hashes > 30) ||
5394 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5395 vmolr |= E1000_VMOLR_MPME;
5396 } else if (vf_data->num_vf_mc_hashes) {
5397 vmolr |= E1000_VMOLR_ROMPE;
5398 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5399 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5400 }
5401 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5402 }
5403}
5404
5405static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5406{
5407 struct e1000_hw *hw = &adapter->hw;
5408 u32 pool_mask, reg, vid;
5409 int i;
5410
5411 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5412
5413 /* Find the vlan filter for this id */
5414 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5415 reg = rd32(E1000_VLVF(i));
5416
5417 /* remove the vf from the pool */
5418 reg &= ~pool_mask;
5419
5420 /* if pool is empty then remove entry from vfta */
5421 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5422 (reg & E1000_VLVF_VLANID_ENABLE)) {
5423 reg = 0;
5424 vid = reg & E1000_VLVF_VLANID_MASK;
5425 igb_vfta_set(hw, vid, false);
5426 }
5427
5428 wr32(E1000_VLVF(i), reg);
5429 }
ae641bdc
AD		 5430
5431 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5432}
5433
5434static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5435{
5436 struct e1000_hw *hw = &adapter->hw;
5437 u32 reg, i;
5438
51466239
AD		 5439 /* The vlvf table only exists on 82576 hardware and newer */
5440 if (hw->mac.type < e1000_82576)
5441 return -1;
5442
5443 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5444 if (!adapter->vfs_allocated_count)
5445 return -1;
5446
5447 /* Find the vlan filter for this id */
5448 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5449 reg = rd32(E1000_VLVF(i));
5450 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5451 vid == (reg & E1000_VLVF_VLANID_MASK))
5452 break;
5453 }
5454
5455 if (add) {
5456 if (i == E1000_VLVF_ARRAY_SIZE) {
5457 /* Did not find a matching VLAN ID entry that was
5458 * enabled. Search for a free filter entry, i.e.
5459 * one without the enable bit set
5460 */
5461 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5462 reg = rd32(E1000_VLVF(i));
5463 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5464 break;
5465 }
5466 }
5467 if (i < E1000_VLVF_ARRAY_SIZE) {
5468 /* Found an enabled/available entry */
5469 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5470
5471 /* if !enabled we need to set this up in vfta */
5472 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5473 /* add VID to filter table */
5474 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5475 reg |= E1000_VLVF_VLANID_ENABLE;
5476 }
cad6d05f
AD		 5477 reg &= ~E1000_VLVF_VLANID_MASK;
5478 reg |= vid;
4ae196df 5479 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5480
5481 /* do not modify RLPML for PF devices */
5482 if (vf >= adapter->vfs_allocated_count)
5483 return 0;
5484
5485 if (!adapter->vf_data[vf].vlans_enabled) {
5486 u32 size;
5487 reg = rd32(E1000_VMOLR(vf));
5488 size = reg & E1000_VMOLR_RLPML_MASK;
5489 size += 4;
5490 reg &= ~E1000_VMOLR_RLPML_MASK;
5491 reg |= size;
5492 wr32(E1000_VMOLR(vf), reg);
5493 }
ae641bdc 5494
51466239 5495 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5496 }
5497 } else {
5498 if (i < E1000_VLVF_ARRAY_SIZE) {
5499 /* remove vf from the pool */
5500 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5501 /* if pool is empty then remove entry from vfta */
5502 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5503 reg = 0;
5504 igb_vfta_set(hw, vid, false);
5505 }
5506 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5507
5508 /* do not modify RLPML for PF devices */
5509 if (vf >= adapter->vfs_allocated_count)
5510 return 0;
5511
5512 adapter->vf_data[vf].vlans_enabled--;
5513 if (!adapter->vf_data[vf].vlans_enabled) {
5514 u32 size;
5515 reg = rd32(E1000_VMOLR(vf));
5516 size = reg & E1000_VMOLR_RLPML_MASK;
5517 size -= 4;
5518 reg &= ~E1000_VMOLR_RLPML_MASK;
5519 reg |= size;
5520 wr32(E1000_VMOLR(vf), reg);
5521 }
4ae196df
AD		 5522 }
5523 }
8151d294
WM		 5524 return 0;
5525}
5526
5527static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5528{
5529 struct e1000_hw *hw = &adapter->hw;
5530
5531 if (vid)
5532 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5533 else
5534 wr32(E1000_VMVIR(vf), 0);
5535}
5536
5537static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5538 int vf, u16 vlan, u8 qos)
5539{
5540 int err = 0;
5541 struct igb_adapter *adapter = netdev_priv(netdev);
5542
5543 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5544 return -EINVAL;
5545 if (vlan || qos) {
5546 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5547 if (err)
5548 goto out;
5549 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5550 igb_set_vmolr(adapter, vf, !vlan);
5551 adapter->vf_data[vf].pf_vlan = vlan;
5552 adapter->vf_data[vf].pf_qos = qos;
5553 dev_info(&adapter->pdev->dev,
5554 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5555 if (test_bit(__IGB_DOWN, &adapter->state)) {
5556 dev_warn(&adapter->pdev->dev,
b980ac18 5557 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5558 dev_warn(&adapter->pdev->dev,
b980ac18 5559 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5560 }
5561 } else {
5562 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5563 false, vf);
8151d294
WM		 5564 igb_set_vmvir(adapter, vlan, vf);
5565 igb_set_vmolr(adapter, vf, true);
5566 adapter->vf_data[vf].pf_vlan = 0;
5567 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5568 }
8151d294 5569out:
b980ac18 5570 return err;
4ae196df
AD		 5571}
5572
6f3dc319
GR		 5573static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5574{
5575 struct e1000_hw *hw = &adapter->hw;
5576 int i;
5577 u32 reg;
5578
5579 /* Find the vlan filter for this id */
5580 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5581 reg = rd32(E1000_VLVF(i));
5582 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5583 vid == (reg & E1000_VLVF_VLANID_MASK))
5584 break;
5585 }
5586
5587 if (i >= E1000_VLVF_ARRAY_SIZE)
5588 i = -1;
5589
5590 return i;
5591}
5592
4ae196df
AD		 5593static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5594{
6f3dc319 5595 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5596 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5597 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5598 int err = 0;
4ae196df 5599
6f3dc319
GR		 5600 /* If in promiscuous mode we need to make sure the PF also has
5601 * the VLAN filter set.
5602 */
5603 if (add && (adapter->netdev->flags & IFF_PROMISC))
5604 err = igb_vlvf_set(adapter, vid, add,
5605 adapter->vfs_allocated_count);
5606 if (err)
5607 goto out;
5608
5609 err = igb_vlvf_set(adapter, vid, add, vf);
5610
5611 if (err)
5612 goto out;
5613
5614 /* Go through all the checks to see if the VLAN filter should
5615 * be wiped completely.
5616 */
5617 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5618 u32 vlvf, bits;
5619
5620 int regndx = igb_find_vlvf_entry(adapter, vid);
5621 if (regndx < 0)
5622 goto out;
5623 /* See if any other pools are set for this VLAN filter
5624 * entry other than the PF.
5625 */
5626 vlvf = bits = rd32(E1000_VLVF(regndx));
5627 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5628 adapter->vfs_allocated_count);
5629 /* If the filter was removed then ensure PF pool bit
5630 * is cleared if the PF only added itself to the pool
5631 * because the PF is in promiscuous mode.
5632 */
5633 if ((vlvf & VLAN_VID_MASK) == vid &&
5634 !test_bit(vid, adapter->active_vlans) &&
5635 !bits)
5636 igb_vlvf_set(adapter, vid, add,
5637 adapter->vfs_allocated_count);
5638 }
5639
5640out:
5641 return err;
4ae196df
AD		 5642}
5643
f2ca0dbe 5644static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5645{
8fa7e0f7
GR		 5646 /* clear flags - except flag that indicates PF has set the MAC */
5647 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5648 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5649
5650 /* reset offloads to defaults */
8151d294 5651 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5652
5653 /* reset vlans for device */
5654 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5655 if (adapter->vf_data[vf].pf_vlan)
5656 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5657 adapter->vf_data[vf].pf_vlan,
5658 adapter->vf_data[vf].pf_qos);
5659 else
5660 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5661
5662 /* reset multicast table array for vf */
5663 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5664
5665 /* Flush and reset the mta with the new values */
ff41f8dc 5666 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5667}
5668
f2ca0dbe
AD		 5669static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5670{
5671 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5672
5ac6f91d 5673 /* clear mac address as we were hotplug removed/added */
8151d294 5674 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5675 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5676
5677 /* process remaining reset events */
5678 igb_vf_reset(adapter, vf);
5679}
5680
5681static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5682{
5683 struct e1000_hw *hw = &adapter->hw;
5684 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5685 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5686 u32 reg, msgbuf[3];
5687 u8 *addr = (u8 *)(&msgbuf[1]);
5688
5689 /* process all the same items cleared in a function level reset */
f2ca0dbe 5690 igb_vf_reset(adapter, vf);
4ae196df
AD		 5691
5692 /* set vf mac address */
26ad9178 5693 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5694
5695 /* enable transmit and receive for vf */
5696 reg = rd32(E1000_VFTE);
5697 wr32(E1000_VFTE, reg | (1 << vf));
5698 reg = rd32(E1000_VFRE);
5699 wr32(E1000_VFRE, reg | (1 << vf));
5700
8fa7e0f7 5701 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5702
5703 /* reply to reset with ack and vf mac address */
5704 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5705 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5706 igb_write_mbx(hw, msgbuf, 3, vf);
5707}
5708
5709static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5710{
b980ac18 5711 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5712 * starting at the second 32 bit word of the msg array
5713 */
f2ca0dbe
AD		 5714 unsigned char *addr = (char *)&msg[1];
5715 int err = -1;
4ae196df 5716
f2ca0dbe
AD		 5717 if (is_valid_ether_addr(addr))
5718 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5719
f2ca0dbe 5720 return err;
4ae196df
AD		 5721}
5722
5723static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5724{
5725 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5726 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5727 u32 msg = E1000_VT_MSGTYPE_NACK;
5728
5729 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5730 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5731 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5732 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5733 vf_data->last_nack = jiffies;
4ae196df
AD		 5734 }
5735}
5736
f2ca0dbe 5737static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5738{
f2ca0dbe
AD		 5739 struct pci_dev *pdev = adapter->pdev;
5740 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5741 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5742 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5743 s32 retval;
5744
f2ca0dbe 5745 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5746
fef45f4c
AD		 5747 if (retval) {
5748 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5749 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5750 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5751 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5752 return;
5753 goto out;
5754 }
4ae196df
AD		 5755
5756 /* this is a message we already processed, do nothing */
5757 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5758 return;
4ae196df 5759
b980ac18 5760 /* until the vf completes a reset it should not be
4ae196df
AD		 5761 * allowed to start any configuration.
5762 */
4ae196df
AD		 5763 if (msgbuf[0] == E1000_VF_RESET) {
5764 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5765 return;
4ae196df
AD		 5766 }
5767
f2ca0dbe 5768 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5769 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5770 return;
5771 retval = -1;
5772 goto out;
4ae196df
AD		 5773 }
5774
5775 switch ((msgbuf[0] & 0xFFFF)) {
5776 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5777 retval = -EINVAL;
5778 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5779 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5780 else
5781 dev_warn(&pdev->dev,
b980ac18
JK		 5782 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5783 vf);
4ae196df 5784 break;
7d5753f0
AD		 5785 case E1000_VF_SET_PROMISC:
5786 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5787 break;
4ae196df
AD		 5788 case E1000_VF_SET_MULTICAST:
5789 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5790 break;
5791 case E1000_VF_SET_LPE:
5792 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5793 break;
5794 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5795 retval = -1;
5796 if (vf_data->pf_vlan)
5797 dev_warn(&pdev->dev,
b980ac18
JK		 5798 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5799 vf);
8151d294
WM		 5800 else
5801 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5802 break;
5803 default:
090b1795 5804 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5805 retval = -1;
5806 break;
5807 }
5808
fef45f4c
AD		 5809 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5810out:
4ae196df
AD		 5811 /* notify the VF of the results of what it sent us */
5812 if (retval)
5813 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5814 else
5815 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5816
4ae196df 5817 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5818}
4ae196df 5819
f2ca0dbe
AD		 5820static void igb_msg_task(struct igb_adapter *adapter)
5821{
5822 struct e1000_hw *hw = &adapter->hw;
5823 u32 vf;
5824
5825 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5826 /* process any reset requests */
5827 if (!igb_check_for_rst(hw, vf))
5828 igb_vf_reset_event(adapter, vf);
5829
5830 /* process any messages pending */
5831 if (!igb_check_for_msg(hw, vf))
5832 igb_rcv_msg_from_vf(adapter, vf);
5833
5834 /* process any acks */
5835 if (!igb_check_for_ack(hw, vf))
5836 igb_rcv_ack_from_vf(adapter, vf);
5837 }
4ae196df
AD		 5838}
5839
68d480c4
AD		 5840/**
5841 * igb_set_uta - Set unicast filter table address
5842 * @adapter: board private structure
5843 *
5844 * The unicast table address is a register array of 32-bit registers.
5845 * The table is meant to be used in a way similar to how the MTA is used
5846 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5847 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5848 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5849 **/
5850static void igb_set_uta(struct igb_adapter *adapter)
5851{
5852 struct e1000_hw *hw = &adapter->hw;
5853 int i;
5854
5855 /* The UTA table only exists on 82576 hardware and newer */
5856 if (hw->mac.type < e1000_82576)
5857 return;
5858
5859 /* we only need to do this if VMDq is enabled */
5860 if (!adapter->vfs_allocated_count)
5861 return;
5862
5863 for (i = 0; i < hw->mac.uta_reg_count; i++)
5864 array_wr32(E1000_UTA, i, ~0);
5865}
5866
9d5c8243 5867/**
b980ac18
JK		 5868 * igb_intr_msi - Interrupt Handler
5869 * @irq: interrupt number
5870 * @data: pointer to a network interface device structure
9d5c8243
AK		 5871 **/
5872static irqreturn_t igb_intr_msi(int irq, void *data)
5873{
047e0030
AD		 5874 struct igb_adapter *adapter = data;
5875 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5876 struct e1000_hw *hw = &adapter->hw;
5877 /* read ICR disables interrupts using IAM */
5878 u32 icr = rd32(E1000_ICR);
5879
047e0030 5880 igb_write_itr(q_vector);
9d5c8243 5881
7f081d40
AD		 5882 if (icr & E1000_ICR_DRSTA)
5883 schedule_work(&adapter->reset_task);
5884
047e0030 5885 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5886 /* HW is reporting DMA is out of sync */
5887 adapter->stats.doosync++;
5888 }
5889
9d5c8243
AK		 5890 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5891 hw->mac.get_link_status = 1;
5892 if (!test_bit(__IGB_DOWN, &adapter->state))
5893 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5894 }
5895
1f6e8178
MV		 5896 if (icr & E1000_ICR_TS) {
5897 u32 tsicr = rd32(E1000_TSICR);
5898
5899 if (tsicr & E1000_TSICR_TXTS) {
5900 /* acknowledge the interrupt */
5901 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5902 /* retrieve hardware timestamp */
5903 schedule_work(&adapter->ptp_tx_work);
5904 }
5905 }
1f6e8178 5906
047e0030 5907 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5908
5909 return IRQ_HANDLED;
5910}
5911
5912/**
b980ac18
JK		 5913 * igb_intr - Legacy Interrupt Handler
5914 * @irq: interrupt number
5915 * @data: pointer to a network interface device structure
9d5c8243
AK		 5916 **/
5917static irqreturn_t igb_intr(int irq, void *data)
5918{
047e0030
AD		 5919 struct igb_adapter *adapter = data;
5920 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5921 struct e1000_hw *hw = &adapter->hw;
5922 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5923 * need for the IMC write
5924 */
9d5c8243 5925 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5926
5927 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5928 * not set, then the adapter didn't send an interrupt
5929 */
9d5c8243
AK		 5930 if (!(icr & E1000_ICR_INT_ASSERTED))
5931 return IRQ_NONE;
5932
0ba82994
AD		 5933 igb_write_itr(q_vector);
5934
7f081d40
AD		 5935 if (icr & E1000_ICR_DRSTA)
5936 schedule_work(&adapter->reset_task);
5937
047e0030 5938 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5939 /* HW is reporting DMA is out of sync */
5940 adapter->stats.doosync++;
5941 }
5942
9d5c8243
AK		 5943 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5944 hw->mac.get_link_status = 1;
5945 /* guard against interrupt when we're going down */
5946 if (!test_bit(__IGB_DOWN, &adapter->state))
5947 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5948 }
5949
1f6e8178
MV		 5950 if (icr & E1000_ICR_TS) {
5951 u32 tsicr = rd32(E1000_TSICR);
5952
5953 if (tsicr & E1000_TSICR_TXTS) {
5954 /* acknowledge the interrupt */
5955 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5956 /* retrieve hardware timestamp */
5957 schedule_work(&adapter->ptp_tx_work);
5958 }
5959 }
1f6e8178 5960
047e0030 5961 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5962
5963 return IRQ_HANDLED;
5964}
5965
c50b52a0 5966static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5967{
047e0030 5968 struct igb_adapter *adapter = q_vector->adapter;
46544258 5969 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5970
0ba82994
AD		 5971 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5972 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5973 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5974 igb_set_itr(q_vector);
46544258 5975 else
047e0030 5976 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5977 }
5978
46544258
AD		 5979 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5980 if (adapter->msix_entries)
047e0030 5981 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5982 else
5983 igb_irq_enable(adapter);
5984 }
9d5c8243
AK		 5985}
5986
46544258 5987/**
b980ac18
JK		 5988 * igb_poll - NAPI Rx polling callback
5989 * @napi: napi polling structure
5990 * @budget: count of how many packets we should handle
46544258
AD		 5991 **/
5992static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5993{
047e0030 5994 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 5995 struct igb_q_vector,
5996 napi);
16eb8815 5997 bool clean_complete = true;
9d5c8243 5998
421e02f0 5999#ifdef CONFIG_IGB_DCA
047e0030
AD		 6000 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6001 igb_update_dca(q_vector);
fe4506b6 6002#endif
0ba82994 6003 if (q_vector->tx.ring)
13fde97a 6004 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6005
0ba82994 6006 if (q_vector->rx.ring)
cd392f5c 6007 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6008
16eb8815
AD		 6009 /* If all work not completed, return budget and keep polling */
6010 if (!clean_complete)
6011 return budget;
46544258 6012
9d5c8243 6013 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6014 napi_complete(napi);
6015 igb_ring_irq_enable(q_vector);
9d5c8243 6016
16eb8815 6017 return 0;
9d5c8243 6018}
6d8126f9 6019
9d5c8243 6020/**
b980ac18
JK		 6021 * igb_clean_tx_irq - Reclaim resources after transmit completes
6022 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6023 *
b980ac18 6024 * returns true if ring is completely cleaned
9d5c8243 6025 **/
047e0030 6026static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6027{
047e0030 6028 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6029 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6030 struct igb_tx_buffer *tx_buffer;
f4128785 6031 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6032 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6033 unsigned int budget = q_vector->tx.work_limit;
8542db05 6034 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6035
13fde97a
AD		 6036 if (test_bit(__IGB_DOWN, &adapter->state))
6037 return true;
0e014cb1 6038
06034649 6039 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6040 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6041 i -= tx_ring->count;
9d5c8243 6042
f4128785
AD		 6043 do {
6044 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6045
6046 /* if next_to_watch is not set then there is no work pending */
6047 if (!eop_desc)
6048 break;
13fde97a 6049
f4128785 6050 /* prevent any other reads prior to eop_desc */
70d289bc 6051 read_barrier_depends();
f4128785 6052
13fde97a
AD		 6053 /* if DD is not set pending work has not been completed */
6054 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6055 break;
6056
8542db05
AD		 6057 /* clear next_to_watch to prevent false hangs */
6058 tx_buffer->next_to_watch = NULL;
9d5c8243 6059
ebe42d16
AD		 6060 /* update the statistics for this packet */
6061 total_bytes += tx_buffer->bytecount;
6062 total_packets += tx_buffer->gso_segs;
13fde97a 6063
ebe42d16
AD		 6064 /* free the skb */
6065 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6066
ebe42d16
AD		 6067 /* unmap skb header data */
6068 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6069 dma_unmap_addr(tx_buffer, dma),
6070 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6071 DMA_TO_DEVICE);
6072
c9f14bf3
AD		 6073 /* clear tx_buffer data */
6074 tx_buffer->skb = NULL;
6075 dma_unmap_len_set(tx_buffer, len, 0);
6076
ebe42d16
AD		 6077 /* clear last DMA location and unmap remaining buffers */
6078 while (tx_desc != eop_desc) {
13fde97a
AD		 6079 tx_buffer++;
6080 tx_desc++;
9d5c8243 6081 i++;
8542db05
AD		 6082 if (unlikely(!i)) {
6083 i -= tx_ring->count;
06034649 6084 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6085 tx_desc = IGB_TX_DESC(tx_ring, 0);
6086 }
ebe42d16
AD		 6087
6088 /* unmap any remaining paged data */
c9f14bf3 6089 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6090 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6091 dma_unmap_addr(tx_buffer, dma),
6092 dma_unmap_len(tx_buffer, len),
ebe42d16 6093 DMA_TO_DEVICE);
c9f14bf3 6094 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6095 }
6096 }
6097
ebe42d16
AD		 6098 /* move us one more past the eop_desc for start of next pkt */
6099 tx_buffer++;
6100 tx_desc++;
6101 i++;
6102 if (unlikely(!i)) {
6103 i -= tx_ring->count;
6104 tx_buffer = tx_ring->tx_buffer_info;
6105 tx_desc = IGB_TX_DESC(tx_ring, 0);
6106 }
f4128785
AD		 6107
6108 /* issue prefetch for next Tx descriptor */
6109 prefetch(tx_desc);
6110
6111 /* update budget accounting */
6112 budget--;
6113 } while (likely(budget));
0e014cb1 6114
bdbc0631
ED		 6115 netdev_tx_completed_queue(txring_txq(tx_ring),
6116 total_packets, total_bytes);
8542db05 6117 i += tx_ring->count;
9d5c8243 6118 tx_ring->next_to_clean = i;
13fde97a
AD		 6119 u64_stats_update_begin(&tx_ring->tx_syncp);
6120 tx_ring->tx_stats.bytes += total_bytes;
6121 tx_ring->tx_stats.packets += total_packets;
6122 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6123 q_vector->tx.total_bytes += total_bytes;
6124 q_vector->tx.total_packets += total_packets;
9d5c8243 6125
6d095fa8 6126 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6127 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6128
9d5c8243 6129 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6130 * check with the clearing of time_stamp and movement of i
6131 */
6d095fa8 6132 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6133 if (tx_buffer->next_to_watch &&
8542db05 6134 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6135 (adapter->tx_timeout_factor * HZ)) &&
6136 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6137
9d5c8243 6138 /* detected Tx unit hang */
59d71989 6139 dev_err(tx_ring->dev,
9d5c8243 6140 "Detected Tx Unit Hang\n"
2d064c06 6141 " Tx Queue <%d>\n"
9d5c8243
AK		 6142 " TDH <%x>\n"
6143 " TDT <%x>\n"
6144 " next_to_use <%x>\n"
6145 " next_to_clean <%x>\n"
9d5c8243
AK		 6146 "buffer_info[next_to_clean]\n"
6147 " time_stamp <%lx>\n"
8542db05 6148 " next_to_watch <%p>\n"
9d5c8243
AK		 6149 " jiffies <%lx>\n"
6150 " desc.status <%x>\n",
2d064c06 6151 tx_ring->queue_index,
238ac817 6152 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6153 readl(tx_ring->tail),
9d5c8243
AK		 6154 tx_ring->next_to_use,
6155 tx_ring->next_to_clean,
8542db05 6156 tx_buffer->time_stamp,
f4128785 6157 tx_buffer->next_to_watch,
9d5c8243 6158 jiffies,
f4128785 6159 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6160 netif_stop_subqueue(tx_ring->netdev,
6161 tx_ring->queue_index);
6162
6163 /* we are about to reset, no point in enabling stuff */
6164 return true;
9d5c8243
AK		 6165 }
6166 }
13fde97a 6167
21ba6fe1 6168#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6169 if (unlikely(total_packets &&
b980ac18
JK		 6170 netif_carrier_ok(tx_ring->netdev) &&
6171 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6172 /* Make sure that anybody stopping the queue after this
6173 * sees the new next_to_clean.
6174 */
6175 smp_mb();
6176 if (__netif_subqueue_stopped(tx_ring->netdev,
6177 tx_ring->queue_index) &&
6178 !(test_bit(__IGB_DOWN, &adapter->state))) {
6179 netif_wake_subqueue(tx_ring->netdev,
6180 tx_ring->queue_index);
6181
6182 u64_stats_update_begin(&tx_ring->tx_syncp);
6183 tx_ring->tx_stats.restart_queue++;
6184 u64_stats_update_end(&tx_ring->tx_syncp);
6185 }
6186 }
6187
6188 return !!budget;
9d5c8243
AK		 6189}
6190
cbc8e55f 6191/**
b980ac18
JK		 6192 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6193 * @rx_ring: rx descriptor ring to store buffers on
6194 * @old_buff: donor buffer to have page reused
cbc8e55f 6195 *
b980ac18 6196 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6197 **/
6198static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6199 struct igb_rx_buffer *old_buff)
6200{
6201 struct igb_rx_buffer *new_buff;
6202 u16 nta = rx_ring->next_to_alloc;
6203
6204 new_buff = &rx_ring->rx_buffer_info[nta];
6205
6206 /* update, and store next to alloc */
6207 nta++;
6208 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6209
6210 /* transfer page from old buffer to new buffer */
6211 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6212
6213 /* sync the buffer for use by the device */
6214 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6215 old_buff->page_offset,
de78d1f9 6216 IGB_RX_BUFSZ,
cbc8e55f
AD		 6217 DMA_FROM_DEVICE);
6218}
6219
74e238ea
AD		 6220static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6221 struct page *page,
6222 unsigned int truesize)
6223{
6224 /* avoid re-using remote pages */
6225 if (unlikely(page_to_nid(page) != numa_node_id()))
6226 return false;
6227
6228#if (PAGE_SIZE < 8192)
6229 /* if we are only owner of page we can reuse it */
6230 if (unlikely(page_count(page) != 1))
6231 return false;
6232
6233 /* flip page offset to other buffer */
6234 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6235
6236 /* since we are the only owner of the page and we need to
6237 * increment it, just set the value to 2 in order to avoid
6238 * an unnecessary locked operation
6239 */
6240 atomic_set(&page->_count, 2);
6241#else
6242 /* move offset up to the next cache line */
6243 rx_buffer->page_offset += truesize;
6244
6245 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6246 return false;
6247
6248 /* bump ref count on page before it is given to the stack */
6249 get_page(page);
6250#endif
6251
6252 return true;
6253}
6254
cbc8e55f 6255/**
b980ac18
JK		 6256 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6257 * @rx_ring: rx descriptor ring to transact packets on
6258 * @rx_buffer: buffer containing page to add
6259 * @rx_desc: descriptor containing length of buffer written by hardware
6260 * @skb: sk_buff to place the data into
cbc8e55f 6261 *
b980ac18
JK		 6262 * This function will add the data contained in rx_buffer->page to the skb.
6263 * This is done either through a direct copy if the data in the buffer is
6264 * less than the skb header size, otherwise it will just attach the page as
6265 * a frag to the skb.
cbc8e55f 6266 *
b980ac18
JK		 6267 * The function will then update the page offset if necessary and return
6268 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6269 **/
6270static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6271 struct igb_rx_buffer *rx_buffer,
6272 union e1000_adv_rx_desc *rx_desc,
6273 struct sk_buff *skb)
6274{
6275 struct page *page = rx_buffer->page;
6276 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6277#if (PAGE_SIZE < 8192)
6278 unsigned int truesize = IGB_RX_BUFSZ;
6279#else
6280 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6281#endif
cbc8e55f
AD		 6282
6283 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6284 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6285
cbc8e55f
AD		 6286 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6287 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6288 va += IGB_TS_HDR_LEN;
6289 size -= IGB_TS_HDR_LEN;
6290 }
6291
cbc8e55f
AD		 6292 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6293
6294 /* we can reuse buffer as-is, just make sure it is local */
6295 if (likely(page_to_nid(page) == numa_node_id()))
6296 return true;
6297
6298 /* this page cannot be reused so discard it */
6299 put_page(page);
6300 return false;
6301 }
6302
6303 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6304 rx_buffer->page_offset, size, truesize);
cbc8e55f 6305
74e238ea
AD		 6306 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6307}
cbc8e55f 6308
2e334eee
AD		 6309static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6310 union e1000_adv_rx_desc *rx_desc,
6311 struct sk_buff *skb)
6312{
6313 struct igb_rx_buffer *rx_buffer;
6314 struct page *page;
6315
6316 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6317
2e334eee
AD		 6318 page = rx_buffer->page;
6319 prefetchw(page);
6320
6321 if (likely(!skb)) {
6322 void *page_addr = page_address(page) +
6323 rx_buffer->page_offset;
6324
6325 /* prefetch first cache line of first page */
6326 prefetch(page_addr);
6327#if L1_CACHE_BYTES < 128
6328 prefetch(page_addr + L1_CACHE_BYTES);
6329#endif
6330
6331 /* allocate a skb to store the frags */
6332 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6333 IGB_RX_HDR_LEN);
6334 if (unlikely(!skb)) {
6335 rx_ring->rx_stats.alloc_failed++;
6336 return NULL;
6337 }
6338
b980ac18 6339 /* we will be copying header into skb->data in
2e334eee
AD		 6340 * pskb_may_pull so it is in our interest to prefetch
6341 * it now to avoid a possible cache miss
6342 */
6343 prefetchw(skb->data);
6344 }
6345
6346 /* we are reusing so sync this buffer for CPU use */
6347 dma_sync_single_range_for_cpu(rx_ring->dev,
6348 rx_buffer->dma,
6349 rx_buffer->page_offset,
de78d1f9 6350 IGB_RX_BUFSZ,
2e334eee
AD		 6351 DMA_FROM_DEVICE);
6352
6353 /* pull page into skb */
6354 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6355 /* hand second half of page back to the ring */
6356 igb_reuse_rx_page(rx_ring, rx_buffer);
6357 } else {
6358 /* we are not reusing the buffer so unmap it */
6359 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6360 PAGE_SIZE, DMA_FROM_DEVICE);
6361 }
6362
6363 /* clear contents of rx_buffer */
6364 rx_buffer->page = NULL;
6365
6366 return skb;
6367}
6368
cd392f5c 6369static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6370 union e1000_adv_rx_desc *rx_desc,
6371 struct sk_buff *skb)
9d5c8243 6372{
bc8acf2c 6373 skb_checksum_none_assert(skb);
9d5c8243 6374
294e7d78 6375 /* Ignore Checksum bit is set */
3ceb90fd 6376 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6377 return;
6378
6379 /* Rx checksum disabled via ethtool */
6380 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6381 return;
85ad76b2 6382
9d5c8243 6383 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6384 if (igb_test_staterr(rx_desc,
6385 E1000_RXDEXT_STATERR_TCPE |
6386 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6387 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6388 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6389 * packets, (aka let the stack check the crc32c)
6390 */
866cff06
AD		 6391 if (!((skb->len == 60) &&
6392 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6393 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6394 ring->rx_stats.csum_err++;
12dcd86b
ED		 6395 u64_stats_update_end(&ring->rx_syncp);
6396 }
9d5c8243 6397 /* let the stack verify checksum errors */
9d5c8243
AK		 6398 return;
6399 }
6400 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6401 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6402 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6403 skb->ip_summed = CHECKSUM_UNNECESSARY;
6404
3ceb90fd
AD		 6405 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6406 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6407}
6408
077887c3
AD		 6409static inline void igb_rx_hash(struct igb_ring *ring,
6410 union e1000_adv_rx_desc *rx_desc,
6411 struct sk_buff *skb)
6412{
6413 if (ring->netdev->features & NETIF_F_RXHASH)
6414 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6415}
6416
2e334eee 6417/**
b980ac18
JK		 6418 * igb_is_non_eop - process handling of non-EOP buffers
6419 * @rx_ring: Rx ring being processed
6420 * @rx_desc: Rx descriptor for current buffer
6421 * @skb: current socket buffer containing buffer in progress
2e334eee 6422 *
b980ac18
JK		 6423 * This function updates next to clean. If the buffer is an EOP buffer
6424 * this function exits returning false, otherwise it will place the
6425 * sk_buff in the next buffer to be chained and return true indicating
6426 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6427 **/
6428static bool igb_is_non_eop(struct igb_ring *rx_ring,
6429 union e1000_adv_rx_desc *rx_desc)
6430{
6431 u32 ntc = rx_ring->next_to_clean + 1;
6432
6433 /* fetch, update, and store next to clean */
6434 ntc = (ntc < rx_ring->count) ? ntc : 0;
6435 rx_ring->next_to_clean = ntc;
6436
6437 prefetch(IGB_RX_DESC(rx_ring, ntc));
6438
6439 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6440 return false;
6441
6442 return true;
6443}
6444
1a1c225b 6445/**
b980ac18
JK		 6446 * igb_get_headlen - determine size of header for LRO/GRO
6447 * @data: pointer to the start of the headers
6448 * @max_len: total length of section to find headers in
1a1c225b 6449 *
b980ac18
JK		 6450 * This function is meant to determine the length of headers that will
6451 * be recognized by hardware for LRO, and GRO offloads. The main
6452 * motivation of doing this is to only perform one pull for IPv4 TCP
6453 * packets so that we can do basic things like calculating the gso_size
6454 * based on the average data per packet.
1a1c225b
AD		 6455 **/
6456static unsigned int igb_get_headlen(unsigned char *data,
6457 unsigned int max_len)
6458{
6459 union {
6460 unsigned char *network;
6461 /* l2 headers */
6462 struct ethhdr *eth;
6463 struct vlan_hdr *vlan;
6464 /* l3 headers */
6465 struct iphdr *ipv4;
6466 struct ipv6hdr *ipv6;
6467 } hdr;
6468 __be16 protocol;
6469 u8 nexthdr = 0; /* default to not TCP */
6470 u8 hlen;
6471
6472 /* this should never happen, but better safe than sorry */
6473 if (max_len < ETH_HLEN)
6474 return max_len;
6475
6476 /* initialize network frame pointer */
6477 hdr.network = data;
6478
6479 /* set first protocol and move network header forward */
6480 protocol = hdr.eth->h_proto;
6481 hdr.network += ETH_HLEN;
6482
6483 /* handle any vlan tag if present */
6484 if (protocol == __constant_htons(ETH_P_8021Q)) {
6485 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6486 return max_len;
6487
6488 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6489 hdr.network += VLAN_HLEN;
6490 }
6491
6492 /* handle L3 protocols */
6493 if (protocol == __constant_htons(ETH_P_IP)) {
6494 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6495 return max_len;
6496
6497 /* access ihl as a u8 to avoid unaligned access on ia64 */
6498 hlen = (hdr.network[0] & 0x0F) << 2;
6499
6500 /* verify hlen meets minimum size requirements */
6501 if (hlen < sizeof(struct iphdr))
6502 return hdr.network - data;
6503
f2fb4ab2 6504 /* record next protocol if header is present */
b9555f66 6505 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6506 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6507 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6508 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6509 return max_len;
6510
6511 /* record next protocol */
6512 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6513 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6514 } else {
6515 return hdr.network - data;
6516 }
6517
f2fb4ab2
AD		 6518 /* relocate pointer to start of L4 header */
6519 hdr.network += hlen;
6520
1a1c225b
AD		 6521 /* finally sort out TCP */
6522 if (nexthdr == IPPROTO_TCP) {
6523 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6524 return max_len;
6525
6526 /* access doff as a u8 to avoid unaligned access on ia64 */
6527 hlen = (hdr.network[12] & 0xF0) >> 2;
6528
6529 /* verify hlen meets minimum size requirements */
6530 if (hlen < sizeof(struct tcphdr))
6531 return hdr.network - data;
6532
6533 hdr.network += hlen;
6534 } else if (nexthdr == IPPROTO_UDP) {
6535 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6536 return max_len;
6537
6538 hdr.network += sizeof(struct udphdr);
6539 }
6540
b980ac18 6541 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6542 * data section of the packet and will be the end of the header.
6543 * If not then it probably represents the end of the last recognized
6544 * header.
6545 */
6546 if ((hdr.network - data) < max_len)
6547 return hdr.network - data;
6548 else
6549 return max_len;
6550}
6551
6552/**
b980ac18
JK		 6553 * igb_pull_tail - igb specific version of skb_pull_tail
6554 * @rx_ring: rx descriptor ring packet is being transacted on
6555 * @rx_desc: pointer to the EOP Rx descriptor
6556 * @skb: pointer to current skb being adjusted
1a1c225b 6557 *
b980ac18
JK		 6558 * This function is an igb specific version of __pskb_pull_tail. The
6559 * main difference between this version and the original function is that
6560 * this function can make several assumptions about the state of things
6561 * that allow for significant optimizations versus the standard function.
6562 * As a result we can do things like drop a frag and maintain an accurate
6563 * truesize for the skb.
1a1c225b
AD		 6564 */
6565static void igb_pull_tail(struct igb_ring *rx_ring,
6566 union e1000_adv_rx_desc *rx_desc,
6567 struct sk_buff *skb)
2d94d8ab 6568{
1a1c225b
AD		 6569 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6570 unsigned char *va;
6571 unsigned int pull_len;
6572
b980ac18 6573 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6574 * working with pages allocated out of the lomem pool per
6575 * alloc_page(GFP_ATOMIC)
2d94d8ab 6576 */
1a1c225b
AD		 6577 va = skb_frag_address(frag);
6578
1a1c225b
AD		 6579 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6580 /* retrieve timestamp from buffer */
6581 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6582
6583 /* update pointers to remove timestamp header */
6584 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6585 frag->page_offset += IGB_TS_HDR_LEN;
6586 skb->data_len -= IGB_TS_HDR_LEN;
6587 skb->len -= IGB_TS_HDR_LEN;
6588
6589 /* move va to start of packet data */
6590 va += IGB_TS_HDR_LEN;
6591 }
6592
b980ac18 6593 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6594 * 60 bytes if the skb->len is less than 60 for skb_pad.
6595 */
6596 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6597
6598 /* align pull length to size of long to optimize memcpy performance */
6599 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6600
6601 /* update all of the pointers */
6602 skb_frag_size_sub(frag, pull_len);
6603 frag->page_offset += pull_len;
6604 skb->data_len -= pull_len;
6605 skb->tail += pull_len;
6606}
6607
6608/**
b980ac18
JK		 6609 * igb_cleanup_headers - Correct corrupted or empty headers
6610 * @rx_ring: rx descriptor ring packet is being transacted on
6611 * @rx_desc: pointer to the EOP Rx descriptor
6612 * @skb: pointer to current skb being fixed
1a1c225b 6613 *
b980ac18
JK		 6614 * Address the case where we are pulling data in on pages only
6615 * and as such no data is present in the skb header.
1a1c225b 6616 *
b980ac18
JK		 6617 * In addition if skb is not at least 60 bytes we need to pad it so that
6618 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6619 *
b980ac18 6620 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6621 **/
6622static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6623 union e1000_adv_rx_desc *rx_desc,
6624 struct sk_buff *skb)
6625{
1a1c225b
AD		 6626 if (unlikely((igb_test_staterr(rx_desc,
6627 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6628 struct net_device *netdev = rx_ring->netdev;
6629 if (!(netdev->features & NETIF_F_RXALL)) {
6630 dev_kfree_skb_any(skb);
6631 return true;
6632 }
6633 }
6634
6635 /* place header in linear portion of buffer */
6636 if (skb_is_nonlinear(skb))
6637 igb_pull_tail(rx_ring, rx_desc, skb);
6638
6639 /* if skb_pad returns an error the skb was freed */
6640 if (unlikely(skb->len < 60)) {
6641 int pad_len = 60 - skb->len;
6642
6643 if (skb_pad(skb, pad_len))
6644 return true;
6645 __skb_put(skb, pad_len);
6646 }
6647
6648 return false;
2d94d8ab
AD		 6649}
6650
db2ee5bd 6651/**
b980ac18
JK		 6652 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6653 * @rx_ring: rx descriptor ring packet is being transacted on
6654 * @rx_desc: pointer to the EOP Rx descriptor
6655 * @skb: pointer to current skb being populated
db2ee5bd 6656 *
b980ac18
JK		 6657 * This function checks the ring, descriptor, and packet information in
6658 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6659 * other fields within the skb.
db2ee5bd
AD		 6660 **/
6661static void igb_process_skb_fields(struct igb_ring *rx_ring,
6662 union e1000_adv_rx_desc *rx_desc,
6663 struct sk_buff *skb)
6664{
6665 struct net_device *dev = rx_ring->netdev;
6666
6667 igb_rx_hash(rx_ring, rx_desc, skb);
6668
6669 igb_rx_checksum(rx_ring, rx_desc, skb);
6670
20a48412 6671 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6672
f646968f 6673 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6674 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6675 u16 vid;
6676 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6677 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6678 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6679 else
6680 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6681
86a9bad3 6682 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6683 }
6684
6685 skb_record_rx_queue(skb, rx_ring->queue_index);
6686
6687 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6688}
6689
2e334eee 6690static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6691{
0ba82994 6692 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6693 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6694 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6695 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6696
2e334eee
AD		 6697 do {
6698 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6699
2e334eee
AD		 6700 /* return some buffers to hardware, one at a time is too slow */
6701 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6702 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6703 cleaned_count = 0;
6704 }
bf36c1a0 6705
2e334eee 6706 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6707
2e334eee
AD		 6708 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6709 break;
9d5c8243 6710
74e238ea
AD		 6711 /* This memory barrier is needed to keep us from reading
6712 * any other fields out of the rx_desc until we know the
6713 * RXD_STAT_DD bit is set
6714 */
6715 rmb();
6716
2e334eee 6717 /* retrieve a buffer from the ring */
f9d40f6a 6718 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6719
2e334eee
AD		 6720 /* exit if we failed to retrieve a buffer */
6721 if (!skb)
6722 break;
1a1c225b 6723
2e334eee 6724 cleaned_count++;
1a1c225b 6725
2e334eee
AD		 6726 /* fetch next buffer in frame if non-eop */
6727 if (igb_is_non_eop(rx_ring, rx_desc))
6728 continue;
1a1c225b
AD		 6729
6730 /* verify the packet layout is correct */
6731 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6732 skb = NULL;
6733 continue;
9d5c8243 6734 }
9d5c8243 6735
db2ee5bd 6736 /* probably a little skewed due to removing CRC */
3ceb90fd 6737 total_bytes += skb->len;
3ceb90fd 6738
db2ee5bd
AD		 6739 /* populate checksum, timestamp, VLAN, and protocol */
6740 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6741
b2cb09b1 6742 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6743
1a1c225b
AD		 6744 /* reset skb pointer */
6745 skb = NULL;
6746
2e334eee
AD		 6747 /* update budget accounting */
6748 total_packets++;
6749 } while (likely(total_packets < budget));
bf36c1a0 6750
1a1c225b
AD		 6751 /* place incomplete frames back on ring for completion */
6752 rx_ring->skb = skb;
6753
12dcd86b 6754 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6755 rx_ring->rx_stats.packets += total_packets;
6756 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6757 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6758 q_vector->rx.total_packets += total_packets;
6759 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6760
6761 if (cleaned_count)
cd392f5c 6762 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6763
2e334eee 6764 return (total_packets < budget);
9d5c8243
AK		 6765}
6766
c023cd88 6767static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6768 struct igb_rx_buffer *bi)
c023cd88
AD		 6769{
6770 struct page *page = bi->page;
cbc8e55f 6771 dma_addr_t dma;
c023cd88 6772
cbc8e55f
AD		 6773 /* since we are recycling buffers we should seldom need to alloc */
6774 if (likely(page))
c023cd88
AD		 6775 return true;
6776
cbc8e55f
AD		 6777 /* alloc new page for storage */
6778 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6779 if (unlikely(!page)) {
6780 rx_ring->rx_stats.alloc_failed++;
6781 return false;
c023cd88
AD		 6782 }
6783
cbc8e55f
AD		 6784 /* map page for use */
6785 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6786
b980ac18 6787 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6788 * there isn't much point in holding memory we can't use
6789 */
1a1c225b 6790 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6791 __free_page(page);
6792
c023cd88
AD		 6793 rx_ring->rx_stats.alloc_failed++;
6794 return false;
6795 }
6796
1a1c225b 6797 bi->dma = dma;
cbc8e55f
AD		 6798 bi->page = page;
6799 bi->page_offset = 0;
1a1c225b 6800
c023cd88
AD		 6801 return true;
6802}
6803
9d5c8243 6804/**
b980ac18
JK		 6805 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6806 * @adapter: address of board private structure
9d5c8243 6807 **/
cd392f5c 6808void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6809{
9d5c8243 6810 union e1000_adv_rx_desc *rx_desc;
06034649 6811 struct igb_rx_buffer *bi;
c023cd88 6812 u16 i = rx_ring->next_to_use;
9d5c8243 6813
cbc8e55f
AD		 6814 /* nothing to do */
6815 if (!cleaned_count)
6816 return;
6817
60136906 6818 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6819 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6820 i -= rx_ring->count;
9d5c8243 6821
cbc8e55f 6822 do {
1a1c225b 6823 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6824 break;
9d5c8243 6825
b980ac18 6826 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6827 * because each write-back erases this info.
6828 */
f9d40f6a 6829 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6830
c023cd88
AD		 6831 rx_desc++;
6832 bi++;
9d5c8243 6833 i++;
c023cd88 6834 if (unlikely(!i)) {
60136906 6835 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6836 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6837 i -= rx_ring->count;
6838 }
6839
6840 /* clear the hdr_addr for the next_to_use descriptor */
6841 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6842
6843 cleaned_count--;
6844 } while (cleaned_count);
9d5c8243 6845
c023cd88
AD		 6846 i += rx_ring->count;
6847
9d5c8243 6848 if (rx_ring->next_to_use != i) {
cbc8e55f 6849 /* record the next descriptor to use */
9d5c8243 6850 rx_ring->next_to_use = i;
9d5c8243 6851
cbc8e55f
AD		 6852 /* update next to alloc since we have filled the ring */
6853 rx_ring->next_to_alloc = i;
6854
b980ac18 6855 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6856 * know there are new descriptors to fetch. (Only
6857 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6858 * such as IA-64).
6859 */
9d5c8243 6860 wmb();
fce99e34 6861 writel(i, rx_ring->tail);
9d5c8243
AK		 6862 }
6863}
6864
6865/**
6866 * igb_mii_ioctl -
6867 * @netdev:
6868 * @ifreq:
6869 * @cmd:
6870 **/
6871static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6872{
6873 struct igb_adapter *adapter = netdev_priv(netdev);
6874 struct mii_ioctl_data *data = if_mii(ifr);
6875
6876 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6877 return -EOPNOTSUPP;
6878
6879 switch (cmd) {
6880 case SIOCGMIIPHY:
6881 data->phy_id = adapter->hw.phy.addr;
6882 break;
6883 case SIOCGMIIREG:
f5f4cf08
AD		 6884 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6885 &data->val_out))
9d5c8243
AK		 6886 return -EIO;
6887 break;
6888 case SIOCSMIIREG:
6889 default:
6890 return -EOPNOTSUPP;
6891 }
6892 return 0;
6893}
6894
6895/**
6896 * igb_ioctl -
6897 * @netdev:
6898 * @ifreq:
6899 * @cmd:
6900 **/
6901static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6902{
6903 switch (cmd) {
6904 case SIOCGMIIPHY:
6905 case SIOCGMIIREG:
6906 case SIOCSMIIREG:
6907 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6908 case SIOCSHWTSTAMP:
a79f4f88 6909 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6910 default:
6911 return -EOPNOTSUPP;
6912 }
6913}
6914
009bc06e
AD		 6915s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6916{
6917 struct igb_adapter *adapter = hw->back;
009bc06e 6918
23d028cc 6919 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6920 return -E1000_ERR_CONFIG;
6921
009bc06e
AD		 6922 return 0;
6923}
6924
6925s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6926{
6927 struct igb_adapter *adapter = hw->back;
009bc06e 6928
23d028cc 6929 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6930 return -E1000_ERR_CONFIG;
6931
009bc06e
AD		 6932 return 0;
6933}
6934
c8f44aff 6935static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6936{
6937 struct igb_adapter *adapter = netdev_priv(netdev);
6938 struct e1000_hw *hw = &adapter->hw;
6939 u32 ctrl, rctl;
f646968f 6940 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6941
5faf030c 6942 if (enable) {
9d5c8243
AK		 6943 /* enable VLAN tag insert/strip */
6944 ctrl = rd32(E1000_CTRL);
6945 ctrl |= E1000_CTRL_VME;
6946 wr32(E1000_CTRL, ctrl);
6947
51466239 6948 /* Disable CFI check */
9d5c8243 6949 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6950 rctl &= ~E1000_RCTL_CFIEN;
6951 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6952 } else {
6953 /* disable VLAN tag insert/strip */
6954 ctrl = rd32(E1000_CTRL);
6955 ctrl &= ~E1000_CTRL_VME;
6956 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6957 }
6958
e1739522 6959 igb_rlpml_set(adapter);
9d5c8243
AK		 6960}
6961
80d5c368
PM		 6962static int igb_vlan_rx_add_vid(struct net_device *netdev,
6963 __be16 proto, u16 vid)
9d5c8243
AK		 6964{
6965 struct igb_adapter *adapter = netdev_priv(netdev);
6966 struct e1000_hw *hw = &adapter->hw;
4ae196df 6967 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6968
51466239
AD		 6969 /* attempt to add filter to vlvf array */
6970 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6971
51466239
AD		 6972 /* add the filter since PF can receive vlans w/o entry in vlvf */
6973 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6974
6975 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6976
6977 return 0;
9d5c8243
AK		 6978}
6979
80d5c368
PM		 6980static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6981 __be16 proto, u16 vid)
9d5c8243
AK		 6982{
6983 struct igb_adapter *adapter = netdev_priv(netdev);
6984 struct e1000_hw *hw = &adapter->hw;
4ae196df 6985 int pf_id = adapter->vfs_allocated_count;
51466239 6986 s32 err;
9d5c8243 6987
51466239
AD		 6988 /* remove vlan from VLVF table array */
6989 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6990
51466239
AD		 6991 /* if vid was not present in VLVF just remove it from table */
6992 if (err)
4ae196df 6993 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6994
6995 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6996
6997 return 0;
9d5c8243
AK		 6998}
6999
7000static void igb_restore_vlan(struct igb_adapter *adapter)
7001{
b2cb09b1 7002 u16 vid;
9d5c8243 7003
5faf030c
AD		 7004 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7005
b2cb09b1 7006 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7007 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7008}
7009
14ad2513 7010int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7011{
090b1795 7012 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7013 struct e1000_mac_info *mac = &adapter->hw.mac;
7014
7015 mac->autoneg = 0;
7016
14ad2513 7017 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7018 * for the switch() below to work
7019 */
14ad2513
DD		 7020 if ((spd & 1) || (dplx & ~1))
7021 goto err_inval;
7022
f502ef7d
AA		 7023 /* Fiber NIC's only allow 1000 gbps Full duplex
7024 * and 100Mbps Full duplex for 100baseFx sfp
7025 */
7026 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7027 switch (spd + dplx) {
7028 case SPEED_10 + DUPLEX_HALF:
7029 case SPEED_10 + DUPLEX_FULL:
7030 case SPEED_100 + DUPLEX_HALF:
7031 goto err_inval;
7032 default:
7033 break;
7034 }
7035 }
cd2638a8 7036
14ad2513 7037 switch (spd + dplx) {
9d5c8243
AK		 7038 case SPEED_10 + DUPLEX_HALF:
7039 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7040 break;
7041 case SPEED_10 + DUPLEX_FULL:
7042 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7043 break;
7044 case SPEED_100 + DUPLEX_HALF:
7045 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7046 break;
7047 case SPEED_100 + DUPLEX_FULL:
7048 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7049 break;
7050 case SPEED_1000 + DUPLEX_FULL:
7051 mac->autoneg = 1;
7052 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7053 break;
7054 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7055 default:
14ad2513 7056 goto err_inval;
9d5c8243 7057 }
8376dad0
JB		 7058
7059 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7060 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7061
9d5c8243 7062 return 0;
14ad2513
DD		 7063
7064err_inval:
7065 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7066 return -EINVAL;
9d5c8243
AK		 7067}
7068
749ab2cd
YZ		 7069static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7070 bool runtime)
9d5c8243
AK		 7071{
7072 struct net_device *netdev = pci_get_drvdata(pdev);
7073 struct igb_adapter *adapter = netdev_priv(netdev);
7074 struct e1000_hw *hw = &adapter->hw;
2d064c06 7075 u32 ctrl, rctl, status;
749ab2cd 7076 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7077#ifdef CONFIG_PM
7078 int retval = 0;
7079#endif
7080
7081 netif_device_detach(netdev);
7082
a88f10ec 7083 if (netif_running(netdev))
749ab2cd 7084 __igb_close(netdev, true);
a88f10ec 7085
047e0030 7086 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7087
7088#ifdef CONFIG_PM
7089 retval = pci_save_state(pdev);
7090 if (retval)
7091 return retval;
7092#endif
7093
7094 status = rd32(E1000_STATUS);
7095 if (status & E1000_STATUS_LU)
7096 wufc &= ~E1000_WUFC_LNKC;
7097
7098 if (wufc) {
7099 igb_setup_rctl(adapter);
ff41f8dc 7100 igb_set_rx_mode(netdev);
9d5c8243
AK		 7101
7102 /* turn on all-multi mode if wake on multicast is enabled */
7103 if (wufc & E1000_WUFC_MC) {
7104 rctl = rd32(E1000_RCTL);
7105 rctl |= E1000_RCTL_MPE;
7106 wr32(E1000_RCTL, rctl);
7107 }
7108
7109 ctrl = rd32(E1000_CTRL);
7110 /* advertise wake from D3Cold */
7111 #define E1000_CTRL_ADVD3WUC 0x00100000
7112 /* phy power management enable */
7113 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7114 ctrl |= E1000_CTRL_ADVD3WUC;
7115 wr32(E1000_CTRL, ctrl);
7116
9d5c8243 7117 /* Allow time for pending master requests to run */
330a6d6a 7118 igb_disable_pcie_master(hw);
9d5c8243
AK		 7119
7120 wr32(E1000_WUC, E1000_WUC_PME_EN);
7121 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7122 } else {
7123 wr32(E1000_WUC, 0);
7124 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7125 }
7126
3fe7c4c9
RW		 7127 *enable_wake = wufc || adapter->en_mng_pt;
7128 if (!*enable_wake)
88a268c1
NN		 7129 igb_power_down_link(adapter);
7130 else
7131 igb_power_up_link(adapter);
9d5c8243
AK		 7132
7133 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7134 * would have already happened in close and is redundant.
7135 */
9d5c8243
AK		 7136 igb_release_hw_control(adapter);
7137
7138 pci_disable_device(pdev);
7139
9d5c8243
AK		 7140 return 0;
7141}
7142
7143#ifdef CONFIG_PM
d9dd966d 7144#ifdef CONFIG_PM_SLEEP
749ab2cd 7145static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7146{
7147 int retval;
7148 bool wake;
749ab2cd 7149 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7150
749ab2cd 7151 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7152 if (retval)
7153 return retval;
7154
7155 if (wake) {
7156 pci_prepare_to_sleep(pdev);
7157 } else {
7158 pci_wake_from_d3(pdev, false);
7159 pci_set_power_state(pdev, PCI_D3hot);
7160 }
7161
7162 return 0;
7163}
d9dd966d 7164#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7165
749ab2cd 7166static int igb_resume(struct device *dev)
9d5c8243 7167{
749ab2cd 7168 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7169 struct net_device *netdev = pci_get_drvdata(pdev);
7170 struct igb_adapter *adapter = netdev_priv(netdev);
7171 struct e1000_hw *hw = &adapter->hw;
7172 u32 err;
7173
7174 pci_set_power_state(pdev, PCI_D0);
7175 pci_restore_state(pdev);
b94f2d77 7176 pci_save_state(pdev);
42bfd33a 7177
aed5dec3 7178 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7179 if (err) {
7180 dev_err(&pdev->dev,
7181 "igb: Cannot enable PCI device from suspend\n");
7182 return err;
7183 }
7184 pci_set_master(pdev);
7185
7186 pci_enable_wake(pdev, PCI_D3hot, 0);
7187 pci_enable_wake(pdev, PCI_D3cold, 0);
7188
53c7d064 7189 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7190 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7191 return -ENOMEM;
9d5c8243
AK		 7192 }
7193
9d5c8243 7194 igb_reset(adapter);
a8564f03
AD		 7195
7196 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7197 * driver.
7198 */
a8564f03
AD		 7199 igb_get_hw_control(adapter);
7200
9d5c8243
AK		 7201 wr32(E1000_WUS, ~0);
7202
749ab2cd 7203 if (netdev->flags & IFF_UP) {
0c2cc02e 7204 rtnl_lock();
749ab2cd 7205 err = __igb_open(netdev, true);
0c2cc02e 7206 rtnl_unlock();
a88f10ec
AD		 7207 if (err)
7208 return err;
7209 }
9d5c8243
AK		 7210
7211 netif_device_attach(netdev);
749ab2cd
YZ		 7212 return 0;
7213}
7214
7215#ifdef CONFIG_PM_RUNTIME
7216static int igb_runtime_idle(struct device *dev)
7217{
7218 struct pci_dev *pdev = to_pci_dev(dev);
7219 struct net_device *netdev = pci_get_drvdata(pdev);
7220 struct igb_adapter *adapter = netdev_priv(netdev);
7221
7222 if (!igb_has_link(adapter))
7223 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7224
7225 return -EBUSY;
7226}
7227
7228static int igb_runtime_suspend(struct device *dev)
7229{
7230 struct pci_dev *pdev = to_pci_dev(dev);
7231 int retval;
7232 bool wake;
7233
7234 retval = __igb_shutdown(pdev, &wake, 1);
7235 if (retval)
7236 return retval;
7237
7238 if (wake) {
7239 pci_prepare_to_sleep(pdev);
7240 } else {
7241 pci_wake_from_d3(pdev, false);
7242 pci_set_power_state(pdev, PCI_D3hot);
7243 }
9d5c8243 7244
9d5c8243
AK		 7245 return 0;
7246}
749ab2cd
YZ		 7247
7248static int igb_runtime_resume(struct device *dev)
7249{
7250 return igb_resume(dev);
7251}
7252#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7253#endif
7254
7255static void igb_shutdown(struct pci_dev *pdev)
7256{
3fe7c4c9
RW		 7257 bool wake;
7258
749ab2cd 7259 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7260
7261 if (system_state == SYSTEM_POWER_OFF) {
7262 pci_wake_from_d3(pdev, wake);
7263 pci_set_power_state(pdev, PCI_D3hot);
7264 }
9d5c8243
AK		 7265}
7266
fa44f2f1
GR		 7267#ifdef CONFIG_PCI_IOV
7268static int igb_sriov_reinit(struct pci_dev *dev)
7269{
7270 struct net_device *netdev = pci_get_drvdata(dev);
7271 struct igb_adapter *adapter = netdev_priv(netdev);
7272 struct pci_dev *pdev = adapter->pdev;
7273
7274 rtnl_lock();
7275
7276 if (netif_running(netdev))
7277 igb_close(netdev);
7278
7279 igb_clear_interrupt_scheme(adapter);
7280
7281 igb_init_queue_configuration(adapter);
7282
7283 if (igb_init_interrupt_scheme(adapter, true)) {
7284 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7285 return -ENOMEM;
7286 }
7287
7288 if (netif_running(netdev))
7289 igb_open(netdev);
7290
7291 rtnl_unlock();
7292
7293 return 0;
7294}
7295
7296static int igb_pci_disable_sriov(struct pci_dev *dev)
7297{
7298 int err = igb_disable_sriov(dev);
7299
7300 if (!err)
7301 err = igb_sriov_reinit(dev);
7302
7303 return err;
7304}
7305
7306static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7307{
7308 int err = igb_enable_sriov(dev, num_vfs);
7309
7310 if (err)
7311 goto out;
7312
7313 err = igb_sriov_reinit(dev);
7314 if (!err)
7315 return num_vfs;
7316
7317out:
7318 return err;
7319}
7320
7321#endif
7322static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7323{
7324#ifdef CONFIG_PCI_IOV
7325 if (num_vfs == 0)
7326 return igb_pci_disable_sriov(dev);
7327 else
7328 return igb_pci_enable_sriov(dev, num_vfs);
7329#endif
7330 return 0;
7331}
7332
9d5c8243 7333#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7334/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7335 * without having to re-enable interrupts. It's not called while
7336 * the interrupt routine is executing.
7337 */
7338static void igb_netpoll(struct net_device *netdev)
7339{
7340 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7341 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7342 struct igb_q_vector *q_vector;
9d5c8243 7343 int i;
9d5c8243 7344
047e0030 7345 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7346 q_vector = adapter->q_vector[i];
7347 if (adapter->msix_entries)
7348 wr32(E1000_EIMC, q_vector->eims_value);
7349 else
7350 igb_irq_disable(adapter);
047e0030 7351 napi_schedule(&q_vector->napi);
eebbbdba 7352 }
9d5c8243
AK		 7353}
7354#endif /* CONFIG_NET_POLL_CONTROLLER */
7355
7356/**
b980ac18
JK		 7357 * igb_io_error_detected - called when PCI error is detected
7358 * @pdev: Pointer to PCI device
7359 * @state: The current pci connection state
9d5c8243 7360 *
b980ac18
JK		 7361 * This function is called after a PCI bus error affecting
7362 * this device has been detected.
7363 **/
9d5c8243
AK		 7364static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7365 pci_channel_state_t state)
7366{
7367 struct net_device *netdev = pci_get_drvdata(pdev);
7368 struct igb_adapter *adapter = netdev_priv(netdev);
7369
7370 netif_device_detach(netdev);
7371
59ed6eec
AD		 7372 if (state == pci_channel_io_perm_failure)
7373 return PCI_ERS_RESULT_DISCONNECT;
7374
9d5c8243
AK		 7375 if (netif_running(netdev))
7376 igb_down(adapter);
7377 pci_disable_device(pdev);
7378
7379 /* Request a slot slot reset. */
7380 return PCI_ERS_RESULT_NEED_RESET;
7381}
7382
7383/**
b980ac18
JK		 7384 * igb_io_slot_reset - called after the pci bus has been reset.
7385 * @pdev: Pointer to PCI device
9d5c8243 7386 *
b980ac18
JK		 7387 * Restart the card from scratch, as if from a cold-boot. Implementation
7388 * resembles the first-half of the igb_resume routine.
7389 **/
9d5c8243
AK		 7390static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7391{
7392 struct net_device *netdev = pci_get_drvdata(pdev);
7393 struct igb_adapter *adapter = netdev_priv(netdev);
7394 struct e1000_hw *hw = &adapter->hw;
40a914fa 7395 pci_ers_result_t result;
42bfd33a 7396 int err;
9d5c8243 7397
aed5dec3 7398 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7399 dev_err(&pdev->dev,
7400 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7401 result = PCI_ERS_RESULT_DISCONNECT;
7402 } else {
7403 pci_set_master(pdev);
7404 pci_restore_state(pdev);
b94f2d77 7405 pci_save_state(pdev);
9d5c8243 7406
40a914fa
AD		 7407 pci_enable_wake(pdev, PCI_D3hot, 0);
7408 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7409
40a914fa
AD		 7410 igb_reset(adapter);
7411 wr32(E1000_WUS, ~0);
7412 result = PCI_ERS_RESULT_RECOVERED;
7413 }
9d5c8243 7414
ea943d41
JK		 7415 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7416 if (err) {
b980ac18
JK		 7417 dev_err(&pdev->dev,
7418 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7419 err);
ea943d41
JK		 7420 /* non-fatal, continue */
7421 }
40a914fa
AD		 7422
7423 return result;
9d5c8243
AK		 7424}
7425
7426/**
b980ac18
JK		 7427 * igb_io_resume - called when traffic can start flowing again.
7428 * @pdev: Pointer to PCI device
9d5c8243 7429 *
b980ac18
JK		 7430 * This callback is called when the error recovery driver tells us that
7431 * its OK to resume normal operation. Implementation resembles the
7432 * second-half of the igb_resume routine.
9d5c8243
AK		 7433 */
7434static void igb_io_resume(struct pci_dev *pdev)
7435{
7436 struct net_device *netdev = pci_get_drvdata(pdev);
7437 struct igb_adapter *adapter = netdev_priv(netdev);
7438
9d5c8243
AK		 7439 if (netif_running(netdev)) {
7440 if (igb_up(adapter)) {
7441 dev_err(&pdev->dev, "igb_up failed after reset\n");
7442 return;
7443 }
7444 }
7445
7446 netif_device_attach(netdev);
7447
7448 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7449 * driver.
7450 */
9d5c8243 7451 igb_get_hw_control(adapter);
9d5c8243
AK		 7452}
7453
26ad9178 7454static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7455 u8 qsel)
26ad9178
AD		 7456{
7457 u32 rar_low, rar_high;
7458 struct e1000_hw *hw = &adapter->hw;
7459
7460 /* HW expects these in little endian so we reverse the byte order
7461 * from network order (big endian) to little endian
7462 */
7463 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7464 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7465 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7466
7467 /* Indicate to hardware the Address is Valid. */
7468 rar_high |= E1000_RAH_AV;
7469
7470 if (hw->mac.type == e1000_82575)
7471 rar_high |= E1000_RAH_POOL_1 * qsel;
7472 else
7473 rar_high |= E1000_RAH_POOL_1 << qsel;
7474
7475 wr32(E1000_RAL(index), rar_low);
7476 wrfl();
7477 wr32(E1000_RAH(index), rar_high);
7478 wrfl();
7479}
7480
4ae196df 7481static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7482 int vf, unsigned char *mac_addr)
4ae196df
AD		 7483{
7484 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7485 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7486 * towards the first, as a result a collision should not be possible
7487 */
ff41f8dc 7488 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7489
37680117 7490 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7491
26ad9178 7492 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7493
7494 return 0;
7495}
7496
8151d294
WM		 7497static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7498{
7499 struct igb_adapter *adapter = netdev_priv(netdev);
7500 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7501 return -EINVAL;
7502 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7503 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7504 dev_info(&adapter->pdev->dev,
7505 "Reload the VF driver to make this change effective.");
8151d294 7506 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7507 dev_warn(&adapter->pdev->dev,
7508 "The VF MAC address has been set, but the PF device is not up.\n");
7509 dev_warn(&adapter->pdev->dev,
7510 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7511 }
7512 return igb_set_vf_mac(adapter, vf, mac);
7513}
7514
17dc566c
LL		 7515static int igb_link_mbps(int internal_link_speed)
7516{
7517 switch (internal_link_speed) {
7518 case SPEED_100:
7519 return 100;
7520 case SPEED_1000:
7521 return 1000;
7522 default:
7523 return 0;
7524 }
7525}
7526
7527static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7528 int link_speed)
7529{
7530 int rf_dec, rf_int;
7531 u32 bcnrc_val;
7532
7533 if (tx_rate != 0) {
7534 /* Calculate the rate factor values to set */
7535 rf_int = link_speed / tx_rate;
7536 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7537 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7538 tx_rate;
17dc566c
LL		 7539
7540 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7541 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7542 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7543 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7544 } else {
7545 bcnrc_val = 0;
7546 }
7547
7548 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7549 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7550 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7551 */
7552 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7553 wr32(E1000_RTTBCNRC, bcnrc_val);
7554}
7555
7556static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7557{
7558 int actual_link_speed, i;
7559 bool reset_rate = false;
7560
7561 /* VF TX rate limit was not set or not supported */
7562 if ((adapter->vf_rate_link_speed == 0) ||
7563 (adapter->hw.mac.type != e1000_82576))
7564 return;
7565
7566 actual_link_speed = igb_link_mbps(adapter->link_speed);
7567 if (actual_link_speed != adapter->vf_rate_link_speed) {
7568 reset_rate = true;
7569 adapter->vf_rate_link_speed = 0;
7570 dev_info(&adapter->pdev->dev,
b980ac18 7571 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7572 }
7573
7574 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7575 if (reset_rate)
7576 adapter->vf_data[i].tx_rate = 0;
7577
7578 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7579 adapter->vf_data[i].tx_rate,
7580 actual_link_speed);
17dc566c
LL		 7581 }
7582}
7583
8151d294
WM		 7584static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7585{
17dc566c
LL		 7586 struct igb_adapter *adapter = netdev_priv(netdev);
7587 struct e1000_hw *hw = &adapter->hw;
7588 int actual_link_speed;
7589
7590 if (hw->mac.type != e1000_82576)
7591 return -EOPNOTSUPP;
7592
7593 actual_link_speed = igb_link_mbps(adapter->link_speed);
7594 if ((vf >= adapter->vfs_allocated_count) ||
7595 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7596 (tx_rate < 0) || (tx_rate > actual_link_speed))
7597 return -EINVAL;
7598
7599 adapter->vf_rate_link_speed = actual_link_speed;
7600 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7601 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7602
7603 return 0;
8151d294
WM		 7604}
7605
70ea4783
LL		 7606static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7607 bool setting)
7608{
7609 struct igb_adapter *adapter = netdev_priv(netdev);
7610 struct e1000_hw *hw = &adapter->hw;
7611 u32 reg_val, reg_offset;
7612
7613 if (!adapter->vfs_allocated_count)
7614 return -EOPNOTSUPP;
7615
7616 if (vf >= adapter->vfs_allocated_count)
7617 return -EINVAL;
7618
7619 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7620 reg_val = rd32(reg_offset);
7621 if (setting)
7622 reg_val |= ((1 << vf) |
7623 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7624 else
7625 reg_val &= ~((1 << vf) |
7626 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7627 wr32(reg_offset, reg_val);
7628
7629 adapter->vf_data[vf].spoofchk_enabled = setting;
7630 return E1000_SUCCESS;
7631}
7632
8151d294
WM		 7633static int igb_ndo_get_vf_config(struct net_device *netdev,
7634 int vf, struct ifla_vf_info *ivi)
7635{
7636 struct igb_adapter *adapter = netdev_priv(netdev);
7637 if (vf >= adapter->vfs_allocated_count)
7638 return -EINVAL;
7639 ivi->vf = vf;
7640 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7641 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7642 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7643 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7644 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7645 return 0;
7646}
7647
4ae196df
AD		 7648static void igb_vmm_control(struct igb_adapter *adapter)
7649{
7650 struct e1000_hw *hw = &adapter->hw;
10d8e907 7651 u32 reg;
4ae196df 7652
52a1dd4d
AD		 7653 switch (hw->mac.type) {
7654 case e1000_82575:
f96a8a0b
CW		 7655 case e1000_i210:
7656 case e1000_i211:
ceb5f13b 7657 case e1000_i354:
52a1dd4d
AD		 7658 default:
7659 /* replication is not supported for 82575 */
4ae196df 7660 return;
52a1dd4d
AD		 7661 case e1000_82576:
7662 /* notify HW that the MAC is adding vlan tags */
7663 reg = rd32(E1000_DTXCTL);
7664 reg |= E1000_DTXCTL_VLAN_ADDED;
7665 wr32(E1000_DTXCTL, reg);
7666 case e1000_82580:
7667 /* enable replication vlan tag stripping */
7668 reg = rd32(E1000_RPLOLR);
7669 reg |= E1000_RPLOLR_STRVLAN;
7670 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7671 case e1000_i350:
7672 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7673 break;
7674 }
10d8e907 7675
d4960307
AD		 7676 if (adapter->vfs_allocated_count) {
7677 igb_vmdq_set_loopback_pf(hw, true);
7678 igb_vmdq_set_replication_pf(hw, true);
13800469 7679 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7680 adapter->vfs_allocated_count);
d4960307
AD		 7681 } else {
7682 igb_vmdq_set_loopback_pf(hw, false);
7683 igb_vmdq_set_replication_pf(hw, false);
7684 }
4ae196df
AD		 7685}
7686
b6e0c419
CW		 7687static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7688{
7689 struct e1000_hw *hw = &adapter->hw;
7690 u32 dmac_thr;
7691 u16 hwm;
7692
7693 if (hw->mac.type > e1000_82580) {
7694 if (adapter->flags & IGB_FLAG_DMAC) {
7695 u32 reg;
7696
7697 /* force threshold to 0. */
7698 wr32(E1000_DMCTXTH, 0);
7699
b980ac18 7700 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7701 * than the Rx threshold. Set hwm to PBA - max frame
7702 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7703 */
e8c626e9
MV		 7704 hwm = 64 * pba - adapter->max_frame_size / 16;
7705 if (hwm < 64 * (pba - 6))
7706 hwm = 64 * (pba - 6);
7707 reg = rd32(E1000_FCRTC);
7708 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7709 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7710 & E1000_FCRTC_RTH_COAL_MASK);
7711 wr32(E1000_FCRTC, reg);
7712
b980ac18 7713 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7714 * frame size, capping it at PBA - 10KB.
7715 */
7716 dmac_thr = pba - adapter->max_frame_size / 512;
7717 if (dmac_thr < pba - 10)
7718 dmac_thr = pba - 10;
b6e0c419
CW		 7719 reg = rd32(E1000_DMACR);
7720 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7721 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7722 & E1000_DMACR_DMACTHR_MASK);
7723
7724 /* transition to L0x or L1 if available..*/
7725 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7726
7727 /* watchdog timer= +-1000 usec in 32usec intervals */
7728 reg |= (1000 >> 5);
0c02dd98
MV		 7729
7730 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7731 if (hw->mac.type != e1000_i354)
7732 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7733
b6e0c419
CW		 7734 wr32(E1000_DMACR, reg);
7735
b980ac18 7736 /* no lower threshold to disable
b6e0c419
CW		 7737 * coalescing(smart fifb)-UTRESH=0
7738 */
7739 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7740
7741 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7742
7743 wr32(E1000_DMCTLX, reg);
7744
b980ac18 7745 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7746 * DMA coal
7747 */
7748 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7749 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7750
b980ac18 7751 /* make low power state decision controlled
b6e0c419
CW		 7752 * by DMA coal
7753 */
7754 reg = rd32(E1000_PCIEMISC);
7755 reg &= ~E1000_PCIEMISC_LX_DECISION;
7756 wr32(E1000_PCIEMISC, reg);
7757 } /* endif adapter->dmac is not disabled */
7758 } else if (hw->mac.type == e1000_82580) {
7759 u32 reg = rd32(E1000_PCIEMISC);
7760 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7761 wr32(E1000_DMACR, 0);
7762 }
7763}
7764
b980ac18
JK		 7765/**
7766 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7767 * @hw: pointer to hardware structure
7768 * @byte_offset: byte offset to read
7769 * @dev_addr: device address
7770 * @data: value read
7771 *
7772 * Performs byte read operation over I2C interface at
7773 * a specified device address.
b980ac18 7774 **/
441fc6fd 7775s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7776 u8 dev_addr, u8 *data)
441fc6fd
CW		 7777{
7778 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7779 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7780 s32 status;
7781 u16 swfw_mask = 0;
7782
7783 if (!this_client)
7784 return E1000_ERR_I2C;
7785
7786 swfw_mask = E1000_SWFW_PHY0_SM;
7787
7788 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7789 != E1000_SUCCESS)
7790 return E1000_ERR_SWFW_SYNC;
7791
7792 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7793 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7794
7795 if (status < 0)
7796 return E1000_ERR_I2C;
7797 else {
7798 *data = status;
7799 return E1000_SUCCESS;
7800 }
7801}
7802
b980ac18
JK		 7803/**
7804 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7805 * @hw: pointer to hardware structure
7806 * @byte_offset: byte offset to write
7807 * @dev_addr: device address
7808 * @data: value to write
7809 *
7810 * Performs byte write operation over I2C interface at
7811 * a specified device address.
b980ac18 7812 **/
441fc6fd 7813s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7814 u8 dev_addr, u8 data)
441fc6fd
CW		 7815{
7816 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7817 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7818 s32 status;
7819 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7820
7821 if (!this_client)
7822 return E1000_ERR_I2C;
7823
7824 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7825 return E1000_ERR_SWFW_SYNC;
7826 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7827 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7828
7829 if (status)
7830 return E1000_ERR_I2C;
7831 else
7832 return E1000_SUCCESS;
7833
7834}
907b7835
LMV		 7835
7836int igb_reinit_queues(struct igb_adapter *adapter)
7837{
7838 struct net_device *netdev = adapter->netdev;
7839 struct pci_dev *pdev = adapter->pdev;
7840 int err = 0;
7841
7842 if (netif_running(netdev))
7843 igb_close(netdev);
7844
7845 igb_clear_interrupt_scheme(adapter);
7846
7847 if (igb_init_interrupt_scheme(adapter, true)) {
7848 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7849 return -ENOMEM;
7850 }
7851
7852 if (netif_running(netdev))
7853 err = igb_open(netdev);
7854
7855 return err;
7856}
9d5c8243 7857/* igb_main.c */
Linux kernel - Deliverables
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