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ip6_gre: Do not allow segmentation offloads GRE_CSUM is enabled with FOU/GUE
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
806ffb1d 53#include <linux/etherdevice.h>
421e02f0 54#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 55#include <linux/dca.h>
56#endif
441fc6fd 57#include <linux/i2c.h>
9d5c8243
AK		 58#include "igb.h"
59
67b1b903 60#define MAJ 5
6fb46902
TF		 61#define MIN 3
62#define BUILD 0
0d1fe82d 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 64__stringify(BUILD) "-k"
9d5c8243
AK		 65char igb_driver_name[] = "igb";
66char igb_driver_version[] = DRV_VERSION;
67static const char igb_driver_string[] =
68 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 69static const char igb_copyright[] =
74cfb2e1 70 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 71
9d5c8243
AK		 72static const struct e1000_info *igb_info_tbl[] = {
73 [board_82575] = &e1000_82575_info,
74};
75
cd1631ce 76static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
112 /* required last entry */
113 {0, }
114};
115
116MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
117
9d5c8243
AK		 118static int igb_setup_all_tx_resources(struct igb_adapter *);
119static int igb_setup_all_rx_resources(struct igb_adapter *);
120static void igb_free_all_tx_resources(struct igb_adapter *);
121static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 122static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 123static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 124static void igb_remove(struct pci_dev *pdev);
9d5c8243 125static int igb_sw_init(struct igb_adapter *);
46eafa59
SA		 126int igb_open(struct net_device *);
127int igb_close(struct net_device *);
53c7d064 128static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 129static void igb_configure_tx(struct igb_adapter *);
130static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 131static void igb_clean_all_tx_rings(struct igb_adapter *);
132static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 133static void igb_clean_tx_ring(struct igb_ring *);
134static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 135static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 136static void igb_update_phy_info(unsigned long);
137static void igb_watchdog(unsigned long);
138static void igb_watchdog_task(struct work_struct *);
cd392f5c 139static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 140static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 141 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 142static int igb_change_mtu(struct net_device *, int);
143static int igb_set_mac(struct net_device *, void *);
bf456abb 144static void igb_set_uta(struct igb_adapter *adapter, bool set);
9d5c8243
AK		 145static irqreturn_t igb_intr(int irq, void *);
146static irqreturn_t igb_intr_msi(int irq, void *);
147static irqreturn_t igb_msix_other(int irq, void *);
047e0030 148static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 149#ifdef CONFIG_IGB_DCA
047e0030 150static void igb_update_dca(struct igb_q_vector *);
fe4506b6 151static void igb_setup_dca(struct igb_adapter *);
421e02f0 152#endif /* CONFIG_IGB_DCA */
661086df 153static int igb_poll(struct napi_struct *, int);
7f0ba845 154static bool igb_clean_tx_irq(struct igb_q_vector *, int);
32b3e08f 155static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 156static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
157static void igb_tx_timeout(struct net_device *);
158static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 159static void igb_vlan_mode(struct net_device *netdev,
160 netdev_features_t features);
80d5c368
PM		 161static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
162static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 163static void igb_restore_vlan(struct igb_adapter *);
26ad9178 164static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 165static void igb_ping_all_vfs(struct igb_adapter *);
166static void igb_msg_task(struct igb_adapter *);
4ae196df 167static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 168static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 169static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 170static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
171static int igb_ndo_set_vf_vlan(struct net_device *netdev,
172 int vf, u16 vlan, u8 qos);
ed616689 173static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 174static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
175 bool setting);
8151d294
WM		 176static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
177 struct ifla_vf_info *ivi);
17dc566c 178static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 179
180#ifdef CONFIG_PCI_IOV
0224d663 181static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 182static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 183static int igb_disable_sriov(struct pci_dev *dev);
184static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd 191static int igb_resume(struct device *);
749ab2cd
YZ		 192static int igb_runtime_suspend(struct device *dev);
193static int igb_runtime_resume(struct device *dev);
194static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 195static const struct dev_pm_ops igb_pm_ops = {
196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
198 igb_runtime_idle)
199};
9d5c8243
AK		 200#endif
201static void igb_shutdown(struct pci_dev *);
fa44f2f1 202static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 203#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 204static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
205static struct notifier_block dca_notifier = {
206 .notifier_call = igb_notify_dca,
207 .next = NULL,
208 .priority = 0
209};
210#endif
9d5c8243
AK		 211#ifdef CONFIG_NET_POLL_CONTROLLER
212/* for netdump / net console */
213static void igb_netpoll(struct net_device *);
214#endif
37680117 215#ifdef CONFIG_PCI_IOV
6dd6d2b7 216static unsigned int max_vfs;
2a3abf6d 217module_param(max_vfs, uint, 0);
c75c4edf 218MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 219#endif /* CONFIG_PCI_IOV */
220
9d5c8243
AK		 221static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
222 pci_channel_state_t);
223static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
224static void igb_io_resume(struct pci_dev *);
225
3646f0e5 226static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 227 .error_detected = igb_io_error_detected,
228 .slot_reset = igb_io_slot_reset,
229 .resume = igb_io_resume,
230};
231
b6e0c419 232static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 233
234static struct pci_driver igb_driver = {
235 .name = igb_driver_name,
236 .id_table = igb_pci_tbl,
237 .probe = igb_probe,
9f9a12f8 238 .remove = igb_remove,
9d5c8243 239#ifdef CONFIG_PM
749ab2cd 240 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 241#endif
242 .shutdown = igb_shutdown,
fa44f2f1 243 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 244 .err_handler = &igb_err_handler
245};
246
247MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
248MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
249MODULE_LICENSE("GPL");
250MODULE_VERSION(DRV_VERSION);
251
b3f4d599 252#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
253static int debug = -1;
254module_param(debug, int, 0);
255MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
256
c97ec42a
TI		 257struct igb_reg_info {
258 u32 ofs;
259 char *name;
260};
261
262static const struct igb_reg_info igb_reg_info_tbl[] = {
263
264 /* General Registers */
265 {E1000_CTRL, "CTRL"},
266 {E1000_STATUS, "STATUS"},
267 {E1000_CTRL_EXT, "CTRL_EXT"},
268
269 /* Interrupt Registers */
270 {E1000_ICR, "ICR"},
271
272 /* RX Registers */
273 {E1000_RCTL, "RCTL"},
274 {E1000_RDLEN(0), "RDLEN"},
275 {E1000_RDH(0), "RDH"},
276 {E1000_RDT(0), "RDT"},
277 {E1000_RXDCTL(0), "RXDCTL"},
278 {E1000_RDBAL(0), "RDBAL"},
279 {E1000_RDBAH(0), "RDBAH"},
280
281 /* TX Registers */
282 {E1000_TCTL, "TCTL"},
283 {E1000_TDBAL(0), "TDBAL"},
284 {E1000_TDBAH(0), "TDBAH"},
285 {E1000_TDLEN(0), "TDLEN"},
286 {E1000_TDH(0), "TDH"},
287 {E1000_TDT(0), "TDT"},
288 {E1000_TXDCTL(0), "TXDCTL"},
289 {E1000_TDFH, "TDFH"},
290 {E1000_TDFT, "TDFT"},
291 {E1000_TDFHS, "TDFHS"},
292 {E1000_TDFPC, "TDFPC"},
293
294 /* List Terminator */
295 {}
296};
297
b980ac18 298/* igb_regdump - register printout routine */
c97ec42a
TI		 299static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
300{
301 int n = 0;
302 char rname[16];
303 u32 regs[8];
304
305 switch (reginfo->ofs) {
306 case E1000_RDLEN(0):
307 for (n = 0; n < 4; n++)
308 regs[n] = rd32(E1000_RDLEN(n));
309 break;
310 case E1000_RDH(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDH(n));
313 break;
314 case E1000_RDT(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDT(n));
317 break;
318 case E1000_RXDCTL(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RXDCTL(n));
321 break;
322 case E1000_RDBAL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RDBAL(n));
325 break;
326 case E1000_RDBAH(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAH(n));
329 break;
330 case E1000_TDBAL(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAL(n));
333 break;
334 case E1000_TDBAH(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_TDBAH(n));
337 break;
338 case E1000_TDLEN(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDLEN(n));
341 break;
342 case E1000_TDH(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDH(n));
345 break;
346 case E1000_TDT(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDT(n));
349 break;
350 case E1000_TXDCTL(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TXDCTL(n));
353 break;
354 default:
876d2d6f 355 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 356 return;
357 }
358
359 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 360 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
361 regs[2], regs[3]);
c97ec42a
TI		 362}
363
b980ac18 364/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 365static void igb_dump(struct igb_adapter *adapter)
366{
367 struct net_device *netdev = adapter->netdev;
368 struct e1000_hw *hw = &adapter->hw;
369 struct igb_reg_info *reginfo;
c97ec42a
TI		 370 struct igb_ring *tx_ring;
371 union e1000_adv_tx_desc *tx_desc;
372 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 373 struct igb_ring *rx_ring;
374 union e1000_adv_rx_desc *rx_desc;
375 u32 staterr;
6ad4edfc 376 u16 i, n;
c97ec42a
TI		 377
378 if (!netif_msg_hw(adapter))
379 return;
380
381 /* Print netdevice Info */
382 if (netdev) {
383 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 384 pr_info("Device Name state trans_start last_rx\n");
876d2d6f 385 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
4d0e9657 386 netdev->state, dev_trans_start(netdev), netdev->last_rx);
c97ec42a
TI		 387 }
388
389 /* Print Registers */
390 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 391 pr_info(" Register Name Value\n");
c97ec42a
TI		 392 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
393 reginfo->name; reginfo++) {
394 igb_regdump(hw, reginfo);
395 }
396
397 /* Print TX Ring Summary */
398 if (!netdev || !netif_running(netdev))
399 goto exit;
400
401 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 402 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 403 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 404 struct igb_tx_buffer *buffer_info;
c97ec42a 405 tx_ring = adapter->tx_ring[n];
06034649 406 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 407 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
408 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 409 (u64)dma_unmap_addr(buffer_info, dma),
410 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 411 buffer_info->next_to_watch,
412 (u64)buffer_info->time_stamp);
c97ec42a
TI		 413 }
414
415 /* Print TX Rings */
416 if (!netif_msg_tx_done(adapter))
417 goto rx_ring_summary;
418
419 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
420
421 /* Transmit Descriptor Formats
422 *
423 * Advanced Transmit Descriptor
424 * +--------------------------------------------------------------+
425 * 0 | Buffer Address [63:0] |
426 * +--------------------------------------------------------------+
427 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
428 * +--------------------------------------------------------------+
429 * 63 46 45 40 39 38 36 35 32 31 24 15 0
430 */
431
432 for (n = 0; n < adapter->num_tx_queues; n++) {
433 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 434 pr_info("------------------------------------\n");
435 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
436 pr_info("------------------------------------\n");
c75c4edf 437 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 440 const char *next_desc;
06034649 441 struct igb_tx_buffer *buffer_info;
60136906 442 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 443 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 444 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
c75c4edf
CW		 455 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
456 i, le64_to_cpu(u0->a),
c97ec42a 457 le64_to_cpu(u0->b),
c9f14bf3
AD		 458 (u64)dma_unmap_addr(buffer_info, dma),
459 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 460 buffer_info->next_to_watch,
461 (u64)buffer_info->time_stamp,
876d2d6f 462 buffer_info->skb, next_desc);
c97ec42a 463
b669588a 464 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 465 print_hex_dump(KERN_INFO, "",
466 DUMP_PREFIX_ADDRESS,
b669588a 467 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 468 dma_unmap_len(buffer_info, len),
469 true);
c97ec42a
TI		 470 }
471 }
472
473 /* Print RX Rings Summary */
474rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 476 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
c75c4edf
CW		 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
516 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 517
518 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 519 const char *next_desc;
06034649
AD		 520 struct igb_rx_buffer *buffer_info;
521 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 522 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 523 u0 = (struct my_u0 *)rx_desc;
524 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 525
526 if (i == rx_ring->next_to_use)
527 next_desc = " NTU";
528 else if (i == rx_ring->next_to_clean)
529 next_desc = " NTC";
530 else
531 next_desc = "";
532
c97ec42a
TI		 533 if (staterr & E1000_RXD_STAT_DD) {
534 /* Descriptor Done */
1a1c225b
AD		 535 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
536 "RWB", i,
c97ec42a
TI		 537 le64_to_cpu(u0->a),
538 le64_to_cpu(u0->b),
1a1c225b 539 next_desc);
c97ec42a 540 } else {
1a1c225b
AD		 541 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
542 "R ", i,
c97ec42a
TI		 543 le64_to_cpu(u0->a),
544 le64_to_cpu(u0->b),
545 (u64)buffer_info->dma,
1a1c225b 546 next_desc);
c97ec42a 547
b669588a 548 if (netif_msg_pktdata(adapter) &&
1a1c225b 549 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 550 print_hex_dump(KERN_INFO, "",
551 DUMP_PREFIX_ADDRESS,
552 16, 1,
b669588a
ET		 553 page_address(buffer_info->page) +
554 buffer_info->page_offset,
de78d1f9 555 IGB_RX_BUFSZ, true);
c97ec42a
TI		 556 }
557 }
c97ec42a
TI		 558 }
559 }
560
561exit:
562 return;
563}
564
b980ac18
JK		 565/**
566 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 567 * @hw: pointer to hardware structure
568 * @i2cctl: Current value of I2CCTL register
569 *
570 * Returns the I2C data bit value
b980ac18 571 **/
441fc6fd
CW		 572static int igb_get_i2c_data(void *data)
573{
574 struct igb_adapter *adapter = (struct igb_adapter *)data;
575 struct e1000_hw *hw = &adapter->hw;
576 s32 i2cctl = rd32(E1000_I2CPARAMS);
577
da1f1dfe 578 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 579}
580
b980ac18
JK		 581/**
582 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 583 * @data: pointer to hardware structure
584 * @state: I2C data value (0 or 1) to set
585 *
586 * Sets the I2C data bit
b980ac18 587 **/
441fc6fd
CW		 588static void igb_set_i2c_data(void *data, int state)
589{
590 struct igb_adapter *adapter = (struct igb_adapter *)data;
591 struct e1000_hw *hw = &adapter->hw;
592 s32 i2cctl = rd32(E1000_I2CPARAMS);
593
594 if (state)
595 i2cctl |= E1000_I2C_DATA_OUT;
596 else
597 i2cctl &= ~E1000_I2C_DATA_OUT;
598
599 i2cctl &= ~E1000_I2C_DATA_OE_N;
600 i2cctl |= E1000_I2C_CLK_OE_N;
601 wr32(E1000_I2CPARAMS, i2cctl);
602 wrfl();
603
604}
605
b980ac18
JK		 606/**
607 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 608 * @data: pointer to hardware structure
609 * @state: state to set clock
610 *
611 * Sets the I2C clock line to state
b980ac18 612 **/
441fc6fd
CW		 613static void igb_set_i2c_clk(void *data, int state)
614{
615 struct igb_adapter *adapter = (struct igb_adapter *)data;
616 struct e1000_hw *hw = &adapter->hw;
617 s32 i2cctl = rd32(E1000_I2CPARAMS);
618
619 if (state) {
620 i2cctl |= E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 } else {
623 i2cctl &= ~E1000_I2C_CLK_OUT;
624 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 }
626 wr32(E1000_I2CPARAMS, i2cctl);
627 wrfl();
628}
629
b980ac18
JK		 630/**
631 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 632 * @data: pointer to hardware structure
633 *
634 * Gets the I2C clock state
b980ac18 635 **/
441fc6fd
CW		 636static int igb_get_i2c_clk(void *data)
637{
638 struct igb_adapter *adapter = (struct igb_adapter *)data;
639 struct e1000_hw *hw = &adapter->hw;
640 s32 i2cctl = rd32(E1000_I2CPARAMS);
641
da1f1dfe 642 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 643}
644
645static const struct i2c_algo_bit_data igb_i2c_algo = {
646 .setsda = igb_set_i2c_data,
647 .setscl = igb_set_i2c_clk,
648 .getsda = igb_get_i2c_data,
649 .getscl = igb_get_i2c_clk,
650 .udelay = 5,
651 .timeout = 20,
652};
653
9d5c8243 654/**
b980ac18
JK		 655 * igb_get_hw_dev - return device
656 * @hw: pointer to hardware structure
657 *
658 * used by hardware layer to print debugging information
9d5c8243 659 **/
c041076a 660struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 661{
662 struct igb_adapter *adapter = hw->back;
c041076a 663 return adapter->netdev;
9d5c8243 664}
38c845c7 665
9d5c8243 666/**
b980ac18 667 * igb_init_module - Driver Registration Routine
9d5c8243 668 *
b980ac18
JK		 669 * igb_init_module is the first routine called when the driver is
670 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 671 **/
672static int __init igb_init_module(void)
673{
674 int ret;
9005df38 675
876d2d6f 676 pr_info("%s - version %s\n",
9d5c8243 677 igb_driver_string, igb_driver_version);
876d2d6f 678 pr_info("%s\n", igb_copyright);
9d5c8243 679
421e02f0 680#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 681 dca_register_notify(&dca_notifier);
682#endif
bbd98fe4 683 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 684 return ret;
685}
686
687module_init(igb_init_module);
688
689/**
b980ac18 690 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 691 *
b980ac18
JK		 692 * igb_exit_module is called just before the driver is removed
693 * from memory.
9d5c8243
AK		 694 **/
695static void __exit igb_exit_module(void)
696{
421e02f0 697#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 698 dca_unregister_notify(&dca_notifier);
699#endif
9d5c8243
AK		 700 pci_unregister_driver(&igb_driver);
701}
702
703module_exit(igb_exit_module);
704
26bc19ec
AD		 705#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706/**
b980ac18
JK		 707 * igb_cache_ring_register - Descriptor ring to register mapping
708 * @adapter: board private structure to initialize
26bc19ec 709 *
b980ac18
JK		 710 * Once we know the feature-set enabled for the device, we'll cache
711 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 712 **/
713static void igb_cache_ring_register(struct igb_adapter *adapter)
714{
ee1b9f06 715 int i = 0, j = 0;
047e0030 716 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 717
718 switch (adapter->hw.mac.type) {
719 case e1000_82576:
720 /* The queues are allocated for virtualization such that VF 0
721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
722 * In order to avoid collision we start at the first free queue
723 * and continue consuming queues in the same sequence
724 */
ee1b9f06 725 if (adapter->vfs_allocated_count) {
a99955fc 726 for (; i < adapter->rss_queues; i++)
3025a446 727 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 728 Q_IDX_82576(i);
ee1b9f06 729 }
b26141d4 730 /* Fall through */
26bc19ec 731 case e1000_82575:
55cac248 732 case e1000_82580:
d2ba2ed8 733 case e1000_i350:
ceb5f13b 734 case e1000_i354:
f96a8a0b
CW		 735 case e1000_i210:
736 case e1000_i211:
b26141d4 737 /* Fall through */
26bc19ec 738 default:
ee1b9f06 739 for (; i < adapter->num_rx_queues; i++)
3025a446 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 741 for (; j < adapter->num_tx_queues; j++)
3025a446 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 743 break;
744 }
745}
746
22a8b291
FT		 747u32 igb_rd32(struct e1000_hw *hw, u32 reg)
748{
749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
751 u32 value = 0;
752
753 if (E1000_REMOVED(hw_addr))
754 return ~value;
755
756 value = readl(&hw_addr[reg]);
757
758 /* reads should not return all F's */
759 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
760 struct net_device *netdev = igb->netdev;
761 hw->hw_addr = NULL;
762 netif_device_detach(netdev);
763 netdev_err(netdev, "PCIe link lost, device now detached\n");
764 }
765
766 return value;
767}
768
4be000c8
AD		 769/**
770 * igb_write_ivar - configure ivar for given MSI-X vector
771 * @hw: pointer to the HW structure
772 * @msix_vector: vector number we are allocating to a given ring
773 * @index: row index of IVAR register to write within IVAR table
774 * @offset: column offset of in IVAR, should be multiple of 8
775 *
776 * This function is intended to handle the writing of the IVAR register
777 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
778 * each containing an cause allocation for an Rx and Tx ring, and a
779 * variable number of rows depending on the number of queues supported.
780 **/
781static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
782 int index, int offset)
783{
784 u32 ivar = array_rd32(E1000_IVAR0, index);
785
786 /* clear any bits that are currently set */
787 ivar &= ~((u32)0xFF << offset);
788
789 /* write vector and valid bit */
790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
791
792 array_wr32(E1000_IVAR0, index, ivar);
793}
794
9d5c8243 795#define IGB_N0_QUEUE -1
047e0030 796static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 797{
047e0030 798 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 799 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 800 int rx_queue = IGB_N0_QUEUE;
801 int tx_queue = IGB_N0_QUEUE;
4be000c8 802 u32 msixbm = 0;
047e0030 803
0ba82994
AD		 804 if (q_vector->rx.ring)
805 rx_queue = q_vector->rx.ring->reg_idx;
806 if (q_vector->tx.ring)
807 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 808
809 switch (hw->mac.type) {
810 case e1000_82575:
9d5c8243 811 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one
813 * or more queues to a vector, we write the appropriate bits
814 * into the MSIXBM register for that vector.
815 */
047e0030 816 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 818 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 821 msixbm |= E1000_EIMS_OTHER;
9d5c8243 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 823 q_vector->eims_value = msixbm;
2d064c06
AD		 824 break;
825 case e1000_82576:
b980ac18 826 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 827 * with 8 rows. The ordering is column-major so we use the
828 * lower 3 bits as the row index, and the 4th bit as the
829 * column offset.
830 */
831 if (rx_queue > IGB_N0_QUEUE)
832 igb_write_ivar(hw, msix_vector,
833 rx_queue & 0x7,
834 (rx_queue & 0x8) << 1);
835 if (tx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 tx_queue & 0x7,
838 ((tx_queue & 0x8) << 1) + 8);
a51d8c21 839 q_vector->eims_value = BIT(msix_vector);
2d064c06 840 break;
55cac248 841 case e1000_82580:
d2ba2ed8 842 case e1000_i350:
ceb5f13b 843 case e1000_i354:
f96a8a0b
CW		 844 case e1000_i210:
845 case e1000_i211:
b980ac18 846 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 847 * however instead of ordering column-major we have things
848 * ordered row-major. So we traverse the table by using
849 * bit 0 as the column offset, and the remaining bits as the
850 * row index.
851 */
852 if (rx_queue > IGB_N0_QUEUE)
853 igb_write_ivar(hw, msix_vector,
854 rx_queue >> 1,
855 (rx_queue & 0x1) << 4);
856 if (tx_queue > IGB_N0_QUEUE)
857 igb_write_ivar(hw, msix_vector,
858 tx_queue >> 1,
859 ((tx_queue & 0x1) << 4) + 8);
a51d8c21 860 q_vector->eims_value = BIT(msix_vector);
55cac248 861 break;
2d064c06
AD		 862 default:
863 BUG();
864 break;
865 }
26b39276
AD		 866
867 /* add q_vector eims value to global eims_enable_mask */
868 adapter->eims_enable_mask |= q_vector->eims_value;
869
870 /* configure q_vector to set itr on first interrupt */
871 q_vector->set_itr = 1;
9d5c8243
AK		 872}
873
874/**
b980ac18
JK		 875 * igb_configure_msix - Configure MSI-X hardware
876 * @adapter: board private structure to initialize
9d5c8243 877 *
b980ac18
JK		 878 * igb_configure_msix sets up the hardware to properly
879 * generate MSI-X interrupts.
9d5c8243
AK		 880 **/
881static void igb_configure_msix(struct igb_adapter *adapter)
882{
883 u32 tmp;
884 int i, vector = 0;
885 struct e1000_hw *hw = &adapter->hw;
886
887 adapter->eims_enable_mask = 0;
9d5c8243
AK		 888
889 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 890 switch (hw->mac.type) {
891 case e1000_82575:
9d5c8243
AK		 892 tmp = rd32(E1000_CTRL_EXT);
893 /* enable MSI-X PBA support*/
894 tmp |= E1000_CTRL_EXT_PBA_CLR;
895
896 /* Auto-Mask interrupts upon ICR read. */
897 tmp |= E1000_CTRL_EXT_EIAME;
898 tmp |= E1000_CTRL_EXT_IRCA;
899
900 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 901
902 /* enable msix_other interrupt */
b980ac18 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 904 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 905
2d064c06
AD		 906 break;
907
908 case e1000_82576:
55cac248 909 case e1000_82580:
d2ba2ed8 910 case e1000_i350:
ceb5f13b 911 case e1000_i354:
f96a8a0b
CW		 912 case e1000_i210:
913 case e1000_i211:
047e0030 914 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 915 * won't stick. And it will take days to debug.
916 */
047e0030 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 918 E1000_GPIE_PBA | E1000_GPIE_EIAME |
919 E1000_GPIE_NSICR);
047e0030
AD		 920
921 /* enable msix_other interrupt */
a51d8c21 922 adapter->eims_other = BIT(vector);
2d064c06 923 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 924
047e0030 925 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 926 break;
927 default:
928 /* do nothing, since nothing else supports MSI-X */
929 break;
930 } /* switch (hw->mac.type) */
047e0030
AD		 931
932 adapter->eims_enable_mask |= adapter->eims_other;
933
26b39276
AD		 934 for (i = 0; i < adapter->num_q_vectors; i++)
935 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 936
9d5c8243
AK		 937 wrfl();
938}
939
940/**
b980ac18
JK		 941 * igb_request_msix - Initialize MSI-X interrupts
942 * @adapter: board private structure to initialize
9d5c8243 943 *
b980ac18
JK		 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
945 * kernel.
9d5c8243
AK		 946 **/
947static int igb_request_msix(struct igb_adapter *adapter)
948{
949 struct net_device *netdev = adapter->netdev;
52285b76 950 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 951
047e0030 952 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 953 igb_msix_other, 0, netdev->name, adapter);
047e0030 954 if (err)
52285b76 955 goto err_out;
047e0030
AD		 956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
52285b76
SA		 960 vector++;
961
7b06a690 962 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 963
0ba82994 964 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
047e0030 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
047e0030 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 972 q_vector->rx.ring->queue_index);
9d5c8243 973 else
047e0030
AD		 974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
9d5c8243 976 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
9d5c8243 979 if (err)
52285b76 980 goto err_free;
9d5c8243
AK		 981 }
982
9d5c8243
AK		 983 igb_configure_msix(adapter);
984 return 0;
52285b76
SA		 985
986err_free:
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995err_out:
9d5c8243
AK		 996 return err;
997}
998
5536d210 999/**
b980ac18
JK		 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
5536d210 1003 *
02ef6e1d 1004 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
02ef6e1d
CW		 1010 adapter->q_vector[v_idx] = NULL;
1011
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
17a402a0
CW		 1015 if (q_vector)
1016 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1017}
1018
1019/**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
cb06d102
CP		 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
5536d210
AD		 1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
2439fc4d 1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1042
5536d210
AD		 1043 netif_napi_del(&q_vector->napi);
1044
02ef6e1d
CW		 1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
cd14ef54 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1052 pci_disable_msix(adapter->pdev);
cd14ef54 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1054 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1058}
1059
047e0030 1060/**
b980ac18
JK		 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
047e0030 1063 *
b980ac18
JK		 1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
047e0030
AD		 1067 **/
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
5536d210
AD		 1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
047e0030 1074 adapter->num_q_vectors = 0;
5536d210 1075
02ef6e1d
CW		 1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
5536d210 1078 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1079 }
047e0030
AD		 1080}
1081
1082/**
b980ac18
JK		 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
047e0030 1085 *
b980ac18
JK		 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
047e0030
AD		 1088 */
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
047e0030
AD		 1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
9d5c8243
AK		 1094
1095/**
b980ac18
JK		 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
9d5c8243 1099 *
b980ac18
JK		 1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
9d5c8243 1102 **/
53c7d064 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1104{
1105 int err;
1106 int numvecs, i;
1107
53c7d064
SA		 1108 if (!msix)
1109 goto msi_only;
cd14ef54 1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1111
83b7180d 1112 /* Number of supported queues. */
a99955fc 1113 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1118
b980ac18 1119 /* start with one vector for every Rx queue */
047e0030
AD		 1120 numvecs = adapter->num_rx_queues;
1121
b980ac18 1122 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
047e0030
AD		 1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
9d5c8243
AK		 1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
479d02df
AG		 1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
0c2cc02e 1139 return;
9d5c8243
AK		 1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144msi_only:
b709323d 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1146#ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1157 wrfl();
2a3abf6d
AD		 1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
4fc82adf 1162 adapter->vfs_allocated_count = 0;
a99955fc 1163 adapter->rss_queues = 1;
4fc82adf 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1165 adapter->num_rx_queues = 1;
661086df 1166 adapter->num_tx_queues = 1;
047e0030 1167 adapter->num_q_vectors = 1;
9d5c8243 1168 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1169 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1170}
1171
5536d210
AD		 1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
047e0030 1179/**
b980ac18
JK		 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
047e0030 1188 *
b980ac18 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1190 **/
5536d210
AD		 1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
047e0030
AD		 1195{
1196 struct igb_q_vector *q_vector;
5536d210
AD		 1197 struct igb_ring *ring;
1198 int ring_count, size;
047e0030 1199
5536d210
AD		 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
02ef6e1d 1209 q_vector = adapter->q_vector[v_idx];
72ddef05 1210 if (!q_vector) {
02ef6e1d 1211 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1212 } else if (size > ksize(q_vector)) {
1213 kfree_rcu(q_vector, rcu);
1214 q_vector = kzalloc(size, GFP_KERNEL);
1215 } else {
c0a06ee1 1216 memset(q_vector, 0, size);
72ddef05 1217 }
5536d210
AD		 1218 if (!q_vector)
1219 return -ENOMEM;
1220
1221 /* initialize NAPI */
1222 netif_napi_add(adapter->netdev, &q_vector->napi,
1223 igb_poll, 64);
1224
1225 /* tie q_vector and adapter together */
1226 adapter->q_vector[v_idx] = q_vector;
1227 q_vector->adapter = adapter;
1228
1229 /* initialize work limits */
1230 q_vector->tx.work_limit = adapter->tx_work_limit;
1231
1232 /* initialize ITR configuration */
7b06a690 1233 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1234 q_vector->itr_val = IGB_START_ITR;
1235
1236 /* initialize pointer to rings */
1237 ring = q_vector->ring;
1238
4e227667
AD		 1239 /* intialize ITR */
1240 if (rxr_count) {
1241 /* rx or rx/tx vector */
1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 q_vector->itr_val = adapter->rx_itr_setting;
1244 } else {
1245 /* tx only vector */
1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 q_vector->itr_val = adapter->tx_itr_setting;
1248 }
1249
5536d210
AD		 1250 if (txr_count) {
1251 /* assign generic ring traits */
1252 ring->dev = &adapter->pdev->dev;
1253 ring->netdev = adapter->netdev;
1254
1255 /* configure backlink on ring */
1256 ring->q_vector = q_vector;
1257
1258 /* update q_vector Tx values */
1259 igb_add_ring(ring, &q_vector->tx);
1260
1261 /* For 82575, context index must be unique per ring. */
1262 if (adapter->hw.mac.type == e1000_82575)
1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1264
1265 /* apply Tx specific ring traits */
1266 ring->count = adapter->tx_ring_count;
1267 ring->queue_index = txr_idx;
1268
827da44c
JS		 1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1271
5536d210
AD		 1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1274
1275 /* push pointer to next ring */
1276 ring++;
047e0030 1277 }
81c2fc22 1278
5536d210
AD		 1279 if (rxr_count) {
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
047e0030 1283
5536d210
AD		 1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
047e0030 1286
5536d210
AD		 1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
047e0030 1289
5536d210
AD		 1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1293
e52c0f96 1294 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1295 * have the tag byte-swapped.
b980ac18 1296 */
5536d210
AD		 1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1299
5536d210
AD		 1300 /* apply Rx specific ring traits */
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1303
827da44c
JS		 1304 u64_stats_init(&ring->rx_syncp);
1305
5536d210
AD		 1306 /* assign ring to adapter */
1307 adapter->rx_ring[rxr_idx] = ring;
1308 }
1309
1310 return 0;
047e0030
AD		 1311}
1312
5536d210 1313
047e0030 1314/**
b980ac18
JK		 1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316 * @adapter: board private structure to initialize
047e0030 1317 *
b980ac18
JK		 1318 * We allocate one q_vector per queue interrupt. If allocation fails we
1319 * return -ENOMEM.
047e0030 1320 **/
5536d210 1321static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1322{
5536d210
AD		 1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327 int err;
047e0030 1328
5536d210
AD		 1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332 0, 0, 1, rxr_idx);
047e0030 1333
5536d210
AD		 1334 if (err)
1335 goto err_out;
1336
1337 /* update counts and index */
1338 rxr_remaining--;
1339 rxr_idx++;
047e0030 1340 }
047e0030 1341 }
5536d210
AD		 1342
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1346
5536d210
AD		 1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1349
1350 if (err)
1351 goto err_out;
1352
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1356 rxr_idx++;
1357 txr_idx++;
1358 }
1359
047e0030 1360 return 0;
5536d210
AD		 1361
1362err_out:
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1366
1367 while (v_idx--)
1368 igb_free_q_vector(adapter, v_idx);
1369
1370 return -ENOMEM;
047e0030
AD		 1371}
1372
1373/**
b980ac18
JK		 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
047e0030 1377 *
b980ac18 1378 * This function initializes the interrupts and allocates all of the queues.
047e0030 1379 **/
53c7d064 1380static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1381{
1382 struct pci_dev *pdev = adapter->pdev;
1383 int err;
1384
53c7d064 1385 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1386
1387 err = igb_alloc_q_vectors(adapter);
1388 if (err) {
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1391 }
1392
5536d210 1393 igb_cache_ring_register(adapter);
047e0030
AD		 1394
1395 return 0;
5536d210 1396
047e0030
AD		 1397err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1399 return err;
1400}
1401
9d5c8243 1402/**
b980ac18
JK		 1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
9d5c8243 1405 *
b980ac18
JK		 1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
9d5c8243
AK		 1408 **/
1409static int igb_request_irq(struct igb_adapter *adapter)
1410{
1411 struct net_device *netdev = adapter->netdev;
047e0030 1412 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1413 int err = 0;
1414
cd14ef54 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1416 err = igb_request_msix(adapter);
844290e5 1417 if (!err)
9d5c8243 1418 goto request_done;
9d5c8243 1419 /* fall back to MSI */
5536d210
AD		 1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
53c7d064 1422
047e0030 1423 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1424 err = igb_init_interrupt_scheme(adapter, false);
1425 if (err)
047e0030 1426 goto request_done;
53c7d064 1427
047e0030
AD		 1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
53c7d064 1430 igb_configure(adapter);
9d5c8243 1431 }
844290e5 1432
c74d588e
AD		 1433 igb_assign_vector(adapter->q_vector[0], 0);
1434
7dfc16fa 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1437 netdev->name, adapter);
9d5c8243
AK		 1438 if (!err)
1439 goto request_done;
047e0030 1440
9d5c8243
AK		 1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
7dfc16fa 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1444 }
1445
c74d588e 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1447 netdev->name, adapter);
9d5c8243 1448
6cb5e577 1449 if (err)
c74d588e 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1451 err);
9d5c8243
AK		 1452
1453request_done:
1454 return err;
1455}
1456
1457static void igb_free_irq(struct igb_adapter *adapter)
1458{
cd14ef54 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1460 int vector = 0, i;
1461
047e0030 1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1463
0d1ae7f4 1464 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1465 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1466 adapter->q_vector[i]);
047e0030
AD		 1467 } else {
1468 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1469 }
9d5c8243
AK		 1470}
1471
1472/**
b980ac18
JK		 1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
9d5c8243
AK		 1475 **/
1476static void igb_irq_disable(struct igb_adapter *adapter)
1477{
1478 struct e1000_hw *hw = &adapter->hw;
1479
b980ac18 1480 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1483 */
cd14ef54 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1485 u32 regval = rd32(E1000_EIAM);
9005df38 1486
2dfd1212
AD		 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1491 }
844290e5
PW		 1492
1493 wr32(E1000_IAM, 0);
9d5c8243
AK		 1494 wr32(E1000_IMC, ~0);
1495 wrfl();
cd14ef54 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1497 int i;
9005df38 1498
81a61859
ET		 1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1501 } else {
1502 synchronize_irq(adapter->pdev->irq);
1503 }
9d5c8243
AK		 1504}
1505
1506/**
b980ac18
JK		 1507 * igb_irq_enable - Enable default interrupt generation settings
1508 * @adapter: board private structure
9d5c8243
AK		 1509 **/
1510static void igb_irq_enable(struct igb_adapter *adapter)
1511{
1512 struct e1000_hw *hw = &adapter->hw;
1513
cd14ef54 1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1516 u32 regval = rd32(E1000_EIAC);
9005df38 1517
2dfd1212
AD		 1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1522 if (adapter->vfs_allocated_count) {
4ae196df 1523 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1524 ims |= E1000_IMS_VMMB;
1525 }
1526 wr32(E1000_IMS, ims);
844290e5 1527 } else {
55cac248
AD		 1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529 E1000_IMS_DRSTA);
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531 E1000_IMS_DRSTA);
844290e5 1532 }
9d5c8243
AK		 1533}
1534
1535static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536{
51466239 1537 struct e1000_hw *hw = &adapter->hw;
8b77c6b2 1538 u16 pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 1539 u16 vid = adapter->hw.mng_cookie.vlan_id;
1540 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1541
1542 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1543 /* add VID to filter table */
8b77c6b2 1544 igb_vfta_set(hw, vid, pf_id, true, true);
51466239
AD		 1545 adapter->mng_vlan_id = vid;
1546 } else {
1547 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1548 }
1549
1550 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1551 (vid != old_vid) &&
b2cb09b1 1552 !test_bit(old_vid, adapter->active_vlans)) {
51466239 1553 /* remove VID from filter table */
8b77c6b2 1554 igb_vfta_set(hw, vid, pf_id, false, true);
9d5c8243
AK		 1555 }
1556}
1557
1558/**
b980ac18
JK		 1559 * igb_release_hw_control - release control of the h/w to f/w
1560 * @adapter: address of board private structure
9d5c8243 1561 *
b980ac18
JK		 1562 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1563 * For ASF and Pass Through versions of f/w this means that the
1564 * driver is no longer loaded.
9d5c8243
AK		 1565 **/
1566static void igb_release_hw_control(struct igb_adapter *adapter)
1567{
1568 struct e1000_hw *hw = &adapter->hw;
1569 u32 ctrl_ext;
1570
1571 /* Let firmware take over control of h/w */
1572 ctrl_ext = rd32(E1000_CTRL_EXT);
1573 wr32(E1000_CTRL_EXT,
1574 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1575}
1576
9d5c8243 1577/**
b980ac18
JK		 1578 * igb_get_hw_control - get control of the h/w from f/w
1579 * @adapter: address of board private structure
9d5c8243 1580 *
b980ac18
JK		 1581 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1582 * For ASF and Pass Through versions of f/w this means that
1583 * the driver is loaded.
9d5c8243
AK		 1584 **/
1585static void igb_get_hw_control(struct igb_adapter *adapter)
1586{
1587 struct e1000_hw *hw = &adapter->hw;
1588 u32 ctrl_ext;
1589
1590 /* Let firmware know the driver has taken over */
1591 ctrl_ext = rd32(E1000_CTRL_EXT);
1592 wr32(E1000_CTRL_EXT,
1593 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1594}
1595
9d5c8243 1596/**
b980ac18
JK		 1597 * igb_configure - configure the hardware for RX and TX
1598 * @adapter: private board structure
9d5c8243
AK		 1599 **/
1600static void igb_configure(struct igb_adapter *adapter)
1601{
1602 struct net_device *netdev = adapter->netdev;
1603 int i;
1604
1605 igb_get_hw_control(adapter);
ff41f8dc 1606 igb_set_rx_mode(netdev);
9d5c8243
AK		 1607
1608 igb_restore_vlan(adapter);
9d5c8243 1609
85b430b4 1610 igb_setup_tctl(adapter);
06cf2666 1611 igb_setup_mrqc(adapter);
9d5c8243 1612 igb_setup_rctl(adapter);
85b430b4
AD		 1613
1614 igb_configure_tx(adapter);
9d5c8243 1615 igb_configure_rx(adapter);
662d7205
AD		 1616
1617 igb_rx_fifo_flush_82575(&adapter->hw);
1618
c493ea45 1619 /* call igb_desc_unused which always leaves
9d5c8243 1620 * at least 1 descriptor unused to make sure
b980ac18
JK		 1621 * next_to_use != next_to_clean
1622 */
9d5c8243 1623 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1624 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1625 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1626 }
9d5c8243
AK		 1627}
1628
88a268c1 1629/**
b980ac18
JK		 1630 * igb_power_up_link - Power up the phy/serdes link
1631 * @adapter: address of board private structure
88a268c1
NN		 1632 **/
1633void igb_power_up_link(struct igb_adapter *adapter)
1634{
76886596
AA		 1635 igb_reset_phy(&adapter->hw);
1636
88a268c1
NN		 1637 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1638 igb_power_up_phy_copper(&adapter->hw);
1639 else
1640 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1641
1642 igb_setup_link(&adapter->hw);
88a268c1
NN		 1643}
1644
1645/**
b980ac18
JK		 1646 * igb_power_down_link - Power down the phy/serdes link
1647 * @adapter: address of board private structure
88a268c1
NN		 1648 */
1649static void igb_power_down_link(struct igb_adapter *adapter)
1650{
1651 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1652 igb_power_down_phy_copper_82575(&adapter->hw);
1653 else
1654 igb_shutdown_serdes_link_82575(&adapter->hw);
1655}
9d5c8243 1656
56cec249
CW		 1657/**
1658 * Detect and switch function for Media Auto Sense
1659 * @adapter: address of the board private structure
1660 **/
1661static void igb_check_swap_media(struct igb_adapter *adapter)
1662{
1663 struct e1000_hw *hw = &adapter->hw;
1664 u32 ctrl_ext, connsw;
1665 bool swap_now = false;
1666
1667 ctrl_ext = rd32(E1000_CTRL_EXT);
1668 connsw = rd32(E1000_CONNSW);
1669
1670 /* need to live swap if current media is copper and we have fiber/serdes
1671 * to go to.
1672 */
1673
1674 if ((hw->phy.media_type == e1000_media_type_copper) &&
1675 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1676 swap_now = true;
1677 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1678 /* copper signal takes time to appear */
1679 if (adapter->copper_tries < 4) {
1680 adapter->copper_tries++;
1681 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1682 wr32(E1000_CONNSW, connsw);
1683 return;
1684 } else {
1685 adapter->copper_tries = 0;
1686 if ((connsw & E1000_CONNSW_PHYSD) &&
1687 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1688 swap_now = true;
1689 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1690 wr32(E1000_CONNSW, connsw);
1691 }
1692 }
1693 }
1694
1695 if (!swap_now)
1696 return;
1697
1698 switch (hw->phy.media_type) {
1699 case e1000_media_type_copper:
1700 netdev_info(adapter->netdev,
1701 "MAS: changing media to fiber/serdes\n");
1702 ctrl_ext |=
1703 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1704 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1705 adapter->copper_tries = 0;
1706 break;
1707 case e1000_media_type_internal_serdes:
1708 case e1000_media_type_fiber:
1709 netdev_info(adapter->netdev,
1710 "MAS: changing media to copper\n");
1711 ctrl_ext &=
1712 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1713 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1714 break;
1715 default:
1716 /* shouldn't get here during regular operation */
1717 netdev_err(adapter->netdev,
1718 "AMS: Invalid media type found, returning\n");
1719 break;
1720 }
1721 wr32(E1000_CTRL_EXT, ctrl_ext);
1722}
1723
9d5c8243 1724/**
b980ac18
JK		 1725 * igb_up - Open the interface and prepare it to handle traffic
1726 * @adapter: board private structure
9d5c8243 1727 **/
9d5c8243
AK		 1728int igb_up(struct igb_adapter *adapter)
1729{
1730 struct e1000_hw *hw = &adapter->hw;
1731 int i;
1732
1733 /* hardware has been reset, we need to reload some things */
1734 igb_configure(adapter);
1735
1736 clear_bit(__IGB_DOWN, &adapter->state);
1737
0d1ae7f4
AD		 1738 for (i = 0; i < adapter->num_q_vectors; i++)
1739 napi_enable(&(adapter->q_vector[i]->napi));
1740
cd14ef54 1741 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1742 igb_configure_msix(adapter);
feeb2721
AD		 1743 else
1744 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1745
1746 /* Clear any pending interrupts. */
1747 rd32(E1000_ICR);
1748 igb_irq_enable(adapter);
1749
d4960307
AD		 1750 /* notify VFs that reset has been completed */
1751 if (adapter->vfs_allocated_count) {
1752 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1753
d4960307
AD		 1754 reg_data |= E1000_CTRL_EXT_PFRSTD;
1755 wr32(E1000_CTRL_EXT, reg_data);
1756 }
1757
4cb9be7a
JB		 1758 netif_tx_start_all_queues(adapter->netdev);
1759
25568a53
AD		 1760 /* start the watchdog. */
1761 hw->mac.get_link_status = 1;
1762 schedule_work(&adapter->watchdog_task);
1763
f4c01e96
CW		 1764 if ((adapter->flags & IGB_FLAG_EEE) &&
1765 (!hw->dev_spec._82575.eee_disable))
1766 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1767
9d5c8243
AK		 1768 return 0;
1769}
1770
1771void igb_down(struct igb_adapter *adapter)
1772{
9d5c8243 1773 struct net_device *netdev = adapter->netdev;
330a6d6a 1774 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1775 u32 tctl, rctl;
1776 int i;
1777
1778 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1779 * reschedule our watchdog timer
1780 */
9d5c8243
AK		 1781 set_bit(__IGB_DOWN, &adapter->state);
1782
1783 /* disable receives in the hardware */
1784 rctl = rd32(E1000_RCTL);
1785 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1786 /* flush and sleep below */
1787
f28ea083 1788 netif_carrier_off(netdev);
fd2ea0a7 1789 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1790
1791 /* disable transmits in the hardware */
1792 tctl = rd32(E1000_TCTL);
1793 tctl &= ~E1000_TCTL_EN;
1794 wr32(E1000_TCTL, tctl);
1795 /* flush both disables and wait for them to finish */
1796 wrfl();
0d451e79 1797 usleep_range(10000, 11000);
9d5c8243 1798
41f149a2
CW		 1799 igb_irq_disable(adapter);
1800
aa9b8cc4
AA		 1801 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1802
41f149a2 1803 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1804 if (adapter->q_vector[i]) {
1805 napi_synchronize(&adapter->q_vector[i]->napi);
1806 napi_disable(&adapter->q_vector[i]->napi);
1807 }
41f149a2 1808 }
9d5c8243 1809
9d5c8243
AK		 1810 del_timer_sync(&adapter->watchdog_timer);
1811 del_timer_sync(&adapter->phy_info_timer);
1812
04fe6358 1813 /* record the stats before reset*/
12dcd86b
ED		 1814 spin_lock(&adapter->stats64_lock);
1815 igb_update_stats(adapter, &adapter->stats64);
1816 spin_unlock(&adapter->stats64_lock);
04fe6358 1817
9d5c8243
AK		 1818 adapter->link_speed = 0;
1819 adapter->link_duplex = 0;
1820
3023682e
JK		 1821 if (!pci_channel_offline(adapter->pdev))
1822 igb_reset(adapter);
16903caa
AD		 1823
1824 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1825 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1826
9d5c8243
AK		 1827 igb_clean_all_tx_rings(adapter);
1828 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1829#ifdef CONFIG_IGB_DCA
1830
1831 /* since we reset the hardware DCA settings were cleared */
1832 igb_setup_dca(adapter);
1833#endif
9d5c8243
AK		 1834}
1835
1836void igb_reinit_locked(struct igb_adapter *adapter)
1837{
1838 WARN_ON(in_interrupt());
1839 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1840 usleep_range(1000, 2000);
9d5c8243
AK		 1841 igb_down(adapter);
1842 igb_up(adapter);
1843 clear_bit(__IGB_RESETTING, &adapter->state);
1844}
1845
56cec249
CW		 1846/** igb_enable_mas - Media Autosense re-enable after swap
1847 *
1848 * @adapter: adapter struct
1849 **/
8cfb879d 1850static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1851{
1852 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1853 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1854
1855 /* configure for SerDes media detect */
8cfb879d
TF		 1856 if ((hw->phy.media_type == e1000_media_type_copper) &&
1857 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1858 connsw |= E1000_CONNSW_ENRGSRC;
1859 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1860 wr32(E1000_CONNSW, connsw);
1861 wrfl();
56cec249 1862 }
56cec249
CW		 1863}
1864
9d5c8243
AK		 1865void igb_reset(struct igb_adapter *adapter)
1866{
090b1795 1867 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1868 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1869 struct e1000_mac_info *mac = &hw->mac;
1870 struct e1000_fc_info *fc = &hw->fc;
45693bcb 1871 u32 pba, hwm;
9d5c8243
AK		 1872
1873 /* Repartition Pba for greater than 9k mtu
1874 * To take effect CTRL.RST is required.
1875 */
fa4dfae0 1876 switch (mac->type) {
d2ba2ed8 1877 case e1000_i350:
ceb5f13b 1878 case e1000_i354:
55cac248
AD		 1879 case e1000_82580:
1880 pba = rd32(E1000_RXPBS);
1881 pba = igb_rxpbs_adjust_82580(pba);
1882 break;
fa4dfae0 1883 case e1000_82576:
d249be54
AD		 1884 pba = rd32(E1000_RXPBS);
1885 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1886 break;
1887 case e1000_82575:
f96a8a0b
CW		 1888 case e1000_i210:
1889 case e1000_i211:
fa4dfae0
AD		 1890 default:
1891 pba = E1000_PBA_34K;
1892 break;
2d064c06 1893 }
9d5c8243 1894
45693bcb
AD		 1895 if (mac->type == e1000_82575) {
1896 u32 min_rx_space, min_tx_space, needed_tx_space;
1897
1898 /* write Rx PBA so that hardware can report correct Tx PBA */
9d5c8243
AK		 1899 wr32(E1000_PBA, pba);
1900
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1906 * expressed in KB.
1907 */
45693bcb
AD		 1908 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1909
1910 /* The Tx FIFO also stores 16 bytes of information about the Tx
1911 * but don't include Ethernet FCS because hardware appends it.
1912 * We only need to round down to the nearest 512 byte block
1913 * count since the value we care about is 2 frames, not 1.
b980ac18 1914 */
45693bcb
AD		 1915 min_tx_space = adapter->max_frame_size;
1916 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1917 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1918
1919 /* upper 16 bits has Tx packet buffer allocation size in KB */
1920 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
9d5c8243
AK		 1921
1922 /* If current Tx allocation is less than the min Tx FIFO size,
1923 * and the min Tx FIFO size is less than the current Rx FIFO
45693bcb 1924 * allocation, take space away from current Rx allocation.
b980ac18 1925 */
45693bcb
AD		 1926 if (needed_tx_space < pba) {
1927 pba -= needed_tx_space;
9d5c8243 1928
b980ac18
JK		 1929 /* if short on Rx space, Rx wins and must trump Tx
1930 * adjustment
1931 */
9d5c8243
AK		 1932 if (pba < min_rx_space)
1933 pba = min_rx_space;
1934 }
45693bcb
AD		 1935
1936 /* adjust PBA for jumbo frames */
2d064c06 1937 wr32(E1000_PBA, pba);
9d5c8243 1938 }
9d5c8243 1939
45693bcb
AD		 1940 /* flow control settings
1941 * The high water mark must be low enough to fit one full frame
1942 * after transmitting the pause frame. As such we must have enough
1943 * space to allow for us to complete our current transmit and then
1944 * receive the frame that is in progress from the link partner.
1945 * Set it to:
1946 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
b980ac18 1947 */
45693bcb 1948 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
9d5c8243 1949
d48507fe 1950 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1951 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1952 fc->pause_time = 0xFFFF;
1953 fc->send_xon = 1;
0cce119a 1954 fc->current_mode = fc->requested_mode;
9d5c8243 1955
4ae196df
AD		 1956 /* disable receive for all VFs and wait one second */
1957 if (adapter->vfs_allocated_count) {
1958 int i;
9005df38 1959
4ae196df 1960 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1961 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1962
1963 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1964 igb_ping_all_vfs(adapter);
4ae196df
AD		 1965
1966 /* disable transmits and receives */
1967 wr32(E1000_VFRE, 0);
1968 wr32(E1000_VFTE, 0);
1969 }
1970
9d5c8243 1971 /* Allow time for pending master requests to run */
330a6d6a 1972 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1973 wr32(E1000_WUC, 0);
1974
56cec249
CW		 1975 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1976 /* need to resetup here after media swap */
1977 adapter->ei.get_invariants(hw);
1978 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1979 }
8cfb879d
TF		 1980 if ((mac->type == e1000_82575) &&
1981 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1982 igb_enable_mas(adapter);
56cec249 1983 }
330a6d6a 1984 if (hw->mac.ops.init_hw(hw))
090b1795 1985 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1986
b980ac18 1987 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1988 * control is off when forcing speed.
1989 */
1990 if (!hw->mac.autoneg)
1991 igb_force_mac_fc(hw);
1992
b6e0c419 1993 igb_init_dmac(adapter, pba);
e428893b
CW		 1994#ifdef CONFIG_IGB_HWMON
1995 /* Re-initialize the thermal sensor on i350 devices. */
1996 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1997 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1998 /* If present, re-initialize the external thermal sensor
1999 * interface.
2000 */
2001 if (adapter->ets)
2002 mac->ops.init_thermal_sensor_thresh(hw);
2003 }
2004 }
2005#endif
b936136d 2006 /* Re-establish EEE setting */
f4c01e96
CW		 2007 if (hw->phy.media_type == e1000_media_type_copper) {
2008 switch (mac->type) {
2009 case e1000_i350:
2010 case e1000_i210:
2011 case e1000_i211:
c4c112f1 2012 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2013 break;
2014 case e1000_i354:
c4c112f1 2015 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2016 break;
2017 default:
2018 break;
2019 }
2020 }
88a268c1
NN		 2021 if (!netif_running(adapter->netdev))
2022 igb_power_down_link(adapter);
2023
9d5c8243
AK		 2024 igb_update_mng_vlan(adapter);
2025
2026 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2027 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2028
1f6e8178
MV		 2029 /* Re-enable PTP, where applicable. */
2030 igb_ptp_reset(adapter);
1f6e8178 2031
330a6d6a 2032 igb_get_phy_info(hw);
9d5c8243
AK		 2033}
2034
c8f44aff
MM		 2035static netdev_features_t igb_fix_features(struct net_device *netdev,
2036 netdev_features_t features)
b2cb09b1 2037{
b980ac18
JK		 2038 /* Since there is no support for separate Rx/Tx vlan accel
2039 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2040 */
f646968f
PM		 2041 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2042 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2043 else
f646968f 2044 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2045
2046 return features;
2047}
2048
c8f44aff
MM		 2049static int igb_set_features(struct net_device *netdev,
2050 netdev_features_t features)
ac52caa3 2051{
c8f44aff 2052 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2053 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2054
f646968f 2055 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2056 igb_vlan_mode(netdev, features);
2057
16903caa 2058 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
89eaefb6
BG		 2059 return 0;
2060
2061 netdev->features = features;
2062
2063 if (netif_running(netdev))
2064 igb_reinit_locked(adapter);
2065 else
2066 igb_reset(adapter);
2067
ac52caa3
MM		 2068 return 0;
2069}
2070
268f9d33
AD		 2071static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2072 struct net_device *dev,
2073 const unsigned char *addr, u16 vid,
2074 u16 flags)
2075{
2076 /* guarantee we can provide a unique filter for the unicast address */
2077 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2078 struct igb_adapter *adapter = netdev_priv(dev);
2079 struct e1000_hw *hw = &adapter->hw;
2080 int vfn = adapter->vfs_allocated_count;
2081 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2082
2083 if (netdev_uc_count(dev) >= rar_entries)
2084 return -ENOMEM;
2085 }
2086
2087 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2088}
2089
e10715d3
AD		 2090#define IGB_MAX_MAC_HDR_LEN 127
2091#define IGB_MAX_NETWORK_HDR_LEN 511
2092
2093static netdev_features_t
2094igb_features_check(struct sk_buff *skb, struct net_device *dev,
2095 netdev_features_t features)
2096{
2097 unsigned int network_hdr_len, mac_hdr_len;
2098
2099 /* Make certain the headers can be described by a context descriptor */
2100 mac_hdr_len = skb_network_header(skb) - skb->data;
2101 if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2102 return features & ~(NETIF_F_HW_CSUM |
2103 NETIF_F_SCTP_CRC |
2104 NETIF_F_HW_VLAN_CTAG_TX |
2105 NETIF_F_TSO |
2106 NETIF_F_TSO6);
2107
2108 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2109 if (unlikely(network_hdr_len > IGB_MAX_NETWORK_HDR_LEN))
2110 return features & ~(NETIF_F_HW_CSUM |
2111 NETIF_F_SCTP_CRC |
2112 NETIF_F_TSO |
2113 NETIF_F_TSO6);
2114
2115 /* We can only support IPV4 TSO in tunnels if we can mangle the
2116 * inner IP ID field, so strip TSO if MANGLEID is not supported.
2117 */
2118 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2119 features &= ~NETIF_F_TSO;
2120
2121 return features;
2122}
2123
2e5c6922 2124static const struct net_device_ops igb_netdev_ops = {
559e9c49 2125 .ndo_open = igb_open,
2e5c6922 2126 .ndo_stop = igb_close,
cd392f5c 2127 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2128 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2129 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2130 .ndo_set_mac_address = igb_set_mac,
2131 .ndo_change_mtu = igb_change_mtu,
2132 .ndo_do_ioctl = igb_ioctl,
2133 .ndo_tx_timeout = igb_tx_timeout,
2134 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2135 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2136 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2137 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2138 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2139 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2140 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2141 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2142#ifdef CONFIG_NET_POLL_CONTROLLER
2143 .ndo_poll_controller = igb_netpoll,
2144#endif
b2cb09b1
JP		 2145 .ndo_fix_features = igb_fix_features,
2146 .ndo_set_features = igb_set_features,
268f9d33 2147 .ndo_fdb_add = igb_ndo_fdb_add,
e10715d3 2148 .ndo_features_check = igb_features_check,
2e5c6922
SH		 2149};
2150
d67974f0
CW		 2151/**
2152 * igb_set_fw_version - Configure version string for ethtool
2153 * @adapter: adapter struct
d67974f0
CW		 2154 **/
2155void igb_set_fw_version(struct igb_adapter *adapter)
2156{
2157 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2158 struct e1000_fw_version fw;
2159
2160 igb_get_fw_version(hw, &fw);
2161
2162 switch (hw->mac.type) {
7dc98a62 2163 case e1000_i210:
0b1a6f2e 2164 case e1000_i211:
7dc98a62
CW		 2165 if (!(igb_get_flash_presence_i210(hw))) {
2166 snprintf(adapter->fw_version,
2167 sizeof(adapter->fw_version),
2168 "%2d.%2d-%d",
2169 fw.invm_major, fw.invm_minor,
2170 fw.invm_img_type);
2171 break;
2172 }
2173 /* fall through */
0b1a6f2e
CW		 2174 default:
2175 /* if option is rom valid, display its version too */
2176 if (fw.or_valid) {
2177 snprintf(adapter->fw_version,
2178 sizeof(adapter->fw_version),
2179 "%d.%d, 0x%08x, %d.%d.%d",
2180 fw.eep_major, fw.eep_minor, fw.etrack_id,
2181 fw.or_major, fw.or_build, fw.or_patch);
2182 /* no option rom */
7dc98a62 2183 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2184 snprintf(adapter->fw_version,
7dc98a62
CW		 2185 sizeof(adapter->fw_version),
2186 "%d.%d, 0x%08x",
2187 fw.eep_major, fw.eep_minor, fw.etrack_id);
2188 } else {
2189 snprintf(adapter->fw_version,
2190 sizeof(adapter->fw_version),
2191 "%d.%d.%d",
2192 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2193 }
2194 break;
d67974f0 2195 }
d67974f0
CW		 2196}
2197
56cec249
CW		 2198/**
2199 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2200 *
2201 * @adapter: adapter struct
2202 **/
2203static void igb_init_mas(struct igb_adapter *adapter)
2204{
2205 struct e1000_hw *hw = &adapter->hw;
2206 u16 eeprom_data;
2207
2208 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2209 switch (hw->bus.func) {
2210 case E1000_FUNC_0:
2211 if (eeprom_data & IGB_MAS_ENABLE_0) {
2212 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2213 netdev_info(adapter->netdev,
2214 "MAS: Enabling Media Autosense for port %d\n",
2215 hw->bus.func);
2216 }
2217 break;
2218 case E1000_FUNC_1:
2219 if (eeprom_data & IGB_MAS_ENABLE_1) {
2220 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2221 netdev_info(adapter->netdev,
2222 "MAS: Enabling Media Autosense for port %d\n",
2223 hw->bus.func);
2224 }
2225 break;
2226 case E1000_FUNC_2:
2227 if (eeprom_data & IGB_MAS_ENABLE_2) {
2228 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2229 netdev_info(adapter->netdev,
2230 "MAS: Enabling Media Autosense for port %d\n",
2231 hw->bus.func);
2232 }
2233 break;
2234 case E1000_FUNC_3:
2235 if (eeprom_data & IGB_MAS_ENABLE_3) {
2236 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2237 netdev_info(adapter->netdev,
2238 "MAS: Enabling Media Autosense for port %d\n",
2239 hw->bus.func);
2240 }
2241 break;
2242 default:
2243 /* Shouldn't get here */
2244 netdev_err(adapter->netdev,
2245 "MAS: Invalid port configuration, returning\n");
2246 break;
2247 }
2248}
2249
b980ac18
JK		 2250/**
2251 * igb_init_i2c - Init I2C interface
441fc6fd 2252 * @adapter: pointer to adapter structure
b980ac18 2253 **/
441fc6fd
CW		 2254static s32 igb_init_i2c(struct igb_adapter *adapter)
2255{
23d87824 2256 s32 status = 0;
441fc6fd
CW		 2257
2258 /* I2C interface supported on i350 devices */
2259 if (adapter->hw.mac.type != e1000_i350)
23d87824 2260 return 0;
441fc6fd
CW		 2261
2262 /* Initialize the i2c bus which is controlled by the registers.
2263 * This bus will use the i2c_algo_bit structue that implements
2264 * the protocol through toggling of the 4 bits in the register.
2265 */
2266 adapter->i2c_adap.owner = THIS_MODULE;
2267 adapter->i2c_algo = igb_i2c_algo;
2268 adapter->i2c_algo.data = adapter;
2269 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2270 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2271 strlcpy(adapter->i2c_adap.name, "igb BB",
2272 sizeof(adapter->i2c_adap.name));
2273 status = i2c_bit_add_bus(&adapter->i2c_adap);
2274 return status;
2275}
2276
9d5c8243 2277/**
b980ac18
JK		 2278 * igb_probe - Device Initialization Routine
2279 * @pdev: PCI device information struct
2280 * @ent: entry in igb_pci_tbl
9d5c8243 2281 *
b980ac18 2282 * Returns 0 on success, negative on failure
9d5c8243 2283 *
b980ac18
JK		 2284 * igb_probe initializes an adapter identified by a pci_dev structure.
2285 * The OS initialization, configuring of the adapter private structure,
2286 * and a hardware reset occur.
9d5c8243 2287 **/
1dd06ae8 2288static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2289{
2290 struct net_device *netdev;
2291 struct igb_adapter *adapter;
2292 struct e1000_hw *hw;
4337e993 2293 u16 eeprom_data = 0;
9835fd73 2294 s32 ret_val;
4337e993 2295 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2296 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2297 int err, pci_using_dac;
9835fd73 2298 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2299
bded64a7
AG		 2300 /* Catch broken hardware that put the wrong VF device ID in
2301 * the PCIe SR-IOV capability.
2302 */
2303 if (pdev->is_virtfn) {
2304 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2305 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2306 return -EINVAL;
2307 }
2308
aed5dec3 2309 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2310 if (err)
2311 return err;
2312
2313 pci_using_dac = 0;
dc4ff9bb 2314 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2315 if (!err) {
dc4ff9bb 2316 pci_using_dac = 1;
9d5c8243 2317 } else {
dc4ff9bb 2318 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2319 if (err) {
dc4ff9bb
RK		 2320 dev_err(&pdev->dev,
2321 "No usable DMA configuration, aborting\n");
2322 goto err_dma;
9d5c8243
AK		 2323 }
2324 }
2325
aed5dec3 2326 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2327 IORESOURCE_MEM),
2328 igb_driver_name);
9d5c8243
AK		 2329 if (err)
2330 goto err_pci_reg;
2331
19d5afd4 2332 pci_enable_pcie_error_reporting(pdev);
40a914fa 2333
9d5c8243 2334 pci_set_master(pdev);
c682fc23 2335 pci_save_state(pdev);
9d5c8243
AK		 2336
2337 err = -ENOMEM;
1bfaf07b 2338 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2339 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2340 if (!netdev)
2341 goto err_alloc_etherdev;
2342
2343 SET_NETDEV_DEV(netdev, &pdev->dev);
2344
2345 pci_set_drvdata(pdev, netdev);
2346 adapter = netdev_priv(netdev);
2347 adapter->netdev = netdev;
2348 adapter->pdev = pdev;
2349 hw = &adapter->hw;
2350 hw->back = adapter;
b3f4d599 2351 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2352
9d5c8243 2353 err = -EIO;
73bf8048
JW		 2354 adapter->io_addr = pci_iomap(pdev, 0, 0);
2355 if (!adapter->io_addr)
9d5c8243 2356 goto err_ioremap;
73bf8048
JW		 2357 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2358 hw->hw_addr = adapter->io_addr;
9d5c8243 2359
2e5c6922 2360 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2361 igb_set_ethtool_ops(netdev);
9d5c8243 2362 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2363
2364 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2365
89dbefb2
AS		 2366 netdev->mem_start = pci_resource_start(pdev, 0);
2367 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2368
9d5c8243
AK		 2369 /* PCI config space info */
2370 hw->vendor_id = pdev->vendor;
2371 hw->device_id = pdev->device;
2372 hw->revision_id = pdev->revision;
2373 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2374 hw->subsystem_device_id = pdev->subsystem_device;
2375
9d5c8243
AK		 2376 /* Copy the default MAC, PHY and NVM function pointers */
2377 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2378 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2379 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2380 /* Initialize skew-specific constants */
2381 err = ei->get_invariants(hw);
2382 if (err)
450c87c8 2383 goto err_sw_init;
9d5c8243 2384
450c87c8 2385 /* setup the private structure */
9d5c8243
AK		 2386 err = igb_sw_init(adapter);
2387 if (err)
2388 goto err_sw_init;
2389
2390 igb_get_bus_info_pcie(hw);
2391
2392 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2393
2394 /* Copper options */
2395 if (hw->phy.media_type == e1000_media_type_copper) {
2396 hw->phy.mdix = AUTO_ALL_MODES;
2397 hw->phy.disable_polarity_correction = false;
2398 hw->phy.ms_type = e1000_ms_hw_default;
2399 }
2400
2401 if (igb_check_reset_block(hw))
2402 dev_info(&pdev->dev,
2403 "PHY reset is blocked due to SOL/IDER session.\n");
2404
b980ac18 2405 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2406 * set by igb_sw_init so we should use an or instead of an
2407 * assignment.
2408 */
2409 netdev->features |= NETIF_F_SG |
077887c3
AD		 2410 NETIF_F_TSO |
2411 NETIF_F_TSO6 |
2412 NETIF_F_RXHASH |
2413 NETIF_F_RXCSUM |
e10715d3 2414 NETIF_F_HW_CSUM;
077887c3 2415
6e033700
AD		 2416 if (hw->mac.type >= e1000_82576)
2417 netdev->features |= NETIF_F_SCTP_CRC;
2418
e10715d3
AD		 2419#define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
2420 NETIF_F_GSO_GRE_CSUM | \
7e13318d 2421 NETIF_F_GSO_IPXIP4 | \
e10715d3
AD		 2422 NETIF_F_GSO_UDP_TUNNEL | \
2423 NETIF_F_GSO_UDP_TUNNEL_CSUM)
2424
2425 netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
2426 netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
2427
077887c3 2428 /* copy netdev features into list of user selectable features */
e10715d3
AD		 2429 netdev->hw_features |= netdev->features |
2430 NETIF_F_HW_VLAN_CTAG_RX |
2431 NETIF_F_HW_VLAN_CTAG_TX |
2432 NETIF_F_RXALL;
077887c3 2433
6e033700
AD		 2434 if (hw->mac.type >= e1000_i350)
2435 netdev->hw_features |= NETIF_F_NTUPLE;
2436
e10715d3
AD		 2437 if (pci_using_dac)
2438 netdev->features |= NETIF_F_HIGHDMA;
6e033700 2439
e10715d3 2440 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
6e033700 2441 netdev->mpls_features |= NETIF_F_HW_CSUM;
e10715d3 2442 netdev->hw_enc_features |= netdev->vlan_features;
48f29ffc 2443
e10715d3
AD		 2444 /* set this bit last since it cannot be part of vlan_features */
2445 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
2446 NETIF_F_HW_VLAN_CTAG_RX |
2447 NETIF_F_HW_VLAN_CTAG_TX;
6b8f0922 2448
e10715d3 2449 netdev->priv_flags |= IFF_SUPP_NOFCS;
9d5c8243 2450
01789349
JP		 2451 netdev->priv_flags |= IFF_UNICAST_FLT;
2452
330a6d6a 2453 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2454
2455 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2456 * known good starting state
2457 */
9d5c8243
AK		 2458 hw->mac.ops.reset_hw(hw);
2459
ef3a0092
CW		 2460 /* make sure the NVM is good , i211/i210 parts can have special NVM
2461 * that doesn't contain a checksum
f96a8a0b 2462 */
ef3a0092
CW		 2463 switch (hw->mac.type) {
2464 case e1000_i210:
2465 case e1000_i211:
2466 if (igb_get_flash_presence_i210(hw)) {
2467 if (hw->nvm.ops.validate(hw) < 0) {
2468 dev_err(&pdev->dev,
2469 "The NVM Checksum Is Not Valid\n");
2470 err = -EIO;
2471 goto err_eeprom;
2472 }
2473 }
2474 break;
2475 default:
f96a8a0b
CW		 2476 if (hw->nvm.ops.validate(hw) < 0) {
2477 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2478 err = -EIO;
2479 goto err_eeprom;
2480 }
ef3a0092 2481 break;
9d5c8243
AK		 2482 }
2483
806ffb1d
JH		 2484 if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
2485 /* copy the MAC address out of the NVM */
2486 if (hw->mac.ops.read_mac_addr(hw))
2487 dev_err(&pdev->dev, "NVM Read Error\n");
2488 }
9d5c8243
AK		 2489
2490 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2491
aaeb6cdf 2492 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2493 dev_err(&pdev->dev, "Invalid MAC Address\n");
2494 err = -EIO;
2495 goto err_eeprom;
2496 }
2497
d67974f0
CW		 2498 /* get firmware version for ethtool -i */
2499 igb_set_fw_version(adapter);
2500
27dff8b2
TF		 2501 /* configure RXPBSIZE and TXPBSIZE */
2502 if (hw->mac.type == e1000_i210) {
2503 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2504 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2505 }
2506
c061b18d 2507 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2508 (unsigned long) adapter);
c061b18d 2509 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2510 (unsigned long) adapter);
9d5c8243
AK		 2511
2512 INIT_WORK(&adapter->reset_task, igb_reset_task);
2513 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2514
450c87c8 2515 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2516 adapter->fc_autoneg = true;
2517 hw->mac.autoneg = true;
2518 hw->phy.autoneg_advertised = 0x2f;
2519
0cce119a
AD		 2520 hw->fc.requested_mode = e1000_fc_default;
2521 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2522
9d5c8243
AK		 2523 igb_validate_mdi_setting(hw);
2524
63d4a8f9 2525 /* By default, support wake on port A */
a2cf8b6c 2526 if (hw->bus.func == 0)
63d4a8f9
MV		 2527 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2528
2529 /* Check the NVM for wake support on non-port A ports */
2530 if (hw->mac.type >= e1000_82580)
55cac248 2531 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2532 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2533 &eeprom_data);
a2cf8b6c
AD		 2534 else if (hw->bus.func == 1)
2535 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2536
63d4a8f9
MV		 2537 if (eeprom_data & IGB_EEPROM_APME)
2538 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2539
2540 /* now that we have the eeprom settings, apply the special cases where
2541 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2542 * lan on a particular port
2543 */
9d5c8243
AK		 2544 switch (pdev->device) {
2545 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2546 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2547 break;
2548 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2549 case E1000_DEV_ID_82576_FIBER:
2550 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2551 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2552 * regardless of eeprom setting
2553 */
9d5c8243 2554 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2555 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2556 break;
c8ea5ea9 2557 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2558 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2559 /* if quad port adapter, disable WoL on all but port A */
2560 if (global_quad_port_a != 0)
63d4a8f9 2561 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2562 else
2563 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2564 /* Reset for multiple quad port adapters */
2565 if (++global_quad_port_a == 4)
2566 global_quad_port_a = 0;
2567 break;
63d4a8f9
MV		 2568 default:
2569 /* If the device can't wake, don't set software support */
2570 if (!device_can_wakeup(&adapter->pdev->dev))
2571 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2572 }
2573
2574 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2575 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2576 adapter->wol |= E1000_WUFC_MAG;
2577
2578 /* Some vendors want WoL disabled by default, but still supported */
2579 if ((hw->mac.type == e1000_i350) &&
2580 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2581 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2582 adapter->wol = 0;
2583 }
2584
5e350b92
TF		 2585 /* Some vendors want the ability to Use the EEPROM setting as
2586 * enable/disable only, and not for capability
2587 */
2588 if (((hw->mac.type == e1000_i350) ||
2589 (hw->mac.type == e1000_i354)) &&
2590 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
2591 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2592 adapter->wol = 0;
2593 }
2594 if (hw->mac.type == e1000_i350) {
2595 if (((pdev->subsystem_device == 0x5001) ||
2596 (pdev->subsystem_device == 0x5002)) &&
2597 (hw->bus.func == 0)) {
2598 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2599 adapter->wol = 0;
2600 }
2601 if (pdev->subsystem_device == 0x1F52)
2602 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2603 }
2604
63d4a8f9
MV		 2605 device_set_wakeup_enable(&adapter->pdev->dev,
2606 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2607
2608 /* reset the hardware with the new settings */
2609 igb_reset(adapter);
2610
441fc6fd
CW		 2611 /* Init the I2C interface */
2612 err = igb_init_i2c(adapter);
2613 if (err) {
2614 dev_err(&pdev->dev, "failed to init i2c interface\n");
2615 goto err_eeprom;
2616 }
2617
9d5c8243 2618 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2619 * driver.
2620 */
9d5c8243
AK		 2621 igb_get_hw_control(adapter);
2622
9d5c8243
AK		 2623 strcpy(netdev->name, "eth%d");
2624 err = register_netdev(netdev);
2625 if (err)
2626 goto err_register;
2627
b168dfc5
JB		 2628 /* carrier off reporting is important to ethtool even BEFORE open */
2629 netif_carrier_off(netdev);
2630
421e02f0 2631#ifdef CONFIG_IGB_DCA
bbd98fe4 2632 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2633 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2634 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2635 igb_setup_dca(adapter);
2636 }
fe4506b6 2637
38c845c7 2638#endif
e428893b
CW		 2639#ifdef CONFIG_IGB_HWMON
2640 /* Initialize the thermal sensor on i350 devices. */
2641 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2642 u16 ets_word;
3c89f6d0 2643
b980ac18 2644 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2645 * external thermal sensor.
2646 */
2647 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2648 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2649 adapter->ets = true;
2650 else
2651 adapter->ets = false;
2652 if (igb_sysfs_init(adapter))
2653 dev_err(&pdev->dev,
2654 "failed to allocate sysfs resources\n");
2655 } else {
2656 adapter->ets = false;
2657 }
2658#endif
56cec249
CW		 2659 /* Check if Media Autosense is enabled */
2660 adapter->ei = *ei;
2661 if (hw->dev_spec._82575.mas_capable)
2662 igb_init_mas(adapter);
2663
673b8b70 2664 /* do hw tstamp init after resetting */
7ebae817 2665 igb_ptp_init(adapter);
673b8b70 2666
9d5c8243 2667 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2668 /* print bus type/speed/width info, not applicable to i354 */
2669 if (hw->mac.type != e1000_i354) {
2670 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2671 netdev->name,
2672 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2673 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2674 "unknown"),
2675 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2676 "Width x4" :
2677 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2678 "Width x2" :
2679 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2680 "Width x1" : "unknown"), netdev->dev_addr);
2681 }
9d5c8243 2682
53ea6c7e
TF		 2683 if ((hw->mac.type >= e1000_i210 ||
2684 igb_get_flash_presence_i210(hw))) {
2685 ret_val = igb_read_part_string(hw, part_str,
2686 E1000_PBANUM_LENGTH);
2687 } else {
2688 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2689 }
2690
9835fd73
CW		 2691 if (ret_val)
2692 strcpy(part_str, "Unknown");
2693 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2694 dev_info(&pdev->dev,
2695 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2696 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2697 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2698 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2699 if (hw->phy.media_type == e1000_media_type_copper) {
2700 switch (hw->mac.type) {
2701 case e1000_i350:
2702 case e1000_i210:
2703 case e1000_i211:
2704 /* Enable EEE for internal copper PHY devices */
c4c112f1 2705 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2706 if ((!err) &&
2707 (!hw->dev_spec._82575.eee_disable)) {
2708 adapter->eee_advert =
2709 MDIO_EEE_100TX | MDIO_EEE_1000T;
2710 adapter->flags |= IGB_FLAG_EEE;
2711 }
2712 break;
2713 case e1000_i354:
ceb5f13b 2714 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2715 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2716 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2717 if ((!err) &&
2718 (!hw->dev_spec._82575.eee_disable)) {
2719 adapter->eee_advert =
2720 MDIO_EEE_100TX | MDIO_EEE_1000T;
2721 adapter->flags |= IGB_FLAG_EEE;
2722 }
2723 }
2724 break;
2725 default:
2726 break;
ceb5f13b 2727 }
09b068d4 2728 }
749ab2cd 2729 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2730 return 0;
2731
2732err_register:
2733 igb_release_hw_control(adapter);
441fc6fd 2734 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2735err_eeprom:
2736 if (!igb_check_reset_block(hw))
f5f4cf08 2737 igb_reset_phy(hw);
9d5c8243
AK		 2738
2739 if (hw->flash_address)
2740 iounmap(hw->flash_address);
9d5c8243 2741err_sw_init:
42ad1a03 2742 kfree(adapter->shadow_vfta);
047e0030 2743 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2744#ifdef CONFIG_PCI_IOV
2745 igb_disable_sriov(pdev);
2746#endif
73bf8048 2747 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2748err_ioremap:
2749 free_netdev(netdev);
2750err_alloc_etherdev:
559e9c49 2751 pci_release_selected_regions(pdev,
b980ac18 2752 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2753err_pci_reg:
2754err_dma:
2755 pci_disable_device(pdev);
2756 return err;
2757}
2758
fa44f2f1 2759#ifdef CONFIG_PCI_IOV
781798a1 2760static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2761{
2762 struct net_device *netdev = pci_get_drvdata(pdev);
2763 struct igb_adapter *adapter = netdev_priv(netdev);
2764 struct e1000_hw *hw = &adapter->hw;
2765
2766 /* reclaim resources allocated to VFs */
2767 if (adapter->vf_data) {
2768 /* disable iov and allow time for transactions to clear */
b09186d2 2769 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2770 dev_warn(&pdev->dev,
2771 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2772 return -EPERM;
2773 } else {
2774 pci_disable_sriov(pdev);
2775 msleep(500);
2776 }
2777
2778 kfree(adapter->vf_data);
2779 adapter->vf_data = NULL;
2780 adapter->vfs_allocated_count = 0;
2781 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2782 wrfl();
2783 msleep(100);
2784 dev_info(&pdev->dev, "IOV Disabled\n");
2785
2786 /* Re-enable DMA Coalescing flag since IOV is turned off */
2787 adapter->flags |= IGB_FLAG_DMAC;
2788 }
2789
2790 return 0;
2791}
2792
2793static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2794{
2795 struct net_device *netdev = pci_get_drvdata(pdev);
2796 struct igb_adapter *adapter = netdev_priv(netdev);
2797 int old_vfs = pci_num_vf(pdev);
2798 int err = 0;
2799 int i;
2800
cd14ef54 2801 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2802 err = -EPERM;
2803 goto out;
2804 }
fa44f2f1
GR		 2805 if (!num_vfs)
2806 goto out;
fa44f2f1 2807
781798a1
SA		 2808 if (old_vfs) {
2809 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2810 old_vfs, max_vfs);
2811 adapter->vfs_allocated_count = old_vfs;
2812 } else
2813 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2814
2815 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2816 sizeof(struct vf_data_storage), GFP_KERNEL);
2817
2818 /* if allocation failed then we do not support SR-IOV */
2819 if (!adapter->vf_data) {
2820 adapter->vfs_allocated_count = 0;
2821 dev_err(&pdev->dev,
2822 "Unable to allocate memory for VF Data Storage\n");
2823 err = -ENOMEM;
2824 goto out;
2825 }
2826
781798a1
SA		 2827 /* only call pci_enable_sriov() if no VFs are allocated already */
2828 if (!old_vfs) {
2829 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2830 if (err)
2831 goto err_out;
2832 }
fa44f2f1
GR		 2833 dev_info(&pdev->dev, "%d VFs allocated\n",
2834 adapter->vfs_allocated_count);
2835 for (i = 0; i < adapter->vfs_allocated_count; i++)
2836 igb_vf_configure(adapter, i);
2837
2838 /* DMA Coalescing is not supported in IOV mode. */
2839 adapter->flags &= ~IGB_FLAG_DMAC;
2840 goto out;
2841
2842err_out:
2843 kfree(adapter->vf_data);
2844 adapter->vf_data = NULL;
2845 adapter->vfs_allocated_count = 0;
2846out:
2847 return err;
2848}
2849
2850#endif
b980ac18 2851/**
441fc6fd
CW		 2852 * igb_remove_i2c - Cleanup I2C interface
2853 * @adapter: pointer to adapter structure
b980ac18 2854 **/
441fc6fd
CW		 2855static void igb_remove_i2c(struct igb_adapter *adapter)
2856{
441fc6fd
CW		 2857 /* free the adapter bus structure */
2858 i2c_del_adapter(&adapter->i2c_adap);
2859}
2860
9d5c8243 2861/**
b980ac18
JK		 2862 * igb_remove - Device Removal Routine
2863 * @pdev: PCI device information struct
9d5c8243 2864 *
b980ac18
JK		 2865 * igb_remove is called by the PCI subsystem to alert the driver
2866 * that it should release a PCI device. The could be caused by a
2867 * Hot-Plug event, or because the driver is going to be removed from
2868 * memory.
9d5c8243 2869 **/
9f9a12f8 2870static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2871{
2872 struct net_device *netdev = pci_get_drvdata(pdev);
2873 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2874 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2875
749ab2cd 2876 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2877#ifdef CONFIG_IGB_HWMON
2878 igb_sysfs_exit(adapter);
2879#endif
441fc6fd 2880 igb_remove_i2c(adapter);
a79f4f88 2881 igb_ptp_stop(adapter);
b980ac18 2882 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2883 * disable watchdog from being rescheduled.
2884 */
9d5c8243
AK		 2885 set_bit(__IGB_DOWN, &adapter->state);
2886 del_timer_sync(&adapter->watchdog_timer);
2887 del_timer_sync(&adapter->phy_info_timer);
2888
760141a5
TH		 2889 cancel_work_sync(&adapter->reset_task);
2890 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2891
421e02f0 2892#ifdef CONFIG_IGB_DCA
7dfc16fa 2893 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2894 dev_info(&pdev->dev, "DCA disabled\n");
2895 dca_remove_requester(&pdev->dev);
7dfc16fa 2896 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2897 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2898 }
2899#endif
2900
9d5c8243 2901 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2902 * would have already happened in close and is redundant.
2903 */
9d5c8243
AK		 2904 igb_release_hw_control(adapter);
2905
37680117 2906#ifdef CONFIG_PCI_IOV
fa44f2f1 2907 igb_disable_sriov(pdev);
37680117 2908#endif
559e9c49 2909
c23d92b8
AW		 2910 unregister_netdev(netdev);
2911
2912 igb_clear_interrupt_scheme(adapter);
2913
73bf8048 2914 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2915 if (hw->flash_address)
2916 iounmap(hw->flash_address);
559e9c49 2917 pci_release_selected_regions(pdev,
b980ac18 2918 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2919
1128c756 2920 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2921 free_netdev(netdev);
2922
19d5afd4 2923 pci_disable_pcie_error_reporting(pdev);
40a914fa 2924
9d5c8243
AK		 2925 pci_disable_device(pdev);
2926}
2927
a6b623e0 2928/**
b980ac18
JK		 2929 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2930 * @adapter: board private structure to initialize
a6b623e0 2931 *
b980ac18
JK		 2932 * This function initializes the vf specific data storage and then attempts to
2933 * allocate the VFs. The reason for ordering it this way is because it is much
2934 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2935 * the memory for the VFs.
a6b623e0 2936 **/
9f9a12f8 2937static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2938{
2939#ifdef CONFIG_PCI_IOV
2940 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2941 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2942
f96a8a0b
CW		 2943 /* Virtualization features not supported on i210 family. */
2944 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2945 return;
2946
be06998f
JB		 2947 /* Of the below we really only want the effect of getting
2948 * IGB_FLAG_HAS_MSIX set (if available), without which
2949 * igb_enable_sriov() has no effect.
2950 */
2951 igb_set_interrupt_capability(adapter, true);
2952 igb_reset_interrupt_capability(adapter);
2953
fa44f2f1 2954 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2955 igb_enable_sriov(pdev, max_vfs);
0224d663 2956
a6b623e0
AD		 2957#endif /* CONFIG_PCI_IOV */
2958}
2959
fa44f2f1 2960static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2961{
2962 struct e1000_hw *hw = &adapter->hw;
374a542d 2963 u32 max_rss_queues;
9d5c8243 2964
374a542d 2965 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2966 switch (hw->mac.type) {
374a542d
MV		 2967 case e1000_i211:
2968 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2969 break;
2970 case e1000_82575:
f96a8a0b 2971 case e1000_i210:
374a542d
MV		 2972 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2973 break;
2974 case e1000_i350:
2975 /* I350 cannot do RSS and SR-IOV at the same time */
2976 if (!!adapter->vfs_allocated_count) {
2977 max_rss_queues = 1;
2978 break;
2979 }
2980 /* fall through */
2981 case e1000_82576:
2982 if (!!adapter->vfs_allocated_count) {
2983 max_rss_queues = 2;
2984 break;
2985 }
2986 /* fall through */
2987 case e1000_82580:
ceb5f13b 2988 case e1000_i354:
374a542d
MV		 2989 default:
2990 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2991 break;
374a542d
MV		 2992 }
2993
2994 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2995
72ddef05
SS		 2996 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2997}
2998
2999void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3000 const u32 max_rss_queues)
3001{
3002 struct e1000_hw *hw = &adapter->hw;
3003
374a542d
MV		 3004 /* Determine if we need to pair queues. */
3005 switch (hw->mac.type) {
3006 case e1000_82575:
f96a8a0b 3007 case e1000_i211:
374a542d 3008 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 3009 break;
374a542d 3010 case e1000_82576:
374a542d
MV		 3011 case e1000_82580:
3012 case e1000_i350:
ceb5f13b 3013 case e1000_i354:
374a542d 3014 case e1000_i210:
f96a8a0b 3015 default:
b980ac18 3016 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 3017 * order to conserve interrupts due to limited supply.
3018 */
3019 if (adapter->rss_queues > (max_rss_queues / 2))
3020 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
37a5d163
SS		 3021 else
3022 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 3023 break;
3024 }
fa44f2f1
GR		 3025}
3026
3027/**
b980ac18
JK		 3028 * igb_sw_init - Initialize general software structures (struct igb_adapter)
3029 * @adapter: board private structure to initialize
fa44f2f1 3030 *
b980ac18
JK		 3031 * igb_sw_init initializes the Adapter private data structure.
3032 * Fields are initialized based on PCI device information and
3033 * OS network device settings (MTU size).
fa44f2f1
GR		 3034 **/
3035static int igb_sw_init(struct igb_adapter *adapter)
3036{
3037 struct e1000_hw *hw = &adapter->hw;
3038 struct net_device *netdev = adapter->netdev;
3039 struct pci_dev *pdev = adapter->pdev;
3040
3041 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3042
3043 /* set default ring sizes */
3044 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3045 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3046
3047 /* set default ITR values */
3048 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3049 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3050
3051 /* set default work limits */
3052 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3053
3054 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3055 VLAN_HLEN;
3056 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3057
3058 spin_lock_init(&adapter->stats64_lock);
3059#ifdef CONFIG_PCI_IOV
3060 switch (hw->mac.type) {
3061 case e1000_82576:
3062 case e1000_i350:
3063 if (max_vfs > 7) {
3064 dev_warn(&pdev->dev,
3065 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 3066 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 3067 } else
3068 adapter->vfs_allocated_count = max_vfs;
3069 if (adapter->vfs_allocated_count)
3070 dev_warn(&pdev->dev,
3071 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3072 break;
3073 default:
3074 break;
3075 }
3076#endif /* CONFIG_PCI_IOV */
3077
cbfe360a
SA		 3078 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3079 adapter->flags |= IGB_FLAG_HAS_MSIX;
3080
ceee3450
TF		 3081 igb_probe_vfs(adapter);
3082
fa44f2f1 3083 igb_init_queue_configuration(adapter);
a99955fc 3084
1128c756 3085 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 3086 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3087 GFP_ATOMIC);
1128c756 3088
a6b623e0 3089 /* This call may decrease the number of queues */
53c7d064 3090 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3091 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3092 return -ENOMEM;
3093 }
3094
3095 /* Explicitly disable IRQ since the NIC can be in any state. */
3096 igb_irq_disable(adapter);
3097
f96a8a0b 3098 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3099 adapter->flags &= ~IGB_FLAG_DMAC;
3100
9d5c8243
AK		 3101 set_bit(__IGB_DOWN, &adapter->state);
3102 return 0;
3103}
3104
3105/**
b980ac18
JK		 3106 * igb_open - Called when a network interface is made active
3107 * @netdev: network interface device structure
9d5c8243 3108 *
b980ac18 3109 * Returns 0 on success, negative value on failure
9d5c8243 3110 *
b980ac18
JK		 3111 * The open entry point is called when a network interface is made
3112 * active by the system (IFF_UP). At this point all resources needed
3113 * for transmit and receive operations are allocated, the interrupt
3114 * handler is registered with the OS, the watchdog timer is started,
3115 * and the stack is notified that the interface is ready.
9d5c8243 3116 **/
749ab2cd 3117static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3118{
3119 struct igb_adapter *adapter = netdev_priv(netdev);
3120 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3121 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3122 int err;
3123 int i;
3124
3125 /* disallow open during test */
749ab2cd
YZ		 3126 if (test_bit(__IGB_TESTING, &adapter->state)) {
3127 WARN_ON(resuming);
9d5c8243 3128 return -EBUSY;
749ab2cd
YZ		 3129 }
3130
3131 if (!resuming)
3132 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3133
b168dfc5
JB		 3134 netif_carrier_off(netdev);
3135
9d5c8243
AK		 3136 /* allocate transmit descriptors */
3137 err = igb_setup_all_tx_resources(adapter);
3138 if (err)
3139 goto err_setup_tx;
3140
3141 /* allocate receive descriptors */
3142 err = igb_setup_all_rx_resources(adapter);
3143 if (err)
3144 goto err_setup_rx;
3145
88a268c1 3146 igb_power_up_link(adapter);
9d5c8243 3147
9d5c8243
AK		 3148 /* before we allocate an interrupt, we must be ready to handle it.
3149 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3150 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3151 * clean_rx handler before we do so.
3152 */
9d5c8243
AK		 3153 igb_configure(adapter);
3154
3155 err = igb_request_irq(adapter);
3156 if (err)
3157 goto err_req_irq;
3158
0c2cc02e
AD		 3159 /* Notify the stack of the actual queue counts. */
3160 err = netif_set_real_num_tx_queues(adapter->netdev,
3161 adapter->num_tx_queues);
3162 if (err)
3163 goto err_set_queues;
3164
3165 err = netif_set_real_num_rx_queues(adapter->netdev,
3166 adapter->num_rx_queues);
3167 if (err)
3168 goto err_set_queues;
3169
9d5c8243
AK		 3170 /* From here on the code is the same as igb_up() */
3171 clear_bit(__IGB_DOWN, &adapter->state);
3172
0d1ae7f4
AD		 3173 for (i = 0; i < adapter->num_q_vectors; i++)
3174 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3175
3176 /* Clear any pending interrupts. */
3177 rd32(E1000_ICR);
844290e5
PW		 3178
3179 igb_irq_enable(adapter);
3180
d4960307
AD		 3181 /* notify VFs that reset has been completed */
3182 if (adapter->vfs_allocated_count) {
3183 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3184
d4960307
AD		 3185 reg_data |= E1000_CTRL_EXT_PFRSTD;
3186 wr32(E1000_CTRL_EXT, reg_data);
3187 }
3188
d55b53ff
JK		 3189 netif_tx_start_all_queues(netdev);
3190
749ab2cd
YZ		 3191 if (!resuming)
3192 pm_runtime_put(&pdev->dev);
3193
25568a53
AD		 3194 /* start the watchdog. */
3195 hw->mac.get_link_status = 1;
3196 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3197
3198 return 0;
3199
0c2cc02e
AD		 3200err_set_queues:
3201 igb_free_irq(adapter);
9d5c8243
AK		 3202err_req_irq:
3203 igb_release_hw_control(adapter);
88a268c1 3204 igb_power_down_link(adapter);
9d5c8243
AK		 3205 igb_free_all_rx_resources(adapter);
3206err_setup_rx:
3207 igb_free_all_tx_resources(adapter);
3208err_setup_tx:
3209 igb_reset(adapter);
749ab2cd
YZ		 3210 if (!resuming)
3211 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3212
3213 return err;
3214}
3215
46eafa59 3216int igb_open(struct net_device *netdev)
749ab2cd
YZ		 3217{
3218 return __igb_open(netdev, false);
3219}
3220
9d5c8243 3221/**
b980ac18
JK		 3222 * igb_close - Disables a network interface
3223 * @netdev: network interface device structure
9d5c8243 3224 *
b980ac18 3225 * Returns 0, this is not allowed to fail
9d5c8243 3226 *
b980ac18
JK		 3227 * The close entry point is called when an interface is de-activated
3228 * by the OS. The hardware is still under the driver's control, but
3229 * needs to be disabled. A global MAC reset is issued to stop the
3230 * hardware, and all transmit and receive resources are freed.
9d5c8243 3231 **/
749ab2cd 3232static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3233{
3234 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3235 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3236
3237 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3238
749ab2cd
YZ		 3239 if (!suspending)
3240 pm_runtime_get_sync(&pdev->dev);
3241
3242 igb_down(adapter);
9d5c8243
AK		 3243 igb_free_irq(adapter);
3244
3245 igb_free_all_tx_resources(adapter);
3246 igb_free_all_rx_resources(adapter);
3247
749ab2cd
YZ		 3248 if (!suspending)
3249 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3250 return 0;
3251}
3252
46eafa59 3253int igb_close(struct net_device *netdev)
749ab2cd
YZ		 3254{
3255 return __igb_close(netdev, false);
3256}
3257
9d5c8243 3258/**
b980ac18
JK		 3259 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3260 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3261 *
b980ac18 3262 * Return 0 on success, negative on failure
9d5c8243 3263 **/
80785298 3264int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3265{
59d71989 3266 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3267 int size;
3268
06034649 3269 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3270
3271 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3272 if (!tx_ring->tx_buffer_info)
9d5c8243 3273 goto err;
9d5c8243
AK		 3274
3275 /* round up to nearest 4K */
85e8d004 3276 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3277 tx_ring->size = ALIGN(tx_ring->size, 4096);
3278
5536d210
AD		 3279 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3280 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3281 if (!tx_ring->desc)
3282 goto err;
3283
9d5c8243
AK		 3284 tx_ring->next_to_use = 0;
3285 tx_ring->next_to_clean = 0;
81c2fc22 3286
9d5c8243
AK		 3287 return 0;
3288
3289err:
06034649 3290 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3291 tx_ring->tx_buffer_info = NULL;
3292 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3293 return -ENOMEM;
3294}
3295
3296/**
b980ac18
JK		 3297 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3298 * (Descriptors) for all queues
3299 * @adapter: board private structure
9d5c8243 3300 *
b980ac18 3301 * Return 0 on success, negative on failure
9d5c8243
AK		 3302 **/
3303static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3304{
439705e1 3305 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3306 int i, err = 0;
3307
3308 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3309 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3310 if (err) {
439705e1 3311 dev_err(&pdev->dev,
9d5c8243
AK		 3312 "Allocation for Tx Queue %u failed\n", i);
3313 for (i--; i >= 0; i--)
3025a446 3314 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3315 break;
3316 }
3317 }
3318
3319 return err;
3320}
3321
3322/**
b980ac18
JK		 3323 * igb_setup_tctl - configure the transmit control registers
3324 * @adapter: Board private structure
9d5c8243 3325 **/
d7ee5b3a 3326void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3327{
9d5c8243
AK		 3328 struct e1000_hw *hw = &adapter->hw;
3329 u32 tctl;
9d5c8243 3330
85b430b4
AD		 3331 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3332 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3333
3334 /* Program the Transmit Control Register */
9d5c8243
AK		 3335 tctl = rd32(E1000_TCTL);
3336 tctl &= ~E1000_TCTL_CT;
3337 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3338 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3339
3340 igb_config_collision_dist(hw);
3341
9d5c8243
AK		 3342 /* Enable transmits */
3343 tctl |= E1000_TCTL_EN;
3344
3345 wr32(E1000_TCTL, tctl);
3346}
3347
85b430b4 3348/**
b980ac18
JK		 3349 * igb_configure_tx_ring - Configure transmit ring after Reset
3350 * @adapter: board private structure
3351 * @ring: tx ring to configure
85b430b4 3352 *
b980ac18 3353 * Configure a transmit ring after a reset.
85b430b4 3354 **/
d7ee5b3a 3355void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3356 struct igb_ring *ring)
85b430b4
AD		 3357{
3358 struct e1000_hw *hw = &adapter->hw;
a74420e0 3359 u32 txdctl = 0;
85b430b4
AD		 3360 u64 tdba = ring->dma;
3361 int reg_idx = ring->reg_idx;
3362
3363 /* disable the queue */
a74420e0 3364 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3365 wrfl();
3366 mdelay(10);
3367
3368 wr32(E1000_TDLEN(reg_idx),
b980ac18 3369 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3370 wr32(E1000_TDBAL(reg_idx),
b980ac18 3371 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3372 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3373
fce99e34 3374 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3375 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3376 writel(0, ring->tail);
85b430b4
AD		 3377
3378 txdctl |= IGB_TX_PTHRESH;
3379 txdctl |= IGB_TX_HTHRESH << 8;
3380 txdctl |= IGB_TX_WTHRESH << 16;
3381
3382 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3383 wr32(E1000_TXDCTL(reg_idx), txdctl);
3384}
3385
3386/**
b980ac18
JK		 3387 * igb_configure_tx - Configure transmit Unit after Reset
3388 * @adapter: board private structure
85b430b4 3389 *
b980ac18 3390 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3391 **/
3392static void igb_configure_tx(struct igb_adapter *adapter)
3393{
3394 int i;
3395
3396 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3397 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3398}
3399
9d5c8243 3400/**
b980ac18
JK		 3401 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3402 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3403 *
b980ac18 3404 * Returns 0 on success, negative on failure
9d5c8243 3405 **/
80785298 3406int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3407{
59d71989 3408 struct device *dev = rx_ring->dev;
f33005a6 3409 int size;
9d5c8243 3410
06034649 3411 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3412
3413 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3414 if (!rx_ring->rx_buffer_info)
9d5c8243 3415 goto err;
9d5c8243 3416
9d5c8243 3417 /* Round up to nearest 4K */
f33005a6 3418 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3419 rx_ring->size = ALIGN(rx_ring->size, 4096);
3420
5536d210
AD		 3421 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3422 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3423 if (!rx_ring->desc)
3424 goto err;
3425
cbc8e55f 3426 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3427 rx_ring->next_to_clean = 0;
3428 rx_ring->next_to_use = 0;
9d5c8243 3429
9d5c8243
AK		 3430 return 0;
3431
3432err:
06034649
AD		 3433 vfree(rx_ring->rx_buffer_info);
3434 rx_ring->rx_buffer_info = NULL;
f33005a6 3435 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3436 return -ENOMEM;
3437}
3438
3439/**
b980ac18
JK		 3440 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3441 * (Descriptors) for all queues
3442 * @adapter: board private structure
9d5c8243 3443 *
b980ac18 3444 * Return 0 on success, negative on failure
9d5c8243
AK		 3445 **/
3446static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3447{
439705e1 3448 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3449 int i, err = 0;
3450
3451 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3452 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3453 if (err) {
439705e1 3454 dev_err(&pdev->dev,
9d5c8243
AK		 3455 "Allocation for Rx Queue %u failed\n", i);
3456 for (i--; i >= 0; i--)
3025a446 3457 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3458 break;
3459 }
3460 }
3461
3462 return err;
3463}
3464
06cf2666 3465/**
b980ac18
JK		 3466 * igb_setup_mrqc - configure the multiple receive queue control registers
3467 * @adapter: Board private structure
06cf2666
AD		 3468 **/
3469static void igb_setup_mrqc(struct igb_adapter *adapter)
3470{
3471 struct e1000_hw *hw = &adapter->hw;
3472 u32 mrqc, rxcsum;
ed12cc9a 3473 u32 j, num_rx_queues;
eb31f849 3474 u32 rss_key[10];
06cf2666 3475
eb31f849 3476 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3477 for (j = 0; j < 10; j++)
eb31f849 3478 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3479
a99955fc 3480 num_rx_queues = adapter->rss_queues;
06cf2666 3481
797fd4be 3482 switch (hw->mac.type) {
797fd4be
AD		 3483 case e1000_82576:
3484 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3485 if (adapter->vfs_allocated_count)
06cf2666 3486 num_rx_queues = 2;
797fd4be
AD		 3487 break;
3488 default:
3489 break;
06cf2666
AD		 3490 }
3491
ed12cc9a
LMV		 3492 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3493 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3494 adapter->rss_indir_tbl[j] =
3495 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3496 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3497 }
ed12cc9a 3498 igb_write_rss_indir_tbl(adapter);
06cf2666 3499
b980ac18 3500 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3501 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3502 * offloads as they are enabled by default
3503 */
3504 rxcsum = rd32(E1000_RXCSUM);
3505 rxcsum |= E1000_RXCSUM_PCSD;
3506
3507 if (adapter->hw.mac.type >= e1000_82576)
3508 /* Enable Receive Checksum Offload for SCTP */
3509 rxcsum |= E1000_RXCSUM_CRCOFL;
3510
3511 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3512 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3513
039454a8
AA		 3514 /* Generate RSS hash based on packet types, TCP/UDP
3515 * port numbers and/or IPv4/v6 src and dst addresses
3516 */
f96a8a0b
CW		 3517 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3518 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3519 E1000_MRQC_RSS_FIELD_IPV6 |
3520 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3521 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3522
039454a8
AA		 3523 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3524 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3525 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3526 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3527
06cf2666
AD		 3528 /* If VMDq is enabled then we set the appropriate mode for that, else
3529 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3530 * if we are only using one queue
3531 */
06cf2666
AD		 3532 if (adapter->vfs_allocated_count) {
3533 if (hw->mac.type > e1000_82575) {
3534 /* Set the default pool for the PF's first queue */
3535 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3536
06cf2666
AD		 3537 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3538 E1000_VT_CTL_DISABLE_DEF_POOL);
3539 vtctl |= adapter->vfs_allocated_count <<
3540 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3541 wr32(E1000_VT_CTL, vtctl);
3542 }
a99955fc 3543 if (adapter->rss_queues > 1)
c883de9f 3544 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
06cf2666 3545 else
f96a8a0b 3546 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3547 } else {
f96a8a0b 3548 if (hw->mac.type != e1000_i211)
c883de9f 3549 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
06cf2666
AD		 3550 }
3551 igb_vmm_control(adapter);
3552
06cf2666
AD		 3553 wr32(E1000_MRQC, mrqc);
3554}
3555
9d5c8243 3556/**
b980ac18
JK		 3557 * igb_setup_rctl - configure the receive control registers
3558 * @adapter: Board private structure
9d5c8243 3559 **/
d7ee5b3a 3560void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3561{
3562 struct e1000_hw *hw = &adapter->hw;
3563 u32 rctl;
9d5c8243
AK		 3564
3565 rctl = rd32(E1000_RCTL);
3566
3567 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3568 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3569
69d728ba 3570 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3571 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3572
b980ac18 3573 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3574 * redirection as it did with e1000. Newer features require
3575 * that the HW strips the CRC.
73cd78f1 3576 */
87cb7e8c 3577 rctl |= E1000_RCTL_SECRC;
9d5c8243 3578
559e9c49 3579 /* disable store bad packets and clear size bits. */
ec54d7d6 3580 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3581
45693bcb 3582 /* enable LPE to allow for reception of jumbo frames */
6ec43fe6 3583 rctl |= E1000_RCTL_LPE;
9d5c8243 3584
952f72a8
AD		 3585 /* disable queue 0 to prevent tail write w/o re-config */
3586 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3587
e1739522
AD		 3588 /* Attention!!! For SR-IOV PF driver operations you must enable
3589 * queue drop for all VF and PF queues to prevent head of line blocking
3590 * if an un-trusted VF does not provide descriptors to hardware.
3591 */
3592 if (adapter->vfs_allocated_count) {
e1739522
AD		 3593 /* set all queue drop enable bits */
3594 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3595 }
3596
89eaefb6
BG		 3597 /* This is useful for sniffing bad packets. */
3598 if (adapter->netdev->features & NETIF_F_RXALL) {
3599 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3600 * in e1000e_set_rx_mode
3601 */
89eaefb6
BG		 3602 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3603 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3604 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3605
16903caa 3606 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
89eaefb6
BG		 3607 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3608 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3609 * and that breaks VLANs.
3610 */
3611 }
3612
9d5c8243
AK		 3613 wr32(E1000_RCTL, rctl);
3614}
3615
7d5753f0 3616static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3617 int vfn)
7d5753f0
AD		 3618{
3619 struct e1000_hw *hw = &adapter->hw;
3620 u32 vmolr;
3621
d3836f8e
AD		 3622 if (size > MAX_JUMBO_FRAME_SIZE)
3623 size = MAX_JUMBO_FRAME_SIZE;
7d5753f0
AD		 3624
3625 vmolr = rd32(E1000_VMOLR(vfn));
3626 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3627 vmolr |= size | E1000_VMOLR_LPE;
3628 wr32(E1000_VMOLR(vfn), vmolr);
3629
3630 return 0;
3631}
3632
030f9f52
CV		 3633static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
3634 int vfn, bool enable)
e1739522 3635{
e1739522 3636 struct e1000_hw *hw = &adapter->hw;
030f9f52 3637 u32 val, reg;
e1739522 3638
030f9f52
CV		 3639 if (hw->mac.type < e1000_82576)
3640 return;
e1739522 3641
030f9f52
CV		 3642 if (hw->mac.type == e1000_i350)
3643 reg = E1000_DVMOLR(vfn);
3644 else
3645 reg = E1000_VMOLR(vfn);
3646
3647 val = rd32(reg);
3648 if (enable)
3649 val |= E1000_VMOLR_STRVLAN;
3650 else
3651 val &= ~(E1000_VMOLR_STRVLAN);
3652 wr32(reg, val);
e1739522
AD		 3653}
3654
8151d294
WM		 3655static inline void igb_set_vmolr(struct igb_adapter *adapter,
3656 int vfn, bool aupe)
7d5753f0
AD		 3657{
3658 struct e1000_hw *hw = &adapter->hw;
3659 u32 vmolr;
3660
b980ac18 3661 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3662 * we should exit and do nothing
3663 */
3664 if (hw->mac.type < e1000_82576)
3665 return;
3666
3667 vmolr = rd32(E1000_VMOLR(vfn));
8151d294 3668 if (aupe)
b980ac18 3669 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3670 else
3671 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3672
3673 /* clear all bits that might not be set */
3674 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3675
a99955fc 3676 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3677 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3678 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3679 * multicast packets
3680 */
3681 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3682 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3683
3684 wr32(E1000_VMOLR(vfn), vmolr);
3685}
3686
85b430b4 3687/**
b980ac18
JK		 3688 * igb_configure_rx_ring - Configure a receive ring after Reset
3689 * @adapter: board private structure
3690 * @ring: receive ring to be configured
85b430b4 3691 *
b980ac18 3692 * Configure the Rx unit of the MAC after a reset.
85b430b4 3693 **/
d7ee5b3a 3694void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3695 struct igb_ring *ring)
85b430b4
AD		 3696{
3697 struct e1000_hw *hw = &adapter->hw;
3698 u64 rdba = ring->dma;
3699 int reg_idx = ring->reg_idx;
a74420e0 3700 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3701
3702 /* disable the queue */
a74420e0 3703 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3704
3705 /* Set DMA base address registers */
3706 wr32(E1000_RDBAL(reg_idx),
3707 rdba & 0x00000000ffffffffULL);
3708 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3709 wr32(E1000_RDLEN(reg_idx),
b980ac18 3710 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3711
3712 /* initialize head and tail */
fce99e34 3713 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3714 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3715 writel(0, ring->tail);
85b430b4 3716
952f72a8 3717 /* set descriptor configuration */
44390ca6 3718 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3719 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3720 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3721 if (hw->mac.type >= e1000_82580)
757b77e2 3722 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3723 /* Only set Drop Enable if we are supporting multiple queues */
3724 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3725 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3726
3727 wr32(E1000_SRRCTL(reg_idx), srrctl);
3728
7d5753f0 3729 /* set filtering for VMDQ pools */
8151d294 3730 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3731
85b430b4
AD		 3732 rxdctl |= IGB_RX_PTHRESH;
3733 rxdctl |= IGB_RX_HTHRESH << 8;
3734 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3735
3736 /* enable receive descriptor fetching */
3737 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3738 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3739}
3740
9d5c8243 3741/**
b980ac18
JK		 3742 * igb_configure_rx - Configure receive Unit after Reset
3743 * @adapter: board private structure
9d5c8243 3744 *
b980ac18 3745 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3746 **/
3747static void igb_configure_rx(struct igb_adapter *adapter)
3748{
9107584e 3749 int i;
9d5c8243 3750
26ad9178
AD		 3751 /* set the correct pool for the PF default MAC address in entry 0 */
3752 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3753 adapter->vfs_allocated_count);
26ad9178 3754
06cf2666 3755 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3756 * the Base and Length of the Rx Descriptor Ring
3757 */
f9d40f6a
AD		 3758 for (i = 0; i < adapter->num_rx_queues; i++)
3759 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3760}
3761
3762/**
b980ac18
JK		 3763 * igb_free_tx_resources - Free Tx Resources per Queue
3764 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3765 *
b980ac18 3766 * Free all transmit software resources
9d5c8243 3767 **/
68fd9910 3768void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3769{
3b644cf6 3770 igb_clean_tx_ring(tx_ring);
9d5c8243 3771
06034649
AD		 3772 vfree(tx_ring->tx_buffer_info);
3773 tx_ring->tx_buffer_info = NULL;
9d5c8243 3774
439705e1
AD		 3775 /* if not set, then don't free */
3776 if (!tx_ring->desc)
3777 return;
3778
59d71989
AD		 3779 dma_free_coherent(tx_ring->dev, tx_ring->size,
3780 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3781
3782 tx_ring->desc = NULL;
3783}
3784
3785/**
b980ac18
JK		 3786 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3787 * @adapter: board private structure
9d5c8243 3788 *
b980ac18 3789 * Free all transmit software resources
9d5c8243
AK		 3790 **/
3791static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3792{
3793 int i;
3794
3795 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3796 if (adapter->tx_ring[i])
3797 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3798}
3799
ebe42d16
AD		 3800void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3801 struct igb_tx_buffer *tx_buffer)
3802{
3803 if (tx_buffer->skb) {
3804 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3805 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3806 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3807 dma_unmap_addr(tx_buffer, dma),
3808 dma_unmap_len(tx_buffer, len),
ebe42d16 3809 DMA_TO_DEVICE);
c9f14bf3 3810 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3811 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3812 dma_unmap_addr(tx_buffer, dma),
3813 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3814 DMA_TO_DEVICE);
3815 }
3816 tx_buffer->next_to_watch = NULL;
3817 tx_buffer->skb = NULL;
c9f14bf3 3818 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3819 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3820}
3821
3822/**
b980ac18
JK		 3823 * igb_clean_tx_ring - Free Tx Buffers
3824 * @tx_ring: ring to be cleaned
9d5c8243 3825 **/
3b644cf6 3826static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3827{
06034649 3828 struct igb_tx_buffer *buffer_info;
9d5c8243 3829 unsigned long size;
6ad4edfc 3830 u16 i;
9d5c8243 3831
06034649 3832 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3833 return;
3834 /* Free all the Tx ring sk_buffs */
3835
3836 for (i = 0; i < tx_ring->count; i++) {
06034649 3837 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3838 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3839 }
3840
dad8a3b3
JF		 3841 netdev_tx_reset_queue(txring_txq(tx_ring));
3842
06034649
AD		 3843 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3844 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3845
3846 /* Zero out the descriptor ring */
9d5c8243
AK		 3847 memset(tx_ring->desc, 0, tx_ring->size);
3848
3849 tx_ring->next_to_use = 0;
3850 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3851}
3852
3853/**
b980ac18
JK		 3854 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3855 * @adapter: board private structure
9d5c8243
AK		 3856 **/
3857static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3858{
3859 int i;
3860
3861 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3862 if (adapter->tx_ring[i])
3863 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3864}
3865
3866/**
b980ac18
JK		 3867 * igb_free_rx_resources - Free Rx Resources
3868 * @rx_ring: ring to clean the resources from
9d5c8243 3869 *
b980ac18 3870 * Free all receive software resources
9d5c8243 3871 **/
68fd9910 3872void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3873{
3b644cf6 3874 igb_clean_rx_ring(rx_ring);
9d5c8243 3875
06034649
AD		 3876 vfree(rx_ring->rx_buffer_info);
3877 rx_ring->rx_buffer_info = NULL;
9d5c8243 3878
439705e1
AD		 3879 /* if not set, then don't free */
3880 if (!rx_ring->desc)
3881 return;
3882
59d71989
AD		 3883 dma_free_coherent(rx_ring->dev, rx_ring->size,
3884 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3885
3886 rx_ring->desc = NULL;
3887}
3888
3889/**
b980ac18
JK		 3890 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3891 * @adapter: board private structure
9d5c8243 3892 *
b980ac18 3893 * Free all receive software resources
9d5c8243
AK		 3894 **/
3895static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3896{
3897 int i;
3898
3899 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3900 if (adapter->rx_ring[i])
3901 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3902}
3903
3904/**
b980ac18
JK		 3905 * igb_clean_rx_ring - Free Rx Buffers per Queue
3906 * @rx_ring: ring to free buffers from
9d5c8243 3907 **/
3b644cf6 3908static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3909{
9d5c8243 3910 unsigned long size;
c023cd88 3911 u16 i;
9d5c8243 3912
1a1c225b
AD		 3913 if (rx_ring->skb)
3914 dev_kfree_skb(rx_ring->skb);
3915 rx_ring->skb = NULL;
3916
06034649 3917 if (!rx_ring->rx_buffer_info)
9d5c8243 3918 return;
439705e1 3919
9d5c8243
AK		 3920 /* Free all the Rx ring sk_buffs */
3921 for (i = 0; i < rx_ring->count; i++) {
06034649 3922 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3923
cbc8e55f
AD		 3924 if (!buffer_info->page)
3925 continue;
3926
3927 dma_unmap_page(rx_ring->dev,
3928 buffer_info->dma,
3929 PAGE_SIZE,
3930 DMA_FROM_DEVICE);
3931 __free_page(buffer_info->page);
3932
1a1c225b 3933 buffer_info->page = NULL;
9d5c8243
AK		 3934 }
3935
06034649
AD		 3936 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3937 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3938
3939 /* Zero out the descriptor ring */
3940 memset(rx_ring->desc, 0, rx_ring->size);
3941
cbc8e55f 3942 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3943 rx_ring->next_to_clean = 0;
3944 rx_ring->next_to_use = 0;
9d5c8243
AK		 3945}
3946
3947/**
b980ac18
JK		 3948 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3949 * @adapter: board private structure
9d5c8243
AK		 3950 **/
3951static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3952{
3953 int i;
3954
3955 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3956 if (adapter->rx_ring[i])
3957 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3958}
3959
3960/**
b980ac18
JK		 3961 * igb_set_mac - Change the Ethernet Address of the NIC
3962 * @netdev: network interface device structure
3963 * @p: pointer to an address structure
9d5c8243 3964 *
b980ac18 3965 * Returns 0 on success, negative on failure
9d5c8243
AK		 3966 **/
3967static int igb_set_mac(struct net_device *netdev, void *p)
3968{
3969 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3970 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3971 struct sockaddr *addr = p;
3972
3973 if (!is_valid_ether_addr(addr->sa_data))
3974 return -EADDRNOTAVAIL;
3975
3976 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3977 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3978
26ad9178
AD		 3979 /* set the correct pool for the new PF MAC address in entry 0 */
3980 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3981 adapter->vfs_allocated_count);
e1739522 3982
9d5c8243
AK		 3983 return 0;
3984}
3985
3986/**
b980ac18
JK		 3987 * igb_write_mc_addr_list - write multicast addresses to MTA
3988 * @netdev: network interface device structure
9d5c8243 3989 *
b980ac18
JK		 3990 * Writes multicast address list to the MTA hash table.
3991 * Returns: -ENOMEM on failure
3992 * 0 on no addresses written
3993 * X on writing X addresses to MTA
9d5c8243 3994 **/
68d480c4 3995static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3996{
3997 struct igb_adapter *adapter = netdev_priv(netdev);
3998 struct e1000_hw *hw = &adapter->hw;
22bedad3 3999 struct netdev_hw_addr *ha;
68d480c4 4000 u8 *mta_list;
9d5c8243
AK		 4001 int i;
4002
4cd24eaf 4003 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 4004 /* nothing to program, so clear mc list */
4005 igb_update_mc_addr_list(hw, NULL, 0);
4006 igb_restore_vf_multicasts(adapter);
4007 return 0;
4008 }
9d5c8243 4009
4cd24eaf 4010 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 4011 if (!mta_list)
4012 return -ENOMEM;
ff41f8dc 4013
68d480c4 4014 /* The shared function expects a packed array of only addresses. */
48e2f183 4015 i = 0;
22bedad3
JP		 4016 netdev_for_each_mc_addr(ha, netdev)
4017 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 4018
68d480c4
AD		 4019 igb_update_mc_addr_list(hw, mta_list, i);
4020 kfree(mta_list);
4021
4cd24eaf 4022 return netdev_mc_count(netdev);
68d480c4
AD		 4023}
4024
4025/**
b980ac18
JK		 4026 * igb_write_uc_addr_list - write unicast addresses to RAR table
4027 * @netdev: network interface device structure
68d480c4 4028 *
b980ac18
JK		 4029 * Writes unicast address list to the RAR table.
4030 * Returns: -ENOMEM on failure/insufficient address space
4031 * 0 on no addresses written
4032 * X on writing X addresses to the RAR table
68d480c4
AD		 4033 **/
4034static int igb_write_uc_addr_list(struct net_device *netdev)
4035{
4036 struct igb_adapter *adapter = netdev_priv(netdev);
4037 struct e1000_hw *hw = &adapter->hw;
4038 unsigned int vfn = adapter->vfs_allocated_count;
4039 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
4040 int count = 0;
4041
4042 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 4043 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 4044 return -ENOMEM;
9d5c8243 4045
32e7bfc4 4046 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 4047 struct netdev_hw_addr *ha;
32e7bfc4
JP		 4048
4049 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 4050 if (!rar_entries)
4051 break;
26ad9178 4052 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 4053 rar_entries--,
4054 vfn);
68d480c4 4055 count++;
ff41f8dc
AD		 4056 }
4057 }
4058 /* write the addresses in reverse order to avoid write combining */
4059 for (; rar_entries > 0 ; rar_entries--) {
4060 wr32(E1000_RAH(rar_entries), 0);
4061 wr32(E1000_RAL(rar_entries), 0);
4062 }
4063 wrfl();
4064
68d480c4
AD		 4065 return count;
4066}
4067
16903caa
AD		 4068static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4069{
4070 struct e1000_hw *hw = &adapter->hw;
4071 u32 i, pf_id;
4072
4073 switch (hw->mac.type) {
4074 case e1000_i210:
4075 case e1000_i211:
4076 case e1000_i350:
4077 /* VLAN filtering needed for VLAN prio filter */
4078 if (adapter->netdev->features & NETIF_F_NTUPLE)
4079 break;
4080 /* fall through */
4081 case e1000_82576:
4082 case e1000_82580:
4083 case e1000_i354:
4084 /* VLAN filtering needed for pool filtering */
4085 if (adapter->vfs_allocated_count)
4086 break;
4087 /* fall through */
4088 default:
4089 return 1;
4090 }
4091
4092 /* We are already in VLAN promisc, nothing to do */
4093 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4094 return 0;
4095
4096 if (!adapter->vfs_allocated_count)
4097 goto set_vfta;
4098
4099 /* Add PF to all active pools */
4100 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4101
4102 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4103 u32 vlvf = rd32(E1000_VLVF(i));
4104
a51d8c21 4105 vlvf |= BIT(pf_id);
16903caa
AD		 4106 wr32(E1000_VLVF(i), vlvf);
4107 }
4108
4109set_vfta:
4110 /* Set all bits in the VLAN filter table array */
4111 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4112 hw->mac.ops.write_vfta(hw, i, ~0U);
4113
4114 /* Set flag so we don't redo unnecessary work */
4115 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4116
4117 return 0;
4118}
4119
4120#define VFTA_BLOCK_SIZE 8
4121static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4122{
4123 struct e1000_hw *hw = &adapter->hw;
4124 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4125 u32 vid_start = vfta_offset * 32;
4126 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4127 u32 i, vid, word, bits, pf_id;
4128
4129 /* guarantee that we don't scrub out management VLAN */
4130 vid = adapter->mng_vlan_id;
4131 if (vid >= vid_start && vid < vid_end)
a51d8c21 4132 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16903caa
AD		 4133
4134 if (!adapter->vfs_allocated_count)
4135 goto set_vfta;
4136
4137 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4138
4139 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4140 u32 vlvf = rd32(E1000_VLVF(i));
4141
4142 /* pull VLAN ID from VLVF */
4143 vid = vlvf & VLAN_VID_MASK;
4144
4145 /* only concern ourselves with a certain range */
4146 if (vid < vid_start || vid >= vid_end)
4147 continue;
4148
4149 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4150 /* record VLAN ID in VFTA */
a51d8c21 4151 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16903caa
AD		 4152
4153 /* if PF is part of this then continue */
4154 if (test_bit(vid, adapter->active_vlans))
4155 continue;
4156 }
4157
4158 /* remove PF from the pool */
a51d8c21 4159 bits = ~BIT(pf_id);
16903caa
AD		 4160 bits &= rd32(E1000_VLVF(i));
4161 wr32(E1000_VLVF(i), bits);
4162 }
4163
4164set_vfta:
4165 /* extract values from active_vlans and write back to VFTA */
4166 for (i = VFTA_BLOCK_SIZE; i--;) {
4167 vid = (vfta_offset + i) * 32;
4168 word = vid / BITS_PER_LONG;
4169 bits = vid % BITS_PER_LONG;
4170
4171 vfta[i] |= adapter->active_vlans[word] >> bits;
4172
4173 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4174 }
4175}
4176
4177static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4178{
4179 u32 i;
4180
4181 /* We are not in VLAN promisc, nothing to do */
4182 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4183 return;
4184
4185 /* Set flag so we don't redo unnecessary work */
4186 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4187
4188 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4189 igb_scrub_vfta(adapter, i);
4190}
4191
68d480c4 4192/**
b980ac18
JK		 4193 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4194 * @netdev: network interface device structure
68d480c4 4195 *
b980ac18
JK		 4196 * The set_rx_mode entry point is called whenever the unicast or multicast
4197 * address lists or the network interface flags are updated. This routine is
4198 * responsible for configuring the hardware for proper unicast, multicast,
4199 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4200 **/
4201static void igb_set_rx_mode(struct net_device *netdev)
4202{
4203 struct igb_adapter *adapter = netdev_priv(netdev);
4204 struct e1000_hw *hw = &adapter->hw;
4205 unsigned int vfn = adapter->vfs_allocated_count;
16903caa 4206 u32 rctl = 0, vmolr = 0;
68d480c4
AD		 4207 int count;
4208
4209 /* Check for Promiscuous and All Multicast modes */
68d480c4 4210 if (netdev->flags & IFF_PROMISC) {
16903caa 4211 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
bf456abb
AD		 4212 vmolr |= E1000_VMOLR_MPME;
4213
4214 /* enable use of UTA filter to force packets to default pool */
4215 if (hw->mac.type == e1000_82576)
4216 vmolr |= E1000_VMOLR_ROPE;
68d480c4
AD		 4217 } else {
4218 if (netdev->flags & IFF_ALLMULTI) {
4219 rctl |= E1000_RCTL_MPE;
4220 vmolr |= E1000_VMOLR_MPME;
4221 } else {
b980ac18 4222 /* Write addresses to the MTA, if the attempt fails
25985edc 4223 * then we should just turn on promiscuous mode so
68d480c4
AD		 4224 * that we can at least receive multicast traffic
4225 */
4226 count = igb_write_mc_addr_list(netdev);
4227 if (count < 0) {
4228 rctl |= E1000_RCTL_MPE;
4229 vmolr |= E1000_VMOLR_MPME;
4230 } else if (count) {
4231 vmolr |= E1000_VMOLR_ROMPE;
4232 }
4233 }
28fc06f5 4234 }
268f9d33
AD		 4235
4236 /* Write addresses to available RAR registers, if there is not
4237 * sufficient space to store all the addresses then enable
4238 * unicast promiscuous mode
4239 */
4240 count = igb_write_uc_addr_list(netdev);
4241 if (count < 0) {
4242 rctl |= E1000_RCTL_UPE;
4243 vmolr |= E1000_VMOLR_ROPE;
28fc06f5 4244 }
16903caa
AD		 4245
4246 /* enable VLAN filtering by default */
4247 rctl |= E1000_RCTL_VFE;
4248
4249 /* disable VLAN filtering for modes that require it */
4250 if ((netdev->flags & IFF_PROMISC) ||
4251 (netdev->features & NETIF_F_RXALL)) {
4252 /* if we fail to set all rules then just clear VFE */
4253 if (igb_vlan_promisc_enable(adapter))
4254 rctl &= ~E1000_RCTL_VFE;
4255 } else {
4256 igb_vlan_promisc_disable(adapter);
4257 }
4258
4259 /* update state of unicast, multicast, and VLAN filtering modes */
4260 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4261 E1000_RCTL_VFE);
68d480c4 4262 wr32(E1000_RCTL, rctl);
28fc06f5 4263
b980ac18 4264 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4265 * the VMOLR to enable the appropriate modes. Without this workaround
4266 * we will have issues with VLAN tag stripping not being done for frames
4267 * that are only arriving because we are the default pool
4268 */
f96a8a0b 4269 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4270 return;
9d5c8243 4271
bf456abb
AD		 4272 /* set UTA to appropriate mode */
4273 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4274
68d480c4 4275 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4276 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
45693bcb
AD		 4277
4278 /* enable Rx jumbo frames, no need for restriction */
4279 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4280 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4281
68d480c4 4282 wr32(E1000_VMOLR(vfn), vmolr);
45693bcb
AD		 4283 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4284
28fc06f5 4285 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4286}
4287
13800469
GR		 4288static void igb_check_wvbr(struct igb_adapter *adapter)
4289{
4290 struct e1000_hw *hw = &adapter->hw;
4291 u32 wvbr = 0;
4292
4293 switch (hw->mac.type) {
4294 case e1000_82576:
4295 case e1000_i350:
81ad807b
CW		 4296 wvbr = rd32(E1000_WVBR);
4297 if (!wvbr)
13800469
GR		 4298 return;
4299 break;
4300 default:
4301 break;
4302 }
4303
4304 adapter->wvbr |= wvbr;
4305}
4306
4307#define IGB_STAGGERED_QUEUE_OFFSET 8
4308
4309static void igb_spoof_check(struct igb_adapter *adapter)
4310{
4311 int j;
4312
4313 if (!adapter->wvbr)
4314 return;
4315
9005df38 4316 for (j = 0; j < adapter->vfs_allocated_count; j++) {
a51d8c21
JK		 4317 if (adapter->wvbr & BIT(j) ||
4318 adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
13800469
GR		 4319 dev_warn(&adapter->pdev->dev,
4320 "Spoof event(s) detected on VF %d\n", j);
4321 adapter->wvbr &=
a51d8c21
JK		 4322 ~(BIT(j) |
4323 BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
13800469
GR		 4324 }
4325 }
4326}
4327
9d5c8243 4328/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4329 * the phy
4330 */
9d5c8243
AK		 4331static void igb_update_phy_info(unsigned long data)
4332{
4333 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4334 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4335}
4336
4d6b725e 4337/**
b980ac18
JK		 4338 * igb_has_link - check shared code for link and determine up/down
4339 * @adapter: pointer to driver private info
4d6b725e 4340 **/
3145535a 4341bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4342{
4343 struct e1000_hw *hw = &adapter->hw;
4344 bool link_active = false;
4d6b725e
AD		 4345
4346 /* get_link_status is set on LSC (link status) interrupt or
4347 * rx sequence error interrupt. get_link_status will stay
4348 * false until the e1000_check_for_link establishes link
4349 * for copper adapters ONLY
4350 */
4351 switch (hw->phy.media_type) {
4352 case e1000_media_type_copper:
e5c3370f
AA		 4353 if (!hw->mac.get_link_status)
4354 return true;
4d6b725e 4355 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4356 hw->mac.ops.check_for_link(hw);
4357 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4358 break;
4359 default:
4360 case e1000_media_type_unknown:
4361 break;
4362 }
4363
aa9b8cc4
AA		 4364 if (((hw->mac.type == e1000_i210) ||
4365 (hw->mac.type == e1000_i211)) &&
4366 (hw->phy.id == I210_I_PHY_ID)) {
4367 if (!netif_carrier_ok(adapter->netdev)) {
4368 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4369 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4370 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4371 adapter->link_check_timeout = jiffies;
4372 }
4373 }
4374
4d6b725e
AD		 4375 return link_active;
4376}
4377
563988dc
SA		 4378static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4379{
4380 bool ret = false;
4381 u32 ctrl_ext, thstat;
4382
f96a8a0b 4383 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4384 if (hw->mac.type == e1000_i350) {
4385 thstat = rd32(E1000_THSTAT);
4386 ctrl_ext = rd32(E1000_CTRL_EXT);
4387
4388 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4389 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4390 ret = !!(thstat & event);
563988dc
SA		 4391 }
4392
4393 return ret;
4394}
4395
1516f0a6
CW		 4396/**
4397 * igb_check_lvmmc - check for malformed packets received
4398 * and indicated in LVMMC register
4399 * @adapter: pointer to adapter
4400 **/
4401static void igb_check_lvmmc(struct igb_adapter *adapter)
4402{
4403 struct e1000_hw *hw = &adapter->hw;
4404 u32 lvmmc;
4405
4406 lvmmc = rd32(E1000_LVMMC);
4407 if (lvmmc) {
4408 if (unlikely(net_ratelimit())) {
4409 netdev_warn(adapter->netdev,
4410 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4411 lvmmc);
4412 }
4413 }
4414}
4415
9d5c8243 4416/**
b980ac18
JK		 4417 * igb_watchdog - Timer Call-back
4418 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4419 **/
4420static void igb_watchdog(unsigned long data)
4421{
4422 struct igb_adapter *adapter = (struct igb_adapter *)data;
4423 /* Do the rest outside of interrupt context */
4424 schedule_work(&adapter->watchdog_task);
4425}
4426
4427static void igb_watchdog_task(struct work_struct *work)
4428{
4429 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4430 struct igb_adapter,
4431 watchdog_task);
9d5c8243 4432 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4433 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4434 struct net_device *netdev = adapter->netdev;
563988dc 4435 u32 link;
7a6ea550 4436 int i;
56cec249 4437 u32 connsw;
b72f3f72 4438 u16 phy_data, retry_count = 20;
9d5c8243 4439
4d6b725e 4440 link = igb_has_link(adapter);
aa9b8cc4
AA		 4441
4442 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4443 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4444 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4445 else
4446 link = false;
4447 }
4448
56cec249
CW		 4449 /* Force link down if we have fiber to swap to */
4450 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4451 if (hw->phy.media_type == e1000_media_type_copper) {
4452 connsw = rd32(E1000_CONNSW);
4453 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4454 link = 0;
4455 }
4456 }
9d5c8243 4457 if (link) {
2bdfc4e2
CW		 4458 /* Perform a reset if the media type changed. */
4459 if (hw->dev_spec._82575.media_changed) {
4460 hw->dev_spec._82575.media_changed = false;
4461 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4462 igb_reset(adapter);
4463 }
749ab2cd
YZ		 4464 /* Cancel scheduled suspend requests. */
4465 pm_runtime_resume(netdev->dev.parent);
4466
9d5c8243
AK		 4467 if (!netif_carrier_ok(netdev)) {
4468 u32 ctrl;
9005df38 4469
330a6d6a 4470 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4471 &adapter->link_speed,
4472 &adapter->link_duplex);
9d5c8243
AK		 4473
4474 ctrl = rd32(E1000_CTRL);
527d47c1 4475 /* Links status message must follow this format */
c75c4edf
CW		 4476 netdev_info(netdev,
4477 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4478 netdev->name,
4479 adapter->link_speed,
4480 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4481 "Full" : "Half",
4482 (ctrl & E1000_CTRL_TFCE) &&
4483 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4484 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4485 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4486
f4c01e96
CW		 4487 /* disable EEE if enabled */
4488 if ((adapter->flags & IGB_FLAG_EEE) &&
4489 (adapter->link_duplex == HALF_DUPLEX)) {
4490 dev_info(&adapter->pdev->dev,
4491 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4492 adapter->hw.dev_spec._82575.eee_disable = true;
4493 adapter->flags &= ~IGB_FLAG_EEE;
4494 }
4495
c0ba4778
KS		 4496 /* check if SmartSpeed worked */
4497 igb_check_downshift(hw);
4498 if (phy->speed_downgraded)
4499 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4500
563988dc 4501 /* check for thermal sensor event */
876d2d6f 4502 if (igb_thermal_sensor_event(hw,
d34a15ab 4503 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4504 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4505
d07f3e37 4506 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4507 adapter->tx_timeout_factor = 1;
4508 switch (adapter->link_speed) {
4509 case SPEED_10:
9d5c8243
AK		 4510 adapter->tx_timeout_factor = 14;
4511 break;
4512 case SPEED_100:
9d5c8243
AK		 4513 /* maybe add some timeout factor ? */
4514 break;
4515 }
4516
b72f3f72
TU		 4517 if (adapter->link_speed != SPEED_1000)
4518 goto no_wait;
4519
4520 /* wait for Remote receiver status OK */
4521retry_read_status:
4522 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
4523 &phy_data)) {
4524 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4525 retry_count) {
4526 msleep(100);
4527 retry_count--;
4528 goto retry_read_status;
4529 } else if (!retry_count) {
4530 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
4531 }
4532 } else {
4533 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
4534 }
4535no_wait:
9d5c8243 4536 netif_carrier_on(netdev);
9d5c8243 4537
4ae196df 4538 igb_ping_all_vfs(adapter);
17dc566c 4539 igb_check_vf_rate_limit(adapter);
4ae196df 4540
4b1a9877 4541 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4542 if (!test_bit(__IGB_DOWN, &adapter->state))
4543 mod_timer(&adapter->phy_info_timer,
4544 round_jiffies(jiffies + 2 * HZ));
4545 }
4546 } else {
4547 if (netif_carrier_ok(netdev)) {
4548 adapter->link_speed = 0;
4549 adapter->link_duplex = 0;
563988dc
SA		 4550
4551 /* check for thermal sensor event */
876d2d6f
JK		 4552 if (igb_thermal_sensor_event(hw,
4553 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4554 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4555 }
563988dc 4556
527d47c1 4557 /* Links status message must follow this format */
c75c4edf 4558 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4559 netdev->name);
9d5c8243 4560 netif_carrier_off(netdev);
4b1a9877 4561
4ae196df
AD		 4562 igb_ping_all_vfs(adapter);
4563
4b1a9877 4564 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4565 if (!test_bit(__IGB_DOWN, &adapter->state))
4566 mod_timer(&adapter->phy_info_timer,
4567 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4568
56cec249
CW		 4569 /* link is down, time to check for alternate media */
4570 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4571 igb_check_swap_media(adapter);
4572 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4573 schedule_work(&adapter->reset_task);
4574 /* return immediately */
4575 return;
4576 }
4577 }
749ab2cd
YZ		 4578 pm_schedule_suspend(netdev->dev.parent,
4579 MSEC_PER_SEC * 5);
56cec249
CW		 4580
4581 /* also check for alternate media here */
4582 } else if (!netif_carrier_ok(netdev) &&
4583 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4584 igb_check_swap_media(adapter);
4585 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4586 schedule_work(&adapter->reset_task);
4587 /* return immediately */
4588 return;
4589 }
9d5c8243
AK		 4590 }
4591 }
4592
12dcd86b
ED		 4593 spin_lock(&adapter->stats64_lock);
4594 igb_update_stats(adapter, &adapter->stats64);
4595 spin_unlock(&adapter->stats64_lock);
9d5c8243 4596
dbabb065 4597 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4598 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4599 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4600 /* We've lost link, so the controller stops DMA,
4601 * but we've got queued Tx work that's never going
4602 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4603 * (Do the reset outside of interrupt context).
4604 */
dbabb065
AD		 4605 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4606 adapter->tx_timeout_count++;
4607 schedule_work(&adapter->reset_task);
4608 /* return immediately since reset is imminent */
4609 return;
4610 }
9d5c8243 4611 }
9d5c8243 4612
dbabb065 4613 /* Force detection of hung controller every watchdog period */
6d095fa8 4614 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4615 }
f7ba205e 4616
b980ac18 4617 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4618 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4619 u32 eics = 0;
9005df38 4620
0d1ae7f4
AD		 4621 for (i = 0; i < adapter->num_q_vectors; i++)
4622 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4623 wr32(E1000_EICS, eics);
4624 } else {
4625 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4626 }
9d5c8243 4627
13800469 4628 igb_spoof_check(adapter);
fc580751 4629 igb_ptp_rx_hang(adapter);
13800469 4630
1516f0a6
CW		 4631 /* Check LVMMC register on i350/i354 only */
4632 if ((adapter->hw.mac.type == e1000_i350) ||
4633 (adapter->hw.mac.type == e1000_i354))
4634 igb_check_lvmmc(adapter);
4635
9d5c8243 4636 /* Reset the timer */
aa9b8cc4
AA		 4637 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4638 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4639 mod_timer(&adapter->watchdog_timer,
4640 round_jiffies(jiffies + HZ));
4641 else
4642 mod_timer(&adapter->watchdog_timer,
4643 round_jiffies(jiffies + 2 * HZ));
4644 }
9d5c8243
AK		 4645}
4646
4647enum latency_range {
4648 lowest_latency = 0,
4649 low_latency = 1,
4650 bulk_latency = 2,
4651 latency_invalid = 255
4652};
4653
6eb5a7f1 4654/**
b980ac18
JK		 4655 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4656 * @q_vector: pointer to q_vector
6eb5a7f1 4657 *
b980ac18
JK		 4658 * Stores a new ITR value based on strictly on packet size. This
4659 * algorithm is less sophisticated than that used in igb_update_itr,
4660 * due to the difficulty of synchronizing statistics across multiple
4661 * receive rings. The divisors and thresholds used by this function
4662 * were determined based on theoretical maximum wire speed and testing
4663 * data, in order to minimize response time while increasing bulk
4664 * throughput.
406d4965 4665 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4666 * NOTE: This function is called only when operating in a multiqueue
4667 * receive environment.
6eb5a7f1 4668 **/
047e0030 4669static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4670{
047e0030 4671 int new_val = q_vector->itr_val;
6eb5a7f1 4672 int avg_wire_size = 0;
047e0030 4673 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4674 unsigned int packets;
9d5c8243 4675
6eb5a7f1
AD		 4676 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4677 * ints/sec - ITR timer value of 120 ticks.
4678 */
4679 if (adapter->link_speed != SPEED_1000) {
0ba82994 4680 new_val = IGB_4K_ITR;
6eb5a7f1 4681 goto set_itr_val;
9d5c8243 4682 }
047e0030 4683
0ba82994
AD		 4684 packets = q_vector->rx.total_packets;
4685 if (packets)
4686 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4687
0ba82994
AD		 4688 packets = q_vector->tx.total_packets;
4689 if (packets)
4690 avg_wire_size = max_t(u32, avg_wire_size,
4691 q_vector->tx.total_bytes / packets);
047e0030
AD		 4692
4693 /* if avg_wire_size isn't set no work was done */
4694 if (!avg_wire_size)
4695 goto clear_counts;
9d5c8243 4696
6eb5a7f1
AD		 4697 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4698 avg_wire_size += 24;
4699
4700 /* Don't starve jumbo frames */
4701 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4702
6eb5a7f1
AD		 4703 /* Give a little boost to mid-size frames */
4704 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4705 new_val = avg_wire_size / 3;
4706 else
4707 new_val = avg_wire_size / 2;
9d5c8243 4708
0ba82994
AD		 4709 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4710 if (new_val < IGB_20K_ITR &&
4711 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4712 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4713 new_val = IGB_20K_ITR;
abe1c363 4714
6eb5a7f1 4715set_itr_val:
047e0030
AD		 4716 if (new_val != q_vector->itr_val) {
4717 q_vector->itr_val = new_val;
4718 q_vector->set_itr = 1;
9d5c8243 4719 }
6eb5a7f1 4720clear_counts:
0ba82994
AD		 4721 q_vector->rx.total_bytes = 0;
4722 q_vector->rx.total_packets = 0;
4723 q_vector->tx.total_bytes = 0;
4724 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4725}
4726
4727/**
b980ac18
JK		 4728 * igb_update_itr - update the dynamic ITR value based on statistics
4729 * @q_vector: pointer to q_vector
4730 * @ring_container: ring info to update the itr for
4731 *
4732 * Stores a new ITR value based on packets and byte
4733 * counts during the last interrupt. The advantage of per interrupt
4734 * computation is faster updates and more accurate ITR for the current
4735 * traffic pattern. Constants in this function were computed
4736 * based on theoretical maximum wire speed and thresholds were set based
4737 * on testing data as well as attempting to minimize response time
4738 * while increasing bulk throughput.
406d4965 4739 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4740 * NOTE: These calculations are only valid when operating in a single-
4741 * queue environment.
9d5c8243 4742 **/
0ba82994
AD		 4743static void igb_update_itr(struct igb_q_vector *q_vector,
4744 struct igb_ring_container *ring_container)
9d5c8243 4745{
0ba82994
AD		 4746 unsigned int packets = ring_container->total_packets;
4747 unsigned int bytes = ring_container->total_bytes;
4748 u8 itrval = ring_container->itr;
9d5c8243 4749
0ba82994 4750 /* no packets, exit with status unchanged */
9d5c8243 4751 if (packets == 0)
0ba82994 4752 return;
9d5c8243 4753
0ba82994 4754 switch (itrval) {
9d5c8243
AK		 4755 case lowest_latency:
4756 /* handle TSO and jumbo frames */
4757 if (bytes/packets > 8000)
0ba82994 4758 itrval = bulk_latency;
9d5c8243 4759 else if ((packets < 5) && (bytes > 512))
0ba82994 4760 itrval = low_latency;
9d5c8243
AK		 4761 break;
4762 case low_latency: /* 50 usec aka 20000 ints/s */
4763 if (bytes > 10000) {
4764 /* this if handles the TSO accounting */
d34a15ab 4765 if (bytes/packets > 8000)
0ba82994 4766 itrval = bulk_latency;
d34a15ab 4767 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4768 itrval = bulk_latency;
d34a15ab 4769 else if ((packets > 35))
0ba82994 4770 itrval = lowest_latency;
9d5c8243 4771 } else if (bytes/packets > 2000) {
0ba82994 4772 itrval = bulk_latency;
9d5c8243 4773 } else if (packets <= 2 && bytes < 512) {
0ba82994 4774 itrval = lowest_latency;
9d5c8243
AK		 4775 }
4776 break;
4777 case bulk_latency: /* 250 usec aka 4000 ints/s */
4778 if (bytes > 25000) {
4779 if (packets > 35)
0ba82994 4780 itrval = low_latency;
1e5c3d21 4781 } else if (bytes < 1500) {
0ba82994 4782 itrval = low_latency;
9d5c8243
AK		 4783 }
4784 break;
4785 }
4786
0ba82994
AD		 4787 /* clear work counters since we have the values we need */
4788 ring_container->total_bytes = 0;
4789 ring_container->total_packets = 0;
4790
4791 /* write updated itr to ring container */
4792 ring_container->itr = itrval;
9d5c8243
AK		 4793}
4794
0ba82994 4795static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4796{
0ba82994 4797 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4798 u32 new_itr = q_vector->itr_val;
0ba82994 4799 u8 current_itr = 0;
9d5c8243
AK		 4800
4801 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4802 if (adapter->link_speed != SPEED_1000) {
4803 current_itr = 0;
0ba82994 4804 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4805 goto set_itr_now;
4806 }
4807
0ba82994
AD		 4808 igb_update_itr(q_vector, &q_vector->tx);
4809 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4810
0ba82994 4811 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4812
6eb5a7f1 4813 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4814 if (current_itr == lowest_latency &&
4815 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4816 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4817 current_itr = low_latency;
4818
9d5c8243
AK		 4819 switch (current_itr) {
4820 /* counts and packets in update_itr are dependent on these numbers */
4821 case lowest_latency:
0ba82994 4822 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4823 break;
4824 case low_latency:
0ba82994 4825 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4826 break;
4827 case bulk_latency:
0ba82994 4828 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4829 break;
4830 default:
4831 break;
4832 }
4833
4834set_itr_now:
047e0030 4835 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4836 /* this attempts to bias the interrupt rate towards Bulk
4837 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4838 * increasing
4839 */
047e0030 4840 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4841 max((new_itr * q_vector->itr_val) /
4842 (new_itr + (q_vector->itr_val >> 2)),
4843 new_itr) : new_itr;
9d5c8243
AK		 4844 /* Don't write the value here; it resets the adapter's
4845 * internal timer, and causes us to delay far longer than
4846 * we should between interrupts. Instead, we write the ITR
4847 * value at the beginning of the next interrupt so the timing
4848 * ends up being correct.
4849 */
047e0030
AD		 4850 q_vector->itr_val = new_itr;
4851 q_vector->set_itr = 1;
9d5c8243 4852 }
9d5c8243
AK		 4853}
4854
c50b52a0
SH		 4855static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4856 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4857{
4858 struct e1000_adv_tx_context_desc *context_desc;
4859 u16 i = tx_ring->next_to_use;
4860
4861 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4862
4863 i++;
4864 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4865
4866 /* set bits to identify this as an advanced context descriptor */
4867 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4868
4869 /* For 82575, context index must be unique per ring. */
866cff06 4870 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4871 mss_l4len_idx |= tx_ring->reg_idx << 4;
4872
4873 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4874 context_desc->seqnum_seed = 0;
4875 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4876 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4877}
4878
7af40ad9
AD		 4879static int igb_tso(struct igb_ring *tx_ring,
4880 struct igb_tx_buffer *first,
4881 u8 *hdr_len)
9d5c8243 4882{
e10715d3 4883 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
7af40ad9 4884 struct sk_buff *skb = first->skb;
e10715d3
AD		 4885 union {
4886 struct iphdr *v4;
4887 struct ipv6hdr *v6;
4888 unsigned char *hdr;
4889 } ip;
4890 union {
4891 struct tcphdr *tcp;
4892 unsigned char *hdr;
4893 } l4;
4894 u32 paylen, l4_offset;
06c14e5a 4895 int err;
7d13a7d0 4896
ed6aa105
AD		 4897 if (skb->ip_summed != CHECKSUM_PARTIAL)
4898 return 0;
4899
7d13a7d0
AD		 4900 if (!skb_is_gso(skb))
4901 return 0;
9d5c8243 4902
06c14e5a
FR		 4903 err = skb_cow_head(skb, 0);
4904 if (err < 0)
4905 return err;
9d5c8243 4906
e10715d3
AD		 4907 ip.hdr = skb_network_header(skb);
4908 l4.hdr = skb_checksum_start(skb);
4909
7d13a7d0
AD		 4910 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4911 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4912
e10715d3
AD		 4913 /* initialize outer IP header fields */
4914 if (ip.v4->version == 4) {
4915 /* IP header will have to cancel out any data that
4916 * is not a part of the outer IP header
4917 */
4918 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
4919 csum_unfold(l4.tcp->check)));
7d13a7d0 4920 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
e10715d3
AD		 4921
4922 ip.v4->tot_len = 0;
7af40ad9
AD		 4923 first->tx_flags |= IGB_TX_FLAGS_TSO |
4924 IGB_TX_FLAGS_CSUM |
4925 IGB_TX_FLAGS_IPV4;
e10715d3
AD		 4926 } else {
4927 ip.v6->payload_len = 0;
7af40ad9
AD		 4928 first->tx_flags |= IGB_TX_FLAGS_TSO |
4929 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4930 }
4931
e10715d3
AD		 4932 /* determine offset of inner transport header */
4933 l4_offset = l4.hdr - skb->data;
4934
4935 /* compute length of segmentation header */
4936 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
4937
4938 /* remove payload length from inner checksum */
4939 paylen = skb->len - l4_offset;
4940 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
9d5c8243 4941
7af40ad9
AD		 4942 /* update gso size and bytecount with header size */
4943 first->gso_segs = skb_shinfo(skb)->gso_segs;
4944 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4945
9d5c8243 4946 /* MSS L4LEN IDX */
e10715d3 4947 mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
7d13a7d0 4948 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4949
7d13a7d0 4950 /* VLAN MACLEN IPLEN */
e10715d3
AD		 4951 vlan_macip_lens = l4.hdr - ip.hdr;
4952 vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4953 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4954
7d13a7d0 4955 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4956
7d13a7d0 4957 return 1;
9d5c8243
AK		 4958}
4959
6e033700
AD		 4960static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
4961{
4962 unsigned int offset = 0;
4963
4964 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
4965
4966 return offset == skb_checksum_start_offset(skb);
4967}
4968
7af40ad9 4969static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4970{
7af40ad9 4971 struct sk_buff *skb = first->skb;
7d13a7d0 4972 u32 vlan_macip_lens = 0;
7d13a7d0 4973 u32 type_tucmd = 0;
9d5c8243 4974
7d13a7d0 4975 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6e033700 4976csum_failed:
7af40ad9
AD		 4977 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4978 return;
6e033700
AD		 4979 goto no_csum;
4980 }
fa4a7ef3 4981
6e033700
AD		 4982 switch (skb->csum_offset) {
4983 case offsetof(struct tcphdr, check):
4984 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4985 /* fall through */
4986 case offsetof(struct udphdr, check):
4987 break;
4988 case offsetof(struct sctphdr, checksum):
4989 /* validate that this is actually an SCTP request */
4990 if (((first->protocol == htons(ETH_P_IP)) &&
4991 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
4992 ((first->protocol == htons(ETH_P_IPV6)) &&
4993 igb_ipv6_csum_is_sctp(skb))) {
4994 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
7d13a7d0 4995 break;
9d5c8243 4996 }
6e033700
AD		 4997 default:
4998 skb_checksum_help(skb);
4999 goto csum_failed;
7d13a7d0 5000 }
9d5c8243 5001
6e033700
AD		 5002 /* update TX checksum flag */
5003 first->tx_flags |= IGB_TX_FLAGS_CSUM;
5004 vlan_macip_lens = skb_checksum_start_offset(skb) -
5005 skb_network_offset(skb);
5006no_csum:
7d13a7d0 5007 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 5008 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 5009
6e033700 5010 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0);
9d5c8243
AK		 5011}
5012
1d9daf45
AD		 5013#define IGB_SET_FLAG(_input, _flag, _result) \
5014 ((_flag <= _result) ? \
5015 ((u32)(_input & _flag) * (_result / _flag)) : \
5016 ((u32)(_input & _flag) / (_flag / _result)))
5017
5018static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 5019{
5020 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 5021 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
5022 E1000_ADVTXD_DCMD_DEXT |
5023 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 5024
5025 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 5026 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
5027 (E1000_ADVTXD_DCMD_VLE));
5028
5029 /* set segmentation bits for TSO */
5030 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
5031 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 5032
5033 /* set timestamp bit if present */
1d9daf45
AD		 5034 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
5035 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 5036
1d9daf45
AD		 5037 /* insert frame checksum */
5038 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 5039
5040 return cmd_type;
5041}
5042
7af40ad9
AD		 5043static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
5044 union e1000_adv_tx_desc *tx_desc,
5045 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 5046{
5047 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
5048
1d9daf45
AD		 5049 /* 82575 requires a unique index per ring */
5050 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 5051 olinfo_status |= tx_ring->reg_idx << 4;
5052
5053 /* insert L4 checksum */
1d9daf45
AD		 5054 olinfo_status |= IGB_SET_FLAG(tx_flags,
5055 IGB_TX_FLAGS_CSUM,
5056 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 5057
1d9daf45
AD		 5058 /* insert IPv4 checksum */
5059 olinfo_status |= IGB_SET_FLAG(tx_flags,
5060 IGB_TX_FLAGS_IPV4,
5061 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 5062
7af40ad9 5063 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 5064}
5065
6f19e12f
DM		 5066static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5067{
5068 struct net_device *netdev = tx_ring->netdev;
5069
5070 netif_stop_subqueue(netdev, tx_ring->queue_index);
5071
5072 /* Herbert's original patch had:
5073 * smp_mb__after_netif_stop_queue();
5074 * but since that doesn't exist yet, just open code it.
5075 */
5076 smp_mb();
5077
5078 /* We need to check again in a case another CPU has just
5079 * made room available.
5080 */
5081 if (igb_desc_unused(tx_ring) < size)
5082 return -EBUSY;
5083
5084 /* A reprieve! */
5085 netif_wake_subqueue(netdev, tx_ring->queue_index);
5086
5087 u64_stats_update_begin(&tx_ring->tx_syncp2);
5088 tx_ring->tx_stats.restart_queue2++;
5089 u64_stats_update_end(&tx_ring->tx_syncp2);
5090
5091 return 0;
5092}
5093
5094static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5095{
5096 if (igb_desc_unused(tx_ring) >= size)
5097 return 0;
5098 return __igb_maybe_stop_tx(tx_ring, size);
5099}
5100
7af40ad9
AD		 5101static void igb_tx_map(struct igb_ring *tx_ring,
5102 struct igb_tx_buffer *first,
ebe42d16 5103 const u8 hdr_len)
9d5c8243 5104{
7af40ad9 5105 struct sk_buff *skb = first->skb;
c9f14bf3 5106 struct igb_tx_buffer *tx_buffer;
ebe42d16 5107 union e1000_adv_tx_desc *tx_desc;
80d0759e 5108 struct skb_frag_struct *frag;
ebe42d16 5109 dma_addr_t dma;
80d0759e 5110 unsigned int data_len, size;
7af40ad9 5111 u32 tx_flags = first->tx_flags;
1d9daf45 5112 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 5113 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 5114
5115 tx_desc = IGB_TX_DESC(tx_ring, i);
5116
80d0759e
AD		 5117 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5118
5119 size = skb_headlen(skb);
5120 data_len = skb->data_len;
ebe42d16
AD		 5121
5122 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 5123
80d0759e
AD		 5124 tx_buffer = first;
5125
5126 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5127 if (dma_mapping_error(tx_ring->dev, dma))
5128 goto dma_error;
5129
5130 /* record length, and DMA address */
5131 dma_unmap_len_set(tx_buffer, len, size);
5132 dma_unmap_addr_set(tx_buffer, dma, dma);
5133
5134 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 5135
ebe42d16
AD		 5136 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5137 tx_desc->read.cmd_type_len =
1d9daf45 5138 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 5139
5140 i++;
5141 tx_desc++;
5142 if (i == tx_ring->count) {
5143 tx_desc = IGB_TX_DESC(tx_ring, 0);
5144 i = 0;
5145 }
80d0759e 5146 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 5147
5148 dma += IGB_MAX_DATA_PER_TXD;
5149 size -= IGB_MAX_DATA_PER_TXD;
5150
ebe42d16
AD		 5151 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5152 }
5153
5154 if (likely(!data_len))
5155 break;
2bbfebe2 5156
1d9daf45 5157 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 5158
65689fef 5159 i++;
ebe42d16
AD		 5160 tx_desc++;
5161 if (i == tx_ring->count) {
5162 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 5163 i = 0;
ebe42d16 5164 }
80d0759e 5165 tx_desc->read.olinfo_status = 0;
65689fef 5166
9e903e08 5167 size = skb_frag_size(frag);
ebe42d16
AD		 5168 data_len -= size;
5169
5170 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 5171 size, DMA_TO_DEVICE);
6366ad33 5172
c9f14bf3 5173 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 5174 }
5175
ebe42d16 5176 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 5177 cmd_type |= size | IGB_TXD_DCMD;
5178 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 5179
80d0759e
AD		 5180 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5181
8542db05
AD		 5182 /* set the timestamp */
5183 first->time_stamp = jiffies;
5184
b980ac18 5185 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 5186 * are new descriptors to fetch. (Only applicable for weak-ordered
5187 * memory model archs, such as IA-64).
5188 *
5189 * We also need this memory barrier to make certain all of the
5190 * status bits have been updated before next_to_watch is written.
5191 */
5192 wmb();
5193
8542db05 5194 /* set next_to_watch value indicating a packet is present */
ebe42d16 5195 first->next_to_watch = tx_desc;
9d5c8243 5196
ebe42d16
AD		 5197 i++;
5198 if (i == tx_ring->count)
5199 i = 0;
6366ad33 5200
ebe42d16 5201 tx_ring->next_to_use = i;
6366ad33 5202
6f19e12f
DM		 5203 /* Make sure there is space in the ring for the next send. */
5204 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5205
5206 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 5207 writel(i, tx_ring->tail);
5208
5209 /* we need this if more than one processor can write to our tail
5210 * at a time, it synchronizes IO on IA64/Altix systems
5211 */
5212 mmiowb();
5213 }
ebe42d16
AD		 5214 return;
5215
5216dma_error:
5217 dev_err(tx_ring->dev, "TX DMA map failed\n");
5218
5219 /* clear dma mappings for failed tx_buffer_info map */
5220 for (;;) {
c9f14bf3
AD		 5221 tx_buffer = &tx_ring->tx_buffer_info[i];
5222 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5223 if (tx_buffer == first)
ebe42d16 5224 break;
a77ff709
NN		 5225 if (i == 0)
5226 i = tx_ring->count;
6366ad33 5227 i--;
6366ad33
AD		 5228 }
5229
9d5c8243 5230 tx_ring->next_to_use = i;
9d5c8243
AK		 5231}
5232
cd392f5c
AD		 5233netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5234 struct igb_ring *tx_ring)
9d5c8243 5235{
8542db05 5236 struct igb_tx_buffer *first;
ebe42d16 5237 int tso;
91d4ee33 5238 u32 tx_flags = 0;
2ee52ad4 5239 unsigned short f;
21ba6fe1 5240 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5241 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5242 u8 hdr_len = 0;
9d5c8243 5243
21ba6fe1
AD		 5244 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5245 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5246 * + 2 desc gap to keep tail from touching head,
9d5c8243 5247 * + 1 desc for context descriptor,
21ba6fe1
AD		 5248 * otherwise try next time
5249 */
2ee52ad4
AD		 5250 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5251 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5252
5253 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5254 /* this is a hard error */
9d5c8243
AK		 5255 return NETDEV_TX_BUSY;
5256 }
33af6bcc 5257
7af40ad9
AD		 5258 /* record the location of the first descriptor for this packet */
5259 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5260 first->skb = skb;
5261 first->bytecount = skb->len;
5262 first->gso_segs = 1;
5263
b646c22e
AD		 5264 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5265 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5266
ed4420a3
JK		 5267 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5268 &adapter->state)) {
b646c22e
AD		 5269 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5270 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5271
5272 adapter->ptp_tx_skb = skb_get(skb);
5273 adapter->ptp_tx_start = jiffies;
5274 if (adapter->hw.mac.type == e1000_82576)
5275 schedule_work(&adapter->ptp_tx_work);
5276 }
33af6bcc 5277 }
9d5c8243 5278
afc835d1
JK		 5279 skb_tx_timestamp(skb);
5280
df8a39de 5281 if (skb_vlan_tag_present(skb)) {
9d5c8243 5282 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5283 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5284 }
5285
7af40ad9
AD		 5286 /* record initial flags and protocol */
5287 first->tx_flags = tx_flags;
5288 first->protocol = protocol;
cdfd01fc 5289
7af40ad9
AD		 5290 tso = igb_tso(tx_ring, first, &hdr_len);
5291 if (tso < 0)
7d13a7d0 5292 goto out_drop;
7af40ad9
AD		 5293 else if (!tso)
5294 igb_tx_csum(tx_ring, first);
9d5c8243 5295
7af40ad9 5296 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5297
9d5c8243 5298 return NETDEV_TX_OK;
7d13a7d0
AD		 5299
5300out_drop:
7af40ad9
AD		 5301 igb_unmap_and_free_tx_resource(tx_ring, first);
5302
7d13a7d0 5303 return NETDEV_TX_OK;
9d5c8243
AK		 5304}
5305
0b725a2c
DM		 5306static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5307 struct sk_buff *skb)
1cc3bd87 5308{
0b725a2c
DM		 5309 unsigned int r_idx = skb->queue_mapping;
5310
1cc3bd87
AD		 5311 if (r_idx >= adapter->num_tx_queues)
5312 r_idx = r_idx % adapter->num_tx_queues;
5313
5314 return adapter->tx_ring[r_idx];
5315}
5316
cd392f5c
AD		 5317static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5318 struct net_device *netdev)
9d5c8243
AK		 5319{
5320 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3 5321
b980ac18 5322 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5323 * in order to meet this minimum size requirement.
5324 */
a94d9e22
AD		 5325 if (skb_put_padto(skb, 17))
5326 return NETDEV_TX_OK;
9d5c8243 5327
1cc3bd87 5328 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5329}
5330
5331/**
b980ac18
JK		 5332 * igb_tx_timeout - Respond to a Tx Hang
5333 * @netdev: network interface device structure
9d5c8243
AK		 5334 **/
5335static void igb_tx_timeout(struct net_device *netdev)
5336{
5337 struct igb_adapter *adapter = netdev_priv(netdev);
5338 struct e1000_hw *hw = &adapter->hw;
5339
5340 /* Do the reset outside of interrupt context */
5341 adapter->tx_timeout_count++;
f7ba205e 5342
06218a8d 5343 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5344 hw->dev_spec._82575.global_device_reset = true;
5345
9d5c8243 5346 schedule_work(&adapter->reset_task);
265de409
AD		 5347 wr32(E1000_EICS,
5348 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5349}
5350
5351static void igb_reset_task(struct work_struct *work)
5352{
5353 struct igb_adapter *adapter;
5354 adapter = container_of(work, struct igb_adapter, reset_task);
5355
c97ec42a
TI		 5356 igb_dump(adapter);
5357 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5358 igb_reinit_locked(adapter);
5359}
5360
5361/**
b980ac18
JK		 5362 * igb_get_stats64 - Get System Network Statistics
5363 * @netdev: network interface device structure
5364 * @stats: rtnl_link_stats64 pointer
9d5c8243 5365 **/
12dcd86b 5366static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5367 struct rtnl_link_stats64 *stats)
9d5c8243 5368{
12dcd86b
ED		 5369 struct igb_adapter *adapter = netdev_priv(netdev);
5370
5371 spin_lock(&adapter->stats64_lock);
5372 igb_update_stats(adapter, &adapter->stats64);
5373 memcpy(stats, &adapter->stats64, sizeof(*stats));
5374 spin_unlock(&adapter->stats64_lock);
5375
5376 return stats;
9d5c8243
AK		 5377}
5378
5379/**
b980ac18
JK		 5380 * igb_change_mtu - Change the Maximum Transfer Unit
5381 * @netdev: network interface device structure
5382 * @new_mtu: new value for maximum frame size
9d5c8243 5383 *
b980ac18 5384 * Returns 0 on success, negative on failure
9d5c8243
AK		 5385 **/
5386static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5387{
5388 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5389 struct pci_dev *pdev = adapter->pdev;
153285f9 5390 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5391
c809d227 5392 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5393 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5394 return -EINVAL;
5395 }
5396
153285f9 5397#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5398 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5399 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5400 return -EINVAL;
5401 }
5402
2ccd994c
AD		 5403 /* adjust max frame to be at least the size of a standard frame */
5404 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5405 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5406
9d5c8243 5407 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5408 usleep_range(1000, 2000);
73cd78f1 5409
9d5c8243
AK		 5410 /* igb_down has a dependency on max_frame_size */
5411 adapter->max_frame_size = max_frame;
559e9c49 5412
4c844851
AD		 5413 if (netif_running(netdev))
5414 igb_down(adapter);
9d5c8243 5415
090b1795 5416 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5417 netdev->mtu, new_mtu);
5418 netdev->mtu = new_mtu;
5419
5420 if (netif_running(netdev))
5421 igb_up(adapter);
5422 else
5423 igb_reset(adapter);
5424
5425 clear_bit(__IGB_RESETTING, &adapter->state);
5426
5427 return 0;
5428}
5429
5430/**
b980ac18
JK		 5431 * igb_update_stats - Update the board statistics counters
5432 * @adapter: board private structure
9d5c8243 5433 **/
12dcd86b
ED		 5434void igb_update_stats(struct igb_adapter *adapter,
5435 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5436{
5437 struct e1000_hw *hw = &adapter->hw;
5438 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5439 u32 reg, mpc;
3f9c0164
AD		 5440 int i;
5441 u64 bytes, packets;
12dcd86b
ED		 5442 unsigned int start;
5443 u64 _bytes, _packets;
9d5c8243 5444
b980ac18 5445 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5446 * connection is down.
5447 */
5448 if (adapter->link_speed == 0)
5449 return;
5450 if (pci_channel_offline(pdev))
5451 return;
5452
3f9c0164
AD		 5453 bytes = 0;
5454 packets = 0;
7f90128e
AA		 5455
5456 rcu_read_lock();
3f9c0164 5457 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5458 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5459 u32 rqdpc = rd32(E1000_RQDPC(i));
5460 if (hw->mac.type >= e1000_i210)
5461 wr32(E1000_RQDPC(i), 0);
12dcd86b 5462
ae1c07a6
AD		 5463 if (rqdpc) {
5464 ring->rx_stats.drops += rqdpc;
5465 net_stats->rx_fifo_errors += rqdpc;
5466 }
12dcd86b
ED		 5467
5468 do {
57a7744e 5469 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5470 _bytes = ring->rx_stats.bytes;
5471 _packets = ring->rx_stats.packets;
57a7744e 5472 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5473 bytes += _bytes;
5474 packets += _packets;
3f9c0164
AD		 5475 }
5476
128e45eb
AD		 5477 net_stats->rx_bytes = bytes;
5478 net_stats->rx_packets = packets;
3f9c0164
AD		 5479
5480 bytes = 0;
5481 packets = 0;
5482 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5483 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5484 do {
57a7744e 5485 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5486 _bytes = ring->tx_stats.bytes;
5487 _packets = ring->tx_stats.packets;
57a7744e 5488 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5489 bytes += _bytes;
5490 packets += _packets;
3f9c0164 5491 }
128e45eb
AD		 5492 net_stats->tx_bytes = bytes;
5493 net_stats->tx_packets = packets;
7f90128e 5494 rcu_read_unlock();
3f9c0164
AD		 5495
5496 /* read stats registers */
9d5c8243
AK		 5497 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5498 adapter->stats.gprc += rd32(E1000_GPRC);
5499 adapter->stats.gorc += rd32(E1000_GORCL);
5500 rd32(E1000_GORCH); /* clear GORCL */
5501 adapter->stats.bprc += rd32(E1000_BPRC);
5502 adapter->stats.mprc += rd32(E1000_MPRC);
5503 adapter->stats.roc += rd32(E1000_ROC);
5504
5505 adapter->stats.prc64 += rd32(E1000_PRC64);
5506 adapter->stats.prc127 += rd32(E1000_PRC127);
5507 adapter->stats.prc255 += rd32(E1000_PRC255);
5508 adapter->stats.prc511 += rd32(E1000_PRC511);
5509 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5510 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5511 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5512 adapter->stats.sec += rd32(E1000_SEC);
5513
fa3d9a6d
MW		 5514 mpc = rd32(E1000_MPC);
5515 adapter->stats.mpc += mpc;
5516 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5517 adapter->stats.scc += rd32(E1000_SCC);
5518 adapter->stats.ecol += rd32(E1000_ECOL);
5519 adapter->stats.mcc += rd32(E1000_MCC);
5520 adapter->stats.latecol += rd32(E1000_LATECOL);
5521 adapter->stats.dc += rd32(E1000_DC);
5522 adapter->stats.rlec += rd32(E1000_RLEC);
5523 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5524 adapter->stats.xontxc += rd32(E1000_XONTXC);
5525 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5526 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5527 adapter->stats.fcruc += rd32(E1000_FCRUC);
5528 adapter->stats.gptc += rd32(E1000_GPTC);
5529 adapter->stats.gotc += rd32(E1000_GOTCL);
5530 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5531 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5532 adapter->stats.ruc += rd32(E1000_RUC);
5533 adapter->stats.rfc += rd32(E1000_RFC);
5534 adapter->stats.rjc += rd32(E1000_RJC);
5535 adapter->stats.tor += rd32(E1000_TORH);
5536 adapter->stats.tot += rd32(E1000_TOTH);
5537 adapter->stats.tpr += rd32(E1000_TPR);
5538
5539 adapter->stats.ptc64 += rd32(E1000_PTC64);
5540 adapter->stats.ptc127 += rd32(E1000_PTC127);
5541 adapter->stats.ptc255 += rd32(E1000_PTC255);
5542 adapter->stats.ptc511 += rd32(E1000_PTC511);
5543 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5544 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5545
5546 adapter->stats.mptc += rd32(E1000_MPTC);
5547 adapter->stats.bptc += rd32(E1000_BPTC);
5548
2d0b0f69
NN		 5549 adapter->stats.tpt += rd32(E1000_TPT);
5550 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5551
5552 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5553 /* read internal phy specific stats */
5554 reg = rd32(E1000_CTRL_EXT);
5555 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5556 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5557
5558 /* this stat has invalid values on i210/i211 */
5559 if ((hw->mac.type != e1000_i210) &&
5560 (hw->mac.type != e1000_i211))
5561 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5562 }
5563
9d5c8243
AK		 5564 adapter->stats.tsctc += rd32(E1000_TSCTC);
5565 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5566
5567 adapter->stats.iac += rd32(E1000_IAC);
5568 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5569 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5570 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5571 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5572 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5573 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5574 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5575 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5576
5577 /* Fill out the OS statistics structure */
128e45eb
AD		 5578 net_stats->multicast = adapter->stats.mprc;
5579 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5580
5581 /* Rx Errors */
5582
5583 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5584 * our own version based on RUC and ROC
5585 */
128e45eb 5586 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5587 adapter->stats.crcerrs + adapter->stats.algnerrc +
5588 adapter->stats.ruc + adapter->stats.roc +
5589 adapter->stats.cexterr;
128e45eb
AD		 5590 net_stats->rx_length_errors = adapter->stats.ruc +
5591 adapter->stats.roc;
5592 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5593 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5594 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5595
5596 /* Tx Errors */
128e45eb
AD		 5597 net_stats->tx_errors = adapter->stats.ecol +
5598 adapter->stats.latecol;
5599 net_stats->tx_aborted_errors = adapter->stats.ecol;
5600 net_stats->tx_window_errors = adapter->stats.latecol;
5601 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5602
5603 /* Tx Dropped needs to be maintained elsewhere */
5604
9d5c8243
AK		 5605 /* Management Stats */
5606 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5607 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5608 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5609
5610 /* OS2BMC Stats */
5611 reg = rd32(E1000_MANC);
5612 if (reg & E1000_MANC_EN_BMC2OS) {
5613 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5614 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5615 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5616 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5617 }
9d5c8243
AK		 5618}
5619
61d7f75f
RC		 5620static void igb_tsync_interrupt(struct igb_adapter *adapter)
5621{
5622 struct e1000_hw *hw = &adapter->hw;
00c65578 5623 struct ptp_clock_event event;
40c9b079 5624 struct timespec64 ts;
720db4ff 5625 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5626
5627 if (tsicr & TSINTR_SYS_WRAP) {
5628 event.type = PTP_CLOCK_PPS;
5629 if (adapter->ptp_caps.pps)
5630 ptp_clock_event(adapter->ptp_clock, &event);
5631 else
5632 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5633 ack |= TSINTR_SYS_WRAP;
5634 }
61d7f75f
RC		 5635
5636 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5637 /* retrieve hardware timestamp */
5638 schedule_work(&adapter->ptp_tx_work);
00c65578 5639 ack |= E1000_TSICR_TXTS;
61d7f75f 5640 }
00c65578 5641
720db4ff
RC		 5642 if (tsicr & TSINTR_TT0) {
5643 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5644 ts = timespec64_add(adapter->perout[0].start,
5645 adapter->perout[0].period);
5646 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5647 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5648 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5649 tsauxc = rd32(E1000_TSAUXC);
5650 tsauxc |= TSAUXC_EN_TT0;
5651 wr32(E1000_TSAUXC, tsauxc);
5652 adapter->perout[0].start = ts;
5653 spin_unlock(&adapter->tmreg_lock);
5654 ack |= TSINTR_TT0;
5655 }
5656
5657 if (tsicr & TSINTR_TT1) {
5658 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5659 ts = timespec64_add(adapter->perout[1].start,
5660 adapter->perout[1].period);
720db4ff 5661 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5662 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5663 tsauxc = rd32(E1000_TSAUXC);
5664 tsauxc |= TSAUXC_EN_TT1;
5665 wr32(E1000_TSAUXC, tsauxc);
5666 adapter->perout[1].start = ts;
5667 spin_unlock(&adapter->tmreg_lock);
5668 ack |= TSINTR_TT1;
5669 }
5670
5671 if (tsicr & TSINTR_AUTT0) {
5672 nsec = rd32(E1000_AUXSTMPL0);
5673 sec = rd32(E1000_AUXSTMPH0);
5674 event.type = PTP_CLOCK_EXTTS;
5675 event.index = 0;
5676 event.timestamp = sec * 1000000000ULL + nsec;
5677 ptp_clock_event(adapter->ptp_clock, &event);
5678 ack |= TSINTR_AUTT0;
5679 }
5680
5681 if (tsicr & TSINTR_AUTT1) {
5682 nsec = rd32(E1000_AUXSTMPL1);
5683 sec = rd32(E1000_AUXSTMPH1);
5684 event.type = PTP_CLOCK_EXTTS;
5685 event.index = 1;
5686 event.timestamp = sec * 1000000000ULL + nsec;
5687 ptp_clock_event(adapter->ptp_clock, &event);
5688 ack |= TSINTR_AUTT1;
5689 }
5690
00c65578
RC		 5691 /* acknowledge the interrupts */
5692 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5693}
5694
9d5c8243
AK		 5695static irqreturn_t igb_msix_other(int irq, void *data)
5696{
047e0030 5697 struct igb_adapter *adapter = data;
9d5c8243 5698 struct e1000_hw *hw = &adapter->hw;
844290e5 5699 u32 icr = rd32(E1000_ICR);
844290e5 5700 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5701
7f081d40
AD		 5702 if (icr & E1000_ICR_DRSTA)
5703 schedule_work(&adapter->reset_task);
5704
047e0030 5705 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5706 /* HW is reporting DMA is out of sync */
5707 adapter->stats.doosync++;
13800469
GR		 5708 /* The DMA Out of Sync is also indication of a spoof event
5709 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5710 * see if it is really a spoof event.
5711 */
13800469 5712 igb_check_wvbr(adapter);
dda0e083 5713 }
eebbbdba 5714
4ae196df
AD		 5715 /* Check for a mailbox event */
5716 if (icr & E1000_ICR_VMMB)
5717 igb_msg_task(adapter);
5718
5719 if (icr & E1000_ICR_LSC) {
5720 hw->mac.get_link_status = 1;
5721 /* guard against interrupt when we're going down */
5722 if (!test_bit(__IGB_DOWN, &adapter->state))
5723 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5724 }
5725
61d7f75f
RC		 5726 if (icr & E1000_ICR_TS)
5727 igb_tsync_interrupt(adapter);
1f6e8178 5728
844290e5 5729 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5730
5731 return IRQ_HANDLED;
5732}
5733
047e0030 5734static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5735{
26b39276 5736 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5737 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5738
047e0030
AD		 5739 if (!q_vector->set_itr)
5740 return;
73cd78f1 5741
047e0030
AD		 5742 if (!itr_val)
5743 itr_val = 0x4;
661086df 5744
26b39276
AD		 5745 if (adapter->hw.mac.type == e1000_82575)
5746 itr_val |= itr_val << 16;
661086df 5747 else
0ba82994 5748 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5749
047e0030
AD		 5750 writel(itr_val, q_vector->itr_register);
5751 q_vector->set_itr = 0;
6eb5a7f1
AD		 5752}
5753
047e0030 5754static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5755{
047e0030 5756 struct igb_q_vector *q_vector = data;
9d5c8243 5757
047e0030
AD		 5758 /* Write the ITR value calculated from the previous interrupt. */
5759 igb_write_itr(q_vector);
9d5c8243 5760
047e0030 5761 napi_schedule(&q_vector->napi);
844290e5 5762
047e0030 5763 return IRQ_HANDLED;
fe4506b6
JC		 5764}
5765
421e02f0 5766#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5767static void igb_update_tx_dca(struct igb_adapter *adapter,
5768 struct igb_ring *tx_ring,
5769 int cpu)
5770{
5771 struct e1000_hw *hw = &adapter->hw;
5772 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5773
5774 if (hw->mac.type != e1000_82575)
5775 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5776
b980ac18 5777 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5778 * DCA is enabled. This is due to a known issue in some chipsets
5779 * which will cause the DCA tag to be cleared.
5780 */
5781 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5782 E1000_DCA_TXCTRL_DATA_RRO_EN |
5783 E1000_DCA_TXCTRL_DESC_DCA_EN;
5784
5785 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5786}
5787
5788static void igb_update_rx_dca(struct igb_adapter *adapter,
5789 struct igb_ring *rx_ring,
5790 int cpu)
5791{
5792 struct e1000_hw *hw = &adapter->hw;
5793 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5794
5795 if (hw->mac.type != e1000_82575)
5796 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5797
b980ac18 5798 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5799 * DCA is enabled. This is due to a known issue in some chipsets
5800 * which will cause the DCA tag to be cleared.
5801 */
5802 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5803 E1000_DCA_RXCTRL_DESC_DCA_EN;
5804
5805 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5806}
5807
047e0030 5808static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5809{
047e0030 5810 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5811 int cpu = get_cpu();
fe4506b6 5812
047e0030
AD		 5813 if (q_vector->cpu == cpu)
5814 goto out_no_update;
5815
6a05004a
AD		 5816 if (q_vector->tx.ring)
5817 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5818
5819 if (q_vector->rx.ring)
5820 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5821
047e0030
AD		 5822 q_vector->cpu = cpu;
5823out_no_update:
fe4506b6
JC		 5824 put_cpu();
5825}
5826
5827static void igb_setup_dca(struct igb_adapter *adapter)
5828{
7e0e99ef 5829 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5830 int i;
5831
7dfc16fa 5832 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5833 return;
5834
7e0e99ef
AD		 5835 /* Always use CB2 mode, difference is masked in the CB driver. */
5836 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5837
047e0030 5838 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5839 adapter->q_vector[i]->cpu = -1;
5840 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5841 }
5842}
5843
5844static int __igb_notify_dca(struct device *dev, void *data)
5845{
5846 struct net_device *netdev = dev_get_drvdata(dev);
5847 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5848 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5849 struct e1000_hw *hw = &adapter->hw;
5850 unsigned long event = *(unsigned long *)data;
5851
5852 switch (event) {
5853 case DCA_PROVIDER_ADD:
5854 /* if already enabled, don't do it again */
7dfc16fa 5855 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5856 break;
fe4506b6 5857 if (dca_add_requester(dev) == 0) {
bbd98fe4 5858 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5859 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5860 igb_setup_dca(adapter);
5861 break;
5862 }
5863 /* Fall Through since DCA is disabled. */
5864 case DCA_PROVIDER_REMOVE:
7dfc16fa 5865 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5866 /* without this a class_device is left
b980ac18
JK		 5867 * hanging around in the sysfs model
5868 */
fe4506b6 5869 dca_remove_requester(dev);
090b1795 5870 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5871 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5872 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5873 }
5874 break;
5875 }
bbd98fe4 5876
fe4506b6 5877 return 0;
9d5c8243
AK		 5878}
5879
fe4506b6 5880static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5881 void *p)
fe4506b6
JC		 5882{
5883 int ret_val;
5884
5885 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5886 __igb_notify_dca);
fe4506b6
JC		 5887
5888 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5889}
421e02f0 5890#endif /* CONFIG_IGB_DCA */
9d5c8243 5891
0224d663
GR		 5892#ifdef CONFIG_PCI_IOV
5893static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5894{
5895 unsigned char mac_addr[ETH_ALEN];
0224d663 5896
5ac6f91d 5897 eth_zero_addr(mac_addr);
0224d663
GR		 5898 igb_set_vf_mac(adapter, vf, mac_addr);
5899
70ea4783
LL		 5900 /* By default spoof check is enabled for all VFs */
5901 adapter->vf_data[vf].spoofchk_enabled = true;
5902
f557147c 5903 return 0;
0224d663
GR		 5904}
5905
0224d663 5906#endif
4ae196df
AD		 5907static void igb_ping_all_vfs(struct igb_adapter *adapter)
5908{
5909 struct e1000_hw *hw = &adapter->hw;
5910 u32 ping;
5911 int i;
5912
5913 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5914 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5915 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5916 ping |= E1000_VT_MSGTYPE_CTS;
5917 igb_write_mbx(hw, &ping, 1, i);
5918 }
5919}
5920
7d5753f0
AD		 5921static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5922{
5923 struct e1000_hw *hw = &adapter->hw;
5924 u32 vmolr = rd32(E1000_VMOLR(vf));
5925 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5926
d85b9004 5927 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5928 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5929 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5930
5931 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5932 vmolr |= E1000_VMOLR_MPME;
d85b9004 5933 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5934 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5935 } else {
b980ac18 5936 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5937 * flag we need to write the hashes to the MTA as this step
5938 * was previously skipped
5939 */
5940 if (vf_data->num_vf_mc_hashes > 30) {
5941 vmolr |= E1000_VMOLR_MPME;
5942 } else if (vf_data->num_vf_mc_hashes) {
5943 int j;
9005df38 5944
7d5753f0
AD		 5945 vmolr |= E1000_VMOLR_ROMPE;
5946 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5947 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5948 }
5949 }
5950
5951 wr32(E1000_VMOLR(vf), vmolr);
5952
5953 /* there are flags left unprocessed, likely not supported */
5954 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5955 return -EINVAL;
5956
5957 return 0;
7d5753f0
AD		 5958}
5959
4ae196df
AD		 5960static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5961 u32 *msgbuf, u32 vf)
5962{
5963 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5964 u16 *hash_list = (u16 *)&msgbuf[1];
5965 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5966 int i;
5967
7d5753f0 5968 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5969 * to this VF for later use to restore when the PF multi cast
5970 * list changes
5971 */
5972 vf_data->num_vf_mc_hashes = n;
5973
7d5753f0
AD		 5974 /* only up to 30 hash values supported */
5975 if (n > 30)
5976 n = 30;
5977
5978 /* store the hashes for later use */
4ae196df 5979 for (i = 0; i < n; i++)
a419aef8 5980 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5981
5982 /* Flush and reset the mta with the new values */
ff41f8dc 5983 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5984
5985 return 0;
5986}
5987
5988static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5989{
5990 struct e1000_hw *hw = &adapter->hw;
5991 struct vf_data_storage *vf_data;
5992 int i, j;
5993
5994 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5995 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5996
7d5753f0
AD		 5997 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5998
4ae196df 5999 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 6000
6001 if ((vf_data->num_vf_mc_hashes > 30) ||
6002 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
6003 vmolr |= E1000_VMOLR_MPME;
6004 } else if (vf_data->num_vf_mc_hashes) {
6005 vmolr |= E1000_VMOLR_ROMPE;
6006 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6007 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6008 }
6009 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 6010 }
6011}
6012
6013static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
6014{
6015 struct e1000_hw *hw = &adapter->hw;
16903caa 6016 u32 pool_mask, vlvf_mask, i;
4ae196df 6017
16903caa
AD		 6018 /* create mask for VF and other pools */
6019 pool_mask = E1000_VLVF_POOLSEL_MASK;
a51d8c21 6020 vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
16903caa
AD		 6021
6022 /* drop PF from pool bits */
a51d8c21
JK		 6023 pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
6024 adapter->vfs_allocated_count);
4ae196df
AD		 6025
6026 /* Find the vlan filter for this id */
16903caa
AD		 6027 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
6028 u32 vlvf = rd32(E1000_VLVF(i));
6029 u32 vfta_mask, vid, vfta;
4ae196df
AD		 6030
6031 /* remove the vf from the pool */
16903caa
AD		 6032 if (!(vlvf & vlvf_mask))
6033 continue;
6034
6035 /* clear out bit from VLVF */
6036 vlvf ^= vlvf_mask;
6037
6038 /* if other pools are present, just remove ourselves */
6039 if (vlvf & pool_mask)
6040 goto update_vlvfb;
4ae196df 6041
16903caa
AD		 6042 /* if PF is present, leave VFTA */
6043 if (vlvf & E1000_VLVF_POOLSEL_MASK)
6044 goto update_vlvf;
4ae196df 6045
16903caa 6046 vid = vlvf & E1000_VLVF_VLANID_MASK;
a51d8c21 6047 vfta_mask = BIT(vid % 32);
16903caa
AD		 6048
6049 /* clear bit from VFTA */
6050 vfta = adapter->shadow_vfta[vid / 32];
6051 if (vfta & vfta_mask)
6052 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
6053update_vlvf:
6054 /* clear pool selection enable */
6055 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6056 vlvf &= E1000_VLVF_POOLSEL_MASK;
6057 else
6058 vlvf = 0;
6059update_vlvfb:
6060 /* clear pool bits */
6061 wr32(E1000_VLVF(i), vlvf);
4ae196df
AD		 6062 }
6063}
ae641bdc 6064
16903caa 6065static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6f3dc319 6066{
16903caa
AD		 6067 u32 vlvf;
6068 int idx;
6f3dc319 6069
16903caa
AD		 6070 /* short cut the special case */
6071 if (vlan == 0)
6072 return 0;
6073
6074 /* Search for the VLAN id in the VLVF entries */
6075 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6076 vlvf = rd32(E1000_VLVF(idx));
6077 if ((vlvf & VLAN_VID_MASK) == vlan)
6f3dc319
GR		 6078 break;
6079 }
6080
16903caa 6081 return idx;
4ae196df
AD		 6082}
6083
8008f68c 6084static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
4ae196df
AD		 6085{
6086 struct e1000_hw *hw = &adapter->hw;
16903caa
AD		 6087 u32 bits, pf_id;
6088 int idx;
51466239 6089
16903caa
AD		 6090 idx = igb_find_vlvf_entry(hw, vid);
6091 if (!idx)
6092 return;
4ae196df 6093
16903caa
AD		 6094 /* See if any other pools are set for this VLAN filter
6095 * entry other than the PF.
6096 */
6097 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
a51d8c21 6098 bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
16903caa
AD		 6099 bits &= rd32(E1000_VLVF(idx));
6100
6101 /* Disable the filter so this falls into the default pool. */
6102 if (!bits) {
6103 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
a51d8c21 6104 wr32(E1000_VLVF(idx), BIT(pf_id));
16903caa
AD		 6105 else
6106 wr32(E1000_VLVF(idx), 0);
4ae196df 6107 }
6f3dc319 6108}
4ae196df 6109
a15d9259
AD		 6110static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6111 bool add, u32 vf)
4ae196df 6112{
a15d9259 6113 int pf_id = adapter->vfs_allocated_count;
6f3dc319 6114 struct e1000_hw *hw = &adapter->hw;
a15d9259 6115 int err;
ae641bdc 6116
a15d9259
AD		 6117 /* If VLAN overlaps with one the PF is currently monitoring make
6118 * sure that we are able to allocate a VLVF entry. This may be
6119 * redundant but it guarantees PF will maintain visibility to
6120 * the VLAN.
6f3dc319 6121 */
16903caa 6122 if (add && test_bit(vid, adapter->active_vlans)) {
a15d9259
AD		 6123 err = igb_vfta_set(hw, vid, pf_id, true, false);
6124 if (err)
6125 return err;
4ae196df 6126 }
6f3dc319 6127
a15d9259 6128 err = igb_vfta_set(hw, vid, vf, add, false);
6f3dc319 6129
16903caa
AD		 6130 if (add && !err)
6131 return err;
6f3dc319 6132
16903caa
AD		 6133 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6134 * we may need to drop the PF pool bit in order to allow us to free
6135 * up the VLVF resources.
6f3dc319 6136 */
16903caa
AD		 6137 if (test_bit(vid, adapter->active_vlans) ||
6138 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6139 igb_update_pf_vlvf(adapter, vid);
6f3dc319 6140
6f3dc319 6141 return err;
8151d294
WM		 6142}
6143
6144static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6145{
6146 struct e1000_hw *hw = &adapter->hw;
6147
6148 if (vid)
6149 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6150 else
6151 wr32(E1000_VMVIR(vf), 0);
6152}
6153
a15d9259
AD		 6154static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6155 u16 vlan, u8 qos)
8151d294 6156{
a15d9259 6157 int err;
8151d294 6158
a15d9259
AD		 6159 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6160 if (err)
6161 return err;
6162
6163 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6164 igb_set_vmolr(adapter, vf, !vlan);
6165
6166 /* revoke access to previous VLAN */
6167 if (vlan != adapter->vf_data[vf].pf_vlan)
6168 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6169 false, vf);
6170
6171 adapter->vf_data[vf].pf_vlan = vlan;
6172 adapter->vf_data[vf].pf_qos = qos;
030f9f52 6173 igb_set_vf_vlan_strip(adapter, vf, true);
a15d9259
AD		 6174 dev_info(&adapter->pdev->dev,
6175 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6176 if (test_bit(__IGB_DOWN, &adapter->state)) {
6177 dev_warn(&adapter->pdev->dev,
6178 "The VF VLAN has been set, but the PF device is not up.\n");
6179 dev_warn(&adapter->pdev->dev,
6180 "Bring the PF device up before attempting to use the VF device.\n");
b980ac18 6181 }
a15d9259 6182
b980ac18 6183 return err;
4ae196df
AD		 6184}
6185
a15d9259 6186static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6f3dc319 6187{
a15d9259
AD		 6188 /* Restore tagless access via VLAN 0 */
6189 igb_set_vf_vlan(adapter, 0, true, vf);
6f3dc319 6190
a15d9259 6191 igb_set_vmvir(adapter, 0, vf);
8151d294 6192 igb_set_vmolr(adapter, vf, true);
4ae196df 6193
a15d9259
AD		 6194 /* Remove any PF assigned VLAN */
6195 if (adapter->vf_data[vf].pf_vlan)
6196 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6197 false, vf);
6f3dc319 6198
a15d9259
AD		 6199 adapter->vf_data[vf].pf_vlan = 0;
6200 adapter->vf_data[vf].pf_qos = 0;
030f9f52 6201 igb_set_vf_vlan_strip(adapter, vf, false);
6f3dc319 6202
a15d9259 6203 return 0;
6f3dc319
GR		 6204}
6205
a15d9259
AD		 6206static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6207 int vf, u16 vlan, u8 qos)
4ae196df 6208{
a15d9259 6209 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 6210
a15d9259
AD		 6211 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6212 return -EINVAL;
6f3dc319 6213
a15d9259
AD		 6214 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6215 igb_disable_port_vlan(adapter, vf);
6216}
6f3dc319 6217
a15d9259
AD		 6218static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6219{
6220 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6221 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
030f9f52 6222 int ret;
6f3dc319 6223
a15d9259
AD		 6224 if (adapter->vf_data[vf].pf_vlan)
6225 return -1;
6f3dc319 6226
a15d9259
AD		 6227 /* VLAN 0 is a special case, don't allow it to be removed */
6228 if (!vid && !add)
6229 return 0;
6230
030f9f52
CV		 6231 ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
6232 if (!ret)
6233 igb_set_vf_vlan_strip(adapter, vf, !!vid);
6234 return ret;
4ae196df
AD		 6235}
6236
f2ca0dbe 6237static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 6238{
a15d9259 6239 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df 6240
a15d9259
AD		 6241 /* clear flags - except flag that indicates PF has set the MAC */
6242 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6243 vf_data->last_nack = jiffies;
4ae196df
AD		 6244
6245 /* reset vlans for device */
6246 igb_clear_vf_vfta(adapter, vf);
a15d9259
AD		 6247 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6248 igb_set_vmvir(adapter, vf_data->pf_vlan |
6249 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6250 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
030f9f52 6251 igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
4ae196df
AD		 6252
6253 /* reset multicast table array for vf */
6254 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6255
6256 /* Flush and reset the mta with the new values */
ff41f8dc 6257 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6258}
6259
f2ca0dbe
AD		 6260static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6261{
6262 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6263
5ac6f91d 6264 /* clear mac address as we were hotplug removed/added */
8151d294 6265 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6266 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6267
6268 /* process remaining reset events */
6269 igb_vf_reset(adapter, vf);
6270}
6271
6272static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6273{
6274 struct e1000_hw *hw = &adapter->hw;
6275 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6276 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6277 u32 reg, msgbuf[3];
6278 u8 *addr = (u8 *)(&msgbuf[1]);
6279
6280 /* process all the same items cleared in a function level reset */
f2ca0dbe 6281 igb_vf_reset(adapter, vf);
4ae196df
AD		 6282
6283 /* set vf mac address */
26ad9178 6284 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6285
6286 /* enable transmit and receive for vf */
6287 reg = rd32(E1000_VFTE);
a51d8c21 6288 wr32(E1000_VFTE, reg | BIT(vf));
4ae196df 6289 reg = rd32(E1000_VFRE);
a51d8c21 6290 wr32(E1000_VFRE, reg | BIT(vf));
4ae196df 6291
8fa7e0f7 6292 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6293
6294 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6295 if (!is_zero_ether_addr(vf_mac)) {
6296 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6297 memcpy(addr, vf_mac, ETH_ALEN);
6298 } else {
6299 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6300 }
4ae196df
AD		 6301 igb_write_mbx(hw, msgbuf, 3, vf);
6302}
6303
6304static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6305{
b980ac18 6306 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6307 * starting at the second 32 bit word of the msg array
6308 */
f2ca0dbe
AD		 6309 unsigned char *addr = (char *)&msg[1];
6310 int err = -1;
4ae196df 6311
f2ca0dbe
AD		 6312 if (is_valid_ether_addr(addr))
6313 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6314
f2ca0dbe 6315 return err;
4ae196df
AD		 6316}
6317
6318static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6319{
6320 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6321 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6322 u32 msg = E1000_VT_MSGTYPE_NACK;
6323
6324 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6325 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6326 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6327 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6328 vf_data->last_nack = jiffies;
4ae196df
AD		 6329 }
6330}
6331
f2ca0dbe 6332static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6333{
f2ca0dbe
AD		 6334 struct pci_dev *pdev = adapter->pdev;
6335 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6336 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6337 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6338 s32 retval;
6339
f2ca0dbe 6340 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6341
fef45f4c
AD		 6342 if (retval) {
6343 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6344 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6345 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6346 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6347 return;
6348 goto out;
6349 }
4ae196df
AD		 6350
6351 /* this is a message we already processed, do nothing */
6352 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6353 return;
4ae196df 6354
b980ac18 6355 /* until the vf completes a reset it should not be
4ae196df
AD		 6356 * allowed to start any configuration.
6357 */
4ae196df
AD		 6358 if (msgbuf[0] == E1000_VF_RESET) {
6359 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6360 return;
4ae196df
AD		 6361 }
6362
f2ca0dbe 6363 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6364 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6365 return;
6366 retval = -1;
6367 goto out;
4ae196df
AD		 6368 }
6369
6370 switch ((msgbuf[0] & 0xFFFF)) {
6371 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6372 retval = -EINVAL;
6373 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6374 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6375 else
6376 dev_warn(&pdev->dev,
b980ac18
JK		 6377 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6378 vf);
4ae196df 6379 break;
7d5753f0
AD		 6380 case E1000_VF_SET_PROMISC:
6381 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6382 break;
4ae196df
AD		 6383 case E1000_VF_SET_MULTICAST:
6384 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6385 break;
6386 case E1000_VF_SET_LPE:
6387 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6388 break;
6389 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6390 retval = -1;
6391 if (vf_data->pf_vlan)
6392 dev_warn(&pdev->dev,
b980ac18
JK		 6393 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6394 vf);
8151d294 6395 else
a15d9259 6396 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
4ae196df
AD		 6397 break;
6398 default:
090b1795 6399 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6400 retval = -1;
6401 break;
6402 }
6403
fef45f4c
AD		 6404 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6405out:
4ae196df
AD		 6406 /* notify the VF of the results of what it sent us */
6407 if (retval)
6408 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6409 else
6410 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6411
4ae196df 6412 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6413}
4ae196df 6414
f2ca0dbe
AD		 6415static void igb_msg_task(struct igb_adapter *adapter)
6416{
6417 struct e1000_hw *hw = &adapter->hw;
6418 u32 vf;
6419
6420 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6421 /* process any reset requests */
6422 if (!igb_check_for_rst(hw, vf))
6423 igb_vf_reset_event(adapter, vf);
6424
6425 /* process any messages pending */
6426 if (!igb_check_for_msg(hw, vf))
6427 igb_rcv_msg_from_vf(adapter, vf);
6428
6429 /* process any acks */
6430 if (!igb_check_for_ack(hw, vf))
6431 igb_rcv_ack_from_vf(adapter, vf);
6432 }
4ae196df
AD		 6433}
6434
68d480c4
AD		 6435/**
6436 * igb_set_uta - Set unicast filter table address
6437 * @adapter: board private structure
bf456abb 6438 * @set: boolean indicating if we are setting or clearing bits
68d480c4
AD		 6439 *
6440 * The unicast table address is a register array of 32-bit registers.
6441 * The table is meant to be used in a way similar to how the MTA is used
6442 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6443 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6444 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4 6445 **/
bf456abb 6446static void igb_set_uta(struct igb_adapter *adapter, bool set)
68d480c4
AD		 6447{
6448 struct e1000_hw *hw = &adapter->hw;
bf456abb 6449 u32 uta = set ? ~0 : 0;
68d480c4
AD		 6450 int i;
6451
68d480c4
AD		 6452 /* we only need to do this if VMDq is enabled */
6453 if (!adapter->vfs_allocated_count)
6454 return;
6455
bf456abb
AD		 6456 for (i = hw->mac.uta_reg_count; i--;)
6457 array_wr32(E1000_UTA, i, uta);
68d480c4
AD		 6458}
6459
9d5c8243 6460/**
b980ac18
JK		 6461 * igb_intr_msi - Interrupt Handler
6462 * @irq: interrupt number
6463 * @data: pointer to a network interface device structure
9d5c8243
AK		 6464 **/
6465static irqreturn_t igb_intr_msi(int irq, void *data)
6466{
047e0030
AD		 6467 struct igb_adapter *adapter = data;
6468 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6469 struct e1000_hw *hw = &adapter->hw;
6470 /* read ICR disables interrupts using IAM */
6471 u32 icr = rd32(E1000_ICR);
6472
047e0030 6473 igb_write_itr(q_vector);
9d5c8243 6474
7f081d40
AD		 6475 if (icr & E1000_ICR_DRSTA)
6476 schedule_work(&adapter->reset_task);
6477
047e0030 6478 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6479 /* HW is reporting DMA is out of sync */
6480 adapter->stats.doosync++;
6481 }
6482
9d5c8243
AK		 6483 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6484 hw->mac.get_link_status = 1;
6485 if (!test_bit(__IGB_DOWN, &adapter->state))
6486 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6487 }
6488
61d7f75f
RC		 6489 if (icr & E1000_ICR_TS)
6490 igb_tsync_interrupt(adapter);
1f6e8178 6491
047e0030 6492 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6493
6494 return IRQ_HANDLED;
6495}
6496
6497/**
b980ac18
JK		 6498 * igb_intr - Legacy Interrupt Handler
6499 * @irq: interrupt number
6500 * @data: pointer to a network interface device structure
9d5c8243
AK		 6501 **/
6502static irqreturn_t igb_intr(int irq, void *data)
6503{
047e0030
AD		 6504 struct igb_adapter *adapter = data;
6505 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6506 struct e1000_hw *hw = &adapter->hw;
6507 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6508 * need for the IMC write
6509 */
9d5c8243 6510 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6511
6512 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6513 * not set, then the adapter didn't send an interrupt
6514 */
9d5c8243
AK		 6515 if (!(icr & E1000_ICR_INT_ASSERTED))
6516 return IRQ_NONE;
6517
0ba82994
AD		 6518 igb_write_itr(q_vector);
6519
7f081d40
AD		 6520 if (icr & E1000_ICR_DRSTA)
6521 schedule_work(&adapter->reset_task);
6522
047e0030 6523 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6524 /* HW is reporting DMA is out of sync */
6525 adapter->stats.doosync++;
6526 }
6527
9d5c8243
AK		 6528 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6529 hw->mac.get_link_status = 1;
6530 /* guard against interrupt when we're going down */
6531 if (!test_bit(__IGB_DOWN, &adapter->state))
6532 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6533 }
6534
61d7f75f
RC		 6535 if (icr & E1000_ICR_TS)
6536 igb_tsync_interrupt(adapter);
1f6e8178 6537
047e0030 6538 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6539
6540 return IRQ_HANDLED;
6541}
6542
c50b52a0 6543static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6544{
047e0030 6545 struct igb_adapter *adapter = q_vector->adapter;
46544258 6546 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6547
0ba82994
AD		 6548 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6549 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6550 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6551 igb_set_itr(q_vector);
46544258 6552 else
047e0030 6553 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6554 }
6555
46544258 6556 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6557 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6558 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6559 else
6560 igb_irq_enable(adapter);
6561 }
9d5c8243
AK		 6562}
6563
46544258 6564/**
b980ac18
JK		 6565 * igb_poll - NAPI Rx polling callback
6566 * @napi: napi polling structure
6567 * @budget: count of how many packets we should handle
46544258
AD		 6568 **/
6569static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6570{
047e0030 6571 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6572 struct igb_q_vector,
6573 napi);
16eb8815 6574 bool clean_complete = true;
32b3e08f 6575 int work_done = 0;
9d5c8243 6576
421e02f0 6577#ifdef CONFIG_IGB_DCA
047e0030
AD		 6578 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6579 igb_update_dca(q_vector);
fe4506b6 6580#endif
0ba82994 6581 if (q_vector->tx.ring)
7f0ba845 6582 clean_complete = igb_clean_tx_irq(q_vector, budget);
9d5c8243 6583
32b3e08f
JB		 6584 if (q_vector->rx.ring) {
6585 int cleaned = igb_clean_rx_irq(q_vector, budget);
6586
6587 work_done += cleaned;
7f0ba845
AD		 6588 if (cleaned >= budget)
6589 clean_complete = false;
32b3e08f 6590 }
047e0030 6591
16eb8815
AD		 6592 /* If all work not completed, return budget and keep polling */
6593 if (!clean_complete)
6594 return budget;
46544258 6595
9d5c8243 6596 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6597 napi_complete_done(napi, work_done);
16eb8815 6598 igb_ring_irq_enable(q_vector);
9d5c8243 6599
16eb8815 6600 return 0;
9d5c8243 6601}
6d8126f9 6602
9d5c8243 6603/**
b980ac18
JK		 6604 * igb_clean_tx_irq - Reclaim resources after transmit completes
6605 * @q_vector: pointer to q_vector containing needed info
7f0ba845 6606 * @napi_budget: Used to determine if we are in netpoll
49ce9c2c 6607 *
b980ac18 6608 * returns true if ring is completely cleaned
9d5c8243 6609 **/
7f0ba845 6610static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
9d5c8243 6611{
047e0030 6612 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6613 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6614 struct igb_tx_buffer *tx_buffer;
f4128785 6615 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6616 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6617 unsigned int budget = q_vector->tx.work_limit;
8542db05 6618 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6619
13fde97a
AD		 6620 if (test_bit(__IGB_DOWN, &adapter->state))
6621 return true;
0e014cb1 6622
06034649 6623 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6624 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6625 i -= tx_ring->count;
9d5c8243 6626
f4128785
AD		 6627 do {
6628 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6629
6630 /* if next_to_watch is not set then there is no work pending */
6631 if (!eop_desc)
6632 break;
13fde97a 6633
f4128785 6634 /* prevent any other reads prior to eop_desc */
70d289bc 6635 read_barrier_depends();
f4128785 6636
13fde97a
AD		 6637 /* if DD is not set pending work has not been completed */
6638 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6639 break;
6640
8542db05
AD		 6641 /* clear next_to_watch to prevent false hangs */
6642 tx_buffer->next_to_watch = NULL;
9d5c8243 6643
ebe42d16
AD		 6644 /* update the statistics for this packet */
6645 total_bytes += tx_buffer->bytecount;
6646 total_packets += tx_buffer->gso_segs;
13fde97a 6647
ebe42d16 6648 /* free the skb */
7f0ba845 6649 napi_consume_skb(tx_buffer->skb, napi_budget);
13fde97a 6650
ebe42d16
AD		 6651 /* unmap skb header data */
6652 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6653 dma_unmap_addr(tx_buffer, dma),
6654 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6655 DMA_TO_DEVICE);
6656
c9f14bf3
AD		 6657 /* clear tx_buffer data */
6658 tx_buffer->skb = NULL;
6659 dma_unmap_len_set(tx_buffer, len, 0);
6660
ebe42d16
AD		 6661 /* clear last DMA location and unmap remaining buffers */
6662 while (tx_desc != eop_desc) {
13fde97a
AD		 6663 tx_buffer++;
6664 tx_desc++;
9d5c8243 6665 i++;
8542db05
AD		 6666 if (unlikely(!i)) {
6667 i -= tx_ring->count;
06034649 6668 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6669 tx_desc = IGB_TX_DESC(tx_ring, 0);
6670 }
ebe42d16
AD		 6671
6672 /* unmap any remaining paged data */
c9f14bf3 6673 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6674 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6675 dma_unmap_addr(tx_buffer, dma),
6676 dma_unmap_len(tx_buffer, len),
ebe42d16 6677 DMA_TO_DEVICE);
c9f14bf3 6678 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6679 }
6680 }
6681
ebe42d16
AD		 6682 /* move us one more past the eop_desc for start of next pkt */
6683 tx_buffer++;
6684 tx_desc++;
6685 i++;
6686 if (unlikely(!i)) {
6687 i -= tx_ring->count;
6688 tx_buffer = tx_ring->tx_buffer_info;
6689 tx_desc = IGB_TX_DESC(tx_ring, 0);
6690 }
f4128785
AD		 6691
6692 /* issue prefetch for next Tx descriptor */
6693 prefetch(tx_desc);
6694
6695 /* update budget accounting */
6696 budget--;
6697 } while (likely(budget));
0e014cb1 6698
bdbc0631
ED		 6699 netdev_tx_completed_queue(txring_txq(tx_ring),
6700 total_packets, total_bytes);
8542db05 6701 i += tx_ring->count;
9d5c8243 6702 tx_ring->next_to_clean = i;
13fde97a
AD		 6703 u64_stats_update_begin(&tx_ring->tx_syncp);
6704 tx_ring->tx_stats.bytes += total_bytes;
6705 tx_ring->tx_stats.packets += total_packets;
6706 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6707 q_vector->tx.total_bytes += total_bytes;
6708 q_vector->tx.total_packets += total_packets;
9d5c8243 6709
6d095fa8 6710 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6711 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6712
9d5c8243 6713 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6714 * check with the clearing of time_stamp and movement of i
6715 */
6d095fa8 6716 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6717 if (tx_buffer->next_to_watch &&
8542db05 6718 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6719 (adapter->tx_timeout_factor * HZ)) &&
6720 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6721
9d5c8243 6722 /* detected Tx unit hang */
59d71989 6723 dev_err(tx_ring->dev,
9d5c8243 6724 "Detected Tx Unit Hang\n"
2d064c06 6725 " Tx Queue <%d>\n"
9d5c8243
AK		 6726 " TDH <%x>\n"
6727 " TDT <%x>\n"
6728 " next_to_use <%x>\n"
6729 " next_to_clean <%x>\n"
9d5c8243
AK		 6730 "buffer_info[next_to_clean]\n"
6731 " time_stamp <%lx>\n"
8542db05 6732 " next_to_watch <%p>\n"
9d5c8243
AK		 6733 " jiffies <%lx>\n"
6734 " desc.status <%x>\n",
2d064c06 6735 tx_ring->queue_index,
238ac817 6736 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6737 readl(tx_ring->tail),
9d5c8243
AK		 6738 tx_ring->next_to_use,
6739 tx_ring->next_to_clean,
8542db05 6740 tx_buffer->time_stamp,
f4128785 6741 tx_buffer->next_to_watch,
9d5c8243 6742 jiffies,
f4128785 6743 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6744 netif_stop_subqueue(tx_ring->netdev,
6745 tx_ring->queue_index);
6746
6747 /* we are about to reset, no point in enabling stuff */
6748 return true;
9d5c8243
AK		 6749 }
6750 }
13fde97a 6751
21ba6fe1 6752#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6753 if (unlikely(total_packets &&
b980ac18
JK		 6754 netif_carrier_ok(tx_ring->netdev) &&
6755 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6756 /* Make sure that anybody stopping the queue after this
6757 * sees the new next_to_clean.
6758 */
6759 smp_mb();
6760 if (__netif_subqueue_stopped(tx_ring->netdev,
6761 tx_ring->queue_index) &&
6762 !(test_bit(__IGB_DOWN, &adapter->state))) {
6763 netif_wake_subqueue(tx_ring->netdev,
6764 tx_ring->queue_index);
6765
6766 u64_stats_update_begin(&tx_ring->tx_syncp);
6767 tx_ring->tx_stats.restart_queue++;
6768 u64_stats_update_end(&tx_ring->tx_syncp);
6769 }
6770 }
6771
6772 return !!budget;
9d5c8243
AK		 6773}
6774
cbc8e55f 6775/**
b980ac18
JK		 6776 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6777 * @rx_ring: rx descriptor ring to store buffers on
6778 * @old_buff: donor buffer to have page reused
cbc8e55f 6779 *
b980ac18 6780 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6781 **/
6782static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6783 struct igb_rx_buffer *old_buff)
6784{
6785 struct igb_rx_buffer *new_buff;
6786 u16 nta = rx_ring->next_to_alloc;
6787
6788 new_buff = &rx_ring->rx_buffer_info[nta];
6789
6790 /* update, and store next to alloc */
6791 nta++;
6792 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6793
6794 /* transfer page from old buffer to new buffer */
a1f63473 6795 *new_buff = *old_buff;
cbc8e55f
AD		 6796
6797 /* sync the buffer for use by the device */
6798 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6799 old_buff->page_offset,
de78d1f9 6800 IGB_RX_BUFSZ,
cbc8e55f
AD		 6801 DMA_FROM_DEVICE);
6802}
6803
95dd44b4
AD		 6804static inline bool igb_page_is_reserved(struct page *page)
6805{
2f064f34 6806 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6807}
6808
74e238ea
AD		 6809static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6810 struct page *page,
6811 unsigned int truesize)
6812{
6813 /* avoid re-using remote pages */
95dd44b4 6814 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6815 return false;
6816
74e238ea
AD		 6817#if (PAGE_SIZE < 8192)
6818 /* if we are only owner of page we can reuse it */
6819 if (unlikely(page_count(page) != 1))
6820 return false;
6821
6822 /* flip page offset to other buffer */
6823 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6824#else
6825 /* move offset up to the next cache line */
6826 rx_buffer->page_offset += truesize;
6827
6828 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6829 return false;
74e238ea
AD		 6830#endif
6831
95dd44b4
AD		 6832 /* Even if we own the page, we are not allowed to use atomic_set()
6833 * This would break get_page_unless_zero() users.
6834 */
fe896d18 6835 page_ref_inc(page);
95dd44b4 6836
74e238ea
AD		 6837 return true;
6838}
6839
cbc8e55f 6840/**
b980ac18
JK		 6841 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6842 * @rx_ring: rx descriptor ring to transact packets on
6843 * @rx_buffer: buffer containing page to add
6844 * @rx_desc: descriptor containing length of buffer written by hardware
6845 * @skb: sk_buff to place the data into
cbc8e55f 6846 *
b980ac18
JK		 6847 * This function will add the data contained in rx_buffer->page to the skb.
6848 * This is done either through a direct copy if the data in the buffer is
6849 * less than the skb header size, otherwise it will just attach the page as
6850 * a frag to the skb.
cbc8e55f 6851 *
b980ac18
JK		 6852 * The function will then update the page offset if necessary and return
6853 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6854 **/
6855static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6856 struct igb_rx_buffer *rx_buffer,
6857 union e1000_adv_rx_desc *rx_desc,
6858 struct sk_buff *skb)
6859{
6860 struct page *page = rx_buffer->page;
f56e7bba 6861 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6862 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6863#if (PAGE_SIZE < 8192)
6864 unsigned int truesize = IGB_RX_BUFSZ;
6865#else
f56e7bba 6866 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6867#endif
f56e7bba 6868 unsigned int pull_len;
cbc8e55f 6869
f56e7bba
AD		 6870 if (unlikely(skb_is_nonlinear(skb)))
6871 goto add_tail_frag;
cbc8e55f 6872
f56e7bba
AD		 6873 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6874 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6875 va += IGB_TS_HDR_LEN;
6876 size -= IGB_TS_HDR_LEN;
6877 }
cbc8e55f 6878
f56e7bba 6879 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6880 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6881
95dd44b4
AD		 6882 /* page is not reserved, we can reuse buffer as-is */
6883 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6884 return true;
6885
6886 /* this page cannot be reused so discard it */
95dd44b4 6887 __free_page(page);
cbc8e55f
AD		 6888 return false;
6889 }
6890
f56e7bba
AD		 6891 /* we need the header to contain the greater of either ETH_HLEN or
6892 * 60 bytes if the skb->len is less than 60 for skb_pad.
6893 */
6894 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6895
6896 /* align pull length to size of long to optimize memcpy performance */
6897 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6898
6899 /* update all of the pointers */
6900 va += pull_len;
6901 size -= pull_len;
6902
6903add_tail_frag:
cbc8e55f 6904 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6905 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6906
74e238ea
AD		 6907 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6908}
cbc8e55f 6909
2e334eee
AD		 6910static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6911 union e1000_adv_rx_desc *rx_desc,
6912 struct sk_buff *skb)
6913{
6914 struct igb_rx_buffer *rx_buffer;
6915 struct page *page;
6916
6917 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6918 page = rx_buffer->page;
6919 prefetchw(page);
6920
6921 if (likely(!skb)) {
6922 void *page_addr = page_address(page) +
6923 rx_buffer->page_offset;
6924
6925 /* prefetch first cache line of first page */
6926 prefetch(page_addr);
6927#if L1_CACHE_BYTES < 128
6928 prefetch(page_addr + L1_CACHE_BYTES);
6929#endif
6930
6931 /* allocate a skb to store the frags */
67fd893e 6932 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6933 if (unlikely(!skb)) {
6934 rx_ring->rx_stats.alloc_failed++;
6935 return NULL;
6936 }
6937
b980ac18 6938 /* we will be copying header into skb->data in
2e334eee
AD		 6939 * pskb_may_pull so it is in our interest to prefetch
6940 * it now to avoid a possible cache miss
6941 */
6942 prefetchw(skb->data);
6943 }
6944
6945 /* we are reusing so sync this buffer for CPU use */
6946 dma_sync_single_range_for_cpu(rx_ring->dev,
6947 rx_buffer->dma,
6948 rx_buffer->page_offset,
de78d1f9 6949 IGB_RX_BUFSZ,
2e334eee
AD		 6950 DMA_FROM_DEVICE);
6951
6952 /* pull page into skb */
6953 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6954 /* hand second half of page back to the ring */
6955 igb_reuse_rx_page(rx_ring, rx_buffer);
6956 } else {
6957 /* we are not reusing the buffer so unmap it */
6958 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6959 PAGE_SIZE, DMA_FROM_DEVICE);
6960 }
6961
6962 /* clear contents of rx_buffer */
6963 rx_buffer->page = NULL;
6964
6965 return skb;
6966}
6967
cd392f5c 6968static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6969 union e1000_adv_rx_desc *rx_desc,
6970 struct sk_buff *skb)
9d5c8243 6971{
bc8acf2c 6972 skb_checksum_none_assert(skb);
9d5c8243 6973
294e7d78 6974 /* Ignore Checksum bit is set */
3ceb90fd 6975 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6976 return;
6977
6978 /* Rx checksum disabled via ethtool */
6979 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6980 return;
85ad76b2 6981
9d5c8243 6982 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6983 if (igb_test_staterr(rx_desc,
6984 E1000_RXDEXT_STATERR_TCPE |
6985 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6986 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6987 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6988 * packets, (aka let the stack check the crc32c)
6989 */
866cff06
AD		 6990 if (!((skb->len == 60) &&
6991 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6992 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6993 ring->rx_stats.csum_err++;
12dcd86b
ED		 6994 u64_stats_update_end(&ring->rx_syncp);
6995 }
9d5c8243 6996 /* let the stack verify checksum errors */
9d5c8243
AK		 6997 return;
6998 }
6999 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 7000 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
7001 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 7002 skb->ip_summed = CHECKSUM_UNNECESSARY;
7003
3ceb90fd
AD		 7004 dev_dbg(ring->dev, "cksum success: bits %08X\n",
7005 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 7006}
7007
077887c3
AD		 7008static inline void igb_rx_hash(struct igb_ring *ring,
7009 union e1000_adv_rx_desc *rx_desc,
7010 struct sk_buff *skb)
7011{
7012 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 7013 skb_set_hash(skb,
7014 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
7015 PKT_HASH_TYPE_L3);
077887c3
AD		 7016}
7017
2e334eee 7018/**
b980ac18
JK		 7019 * igb_is_non_eop - process handling of non-EOP buffers
7020 * @rx_ring: Rx ring being processed
7021 * @rx_desc: Rx descriptor for current buffer
7022 * @skb: current socket buffer containing buffer in progress
2e334eee 7023 *
b980ac18
JK		 7024 * This function updates next to clean. If the buffer is an EOP buffer
7025 * this function exits returning false, otherwise it will place the
7026 * sk_buff in the next buffer to be chained and return true indicating
7027 * that this is in fact a non-EOP buffer.
2e334eee
AD		 7028 **/
7029static bool igb_is_non_eop(struct igb_ring *rx_ring,
7030 union e1000_adv_rx_desc *rx_desc)
7031{
7032 u32 ntc = rx_ring->next_to_clean + 1;
7033
7034 /* fetch, update, and store next to clean */
7035 ntc = (ntc < rx_ring->count) ? ntc : 0;
7036 rx_ring->next_to_clean = ntc;
7037
7038 prefetch(IGB_RX_DESC(rx_ring, ntc));
7039
7040 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
7041 return false;
7042
7043 return true;
7044}
7045
1a1c225b 7046/**
b980ac18
JK		 7047 * igb_cleanup_headers - Correct corrupted or empty headers
7048 * @rx_ring: rx descriptor ring packet is being transacted on
7049 * @rx_desc: pointer to the EOP Rx descriptor
7050 * @skb: pointer to current skb being fixed
1a1c225b 7051 *
b980ac18
JK		 7052 * Address the case where we are pulling data in on pages only
7053 * and as such no data is present in the skb header.
1a1c225b 7054 *
b980ac18
JK		 7055 * In addition if skb is not at least 60 bytes we need to pad it so that
7056 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 7057 *
b980ac18 7058 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 7059 **/
7060static bool igb_cleanup_headers(struct igb_ring *rx_ring,
7061 union e1000_adv_rx_desc *rx_desc,
7062 struct sk_buff *skb)
7063{
1a1c225b
AD		 7064 if (unlikely((igb_test_staterr(rx_desc,
7065 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
7066 struct net_device *netdev = rx_ring->netdev;
7067 if (!(netdev->features & NETIF_F_RXALL)) {
7068 dev_kfree_skb_any(skb);
7069 return true;
7070 }
7071 }
7072
a94d9e22
AD		 7073 /* if eth_skb_pad returns an error the skb was freed */
7074 if (eth_skb_pad(skb))
7075 return true;
1a1c225b
AD		 7076
7077 return false;
2d94d8ab
AD		 7078}
7079
db2ee5bd 7080/**
b980ac18
JK		 7081 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
7082 * @rx_ring: rx descriptor ring packet is being transacted on
7083 * @rx_desc: pointer to the EOP Rx descriptor
7084 * @skb: pointer to current skb being populated
db2ee5bd 7085 *
b980ac18
JK		 7086 * This function checks the ring, descriptor, and packet information in
7087 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
7088 * other fields within the skb.
db2ee5bd
AD		 7089 **/
7090static void igb_process_skb_fields(struct igb_ring *rx_ring,
7091 union e1000_adv_rx_desc *rx_desc,
7092 struct sk_buff *skb)
7093{
7094 struct net_device *dev = rx_ring->netdev;
7095
7096 igb_rx_hash(rx_ring, rx_desc, skb);
7097
7098 igb_rx_checksum(rx_ring, rx_desc, skb);
7099
5499a968
JK		 7100 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7101 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7102 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 7103
f646968f 7104 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 7105 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7106 u16 vid;
9005df38 7107
db2ee5bd
AD		 7108 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7109 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7110 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7111 else
7112 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7113
86a9bad3 7114 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 7115 }
7116
7117 skb_record_rx_queue(skb, rx_ring->queue_index);
7118
7119 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7120}
7121
32b3e08f 7122static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 7123{
0ba82994 7124 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 7125 struct sk_buff *skb = rx_ring->skb;
9d5c8243 7126 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 7127 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 7128
57ba34c9 7129 while (likely(total_packets < budget)) {
2e334eee 7130 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7131
2e334eee
AD		 7132 /* return some buffers to hardware, one at a time is too slow */
7133 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7134 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7135 cleaned_count = 0;
7136 }
bf36c1a0 7137
2e334eee 7138 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7139
124b74c1 7140 if (!rx_desc->wb.upper.status_error)
2e334eee 7141 break;
9d5c8243 7142
74e238ea
AD		 7143 /* This memory barrier is needed to keep us from reading
7144 * any other fields out of the rx_desc until we know the
124b74c1 7145 * descriptor has been written back
74e238ea 7146 */
124b74c1 7147 dma_rmb();
74e238ea 7148
2e334eee 7149 /* retrieve a buffer from the ring */
f9d40f6a 7150 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7151
2e334eee
AD		 7152 /* exit if we failed to retrieve a buffer */
7153 if (!skb)
7154 break;
1a1c225b 7155
2e334eee 7156 cleaned_count++;
1a1c225b 7157
2e334eee
AD		 7158 /* fetch next buffer in frame if non-eop */
7159 if (igb_is_non_eop(rx_ring, rx_desc))
7160 continue;
1a1c225b
AD		 7161
7162 /* verify the packet layout is correct */
7163 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7164 skb = NULL;
7165 continue;
9d5c8243 7166 }
9d5c8243 7167
db2ee5bd 7168 /* probably a little skewed due to removing CRC */
3ceb90fd 7169 total_bytes += skb->len;
3ceb90fd 7170
db2ee5bd
AD		 7171 /* populate checksum, timestamp, VLAN, and protocol */
7172 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7173
b2cb09b1 7174 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7175
1a1c225b
AD		 7176 /* reset skb pointer */
7177 skb = NULL;
7178
2e334eee
AD		 7179 /* update budget accounting */
7180 total_packets++;
57ba34c9 7181 }
bf36c1a0 7182
1a1c225b
AD		 7183 /* place incomplete frames back on ring for completion */
7184 rx_ring->skb = skb;
7185
12dcd86b 7186 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7187 rx_ring->rx_stats.packets += total_packets;
7188 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7189 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7190 q_vector->rx.total_packets += total_packets;
7191 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7192
7193 if (cleaned_count)
cd392f5c 7194 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7195
32b3e08f 7196 return total_packets;
9d5c8243
AK		 7197}
7198
c023cd88 7199static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7200 struct igb_rx_buffer *bi)
c023cd88
AD		 7201{
7202 struct page *page = bi->page;
cbc8e55f 7203 dma_addr_t dma;
c023cd88 7204
cbc8e55f
AD		 7205 /* since we are recycling buffers we should seldom need to alloc */
7206 if (likely(page))
c023cd88
AD		 7207 return true;
7208
cbc8e55f 7209 /* alloc new page for storage */
42b17f09 7210 page = dev_alloc_page();
cbc8e55f
AD		 7211 if (unlikely(!page)) {
7212 rx_ring->rx_stats.alloc_failed++;
7213 return false;
c023cd88
AD		 7214 }
7215
cbc8e55f
AD		 7216 /* map page for use */
7217 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7218
b980ac18 7219 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7220 * there isn't much point in holding memory we can't use
7221 */
1a1c225b 7222 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7223 __free_page(page);
7224
c023cd88
AD		 7225 rx_ring->rx_stats.alloc_failed++;
7226 return false;
7227 }
7228
1a1c225b 7229 bi->dma = dma;
cbc8e55f
AD		 7230 bi->page = page;
7231 bi->page_offset = 0;
1a1c225b 7232
c023cd88
AD		 7233 return true;
7234}
7235
9d5c8243 7236/**
b980ac18
JK		 7237 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7238 * @adapter: address of board private structure
9d5c8243 7239 **/
cd392f5c 7240void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7241{
9d5c8243 7242 union e1000_adv_rx_desc *rx_desc;
06034649 7243 struct igb_rx_buffer *bi;
c023cd88 7244 u16 i = rx_ring->next_to_use;
9d5c8243 7245
cbc8e55f
AD		 7246 /* nothing to do */
7247 if (!cleaned_count)
7248 return;
7249
60136906 7250 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7251 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7252 i -= rx_ring->count;
9d5c8243 7253
cbc8e55f 7254 do {
1a1c225b 7255 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7256 break;
9d5c8243 7257
b980ac18 7258 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7259 * because each write-back erases this info.
7260 */
f9d40f6a 7261 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7262
c023cd88
AD		 7263 rx_desc++;
7264 bi++;
9d5c8243 7265 i++;
c023cd88 7266 if (unlikely(!i)) {
60136906 7267 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7268 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7269 i -= rx_ring->count;
7270 }
7271
95dd44b4
AD		 7272 /* clear the status bits for the next_to_use descriptor */
7273 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7274
7275 cleaned_count--;
7276 } while (cleaned_count);
9d5c8243 7277
c023cd88
AD		 7278 i += rx_ring->count;
7279
9d5c8243 7280 if (rx_ring->next_to_use != i) {
cbc8e55f 7281 /* record the next descriptor to use */
9d5c8243 7282 rx_ring->next_to_use = i;
9d5c8243 7283
cbc8e55f
AD		 7284 /* update next to alloc since we have filled the ring */
7285 rx_ring->next_to_alloc = i;
7286
b980ac18 7287 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7288 * know there are new descriptors to fetch. (Only
7289 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7290 * such as IA-64).
7291 */
9d5c8243 7292 wmb();
fce99e34 7293 writel(i, rx_ring->tail);
9d5c8243
AK		 7294 }
7295}
7296
7297/**
7298 * igb_mii_ioctl -
7299 * @netdev:
7300 * @ifreq:
7301 * @cmd:
7302 **/
7303static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7304{
7305 struct igb_adapter *adapter = netdev_priv(netdev);
7306 struct mii_ioctl_data *data = if_mii(ifr);
7307
7308 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7309 return -EOPNOTSUPP;
7310
7311 switch (cmd) {
7312 case SIOCGMIIPHY:
7313 data->phy_id = adapter->hw.phy.addr;
7314 break;
7315 case SIOCGMIIREG:
f5f4cf08 7316 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7317 &data->val_out))
9d5c8243
AK		 7318 return -EIO;
7319 break;
7320 case SIOCSMIIREG:
7321 default:
7322 return -EOPNOTSUPP;
7323 }
7324 return 0;
7325}
7326
7327/**
7328 * igb_ioctl -
7329 * @netdev:
7330 * @ifreq:
7331 * @cmd:
7332 **/
7333static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7334{
7335 switch (cmd) {
7336 case SIOCGMIIPHY:
7337 case SIOCGMIIREG:
7338 case SIOCSMIIREG:
7339 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7340 case SIOCGHWTSTAMP:
7341 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7342 case SIOCSHWTSTAMP:
6ab5f7b2 7343 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7344 default:
7345 return -EOPNOTSUPP;
7346 }
7347}
7348
94826487
TF		 7349void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7350{
7351 struct igb_adapter *adapter = hw->back;
7352
7353 pci_read_config_word(adapter->pdev, reg, value);
7354}
7355
7356void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7357{
7358 struct igb_adapter *adapter = hw->back;
7359
7360 pci_write_config_word(adapter->pdev, reg, *value);
7361}
7362
009bc06e
AD		 7363s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7364{
7365 struct igb_adapter *adapter = hw->back;
009bc06e 7366
23d028cc 7367 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7368 return -E1000_ERR_CONFIG;
7369
009bc06e
AD		 7370 return 0;
7371}
7372
7373s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7374{
7375 struct igb_adapter *adapter = hw->back;
009bc06e 7376
23d028cc 7377 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7378 return -E1000_ERR_CONFIG;
7379
009bc06e
AD		 7380 return 0;
7381}
7382
c8f44aff 7383static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7384{
7385 struct igb_adapter *adapter = netdev_priv(netdev);
7386 struct e1000_hw *hw = &adapter->hw;
7387 u32 ctrl, rctl;
f646968f 7388 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7389
5faf030c 7390 if (enable) {
9d5c8243
AK		 7391 /* enable VLAN tag insert/strip */
7392 ctrl = rd32(E1000_CTRL);
7393 ctrl |= E1000_CTRL_VME;
7394 wr32(E1000_CTRL, ctrl);
7395
51466239 7396 /* Disable CFI check */
9d5c8243 7397 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7398 rctl &= ~E1000_RCTL_CFIEN;
7399 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7400 } else {
7401 /* disable VLAN tag insert/strip */
7402 ctrl = rd32(E1000_CTRL);
7403 ctrl &= ~E1000_CTRL_VME;
7404 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7405 }
7406
030f9f52 7407 igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
9d5c8243
AK		 7408}
7409
80d5c368
PM		 7410static int igb_vlan_rx_add_vid(struct net_device *netdev,
7411 __be16 proto, u16 vid)
9d5c8243
AK		 7412{
7413 struct igb_adapter *adapter = netdev_priv(netdev);
7414 struct e1000_hw *hw = &adapter->hw;
4ae196df 7415 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7416
51466239 7417 /* add the filter since PF can receive vlans w/o entry in vlvf */
16903caa
AD		 7418 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7419 igb_vfta_set(hw, vid, pf_id, true, !!vid);
b2cb09b1
JP		 7420
7421 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7422
7423 return 0;
9d5c8243
AK		 7424}
7425
80d5c368
PM		 7426static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7427 __be16 proto, u16 vid)
9d5c8243
AK		 7428{
7429 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 7430 int pf_id = adapter->vfs_allocated_count;
8b77c6b2 7431 struct e1000_hw *hw = &adapter->hw;
9d5c8243 7432
8b77c6b2 7433 /* remove VID from filter table */
16903caa
AD		 7434 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7435 igb_vfta_set(hw, vid, pf_id, false, true);
b2cb09b1
JP		 7436
7437 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7438
7439 return 0;
9d5c8243
AK		 7440}
7441
7442static void igb_restore_vlan(struct igb_adapter *adapter)
7443{
5982a556 7444 u16 vid = 1;
9d5c8243 7445
5faf030c 7446 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
5982a556 7447 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
5faf030c 7448
5982a556 7449 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7450 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7451}
7452
14ad2513 7453int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7454{
090b1795 7455 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7456 struct e1000_mac_info *mac = &adapter->hw.mac;
7457
7458 mac->autoneg = 0;
7459
14ad2513 7460 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7461 * for the switch() below to work
7462 */
14ad2513
DD		 7463 if ((spd & 1) || (dplx & ~1))
7464 goto err_inval;
7465
f502ef7d
AA		 7466 /* Fiber NIC's only allow 1000 gbps Full duplex
7467 * and 100Mbps Full duplex for 100baseFx sfp
7468 */
7469 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7470 switch (spd + dplx) {
7471 case SPEED_10 + DUPLEX_HALF:
7472 case SPEED_10 + DUPLEX_FULL:
7473 case SPEED_100 + DUPLEX_HALF:
7474 goto err_inval;
7475 default:
7476 break;
7477 }
7478 }
cd2638a8 7479
14ad2513 7480 switch (spd + dplx) {
9d5c8243
AK		 7481 case SPEED_10 + DUPLEX_HALF:
7482 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7483 break;
7484 case SPEED_10 + DUPLEX_FULL:
7485 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7486 break;
7487 case SPEED_100 + DUPLEX_HALF:
7488 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7489 break;
7490 case SPEED_100 + DUPLEX_FULL:
7491 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7492 break;
7493 case SPEED_1000 + DUPLEX_FULL:
7494 mac->autoneg = 1;
7495 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7496 break;
7497 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7498 default:
14ad2513 7499 goto err_inval;
9d5c8243 7500 }
8376dad0
JB		 7501
7502 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7503 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7504
9d5c8243 7505 return 0;
14ad2513
DD		 7506
7507err_inval:
7508 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7509 return -EINVAL;
9d5c8243
AK		 7510}
7511
749ab2cd
YZ		 7512static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7513 bool runtime)
9d5c8243
AK		 7514{
7515 struct net_device *netdev = pci_get_drvdata(pdev);
7516 struct igb_adapter *adapter = netdev_priv(netdev);
7517 struct e1000_hw *hw = &adapter->hw;
2d064c06 7518 u32 ctrl, rctl, status;
749ab2cd 7519 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7520#ifdef CONFIG_PM
7521 int retval = 0;
7522#endif
7523
7524 netif_device_detach(netdev);
7525
a88f10ec 7526 if (netif_running(netdev))
749ab2cd 7527 __igb_close(netdev, true);
a88f10ec 7528
047e0030 7529 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7530
7531#ifdef CONFIG_PM
7532 retval = pci_save_state(pdev);
7533 if (retval)
7534 return retval;
7535#endif
7536
7537 status = rd32(E1000_STATUS);
7538 if (status & E1000_STATUS_LU)
7539 wufc &= ~E1000_WUFC_LNKC;
7540
7541 if (wufc) {
7542 igb_setup_rctl(adapter);
ff41f8dc 7543 igb_set_rx_mode(netdev);
9d5c8243
AK		 7544
7545 /* turn on all-multi mode if wake on multicast is enabled */
7546 if (wufc & E1000_WUFC_MC) {
7547 rctl = rd32(E1000_RCTL);
7548 rctl |= E1000_RCTL_MPE;
7549 wr32(E1000_RCTL, rctl);
7550 }
7551
7552 ctrl = rd32(E1000_CTRL);
7553 /* advertise wake from D3Cold */
7554 #define E1000_CTRL_ADVD3WUC 0x00100000
7555 /* phy power management enable */
7556 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7557 ctrl |= E1000_CTRL_ADVD3WUC;
7558 wr32(E1000_CTRL, ctrl);
7559
9d5c8243 7560 /* Allow time for pending master requests to run */
330a6d6a 7561 igb_disable_pcie_master(hw);
9d5c8243
AK		 7562
7563 wr32(E1000_WUC, E1000_WUC_PME_EN);
7564 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7565 } else {
7566 wr32(E1000_WUC, 0);
7567 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7568 }
7569
3fe7c4c9
RW		 7570 *enable_wake = wufc || adapter->en_mng_pt;
7571 if (!*enable_wake)
88a268c1
NN		 7572 igb_power_down_link(adapter);
7573 else
7574 igb_power_up_link(adapter);
9d5c8243
AK		 7575
7576 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7577 * would have already happened in close and is redundant.
7578 */
9d5c8243
AK		 7579 igb_release_hw_control(adapter);
7580
7581 pci_disable_device(pdev);
7582
9d5c8243
AK		 7583 return 0;
7584}
7585
7586#ifdef CONFIG_PM
d9dd966d 7587#ifdef CONFIG_PM_SLEEP
749ab2cd 7588static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7589{
7590 int retval;
7591 bool wake;
749ab2cd 7592 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7593
749ab2cd 7594 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7595 if (retval)
7596 return retval;
7597
7598 if (wake) {
7599 pci_prepare_to_sleep(pdev);
7600 } else {
7601 pci_wake_from_d3(pdev, false);
7602 pci_set_power_state(pdev, PCI_D3hot);
7603 }
7604
7605 return 0;
7606}
d9dd966d 7607#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7608
749ab2cd 7609static int igb_resume(struct device *dev)
9d5c8243 7610{
749ab2cd 7611 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7612 struct net_device *netdev = pci_get_drvdata(pdev);
7613 struct igb_adapter *adapter = netdev_priv(netdev);
7614 struct e1000_hw *hw = &adapter->hw;
7615 u32 err;
7616
7617 pci_set_power_state(pdev, PCI_D0);
7618 pci_restore_state(pdev);
b94f2d77 7619 pci_save_state(pdev);
42bfd33a 7620
17a402a0
CW		 7621 if (!pci_device_is_present(pdev))
7622 return -ENODEV;
aed5dec3 7623 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7624 if (err) {
7625 dev_err(&pdev->dev,
7626 "igb: Cannot enable PCI device from suspend\n");
7627 return err;
7628 }
7629 pci_set_master(pdev);
7630
7631 pci_enable_wake(pdev, PCI_D3hot, 0);
7632 pci_enable_wake(pdev, PCI_D3cold, 0);
7633
53c7d064 7634 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7635 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7636 return -ENOMEM;
9d5c8243
AK		 7637 }
7638
9d5c8243 7639 igb_reset(adapter);
a8564f03
AD		 7640
7641 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7642 * driver.
7643 */
a8564f03
AD		 7644 igb_get_hw_control(adapter);
7645
9d5c8243
AK		 7646 wr32(E1000_WUS, ~0);
7647
749ab2cd 7648 if (netdev->flags & IFF_UP) {
0c2cc02e 7649 rtnl_lock();
749ab2cd 7650 err = __igb_open(netdev, true);
0c2cc02e 7651 rtnl_unlock();
a88f10ec
AD		 7652 if (err)
7653 return err;
7654 }
9d5c8243
AK		 7655
7656 netif_device_attach(netdev);
749ab2cd
YZ		 7657 return 0;
7658}
7659
749ab2cd
YZ		 7660static int igb_runtime_idle(struct device *dev)
7661{
7662 struct pci_dev *pdev = to_pci_dev(dev);
7663 struct net_device *netdev = pci_get_drvdata(pdev);
7664 struct igb_adapter *adapter = netdev_priv(netdev);
7665
7666 if (!igb_has_link(adapter))
7667 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7668
7669 return -EBUSY;
7670}
7671
7672static int igb_runtime_suspend(struct device *dev)
7673{
7674 struct pci_dev *pdev = to_pci_dev(dev);
7675 int retval;
7676 bool wake;
7677
7678 retval = __igb_shutdown(pdev, &wake, 1);
7679 if (retval)
7680 return retval;
7681
7682 if (wake) {
7683 pci_prepare_to_sleep(pdev);
7684 } else {
7685 pci_wake_from_d3(pdev, false);
7686 pci_set_power_state(pdev, PCI_D3hot);
7687 }
9d5c8243 7688
9d5c8243
AK		 7689 return 0;
7690}
749ab2cd
YZ		 7691
7692static int igb_runtime_resume(struct device *dev)
7693{
7694 return igb_resume(dev);
7695}
d61c81cb 7696#endif /* CONFIG_PM */
9d5c8243
AK		 7697
7698static void igb_shutdown(struct pci_dev *pdev)
7699{
3fe7c4c9
RW		 7700 bool wake;
7701
749ab2cd 7702 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7703
7704 if (system_state == SYSTEM_POWER_OFF) {
7705 pci_wake_from_d3(pdev, wake);
7706 pci_set_power_state(pdev, PCI_D3hot);
7707 }
9d5c8243
AK		 7708}
7709
fa44f2f1
GR		 7710#ifdef CONFIG_PCI_IOV
7711static int igb_sriov_reinit(struct pci_dev *dev)
7712{
7713 struct net_device *netdev = pci_get_drvdata(dev);
7714 struct igb_adapter *adapter = netdev_priv(netdev);
7715 struct pci_dev *pdev = adapter->pdev;
7716
7717 rtnl_lock();
7718
7719 if (netif_running(netdev))
7720 igb_close(netdev);
76252723
SA		 7721 else
7722 igb_reset(adapter);
fa44f2f1
GR		 7723
7724 igb_clear_interrupt_scheme(adapter);
7725
7726 igb_init_queue_configuration(adapter);
7727
7728 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7729 rtnl_unlock();
fa44f2f1
GR		 7730 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7731 return -ENOMEM;
7732 }
7733
7734 if (netif_running(netdev))
7735 igb_open(netdev);
7736
7737 rtnl_unlock();
7738
7739 return 0;
7740}
7741
7742static int igb_pci_disable_sriov(struct pci_dev *dev)
7743{
7744 int err = igb_disable_sriov(dev);
7745
7746 if (!err)
7747 err = igb_sriov_reinit(dev);
7748
7749 return err;
7750}
7751
7752static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7753{
7754 int err = igb_enable_sriov(dev, num_vfs);
7755
7756 if (err)
7757 goto out;
7758
7759 err = igb_sriov_reinit(dev);
7760 if (!err)
7761 return num_vfs;
7762
7763out:
7764 return err;
7765}
7766
7767#endif
7768static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7769{
7770#ifdef CONFIG_PCI_IOV
7771 if (num_vfs == 0)
7772 return igb_pci_disable_sriov(dev);
7773 else
7774 return igb_pci_enable_sriov(dev, num_vfs);
7775#endif
7776 return 0;
7777}
7778
9d5c8243 7779#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7780/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7781 * without having to re-enable interrupts. It's not called while
7782 * the interrupt routine is executing.
7783 */
7784static void igb_netpoll(struct net_device *netdev)
7785{
7786 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7787 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7788 struct igb_q_vector *q_vector;
9d5c8243 7789 int i;
9d5c8243 7790
047e0030 7791 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7792 q_vector = adapter->q_vector[i];
cd14ef54 7793 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7794 wr32(E1000_EIMC, q_vector->eims_value);
7795 else
7796 igb_irq_disable(adapter);
047e0030 7797 napi_schedule(&q_vector->napi);
eebbbdba 7798 }
9d5c8243
AK		 7799}
7800#endif /* CONFIG_NET_POLL_CONTROLLER */
7801
7802/**
b980ac18
JK		 7803 * igb_io_error_detected - called when PCI error is detected
7804 * @pdev: Pointer to PCI device
7805 * @state: The current pci connection state
9d5c8243 7806 *
b980ac18
JK		 7807 * This function is called after a PCI bus error affecting
7808 * this device has been detected.
7809 **/
9d5c8243
AK		 7810static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7811 pci_channel_state_t state)
7812{
7813 struct net_device *netdev = pci_get_drvdata(pdev);
7814 struct igb_adapter *adapter = netdev_priv(netdev);
7815
7816 netif_device_detach(netdev);
7817
59ed6eec
AD		 7818 if (state == pci_channel_io_perm_failure)
7819 return PCI_ERS_RESULT_DISCONNECT;
7820
9d5c8243
AK		 7821 if (netif_running(netdev))
7822 igb_down(adapter);
7823 pci_disable_device(pdev);
7824
7825 /* Request a slot slot reset. */
7826 return PCI_ERS_RESULT_NEED_RESET;
7827}
7828
7829/**
b980ac18
JK		 7830 * igb_io_slot_reset - called after the pci bus has been reset.
7831 * @pdev: Pointer to PCI device
9d5c8243 7832 *
b980ac18
JK		 7833 * Restart the card from scratch, as if from a cold-boot. Implementation
7834 * resembles the first-half of the igb_resume routine.
7835 **/
9d5c8243
AK		 7836static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7837{
7838 struct net_device *netdev = pci_get_drvdata(pdev);
7839 struct igb_adapter *adapter = netdev_priv(netdev);
7840 struct e1000_hw *hw = &adapter->hw;
40a914fa 7841 pci_ers_result_t result;
42bfd33a 7842 int err;
9d5c8243 7843
aed5dec3 7844 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7845 dev_err(&pdev->dev,
7846 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7847 result = PCI_ERS_RESULT_DISCONNECT;
7848 } else {
7849 pci_set_master(pdev);
7850 pci_restore_state(pdev);
b94f2d77 7851 pci_save_state(pdev);
9d5c8243 7852
40a914fa
AD		 7853 pci_enable_wake(pdev, PCI_D3hot, 0);
7854 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7855
40a914fa
AD		 7856 igb_reset(adapter);
7857 wr32(E1000_WUS, ~0);
7858 result = PCI_ERS_RESULT_RECOVERED;
7859 }
9d5c8243 7860
ea943d41
JK		 7861 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7862 if (err) {
b980ac18
JK		 7863 dev_err(&pdev->dev,
7864 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7865 err);
ea943d41
JK		 7866 /* non-fatal, continue */
7867 }
40a914fa
AD		 7868
7869 return result;
9d5c8243
AK		 7870}
7871
7872/**
b980ac18
JK		 7873 * igb_io_resume - called when traffic can start flowing again.
7874 * @pdev: Pointer to PCI device
9d5c8243 7875 *
b980ac18
JK		 7876 * This callback is called when the error recovery driver tells us that
7877 * its OK to resume normal operation. Implementation resembles the
7878 * second-half of the igb_resume routine.
9d5c8243
AK		 7879 */
7880static void igb_io_resume(struct pci_dev *pdev)
7881{
7882 struct net_device *netdev = pci_get_drvdata(pdev);
7883 struct igb_adapter *adapter = netdev_priv(netdev);
7884
9d5c8243
AK		 7885 if (netif_running(netdev)) {
7886 if (igb_up(adapter)) {
7887 dev_err(&pdev->dev, "igb_up failed after reset\n");
7888 return;
7889 }
7890 }
7891
7892 netif_device_attach(netdev);
7893
7894 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7895 * driver.
7896 */
9d5c8243 7897 igb_get_hw_control(adapter);
9d5c8243
AK		 7898}
7899
26ad9178 7900static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7901 u8 qsel)
26ad9178 7902{
26ad9178 7903 struct e1000_hw *hw = &adapter->hw;
c3278587 7904 u32 rar_low, rar_high;
26ad9178 7905
415cd2a6
AD		 7906 /* HW expects these to be in network order when they are plugged
7907 * into the registers which are little endian. In order to guarantee
7908 * that ordering we need to do an leXX_to_cpup here in order to be
7909 * ready for the byteswap that occurs with writel
26ad9178 7910 */
415cd2a6
AD		 7911 rar_low = le32_to_cpup((__le32 *)(addr));
7912 rar_high = le16_to_cpup((__le16 *)(addr + 4));
26ad9178
AD		 7913
7914 /* Indicate to hardware the Address is Valid. */
7915 rar_high |= E1000_RAH_AV;
7916
7917 if (hw->mac.type == e1000_82575)
7918 rar_high |= E1000_RAH_POOL_1 * qsel;
7919 else
7920 rar_high |= E1000_RAH_POOL_1 << qsel;
7921
7922 wr32(E1000_RAL(index), rar_low);
7923 wrfl();
7924 wr32(E1000_RAH(index), rar_high);
7925 wrfl();
7926}
7927
4ae196df 7928static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7929 int vf, unsigned char *mac_addr)
4ae196df
AD		 7930{
7931 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7932 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7933 * towards the first, as a result a collision should not be possible
7934 */
ff41f8dc 7935 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7936
37680117 7937 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7938
26ad9178 7939 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7940
7941 return 0;
7942}
7943
8151d294
WM		 7944static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7945{
7946 struct igb_adapter *adapter = netdev_priv(netdev);
7947 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7948 return -EINVAL;
7949 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7950 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7951 dev_info(&adapter->pdev->dev,
7952 "Reload the VF driver to make this change effective.");
8151d294 7953 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7954 dev_warn(&adapter->pdev->dev,
7955 "The VF MAC address has been set, but the PF device is not up.\n");
7956 dev_warn(&adapter->pdev->dev,
7957 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7958 }
7959 return igb_set_vf_mac(adapter, vf, mac);
7960}
7961
17dc566c
LL		 7962static int igb_link_mbps(int internal_link_speed)
7963{
7964 switch (internal_link_speed) {
7965 case SPEED_100:
7966 return 100;
7967 case SPEED_1000:
7968 return 1000;
7969 default:
7970 return 0;
7971 }
7972}
7973
7974static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7975 int link_speed)
7976{
7977 int rf_dec, rf_int;
7978 u32 bcnrc_val;
7979
7980 if (tx_rate != 0) {
7981 /* Calculate the rate factor values to set */
7982 rf_int = link_speed / tx_rate;
7983 rf_dec = (link_speed - (rf_int * tx_rate));
a51d8c21 7984 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
b980ac18 7985 tx_rate;
17dc566c
LL		 7986
7987 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7988 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7989 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7990 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7991 } else {
7992 bcnrc_val = 0;
7993 }
7994
7995 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7996 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7997 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7998 */
7999 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 8000 wr32(E1000_RTTBCNRC, bcnrc_val);
8001}
8002
8003static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
8004{
8005 int actual_link_speed, i;
8006 bool reset_rate = false;
8007
8008 /* VF TX rate limit was not set or not supported */
8009 if ((adapter->vf_rate_link_speed == 0) ||
8010 (adapter->hw.mac.type != e1000_82576))
8011 return;
8012
8013 actual_link_speed = igb_link_mbps(adapter->link_speed);
8014 if (actual_link_speed != adapter->vf_rate_link_speed) {
8015 reset_rate = true;
8016 adapter->vf_rate_link_speed = 0;
8017 dev_info(&adapter->pdev->dev,
b980ac18 8018 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 8019 }
8020
8021 for (i = 0; i < adapter->vfs_allocated_count; i++) {
8022 if (reset_rate)
8023 adapter->vf_data[i].tx_rate = 0;
8024
8025 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 8026 adapter->vf_data[i].tx_rate,
8027 actual_link_speed);
17dc566c
LL		 8028 }
8029}
8030
ed616689
SC		 8031static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
8032 int min_tx_rate, int max_tx_rate)
8151d294 8033{
17dc566c
LL		 8034 struct igb_adapter *adapter = netdev_priv(netdev);
8035 struct e1000_hw *hw = &adapter->hw;
8036 int actual_link_speed;
8037
8038 if (hw->mac.type != e1000_82576)
8039 return -EOPNOTSUPP;
8040
ed616689
SC		 8041 if (min_tx_rate)
8042 return -EINVAL;
8043
17dc566c
LL		 8044 actual_link_speed = igb_link_mbps(adapter->link_speed);
8045 if ((vf >= adapter->vfs_allocated_count) ||
8046 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 8047 (max_tx_rate < 0) ||
8048 (max_tx_rate > actual_link_speed))
17dc566c
LL		 8049 return -EINVAL;
8050
8051 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 8052 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
8053 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 8054
8055 return 0;
8151d294
WM		 8056}
8057
70ea4783
LL		 8058static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
8059 bool setting)
8060{
8061 struct igb_adapter *adapter = netdev_priv(netdev);
8062 struct e1000_hw *hw = &adapter->hw;
8063 u32 reg_val, reg_offset;
8064
8065 if (!adapter->vfs_allocated_count)
8066 return -EOPNOTSUPP;
8067
8068 if (vf >= adapter->vfs_allocated_count)
8069 return -EINVAL;
8070
8071 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
8072 reg_val = rd32(reg_offset);
8073 if (setting)
a51d8c21
JK		 8074 reg_val |= (BIT(vf) |
8075 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
70ea4783 8076 else
a51d8c21
JK		 8077 reg_val &= ~(BIT(vf) |
8078 BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
70ea4783
LL		 8079 wr32(reg_offset, reg_val);
8080
8081 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 8082 return 0;
70ea4783
LL		 8083}
8084
8151d294
WM		 8085static int igb_ndo_get_vf_config(struct net_device *netdev,
8086 int vf, struct ifla_vf_info *ivi)
8087{
8088 struct igb_adapter *adapter = netdev_priv(netdev);
8089 if (vf >= adapter->vfs_allocated_count)
8090 return -EINVAL;
8091 ivi->vf = vf;
8092 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 8093 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8094 ivi->min_tx_rate = 0;
8151d294
WM		 8095 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8096 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 8097 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 8098 return 0;
8099}
8100
4ae196df
AD		 8101static void igb_vmm_control(struct igb_adapter *adapter)
8102{
8103 struct e1000_hw *hw = &adapter->hw;
10d8e907 8104 u32 reg;
4ae196df 8105
52a1dd4d
AD		 8106 switch (hw->mac.type) {
8107 case e1000_82575:
f96a8a0b
CW		 8108 case e1000_i210:
8109 case e1000_i211:
ceb5f13b 8110 case e1000_i354:
52a1dd4d
AD		 8111 default:
8112 /* replication is not supported for 82575 */
4ae196df 8113 return;
52a1dd4d
AD		 8114 case e1000_82576:
8115 /* notify HW that the MAC is adding vlan tags */
8116 reg = rd32(E1000_DTXCTL);
8117 reg |= E1000_DTXCTL_VLAN_ADDED;
8118 wr32(E1000_DTXCTL, reg);
b26141d4 8119 /* Fall through */
52a1dd4d
AD		 8120 case e1000_82580:
8121 /* enable replication vlan tag stripping */
8122 reg = rd32(E1000_RPLOLR);
8123 reg |= E1000_RPLOLR_STRVLAN;
8124 wr32(E1000_RPLOLR, reg);
b26141d4 8125 /* Fall through */
d2ba2ed8
AD		 8126 case e1000_i350:
8127 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8128 break;
8129 }
10d8e907 8130
d4960307
AD		 8131 if (adapter->vfs_allocated_count) {
8132 igb_vmdq_set_loopback_pf(hw, true);
8133 igb_vmdq_set_replication_pf(hw, true);
13800469 8134 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8135 adapter->vfs_allocated_count);
d4960307
AD		 8136 } else {
8137 igb_vmdq_set_loopback_pf(hw, false);
8138 igb_vmdq_set_replication_pf(hw, false);
8139 }
4ae196df
AD		 8140}
8141
b6e0c419
CW		 8142static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8143{
8144 struct e1000_hw *hw = &adapter->hw;
8145 u32 dmac_thr;
8146 u16 hwm;
8147
8148 if (hw->mac.type > e1000_82580) {
8149 if (adapter->flags & IGB_FLAG_DMAC) {
8150 u32 reg;
8151
8152 /* force threshold to 0. */
8153 wr32(E1000_DMCTXTH, 0);
8154
b980ac18 8155 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8156 * than the Rx threshold. Set hwm to PBA - max frame
8157 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8158 */
45693bcb 8159 hwm = 64 * (pba - 6);
e8c626e9
MV		 8160 reg = rd32(E1000_FCRTC);
8161 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8162 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8163 & E1000_FCRTC_RTH_COAL_MASK);
8164 wr32(E1000_FCRTC, reg);
8165
b980ac18 8166 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8167 * frame size, capping it at PBA - 10KB.
8168 */
45693bcb 8169 dmac_thr = pba - 10;
b6e0c419
CW		 8170 reg = rd32(E1000_DMACR);
8171 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8172 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8173 & E1000_DMACR_DMACTHR_MASK);
8174
8175 /* transition to L0x or L1 if available..*/
8176 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8177
8178 /* watchdog timer= +-1000 usec in 32usec intervals */
8179 reg |= (1000 >> 5);
0c02dd98
MV		 8180
8181 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8182 if (hw->mac.type != e1000_i354)
8183 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8184
b6e0c419
CW		 8185 wr32(E1000_DMACR, reg);
8186
b980ac18 8187 /* no lower threshold to disable
b6e0c419
CW		 8188 * coalescing(smart fifb)-UTRESH=0
8189 */
8190 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8191
8192 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8193
8194 wr32(E1000_DMCTLX, reg);
8195
b980ac18 8196 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8197 * DMA coal
8198 */
8199 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8200 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8201
b980ac18 8202 /* make low power state decision controlled
b6e0c419
CW		 8203 * by DMA coal
8204 */
8205 reg = rd32(E1000_PCIEMISC);
8206 reg &= ~E1000_PCIEMISC_LX_DECISION;
8207 wr32(E1000_PCIEMISC, reg);
8208 } /* endif adapter->dmac is not disabled */
8209 } else if (hw->mac.type == e1000_82580) {
8210 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8211
b6e0c419
CW		 8212 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8213 wr32(E1000_DMACR, 0);
8214 }
8215}
8216
b980ac18
JK		 8217/**
8218 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8219 * @hw: pointer to hardware structure
8220 * @byte_offset: byte offset to read
8221 * @dev_addr: device address
8222 * @data: value read
8223 *
8224 * Performs byte read operation over I2C interface at
8225 * a specified device address.
b980ac18 8226 **/
441fc6fd 8227s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8228 u8 dev_addr, u8 *data)
441fc6fd
CW		 8229{
8230 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8231 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8232 s32 status;
8233 u16 swfw_mask = 0;
8234
8235 if (!this_client)
8236 return E1000_ERR_I2C;
8237
8238 swfw_mask = E1000_SWFW_PHY0_SM;
8239
23d87824 8240 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8241 return E1000_ERR_SWFW_SYNC;
8242
8243 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8244 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8245
8246 if (status < 0)
8247 return E1000_ERR_I2C;
8248 else {
8249 *data = status;
23d87824 8250 return 0;
441fc6fd
CW		 8251 }
8252}
8253
b980ac18
JK		 8254/**
8255 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8256 * @hw: pointer to hardware structure
8257 * @byte_offset: byte offset to write
8258 * @dev_addr: device address
8259 * @data: value to write
8260 *
8261 * Performs byte write operation over I2C interface at
8262 * a specified device address.
b980ac18 8263 **/
441fc6fd 8264s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8265 u8 dev_addr, u8 data)
441fc6fd
CW		 8266{
8267 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8268 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8269 s32 status;
8270 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8271
8272 if (!this_client)
8273 return E1000_ERR_I2C;
8274
23d87824 8275 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8276 return E1000_ERR_SWFW_SYNC;
8277 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8278 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8279
8280 if (status)
8281 return E1000_ERR_I2C;
8282 else
23d87824 8283 return 0;
441fc6fd
CW		 8284
8285}
907b7835
LMV		 8286
8287int igb_reinit_queues(struct igb_adapter *adapter)
8288{
8289 struct net_device *netdev = adapter->netdev;
8290 struct pci_dev *pdev = adapter->pdev;
8291 int err = 0;
8292
8293 if (netif_running(netdev))
8294 igb_close(netdev);
8295
02ef6e1d 8296 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8297
8298 if (igb_init_interrupt_scheme(adapter, true)) {
8299 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8300 return -ENOMEM;
8301 }
8302
8303 if (netif_running(netdev))
8304 err = igb_open(netdev);
8305
8306 return err;
8307}
9d5c8243 8308/* igb_main.c */
Linux kernel - Deliverables
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