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igb: Cleanups to fix static initialization
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903
CW		 59#define MAJ 5
60#define MIN 0
66f40b8a 61#define BUILD 5
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
a3aa1884 75static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117void igb_reset(struct igb_adapter *);
118static int igb_setup_all_tx_resources(struct igb_adapter *);
119static int igb_setup_all_rx_resources(struct igb_adapter *);
120static void igb_free_all_tx_resources(struct igb_adapter *);
121static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 122static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 123static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 124static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 125static int igb_sw_init(struct igb_adapter *);
126static int igb_open(struct net_device *);
127static int igb_close(struct net_device *);
53c7d064 128static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 129static void igb_configure_tx(struct igb_adapter *);
130static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 131static void igb_clean_all_tx_rings(struct igb_adapter *);
132static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 133static void igb_clean_tx_ring(struct igb_ring *);
134static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 135static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 136static void igb_update_phy_info(unsigned long);
137static void igb_watchdog(unsigned long);
138static void igb_watchdog_task(struct work_struct *);
cd392f5c 139static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 140static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 141 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 142static int igb_change_mtu(struct net_device *, int);
143static int igb_set_mac(struct net_device *, void *);
68d480c4 144static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 145static irqreturn_t igb_intr(int irq, void *);
146static irqreturn_t igb_intr_msi(int irq, void *);
147static irqreturn_t igb_msix_other(int irq, void *);
047e0030 148static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 149#ifdef CONFIG_IGB_DCA
047e0030 150static void igb_update_dca(struct igb_q_vector *);
fe4506b6 151static void igb_setup_dca(struct igb_adapter *);
421e02f0 152#endif /* CONFIG_IGB_DCA */
661086df 153static int igb_poll(struct napi_struct *, int);
13fde97a 154static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 155static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 156static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
157static void igb_tx_timeout(struct net_device *);
158static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 159static void igb_vlan_mode(struct net_device *netdev,
160 netdev_features_t features);
80d5c368
PM		 161static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
162static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 163static void igb_restore_vlan(struct igb_adapter *);
26ad9178 164static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 165static void igb_ping_all_vfs(struct igb_adapter *);
166static void igb_msg_task(struct igb_adapter *);
4ae196df 167static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 168static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 169static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 170static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
171static int igb_ndo_set_vf_vlan(struct net_device *netdev,
172 int vf, u16 vlan, u8 qos);
173static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 174static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
175 bool setting);
8151d294
WM		 176static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
177 struct ifla_vf_info *ivi);
17dc566c 178static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 179
180#ifdef CONFIG_PCI_IOV
0224d663 181static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 182static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 183#endif
9d5c8243 184
9d5c8243 185#ifdef CONFIG_PM
d9dd966d 186#ifdef CONFIG_PM_SLEEP
749ab2cd 187static int igb_suspend(struct device *);
d9dd966d 188#endif
749ab2cd
YZ		 189static int igb_resume(struct device *);
190#ifdef CONFIG_PM_RUNTIME
191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
194#endif
195static const struct dev_pm_ops igb_pm_ops = {
196 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
197 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
198 igb_runtime_idle)
199};
9d5c8243
AK		 200#endif
201static void igb_shutdown(struct pci_dev *);
fa44f2f1 202static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 203#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 204static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
205static struct notifier_block dca_notifier = {
206 .notifier_call = igb_notify_dca,
207 .next = NULL,
208 .priority = 0
209};
210#endif
9d5c8243
AK		 211#ifdef CONFIG_NET_POLL_CONTROLLER
212/* for netdump / net console */
213static void igb_netpoll(struct net_device *);
214#endif
37680117 215#ifdef CONFIG_PCI_IOV
6dd6d2b7 216static unsigned int max_vfs;
2a3abf6d 217module_param(max_vfs, uint, 0);
c75c4edf 218MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 219#endif /* CONFIG_PCI_IOV */
220
9d5c8243
AK		 221static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
222 pci_channel_state_t);
223static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
224static void igb_io_resume(struct pci_dev *);
225
3646f0e5 226static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 227 .error_detected = igb_io_error_detected,
228 .slot_reset = igb_io_slot_reset,
229 .resume = igb_io_resume,
230};
231
b6e0c419 232static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 233
234static struct pci_driver igb_driver = {
235 .name = igb_driver_name,
236 .id_table = igb_pci_tbl,
237 .probe = igb_probe,
9f9a12f8 238 .remove = igb_remove,
9d5c8243 239#ifdef CONFIG_PM
749ab2cd 240 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 241#endif
242 .shutdown = igb_shutdown,
fa44f2f1 243 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 244 .err_handler = &igb_err_handler
245};
246
247MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
248MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
249MODULE_LICENSE("GPL");
250MODULE_VERSION(DRV_VERSION);
251
b3f4d599 252#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
253static int debug = -1;
254module_param(debug, int, 0);
255MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
256
c97ec42a
TI		 257struct igb_reg_info {
258 u32 ofs;
259 char *name;
260};
261
262static const struct igb_reg_info igb_reg_info_tbl[] = {
263
264 /* General Registers */
265 {E1000_CTRL, "CTRL"},
266 {E1000_STATUS, "STATUS"},
267 {E1000_CTRL_EXT, "CTRL_EXT"},
268
269 /* Interrupt Registers */
270 {E1000_ICR, "ICR"},
271
272 /* RX Registers */
273 {E1000_RCTL, "RCTL"},
274 {E1000_RDLEN(0), "RDLEN"},
275 {E1000_RDH(0), "RDH"},
276 {E1000_RDT(0), "RDT"},
277 {E1000_RXDCTL(0), "RXDCTL"},
278 {E1000_RDBAL(0), "RDBAL"},
279 {E1000_RDBAH(0), "RDBAH"},
280
281 /* TX Registers */
282 {E1000_TCTL, "TCTL"},
283 {E1000_TDBAL(0), "TDBAL"},
284 {E1000_TDBAH(0), "TDBAH"},
285 {E1000_TDLEN(0), "TDLEN"},
286 {E1000_TDH(0), "TDH"},
287 {E1000_TDT(0), "TDT"},
288 {E1000_TXDCTL(0), "TXDCTL"},
289 {E1000_TDFH, "TDFH"},
290 {E1000_TDFT, "TDFT"},
291 {E1000_TDFHS, "TDFHS"},
292 {E1000_TDFPC, "TDFPC"},
293
294 /* List Terminator */
295 {}
296};
297
b980ac18 298/* igb_regdump - register printout routine */
c97ec42a
TI		 299static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
300{
301 int n = 0;
302 char rname[16];
303 u32 regs[8];
304
305 switch (reginfo->ofs) {
306 case E1000_RDLEN(0):
307 for (n = 0; n < 4; n++)
308 regs[n] = rd32(E1000_RDLEN(n));
309 break;
310 case E1000_RDH(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDH(n));
313 break;
314 case E1000_RDT(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDT(n));
317 break;
318 case E1000_RXDCTL(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RXDCTL(n));
321 break;
322 case E1000_RDBAL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RDBAL(n));
325 break;
326 case E1000_RDBAH(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAH(n));
329 break;
330 case E1000_TDBAL(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAL(n));
333 break;
334 case E1000_TDBAH(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_TDBAH(n));
337 break;
338 case E1000_TDLEN(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDLEN(n));
341 break;
342 case E1000_TDH(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDH(n));
345 break;
346 case E1000_TDT(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDT(n));
349 break;
350 case E1000_TXDCTL(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TXDCTL(n));
353 break;
354 default:
876d2d6f 355 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 356 return;
357 }
358
359 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 360 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
361 regs[2], regs[3]);
c97ec42a
TI		 362}
363
b980ac18 364/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 365static void igb_dump(struct igb_adapter *adapter)
366{
367 struct net_device *netdev = adapter->netdev;
368 struct e1000_hw *hw = &adapter->hw;
369 struct igb_reg_info *reginfo;
c97ec42a
TI		 370 struct igb_ring *tx_ring;
371 union e1000_adv_tx_desc *tx_desc;
372 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 373 struct igb_ring *rx_ring;
374 union e1000_adv_rx_desc *rx_desc;
375 u32 staterr;
6ad4edfc 376 u16 i, n;
c97ec42a
TI		 377
378 if (!netif_msg_hw(adapter))
379 return;
380
381 /* Print netdevice Info */
382 if (netdev) {
383 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 384 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 385 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
386 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 387 }
388
389 /* Print Registers */
390 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 391 pr_info(" Register Name Value\n");
c97ec42a
TI		 392 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
393 reginfo->name; reginfo++) {
394 igb_regdump(hw, reginfo);
395 }
396
397 /* Print TX Ring Summary */
398 if (!netdev || !netif_running(netdev))
399 goto exit;
400
401 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 402 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 403 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 404 struct igb_tx_buffer *buffer_info;
c97ec42a 405 tx_ring = adapter->tx_ring[n];
06034649 406 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 407 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
408 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 409 (u64)dma_unmap_addr(buffer_info, dma),
410 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 411 buffer_info->next_to_watch,
412 (u64)buffer_info->time_stamp);
c97ec42a
TI		 413 }
414
415 /* Print TX Rings */
416 if (!netif_msg_tx_done(adapter))
417 goto rx_ring_summary;
418
419 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
420
421 /* Transmit Descriptor Formats
422 *
423 * Advanced Transmit Descriptor
424 * +--------------------------------------------------------------+
425 * 0 | Buffer Address [63:0] |
426 * +--------------------------------------------------------------+
427 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
428 * +--------------------------------------------------------------+
429 * 63 46 45 40 39 38 36 35 32 31 24 15 0
430 */
431
432 for (n = 0; n < adapter->num_tx_queues; n++) {
433 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 434 pr_info("------------------------------------\n");
435 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
436 pr_info("------------------------------------\n");
c75c4edf 437 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 438
439 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 440 const char *next_desc;
06034649 441 struct igb_tx_buffer *buffer_info;
60136906 442 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 443 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 444 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 445 if (i == tx_ring->next_to_use &&
446 i == tx_ring->next_to_clean)
447 next_desc = " NTC/U";
448 else if (i == tx_ring->next_to_use)
449 next_desc = " NTU";
450 else if (i == tx_ring->next_to_clean)
451 next_desc = " NTC";
452 else
453 next_desc = "";
454
c75c4edf
CW		 455 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
456 i, le64_to_cpu(u0->a),
c97ec42a 457 le64_to_cpu(u0->b),
c9f14bf3
AD		 458 (u64)dma_unmap_addr(buffer_info, dma),
459 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 460 buffer_info->next_to_watch,
461 (u64)buffer_info->time_stamp,
876d2d6f 462 buffer_info->skb, next_desc);
c97ec42a 463
b669588a 464 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 465 print_hex_dump(KERN_INFO, "",
466 DUMP_PREFIX_ADDRESS,
b669588a 467 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 468 dma_unmap_len(buffer_info, len),
469 true);
c97ec42a
TI		 470 }
471 }
472
473 /* Print RX Rings Summary */
474rx_ring_summary:
475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 476 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 477 for (n = 0; n < adapter->num_rx_queues; n++) {
478 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 479 pr_info(" %5d %5X %5X\n",
480 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 481 }
482
483 /* Print RX Rings */
484 if (!netif_msg_rx_status(adapter))
485 goto exit;
486
487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
488
489 /* Advanced Receive Descriptor (Read) Format
490 * 63 1 0
491 * +-----------------------------------------------------+
492 * 0 | Packet Buffer Address [63:1] |A0/NSE|
493 * +----------------------------------------------+------+
494 * 8 | Header Buffer Address [63:1] | DD |
495 * +-----------------------------------------------------+
496 *
497 *
498 * Advanced Receive Descriptor (Write-Back) Format
499 *
500 * 63 48 47 32 31 30 21 20 17 16 4 3 0
501 * +------------------------------------------------------+
502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
503 * | Checksum Ident | | | | Type | Type |
504 * +------------------------------------------------------+
505 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
506 * +------------------------------------------------------+
507 * 63 48 47 32 31 20 19 0
508 */
509
510 for (n = 0; n < adapter->num_rx_queues; n++) {
511 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 512 pr_info("------------------------------------\n");
513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
514 pr_info("------------------------------------\n");
c75c4edf
CW		 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
516 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 517
518 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 519 const char *next_desc;
06034649
AD		 520 struct igb_rx_buffer *buffer_info;
521 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 522 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 523 u0 = (struct my_u0 *)rx_desc;
524 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 525
526 if (i == rx_ring->next_to_use)
527 next_desc = " NTU";
528 else if (i == rx_ring->next_to_clean)
529 next_desc = " NTC";
530 else
531 next_desc = "";
532
c97ec42a
TI		 533 if (staterr & E1000_RXD_STAT_DD) {
534 /* Descriptor Done */
1a1c225b
AD		 535 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
536 "RWB", i,
c97ec42a
TI		 537 le64_to_cpu(u0->a),
538 le64_to_cpu(u0->b),
1a1c225b 539 next_desc);
c97ec42a 540 } else {
1a1c225b
AD		 541 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
542 "R ", i,
c97ec42a
TI		 543 le64_to_cpu(u0->a),
544 le64_to_cpu(u0->b),
545 (u64)buffer_info->dma,
1a1c225b 546 next_desc);
c97ec42a 547
b669588a 548 if (netif_msg_pktdata(adapter) &&
1a1c225b 549 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 550 print_hex_dump(KERN_INFO, "",
551 DUMP_PREFIX_ADDRESS,
552 16, 1,
b669588a
ET		 553 page_address(buffer_info->page) +
554 buffer_info->page_offset,
de78d1f9 555 IGB_RX_BUFSZ, true);
c97ec42a
TI		 556 }
557 }
c97ec42a
TI		 558 }
559 }
560
561exit:
562 return;
563}
564
b980ac18
JK		 565/**
566 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 567 * @hw: pointer to hardware structure
568 * @i2cctl: Current value of I2CCTL register
569 *
570 * Returns the I2C data bit value
b980ac18 571 **/
441fc6fd
CW		 572static int igb_get_i2c_data(void *data)
573{
574 struct igb_adapter *adapter = (struct igb_adapter *)data;
575 struct e1000_hw *hw = &adapter->hw;
576 s32 i2cctl = rd32(E1000_I2CPARAMS);
577
da1f1dfe 578 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 579}
580
b980ac18
JK		 581/**
582 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 583 * @data: pointer to hardware structure
584 * @state: I2C data value (0 or 1) to set
585 *
586 * Sets the I2C data bit
b980ac18 587 **/
441fc6fd
CW		 588static void igb_set_i2c_data(void *data, int state)
589{
590 struct igb_adapter *adapter = (struct igb_adapter *)data;
591 struct e1000_hw *hw = &adapter->hw;
592 s32 i2cctl = rd32(E1000_I2CPARAMS);
593
594 if (state)
595 i2cctl |= E1000_I2C_DATA_OUT;
596 else
597 i2cctl &= ~E1000_I2C_DATA_OUT;
598
599 i2cctl &= ~E1000_I2C_DATA_OE_N;
600 i2cctl |= E1000_I2C_CLK_OE_N;
601 wr32(E1000_I2CPARAMS, i2cctl);
602 wrfl();
603
604}
605
b980ac18
JK		 606/**
607 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 608 * @data: pointer to hardware structure
609 * @state: state to set clock
610 *
611 * Sets the I2C clock line to state
b980ac18 612 **/
441fc6fd
CW		 613static void igb_set_i2c_clk(void *data, int state)
614{
615 struct igb_adapter *adapter = (struct igb_adapter *)data;
616 struct e1000_hw *hw = &adapter->hw;
617 s32 i2cctl = rd32(E1000_I2CPARAMS);
618
619 if (state) {
620 i2cctl |= E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 } else {
623 i2cctl &= ~E1000_I2C_CLK_OUT;
624 i2cctl &= ~E1000_I2C_CLK_OE_N;
625 }
626 wr32(E1000_I2CPARAMS, i2cctl);
627 wrfl();
628}
629
b980ac18
JK		 630/**
631 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 632 * @data: pointer to hardware structure
633 *
634 * Gets the I2C clock state
b980ac18 635 **/
441fc6fd
CW		 636static int igb_get_i2c_clk(void *data)
637{
638 struct igb_adapter *adapter = (struct igb_adapter *)data;
639 struct e1000_hw *hw = &adapter->hw;
640 s32 i2cctl = rd32(E1000_I2CPARAMS);
641
da1f1dfe 642 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 643}
644
645static const struct i2c_algo_bit_data igb_i2c_algo = {
646 .setsda = igb_set_i2c_data,
647 .setscl = igb_set_i2c_clk,
648 .getsda = igb_get_i2c_data,
649 .getscl = igb_get_i2c_clk,
650 .udelay = 5,
651 .timeout = 20,
652};
653
9d5c8243 654/**
b980ac18
JK		 655 * igb_get_hw_dev - return device
656 * @hw: pointer to hardware structure
657 *
658 * used by hardware layer to print debugging information
9d5c8243 659 **/
c041076a 660struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 661{
662 struct igb_adapter *adapter = hw->back;
c041076a 663 return adapter->netdev;
9d5c8243 664}
38c845c7 665
9d5c8243 666/**
b980ac18 667 * igb_init_module - Driver Registration Routine
9d5c8243 668 *
b980ac18
JK		 669 * igb_init_module is the first routine called when the driver is
670 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 671 **/
672static int __init igb_init_module(void)
673{
674 int ret;
9005df38 675
876d2d6f 676 pr_info("%s - version %s\n",
9d5c8243 677 igb_driver_string, igb_driver_version);
876d2d6f 678 pr_info("%s\n", igb_copyright);
9d5c8243 679
421e02f0 680#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 681 dca_register_notify(&dca_notifier);
682#endif
bbd98fe4 683 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 684 return ret;
685}
686
687module_init(igb_init_module);
688
689/**
b980ac18 690 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 691 *
b980ac18
JK		 692 * igb_exit_module is called just before the driver is removed
693 * from memory.
9d5c8243
AK		 694 **/
695static void __exit igb_exit_module(void)
696{
421e02f0 697#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 698 dca_unregister_notify(&dca_notifier);
699#endif
9d5c8243
AK		 700 pci_unregister_driver(&igb_driver);
701}
702
703module_exit(igb_exit_module);
704
26bc19ec
AD		 705#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
706/**
b980ac18
JK		 707 * igb_cache_ring_register - Descriptor ring to register mapping
708 * @adapter: board private structure to initialize
26bc19ec 709 *
b980ac18
JK		 710 * Once we know the feature-set enabled for the device, we'll cache
711 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 712 **/
713static void igb_cache_ring_register(struct igb_adapter *adapter)
714{
ee1b9f06 715 int i = 0, j = 0;
047e0030 716 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 717
718 switch (adapter->hw.mac.type) {
719 case e1000_82576:
720 /* The queues are allocated for virtualization such that VF 0
721 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
722 * In order to avoid collision we start at the first free queue
723 * and continue consuming queues in the same sequence
724 */
ee1b9f06 725 if (adapter->vfs_allocated_count) {
a99955fc 726 for (; i < adapter->rss_queues; i++)
3025a446 727 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 728 Q_IDX_82576(i);
ee1b9f06 729 }
b26141d4 730 /* Fall through */
26bc19ec 731 case e1000_82575:
55cac248 732 case e1000_82580:
d2ba2ed8 733 case e1000_i350:
ceb5f13b 734 case e1000_i354:
f96a8a0b
CW		 735 case e1000_i210:
736 case e1000_i211:
b26141d4 737 /* Fall through */
26bc19ec 738 default:
ee1b9f06 739 for (; i < adapter->num_rx_queues; i++)
3025a446 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 741 for (; j < adapter->num_tx_queues; j++)
3025a446 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 743 break;
744 }
745}
746
22a8b291
FT		 747u32 igb_rd32(struct e1000_hw *hw, u32 reg)
748{
749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
751 u32 value = 0;
752
753 if (E1000_REMOVED(hw_addr))
754 return ~value;
755
756 value = readl(&hw_addr[reg]);
757
758 /* reads should not return all F's */
759 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
760 struct net_device *netdev = igb->netdev;
761 hw->hw_addr = NULL;
762 netif_device_detach(netdev);
763 netdev_err(netdev, "PCIe link lost, device now detached\n");
764 }
765
766 return value;
767}
768
4be000c8
AD		 769/**
770 * igb_write_ivar - configure ivar for given MSI-X vector
771 * @hw: pointer to the HW structure
772 * @msix_vector: vector number we are allocating to a given ring
773 * @index: row index of IVAR register to write within IVAR table
774 * @offset: column offset of in IVAR, should be multiple of 8
775 *
776 * This function is intended to handle the writing of the IVAR register
777 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
778 * each containing an cause allocation for an Rx and Tx ring, and a
779 * variable number of rows depending on the number of queues supported.
780 **/
781static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
782 int index, int offset)
783{
784 u32 ivar = array_rd32(E1000_IVAR0, index);
785
786 /* clear any bits that are currently set */
787 ivar &= ~((u32)0xFF << offset);
788
789 /* write vector and valid bit */
790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
791
792 array_wr32(E1000_IVAR0, index, ivar);
793}
794
9d5c8243 795#define IGB_N0_QUEUE -1
047e0030 796static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 797{
047e0030 798 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 799 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 800 int rx_queue = IGB_N0_QUEUE;
801 int tx_queue = IGB_N0_QUEUE;
4be000c8 802 u32 msixbm = 0;
047e0030 803
0ba82994
AD		 804 if (q_vector->rx.ring)
805 rx_queue = q_vector->rx.ring->reg_idx;
806 if (q_vector->tx.ring)
807 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 808
809 switch (hw->mac.type) {
810 case e1000_82575:
9d5c8243 811 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one
813 * or more queues to a vector, we write the appropriate bits
814 * into the MSIXBM register for that vector.
815 */
047e0030 816 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 818 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 821 msixbm |= E1000_EIMS_OTHER;
9d5c8243 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 823 q_vector->eims_value = msixbm;
2d064c06
AD		 824 break;
825 case e1000_82576:
b980ac18 826 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 827 * with 8 rows. The ordering is column-major so we use the
828 * lower 3 bits as the row index, and the 4th bit as the
829 * column offset.
830 */
831 if (rx_queue > IGB_N0_QUEUE)
832 igb_write_ivar(hw, msix_vector,
833 rx_queue & 0x7,
834 (rx_queue & 0x8) << 1);
835 if (tx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 tx_queue & 0x7,
838 ((tx_queue & 0x8) << 1) + 8);
047e0030 839 q_vector->eims_value = 1 << msix_vector;
2d064c06 840 break;
55cac248 841 case e1000_82580:
d2ba2ed8 842 case e1000_i350:
ceb5f13b 843 case e1000_i354:
f96a8a0b
CW		 844 case e1000_i210:
845 case e1000_i211:
b980ac18 846 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 847 * however instead of ordering column-major we have things
848 * ordered row-major. So we traverse the table by using
849 * bit 0 as the column offset, and the remaining bits as the
850 * row index.
851 */
852 if (rx_queue > IGB_N0_QUEUE)
853 igb_write_ivar(hw, msix_vector,
854 rx_queue >> 1,
855 (rx_queue & 0x1) << 4);
856 if (tx_queue > IGB_N0_QUEUE)
857 igb_write_ivar(hw, msix_vector,
858 tx_queue >> 1,
859 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 860 q_vector->eims_value = 1 << msix_vector;
861 break;
2d064c06
AD		 862 default:
863 BUG();
864 break;
865 }
26b39276
AD		 866
867 /* add q_vector eims value to global eims_enable_mask */
868 adapter->eims_enable_mask |= q_vector->eims_value;
869
870 /* configure q_vector to set itr on first interrupt */
871 q_vector->set_itr = 1;
9d5c8243
AK		 872}
873
874/**
b980ac18
JK		 875 * igb_configure_msix - Configure MSI-X hardware
876 * @adapter: board private structure to initialize
9d5c8243 877 *
b980ac18
JK		 878 * igb_configure_msix sets up the hardware to properly
879 * generate MSI-X interrupts.
9d5c8243
AK		 880 **/
881static void igb_configure_msix(struct igb_adapter *adapter)
882{
883 u32 tmp;
884 int i, vector = 0;
885 struct e1000_hw *hw = &adapter->hw;
886
887 adapter->eims_enable_mask = 0;
9d5c8243
AK		 888
889 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 890 switch (hw->mac.type) {
891 case e1000_82575:
9d5c8243
AK		 892 tmp = rd32(E1000_CTRL_EXT);
893 /* enable MSI-X PBA support*/
894 tmp |= E1000_CTRL_EXT_PBA_CLR;
895
896 /* Auto-Mask interrupts upon ICR read. */
897 tmp |= E1000_CTRL_EXT_EIAME;
898 tmp |= E1000_CTRL_EXT_IRCA;
899
900 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 901
902 /* enable msix_other interrupt */
b980ac18 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 904 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 905
2d064c06
AD		 906 break;
907
908 case e1000_82576:
55cac248 909 case e1000_82580:
d2ba2ed8 910 case e1000_i350:
ceb5f13b 911 case e1000_i354:
f96a8a0b
CW		 912 case e1000_i210:
913 case e1000_i211:
047e0030 914 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 915 * won't stick. And it will take days to debug.
916 */
047e0030 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 918 E1000_GPIE_PBA | E1000_GPIE_EIAME |
919 E1000_GPIE_NSICR);
047e0030
AD		 920
921 /* enable msix_other interrupt */
922 adapter->eims_other = 1 << vector;
2d064c06 923 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 924
047e0030 925 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 926 break;
927 default:
928 /* do nothing, since nothing else supports MSI-X */
929 break;
930 } /* switch (hw->mac.type) */
047e0030
AD		 931
932 adapter->eims_enable_mask |= adapter->eims_other;
933
26b39276
AD		 934 for (i = 0; i < adapter->num_q_vectors; i++)
935 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 936
9d5c8243
AK		 937 wrfl();
938}
939
940/**
b980ac18
JK		 941 * igb_request_msix - Initialize MSI-X interrupts
942 * @adapter: board private structure to initialize
9d5c8243 943 *
b980ac18
JK		 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
945 * kernel.
9d5c8243
AK		 946 **/
947static int igb_request_msix(struct igb_adapter *adapter)
948{
949 struct net_device *netdev = adapter->netdev;
047e0030 950 struct e1000_hw *hw = &adapter->hw;
52285b76 951 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 952
047e0030 953 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 954 igb_msix_other, 0, netdev->name, adapter);
047e0030 955 if (err)
52285b76 956 goto err_out;
047e0030
AD		 957
958 for (i = 0; i < adapter->num_q_vectors; i++) {
959 struct igb_q_vector *q_vector = adapter->q_vector[i];
960
52285b76
SA		 961 vector++;
962
047e0030
AD		 963 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
964
0ba82994 965 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 966 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 967 q_vector->rx.ring->queue_index);
968 else if (q_vector->tx.ring)
047e0030 969 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 970 q_vector->tx.ring->queue_index);
971 else if (q_vector->rx.ring)
047e0030 972 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 973 q_vector->rx.ring->queue_index);
9d5c8243 974 else
047e0030
AD		 975 sprintf(q_vector->name, "%s-unused", netdev->name);
976
9d5c8243 977 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 978 igb_msix_ring, 0, q_vector->name,
979 q_vector);
9d5c8243 980 if (err)
52285b76 981 goto err_free;
9d5c8243
AK		 982 }
983
9d5c8243
AK		 984 igb_configure_msix(adapter);
985 return 0;
52285b76
SA		 986
987err_free:
988 /* free already assigned IRQs */
989 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
990
991 vector--;
992 for (i = 0; i < vector; i++) {
993 free_irq(adapter->msix_entries[free_vector++].vector,
994 adapter->q_vector[i]);
995 }
996err_out:
9d5c8243
AK		 997 return err;
998}
999
5536d210 1000/**
b980ac18
JK		 1001 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1002 * @adapter: board private structure to initialize
1003 * @v_idx: Index of vector to be freed
5536d210 1004 *
02ef6e1d 1005 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1006 **/
1007static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1008{
1009 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1010
02ef6e1d
CW		 1011 adapter->q_vector[v_idx] = NULL;
1012
1013 /* igb_get_stats64() might access the rings on this vector,
1014 * we must wait a grace period before freeing it.
1015 */
1016 kfree_rcu(q_vector, rcu);
1017}
1018
1019/**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
cb06d102
CP		 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
5536d210
AD		 1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
1041 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1042
5536d210
AD		 1043 netif_napi_del(&q_vector->napi);
1044
02ef6e1d
CW		 1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
cd14ef54 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1052 pci_disable_msix(adapter->pdev);
cd14ef54 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1054 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1058}
1059
047e0030 1060/**
b980ac18
JK		 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
047e0030 1063 *
b980ac18
JK		 1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
047e0030
AD		 1067 **/
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
5536d210
AD		 1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
047e0030 1074 adapter->num_q_vectors = 0;
5536d210 1075
02ef6e1d
CW		 1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
5536d210 1078 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1079 }
047e0030
AD		 1080}
1081
1082/**
b980ac18
JK		 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
047e0030 1085 *
b980ac18
JK		 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
047e0030
AD		 1088 */
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
047e0030
AD		 1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
9d5c8243
AK		 1094
1095/**
b980ac18
JK		 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
9d5c8243 1099 *
b980ac18
JK		 1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
9d5c8243 1102 **/
53c7d064 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1104{
1105 int err;
1106 int numvecs, i;
1107
53c7d064
SA		 1108 if (!msix)
1109 goto msi_only;
cd14ef54 1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1111
83b7180d 1112 /* Number of supported queues. */
a99955fc 1113 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1118
b980ac18 1119 /* start with one vector for every Rx queue */
047e0030
AD		 1120 numvecs = adapter->num_rx_queues;
1121
b980ac18 1122 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
047e0030
AD		 1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
9d5c8243
AK		 1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
479d02df
AG		 1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
0c2cc02e 1139 return;
9d5c8243
AK		 1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144msi_only:
b709323d 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1146#ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1157 wrfl();
2a3abf6d
AD		 1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
4fc82adf 1162 adapter->vfs_allocated_count = 0;
a99955fc 1163 adapter->rss_queues = 1;
4fc82adf 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1165 adapter->num_rx_queues = 1;
661086df 1166 adapter->num_tx_queues = 1;
047e0030 1167 adapter->num_q_vectors = 1;
9d5c8243 1168 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1169 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1170}
1171
5536d210
AD		 1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
047e0030 1179/**
b980ac18
JK		 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
047e0030 1188 *
b980ac18 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1190 **/
5536d210
AD		 1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
047e0030
AD		 1195{
1196 struct igb_q_vector *q_vector;
5536d210
AD		 1197 struct igb_ring *ring;
1198 int ring_count, size;
047e0030 1199
5536d210
AD		 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
02ef6e1d
CW		 1209 q_vector = adapter->q_vector[v_idx];
1210 if (!q_vector)
1211 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1212 if (!q_vector)
1213 return -ENOMEM;
1214
1215 /* initialize NAPI */
1216 netif_napi_add(adapter->netdev, &q_vector->napi,
1217 igb_poll, 64);
1218
1219 /* tie q_vector and adapter together */
1220 adapter->q_vector[v_idx] = q_vector;
1221 q_vector->adapter = adapter;
1222
1223 /* initialize work limits */
1224 q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226 /* initialize ITR configuration */
1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1228 q_vector->itr_val = IGB_START_ITR;
1229
1230 /* initialize pointer to rings */
1231 ring = q_vector->ring;
1232
4e227667
AD		 1233 /* intialize ITR */
1234 if (rxr_count) {
1235 /* rx or rx/tx vector */
1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237 q_vector->itr_val = adapter->rx_itr_setting;
1238 } else {
1239 /* tx only vector */
1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241 q_vector->itr_val = adapter->tx_itr_setting;
1242 }
1243
5536d210
AD		 1244 if (txr_count) {
1245 /* assign generic ring traits */
1246 ring->dev = &adapter->pdev->dev;
1247 ring->netdev = adapter->netdev;
1248
1249 /* configure backlink on ring */
1250 ring->q_vector = q_vector;
1251
1252 /* update q_vector Tx values */
1253 igb_add_ring(ring, &q_vector->tx);
1254
1255 /* For 82575, context index must be unique per ring. */
1256 if (adapter->hw.mac.type == e1000_82575)
1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259 /* apply Tx specific ring traits */
1260 ring->count = adapter->tx_ring_count;
1261 ring->queue_index = txr_idx;
1262
827da44c
JS		 1263 u64_stats_init(&ring->tx_syncp);
1264 u64_stats_init(&ring->tx_syncp2);
1265
5536d210
AD		 1266 /* assign ring to adapter */
1267 adapter->tx_ring[txr_idx] = ring;
1268
1269 /* push pointer to next ring */
1270 ring++;
047e0030 1271 }
81c2fc22 1272
5536d210
AD		 1273 if (rxr_count) {
1274 /* assign generic ring traits */
1275 ring->dev = &adapter->pdev->dev;
1276 ring->netdev = adapter->netdev;
047e0030 1277
5536d210
AD		 1278 /* configure backlink on ring */
1279 ring->q_vector = q_vector;
047e0030 1280
5536d210
AD		 1281 /* update q_vector Rx values */
1282 igb_add_ring(ring, &q_vector->rx);
047e0030 1283
5536d210
AD		 1284 /* set flag indicating ring supports SCTP checksum offload */
1285 if (adapter->hw.mac.type >= e1000_82576)
1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1287
e52c0f96 1288 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1289 * have the tag byte-swapped.
b980ac18 1290 */
5536d210
AD		 1291 if (adapter->hw.mac.type >= e1000_i350)
1292 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1293
5536d210
AD		 1294 /* apply Rx specific ring traits */
1295 ring->count = adapter->rx_ring_count;
1296 ring->queue_index = rxr_idx;
1297
827da44c
JS		 1298 u64_stats_init(&ring->rx_syncp);
1299
5536d210
AD		 1300 /* assign ring to adapter */
1301 adapter->rx_ring[rxr_idx] = ring;
1302 }
1303
1304 return 0;
047e0030
AD		 1305}
1306
5536d210 1307
047e0030 1308/**
b980ac18
JK		 1309 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1310 * @adapter: board private structure to initialize
047e0030 1311 *
b980ac18
JK		 1312 * We allocate one q_vector per queue interrupt. If allocation fails we
1313 * return -ENOMEM.
047e0030 1314 **/
5536d210 1315static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1316{
5536d210
AD		 1317 int q_vectors = adapter->num_q_vectors;
1318 int rxr_remaining = adapter->num_rx_queues;
1319 int txr_remaining = adapter->num_tx_queues;
1320 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1321 int err;
047e0030 1322
5536d210
AD		 1323 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1324 for (; rxr_remaining; v_idx++) {
1325 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1326 0, 0, 1, rxr_idx);
047e0030 1327
5536d210
AD		 1328 if (err)
1329 goto err_out;
1330
1331 /* update counts and index */
1332 rxr_remaining--;
1333 rxr_idx++;
047e0030 1334 }
047e0030 1335 }
5536d210
AD		 1336
1337 for (; v_idx < q_vectors; v_idx++) {
1338 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1339 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1340
5536d210
AD		 1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1342 tqpv, txr_idx, rqpv, rxr_idx);
1343
1344 if (err)
1345 goto err_out;
1346
1347 /* update counts and index */
1348 rxr_remaining -= rqpv;
1349 txr_remaining -= tqpv;
1350 rxr_idx++;
1351 txr_idx++;
1352 }
1353
047e0030 1354 return 0;
5536d210
AD		 1355
1356err_out:
1357 adapter->num_tx_queues = 0;
1358 adapter->num_rx_queues = 0;
1359 adapter->num_q_vectors = 0;
1360
1361 while (v_idx--)
1362 igb_free_q_vector(adapter, v_idx);
1363
1364 return -ENOMEM;
047e0030
AD		 1365}
1366
1367/**
b980ac18
JK		 1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1369 * @adapter: board private structure to initialize
1370 * @msix: boolean value of MSIX capability
047e0030 1371 *
b980ac18 1372 * This function initializes the interrupts and allocates all of the queues.
047e0030 1373 **/
53c7d064 1374static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1375{
1376 struct pci_dev *pdev = adapter->pdev;
1377 int err;
1378
53c7d064 1379 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1380
1381 err = igb_alloc_q_vectors(adapter);
1382 if (err) {
1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1384 goto err_alloc_q_vectors;
1385 }
1386
5536d210 1387 igb_cache_ring_register(adapter);
047e0030
AD		 1388
1389 return 0;
5536d210 1390
047e0030
AD		 1391err_alloc_q_vectors:
1392 igb_reset_interrupt_capability(adapter);
1393 return err;
1394}
1395
9d5c8243 1396/**
b980ac18
JK		 1397 * igb_request_irq - initialize interrupts
1398 * @adapter: board private structure to initialize
9d5c8243 1399 *
b980ac18
JK		 1400 * Attempts to configure interrupts using the best available
1401 * capabilities of the hardware and kernel.
9d5c8243
AK		 1402 **/
1403static int igb_request_irq(struct igb_adapter *adapter)
1404{
1405 struct net_device *netdev = adapter->netdev;
047e0030 1406 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1407 int err = 0;
1408
cd14ef54 1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1410 err = igb_request_msix(adapter);
844290e5 1411 if (!err)
9d5c8243 1412 goto request_done;
9d5c8243 1413 /* fall back to MSI */
5536d210
AD		 1414 igb_free_all_tx_resources(adapter);
1415 igb_free_all_rx_resources(adapter);
53c7d064 1416
047e0030 1417 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1418 err = igb_init_interrupt_scheme(adapter, false);
1419 if (err)
047e0030 1420 goto request_done;
53c7d064 1421
047e0030
AD		 1422 igb_setup_all_tx_resources(adapter);
1423 igb_setup_all_rx_resources(adapter);
53c7d064 1424 igb_configure(adapter);
9d5c8243 1425 }
844290e5 1426
c74d588e
AD		 1427 igb_assign_vector(adapter->q_vector[0], 0);
1428
7dfc16fa 1429 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1430 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1431 netdev->name, adapter);
9d5c8243
AK		 1432 if (!err)
1433 goto request_done;
047e0030 1434
9d5c8243
AK		 1435 /* fall back to legacy interrupts */
1436 igb_reset_interrupt_capability(adapter);
7dfc16fa 1437 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1438 }
1439
c74d588e 1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1441 netdev->name, adapter);
9d5c8243 1442
6cb5e577 1443 if (err)
c74d588e 1444 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1445 err);
9d5c8243
AK		 1446
1447request_done:
1448 return err;
1449}
1450
1451static void igb_free_irq(struct igb_adapter *adapter)
1452{
cd14ef54 1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1454 int vector = 0, i;
1455
047e0030 1456 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1457
0d1ae7f4 1458 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1459 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1460 adapter->q_vector[i]);
047e0030
AD		 1461 } else {
1462 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1463 }
9d5c8243
AK		 1464}
1465
1466/**
b980ac18
JK		 1467 * igb_irq_disable - Mask off interrupt generation on the NIC
1468 * @adapter: board private structure
9d5c8243
AK		 1469 **/
1470static void igb_irq_disable(struct igb_adapter *adapter)
1471{
1472 struct e1000_hw *hw = &adapter->hw;
1473
b980ac18 1474 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1475 * mapped into these registers and so clearing the bits can cause
1476 * issues on the VF drivers so we only need to clear what we set
1477 */
cd14ef54 1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1479 u32 regval = rd32(E1000_EIAM);
9005df38 1480
2dfd1212
AD		 1481 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1482 wr32(E1000_EIMC, adapter->eims_enable_mask);
1483 regval = rd32(E1000_EIAC);
1484 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1485 }
844290e5
PW		 1486
1487 wr32(E1000_IAM, 0);
9d5c8243
AK		 1488 wr32(E1000_IMC, ~0);
1489 wrfl();
cd14ef54 1490 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1491 int i;
9005df38 1492
81a61859
ET		 1493 for (i = 0; i < adapter->num_q_vectors; i++)
1494 synchronize_irq(adapter->msix_entries[i].vector);
1495 } else {
1496 synchronize_irq(adapter->pdev->irq);
1497 }
9d5c8243
AK		 1498}
1499
1500/**
b980ac18
JK		 1501 * igb_irq_enable - Enable default interrupt generation settings
1502 * @adapter: board private structure
9d5c8243
AK		 1503 **/
1504static void igb_irq_enable(struct igb_adapter *adapter)
1505{
1506 struct e1000_hw *hw = &adapter->hw;
1507
cd14ef54 1508 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1509 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1510 u32 regval = rd32(E1000_EIAC);
9005df38 1511
2dfd1212
AD		 1512 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1513 regval = rd32(E1000_EIAM);
1514 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1515 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1516 if (adapter->vfs_allocated_count) {
4ae196df 1517 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1518 ims |= E1000_IMS_VMMB;
1519 }
1520 wr32(E1000_IMS, ims);
844290e5 1521 } else {
55cac248
AD		 1522 wr32(E1000_IMS, IMS_ENABLE_MASK |
1523 E1000_IMS_DRSTA);
1524 wr32(E1000_IAM, IMS_ENABLE_MASK |
1525 E1000_IMS_DRSTA);
844290e5 1526 }
9d5c8243
AK		 1527}
1528
1529static void igb_update_mng_vlan(struct igb_adapter *adapter)
1530{
51466239 1531 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1532 u16 vid = adapter->hw.mng_cookie.vlan_id;
1533 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1534
1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1536 /* add VID to filter table */
1537 igb_vfta_set(hw, vid, true);
1538 adapter->mng_vlan_id = vid;
1539 } else {
1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1541 }
1542
1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1544 (vid != old_vid) &&
b2cb09b1 1545 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1546 /* remove VID from filter table */
1547 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1548 }
1549}
1550
1551/**
b980ac18
JK		 1552 * igb_release_hw_control - release control of the h/w to f/w
1553 * @adapter: address of board private structure
9d5c8243 1554 *
b980ac18
JK		 1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1556 * For ASF and Pass Through versions of f/w this means that the
1557 * driver is no longer loaded.
9d5c8243
AK		 1558 **/
1559static void igb_release_hw_control(struct igb_adapter *adapter)
1560{
1561 struct e1000_hw *hw = &adapter->hw;
1562 u32 ctrl_ext;
1563
1564 /* Let firmware take over control of h/w */
1565 ctrl_ext = rd32(E1000_CTRL_EXT);
1566 wr32(E1000_CTRL_EXT,
1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1568}
1569
9d5c8243 1570/**
b980ac18
JK		 1571 * igb_get_hw_control - get control of the h/w from f/w
1572 * @adapter: address of board private structure
9d5c8243 1573 *
b980ac18
JK		 1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1575 * For ASF and Pass Through versions of f/w this means that
1576 * the driver is loaded.
9d5c8243
AK		 1577 **/
1578static void igb_get_hw_control(struct igb_adapter *adapter)
1579{
1580 struct e1000_hw *hw = &adapter->hw;
1581 u32 ctrl_ext;
1582
1583 /* Let firmware know the driver has taken over */
1584 ctrl_ext = rd32(E1000_CTRL_EXT);
1585 wr32(E1000_CTRL_EXT,
1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1587}
1588
9d5c8243 1589/**
b980ac18
JK		 1590 * igb_configure - configure the hardware for RX and TX
1591 * @adapter: private board structure
9d5c8243
AK		 1592 **/
1593static void igb_configure(struct igb_adapter *adapter)
1594{
1595 struct net_device *netdev = adapter->netdev;
1596 int i;
1597
1598 igb_get_hw_control(adapter);
ff41f8dc 1599 igb_set_rx_mode(netdev);
9d5c8243
AK		 1600
1601 igb_restore_vlan(adapter);
9d5c8243 1602
85b430b4 1603 igb_setup_tctl(adapter);
06cf2666 1604 igb_setup_mrqc(adapter);
9d5c8243 1605 igb_setup_rctl(adapter);
85b430b4
AD		 1606
1607 igb_configure_tx(adapter);
9d5c8243 1608 igb_configure_rx(adapter);
662d7205
AD		 1609
1610 igb_rx_fifo_flush_82575(&adapter->hw);
1611
c493ea45 1612 /* call igb_desc_unused which always leaves
9d5c8243 1613 * at least 1 descriptor unused to make sure
b980ac18
JK		 1614 * next_to_use != next_to_clean
1615 */
9d5c8243 1616 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1617 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1618 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1619 }
9d5c8243
AK		 1620}
1621
88a268c1 1622/**
b980ac18
JK		 1623 * igb_power_up_link - Power up the phy/serdes link
1624 * @adapter: address of board private structure
88a268c1
NN		 1625 **/
1626void igb_power_up_link(struct igb_adapter *adapter)
1627{
76886596
AA		 1628 igb_reset_phy(&adapter->hw);
1629
88a268c1
NN		 1630 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1631 igb_power_up_phy_copper(&adapter->hw);
1632 else
1633 igb_power_up_serdes_link_82575(&adapter->hw);
1634}
1635
1636/**
b980ac18
JK		 1637 * igb_power_down_link - Power down the phy/serdes link
1638 * @adapter: address of board private structure
88a268c1
NN		 1639 */
1640static void igb_power_down_link(struct igb_adapter *adapter)
1641{
1642 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1643 igb_power_down_phy_copper_82575(&adapter->hw);
1644 else
1645 igb_shutdown_serdes_link_82575(&adapter->hw);
1646}
9d5c8243 1647
56cec249
CW		 1648/**
1649 * Detect and switch function for Media Auto Sense
1650 * @adapter: address of the board private structure
1651 **/
1652static void igb_check_swap_media(struct igb_adapter *adapter)
1653{
1654 struct e1000_hw *hw = &adapter->hw;
1655 u32 ctrl_ext, connsw;
1656 bool swap_now = false;
1657
1658 ctrl_ext = rd32(E1000_CTRL_EXT);
1659 connsw = rd32(E1000_CONNSW);
1660
1661 /* need to live swap if current media is copper and we have fiber/serdes
1662 * to go to.
1663 */
1664
1665 if ((hw->phy.media_type == e1000_media_type_copper) &&
1666 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1667 swap_now = true;
1668 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1669 /* copper signal takes time to appear */
1670 if (adapter->copper_tries < 4) {
1671 adapter->copper_tries++;
1672 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1673 wr32(E1000_CONNSW, connsw);
1674 return;
1675 } else {
1676 adapter->copper_tries = 0;
1677 if ((connsw & E1000_CONNSW_PHYSD) &&
1678 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1679 swap_now = true;
1680 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 }
1683 }
1684 }
1685
1686 if (!swap_now)
1687 return;
1688
1689 switch (hw->phy.media_type) {
1690 case e1000_media_type_copper:
1691 netdev_info(adapter->netdev,
1692 "MAS: changing media to fiber/serdes\n");
1693 ctrl_ext |=
1694 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1695 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1696 adapter->copper_tries = 0;
1697 break;
1698 case e1000_media_type_internal_serdes:
1699 case e1000_media_type_fiber:
1700 netdev_info(adapter->netdev,
1701 "MAS: changing media to copper\n");
1702 ctrl_ext &=
1703 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1704 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1705 break;
1706 default:
1707 /* shouldn't get here during regular operation */
1708 netdev_err(adapter->netdev,
1709 "AMS: Invalid media type found, returning\n");
1710 break;
1711 }
1712 wr32(E1000_CTRL_EXT, ctrl_ext);
1713}
1714
9d5c8243 1715/**
b980ac18
JK		 1716 * igb_up - Open the interface and prepare it to handle traffic
1717 * @adapter: board private structure
9d5c8243 1718 **/
9d5c8243
AK		 1719int igb_up(struct igb_adapter *adapter)
1720{
1721 struct e1000_hw *hw = &adapter->hw;
1722 int i;
1723
1724 /* hardware has been reset, we need to reload some things */
1725 igb_configure(adapter);
1726
1727 clear_bit(__IGB_DOWN, &adapter->state);
1728
0d1ae7f4
AD		 1729 for (i = 0; i < adapter->num_q_vectors; i++)
1730 napi_enable(&(adapter->q_vector[i]->napi));
1731
cd14ef54 1732 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1733 igb_configure_msix(adapter);
feeb2721
AD		 1734 else
1735 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1736
1737 /* Clear any pending interrupts. */
1738 rd32(E1000_ICR);
1739 igb_irq_enable(adapter);
1740
d4960307
AD		 1741 /* notify VFs that reset has been completed */
1742 if (adapter->vfs_allocated_count) {
1743 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1744
d4960307
AD		 1745 reg_data |= E1000_CTRL_EXT_PFRSTD;
1746 wr32(E1000_CTRL_EXT, reg_data);
1747 }
1748
4cb9be7a
JB		 1749 netif_tx_start_all_queues(adapter->netdev);
1750
25568a53
AD		 1751 /* start the watchdog. */
1752 hw->mac.get_link_status = 1;
1753 schedule_work(&adapter->watchdog_task);
1754
f4c01e96
CW		 1755 if ((adapter->flags & IGB_FLAG_EEE) &&
1756 (!hw->dev_spec._82575.eee_disable))
1757 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1758
9d5c8243
AK		 1759 return 0;
1760}
1761
1762void igb_down(struct igb_adapter *adapter)
1763{
9d5c8243 1764 struct net_device *netdev = adapter->netdev;
330a6d6a 1765 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1766 u32 tctl, rctl;
1767 int i;
1768
1769 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1770 * reschedule our watchdog timer
1771 */
9d5c8243
AK		 1772 set_bit(__IGB_DOWN, &adapter->state);
1773
1774 /* disable receives in the hardware */
1775 rctl = rd32(E1000_RCTL);
1776 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1777 /* flush and sleep below */
1778
fd2ea0a7 1779 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1780
1781 /* disable transmits in the hardware */
1782 tctl = rd32(E1000_TCTL);
1783 tctl &= ~E1000_TCTL_EN;
1784 wr32(E1000_TCTL, tctl);
1785 /* flush both disables and wait for them to finish */
1786 wrfl();
0d451e79 1787 usleep_range(10000, 11000);
9d5c8243 1788
41f149a2
CW		 1789 igb_irq_disable(adapter);
1790
aa9b8cc4
AA		 1791 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1792
41f149a2
CW		 1793 for (i = 0; i < adapter->num_q_vectors; i++) {
1794 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1795 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1796 }
9d5c8243 1797
9d5c8243
AK		 1798
1799 del_timer_sync(&adapter->watchdog_timer);
1800 del_timer_sync(&adapter->phy_info_timer);
1801
9d5c8243 1802 netif_carrier_off(netdev);
04fe6358
AD		 1803
1804 /* record the stats before reset*/
12dcd86b
ED		 1805 spin_lock(&adapter->stats64_lock);
1806 igb_update_stats(adapter, &adapter->stats64);
1807 spin_unlock(&adapter->stats64_lock);
04fe6358 1808
9d5c8243
AK		 1809 adapter->link_speed = 0;
1810 adapter->link_duplex = 0;
1811
3023682e
JK		 1812 if (!pci_channel_offline(adapter->pdev))
1813 igb_reset(adapter);
9d5c8243
AK		 1814 igb_clean_all_tx_rings(adapter);
1815 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1816#ifdef CONFIG_IGB_DCA
1817
1818 /* since we reset the hardware DCA settings were cleared */
1819 igb_setup_dca(adapter);
1820#endif
9d5c8243
AK		 1821}
1822
1823void igb_reinit_locked(struct igb_adapter *adapter)
1824{
1825 WARN_ON(in_interrupt());
1826 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1827 usleep_range(1000, 2000);
9d5c8243
AK		 1828 igb_down(adapter);
1829 igb_up(adapter);
1830 clear_bit(__IGB_RESETTING, &adapter->state);
1831}
1832
56cec249
CW		 1833/** igb_enable_mas - Media Autosense re-enable after swap
1834 *
1835 * @adapter: adapter struct
1836 **/
1837static s32 igb_enable_mas(struct igb_adapter *adapter)
1838{
1839 struct e1000_hw *hw = &adapter->hw;
1840 u32 connsw;
1841 s32 ret_val = 0;
1842
1843 connsw = rd32(E1000_CONNSW);
1844 if (!(hw->phy.media_type == e1000_media_type_copper))
1845 return ret_val;
1846
1847 /* configure for SerDes media detect */
1848 if (!(connsw & E1000_CONNSW_SERDESD)) {
1849 connsw |= E1000_CONNSW_ENRGSRC;
1850 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1851 wr32(E1000_CONNSW, connsw);
1852 wrfl();
1853 } else if (connsw & E1000_CONNSW_SERDESD) {
1854 /* already SerDes, no need to enable anything */
1855 return ret_val;
1856 } else {
1857 netdev_info(adapter->netdev,
1858 "MAS: Unable to configure feature, disabling..\n");
1859 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1860 }
1861 return ret_val;
1862}
1863
9d5c8243
AK		 1864void igb_reset(struct igb_adapter *adapter)
1865{
090b1795 1866 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1867 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1868 struct e1000_mac_info *mac = &hw->mac;
1869 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1870 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1871
1872 /* Repartition Pba for greater than 9k mtu
1873 * To take effect CTRL.RST is required.
1874 */
fa4dfae0 1875 switch (mac->type) {
d2ba2ed8 1876 case e1000_i350:
ceb5f13b 1877 case e1000_i354:
55cac248
AD		 1878 case e1000_82580:
1879 pba = rd32(E1000_RXPBS);
1880 pba = igb_rxpbs_adjust_82580(pba);
1881 break;
fa4dfae0 1882 case e1000_82576:
d249be54
AD		 1883 pba = rd32(E1000_RXPBS);
1884 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1885 break;
1886 case e1000_82575:
f96a8a0b
CW		 1887 case e1000_i210:
1888 case e1000_i211:
fa4dfae0
AD		 1889 default:
1890 pba = E1000_PBA_34K;
1891 break;
2d064c06 1892 }
9d5c8243 1893
2d064c06
AD		 1894 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1895 (mac->type < e1000_82576)) {
9d5c8243
AK		 1896 /* adjust PBA for jumbo frames */
1897 wr32(E1000_PBA, pba);
1898
1899 /* To maintain wire speed transmits, the Tx FIFO should be
1900 * large enough to accommodate two full transmit packets,
1901 * rounded up to the next 1KB and expressed in KB. Likewise,
1902 * the Rx FIFO should be large enough to accommodate at least
1903 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1904 * expressed in KB.
1905 */
9d5c8243
AK		 1906 pba = rd32(E1000_PBA);
1907 /* upper 16 bits has Tx packet buffer allocation size in KB */
1908 tx_space = pba >> 16;
1909 /* lower 16 bits has Rx packet buffer allocation size in KB */
1910 pba &= 0xffff;
b980ac18
JK		 1911 /* the Tx fifo also stores 16 bytes of information about the Tx
1912 * but don't include ethernet FCS because hardware appends it
1913 */
9d5c8243 1914 min_tx_space = (adapter->max_frame_size +
85e8d004 1915 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1916 ETH_FCS_LEN) * 2;
1917 min_tx_space = ALIGN(min_tx_space, 1024);
1918 min_tx_space >>= 10;
1919 /* software strips receive CRC, so leave room for it */
1920 min_rx_space = adapter->max_frame_size;
1921 min_rx_space = ALIGN(min_rx_space, 1024);
1922 min_rx_space >>= 10;
1923
1924 /* If current Tx allocation is less than the min Tx FIFO size,
1925 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1926 * allocation, take space away from current Rx allocation
1927 */
9d5c8243
AK		 1928 if (tx_space < min_tx_space &&
1929 ((min_tx_space - tx_space) < pba)) {
1930 pba = pba - (min_tx_space - tx_space);
1931
b980ac18
JK		 1932 /* if short on Rx space, Rx wins and must trump Tx
1933 * adjustment
1934 */
9d5c8243
AK		 1935 if (pba < min_rx_space)
1936 pba = min_rx_space;
1937 }
2d064c06 1938 wr32(E1000_PBA, pba);
9d5c8243 1939 }
9d5c8243
AK		 1940
1941 /* flow control settings */
1942 /* The high water mark must be low enough to fit one full frame
1943 * (or the size used for early receive) above it in the Rx FIFO.
1944 * Set it to the lower of:
1945 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1946 * - the full Rx FIFO size minus one full frame
1947 */
9d5c8243 1948 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1949 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1950
d48507fe 1951 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1952 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1953 fc->pause_time = 0xFFFF;
1954 fc->send_xon = 1;
0cce119a 1955 fc->current_mode = fc->requested_mode;
9d5c8243 1956
4ae196df
AD		 1957 /* disable receive for all VFs and wait one second */
1958 if (adapter->vfs_allocated_count) {
1959 int i;
9005df38 1960
4ae196df 1961 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1962 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1963
1964 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1965 igb_ping_all_vfs(adapter);
4ae196df
AD		 1966
1967 /* disable transmits and receives */
1968 wr32(E1000_VFRE, 0);
1969 wr32(E1000_VFTE, 0);
1970 }
1971
9d5c8243 1972 /* Allow time for pending master requests to run */
330a6d6a 1973 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1974 wr32(E1000_WUC, 0);
1975
56cec249
CW		 1976 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1977 /* need to resetup here after media swap */
1978 adapter->ei.get_invariants(hw);
1979 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1980 }
1981 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1982 if (igb_enable_mas(adapter))
1983 dev_err(&pdev->dev,
1984 "Error enabling Media Auto Sense\n");
1985 }
330a6d6a 1986 if (hw->mac.ops.init_hw(hw))
090b1795 1987 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1988
b980ac18 1989 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1990 * control is off when forcing speed.
1991 */
1992 if (!hw->mac.autoneg)
1993 igb_force_mac_fc(hw);
1994
b6e0c419 1995 igb_init_dmac(adapter, pba);
e428893b
CW		 1996#ifdef CONFIG_IGB_HWMON
1997 /* Re-initialize the thermal sensor on i350 devices. */
1998 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1999 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2000 /* If present, re-initialize the external thermal sensor
2001 * interface.
2002 */
2003 if (adapter->ets)
2004 mac->ops.init_thermal_sensor_thresh(hw);
2005 }
2006 }
2007#endif
b936136d 2008 /* Re-establish EEE setting */
f4c01e96
CW		 2009 if (hw->phy.media_type == e1000_media_type_copper) {
2010 switch (mac->type) {
2011 case e1000_i350:
2012 case e1000_i210:
2013 case e1000_i211:
2014 igb_set_eee_i350(hw);
2015 break;
2016 case e1000_i354:
2017 igb_set_eee_i354(hw);
2018 break;
2019 default:
2020 break;
2021 }
2022 }
88a268c1
NN		 2023 if (!netif_running(adapter->netdev))
2024 igb_power_down_link(adapter);
2025
9d5c8243
AK		 2026 igb_update_mng_vlan(adapter);
2027
2028 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2029 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2030
1f6e8178
MV		 2031 /* Re-enable PTP, where applicable. */
2032 igb_ptp_reset(adapter);
1f6e8178 2033
330a6d6a 2034 igb_get_phy_info(hw);
9d5c8243
AK		 2035}
2036
c8f44aff
MM		 2037static netdev_features_t igb_fix_features(struct net_device *netdev,
2038 netdev_features_t features)
b2cb09b1 2039{
b980ac18
JK		 2040 /* Since there is no support for separate Rx/Tx vlan accel
2041 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2042 */
f646968f
PM		 2043 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2044 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2045 else
f646968f 2046 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2047
2048 return features;
2049}
2050
c8f44aff
MM		 2051static int igb_set_features(struct net_device *netdev,
2052 netdev_features_t features)
ac52caa3 2053{
c8f44aff 2054 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2055 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2056
f646968f 2057 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2058 igb_vlan_mode(netdev, features);
2059
89eaefb6
BG		 2060 if (!(changed & NETIF_F_RXALL))
2061 return 0;
2062
2063 netdev->features = features;
2064
2065 if (netif_running(netdev))
2066 igb_reinit_locked(adapter);
2067 else
2068 igb_reset(adapter);
2069
ac52caa3
MM		 2070 return 0;
2071}
2072
2e5c6922 2073static const struct net_device_ops igb_netdev_ops = {
559e9c49 2074 .ndo_open = igb_open,
2e5c6922 2075 .ndo_stop = igb_close,
cd392f5c 2076 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2077 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2078 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2079 .ndo_set_mac_address = igb_set_mac,
2080 .ndo_change_mtu = igb_change_mtu,
2081 .ndo_do_ioctl = igb_ioctl,
2082 .ndo_tx_timeout = igb_tx_timeout,
2083 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2084 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2085 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2086 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2087 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2088 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 2089 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2090 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2091#ifdef CONFIG_NET_POLL_CONTROLLER
2092 .ndo_poll_controller = igb_netpoll,
2093#endif
b2cb09b1
JP		 2094 .ndo_fix_features = igb_fix_features,
2095 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2096};
2097
d67974f0
CW		 2098/**
2099 * igb_set_fw_version - Configure version string for ethtool
2100 * @adapter: adapter struct
d67974f0
CW		 2101 **/
2102void igb_set_fw_version(struct igb_adapter *adapter)
2103{
2104 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2105 struct e1000_fw_version fw;
2106
2107 igb_get_fw_version(hw, &fw);
2108
2109 switch (hw->mac.type) {
7dc98a62 2110 case e1000_i210:
0b1a6f2e 2111 case e1000_i211:
7dc98a62
CW		 2112 if (!(igb_get_flash_presence_i210(hw))) {
2113 snprintf(adapter->fw_version,
2114 sizeof(adapter->fw_version),
2115 "%2d.%2d-%d",
2116 fw.invm_major, fw.invm_minor,
2117 fw.invm_img_type);
2118 break;
2119 }
2120 /* fall through */
0b1a6f2e
CW		 2121 default:
2122 /* if option is rom valid, display its version too */
2123 if (fw.or_valid) {
2124 snprintf(adapter->fw_version,
2125 sizeof(adapter->fw_version),
2126 "%d.%d, 0x%08x, %d.%d.%d",
2127 fw.eep_major, fw.eep_minor, fw.etrack_id,
2128 fw.or_major, fw.or_build, fw.or_patch);
2129 /* no option rom */
7dc98a62 2130 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2131 snprintf(adapter->fw_version,
7dc98a62
CW		 2132 sizeof(adapter->fw_version),
2133 "%d.%d, 0x%08x",
2134 fw.eep_major, fw.eep_minor, fw.etrack_id);
2135 } else {
2136 snprintf(adapter->fw_version,
2137 sizeof(adapter->fw_version),
2138 "%d.%d.%d",
2139 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2140 }
2141 break;
d67974f0 2142 }
d67974f0
CW		 2143 return;
2144}
2145
56cec249
CW		 2146/**
2147 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2148 *
2149 * @adapter: adapter struct
2150 **/
2151static void igb_init_mas(struct igb_adapter *adapter)
2152{
2153 struct e1000_hw *hw = &adapter->hw;
2154 u16 eeprom_data;
2155
2156 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2157 switch (hw->bus.func) {
2158 case E1000_FUNC_0:
2159 if (eeprom_data & IGB_MAS_ENABLE_0) {
2160 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2161 netdev_info(adapter->netdev,
2162 "MAS: Enabling Media Autosense for port %d\n",
2163 hw->bus.func);
2164 }
2165 break;
2166 case E1000_FUNC_1:
2167 if (eeprom_data & IGB_MAS_ENABLE_1) {
2168 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2169 netdev_info(adapter->netdev,
2170 "MAS: Enabling Media Autosense for port %d\n",
2171 hw->bus.func);
2172 }
2173 break;
2174 case E1000_FUNC_2:
2175 if (eeprom_data & IGB_MAS_ENABLE_2) {
2176 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2177 netdev_info(adapter->netdev,
2178 "MAS: Enabling Media Autosense for port %d\n",
2179 hw->bus.func);
2180 }
2181 break;
2182 case E1000_FUNC_3:
2183 if (eeprom_data & IGB_MAS_ENABLE_3) {
2184 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2185 netdev_info(adapter->netdev,
2186 "MAS: Enabling Media Autosense for port %d\n",
2187 hw->bus.func);
2188 }
2189 break;
2190 default:
2191 /* Shouldn't get here */
2192 netdev_err(adapter->netdev,
2193 "MAS: Invalid port configuration, returning\n");
2194 break;
2195 }
2196}
2197
b980ac18
JK		 2198/**
2199 * igb_init_i2c - Init I2C interface
441fc6fd 2200 * @adapter: pointer to adapter structure
b980ac18 2201 **/
441fc6fd
CW		 2202static s32 igb_init_i2c(struct igb_adapter *adapter)
2203{
2204 s32 status = E1000_SUCCESS;
2205
2206 /* I2C interface supported on i350 devices */
2207 if (adapter->hw.mac.type != e1000_i350)
2208 return E1000_SUCCESS;
2209
2210 /* Initialize the i2c bus which is controlled by the registers.
2211 * This bus will use the i2c_algo_bit structue that implements
2212 * the protocol through toggling of the 4 bits in the register.
2213 */
2214 adapter->i2c_adap.owner = THIS_MODULE;
2215 adapter->i2c_algo = igb_i2c_algo;
2216 adapter->i2c_algo.data = adapter;
2217 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2218 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2219 strlcpy(adapter->i2c_adap.name, "igb BB",
2220 sizeof(adapter->i2c_adap.name));
2221 status = i2c_bit_add_bus(&adapter->i2c_adap);
2222 return status;
2223}
2224
9d5c8243 2225/**
b980ac18
JK		 2226 * igb_probe - Device Initialization Routine
2227 * @pdev: PCI device information struct
2228 * @ent: entry in igb_pci_tbl
9d5c8243 2229 *
b980ac18 2230 * Returns 0 on success, negative on failure
9d5c8243 2231 *
b980ac18
JK		 2232 * igb_probe initializes an adapter identified by a pci_dev structure.
2233 * The OS initialization, configuring of the adapter private structure,
2234 * and a hardware reset occur.
9d5c8243 2235 **/
1dd06ae8 2236static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2237{
2238 struct net_device *netdev;
2239 struct igb_adapter *adapter;
2240 struct e1000_hw *hw;
4337e993 2241 u16 eeprom_data = 0;
9835fd73 2242 s32 ret_val;
4337e993 2243 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2244 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2245 int err, pci_using_dac;
9835fd73 2246 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2247
bded64a7
AG		 2248 /* Catch broken hardware that put the wrong VF device ID in
2249 * the PCIe SR-IOV capability.
2250 */
2251 if (pdev->is_virtfn) {
2252 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2253 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2254 return -EINVAL;
2255 }
2256
aed5dec3 2257 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2258 if (err)
2259 return err;
2260
2261 pci_using_dac = 0;
dc4ff9bb 2262 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2263 if (!err) {
dc4ff9bb 2264 pci_using_dac = 1;
9d5c8243 2265 } else {
dc4ff9bb 2266 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2267 if (err) {
dc4ff9bb
RK		 2268 dev_err(&pdev->dev,
2269 "No usable DMA configuration, aborting\n");
2270 goto err_dma;
9d5c8243
AK		 2271 }
2272 }
2273
aed5dec3 2274 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2275 IORESOURCE_MEM),
2276 igb_driver_name);
9d5c8243
AK		 2277 if (err)
2278 goto err_pci_reg;
2279
19d5afd4 2280 pci_enable_pcie_error_reporting(pdev);
40a914fa 2281
9d5c8243 2282 pci_set_master(pdev);
c682fc23 2283 pci_save_state(pdev);
9d5c8243
AK		 2284
2285 err = -ENOMEM;
1bfaf07b 2286 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2287 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2288 if (!netdev)
2289 goto err_alloc_etherdev;
2290
2291 SET_NETDEV_DEV(netdev, &pdev->dev);
2292
2293 pci_set_drvdata(pdev, netdev);
2294 adapter = netdev_priv(netdev);
2295 adapter->netdev = netdev;
2296 adapter->pdev = pdev;
2297 hw = &adapter->hw;
2298 hw->back = adapter;
b3f4d599 2299 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2300
9d5c8243 2301 err = -EIO;
89dbefb2 2302 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2303 if (!hw->hw_addr)
9d5c8243
AK		 2304 goto err_ioremap;
2305
2e5c6922 2306 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2307 igb_set_ethtool_ops(netdev);
9d5c8243 2308 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2309
2310 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2311
89dbefb2
AS		 2312 netdev->mem_start = pci_resource_start(pdev, 0);
2313 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2314
9d5c8243
AK		 2315 /* PCI config space info */
2316 hw->vendor_id = pdev->vendor;
2317 hw->device_id = pdev->device;
2318 hw->revision_id = pdev->revision;
2319 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2320 hw->subsystem_device_id = pdev->subsystem_device;
2321
9d5c8243
AK		 2322 /* Copy the default MAC, PHY and NVM function pointers */
2323 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2324 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2325 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2326 /* Initialize skew-specific constants */
2327 err = ei->get_invariants(hw);
2328 if (err)
450c87c8 2329 goto err_sw_init;
9d5c8243 2330
450c87c8 2331 /* setup the private structure */
9d5c8243
AK		 2332 err = igb_sw_init(adapter);
2333 if (err)
2334 goto err_sw_init;
2335
2336 igb_get_bus_info_pcie(hw);
2337
2338 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2339
2340 /* Copper options */
2341 if (hw->phy.media_type == e1000_media_type_copper) {
2342 hw->phy.mdix = AUTO_ALL_MODES;
2343 hw->phy.disable_polarity_correction = false;
2344 hw->phy.ms_type = e1000_ms_hw_default;
2345 }
2346
2347 if (igb_check_reset_block(hw))
2348 dev_info(&pdev->dev,
2349 "PHY reset is blocked due to SOL/IDER session.\n");
2350
b980ac18 2351 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2352 * set by igb_sw_init so we should use an or instead of an
2353 * assignment.
2354 */
2355 netdev->features |= NETIF_F_SG |
2356 NETIF_F_IP_CSUM |
2357 NETIF_F_IPV6_CSUM |
2358 NETIF_F_TSO |
2359 NETIF_F_TSO6 |
2360 NETIF_F_RXHASH |
2361 NETIF_F_RXCSUM |
f646968f
PM		 2362 NETIF_F_HW_VLAN_CTAG_RX |
2363 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2364
2365 /* copy netdev features into list of user selectable features */
2366 netdev->hw_features |= netdev->features;
89eaefb6 2367 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2368
2369 /* set this bit last since it cannot be part of hw_features */
f646968f 2370 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2371
2372 netdev->vlan_features |= NETIF_F_TSO |
2373 NETIF_F_TSO6 |
2374 NETIF_F_IP_CSUM |
2375 NETIF_F_IPV6_CSUM |
2376 NETIF_F_SG;
48f29ffc 2377
6b8f0922
BG		 2378 netdev->priv_flags |= IFF_SUPP_NOFCS;
2379
7b872a55 2380 if (pci_using_dac) {
9d5c8243 2381 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2382 netdev->vlan_features |= NETIF_F_HIGHDMA;
2383 }
9d5c8243 2384
ac52caa3
MM		 2385 if (hw->mac.type >= e1000_82576) {
2386 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2387 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2388 }
b9473560 2389
01789349
JP		 2390 netdev->priv_flags |= IFF_UNICAST_FLT;
2391
330a6d6a 2392 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2393
2394 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2395 * known good starting state
2396 */
9d5c8243
AK		 2397 hw->mac.ops.reset_hw(hw);
2398
ef3a0092
CW		 2399 /* make sure the NVM is good , i211/i210 parts can have special NVM
2400 * that doesn't contain a checksum
f96a8a0b 2401 */
ef3a0092
CW		 2402 switch (hw->mac.type) {
2403 case e1000_i210:
2404 case e1000_i211:
2405 if (igb_get_flash_presence_i210(hw)) {
2406 if (hw->nvm.ops.validate(hw) < 0) {
2407 dev_err(&pdev->dev,
2408 "The NVM Checksum Is Not Valid\n");
2409 err = -EIO;
2410 goto err_eeprom;
2411 }
2412 }
2413 break;
2414 default:
f96a8a0b
CW		 2415 if (hw->nvm.ops.validate(hw) < 0) {
2416 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2417 err = -EIO;
2418 goto err_eeprom;
2419 }
ef3a0092 2420 break;
9d5c8243
AK		 2421 }
2422
2423 /* copy the MAC address out of the NVM */
2424 if (hw->mac.ops.read_mac_addr(hw))
2425 dev_err(&pdev->dev, "NVM Read Error\n");
2426
2427 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2428
aaeb6cdf 2429 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2430 dev_err(&pdev->dev, "Invalid MAC Address\n");
2431 err = -EIO;
2432 goto err_eeprom;
2433 }
2434
d67974f0
CW		 2435 /* get firmware version for ethtool -i */
2436 igb_set_fw_version(adapter);
2437
c061b18d 2438 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2439 (unsigned long) adapter);
c061b18d 2440 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2441 (unsigned long) adapter);
9d5c8243
AK		 2442
2443 INIT_WORK(&adapter->reset_task, igb_reset_task);
2444 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2445
450c87c8 2446 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2447 adapter->fc_autoneg = true;
2448 hw->mac.autoneg = true;
2449 hw->phy.autoneg_advertised = 0x2f;
2450
0cce119a
AD		 2451 hw->fc.requested_mode = e1000_fc_default;
2452 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2453
9d5c8243
AK		 2454 igb_validate_mdi_setting(hw);
2455
63d4a8f9 2456 /* By default, support wake on port A */
a2cf8b6c 2457 if (hw->bus.func == 0)
63d4a8f9
MV		 2458 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2459
2460 /* Check the NVM for wake support on non-port A ports */
2461 if (hw->mac.type >= e1000_82580)
55cac248 2462 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2463 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2464 &eeprom_data);
a2cf8b6c
AD		 2465 else if (hw->bus.func == 1)
2466 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2467
63d4a8f9
MV		 2468 if (eeprom_data & IGB_EEPROM_APME)
2469 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2470
2471 /* now that we have the eeprom settings, apply the special cases where
2472 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2473 * lan on a particular port
2474 */
9d5c8243
AK		 2475 switch (pdev->device) {
2476 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2477 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2478 break;
2479 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2480 case E1000_DEV_ID_82576_FIBER:
2481 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2482 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2483 * regardless of eeprom setting
2484 */
9d5c8243 2485 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2486 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2487 break;
c8ea5ea9 2488 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2489 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2490 /* if quad port adapter, disable WoL on all but port A */
2491 if (global_quad_port_a != 0)
63d4a8f9 2492 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2493 else
2494 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2495 /* Reset for multiple quad port adapters */
2496 if (++global_quad_port_a == 4)
2497 global_quad_port_a = 0;
2498 break;
63d4a8f9
MV		 2499 default:
2500 /* If the device can't wake, don't set software support */
2501 if (!device_can_wakeup(&adapter->pdev->dev))
2502 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2503 }
2504
2505 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2506 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2507 adapter->wol |= E1000_WUFC_MAG;
2508
2509 /* Some vendors want WoL disabled by default, but still supported */
2510 if ((hw->mac.type == e1000_i350) &&
2511 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2512 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2513 adapter->wol = 0;
2514 }
2515
2516 device_set_wakeup_enable(&adapter->pdev->dev,
2517 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2518
2519 /* reset the hardware with the new settings */
2520 igb_reset(adapter);
2521
441fc6fd
CW		 2522 /* Init the I2C interface */
2523 err = igb_init_i2c(adapter);
2524 if (err) {
2525 dev_err(&pdev->dev, "failed to init i2c interface\n");
2526 goto err_eeprom;
2527 }
2528
9d5c8243 2529 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2530 * driver.
2531 */
9d5c8243
AK		 2532 igb_get_hw_control(adapter);
2533
9d5c8243
AK		 2534 strcpy(netdev->name, "eth%d");
2535 err = register_netdev(netdev);
2536 if (err)
2537 goto err_register;
2538
b168dfc5
JB		 2539 /* carrier off reporting is important to ethtool even BEFORE open */
2540 netif_carrier_off(netdev);
2541
421e02f0 2542#ifdef CONFIG_IGB_DCA
bbd98fe4 2543 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2544 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2545 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2546 igb_setup_dca(adapter);
2547 }
fe4506b6 2548
38c845c7 2549#endif
e428893b
CW		 2550#ifdef CONFIG_IGB_HWMON
2551 /* Initialize the thermal sensor on i350 devices. */
2552 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2553 u16 ets_word;
3c89f6d0 2554
b980ac18 2555 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2556 * external thermal sensor.
2557 */
2558 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2559 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2560 adapter->ets = true;
2561 else
2562 adapter->ets = false;
2563 if (igb_sysfs_init(adapter))
2564 dev_err(&pdev->dev,
2565 "failed to allocate sysfs resources\n");
2566 } else {
2567 adapter->ets = false;
2568 }
2569#endif
56cec249
CW		 2570 /* Check if Media Autosense is enabled */
2571 adapter->ei = *ei;
2572 if (hw->dev_spec._82575.mas_capable)
2573 igb_init_mas(adapter);
2574
673b8b70 2575 /* do hw tstamp init after resetting */
7ebae817 2576 igb_ptp_init(adapter);
673b8b70 2577
9d5c8243 2578 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2579 /* print bus type/speed/width info, not applicable to i354 */
2580 if (hw->mac.type != e1000_i354) {
2581 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2582 netdev->name,
2583 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2584 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2585 "unknown"),
2586 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2587 "Width x4" :
2588 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2589 "Width x2" :
2590 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2591 "Width x1" : "unknown"), netdev->dev_addr);
2592 }
9d5c8243 2593
53ea6c7e
TF		 2594 if ((hw->mac.type >= e1000_i210 ||
2595 igb_get_flash_presence_i210(hw))) {
2596 ret_val = igb_read_part_string(hw, part_str,
2597 E1000_PBANUM_LENGTH);
2598 } else {
2599 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2600 }
2601
9835fd73
CW		 2602 if (ret_val)
2603 strcpy(part_str, "Unknown");
2604 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2605 dev_info(&pdev->dev,
2606 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2607 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2608 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2609 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2610 if (hw->phy.media_type == e1000_media_type_copper) {
2611 switch (hw->mac.type) {
2612 case e1000_i350:
2613 case e1000_i210:
2614 case e1000_i211:
2615 /* Enable EEE for internal copper PHY devices */
2616 err = igb_set_eee_i350(hw);
2617 if ((!err) &&
2618 (!hw->dev_spec._82575.eee_disable)) {
2619 adapter->eee_advert =
2620 MDIO_EEE_100TX | MDIO_EEE_1000T;
2621 adapter->flags |= IGB_FLAG_EEE;
2622 }
2623 break;
2624 case e1000_i354:
ceb5f13b 2625 if ((rd32(E1000_CTRL_EXT) &
f4c01e96
CW		 2626 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2627 err = igb_set_eee_i354(hw);
2628 if ((!err) &&
2629 (!hw->dev_spec._82575.eee_disable)) {
2630 adapter->eee_advert =
2631 MDIO_EEE_100TX | MDIO_EEE_1000T;
2632 adapter->flags |= IGB_FLAG_EEE;
2633 }
2634 }
2635 break;
2636 default:
2637 break;
ceb5f13b 2638 }
09b068d4 2639 }
749ab2cd 2640 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2641 return 0;
2642
2643err_register:
2644 igb_release_hw_control(adapter);
441fc6fd 2645 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2646err_eeprom:
2647 if (!igb_check_reset_block(hw))
f5f4cf08 2648 igb_reset_phy(hw);
9d5c8243
AK		 2649
2650 if (hw->flash_address)
2651 iounmap(hw->flash_address);
9d5c8243 2652err_sw_init:
047e0030 2653 igb_clear_interrupt_scheme(adapter);
75009b3a 2654 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2655err_ioremap:
2656 free_netdev(netdev);
2657err_alloc_etherdev:
559e9c49 2658 pci_release_selected_regions(pdev,
b980ac18 2659 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2660err_pci_reg:
2661err_dma:
2662 pci_disable_device(pdev);
2663 return err;
2664}
2665
fa44f2f1 2666#ifdef CONFIG_PCI_IOV
781798a1 2667static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2668{
2669 struct net_device *netdev = pci_get_drvdata(pdev);
2670 struct igb_adapter *adapter = netdev_priv(netdev);
2671 struct e1000_hw *hw = &adapter->hw;
2672
2673 /* reclaim resources allocated to VFs */
2674 if (adapter->vf_data) {
2675 /* disable iov and allow time for transactions to clear */
b09186d2 2676 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2677 dev_warn(&pdev->dev,
2678 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2679 return -EPERM;
2680 } else {
2681 pci_disable_sriov(pdev);
2682 msleep(500);
2683 }
2684
2685 kfree(adapter->vf_data);
2686 adapter->vf_data = NULL;
2687 adapter->vfs_allocated_count = 0;
2688 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2689 wrfl();
2690 msleep(100);
2691 dev_info(&pdev->dev, "IOV Disabled\n");
2692
2693 /* Re-enable DMA Coalescing flag since IOV is turned off */
2694 adapter->flags |= IGB_FLAG_DMAC;
2695 }
2696
2697 return 0;
2698}
2699
2700static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2701{
2702 struct net_device *netdev = pci_get_drvdata(pdev);
2703 struct igb_adapter *adapter = netdev_priv(netdev);
2704 int old_vfs = pci_num_vf(pdev);
2705 int err = 0;
2706 int i;
2707
cd14ef54 2708 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2709 err = -EPERM;
2710 goto out;
2711 }
fa44f2f1
GR		 2712 if (!num_vfs)
2713 goto out;
fa44f2f1 2714
781798a1
SA		 2715 if (old_vfs) {
2716 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2717 old_vfs, max_vfs);
2718 adapter->vfs_allocated_count = old_vfs;
2719 } else
2720 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2721
2722 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2723 sizeof(struct vf_data_storage), GFP_KERNEL);
2724
2725 /* if allocation failed then we do not support SR-IOV */
2726 if (!adapter->vf_data) {
2727 adapter->vfs_allocated_count = 0;
2728 dev_err(&pdev->dev,
2729 "Unable to allocate memory for VF Data Storage\n");
2730 err = -ENOMEM;
2731 goto out;
2732 }
2733
781798a1
SA		 2734 /* only call pci_enable_sriov() if no VFs are allocated already */
2735 if (!old_vfs) {
2736 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2737 if (err)
2738 goto err_out;
2739 }
fa44f2f1
GR		 2740 dev_info(&pdev->dev, "%d VFs allocated\n",
2741 adapter->vfs_allocated_count);
2742 for (i = 0; i < adapter->vfs_allocated_count; i++)
2743 igb_vf_configure(adapter, i);
2744
2745 /* DMA Coalescing is not supported in IOV mode. */
2746 adapter->flags &= ~IGB_FLAG_DMAC;
2747 goto out;
2748
2749err_out:
2750 kfree(adapter->vf_data);
2751 adapter->vf_data = NULL;
2752 adapter->vfs_allocated_count = 0;
2753out:
2754 return err;
2755}
2756
2757#endif
b980ac18 2758/**
441fc6fd
CW		 2759 * igb_remove_i2c - Cleanup I2C interface
2760 * @adapter: pointer to adapter structure
b980ac18 2761 **/
441fc6fd
CW		 2762static void igb_remove_i2c(struct igb_adapter *adapter)
2763{
441fc6fd
CW		 2764 /* free the adapter bus structure */
2765 i2c_del_adapter(&adapter->i2c_adap);
2766}
2767
9d5c8243 2768/**
b980ac18
JK		 2769 * igb_remove - Device Removal Routine
2770 * @pdev: PCI device information struct
9d5c8243 2771 *
b980ac18
JK		 2772 * igb_remove is called by the PCI subsystem to alert the driver
2773 * that it should release a PCI device. The could be caused by a
2774 * Hot-Plug event, or because the driver is going to be removed from
2775 * memory.
9d5c8243 2776 **/
9f9a12f8 2777static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2778{
2779 struct net_device *netdev = pci_get_drvdata(pdev);
2780 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2781 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2782
749ab2cd 2783 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2784#ifdef CONFIG_IGB_HWMON
2785 igb_sysfs_exit(adapter);
2786#endif
441fc6fd 2787 igb_remove_i2c(adapter);
a79f4f88 2788 igb_ptp_stop(adapter);
b980ac18 2789 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2790 * disable watchdog from being rescheduled.
2791 */
9d5c8243
AK		 2792 set_bit(__IGB_DOWN, &adapter->state);
2793 del_timer_sync(&adapter->watchdog_timer);
2794 del_timer_sync(&adapter->phy_info_timer);
2795
760141a5
TH		 2796 cancel_work_sync(&adapter->reset_task);
2797 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2798
421e02f0 2799#ifdef CONFIG_IGB_DCA
7dfc16fa 2800 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2801 dev_info(&pdev->dev, "DCA disabled\n");
2802 dca_remove_requester(&pdev->dev);
7dfc16fa 2803 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2804 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2805 }
2806#endif
2807
9d5c8243 2808 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2809 * would have already happened in close and is redundant.
2810 */
9d5c8243
AK		 2811 igb_release_hw_control(adapter);
2812
2813 unregister_netdev(netdev);
2814
047e0030 2815 igb_clear_interrupt_scheme(adapter);
9d5c8243 2816
37680117 2817#ifdef CONFIG_PCI_IOV
fa44f2f1 2818 igb_disable_sriov(pdev);
37680117 2819#endif
559e9c49 2820
75009b3a 2821 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2822 if (hw->flash_address)
2823 iounmap(hw->flash_address);
559e9c49 2824 pci_release_selected_regions(pdev,
b980ac18 2825 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2826
1128c756 2827 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2828 free_netdev(netdev);
2829
19d5afd4 2830 pci_disable_pcie_error_reporting(pdev);
40a914fa 2831
9d5c8243
AK		 2832 pci_disable_device(pdev);
2833}
2834
a6b623e0 2835/**
b980ac18
JK		 2836 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2837 * @adapter: board private structure to initialize
a6b623e0 2838 *
b980ac18
JK		 2839 * This function initializes the vf specific data storage and then attempts to
2840 * allocate the VFs. The reason for ordering it this way is because it is much
2841 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2842 * the memory for the VFs.
a6b623e0 2843 **/
9f9a12f8 2844static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2845{
2846#ifdef CONFIG_PCI_IOV
2847 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2848 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2849
f96a8a0b
CW		 2850 /* Virtualization features not supported on i210 family. */
2851 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2852 return;
2853
fa44f2f1 2854 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2855 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2856
a6b623e0
AD		 2857#endif /* CONFIG_PCI_IOV */
2858}
2859
fa44f2f1 2860static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2861{
2862 struct e1000_hw *hw = &adapter->hw;
374a542d 2863 u32 max_rss_queues;
9d5c8243 2864
374a542d 2865 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2866 switch (hw->mac.type) {
374a542d
MV		 2867 case e1000_i211:
2868 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2869 break;
2870 case e1000_82575:
f96a8a0b 2871 case e1000_i210:
374a542d
MV		 2872 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2873 break;
2874 case e1000_i350:
2875 /* I350 cannot do RSS and SR-IOV at the same time */
2876 if (!!adapter->vfs_allocated_count) {
2877 max_rss_queues = 1;
2878 break;
2879 }
2880 /* fall through */
2881 case e1000_82576:
2882 if (!!adapter->vfs_allocated_count) {
2883 max_rss_queues = 2;
2884 break;
2885 }
2886 /* fall through */
2887 case e1000_82580:
ceb5f13b 2888 case e1000_i354:
374a542d
MV		 2889 default:
2890 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2891 break;
374a542d
MV		 2892 }
2893
2894 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2895
2896 /* Determine if we need to pair queues. */
2897 switch (hw->mac.type) {
2898 case e1000_82575:
f96a8a0b 2899 case e1000_i211:
374a542d 2900 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2901 break;
374a542d 2902 case e1000_82576:
b980ac18 2903 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2904 * should pair the queues in order to conserve interrupts due
2905 * to limited supply.
2906 */
2907 if ((adapter->rss_queues > 1) &&
2908 (adapter->vfs_allocated_count > 6))
2909 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2910 /* fall through */
2911 case e1000_82580:
2912 case e1000_i350:
ceb5f13b 2913 case e1000_i354:
374a542d 2914 case e1000_i210:
f96a8a0b 2915 default:
b980ac18 2916 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2917 * order to conserve interrupts due to limited supply.
2918 */
2919 if (adapter->rss_queues > (max_rss_queues / 2))
2920 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2921 break;
2922 }
fa44f2f1
GR		 2923}
2924
2925/**
b980ac18
JK		 2926 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2927 * @adapter: board private structure to initialize
fa44f2f1 2928 *
b980ac18
JK		 2929 * igb_sw_init initializes the Adapter private data structure.
2930 * Fields are initialized based on PCI device information and
2931 * OS network device settings (MTU size).
fa44f2f1
GR		 2932 **/
2933static int igb_sw_init(struct igb_adapter *adapter)
2934{
2935 struct e1000_hw *hw = &adapter->hw;
2936 struct net_device *netdev = adapter->netdev;
2937 struct pci_dev *pdev = adapter->pdev;
2938
2939 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2940
2941 /* set default ring sizes */
2942 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2943 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2944
2945 /* set default ITR values */
2946 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2947 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2948
2949 /* set default work limits */
2950 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2951
2952 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2953 VLAN_HLEN;
2954 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2955
2956 spin_lock_init(&adapter->stats64_lock);
2957#ifdef CONFIG_PCI_IOV
2958 switch (hw->mac.type) {
2959 case e1000_82576:
2960 case e1000_i350:
2961 if (max_vfs > 7) {
2962 dev_warn(&pdev->dev,
2963 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2964 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2965 } else
2966 adapter->vfs_allocated_count = max_vfs;
2967 if (adapter->vfs_allocated_count)
2968 dev_warn(&pdev->dev,
2969 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2970 break;
2971 default:
2972 break;
2973 }
2974#endif /* CONFIG_PCI_IOV */
2975
2976 igb_init_queue_configuration(adapter);
a99955fc 2977
1128c756 2978 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2979 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2980 GFP_ATOMIC);
1128c756 2981
a6b623e0 2982 /* This call may decrease the number of queues */
53c7d064 2983 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2984 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2985 return -ENOMEM;
2986 }
2987
a6b623e0
AD		 2988 igb_probe_vfs(adapter);
2989
9d5c8243
AK		 2990 /* Explicitly disable IRQ since the NIC can be in any state. */
2991 igb_irq_disable(adapter);
2992
f96a8a0b 2993 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2994 adapter->flags &= ~IGB_FLAG_DMAC;
2995
9d5c8243
AK		 2996 set_bit(__IGB_DOWN, &adapter->state);
2997 return 0;
2998}
2999
3000/**
b980ac18
JK		 3001 * igb_open - Called when a network interface is made active
3002 * @netdev: network interface device structure
9d5c8243 3003 *
b980ac18 3004 * Returns 0 on success, negative value on failure
9d5c8243 3005 *
b980ac18
JK		 3006 * The open entry point is called when a network interface is made
3007 * active by the system (IFF_UP). At this point all resources needed
3008 * for transmit and receive operations are allocated, the interrupt
3009 * handler is registered with the OS, the watchdog timer is started,
3010 * and the stack is notified that the interface is ready.
9d5c8243 3011 **/
749ab2cd 3012static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3013{
3014 struct igb_adapter *adapter = netdev_priv(netdev);
3015 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3016 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3017 int err;
3018 int i;
3019
3020 /* disallow open during test */
749ab2cd
YZ		 3021 if (test_bit(__IGB_TESTING, &adapter->state)) {
3022 WARN_ON(resuming);
9d5c8243 3023 return -EBUSY;
749ab2cd
YZ		 3024 }
3025
3026 if (!resuming)
3027 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3028
b168dfc5
JB		 3029 netif_carrier_off(netdev);
3030
9d5c8243
AK		 3031 /* allocate transmit descriptors */
3032 err = igb_setup_all_tx_resources(adapter);
3033 if (err)
3034 goto err_setup_tx;
3035
3036 /* allocate receive descriptors */
3037 err = igb_setup_all_rx_resources(adapter);
3038 if (err)
3039 goto err_setup_rx;
3040
88a268c1 3041 igb_power_up_link(adapter);
9d5c8243 3042
9d5c8243
AK		 3043 /* before we allocate an interrupt, we must be ready to handle it.
3044 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3045 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3046 * clean_rx handler before we do so.
3047 */
9d5c8243
AK		 3048 igb_configure(adapter);
3049
3050 err = igb_request_irq(adapter);
3051 if (err)
3052 goto err_req_irq;
3053
0c2cc02e
AD		 3054 /* Notify the stack of the actual queue counts. */
3055 err = netif_set_real_num_tx_queues(adapter->netdev,
3056 adapter->num_tx_queues);
3057 if (err)
3058 goto err_set_queues;
3059
3060 err = netif_set_real_num_rx_queues(adapter->netdev,
3061 adapter->num_rx_queues);
3062 if (err)
3063 goto err_set_queues;
3064
9d5c8243
AK		 3065 /* From here on the code is the same as igb_up() */
3066 clear_bit(__IGB_DOWN, &adapter->state);
3067
0d1ae7f4
AD		 3068 for (i = 0; i < adapter->num_q_vectors; i++)
3069 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3070
3071 /* Clear any pending interrupts. */
3072 rd32(E1000_ICR);
844290e5
PW		 3073
3074 igb_irq_enable(adapter);
3075
d4960307
AD		 3076 /* notify VFs that reset has been completed */
3077 if (adapter->vfs_allocated_count) {
3078 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3079
d4960307
AD		 3080 reg_data |= E1000_CTRL_EXT_PFRSTD;
3081 wr32(E1000_CTRL_EXT, reg_data);
3082 }
3083
d55b53ff
JK		 3084 netif_tx_start_all_queues(netdev);
3085
749ab2cd
YZ		 3086 if (!resuming)
3087 pm_runtime_put(&pdev->dev);
3088
25568a53
AD		 3089 /* start the watchdog. */
3090 hw->mac.get_link_status = 1;
3091 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3092
3093 return 0;
3094
0c2cc02e
AD		 3095err_set_queues:
3096 igb_free_irq(adapter);
9d5c8243
AK		 3097err_req_irq:
3098 igb_release_hw_control(adapter);
88a268c1 3099 igb_power_down_link(adapter);
9d5c8243
AK		 3100 igb_free_all_rx_resources(adapter);
3101err_setup_rx:
3102 igb_free_all_tx_resources(adapter);
3103err_setup_tx:
3104 igb_reset(adapter);
749ab2cd
YZ		 3105 if (!resuming)
3106 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3107
3108 return err;
3109}
3110
749ab2cd
YZ		 3111static int igb_open(struct net_device *netdev)
3112{
3113 return __igb_open(netdev, false);
3114}
3115
9d5c8243 3116/**
b980ac18
JK		 3117 * igb_close - Disables a network interface
3118 * @netdev: network interface device structure
9d5c8243 3119 *
b980ac18 3120 * Returns 0, this is not allowed to fail
9d5c8243 3121 *
b980ac18
JK		 3122 * The close entry point is called when an interface is de-activated
3123 * by the OS. The hardware is still under the driver's control, but
3124 * needs to be disabled. A global MAC reset is issued to stop the
3125 * hardware, and all transmit and receive resources are freed.
9d5c8243 3126 **/
749ab2cd 3127static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3128{
3129 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3130 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3131
3132 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3133
749ab2cd
YZ		 3134 if (!suspending)
3135 pm_runtime_get_sync(&pdev->dev);
3136
3137 igb_down(adapter);
9d5c8243
AK		 3138 igb_free_irq(adapter);
3139
3140 igb_free_all_tx_resources(adapter);
3141 igb_free_all_rx_resources(adapter);
3142
749ab2cd
YZ		 3143 if (!suspending)
3144 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3145 return 0;
3146}
3147
749ab2cd
YZ		 3148static int igb_close(struct net_device *netdev)
3149{
3150 return __igb_close(netdev, false);
3151}
3152
9d5c8243 3153/**
b980ac18
JK		 3154 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3155 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3156 *
b980ac18 3157 * Return 0 on success, negative on failure
9d5c8243 3158 **/
80785298 3159int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3160{
59d71989 3161 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3162 int size;
3163
06034649 3164 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3165
3166 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3167 if (!tx_ring->tx_buffer_info)
9d5c8243 3168 goto err;
9d5c8243
AK		 3169
3170 /* round up to nearest 4K */
85e8d004 3171 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3172 tx_ring->size = ALIGN(tx_ring->size, 4096);
3173
5536d210
AD		 3174 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3175 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3176 if (!tx_ring->desc)
3177 goto err;
3178
9d5c8243
AK		 3179 tx_ring->next_to_use = 0;
3180 tx_ring->next_to_clean = 0;
81c2fc22 3181
9d5c8243
AK		 3182 return 0;
3183
3184err:
06034649 3185 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3186 tx_ring->tx_buffer_info = NULL;
3187 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3188 return -ENOMEM;
3189}
3190
3191/**
b980ac18
JK		 3192 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3193 * (Descriptors) for all queues
3194 * @adapter: board private structure
9d5c8243 3195 *
b980ac18 3196 * Return 0 on success, negative on failure
9d5c8243
AK		 3197 **/
3198static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3199{
439705e1 3200 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3201 int i, err = 0;
3202
3203 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3204 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3205 if (err) {
439705e1 3206 dev_err(&pdev->dev,
9d5c8243
AK		 3207 "Allocation for Tx Queue %u failed\n", i);
3208 for (i--; i >= 0; i--)
3025a446 3209 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3210 break;
3211 }
3212 }
3213
3214 return err;
3215}
3216
3217/**
b980ac18
JK		 3218 * igb_setup_tctl - configure the transmit control registers
3219 * @adapter: Board private structure
9d5c8243 3220 **/
d7ee5b3a 3221void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3222{
9d5c8243
AK		 3223 struct e1000_hw *hw = &adapter->hw;
3224 u32 tctl;
9d5c8243 3225
85b430b4
AD		 3226 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3227 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3228
3229 /* Program the Transmit Control Register */
9d5c8243
AK		 3230 tctl = rd32(E1000_TCTL);
3231 tctl &= ~E1000_TCTL_CT;
3232 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3233 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3234
3235 igb_config_collision_dist(hw);
3236
9d5c8243
AK		 3237 /* Enable transmits */
3238 tctl |= E1000_TCTL_EN;
3239
3240 wr32(E1000_TCTL, tctl);
3241}
3242
85b430b4 3243/**
b980ac18
JK		 3244 * igb_configure_tx_ring - Configure transmit ring after Reset
3245 * @adapter: board private structure
3246 * @ring: tx ring to configure
85b430b4 3247 *
b980ac18 3248 * Configure a transmit ring after a reset.
85b430b4 3249 **/
d7ee5b3a 3250void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3251 struct igb_ring *ring)
85b430b4
AD		 3252{
3253 struct e1000_hw *hw = &adapter->hw;
a74420e0 3254 u32 txdctl = 0;
85b430b4
AD		 3255 u64 tdba = ring->dma;
3256 int reg_idx = ring->reg_idx;
3257
3258 /* disable the queue */
a74420e0 3259 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3260 wrfl();
3261 mdelay(10);
3262
3263 wr32(E1000_TDLEN(reg_idx),
b980ac18 3264 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3265 wr32(E1000_TDBAL(reg_idx),
b980ac18 3266 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3267 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3268
fce99e34 3269 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3270 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3271 writel(0, ring->tail);
85b430b4
AD		 3272
3273 txdctl |= IGB_TX_PTHRESH;
3274 txdctl |= IGB_TX_HTHRESH << 8;
3275 txdctl |= IGB_TX_WTHRESH << 16;
3276
3277 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3278 wr32(E1000_TXDCTL(reg_idx), txdctl);
3279}
3280
3281/**
b980ac18
JK		 3282 * igb_configure_tx - Configure transmit Unit after Reset
3283 * @adapter: board private structure
85b430b4 3284 *
b980ac18 3285 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3286 **/
3287static void igb_configure_tx(struct igb_adapter *adapter)
3288{
3289 int i;
3290
3291 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3292 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3293}
3294
9d5c8243 3295/**
b980ac18
JK		 3296 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3297 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3298 *
b980ac18 3299 * Returns 0 on success, negative on failure
9d5c8243 3300 **/
80785298 3301int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3302{
59d71989 3303 struct device *dev = rx_ring->dev;
f33005a6 3304 int size;
9d5c8243 3305
06034649 3306 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3307
3308 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3309 if (!rx_ring->rx_buffer_info)
9d5c8243 3310 goto err;
9d5c8243 3311
9d5c8243 3312 /* Round up to nearest 4K */
f33005a6 3313 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3314 rx_ring->size = ALIGN(rx_ring->size, 4096);
3315
5536d210
AD		 3316 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3317 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3318 if (!rx_ring->desc)
3319 goto err;
3320
cbc8e55f 3321 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3322 rx_ring->next_to_clean = 0;
3323 rx_ring->next_to_use = 0;
9d5c8243 3324
9d5c8243
AK		 3325 return 0;
3326
3327err:
06034649
AD		 3328 vfree(rx_ring->rx_buffer_info);
3329 rx_ring->rx_buffer_info = NULL;
f33005a6 3330 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3331 return -ENOMEM;
3332}
3333
3334/**
b980ac18
JK		 3335 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3336 * (Descriptors) for all queues
3337 * @adapter: board private structure
9d5c8243 3338 *
b980ac18 3339 * Return 0 on success, negative on failure
9d5c8243
AK		 3340 **/
3341static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3342{
439705e1 3343 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3344 int i, err = 0;
3345
3346 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3347 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3348 if (err) {
439705e1 3349 dev_err(&pdev->dev,
9d5c8243
AK		 3350 "Allocation for Rx Queue %u failed\n", i);
3351 for (i--; i >= 0; i--)
3025a446 3352 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3353 break;
3354 }
3355 }
3356
3357 return err;
3358}
3359
06cf2666 3360/**
b980ac18
JK		 3361 * igb_setup_mrqc - configure the multiple receive queue control registers
3362 * @adapter: Board private structure
06cf2666
AD		 3363 **/
3364static void igb_setup_mrqc(struct igb_adapter *adapter)
3365{
3366 struct e1000_hw *hw = &adapter->hw;
3367 u32 mrqc, rxcsum;
ed12cc9a 3368 u32 j, num_rx_queues;
a57fe23e
AD		 3369 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3370 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3371 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3372 0xFA01ACBE };
06cf2666
AD		 3373
3374 /* Fill out hash function seeds */
a57fe23e
AD		 3375 for (j = 0; j < 10; j++)
3376 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3377
a99955fc 3378 num_rx_queues = adapter->rss_queues;
06cf2666 3379
797fd4be 3380 switch (hw->mac.type) {
797fd4be
AD		 3381 case e1000_82576:
3382 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3383 if (adapter->vfs_allocated_count)
06cf2666 3384 num_rx_queues = 2;
797fd4be
AD		 3385 break;
3386 default:
3387 break;
06cf2666
AD		 3388 }
3389
ed12cc9a
LMV		 3390 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3391 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3392 adapter->rss_indir_tbl[j] =
3393 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3394 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3395 }
ed12cc9a 3396 igb_write_rss_indir_tbl(adapter);
06cf2666 3397
b980ac18 3398 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3399 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3400 * offloads as they are enabled by default
3401 */
3402 rxcsum = rd32(E1000_RXCSUM);
3403 rxcsum |= E1000_RXCSUM_PCSD;
3404
3405 if (adapter->hw.mac.type >= e1000_82576)
3406 /* Enable Receive Checksum Offload for SCTP */
3407 rxcsum |= E1000_RXCSUM_CRCOFL;
3408
3409 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3410 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3411
039454a8
AA		 3412 /* Generate RSS hash based on packet types, TCP/UDP
3413 * port numbers and/or IPv4/v6 src and dst addresses
3414 */
f96a8a0b
CW		 3415 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3416 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3417 E1000_MRQC_RSS_FIELD_IPV6 |
3418 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3419 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3420
039454a8
AA		 3421 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3422 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3423 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3424 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3425
06cf2666
AD		 3426 /* If VMDq is enabled then we set the appropriate mode for that, else
3427 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3428 * if we are only using one queue
3429 */
06cf2666
AD		 3430 if (adapter->vfs_allocated_count) {
3431 if (hw->mac.type > e1000_82575) {
3432 /* Set the default pool for the PF's first queue */
3433 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3434
06cf2666
AD		 3435 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3436 E1000_VT_CTL_DISABLE_DEF_POOL);
3437 vtctl |= adapter->vfs_allocated_count <<
3438 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3439 wr32(E1000_VT_CTL, vtctl);
3440 }
a99955fc 3441 if (adapter->rss_queues > 1)
f96a8a0b 3442 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3443 else
f96a8a0b 3444 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3445 } else {
f96a8a0b
CW		 3446 if (hw->mac.type != e1000_i211)
3447 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3448 }
3449 igb_vmm_control(adapter);
3450
06cf2666
AD		 3451 wr32(E1000_MRQC, mrqc);
3452}
3453
9d5c8243 3454/**
b980ac18
JK		 3455 * igb_setup_rctl - configure the receive control registers
3456 * @adapter: Board private structure
9d5c8243 3457 **/
d7ee5b3a 3458void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3459{
3460 struct e1000_hw *hw = &adapter->hw;
3461 u32 rctl;
9d5c8243
AK		 3462
3463 rctl = rd32(E1000_RCTL);
3464
3465 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3466 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3467
69d728ba 3468 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3469 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3470
b980ac18 3471 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3472 * redirection as it did with e1000. Newer features require
3473 * that the HW strips the CRC.
73cd78f1 3474 */
87cb7e8c 3475 rctl |= E1000_RCTL_SECRC;
9d5c8243 3476
559e9c49 3477 /* disable store bad packets and clear size bits. */
ec54d7d6 3478 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3479
6ec43fe6
AD		 3480 /* enable LPE to prevent packets larger than max_frame_size */
3481 rctl |= E1000_RCTL_LPE;
9d5c8243 3482
952f72a8
AD		 3483 /* disable queue 0 to prevent tail write w/o re-config */
3484 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3485
e1739522
AD		 3486 /* Attention!!! For SR-IOV PF driver operations you must enable
3487 * queue drop for all VF and PF queues to prevent head of line blocking
3488 * if an un-trusted VF does not provide descriptors to hardware.
3489 */
3490 if (adapter->vfs_allocated_count) {
e1739522
AD		 3491 /* set all queue drop enable bits */
3492 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3493 }
3494
89eaefb6
BG		 3495 /* This is useful for sniffing bad packets. */
3496 if (adapter->netdev->features & NETIF_F_RXALL) {
3497 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3498 * in e1000e_set_rx_mode
3499 */
89eaefb6
BG		 3500 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3501 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3502 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3503
3504 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3505 E1000_RCTL_DPF | /* Allow filtered pause */
3506 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3507 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3508 * and that breaks VLANs.
3509 */
3510 }
3511
9d5c8243
AK		 3512 wr32(E1000_RCTL, rctl);
3513}
3514
7d5753f0 3515static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3516 int vfn)
7d5753f0
AD		 3517{
3518 struct e1000_hw *hw = &adapter->hw;
3519 u32 vmolr;
3520
3521 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3522 * increase the size to support vlan tags
3523 */
7d5753f0
AD		 3524 if (vfn < adapter->vfs_allocated_count &&
3525 adapter->vf_data[vfn].vlans_enabled)
3526 size += VLAN_TAG_SIZE;
3527
3528 vmolr = rd32(E1000_VMOLR(vfn));
3529 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3530 vmolr |= size | E1000_VMOLR_LPE;
3531 wr32(E1000_VMOLR(vfn), vmolr);
3532
3533 return 0;
3534}
3535
e1739522 3536/**
b980ac18
JK		 3537 * igb_rlpml_set - set maximum receive packet size
3538 * @adapter: board private structure
e1739522 3539 *
b980ac18 3540 * Configure maximum receivable packet size.
e1739522
AD		 3541 **/
3542static void igb_rlpml_set(struct igb_adapter *adapter)
3543{
153285f9 3544 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3545 struct e1000_hw *hw = &adapter->hw;
3546 u16 pf_id = adapter->vfs_allocated_count;
3547
e1739522
AD		 3548 if (pf_id) {
3549 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3550 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3551 * to our max jumbo frame size, in case we need to enable
3552 * jumbo frames on one of the rings later.
3553 * This will not pass over-length frames into the default
3554 * queue because it's gated by the VMOLR.RLPML.
3555 */
7d5753f0 3556 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3557 }
3558
3559 wr32(E1000_RLPML, max_frame_size);
3560}
3561
8151d294
WM		 3562static inline void igb_set_vmolr(struct igb_adapter *adapter,
3563 int vfn, bool aupe)
7d5753f0
AD		 3564{
3565 struct e1000_hw *hw = &adapter->hw;
3566 u32 vmolr;
3567
b980ac18 3568 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3569 * we should exit and do nothing
3570 */
3571 if (hw->mac.type < e1000_82576)
3572 return;
3573
3574 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3575 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3576 if (hw->mac.type == e1000_i350) {
3577 u32 dvmolr;
3578
3579 dvmolr = rd32(E1000_DVMOLR(vfn));
3580 dvmolr |= E1000_DVMOLR_STRVLAN;
3581 wr32(E1000_DVMOLR(vfn), dvmolr);
3582 }
8151d294 3583 if (aupe)
b980ac18 3584 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3585 else
3586 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3587
3588 /* clear all bits that might not be set */
3589 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3590
a99955fc 3591 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3592 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3593 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3594 * multicast packets
3595 */
3596 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3597 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3598
3599 wr32(E1000_VMOLR(vfn), vmolr);
3600}
3601
85b430b4 3602/**
b980ac18
JK		 3603 * igb_configure_rx_ring - Configure a receive ring after Reset
3604 * @adapter: board private structure
3605 * @ring: receive ring to be configured
85b430b4 3606 *
b980ac18 3607 * Configure the Rx unit of the MAC after a reset.
85b430b4 3608 **/
d7ee5b3a 3609void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3610 struct igb_ring *ring)
85b430b4
AD		 3611{
3612 struct e1000_hw *hw = &adapter->hw;
3613 u64 rdba = ring->dma;
3614 int reg_idx = ring->reg_idx;
a74420e0 3615 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3616
3617 /* disable the queue */
a74420e0 3618 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3619
3620 /* Set DMA base address registers */
3621 wr32(E1000_RDBAL(reg_idx),
3622 rdba & 0x00000000ffffffffULL);
3623 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3624 wr32(E1000_RDLEN(reg_idx),
b980ac18 3625 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3626
3627 /* initialize head and tail */
fce99e34 3628 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3629 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3630 writel(0, ring->tail);
85b430b4 3631
952f72a8 3632 /* set descriptor configuration */
44390ca6 3633 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3634 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3635 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3636 if (hw->mac.type >= e1000_82580)
757b77e2 3637 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3638 /* Only set Drop Enable if we are supporting multiple queues */
3639 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3640 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3641
3642 wr32(E1000_SRRCTL(reg_idx), srrctl);
3643
7d5753f0 3644 /* set filtering for VMDQ pools */
8151d294 3645 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3646
85b430b4
AD		 3647 rxdctl |= IGB_RX_PTHRESH;
3648 rxdctl |= IGB_RX_HTHRESH << 8;
3649 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3650
3651 /* enable receive descriptor fetching */
3652 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3653 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3654}
3655
9d5c8243 3656/**
b980ac18
JK		 3657 * igb_configure_rx - Configure receive Unit after Reset
3658 * @adapter: board private structure
9d5c8243 3659 *
b980ac18 3660 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3661 **/
3662static void igb_configure_rx(struct igb_adapter *adapter)
3663{
9107584e 3664 int i;
9d5c8243 3665
68d480c4
AD		 3666 /* set UTA to appropriate mode */
3667 igb_set_uta(adapter);
3668
26ad9178
AD		 3669 /* set the correct pool for the PF default MAC address in entry 0 */
3670 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3671 adapter->vfs_allocated_count);
26ad9178 3672
06cf2666 3673 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3674 * the Base and Length of the Rx Descriptor Ring
3675 */
f9d40f6a
AD		 3676 for (i = 0; i < adapter->num_rx_queues; i++)
3677 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3678}
3679
3680/**
b980ac18
JK		 3681 * igb_free_tx_resources - Free Tx Resources per Queue
3682 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3683 *
b980ac18 3684 * Free all transmit software resources
9d5c8243 3685 **/
68fd9910 3686void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3687{
3b644cf6 3688 igb_clean_tx_ring(tx_ring);
9d5c8243 3689
06034649
AD		 3690 vfree(tx_ring->tx_buffer_info);
3691 tx_ring->tx_buffer_info = NULL;
9d5c8243 3692
439705e1
AD		 3693 /* if not set, then don't free */
3694 if (!tx_ring->desc)
3695 return;
3696
59d71989
AD		 3697 dma_free_coherent(tx_ring->dev, tx_ring->size,
3698 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3699
3700 tx_ring->desc = NULL;
3701}
3702
3703/**
b980ac18
JK		 3704 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3705 * @adapter: board private structure
9d5c8243 3706 *
b980ac18 3707 * Free all transmit software resources
9d5c8243
AK		 3708 **/
3709static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3710{
3711 int i;
3712
3713 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3714 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3715}
3716
ebe42d16
AD		 3717void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3718 struct igb_tx_buffer *tx_buffer)
3719{
3720 if (tx_buffer->skb) {
3721 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3722 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3723 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3724 dma_unmap_addr(tx_buffer, dma),
3725 dma_unmap_len(tx_buffer, len),
ebe42d16 3726 DMA_TO_DEVICE);
c9f14bf3 3727 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3728 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3729 dma_unmap_addr(tx_buffer, dma),
3730 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3731 DMA_TO_DEVICE);
3732 }
3733 tx_buffer->next_to_watch = NULL;
3734 tx_buffer->skb = NULL;
c9f14bf3 3735 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3736 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3737}
3738
3739/**
b980ac18
JK		 3740 * igb_clean_tx_ring - Free Tx Buffers
3741 * @tx_ring: ring to be cleaned
9d5c8243 3742 **/
3b644cf6 3743static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3744{
06034649 3745 struct igb_tx_buffer *buffer_info;
9d5c8243 3746 unsigned long size;
6ad4edfc 3747 u16 i;
9d5c8243 3748
06034649 3749 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3750 return;
3751 /* Free all the Tx ring sk_buffs */
3752
3753 for (i = 0; i < tx_ring->count; i++) {
06034649 3754 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3755 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3756 }
3757
dad8a3b3
JF		 3758 netdev_tx_reset_queue(txring_txq(tx_ring));
3759
06034649
AD		 3760 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3761 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3762
3763 /* Zero out the descriptor ring */
9d5c8243
AK		 3764 memset(tx_ring->desc, 0, tx_ring->size);
3765
3766 tx_ring->next_to_use = 0;
3767 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3768}
3769
3770/**
b980ac18
JK		 3771 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3772 * @adapter: board private structure
9d5c8243
AK		 3773 **/
3774static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3775{
3776 int i;
3777
3778 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3779 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3780}
3781
3782/**
b980ac18
JK		 3783 * igb_free_rx_resources - Free Rx Resources
3784 * @rx_ring: ring to clean the resources from
9d5c8243 3785 *
b980ac18 3786 * Free all receive software resources
9d5c8243 3787 **/
68fd9910 3788void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3789{
3b644cf6 3790 igb_clean_rx_ring(rx_ring);
9d5c8243 3791
06034649
AD		 3792 vfree(rx_ring->rx_buffer_info);
3793 rx_ring->rx_buffer_info = NULL;
9d5c8243 3794
439705e1
AD		 3795 /* if not set, then don't free */
3796 if (!rx_ring->desc)
3797 return;
3798
59d71989
AD		 3799 dma_free_coherent(rx_ring->dev, rx_ring->size,
3800 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3801
3802 rx_ring->desc = NULL;
3803}
3804
3805/**
b980ac18
JK		 3806 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3807 * @adapter: board private structure
9d5c8243 3808 *
b980ac18 3809 * Free all receive software resources
9d5c8243
AK		 3810 **/
3811static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3812{
3813 int i;
3814
3815 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3816 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3817}
3818
3819/**
b980ac18
JK		 3820 * igb_clean_rx_ring - Free Rx Buffers per Queue
3821 * @rx_ring: ring to free buffers from
9d5c8243 3822 **/
3b644cf6 3823static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3824{
9d5c8243 3825 unsigned long size;
c023cd88 3826 u16 i;
9d5c8243 3827
1a1c225b
AD		 3828 if (rx_ring->skb)
3829 dev_kfree_skb(rx_ring->skb);
3830 rx_ring->skb = NULL;
3831
06034649 3832 if (!rx_ring->rx_buffer_info)
9d5c8243 3833 return;
439705e1 3834
9d5c8243
AK		 3835 /* Free all the Rx ring sk_buffs */
3836 for (i = 0; i < rx_ring->count; i++) {
06034649 3837 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3838
cbc8e55f
AD		 3839 if (!buffer_info->page)
3840 continue;
3841
3842 dma_unmap_page(rx_ring->dev,
3843 buffer_info->dma,
3844 PAGE_SIZE,
3845 DMA_FROM_DEVICE);
3846 __free_page(buffer_info->page);
3847
1a1c225b 3848 buffer_info->page = NULL;
9d5c8243
AK		 3849 }
3850
06034649
AD		 3851 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3852 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3853
3854 /* Zero out the descriptor ring */
3855 memset(rx_ring->desc, 0, rx_ring->size);
3856
cbc8e55f 3857 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3858 rx_ring->next_to_clean = 0;
3859 rx_ring->next_to_use = 0;
9d5c8243
AK		 3860}
3861
3862/**
b980ac18
JK		 3863 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3864 * @adapter: board private structure
9d5c8243
AK		 3865 **/
3866static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3867{
3868 int i;
3869
3870 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3871 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3872}
3873
3874/**
b980ac18
JK		 3875 * igb_set_mac - Change the Ethernet Address of the NIC
3876 * @netdev: network interface device structure
3877 * @p: pointer to an address structure
9d5c8243 3878 *
b980ac18 3879 * Returns 0 on success, negative on failure
9d5c8243
AK		 3880 **/
3881static int igb_set_mac(struct net_device *netdev, void *p)
3882{
3883 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3884 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3885 struct sockaddr *addr = p;
3886
3887 if (!is_valid_ether_addr(addr->sa_data))
3888 return -EADDRNOTAVAIL;
3889
3890 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3891 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3892
26ad9178
AD		 3893 /* set the correct pool for the new PF MAC address in entry 0 */
3894 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3895 adapter->vfs_allocated_count);
e1739522 3896
9d5c8243
AK		 3897 return 0;
3898}
3899
3900/**
b980ac18
JK		 3901 * igb_write_mc_addr_list - write multicast addresses to MTA
3902 * @netdev: network interface device structure
9d5c8243 3903 *
b980ac18
JK		 3904 * Writes multicast address list to the MTA hash table.
3905 * Returns: -ENOMEM on failure
3906 * 0 on no addresses written
3907 * X on writing X addresses to MTA
9d5c8243 3908 **/
68d480c4 3909static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3910{
3911 struct igb_adapter *adapter = netdev_priv(netdev);
3912 struct e1000_hw *hw = &adapter->hw;
22bedad3 3913 struct netdev_hw_addr *ha;
68d480c4 3914 u8 *mta_list;
9d5c8243
AK		 3915 int i;
3916
4cd24eaf 3917 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3918 /* nothing to program, so clear mc list */
3919 igb_update_mc_addr_list(hw, NULL, 0);
3920 igb_restore_vf_multicasts(adapter);
3921 return 0;
3922 }
9d5c8243 3923
4cd24eaf 3924 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3925 if (!mta_list)
3926 return -ENOMEM;
ff41f8dc 3927
68d480c4 3928 /* The shared function expects a packed array of only addresses. */
48e2f183 3929 i = 0;
22bedad3
JP		 3930 netdev_for_each_mc_addr(ha, netdev)
3931 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3932
68d480c4
AD		 3933 igb_update_mc_addr_list(hw, mta_list, i);
3934 kfree(mta_list);
3935
4cd24eaf 3936 return netdev_mc_count(netdev);
68d480c4
AD		 3937}
3938
3939/**
b980ac18
JK		 3940 * igb_write_uc_addr_list - write unicast addresses to RAR table
3941 * @netdev: network interface device structure
68d480c4 3942 *
b980ac18
JK		 3943 * Writes unicast address list to the RAR table.
3944 * Returns: -ENOMEM on failure/insufficient address space
3945 * 0 on no addresses written
3946 * X on writing X addresses to the RAR table
68d480c4
AD		 3947 **/
3948static int igb_write_uc_addr_list(struct net_device *netdev)
3949{
3950 struct igb_adapter *adapter = netdev_priv(netdev);
3951 struct e1000_hw *hw = &adapter->hw;
3952 unsigned int vfn = adapter->vfs_allocated_count;
3953 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3954 int count = 0;
3955
3956 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3957 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3958 return -ENOMEM;
9d5c8243 3959
32e7bfc4 3960 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3961 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3962
3963 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3964 if (!rar_entries)
3965 break;
26ad9178 3966 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3967 rar_entries--,
3968 vfn);
68d480c4 3969 count++;
ff41f8dc
AD		 3970 }
3971 }
3972 /* write the addresses in reverse order to avoid write combining */
3973 for (; rar_entries > 0 ; rar_entries--) {
3974 wr32(E1000_RAH(rar_entries), 0);
3975 wr32(E1000_RAL(rar_entries), 0);
3976 }
3977 wrfl();
3978
68d480c4
AD		 3979 return count;
3980}
3981
3982/**
b980ac18
JK		 3983 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3984 * @netdev: network interface device structure
68d480c4 3985 *
b980ac18
JK		 3986 * The set_rx_mode entry point is called whenever the unicast or multicast
3987 * address lists or the network interface flags are updated. This routine is
3988 * responsible for configuring the hardware for proper unicast, multicast,
3989 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3990 **/
3991static void igb_set_rx_mode(struct net_device *netdev)
3992{
3993 struct igb_adapter *adapter = netdev_priv(netdev);
3994 struct e1000_hw *hw = &adapter->hw;
3995 unsigned int vfn = adapter->vfs_allocated_count;
3996 u32 rctl, vmolr = 0;
3997 int count;
3998
3999 /* Check for Promiscuous and All Multicast modes */
4000 rctl = rd32(E1000_RCTL);
4001
4002 /* clear the effected bits */
4003 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4004
4005 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4006 /* retain VLAN HW filtering if in VT mode */
7e44892c 4007 if (adapter->vfs_allocated_count)
6f3dc319 4008 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4009 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4010 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4011 } else {
4012 if (netdev->flags & IFF_ALLMULTI) {
4013 rctl |= E1000_RCTL_MPE;
4014 vmolr |= E1000_VMOLR_MPME;
4015 } else {
b980ac18 4016 /* Write addresses to the MTA, if the attempt fails
25985edc 4017 * then we should just turn on promiscuous mode so
68d480c4
AD		 4018 * that we can at least receive multicast traffic
4019 */
4020 count = igb_write_mc_addr_list(netdev);
4021 if (count < 0) {
4022 rctl |= E1000_RCTL_MPE;
4023 vmolr |= E1000_VMOLR_MPME;
4024 } else if (count) {
4025 vmolr |= E1000_VMOLR_ROMPE;
4026 }
4027 }
b980ac18 4028 /* Write addresses to available RAR registers, if there is not
68d480c4 4029 * sufficient space to store all the addresses then enable
25985edc 4030 * unicast promiscuous mode
68d480c4
AD		 4031 */
4032 count = igb_write_uc_addr_list(netdev);
4033 if (count < 0) {
4034 rctl |= E1000_RCTL_UPE;
4035 vmolr |= E1000_VMOLR_ROPE;
4036 }
4037 rctl |= E1000_RCTL_VFE;
28fc06f5 4038 }
68d480c4 4039 wr32(E1000_RCTL, rctl);
28fc06f5 4040
b980ac18 4041 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4042 * the VMOLR to enable the appropriate modes. Without this workaround
4043 * we will have issues with VLAN tag stripping not being done for frames
4044 * that are only arriving because we are the default pool
4045 */
f96a8a0b 4046 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4047 return;
9d5c8243 4048
68d480c4 4049 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4050 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4051 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4052 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4053}
4054
13800469
GR		 4055static void igb_check_wvbr(struct igb_adapter *adapter)
4056{
4057 struct e1000_hw *hw = &adapter->hw;
4058 u32 wvbr = 0;
4059
4060 switch (hw->mac.type) {
4061 case e1000_82576:
4062 case e1000_i350:
81ad807b
CW		 4063 wvbr = rd32(E1000_WVBR);
4064 if (!wvbr)
13800469
GR		 4065 return;
4066 break;
4067 default:
4068 break;
4069 }
4070
4071 adapter->wvbr |= wvbr;
4072}
4073
4074#define IGB_STAGGERED_QUEUE_OFFSET 8
4075
4076static void igb_spoof_check(struct igb_adapter *adapter)
4077{
4078 int j;
4079
4080 if (!adapter->wvbr)
4081 return;
4082
9005df38 4083 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4084 if (adapter->wvbr & (1 << j) ||
4085 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4086 dev_warn(&adapter->pdev->dev,
4087 "Spoof event(s) detected on VF %d\n", j);
4088 adapter->wvbr &=
4089 ~((1 << j) |
4090 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4091 }
4092 }
4093}
4094
9d5c8243 4095/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4096 * the phy
4097 */
9d5c8243
AK		 4098static void igb_update_phy_info(unsigned long data)
4099{
4100 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4101 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4102}
4103
4d6b725e 4104/**
b980ac18
JK		 4105 * igb_has_link - check shared code for link and determine up/down
4106 * @adapter: pointer to driver private info
4d6b725e 4107 **/
3145535a 4108bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4109{
4110 struct e1000_hw *hw = &adapter->hw;
4111 bool link_active = false;
4d6b725e
AD		 4112
4113 /* get_link_status is set on LSC (link status) interrupt or
4114 * rx sequence error interrupt. get_link_status will stay
4115 * false until the e1000_check_for_link establishes link
4116 * for copper adapters ONLY
4117 */
4118 switch (hw->phy.media_type) {
4119 case e1000_media_type_copper:
e5c3370f
AA		 4120 if (!hw->mac.get_link_status)
4121 return true;
4d6b725e 4122 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4123 hw->mac.ops.check_for_link(hw);
4124 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4125 break;
4126 default:
4127 case e1000_media_type_unknown:
4128 break;
4129 }
4130
aa9b8cc4
AA		 4131 if (((hw->mac.type == e1000_i210) ||
4132 (hw->mac.type == e1000_i211)) &&
4133 (hw->phy.id == I210_I_PHY_ID)) {
4134 if (!netif_carrier_ok(adapter->netdev)) {
4135 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4136 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4137 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4138 adapter->link_check_timeout = jiffies;
4139 }
4140 }
4141
4d6b725e
AD		 4142 return link_active;
4143}
4144
563988dc
SA		 4145static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4146{
4147 bool ret = false;
4148 u32 ctrl_ext, thstat;
4149
f96a8a0b 4150 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4151 if (hw->mac.type == e1000_i350) {
4152 thstat = rd32(E1000_THSTAT);
4153 ctrl_ext = rd32(E1000_CTRL_EXT);
4154
4155 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4156 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4157 ret = !!(thstat & event);
563988dc
SA		 4158 }
4159
4160 return ret;
4161}
4162
9d5c8243 4163/**
b980ac18
JK		 4164 * igb_watchdog - Timer Call-back
4165 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4166 **/
4167static void igb_watchdog(unsigned long data)
4168{
4169 struct igb_adapter *adapter = (struct igb_adapter *)data;
4170 /* Do the rest outside of interrupt context */
4171 schedule_work(&adapter->watchdog_task);
4172}
4173
4174static void igb_watchdog_task(struct work_struct *work)
4175{
4176 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4177 struct igb_adapter,
4178 watchdog_task);
9d5c8243 4179 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4180 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4181 struct net_device *netdev = adapter->netdev;
563988dc 4182 u32 link;
7a6ea550 4183 int i;
56cec249 4184 u32 connsw;
9d5c8243 4185
4d6b725e 4186 link = igb_has_link(adapter);
aa9b8cc4
AA		 4187
4188 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4189 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4190 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4191 else
4192 link = false;
4193 }
4194
56cec249
CW		 4195 /* Force link down if we have fiber to swap to */
4196 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4197 if (hw->phy.media_type == e1000_media_type_copper) {
4198 connsw = rd32(E1000_CONNSW);
4199 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4200 link = 0;
4201 }
4202 }
9d5c8243 4203 if (link) {
2bdfc4e2
CW		 4204 /* Perform a reset if the media type changed. */
4205 if (hw->dev_spec._82575.media_changed) {
4206 hw->dev_spec._82575.media_changed = false;
4207 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4208 igb_reset(adapter);
4209 }
749ab2cd
YZ		 4210 /* Cancel scheduled suspend requests. */
4211 pm_runtime_resume(netdev->dev.parent);
4212
9d5c8243
AK		 4213 if (!netif_carrier_ok(netdev)) {
4214 u32 ctrl;
9005df38 4215
330a6d6a 4216 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4217 &adapter->link_speed,
4218 &adapter->link_duplex);
9d5c8243
AK		 4219
4220 ctrl = rd32(E1000_CTRL);
527d47c1 4221 /* Links status message must follow this format */
c75c4edf
CW		 4222 netdev_info(netdev,
4223 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4224 netdev->name,
4225 adapter->link_speed,
4226 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4227 "Full" : "Half",
4228 (ctrl & E1000_CTRL_TFCE) &&
4229 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4230 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4231 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4232
f4c01e96
CW		 4233 /* disable EEE if enabled */
4234 if ((adapter->flags & IGB_FLAG_EEE) &&
4235 (adapter->link_duplex == HALF_DUPLEX)) {
4236 dev_info(&adapter->pdev->dev,
4237 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4238 adapter->hw.dev_spec._82575.eee_disable = true;
4239 adapter->flags &= ~IGB_FLAG_EEE;
4240 }
4241
c0ba4778
KS		 4242 /* check if SmartSpeed worked */
4243 igb_check_downshift(hw);
4244 if (phy->speed_downgraded)
4245 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4246
563988dc 4247 /* check for thermal sensor event */
876d2d6f 4248 if (igb_thermal_sensor_event(hw,
d34a15ab 4249 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4250 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4251
d07f3e37 4252 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4253 adapter->tx_timeout_factor = 1;
4254 switch (adapter->link_speed) {
4255 case SPEED_10:
9d5c8243
AK		 4256 adapter->tx_timeout_factor = 14;
4257 break;
4258 case SPEED_100:
9d5c8243
AK		 4259 /* maybe add some timeout factor ? */
4260 break;
4261 }
4262
4263 netif_carrier_on(netdev);
9d5c8243 4264
4ae196df 4265 igb_ping_all_vfs(adapter);
17dc566c 4266 igb_check_vf_rate_limit(adapter);
4ae196df 4267
4b1a9877 4268 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4269 if (!test_bit(__IGB_DOWN, &adapter->state))
4270 mod_timer(&adapter->phy_info_timer,
4271 round_jiffies(jiffies + 2 * HZ));
4272 }
4273 } else {
4274 if (netif_carrier_ok(netdev)) {
4275 adapter->link_speed = 0;
4276 adapter->link_duplex = 0;
563988dc
SA		 4277
4278 /* check for thermal sensor event */
876d2d6f
JK		 4279 if (igb_thermal_sensor_event(hw,
4280 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4281 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4282 }
563988dc 4283
527d47c1 4284 /* Links status message must follow this format */
c75c4edf 4285 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4286 netdev->name);
9d5c8243 4287 netif_carrier_off(netdev);
4b1a9877 4288
4ae196df
AD		 4289 igb_ping_all_vfs(adapter);
4290
4b1a9877 4291 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4292 if (!test_bit(__IGB_DOWN, &adapter->state))
4293 mod_timer(&adapter->phy_info_timer,
4294 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4295
56cec249
CW		 4296 /* link is down, time to check for alternate media */
4297 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4298 igb_check_swap_media(adapter);
4299 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4300 schedule_work(&adapter->reset_task);
4301 /* return immediately */
4302 return;
4303 }
4304 }
749ab2cd
YZ		 4305 pm_schedule_suspend(netdev->dev.parent,
4306 MSEC_PER_SEC * 5);
56cec249
CW		 4307
4308 /* also check for alternate media here */
4309 } else if (!netif_carrier_ok(netdev) &&
4310 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4311 igb_check_swap_media(adapter);
4312 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4313 schedule_work(&adapter->reset_task);
4314 /* return immediately */
4315 return;
4316 }
9d5c8243
AK		 4317 }
4318 }
4319
12dcd86b
ED		 4320 spin_lock(&adapter->stats64_lock);
4321 igb_update_stats(adapter, &adapter->stats64);
4322 spin_unlock(&adapter->stats64_lock);
9d5c8243 4323
dbabb065 4324 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4325 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4326 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4327 /* We've lost link, so the controller stops DMA,
4328 * but we've got queued Tx work that's never going
4329 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4330 * (Do the reset outside of interrupt context).
4331 */
dbabb065
AD		 4332 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4333 adapter->tx_timeout_count++;
4334 schedule_work(&adapter->reset_task);
4335 /* return immediately since reset is imminent */
4336 return;
4337 }
9d5c8243 4338 }
9d5c8243 4339
dbabb065 4340 /* Force detection of hung controller every watchdog period */
6d095fa8 4341 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4342 }
f7ba205e 4343
b980ac18 4344 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4345 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4346 u32 eics = 0;
9005df38 4347
0d1ae7f4
AD		 4348 for (i = 0; i < adapter->num_q_vectors; i++)
4349 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4350 wr32(E1000_EICS, eics);
4351 } else {
4352 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4353 }
9d5c8243 4354
13800469 4355 igb_spoof_check(adapter);
fc580751 4356 igb_ptp_rx_hang(adapter);
13800469 4357
9d5c8243 4358 /* Reset the timer */
aa9b8cc4
AA		 4359 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4360 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4361 mod_timer(&adapter->watchdog_timer,
4362 round_jiffies(jiffies + HZ));
4363 else
4364 mod_timer(&adapter->watchdog_timer,
4365 round_jiffies(jiffies + 2 * HZ));
4366 }
9d5c8243
AK		 4367}
4368
4369enum latency_range {
4370 lowest_latency = 0,
4371 low_latency = 1,
4372 bulk_latency = 2,
4373 latency_invalid = 255
4374};
4375
6eb5a7f1 4376/**
b980ac18
JK		 4377 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4378 * @q_vector: pointer to q_vector
6eb5a7f1 4379 *
b980ac18
JK		 4380 * Stores a new ITR value based on strictly on packet size. This
4381 * algorithm is less sophisticated than that used in igb_update_itr,
4382 * due to the difficulty of synchronizing statistics across multiple
4383 * receive rings. The divisors and thresholds used by this function
4384 * were determined based on theoretical maximum wire speed and testing
4385 * data, in order to minimize response time while increasing bulk
4386 * throughput.
406d4965 4387 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4388 * NOTE: This function is called only when operating in a multiqueue
4389 * receive environment.
6eb5a7f1 4390 **/
047e0030 4391static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4392{
047e0030 4393 int new_val = q_vector->itr_val;
6eb5a7f1 4394 int avg_wire_size = 0;
047e0030 4395 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4396 unsigned int packets;
9d5c8243 4397
6eb5a7f1
AD		 4398 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4399 * ints/sec - ITR timer value of 120 ticks.
4400 */
4401 if (adapter->link_speed != SPEED_1000) {
0ba82994 4402 new_val = IGB_4K_ITR;
6eb5a7f1 4403 goto set_itr_val;
9d5c8243 4404 }
047e0030 4405
0ba82994
AD		 4406 packets = q_vector->rx.total_packets;
4407 if (packets)
4408 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4409
0ba82994
AD		 4410 packets = q_vector->tx.total_packets;
4411 if (packets)
4412 avg_wire_size = max_t(u32, avg_wire_size,
4413 q_vector->tx.total_bytes / packets);
047e0030
AD		 4414
4415 /* if avg_wire_size isn't set no work was done */
4416 if (!avg_wire_size)
4417 goto clear_counts;
9d5c8243 4418
6eb5a7f1
AD		 4419 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4420 avg_wire_size += 24;
4421
4422 /* Don't starve jumbo frames */
4423 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4424
6eb5a7f1
AD		 4425 /* Give a little boost to mid-size frames */
4426 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4427 new_val = avg_wire_size / 3;
4428 else
4429 new_val = avg_wire_size / 2;
9d5c8243 4430
0ba82994
AD		 4431 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4432 if (new_val < IGB_20K_ITR &&
4433 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4434 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4435 new_val = IGB_20K_ITR;
abe1c363 4436
6eb5a7f1 4437set_itr_val:
047e0030
AD		 4438 if (new_val != q_vector->itr_val) {
4439 q_vector->itr_val = new_val;
4440 q_vector->set_itr = 1;
9d5c8243 4441 }
6eb5a7f1 4442clear_counts:
0ba82994
AD		 4443 q_vector->rx.total_bytes = 0;
4444 q_vector->rx.total_packets = 0;
4445 q_vector->tx.total_bytes = 0;
4446 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4447}
4448
4449/**
b980ac18
JK		 4450 * igb_update_itr - update the dynamic ITR value based on statistics
4451 * @q_vector: pointer to q_vector
4452 * @ring_container: ring info to update the itr for
4453 *
4454 * Stores a new ITR value based on packets and byte
4455 * counts during the last interrupt. The advantage of per interrupt
4456 * computation is faster updates and more accurate ITR for the current
4457 * traffic pattern. Constants in this function were computed
4458 * based on theoretical maximum wire speed and thresholds were set based
4459 * on testing data as well as attempting to minimize response time
4460 * while increasing bulk throughput.
406d4965 4461 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4462 * NOTE: These calculations are only valid when operating in a single-
4463 * queue environment.
9d5c8243 4464 **/
0ba82994
AD		 4465static void igb_update_itr(struct igb_q_vector *q_vector,
4466 struct igb_ring_container *ring_container)
9d5c8243 4467{
0ba82994
AD		 4468 unsigned int packets = ring_container->total_packets;
4469 unsigned int bytes = ring_container->total_bytes;
4470 u8 itrval = ring_container->itr;
9d5c8243 4471
0ba82994 4472 /* no packets, exit with status unchanged */
9d5c8243 4473 if (packets == 0)
0ba82994 4474 return;
9d5c8243 4475
0ba82994 4476 switch (itrval) {
9d5c8243
AK		 4477 case lowest_latency:
4478 /* handle TSO and jumbo frames */
4479 if (bytes/packets > 8000)
0ba82994 4480 itrval = bulk_latency;
9d5c8243 4481 else if ((packets < 5) && (bytes > 512))
0ba82994 4482 itrval = low_latency;
9d5c8243
AK		 4483 break;
4484 case low_latency: /* 50 usec aka 20000 ints/s */
4485 if (bytes > 10000) {
4486 /* this if handles the TSO accounting */
d34a15ab 4487 if (bytes/packets > 8000)
0ba82994 4488 itrval = bulk_latency;
d34a15ab 4489 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4490 itrval = bulk_latency;
d34a15ab 4491 else if ((packets > 35))
0ba82994 4492 itrval = lowest_latency;
9d5c8243 4493 } else if (bytes/packets > 2000) {
0ba82994 4494 itrval = bulk_latency;
9d5c8243 4495 } else if (packets <= 2 && bytes < 512) {
0ba82994 4496 itrval = lowest_latency;
9d5c8243
AK		 4497 }
4498 break;
4499 case bulk_latency: /* 250 usec aka 4000 ints/s */
4500 if (bytes > 25000) {
4501 if (packets > 35)
0ba82994 4502 itrval = low_latency;
1e5c3d21 4503 } else if (bytes < 1500) {
0ba82994 4504 itrval = low_latency;
9d5c8243
AK		 4505 }
4506 break;
4507 }
4508
0ba82994
AD		 4509 /* clear work counters since we have the values we need */
4510 ring_container->total_bytes = 0;
4511 ring_container->total_packets = 0;
4512
4513 /* write updated itr to ring container */
4514 ring_container->itr = itrval;
9d5c8243
AK		 4515}
4516
0ba82994 4517static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4518{
0ba82994 4519 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4520 u32 new_itr = q_vector->itr_val;
0ba82994 4521 u8 current_itr = 0;
9d5c8243
AK		 4522
4523 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4524 if (adapter->link_speed != SPEED_1000) {
4525 current_itr = 0;
0ba82994 4526 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4527 goto set_itr_now;
4528 }
4529
0ba82994
AD		 4530 igb_update_itr(q_vector, &q_vector->tx);
4531 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4532
0ba82994 4533 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4534
6eb5a7f1 4535 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4536 if (current_itr == lowest_latency &&
4537 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4538 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4539 current_itr = low_latency;
4540
9d5c8243
AK		 4541 switch (current_itr) {
4542 /* counts and packets in update_itr are dependent on these numbers */
4543 case lowest_latency:
0ba82994 4544 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4545 break;
4546 case low_latency:
0ba82994 4547 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4548 break;
4549 case bulk_latency:
0ba82994 4550 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4551 break;
4552 default:
4553 break;
4554 }
4555
4556set_itr_now:
047e0030 4557 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4558 /* this attempts to bias the interrupt rate towards Bulk
4559 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4560 * increasing
4561 */
047e0030 4562 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4563 max((new_itr * q_vector->itr_val) /
4564 (new_itr + (q_vector->itr_val >> 2)),
4565 new_itr) : new_itr;
9d5c8243
AK		 4566 /* Don't write the value here; it resets the adapter's
4567 * internal timer, and causes us to delay far longer than
4568 * we should between interrupts. Instead, we write the ITR
4569 * value at the beginning of the next interrupt so the timing
4570 * ends up being correct.
4571 */
047e0030
AD		 4572 q_vector->itr_val = new_itr;
4573 q_vector->set_itr = 1;
9d5c8243 4574 }
9d5c8243
AK		 4575}
4576
c50b52a0
SH		 4577static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4578 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4579{
4580 struct e1000_adv_tx_context_desc *context_desc;
4581 u16 i = tx_ring->next_to_use;
4582
4583 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4584
4585 i++;
4586 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4587
4588 /* set bits to identify this as an advanced context descriptor */
4589 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4590
4591 /* For 82575, context index must be unique per ring. */
866cff06 4592 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4593 mss_l4len_idx |= tx_ring->reg_idx << 4;
4594
4595 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4596 context_desc->seqnum_seed = 0;
4597 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4598 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4599}
4600
7af40ad9
AD		 4601static int igb_tso(struct igb_ring *tx_ring,
4602 struct igb_tx_buffer *first,
4603 u8 *hdr_len)
9d5c8243 4604{
7af40ad9 4605 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4606 u32 vlan_macip_lens, type_tucmd;
4607 u32 mss_l4len_idx, l4len;
06c14e5a 4608 int err;
7d13a7d0 4609
ed6aa105
AD		 4610 if (skb->ip_summed != CHECKSUM_PARTIAL)
4611 return 0;
4612
7d13a7d0
AD		 4613 if (!skb_is_gso(skb))
4614 return 0;
9d5c8243 4615
06c14e5a
FR		 4616 err = skb_cow_head(skb, 0);
4617 if (err < 0)
4618 return err;
9d5c8243 4619
7d13a7d0
AD		 4620 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4621 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4622
7c4d16ff 4623 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4624 struct iphdr *iph = ip_hdr(skb);
4625 iph->tot_len = 0;
4626 iph->check = 0;
4627 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4628 iph->daddr, 0,
4629 IPPROTO_TCP,
4630 0);
7d13a7d0 4631 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4632 first->tx_flags |= IGB_TX_FLAGS_TSO |
4633 IGB_TX_FLAGS_CSUM |
4634 IGB_TX_FLAGS_IPV4;
8e1e8a47 4635 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4636 ipv6_hdr(skb)->payload_len = 0;
4637 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4638 &ipv6_hdr(skb)->daddr,
4639 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4640 first->tx_flags |= IGB_TX_FLAGS_TSO |
4641 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4642 }
4643
7af40ad9 4644 /* compute header lengths */
7d13a7d0
AD		 4645 l4len = tcp_hdrlen(skb);
4646 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4647
7af40ad9
AD		 4648 /* update gso size and bytecount with header size */
4649 first->gso_segs = skb_shinfo(skb)->gso_segs;
4650 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4651
9d5c8243 4652 /* MSS L4LEN IDX */
7d13a7d0
AD		 4653 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4654 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4655
7d13a7d0
AD		 4656 /* VLAN MACLEN IPLEN */
4657 vlan_macip_lens = skb_network_header_len(skb);
4658 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4659 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4660
7d13a7d0 4661 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4662
7d13a7d0 4663 return 1;
9d5c8243
AK		 4664}
4665
7af40ad9 4666static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4667{
7af40ad9 4668 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4669 u32 vlan_macip_lens = 0;
4670 u32 mss_l4len_idx = 0;
4671 u32 type_tucmd = 0;
9d5c8243 4672
7d13a7d0 4673 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4674 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4675 return;
7d13a7d0
AD		 4676 } else {
4677 u8 l4_hdr = 0;
9005df38 4678
7af40ad9 4679 switch (first->protocol) {
7c4d16ff 4680 case htons(ETH_P_IP):
7d13a7d0
AD		 4681 vlan_macip_lens |= skb_network_header_len(skb);
4682 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4683 l4_hdr = ip_hdr(skb)->protocol;
4684 break;
7c4d16ff 4685 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4686 vlan_macip_lens |= skb_network_header_len(skb);
4687 l4_hdr = ipv6_hdr(skb)->nexthdr;
4688 break;
4689 default:
4690 if (unlikely(net_ratelimit())) {
4691 dev_warn(tx_ring->dev,
b980ac18
JK		 4692 "partial checksum but proto=%x!\n",
4693 first->protocol);
fa4a7ef3 4694 }
7d13a7d0
AD		 4695 break;
4696 }
fa4a7ef3 4697
7d13a7d0
AD		 4698 switch (l4_hdr) {
4699 case IPPROTO_TCP:
4700 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4701 mss_l4len_idx = tcp_hdrlen(skb) <<
4702 E1000_ADVTXD_L4LEN_SHIFT;
4703 break;
4704 case IPPROTO_SCTP:
4705 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4706 mss_l4len_idx = sizeof(struct sctphdr) <<
4707 E1000_ADVTXD_L4LEN_SHIFT;
4708 break;
4709 case IPPROTO_UDP:
4710 mss_l4len_idx = sizeof(struct udphdr) <<
4711 E1000_ADVTXD_L4LEN_SHIFT;
4712 break;
4713 default:
4714 if (unlikely(net_ratelimit())) {
4715 dev_warn(tx_ring->dev,
b980ac18
JK		 4716 "partial checksum but l4 proto=%x!\n",
4717 l4_hdr);
44b0cda3 4718 }
7d13a7d0 4719 break;
9d5c8243 4720 }
7af40ad9
AD		 4721
4722 /* update TX checksum flag */
4723 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4724 }
9d5c8243 4725
7d13a7d0 4726 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4727 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4728
7d13a7d0 4729 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4730}
4731
1d9daf45
AD		 4732#define IGB_SET_FLAG(_input, _flag, _result) \
4733 ((_flag <= _result) ? \
4734 ((u32)(_input & _flag) * (_result / _flag)) : \
4735 ((u32)(_input & _flag) / (_flag / _result)))
4736
4737static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4738{
4739 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4740 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4741 E1000_ADVTXD_DCMD_DEXT |
4742 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4743
4744 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4745 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4746 (E1000_ADVTXD_DCMD_VLE));
4747
4748 /* set segmentation bits for TSO */
4749 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4750 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4751
4752 /* set timestamp bit if present */
1d9daf45
AD		 4753 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4754 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4755
1d9daf45
AD		 4756 /* insert frame checksum */
4757 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4758
4759 return cmd_type;
4760}
4761
7af40ad9
AD		 4762static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4763 union e1000_adv_tx_desc *tx_desc,
4764 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4765{
4766 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4767
1d9daf45
AD		 4768 /* 82575 requires a unique index per ring */
4769 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4770 olinfo_status |= tx_ring->reg_idx << 4;
4771
4772 /* insert L4 checksum */
1d9daf45
AD		 4773 olinfo_status |= IGB_SET_FLAG(tx_flags,
4774 IGB_TX_FLAGS_CSUM,
4775 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4776
1d9daf45
AD		 4777 /* insert IPv4 checksum */
4778 olinfo_status |= IGB_SET_FLAG(tx_flags,
4779 IGB_TX_FLAGS_IPV4,
4780 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4781
7af40ad9 4782 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4783}
4784
7af40ad9
AD		 4785static void igb_tx_map(struct igb_ring *tx_ring,
4786 struct igb_tx_buffer *first,
ebe42d16 4787 const u8 hdr_len)
9d5c8243 4788{
7af40ad9 4789 struct sk_buff *skb = first->skb;
c9f14bf3 4790 struct igb_tx_buffer *tx_buffer;
ebe42d16 4791 union e1000_adv_tx_desc *tx_desc;
80d0759e 4792 struct skb_frag_struct *frag;
ebe42d16 4793 dma_addr_t dma;
80d0759e 4794 unsigned int data_len, size;
7af40ad9 4795 u32 tx_flags = first->tx_flags;
1d9daf45 4796 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4797 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4798
4799 tx_desc = IGB_TX_DESC(tx_ring, i);
4800
80d0759e
AD		 4801 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4802
4803 size = skb_headlen(skb);
4804 data_len = skb->data_len;
ebe42d16
AD		 4805
4806 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4807
80d0759e
AD		 4808 tx_buffer = first;
4809
4810 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4811 if (dma_mapping_error(tx_ring->dev, dma))
4812 goto dma_error;
4813
4814 /* record length, and DMA address */
4815 dma_unmap_len_set(tx_buffer, len, size);
4816 dma_unmap_addr_set(tx_buffer, dma, dma);
4817
4818 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4819
ebe42d16
AD		 4820 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4821 tx_desc->read.cmd_type_len =
1d9daf45 4822 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4823
4824 i++;
4825 tx_desc++;
4826 if (i == tx_ring->count) {
4827 tx_desc = IGB_TX_DESC(tx_ring, 0);
4828 i = 0;
4829 }
80d0759e 4830 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4831
4832 dma += IGB_MAX_DATA_PER_TXD;
4833 size -= IGB_MAX_DATA_PER_TXD;
4834
ebe42d16
AD		 4835 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4836 }
4837
4838 if (likely(!data_len))
4839 break;
2bbfebe2 4840
1d9daf45 4841 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4842
65689fef 4843 i++;
ebe42d16
AD		 4844 tx_desc++;
4845 if (i == tx_ring->count) {
4846 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4847 i = 0;
ebe42d16 4848 }
80d0759e 4849 tx_desc->read.olinfo_status = 0;
65689fef 4850
9e903e08 4851 size = skb_frag_size(frag);
ebe42d16
AD		 4852 data_len -= size;
4853
4854 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4855 size, DMA_TO_DEVICE);
6366ad33 4856
c9f14bf3 4857 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4858 }
4859
ebe42d16 4860 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4861 cmd_type |= size | IGB_TXD_DCMD;
4862 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4863
80d0759e
AD		 4864 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4865
8542db05
AD		 4866 /* set the timestamp */
4867 first->time_stamp = jiffies;
4868
b980ac18 4869 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4870 * are new descriptors to fetch. (Only applicable for weak-ordered
4871 * memory model archs, such as IA-64).
4872 *
4873 * We also need this memory barrier to make certain all of the
4874 * status bits have been updated before next_to_watch is written.
4875 */
4876 wmb();
4877
8542db05 4878 /* set next_to_watch value indicating a packet is present */
ebe42d16 4879 first->next_to_watch = tx_desc;
9d5c8243 4880
ebe42d16
AD		 4881 i++;
4882 if (i == tx_ring->count)
4883 i = 0;
6366ad33 4884
ebe42d16 4885 tx_ring->next_to_use = i;
6366ad33 4886
ebe42d16 4887 writel(i, tx_ring->tail);
6366ad33 4888
ebe42d16 4889 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4890 * at a time, it synchronizes IO on IA64/Altix systems
4891 */
ebe42d16
AD		 4892 mmiowb();
4893
4894 return;
4895
4896dma_error:
4897 dev_err(tx_ring->dev, "TX DMA map failed\n");
4898
4899 /* clear dma mappings for failed tx_buffer_info map */
4900 for (;;) {
c9f14bf3
AD		 4901 tx_buffer = &tx_ring->tx_buffer_info[i];
4902 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4903 if (tx_buffer == first)
ebe42d16 4904 break;
a77ff709
NN		 4905 if (i == 0)
4906 i = tx_ring->count;
6366ad33 4907 i--;
6366ad33
AD		 4908 }
4909
9d5c8243 4910 tx_ring->next_to_use = i;
9d5c8243
AK		 4911}
4912
6ad4edfc 4913static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4914{
e694e964
AD		 4915 struct net_device *netdev = tx_ring->netdev;
4916
661086df 4917 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4918
9d5c8243
AK		 4919 /* Herbert's original patch had:
4920 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4921 * but since that doesn't exist yet, just open code it.
4922 */
9d5c8243
AK		 4923 smp_mb();
4924
4925 /* We need to check again in a case another CPU has just
b980ac18
JK		 4926 * made room available.
4927 */
c493ea45 4928 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4929 return -EBUSY;
4930
4931 /* A reprieve! */
661086df 4932 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4933
4934 u64_stats_update_begin(&tx_ring->tx_syncp2);
4935 tx_ring->tx_stats.restart_queue2++;
4936 u64_stats_update_end(&tx_ring->tx_syncp2);
4937
9d5c8243
AK		 4938 return 0;
4939}
4940
6ad4edfc 4941static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4942{
c493ea45 4943 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4944 return 0;
e694e964 4945 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4946}
4947
cd392f5c
AD		 4948netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4949 struct igb_ring *tx_ring)
9d5c8243 4950{
8542db05 4951 struct igb_tx_buffer *first;
ebe42d16 4952 int tso;
91d4ee33 4953 u32 tx_flags = 0;
21ba6fe1 4954 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4955 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4956 u8 hdr_len = 0;
9d5c8243 4957
21ba6fe1
AD		 4958 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4959 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4960 * + 2 desc gap to keep tail from touching head,
9d5c8243 4961 * + 1 desc for context descriptor,
21ba6fe1
AD		 4962 * otherwise try next time
4963 */
4964 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4965 unsigned short f;
9005df38 4966
21ba6fe1
AD		 4967 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4968 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4969 } else {
4970 count += skb_shinfo(skb)->nr_frags;
4971 }
4972
4973 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4974 /* this is a hard error */
9d5c8243
AK		 4975 return NETDEV_TX_BUSY;
4976 }
33af6bcc 4977
7af40ad9
AD		 4978 /* record the location of the first descriptor for this packet */
4979 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4980 first->skb = skb;
4981 first->bytecount = skb->len;
4982 first->gso_segs = 1;
4983
b646c22e
AD		 4984 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4985 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4986
ed4420a3
JK		 4987 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
4988 &adapter->state)) {
b646c22e
AD		 4989 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4990 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4991
4992 adapter->ptp_tx_skb = skb_get(skb);
4993 adapter->ptp_tx_start = jiffies;
4994 if (adapter->hw.mac.type == e1000_82576)
4995 schedule_work(&adapter->ptp_tx_work);
4996 }
33af6bcc 4997 }
9d5c8243 4998
afc835d1
JK		 4999 skb_tx_timestamp(skb);
5000
eab6d18d 5001 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 5002 tx_flags |= IGB_TX_FLAGS_VLAN;
5003 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5004 }
5005
7af40ad9
AD		 5006 /* record initial flags and protocol */
5007 first->tx_flags = tx_flags;
5008 first->protocol = protocol;
cdfd01fc 5009
7af40ad9
AD		 5010 tso = igb_tso(tx_ring, first, &hdr_len);
5011 if (tso < 0)
7d13a7d0 5012 goto out_drop;
7af40ad9
AD		 5013 else if (!tso)
5014 igb_tx_csum(tx_ring, first);
9d5c8243 5015
7af40ad9 5016 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 5017
5018 /* Make sure there is space in the ring for the next send. */
21ba6fe1 5019 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 5020
9d5c8243 5021 return NETDEV_TX_OK;
7d13a7d0
AD		 5022
5023out_drop:
7af40ad9
AD		 5024 igb_unmap_and_free_tx_resource(tx_ring, first);
5025
7d13a7d0 5026 return NETDEV_TX_OK;
9d5c8243
AK		 5027}
5028
1cc3bd87
AD		 5029static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5030 struct sk_buff *skb)
5031{
5032 unsigned int r_idx = skb->queue_mapping;
5033
5034 if (r_idx >= adapter->num_tx_queues)
5035 r_idx = r_idx % adapter->num_tx_queues;
5036
5037 return adapter->tx_ring[r_idx];
5038}
5039
cd392f5c
AD		 5040static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5041 struct net_device *netdev)
9d5c8243
AK		 5042{
5043 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5044
5045 if (test_bit(__IGB_DOWN, &adapter->state)) {
5046 dev_kfree_skb_any(skb);
5047 return NETDEV_TX_OK;
5048 }
5049
5050 if (skb->len <= 0) {
5051 dev_kfree_skb_any(skb);
5052 return NETDEV_TX_OK;
5053 }
5054
b980ac18 5055 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5056 * in order to meet this minimum size requirement.
5057 */
ea5ceeab
TD		 5058 if (unlikely(skb->len < 17)) {
5059 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 5060 return NETDEV_TX_OK;
5061 skb->len = 17;
ea5ceeab 5062 skb_set_tail_pointer(skb, 17);
1cc3bd87 5063 }
9d5c8243 5064
1cc3bd87 5065 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5066}
5067
5068/**
b980ac18
JK		 5069 * igb_tx_timeout - Respond to a Tx Hang
5070 * @netdev: network interface device structure
9d5c8243
AK		 5071 **/
5072static void igb_tx_timeout(struct net_device *netdev)
5073{
5074 struct igb_adapter *adapter = netdev_priv(netdev);
5075 struct e1000_hw *hw = &adapter->hw;
5076
5077 /* Do the reset outside of interrupt context */
5078 adapter->tx_timeout_count++;
f7ba205e 5079
06218a8d 5080 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5081 hw->dev_spec._82575.global_device_reset = true;
5082
9d5c8243 5083 schedule_work(&adapter->reset_task);
265de409
AD		 5084 wr32(E1000_EICS,
5085 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5086}
5087
5088static void igb_reset_task(struct work_struct *work)
5089{
5090 struct igb_adapter *adapter;
5091 adapter = container_of(work, struct igb_adapter, reset_task);
5092
c97ec42a
TI		 5093 igb_dump(adapter);
5094 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5095 igb_reinit_locked(adapter);
5096}
5097
5098/**
b980ac18
JK		 5099 * igb_get_stats64 - Get System Network Statistics
5100 * @netdev: network interface device structure
5101 * @stats: rtnl_link_stats64 pointer
9d5c8243 5102 **/
12dcd86b 5103static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5104 struct rtnl_link_stats64 *stats)
9d5c8243 5105{
12dcd86b
ED		 5106 struct igb_adapter *adapter = netdev_priv(netdev);
5107
5108 spin_lock(&adapter->stats64_lock);
5109 igb_update_stats(adapter, &adapter->stats64);
5110 memcpy(stats, &adapter->stats64, sizeof(*stats));
5111 spin_unlock(&adapter->stats64_lock);
5112
5113 return stats;
9d5c8243
AK		 5114}
5115
5116/**
b980ac18
JK		 5117 * igb_change_mtu - Change the Maximum Transfer Unit
5118 * @netdev: network interface device structure
5119 * @new_mtu: new value for maximum frame size
9d5c8243 5120 *
b980ac18 5121 * Returns 0 on success, negative on failure
9d5c8243
AK		 5122 **/
5123static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5124{
5125 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5126 struct pci_dev *pdev = adapter->pdev;
153285f9 5127 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5128
c809d227 5129 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5130 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5131 return -EINVAL;
5132 }
5133
153285f9 5134#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5135 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5136 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5137 return -EINVAL;
5138 }
5139
2ccd994c
AD		 5140 /* adjust max frame to be at least the size of a standard frame */
5141 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5142 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5143
9d5c8243 5144 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5145 usleep_range(1000, 2000);
73cd78f1 5146
9d5c8243
AK		 5147 /* igb_down has a dependency on max_frame_size */
5148 adapter->max_frame_size = max_frame;
559e9c49 5149
4c844851
AD		 5150 if (netif_running(netdev))
5151 igb_down(adapter);
9d5c8243 5152
090b1795 5153 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5154 netdev->mtu, new_mtu);
5155 netdev->mtu = new_mtu;
5156
5157 if (netif_running(netdev))
5158 igb_up(adapter);
5159 else
5160 igb_reset(adapter);
5161
5162 clear_bit(__IGB_RESETTING, &adapter->state);
5163
5164 return 0;
5165}
5166
5167/**
b980ac18
JK		 5168 * igb_update_stats - Update the board statistics counters
5169 * @adapter: board private structure
9d5c8243 5170 **/
12dcd86b
ED		 5171void igb_update_stats(struct igb_adapter *adapter,
5172 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5173{
5174 struct e1000_hw *hw = &adapter->hw;
5175 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5176 u32 reg, mpc;
9d5c8243 5177 u16 phy_tmp;
3f9c0164
AD		 5178 int i;
5179 u64 bytes, packets;
12dcd86b
ED		 5180 unsigned int start;
5181 u64 _bytes, _packets;
9d5c8243
AK		 5182
5183#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
5184
b980ac18 5185 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5186 * connection is down.
5187 */
5188 if (adapter->link_speed == 0)
5189 return;
5190 if (pci_channel_offline(pdev))
5191 return;
5192
3f9c0164
AD		 5193 bytes = 0;
5194 packets = 0;
7f90128e
AA		 5195
5196 rcu_read_lock();
3f9c0164 5197 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5198 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5199 u32 rqdpc = rd32(E1000_RQDPC(i));
5200 if (hw->mac.type >= e1000_i210)
5201 wr32(E1000_RQDPC(i), 0);
12dcd86b 5202
ae1c07a6
AD		 5203 if (rqdpc) {
5204 ring->rx_stats.drops += rqdpc;
5205 net_stats->rx_fifo_errors += rqdpc;
5206 }
12dcd86b
ED		 5207
5208 do {
57a7744e 5209 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5210 _bytes = ring->rx_stats.bytes;
5211 _packets = ring->rx_stats.packets;
57a7744e 5212 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5213 bytes += _bytes;
5214 packets += _packets;
3f9c0164
AD		 5215 }
5216
128e45eb
AD		 5217 net_stats->rx_bytes = bytes;
5218 net_stats->rx_packets = packets;
3f9c0164
AD		 5219
5220 bytes = 0;
5221 packets = 0;
5222 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5223 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5224 do {
57a7744e 5225 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5226 _bytes = ring->tx_stats.bytes;
5227 _packets = ring->tx_stats.packets;
57a7744e 5228 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5229 bytes += _bytes;
5230 packets += _packets;
3f9c0164 5231 }
128e45eb
AD		 5232 net_stats->tx_bytes = bytes;
5233 net_stats->tx_packets = packets;
7f90128e 5234 rcu_read_unlock();
3f9c0164
AD		 5235
5236 /* read stats registers */
9d5c8243
AK		 5237 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5238 adapter->stats.gprc += rd32(E1000_GPRC);
5239 adapter->stats.gorc += rd32(E1000_GORCL);
5240 rd32(E1000_GORCH); /* clear GORCL */
5241 adapter->stats.bprc += rd32(E1000_BPRC);
5242 adapter->stats.mprc += rd32(E1000_MPRC);
5243 adapter->stats.roc += rd32(E1000_ROC);
5244
5245 adapter->stats.prc64 += rd32(E1000_PRC64);
5246 adapter->stats.prc127 += rd32(E1000_PRC127);
5247 adapter->stats.prc255 += rd32(E1000_PRC255);
5248 adapter->stats.prc511 += rd32(E1000_PRC511);
5249 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5250 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5251 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5252 adapter->stats.sec += rd32(E1000_SEC);
5253
fa3d9a6d
MW		 5254 mpc = rd32(E1000_MPC);
5255 adapter->stats.mpc += mpc;
5256 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5257 adapter->stats.scc += rd32(E1000_SCC);
5258 adapter->stats.ecol += rd32(E1000_ECOL);
5259 adapter->stats.mcc += rd32(E1000_MCC);
5260 adapter->stats.latecol += rd32(E1000_LATECOL);
5261 adapter->stats.dc += rd32(E1000_DC);
5262 adapter->stats.rlec += rd32(E1000_RLEC);
5263 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5264 adapter->stats.xontxc += rd32(E1000_XONTXC);
5265 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5266 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5267 adapter->stats.fcruc += rd32(E1000_FCRUC);
5268 adapter->stats.gptc += rd32(E1000_GPTC);
5269 adapter->stats.gotc += rd32(E1000_GOTCL);
5270 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5271 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5272 adapter->stats.ruc += rd32(E1000_RUC);
5273 adapter->stats.rfc += rd32(E1000_RFC);
5274 adapter->stats.rjc += rd32(E1000_RJC);
5275 adapter->stats.tor += rd32(E1000_TORH);
5276 adapter->stats.tot += rd32(E1000_TOTH);
5277 adapter->stats.tpr += rd32(E1000_TPR);
5278
5279 adapter->stats.ptc64 += rd32(E1000_PTC64);
5280 adapter->stats.ptc127 += rd32(E1000_PTC127);
5281 adapter->stats.ptc255 += rd32(E1000_PTC255);
5282 adapter->stats.ptc511 += rd32(E1000_PTC511);
5283 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5284 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5285
5286 adapter->stats.mptc += rd32(E1000_MPTC);
5287 adapter->stats.bptc += rd32(E1000_BPTC);
5288
2d0b0f69
NN		 5289 adapter->stats.tpt += rd32(E1000_TPT);
5290 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5291
5292 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5293 /* read internal phy specific stats */
5294 reg = rd32(E1000_CTRL_EXT);
5295 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5296 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5297
5298 /* this stat has invalid values on i210/i211 */
5299 if ((hw->mac.type != e1000_i210) &&
5300 (hw->mac.type != e1000_i211))
5301 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5302 }
5303
9d5c8243
AK		 5304 adapter->stats.tsctc += rd32(E1000_TSCTC);
5305 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5306
5307 adapter->stats.iac += rd32(E1000_IAC);
5308 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5309 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5310 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5311 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5312 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5313 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5314 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5315 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5316
5317 /* Fill out the OS statistics structure */
128e45eb
AD		 5318 net_stats->multicast = adapter->stats.mprc;
5319 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5320
5321 /* Rx Errors */
5322
5323 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5324 * our own version based on RUC and ROC
5325 */
128e45eb 5326 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5327 adapter->stats.crcerrs + adapter->stats.algnerrc +
5328 adapter->stats.ruc + adapter->stats.roc +
5329 adapter->stats.cexterr;
128e45eb
AD		 5330 net_stats->rx_length_errors = adapter->stats.ruc +
5331 adapter->stats.roc;
5332 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5333 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5334 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5335
5336 /* Tx Errors */
128e45eb
AD		 5337 net_stats->tx_errors = adapter->stats.ecol +
5338 adapter->stats.latecol;
5339 net_stats->tx_aborted_errors = adapter->stats.ecol;
5340 net_stats->tx_window_errors = adapter->stats.latecol;
5341 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5342
5343 /* Tx Dropped needs to be maintained elsewhere */
5344
5345 /* Phy Stats */
5346 if (hw->phy.media_type == e1000_media_type_copper) {
5347 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5348 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5349 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5350 adapter->phy_stats.idle_errors += phy_tmp;
5351 }
5352 }
5353
5354 /* Management Stats */
5355 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5356 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5357 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5358
5359 /* OS2BMC Stats */
5360 reg = rd32(E1000_MANC);
5361 if (reg & E1000_MANC_EN_BMC2OS) {
5362 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5363 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5364 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5365 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5366 }
9d5c8243
AK		 5367}
5368
9d5c8243
AK		 5369static irqreturn_t igb_msix_other(int irq, void *data)
5370{
047e0030 5371 struct igb_adapter *adapter = data;
9d5c8243 5372 struct e1000_hw *hw = &adapter->hw;
844290e5 5373 u32 icr = rd32(E1000_ICR);
844290e5 5374 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5375
7f081d40
AD		 5376 if (icr & E1000_ICR_DRSTA)
5377 schedule_work(&adapter->reset_task);
5378
047e0030 5379 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5380 /* HW is reporting DMA is out of sync */
5381 adapter->stats.doosync++;
13800469
GR		 5382 /* The DMA Out of Sync is also indication of a spoof event
5383 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5384 * see if it is really a spoof event.
5385 */
13800469 5386 igb_check_wvbr(adapter);
dda0e083 5387 }
eebbbdba 5388
4ae196df
AD		 5389 /* Check for a mailbox event */
5390 if (icr & E1000_ICR_VMMB)
5391 igb_msg_task(adapter);
5392
5393 if (icr & E1000_ICR_LSC) {
5394 hw->mac.get_link_status = 1;
5395 /* guard against interrupt when we're going down */
5396 if (!test_bit(__IGB_DOWN, &adapter->state))
5397 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5398 }
5399
1f6e8178
MV		 5400 if (icr & E1000_ICR_TS) {
5401 u32 tsicr = rd32(E1000_TSICR);
5402
5403 if (tsicr & E1000_TSICR_TXTS) {
5404 /* acknowledge the interrupt */
5405 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5406 /* retrieve hardware timestamp */
5407 schedule_work(&adapter->ptp_tx_work);
5408 }
5409 }
1f6e8178 5410
844290e5 5411 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5412
5413 return IRQ_HANDLED;
5414}
5415
047e0030 5416static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5417{
26b39276 5418 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5419 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5420
047e0030
AD		 5421 if (!q_vector->set_itr)
5422 return;
73cd78f1 5423
047e0030
AD		 5424 if (!itr_val)
5425 itr_val = 0x4;
661086df 5426
26b39276
AD		 5427 if (adapter->hw.mac.type == e1000_82575)
5428 itr_val |= itr_val << 16;
661086df 5429 else
0ba82994 5430 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5431
047e0030
AD		 5432 writel(itr_val, q_vector->itr_register);
5433 q_vector->set_itr = 0;
6eb5a7f1
AD		 5434}
5435
047e0030 5436static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5437{
047e0030 5438 struct igb_q_vector *q_vector = data;
9d5c8243 5439
047e0030
AD		 5440 /* Write the ITR value calculated from the previous interrupt. */
5441 igb_write_itr(q_vector);
9d5c8243 5442
047e0030 5443 napi_schedule(&q_vector->napi);
844290e5 5444
047e0030 5445 return IRQ_HANDLED;
fe4506b6
JC		 5446}
5447
421e02f0 5448#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5449static void igb_update_tx_dca(struct igb_adapter *adapter,
5450 struct igb_ring *tx_ring,
5451 int cpu)
5452{
5453 struct e1000_hw *hw = &adapter->hw;
5454 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5455
5456 if (hw->mac.type != e1000_82575)
5457 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5458
b980ac18 5459 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5460 * DCA is enabled. This is due to a known issue in some chipsets
5461 * which will cause the DCA tag to be cleared.
5462 */
5463 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5464 E1000_DCA_TXCTRL_DATA_RRO_EN |
5465 E1000_DCA_TXCTRL_DESC_DCA_EN;
5466
5467 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5468}
5469
5470static void igb_update_rx_dca(struct igb_adapter *adapter,
5471 struct igb_ring *rx_ring,
5472 int cpu)
5473{
5474 struct e1000_hw *hw = &adapter->hw;
5475 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5476
5477 if (hw->mac.type != e1000_82575)
5478 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5479
b980ac18 5480 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5481 * DCA is enabled. This is due to a known issue in some chipsets
5482 * which will cause the DCA tag to be cleared.
5483 */
5484 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5485 E1000_DCA_RXCTRL_DESC_DCA_EN;
5486
5487 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5488}
5489
047e0030 5490static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5491{
047e0030 5492 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5493 int cpu = get_cpu();
fe4506b6 5494
047e0030
AD		 5495 if (q_vector->cpu == cpu)
5496 goto out_no_update;
5497
6a05004a
AD		 5498 if (q_vector->tx.ring)
5499 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5500
5501 if (q_vector->rx.ring)
5502 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5503
047e0030
AD		 5504 q_vector->cpu = cpu;
5505out_no_update:
fe4506b6
JC		 5506 put_cpu();
5507}
5508
5509static void igb_setup_dca(struct igb_adapter *adapter)
5510{
7e0e99ef 5511 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5512 int i;
5513
7dfc16fa 5514 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5515 return;
5516
7e0e99ef
AD		 5517 /* Always use CB2 mode, difference is masked in the CB driver. */
5518 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5519
047e0030 5520 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5521 adapter->q_vector[i]->cpu = -1;
5522 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5523 }
5524}
5525
5526static int __igb_notify_dca(struct device *dev, void *data)
5527{
5528 struct net_device *netdev = dev_get_drvdata(dev);
5529 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5530 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5531 struct e1000_hw *hw = &adapter->hw;
5532 unsigned long event = *(unsigned long *)data;
5533
5534 switch (event) {
5535 case DCA_PROVIDER_ADD:
5536 /* if already enabled, don't do it again */
7dfc16fa 5537 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5538 break;
fe4506b6 5539 if (dca_add_requester(dev) == 0) {
bbd98fe4 5540 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5541 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5542 igb_setup_dca(adapter);
5543 break;
5544 }
5545 /* Fall Through since DCA is disabled. */
5546 case DCA_PROVIDER_REMOVE:
7dfc16fa 5547 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5548 /* without this a class_device is left
b980ac18
JK		 5549 * hanging around in the sysfs model
5550 */
fe4506b6 5551 dca_remove_requester(dev);
090b1795 5552 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5553 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5554 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5555 }
5556 break;
5557 }
bbd98fe4 5558
fe4506b6 5559 return 0;
9d5c8243
AK		 5560}
5561
fe4506b6 5562static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5563 void *p)
fe4506b6
JC		 5564{
5565 int ret_val;
5566
5567 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5568 __igb_notify_dca);
fe4506b6
JC		 5569
5570 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5571}
421e02f0 5572#endif /* CONFIG_IGB_DCA */
9d5c8243 5573
0224d663
GR		 5574#ifdef CONFIG_PCI_IOV
5575static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5576{
5577 unsigned char mac_addr[ETH_ALEN];
0224d663 5578
5ac6f91d 5579 eth_zero_addr(mac_addr);
0224d663
GR		 5580 igb_set_vf_mac(adapter, vf, mac_addr);
5581
70ea4783
LL		 5582 /* By default spoof check is enabled for all VFs */
5583 adapter->vf_data[vf].spoofchk_enabled = true;
5584
f557147c 5585 return 0;
0224d663
GR		 5586}
5587
0224d663 5588#endif
4ae196df
AD		 5589static void igb_ping_all_vfs(struct igb_adapter *adapter)
5590{
5591 struct e1000_hw *hw = &adapter->hw;
5592 u32 ping;
5593 int i;
5594
5595 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5596 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5597 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5598 ping |= E1000_VT_MSGTYPE_CTS;
5599 igb_write_mbx(hw, &ping, 1, i);
5600 }
5601}
5602
7d5753f0
AD		 5603static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5604{
5605 struct e1000_hw *hw = &adapter->hw;
5606 u32 vmolr = rd32(E1000_VMOLR(vf));
5607 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5608
d85b9004 5609 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5610 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5611 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5612
5613 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5614 vmolr |= E1000_VMOLR_MPME;
d85b9004 5615 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5616 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5617 } else {
b980ac18 5618 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5619 * flag we need to write the hashes to the MTA as this step
5620 * was previously skipped
5621 */
5622 if (vf_data->num_vf_mc_hashes > 30) {
5623 vmolr |= E1000_VMOLR_MPME;
5624 } else if (vf_data->num_vf_mc_hashes) {
5625 int j;
9005df38 5626
7d5753f0
AD		 5627 vmolr |= E1000_VMOLR_ROMPE;
5628 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5629 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5630 }
5631 }
5632
5633 wr32(E1000_VMOLR(vf), vmolr);
5634
5635 /* there are flags left unprocessed, likely not supported */
5636 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5637 return -EINVAL;
5638
5639 return 0;
7d5753f0
AD		 5640}
5641
4ae196df
AD		 5642static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5643 u32 *msgbuf, u32 vf)
5644{
5645 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5646 u16 *hash_list = (u16 *)&msgbuf[1];
5647 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5648 int i;
5649
7d5753f0 5650 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5651 * to this VF for later use to restore when the PF multi cast
5652 * list changes
5653 */
5654 vf_data->num_vf_mc_hashes = n;
5655
7d5753f0
AD		 5656 /* only up to 30 hash values supported */
5657 if (n > 30)
5658 n = 30;
5659
5660 /* store the hashes for later use */
4ae196df 5661 for (i = 0; i < n; i++)
a419aef8 5662 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5663
5664 /* Flush and reset the mta with the new values */
ff41f8dc 5665 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5666
5667 return 0;
5668}
5669
5670static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5671{
5672 struct e1000_hw *hw = &adapter->hw;
5673 struct vf_data_storage *vf_data;
5674 int i, j;
5675
5676 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5677 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5678
7d5753f0
AD		 5679 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5680
4ae196df 5681 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5682
5683 if ((vf_data->num_vf_mc_hashes > 30) ||
5684 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5685 vmolr |= E1000_VMOLR_MPME;
5686 } else if (vf_data->num_vf_mc_hashes) {
5687 vmolr |= E1000_VMOLR_ROMPE;
5688 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5689 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5690 }
5691 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5692 }
5693}
5694
5695static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5696{
5697 struct e1000_hw *hw = &adapter->hw;
5698 u32 pool_mask, reg, vid;
5699 int i;
5700
5701 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5702
5703 /* Find the vlan filter for this id */
5704 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5705 reg = rd32(E1000_VLVF(i));
5706
5707 /* remove the vf from the pool */
5708 reg &= ~pool_mask;
5709
5710 /* if pool is empty then remove entry from vfta */
5711 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5712 (reg & E1000_VLVF_VLANID_ENABLE)) {
5713 reg = 0;
5714 vid = reg & E1000_VLVF_VLANID_MASK;
5715 igb_vfta_set(hw, vid, false);
5716 }
5717
5718 wr32(E1000_VLVF(i), reg);
5719 }
ae641bdc
AD		 5720
5721 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5722}
5723
5724static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5725{
5726 struct e1000_hw *hw = &adapter->hw;
5727 u32 reg, i;
5728
51466239
AD		 5729 /* The vlvf table only exists on 82576 hardware and newer */
5730 if (hw->mac.type < e1000_82576)
5731 return -1;
5732
5733 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5734 if (!adapter->vfs_allocated_count)
5735 return -1;
5736
5737 /* Find the vlan filter for this id */
5738 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5739 reg = rd32(E1000_VLVF(i));
5740 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5741 vid == (reg & E1000_VLVF_VLANID_MASK))
5742 break;
5743 }
5744
5745 if (add) {
5746 if (i == E1000_VLVF_ARRAY_SIZE) {
5747 /* Did not find a matching VLAN ID entry that was
5748 * enabled. Search for a free filter entry, i.e.
5749 * one without the enable bit set
5750 */
5751 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5752 reg = rd32(E1000_VLVF(i));
5753 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5754 break;
5755 }
5756 }
5757 if (i < E1000_VLVF_ARRAY_SIZE) {
5758 /* Found an enabled/available entry */
5759 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5760
5761 /* if !enabled we need to set this up in vfta */
5762 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5763 /* add VID to filter table */
5764 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5765 reg |= E1000_VLVF_VLANID_ENABLE;
5766 }
cad6d05f
AD		 5767 reg &= ~E1000_VLVF_VLANID_MASK;
5768 reg |= vid;
4ae196df 5769 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5770
5771 /* do not modify RLPML for PF devices */
5772 if (vf >= adapter->vfs_allocated_count)
5773 return 0;
5774
5775 if (!adapter->vf_data[vf].vlans_enabled) {
5776 u32 size;
9005df38 5777
ae641bdc
AD		 5778 reg = rd32(E1000_VMOLR(vf));
5779 size = reg & E1000_VMOLR_RLPML_MASK;
5780 size += 4;
5781 reg &= ~E1000_VMOLR_RLPML_MASK;
5782 reg |= size;
5783 wr32(E1000_VMOLR(vf), reg);
5784 }
ae641bdc 5785
51466239 5786 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5787 }
5788 } else {
5789 if (i < E1000_VLVF_ARRAY_SIZE) {
5790 /* remove vf from the pool */
5791 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5792 /* if pool is empty then remove entry from vfta */
5793 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5794 reg = 0;
5795 igb_vfta_set(hw, vid, false);
5796 }
5797 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5798
5799 /* do not modify RLPML for PF devices */
5800 if (vf >= adapter->vfs_allocated_count)
5801 return 0;
5802
5803 adapter->vf_data[vf].vlans_enabled--;
5804 if (!adapter->vf_data[vf].vlans_enabled) {
5805 u32 size;
9005df38 5806
ae641bdc
AD		 5807 reg = rd32(E1000_VMOLR(vf));
5808 size = reg & E1000_VMOLR_RLPML_MASK;
5809 size -= 4;
5810 reg &= ~E1000_VMOLR_RLPML_MASK;
5811 reg |= size;
5812 wr32(E1000_VMOLR(vf), reg);
5813 }
4ae196df
AD		 5814 }
5815 }
8151d294
WM		 5816 return 0;
5817}
5818
5819static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5820{
5821 struct e1000_hw *hw = &adapter->hw;
5822
5823 if (vid)
5824 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5825 else
5826 wr32(E1000_VMVIR(vf), 0);
5827}
5828
5829static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5830 int vf, u16 vlan, u8 qos)
5831{
5832 int err = 0;
5833 struct igb_adapter *adapter = netdev_priv(netdev);
5834
5835 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5836 return -EINVAL;
5837 if (vlan || qos) {
5838 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5839 if (err)
5840 goto out;
5841 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5842 igb_set_vmolr(adapter, vf, !vlan);
5843 adapter->vf_data[vf].pf_vlan = vlan;
5844 adapter->vf_data[vf].pf_qos = qos;
5845 dev_info(&adapter->pdev->dev,
5846 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5847 if (test_bit(__IGB_DOWN, &adapter->state)) {
5848 dev_warn(&adapter->pdev->dev,
b980ac18 5849 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5850 dev_warn(&adapter->pdev->dev,
b980ac18 5851 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5852 }
5853 } else {
5854 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5855 false, vf);
8151d294
WM		 5856 igb_set_vmvir(adapter, vlan, vf);
5857 igb_set_vmolr(adapter, vf, true);
5858 adapter->vf_data[vf].pf_vlan = 0;
5859 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5860 }
8151d294 5861out:
b980ac18 5862 return err;
4ae196df
AD		 5863}
5864
6f3dc319
GR		 5865static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5866{
5867 struct e1000_hw *hw = &adapter->hw;
5868 int i;
5869 u32 reg;
5870
5871 /* Find the vlan filter for this id */
5872 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5873 reg = rd32(E1000_VLVF(i));
5874 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5875 vid == (reg & E1000_VLVF_VLANID_MASK))
5876 break;
5877 }
5878
5879 if (i >= E1000_VLVF_ARRAY_SIZE)
5880 i = -1;
5881
5882 return i;
5883}
5884
4ae196df
AD		 5885static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5886{
6f3dc319 5887 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5888 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5889 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5890 int err = 0;
4ae196df 5891
6f3dc319
GR		 5892 /* If in promiscuous mode we need to make sure the PF also has
5893 * the VLAN filter set.
5894 */
5895 if (add && (adapter->netdev->flags & IFF_PROMISC))
5896 err = igb_vlvf_set(adapter, vid, add,
5897 adapter->vfs_allocated_count);
5898 if (err)
5899 goto out;
5900
5901 err = igb_vlvf_set(adapter, vid, add, vf);
5902
5903 if (err)
5904 goto out;
5905
5906 /* Go through all the checks to see if the VLAN filter should
5907 * be wiped completely.
5908 */
5909 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5910 u32 vlvf, bits;
6f3dc319 5911 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 5912
6f3dc319
GR		 5913 if (regndx < 0)
5914 goto out;
5915 /* See if any other pools are set for this VLAN filter
5916 * entry other than the PF.
5917 */
5918 vlvf = bits = rd32(E1000_VLVF(regndx));
5919 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5920 adapter->vfs_allocated_count);
5921 /* If the filter was removed then ensure PF pool bit
5922 * is cleared if the PF only added itself to the pool
5923 * because the PF is in promiscuous mode.
5924 */
5925 if ((vlvf & VLAN_VID_MASK) == vid &&
5926 !test_bit(vid, adapter->active_vlans) &&
5927 !bits)
5928 igb_vlvf_set(adapter, vid, add,
5929 adapter->vfs_allocated_count);
5930 }
5931
5932out:
5933 return err;
4ae196df
AD		 5934}
5935
f2ca0dbe 5936static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5937{
8fa7e0f7
GR		 5938 /* clear flags - except flag that indicates PF has set the MAC */
5939 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5940 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5941
5942 /* reset offloads to defaults */
8151d294 5943 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5944
5945 /* reset vlans for device */
5946 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5947 if (adapter->vf_data[vf].pf_vlan)
5948 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5949 adapter->vf_data[vf].pf_vlan,
5950 adapter->vf_data[vf].pf_qos);
5951 else
5952 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5953
5954 /* reset multicast table array for vf */
5955 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5956
5957 /* Flush and reset the mta with the new values */
ff41f8dc 5958 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5959}
5960
f2ca0dbe
AD		 5961static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5962{
5963 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5964
5ac6f91d 5965 /* clear mac address as we were hotplug removed/added */
8151d294 5966 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5967 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5968
5969 /* process remaining reset events */
5970 igb_vf_reset(adapter, vf);
5971}
5972
5973static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5974{
5975 struct e1000_hw *hw = &adapter->hw;
5976 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5977 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5978 u32 reg, msgbuf[3];
5979 u8 *addr = (u8 *)(&msgbuf[1]);
5980
5981 /* process all the same items cleared in a function level reset */
f2ca0dbe 5982 igb_vf_reset(adapter, vf);
4ae196df
AD		 5983
5984 /* set vf mac address */
26ad9178 5985 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5986
5987 /* enable transmit and receive for vf */
5988 reg = rd32(E1000_VFTE);
5989 wr32(E1000_VFTE, reg | (1 << vf));
5990 reg = rd32(E1000_VFRE);
5991 wr32(E1000_VFRE, reg | (1 << vf));
5992
8fa7e0f7 5993 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5994
5995 /* reply to reset with ack and vf mac address */
5996 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5997 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5998 igb_write_mbx(hw, msgbuf, 3, vf);
5999}
6000
6001static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6002{
b980ac18 6003 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6004 * starting at the second 32 bit word of the msg array
6005 */
f2ca0dbe
AD		 6006 unsigned char *addr = (char *)&msg[1];
6007 int err = -1;
4ae196df 6008
f2ca0dbe
AD		 6009 if (is_valid_ether_addr(addr))
6010 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6011
f2ca0dbe 6012 return err;
4ae196df
AD		 6013}
6014
6015static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6016{
6017 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6018 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6019 u32 msg = E1000_VT_MSGTYPE_NACK;
6020
6021 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6022 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6023 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6024 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6025 vf_data->last_nack = jiffies;
4ae196df
AD		 6026 }
6027}
6028
f2ca0dbe 6029static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6030{
f2ca0dbe
AD		 6031 struct pci_dev *pdev = adapter->pdev;
6032 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6033 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6034 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6035 s32 retval;
6036
f2ca0dbe 6037 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6038
fef45f4c
AD		 6039 if (retval) {
6040 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6041 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6042 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6043 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6044 return;
6045 goto out;
6046 }
4ae196df
AD		 6047
6048 /* this is a message we already processed, do nothing */
6049 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6050 return;
4ae196df 6051
b980ac18 6052 /* until the vf completes a reset it should not be
4ae196df
AD		 6053 * allowed to start any configuration.
6054 */
4ae196df
AD		 6055 if (msgbuf[0] == E1000_VF_RESET) {
6056 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6057 return;
4ae196df
AD		 6058 }
6059
f2ca0dbe 6060 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6061 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6062 return;
6063 retval = -1;
6064 goto out;
4ae196df
AD		 6065 }
6066
6067 switch ((msgbuf[0] & 0xFFFF)) {
6068 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6069 retval = -EINVAL;
6070 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6071 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6072 else
6073 dev_warn(&pdev->dev,
b980ac18
JK		 6074 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6075 vf);
4ae196df 6076 break;
7d5753f0
AD		 6077 case E1000_VF_SET_PROMISC:
6078 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6079 break;
4ae196df
AD		 6080 case E1000_VF_SET_MULTICAST:
6081 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6082 break;
6083 case E1000_VF_SET_LPE:
6084 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6085 break;
6086 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6087 retval = -1;
6088 if (vf_data->pf_vlan)
6089 dev_warn(&pdev->dev,
b980ac18
JK		 6090 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6091 vf);
8151d294
WM		 6092 else
6093 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6094 break;
6095 default:
090b1795 6096 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6097 retval = -1;
6098 break;
6099 }
6100
fef45f4c
AD		 6101 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6102out:
4ae196df
AD		 6103 /* notify the VF of the results of what it sent us */
6104 if (retval)
6105 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6106 else
6107 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6108
4ae196df 6109 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6110}
4ae196df 6111
f2ca0dbe
AD		 6112static void igb_msg_task(struct igb_adapter *adapter)
6113{
6114 struct e1000_hw *hw = &adapter->hw;
6115 u32 vf;
6116
6117 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6118 /* process any reset requests */
6119 if (!igb_check_for_rst(hw, vf))
6120 igb_vf_reset_event(adapter, vf);
6121
6122 /* process any messages pending */
6123 if (!igb_check_for_msg(hw, vf))
6124 igb_rcv_msg_from_vf(adapter, vf);
6125
6126 /* process any acks */
6127 if (!igb_check_for_ack(hw, vf))
6128 igb_rcv_ack_from_vf(adapter, vf);
6129 }
4ae196df
AD		 6130}
6131
68d480c4
AD		 6132/**
6133 * igb_set_uta - Set unicast filter table address
6134 * @adapter: board private structure
6135 *
6136 * The unicast table address is a register array of 32-bit registers.
6137 * The table is meant to be used in a way similar to how the MTA is used
6138 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6139 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6140 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6141 **/
6142static void igb_set_uta(struct igb_adapter *adapter)
6143{
6144 struct e1000_hw *hw = &adapter->hw;
6145 int i;
6146
6147 /* The UTA table only exists on 82576 hardware and newer */
6148 if (hw->mac.type < e1000_82576)
6149 return;
6150
6151 /* we only need to do this if VMDq is enabled */
6152 if (!adapter->vfs_allocated_count)
6153 return;
6154
6155 for (i = 0; i < hw->mac.uta_reg_count; i++)
6156 array_wr32(E1000_UTA, i, ~0);
6157}
6158
9d5c8243 6159/**
b980ac18
JK		 6160 * igb_intr_msi - Interrupt Handler
6161 * @irq: interrupt number
6162 * @data: pointer to a network interface device structure
9d5c8243
AK		 6163 **/
6164static irqreturn_t igb_intr_msi(int irq, void *data)
6165{
047e0030
AD		 6166 struct igb_adapter *adapter = data;
6167 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6168 struct e1000_hw *hw = &adapter->hw;
6169 /* read ICR disables interrupts using IAM */
6170 u32 icr = rd32(E1000_ICR);
6171
047e0030 6172 igb_write_itr(q_vector);
9d5c8243 6173
7f081d40
AD		 6174 if (icr & E1000_ICR_DRSTA)
6175 schedule_work(&adapter->reset_task);
6176
047e0030 6177 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6178 /* HW is reporting DMA is out of sync */
6179 adapter->stats.doosync++;
6180 }
6181
9d5c8243
AK		 6182 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6183 hw->mac.get_link_status = 1;
6184 if (!test_bit(__IGB_DOWN, &adapter->state))
6185 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6186 }
6187
1f6e8178
MV		 6188 if (icr & E1000_ICR_TS) {
6189 u32 tsicr = rd32(E1000_TSICR);
6190
6191 if (tsicr & E1000_TSICR_TXTS) {
6192 /* acknowledge the interrupt */
6193 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6194 /* retrieve hardware timestamp */
6195 schedule_work(&adapter->ptp_tx_work);
6196 }
6197 }
1f6e8178 6198
047e0030 6199 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6200
6201 return IRQ_HANDLED;
6202}
6203
6204/**
b980ac18
JK		 6205 * igb_intr - Legacy Interrupt Handler
6206 * @irq: interrupt number
6207 * @data: pointer to a network interface device structure
9d5c8243
AK		 6208 **/
6209static irqreturn_t igb_intr(int irq, void *data)
6210{
047e0030
AD		 6211 struct igb_adapter *adapter = data;
6212 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6213 struct e1000_hw *hw = &adapter->hw;
6214 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6215 * need for the IMC write
6216 */
9d5c8243 6217 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6218
6219 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6220 * not set, then the adapter didn't send an interrupt
6221 */
9d5c8243
AK		 6222 if (!(icr & E1000_ICR_INT_ASSERTED))
6223 return IRQ_NONE;
6224
0ba82994
AD		 6225 igb_write_itr(q_vector);
6226
7f081d40
AD		 6227 if (icr & E1000_ICR_DRSTA)
6228 schedule_work(&adapter->reset_task);
6229
047e0030 6230 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6231 /* HW is reporting DMA is out of sync */
6232 adapter->stats.doosync++;
6233 }
6234
9d5c8243
AK		 6235 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6236 hw->mac.get_link_status = 1;
6237 /* guard against interrupt when we're going down */
6238 if (!test_bit(__IGB_DOWN, &adapter->state))
6239 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6240 }
6241
1f6e8178
MV		 6242 if (icr & E1000_ICR_TS) {
6243 u32 tsicr = rd32(E1000_TSICR);
6244
6245 if (tsicr & E1000_TSICR_TXTS) {
6246 /* acknowledge the interrupt */
6247 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6248 /* retrieve hardware timestamp */
6249 schedule_work(&adapter->ptp_tx_work);
6250 }
6251 }
1f6e8178 6252
047e0030 6253 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6254
6255 return IRQ_HANDLED;
6256}
6257
c50b52a0 6258static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6259{
047e0030 6260 struct igb_adapter *adapter = q_vector->adapter;
46544258 6261 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6262
0ba82994
AD		 6263 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6264 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6265 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6266 igb_set_itr(q_vector);
46544258 6267 else
047e0030 6268 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6269 }
6270
46544258 6271 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6272 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6273 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6274 else
6275 igb_irq_enable(adapter);
6276 }
9d5c8243
AK		 6277}
6278
46544258 6279/**
b980ac18
JK		 6280 * igb_poll - NAPI Rx polling callback
6281 * @napi: napi polling structure
6282 * @budget: count of how many packets we should handle
46544258
AD		 6283 **/
6284static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6285{
047e0030 6286 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6287 struct igb_q_vector,
6288 napi);
16eb8815 6289 bool clean_complete = true;
9d5c8243 6290
421e02f0 6291#ifdef CONFIG_IGB_DCA
047e0030
AD		 6292 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6293 igb_update_dca(q_vector);
fe4506b6 6294#endif
0ba82994 6295 if (q_vector->tx.ring)
13fde97a 6296 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6297
0ba82994 6298 if (q_vector->rx.ring)
cd392f5c 6299 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6300
16eb8815
AD		 6301 /* If all work not completed, return budget and keep polling */
6302 if (!clean_complete)
6303 return budget;
46544258 6304
9d5c8243 6305 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6306 napi_complete(napi);
6307 igb_ring_irq_enable(q_vector);
9d5c8243 6308
16eb8815 6309 return 0;
9d5c8243 6310}
6d8126f9 6311
9d5c8243 6312/**
b980ac18
JK		 6313 * igb_clean_tx_irq - Reclaim resources after transmit completes
6314 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6315 *
b980ac18 6316 * returns true if ring is completely cleaned
9d5c8243 6317 **/
047e0030 6318static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6319{
047e0030 6320 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6321 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6322 struct igb_tx_buffer *tx_buffer;
f4128785 6323 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6324 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6325 unsigned int budget = q_vector->tx.work_limit;
8542db05 6326 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6327
13fde97a
AD		 6328 if (test_bit(__IGB_DOWN, &adapter->state))
6329 return true;
0e014cb1 6330
06034649 6331 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6332 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6333 i -= tx_ring->count;
9d5c8243 6334
f4128785
AD		 6335 do {
6336 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6337
6338 /* if next_to_watch is not set then there is no work pending */
6339 if (!eop_desc)
6340 break;
13fde97a 6341
f4128785 6342 /* prevent any other reads prior to eop_desc */
70d289bc 6343 read_barrier_depends();
f4128785 6344
13fde97a
AD		 6345 /* if DD is not set pending work has not been completed */
6346 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6347 break;
6348
8542db05
AD		 6349 /* clear next_to_watch to prevent false hangs */
6350 tx_buffer->next_to_watch = NULL;
9d5c8243 6351
ebe42d16
AD		 6352 /* update the statistics for this packet */
6353 total_bytes += tx_buffer->bytecount;
6354 total_packets += tx_buffer->gso_segs;
13fde97a 6355
ebe42d16
AD		 6356 /* free the skb */
6357 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6358
ebe42d16
AD		 6359 /* unmap skb header data */
6360 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6361 dma_unmap_addr(tx_buffer, dma),
6362 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6363 DMA_TO_DEVICE);
6364
c9f14bf3
AD		 6365 /* clear tx_buffer data */
6366 tx_buffer->skb = NULL;
6367 dma_unmap_len_set(tx_buffer, len, 0);
6368
ebe42d16
AD		 6369 /* clear last DMA location and unmap remaining buffers */
6370 while (tx_desc != eop_desc) {
13fde97a
AD		 6371 tx_buffer++;
6372 tx_desc++;
9d5c8243 6373 i++;
8542db05
AD		 6374 if (unlikely(!i)) {
6375 i -= tx_ring->count;
06034649 6376 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6377 tx_desc = IGB_TX_DESC(tx_ring, 0);
6378 }
ebe42d16
AD		 6379
6380 /* unmap any remaining paged data */
c9f14bf3 6381 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6382 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6383 dma_unmap_addr(tx_buffer, dma),
6384 dma_unmap_len(tx_buffer, len),
ebe42d16 6385 DMA_TO_DEVICE);
c9f14bf3 6386 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6387 }
6388 }
6389
ebe42d16
AD		 6390 /* move us one more past the eop_desc for start of next pkt */
6391 tx_buffer++;
6392 tx_desc++;
6393 i++;
6394 if (unlikely(!i)) {
6395 i -= tx_ring->count;
6396 tx_buffer = tx_ring->tx_buffer_info;
6397 tx_desc = IGB_TX_DESC(tx_ring, 0);
6398 }
f4128785
AD		 6399
6400 /* issue prefetch for next Tx descriptor */
6401 prefetch(tx_desc);
6402
6403 /* update budget accounting */
6404 budget--;
6405 } while (likely(budget));
0e014cb1 6406
bdbc0631
ED		 6407 netdev_tx_completed_queue(txring_txq(tx_ring),
6408 total_packets, total_bytes);
8542db05 6409 i += tx_ring->count;
9d5c8243 6410 tx_ring->next_to_clean = i;
13fde97a
AD		 6411 u64_stats_update_begin(&tx_ring->tx_syncp);
6412 tx_ring->tx_stats.bytes += total_bytes;
6413 tx_ring->tx_stats.packets += total_packets;
6414 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6415 q_vector->tx.total_bytes += total_bytes;
6416 q_vector->tx.total_packets += total_packets;
9d5c8243 6417
6d095fa8 6418 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6419 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6420
9d5c8243 6421 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6422 * check with the clearing of time_stamp and movement of i
6423 */
6d095fa8 6424 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6425 if (tx_buffer->next_to_watch &&
8542db05 6426 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6427 (adapter->tx_timeout_factor * HZ)) &&
6428 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6429
9d5c8243 6430 /* detected Tx unit hang */
59d71989 6431 dev_err(tx_ring->dev,
9d5c8243 6432 "Detected Tx Unit Hang\n"
2d064c06 6433 " Tx Queue <%d>\n"
9d5c8243
AK		 6434 " TDH <%x>\n"
6435 " TDT <%x>\n"
6436 " next_to_use <%x>\n"
6437 " next_to_clean <%x>\n"
9d5c8243
AK		 6438 "buffer_info[next_to_clean]\n"
6439 " time_stamp <%lx>\n"
8542db05 6440 " next_to_watch <%p>\n"
9d5c8243
AK		 6441 " jiffies <%lx>\n"
6442 " desc.status <%x>\n",
2d064c06 6443 tx_ring->queue_index,
238ac817 6444 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6445 readl(tx_ring->tail),
9d5c8243
AK		 6446 tx_ring->next_to_use,
6447 tx_ring->next_to_clean,
8542db05 6448 tx_buffer->time_stamp,
f4128785 6449 tx_buffer->next_to_watch,
9d5c8243 6450 jiffies,
f4128785 6451 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6452 netif_stop_subqueue(tx_ring->netdev,
6453 tx_ring->queue_index);
6454
6455 /* we are about to reset, no point in enabling stuff */
6456 return true;
9d5c8243
AK		 6457 }
6458 }
13fde97a 6459
21ba6fe1 6460#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6461 if (unlikely(total_packets &&
b980ac18
JK		 6462 netif_carrier_ok(tx_ring->netdev) &&
6463 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6464 /* Make sure that anybody stopping the queue after this
6465 * sees the new next_to_clean.
6466 */
6467 smp_mb();
6468 if (__netif_subqueue_stopped(tx_ring->netdev,
6469 tx_ring->queue_index) &&
6470 !(test_bit(__IGB_DOWN, &adapter->state))) {
6471 netif_wake_subqueue(tx_ring->netdev,
6472 tx_ring->queue_index);
6473
6474 u64_stats_update_begin(&tx_ring->tx_syncp);
6475 tx_ring->tx_stats.restart_queue++;
6476 u64_stats_update_end(&tx_ring->tx_syncp);
6477 }
6478 }
6479
6480 return !!budget;
9d5c8243
AK		 6481}
6482
cbc8e55f 6483/**
b980ac18
JK		 6484 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6485 * @rx_ring: rx descriptor ring to store buffers on
6486 * @old_buff: donor buffer to have page reused
cbc8e55f 6487 *
b980ac18 6488 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6489 **/
6490static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6491 struct igb_rx_buffer *old_buff)
6492{
6493 struct igb_rx_buffer *new_buff;
6494 u16 nta = rx_ring->next_to_alloc;
6495
6496 new_buff = &rx_ring->rx_buffer_info[nta];
6497
6498 /* update, and store next to alloc */
6499 nta++;
6500 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6501
6502 /* transfer page from old buffer to new buffer */
6503 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6504
6505 /* sync the buffer for use by the device */
6506 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6507 old_buff->page_offset,
de78d1f9 6508 IGB_RX_BUFSZ,
cbc8e55f
AD		 6509 DMA_FROM_DEVICE);
6510}
6511
74e238ea
AD		 6512static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6513 struct page *page,
6514 unsigned int truesize)
6515{
6516 /* avoid re-using remote pages */
6517 if (unlikely(page_to_nid(page) != numa_node_id()))
6518 return false;
6519
6520#if (PAGE_SIZE < 8192)
6521 /* if we are only owner of page we can reuse it */
6522 if (unlikely(page_count(page) != 1))
6523 return false;
6524
6525 /* flip page offset to other buffer */
6526 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6527
6528 /* since we are the only owner of the page and we need to
6529 * increment it, just set the value to 2 in order to avoid
6530 * an unnecessary locked operation
6531 */
6532 atomic_set(&page->_count, 2);
6533#else
6534 /* move offset up to the next cache line */
6535 rx_buffer->page_offset += truesize;
6536
6537 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6538 return false;
6539
6540 /* bump ref count on page before it is given to the stack */
6541 get_page(page);
6542#endif
6543
6544 return true;
6545}
6546
cbc8e55f 6547/**
b980ac18
JK		 6548 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6549 * @rx_ring: rx descriptor ring to transact packets on
6550 * @rx_buffer: buffer containing page to add
6551 * @rx_desc: descriptor containing length of buffer written by hardware
6552 * @skb: sk_buff to place the data into
cbc8e55f 6553 *
b980ac18
JK		 6554 * This function will add the data contained in rx_buffer->page to the skb.
6555 * This is done either through a direct copy if the data in the buffer is
6556 * less than the skb header size, otherwise it will just attach the page as
6557 * a frag to the skb.
cbc8e55f 6558 *
b980ac18
JK		 6559 * The function will then update the page offset if necessary and return
6560 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6561 **/
6562static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6563 struct igb_rx_buffer *rx_buffer,
6564 union e1000_adv_rx_desc *rx_desc,
6565 struct sk_buff *skb)
6566{
6567 struct page *page = rx_buffer->page;
6568 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6569#if (PAGE_SIZE < 8192)
6570 unsigned int truesize = IGB_RX_BUFSZ;
6571#else
6572 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6573#endif
cbc8e55f
AD		 6574
6575 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6576 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6577
cbc8e55f
AD		 6578 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6579 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6580 va += IGB_TS_HDR_LEN;
6581 size -= IGB_TS_HDR_LEN;
6582 }
6583
cbc8e55f
AD		 6584 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6585
6586 /* we can reuse buffer as-is, just make sure it is local */
6587 if (likely(page_to_nid(page) == numa_node_id()))
6588 return true;
6589
6590 /* this page cannot be reused so discard it */
6591 put_page(page);
6592 return false;
6593 }
6594
6595 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6596 rx_buffer->page_offset, size, truesize);
cbc8e55f 6597
74e238ea
AD		 6598 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6599}
cbc8e55f 6600
2e334eee
AD		 6601static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6602 union e1000_adv_rx_desc *rx_desc,
6603 struct sk_buff *skb)
6604{
6605 struct igb_rx_buffer *rx_buffer;
6606 struct page *page;
6607
6608 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6609
2e334eee
AD		 6610 page = rx_buffer->page;
6611 prefetchw(page);
6612
6613 if (likely(!skb)) {
6614 void *page_addr = page_address(page) +
6615 rx_buffer->page_offset;
6616
6617 /* prefetch first cache line of first page */
6618 prefetch(page_addr);
6619#if L1_CACHE_BYTES < 128
6620 prefetch(page_addr + L1_CACHE_BYTES);
6621#endif
6622
6623 /* allocate a skb to store the frags */
6624 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6625 IGB_RX_HDR_LEN);
6626 if (unlikely(!skb)) {
6627 rx_ring->rx_stats.alloc_failed++;
6628 return NULL;
6629 }
6630
b980ac18 6631 /* we will be copying header into skb->data in
2e334eee
AD		 6632 * pskb_may_pull so it is in our interest to prefetch
6633 * it now to avoid a possible cache miss
6634 */
6635 prefetchw(skb->data);
6636 }
6637
6638 /* we are reusing so sync this buffer for CPU use */
6639 dma_sync_single_range_for_cpu(rx_ring->dev,
6640 rx_buffer->dma,
6641 rx_buffer->page_offset,
de78d1f9 6642 IGB_RX_BUFSZ,
2e334eee
AD		 6643 DMA_FROM_DEVICE);
6644
6645 /* pull page into skb */
6646 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6647 /* hand second half of page back to the ring */
6648 igb_reuse_rx_page(rx_ring, rx_buffer);
6649 } else {
6650 /* we are not reusing the buffer so unmap it */
6651 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6652 PAGE_SIZE, DMA_FROM_DEVICE);
6653 }
6654
6655 /* clear contents of rx_buffer */
6656 rx_buffer->page = NULL;
6657
6658 return skb;
6659}
6660
cd392f5c 6661static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6662 union e1000_adv_rx_desc *rx_desc,
6663 struct sk_buff *skb)
9d5c8243 6664{
bc8acf2c 6665 skb_checksum_none_assert(skb);
9d5c8243 6666
294e7d78 6667 /* Ignore Checksum bit is set */
3ceb90fd 6668 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6669 return;
6670
6671 /* Rx checksum disabled via ethtool */
6672 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6673 return;
85ad76b2 6674
9d5c8243 6675 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6676 if (igb_test_staterr(rx_desc,
6677 E1000_RXDEXT_STATERR_TCPE |
6678 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6679 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6680 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6681 * packets, (aka let the stack check the crc32c)
6682 */
866cff06
AD		 6683 if (!((skb->len == 60) &&
6684 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6685 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6686 ring->rx_stats.csum_err++;
12dcd86b
ED		 6687 u64_stats_update_end(&ring->rx_syncp);
6688 }
9d5c8243 6689 /* let the stack verify checksum errors */
9d5c8243
AK		 6690 return;
6691 }
6692 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6693 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6694 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6695 skb->ip_summed = CHECKSUM_UNNECESSARY;
6696
3ceb90fd
AD		 6697 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6698 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6699}
6700
077887c3
AD		 6701static inline void igb_rx_hash(struct igb_ring *ring,
6702 union e1000_adv_rx_desc *rx_desc,
6703 struct sk_buff *skb)
6704{
6705 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6706 skb_set_hash(skb,
6707 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6708 PKT_HASH_TYPE_L3);
077887c3
AD		 6709}
6710
2e334eee 6711/**
b980ac18
JK		 6712 * igb_is_non_eop - process handling of non-EOP buffers
6713 * @rx_ring: Rx ring being processed
6714 * @rx_desc: Rx descriptor for current buffer
6715 * @skb: current socket buffer containing buffer in progress
2e334eee 6716 *
b980ac18
JK		 6717 * This function updates next to clean. If the buffer is an EOP buffer
6718 * this function exits returning false, otherwise it will place the
6719 * sk_buff in the next buffer to be chained and return true indicating
6720 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6721 **/
6722static bool igb_is_non_eop(struct igb_ring *rx_ring,
6723 union e1000_adv_rx_desc *rx_desc)
6724{
6725 u32 ntc = rx_ring->next_to_clean + 1;
6726
6727 /* fetch, update, and store next to clean */
6728 ntc = (ntc < rx_ring->count) ? ntc : 0;
6729 rx_ring->next_to_clean = ntc;
6730
6731 prefetch(IGB_RX_DESC(rx_ring, ntc));
6732
6733 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6734 return false;
6735
6736 return true;
6737}
6738
1a1c225b 6739/**
b980ac18
JK		 6740 * igb_get_headlen - determine size of header for LRO/GRO
6741 * @data: pointer to the start of the headers
6742 * @max_len: total length of section to find headers in
1a1c225b 6743 *
b980ac18
JK		 6744 * This function is meant to determine the length of headers that will
6745 * be recognized by hardware for LRO, and GRO offloads. The main
6746 * motivation of doing this is to only perform one pull for IPv4 TCP
6747 * packets so that we can do basic things like calculating the gso_size
6748 * based on the average data per packet.
1a1c225b
AD		 6749 **/
6750static unsigned int igb_get_headlen(unsigned char *data,
6751 unsigned int max_len)
6752{
6753 union {
6754 unsigned char *network;
6755 /* l2 headers */
6756 struct ethhdr *eth;
6757 struct vlan_hdr *vlan;
6758 /* l3 headers */
6759 struct iphdr *ipv4;
6760 struct ipv6hdr *ipv6;
6761 } hdr;
6762 __be16 protocol;
6763 u8 nexthdr = 0; /* default to not TCP */
6764 u8 hlen;
6765
6766 /* this should never happen, but better safe than sorry */
6767 if (max_len < ETH_HLEN)
6768 return max_len;
6769
6770 /* initialize network frame pointer */
6771 hdr.network = data;
6772
6773 /* set first protocol and move network header forward */
6774 protocol = hdr.eth->h_proto;
6775 hdr.network += ETH_HLEN;
6776
6777 /* handle any vlan tag if present */
7c4d16ff 6778 if (protocol == htons(ETH_P_8021Q)) {
1a1c225b
AD		 6779 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6780 return max_len;
6781
6782 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6783 hdr.network += VLAN_HLEN;
6784 }
6785
6786 /* handle L3 protocols */
7c4d16ff 6787 if (protocol == htons(ETH_P_IP)) {
1a1c225b
AD		 6788 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6789 return max_len;
6790
6791 /* access ihl as a u8 to avoid unaligned access on ia64 */
6792 hlen = (hdr.network[0] & 0x0F) << 2;
6793
6794 /* verify hlen meets minimum size requirements */
6795 if (hlen < sizeof(struct iphdr))
6796 return hdr.network - data;
6797
f2fb4ab2 6798 /* record next protocol if header is present */
b9555f66 6799 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6800 nexthdr = hdr.ipv4->protocol;
7c4d16ff 6801 } else if (protocol == htons(ETH_P_IPV6)) {
1a1c225b
AD		 6802 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6803 return max_len;
6804
6805 /* record next protocol */
6806 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6807 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6808 } else {
6809 return hdr.network - data;
6810 }
6811
f2fb4ab2
AD		 6812 /* relocate pointer to start of L4 header */
6813 hdr.network += hlen;
6814
1a1c225b
AD		 6815 /* finally sort out TCP */
6816 if (nexthdr == IPPROTO_TCP) {
6817 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6818 return max_len;
6819
6820 /* access doff as a u8 to avoid unaligned access on ia64 */
6821 hlen = (hdr.network[12] & 0xF0) >> 2;
6822
6823 /* verify hlen meets minimum size requirements */
6824 if (hlen < sizeof(struct tcphdr))
6825 return hdr.network - data;
6826
6827 hdr.network += hlen;
6828 } else if (nexthdr == IPPROTO_UDP) {
6829 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6830 return max_len;
6831
6832 hdr.network += sizeof(struct udphdr);
6833 }
6834
b980ac18 6835 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6836 * data section of the packet and will be the end of the header.
6837 * If not then it probably represents the end of the last recognized
6838 * header.
6839 */
6840 if ((hdr.network - data) < max_len)
6841 return hdr.network - data;
6842 else
6843 return max_len;
6844}
6845
6846/**
b980ac18
JK		 6847 * igb_pull_tail - igb specific version of skb_pull_tail
6848 * @rx_ring: rx descriptor ring packet is being transacted on
6849 * @rx_desc: pointer to the EOP Rx descriptor
6850 * @skb: pointer to current skb being adjusted
1a1c225b 6851 *
b980ac18
JK		 6852 * This function is an igb specific version of __pskb_pull_tail. The
6853 * main difference between this version and the original function is that
6854 * this function can make several assumptions about the state of things
6855 * that allow for significant optimizations versus the standard function.
6856 * As a result we can do things like drop a frag and maintain an accurate
6857 * truesize for the skb.
1a1c225b
AD		 6858 */
6859static void igb_pull_tail(struct igb_ring *rx_ring,
6860 union e1000_adv_rx_desc *rx_desc,
6861 struct sk_buff *skb)
2d94d8ab 6862{
1a1c225b
AD		 6863 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6864 unsigned char *va;
6865 unsigned int pull_len;
6866
b980ac18 6867 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6868 * working with pages allocated out of the lomem pool per
6869 * alloc_page(GFP_ATOMIC)
2d94d8ab 6870 */
1a1c225b
AD		 6871 va = skb_frag_address(frag);
6872
1a1c225b
AD		 6873 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6874 /* retrieve timestamp from buffer */
6875 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6876
6877 /* update pointers to remove timestamp header */
6878 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6879 frag->page_offset += IGB_TS_HDR_LEN;
6880 skb->data_len -= IGB_TS_HDR_LEN;
6881 skb->len -= IGB_TS_HDR_LEN;
6882
6883 /* move va to start of packet data */
6884 va += IGB_TS_HDR_LEN;
6885 }
6886
b980ac18 6887 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6888 * 60 bytes if the skb->len is less than 60 for skb_pad.
6889 */
6890 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6891
6892 /* align pull length to size of long to optimize memcpy performance */
6893 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6894
6895 /* update all of the pointers */
6896 skb_frag_size_sub(frag, pull_len);
6897 frag->page_offset += pull_len;
6898 skb->data_len -= pull_len;
6899 skb->tail += pull_len;
6900}
6901
6902/**
b980ac18
JK		 6903 * igb_cleanup_headers - Correct corrupted or empty headers
6904 * @rx_ring: rx descriptor ring packet is being transacted on
6905 * @rx_desc: pointer to the EOP Rx descriptor
6906 * @skb: pointer to current skb being fixed
1a1c225b 6907 *
b980ac18
JK		 6908 * Address the case where we are pulling data in on pages only
6909 * and as such no data is present in the skb header.
1a1c225b 6910 *
b980ac18
JK		 6911 * In addition if skb is not at least 60 bytes we need to pad it so that
6912 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6913 *
b980ac18 6914 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6915 **/
6916static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6917 union e1000_adv_rx_desc *rx_desc,
6918 struct sk_buff *skb)
6919{
1a1c225b
AD		 6920 if (unlikely((igb_test_staterr(rx_desc,
6921 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6922 struct net_device *netdev = rx_ring->netdev;
6923 if (!(netdev->features & NETIF_F_RXALL)) {
6924 dev_kfree_skb_any(skb);
6925 return true;
6926 }
6927 }
6928
6929 /* place header in linear portion of buffer */
6930 if (skb_is_nonlinear(skb))
6931 igb_pull_tail(rx_ring, rx_desc, skb);
6932
6933 /* if skb_pad returns an error the skb was freed */
6934 if (unlikely(skb->len < 60)) {
6935 int pad_len = 60 - skb->len;
6936
6937 if (skb_pad(skb, pad_len))
6938 return true;
6939 __skb_put(skb, pad_len);
6940 }
6941
6942 return false;
2d94d8ab
AD		 6943}
6944
db2ee5bd 6945/**
b980ac18
JK		 6946 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6947 * @rx_ring: rx descriptor ring packet is being transacted on
6948 * @rx_desc: pointer to the EOP Rx descriptor
6949 * @skb: pointer to current skb being populated
db2ee5bd 6950 *
b980ac18
JK		 6951 * This function checks the ring, descriptor, and packet information in
6952 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6953 * other fields within the skb.
db2ee5bd
AD		 6954 **/
6955static void igb_process_skb_fields(struct igb_ring *rx_ring,
6956 union e1000_adv_rx_desc *rx_desc,
6957 struct sk_buff *skb)
6958{
6959 struct net_device *dev = rx_ring->netdev;
6960
6961 igb_rx_hash(rx_ring, rx_desc, skb);
6962
6963 igb_rx_checksum(rx_ring, rx_desc, skb);
6964
5499a968
JK		 6965 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6966 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6967 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6968
f646968f 6969 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6970 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6971 u16 vid;
9005df38 6972
db2ee5bd
AD		 6973 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6974 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6975 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6976 else
6977 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6978
86a9bad3 6979 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6980 }
6981
6982 skb_record_rx_queue(skb, rx_ring->queue_index);
6983
6984 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6985}
6986
2e334eee 6987static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6988{
0ba82994 6989 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6990 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6991 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6992 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6993
57ba34c9 6994 while (likely(total_packets < budget)) {
2e334eee 6995 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6996
2e334eee
AD		 6997 /* return some buffers to hardware, one at a time is too slow */
6998 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6999 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7000 cleaned_count = 0;
7001 }
bf36c1a0 7002
2e334eee 7003 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7004
2e334eee
AD		 7005 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
7006 break;
9d5c8243 7007
74e238ea
AD		 7008 /* This memory barrier is needed to keep us from reading
7009 * any other fields out of the rx_desc until we know the
7010 * RXD_STAT_DD bit is set
7011 */
7012 rmb();
7013
2e334eee 7014 /* retrieve a buffer from the ring */
f9d40f6a 7015 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7016
2e334eee
AD		 7017 /* exit if we failed to retrieve a buffer */
7018 if (!skb)
7019 break;
1a1c225b 7020
2e334eee 7021 cleaned_count++;
1a1c225b 7022
2e334eee
AD		 7023 /* fetch next buffer in frame if non-eop */
7024 if (igb_is_non_eop(rx_ring, rx_desc))
7025 continue;
1a1c225b
AD		 7026
7027 /* verify the packet layout is correct */
7028 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7029 skb = NULL;
7030 continue;
9d5c8243 7031 }
9d5c8243 7032
db2ee5bd 7033 /* probably a little skewed due to removing CRC */
3ceb90fd 7034 total_bytes += skb->len;
3ceb90fd 7035
db2ee5bd
AD		 7036 /* populate checksum, timestamp, VLAN, and protocol */
7037 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7038
b2cb09b1 7039 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7040
1a1c225b
AD		 7041 /* reset skb pointer */
7042 skb = NULL;
7043
2e334eee
AD		 7044 /* update budget accounting */
7045 total_packets++;
57ba34c9 7046 }
bf36c1a0 7047
1a1c225b
AD		 7048 /* place incomplete frames back on ring for completion */
7049 rx_ring->skb = skb;
7050
12dcd86b 7051 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7052 rx_ring->rx_stats.packets += total_packets;
7053 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7054 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7055 q_vector->rx.total_packets += total_packets;
7056 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7057
7058 if (cleaned_count)
cd392f5c 7059 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7060
da1f1dfe 7061 return total_packets < budget;
9d5c8243
AK		 7062}
7063
c023cd88 7064static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7065 struct igb_rx_buffer *bi)
c023cd88
AD		 7066{
7067 struct page *page = bi->page;
cbc8e55f 7068 dma_addr_t dma;
c023cd88 7069
cbc8e55f
AD		 7070 /* since we are recycling buffers we should seldom need to alloc */
7071 if (likely(page))
c023cd88
AD		 7072 return true;
7073
cbc8e55f
AD		 7074 /* alloc new page for storage */
7075 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
7076 if (unlikely(!page)) {
7077 rx_ring->rx_stats.alloc_failed++;
7078 return false;
c023cd88
AD		 7079 }
7080
cbc8e55f
AD		 7081 /* map page for use */
7082 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7083
b980ac18 7084 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7085 * there isn't much point in holding memory we can't use
7086 */
1a1c225b 7087 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7088 __free_page(page);
7089
c023cd88
AD		 7090 rx_ring->rx_stats.alloc_failed++;
7091 return false;
7092 }
7093
1a1c225b 7094 bi->dma = dma;
cbc8e55f
AD		 7095 bi->page = page;
7096 bi->page_offset = 0;
1a1c225b 7097
c023cd88
AD		 7098 return true;
7099}
7100
9d5c8243 7101/**
b980ac18
JK		 7102 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7103 * @adapter: address of board private structure
9d5c8243 7104 **/
cd392f5c 7105void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7106{
9d5c8243 7107 union e1000_adv_rx_desc *rx_desc;
06034649 7108 struct igb_rx_buffer *bi;
c023cd88 7109 u16 i = rx_ring->next_to_use;
9d5c8243 7110
cbc8e55f
AD		 7111 /* nothing to do */
7112 if (!cleaned_count)
7113 return;
7114
60136906 7115 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7116 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7117 i -= rx_ring->count;
9d5c8243 7118
cbc8e55f 7119 do {
1a1c225b 7120 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7121 break;
9d5c8243 7122
b980ac18 7123 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7124 * because each write-back erases this info.
7125 */
f9d40f6a 7126 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7127
c023cd88
AD		 7128 rx_desc++;
7129 bi++;
9d5c8243 7130 i++;
c023cd88 7131 if (unlikely(!i)) {
60136906 7132 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7133 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7134 i -= rx_ring->count;
7135 }
7136
7137 /* clear the hdr_addr for the next_to_use descriptor */
7138 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7139
7140 cleaned_count--;
7141 } while (cleaned_count);
9d5c8243 7142
c023cd88
AD		 7143 i += rx_ring->count;
7144
9d5c8243 7145 if (rx_ring->next_to_use != i) {
cbc8e55f 7146 /* record the next descriptor to use */
9d5c8243 7147 rx_ring->next_to_use = i;
9d5c8243 7148
cbc8e55f
AD		 7149 /* update next to alloc since we have filled the ring */
7150 rx_ring->next_to_alloc = i;
7151
b980ac18 7152 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7153 * know there are new descriptors to fetch. (Only
7154 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7155 * such as IA-64).
7156 */
9d5c8243 7157 wmb();
fce99e34 7158 writel(i, rx_ring->tail);
9d5c8243
AK		 7159 }
7160}
7161
7162/**
7163 * igb_mii_ioctl -
7164 * @netdev:
7165 * @ifreq:
7166 * @cmd:
7167 **/
7168static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7169{
7170 struct igb_adapter *adapter = netdev_priv(netdev);
7171 struct mii_ioctl_data *data = if_mii(ifr);
7172
7173 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7174 return -EOPNOTSUPP;
7175
7176 switch (cmd) {
7177 case SIOCGMIIPHY:
7178 data->phy_id = adapter->hw.phy.addr;
7179 break;
7180 case SIOCGMIIREG:
f5f4cf08 7181 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7182 &data->val_out))
9d5c8243
AK		 7183 return -EIO;
7184 break;
7185 case SIOCSMIIREG:
7186 default:
7187 return -EOPNOTSUPP;
7188 }
7189 return 0;
7190}
7191
7192/**
7193 * igb_ioctl -
7194 * @netdev:
7195 * @ifreq:
7196 * @cmd:
7197 **/
7198static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7199{
7200 switch (cmd) {
7201 case SIOCGMIIPHY:
7202 case SIOCGMIIREG:
7203 case SIOCSMIIREG:
7204 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7205 case SIOCGHWTSTAMP:
7206 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7207 case SIOCSHWTSTAMP:
6ab5f7b2 7208 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7209 default:
7210 return -EOPNOTSUPP;
7211 }
7212}
7213
009bc06e
AD		 7214s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7215{
7216 struct igb_adapter *adapter = hw->back;
009bc06e 7217
23d028cc 7218 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7219 return -E1000_ERR_CONFIG;
7220
009bc06e
AD		 7221 return 0;
7222}
7223
7224s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7225{
7226 struct igb_adapter *adapter = hw->back;
009bc06e 7227
23d028cc 7228 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7229 return -E1000_ERR_CONFIG;
7230
009bc06e
AD		 7231 return 0;
7232}
7233
c8f44aff 7234static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7235{
7236 struct igb_adapter *adapter = netdev_priv(netdev);
7237 struct e1000_hw *hw = &adapter->hw;
7238 u32 ctrl, rctl;
f646968f 7239 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7240
5faf030c 7241 if (enable) {
9d5c8243
AK		 7242 /* enable VLAN tag insert/strip */
7243 ctrl = rd32(E1000_CTRL);
7244 ctrl |= E1000_CTRL_VME;
7245 wr32(E1000_CTRL, ctrl);
7246
51466239 7247 /* Disable CFI check */
9d5c8243 7248 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7249 rctl &= ~E1000_RCTL_CFIEN;
7250 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7251 } else {
7252 /* disable VLAN tag insert/strip */
7253 ctrl = rd32(E1000_CTRL);
7254 ctrl &= ~E1000_CTRL_VME;
7255 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7256 }
7257
e1739522 7258 igb_rlpml_set(adapter);
9d5c8243
AK		 7259}
7260
80d5c368
PM		 7261static int igb_vlan_rx_add_vid(struct net_device *netdev,
7262 __be16 proto, u16 vid)
9d5c8243
AK		 7263{
7264 struct igb_adapter *adapter = netdev_priv(netdev);
7265 struct e1000_hw *hw = &adapter->hw;
4ae196df 7266 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7267
51466239
AD		 7268 /* attempt to add filter to vlvf array */
7269 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7270
51466239
AD		 7271 /* add the filter since PF can receive vlans w/o entry in vlvf */
7272 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7273
7274 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7275
7276 return 0;
9d5c8243
AK		 7277}
7278
80d5c368
PM		 7279static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7280 __be16 proto, u16 vid)
9d5c8243
AK		 7281{
7282 struct igb_adapter *adapter = netdev_priv(netdev);
7283 struct e1000_hw *hw = &adapter->hw;
4ae196df 7284 int pf_id = adapter->vfs_allocated_count;
51466239 7285 s32 err;
9d5c8243 7286
51466239
AD		 7287 /* remove vlan from VLVF table array */
7288 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7289
51466239
AD		 7290 /* if vid was not present in VLVF just remove it from table */
7291 if (err)
4ae196df 7292 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7293
7294 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7295
7296 return 0;
9d5c8243
AK		 7297}
7298
7299static void igb_restore_vlan(struct igb_adapter *adapter)
7300{
b2cb09b1 7301 u16 vid;
9d5c8243 7302
5faf030c
AD		 7303 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7304
b2cb09b1 7305 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7306 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7307}
7308
14ad2513 7309int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7310{
090b1795 7311 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7312 struct e1000_mac_info *mac = &adapter->hw.mac;
7313
7314 mac->autoneg = 0;
7315
14ad2513 7316 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7317 * for the switch() below to work
7318 */
14ad2513
DD		 7319 if ((spd & 1) || (dplx & ~1))
7320 goto err_inval;
7321
f502ef7d
AA		 7322 /* Fiber NIC's only allow 1000 gbps Full duplex
7323 * and 100Mbps Full duplex for 100baseFx sfp
7324 */
7325 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7326 switch (spd + dplx) {
7327 case SPEED_10 + DUPLEX_HALF:
7328 case SPEED_10 + DUPLEX_FULL:
7329 case SPEED_100 + DUPLEX_HALF:
7330 goto err_inval;
7331 default:
7332 break;
7333 }
7334 }
cd2638a8 7335
14ad2513 7336 switch (spd + dplx) {
9d5c8243
AK		 7337 case SPEED_10 + DUPLEX_HALF:
7338 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7339 break;
7340 case SPEED_10 + DUPLEX_FULL:
7341 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7342 break;
7343 case SPEED_100 + DUPLEX_HALF:
7344 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7345 break;
7346 case SPEED_100 + DUPLEX_FULL:
7347 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7348 break;
7349 case SPEED_1000 + DUPLEX_FULL:
7350 mac->autoneg = 1;
7351 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7352 break;
7353 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7354 default:
14ad2513 7355 goto err_inval;
9d5c8243 7356 }
8376dad0
JB		 7357
7358 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7359 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7360
9d5c8243 7361 return 0;
14ad2513
DD		 7362
7363err_inval:
7364 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7365 return -EINVAL;
9d5c8243
AK		 7366}
7367
749ab2cd
YZ		 7368static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7369 bool runtime)
9d5c8243
AK		 7370{
7371 struct net_device *netdev = pci_get_drvdata(pdev);
7372 struct igb_adapter *adapter = netdev_priv(netdev);
7373 struct e1000_hw *hw = &adapter->hw;
2d064c06 7374 u32 ctrl, rctl, status;
749ab2cd 7375 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7376#ifdef CONFIG_PM
7377 int retval = 0;
7378#endif
7379
7380 netif_device_detach(netdev);
7381
a88f10ec 7382 if (netif_running(netdev))
749ab2cd 7383 __igb_close(netdev, true);
a88f10ec 7384
047e0030 7385 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7386
7387#ifdef CONFIG_PM
7388 retval = pci_save_state(pdev);
7389 if (retval)
7390 return retval;
7391#endif
7392
7393 status = rd32(E1000_STATUS);
7394 if (status & E1000_STATUS_LU)
7395 wufc &= ~E1000_WUFC_LNKC;
7396
7397 if (wufc) {
7398 igb_setup_rctl(adapter);
ff41f8dc 7399 igb_set_rx_mode(netdev);
9d5c8243
AK		 7400
7401 /* turn on all-multi mode if wake on multicast is enabled */
7402 if (wufc & E1000_WUFC_MC) {
7403 rctl = rd32(E1000_RCTL);
7404 rctl |= E1000_RCTL_MPE;
7405 wr32(E1000_RCTL, rctl);
7406 }
7407
7408 ctrl = rd32(E1000_CTRL);
7409 /* advertise wake from D3Cold */
7410 #define E1000_CTRL_ADVD3WUC 0x00100000
7411 /* phy power management enable */
7412 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7413 ctrl |= E1000_CTRL_ADVD3WUC;
7414 wr32(E1000_CTRL, ctrl);
7415
9d5c8243 7416 /* Allow time for pending master requests to run */
330a6d6a 7417 igb_disable_pcie_master(hw);
9d5c8243
AK		 7418
7419 wr32(E1000_WUC, E1000_WUC_PME_EN);
7420 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7421 } else {
7422 wr32(E1000_WUC, 0);
7423 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7424 }
7425
3fe7c4c9
RW		 7426 *enable_wake = wufc || adapter->en_mng_pt;
7427 if (!*enable_wake)
88a268c1
NN		 7428 igb_power_down_link(adapter);
7429 else
7430 igb_power_up_link(adapter);
9d5c8243
AK		 7431
7432 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7433 * would have already happened in close and is redundant.
7434 */
9d5c8243
AK		 7435 igb_release_hw_control(adapter);
7436
7437 pci_disable_device(pdev);
7438
9d5c8243
AK		 7439 return 0;
7440}
7441
7442#ifdef CONFIG_PM
d9dd966d 7443#ifdef CONFIG_PM_SLEEP
749ab2cd 7444static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7445{
7446 int retval;
7447 bool wake;
749ab2cd 7448 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7449
749ab2cd 7450 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7451 if (retval)
7452 return retval;
7453
7454 if (wake) {
7455 pci_prepare_to_sleep(pdev);
7456 } else {
7457 pci_wake_from_d3(pdev, false);
7458 pci_set_power_state(pdev, PCI_D3hot);
7459 }
7460
7461 return 0;
7462}
d9dd966d 7463#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7464
749ab2cd 7465static int igb_resume(struct device *dev)
9d5c8243 7466{
749ab2cd 7467 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7468 struct net_device *netdev = pci_get_drvdata(pdev);
7469 struct igb_adapter *adapter = netdev_priv(netdev);
7470 struct e1000_hw *hw = &adapter->hw;
7471 u32 err;
7472
7473 pci_set_power_state(pdev, PCI_D0);
7474 pci_restore_state(pdev);
b94f2d77 7475 pci_save_state(pdev);
42bfd33a 7476
aed5dec3 7477 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7478 if (err) {
7479 dev_err(&pdev->dev,
7480 "igb: Cannot enable PCI device from suspend\n");
7481 return err;
7482 }
7483 pci_set_master(pdev);
7484
7485 pci_enable_wake(pdev, PCI_D3hot, 0);
7486 pci_enable_wake(pdev, PCI_D3cold, 0);
7487
53c7d064 7488 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7489 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7490 return -ENOMEM;
9d5c8243
AK		 7491 }
7492
9d5c8243 7493 igb_reset(adapter);
a8564f03
AD		 7494
7495 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7496 * driver.
7497 */
a8564f03
AD		 7498 igb_get_hw_control(adapter);
7499
9d5c8243
AK		 7500 wr32(E1000_WUS, ~0);
7501
749ab2cd 7502 if (netdev->flags & IFF_UP) {
0c2cc02e 7503 rtnl_lock();
749ab2cd 7504 err = __igb_open(netdev, true);
0c2cc02e 7505 rtnl_unlock();
a88f10ec
AD		 7506 if (err)
7507 return err;
7508 }
9d5c8243
AK		 7509
7510 netif_device_attach(netdev);
749ab2cd
YZ		 7511 return 0;
7512}
7513
7514#ifdef CONFIG_PM_RUNTIME
7515static int igb_runtime_idle(struct device *dev)
7516{
7517 struct pci_dev *pdev = to_pci_dev(dev);
7518 struct net_device *netdev = pci_get_drvdata(pdev);
7519 struct igb_adapter *adapter = netdev_priv(netdev);
7520
7521 if (!igb_has_link(adapter))
7522 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7523
7524 return -EBUSY;
7525}
7526
7527static int igb_runtime_suspend(struct device *dev)
7528{
7529 struct pci_dev *pdev = to_pci_dev(dev);
7530 int retval;
7531 bool wake;
7532
7533 retval = __igb_shutdown(pdev, &wake, 1);
7534 if (retval)
7535 return retval;
7536
7537 if (wake) {
7538 pci_prepare_to_sleep(pdev);
7539 } else {
7540 pci_wake_from_d3(pdev, false);
7541 pci_set_power_state(pdev, PCI_D3hot);
7542 }
9d5c8243 7543
9d5c8243
AK		 7544 return 0;
7545}
749ab2cd
YZ		 7546
7547static int igb_runtime_resume(struct device *dev)
7548{
7549 return igb_resume(dev);
7550}
7551#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7552#endif
7553
7554static void igb_shutdown(struct pci_dev *pdev)
7555{
3fe7c4c9
RW		 7556 bool wake;
7557
749ab2cd 7558 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7559
7560 if (system_state == SYSTEM_POWER_OFF) {
7561 pci_wake_from_d3(pdev, wake);
7562 pci_set_power_state(pdev, PCI_D3hot);
7563 }
9d5c8243
AK		 7564}
7565
fa44f2f1
GR		 7566#ifdef CONFIG_PCI_IOV
7567static int igb_sriov_reinit(struct pci_dev *dev)
7568{
7569 struct net_device *netdev = pci_get_drvdata(dev);
7570 struct igb_adapter *adapter = netdev_priv(netdev);
7571 struct pci_dev *pdev = adapter->pdev;
7572
7573 rtnl_lock();
7574
7575 if (netif_running(netdev))
7576 igb_close(netdev);
7577
7578 igb_clear_interrupt_scheme(adapter);
7579
7580 igb_init_queue_configuration(adapter);
7581
7582 if (igb_init_interrupt_scheme(adapter, true)) {
7583 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7584 return -ENOMEM;
7585 }
7586
7587 if (netif_running(netdev))
7588 igb_open(netdev);
7589
7590 rtnl_unlock();
7591
7592 return 0;
7593}
7594
7595static int igb_pci_disable_sriov(struct pci_dev *dev)
7596{
7597 int err = igb_disable_sriov(dev);
7598
7599 if (!err)
7600 err = igb_sriov_reinit(dev);
7601
7602 return err;
7603}
7604
7605static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7606{
7607 int err = igb_enable_sriov(dev, num_vfs);
7608
7609 if (err)
7610 goto out;
7611
7612 err = igb_sriov_reinit(dev);
7613 if (!err)
7614 return num_vfs;
7615
7616out:
7617 return err;
7618}
7619
7620#endif
7621static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7622{
7623#ifdef CONFIG_PCI_IOV
7624 if (num_vfs == 0)
7625 return igb_pci_disable_sriov(dev);
7626 else
7627 return igb_pci_enable_sriov(dev, num_vfs);
7628#endif
7629 return 0;
7630}
7631
9d5c8243 7632#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7633/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7634 * without having to re-enable interrupts. It's not called while
7635 * the interrupt routine is executing.
7636 */
7637static void igb_netpoll(struct net_device *netdev)
7638{
7639 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7640 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7641 struct igb_q_vector *q_vector;
9d5c8243 7642 int i;
9d5c8243 7643
047e0030 7644 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7645 q_vector = adapter->q_vector[i];
cd14ef54 7646 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7647 wr32(E1000_EIMC, q_vector->eims_value);
7648 else
7649 igb_irq_disable(adapter);
047e0030 7650 napi_schedule(&q_vector->napi);
eebbbdba 7651 }
9d5c8243
AK		 7652}
7653#endif /* CONFIG_NET_POLL_CONTROLLER */
7654
7655/**
b980ac18
JK		 7656 * igb_io_error_detected - called when PCI error is detected
7657 * @pdev: Pointer to PCI device
7658 * @state: The current pci connection state
9d5c8243 7659 *
b980ac18
JK		 7660 * This function is called after a PCI bus error affecting
7661 * this device has been detected.
7662 **/
9d5c8243
AK		 7663static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7664 pci_channel_state_t state)
7665{
7666 struct net_device *netdev = pci_get_drvdata(pdev);
7667 struct igb_adapter *adapter = netdev_priv(netdev);
7668
7669 netif_device_detach(netdev);
7670
59ed6eec
AD		 7671 if (state == pci_channel_io_perm_failure)
7672 return PCI_ERS_RESULT_DISCONNECT;
7673
9d5c8243
AK		 7674 if (netif_running(netdev))
7675 igb_down(adapter);
7676 pci_disable_device(pdev);
7677
7678 /* Request a slot slot reset. */
7679 return PCI_ERS_RESULT_NEED_RESET;
7680}
7681
7682/**
b980ac18
JK		 7683 * igb_io_slot_reset - called after the pci bus has been reset.
7684 * @pdev: Pointer to PCI device
9d5c8243 7685 *
b980ac18
JK		 7686 * Restart the card from scratch, as if from a cold-boot. Implementation
7687 * resembles the first-half of the igb_resume routine.
7688 **/
9d5c8243
AK		 7689static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7690{
7691 struct net_device *netdev = pci_get_drvdata(pdev);
7692 struct igb_adapter *adapter = netdev_priv(netdev);
7693 struct e1000_hw *hw = &adapter->hw;
40a914fa 7694 pci_ers_result_t result;
42bfd33a 7695 int err;
9d5c8243 7696
aed5dec3 7697 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7698 dev_err(&pdev->dev,
7699 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7700 result = PCI_ERS_RESULT_DISCONNECT;
7701 } else {
7702 pci_set_master(pdev);
7703 pci_restore_state(pdev);
b94f2d77 7704 pci_save_state(pdev);
9d5c8243 7705
40a914fa
AD		 7706 pci_enable_wake(pdev, PCI_D3hot, 0);
7707 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7708
40a914fa
AD		 7709 igb_reset(adapter);
7710 wr32(E1000_WUS, ~0);
7711 result = PCI_ERS_RESULT_RECOVERED;
7712 }
9d5c8243 7713
ea943d41
JK		 7714 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7715 if (err) {
b980ac18
JK		 7716 dev_err(&pdev->dev,
7717 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7718 err);
ea943d41
JK		 7719 /* non-fatal, continue */
7720 }
40a914fa
AD		 7721
7722 return result;
9d5c8243
AK		 7723}
7724
7725/**
b980ac18
JK		 7726 * igb_io_resume - called when traffic can start flowing again.
7727 * @pdev: Pointer to PCI device
9d5c8243 7728 *
b980ac18
JK		 7729 * This callback is called when the error recovery driver tells us that
7730 * its OK to resume normal operation. Implementation resembles the
7731 * second-half of the igb_resume routine.
9d5c8243
AK		 7732 */
7733static void igb_io_resume(struct pci_dev *pdev)
7734{
7735 struct net_device *netdev = pci_get_drvdata(pdev);
7736 struct igb_adapter *adapter = netdev_priv(netdev);
7737
9d5c8243
AK		 7738 if (netif_running(netdev)) {
7739 if (igb_up(adapter)) {
7740 dev_err(&pdev->dev, "igb_up failed after reset\n");
7741 return;
7742 }
7743 }
7744
7745 netif_device_attach(netdev);
7746
7747 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7748 * driver.
7749 */
9d5c8243 7750 igb_get_hw_control(adapter);
9d5c8243
AK		 7751}
7752
26ad9178 7753static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7754 u8 qsel)
26ad9178
AD		 7755{
7756 u32 rar_low, rar_high;
7757 struct e1000_hw *hw = &adapter->hw;
7758
7759 /* HW expects these in little endian so we reverse the byte order
7760 * from network order (big endian) to little endian
7761 */
7762 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7763 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7764 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7765
7766 /* Indicate to hardware the Address is Valid. */
7767 rar_high |= E1000_RAH_AV;
7768
7769 if (hw->mac.type == e1000_82575)
7770 rar_high |= E1000_RAH_POOL_1 * qsel;
7771 else
7772 rar_high |= E1000_RAH_POOL_1 << qsel;
7773
7774 wr32(E1000_RAL(index), rar_low);
7775 wrfl();
7776 wr32(E1000_RAH(index), rar_high);
7777 wrfl();
7778}
7779
4ae196df 7780static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7781 int vf, unsigned char *mac_addr)
4ae196df
AD		 7782{
7783 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7784 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7785 * towards the first, as a result a collision should not be possible
7786 */
ff41f8dc 7787 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7788
37680117 7789 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7790
26ad9178 7791 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7792
7793 return 0;
7794}
7795
8151d294
WM		 7796static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7797{
7798 struct igb_adapter *adapter = netdev_priv(netdev);
7799 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7800 return -EINVAL;
7801 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7802 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7803 dev_info(&adapter->pdev->dev,
7804 "Reload the VF driver to make this change effective.");
8151d294 7805 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7806 dev_warn(&adapter->pdev->dev,
7807 "The VF MAC address has been set, but the PF device is not up.\n");
7808 dev_warn(&adapter->pdev->dev,
7809 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7810 }
7811 return igb_set_vf_mac(adapter, vf, mac);
7812}
7813
17dc566c
LL		 7814static int igb_link_mbps(int internal_link_speed)
7815{
7816 switch (internal_link_speed) {
7817 case SPEED_100:
7818 return 100;
7819 case SPEED_1000:
7820 return 1000;
7821 default:
7822 return 0;
7823 }
7824}
7825
7826static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7827 int link_speed)
7828{
7829 int rf_dec, rf_int;
7830 u32 bcnrc_val;
7831
7832 if (tx_rate != 0) {
7833 /* Calculate the rate factor values to set */
7834 rf_int = link_speed / tx_rate;
7835 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7836 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7837 tx_rate;
17dc566c
LL		 7838
7839 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7840 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7841 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7842 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7843 } else {
7844 bcnrc_val = 0;
7845 }
7846
7847 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7848 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7849 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7850 */
7851 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7852 wr32(E1000_RTTBCNRC, bcnrc_val);
7853}
7854
7855static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7856{
7857 int actual_link_speed, i;
7858 bool reset_rate = false;
7859
7860 /* VF TX rate limit was not set or not supported */
7861 if ((adapter->vf_rate_link_speed == 0) ||
7862 (adapter->hw.mac.type != e1000_82576))
7863 return;
7864
7865 actual_link_speed = igb_link_mbps(adapter->link_speed);
7866 if (actual_link_speed != adapter->vf_rate_link_speed) {
7867 reset_rate = true;
7868 adapter->vf_rate_link_speed = 0;
7869 dev_info(&adapter->pdev->dev,
b980ac18 7870 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7871 }
7872
7873 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7874 if (reset_rate)
7875 adapter->vf_data[i].tx_rate = 0;
7876
7877 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7878 adapter->vf_data[i].tx_rate,
7879 actual_link_speed);
17dc566c
LL		 7880 }
7881}
7882
8151d294
WM		 7883static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7884{
17dc566c
LL		 7885 struct igb_adapter *adapter = netdev_priv(netdev);
7886 struct e1000_hw *hw = &adapter->hw;
7887 int actual_link_speed;
7888
7889 if (hw->mac.type != e1000_82576)
7890 return -EOPNOTSUPP;
7891
7892 actual_link_speed = igb_link_mbps(adapter->link_speed);
7893 if ((vf >= adapter->vfs_allocated_count) ||
7894 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7895 (tx_rate < 0) || (tx_rate > actual_link_speed))
7896 return -EINVAL;
7897
7898 adapter->vf_rate_link_speed = actual_link_speed;
7899 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7900 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7901
7902 return 0;
8151d294
WM		 7903}
7904
70ea4783
LL		 7905static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7906 bool setting)
7907{
7908 struct igb_adapter *adapter = netdev_priv(netdev);
7909 struct e1000_hw *hw = &adapter->hw;
7910 u32 reg_val, reg_offset;
7911
7912 if (!adapter->vfs_allocated_count)
7913 return -EOPNOTSUPP;
7914
7915 if (vf >= adapter->vfs_allocated_count)
7916 return -EINVAL;
7917
7918 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7919 reg_val = rd32(reg_offset);
7920 if (setting)
7921 reg_val |= ((1 << vf) |
7922 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7923 else
7924 reg_val &= ~((1 << vf) |
7925 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7926 wr32(reg_offset, reg_val);
7927
7928 adapter->vf_data[vf].spoofchk_enabled = setting;
7929 return E1000_SUCCESS;
7930}
7931
8151d294
WM		 7932static int igb_ndo_get_vf_config(struct net_device *netdev,
7933 int vf, struct ifla_vf_info *ivi)
7934{
7935 struct igb_adapter *adapter = netdev_priv(netdev);
7936 if (vf >= adapter->vfs_allocated_count)
7937 return -EINVAL;
7938 ivi->vf = vf;
7939 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7940 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7941 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7942 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7943 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7944 return 0;
7945}
7946
4ae196df
AD		 7947static void igb_vmm_control(struct igb_adapter *adapter)
7948{
7949 struct e1000_hw *hw = &adapter->hw;
10d8e907 7950 u32 reg;
4ae196df 7951
52a1dd4d
AD		 7952 switch (hw->mac.type) {
7953 case e1000_82575:
f96a8a0b
CW		 7954 case e1000_i210:
7955 case e1000_i211:
ceb5f13b 7956 case e1000_i354:
52a1dd4d
AD		 7957 default:
7958 /* replication is not supported for 82575 */
4ae196df 7959 return;
52a1dd4d
AD		 7960 case e1000_82576:
7961 /* notify HW that the MAC is adding vlan tags */
7962 reg = rd32(E1000_DTXCTL);
7963 reg |= E1000_DTXCTL_VLAN_ADDED;
7964 wr32(E1000_DTXCTL, reg);
b26141d4 7965 /* Fall through */
52a1dd4d
AD		 7966 case e1000_82580:
7967 /* enable replication vlan tag stripping */
7968 reg = rd32(E1000_RPLOLR);
7969 reg |= E1000_RPLOLR_STRVLAN;
7970 wr32(E1000_RPLOLR, reg);
b26141d4 7971 /* Fall through */
d2ba2ed8
AD		 7972 case e1000_i350:
7973 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7974 break;
7975 }
10d8e907 7976
d4960307
AD		 7977 if (adapter->vfs_allocated_count) {
7978 igb_vmdq_set_loopback_pf(hw, true);
7979 igb_vmdq_set_replication_pf(hw, true);
13800469 7980 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7981 adapter->vfs_allocated_count);
d4960307
AD		 7982 } else {
7983 igb_vmdq_set_loopback_pf(hw, false);
7984 igb_vmdq_set_replication_pf(hw, false);
7985 }
4ae196df
AD		 7986}
7987
b6e0c419
CW		 7988static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7989{
7990 struct e1000_hw *hw = &adapter->hw;
7991 u32 dmac_thr;
7992 u16 hwm;
7993
7994 if (hw->mac.type > e1000_82580) {
7995 if (adapter->flags & IGB_FLAG_DMAC) {
7996 u32 reg;
7997
7998 /* force threshold to 0. */
7999 wr32(E1000_DMCTXTH, 0);
8000
b980ac18 8001 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8002 * than the Rx threshold. Set hwm to PBA - max frame
8003 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8004 */
e8c626e9
MV		 8005 hwm = 64 * pba - adapter->max_frame_size / 16;
8006 if (hwm < 64 * (pba - 6))
8007 hwm = 64 * (pba - 6);
8008 reg = rd32(E1000_FCRTC);
8009 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8010 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8011 & E1000_FCRTC_RTH_COAL_MASK);
8012 wr32(E1000_FCRTC, reg);
8013
b980ac18 8014 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8015 * frame size, capping it at PBA - 10KB.
8016 */
8017 dmac_thr = pba - adapter->max_frame_size / 512;
8018 if (dmac_thr < pba - 10)
8019 dmac_thr = pba - 10;
b6e0c419
CW		 8020 reg = rd32(E1000_DMACR);
8021 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8022 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8023 & E1000_DMACR_DMACTHR_MASK);
8024
8025 /* transition to L0x or L1 if available..*/
8026 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8027
8028 /* watchdog timer= +-1000 usec in 32usec intervals */
8029 reg |= (1000 >> 5);
0c02dd98
MV		 8030
8031 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8032 if (hw->mac.type != e1000_i354)
8033 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8034
b6e0c419
CW		 8035 wr32(E1000_DMACR, reg);
8036
b980ac18 8037 /* no lower threshold to disable
b6e0c419
CW		 8038 * coalescing(smart fifb)-UTRESH=0
8039 */
8040 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8041
8042 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8043
8044 wr32(E1000_DMCTLX, reg);
8045
b980ac18 8046 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8047 * DMA coal
8048 */
8049 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8050 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8051
b980ac18 8052 /* make low power state decision controlled
b6e0c419
CW		 8053 * by DMA coal
8054 */
8055 reg = rd32(E1000_PCIEMISC);
8056 reg &= ~E1000_PCIEMISC_LX_DECISION;
8057 wr32(E1000_PCIEMISC, reg);
8058 } /* endif adapter->dmac is not disabled */
8059 } else if (hw->mac.type == e1000_82580) {
8060 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8061
b6e0c419
CW		 8062 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8063 wr32(E1000_DMACR, 0);
8064 }
8065}
8066
b980ac18
JK		 8067/**
8068 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8069 * @hw: pointer to hardware structure
8070 * @byte_offset: byte offset to read
8071 * @dev_addr: device address
8072 * @data: value read
8073 *
8074 * Performs byte read operation over I2C interface at
8075 * a specified device address.
b980ac18 8076 **/
441fc6fd 8077s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8078 u8 dev_addr, u8 *data)
441fc6fd
CW		 8079{
8080 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8081 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8082 s32 status;
8083 u16 swfw_mask = 0;
8084
8085 if (!this_client)
8086 return E1000_ERR_I2C;
8087
8088 swfw_mask = E1000_SWFW_PHY0_SM;
8089
8090 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
8091 != E1000_SUCCESS)
8092 return E1000_ERR_SWFW_SYNC;
8093
8094 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8095 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8096
8097 if (status < 0)
8098 return E1000_ERR_I2C;
8099 else {
8100 *data = status;
8101 return E1000_SUCCESS;
8102 }
8103}
8104
b980ac18
JK		 8105/**
8106 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8107 * @hw: pointer to hardware structure
8108 * @byte_offset: byte offset to write
8109 * @dev_addr: device address
8110 * @data: value to write
8111 *
8112 * Performs byte write operation over I2C interface at
8113 * a specified device address.
b980ac18 8114 **/
441fc6fd 8115s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8116 u8 dev_addr, u8 data)
441fc6fd
CW		 8117{
8118 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8119 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8120 s32 status;
8121 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8122
8123 if (!this_client)
8124 return E1000_ERR_I2C;
8125
8126 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
8127 return E1000_ERR_SWFW_SYNC;
8128 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8129 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8130
8131 if (status)
8132 return E1000_ERR_I2C;
8133 else
8134 return E1000_SUCCESS;
8135
8136}
907b7835
LMV		 8137
8138int igb_reinit_queues(struct igb_adapter *adapter)
8139{
8140 struct net_device *netdev = adapter->netdev;
8141 struct pci_dev *pdev = adapter->pdev;
8142 int err = 0;
8143
8144 if (netif_running(netdev))
8145 igb_close(netdev);
8146
02ef6e1d 8147 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8148
8149 if (igb_init_interrupt_scheme(adapter, true)) {
8150 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8151 return -ENOMEM;
8152 }
8153
8154 if (netif_running(netdev))
8155 err = igb_open(netdev);
8156
8157 return err;
8158}
9d5c8243 8159/* igb_main.c */
Linux kernel - Deliverables
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