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igb: fix driver reload with VF assigned to guest
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
66f40b8a 65#define BUILD 5
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 126static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 128static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
53c7d064 132static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 139static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
cd392f5c 143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
68d480c4 148static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
047e0030 152static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 153#ifdef CONFIG_IGB_DCA
047e0030 154static void igb_update_dca(struct igb_q_vector *);
fe4506b6 155static void igb_setup_dca(struct igb_adapter *);
421e02f0 156#endif /* CONFIG_IGB_DCA */
661086df 157static int igb_poll(struct napi_struct *, int);
13fde97a 158static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
c8f44aff 163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 166static void igb_restore_vlan(struct igb_adapter *);
26ad9178 167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
4ae196df 170static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
8151d294
WM		 179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
17dc566c 181static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 185static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 186#endif
9d5c8243 187
9d5c8243 188#ifdef CONFIG_PM
d9dd966d 189#ifdef CONFIG_PM_SLEEP
749ab2cd 190static int igb_suspend(struct device *);
d9dd966d 191#endif
749ab2cd
YZ		 192static int igb_resume(struct device *);
193#ifdef CONFIG_PM_RUNTIME
194static int igb_runtime_suspend(struct device *dev);
195static int igb_runtime_resume(struct device *dev);
196static int igb_runtime_idle(struct device *dev);
197#endif
198static const struct dev_pm_ops igb_pm_ops = {
199 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
200 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
201 igb_runtime_idle)
202};
9d5c8243
AK		 203#endif
204static void igb_shutdown(struct pci_dev *);
fa44f2f1 205static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
208static struct notifier_block dca_notifier = {
209 .notifier_call = igb_notify_dca,
210 .next = NULL,
211 .priority = 0
212};
213#endif
9d5c8243
AK		 214#ifdef CONFIG_NET_POLL_CONTROLLER
215/* for netdump / net console */
216static void igb_netpoll(struct net_device *);
217#endif
37680117 218#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 219static unsigned int max_vfs = 0;
220module_param(max_vfs, uint, 0);
221MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
222 "per physical function");
223#endif /* CONFIG_PCI_IOV */
224
9d5c8243
AK		 225static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
226 pci_channel_state_t);
227static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
228static void igb_io_resume(struct pci_dev *);
229
3646f0e5 230static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 231 .error_detected = igb_io_error_detected,
232 .slot_reset = igb_io_slot_reset,
233 .resume = igb_io_resume,
234};
235
b6e0c419 236static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 237
238static struct pci_driver igb_driver = {
239 .name = igb_driver_name,
240 .id_table = igb_pci_tbl,
241 .probe = igb_probe,
9f9a12f8 242 .remove = igb_remove,
9d5c8243 243#ifdef CONFIG_PM
749ab2cd 244 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 245#endif
246 .shutdown = igb_shutdown,
fa44f2f1 247 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 248 .err_handler = &igb_err_handler
249};
250
251MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
252MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
253MODULE_LICENSE("GPL");
254MODULE_VERSION(DRV_VERSION);
255
b3f4d599 256#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
257static int debug = -1;
258module_param(debug, int, 0);
259MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
260
c97ec42a
TI		 261struct igb_reg_info {
262 u32 ofs;
263 char *name;
264};
265
266static const struct igb_reg_info igb_reg_info_tbl[] = {
267
268 /* General Registers */
269 {E1000_CTRL, "CTRL"},
270 {E1000_STATUS, "STATUS"},
271 {E1000_CTRL_EXT, "CTRL_EXT"},
272
273 /* Interrupt Registers */
274 {E1000_ICR, "ICR"},
275
276 /* RX Registers */
277 {E1000_RCTL, "RCTL"},
278 {E1000_RDLEN(0), "RDLEN"},
279 {E1000_RDH(0), "RDH"},
280 {E1000_RDT(0), "RDT"},
281 {E1000_RXDCTL(0), "RXDCTL"},
282 {E1000_RDBAL(0), "RDBAL"},
283 {E1000_RDBAH(0), "RDBAH"},
284
285 /* TX Registers */
286 {E1000_TCTL, "TCTL"},
287 {E1000_TDBAL(0), "TDBAL"},
288 {E1000_TDBAH(0), "TDBAH"},
289 {E1000_TDLEN(0), "TDLEN"},
290 {E1000_TDH(0), "TDH"},
291 {E1000_TDT(0), "TDT"},
292 {E1000_TXDCTL(0), "TXDCTL"},
293 {E1000_TDFH, "TDFH"},
294 {E1000_TDFT, "TDFT"},
295 {E1000_TDFHS, "TDFHS"},
296 {E1000_TDFPC, "TDFPC"},
297
298 /* List Terminator */
299 {}
300};
301
b980ac18 302/* igb_regdump - register printout routine */
c97ec42a
TI		 303static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
304{
305 int n = 0;
306 char rname[16];
307 u32 regs[8];
308
309 switch (reginfo->ofs) {
310 case E1000_RDLEN(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDLEN(n));
313 break;
314 case E1000_RDH(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDH(n));
317 break;
318 case E1000_RDT(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RDT(n));
321 break;
322 case E1000_RXDCTL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RXDCTL(n));
325 break;
326 case E1000_RDBAL(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAL(n));
329 break;
330 case E1000_RDBAH(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAH(n));
333 break;
334 case E1000_TDBAL(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_RDBAL(n));
337 break;
338 case E1000_TDBAH(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDBAH(n));
341 break;
342 case E1000_TDLEN(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDLEN(n));
345 break;
346 case E1000_TDH(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDH(n));
349 break;
350 case E1000_TDT(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TDT(n));
353 break;
354 case E1000_TXDCTL(0):
355 for (n = 0; n < 4; n++)
356 regs[n] = rd32(E1000_TXDCTL(n));
357 break;
358 default:
876d2d6f 359 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 360 return;
361 }
362
363 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 364 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
365 regs[2], regs[3]);
c97ec42a
TI		 366}
367
b980ac18 368/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 369static void igb_dump(struct igb_adapter *adapter)
370{
371 struct net_device *netdev = adapter->netdev;
372 struct e1000_hw *hw = &adapter->hw;
373 struct igb_reg_info *reginfo;
c97ec42a
TI		 374 struct igb_ring *tx_ring;
375 union e1000_adv_tx_desc *tx_desc;
376 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 377 struct igb_ring *rx_ring;
378 union e1000_adv_rx_desc *rx_desc;
379 u32 staterr;
6ad4edfc 380 u16 i, n;
c97ec42a
TI		 381
382 if (!netif_msg_hw(adapter))
383 return;
384
385 /* Print netdevice Info */
386 if (netdev) {
387 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 388 pr_info("Device Name state trans_start "
389 "last_rx\n");
390 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
391 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 392 }
393
394 /* Print Registers */
395 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 396 pr_info(" Register Name Value\n");
c97ec42a
TI		 397 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
398 reginfo->name; reginfo++) {
399 igb_regdump(hw, reginfo);
400 }
401
402 /* Print TX Ring Summary */
403 if (!netdev || !netif_running(netdev))
404 goto exit;
405
406 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 407 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 408 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 409 struct igb_tx_buffer *buffer_info;
c97ec42a 410 tx_ring = adapter->tx_ring[n];
06034649 411 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 412 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
413 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 414 (u64)dma_unmap_addr(buffer_info, dma),
415 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 416 buffer_info->next_to_watch,
417 (u64)buffer_info->time_stamp);
c97ec42a
TI		 418 }
419
420 /* Print TX Rings */
421 if (!netif_msg_tx_done(adapter))
422 goto rx_ring_summary;
423
424 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
425
426 /* Transmit Descriptor Formats
427 *
428 * Advanced Transmit Descriptor
429 * +--------------------------------------------------------------+
430 * 0 | Buffer Address [63:0] |
431 * +--------------------------------------------------------------+
432 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
433 * +--------------------------------------------------------------+
434 * 63 46 45 40 39 38 36 35 32 31 24 15 0
435 */
436
437 for (n = 0; n < adapter->num_tx_queues; n++) {
438 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 439 pr_info("------------------------------------\n");
440 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
441 pr_info("------------------------------------\n");
442 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
443 "[bi->dma ] leng ntw timestamp "
444 "bi->skb\n");
c97ec42a
TI		 445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 447 const char *next_desc;
06034649 448 struct igb_tx_buffer *buffer_info;
60136906 449 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 450 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 451 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 452 if (i == tx_ring->next_to_use &&
453 i == tx_ring->next_to_clean)
454 next_desc = " NTC/U";
455 else if (i == tx_ring->next_to_use)
456 next_desc = " NTU";
457 else if (i == tx_ring->next_to_clean)
458 next_desc = " NTC";
459 else
460 next_desc = "";
461
462 pr_info("T [0x%03X] %016llX %016llX %016llX"
463 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 464 le64_to_cpu(u0->a),
465 le64_to_cpu(u0->b),
c9f14bf3
AD		 466 (u64)dma_unmap_addr(buffer_info, dma),
467 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 468 buffer_info->next_to_watch,
469 (u64)buffer_info->time_stamp,
876d2d6f 470 buffer_info->skb, next_desc);
c97ec42a 471
b669588a 472 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 473 print_hex_dump(KERN_INFO, "",
474 DUMP_PREFIX_ADDRESS,
b669588a 475 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 476 dma_unmap_len(buffer_info, len),
477 true);
c97ec42a
TI		 478 }
479 }
480
481 /* Print RX Rings Summary */
482rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 484 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 487 pr_info(" %5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
497 /* Advanced Receive Descriptor (Read) Format
498 * 63 1 0
499 * +-----------------------------------------------------+
500 * 0 | Packet Buffer Address [63:1] |A0/NSE|
501 * +----------------------------------------------+------+
502 * 8 | Header Buffer Address [63:1] | DD |
503 * +-----------------------------------------------------+
504 *
505 *
506 * Advanced Receive Descriptor (Write-Back) Format
507 *
508 * 63 48 47 32 31 30 21 20 17 16 4 3 0
509 * +------------------------------------------------------+
510 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
511 * | Checksum Ident | | | | Type | Type |
512 * +------------------------------------------------------+
513 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
514 * +------------------------------------------------------+
515 * 63 48 47 32 31 20 19 0
516 */
517
518 for (n = 0; n < adapter->num_rx_queues; n++) {
519 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 520 pr_info("------------------------------------\n");
521 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
522 pr_info("------------------------------------\n");
523 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
524 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
525 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
526 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 527
528 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 529 const char *next_desc;
06034649
AD		 530 struct igb_rx_buffer *buffer_info;
531 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 532 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 533 u0 = (struct my_u0 *)rx_desc;
534 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 535
536 if (i == rx_ring->next_to_use)
537 next_desc = " NTU";
538 else if (i == rx_ring->next_to_clean)
539 next_desc = " NTC";
540 else
541 next_desc = "";
542
c97ec42a
TI		 543 if (staterr & E1000_RXD_STAT_DD) {
544 /* Descriptor Done */
1a1c225b
AD		 545 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
546 "RWB", i,
c97ec42a
TI		 547 le64_to_cpu(u0->a),
548 le64_to_cpu(u0->b),
1a1c225b 549 next_desc);
c97ec42a 550 } else {
1a1c225b
AD		 551 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
552 "R ", i,
c97ec42a
TI		 553 le64_to_cpu(u0->a),
554 le64_to_cpu(u0->b),
555 (u64)buffer_info->dma,
1a1c225b 556 next_desc);
c97ec42a 557
b669588a 558 if (netif_msg_pktdata(adapter) &&
1a1c225b 559 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 560 print_hex_dump(KERN_INFO, "",
561 DUMP_PREFIX_ADDRESS,
562 16, 1,
b669588a
ET		 563 page_address(buffer_info->page) +
564 buffer_info->page_offset,
de78d1f9 565 IGB_RX_BUFSZ, true);
c97ec42a
TI		 566 }
567 }
c97ec42a
TI		 568 }
569 }
570
571exit:
572 return;
573}
574
b980ac18
JK		 575/**
576 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 577 * @hw: pointer to hardware structure
578 * @i2cctl: Current value of I2CCTL register
579 *
580 * Returns the I2C data bit value
b980ac18 581 **/
441fc6fd
CW		 582static int igb_get_i2c_data(void *data)
583{
584 struct igb_adapter *adapter = (struct igb_adapter *)data;
585 struct e1000_hw *hw = &adapter->hw;
586 s32 i2cctl = rd32(E1000_I2CPARAMS);
587
588 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
589}
590
b980ac18
JK		 591/**
592 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 593 * @data: pointer to hardware structure
594 * @state: I2C data value (0 or 1) to set
595 *
596 * Sets the I2C data bit
b980ac18 597 **/
441fc6fd
CW		 598static void igb_set_i2c_data(void *data, int state)
599{
600 struct igb_adapter *adapter = (struct igb_adapter *)data;
601 struct e1000_hw *hw = &adapter->hw;
602 s32 i2cctl = rd32(E1000_I2CPARAMS);
603
604 if (state)
605 i2cctl |= E1000_I2C_DATA_OUT;
606 else
607 i2cctl &= ~E1000_I2C_DATA_OUT;
608
609 i2cctl &= ~E1000_I2C_DATA_OE_N;
610 i2cctl |= E1000_I2C_CLK_OE_N;
611 wr32(E1000_I2CPARAMS, i2cctl);
612 wrfl();
613
614}
615
b980ac18
JK		 616/**
617 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 618 * @data: pointer to hardware structure
619 * @state: state to set clock
620 *
621 * Sets the I2C clock line to state
b980ac18 622 **/
441fc6fd
CW		 623static void igb_set_i2c_clk(void *data, int state)
624{
625 struct igb_adapter *adapter = (struct igb_adapter *)data;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 i2cctl = rd32(E1000_I2CPARAMS);
628
629 if (state) {
630 i2cctl |= E1000_I2C_CLK_OUT;
631 i2cctl &= ~E1000_I2C_CLK_OE_N;
632 } else {
633 i2cctl &= ~E1000_I2C_CLK_OUT;
634 i2cctl &= ~E1000_I2C_CLK_OE_N;
635 }
636 wr32(E1000_I2CPARAMS, i2cctl);
637 wrfl();
638}
639
b980ac18
JK		 640/**
641 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 642 * @data: pointer to hardware structure
643 *
644 * Gets the I2C clock state
b980ac18 645 **/
441fc6fd
CW		 646static int igb_get_i2c_clk(void *data)
647{
648 struct igb_adapter *adapter = (struct igb_adapter *)data;
649 struct e1000_hw *hw = &adapter->hw;
650 s32 i2cctl = rd32(E1000_I2CPARAMS);
651
652 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
653}
654
655static const struct i2c_algo_bit_data igb_i2c_algo = {
656 .setsda = igb_set_i2c_data,
657 .setscl = igb_set_i2c_clk,
658 .getsda = igb_get_i2c_data,
659 .getscl = igb_get_i2c_clk,
660 .udelay = 5,
661 .timeout = 20,
662};
663
9d5c8243 664/**
b980ac18
JK		 665 * igb_get_hw_dev - return device
666 * @hw: pointer to hardware structure
667 *
668 * used by hardware layer to print debugging information
9d5c8243 669 **/
c041076a 670struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 671{
672 struct igb_adapter *adapter = hw->back;
c041076a 673 return adapter->netdev;
9d5c8243 674}
38c845c7 675
9d5c8243 676/**
b980ac18 677 * igb_init_module - Driver Registration Routine
9d5c8243 678 *
b980ac18
JK		 679 * igb_init_module is the first routine called when the driver is
680 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 681 **/
682static int __init igb_init_module(void)
683{
684 int ret;
876d2d6f 685 pr_info("%s - version %s\n",
9d5c8243
AK		 686 igb_driver_string, igb_driver_version);
687
876d2d6f 688 pr_info("%s\n", igb_copyright);
9d5c8243 689
421e02f0 690#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 691 dca_register_notify(&dca_notifier);
692#endif
bbd98fe4 693 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 694 return ret;
695}
696
697module_init(igb_init_module);
698
699/**
b980ac18 700 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 701 *
b980ac18
JK		 702 * igb_exit_module is called just before the driver is removed
703 * from memory.
9d5c8243
AK		 704 **/
705static void __exit igb_exit_module(void)
706{
421e02f0 707#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 708 dca_unregister_notify(&dca_notifier);
709#endif
9d5c8243
AK		 710 pci_unregister_driver(&igb_driver);
711}
712
713module_exit(igb_exit_module);
714
26bc19ec
AD		 715#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
716/**
b980ac18
JK		 717 * igb_cache_ring_register - Descriptor ring to register mapping
718 * @adapter: board private structure to initialize
26bc19ec 719 *
b980ac18
JK		 720 * Once we know the feature-set enabled for the device, we'll cache
721 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 722 **/
723static void igb_cache_ring_register(struct igb_adapter *adapter)
724{
ee1b9f06 725 int i = 0, j = 0;
047e0030 726 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 727
728 switch (adapter->hw.mac.type) {
729 case e1000_82576:
730 /* The queues are allocated for virtualization such that VF 0
731 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
732 * In order to avoid collision we start at the first free queue
733 * and continue consuming queues in the same sequence
734 */
ee1b9f06 735 if (adapter->vfs_allocated_count) {
a99955fc 736 for (; i < adapter->rss_queues; i++)
3025a446 737 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 738 Q_IDX_82576(i);
ee1b9f06 739 }
26bc19ec 740 case e1000_82575:
55cac248 741 case e1000_82580:
d2ba2ed8 742 case e1000_i350:
ceb5f13b 743 case e1000_i354:
f96a8a0b
CW		 744 case e1000_i210:
745 case e1000_i211:
26bc19ec 746 default:
ee1b9f06 747 for (; i < adapter->num_rx_queues; i++)
3025a446 748 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 749 for (; j < adapter->num_tx_queues; j++)
3025a446 750 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 751 break;
752 }
753}
754
4be000c8
AD		 755/**
756 * igb_write_ivar - configure ivar for given MSI-X vector
757 * @hw: pointer to the HW structure
758 * @msix_vector: vector number we are allocating to a given ring
759 * @index: row index of IVAR register to write within IVAR table
760 * @offset: column offset of in IVAR, should be multiple of 8
761 *
762 * This function is intended to handle the writing of the IVAR register
763 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
764 * each containing an cause allocation for an Rx and Tx ring, and a
765 * variable number of rows depending on the number of queues supported.
766 **/
767static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
768 int index, int offset)
769{
770 u32 ivar = array_rd32(E1000_IVAR0, index);
771
772 /* clear any bits that are currently set */
773 ivar &= ~((u32)0xFF << offset);
774
775 /* write vector and valid bit */
776 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
777
778 array_wr32(E1000_IVAR0, index, ivar);
779}
780
9d5c8243 781#define IGB_N0_QUEUE -1
047e0030 782static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 783{
047e0030 784 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 785 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 786 int rx_queue = IGB_N0_QUEUE;
787 int tx_queue = IGB_N0_QUEUE;
4be000c8 788 u32 msixbm = 0;
047e0030 789
0ba82994
AD		 790 if (q_vector->rx.ring)
791 rx_queue = q_vector->rx.ring->reg_idx;
792 if (q_vector->tx.ring)
793 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 794
795 switch (hw->mac.type) {
796 case e1000_82575:
9d5c8243 797 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 798 * bitmask for the EICR/EIMS/EIMC registers. To assign one
799 * or more queues to a vector, we write the appropriate bits
800 * into the MSIXBM register for that vector.
801 */
047e0030 802 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 803 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 804 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 805 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 806 if (!adapter->msix_entries && msix_vector == 0)
807 msixbm |= E1000_EIMS_OTHER;
9d5c8243 808 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 809 q_vector->eims_value = msixbm;
2d064c06
AD		 810 break;
811 case e1000_82576:
b980ac18 812 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 813 * with 8 rows. The ordering is column-major so we use the
814 * lower 3 bits as the row index, and the 4th bit as the
815 * column offset.
816 */
817 if (rx_queue > IGB_N0_QUEUE)
818 igb_write_ivar(hw, msix_vector,
819 rx_queue & 0x7,
820 (rx_queue & 0x8) << 1);
821 if (tx_queue > IGB_N0_QUEUE)
822 igb_write_ivar(hw, msix_vector,
823 tx_queue & 0x7,
824 ((tx_queue & 0x8) << 1) + 8);
047e0030 825 q_vector->eims_value = 1 << msix_vector;
2d064c06 826 break;
55cac248 827 case e1000_82580:
d2ba2ed8 828 case e1000_i350:
ceb5f13b 829 case e1000_i354:
f96a8a0b
CW		 830 case e1000_i210:
831 case e1000_i211:
b980ac18 832 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 833 * however instead of ordering column-major we have things
834 * ordered row-major. So we traverse the table by using
835 * bit 0 as the column offset, and the remaining bits as the
836 * row index.
837 */
838 if (rx_queue > IGB_N0_QUEUE)
839 igb_write_ivar(hw, msix_vector,
840 rx_queue >> 1,
841 (rx_queue & 0x1) << 4);
842 if (tx_queue > IGB_N0_QUEUE)
843 igb_write_ivar(hw, msix_vector,
844 tx_queue >> 1,
845 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 846 q_vector->eims_value = 1 << msix_vector;
847 break;
2d064c06
AD		 848 default:
849 BUG();
850 break;
851 }
26b39276
AD		 852
853 /* add q_vector eims value to global eims_enable_mask */
854 adapter->eims_enable_mask |= q_vector->eims_value;
855
856 /* configure q_vector to set itr on first interrupt */
857 q_vector->set_itr = 1;
9d5c8243
AK		 858}
859
860/**
b980ac18
JK		 861 * igb_configure_msix - Configure MSI-X hardware
862 * @adapter: board private structure to initialize
9d5c8243 863 *
b980ac18
JK		 864 * igb_configure_msix sets up the hardware to properly
865 * generate MSI-X interrupts.
9d5c8243
AK		 866 **/
867static void igb_configure_msix(struct igb_adapter *adapter)
868{
869 u32 tmp;
870 int i, vector = 0;
871 struct e1000_hw *hw = &adapter->hw;
872
873 adapter->eims_enable_mask = 0;
9d5c8243
AK		 874
875 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 876 switch (hw->mac.type) {
877 case e1000_82575:
9d5c8243
AK		 878 tmp = rd32(E1000_CTRL_EXT);
879 /* enable MSI-X PBA support*/
880 tmp |= E1000_CTRL_EXT_PBA_CLR;
881
882 /* Auto-Mask interrupts upon ICR read. */
883 tmp |= E1000_CTRL_EXT_EIAME;
884 tmp |= E1000_CTRL_EXT_IRCA;
885
886 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 887
888 /* enable msix_other interrupt */
b980ac18 889 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 890 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 891
2d064c06
AD		 892 break;
893
894 case e1000_82576:
55cac248 895 case e1000_82580:
d2ba2ed8 896 case e1000_i350:
ceb5f13b 897 case e1000_i354:
f96a8a0b
CW		 898 case e1000_i210:
899 case e1000_i211:
047e0030 900 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 901 * won't stick. And it will take days to debug.
902 */
047e0030 903 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 904 E1000_GPIE_PBA | E1000_GPIE_EIAME |
905 E1000_GPIE_NSICR);
047e0030
AD		 906
907 /* enable msix_other interrupt */
908 adapter->eims_other = 1 << vector;
2d064c06 909 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 910
047e0030 911 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 912 break;
913 default:
914 /* do nothing, since nothing else supports MSI-X */
915 break;
916 } /* switch (hw->mac.type) */
047e0030
AD		 917
918 adapter->eims_enable_mask |= adapter->eims_other;
919
26b39276
AD		 920 for (i = 0; i < adapter->num_q_vectors; i++)
921 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 922
9d5c8243
AK		 923 wrfl();
924}
925
926/**
b980ac18
JK		 927 * igb_request_msix - Initialize MSI-X interrupts
928 * @adapter: board private structure to initialize
9d5c8243 929 *
b980ac18
JK		 930 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
931 * kernel.
9d5c8243
AK		 932 **/
933static int igb_request_msix(struct igb_adapter *adapter)
934{
935 struct net_device *netdev = adapter->netdev;
047e0030 936 struct e1000_hw *hw = &adapter->hw;
52285b76 937 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 938
047e0030 939 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 940 igb_msix_other, 0, netdev->name, adapter);
047e0030 941 if (err)
52285b76 942 goto err_out;
047e0030
AD		 943
944 for (i = 0; i < adapter->num_q_vectors; i++) {
945 struct igb_q_vector *q_vector = adapter->q_vector[i];
946
52285b76
SA		 947 vector++;
948
047e0030
AD		 949 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
950
0ba82994 951 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 952 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 953 q_vector->rx.ring->queue_index);
954 else if (q_vector->tx.ring)
047e0030 955 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 956 q_vector->tx.ring->queue_index);
957 else if (q_vector->rx.ring)
047e0030 958 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 959 q_vector->rx.ring->queue_index);
9d5c8243 960 else
047e0030
AD		 961 sprintf(q_vector->name, "%s-unused", netdev->name);
962
9d5c8243 963 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 964 igb_msix_ring, 0, q_vector->name,
965 q_vector);
9d5c8243 966 if (err)
52285b76 967 goto err_free;
9d5c8243
AK		 968 }
969
9d5c8243
AK		 970 igb_configure_msix(adapter);
971 return 0;
52285b76
SA		 972
973err_free:
974 /* free already assigned IRQs */
975 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
976
977 vector--;
978 for (i = 0; i < vector; i++) {
979 free_irq(adapter->msix_entries[free_vector++].vector,
980 adapter->q_vector[i]);
981 }
982err_out:
9d5c8243
AK		 983 return err;
984}
985
986static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
987{
988 if (adapter->msix_entries) {
989 pci_disable_msix(adapter->pdev);
990 kfree(adapter->msix_entries);
991 adapter->msix_entries = NULL;
047e0030 992 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 993 pci_disable_msi(adapter->pdev);
047e0030 994 }
9d5c8243
AK		 995}
996
5536d210 997/**
b980ac18
JK		 998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
5536d210 1001 *
b980ac18
JK		 1002 * This function frees the memory allocated to the q_vector. In addition if
1003 * NAPI is enabled it will delete any references to the NAPI struct prior
1004 * to freeing the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
1010 if (q_vector->tx.ring)
1011 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1012
1013 if (q_vector->rx.ring)
1014 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1015
1016 adapter->q_vector[v_idx] = NULL;
1017 netif_napi_del(&q_vector->napi);
1018
7f90128e 1019 /* igb_get_stats64() might access the rings on this vector,
5536d210
AD		 1020 * we must wait a grace period before freeing it.
1021 */
1022 kfree_rcu(q_vector, rcu);
1023}
1024
047e0030 1025/**
b980ac18
JK		 1026 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1027 * @adapter: board private structure to initialize
047e0030 1028 *
b980ac18
JK		 1029 * This function frees the memory allocated to the q_vectors. In addition if
1030 * NAPI is enabled it will delete any references to the NAPI struct prior
1031 * to freeing the q_vector.
047e0030
AD		 1032 **/
1033static void igb_free_q_vectors(struct igb_adapter *adapter)
1034{
5536d210
AD		 1035 int v_idx = adapter->num_q_vectors;
1036
1037 adapter->num_tx_queues = 0;
1038 adapter->num_rx_queues = 0;
047e0030 1039 adapter->num_q_vectors = 0;
5536d210
AD		 1040
1041 while (v_idx--)
1042 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1043}
1044
1045/**
b980ac18
JK		 1046 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1047 * @adapter: board private structure to initialize
047e0030 1048 *
b980ac18
JK		 1049 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1050 * MSI-X interrupts allocated.
047e0030
AD		 1051 */
1052static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1053{
047e0030
AD		 1054 igb_free_q_vectors(adapter);
1055 igb_reset_interrupt_capability(adapter);
1056}
9d5c8243
AK		 1057
1058/**
b980ac18
JK		 1059 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1060 * @adapter: board private structure to initialize
1061 * @msix: boolean value of MSIX capability
9d5c8243 1062 *
b980ac18
JK		 1063 * Attempt to configure interrupts using the best available
1064 * capabilities of the hardware and kernel.
9d5c8243 1065 **/
53c7d064 1066static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1067{
1068 int err;
1069 int numvecs, i;
1070
53c7d064
SA		 1071 if (!msix)
1072 goto msi_only;
1073
83b7180d 1074 /* Number of supported queues. */
a99955fc 1075 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1076 if (adapter->vfs_allocated_count)
1077 adapter->num_tx_queues = 1;
1078 else
1079 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1080
b980ac18 1081 /* start with one vector for every Rx queue */
047e0030
AD		 1082 numvecs = adapter->num_rx_queues;
1083
b980ac18 1084 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1085 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1086 numvecs += adapter->num_tx_queues;
047e0030
AD		 1087
1088 /* store the number of vectors reserved for queues */
1089 adapter->num_q_vectors = numvecs;
1090
1091 /* add 1 vector for link status interrupts */
1092 numvecs++;
9d5c8243
AK		 1093 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1094 GFP_KERNEL);
f96a8a0b 1095
9d5c8243
AK		 1096 if (!adapter->msix_entries)
1097 goto msi_only;
1098
1099 for (i = 0; i < numvecs; i++)
1100 adapter->msix_entries[i].entry = i;
1101
1102 err = pci_enable_msix(adapter->pdev,
1103 adapter->msix_entries,
1104 numvecs);
1105 if (err == 0)
0c2cc02e 1106 return;
9d5c8243
AK		 1107
1108 igb_reset_interrupt_capability(adapter);
1109
1110 /* If we can't do MSI-X, try MSI */
1111msi_only:
2a3abf6d
AD		 1112#ifdef CONFIG_PCI_IOV
1113 /* disable SR-IOV for non MSI-X configurations */
1114 if (adapter->vf_data) {
1115 struct e1000_hw *hw = &adapter->hw;
1116 /* disable iov and allow time for transactions to clear */
1117 pci_disable_sriov(adapter->pdev);
1118 msleep(500);
1119
1120 kfree(adapter->vf_data);
1121 adapter->vf_data = NULL;
1122 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1123 wrfl();
2a3abf6d
AD		 1124 msleep(100);
1125 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1126 }
1127#endif
4fc82adf 1128 adapter->vfs_allocated_count = 0;
a99955fc 1129 adapter->rss_queues = 1;
4fc82adf 1130 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1131 adapter->num_rx_queues = 1;
661086df 1132 adapter->num_tx_queues = 1;
047e0030 1133 adapter->num_q_vectors = 1;
9d5c8243 1134 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1135 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1136}
1137
5536d210
AD		 1138static void igb_add_ring(struct igb_ring *ring,
1139 struct igb_ring_container *head)
1140{
1141 head->ring = ring;
1142 head->count++;
1143}
1144
047e0030 1145/**
b980ac18
JK		 1146 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1147 * @adapter: board private structure to initialize
1148 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1149 * @v_idx: index of vector in adapter struct
1150 * @txr_count: total number of Tx rings to allocate
1151 * @txr_idx: index of first Tx ring to allocate
1152 * @rxr_count: total number of Rx rings to allocate
1153 * @rxr_idx: index of first Rx ring to allocate
047e0030 1154 *
b980ac18 1155 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1156 **/
5536d210
AD		 1157static int igb_alloc_q_vector(struct igb_adapter *adapter,
1158 int v_count, int v_idx,
1159 int txr_count, int txr_idx,
1160 int rxr_count, int rxr_idx)
047e0030
AD		 1161{
1162 struct igb_q_vector *q_vector;
5536d210
AD		 1163 struct igb_ring *ring;
1164 int ring_count, size;
047e0030 1165
5536d210
AD		 1166 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1167 if (txr_count > 1 || rxr_count > 1)
1168 return -ENOMEM;
1169
1170 ring_count = txr_count + rxr_count;
1171 size = sizeof(struct igb_q_vector) +
1172 (sizeof(struct igb_ring) * ring_count);
1173
1174 /* allocate q_vector and rings */
1175 q_vector = kzalloc(size, GFP_KERNEL);
1176 if (!q_vector)
1177 return -ENOMEM;
1178
1179 /* initialize NAPI */
1180 netif_napi_add(adapter->netdev, &q_vector->napi,
1181 igb_poll, 64);
1182
1183 /* tie q_vector and adapter together */
1184 adapter->q_vector[v_idx] = q_vector;
1185 q_vector->adapter = adapter;
1186
1187 /* initialize work limits */
1188 q_vector->tx.work_limit = adapter->tx_work_limit;
1189
1190 /* initialize ITR configuration */
1191 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1192 q_vector->itr_val = IGB_START_ITR;
1193
1194 /* initialize pointer to rings */
1195 ring = q_vector->ring;
1196
4e227667
AD		 1197 /* intialize ITR */
1198 if (rxr_count) {
1199 /* rx or rx/tx vector */
1200 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1201 q_vector->itr_val = adapter->rx_itr_setting;
1202 } else {
1203 /* tx only vector */
1204 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1205 q_vector->itr_val = adapter->tx_itr_setting;
1206 }
1207
5536d210
AD		 1208 if (txr_count) {
1209 /* assign generic ring traits */
1210 ring->dev = &adapter->pdev->dev;
1211 ring->netdev = adapter->netdev;
1212
1213 /* configure backlink on ring */
1214 ring->q_vector = q_vector;
1215
1216 /* update q_vector Tx values */
1217 igb_add_ring(ring, &q_vector->tx);
1218
1219 /* For 82575, context index must be unique per ring. */
1220 if (adapter->hw.mac.type == e1000_82575)
1221 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1222
1223 /* apply Tx specific ring traits */
1224 ring->count = adapter->tx_ring_count;
1225 ring->queue_index = txr_idx;
1226
1227 /* assign ring to adapter */
1228 adapter->tx_ring[txr_idx] = ring;
1229
1230 /* push pointer to next ring */
1231 ring++;
047e0030 1232 }
81c2fc22 1233
5536d210
AD		 1234 if (rxr_count) {
1235 /* assign generic ring traits */
1236 ring->dev = &adapter->pdev->dev;
1237 ring->netdev = adapter->netdev;
047e0030 1238
5536d210
AD		 1239 /* configure backlink on ring */
1240 ring->q_vector = q_vector;
047e0030 1241
5536d210
AD		 1242 /* update q_vector Rx values */
1243 igb_add_ring(ring, &q_vector->rx);
047e0030 1244
5536d210
AD		 1245 /* set flag indicating ring supports SCTP checksum offload */
1246 if (adapter->hw.mac.type >= e1000_82576)
1247 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1248
ceb5f13b
CW		 1249 /*
1250 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1251 * have the tag byte-swapped.
b980ac18 1252 */
5536d210
AD		 1253 if (adapter->hw.mac.type >= e1000_i350)
1254 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1255
5536d210
AD		 1256 /* apply Rx specific ring traits */
1257 ring->count = adapter->rx_ring_count;
1258 ring->queue_index = rxr_idx;
1259
1260 /* assign ring to adapter */
1261 adapter->rx_ring[rxr_idx] = ring;
1262 }
1263
1264 return 0;
047e0030
AD		 1265}
1266
5536d210 1267
047e0030 1268/**
b980ac18
JK		 1269 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1270 * @adapter: board private structure to initialize
047e0030 1271 *
b980ac18
JK		 1272 * We allocate one q_vector per queue interrupt. If allocation fails we
1273 * return -ENOMEM.
047e0030 1274 **/
5536d210 1275static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1276{
5536d210
AD		 1277 int q_vectors = adapter->num_q_vectors;
1278 int rxr_remaining = adapter->num_rx_queues;
1279 int txr_remaining = adapter->num_tx_queues;
1280 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1281 int err;
047e0030 1282
5536d210
AD		 1283 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1284 for (; rxr_remaining; v_idx++) {
1285 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1286 0, 0, 1, rxr_idx);
047e0030 1287
5536d210
AD		 1288 if (err)
1289 goto err_out;
1290
1291 /* update counts and index */
1292 rxr_remaining--;
1293 rxr_idx++;
047e0030 1294 }
047e0030 1295 }
5536d210
AD		 1296
1297 for (; v_idx < q_vectors; v_idx++) {
1298 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1299 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1300 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1301 tqpv, txr_idx, rqpv, rxr_idx);
1302
1303 if (err)
1304 goto err_out;
1305
1306 /* update counts and index */
1307 rxr_remaining -= rqpv;
1308 txr_remaining -= tqpv;
1309 rxr_idx++;
1310 txr_idx++;
1311 }
1312
047e0030 1313 return 0;
5536d210
AD		 1314
1315err_out:
1316 adapter->num_tx_queues = 0;
1317 adapter->num_rx_queues = 0;
1318 adapter->num_q_vectors = 0;
1319
1320 while (v_idx--)
1321 igb_free_q_vector(adapter, v_idx);
1322
1323 return -ENOMEM;
047e0030
AD		 1324}
1325
1326/**
b980ac18
JK		 1327 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1328 * @adapter: board private structure to initialize
1329 * @msix: boolean value of MSIX capability
047e0030 1330 *
b980ac18 1331 * This function initializes the interrupts and allocates all of the queues.
047e0030 1332 **/
53c7d064 1333static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1334{
1335 struct pci_dev *pdev = adapter->pdev;
1336 int err;
1337
53c7d064 1338 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1339
1340 err = igb_alloc_q_vectors(adapter);
1341 if (err) {
1342 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1343 goto err_alloc_q_vectors;
1344 }
1345
5536d210 1346 igb_cache_ring_register(adapter);
047e0030
AD		 1347
1348 return 0;
5536d210 1349
047e0030
AD		 1350err_alloc_q_vectors:
1351 igb_reset_interrupt_capability(adapter);
1352 return err;
1353}
1354
9d5c8243 1355/**
b980ac18
JK		 1356 * igb_request_irq - initialize interrupts
1357 * @adapter: board private structure to initialize
9d5c8243 1358 *
b980ac18
JK		 1359 * Attempts to configure interrupts using the best available
1360 * capabilities of the hardware and kernel.
9d5c8243
AK		 1361 **/
1362static int igb_request_irq(struct igb_adapter *adapter)
1363{
1364 struct net_device *netdev = adapter->netdev;
047e0030 1365 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1366 int err = 0;
1367
1368 if (adapter->msix_entries) {
1369 err = igb_request_msix(adapter);
844290e5 1370 if (!err)
9d5c8243 1371 goto request_done;
9d5c8243 1372 /* fall back to MSI */
5536d210
AD		 1373 igb_free_all_tx_resources(adapter);
1374 igb_free_all_rx_resources(adapter);
53c7d064 1375
047e0030 1376 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1377 err = igb_init_interrupt_scheme(adapter, false);
1378 if (err)
047e0030 1379 goto request_done;
53c7d064 1380
047e0030
AD		 1381 igb_setup_all_tx_resources(adapter);
1382 igb_setup_all_rx_resources(adapter);
53c7d064 1383 igb_configure(adapter);
9d5c8243 1384 }
844290e5 1385
c74d588e
AD		 1386 igb_assign_vector(adapter->q_vector[0], 0);
1387
7dfc16fa 1388 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1389 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1390 netdev->name, adapter);
9d5c8243
AK		 1391 if (!err)
1392 goto request_done;
047e0030 1393
9d5c8243
AK		 1394 /* fall back to legacy interrupts */
1395 igb_reset_interrupt_capability(adapter);
7dfc16fa 1396 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1397 }
1398
c74d588e 1399 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1400 netdev->name, adapter);
9d5c8243 1401
6cb5e577 1402 if (err)
c74d588e 1403 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1404 err);
9d5c8243
AK		 1405
1406request_done:
1407 return err;
1408}
1409
1410static void igb_free_irq(struct igb_adapter *adapter)
1411{
9d5c8243
AK		 1412 if (adapter->msix_entries) {
1413 int vector = 0, i;
1414
047e0030 1415 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1416
0d1ae7f4 1417 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1418 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1419 adapter->q_vector[i]);
047e0030
AD		 1420 } else {
1421 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1422 }
9d5c8243
AK		 1423}
1424
1425/**
b980ac18
JK		 1426 * igb_irq_disable - Mask off interrupt generation on the NIC
1427 * @adapter: board private structure
9d5c8243
AK		 1428 **/
1429static void igb_irq_disable(struct igb_adapter *adapter)
1430{
1431 struct e1000_hw *hw = &adapter->hw;
1432
b980ac18 1433 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1434 * mapped into these registers and so clearing the bits can cause
1435 * issues on the VF drivers so we only need to clear what we set
1436 */
9d5c8243 1437 if (adapter->msix_entries) {
2dfd1212
AD		 1438 u32 regval = rd32(E1000_EIAM);
1439 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1440 wr32(E1000_EIMC, adapter->eims_enable_mask);
1441 regval = rd32(E1000_EIAC);
1442 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1443 }
844290e5
PW		 1444
1445 wr32(E1000_IAM, 0);
9d5c8243
AK		 1446 wr32(E1000_IMC, ~0);
1447 wrfl();
81a61859
ET		 1448 if (adapter->msix_entries) {
1449 int i;
1450 for (i = 0; i < adapter->num_q_vectors; i++)
1451 synchronize_irq(adapter->msix_entries[i].vector);
1452 } else {
1453 synchronize_irq(adapter->pdev->irq);
1454 }
9d5c8243
AK		 1455}
1456
1457/**
b980ac18
JK		 1458 * igb_irq_enable - Enable default interrupt generation settings
1459 * @adapter: board private structure
9d5c8243
AK		 1460 **/
1461static void igb_irq_enable(struct igb_adapter *adapter)
1462{
1463 struct e1000_hw *hw = &adapter->hw;
1464
1465 if (adapter->msix_entries) {
06218a8d 1466 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1467 u32 regval = rd32(E1000_EIAC);
1468 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1469 regval = rd32(E1000_EIAM);
1470 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1471 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1472 if (adapter->vfs_allocated_count) {
4ae196df 1473 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1474 ims |= E1000_IMS_VMMB;
1475 }
1476 wr32(E1000_IMS, ims);
844290e5 1477 } else {
55cac248
AD		 1478 wr32(E1000_IMS, IMS_ENABLE_MASK |
1479 E1000_IMS_DRSTA);
1480 wr32(E1000_IAM, IMS_ENABLE_MASK |
1481 E1000_IMS_DRSTA);
844290e5 1482 }
9d5c8243
AK		 1483}
1484
1485static void igb_update_mng_vlan(struct igb_adapter *adapter)
1486{
51466239 1487 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1488 u16 vid = adapter->hw.mng_cookie.vlan_id;
1489 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1490
1491 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1492 /* add VID to filter table */
1493 igb_vfta_set(hw, vid, true);
1494 adapter->mng_vlan_id = vid;
1495 } else {
1496 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1497 }
1498
1499 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1500 (vid != old_vid) &&
b2cb09b1 1501 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1502 /* remove VID from filter table */
1503 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1504 }
1505}
1506
1507/**
b980ac18
JK		 1508 * igb_release_hw_control - release control of the h/w to f/w
1509 * @adapter: address of board private structure
9d5c8243 1510 *
b980ac18
JK		 1511 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1512 * For ASF and Pass Through versions of f/w this means that the
1513 * driver is no longer loaded.
9d5c8243
AK		 1514 **/
1515static void igb_release_hw_control(struct igb_adapter *adapter)
1516{
1517 struct e1000_hw *hw = &adapter->hw;
1518 u32 ctrl_ext;
1519
1520 /* Let firmware take over control of h/w */
1521 ctrl_ext = rd32(E1000_CTRL_EXT);
1522 wr32(E1000_CTRL_EXT,
1523 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1524}
1525
9d5c8243 1526/**
b980ac18
JK		 1527 * igb_get_hw_control - get control of the h/w from f/w
1528 * @adapter: address of board private structure
9d5c8243 1529 *
b980ac18
JK		 1530 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1531 * For ASF and Pass Through versions of f/w this means that
1532 * the driver is loaded.
9d5c8243
AK		 1533 **/
1534static void igb_get_hw_control(struct igb_adapter *adapter)
1535{
1536 struct e1000_hw *hw = &adapter->hw;
1537 u32 ctrl_ext;
1538
1539 /* Let firmware know the driver has taken over */
1540 ctrl_ext = rd32(E1000_CTRL_EXT);
1541 wr32(E1000_CTRL_EXT,
1542 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1543}
1544
9d5c8243 1545/**
b980ac18
JK		 1546 * igb_configure - configure the hardware for RX and TX
1547 * @adapter: private board structure
9d5c8243
AK		 1548 **/
1549static void igb_configure(struct igb_adapter *adapter)
1550{
1551 struct net_device *netdev = adapter->netdev;
1552 int i;
1553
1554 igb_get_hw_control(adapter);
ff41f8dc 1555 igb_set_rx_mode(netdev);
9d5c8243
AK		 1556
1557 igb_restore_vlan(adapter);
9d5c8243 1558
85b430b4 1559 igb_setup_tctl(adapter);
06cf2666 1560 igb_setup_mrqc(adapter);
9d5c8243 1561 igb_setup_rctl(adapter);
85b430b4
AD		 1562
1563 igb_configure_tx(adapter);
9d5c8243 1564 igb_configure_rx(adapter);
662d7205
AD		 1565
1566 igb_rx_fifo_flush_82575(&adapter->hw);
1567
c493ea45 1568 /* call igb_desc_unused which always leaves
9d5c8243 1569 * at least 1 descriptor unused to make sure
b980ac18
JK		 1570 * next_to_use != next_to_clean
1571 */
9d5c8243 1572 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1573 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1574 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1575 }
9d5c8243
AK		 1576}
1577
88a268c1 1578/**
b980ac18
JK		 1579 * igb_power_up_link - Power up the phy/serdes link
1580 * @adapter: address of board private structure
88a268c1
NN		 1581 **/
1582void igb_power_up_link(struct igb_adapter *adapter)
1583{
76886596
AA		 1584 igb_reset_phy(&adapter->hw);
1585
88a268c1
NN		 1586 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1587 igb_power_up_phy_copper(&adapter->hw);
1588 else
1589 igb_power_up_serdes_link_82575(&adapter->hw);
1590}
1591
1592/**
b980ac18
JK		 1593 * igb_power_down_link - Power down the phy/serdes link
1594 * @adapter: address of board private structure
88a268c1
NN		 1595 */
1596static void igb_power_down_link(struct igb_adapter *adapter)
1597{
1598 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1599 igb_power_down_phy_copper_82575(&adapter->hw);
1600 else
1601 igb_shutdown_serdes_link_82575(&adapter->hw);
1602}
9d5c8243
AK		 1603
1604/**
b980ac18
JK		 1605 * igb_up - Open the interface and prepare it to handle traffic
1606 * @adapter: board private structure
9d5c8243 1607 **/
9d5c8243
AK		 1608int igb_up(struct igb_adapter *adapter)
1609{
1610 struct e1000_hw *hw = &adapter->hw;
1611 int i;
1612
1613 /* hardware has been reset, we need to reload some things */
1614 igb_configure(adapter);
1615
1616 clear_bit(__IGB_DOWN, &adapter->state);
1617
0d1ae7f4
AD		 1618 for (i = 0; i < adapter->num_q_vectors; i++)
1619 napi_enable(&(adapter->q_vector[i]->napi));
1620
844290e5 1621 if (adapter->msix_entries)
9d5c8243 1622 igb_configure_msix(adapter);
feeb2721
AD		 1623 else
1624 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1625
1626 /* Clear any pending interrupts. */
1627 rd32(E1000_ICR);
1628 igb_irq_enable(adapter);
1629
d4960307
AD		 1630 /* notify VFs that reset has been completed */
1631 if (adapter->vfs_allocated_count) {
1632 u32 reg_data = rd32(E1000_CTRL_EXT);
1633 reg_data |= E1000_CTRL_EXT_PFRSTD;
1634 wr32(E1000_CTRL_EXT, reg_data);
1635 }
1636
4cb9be7a
JB		 1637 netif_tx_start_all_queues(adapter->netdev);
1638
25568a53
AD		 1639 /* start the watchdog. */
1640 hw->mac.get_link_status = 1;
1641 schedule_work(&adapter->watchdog_task);
1642
9d5c8243
AK		 1643 return 0;
1644}
1645
1646void igb_down(struct igb_adapter *adapter)
1647{
9d5c8243 1648 struct net_device *netdev = adapter->netdev;
330a6d6a 1649 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1650 u32 tctl, rctl;
1651 int i;
1652
1653 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1654 * reschedule our watchdog timer
1655 */
9d5c8243
AK		 1656 set_bit(__IGB_DOWN, &adapter->state);
1657
1658 /* disable receives in the hardware */
1659 rctl = rd32(E1000_RCTL);
1660 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1661 /* flush and sleep below */
1662
fd2ea0a7 1663 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1664
1665 /* disable transmits in the hardware */
1666 tctl = rd32(E1000_TCTL);
1667 tctl &= ~E1000_TCTL_EN;
1668 wr32(E1000_TCTL, tctl);
1669 /* flush both disables and wait for them to finish */
1670 wrfl();
1671 msleep(10);
1672
41f149a2
CW		 1673 igb_irq_disable(adapter);
1674
aa9b8cc4
AA		 1675 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1676
41f149a2
CW		 1677 for (i = 0; i < adapter->num_q_vectors; i++) {
1678 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1679 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1680 }
9d5c8243 1681
9d5c8243
AK		 1682
1683 del_timer_sync(&adapter->watchdog_timer);
1684 del_timer_sync(&adapter->phy_info_timer);
1685
9d5c8243 1686 netif_carrier_off(netdev);
04fe6358
AD		 1687
1688 /* record the stats before reset*/
12dcd86b
ED		 1689 spin_lock(&adapter->stats64_lock);
1690 igb_update_stats(adapter, &adapter->stats64);
1691 spin_unlock(&adapter->stats64_lock);
04fe6358 1692
9d5c8243
AK		 1693 adapter->link_speed = 0;
1694 adapter->link_duplex = 0;
1695
3023682e
JK		 1696 if (!pci_channel_offline(adapter->pdev))
1697 igb_reset(adapter);
9d5c8243
AK		 1698 igb_clean_all_tx_rings(adapter);
1699 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1700#ifdef CONFIG_IGB_DCA
1701
1702 /* since we reset the hardware DCA settings were cleared */
1703 igb_setup_dca(adapter);
1704#endif
9d5c8243
AK		 1705}
1706
1707void igb_reinit_locked(struct igb_adapter *adapter)
1708{
1709 WARN_ON(in_interrupt());
1710 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1711 msleep(1);
1712 igb_down(adapter);
1713 igb_up(adapter);
1714 clear_bit(__IGB_RESETTING, &adapter->state);
1715}
1716
1717void igb_reset(struct igb_adapter *adapter)
1718{
090b1795 1719 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1720 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1721 struct e1000_mac_info *mac = &hw->mac;
1722 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1723 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1724
1725 /* Repartition Pba for greater than 9k mtu
1726 * To take effect CTRL.RST is required.
1727 */
fa4dfae0 1728 switch (mac->type) {
d2ba2ed8 1729 case e1000_i350:
ceb5f13b 1730 case e1000_i354:
55cac248
AD		 1731 case e1000_82580:
1732 pba = rd32(E1000_RXPBS);
1733 pba = igb_rxpbs_adjust_82580(pba);
1734 break;
fa4dfae0 1735 case e1000_82576:
d249be54
AD		 1736 pba = rd32(E1000_RXPBS);
1737 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1738 break;
1739 case e1000_82575:
f96a8a0b
CW		 1740 case e1000_i210:
1741 case e1000_i211:
fa4dfae0
AD		 1742 default:
1743 pba = E1000_PBA_34K;
1744 break;
2d064c06 1745 }
9d5c8243 1746
2d064c06
AD		 1747 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1748 (mac->type < e1000_82576)) {
9d5c8243
AK		 1749 /* adjust PBA for jumbo frames */
1750 wr32(E1000_PBA, pba);
1751
1752 /* To maintain wire speed transmits, the Tx FIFO should be
1753 * large enough to accommodate two full transmit packets,
1754 * rounded up to the next 1KB and expressed in KB. Likewise,
1755 * the Rx FIFO should be large enough to accommodate at least
1756 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1757 * expressed in KB.
1758 */
9d5c8243
AK		 1759 pba = rd32(E1000_PBA);
1760 /* upper 16 bits has Tx packet buffer allocation size in KB */
1761 tx_space = pba >> 16;
1762 /* lower 16 bits has Rx packet buffer allocation size in KB */
1763 pba &= 0xffff;
b980ac18
JK		 1764 /* the Tx fifo also stores 16 bytes of information about the Tx
1765 * but don't include ethernet FCS because hardware appends it
1766 */
9d5c8243 1767 min_tx_space = (adapter->max_frame_size +
85e8d004 1768 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1769 ETH_FCS_LEN) * 2;
1770 min_tx_space = ALIGN(min_tx_space, 1024);
1771 min_tx_space >>= 10;
1772 /* software strips receive CRC, so leave room for it */
1773 min_rx_space = adapter->max_frame_size;
1774 min_rx_space = ALIGN(min_rx_space, 1024);
1775 min_rx_space >>= 10;
1776
1777 /* If current Tx allocation is less than the min Tx FIFO size,
1778 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1779 * allocation, take space away from current Rx allocation
1780 */
9d5c8243
AK		 1781 if (tx_space < min_tx_space &&
1782 ((min_tx_space - tx_space) < pba)) {
1783 pba = pba - (min_tx_space - tx_space);
1784
b980ac18
JK		 1785 /* if short on Rx space, Rx wins and must trump Tx
1786 * adjustment
1787 */
9d5c8243
AK		 1788 if (pba < min_rx_space)
1789 pba = min_rx_space;
1790 }
2d064c06 1791 wr32(E1000_PBA, pba);
9d5c8243 1792 }
9d5c8243
AK		 1793
1794 /* flow control settings */
1795 /* The high water mark must be low enough to fit one full frame
1796 * (or the size used for early receive) above it in the Rx FIFO.
1797 * Set it to the lower of:
1798 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1799 * - the full Rx FIFO size minus one full frame
1800 */
9d5c8243 1801 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1802 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1803
d48507fe 1804 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1805 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1806 fc->pause_time = 0xFFFF;
1807 fc->send_xon = 1;
0cce119a 1808 fc->current_mode = fc->requested_mode;
9d5c8243 1809
4ae196df
AD		 1810 /* disable receive for all VFs and wait one second */
1811 if (adapter->vfs_allocated_count) {
1812 int i;
1813 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1814 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1815
1816 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1817 igb_ping_all_vfs(adapter);
4ae196df
AD		 1818
1819 /* disable transmits and receives */
1820 wr32(E1000_VFRE, 0);
1821 wr32(E1000_VFTE, 0);
1822 }
1823
9d5c8243 1824 /* Allow time for pending master requests to run */
330a6d6a 1825 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1826 wr32(E1000_WUC, 0);
1827
330a6d6a 1828 if (hw->mac.ops.init_hw(hw))
090b1795 1829 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1830
b980ac18 1831 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1832 * control is off when forcing speed.
1833 */
1834 if (!hw->mac.autoneg)
1835 igb_force_mac_fc(hw);
1836
b6e0c419 1837 igb_init_dmac(adapter, pba);
e428893b
CW		 1838#ifdef CONFIG_IGB_HWMON
1839 /* Re-initialize the thermal sensor on i350 devices. */
1840 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1841 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1842 /* If present, re-initialize the external thermal sensor
1843 * interface.
1844 */
1845 if (adapter->ets)
1846 mac->ops.init_thermal_sensor_thresh(hw);
1847 }
1848 }
1849#endif
88a268c1
NN		 1850 if (!netif_running(adapter->netdev))
1851 igb_power_down_link(adapter);
1852
9d5c8243
AK		 1853 igb_update_mng_vlan(adapter);
1854
1855 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1856 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1857
1f6e8178
MV		 1858 /* Re-enable PTP, where applicable. */
1859 igb_ptp_reset(adapter);
1f6e8178 1860
330a6d6a 1861 igb_get_phy_info(hw);
9d5c8243
AK		 1862}
1863
c8f44aff
MM		 1864static netdev_features_t igb_fix_features(struct net_device *netdev,
1865 netdev_features_t features)
b2cb09b1 1866{
b980ac18
JK		 1867 /* Since there is no support for separate Rx/Tx vlan accel
1868 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1869 */
f646968f
PM		 1870 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1871 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1872 else
f646968f 1873 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1874
1875 return features;
1876}
1877
c8f44aff
MM		 1878static int igb_set_features(struct net_device *netdev,
1879 netdev_features_t features)
ac52caa3 1880{
c8f44aff 1881 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1882 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1883
f646968f 1884 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1885 igb_vlan_mode(netdev, features);
1886
89eaefb6
BG		 1887 if (!(changed & NETIF_F_RXALL))
1888 return 0;
1889
1890 netdev->features = features;
1891
1892 if (netif_running(netdev))
1893 igb_reinit_locked(adapter);
1894 else
1895 igb_reset(adapter);
1896
ac52caa3
MM		 1897 return 0;
1898}
1899
2e5c6922 1900static const struct net_device_ops igb_netdev_ops = {
559e9c49 1901 .ndo_open = igb_open,
2e5c6922 1902 .ndo_stop = igb_close,
cd392f5c 1903 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1904 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1905 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1906 .ndo_set_mac_address = igb_set_mac,
1907 .ndo_change_mtu = igb_change_mtu,
1908 .ndo_do_ioctl = igb_ioctl,
1909 .ndo_tx_timeout = igb_tx_timeout,
1910 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1911 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1912 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1913 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1914 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1915 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1916 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1917 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1918#ifdef CONFIG_NET_POLL_CONTROLLER
1919 .ndo_poll_controller = igb_netpoll,
1920#endif
b2cb09b1
JP		 1921 .ndo_fix_features = igb_fix_features,
1922 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1923};
1924
d67974f0
CW		 1925/**
1926 * igb_set_fw_version - Configure version string for ethtool
1927 * @adapter: adapter struct
d67974f0
CW		 1928 **/
1929void igb_set_fw_version(struct igb_adapter *adapter)
1930{
1931 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1932 struct e1000_fw_version fw;
1933
1934 igb_get_fw_version(hw, &fw);
1935
1936 switch (hw->mac.type) {
7dc98a62 1937 case e1000_i210:
0b1a6f2e 1938 case e1000_i211:
7dc98a62
CW		 1939 if (!(igb_get_flash_presence_i210(hw))) {
1940 snprintf(adapter->fw_version,
1941 sizeof(adapter->fw_version),
1942 "%2d.%2d-%d",
1943 fw.invm_major, fw.invm_minor,
1944 fw.invm_img_type);
1945 break;
1946 }
1947 /* fall through */
0b1a6f2e
CW		 1948 default:
1949 /* if option is rom valid, display its version too */
1950 if (fw.or_valid) {
1951 snprintf(adapter->fw_version,
1952 sizeof(adapter->fw_version),
1953 "%d.%d, 0x%08x, %d.%d.%d",
1954 fw.eep_major, fw.eep_minor, fw.etrack_id,
1955 fw.or_major, fw.or_build, fw.or_patch);
1956 /* no option rom */
7dc98a62 1957 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 1958 snprintf(adapter->fw_version,
7dc98a62
CW		 1959 sizeof(adapter->fw_version),
1960 "%d.%d, 0x%08x",
1961 fw.eep_major, fw.eep_minor, fw.etrack_id);
1962 } else {
1963 snprintf(adapter->fw_version,
1964 sizeof(adapter->fw_version),
1965 "%d.%d.%d",
1966 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 1967 }
1968 break;
d67974f0 1969 }
d67974f0
CW		 1970 return;
1971}
1972
b980ac18
JK		 1973/**
1974 * igb_init_i2c - Init I2C interface
441fc6fd 1975 * @adapter: pointer to adapter structure
b980ac18 1976 **/
441fc6fd
CW		 1977static s32 igb_init_i2c(struct igb_adapter *adapter)
1978{
1979 s32 status = E1000_SUCCESS;
1980
1981 /* I2C interface supported on i350 devices */
1982 if (adapter->hw.mac.type != e1000_i350)
1983 return E1000_SUCCESS;
1984
1985 /* Initialize the i2c bus which is controlled by the registers.
1986 * This bus will use the i2c_algo_bit structue that implements
1987 * the protocol through toggling of the 4 bits in the register.
1988 */
1989 adapter->i2c_adap.owner = THIS_MODULE;
1990 adapter->i2c_algo = igb_i2c_algo;
1991 adapter->i2c_algo.data = adapter;
1992 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1993 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1994 strlcpy(adapter->i2c_adap.name, "igb BB",
1995 sizeof(adapter->i2c_adap.name));
1996 status = i2c_bit_add_bus(&adapter->i2c_adap);
1997 return status;
1998}
1999
9d5c8243 2000/**
b980ac18
JK		 2001 * igb_probe - Device Initialization Routine
2002 * @pdev: PCI device information struct
2003 * @ent: entry in igb_pci_tbl
9d5c8243 2004 *
b980ac18 2005 * Returns 0 on success, negative on failure
9d5c8243 2006 *
b980ac18
JK		 2007 * igb_probe initializes an adapter identified by a pci_dev structure.
2008 * The OS initialization, configuring of the adapter private structure,
2009 * and a hardware reset occur.
9d5c8243 2010 **/
1dd06ae8 2011static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2012{
2013 struct net_device *netdev;
2014 struct igb_adapter *adapter;
2015 struct e1000_hw *hw;
4337e993 2016 u16 eeprom_data = 0;
9835fd73 2017 s32 ret_val;
4337e993 2018 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 2019 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2020 unsigned long mmio_start, mmio_len;
2d6a5e95 2021 int err, pci_using_dac;
9835fd73 2022 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2023
bded64a7
AG		 2024 /* Catch broken hardware that put the wrong VF device ID in
2025 * the PCIe SR-IOV capability.
2026 */
2027 if (pdev->is_virtfn) {
2028 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2029 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2030 return -EINVAL;
2031 }
2032
aed5dec3 2033 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2034 if (err)
2035 return err;
2036
2037 pci_using_dac = 0;
59d71989 2038 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2039 if (!err) {
59d71989 2040 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 2041 if (!err)
2042 pci_using_dac = 1;
2043 } else {
59d71989 2044 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2045 if (err) {
b980ac18
JK		 2046 err = dma_set_coherent_mask(&pdev->dev,
2047 DMA_BIT_MASK(32));
9d5c8243 2048 if (err) {
b980ac18
JK		 2049 dev_err(&pdev->dev,
2050 "No usable DMA configuration, aborting\n");
9d5c8243
AK		 2051 goto err_dma;
2052 }
2053 }
2054 }
2055
aed5dec3 2056 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2057 IORESOURCE_MEM),
2058 igb_driver_name);
9d5c8243
AK		 2059 if (err)
2060 goto err_pci_reg;
2061
19d5afd4 2062 pci_enable_pcie_error_reporting(pdev);
40a914fa 2063
9d5c8243 2064 pci_set_master(pdev);
c682fc23 2065 pci_save_state(pdev);
9d5c8243
AK		 2066
2067 err = -ENOMEM;
1bfaf07b 2068 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2069 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2070 if (!netdev)
2071 goto err_alloc_etherdev;
2072
2073 SET_NETDEV_DEV(netdev, &pdev->dev);
2074
2075 pci_set_drvdata(pdev, netdev);
2076 adapter = netdev_priv(netdev);
2077 adapter->netdev = netdev;
2078 adapter->pdev = pdev;
2079 hw = &adapter->hw;
2080 hw->back = adapter;
b3f4d599 2081 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2082
2083 mmio_start = pci_resource_start(pdev, 0);
2084 mmio_len = pci_resource_len(pdev, 0);
2085
2086 err = -EIO;
28b0759c
AD		 2087 hw->hw_addr = ioremap(mmio_start, mmio_len);
2088 if (!hw->hw_addr)
9d5c8243
AK		 2089 goto err_ioremap;
2090
2e5c6922 2091 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2092 igb_set_ethtool_ops(netdev);
9d5c8243 2093 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2094
2095 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2096
2097 netdev->mem_start = mmio_start;
2098 netdev->mem_end = mmio_start + mmio_len;
2099
9d5c8243
AK		 2100 /* PCI config space info */
2101 hw->vendor_id = pdev->vendor;
2102 hw->device_id = pdev->device;
2103 hw->revision_id = pdev->revision;
2104 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2105 hw->subsystem_device_id = pdev->subsystem_device;
2106
9d5c8243
AK		 2107 /* Copy the default MAC, PHY and NVM function pointers */
2108 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2109 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2110 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2111 /* Initialize skew-specific constants */
2112 err = ei->get_invariants(hw);
2113 if (err)
450c87c8 2114 goto err_sw_init;
9d5c8243 2115
450c87c8 2116 /* setup the private structure */
9d5c8243
AK		 2117 err = igb_sw_init(adapter);
2118 if (err)
2119 goto err_sw_init;
2120
2121 igb_get_bus_info_pcie(hw);
2122
2123 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2124
2125 /* Copper options */
2126 if (hw->phy.media_type == e1000_media_type_copper) {
2127 hw->phy.mdix = AUTO_ALL_MODES;
2128 hw->phy.disable_polarity_correction = false;
2129 hw->phy.ms_type = e1000_ms_hw_default;
2130 }
2131
2132 if (igb_check_reset_block(hw))
2133 dev_info(&pdev->dev,
2134 "PHY reset is blocked due to SOL/IDER session.\n");
2135
b980ac18 2136 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2137 * set by igb_sw_init so we should use an or instead of an
2138 * assignment.
2139 */
2140 netdev->features |= NETIF_F_SG |
2141 NETIF_F_IP_CSUM |
2142 NETIF_F_IPV6_CSUM |
2143 NETIF_F_TSO |
2144 NETIF_F_TSO6 |
2145 NETIF_F_RXHASH |
2146 NETIF_F_RXCSUM |
f646968f
PM		 2147 NETIF_F_HW_VLAN_CTAG_RX |
2148 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2149
2150 /* copy netdev features into list of user selectable features */
2151 netdev->hw_features |= netdev->features;
89eaefb6 2152 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2153
2154 /* set this bit last since it cannot be part of hw_features */
f646968f 2155 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2156
2157 netdev->vlan_features |= NETIF_F_TSO |
2158 NETIF_F_TSO6 |
2159 NETIF_F_IP_CSUM |
2160 NETIF_F_IPV6_CSUM |
2161 NETIF_F_SG;
48f29ffc 2162
6b8f0922
BG		 2163 netdev->priv_flags |= IFF_SUPP_NOFCS;
2164
7b872a55 2165 if (pci_using_dac) {
9d5c8243 2166 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2167 netdev->vlan_features |= NETIF_F_HIGHDMA;
2168 }
9d5c8243 2169
ac52caa3
MM		 2170 if (hw->mac.type >= e1000_82576) {
2171 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2172 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2173 }
b9473560 2174
01789349
JP		 2175 netdev->priv_flags |= IFF_UNICAST_FLT;
2176
330a6d6a 2177 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2178
2179 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2180 * known good starting state
2181 */
9d5c8243
AK		 2182 hw->mac.ops.reset_hw(hw);
2183
ef3a0092
CW		 2184 /* make sure the NVM is good , i211/i210 parts can have special NVM
2185 * that doesn't contain a checksum
f96a8a0b 2186 */
ef3a0092
CW		 2187 switch (hw->mac.type) {
2188 case e1000_i210:
2189 case e1000_i211:
2190 if (igb_get_flash_presence_i210(hw)) {
2191 if (hw->nvm.ops.validate(hw) < 0) {
2192 dev_err(&pdev->dev,
2193 "The NVM Checksum Is Not Valid\n");
2194 err = -EIO;
2195 goto err_eeprom;
2196 }
2197 }
2198 break;
2199 default:
f96a8a0b
CW		 2200 if (hw->nvm.ops.validate(hw) < 0) {
2201 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2202 err = -EIO;
2203 goto err_eeprom;
2204 }
ef3a0092 2205 break;
9d5c8243
AK		 2206 }
2207
2208 /* copy the MAC address out of the NVM */
2209 if (hw->mac.ops.read_mac_addr(hw))
2210 dev_err(&pdev->dev, "NVM Read Error\n");
2211
2212 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2213
aaeb6cdf 2214 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2215 dev_err(&pdev->dev, "Invalid MAC Address\n");
2216 err = -EIO;
2217 goto err_eeprom;
2218 }
2219
d67974f0
CW		 2220 /* get firmware version for ethtool -i */
2221 igb_set_fw_version(adapter);
2222
c061b18d 2223 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2224 (unsigned long) adapter);
c061b18d 2225 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2226 (unsigned long) adapter);
9d5c8243
AK		 2227
2228 INIT_WORK(&adapter->reset_task, igb_reset_task);
2229 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2230
450c87c8 2231 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2232 adapter->fc_autoneg = true;
2233 hw->mac.autoneg = true;
2234 hw->phy.autoneg_advertised = 0x2f;
2235
0cce119a
AD		 2236 hw->fc.requested_mode = e1000_fc_default;
2237 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2238
9d5c8243
AK		 2239 igb_validate_mdi_setting(hw);
2240
63d4a8f9 2241 /* By default, support wake on port A */
a2cf8b6c 2242 if (hw->bus.func == 0)
63d4a8f9
MV		 2243 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2244
2245 /* Check the NVM for wake support on non-port A ports */
2246 if (hw->mac.type >= e1000_82580)
55cac248 2247 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2248 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2249 &eeprom_data);
a2cf8b6c
AD		 2250 else if (hw->bus.func == 1)
2251 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2252
63d4a8f9
MV		 2253 if (eeprom_data & IGB_EEPROM_APME)
2254 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2255
2256 /* now that we have the eeprom settings, apply the special cases where
2257 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2258 * lan on a particular port
2259 */
9d5c8243
AK		 2260 switch (pdev->device) {
2261 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2262 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2263 break;
2264 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2265 case E1000_DEV_ID_82576_FIBER:
2266 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2267 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2268 * regardless of eeprom setting
2269 */
9d5c8243 2270 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2271 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2272 break;
c8ea5ea9 2273 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2274 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2275 /* if quad port adapter, disable WoL on all but port A */
2276 if (global_quad_port_a != 0)
63d4a8f9 2277 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2278 else
2279 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2280 /* Reset for multiple quad port adapters */
2281 if (++global_quad_port_a == 4)
2282 global_quad_port_a = 0;
2283 break;
63d4a8f9
MV		 2284 default:
2285 /* If the device can't wake, don't set software support */
2286 if (!device_can_wakeup(&adapter->pdev->dev))
2287 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2288 }
2289
2290 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2291 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2292 adapter->wol |= E1000_WUFC_MAG;
2293
2294 /* Some vendors want WoL disabled by default, but still supported */
2295 if ((hw->mac.type == e1000_i350) &&
2296 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2297 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2298 adapter->wol = 0;
2299 }
2300
2301 device_set_wakeup_enable(&adapter->pdev->dev,
2302 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2303
2304 /* reset the hardware with the new settings */
2305 igb_reset(adapter);
2306
441fc6fd
CW		 2307 /* Init the I2C interface */
2308 err = igb_init_i2c(adapter);
2309 if (err) {
2310 dev_err(&pdev->dev, "failed to init i2c interface\n");
2311 goto err_eeprom;
2312 }
2313
9d5c8243
AK		 2314 /* let the f/w know that the h/w is now under the control of the
2315 * driver. */
2316 igb_get_hw_control(adapter);
2317
9d5c8243
AK		 2318 strcpy(netdev->name, "eth%d");
2319 err = register_netdev(netdev);
2320 if (err)
2321 goto err_register;
2322
b168dfc5
JB		 2323 /* carrier off reporting is important to ethtool even BEFORE open */
2324 netif_carrier_off(netdev);
2325
421e02f0 2326#ifdef CONFIG_IGB_DCA
bbd98fe4 2327 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2328 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2329 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2330 igb_setup_dca(adapter);
2331 }
fe4506b6 2332
38c845c7 2333#endif
e428893b
CW		 2334#ifdef CONFIG_IGB_HWMON
2335 /* Initialize the thermal sensor on i350 devices. */
2336 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2337 u16 ets_word;
3c89f6d0 2338
b980ac18 2339 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2340 * external thermal sensor.
2341 */
2342 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2343 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2344 adapter->ets = true;
2345 else
2346 adapter->ets = false;
2347 if (igb_sysfs_init(adapter))
2348 dev_err(&pdev->dev,
2349 "failed to allocate sysfs resources\n");
2350 } else {
2351 adapter->ets = false;
2352 }
2353#endif
673b8b70 2354 /* do hw tstamp init after resetting */
7ebae817 2355 igb_ptp_init(adapter);
673b8b70 2356
9d5c8243 2357 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2358 /* print bus type/speed/width info, not applicable to i354 */
2359 if (hw->mac.type != e1000_i354) {
2360 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2361 netdev->name,
2362 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2363 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2364 "unknown"),
2365 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2366 "Width x4" :
2367 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2368 "Width x2" :
2369 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2370 "Width x1" : "unknown"), netdev->dev_addr);
2371 }
9d5c8243 2372
53ea6c7e
TF		 2373 if ((hw->mac.type >= e1000_i210 ||
2374 igb_get_flash_presence_i210(hw))) {
2375 ret_val = igb_read_part_string(hw, part_str,
2376 E1000_PBANUM_LENGTH);
2377 } else {
2378 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2379 }
2380
9835fd73
CW		 2381 if (ret_val)
2382 strcpy(part_str, "Unknown");
2383 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2384 dev_info(&pdev->dev,
2385 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2386 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2387 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2388 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2389 switch (hw->mac.type) {
2390 case e1000_i350:
f96a8a0b
CW		 2391 case e1000_i210:
2392 case e1000_i211:
09b068d4
CW		 2393 igb_set_eee_i350(hw);
2394 break;
ceb5f13b
CW		 2395 case e1000_i354:
2396 if (hw->phy.media_type == e1000_media_type_copper) {
2397 if ((rd32(E1000_CTRL_EXT) &
2398 E1000_CTRL_EXT_LINK_MODE_SGMII))
2399 igb_set_eee_i354(hw);
2400 }
2401 break;
09b068d4
CW		 2402 default:
2403 break;
2404 }
749ab2cd
YZ		 2405
2406 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2407 return 0;
2408
2409err_register:
2410 igb_release_hw_control(adapter);
441fc6fd 2411 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2412err_eeprom:
2413 if (!igb_check_reset_block(hw))
f5f4cf08 2414 igb_reset_phy(hw);
9d5c8243
AK		 2415
2416 if (hw->flash_address)
2417 iounmap(hw->flash_address);
9d5c8243 2418err_sw_init:
047e0030 2419 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2420 iounmap(hw->hw_addr);
2421err_ioremap:
2422 free_netdev(netdev);
2423err_alloc_etherdev:
559e9c49 2424 pci_release_selected_regions(pdev,
b980ac18 2425 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2426err_pci_reg:
2427err_dma:
2428 pci_disable_device(pdev);
2429 return err;
2430}
2431
fa44f2f1 2432#ifdef CONFIG_PCI_IOV
781798a1 2433static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2434{
2435 struct net_device *netdev = pci_get_drvdata(pdev);
2436 struct igb_adapter *adapter = netdev_priv(netdev);
2437 struct e1000_hw *hw = &adapter->hw;
2438
2439 /* reclaim resources allocated to VFs */
2440 if (adapter->vf_data) {
2441 /* disable iov and allow time for transactions to clear */
b09186d2 2442 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2443 dev_warn(&pdev->dev,
2444 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2445 return -EPERM;
2446 } else {
2447 pci_disable_sriov(pdev);
2448 msleep(500);
2449 }
2450
2451 kfree(adapter->vf_data);
2452 adapter->vf_data = NULL;
2453 adapter->vfs_allocated_count = 0;
2454 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2455 wrfl();
2456 msleep(100);
2457 dev_info(&pdev->dev, "IOV Disabled\n");
2458
2459 /* Re-enable DMA Coalescing flag since IOV is turned off */
2460 adapter->flags |= IGB_FLAG_DMAC;
2461 }
2462
2463 return 0;
2464}
2465
2466static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2467{
2468 struct net_device *netdev = pci_get_drvdata(pdev);
2469 struct igb_adapter *adapter = netdev_priv(netdev);
2470 int old_vfs = pci_num_vf(pdev);
2471 int err = 0;
2472 int i;
2473
781798a1 2474 if (!adapter->msix_entries || num_vfs > 7) {
50267196
MW		 2475 err = -EPERM;
2476 goto out;
2477 }
fa44f2f1
GR		 2478 if (!num_vfs)
2479 goto out;
fa44f2f1 2480
781798a1
SA		 2481 if (old_vfs) {
2482 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2483 old_vfs, max_vfs);
2484 adapter->vfs_allocated_count = old_vfs;
2485 } else
2486 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2487
2488 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2489 sizeof(struct vf_data_storage), GFP_KERNEL);
2490
2491 /* if allocation failed then we do not support SR-IOV */
2492 if (!adapter->vf_data) {
2493 adapter->vfs_allocated_count = 0;
2494 dev_err(&pdev->dev,
2495 "Unable to allocate memory for VF Data Storage\n");
2496 err = -ENOMEM;
2497 goto out;
2498 }
2499
781798a1
SA		 2500 /* only call pci_enable_sriov() if no VFs are allocated already */
2501 if (!old_vfs) {
2502 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2503 if (err)
2504 goto err_out;
2505 }
fa44f2f1
GR		 2506 dev_info(&pdev->dev, "%d VFs allocated\n",
2507 adapter->vfs_allocated_count);
2508 for (i = 0; i < adapter->vfs_allocated_count; i++)
2509 igb_vf_configure(adapter, i);
2510
2511 /* DMA Coalescing is not supported in IOV mode. */
2512 adapter->flags &= ~IGB_FLAG_DMAC;
2513 goto out;
2514
2515err_out:
2516 kfree(adapter->vf_data);
2517 adapter->vf_data = NULL;
2518 adapter->vfs_allocated_count = 0;
2519out:
2520 return err;
2521}
2522
2523#endif
b980ac18 2524/**
441fc6fd
CW		 2525 * igb_remove_i2c - Cleanup I2C interface
2526 * @adapter: pointer to adapter structure
b980ac18 2527 **/
441fc6fd
CW		 2528static void igb_remove_i2c(struct igb_adapter *adapter)
2529{
441fc6fd
CW		 2530 /* free the adapter bus structure */
2531 i2c_del_adapter(&adapter->i2c_adap);
2532}
2533
9d5c8243 2534/**
b980ac18
JK		 2535 * igb_remove - Device Removal Routine
2536 * @pdev: PCI device information struct
9d5c8243 2537 *
b980ac18
JK		 2538 * igb_remove is called by the PCI subsystem to alert the driver
2539 * that it should release a PCI device. The could be caused by a
2540 * Hot-Plug event, or because the driver is going to be removed from
2541 * memory.
9d5c8243 2542 **/
9f9a12f8 2543static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2544{
2545 struct net_device *netdev = pci_get_drvdata(pdev);
2546 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2547 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2548
749ab2cd 2549 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2550#ifdef CONFIG_IGB_HWMON
2551 igb_sysfs_exit(adapter);
2552#endif
441fc6fd 2553 igb_remove_i2c(adapter);
a79f4f88 2554 igb_ptp_stop(adapter);
b980ac18 2555 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2556 * disable watchdog from being rescheduled.
2557 */
9d5c8243
AK		 2558 set_bit(__IGB_DOWN, &adapter->state);
2559 del_timer_sync(&adapter->watchdog_timer);
2560 del_timer_sync(&adapter->phy_info_timer);
2561
760141a5
TH		 2562 cancel_work_sync(&adapter->reset_task);
2563 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2564
421e02f0 2565#ifdef CONFIG_IGB_DCA
7dfc16fa 2566 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2567 dev_info(&pdev->dev, "DCA disabled\n");
2568 dca_remove_requester(&pdev->dev);
7dfc16fa 2569 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2570 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2571 }
2572#endif
2573
9d5c8243 2574 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2575 * would have already happened in close and is redundant.
2576 */
9d5c8243
AK		 2577 igb_release_hw_control(adapter);
2578
2579 unregister_netdev(netdev);
2580
047e0030 2581 igb_clear_interrupt_scheme(adapter);
9d5c8243 2582
37680117 2583#ifdef CONFIG_PCI_IOV
fa44f2f1 2584 igb_disable_sriov(pdev);
37680117 2585#endif
559e9c49 2586
28b0759c
AD		 2587 iounmap(hw->hw_addr);
2588 if (hw->flash_address)
2589 iounmap(hw->flash_address);
559e9c49 2590 pci_release_selected_regions(pdev,
b980ac18 2591 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2592
1128c756 2593 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2594 free_netdev(netdev);
2595
19d5afd4 2596 pci_disable_pcie_error_reporting(pdev);
40a914fa 2597
9d5c8243
AK		 2598 pci_disable_device(pdev);
2599}
2600
a6b623e0 2601/**
b980ac18
JK		 2602 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2603 * @adapter: board private structure to initialize
a6b623e0 2604 *
b980ac18
JK		 2605 * This function initializes the vf specific data storage and then attempts to
2606 * allocate the VFs. The reason for ordering it this way is because it is much
2607 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2608 * the memory for the VFs.
a6b623e0 2609 **/
9f9a12f8 2610static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2611{
2612#ifdef CONFIG_PCI_IOV
2613 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2614 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2615
f96a8a0b
CW		 2616 /* Virtualization features not supported on i210 family. */
2617 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2618 return;
2619
fa44f2f1 2620 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2621 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2622
a6b623e0
AD		 2623#endif /* CONFIG_PCI_IOV */
2624}
2625
fa44f2f1 2626static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2627{
2628 struct e1000_hw *hw = &adapter->hw;
374a542d 2629 u32 max_rss_queues;
9d5c8243 2630
374a542d 2631 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2632 switch (hw->mac.type) {
374a542d
MV		 2633 case e1000_i211:
2634 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2635 break;
2636 case e1000_82575:
f96a8a0b 2637 case e1000_i210:
374a542d
MV		 2638 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2639 break;
2640 case e1000_i350:
2641 /* I350 cannot do RSS and SR-IOV at the same time */
2642 if (!!adapter->vfs_allocated_count) {
2643 max_rss_queues = 1;
2644 break;
2645 }
2646 /* fall through */
2647 case e1000_82576:
2648 if (!!adapter->vfs_allocated_count) {
2649 max_rss_queues = 2;
2650 break;
2651 }
2652 /* fall through */
2653 case e1000_82580:
ceb5f13b 2654 case e1000_i354:
374a542d
MV		 2655 default:
2656 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2657 break;
374a542d
MV		 2658 }
2659
2660 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2661
2662 /* Determine if we need to pair queues. */
2663 switch (hw->mac.type) {
2664 case e1000_82575:
f96a8a0b 2665 case e1000_i211:
374a542d 2666 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2667 break;
374a542d 2668 case e1000_82576:
b980ac18 2669 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2670 * should pair the queues in order to conserve interrupts due
2671 * to limited supply.
2672 */
2673 if ((adapter->rss_queues > 1) &&
2674 (adapter->vfs_allocated_count > 6))
2675 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2676 /* fall through */
2677 case e1000_82580:
2678 case e1000_i350:
ceb5f13b 2679 case e1000_i354:
374a542d 2680 case e1000_i210:
f96a8a0b 2681 default:
b980ac18 2682 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2683 * order to conserve interrupts due to limited supply.
2684 */
2685 if (adapter->rss_queues > (max_rss_queues / 2))
2686 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2687 break;
2688 }
fa44f2f1
GR		 2689}
2690
2691/**
b980ac18
JK		 2692 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2693 * @adapter: board private structure to initialize
fa44f2f1 2694 *
b980ac18
JK		 2695 * igb_sw_init initializes the Adapter private data structure.
2696 * Fields are initialized based on PCI device information and
2697 * OS network device settings (MTU size).
fa44f2f1
GR		 2698 **/
2699static int igb_sw_init(struct igb_adapter *adapter)
2700{
2701 struct e1000_hw *hw = &adapter->hw;
2702 struct net_device *netdev = adapter->netdev;
2703 struct pci_dev *pdev = adapter->pdev;
2704
2705 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2706
2707 /* set default ring sizes */
2708 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2709 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2710
2711 /* set default ITR values */
2712 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2713 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2714
2715 /* set default work limits */
2716 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2717
2718 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2719 VLAN_HLEN;
2720 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2721
2722 spin_lock_init(&adapter->stats64_lock);
2723#ifdef CONFIG_PCI_IOV
2724 switch (hw->mac.type) {
2725 case e1000_82576:
2726 case e1000_i350:
2727 if (max_vfs > 7) {
2728 dev_warn(&pdev->dev,
2729 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2730 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2731 } else
2732 adapter->vfs_allocated_count = max_vfs;
2733 if (adapter->vfs_allocated_count)
2734 dev_warn(&pdev->dev,
2735 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2736 break;
2737 default:
2738 break;
2739 }
2740#endif /* CONFIG_PCI_IOV */
2741
2742 igb_init_queue_configuration(adapter);
a99955fc 2743
1128c756 2744 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2745 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2746 GFP_ATOMIC);
1128c756 2747
a6b623e0 2748 /* This call may decrease the number of queues */
53c7d064 2749 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2750 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2751 return -ENOMEM;
2752 }
2753
a6b623e0
AD		 2754 igb_probe_vfs(adapter);
2755
9d5c8243
AK		 2756 /* Explicitly disable IRQ since the NIC can be in any state. */
2757 igb_irq_disable(adapter);
2758
f96a8a0b 2759 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2760 adapter->flags &= ~IGB_FLAG_DMAC;
2761
9d5c8243
AK		 2762 set_bit(__IGB_DOWN, &adapter->state);
2763 return 0;
2764}
2765
2766/**
b980ac18
JK		 2767 * igb_open - Called when a network interface is made active
2768 * @netdev: network interface device structure
9d5c8243 2769 *
b980ac18 2770 * Returns 0 on success, negative value on failure
9d5c8243 2771 *
b980ac18
JK		 2772 * The open entry point is called when a network interface is made
2773 * active by the system (IFF_UP). At this point all resources needed
2774 * for transmit and receive operations are allocated, the interrupt
2775 * handler is registered with the OS, the watchdog timer is started,
2776 * and the stack is notified that the interface is ready.
9d5c8243 2777 **/
749ab2cd 2778static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2779{
2780 struct igb_adapter *adapter = netdev_priv(netdev);
2781 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2782 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2783 int err;
2784 int i;
2785
2786 /* disallow open during test */
749ab2cd
YZ		 2787 if (test_bit(__IGB_TESTING, &adapter->state)) {
2788 WARN_ON(resuming);
9d5c8243 2789 return -EBUSY;
749ab2cd
YZ		 2790 }
2791
2792 if (!resuming)
2793 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2794
b168dfc5
JB		 2795 netif_carrier_off(netdev);
2796
9d5c8243
AK		 2797 /* allocate transmit descriptors */
2798 err = igb_setup_all_tx_resources(adapter);
2799 if (err)
2800 goto err_setup_tx;
2801
2802 /* allocate receive descriptors */
2803 err = igb_setup_all_rx_resources(adapter);
2804 if (err)
2805 goto err_setup_rx;
2806
88a268c1 2807 igb_power_up_link(adapter);
9d5c8243 2808
9d5c8243
AK		 2809 /* before we allocate an interrupt, we must be ready to handle it.
2810 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2811 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2812 * clean_rx handler before we do so.
2813 */
9d5c8243
AK		 2814 igb_configure(adapter);
2815
2816 err = igb_request_irq(adapter);
2817 if (err)
2818 goto err_req_irq;
2819
0c2cc02e
AD		 2820 /* Notify the stack of the actual queue counts. */
2821 err = netif_set_real_num_tx_queues(adapter->netdev,
2822 adapter->num_tx_queues);
2823 if (err)
2824 goto err_set_queues;
2825
2826 err = netif_set_real_num_rx_queues(adapter->netdev,
2827 adapter->num_rx_queues);
2828 if (err)
2829 goto err_set_queues;
2830
9d5c8243
AK		 2831 /* From here on the code is the same as igb_up() */
2832 clear_bit(__IGB_DOWN, &adapter->state);
2833
0d1ae7f4
AD		 2834 for (i = 0; i < adapter->num_q_vectors; i++)
2835 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2836
2837 /* Clear any pending interrupts. */
2838 rd32(E1000_ICR);
844290e5
PW		 2839
2840 igb_irq_enable(adapter);
2841
d4960307
AD		 2842 /* notify VFs that reset has been completed */
2843 if (adapter->vfs_allocated_count) {
2844 u32 reg_data = rd32(E1000_CTRL_EXT);
2845 reg_data |= E1000_CTRL_EXT_PFRSTD;
2846 wr32(E1000_CTRL_EXT, reg_data);
2847 }
2848
d55b53ff
JK		 2849 netif_tx_start_all_queues(netdev);
2850
749ab2cd
YZ		 2851 if (!resuming)
2852 pm_runtime_put(&pdev->dev);
2853
25568a53
AD		 2854 /* start the watchdog. */
2855 hw->mac.get_link_status = 1;
2856 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2857
2858 return 0;
2859
0c2cc02e
AD		 2860err_set_queues:
2861 igb_free_irq(adapter);
9d5c8243
AK		 2862err_req_irq:
2863 igb_release_hw_control(adapter);
88a268c1 2864 igb_power_down_link(adapter);
9d5c8243
AK		 2865 igb_free_all_rx_resources(adapter);
2866err_setup_rx:
2867 igb_free_all_tx_resources(adapter);
2868err_setup_tx:
2869 igb_reset(adapter);
749ab2cd
YZ		 2870 if (!resuming)
2871 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2872
2873 return err;
2874}
2875
749ab2cd
YZ		 2876static int igb_open(struct net_device *netdev)
2877{
2878 return __igb_open(netdev, false);
2879}
2880
9d5c8243 2881/**
b980ac18
JK		 2882 * igb_close - Disables a network interface
2883 * @netdev: network interface device structure
9d5c8243 2884 *
b980ac18 2885 * Returns 0, this is not allowed to fail
9d5c8243 2886 *
b980ac18
JK		 2887 * The close entry point is called when an interface is de-activated
2888 * by the OS. The hardware is still under the driver's control, but
2889 * needs to be disabled. A global MAC reset is issued to stop the
2890 * hardware, and all transmit and receive resources are freed.
9d5c8243 2891 **/
749ab2cd 2892static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2893{
2894 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2895 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2896
2897 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2898
749ab2cd
YZ		 2899 if (!suspending)
2900 pm_runtime_get_sync(&pdev->dev);
2901
2902 igb_down(adapter);
9d5c8243
AK		 2903 igb_free_irq(adapter);
2904
2905 igb_free_all_tx_resources(adapter);
2906 igb_free_all_rx_resources(adapter);
2907
749ab2cd
YZ		 2908 if (!suspending)
2909 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2910 return 0;
2911}
2912
749ab2cd
YZ		 2913static int igb_close(struct net_device *netdev)
2914{
2915 return __igb_close(netdev, false);
2916}
2917
9d5c8243 2918/**
b980ac18
JK		 2919 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2920 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2921 *
b980ac18 2922 * Return 0 on success, negative on failure
9d5c8243 2923 **/
80785298 2924int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2925{
59d71989 2926 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2927 int size;
2928
06034649 2929 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2930
2931 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2932 if (!tx_ring->tx_buffer_info)
9d5c8243 2933 goto err;
9d5c8243
AK		 2934
2935 /* round up to nearest 4K */
85e8d004 2936 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2937 tx_ring->size = ALIGN(tx_ring->size, 4096);
2938
5536d210
AD		 2939 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2940 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2941 if (!tx_ring->desc)
2942 goto err;
2943
9d5c8243
AK		 2944 tx_ring->next_to_use = 0;
2945 tx_ring->next_to_clean = 0;
81c2fc22 2946
9d5c8243
AK		 2947 return 0;
2948
2949err:
06034649 2950 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2951 tx_ring->tx_buffer_info = NULL;
2952 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2953 return -ENOMEM;
2954}
2955
2956/**
b980ac18
JK		 2957 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2958 * (Descriptors) for all queues
2959 * @adapter: board private structure
9d5c8243 2960 *
b980ac18 2961 * Return 0 on success, negative on failure
9d5c8243
AK		 2962 **/
2963static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2964{
439705e1 2965 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2966 int i, err = 0;
2967
2968 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2969 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2970 if (err) {
439705e1 2971 dev_err(&pdev->dev,
9d5c8243
AK		 2972 "Allocation for Tx Queue %u failed\n", i);
2973 for (i--; i >= 0; i--)
3025a446 2974 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2975 break;
2976 }
2977 }
2978
2979 return err;
2980}
2981
2982/**
b980ac18
JK		 2983 * igb_setup_tctl - configure the transmit control registers
2984 * @adapter: Board private structure
9d5c8243 2985 **/
d7ee5b3a 2986void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2987{
9d5c8243
AK		 2988 struct e1000_hw *hw = &adapter->hw;
2989 u32 tctl;
9d5c8243 2990
85b430b4
AD		 2991 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2992 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2993
2994 /* Program the Transmit Control Register */
9d5c8243
AK		 2995 tctl = rd32(E1000_TCTL);
2996 tctl &= ~E1000_TCTL_CT;
2997 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2998 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2999
3000 igb_config_collision_dist(hw);
3001
9d5c8243
AK		 3002 /* Enable transmits */
3003 tctl |= E1000_TCTL_EN;
3004
3005 wr32(E1000_TCTL, tctl);
3006}
3007
85b430b4 3008/**
b980ac18
JK		 3009 * igb_configure_tx_ring - Configure transmit ring after Reset
3010 * @adapter: board private structure
3011 * @ring: tx ring to configure
85b430b4 3012 *
b980ac18 3013 * Configure a transmit ring after a reset.
85b430b4 3014 **/
d7ee5b3a
AD		 3015void igb_configure_tx_ring(struct igb_adapter *adapter,
3016 struct igb_ring *ring)
85b430b4
AD		 3017{
3018 struct e1000_hw *hw = &adapter->hw;
a74420e0 3019 u32 txdctl = 0;
85b430b4
AD		 3020 u64 tdba = ring->dma;
3021 int reg_idx = ring->reg_idx;
3022
3023 /* disable the queue */
a74420e0 3024 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3025 wrfl();
3026 mdelay(10);
3027
3028 wr32(E1000_TDLEN(reg_idx),
b980ac18 3029 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3030 wr32(E1000_TDBAL(reg_idx),
b980ac18 3031 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3032 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3033
fce99e34 3034 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3035 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3036 writel(0, ring->tail);
85b430b4
AD		 3037
3038 txdctl |= IGB_TX_PTHRESH;
3039 txdctl |= IGB_TX_HTHRESH << 8;
3040 txdctl |= IGB_TX_WTHRESH << 16;
3041
3042 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3043 wr32(E1000_TXDCTL(reg_idx), txdctl);
3044}
3045
3046/**
b980ac18
JK		 3047 * igb_configure_tx - Configure transmit Unit after Reset
3048 * @adapter: board private structure
85b430b4 3049 *
b980ac18 3050 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3051 **/
3052static void igb_configure_tx(struct igb_adapter *adapter)
3053{
3054 int i;
3055
3056 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3057 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3058}
3059
9d5c8243 3060/**
b980ac18
JK		 3061 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3062 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3063 *
b980ac18 3064 * Returns 0 on success, negative on failure
9d5c8243 3065 **/
80785298 3066int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3067{
59d71989 3068 struct device *dev = rx_ring->dev;
f33005a6 3069 int size;
9d5c8243 3070
06034649 3071 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3072
3073 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3074 if (!rx_ring->rx_buffer_info)
9d5c8243 3075 goto err;
9d5c8243 3076
9d5c8243 3077 /* Round up to nearest 4K */
f33005a6 3078 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3079 rx_ring->size = ALIGN(rx_ring->size, 4096);
3080
5536d210
AD		 3081 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3082 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3083 if (!rx_ring->desc)
3084 goto err;
3085
cbc8e55f 3086 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3087 rx_ring->next_to_clean = 0;
3088 rx_ring->next_to_use = 0;
9d5c8243 3089
9d5c8243
AK		 3090 return 0;
3091
3092err:
06034649
AD		 3093 vfree(rx_ring->rx_buffer_info);
3094 rx_ring->rx_buffer_info = NULL;
f33005a6 3095 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3096 return -ENOMEM;
3097}
3098
3099/**
b980ac18
JK		 3100 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3101 * (Descriptors) for all queues
3102 * @adapter: board private structure
9d5c8243 3103 *
b980ac18 3104 * Return 0 on success, negative on failure
9d5c8243
AK		 3105 **/
3106static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3107{
439705e1 3108 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3109 int i, err = 0;
3110
3111 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3112 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3113 if (err) {
439705e1 3114 dev_err(&pdev->dev,
9d5c8243
AK		 3115 "Allocation for Rx Queue %u failed\n", i);
3116 for (i--; i >= 0; i--)
3025a446 3117 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3118 break;
3119 }
3120 }
3121
3122 return err;
3123}
3124
06cf2666 3125/**
b980ac18
JK		 3126 * igb_setup_mrqc - configure the multiple receive queue control registers
3127 * @adapter: Board private structure
06cf2666
AD		 3128 **/
3129static void igb_setup_mrqc(struct igb_adapter *adapter)
3130{
3131 struct e1000_hw *hw = &adapter->hw;
3132 u32 mrqc, rxcsum;
ed12cc9a 3133 u32 j, num_rx_queues;
a57fe23e
AD		 3134 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3135 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3136 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3137 0xFA01ACBE };
06cf2666
AD		 3138
3139 /* Fill out hash function seeds */
a57fe23e
AD		 3140 for (j = 0; j < 10; j++)
3141 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3142
a99955fc 3143 num_rx_queues = adapter->rss_queues;
06cf2666 3144
797fd4be 3145 switch (hw->mac.type) {
797fd4be
AD		 3146 case e1000_82576:
3147 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3148 if (adapter->vfs_allocated_count)
06cf2666 3149 num_rx_queues = 2;
797fd4be
AD		 3150 break;
3151 default:
3152 break;
06cf2666
AD		 3153 }
3154
ed12cc9a
LMV		 3155 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3156 for (j = 0; j < IGB_RETA_SIZE; j++)
3157 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3158 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3159 }
ed12cc9a 3160 igb_write_rss_indir_tbl(adapter);
06cf2666 3161
b980ac18 3162 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3163 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3164 * offloads as they are enabled by default
3165 */
3166 rxcsum = rd32(E1000_RXCSUM);
3167 rxcsum |= E1000_RXCSUM_PCSD;
3168
3169 if (adapter->hw.mac.type >= e1000_82576)
3170 /* Enable Receive Checksum Offload for SCTP */
3171 rxcsum |= E1000_RXCSUM_CRCOFL;
3172
3173 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3174 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3175
039454a8
AA		 3176 /* Generate RSS hash based on packet types, TCP/UDP
3177 * port numbers and/or IPv4/v6 src and dst addresses
3178 */
f96a8a0b
CW		 3179 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3180 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3181 E1000_MRQC_RSS_FIELD_IPV6 |
3182 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3183 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3184
039454a8
AA		 3185 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3186 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3187 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3188 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3189
06cf2666
AD		 3190 /* If VMDq is enabled then we set the appropriate mode for that, else
3191 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3192 * if we are only using one queue
3193 */
06cf2666
AD		 3194 if (adapter->vfs_allocated_count) {
3195 if (hw->mac.type > e1000_82575) {
3196 /* Set the default pool for the PF's first queue */
3197 u32 vtctl = rd32(E1000_VT_CTL);
3198 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3199 E1000_VT_CTL_DISABLE_DEF_POOL);
3200 vtctl |= adapter->vfs_allocated_count <<
3201 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3202 wr32(E1000_VT_CTL, vtctl);
3203 }
a99955fc 3204 if (adapter->rss_queues > 1)
f96a8a0b 3205 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3206 else
f96a8a0b 3207 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3208 } else {
f96a8a0b
CW		 3209 if (hw->mac.type != e1000_i211)
3210 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3211 }
3212 igb_vmm_control(adapter);
3213
06cf2666
AD		 3214 wr32(E1000_MRQC, mrqc);
3215}
3216
9d5c8243 3217/**
b980ac18
JK		 3218 * igb_setup_rctl - configure the receive control registers
3219 * @adapter: Board private structure
9d5c8243 3220 **/
d7ee5b3a 3221void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3222{
3223 struct e1000_hw *hw = &adapter->hw;
3224 u32 rctl;
9d5c8243
AK		 3225
3226 rctl = rd32(E1000_RCTL);
3227
3228 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3229 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3230
69d728ba 3231 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3232 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3233
b980ac18 3234 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3235 * redirection as it did with e1000. Newer features require
3236 * that the HW strips the CRC.
73cd78f1 3237 */
87cb7e8c 3238 rctl |= E1000_RCTL_SECRC;
9d5c8243 3239
559e9c49 3240 /* disable store bad packets and clear size bits. */
ec54d7d6 3241 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3242
6ec43fe6
AD		 3243 /* enable LPE to prevent packets larger than max_frame_size */
3244 rctl |= E1000_RCTL_LPE;
9d5c8243 3245
952f72a8
AD		 3246 /* disable queue 0 to prevent tail write w/o re-config */
3247 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3248
e1739522
AD		 3249 /* Attention!!! For SR-IOV PF driver operations you must enable
3250 * queue drop for all VF and PF queues to prevent head of line blocking
3251 * if an un-trusted VF does not provide descriptors to hardware.
3252 */
3253 if (adapter->vfs_allocated_count) {
e1739522
AD		 3254 /* set all queue drop enable bits */
3255 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3256 }
3257
89eaefb6
BG		 3258 /* This is useful for sniffing bad packets. */
3259 if (adapter->netdev->features & NETIF_F_RXALL) {
3260 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3261 * in e1000e_set_rx_mode
3262 */
89eaefb6
BG		 3263 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3264 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3265 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3266
3267 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3268 E1000_RCTL_DPF | /* Allow filtered pause */
3269 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3270 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3271 * and that breaks VLANs.
3272 */
3273 }
3274
9d5c8243
AK		 3275 wr32(E1000_RCTL, rctl);
3276}
3277
7d5753f0
AD		 3278static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3279 int vfn)
3280{
3281 struct e1000_hw *hw = &adapter->hw;
3282 u32 vmolr;
3283
3284 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3285 * increase the size to support vlan tags
3286 */
7d5753f0
AD		 3287 if (vfn < adapter->vfs_allocated_count &&
3288 adapter->vf_data[vfn].vlans_enabled)
3289 size += VLAN_TAG_SIZE;
3290
3291 vmolr = rd32(E1000_VMOLR(vfn));
3292 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3293 vmolr |= size | E1000_VMOLR_LPE;
3294 wr32(E1000_VMOLR(vfn), vmolr);
3295
3296 return 0;
3297}
3298
e1739522 3299/**
b980ac18
JK		 3300 * igb_rlpml_set - set maximum receive packet size
3301 * @adapter: board private structure
e1739522 3302 *
b980ac18 3303 * Configure maximum receivable packet size.
e1739522
AD		 3304 **/
3305static void igb_rlpml_set(struct igb_adapter *adapter)
3306{
153285f9 3307 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3308 struct e1000_hw *hw = &adapter->hw;
3309 u16 pf_id = adapter->vfs_allocated_count;
3310
e1739522
AD		 3311 if (pf_id) {
3312 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3313 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3314 * to our max jumbo frame size, in case we need to enable
3315 * jumbo frames on one of the rings later.
3316 * This will not pass over-length frames into the default
3317 * queue because it's gated by the VMOLR.RLPML.
3318 */
7d5753f0 3319 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3320 }
3321
3322 wr32(E1000_RLPML, max_frame_size);
3323}
3324
8151d294
WM		 3325static inline void igb_set_vmolr(struct igb_adapter *adapter,
3326 int vfn, bool aupe)
7d5753f0
AD		 3327{
3328 struct e1000_hw *hw = &adapter->hw;
3329 u32 vmolr;
3330
b980ac18 3331 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3332 * we should exit and do nothing
3333 */
3334 if (hw->mac.type < e1000_82576)
3335 return;
3336
3337 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3338 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3339 if (aupe)
b980ac18 3340 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3341 else
3342 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3343
3344 /* clear all bits that might not be set */
3345 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3346
a99955fc 3347 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3348 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3349 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3350 * multicast packets
3351 */
3352 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3353 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3354
3355 wr32(E1000_VMOLR(vfn), vmolr);
3356}
3357
85b430b4 3358/**
b980ac18
JK		 3359 * igb_configure_rx_ring - Configure a receive ring after Reset
3360 * @adapter: board private structure
3361 * @ring: receive ring to be configured
85b430b4 3362 *
b980ac18 3363 * Configure the Rx unit of the MAC after a reset.
85b430b4 3364 **/
d7ee5b3a 3365void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3366 struct igb_ring *ring)
85b430b4
AD		 3367{
3368 struct e1000_hw *hw = &adapter->hw;
3369 u64 rdba = ring->dma;
3370 int reg_idx = ring->reg_idx;
a74420e0 3371 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3372
3373 /* disable the queue */
a74420e0 3374 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3375
3376 /* Set DMA base address registers */
3377 wr32(E1000_RDBAL(reg_idx),
3378 rdba & 0x00000000ffffffffULL);
3379 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3380 wr32(E1000_RDLEN(reg_idx),
b980ac18 3381 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3382
3383 /* initialize head and tail */
fce99e34 3384 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3385 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3386 writel(0, ring->tail);
85b430b4 3387
952f72a8 3388 /* set descriptor configuration */
44390ca6 3389 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3390 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3391 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3392 if (hw->mac.type >= e1000_82580)
757b77e2 3393 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3394 /* Only set Drop Enable if we are supporting multiple queues */
3395 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3396 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3397
3398 wr32(E1000_SRRCTL(reg_idx), srrctl);
3399
7d5753f0 3400 /* set filtering for VMDQ pools */
8151d294 3401 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3402
85b430b4
AD		 3403 rxdctl |= IGB_RX_PTHRESH;
3404 rxdctl |= IGB_RX_HTHRESH << 8;
3405 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3406
3407 /* enable receive descriptor fetching */
3408 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3409 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3410}
3411
9d5c8243 3412/**
b980ac18
JK		 3413 * igb_configure_rx - Configure receive Unit after Reset
3414 * @adapter: board private structure
9d5c8243 3415 *
b980ac18 3416 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3417 **/
3418static void igb_configure_rx(struct igb_adapter *adapter)
3419{
9107584e 3420 int i;
9d5c8243 3421
68d480c4
AD		 3422 /* set UTA to appropriate mode */
3423 igb_set_uta(adapter);
3424
26ad9178
AD		 3425 /* set the correct pool for the PF default MAC address in entry 0 */
3426 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3427 adapter->vfs_allocated_count);
26ad9178 3428
06cf2666 3429 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3430 * the Base and Length of the Rx Descriptor Ring
3431 */
f9d40f6a
AD		 3432 for (i = 0; i < adapter->num_rx_queues; i++)
3433 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3434}
3435
3436/**
b980ac18
JK		 3437 * igb_free_tx_resources - Free Tx Resources per Queue
3438 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3439 *
b980ac18 3440 * Free all transmit software resources
9d5c8243 3441 **/
68fd9910 3442void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3443{
3b644cf6 3444 igb_clean_tx_ring(tx_ring);
9d5c8243 3445
06034649
AD		 3446 vfree(tx_ring->tx_buffer_info);
3447 tx_ring->tx_buffer_info = NULL;
9d5c8243 3448
439705e1
AD		 3449 /* if not set, then don't free */
3450 if (!tx_ring->desc)
3451 return;
3452
59d71989
AD		 3453 dma_free_coherent(tx_ring->dev, tx_ring->size,
3454 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3455
3456 tx_ring->desc = NULL;
3457}
3458
3459/**
b980ac18
JK		 3460 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3461 * @adapter: board private structure
9d5c8243 3462 *
b980ac18 3463 * Free all transmit software resources
9d5c8243
AK		 3464 **/
3465static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3466{
3467 int i;
3468
3469 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3470 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3471}
3472
ebe42d16
AD		 3473void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3474 struct igb_tx_buffer *tx_buffer)
3475{
3476 if (tx_buffer->skb) {
3477 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3478 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3479 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3480 dma_unmap_addr(tx_buffer, dma),
3481 dma_unmap_len(tx_buffer, len),
ebe42d16 3482 DMA_TO_DEVICE);
c9f14bf3 3483 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3484 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3485 dma_unmap_addr(tx_buffer, dma),
3486 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3487 DMA_TO_DEVICE);
3488 }
3489 tx_buffer->next_to_watch = NULL;
3490 tx_buffer->skb = NULL;
c9f14bf3 3491 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3492 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3493}
3494
3495/**
b980ac18
JK		 3496 * igb_clean_tx_ring - Free Tx Buffers
3497 * @tx_ring: ring to be cleaned
9d5c8243 3498 **/
3b644cf6 3499static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3500{
06034649 3501 struct igb_tx_buffer *buffer_info;
9d5c8243 3502 unsigned long size;
6ad4edfc 3503 u16 i;
9d5c8243 3504
06034649 3505 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3506 return;
3507 /* Free all the Tx ring sk_buffs */
3508
3509 for (i = 0; i < tx_ring->count; i++) {
06034649 3510 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3511 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3512 }
3513
dad8a3b3
JF		 3514 netdev_tx_reset_queue(txring_txq(tx_ring));
3515
06034649
AD		 3516 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3517 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3518
3519 /* Zero out the descriptor ring */
9d5c8243
AK		 3520 memset(tx_ring->desc, 0, tx_ring->size);
3521
3522 tx_ring->next_to_use = 0;
3523 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3524}
3525
3526/**
b980ac18
JK		 3527 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3528 * @adapter: board private structure
9d5c8243
AK		 3529 **/
3530static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3531{
3532 int i;
3533
3534 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3535 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3536}
3537
3538/**
b980ac18
JK		 3539 * igb_free_rx_resources - Free Rx Resources
3540 * @rx_ring: ring to clean the resources from
9d5c8243 3541 *
b980ac18 3542 * Free all receive software resources
9d5c8243 3543 **/
68fd9910 3544void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3545{
3b644cf6 3546 igb_clean_rx_ring(rx_ring);
9d5c8243 3547
06034649
AD		 3548 vfree(rx_ring->rx_buffer_info);
3549 rx_ring->rx_buffer_info = NULL;
9d5c8243 3550
439705e1
AD		 3551 /* if not set, then don't free */
3552 if (!rx_ring->desc)
3553 return;
3554
59d71989
AD		 3555 dma_free_coherent(rx_ring->dev, rx_ring->size,
3556 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3557
3558 rx_ring->desc = NULL;
3559}
3560
3561/**
b980ac18
JK		 3562 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3563 * @adapter: board private structure
9d5c8243 3564 *
b980ac18 3565 * Free all receive software resources
9d5c8243
AK		 3566 **/
3567static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3568{
3569 int i;
3570
3571 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3572 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3573}
3574
3575/**
b980ac18
JK		 3576 * igb_clean_rx_ring - Free Rx Buffers per Queue
3577 * @rx_ring: ring to free buffers from
9d5c8243 3578 **/
3b644cf6 3579static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3580{
9d5c8243 3581 unsigned long size;
c023cd88 3582 u16 i;
9d5c8243 3583
1a1c225b
AD		 3584 if (rx_ring->skb)
3585 dev_kfree_skb(rx_ring->skb);
3586 rx_ring->skb = NULL;
3587
06034649 3588 if (!rx_ring->rx_buffer_info)
9d5c8243 3589 return;
439705e1 3590
9d5c8243
AK		 3591 /* Free all the Rx ring sk_buffs */
3592 for (i = 0; i < rx_ring->count; i++) {
06034649 3593 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3594
cbc8e55f
AD		 3595 if (!buffer_info->page)
3596 continue;
3597
3598 dma_unmap_page(rx_ring->dev,
3599 buffer_info->dma,
3600 PAGE_SIZE,
3601 DMA_FROM_DEVICE);
3602 __free_page(buffer_info->page);
3603
1a1c225b 3604 buffer_info->page = NULL;
9d5c8243
AK		 3605 }
3606
06034649
AD		 3607 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3608 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3609
3610 /* Zero out the descriptor ring */
3611 memset(rx_ring->desc, 0, rx_ring->size);
3612
cbc8e55f 3613 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3614 rx_ring->next_to_clean = 0;
3615 rx_ring->next_to_use = 0;
9d5c8243
AK		 3616}
3617
3618/**
b980ac18
JK		 3619 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3620 * @adapter: board private structure
9d5c8243
AK		 3621 **/
3622static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3623{
3624 int i;
3625
3626 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3627 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3628}
3629
3630/**
b980ac18
JK		 3631 * igb_set_mac - Change the Ethernet Address of the NIC
3632 * @netdev: network interface device structure
3633 * @p: pointer to an address structure
9d5c8243 3634 *
b980ac18 3635 * Returns 0 on success, negative on failure
9d5c8243
AK		 3636 **/
3637static int igb_set_mac(struct net_device *netdev, void *p)
3638{
3639 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3640 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3641 struct sockaddr *addr = p;
3642
3643 if (!is_valid_ether_addr(addr->sa_data))
3644 return -EADDRNOTAVAIL;
3645
3646 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3647 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3648
26ad9178
AD		 3649 /* set the correct pool for the new PF MAC address in entry 0 */
3650 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3651 adapter->vfs_allocated_count);
e1739522 3652
9d5c8243
AK		 3653 return 0;
3654}
3655
3656/**
b980ac18
JK		 3657 * igb_write_mc_addr_list - write multicast addresses to MTA
3658 * @netdev: network interface device structure
9d5c8243 3659 *
b980ac18
JK		 3660 * Writes multicast address list to the MTA hash table.
3661 * Returns: -ENOMEM on failure
3662 * 0 on no addresses written
3663 * X on writing X addresses to MTA
9d5c8243 3664 **/
68d480c4 3665static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3666{
3667 struct igb_adapter *adapter = netdev_priv(netdev);
3668 struct e1000_hw *hw = &adapter->hw;
22bedad3 3669 struct netdev_hw_addr *ha;
68d480c4 3670 u8 *mta_list;
9d5c8243
AK		 3671 int i;
3672
4cd24eaf 3673 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3674 /* nothing to program, so clear mc list */
3675 igb_update_mc_addr_list(hw, NULL, 0);
3676 igb_restore_vf_multicasts(adapter);
3677 return 0;
3678 }
9d5c8243 3679
4cd24eaf 3680 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3681 if (!mta_list)
3682 return -ENOMEM;
ff41f8dc 3683
68d480c4 3684 /* The shared function expects a packed array of only addresses. */
48e2f183 3685 i = 0;
22bedad3
JP		 3686 netdev_for_each_mc_addr(ha, netdev)
3687 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3688
68d480c4
AD		 3689 igb_update_mc_addr_list(hw, mta_list, i);
3690 kfree(mta_list);
3691
4cd24eaf 3692 return netdev_mc_count(netdev);
68d480c4
AD		 3693}
3694
3695/**
b980ac18
JK		 3696 * igb_write_uc_addr_list - write unicast addresses to RAR table
3697 * @netdev: network interface device structure
68d480c4 3698 *
b980ac18
JK		 3699 * Writes unicast address list to the RAR table.
3700 * Returns: -ENOMEM on failure/insufficient address space
3701 * 0 on no addresses written
3702 * X on writing X addresses to the RAR table
68d480c4
AD		 3703 **/
3704static int igb_write_uc_addr_list(struct net_device *netdev)
3705{
3706 struct igb_adapter *adapter = netdev_priv(netdev);
3707 struct e1000_hw *hw = &adapter->hw;
3708 unsigned int vfn = adapter->vfs_allocated_count;
3709 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3710 int count = 0;
3711
3712 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3713 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3714 return -ENOMEM;
9d5c8243 3715
32e7bfc4 3716 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3717 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3718
3719 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3720 if (!rar_entries)
3721 break;
26ad9178 3722 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3723 rar_entries--,
3724 vfn);
68d480c4 3725 count++;
ff41f8dc
AD		 3726 }
3727 }
3728 /* write the addresses in reverse order to avoid write combining */
3729 for (; rar_entries > 0 ; rar_entries--) {
3730 wr32(E1000_RAH(rar_entries), 0);
3731 wr32(E1000_RAL(rar_entries), 0);
3732 }
3733 wrfl();
3734
68d480c4
AD		 3735 return count;
3736}
3737
3738/**
b980ac18
JK		 3739 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3740 * @netdev: network interface device structure
68d480c4 3741 *
b980ac18
JK		 3742 * The set_rx_mode entry point is called whenever the unicast or multicast
3743 * address lists or the network interface flags are updated. This routine is
3744 * responsible for configuring the hardware for proper unicast, multicast,
3745 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3746 **/
3747static void igb_set_rx_mode(struct net_device *netdev)
3748{
3749 struct igb_adapter *adapter = netdev_priv(netdev);
3750 struct e1000_hw *hw = &adapter->hw;
3751 unsigned int vfn = adapter->vfs_allocated_count;
3752 u32 rctl, vmolr = 0;
3753 int count;
3754
3755 /* Check for Promiscuous and All Multicast modes */
3756 rctl = rd32(E1000_RCTL);
3757
3758 /* clear the effected bits */
3759 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3760
3761 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3762 /* retain VLAN HW filtering if in VT mode */
7e44892c 3763 if (adapter->vfs_allocated_count)
6f3dc319 3764 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3765 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3766 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3767 } else {
3768 if (netdev->flags & IFF_ALLMULTI) {
3769 rctl |= E1000_RCTL_MPE;
3770 vmolr |= E1000_VMOLR_MPME;
3771 } else {
b980ac18 3772 /* Write addresses to the MTA, if the attempt fails
25985edc 3773 * then we should just turn on promiscuous mode so
68d480c4
AD		 3774 * that we can at least receive multicast traffic
3775 */
3776 count = igb_write_mc_addr_list(netdev);
3777 if (count < 0) {
3778 rctl |= E1000_RCTL_MPE;
3779 vmolr |= E1000_VMOLR_MPME;
3780 } else if (count) {
3781 vmolr |= E1000_VMOLR_ROMPE;
3782 }
3783 }
b980ac18 3784 /* Write addresses to available RAR registers, if there is not
68d480c4 3785 * sufficient space to store all the addresses then enable
25985edc 3786 * unicast promiscuous mode
68d480c4
AD		 3787 */
3788 count = igb_write_uc_addr_list(netdev);
3789 if (count < 0) {
3790 rctl |= E1000_RCTL_UPE;
3791 vmolr |= E1000_VMOLR_ROPE;
3792 }
3793 rctl |= E1000_RCTL_VFE;
28fc06f5 3794 }
68d480c4 3795 wr32(E1000_RCTL, rctl);
28fc06f5 3796
b980ac18 3797 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3798 * the VMOLR to enable the appropriate modes. Without this workaround
3799 * we will have issues with VLAN tag stripping not being done for frames
3800 * that are only arriving because we are the default pool
3801 */
f96a8a0b 3802 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3803 return;
9d5c8243 3804
68d480c4 3805 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3806 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3807 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3808 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3809}
3810
13800469
GR		 3811static void igb_check_wvbr(struct igb_adapter *adapter)
3812{
3813 struct e1000_hw *hw = &adapter->hw;
3814 u32 wvbr = 0;
3815
3816 switch (hw->mac.type) {
3817 case e1000_82576:
3818 case e1000_i350:
3819 if (!(wvbr = rd32(E1000_WVBR)))
3820 return;
3821 break;
3822 default:
3823 break;
3824 }
3825
3826 adapter->wvbr |= wvbr;
3827}
3828
3829#define IGB_STAGGERED_QUEUE_OFFSET 8
3830
3831static void igb_spoof_check(struct igb_adapter *adapter)
3832{
3833 int j;
3834
3835 if (!adapter->wvbr)
3836 return;
3837
3838 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3839 if (adapter->wvbr & (1 << j) ||
3840 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3841 dev_warn(&adapter->pdev->dev,
3842 "Spoof event(s) detected on VF %d\n", j);
3843 adapter->wvbr &=
3844 ~((1 << j) |
3845 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3846 }
3847 }
3848}
3849
9d5c8243 3850/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3851 * the phy
3852 */
9d5c8243
AK		 3853static void igb_update_phy_info(unsigned long data)
3854{
3855 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3856 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3857}
3858
4d6b725e 3859/**
b980ac18
JK		 3860 * igb_has_link - check shared code for link and determine up/down
3861 * @adapter: pointer to driver private info
4d6b725e 3862 **/
3145535a 3863bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3864{
3865 struct e1000_hw *hw = &adapter->hw;
3866 bool link_active = false;
4d6b725e
AD		 3867
3868 /* get_link_status is set on LSC (link status) interrupt or
3869 * rx sequence error interrupt. get_link_status will stay
3870 * false until the e1000_check_for_link establishes link
3871 * for copper adapters ONLY
3872 */
3873 switch (hw->phy.media_type) {
3874 case e1000_media_type_copper:
e5c3370f
AA		 3875 if (!hw->mac.get_link_status)
3876 return true;
4d6b725e 3877 case e1000_media_type_internal_serdes:
e5c3370f
AA		 3878 hw->mac.ops.check_for_link(hw);
3879 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 3880 break;
3881 default:
3882 case e1000_media_type_unknown:
3883 break;
3884 }
3885
aa9b8cc4
AA		 3886 if (((hw->mac.type == e1000_i210) ||
3887 (hw->mac.type == e1000_i211)) &&
3888 (hw->phy.id == I210_I_PHY_ID)) {
3889 if (!netif_carrier_ok(adapter->netdev)) {
3890 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3891 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
3892 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
3893 adapter->link_check_timeout = jiffies;
3894 }
3895 }
3896
4d6b725e
AD		 3897 return link_active;
3898}
3899
563988dc
SA		 3900static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3901{
3902 bool ret = false;
3903 u32 ctrl_ext, thstat;
3904
f96a8a0b 3905 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3906 if (hw->mac.type == e1000_i350) {
3907 thstat = rd32(E1000_THSTAT);
3908 ctrl_ext = rd32(E1000_CTRL_EXT);
3909
3910 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3911 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3912 ret = !!(thstat & event);
563988dc
SA		 3913 }
3914
3915 return ret;
3916}
3917
9d5c8243 3918/**
b980ac18
JK		 3919 * igb_watchdog - Timer Call-back
3920 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3921 **/
3922static void igb_watchdog(unsigned long data)
3923{
3924 struct igb_adapter *adapter = (struct igb_adapter *)data;
3925 /* Do the rest outside of interrupt context */
3926 schedule_work(&adapter->watchdog_task);
3927}
3928
3929static void igb_watchdog_task(struct work_struct *work)
3930{
3931 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3932 struct igb_adapter,
3933 watchdog_task);
9d5c8243 3934 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3935 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3936 struct net_device *netdev = adapter->netdev;
563988dc 3937 u32 link;
7a6ea550 3938 int i;
9d5c8243 3939
4d6b725e 3940 link = igb_has_link(adapter);
aa9b8cc4
AA		 3941
3942 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
3943 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
3944 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3945 else
3946 link = false;
3947 }
3948
9d5c8243 3949 if (link) {
749ab2cd
YZ		 3950 /* Cancel scheduled suspend requests. */
3951 pm_runtime_resume(netdev->dev.parent);
3952
9d5c8243
AK		 3953 if (!netif_carrier_ok(netdev)) {
3954 u32 ctrl;
330a6d6a 3955 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3956 &adapter->link_speed,
3957 &adapter->link_duplex);
9d5c8243
AK		 3958
3959 ctrl = rd32(E1000_CTRL);
527d47c1 3960 /* Links status message must follow this format */
876d2d6f
JK		 3961 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3962 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3963 netdev->name,
3964 adapter->link_speed,
3965 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3966 "Full" : "Half",
3967 (ctrl & E1000_CTRL_TFCE) &&
3968 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3969 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3970 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3971
c0ba4778
KS		 3972 /* check if SmartSpeed worked */
3973 igb_check_downshift(hw);
3974 if (phy->speed_downgraded)
3975 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3976
563988dc 3977 /* check for thermal sensor event */
876d2d6f
JK		 3978 if (igb_thermal_sensor_event(hw,
3979 E1000_THSTAT_LINK_THROTTLE)) {
3980 netdev_info(netdev, "The network adapter link "
3981 "speed was downshifted because it "
3982 "overheated\n");
7ef5ed1c 3983 }
563988dc 3984
d07f3e37 3985 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3986 adapter->tx_timeout_factor = 1;
3987 switch (adapter->link_speed) {
3988 case SPEED_10:
9d5c8243
AK		 3989 adapter->tx_timeout_factor = 14;
3990 break;
3991 case SPEED_100:
9d5c8243
AK		 3992 /* maybe add some timeout factor ? */
3993 break;
3994 }
3995
3996 netif_carrier_on(netdev);
9d5c8243 3997
4ae196df 3998 igb_ping_all_vfs(adapter);
17dc566c 3999 igb_check_vf_rate_limit(adapter);
4ae196df 4000
4b1a9877 4001 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4002 if (!test_bit(__IGB_DOWN, &adapter->state))
4003 mod_timer(&adapter->phy_info_timer,
4004 round_jiffies(jiffies + 2 * HZ));
4005 }
4006 } else {
4007 if (netif_carrier_ok(netdev)) {
4008 adapter->link_speed = 0;
4009 adapter->link_duplex = 0;
563988dc
SA		 4010
4011 /* check for thermal sensor event */
876d2d6f
JK		 4012 if (igb_thermal_sensor_event(hw,
4013 E1000_THSTAT_PWR_DOWN)) {
4014 netdev_err(netdev, "The network adapter was "
4015 "stopped because it overheated\n");
7ef5ed1c 4016 }
563988dc 4017
527d47c1
AD		 4018 /* Links status message must follow this format */
4019 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4020 netdev->name);
9d5c8243 4021 netif_carrier_off(netdev);
4b1a9877 4022
4ae196df
AD		 4023 igb_ping_all_vfs(adapter);
4024
4b1a9877 4025 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4026 if (!test_bit(__IGB_DOWN, &adapter->state))
4027 mod_timer(&adapter->phy_info_timer,
4028 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 4029
4030 pm_schedule_suspend(netdev->dev.parent,
4031 MSEC_PER_SEC * 5);
9d5c8243
AK		 4032 }
4033 }
4034
12dcd86b
ED		 4035 spin_lock(&adapter->stats64_lock);
4036 igb_update_stats(adapter, &adapter->stats64);
4037 spin_unlock(&adapter->stats64_lock);
9d5c8243 4038
dbabb065 4039 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4040 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4041 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4042 /* We've lost link, so the controller stops DMA,
4043 * but we've got queued Tx work that's never going
4044 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4045 * (Do the reset outside of interrupt context).
4046 */
dbabb065
AD		 4047 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4048 adapter->tx_timeout_count++;
4049 schedule_work(&adapter->reset_task);
4050 /* return immediately since reset is imminent */
4051 return;
4052 }
9d5c8243 4053 }
9d5c8243 4054
dbabb065 4055 /* Force detection of hung controller every watchdog period */
6d095fa8 4056 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4057 }
f7ba205e 4058
b980ac18 4059 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4060 if (adapter->msix_entries) {
047e0030 4061 u32 eics = 0;
0d1ae7f4
AD		 4062 for (i = 0; i < adapter->num_q_vectors; i++)
4063 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4064 wr32(E1000_EICS, eics);
4065 } else {
4066 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4067 }
9d5c8243 4068
13800469 4069 igb_spoof_check(adapter);
fc580751 4070 igb_ptp_rx_hang(adapter);
13800469 4071
9d5c8243 4072 /* Reset the timer */
aa9b8cc4
AA		 4073 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4074 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4075 mod_timer(&adapter->watchdog_timer,
4076 round_jiffies(jiffies + HZ));
4077 else
4078 mod_timer(&adapter->watchdog_timer,
4079 round_jiffies(jiffies + 2 * HZ));
4080 }
9d5c8243
AK		 4081}
4082
4083enum latency_range {
4084 lowest_latency = 0,
4085 low_latency = 1,
4086 bulk_latency = 2,
4087 latency_invalid = 255
4088};
4089
6eb5a7f1 4090/**
b980ac18
JK		 4091 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4092 * @q_vector: pointer to q_vector
6eb5a7f1 4093 *
b980ac18
JK		 4094 * Stores a new ITR value based on strictly on packet size. This
4095 * algorithm is less sophisticated than that used in igb_update_itr,
4096 * due to the difficulty of synchronizing statistics across multiple
4097 * receive rings. The divisors and thresholds used by this function
4098 * were determined based on theoretical maximum wire speed and testing
4099 * data, in order to minimize response time while increasing bulk
4100 * throughput.
4101 * This functionality is controlled by the InterruptThrottleRate module
4102 * parameter (see igb_param.c)
4103 * NOTE: This function is called only when operating in a multiqueue
4104 * receive environment.
6eb5a7f1 4105 **/
047e0030 4106static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4107{
047e0030 4108 int new_val = q_vector->itr_val;
6eb5a7f1 4109 int avg_wire_size = 0;
047e0030 4110 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4111 unsigned int packets;
9d5c8243 4112
6eb5a7f1
AD		 4113 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4114 * ints/sec - ITR timer value of 120 ticks.
4115 */
4116 if (adapter->link_speed != SPEED_1000) {
0ba82994 4117 new_val = IGB_4K_ITR;
6eb5a7f1 4118 goto set_itr_val;
9d5c8243 4119 }
047e0030 4120
0ba82994
AD		 4121 packets = q_vector->rx.total_packets;
4122 if (packets)
4123 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4124
0ba82994
AD		 4125 packets = q_vector->tx.total_packets;
4126 if (packets)
4127 avg_wire_size = max_t(u32, avg_wire_size,
4128 q_vector->tx.total_bytes / packets);
047e0030
AD		 4129
4130 /* if avg_wire_size isn't set no work was done */
4131 if (!avg_wire_size)
4132 goto clear_counts;
9d5c8243 4133
6eb5a7f1
AD		 4134 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4135 avg_wire_size += 24;
4136
4137 /* Don't starve jumbo frames */
4138 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4139
6eb5a7f1
AD		 4140 /* Give a little boost to mid-size frames */
4141 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4142 new_val = avg_wire_size / 3;
4143 else
4144 new_val = avg_wire_size / 2;
9d5c8243 4145
0ba82994
AD		 4146 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4147 if (new_val < IGB_20K_ITR &&
4148 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4149 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4150 new_val = IGB_20K_ITR;
abe1c363 4151
6eb5a7f1 4152set_itr_val:
047e0030
AD		 4153 if (new_val != q_vector->itr_val) {
4154 q_vector->itr_val = new_val;
4155 q_vector->set_itr = 1;
9d5c8243 4156 }
6eb5a7f1 4157clear_counts:
0ba82994
AD		 4158 q_vector->rx.total_bytes = 0;
4159 q_vector->rx.total_packets = 0;
4160 q_vector->tx.total_bytes = 0;
4161 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4162}
4163
4164/**
b980ac18
JK		 4165 * igb_update_itr - update the dynamic ITR value based on statistics
4166 * @q_vector: pointer to q_vector
4167 * @ring_container: ring info to update the itr for
4168 *
4169 * Stores a new ITR value based on packets and byte
4170 * counts during the last interrupt. The advantage of per interrupt
4171 * computation is faster updates and more accurate ITR for the current
4172 * traffic pattern. Constants in this function were computed
4173 * based on theoretical maximum wire speed and thresholds were set based
4174 * on testing data as well as attempting to minimize response time
4175 * while increasing bulk throughput.
4176 * this functionality is controlled by the InterruptThrottleRate module
4177 * parameter (see igb_param.c)
4178 * NOTE: These calculations are only valid when operating in a single-
4179 * queue environment.
9d5c8243 4180 **/
0ba82994
AD		 4181static void igb_update_itr(struct igb_q_vector *q_vector,
4182 struct igb_ring_container *ring_container)
9d5c8243 4183{
0ba82994
AD		 4184 unsigned int packets = ring_container->total_packets;
4185 unsigned int bytes = ring_container->total_bytes;
4186 u8 itrval = ring_container->itr;
9d5c8243 4187
0ba82994 4188 /* no packets, exit with status unchanged */
9d5c8243 4189 if (packets == 0)
0ba82994 4190 return;
9d5c8243 4191
0ba82994 4192 switch (itrval) {
9d5c8243
AK		 4193 case lowest_latency:
4194 /* handle TSO and jumbo frames */
4195 if (bytes/packets > 8000)
0ba82994 4196 itrval = bulk_latency;
9d5c8243 4197 else if ((packets < 5) && (bytes > 512))
0ba82994 4198 itrval = low_latency;
9d5c8243
AK		 4199 break;
4200 case low_latency: /* 50 usec aka 20000 ints/s */
4201 if (bytes > 10000) {
4202 /* this if handles the TSO accounting */
4203 if (bytes/packets > 8000) {
0ba82994 4204 itrval = bulk_latency;
9d5c8243 4205 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4206 itrval = bulk_latency;
9d5c8243 4207 } else if ((packets > 35)) {
0ba82994 4208 itrval = lowest_latency;
9d5c8243
AK		 4209 }
4210 } else if (bytes/packets > 2000) {
0ba82994 4211 itrval = bulk_latency;
9d5c8243 4212 } else if (packets <= 2 && bytes < 512) {
0ba82994 4213 itrval = lowest_latency;
9d5c8243
AK		 4214 }
4215 break;
4216 case bulk_latency: /* 250 usec aka 4000 ints/s */
4217 if (bytes > 25000) {
4218 if (packets > 35)
0ba82994 4219 itrval = low_latency;
1e5c3d21 4220 } else if (bytes < 1500) {
0ba82994 4221 itrval = low_latency;
9d5c8243
AK		 4222 }
4223 break;
4224 }
4225
0ba82994
AD		 4226 /* clear work counters since we have the values we need */
4227 ring_container->total_bytes = 0;
4228 ring_container->total_packets = 0;
4229
4230 /* write updated itr to ring container */
4231 ring_container->itr = itrval;
9d5c8243
AK		 4232}
4233
0ba82994 4234static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4235{
0ba82994 4236 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4237 u32 new_itr = q_vector->itr_val;
0ba82994 4238 u8 current_itr = 0;
9d5c8243
AK		 4239
4240 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4241 if (adapter->link_speed != SPEED_1000) {
4242 current_itr = 0;
0ba82994 4243 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4244 goto set_itr_now;
4245 }
4246
0ba82994
AD		 4247 igb_update_itr(q_vector, &q_vector->tx);
4248 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4249
0ba82994 4250 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4251
6eb5a7f1 4252 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4253 if (current_itr == lowest_latency &&
4254 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4255 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4256 current_itr = low_latency;
4257
9d5c8243
AK		 4258 switch (current_itr) {
4259 /* counts and packets in update_itr are dependent on these numbers */
4260 case lowest_latency:
0ba82994 4261 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4262 break;
4263 case low_latency:
0ba82994 4264 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4265 break;
4266 case bulk_latency:
0ba82994 4267 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4268 break;
4269 default:
4270 break;
4271 }
4272
4273set_itr_now:
047e0030 4274 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4275 /* this attempts to bias the interrupt rate towards Bulk
4276 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4277 * increasing
4278 */
047e0030 4279 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4280 max((new_itr * q_vector->itr_val) /
4281 (new_itr + (q_vector->itr_val >> 2)),
4282 new_itr) : new_itr;
9d5c8243
AK		 4283 /* Don't write the value here; it resets the adapter's
4284 * internal timer, and causes us to delay far longer than
4285 * we should between interrupts. Instead, we write the ITR
4286 * value at the beginning of the next interrupt so the timing
4287 * ends up being correct.
4288 */
047e0030
AD		 4289 q_vector->itr_val = new_itr;
4290 q_vector->set_itr = 1;
9d5c8243 4291 }
9d5c8243
AK		 4292}
4293
c50b52a0
SH		 4294static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4295 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4296{
4297 struct e1000_adv_tx_context_desc *context_desc;
4298 u16 i = tx_ring->next_to_use;
4299
4300 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4301
4302 i++;
4303 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4304
4305 /* set bits to identify this as an advanced context descriptor */
4306 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4307
4308 /* For 82575, context index must be unique per ring. */
866cff06 4309 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4310 mss_l4len_idx |= tx_ring->reg_idx << 4;
4311
4312 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4313 context_desc->seqnum_seed = 0;
4314 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4315 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4316}
4317
7af40ad9
AD		 4318static int igb_tso(struct igb_ring *tx_ring,
4319 struct igb_tx_buffer *first,
4320 u8 *hdr_len)
9d5c8243 4321{
7af40ad9 4322 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4323 u32 vlan_macip_lens, type_tucmd;
4324 u32 mss_l4len_idx, l4len;
4325
ed6aa105
AD		 4326 if (skb->ip_summed != CHECKSUM_PARTIAL)
4327 return 0;
4328
7d13a7d0
AD		 4329 if (!skb_is_gso(skb))
4330 return 0;
9d5c8243
AK		 4331
4332 if (skb_header_cloned(skb)) {
7af40ad9 4333 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4334 if (err)
4335 return err;
4336 }
4337
7d13a7d0
AD		 4338 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4339 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4340
7af40ad9 4341 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4342 struct iphdr *iph = ip_hdr(skb);
4343 iph->tot_len = 0;
4344 iph->check = 0;
4345 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4346 iph->daddr, 0,
4347 IPPROTO_TCP,
4348 0);
7d13a7d0 4349 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4350 first->tx_flags |= IGB_TX_FLAGS_TSO |
4351 IGB_TX_FLAGS_CSUM |
4352 IGB_TX_FLAGS_IPV4;
8e1e8a47 4353 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4354 ipv6_hdr(skb)->payload_len = 0;
4355 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4356 &ipv6_hdr(skb)->daddr,
4357 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4358 first->tx_flags |= IGB_TX_FLAGS_TSO |
4359 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4360 }
4361
7af40ad9 4362 /* compute header lengths */
7d13a7d0
AD		 4363 l4len = tcp_hdrlen(skb);
4364 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4365
7af40ad9
AD		 4366 /* update gso size and bytecount with header size */
4367 first->gso_segs = skb_shinfo(skb)->gso_segs;
4368 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4369
9d5c8243 4370 /* MSS L4LEN IDX */
7d13a7d0
AD		 4371 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4372 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4373
7d13a7d0
AD		 4374 /* VLAN MACLEN IPLEN */
4375 vlan_macip_lens = skb_network_header_len(skb);
4376 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4377 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4378
7d13a7d0 4379 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4380
7d13a7d0 4381 return 1;
9d5c8243
AK		 4382}
4383
7af40ad9 4384static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4385{
7af40ad9 4386 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4387 u32 vlan_macip_lens = 0;
4388 u32 mss_l4len_idx = 0;
4389 u32 type_tucmd = 0;
9d5c8243 4390
7d13a7d0 4391 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4392 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4393 return;
7d13a7d0
AD		 4394 } else {
4395 u8 l4_hdr = 0;
7af40ad9 4396 switch (first->protocol) {
7d13a7d0
AD		 4397 case __constant_htons(ETH_P_IP):
4398 vlan_macip_lens |= skb_network_header_len(skb);
4399 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4400 l4_hdr = ip_hdr(skb)->protocol;
4401 break;
4402 case __constant_htons(ETH_P_IPV6):
4403 vlan_macip_lens |= skb_network_header_len(skb);
4404 l4_hdr = ipv6_hdr(skb)->nexthdr;
4405 break;
4406 default:
4407 if (unlikely(net_ratelimit())) {
4408 dev_warn(tx_ring->dev,
b980ac18
JK		 4409 "partial checksum but proto=%x!\n",
4410 first->protocol);
fa4a7ef3 4411 }
7d13a7d0
AD		 4412 break;
4413 }
fa4a7ef3 4414
7d13a7d0
AD		 4415 switch (l4_hdr) {
4416 case IPPROTO_TCP:
4417 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4418 mss_l4len_idx = tcp_hdrlen(skb) <<
4419 E1000_ADVTXD_L4LEN_SHIFT;
4420 break;
4421 case IPPROTO_SCTP:
4422 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4423 mss_l4len_idx = sizeof(struct sctphdr) <<
4424 E1000_ADVTXD_L4LEN_SHIFT;
4425 break;
4426 case IPPROTO_UDP:
4427 mss_l4len_idx = sizeof(struct udphdr) <<
4428 E1000_ADVTXD_L4LEN_SHIFT;
4429 break;
4430 default:
4431 if (unlikely(net_ratelimit())) {
4432 dev_warn(tx_ring->dev,
b980ac18
JK		 4433 "partial checksum but l4 proto=%x!\n",
4434 l4_hdr);
44b0cda3 4435 }
7d13a7d0 4436 break;
9d5c8243 4437 }
7af40ad9
AD		 4438
4439 /* update TX checksum flag */
4440 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4441 }
9d5c8243 4442
7d13a7d0 4443 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4444 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4445
7d13a7d0 4446 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4447}
4448
1d9daf45
AD		 4449#define IGB_SET_FLAG(_input, _flag, _result) \
4450 ((_flag <= _result) ? \
4451 ((u32)(_input & _flag) * (_result / _flag)) : \
4452 ((u32)(_input & _flag) / (_flag / _result)))
4453
4454static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4455{
4456 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4457 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4458 E1000_ADVTXD_DCMD_DEXT |
4459 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4460
4461 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4462 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4463 (E1000_ADVTXD_DCMD_VLE));
4464
4465 /* set segmentation bits for TSO */
4466 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4467 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4468
4469 /* set timestamp bit if present */
1d9daf45
AD		 4470 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4471 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4472
1d9daf45
AD		 4473 /* insert frame checksum */
4474 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4475
4476 return cmd_type;
4477}
4478
7af40ad9
AD		 4479static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4480 union e1000_adv_tx_desc *tx_desc,
4481 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4482{
4483 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4484
1d9daf45
AD		 4485 /* 82575 requires a unique index per ring */
4486 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4487 olinfo_status |= tx_ring->reg_idx << 4;
4488
4489 /* insert L4 checksum */
1d9daf45
AD		 4490 olinfo_status |= IGB_SET_FLAG(tx_flags,
4491 IGB_TX_FLAGS_CSUM,
4492 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4493
1d9daf45
AD		 4494 /* insert IPv4 checksum */
4495 olinfo_status |= IGB_SET_FLAG(tx_flags,
4496 IGB_TX_FLAGS_IPV4,
4497 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4498
7af40ad9 4499 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4500}
4501
7af40ad9
AD		 4502static void igb_tx_map(struct igb_ring *tx_ring,
4503 struct igb_tx_buffer *first,
ebe42d16 4504 const u8 hdr_len)
9d5c8243 4505{
7af40ad9 4506 struct sk_buff *skb = first->skb;
c9f14bf3 4507 struct igb_tx_buffer *tx_buffer;
ebe42d16 4508 union e1000_adv_tx_desc *tx_desc;
80d0759e 4509 struct skb_frag_struct *frag;
ebe42d16 4510 dma_addr_t dma;
80d0759e 4511 unsigned int data_len, size;
7af40ad9 4512 u32 tx_flags = first->tx_flags;
1d9daf45 4513 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4514 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4515
4516 tx_desc = IGB_TX_DESC(tx_ring, i);
4517
80d0759e
AD		 4518 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4519
4520 size = skb_headlen(skb);
4521 data_len = skb->data_len;
ebe42d16
AD		 4522
4523 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4524
80d0759e
AD		 4525 tx_buffer = first;
4526
4527 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4528 if (dma_mapping_error(tx_ring->dev, dma))
4529 goto dma_error;
4530
4531 /* record length, and DMA address */
4532 dma_unmap_len_set(tx_buffer, len, size);
4533 dma_unmap_addr_set(tx_buffer, dma, dma);
4534
4535 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4536
ebe42d16
AD		 4537 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4538 tx_desc->read.cmd_type_len =
1d9daf45 4539 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4540
4541 i++;
4542 tx_desc++;
4543 if (i == tx_ring->count) {
4544 tx_desc = IGB_TX_DESC(tx_ring, 0);
4545 i = 0;
4546 }
80d0759e 4547 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4548
4549 dma += IGB_MAX_DATA_PER_TXD;
4550 size -= IGB_MAX_DATA_PER_TXD;
4551
ebe42d16
AD		 4552 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4553 }
4554
4555 if (likely(!data_len))
4556 break;
2bbfebe2 4557
1d9daf45 4558 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4559
65689fef 4560 i++;
ebe42d16
AD		 4561 tx_desc++;
4562 if (i == tx_ring->count) {
4563 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4564 i = 0;
ebe42d16 4565 }
80d0759e 4566 tx_desc->read.olinfo_status = 0;
65689fef 4567
9e903e08 4568 size = skb_frag_size(frag);
ebe42d16
AD		 4569 data_len -= size;
4570
4571 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4572 size, DMA_TO_DEVICE);
6366ad33 4573
c9f14bf3 4574 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4575 }
4576
ebe42d16 4577 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4578 cmd_type |= size | IGB_TXD_DCMD;
4579 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4580
80d0759e
AD		 4581 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4582
8542db05
AD		 4583 /* set the timestamp */
4584 first->time_stamp = jiffies;
4585
b980ac18 4586 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4587 * are new descriptors to fetch. (Only applicable for weak-ordered
4588 * memory model archs, such as IA-64).
4589 *
4590 * We also need this memory barrier to make certain all of the
4591 * status bits have been updated before next_to_watch is written.
4592 */
4593 wmb();
4594
8542db05 4595 /* set next_to_watch value indicating a packet is present */
ebe42d16 4596 first->next_to_watch = tx_desc;
9d5c8243 4597
ebe42d16
AD		 4598 i++;
4599 if (i == tx_ring->count)
4600 i = 0;
6366ad33 4601
ebe42d16 4602 tx_ring->next_to_use = i;
6366ad33 4603
ebe42d16 4604 writel(i, tx_ring->tail);
6366ad33 4605
ebe42d16 4606 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4607 * at a time, it synchronizes IO on IA64/Altix systems
4608 */
ebe42d16
AD		 4609 mmiowb();
4610
4611 return;
4612
4613dma_error:
4614 dev_err(tx_ring->dev, "TX DMA map failed\n");
4615
4616 /* clear dma mappings for failed tx_buffer_info map */
4617 for (;;) {
c9f14bf3
AD		 4618 tx_buffer = &tx_ring->tx_buffer_info[i];
4619 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4620 if (tx_buffer == first)
ebe42d16 4621 break;
a77ff709
NN		 4622 if (i == 0)
4623 i = tx_ring->count;
6366ad33 4624 i--;
6366ad33
AD		 4625 }
4626
9d5c8243 4627 tx_ring->next_to_use = i;
9d5c8243
AK		 4628}
4629
6ad4edfc 4630static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4631{
e694e964
AD		 4632 struct net_device *netdev = tx_ring->netdev;
4633
661086df 4634 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4635
9d5c8243
AK		 4636 /* Herbert's original patch had:
4637 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4638 * but since that doesn't exist yet, just open code it.
4639 */
9d5c8243
AK		 4640 smp_mb();
4641
4642 /* We need to check again in a case another CPU has just
b980ac18
JK		 4643 * made room available.
4644 */
c493ea45 4645 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4646 return -EBUSY;
4647
4648 /* A reprieve! */
661086df 4649 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4650
4651 u64_stats_update_begin(&tx_ring->tx_syncp2);
4652 tx_ring->tx_stats.restart_queue2++;
4653 u64_stats_update_end(&tx_ring->tx_syncp2);
4654
9d5c8243
AK		 4655 return 0;
4656}
4657
6ad4edfc 4658static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4659{
c493ea45 4660 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4661 return 0;
e694e964 4662 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4663}
4664
cd392f5c
AD		 4665netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4666 struct igb_ring *tx_ring)
9d5c8243 4667{
8542db05 4668 struct igb_tx_buffer *first;
ebe42d16 4669 int tso;
91d4ee33 4670 u32 tx_flags = 0;
21ba6fe1 4671 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4672 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4673 u8 hdr_len = 0;
9d5c8243 4674
21ba6fe1
AD		 4675 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4676 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4677 * + 2 desc gap to keep tail from touching head,
9d5c8243 4678 * + 1 desc for context descriptor,
21ba6fe1
AD		 4679 * otherwise try next time
4680 */
4681 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4682 unsigned short f;
4683 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4684 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4685 } else {
4686 count += skb_shinfo(skb)->nr_frags;
4687 }
4688
4689 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4690 /* this is a hard error */
9d5c8243
AK		 4691 return NETDEV_TX_BUSY;
4692 }
33af6bcc 4693
7af40ad9
AD		 4694 /* record the location of the first descriptor for this packet */
4695 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4696 first->skb = skb;
4697 first->bytecount = skb->len;
4698 first->gso_segs = 1;
4699
b66e2397
MV		 4700 skb_tx_timestamp(skb);
4701
b646c22e
AD		 4702 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4703 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4704
b646c22e
AD		 4705 if (!(adapter->ptp_tx_skb)) {
4706 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4707 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4708
4709 adapter->ptp_tx_skb = skb_get(skb);
4710 adapter->ptp_tx_start = jiffies;
4711 if (adapter->hw.mac.type == e1000_82576)
4712 schedule_work(&adapter->ptp_tx_work);
4713 }
33af6bcc 4714 }
9d5c8243 4715
eab6d18d 4716 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4717 tx_flags |= IGB_TX_FLAGS_VLAN;
4718 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4719 }
4720
7af40ad9
AD		 4721 /* record initial flags and protocol */
4722 first->tx_flags = tx_flags;
4723 first->protocol = protocol;
cdfd01fc 4724
7af40ad9
AD		 4725 tso = igb_tso(tx_ring, first, &hdr_len);
4726 if (tso < 0)
7d13a7d0 4727 goto out_drop;
7af40ad9
AD		 4728 else if (!tso)
4729 igb_tx_csum(tx_ring, first);
9d5c8243 4730
7af40ad9 4731 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4732
4733 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4734 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4735
9d5c8243 4736 return NETDEV_TX_OK;
7d13a7d0
AD		 4737
4738out_drop:
7af40ad9
AD		 4739 igb_unmap_and_free_tx_resource(tx_ring, first);
4740
7d13a7d0 4741 return NETDEV_TX_OK;
9d5c8243
AK		 4742}
4743
1cc3bd87
AD		 4744static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4745 struct sk_buff *skb)
4746{
4747 unsigned int r_idx = skb->queue_mapping;
4748
4749 if (r_idx >= adapter->num_tx_queues)
4750 r_idx = r_idx % adapter->num_tx_queues;
4751
4752 return adapter->tx_ring[r_idx];
4753}
4754
cd392f5c
AD		 4755static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4756 struct net_device *netdev)
9d5c8243
AK		 4757{
4758 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4759
4760 if (test_bit(__IGB_DOWN, &adapter->state)) {
4761 dev_kfree_skb_any(skb);
4762 return NETDEV_TX_OK;
4763 }
4764
4765 if (skb->len <= 0) {
4766 dev_kfree_skb_any(skb);
4767 return NETDEV_TX_OK;
4768 }
4769
b980ac18 4770 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4771 * in order to meet this minimum size requirement.
4772 */
ea5ceeab
TD		 4773 if (unlikely(skb->len < 17)) {
4774 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4775 return NETDEV_TX_OK;
4776 skb->len = 17;
ea5ceeab 4777 skb_set_tail_pointer(skb, 17);
1cc3bd87 4778 }
9d5c8243 4779
1cc3bd87 4780 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4781}
4782
4783/**
b980ac18
JK		 4784 * igb_tx_timeout - Respond to a Tx Hang
4785 * @netdev: network interface device structure
9d5c8243
AK		 4786 **/
4787static void igb_tx_timeout(struct net_device *netdev)
4788{
4789 struct igb_adapter *adapter = netdev_priv(netdev);
4790 struct e1000_hw *hw = &adapter->hw;
4791
4792 /* Do the reset outside of interrupt context */
4793 adapter->tx_timeout_count++;
f7ba205e 4794
06218a8d 4795 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4796 hw->dev_spec._82575.global_device_reset = true;
4797
9d5c8243 4798 schedule_work(&adapter->reset_task);
265de409
AD		 4799 wr32(E1000_EICS,
4800 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4801}
4802
4803static void igb_reset_task(struct work_struct *work)
4804{
4805 struct igb_adapter *adapter;
4806 adapter = container_of(work, struct igb_adapter, reset_task);
4807
c97ec42a
TI		 4808 igb_dump(adapter);
4809 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4810 igb_reinit_locked(adapter);
4811}
4812
4813/**
b980ac18
JK		 4814 * igb_get_stats64 - Get System Network Statistics
4815 * @netdev: network interface device structure
4816 * @stats: rtnl_link_stats64 pointer
9d5c8243 4817 **/
12dcd86b 4818static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4819 struct rtnl_link_stats64 *stats)
9d5c8243 4820{
12dcd86b
ED		 4821 struct igb_adapter *adapter = netdev_priv(netdev);
4822
4823 spin_lock(&adapter->stats64_lock);
4824 igb_update_stats(adapter, &adapter->stats64);
4825 memcpy(stats, &adapter->stats64, sizeof(*stats));
4826 spin_unlock(&adapter->stats64_lock);
4827
4828 return stats;
9d5c8243
AK		 4829}
4830
4831/**
b980ac18
JK		 4832 * igb_change_mtu - Change the Maximum Transfer Unit
4833 * @netdev: network interface device structure
4834 * @new_mtu: new value for maximum frame size
9d5c8243 4835 *
b980ac18 4836 * Returns 0 on success, negative on failure
9d5c8243
AK		 4837 **/
4838static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4839{
4840 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4841 struct pci_dev *pdev = adapter->pdev;
153285f9 4842 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4843
c809d227 4844 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4845 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4846 return -EINVAL;
4847 }
4848
153285f9 4849#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4850 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4851 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4852 return -EINVAL;
4853 }
4854
2ccd994c
AD		 4855 /* adjust max frame to be at least the size of a standard frame */
4856 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4857 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4858
9d5c8243
AK		 4859 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4860 msleep(1);
73cd78f1 4861
9d5c8243
AK		 4862 /* igb_down has a dependency on max_frame_size */
4863 adapter->max_frame_size = max_frame;
559e9c49 4864
4c844851
AD		 4865 if (netif_running(netdev))
4866 igb_down(adapter);
9d5c8243 4867
090b1795 4868 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4869 netdev->mtu, new_mtu);
4870 netdev->mtu = new_mtu;
4871
4872 if (netif_running(netdev))
4873 igb_up(adapter);
4874 else
4875 igb_reset(adapter);
4876
4877 clear_bit(__IGB_RESETTING, &adapter->state);
4878
4879 return 0;
4880}
4881
4882/**
b980ac18
JK		 4883 * igb_update_stats - Update the board statistics counters
4884 * @adapter: board private structure
9d5c8243 4885 **/
12dcd86b
ED		 4886void igb_update_stats(struct igb_adapter *adapter,
4887 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4888{
4889 struct e1000_hw *hw = &adapter->hw;
4890 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4891 u32 reg, mpc;
9d5c8243 4892 u16 phy_tmp;
3f9c0164
AD		 4893 int i;
4894 u64 bytes, packets;
12dcd86b
ED		 4895 unsigned int start;
4896 u64 _bytes, _packets;
9d5c8243
AK		 4897
4898#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4899
b980ac18 4900 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4901 * connection is down.
4902 */
4903 if (adapter->link_speed == 0)
4904 return;
4905 if (pci_channel_offline(pdev))
4906 return;
4907
3f9c0164
AD		 4908 bytes = 0;
4909 packets = 0;
7f90128e
AA		 4910
4911 rcu_read_lock();
3f9c0164 4912 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4913 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4914 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4915
ae1c07a6
AD		 4916 if (rqdpc) {
4917 ring->rx_stats.drops += rqdpc;
4918 net_stats->rx_fifo_errors += rqdpc;
4919 }
12dcd86b
ED		 4920
4921 do {
4922 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4923 _bytes = ring->rx_stats.bytes;
4924 _packets = ring->rx_stats.packets;
4925 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4926 bytes += _bytes;
4927 packets += _packets;
3f9c0164
AD		 4928 }
4929
128e45eb
AD		 4930 net_stats->rx_bytes = bytes;
4931 net_stats->rx_packets = packets;
3f9c0164
AD		 4932
4933 bytes = 0;
4934 packets = 0;
4935 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4936 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4937 do {
4938 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4939 _bytes = ring->tx_stats.bytes;
4940 _packets = ring->tx_stats.packets;
4941 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4942 bytes += _bytes;
4943 packets += _packets;
3f9c0164 4944 }
128e45eb
AD		 4945 net_stats->tx_bytes = bytes;
4946 net_stats->tx_packets = packets;
7f90128e 4947 rcu_read_unlock();
3f9c0164
AD		 4948
4949 /* read stats registers */
9d5c8243
AK		 4950 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4951 adapter->stats.gprc += rd32(E1000_GPRC);
4952 adapter->stats.gorc += rd32(E1000_GORCL);
4953 rd32(E1000_GORCH); /* clear GORCL */
4954 adapter->stats.bprc += rd32(E1000_BPRC);
4955 adapter->stats.mprc += rd32(E1000_MPRC);
4956 adapter->stats.roc += rd32(E1000_ROC);
4957
4958 adapter->stats.prc64 += rd32(E1000_PRC64);
4959 adapter->stats.prc127 += rd32(E1000_PRC127);
4960 adapter->stats.prc255 += rd32(E1000_PRC255);
4961 adapter->stats.prc511 += rd32(E1000_PRC511);
4962 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4963 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4964 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4965 adapter->stats.sec += rd32(E1000_SEC);
4966
fa3d9a6d
MW		 4967 mpc = rd32(E1000_MPC);
4968 adapter->stats.mpc += mpc;
4969 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4970 adapter->stats.scc += rd32(E1000_SCC);
4971 adapter->stats.ecol += rd32(E1000_ECOL);
4972 adapter->stats.mcc += rd32(E1000_MCC);
4973 adapter->stats.latecol += rd32(E1000_LATECOL);
4974 adapter->stats.dc += rd32(E1000_DC);
4975 adapter->stats.rlec += rd32(E1000_RLEC);
4976 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4977 adapter->stats.xontxc += rd32(E1000_XONTXC);
4978 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4979 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4980 adapter->stats.fcruc += rd32(E1000_FCRUC);
4981 adapter->stats.gptc += rd32(E1000_GPTC);
4982 adapter->stats.gotc += rd32(E1000_GOTCL);
4983 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4984 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4985 adapter->stats.ruc += rd32(E1000_RUC);
4986 adapter->stats.rfc += rd32(E1000_RFC);
4987 adapter->stats.rjc += rd32(E1000_RJC);
4988 adapter->stats.tor += rd32(E1000_TORH);
4989 adapter->stats.tot += rd32(E1000_TOTH);
4990 adapter->stats.tpr += rd32(E1000_TPR);
4991
4992 adapter->stats.ptc64 += rd32(E1000_PTC64);
4993 adapter->stats.ptc127 += rd32(E1000_PTC127);
4994 adapter->stats.ptc255 += rd32(E1000_PTC255);
4995 adapter->stats.ptc511 += rd32(E1000_PTC511);
4996 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4997 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4998
4999 adapter->stats.mptc += rd32(E1000_MPTC);
5000 adapter->stats.bptc += rd32(E1000_BPTC);
5001
2d0b0f69
NN		 5002 adapter->stats.tpt += rd32(E1000_TPT);
5003 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5004
5005 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5006 /* read internal phy specific stats */
5007 reg = rd32(E1000_CTRL_EXT);
5008 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5009 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5010
5011 /* this stat has invalid values on i210/i211 */
5012 if ((hw->mac.type != e1000_i210) &&
5013 (hw->mac.type != e1000_i211))
5014 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5015 }
5016
9d5c8243
AK		 5017 adapter->stats.tsctc += rd32(E1000_TSCTC);
5018 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5019
5020 adapter->stats.iac += rd32(E1000_IAC);
5021 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5022 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5023 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5024 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5025 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5026 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5027 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5028 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5029
5030 /* Fill out the OS statistics structure */
128e45eb
AD		 5031 net_stats->multicast = adapter->stats.mprc;
5032 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5033
5034 /* Rx Errors */
5035
5036 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5037 * our own version based on RUC and ROC
5038 */
128e45eb 5039 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5040 adapter->stats.crcerrs + adapter->stats.algnerrc +
5041 adapter->stats.ruc + adapter->stats.roc +
5042 adapter->stats.cexterr;
128e45eb
AD		 5043 net_stats->rx_length_errors = adapter->stats.ruc +
5044 adapter->stats.roc;
5045 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5046 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5047 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5048
5049 /* Tx Errors */
128e45eb
AD		 5050 net_stats->tx_errors = adapter->stats.ecol +
5051 adapter->stats.latecol;
5052 net_stats->tx_aborted_errors = adapter->stats.ecol;
5053 net_stats->tx_window_errors = adapter->stats.latecol;
5054 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5055
5056 /* Tx Dropped needs to be maintained elsewhere */
5057
5058 /* Phy Stats */
5059 if (hw->phy.media_type == e1000_media_type_copper) {
5060 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5061 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5062 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5063 adapter->phy_stats.idle_errors += phy_tmp;
5064 }
5065 }
5066
5067 /* Management Stats */
5068 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5069 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5070 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5071
5072 /* OS2BMC Stats */
5073 reg = rd32(E1000_MANC);
5074 if (reg & E1000_MANC_EN_BMC2OS) {
5075 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5076 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5077 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5078 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5079 }
9d5c8243
AK		 5080}
5081
9d5c8243
AK		 5082static irqreturn_t igb_msix_other(int irq, void *data)
5083{
047e0030 5084 struct igb_adapter *adapter = data;
9d5c8243 5085 struct e1000_hw *hw = &adapter->hw;
844290e5 5086 u32 icr = rd32(E1000_ICR);
844290e5 5087 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5088
7f081d40
AD		 5089 if (icr & E1000_ICR_DRSTA)
5090 schedule_work(&adapter->reset_task);
5091
047e0030 5092 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5093 /* HW is reporting DMA is out of sync */
5094 adapter->stats.doosync++;
13800469
GR		 5095 /* The DMA Out of Sync is also indication of a spoof event
5096 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5097 * see if it is really a spoof event.
5098 */
13800469 5099 igb_check_wvbr(adapter);
dda0e083 5100 }
eebbbdba 5101
4ae196df
AD		 5102 /* Check for a mailbox event */
5103 if (icr & E1000_ICR_VMMB)
5104 igb_msg_task(adapter);
5105
5106 if (icr & E1000_ICR_LSC) {
5107 hw->mac.get_link_status = 1;
5108 /* guard against interrupt when we're going down */
5109 if (!test_bit(__IGB_DOWN, &adapter->state))
5110 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5111 }
5112
1f6e8178
MV		 5113 if (icr & E1000_ICR_TS) {
5114 u32 tsicr = rd32(E1000_TSICR);
5115
5116 if (tsicr & E1000_TSICR_TXTS) {
5117 /* acknowledge the interrupt */
5118 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5119 /* retrieve hardware timestamp */
5120 schedule_work(&adapter->ptp_tx_work);
5121 }
5122 }
1f6e8178 5123
844290e5 5124 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5125
5126 return IRQ_HANDLED;
5127}
5128
047e0030 5129static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5130{
26b39276 5131 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5132 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5133
047e0030
AD		 5134 if (!q_vector->set_itr)
5135 return;
73cd78f1 5136
047e0030
AD		 5137 if (!itr_val)
5138 itr_val = 0x4;
661086df 5139
26b39276
AD		 5140 if (adapter->hw.mac.type == e1000_82575)
5141 itr_val |= itr_val << 16;
661086df 5142 else
0ba82994 5143 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5144
047e0030
AD		 5145 writel(itr_val, q_vector->itr_register);
5146 q_vector->set_itr = 0;
6eb5a7f1
AD		 5147}
5148
047e0030 5149static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5150{
047e0030 5151 struct igb_q_vector *q_vector = data;
9d5c8243 5152
047e0030
AD		 5153 /* Write the ITR value calculated from the previous interrupt. */
5154 igb_write_itr(q_vector);
9d5c8243 5155
047e0030 5156 napi_schedule(&q_vector->napi);
844290e5 5157
047e0030 5158 return IRQ_HANDLED;
fe4506b6
JC		 5159}
5160
421e02f0 5161#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5162static void igb_update_tx_dca(struct igb_adapter *adapter,
5163 struct igb_ring *tx_ring,
5164 int cpu)
5165{
5166 struct e1000_hw *hw = &adapter->hw;
5167 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5168
5169 if (hw->mac.type != e1000_82575)
5170 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5171
b980ac18 5172 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5173 * DCA is enabled. This is due to a known issue in some chipsets
5174 * which will cause the DCA tag to be cleared.
5175 */
5176 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5177 E1000_DCA_TXCTRL_DATA_RRO_EN |
5178 E1000_DCA_TXCTRL_DESC_DCA_EN;
5179
5180 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5181}
5182
5183static void igb_update_rx_dca(struct igb_adapter *adapter,
5184 struct igb_ring *rx_ring,
5185 int cpu)
5186{
5187 struct e1000_hw *hw = &adapter->hw;
5188 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5189
5190 if (hw->mac.type != e1000_82575)
5191 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5192
b980ac18 5193 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5194 * DCA is enabled. This is due to a known issue in some chipsets
5195 * which will cause the DCA tag to be cleared.
5196 */
5197 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5198 E1000_DCA_RXCTRL_DESC_DCA_EN;
5199
5200 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5201}
5202
047e0030 5203static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5204{
047e0030 5205 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5206 int cpu = get_cpu();
fe4506b6 5207
047e0030
AD		 5208 if (q_vector->cpu == cpu)
5209 goto out_no_update;
5210
6a05004a
AD		 5211 if (q_vector->tx.ring)
5212 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5213
5214 if (q_vector->rx.ring)
5215 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5216
047e0030
AD		 5217 q_vector->cpu = cpu;
5218out_no_update:
fe4506b6
JC		 5219 put_cpu();
5220}
5221
5222static void igb_setup_dca(struct igb_adapter *adapter)
5223{
7e0e99ef 5224 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5225 int i;
5226
7dfc16fa 5227 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5228 return;
5229
7e0e99ef
AD		 5230 /* Always use CB2 mode, difference is masked in the CB driver. */
5231 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5232
047e0030 5233 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5234 adapter->q_vector[i]->cpu = -1;
5235 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5236 }
5237}
5238
5239static int __igb_notify_dca(struct device *dev, void *data)
5240{
5241 struct net_device *netdev = dev_get_drvdata(dev);
5242 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5243 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5244 struct e1000_hw *hw = &adapter->hw;
5245 unsigned long event = *(unsigned long *)data;
5246
5247 switch (event) {
5248 case DCA_PROVIDER_ADD:
5249 /* if already enabled, don't do it again */
7dfc16fa 5250 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5251 break;
fe4506b6 5252 if (dca_add_requester(dev) == 0) {
bbd98fe4 5253 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5254 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5255 igb_setup_dca(adapter);
5256 break;
5257 }
5258 /* Fall Through since DCA is disabled. */
5259 case DCA_PROVIDER_REMOVE:
7dfc16fa 5260 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5261 /* without this a class_device is left
b980ac18
JK		 5262 * hanging around in the sysfs model
5263 */
fe4506b6 5264 dca_remove_requester(dev);
090b1795 5265 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5266 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5267 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5268 }
5269 break;
5270 }
bbd98fe4 5271
fe4506b6 5272 return 0;
9d5c8243
AK		 5273}
5274
fe4506b6 5275static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5276 void *p)
fe4506b6
JC		 5277{
5278 int ret_val;
5279
5280 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5281 __igb_notify_dca);
fe4506b6
JC		 5282
5283 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5284}
421e02f0 5285#endif /* CONFIG_IGB_DCA */
9d5c8243 5286
0224d663
GR		 5287#ifdef CONFIG_PCI_IOV
5288static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5289{
5290 unsigned char mac_addr[ETH_ALEN];
0224d663 5291
5ac6f91d 5292 eth_zero_addr(mac_addr);
0224d663
GR		 5293 igb_set_vf_mac(adapter, vf, mac_addr);
5294
70ea4783
LL		 5295 /* By default spoof check is enabled for all VFs */
5296 adapter->vf_data[vf].spoofchk_enabled = true;
5297
f557147c 5298 return 0;
0224d663
GR		 5299}
5300
0224d663 5301#endif
4ae196df
AD		 5302static void igb_ping_all_vfs(struct igb_adapter *adapter)
5303{
5304 struct e1000_hw *hw = &adapter->hw;
5305 u32 ping;
5306 int i;
5307
5308 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5309 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5310 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5311 ping |= E1000_VT_MSGTYPE_CTS;
5312 igb_write_mbx(hw, &ping, 1, i);
5313 }
5314}
5315
7d5753f0
AD		 5316static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5317{
5318 struct e1000_hw *hw = &adapter->hw;
5319 u32 vmolr = rd32(E1000_VMOLR(vf));
5320 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5321
d85b9004 5322 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5323 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5324 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5325
5326 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5327 vmolr |= E1000_VMOLR_MPME;
d85b9004 5328 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5329 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5330 } else {
b980ac18 5331 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5332 * flag we need to write the hashes to the MTA as this step
5333 * was previously skipped
5334 */
5335 if (vf_data->num_vf_mc_hashes > 30) {
5336 vmolr |= E1000_VMOLR_MPME;
5337 } else if (vf_data->num_vf_mc_hashes) {
5338 int j;
5339 vmolr |= E1000_VMOLR_ROMPE;
5340 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5341 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5342 }
5343 }
5344
5345 wr32(E1000_VMOLR(vf), vmolr);
5346
5347 /* there are flags left unprocessed, likely not supported */
5348 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5349 return -EINVAL;
5350
5351 return 0;
7d5753f0
AD		 5352}
5353
4ae196df
AD		 5354static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5355 u32 *msgbuf, u32 vf)
5356{
5357 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5358 u16 *hash_list = (u16 *)&msgbuf[1];
5359 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5360 int i;
5361
7d5753f0 5362 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5363 * to this VF for later use to restore when the PF multi cast
5364 * list changes
5365 */
5366 vf_data->num_vf_mc_hashes = n;
5367
7d5753f0
AD		 5368 /* only up to 30 hash values supported */
5369 if (n > 30)
5370 n = 30;
5371
5372 /* store the hashes for later use */
4ae196df 5373 for (i = 0; i < n; i++)
a419aef8 5374 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5375
5376 /* Flush and reset the mta with the new values */
ff41f8dc 5377 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5378
5379 return 0;
5380}
5381
5382static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5383{
5384 struct e1000_hw *hw = &adapter->hw;
5385 struct vf_data_storage *vf_data;
5386 int i, j;
5387
5388 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5389 u32 vmolr = rd32(E1000_VMOLR(i));
5390 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5391
4ae196df 5392 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5393
5394 if ((vf_data->num_vf_mc_hashes > 30) ||
5395 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5396 vmolr |= E1000_VMOLR_MPME;
5397 } else if (vf_data->num_vf_mc_hashes) {
5398 vmolr |= E1000_VMOLR_ROMPE;
5399 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5400 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5401 }
5402 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5403 }
5404}
5405
5406static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5407{
5408 struct e1000_hw *hw = &adapter->hw;
5409 u32 pool_mask, reg, vid;
5410 int i;
5411
5412 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5413
5414 /* Find the vlan filter for this id */
5415 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5416 reg = rd32(E1000_VLVF(i));
5417
5418 /* remove the vf from the pool */
5419 reg &= ~pool_mask;
5420
5421 /* if pool is empty then remove entry from vfta */
5422 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5423 (reg & E1000_VLVF_VLANID_ENABLE)) {
5424 reg = 0;
5425 vid = reg & E1000_VLVF_VLANID_MASK;
5426 igb_vfta_set(hw, vid, false);
5427 }
5428
5429 wr32(E1000_VLVF(i), reg);
5430 }
ae641bdc
AD		 5431
5432 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5433}
5434
5435static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5436{
5437 struct e1000_hw *hw = &adapter->hw;
5438 u32 reg, i;
5439
51466239
AD		 5440 /* The vlvf table only exists on 82576 hardware and newer */
5441 if (hw->mac.type < e1000_82576)
5442 return -1;
5443
5444 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5445 if (!adapter->vfs_allocated_count)
5446 return -1;
5447
5448 /* Find the vlan filter for this id */
5449 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5450 reg = rd32(E1000_VLVF(i));
5451 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5452 vid == (reg & E1000_VLVF_VLANID_MASK))
5453 break;
5454 }
5455
5456 if (add) {
5457 if (i == E1000_VLVF_ARRAY_SIZE) {
5458 /* Did not find a matching VLAN ID entry that was
5459 * enabled. Search for a free filter entry, i.e.
5460 * one without the enable bit set
5461 */
5462 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5463 reg = rd32(E1000_VLVF(i));
5464 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5465 break;
5466 }
5467 }
5468 if (i < E1000_VLVF_ARRAY_SIZE) {
5469 /* Found an enabled/available entry */
5470 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5471
5472 /* if !enabled we need to set this up in vfta */
5473 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5474 /* add VID to filter table */
5475 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5476 reg |= E1000_VLVF_VLANID_ENABLE;
5477 }
cad6d05f
AD		 5478 reg &= ~E1000_VLVF_VLANID_MASK;
5479 reg |= vid;
4ae196df 5480 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5481
5482 /* do not modify RLPML for PF devices */
5483 if (vf >= adapter->vfs_allocated_count)
5484 return 0;
5485
5486 if (!adapter->vf_data[vf].vlans_enabled) {
5487 u32 size;
5488 reg = rd32(E1000_VMOLR(vf));
5489 size = reg & E1000_VMOLR_RLPML_MASK;
5490 size += 4;
5491 reg &= ~E1000_VMOLR_RLPML_MASK;
5492 reg |= size;
5493 wr32(E1000_VMOLR(vf), reg);
5494 }
ae641bdc 5495
51466239 5496 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5497 }
5498 } else {
5499 if (i < E1000_VLVF_ARRAY_SIZE) {
5500 /* remove vf from the pool */
5501 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5502 /* if pool is empty then remove entry from vfta */
5503 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5504 reg = 0;
5505 igb_vfta_set(hw, vid, false);
5506 }
5507 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5508
5509 /* do not modify RLPML for PF devices */
5510 if (vf >= adapter->vfs_allocated_count)
5511 return 0;
5512
5513 adapter->vf_data[vf].vlans_enabled--;
5514 if (!adapter->vf_data[vf].vlans_enabled) {
5515 u32 size;
5516 reg = rd32(E1000_VMOLR(vf));
5517 size = reg & E1000_VMOLR_RLPML_MASK;
5518 size -= 4;
5519 reg &= ~E1000_VMOLR_RLPML_MASK;
5520 reg |= size;
5521 wr32(E1000_VMOLR(vf), reg);
5522 }
4ae196df
AD		 5523 }
5524 }
8151d294
WM		 5525 return 0;
5526}
5527
5528static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5529{
5530 struct e1000_hw *hw = &adapter->hw;
5531
5532 if (vid)
5533 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5534 else
5535 wr32(E1000_VMVIR(vf), 0);
5536}
5537
5538static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5539 int vf, u16 vlan, u8 qos)
5540{
5541 int err = 0;
5542 struct igb_adapter *adapter = netdev_priv(netdev);
5543
5544 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5545 return -EINVAL;
5546 if (vlan || qos) {
5547 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5548 if (err)
5549 goto out;
5550 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5551 igb_set_vmolr(adapter, vf, !vlan);
5552 adapter->vf_data[vf].pf_vlan = vlan;
5553 adapter->vf_data[vf].pf_qos = qos;
5554 dev_info(&adapter->pdev->dev,
5555 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5556 if (test_bit(__IGB_DOWN, &adapter->state)) {
5557 dev_warn(&adapter->pdev->dev,
b980ac18 5558 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5559 dev_warn(&adapter->pdev->dev,
b980ac18 5560 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5561 }
5562 } else {
5563 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5564 false, vf);
8151d294
WM		 5565 igb_set_vmvir(adapter, vlan, vf);
5566 igb_set_vmolr(adapter, vf, true);
5567 adapter->vf_data[vf].pf_vlan = 0;
5568 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5569 }
8151d294 5570out:
b980ac18 5571 return err;
4ae196df
AD		 5572}
5573
6f3dc319
GR		 5574static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5575{
5576 struct e1000_hw *hw = &adapter->hw;
5577 int i;
5578 u32 reg;
5579
5580 /* Find the vlan filter for this id */
5581 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5582 reg = rd32(E1000_VLVF(i));
5583 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5584 vid == (reg & E1000_VLVF_VLANID_MASK))
5585 break;
5586 }
5587
5588 if (i >= E1000_VLVF_ARRAY_SIZE)
5589 i = -1;
5590
5591 return i;
5592}
5593
4ae196df
AD		 5594static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5595{
6f3dc319 5596 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5597 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5598 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5599 int err = 0;
4ae196df 5600
6f3dc319
GR		 5601 /* If in promiscuous mode we need to make sure the PF also has
5602 * the VLAN filter set.
5603 */
5604 if (add && (adapter->netdev->flags & IFF_PROMISC))
5605 err = igb_vlvf_set(adapter, vid, add,
5606 adapter->vfs_allocated_count);
5607 if (err)
5608 goto out;
5609
5610 err = igb_vlvf_set(adapter, vid, add, vf);
5611
5612 if (err)
5613 goto out;
5614
5615 /* Go through all the checks to see if the VLAN filter should
5616 * be wiped completely.
5617 */
5618 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5619 u32 vlvf, bits;
5620
5621 int regndx = igb_find_vlvf_entry(adapter, vid);
5622 if (regndx < 0)
5623 goto out;
5624 /* See if any other pools are set for this VLAN filter
5625 * entry other than the PF.
5626 */
5627 vlvf = bits = rd32(E1000_VLVF(regndx));
5628 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5629 adapter->vfs_allocated_count);
5630 /* If the filter was removed then ensure PF pool bit
5631 * is cleared if the PF only added itself to the pool
5632 * because the PF is in promiscuous mode.
5633 */
5634 if ((vlvf & VLAN_VID_MASK) == vid &&
5635 !test_bit(vid, adapter->active_vlans) &&
5636 !bits)
5637 igb_vlvf_set(adapter, vid, add,
5638 adapter->vfs_allocated_count);
5639 }
5640
5641out:
5642 return err;
4ae196df
AD		 5643}
5644
f2ca0dbe 5645static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5646{
8fa7e0f7
GR		 5647 /* clear flags - except flag that indicates PF has set the MAC */
5648 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5649 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5650
5651 /* reset offloads to defaults */
8151d294 5652 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5653
5654 /* reset vlans for device */
5655 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5656 if (adapter->vf_data[vf].pf_vlan)
5657 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5658 adapter->vf_data[vf].pf_vlan,
5659 adapter->vf_data[vf].pf_qos);
5660 else
5661 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5662
5663 /* reset multicast table array for vf */
5664 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5665
5666 /* Flush and reset the mta with the new values */
ff41f8dc 5667 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5668}
5669
f2ca0dbe
AD		 5670static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5671{
5672 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5673
5ac6f91d 5674 /* clear mac address as we were hotplug removed/added */
8151d294 5675 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5676 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5677
5678 /* process remaining reset events */
5679 igb_vf_reset(adapter, vf);
5680}
5681
5682static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5683{
5684 struct e1000_hw *hw = &adapter->hw;
5685 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5686 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5687 u32 reg, msgbuf[3];
5688 u8 *addr = (u8 *)(&msgbuf[1]);
5689
5690 /* process all the same items cleared in a function level reset */
f2ca0dbe 5691 igb_vf_reset(adapter, vf);
4ae196df
AD		 5692
5693 /* set vf mac address */
26ad9178 5694 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5695
5696 /* enable transmit and receive for vf */
5697 reg = rd32(E1000_VFTE);
5698 wr32(E1000_VFTE, reg | (1 << vf));
5699 reg = rd32(E1000_VFRE);
5700 wr32(E1000_VFRE, reg | (1 << vf));
5701
8fa7e0f7 5702 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5703
5704 /* reply to reset with ack and vf mac address */
5705 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5706 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5707 igb_write_mbx(hw, msgbuf, 3, vf);
5708}
5709
5710static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5711{
b980ac18 5712 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5713 * starting at the second 32 bit word of the msg array
5714 */
f2ca0dbe
AD		 5715 unsigned char *addr = (char *)&msg[1];
5716 int err = -1;
4ae196df 5717
f2ca0dbe
AD		 5718 if (is_valid_ether_addr(addr))
5719 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5720
f2ca0dbe 5721 return err;
4ae196df
AD		 5722}
5723
5724static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5725{
5726 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5727 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5728 u32 msg = E1000_VT_MSGTYPE_NACK;
5729
5730 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5731 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5732 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5733 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5734 vf_data->last_nack = jiffies;
4ae196df
AD		 5735 }
5736}
5737
f2ca0dbe 5738static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5739{
f2ca0dbe
AD		 5740 struct pci_dev *pdev = adapter->pdev;
5741 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5742 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5743 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5744 s32 retval;
5745
f2ca0dbe 5746 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5747
fef45f4c
AD		 5748 if (retval) {
5749 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5750 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5751 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5752 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5753 return;
5754 goto out;
5755 }
4ae196df
AD		 5756
5757 /* this is a message we already processed, do nothing */
5758 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5759 return;
4ae196df 5760
b980ac18 5761 /* until the vf completes a reset it should not be
4ae196df
AD		 5762 * allowed to start any configuration.
5763 */
4ae196df
AD		 5764 if (msgbuf[0] == E1000_VF_RESET) {
5765 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5766 return;
4ae196df
AD		 5767 }
5768
f2ca0dbe 5769 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5770 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5771 return;
5772 retval = -1;
5773 goto out;
4ae196df
AD		 5774 }
5775
5776 switch ((msgbuf[0] & 0xFFFF)) {
5777 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5778 retval = -EINVAL;
5779 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5780 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5781 else
5782 dev_warn(&pdev->dev,
b980ac18
JK		 5783 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5784 vf);
4ae196df 5785 break;
7d5753f0
AD		 5786 case E1000_VF_SET_PROMISC:
5787 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5788 break;
4ae196df
AD		 5789 case E1000_VF_SET_MULTICAST:
5790 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5791 break;
5792 case E1000_VF_SET_LPE:
5793 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5794 break;
5795 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5796 retval = -1;
5797 if (vf_data->pf_vlan)
5798 dev_warn(&pdev->dev,
b980ac18
JK		 5799 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5800 vf);
8151d294
WM		 5801 else
5802 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5803 break;
5804 default:
090b1795 5805 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5806 retval = -1;
5807 break;
5808 }
5809
fef45f4c
AD		 5810 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5811out:
4ae196df
AD		 5812 /* notify the VF of the results of what it sent us */
5813 if (retval)
5814 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5815 else
5816 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5817
4ae196df 5818 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5819}
4ae196df 5820
f2ca0dbe
AD		 5821static void igb_msg_task(struct igb_adapter *adapter)
5822{
5823 struct e1000_hw *hw = &adapter->hw;
5824 u32 vf;
5825
5826 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5827 /* process any reset requests */
5828 if (!igb_check_for_rst(hw, vf))
5829 igb_vf_reset_event(adapter, vf);
5830
5831 /* process any messages pending */
5832 if (!igb_check_for_msg(hw, vf))
5833 igb_rcv_msg_from_vf(adapter, vf);
5834
5835 /* process any acks */
5836 if (!igb_check_for_ack(hw, vf))
5837 igb_rcv_ack_from_vf(adapter, vf);
5838 }
4ae196df
AD		 5839}
5840
68d480c4
AD		 5841/**
5842 * igb_set_uta - Set unicast filter table address
5843 * @adapter: board private structure
5844 *
5845 * The unicast table address is a register array of 32-bit registers.
5846 * The table is meant to be used in a way similar to how the MTA is used
5847 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5848 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5849 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5850 **/
5851static void igb_set_uta(struct igb_adapter *adapter)
5852{
5853 struct e1000_hw *hw = &adapter->hw;
5854 int i;
5855
5856 /* The UTA table only exists on 82576 hardware and newer */
5857 if (hw->mac.type < e1000_82576)
5858 return;
5859
5860 /* we only need to do this if VMDq is enabled */
5861 if (!adapter->vfs_allocated_count)
5862 return;
5863
5864 for (i = 0; i < hw->mac.uta_reg_count; i++)
5865 array_wr32(E1000_UTA, i, ~0);
5866}
5867
9d5c8243 5868/**
b980ac18
JK		 5869 * igb_intr_msi - Interrupt Handler
5870 * @irq: interrupt number
5871 * @data: pointer to a network interface device structure
9d5c8243
AK		 5872 **/
5873static irqreturn_t igb_intr_msi(int irq, void *data)
5874{
047e0030
AD		 5875 struct igb_adapter *adapter = data;
5876 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5877 struct e1000_hw *hw = &adapter->hw;
5878 /* read ICR disables interrupts using IAM */
5879 u32 icr = rd32(E1000_ICR);
5880
047e0030 5881 igb_write_itr(q_vector);
9d5c8243 5882
7f081d40
AD		 5883 if (icr & E1000_ICR_DRSTA)
5884 schedule_work(&adapter->reset_task);
5885
047e0030 5886 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5887 /* HW is reporting DMA is out of sync */
5888 adapter->stats.doosync++;
5889 }
5890
9d5c8243
AK		 5891 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5892 hw->mac.get_link_status = 1;
5893 if (!test_bit(__IGB_DOWN, &adapter->state))
5894 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5895 }
5896
1f6e8178
MV		 5897 if (icr & E1000_ICR_TS) {
5898 u32 tsicr = rd32(E1000_TSICR);
5899
5900 if (tsicr & E1000_TSICR_TXTS) {
5901 /* acknowledge the interrupt */
5902 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5903 /* retrieve hardware timestamp */
5904 schedule_work(&adapter->ptp_tx_work);
5905 }
5906 }
1f6e8178 5907
047e0030 5908 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5909
5910 return IRQ_HANDLED;
5911}
5912
5913/**
b980ac18
JK		 5914 * igb_intr - Legacy Interrupt Handler
5915 * @irq: interrupt number
5916 * @data: pointer to a network interface device structure
9d5c8243
AK		 5917 **/
5918static irqreturn_t igb_intr(int irq, void *data)
5919{
047e0030
AD		 5920 struct igb_adapter *adapter = data;
5921 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5922 struct e1000_hw *hw = &adapter->hw;
5923 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5924 * need for the IMC write
5925 */
9d5c8243 5926 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5927
5928 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5929 * not set, then the adapter didn't send an interrupt
5930 */
9d5c8243
AK		 5931 if (!(icr & E1000_ICR_INT_ASSERTED))
5932 return IRQ_NONE;
5933
0ba82994
AD		 5934 igb_write_itr(q_vector);
5935
7f081d40
AD		 5936 if (icr & E1000_ICR_DRSTA)
5937 schedule_work(&adapter->reset_task);
5938
047e0030 5939 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5940 /* HW is reporting DMA is out of sync */
5941 adapter->stats.doosync++;
5942 }
5943
9d5c8243
AK		 5944 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5945 hw->mac.get_link_status = 1;
5946 /* guard against interrupt when we're going down */
5947 if (!test_bit(__IGB_DOWN, &adapter->state))
5948 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5949 }
5950
1f6e8178
MV		 5951 if (icr & E1000_ICR_TS) {
5952 u32 tsicr = rd32(E1000_TSICR);
5953
5954 if (tsicr & E1000_TSICR_TXTS) {
5955 /* acknowledge the interrupt */
5956 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5957 /* retrieve hardware timestamp */
5958 schedule_work(&adapter->ptp_tx_work);
5959 }
5960 }
1f6e8178 5961
047e0030 5962 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5963
5964 return IRQ_HANDLED;
5965}
5966
c50b52a0 5967static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5968{
047e0030 5969 struct igb_adapter *adapter = q_vector->adapter;
46544258 5970 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5971
0ba82994
AD		 5972 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5973 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5974 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5975 igb_set_itr(q_vector);
46544258 5976 else
047e0030 5977 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5978 }
5979
46544258
AD		 5980 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5981 if (adapter->msix_entries)
047e0030 5982 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5983 else
5984 igb_irq_enable(adapter);
5985 }
9d5c8243
AK		 5986}
5987
46544258 5988/**
b980ac18
JK		 5989 * igb_poll - NAPI Rx polling callback
5990 * @napi: napi polling structure
5991 * @budget: count of how many packets we should handle
46544258
AD		 5992 **/
5993static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5994{
047e0030 5995 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 5996 struct igb_q_vector,
5997 napi);
16eb8815 5998 bool clean_complete = true;
9d5c8243 5999
421e02f0 6000#ifdef CONFIG_IGB_DCA
047e0030
AD		 6001 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6002 igb_update_dca(q_vector);
fe4506b6 6003#endif
0ba82994 6004 if (q_vector->tx.ring)
13fde97a 6005 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6006
0ba82994 6007 if (q_vector->rx.ring)
cd392f5c 6008 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6009
16eb8815
AD		 6010 /* If all work not completed, return budget and keep polling */
6011 if (!clean_complete)
6012 return budget;
46544258 6013
9d5c8243 6014 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6015 napi_complete(napi);
6016 igb_ring_irq_enable(q_vector);
9d5c8243 6017
16eb8815 6018 return 0;
9d5c8243 6019}
6d8126f9 6020
9d5c8243 6021/**
b980ac18
JK		 6022 * igb_clean_tx_irq - Reclaim resources after transmit completes
6023 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6024 *
b980ac18 6025 * returns true if ring is completely cleaned
9d5c8243 6026 **/
047e0030 6027static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6028{
047e0030 6029 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6030 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6031 struct igb_tx_buffer *tx_buffer;
f4128785 6032 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6033 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6034 unsigned int budget = q_vector->tx.work_limit;
8542db05 6035 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6036
13fde97a
AD		 6037 if (test_bit(__IGB_DOWN, &adapter->state))
6038 return true;
0e014cb1 6039
06034649 6040 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6041 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6042 i -= tx_ring->count;
9d5c8243 6043
f4128785
AD		 6044 do {
6045 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6046
6047 /* if next_to_watch is not set then there is no work pending */
6048 if (!eop_desc)
6049 break;
13fde97a 6050
f4128785 6051 /* prevent any other reads prior to eop_desc */
70d289bc 6052 read_barrier_depends();
f4128785 6053
13fde97a
AD		 6054 /* if DD is not set pending work has not been completed */
6055 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6056 break;
6057
8542db05
AD		 6058 /* clear next_to_watch to prevent false hangs */
6059 tx_buffer->next_to_watch = NULL;
9d5c8243 6060
ebe42d16
AD		 6061 /* update the statistics for this packet */
6062 total_bytes += tx_buffer->bytecount;
6063 total_packets += tx_buffer->gso_segs;
13fde97a 6064
ebe42d16
AD		 6065 /* free the skb */
6066 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6067
ebe42d16
AD		 6068 /* unmap skb header data */
6069 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6070 dma_unmap_addr(tx_buffer, dma),
6071 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6072 DMA_TO_DEVICE);
6073
c9f14bf3
AD		 6074 /* clear tx_buffer data */
6075 tx_buffer->skb = NULL;
6076 dma_unmap_len_set(tx_buffer, len, 0);
6077
ebe42d16
AD		 6078 /* clear last DMA location and unmap remaining buffers */
6079 while (tx_desc != eop_desc) {
13fde97a
AD		 6080 tx_buffer++;
6081 tx_desc++;
9d5c8243 6082 i++;
8542db05
AD		 6083 if (unlikely(!i)) {
6084 i -= tx_ring->count;
06034649 6085 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6086 tx_desc = IGB_TX_DESC(tx_ring, 0);
6087 }
ebe42d16
AD		 6088
6089 /* unmap any remaining paged data */
c9f14bf3 6090 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6091 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6092 dma_unmap_addr(tx_buffer, dma),
6093 dma_unmap_len(tx_buffer, len),
ebe42d16 6094 DMA_TO_DEVICE);
c9f14bf3 6095 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6096 }
6097 }
6098
ebe42d16
AD		 6099 /* move us one more past the eop_desc for start of next pkt */
6100 tx_buffer++;
6101 tx_desc++;
6102 i++;
6103 if (unlikely(!i)) {
6104 i -= tx_ring->count;
6105 tx_buffer = tx_ring->tx_buffer_info;
6106 tx_desc = IGB_TX_DESC(tx_ring, 0);
6107 }
f4128785
AD		 6108
6109 /* issue prefetch for next Tx descriptor */
6110 prefetch(tx_desc);
6111
6112 /* update budget accounting */
6113 budget--;
6114 } while (likely(budget));
0e014cb1 6115
bdbc0631
ED		 6116 netdev_tx_completed_queue(txring_txq(tx_ring),
6117 total_packets, total_bytes);
8542db05 6118 i += tx_ring->count;
9d5c8243 6119 tx_ring->next_to_clean = i;
13fde97a
AD		 6120 u64_stats_update_begin(&tx_ring->tx_syncp);
6121 tx_ring->tx_stats.bytes += total_bytes;
6122 tx_ring->tx_stats.packets += total_packets;
6123 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6124 q_vector->tx.total_bytes += total_bytes;
6125 q_vector->tx.total_packets += total_packets;
9d5c8243 6126
6d095fa8 6127 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6128 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6129
9d5c8243 6130 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6131 * check with the clearing of time_stamp and movement of i
6132 */
6d095fa8 6133 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6134 if (tx_buffer->next_to_watch &&
8542db05 6135 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6136 (adapter->tx_timeout_factor * HZ)) &&
6137 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6138
9d5c8243 6139 /* detected Tx unit hang */
59d71989 6140 dev_err(tx_ring->dev,
9d5c8243 6141 "Detected Tx Unit Hang\n"
2d064c06 6142 " Tx Queue <%d>\n"
9d5c8243
AK		 6143 " TDH <%x>\n"
6144 " TDT <%x>\n"
6145 " next_to_use <%x>\n"
6146 " next_to_clean <%x>\n"
9d5c8243
AK		 6147 "buffer_info[next_to_clean]\n"
6148 " time_stamp <%lx>\n"
8542db05 6149 " next_to_watch <%p>\n"
9d5c8243
AK		 6150 " jiffies <%lx>\n"
6151 " desc.status <%x>\n",
2d064c06 6152 tx_ring->queue_index,
238ac817 6153 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6154 readl(tx_ring->tail),
9d5c8243
AK		 6155 tx_ring->next_to_use,
6156 tx_ring->next_to_clean,
8542db05 6157 tx_buffer->time_stamp,
f4128785 6158 tx_buffer->next_to_watch,
9d5c8243 6159 jiffies,
f4128785 6160 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6161 netif_stop_subqueue(tx_ring->netdev,
6162 tx_ring->queue_index);
6163
6164 /* we are about to reset, no point in enabling stuff */
6165 return true;
9d5c8243
AK		 6166 }
6167 }
13fde97a 6168
21ba6fe1 6169#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6170 if (unlikely(total_packets &&
b980ac18
JK		 6171 netif_carrier_ok(tx_ring->netdev) &&
6172 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6173 /* Make sure that anybody stopping the queue after this
6174 * sees the new next_to_clean.
6175 */
6176 smp_mb();
6177 if (__netif_subqueue_stopped(tx_ring->netdev,
6178 tx_ring->queue_index) &&
6179 !(test_bit(__IGB_DOWN, &adapter->state))) {
6180 netif_wake_subqueue(tx_ring->netdev,
6181 tx_ring->queue_index);
6182
6183 u64_stats_update_begin(&tx_ring->tx_syncp);
6184 tx_ring->tx_stats.restart_queue++;
6185 u64_stats_update_end(&tx_ring->tx_syncp);
6186 }
6187 }
6188
6189 return !!budget;
9d5c8243
AK		 6190}
6191
cbc8e55f 6192/**
b980ac18
JK		 6193 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6194 * @rx_ring: rx descriptor ring to store buffers on
6195 * @old_buff: donor buffer to have page reused
cbc8e55f 6196 *
b980ac18 6197 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6198 **/
6199static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6200 struct igb_rx_buffer *old_buff)
6201{
6202 struct igb_rx_buffer *new_buff;
6203 u16 nta = rx_ring->next_to_alloc;
6204
6205 new_buff = &rx_ring->rx_buffer_info[nta];
6206
6207 /* update, and store next to alloc */
6208 nta++;
6209 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6210
6211 /* transfer page from old buffer to new buffer */
6212 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6213
6214 /* sync the buffer for use by the device */
6215 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6216 old_buff->page_offset,
de78d1f9 6217 IGB_RX_BUFSZ,
cbc8e55f
AD		 6218 DMA_FROM_DEVICE);
6219}
6220
74e238ea
AD		 6221static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6222 struct page *page,
6223 unsigned int truesize)
6224{
6225 /* avoid re-using remote pages */
6226 if (unlikely(page_to_nid(page) != numa_node_id()))
6227 return false;
6228
6229#if (PAGE_SIZE < 8192)
6230 /* if we are only owner of page we can reuse it */
6231 if (unlikely(page_count(page) != 1))
6232 return false;
6233
6234 /* flip page offset to other buffer */
6235 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6236
6237 /* since we are the only owner of the page and we need to
6238 * increment it, just set the value to 2 in order to avoid
6239 * an unnecessary locked operation
6240 */
6241 atomic_set(&page->_count, 2);
6242#else
6243 /* move offset up to the next cache line */
6244 rx_buffer->page_offset += truesize;
6245
6246 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6247 return false;
6248
6249 /* bump ref count on page before it is given to the stack */
6250 get_page(page);
6251#endif
6252
6253 return true;
6254}
6255
cbc8e55f 6256/**
b980ac18
JK		 6257 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6258 * @rx_ring: rx descriptor ring to transact packets on
6259 * @rx_buffer: buffer containing page to add
6260 * @rx_desc: descriptor containing length of buffer written by hardware
6261 * @skb: sk_buff to place the data into
cbc8e55f 6262 *
b980ac18
JK		 6263 * This function will add the data contained in rx_buffer->page to the skb.
6264 * This is done either through a direct copy if the data in the buffer is
6265 * less than the skb header size, otherwise it will just attach the page as
6266 * a frag to the skb.
cbc8e55f 6267 *
b980ac18
JK		 6268 * The function will then update the page offset if necessary and return
6269 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6270 **/
6271static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6272 struct igb_rx_buffer *rx_buffer,
6273 union e1000_adv_rx_desc *rx_desc,
6274 struct sk_buff *skb)
6275{
6276 struct page *page = rx_buffer->page;
6277 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6278#if (PAGE_SIZE < 8192)
6279 unsigned int truesize = IGB_RX_BUFSZ;
6280#else
6281 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6282#endif
cbc8e55f
AD		 6283
6284 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6285 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6286
cbc8e55f
AD		 6287 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6288 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6289 va += IGB_TS_HDR_LEN;
6290 size -= IGB_TS_HDR_LEN;
6291 }
6292
cbc8e55f
AD		 6293 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6294
6295 /* we can reuse buffer as-is, just make sure it is local */
6296 if (likely(page_to_nid(page) == numa_node_id()))
6297 return true;
6298
6299 /* this page cannot be reused so discard it */
6300 put_page(page);
6301 return false;
6302 }
6303
6304 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6305 rx_buffer->page_offset, size, truesize);
cbc8e55f 6306
74e238ea
AD		 6307 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6308}
cbc8e55f 6309
2e334eee
AD		 6310static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6311 union e1000_adv_rx_desc *rx_desc,
6312 struct sk_buff *skb)
6313{
6314 struct igb_rx_buffer *rx_buffer;
6315 struct page *page;
6316
6317 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6318
2e334eee
AD		 6319 page = rx_buffer->page;
6320 prefetchw(page);
6321
6322 if (likely(!skb)) {
6323 void *page_addr = page_address(page) +
6324 rx_buffer->page_offset;
6325
6326 /* prefetch first cache line of first page */
6327 prefetch(page_addr);
6328#if L1_CACHE_BYTES < 128
6329 prefetch(page_addr + L1_CACHE_BYTES);
6330#endif
6331
6332 /* allocate a skb to store the frags */
6333 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6334 IGB_RX_HDR_LEN);
6335 if (unlikely(!skb)) {
6336 rx_ring->rx_stats.alloc_failed++;
6337 return NULL;
6338 }
6339
b980ac18 6340 /* we will be copying header into skb->data in
2e334eee
AD		 6341 * pskb_may_pull so it is in our interest to prefetch
6342 * it now to avoid a possible cache miss
6343 */
6344 prefetchw(skb->data);
6345 }
6346
6347 /* we are reusing so sync this buffer for CPU use */
6348 dma_sync_single_range_for_cpu(rx_ring->dev,
6349 rx_buffer->dma,
6350 rx_buffer->page_offset,
de78d1f9 6351 IGB_RX_BUFSZ,
2e334eee
AD		 6352 DMA_FROM_DEVICE);
6353
6354 /* pull page into skb */
6355 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6356 /* hand second half of page back to the ring */
6357 igb_reuse_rx_page(rx_ring, rx_buffer);
6358 } else {
6359 /* we are not reusing the buffer so unmap it */
6360 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6361 PAGE_SIZE, DMA_FROM_DEVICE);
6362 }
6363
6364 /* clear contents of rx_buffer */
6365 rx_buffer->page = NULL;
6366
6367 return skb;
6368}
6369
cd392f5c 6370static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6371 union e1000_adv_rx_desc *rx_desc,
6372 struct sk_buff *skb)
9d5c8243 6373{
bc8acf2c 6374 skb_checksum_none_assert(skb);
9d5c8243 6375
294e7d78 6376 /* Ignore Checksum bit is set */
3ceb90fd 6377 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6378 return;
6379
6380 /* Rx checksum disabled via ethtool */
6381 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6382 return;
85ad76b2 6383
9d5c8243 6384 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6385 if (igb_test_staterr(rx_desc,
6386 E1000_RXDEXT_STATERR_TCPE |
6387 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6388 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6389 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6390 * packets, (aka let the stack check the crc32c)
6391 */
866cff06
AD		 6392 if (!((skb->len == 60) &&
6393 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6394 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6395 ring->rx_stats.csum_err++;
12dcd86b
ED		 6396 u64_stats_update_end(&ring->rx_syncp);
6397 }
9d5c8243 6398 /* let the stack verify checksum errors */
9d5c8243
AK		 6399 return;
6400 }
6401 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6402 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6403 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6404 skb->ip_summed = CHECKSUM_UNNECESSARY;
6405
3ceb90fd
AD		 6406 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6407 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6408}
6409
077887c3
AD		 6410static inline void igb_rx_hash(struct igb_ring *ring,
6411 union e1000_adv_rx_desc *rx_desc,
6412 struct sk_buff *skb)
6413{
6414 if (ring->netdev->features & NETIF_F_RXHASH)
6415 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6416}
6417
2e334eee 6418/**
b980ac18
JK		 6419 * igb_is_non_eop - process handling of non-EOP buffers
6420 * @rx_ring: Rx ring being processed
6421 * @rx_desc: Rx descriptor for current buffer
6422 * @skb: current socket buffer containing buffer in progress
2e334eee 6423 *
b980ac18
JK		 6424 * This function updates next to clean. If the buffer is an EOP buffer
6425 * this function exits returning false, otherwise it will place the
6426 * sk_buff in the next buffer to be chained and return true indicating
6427 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6428 **/
6429static bool igb_is_non_eop(struct igb_ring *rx_ring,
6430 union e1000_adv_rx_desc *rx_desc)
6431{
6432 u32 ntc = rx_ring->next_to_clean + 1;
6433
6434 /* fetch, update, and store next to clean */
6435 ntc = (ntc < rx_ring->count) ? ntc : 0;
6436 rx_ring->next_to_clean = ntc;
6437
6438 prefetch(IGB_RX_DESC(rx_ring, ntc));
6439
6440 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6441 return false;
6442
6443 return true;
6444}
6445
1a1c225b 6446/**
b980ac18
JK		 6447 * igb_get_headlen - determine size of header for LRO/GRO
6448 * @data: pointer to the start of the headers
6449 * @max_len: total length of section to find headers in
1a1c225b 6450 *
b980ac18
JK		 6451 * This function is meant to determine the length of headers that will
6452 * be recognized by hardware for LRO, and GRO offloads. The main
6453 * motivation of doing this is to only perform one pull for IPv4 TCP
6454 * packets so that we can do basic things like calculating the gso_size
6455 * based on the average data per packet.
1a1c225b
AD		 6456 **/
6457static unsigned int igb_get_headlen(unsigned char *data,
6458 unsigned int max_len)
6459{
6460 union {
6461 unsigned char *network;
6462 /* l2 headers */
6463 struct ethhdr *eth;
6464 struct vlan_hdr *vlan;
6465 /* l3 headers */
6466 struct iphdr *ipv4;
6467 struct ipv6hdr *ipv6;
6468 } hdr;
6469 __be16 protocol;
6470 u8 nexthdr = 0; /* default to not TCP */
6471 u8 hlen;
6472
6473 /* this should never happen, but better safe than sorry */
6474 if (max_len < ETH_HLEN)
6475 return max_len;
6476
6477 /* initialize network frame pointer */
6478 hdr.network = data;
6479
6480 /* set first protocol and move network header forward */
6481 protocol = hdr.eth->h_proto;
6482 hdr.network += ETH_HLEN;
6483
6484 /* handle any vlan tag if present */
6485 if (protocol == __constant_htons(ETH_P_8021Q)) {
6486 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6487 return max_len;
6488
6489 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6490 hdr.network += VLAN_HLEN;
6491 }
6492
6493 /* handle L3 protocols */
6494 if (protocol == __constant_htons(ETH_P_IP)) {
6495 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6496 return max_len;
6497
6498 /* access ihl as a u8 to avoid unaligned access on ia64 */
6499 hlen = (hdr.network[0] & 0x0F) << 2;
6500
6501 /* verify hlen meets minimum size requirements */
6502 if (hlen < sizeof(struct iphdr))
6503 return hdr.network - data;
6504
f2fb4ab2 6505 /* record next protocol if header is present */
b9555f66 6506 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6507 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6508 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6509 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6510 return max_len;
6511
6512 /* record next protocol */
6513 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6514 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6515 } else {
6516 return hdr.network - data;
6517 }
6518
f2fb4ab2
AD		 6519 /* relocate pointer to start of L4 header */
6520 hdr.network += hlen;
6521
1a1c225b
AD		 6522 /* finally sort out TCP */
6523 if (nexthdr == IPPROTO_TCP) {
6524 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6525 return max_len;
6526
6527 /* access doff as a u8 to avoid unaligned access on ia64 */
6528 hlen = (hdr.network[12] & 0xF0) >> 2;
6529
6530 /* verify hlen meets minimum size requirements */
6531 if (hlen < sizeof(struct tcphdr))
6532 return hdr.network - data;
6533
6534 hdr.network += hlen;
6535 } else if (nexthdr == IPPROTO_UDP) {
6536 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6537 return max_len;
6538
6539 hdr.network += sizeof(struct udphdr);
6540 }
6541
b980ac18 6542 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6543 * data section of the packet and will be the end of the header.
6544 * If not then it probably represents the end of the last recognized
6545 * header.
6546 */
6547 if ((hdr.network - data) < max_len)
6548 return hdr.network - data;
6549 else
6550 return max_len;
6551}
6552
6553/**
b980ac18
JK		 6554 * igb_pull_tail - igb specific version of skb_pull_tail
6555 * @rx_ring: rx descriptor ring packet is being transacted on
6556 * @rx_desc: pointer to the EOP Rx descriptor
6557 * @skb: pointer to current skb being adjusted
1a1c225b 6558 *
b980ac18
JK		 6559 * This function is an igb specific version of __pskb_pull_tail. The
6560 * main difference between this version and the original function is that
6561 * this function can make several assumptions about the state of things
6562 * that allow for significant optimizations versus the standard function.
6563 * As a result we can do things like drop a frag and maintain an accurate
6564 * truesize for the skb.
1a1c225b
AD		 6565 */
6566static void igb_pull_tail(struct igb_ring *rx_ring,
6567 union e1000_adv_rx_desc *rx_desc,
6568 struct sk_buff *skb)
2d94d8ab 6569{
1a1c225b
AD		 6570 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6571 unsigned char *va;
6572 unsigned int pull_len;
6573
b980ac18 6574 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6575 * working with pages allocated out of the lomem pool per
6576 * alloc_page(GFP_ATOMIC)
2d94d8ab 6577 */
1a1c225b
AD		 6578 va = skb_frag_address(frag);
6579
1a1c225b
AD		 6580 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6581 /* retrieve timestamp from buffer */
6582 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6583
6584 /* update pointers to remove timestamp header */
6585 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6586 frag->page_offset += IGB_TS_HDR_LEN;
6587 skb->data_len -= IGB_TS_HDR_LEN;
6588 skb->len -= IGB_TS_HDR_LEN;
6589
6590 /* move va to start of packet data */
6591 va += IGB_TS_HDR_LEN;
6592 }
6593
b980ac18 6594 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6595 * 60 bytes if the skb->len is less than 60 for skb_pad.
6596 */
6597 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6598
6599 /* align pull length to size of long to optimize memcpy performance */
6600 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6601
6602 /* update all of the pointers */
6603 skb_frag_size_sub(frag, pull_len);
6604 frag->page_offset += pull_len;
6605 skb->data_len -= pull_len;
6606 skb->tail += pull_len;
6607}
6608
6609/**
b980ac18
JK		 6610 * igb_cleanup_headers - Correct corrupted or empty headers
6611 * @rx_ring: rx descriptor ring packet is being transacted on
6612 * @rx_desc: pointer to the EOP Rx descriptor
6613 * @skb: pointer to current skb being fixed
1a1c225b 6614 *
b980ac18
JK		 6615 * Address the case where we are pulling data in on pages only
6616 * and as such no data is present in the skb header.
1a1c225b 6617 *
b980ac18
JK		 6618 * In addition if skb is not at least 60 bytes we need to pad it so that
6619 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6620 *
b980ac18 6621 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6622 **/
6623static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6624 union e1000_adv_rx_desc *rx_desc,
6625 struct sk_buff *skb)
6626{
1a1c225b
AD		 6627 if (unlikely((igb_test_staterr(rx_desc,
6628 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6629 struct net_device *netdev = rx_ring->netdev;
6630 if (!(netdev->features & NETIF_F_RXALL)) {
6631 dev_kfree_skb_any(skb);
6632 return true;
6633 }
6634 }
6635
6636 /* place header in linear portion of buffer */
6637 if (skb_is_nonlinear(skb))
6638 igb_pull_tail(rx_ring, rx_desc, skb);
6639
6640 /* if skb_pad returns an error the skb was freed */
6641 if (unlikely(skb->len < 60)) {
6642 int pad_len = 60 - skb->len;
6643
6644 if (skb_pad(skb, pad_len))
6645 return true;
6646 __skb_put(skb, pad_len);
6647 }
6648
6649 return false;
2d94d8ab
AD		 6650}
6651
db2ee5bd 6652/**
b980ac18
JK		 6653 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6654 * @rx_ring: rx descriptor ring packet is being transacted on
6655 * @rx_desc: pointer to the EOP Rx descriptor
6656 * @skb: pointer to current skb being populated
db2ee5bd 6657 *
b980ac18
JK		 6658 * This function checks the ring, descriptor, and packet information in
6659 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6660 * other fields within the skb.
db2ee5bd
AD		 6661 **/
6662static void igb_process_skb_fields(struct igb_ring *rx_ring,
6663 union e1000_adv_rx_desc *rx_desc,
6664 struct sk_buff *skb)
6665{
6666 struct net_device *dev = rx_ring->netdev;
6667
6668 igb_rx_hash(rx_ring, rx_desc, skb);
6669
6670 igb_rx_checksum(rx_ring, rx_desc, skb);
6671
20a48412 6672 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6673
f646968f 6674 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6675 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6676 u16 vid;
6677 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6678 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6679 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6680 else
6681 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6682
86a9bad3 6683 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6684 }
6685
6686 skb_record_rx_queue(skb, rx_ring->queue_index);
6687
6688 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6689}
6690
2e334eee 6691static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6692{
0ba82994 6693 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6694 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6695 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6696 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6697
2e334eee
AD		 6698 do {
6699 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6700
2e334eee
AD		 6701 /* return some buffers to hardware, one at a time is too slow */
6702 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6703 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6704 cleaned_count = 0;
6705 }
bf36c1a0 6706
2e334eee 6707 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6708
2e334eee
AD		 6709 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6710 break;
9d5c8243 6711
74e238ea
AD		 6712 /* This memory barrier is needed to keep us from reading
6713 * any other fields out of the rx_desc until we know the
6714 * RXD_STAT_DD bit is set
6715 */
6716 rmb();
6717
2e334eee 6718 /* retrieve a buffer from the ring */
f9d40f6a 6719 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6720
2e334eee
AD		 6721 /* exit if we failed to retrieve a buffer */
6722 if (!skb)
6723 break;
1a1c225b 6724
2e334eee 6725 cleaned_count++;
1a1c225b 6726
2e334eee
AD		 6727 /* fetch next buffer in frame if non-eop */
6728 if (igb_is_non_eop(rx_ring, rx_desc))
6729 continue;
1a1c225b
AD		 6730
6731 /* verify the packet layout is correct */
6732 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6733 skb = NULL;
6734 continue;
9d5c8243 6735 }
9d5c8243 6736
db2ee5bd 6737 /* probably a little skewed due to removing CRC */
3ceb90fd 6738 total_bytes += skb->len;
3ceb90fd 6739
db2ee5bd
AD		 6740 /* populate checksum, timestamp, VLAN, and protocol */
6741 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6742
b2cb09b1 6743 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6744
1a1c225b
AD		 6745 /* reset skb pointer */
6746 skb = NULL;
6747
2e334eee
AD		 6748 /* update budget accounting */
6749 total_packets++;
6750 } while (likely(total_packets < budget));
bf36c1a0 6751
1a1c225b
AD		 6752 /* place incomplete frames back on ring for completion */
6753 rx_ring->skb = skb;
6754
12dcd86b 6755 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6756 rx_ring->rx_stats.packets += total_packets;
6757 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6758 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6759 q_vector->rx.total_packets += total_packets;
6760 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6761
6762 if (cleaned_count)
cd392f5c 6763 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6764
2e334eee 6765 return (total_packets < budget);
9d5c8243
AK		 6766}
6767
c023cd88 6768static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6769 struct igb_rx_buffer *bi)
c023cd88
AD		 6770{
6771 struct page *page = bi->page;
cbc8e55f 6772 dma_addr_t dma;
c023cd88 6773
cbc8e55f
AD		 6774 /* since we are recycling buffers we should seldom need to alloc */
6775 if (likely(page))
c023cd88
AD		 6776 return true;
6777
cbc8e55f
AD		 6778 /* alloc new page for storage */
6779 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6780 if (unlikely(!page)) {
6781 rx_ring->rx_stats.alloc_failed++;
6782 return false;
c023cd88
AD		 6783 }
6784
cbc8e55f
AD		 6785 /* map page for use */
6786 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6787
b980ac18 6788 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6789 * there isn't much point in holding memory we can't use
6790 */
1a1c225b 6791 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6792 __free_page(page);
6793
c023cd88
AD		 6794 rx_ring->rx_stats.alloc_failed++;
6795 return false;
6796 }
6797
1a1c225b 6798 bi->dma = dma;
cbc8e55f
AD		 6799 bi->page = page;
6800 bi->page_offset = 0;
1a1c225b 6801
c023cd88
AD		 6802 return true;
6803}
6804
9d5c8243 6805/**
b980ac18
JK		 6806 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6807 * @adapter: address of board private structure
9d5c8243 6808 **/
cd392f5c 6809void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6810{
9d5c8243 6811 union e1000_adv_rx_desc *rx_desc;
06034649 6812 struct igb_rx_buffer *bi;
c023cd88 6813 u16 i = rx_ring->next_to_use;
9d5c8243 6814
cbc8e55f
AD		 6815 /* nothing to do */
6816 if (!cleaned_count)
6817 return;
6818
60136906 6819 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6820 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6821 i -= rx_ring->count;
9d5c8243 6822
cbc8e55f 6823 do {
1a1c225b 6824 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6825 break;
9d5c8243 6826
b980ac18 6827 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6828 * because each write-back erases this info.
6829 */
f9d40f6a 6830 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6831
c023cd88
AD		 6832 rx_desc++;
6833 bi++;
9d5c8243 6834 i++;
c023cd88 6835 if (unlikely(!i)) {
60136906 6836 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6837 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6838 i -= rx_ring->count;
6839 }
6840
6841 /* clear the hdr_addr for the next_to_use descriptor */
6842 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6843
6844 cleaned_count--;
6845 } while (cleaned_count);
9d5c8243 6846
c023cd88
AD		 6847 i += rx_ring->count;
6848
9d5c8243 6849 if (rx_ring->next_to_use != i) {
cbc8e55f 6850 /* record the next descriptor to use */
9d5c8243 6851 rx_ring->next_to_use = i;
9d5c8243 6852
cbc8e55f
AD		 6853 /* update next to alloc since we have filled the ring */
6854 rx_ring->next_to_alloc = i;
6855
b980ac18 6856 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6857 * know there are new descriptors to fetch. (Only
6858 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6859 * such as IA-64).
6860 */
9d5c8243 6861 wmb();
fce99e34 6862 writel(i, rx_ring->tail);
9d5c8243
AK		 6863 }
6864}
6865
6866/**
6867 * igb_mii_ioctl -
6868 * @netdev:
6869 * @ifreq:
6870 * @cmd:
6871 **/
6872static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6873{
6874 struct igb_adapter *adapter = netdev_priv(netdev);
6875 struct mii_ioctl_data *data = if_mii(ifr);
6876
6877 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6878 return -EOPNOTSUPP;
6879
6880 switch (cmd) {
6881 case SIOCGMIIPHY:
6882 data->phy_id = adapter->hw.phy.addr;
6883 break;
6884 case SIOCGMIIREG:
f5f4cf08
AD		 6885 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6886 &data->val_out))
9d5c8243
AK		 6887 return -EIO;
6888 break;
6889 case SIOCSMIIREG:
6890 default:
6891 return -EOPNOTSUPP;
6892 }
6893 return 0;
6894}
6895
6896/**
6897 * igb_ioctl -
6898 * @netdev:
6899 * @ifreq:
6900 * @cmd:
6901 **/
6902static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6903{
6904 switch (cmd) {
6905 case SIOCGMIIPHY:
6906 case SIOCGMIIREG:
6907 case SIOCSMIIREG:
6908 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6909 case SIOCSHWTSTAMP:
a79f4f88 6910 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6911 default:
6912 return -EOPNOTSUPP;
6913 }
6914}
6915
009bc06e
AD		 6916s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6917{
6918 struct igb_adapter *adapter = hw->back;
009bc06e 6919
23d028cc 6920 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6921 return -E1000_ERR_CONFIG;
6922
009bc06e
AD		 6923 return 0;
6924}
6925
6926s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6927{
6928 struct igb_adapter *adapter = hw->back;
009bc06e 6929
23d028cc 6930 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6931 return -E1000_ERR_CONFIG;
6932
009bc06e
AD		 6933 return 0;
6934}
6935
c8f44aff 6936static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6937{
6938 struct igb_adapter *adapter = netdev_priv(netdev);
6939 struct e1000_hw *hw = &adapter->hw;
6940 u32 ctrl, rctl;
f646968f 6941 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6942
5faf030c 6943 if (enable) {
9d5c8243
AK		 6944 /* enable VLAN tag insert/strip */
6945 ctrl = rd32(E1000_CTRL);
6946 ctrl |= E1000_CTRL_VME;
6947 wr32(E1000_CTRL, ctrl);
6948
51466239 6949 /* Disable CFI check */
9d5c8243 6950 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6951 rctl &= ~E1000_RCTL_CFIEN;
6952 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6953 } else {
6954 /* disable VLAN tag insert/strip */
6955 ctrl = rd32(E1000_CTRL);
6956 ctrl &= ~E1000_CTRL_VME;
6957 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6958 }
6959
e1739522 6960 igb_rlpml_set(adapter);
9d5c8243
AK		 6961}
6962
80d5c368
PM		 6963static int igb_vlan_rx_add_vid(struct net_device *netdev,
6964 __be16 proto, u16 vid)
9d5c8243
AK		 6965{
6966 struct igb_adapter *adapter = netdev_priv(netdev);
6967 struct e1000_hw *hw = &adapter->hw;
4ae196df 6968 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6969
51466239
AD		 6970 /* attempt to add filter to vlvf array */
6971 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6972
51466239
AD		 6973 /* add the filter since PF can receive vlans w/o entry in vlvf */
6974 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6975
6976 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6977
6978 return 0;
9d5c8243
AK		 6979}
6980
80d5c368
PM		 6981static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6982 __be16 proto, u16 vid)
9d5c8243
AK		 6983{
6984 struct igb_adapter *adapter = netdev_priv(netdev);
6985 struct e1000_hw *hw = &adapter->hw;
4ae196df 6986 int pf_id = adapter->vfs_allocated_count;
51466239 6987 s32 err;
9d5c8243 6988
51466239
AD		 6989 /* remove vlan from VLVF table array */
6990 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6991
51466239
AD		 6992 /* if vid was not present in VLVF just remove it from table */
6993 if (err)
4ae196df 6994 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6995
6996 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6997
6998 return 0;
9d5c8243
AK		 6999}
7000
7001static void igb_restore_vlan(struct igb_adapter *adapter)
7002{
b2cb09b1 7003 u16 vid;
9d5c8243 7004
5faf030c
AD		 7005 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7006
b2cb09b1 7007 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7008 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7009}
7010
14ad2513 7011int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7012{
090b1795 7013 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7014 struct e1000_mac_info *mac = &adapter->hw.mac;
7015
7016 mac->autoneg = 0;
7017
14ad2513 7018 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7019 * for the switch() below to work
7020 */
14ad2513
DD		 7021 if ((spd & 1) || (dplx & ~1))
7022 goto err_inval;
7023
f502ef7d
AA		 7024 /* Fiber NIC's only allow 1000 gbps Full duplex
7025 * and 100Mbps Full duplex for 100baseFx sfp
7026 */
7027 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7028 switch (spd + dplx) {
7029 case SPEED_10 + DUPLEX_HALF:
7030 case SPEED_10 + DUPLEX_FULL:
7031 case SPEED_100 + DUPLEX_HALF:
7032 goto err_inval;
7033 default:
7034 break;
7035 }
7036 }
cd2638a8 7037
14ad2513 7038 switch (spd + dplx) {
9d5c8243
AK		 7039 case SPEED_10 + DUPLEX_HALF:
7040 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7041 break;
7042 case SPEED_10 + DUPLEX_FULL:
7043 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7044 break;
7045 case SPEED_100 + DUPLEX_HALF:
7046 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7047 break;
7048 case SPEED_100 + DUPLEX_FULL:
7049 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7050 break;
7051 case SPEED_1000 + DUPLEX_FULL:
7052 mac->autoneg = 1;
7053 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7054 break;
7055 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7056 default:
14ad2513 7057 goto err_inval;
9d5c8243 7058 }
8376dad0
JB		 7059
7060 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7061 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7062
9d5c8243 7063 return 0;
14ad2513
DD		 7064
7065err_inval:
7066 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7067 return -EINVAL;
9d5c8243
AK		 7068}
7069
749ab2cd
YZ		 7070static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7071 bool runtime)
9d5c8243
AK		 7072{
7073 struct net_device *netdev = pci_get_drvdata(pdev);
7074 struct igb_adapter *adapter = netdev_priv(netdev);
7075 struct e1000_hw *hw = &adapter->hw;
2d064c06 7076 u32 ctrl, rctl, status;
749ab2cd 7077 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7078#ifdef CONFIG_PM
7079 int retval = 0;
7080#endif
7081
7082 netif_device_detach(netdev);
7083
a88f10ec 7084 if (netif_running(netdev))
749ab2cd 7085 __igb_close(netdev, true);
a88f10ec 7086
047e0030 7087 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7088
7089#ifdef CONFIG_PM
7090 retval = pci_save_state(pdev);
7091 if (retval)
7092 return retval;
7093#endif
7094
7095 status = rd32(E1000_STATUS);
7096 if (status & E1000_STATUS_LU)
7097 wufc &= ~E1000_WUFC_LNKC;
7098
7099 if (wufc) {
7100 igb_setup_rctl(adapter);
ff41f8dc 7101 igb_set_rx_mode(netdev);
9d5c8243
AK		 7102
7103 /* turn on all-multi mode if wake on multicast is enabled */
7104 if (wufc & E1000_WUFC_MC) {
7105 rctl = rd32(E1000_RCTL);
7106 rctl |= E1000_RCTL_MPE;
7107 wr32(E1000_RCTL, rctl);
7108 }
7109
7110 ctrl = rd32(E1000_CTRL);
7111 /* advertise wake from D3Cold */
7112 #define E1000_CTRL_ADVD3WUC 0x00100000
7113 /* phy power management enable */
7114 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7115 ctrl |= E1000_CTRL_ADVD3WUC;
7116 wr32(E1000_CTRL, ctrl);
7117
9d5c8243 7118 /* Allow time for pending master requests to run */
330a6d6a 7119 igb_disable_pcie_master(hw);
9d5c8243
AK		 7120
7121 wr32(E1000_WUC, E1000_WUC_PME_EN);
7122 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7123 } else {
7124 wr32(E1000_WUC, 0);
7125 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7126 }
7127
3fe7c4c9
RW		 7128 *enable_wake = wufc || adapter->en_mng_pt;
7129 if (!*enable_wake)
88a268c1
NN		 7130 igb_power_down_link(adapter);
7131 else
7132 igb_power_up_link(adapter);
9d5c8243
AK		 7133
7134 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7135 * would have already happened in close and is redundant.
7136 */
9d5c8243
AK		 7137 igb_release_hw_control(adapter);
7138
7139 pci_disable_device(pdev);
7140
9d5c8243
AK		 7141 return 0;
7142}
7143
7144#ifdef CONFIG_PM
d9dd966d 7145#ifdef CONFIG_PM_SLEEP
749ab2cd 7146static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7147{
7148 int retval;
7149 bool wake;
749ab2cd 7150 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7151
749ab2cd 7152 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7153 if (retval)
7154 return retval;
7155
7156 if (wake) {
7157 pci_prepare_to_sleep(pdev);
7158 } else {
7159 pci_wake_from_d3(pdev, false);
7160 pci_set_power_state(pdev, PCI_D3hot);
7161 }
7162
7163 return 0;
7164}
d9dd966d 7165#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7166
749ab2cd 7167static int igb_resume(struct device *dev)
9d5c8243 7168{
749ab2cd 7169 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7170 struct net_device *netdev = pci_get_drvdata(pdev);
7171 struct igb_adapter *adapter = netdev_priv(netdev);
7172 struct e1000_hw *hw = &adapter->hw;
7173 u32 err;
7174
7175 pci_set_power_state(pdev, PCI_D0);
7176 pci_restore_state(pdev);
b94f2d77 7177 pci_save_state(pdev);
42bfd33a 7178
aed5dec3 7179 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7180 if (err) {
7181 dev_err(&pdev->dev,
7182 "igb: Cannot enable PCI device from suspend\n");
7183 return err;
7184 }
7185 pci_set_master(pdev);
7186
7187 pci_enable_wake(pdev, PCI_D3hot, 0);
7188 pci_enable_wake(pdev, PCI_D3cold, 0);
7189
53c7d064 7190 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7191 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7192 return -ENOMEM;
9d5c8243
AK		 7193 }
7194
9d5c8243 7195 igb_reset(adapter);
a8564f03
AD		 7196
7197 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7198 * driver.
7199 */
a8564f03
AD		 7200 igb_get_hw_control(adapter);
7201
9d5c8243
AK		 7202 wr32(E1000_WUS, ~0);
7203
749ab2cd 7204 if (netdev->flags & IFF_UP) {
0c2cc02e 7205 rtnl_lock();
749ab2cd 7206 err = __igb_open(netdev, true);
0c2cc02e 7207 rtnl_unlock();
a88f10ec
AD		 7208 if (err)
7209 return err;
7210 }
9d5c8243
AK		 7211
7212 netif_device_attach(netdev);
749ab2cd
YZ		 7213 return 0;
7214}
7215
7216#ifdef CONFIG_PM_RUNTIME
7217static int igb_runtime_idle(struct device *dev)
7218{
7219 struct pci_dev *pdev = to_pci_dev(dev);
7220 struct net_device *netdev = pci_get_drvdata(pdev);
7221 struct igb_adapter *adapter = netdev_priv(netdev);
7222
7223 if (!igb_has_link(adapter))
7224 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7225
7226 return -EBUSY;
7227}
7228
7229static int igb_runtime_suspend(struct device *dev)
7230{
7231 struct pci_dev *pdev = to_pci_dev(dev);
7232 int retval;
7233 bool wake;
7234
7235 retval = __igb_shutdown(pdev, &wake, 1);
7236 if (retval)
7237 return retval;
7238
7239 if (wake) {
7240 pci_prepare_to_sleep(pdev);
7241 } else {
7242 pci_wake_from_d3(pdev, false);
7243 pci_set_power_state(pdev, PCI_D3hot);
7244 }
9d5c8243 7245
9d5c8243
AK		 7246 return 0;
7247}
749ab2cd
YZ		 7248
7249static int igb_runtime_resume(struct device *dev)
7250{
7251 return igb_resume(dev);
7252}
7253#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7254#endif
7255
7256static void igb_shutdown(struct pci_dev *pdev)
7257{
3fe7c4c9
RW		 7258 bool wake;
7259
749ab2cd 7260 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7261
7262 if (system_state == SYSTEM_POWER_OFF) {
7263 pci_wake_from_d3(pdev, wake);
7264 pci_set_power_state(pdev, PCI_D3hot);
7265 }
9d5c8243
AK		 7266}
7267
fa44f2f1
GR		 7268#ifdef CONFIG_PCI_IOV
7269static int igb_sriov_reinit(struct pci_dev *dev)
7270{
7271 struct net_device *netdev = pci_get_drvdata(dev);
7272 struct igb_adapter *adapter = netdev_priv(netdev);
7273 struct pci_dev *pdev = adapter->pdev;
7274
7275 rtnl_lock();
7276
7277 if (netif_running(netdev))
7278 igb_close(netdev);
7279
7280 igb_clear_interrupt_scheme(adapter);
7281
7282 igb_init_queue_configuration(adapter);
7283
7284 if (igb_init_interrupt_scheme(adapter, true)) {
7285 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7286 return -ENOMEM;
7287 }
7288
7289 if (netif_running(netdev))
7290 igb_open(netdev);
7291
7292 rtnl_unlock();
7293
7294 return 0;
7295}
7296
7297static int igb_pci_disable_sriov(struct pci_dev *dev)
7298{
7299 int err = igb_disable_sriov(dev);
7300
7301 if (!err)
7302 err = igb_sriov_reinit(dev);
7303
7304 return err;
7305}
7306
7307static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7308{
7309 int err = igb_enable_sriov(dev, num_vfs);
7310
7311 if (err)
7312 goto out;
7313
7314 err = igb_sriov_reinit(dev);
7315 if (!err)
7316 return num_vfs;
7317
7318out:
7319 return err;
7320}
7321
7322#endif
7323static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7324{
7325#ifdef CONFIG_PCI_IOV
7326 if (num_vfs == 0)
7327 return igb_pci_disable_sriov(dev);
7328 else
7329 return igb_pci_enable_sriov(dev, num_vfs);
7330#endif
7331 return 0;
7332}
7333
9d5c8243 7334#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7335/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7336 * without having to re-enable interrupts. It's not called while
7337 * the interrupt routine is executing.
7338 */
7339static void igb_netpoll(struct net_device *netdev)
7340{
7341 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7342 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7343 struct igb_q_vector *q_vector;
9d5c8243 7344 int i;
9d5c8243 7345
047e0030 7346 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7347 q_vector = adapter->q_vector[i];
7348 if (adapter->msix_entries)
7349 wr32(E1000_EIMC, q_vector->eims_value);
7350 else
7351 igb_irq_disable(adapter);
047e0030 7352 napi_schedule(&q_vector->napi);
eebbbdba 7353 }
9d5c8243
AK		 7354}
7355#endif /* CONFIG_NET_POLL_CONTROLLER */
7356
7357/**
b980ac18
JK		 7358 * igb_io_error_detected - called when PCI error is detected
7359 * @pdev: Pointer to PCI device
7360 * @state: The current pci connection state
9d5c8243 7361 *
b980ac18
JK		 7362 * This function is called after a PCI bus error affecting
7363 * this device has been detected.
7364 **/
9d5c8243
AK		 7365static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7366 pci_channel_state_t state)
7367{
7368 struct net_device *netdev = pci_get_drvdata(pdev);
7369 struct igb_adapter *adapter = netdev_priv(netdev);
7370
7371 netif_device_detach(netdev);
7372
59ed6eec
AD		 7373 if (state == pci_channel_io_perm_failure)
7374 return PCI_ERS_RESULT_DISCONNECT;
7375
9d5c8243
AK		 7376 if (netif_running(netdev))
7377 igb_down(adapter);
7378 pci_disable_device(pdev);
7379
7380 /* Request a slot slot reset. */
7381 return PCI_ERS_RESULT_NEED_RESET;
7382}
7383
7384/**
b980ac18
JK		 7385 * igb_io_slot_reset - called after the pci bus has been reset.
7386 * @pdev: Pointer to PCI device
9d5c8243 7387 *
b980ac18
JK		 7388 * Restart the card from scratch, as if from a cold-boot. Implementation
7389 * resembles the first-half of the igb_resume routine.
7390 **/
9d5c8243
AK		 7391static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7392{
7393 struct net_device *netdev = pci_get_drvdata(pdev);
7394 struct igb_adapter *adapter = netdev_priv(netdev);
7395 struct e1000_hw *hw = &adapter->hw;
40a914fa 7396 pci_ers_result_t result;
42bfd33a 7397 int err;
9d5c8243 7398
aed5dec3 7399 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7400 dev_err(&pdev->dev,
7401 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7402 result = PCI_ERS_RESULT_DISCONNECT;
7403 } else {
7404 pci_set_master(pdev);
7405 pci_restore_state(pdev);
b94f2d77 7406 pci_save_state(pdev);
9d5c8243 7407
40a914fa
AD		 7408 pci_enable_wake(pdev, PCI_D3hot, 0);
7409 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7410
40a914fa
AD		 7411 igb_reset(adapter);
7412 wr32(E1000_WUS, ~0);
7413 result = PCI_ERS_RESULT_RECOVERED;
7414 }
9d5c8243 7415
ea943d41
JK		 7416 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7417 if (err) {
b980ac18
JK		 7418 dev_err(&pdev->dev,
7419 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7420 err);
ea943d41
JK		 7421 /* non-fatal, continue */
7422 }
40a914fa
AD		 7423
7424 return result;
9d5c8243
AK		 7425}
7426
7427/**
b980ac18
JK		 7428 * igb_io_resume - called when traffic can start flowing again.
7429 * @pdev: Pointer to PCI device
9d5c8243 7430 *
b980ac18
JK		 7431 * This callback is called when the error recovery driver tells us that
7432 * its OK to resume normal operation. Implementation resembles the
7433 * second-half of the igb_resume routine.
9d5c8243
AK		 7434 */
7435static void igb_io_resume(struct pci_dev *pdev)
7436{
7437 struct net_device *netdev = pci_get_drvdata(pdev);
7438 struct igb_adapter *adapter = netdev_priv(netdev);
7439
9d5c8243
AK		 7440 if (netif_running(netdev)) {
7441 if (igb_up(adapter)) {
7442 dev_err(&pdev->dev, "igb_up failed after reset\n");
7443 return;
7444 }
7445 }
7446
7447 netif_device_attach(netdev);
7448
7449 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7450 * driver.
7451 */
9d5c8243 7452 igb_get_hw_control(adapter);
9d5c8243
AK		 7453}
7454
26ad9178 7455static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7456 u8 qsel)
26ad9178
AD		 7457{
7458 u32 rar_low, rar_high;
7459 struct e1000_hw *hw = &adapter->hw;
7460
7461 /* HW expects these in little endian so we reverse the byte order
7462 * from network order (big endian) to little endian
7463 */
7464 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7465 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7466 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7467
7468 /* Indicate to hardware the Address is Valid. */
7469 rar_high |= E1000_RAH_AV;
7470
7471 if (hw->mac.type == e1000_82575)
7472 rar_high |= E1000_RAH_POOL_1 * qsel;
7473 else
7474 rar_high |= E1000_RAH_POOL_1 << qsel;
7475
7476 wr32(E1000_RAL(index), rar_low);
7477 wrfl();
7478 wr32(E1000_RAH(index), rar_high);
7479 wrfl();
7480}
7481
4ae196df 7482static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7483 int vf, unsigned char *mac_addr)
4ae196df
AD		 7484{
7485 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7486 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7487 * towards the first, as a result a collision should not be possible
7488 */
ff41f8dc 7489 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7490
37680117 7491 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7492
26ad9178 7493 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7494
7495 return 0;
7496}
7497
8151d294
WM		 7498static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7499{
7500 struct igb_adapter *adapter = netdev_priv(netdev);
7501 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7502 return -EINVAL;
7503 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7504 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7505 dev_info(&adapter->pdev->dev,
7506 "Reload the VF driver to make this change effective.");
8151d294 7507 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7508 dev_warn(&adapter->pdev->dev,
7509 "The VF MAC address has been set, but the PF device is not up.\n");
7510 dev_warn(&adapter->pdev->dev,
7511 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7512 }
7513 return igb_set_vf_mac(adapter, vf, mac);
7514}
7515
17dc566c
LL		 7516static int igb_link_mbps(int internal_link_speed)
7517{
7518 switch (internal_link_speed) {
7519 case SPEED_100:
7520 return 100;
7521 case SPEED_1000:
7522 return 1000;
7523 default:
7524 return 0;
7525 }
7526}
7527
7528static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7529 int link_speed)
7530{
7531 int rf_dec, rf_int;
7532 u32 bcnrc_val;
7533
7534 if (tx_rate != 0) {
7535 /* Calculate the rate factor values to set */
7536 rf_int = link_speed / tx_rate;
7537 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7538 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7539 tx_rate;
17dc566c
LL		 7540
7541 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7542 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7543 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7544 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7545 } else {
7546 bcnrc_val = 0;
7547 }
7548
7549 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7550 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7551 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7552 */
7553 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7554 wr32(E1000_RTTBCNRC, bcnrc_val);
7555}
7556
7557static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7558{
7559 int actual_link_speed, i;
7560 bool reset_rate = false;
7561
7562 /* VF TX rate limit was not set or not supported */
7563 if ((adapter->vf_rate_link_speed == 0) ||
7564 (adapter->hw.mac.type != e1000_82576))
7565 return;
7566
7567 actual_link_speed = igb_link_mbps(adapter->link_speed);
7568 if (actual_link_speed != adapter->vf_rate_link_speed) {
7569 reset_rate = true;
7570 adapter->vf_rate_link_speed = 0;
7571 dev_info(&adapter->pdev->dev,
b980ac18 7572 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7573 }
7574
7575 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7576 if (reset_rate)
7577 adapter->vf_data[i].tx_rate = 0;
7578
7579 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7580 adapter->vf_data[i].tx_rate,
7581 actual_link_speed);
17dc566c
LL		 7582 }
7583}
7584
8151d294
WM		 7585static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7586{
17dc566c
LL		 7587 struct igb_adapter *adapter = netdev_priv(netdev);
7588 struct e1000_hw *hw = &adapter->hw;
7589 int actual_link_speed;
7590
7591 if (hw->mac.type != e1000_82576)
7592 return -EOPNOTSUPP;
7593
7594 actual_link_speed = igb_link_mbps(adapter->link_speed);
7595 if ((vf >= adapter->vfs_allocated_count) ||
7596 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7597 (tx_rate < 0) || (tx_rate > actual_link_speed))
7598 return -EINVAL;
7599
7600 adapter->vf_rate_link_speed = actual_link_speed;
7601 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7602 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7603
7604 return 0;
8151d294
WM		 7605}
7606
70ea4783
LL		 7607static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7608 bool setting)
7609{
7610 struct igb_adapter *adapter = netdev_priv(netdev);
7611 struct e1000_hw *hw = &adapter->hw;
7612 u32 reg_val, reg_offset;
7613
7614 if (!adapter->vfs_allocated_count)
7615 return -EOPNOTSUPP;
7616
7617 if (vf >= adapter->vfs_allocated_count)
7618 return -EINVAL;
7619
7620 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7621 reg_val = rd32(reg_offset);
7622 if (setting)
7623 reg_val |= ((1 << vf) |
7624 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7625 else
7626 reg_val &= ~((1 << vf) |
7627 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7628 wr32(reg_offset, reg_val);
7629
7630 adapter->vf_data[vf].spoofchk_enabled = setting;
7631 return E1000_SUCCESS;
7632}
7633
8151d294
WM		 7634static int igb_ndo_get_vf_config(struct net_device *netdev,
7635 int vf, struct ifla_vf_info *ivi)
7636{
7637 struct igb_adapter *adapter = netdev_priv(netdev);
7638 if (vf >= adapter->vfs_allocated_count)
7639 return -EINVAL;
7640 ivi->vf = vf;
7641 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7642 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7643 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7644 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7645 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7646 return 0;
7647}
7648
4ae196df
AD		 7649static void igb_vmm_control(struct igb_adapter *adapter)
7650{
7651 struct e1000_hw *hw = &adapter->hw;
10d8e907 7652 u32 reg;
4ae196df 7653
52a1dd4d
AD		 7654 switch (hw->mac.type) {
7655 case e1000_82575:
f96a8a0b
CW		 7656 case e1000_i210:
7657 case e1000_i211:
ceb5f13b 7658 case e1000_i354:
52a1dd4d
AD		 7659 default:
7660 /* replication is not supported for 82575 */
4ae196df 7661 return;
52a1dd4d
AD		 7662 case e1000_82576:
7663 /* notify HW that the MAC is adding vlan tags */
7664 reg = rd32(E1000_DTXCTL);
7665 reg |= E1000_DTXCTL_VLAN_ADDED;
7666 wr32(E1000_DTXCTL, reg);
7667 case e1000_82580:
7668 /* enable replication vlan tag stripping */
7669 reg = rd32(E1000_RPLOLR);
7670 reg |= E1000_RPLOLR_STRVLAN;
7671 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7672 case e1000_i350:
7673 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7674 break;
7675 }
10d8e907 7676
d4960307
AD		 7677 if (adapter->vfs_allocated_count) {
7678 igb_vmdq_set_loopback_pf(hw, true);
7679 igb_vmdq_set_replication_pf(hw, true);
13800469 7680 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7681 adapter->vfs_allocated_count);
d4960307
AD		 7682 } else {
7683 igb_vmdq_set_loopback_pf(hw, false);
7684 igb_vmdq_set_replication_pf(hw, false);
7685 }
4ae196df
AD		 7686}
7687
b6e0c419
CW		 7688static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7689{
7690 struct e1000_hw *hw = &adapter->hw;
7691 u32 dmac_thr;
7692 u16 hwm;
7693
7694 if (hw->mac.type > e1000_82580) {
7695 if (adapter->flags & IGB_FLAG_DMAC) {
7696 u32 reg;
7697
7698 /* force threshold to 0. */
7699 wr32(E1000_DMCTXTH, 0);
7700
b980ac18 7701 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7702 * than the Rx threshold. Set hwm to PBA - max frame
7703 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7704 */
e8c626e9
MV		 7705 hwm = 64 * pba - adapter->max_frame_size / 16;
7706 if (hwm < 64 * (pba - 6))
7707 hwm = 64 * (pba - 6);
7708 reg = rd32(E1000_FCRTC);
7709 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7710 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7711 & E1000_FCRTC_RTH_COAL_MASK);
7712 wr32(E1000_FCRTC, reg);
7713
b980ac18 7714 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7715 * frame size, capping it at PBA - 10KB.
7716 */
7717 dmac_thr = pba - adapter->max_frame_size / 512;
7718 if (dmac_thr < pba - 10)
7719 dmac_thr = pba - 10;
b6e0c419
CW		 7720 reg = rd32(E1000_DMACR);
7721 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7722 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7723 & E1000_DMACR_DMACTHR_MASK);
7724
7725 /* transition to L0x or L1 if available..*/
7726 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7727
7728 /* watchdog timer= +-1000 usec in 32usec intervals */
7729 reg |= (1000 >> 5);
0c02dd98
MV		 7730
7731 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7732 if (hw->mac.type != e1000_i354)
7733 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7734
b6e0c419
CW		 7735 wr32(E1000_DMACR, reg);
7736
b980ac18 7737 /* no lower threshold to disable
b6e0c419
CW		 7738 * coalescing(smart fifb)-UTRESH=0
7739 */
7740 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7741
7742 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7743
7744 wr32(E1000_DMCTLX, reg);
7745
b980ac18 7746 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7747 * DMA coal
7748 */
7749 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7750 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7751
b980ac18 7752 /* make low power state decision controlled
b6e0c419
CW		 7753 * by DMA coal
7754 */
7755 reg = rd32(E1000_PCIEMISC);
7756 reg &= ~E1000_PCIEMISC_LX_DECISION;
7757 wr32(E1000_PCIEMISC, reg);
7758 } /* endif adapter->dmac is not disabled */
7759 } else if (hw->mac.type == e1000_82580) {
7760 u32 reg = rd32(E1000_PCIEMISC);
7761 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7762 wr32(E1000_DMACR, 0);
7763 }
7764}
7765
b980ac18
JK		 7766/**
7767 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7768 * @hw: pointer to hardware structure
7769 * @byte_offset: byte offset to read
7770 * @dev_addr: device address
7771 * @data: value read
7772 *
7773 * Performs byte read operation over I2C interface at
7774 * a specified device address.
b980ac18 7775 **/
441fc6fd 7776s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7777 u8 dev_addr, u8 *data)
441fc6fd
CW		 7778{
7779 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7780 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7781 s32 status;
7782 u16 swfw_mask = 0;
7783
7784 if (!this_client)
7785 return E1000_ERR_I2C;
7786
7787 swfw_mask = E1000_SWFW_PHY0_SM;
7788
7789 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7790 != E1000_SUCCESS)
7791 return E1000_ERR_SWFW_SYNC;
7792
7793 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7794 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7795
7796 if (status < 0)
7797 return E1000_ERR_I2C;
7798 else {
7799 *data = status;
7800 return E1000_SUCCESS;
7801 }
7802}
7803
b980ac18
JK		 7804/**
7805 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7806 * @hw: pointer to hardware structure
7807 * @byte_offset: byte offset to write
7808 * @dev_addr: device address
7809 * @data: value to write
7810 *
7811 * Performs byte write operation over I2C interface at
7812 * a specified device address.
b980ac18 7813 **/
441fc6fd 7814s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7815 u8 dev_addr, u8 data)
441fc6fd
CW		 7816{
7817 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7818 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7819 s32 status;
7820 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7821
7822 if (!this_client)
7823 return E1000_ERR_I2C;
7824
7825 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7826 return E1000_ERR_SWFW_SYNC;
7827 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7828 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7829
7830 if (status)
7831 return E1000_ERR_I2C;
7832 else
7833 return E1000_SUCCESS;
7834
7835}
907b7835
LMV		 7836
7837int igb_reinit_queues(struct igb_adapter *adapter)
7838{
7839 struct net_device *netdev = adapter->netdev;
7840 struct pci_dev *pdev = adapter->pdev;
7841 int err = 0;
7842
7843 if (netif_running(netdev))
7844 igb_close(netdev);
7845
7846 igb_clear_interrupt_scheme(adapter);
7847
7848 if (igb_init_interrupt_scheme(adapter, true)) {
7849 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7850 return -ENOMEM;
7851 }
7852
7853 if (netif_running(netdev))
7854 err = igb_open(netdev);
7855
7856 return err;
7857}
9d5c8243 7858/* igb_main.c */
Linux kernel - Deliverables
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