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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
4297f99b | 4 | Copyright(c) 2007-2011 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/types.h> | |
30 | #include <linux/init.h> | |
b2cb09b1 | 31 | #include <linux/bitops.h> |
9d5c8243 AK |
32 | #include <linux/vmalloc.h> |
33 | #include <linux/pagemap.h> | |
34 | #include <linux/netdevice.h> | |
9d5c8243 | 35 | #include <linux/ipv6.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
9d5c8243 AK |
37 | #include <net/checksum.h> |
38 | #include <net/ip6_checksum.h> | |
c6cb090b | 39 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
40 | #include <linux/mii.h> |
41 | #include <linux/ethtool.h> | |
01789349 | 42 | #include <linux/if.h> |
9d5c8243 AK |
43 | #include <linux/if_vlan.h> |
44 | #include <linux/pci.h> | |
c54106bb | 45 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
46 | #include <linux/delay.h> |
47 | #include <linux/interrupt.h> | |
7d13a7d0 AD |
48 | #include <linux/ip.h> |
49 | #include <linux/tcp.h> | |
50 | #include <linux/sctp.h> | |
9d5c8243 | 51 | #include <linux/if_ether.h> |
40a914fa | 52 | #include <linux/aer.h> |
70c71606 | 53 | #include <linux/prefetch.h> |
421e02f0 | 54 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
55 | #include <linux/dca.h> |
56 | #endif | |
9d5c8243 AK |
57 | #include "igb.h" |
58 | ||
0d1fe82d CW |
59 | #define MAJ 3 |
60 | #define MIN 0 | |
61 | #define BUILD 6 | |
0d1fe82d | 62 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
929dd047 | 63 | __stringify(BUILD) "-k" |
9d5c8243 AK |
64 | char igb_driver_name[] = "igb"; |
65 | char igb_driver_version[] = DRV_VERSION; | |
66 | static const char igb_driver_string[] = | |
67 | "Intel(R) Gigabit Ethernet Network Driver"; | |
4c4b42cb | 68 | static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation."; |
9d5c8243 | 69 | |
9d5c8243 AK |
70 | static const struct e1000_info *igb_info_tbl[] = { |
71 | [board_82575] = &e1000_82575_info, | |
72 | }; | |
73 | ||
a3aa1884 | 74 | static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { |
d2ba2ed8 AD |
75 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, |
76 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, | |
77 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, | |
78 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, | |
55cac248 AD |
79 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, |
80 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, | |
6493d24f | 81 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, |
55cac248 AD |
82 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, |
83 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, | |
84 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, | |
308fb39a JG |
85 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, |
86 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, | |
1b5dda33 GJ |
87 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, |
88 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, | |
2d064c06 | 89 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
9eb2341d | 90 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
747d49ba | 91 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, |
2d064c06 AD |
92 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
93 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
4703bf73 | 94 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
b894fa26 | 95 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, |
c8ea5ea9 | 96 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
9d5c8243 AK |
97 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
98 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
99 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
100 | /* required last entry */ | |
101 | {0, } | |
102 | }; | |
103 | ||
104 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
105 | ||
106 | void igb_reset(struct igb_adapter *); | |
107 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
108 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
109 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
110 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
06cf2666 | 111 | static void igb_setup_mrqc(struct igb_adapter *); |
9d5c8243 AK |
112 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); |
113 | static void __devexit igb_remove(struct pci_dev *pdev); | |
673b8b70 | 114 | static void igb_init_hw_timer(struct igb_adapter *adapter); |
9d5c8243 AK |
115 | static int igb_sw_init(struct igb_adapter *); |
116 | static int igb_open(struct net_device *); | |
117 | static int igb_close(struct net_device *); | |
118 | static void igb_configure_tx(struct igb_adapter *); | |
119 | static void igb_configure_rx(struct igb_adapter *); | |
9d5c8243 AK |
120 | static void igb_clean_all_tx_rings(struct igb_adapter *); |
121 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
122 | static void igb_clean_tx_ring(struct igb_ring *); |
123 | static void igb_clean_rx_ring(struct igb_ring *); | |
ff41f8dc | 124 | static void igb_set_rx_mode(struct net_device *); |
9d5c8243 AK |
125 | static void igb_update_phy_info(unsigned long); |
126 | static void igb_watchdog(unsigned long); | |
127 | static void igb_watchdog_task(struct work_struct *); | |
cd392f5c | 128 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); |
12dcd86b ED |
129 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, |
130 | struct rtnl_link_stats64 *stats); | |
9d5c8243 AK |
131 | static int igb_change_mtu(struct net_device *, int); |
132 | static int igb_set_mac(struct net_device *, void *); | |
68d480c4 | 133 | static void igb_set_uta(struct igb_adapter *adapter); |
9d5c8243 AK |
134 | static irqreturn_t igb_intr(int irq, void *); |
135 | static irqreturn_t igb_intr_msi(int irq, void *); | |
136 | static irqreturn_t igb_msix_other(int irq, void *); | |
047e0030 | 137 | static irqreturn_t igb_msix_ring(int irq, void *); |
421e02f0 | 138 | #ifdef CONFIG_IGB_DCA |
047e0030 | 139 | static void igb_update_dca(struct igb_q_vector *); |
fe4506b6 | 140 | static void igb_setup_dca(struct igb_adapter *); |
421e02f0 | 141 | #endif /* CONFIG_IGB_DCA */ |
661086df | 142 | static int igb_poll(struct napi_struct *, int); |
13fde97a | 143 | static bool igb_clean_tx_irq(struct igb_q_vector *); |
cd392f5c | 144 | static bool igb_clean_rx_irq(struct igb_q_vector *, int); |
9d5c8243 AK |
145 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
146 | static void igb_tx_timeout(struct net_device *); | |
147 | static void igb_reset_task(struct work_struct *); | |
b2cb09b1 | 148 | static void igb_vlan_mode(struct net_device *netdev, u32 features); |
9d5c8243 AK |
149 | static void igb_vlan_rx_add_vid(struct net_device *, u16); |
150 | static void igb_vlan_rx_kill_vid(struct net_device *, u16); | |
151 | static void igb_restore_vlan(struct igb_adapter *); | |
26ad9178 | 152 | static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); |
4ae196df AD |
153 | static void igb_ping_all_vfs(struct igb_adapter *); |
154 | static void igb_msg_task(struct igb_adapter *); | |
4ae196df | 155 | static void igb_vmm_control(struct igb_adapter *); |
f2ca0dbe | 156 | static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
4ae196df | 157 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
8151d294 WM |
158 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); |
159 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
160 | int vf, u16 vlan, u8 qos); | |
161 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); | |
162 | static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, | |
163 | struct ifla_vf_info *ivi); | |
17dc566c | 164 | static void igb_check_vf_rate_limit(struct igb_adapter *); |
9d5c8243 | 165 | |
9d5c8243 | 166 | #ifdef CONFIG_PM |
3fe7c4c9 | 167 | static int igb_suspend(struct pci_dev *, pm_message_t); |
9d5c8243 AK |
168 | static int igb_resume(struct pci_dev *); |
169 | #endif | |
170 | static void igb_shutdown(struct pci_dev *); | |
421e02f0 | 171 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
172 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
173 | static struct notifier_block dca_notifier = { | |
174 | .notifier_call = igb_notify_dca, | |
175 | .next = NULL, | |
176 | .priority = 0 | |
177 | }; | |
178 | #endif | |
9d5c8243 AK |
179 | #ifdef CONFIG_NET_POLL_CONTROLLER |
180 | /* for netdump / net console */ | |
181 | static void igb_netpoll(struct net_device *); | |
182 | #endif | |
37680117 | 183 | #ifdef CONFIG_PCI_IOV |
2a3abf6d AD |
184 | static unsigned int max_vfs = 0; |
185 | module_param(max_vfs, uint, 0); | |
186 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
187 | "per physical function"); | |
188 | #endif /* CONFIG_PCI_IOV */ | |
189 | ||
9d5c8243 AK |
190 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
191 | pci_channel_state_t); | |
192 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
193 | static void igb_io_resume(struct pci_dev *); | |
194 | ||
195 | static struct pci_error_handlers igb_err_handler = { | |
196 | .error_detected = igb_io_error_detected, | |
197 | .slot_reset = igb_io_slot_reset, | |
198 | .resume = igb_io_resume, | |
199 | }; | |
200 | ||
201 | ||
202 | static struct pci_driver igb_driver = { | |
203 | .name = igb_driver_name, | |
204 | .id_table = igb_pci_tbl, | |
205 | .probe = igb_probe, | |
206 | .remove = __devexit_p(igb_remove), | |
207 | #ifdef CONFIG_PM | |
25985edc | 208 | /* Power Management Hooks */ |
9d5c8243 AK |
209 | .suspend = igb_suspend, |
210 | .resume = igb_resume, | |
211 | #endif | |
212 | .shutdown = igb_shutdown, | |
213 | .err_handler = &igb_err_handler | |
214 | }; | |
215 | ||
216 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
217 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
218 | MODULE_LICENSE("GPL"); | |
219 | MODULE_VERSION(DRV_VERSION); | |
220 | ||
c97ec42a TI |
221 | struct igb_reg_info { |
222 | u32 ofs; | |
223 | char *name; | |
224 | }; | |
225 | ||
226 | static const struct igb_reg_info igb_reg_info_tbl[] = { | |
227 | ||
228 | /* General Registers */ | |
229 | {E1000_CTRL, "CTRL"}, | |
230 | {E1000_STATUS, "STATUS"}, | |
231 | {E1000_CTRL_EXT, "CTRL_EXT"}, | |
232 | ||
233 | /* Interrupt Registers */ | |
234 | {E1000_ICR, "ICR"}, | |
235 | ||
236 | /* RX Registers */ | |
237 | {E1000_RCTL, "RCTL"}, | |
238 | {E1000_RDLEN(0), "RDLEN"}, | |
239 | {E1000_RDH(0), "RDH"}, | |
240 | {E1000_RDT(0), "RDT"}, | |
241 | {E1000_RXDCTL(0), "RXDCTL"}, | |
242 | {E1000_RDBAL(0), "RDBAL"}, | |
243 | {E1000_RDBAH(0), "RDBAH"}, | |
244 | ||
245 | /* TX Registers */ | |
246 | {E1000_TCTL, "TCTL"}, | |
247 | {E1000_TDBAL(0), "TDBAL"}, | |
248 | {E1000_TDBAH(0), "TDBAH"}, | |
249 | {E1000_TDLEN(0), "TDLEN"}, | |
250 | {E1000_TDH(0), "TDH"}, | |
251 | {E1000_TDT(0), "TDT"}, | |
252 | {E1000_TXDCTL(0), "TXDCTL"}, | |
253 | {E1000_TDFH, "TDFH"}, | |
254 | {E1000_TDFT, "TDFT"}, | |
255 | {E1000_TDFHS, "TDFHS"}, | |
256 | {E1000_TDFPC, "TDFPC"}, | |
257 | ||
258 | /* List Terminator */ | |
259 | {} | |
260 | }; | |
261 | ||
262 | /* | |
263 | * igb_regdump - register printout routine | |
264 | */ | |
265 | static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) | |
266 | { | |
267 | int n = 0; | |
268 | char rname[16]; | |
269 | u32 regs[8]; | |
270 | ||
271 | switch (reginfo->ofs) { | |
272 | case E1000_RDLEN(0): | |
273 | for (n = 0; n < 4; n++) | |
274 | regs[n] = rd32(E1000_RDLEN(n)); | |
275 | break; | |
276 | case E1000_RDH(0): | |
277 | for (n = 0; n < 4; n++) | |
278 | regs[n] = rd32(E1000_RDH(n)); | |
279 | break; | |
280 | case E1000_RDT(0): | |
281 | for (n = 0; n < 4; n++) | |
282 | regs[n] = rd32(E1000_RDT(n)); | |
283 | break; | |
284 | case E1000_RXDCTL(0): | |
285 | for (n = 0; n < 4; n++) | |
286 | regs[n] = rd32(E1000_RXDCTL(n)); | |
287 | break; | |
288 | case E1000_RDBAL(0): | |
289 | for (n = 0; n < 4; n++) | |
290 | regs[n] = rd32(E1000_RDBAL(n)); | |
291 | break; | |
292 | case E1000_RDBAH(0): | |
293 | for (n = 0; n < 4; n++) | |
294 | regs[n] = rd32(E1000_RDBAH(n)); | |
295 | break; | |
296 | case E1000_TDBAL(0): | |
297 | for (n = 0; n < 4; n++) | |
298 | regs[n] = rd32(E1000_RDBAL(n)); | |
299 | break; | |
300 | case E1000_TDBAH(0): | |
301 | for (n = 0; n < 4; n++) | |
302 | regs[n] = rd32(E1000_TDBAH(n)); | |
303 | break; | |
304 | case E1000_TDLEN(0): | |
305 | for (n = 0; n < 4; n++) | |
306 | regs[n] = rd32(E1000_TDLEN(n)); | |
307 | break; | |
308 | case E1000_TDH(0): | |
309 | for (n = 0; n < 4; n++) | |
310 | regs[n] = rd32(E1000_TDH(n)); | |
311 | break; | |
312 | case E1000_TDT(0): | |
313 | for (n = 0; n < 4; n++) | |
314 | regs[n] = rd32(E1000_TDT(n)); | |
315 | break; | |
316 | case E1000_TXDCTL(0): | |
317 | for (n = 0; n < 4; n++) | |
318 | regs[n] = rd32(E1000_TXDCTL(n)); | |
319 | break; | |
320 | default: | |
321 | printk(KERN_INFO "%-15s %08x\n", | |
322 | reginfo->name, rd32(reginfo->ofs)); | |
323 | return; | |
324 | } | |
325 | ||
326 | snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); | |
327 | printk(KERN_INFO "%-15s ", rname); | |
328 | for (n = 0; n < 4; n++) | |
329 | printk(KERN_CONT "%08x ", regs[n]); | |
330 | printk(KERN_CONT "\n"); | |
331 | } | |
332 | ||
333 | /* | |
334 | * igb_dump - Print registers, tx-rings and rx-rings | |
335 | */ | |
336 | static void igb_dump(struct igb_adapter *adapter) | |
337 | { | |
338 | struct net_device *netdev = adapter->netdev; | |
339 | struct e1000_hw *hw = &adapter->hw; | |
340 | struct igb_reg_info *reginfo; | |
341 | int n = 0; | |
342 | struct igb_ring *tx_ring; | |
343 | union e1000_adv_tx_desc *tx_desc; | |
344 | struct my_u0 { u64 a; u64 b; } *u0; | |
c97ec42a TI |
345 | struct igb_ring *rx_ring; |
346 | union e1000_adv_rx_desc *rx_desc; | |
347 | u32 staterr; | |
348 | int i = 0; | |
349 | ||
350 | if (!netif_msg_hw(adapter)) | |
351 | return; | |
352 | ||
353 | /* Print netdevice Info */ | |
354 | if (netdev) { | |
355 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
356 | printk(KERN_INFO "Device Name state " | |
357 | "trans_start last_rx\n"); | |
358 | printk(KERN_INFO "%-15s %016lX %016lX %016lX\n", | |
359 | netdev->name, | |
360 | netdev->state, | |
361 | netdev->trans_start, | |
362 | netdev->last_rx); | |
363 | } | |
364 | ||
365 | /* Print Registers */ | |
366 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
367 | printk(KERN_INFO " Register Name Value\n"); | |
368 | for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; | |
369 | reginfo->name; reginfo++) { | |
370 | igb_regdump(hw, reginfo); | |
371 | } | |
372 | ||
373 | /* Print TX Ring Summary */ | |
374 | if (!netdev || !netif_running(netdev)) | |
375 | goto exit; | |
376 | ||
377 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
378 | printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ]" | |
379 | " leng ntw timestamp\n"); | |
380 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
06034649 | 381 | struct igb_tx_buffer *buffer_info; |
c97ec42a | 382 | tx_ring = adapter->tx_ring[n]; |
06034649 | 383 | buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
8542db05 | 384 | printk(KERN_INFO " %5d %5X %5X %016llX %04X %p %016llX\n", |
c97ec42a TI |
385 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
386 | (u64)buffer_info->dma, | |
387 | buffer_info->length, | |
388 | buffer_info->next_to_watch, | |
389 | (u64)buffer_info->time_stamp); | |
390 | } | |
391 | ||
392 | /* Print TX Rings */ | |
393 | if (!netif_msg_tx_done(adapter)) | |
394 | goto rx_ring_summary; | |
395 | ||
396 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
397 | ||
398 | /* Transmit Descriptor Formats | |
399 | * | |
400 | * Advanced Transmit Descriptor | |
401 | * +--------------------------------------------------------------+ | |
402 | * 0 | Buffer Address [63:0] | | |
403 | * +--------------------------------------------------------------+ | |
404 | * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | | |
405 | * +--------------------------------------------------------------+ | |
406 | * 63 46 45 40 39 38 36 35 32 31 24 15 0 | |
407 | */ | |
408 | ||
409 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
410 | tx_ring = adapter->tx_ring[n]; | |
411 | printk(KERN_INFO "------------------------------------\n"); | |
412 | printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
413 | printk(KERN_INFO "------------------------------------\n"); | |
414 | printk(KERN_INFO "T [desc] [address 63:0 ] " | |
415 | "[PlPOCIStDDM Ln] [bi->dma ] " | |
416 | "leng ntw timestamp bi->skb\n"); | |
417 | ||
418 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
06034649 | 419 | struct igb_tx_buffer *buffer_info; |
60136906 | 420 | tx_desc = IGB_TX_DESC(tx_ring, i); |
06034649 | 421 | buffer_info = &tx_ring->tx_buffer_info[i]; |
c97ec42a TI |
422 | u0 = (struct my_u0 *)tx_desc; |
423 | printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX" | |
8542db05 | 424 | " %04X %p %016llX %p", i, |
c97ec42a TI |
425 | le64_to_cpu(u0->a), |
426 | le64_to_cpu(u0->b), | |
427 | (u64)buffer_info->dma, | |
428 | buffer_info->length, | |
429 | buffer_info->next_to_watch, | |
430 | (u64)buffer_info->time_stamp, | |
431 | buffer_info->skb); | |
432 | if (i == tx_ring->next_to_use && | |
433 | i == tx_ring->next_to_clean) | |
434 | printk(KERN_CONT " NTC/U\n"); | |
435 | else if (i == tx_ring->next_to_use) | |
436 | printk(KERN_CONT " NTU\n"); | |
437 | else if (i == tx_ring->next_to_clean) | |
438 | printk(KERN_CONT " NTC\n"); | |
439 | else | |
440 | printk(KERN_CONT "\n"); | |
441 | ||
442 | if (netif_msg_pktdata(adapter) && buffer_info->dma != 0) | |
443 | print_hex_dump(KERN_INFO, "", | |
444 | DUMP_PREFIX_ADDRESS, | |
445 | 16, 1, phys_to_virt(buffer_info->dma), | |
446 | buffer_info->length, true); | |
447 | } | |
448 | } | |
449 | ||
450 | /* Print RX Rings Summary */ | |
451 | rx_ring_summary: | |
452 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
453 | printk(KERN_INFO "Queue [NTU] [NTC]\n"); | |
454 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
455 | rx_ring = adapter->rx_ring[n]; | |
456 | printk(KERN_INFO " %5d %5X %5X\n", n, | |
457 | rx_ring->next_to_use, rx_ring->next_to_clean); | |
458 | } | |
459 | ||
460 | /* Print RX Rings */ | |
461 | if (!netif_msg_rx_status(adapter)) | |
462 | goto exit; | |
463 | ||
464 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
465 | ||
466 | /* Advanced Receive Descriptor (Read) Format | |
467 | * 63 1 0 | |
468 | * +-----------------------------------------------------+ | |
469 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
470 | * +----------------------------------------------+------+ | |
471 | * 8 | Header Buffer Address [63:1] | DD | | |
472 | * +-----------------------------------------------------+ | |
473 | * | |
474 | * | |
475 | * Advanced Receive Descriptor (Write-Back) Format | |
476 | * | |
477 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
478 | * +------------------------------------------------------+ | |
479 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
480 | * | Checksum Ident | | | | Type | Type | | |
481 | * +------------------------------------------------------+ | |
482 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
483 | * +------------------------------------------------------+ | |
484 | * 63 48 47 32 31 20 19 0 | |
485 | */ | |
486 | ||
487 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
488 | rx_ring = adapter->rx_ring[n]; | |
489 | printk(KERN_INFO "------------------------------------\n"); | |
490 | printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
491 | printk(KERN_INFO "------------------------------------\n"); | |
492 | printk(KERN_INFO "R [desc] [ PktBuf A0] " | |
493 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " | |
494 | "<-- Adv Rx Read format\n"); | |
495 | printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] " | |
496 | "[vl er S cks ln] ---------------- [bi->skb] " | |
497 | "<-- Adv Rx Write-Back format\n"); | |
498 | ||
499 | for (i = 0; i < rx_ring->count; i++) { | |
06034649 AD |
500 | struct igb_rx_buffer *buffer_info; |
501 | buffer_info = &rx_ring->rx_buffer_info[i]; | |
60136906 | 502 | rx_desc = IGB_RX_DESC(rx_ring, i); |
c97ec42a TI |
503 | u0 = (struct my_u0 *)rx_desc; |
504 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
505 | if (staterr & E1000_RXD_STAT_DD) { | |
506 | /* Descriptor Done */ | |
507 | printk(KERN_INFO "RWB[0x%03X] %016llX " | |
508 | "%016llX ---------------- %p", i, | |
509 | le64_to_cpu(u0->a), | |
510 | le64_to_cpu(u0->b), | |
511 | buffer_info->skb); | |
512 | } else { | |
513 | printk(KERN_INFO "R [0x%03X] %016llX " | |
514 | "%016llX %016llX %p", i, | |
515 | le64_to_cpu(u0->a), | |
516 | le64_to_cpu(u0->b), | |
517 | (u64)buffer_info->dma, | |
518 | buffer_info->skb); | |
519 | ||
520 | if (netif_msg_pktdata(adapter)) { | |
521 | print_hex_dump(KERN_INFO, "", | |
522 | DUMP_PREFIX_ADDRESS, | |
523 | 16, 1, | |
524 | phys_to_virt(buffer_info->dma), | |
44390ca6 AD |
525 | IGB_RX_HDR_LEN, true); |
526 | print_hex_dump(KERN_INFO, "", | |
527 | DUMP_PREFIX_ADDRESS, | |
528 | 16, 1, | |
529 | phys_to_virt( | |
530 | buffer_info->page_dma + | |
531 | buffer_info->page_offset), | |
532 | PAGE_SIZE/2, true); | |
c97ec42a TI |
533 | } |
534 | } | |
535 | ||
536 | if (i == rx_ring->next_to_use) | |
537 | printk(KERN_CONT " NTU\n"); | |
538 | else if (i == rx_ring->next_to_clean) | |
539 | printk(KERN_CONT " NTC\n"); | |
540 | else | |
541 | printk(KERN_CONT "\n"); | |
542 | ||
543 | } | |
544 | } | |
545 | ||
546 | exit: | |
547 | return; | |
548 | } | |
549 | ||
550 | ||
38c845c7 PO |
551 | /** |
552 | * igb_read_clock - read raw cycle counter (to be used by time counter) | |
553 | */ | |
554 | static cycle_t igb_read_clock(const struct cyclecounter *tc) | |
555 | { | |
556 | struct igb_adapter *adapter = | |
557 | container_of(tc, struct igb_adapter, cycles); | |
558 | struct e1000_hw *hw = &adapter->hw; | |
c5b9bd5e AD |
559 | u64 stamp = 0; |
560 | int shift = 0; | |
38c845c7 | 561 | |
55cac248 AD |
562 | /* |
563 | * The timestamp latches on lowest register read. For the 82580 | |
564 | * the lowest register is SYSTIMR instead of SYSTIML. However we never | |
565 | * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it. | |
566 | */ | |
567 | if (hw->mac.type == e1000_82580) { | |
568 | stamp = rd32(E1000_SYSTIMR) >> 8; | |
569 | shift = IGB_82580_TSYNC_SHIFT; | |
570 | } | |
571 | ||
c5b9bd5e AD |
572 | stamp |= (u64)rd32(E1000_SYSTIML) << shift; |
573 | stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32); | |
38c845c7 PO |
574 | return stamp; |
575 | } | |
576 | ||
9d5c8243 | 577 | /** |
c041076a | 578 | * igb_get_hw_dev - return device |
9d5c8243 AK |
579 | * used by hardware layer to print debugging information |
580 | **/ | |
c041076a | 581 | struct net_device *igb_get_hw_dev(struct e1000_hw *hw) |
9d5c8243 AK |
582 | { |
583 | struct igb_adapter *adapter = hw->back; | |
c041076a | 584 | return adapter->netdev; |
9d5c8243 | 585 | } |
38c845c7 | 586 | |
9d5c8243 AK |
587 | /** |
588 | * igb_init_module - Driver Registration Routine | |
589 | * | |
590 | * igb_init_module is the first routine called when the driver is | |
591 | * loaded. All it does is register with the PCI subsystem. | |
592 | **/ | |
593 | static int __init igb_init_module(void) | |
594 | { | |
595 | int ret; | |
596 | printk(KERN_INFO "%s - version %s\n", | |
597 | igb_driver_string, igb_driver_version); | |
598 | ||
599 | printk(KERN_INFO "%s\n", igb_copyright); | |
600 | ||
421e02f0 | 601 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
602 | dca_register_notify(&dca_notifier); |
603 | #endif | |
bbd98fe4 | 604 | ret = pci_register_driver(&igb_driver); |
9d5c8243 AK |
605 | return ret; |
606 | } | |
607 | ||
608 | module_init(igb_init_module); | |
609 | ||
610 | /** | |
611 | * igb_exit_module - Driver Exit Cleanup Routine | |
612 | * | |
613 | * igb_exit_module is called just before the driver is removed | |
614 | * from memory. | |
615 | **/ | |
616 | static void __exit igb_exit_module(void) | |
617 | { | |
421e02f0 | 618 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
619 | dca_unregister_notify(&dca_notifier); |
620 | #endif | |
9d5c8243 AK |
621 | pci_unregister_driver(&igb_driver); |
622 | } | |
623 | ||
624 | module_exit(igb_exit_module); | |
625 | ||
26bc19ec AD |
626 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
627 | /** | |
628 | * igb_cache_ring_register - Descriptor ring to register mapping | |
629 | * @adapter: board private structure to initialize | |
630 | * | |
631 | * Once we know the feature-set enabled for the device, we'll cache | |
632 | * the register offset the descriptor ring is assigned to. | |
633 | **/ | |
634 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
635 | { | |
ee1b9f06 | 636 | int i = 0, j = 0; |
047e0030 | 637 | u32 rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
638 | |
639 | switch (adapter->hw.mac.type) { | |
640 | case e1000_82576: | |
641 | /* The queues are allocated for virtualization such that VF 0 | |
642 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
643 | * In order to avoid collision we start at the first free queue | |
644 | * and continue consuming queues in the same sequence | |
645 | */ | |
ee1b9f06 | 646 | if (adapter->vfs_allocated_count) { |
a99955fc | 647 | for (; i < adapter->rss_queues; i++) |
3025a446 AD |
648 | adapter->rx_ring[i]->reg_idx = rbase_offset + |
649 | Q_IDX_82576(i); | |
ee1b9f06 | 650 | } |
26bc19ec | 651 | case e1000_82575: |
55cac248 | 652 | case e1000_82580: |
d2ba2ed8 | 653 | case e1000_i350: |
26bc19ec | 654 | default: |
ee1b9f06 | 655 | for (; i < adapter->num_rx_queues; i++) |
3025a446 | 656 | adapter->rx_ring[i]->reg_idx = rbase_offset + i; |
ee1b9f06 | 657 | for (; j < adapter->num_tx_queues; j++) |
3025a446 | 658 | adapter->tx_ring[j]->reg_idx = rbase_offset + j; |
26bc19ec AD |
659 | break; |
660 | } | |
661 | } | |
662 | ||
047e0030 AD |
663 | static void igb_free_queues(struct igb_adapter *adapter) |
664 | { | |
3025a446 | 665 | int i; |
047e0030 | 666 | |
3025a446 AD |
667 | for (i = 0; i < adapter->num_tx_queues; i++) { |
668 | kfree(adapter->tx_ring[i]); | |
669 | adapter->tx_ring[i] = NULL; | |
670 | } | |
671 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
672 | kfree(adapter->rx_ring[i]); | |
673 | adapter->rx_ring[i] = NULL; | |
674 | } | |
047e0030 AD |
675 | adapter->num_rx_queues = 0; |
676 | adapter->num_tx_queues = 0; | |
677 | } | |
678 | ||
9d5c8243 AK |
679 | /** |
680 | * igb_alloc_queues - Allocate memory for all rings | |
681 | * @adapter: board private structure to initialize | |
682 | * | |
683 | * We allocate one ring per queue at run-time since we don't know the | |
684 | * number of queues at compile-time. | |
685 | **/ | |
686 | static int igb_alloc_queues(struct igb_adapter *adapter) | |
687 | { | |
3025a446 | 688 | struct igb_ring *ring; |
9d5c8243 AK |
689 | int i; |
690 | ||
661086df | 691 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 AD |
692 | ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); |
693 | if (!ring) | |
694 | goto err; | |
68fd9910 | 695 | ring->count = adapter->tx_ring_count; |
661086df | 696 | ring->queue_index = i; |
59d71989 | 697 | ring->dev = &adapter->pdev->dev; |
e694e964 | 698 | ring->netdev = adapter->netdev; |
85ad76b2 AD |
699 | /* For 82575, context index must be unique per ring. */ |
700 | if (adapter->hw.mac.type == e1000_82575) | |
701 | ring->flags = IGB_RING_FLAG_TX_CTX_IDX; | |
3025a446 | 702 | adapter->tx_ring[i] = ring; |
661086df | 703 | } |
85ad76b2 | 704 | |
9d5c8243 | 705 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3025a446 AD |
706 | ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); |
707 | if (!ring) | |
708 | goto err; | |
68fd9910 | 709 | ring->count = adapter->rx_ring_count; |
844290e5 | 710 | ring->queue_index = i; |
59d71989 | 711 | ring->dev = &adapter->pdev->dev; |
e694e964 | 712 | ring->netdev = adapter->netdev; |
85ad76b2 AD |
713 | ring->flags = IGB_RING_FLAG_RX_CSUM; /* enable rx checksum */ |
714 | /* set flag indicating ring supports SCTP checksum offload */ | |
715 | if (adapter->hw.mac.type >= e1000_82576) | |
716 | ring->flags |= IGB_RING_FLAG_RX_SCTP_CSUM; | |
3025a446 | 717 | adapter->rx_ring[i] = ring; |
9d5c8243 | 718 | } |
26bc19ec AD |
719 | |
720 | igb_cache_ring_register(adapter); | |
9d5c8243 | 721 | |
047e0030 | 722 | return 0; |
a88f10ec | 723 | |
047e0030 AD |
724 | err: |
725 | igb_free_queues(adapter); | |
d1a8c9e1 | 726 | |
047e0030 | 727 | return -ENOMEM; |
a88f10ec AD |
728 | } |
729 | ||
9d5c8243 | 730 | #define IGB_N0_QUEUE -1 |
047e0030 | 731 | static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
9d5c8243 AK |
732 | { |
733 | u32 msixbm = 0; | |
047e0030 | 734 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 735 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 | 736 | u32 ivar, index; |
047e0030 AD |
737 | int rx_queue = IGB_N0_QUEUE; |
738 | int tx_queue = IGB_N0_QUEUE; | |
739 | ||
740 | if (q_vector->rx_ring) | |
741 | rx_queue = q_vector->rx_ring->reg_idx; | |
742 | if (q_vector->tx_ring) | |
743 | tx_queue = q_vector->tx_ring->reg_idx; | |
2d064c06 AD |
744 | |
745 | switch (hw->mac.type) { | |
746 | case e1000_82575: | |
9d5c8243 AK |
747 | /* The 82575 assigns vectors using a bitmask, which matches the |
748 | bitmask for the EICR/EIMS/EIMC registers. To assign one | |
749 | or more queues to a vector, we write the appropriate bits | |
750 | into the MSIXBM register for that vector. */ | |
047e0030 | 751 | if (rx_queue > IGB_N0_QUEUE) |
9d5c8243 | 752 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
047e0030 | 753 | if (tx_queue > IGB_N0_QUEUE) |
9d5c8243 | 754 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
feeb2721 AD |
755 | if (!adapter->msix_entries && msix_vector == 0) |
756 | msixbm |= E1000_EIMS_OTHER; | |
9d5c8243 | 757 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
047e0030 | 758 | q_vector->eims_value = msixbm; |
2d064c06 AD |
759 | break; |
760 | case e1000_82576: | |
26bc19ec | 761 | /* 82576 uses a table-based method for assigning vectors. |
2d064c06 AD |
762 | Each queue has a single entry in the table to which we write |
763 | a vector number along with a "valid" bit. Sadly, the layout | |
764 | of the table is somewhat counterintuitive. */ | |
765 | if (rx_queue > IGB_N0_QUEUE) { | |
047e0030 | 766 | index = (rx_queue & 0x7); |
2d064c06 | 767 | ivar = array_rd32(E1000_IVAR0, index); |
047e0030 | 768 | if (rx_queue < 8) { |
26bc19ec AD |
769 | /* vector goes into low byte of register */ |
770 | ivar = ivar & 0xFFFFFF00; | |
771 | ivar |= msix_vector | E1000_IVAR_VALID; | |
047e0030 AD |
772 | } else { |
773 | /* vector goes into third byte of register */ | |
774 | ivar = ivar & 0xFF00FFFF; | |
775 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
2d064c06 | 776 | } |
2d064c06 AD |
777 | array_wr32(E1000_IVAR0, index, ivar); |
778 | } | |
779 | if (tx_queue > IGB_N0_QUEUE) { | |
047e0030 | 780 | index = (tx_queue & 0x7); |
2d064c06 | 781 | ivar = array_rd32(E1000_IVAR0, index); |
047e0030 | 782 | if (tx_queue < 8) { |
26bc19ec AD |
783 | /* vector goes into second byte of register */ |
784 | ivar = ivar & 0xFFFF00FF; | |
785 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
047e0030 AD |
786 | } else { |
787 | /* vector goes into high byte of register */ | |
788 | ivar = ivar & 0x00FFFFFF; | |
789 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
2d064c06 | 790 | } |
2d064c06 AD |
791 | array_wr32(E1000_IVAR0, index, ivar); |
792 | } | |
047e0030 | 793 | q_vector->eims_value = 1 << msix_vector; |
2d064c06 | 794 | break; |
55cac248 | 795 | case e1000_82580: |
d2ba2ed8 | 796 | case e1000_i350: |
55cac248 AD |
797 | /* 82580 uses the same table-based approach as 82576 but has fewer |
798 | entries as a result we carry over for queues greater than 4. */ | |
799 | if (rx_queue > IGB_N0_QUEUE) { | |
800 | index = (rx_queue >> 1); | |
801 | ivar = array_rd32(E1000_IVAR0, index); | |
802 | if (rx_queue & 0x1) { | |
803 | /* vector goes into third byte of register */ | |
804 | ivar = ivar & 0xFF00FFFF; | |
805 | ivar |= (msix_vector | E1000_IVAR_VALID) << 16; | |
806 | } else { | |
807 | /* vector goes into low byte of register */ | |
808 | ivar = ivar & 0xFFFFFF00; | |
809 | ivar |= msix_vector | E1000_IVAR_VALID; | |
810 | } | |
811 | array_wr32(E1000_IVAR0, index, ivar); | |
812 | } | |
813 | if (tx_queue > IGB_N0_QUEUE) { | |
814 | index = (tx_queue >> 1); | |
815 | ivar = array_rd32(E1000_IVAR0, index); | |
816 | if (tx_queue & 0x1) { | |
817 | /* vector goes into high byte of register */ | |
818 | ivar = ivar & 0x00FFFFFF; | |
819 | ivar |= (msix_vector | E1000_IVAR_VALID) << 24; | |
820 | } else { | |
821 | /* vector goes into second byte of register */ | |
822 | ivar = ivar & 0xFFFF00FF; | |
823 | ivar |= (msix_vector | E1000_IVAR_VALID) << 8; | |
824 | } | |
825 | array_wr32(E1000_IVAR0, index, ivar); | |
826 | } | |
827 | q_vector->eims_value = 1 << msix_vector; | |
828 | break; | |
2d064c06 AD |
829 | default: |
830 | BUG(); | |
831 | break; | |
832 | } | |
26b39276 AD |
833 | |
834 | /* add q_vector eims value to global eims_enable_mask */ | |
835 | adapter->eims_enable_mask |= q_vector->eims_value; | |
836 | ||
837 | /* configure q_vector to set itr on first interrupt */ | |
838 | q_vector->set_itr = 1; | |
9d5c8243 AK |
839 | } |
840 | ||
841 | /** | |
842 | * igb_configure_msix - Configure MSI-X hardware | |
843 | * | |
844 | * igb_configure_msix sets up the hardware to properly | |
845 | * generate MSI-X interrupts. | |
846 | **/ | |
847 | static void igb_configure_msix(struct igb_adapter *adapter) | |
848 | { | |
849 | u32 tmp; | |
850 | int i, vector = 0; | |
851 | struct e1000_hw *hw = &adapter->hw; | |
852 | ||
853 | adapter->eims_enable_mask = 0; | |
9d5c8243 AK |
854 | |
855 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
856 | switch (hw->mac.type) { |
857 | case e1000_82575: | |
9d5c8243 AK |
858 | tmp = rd32(E1000_CTRL_EXT); |
859 | /* enable MSI-X PBA support*/ | |
860 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
861 | ||
862 | /* Auto-Mask interrupts upon ICR read. */ | |
863 | tmp |= E1000_CTRL_EXT_EIAME; | |
864 | tmp |= E1000_CTRL_EXT_IRCA; | |
865 | ||
866 | wr32(E1000_CTRL_EXT, tmp); | |
047e0030 AD |
867 | |
868 | /* enable msix_other interrupt */ | |
869 | array_wr32(E1000_MSIXBM(0), vector++, | |
870 | E1000_EIMS_OTHER); | |
844290e5 | 871 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 872 | |
2d064c06 AD |
873 | break; |
874 | ||
875 | case e1000_82576: | |
55cac248 | 876 | case e1000_82580: |
d2ba2ed8 | 877 | case e1000_i350: |
047e0030 AD |
878 | /* Turn on MSI-X capability first, or our settings |
879 | * won't stick. And it will take days to debug. */ | |
880 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | | |
881 | E1000_GPIE_PBA | E1000_GPIE_EIAME | | |
882 | E1000_GPIE_NSICR); | |
883 | ||
884 | /* enable msix_other interrupt */ | |
885 | adapter->eims_other = 1 << vector; | |
2d064c06 | 886 | tmp = (vector++ | E1000_IVAR_VALID) << 8; |
2d064c06 | 887 | |
047e0030 | 888 | wr32(E1000_IVAR_MISC, tmp); |
2d064c06 AD |
889 | break; |
890 | default: | |
891 | /* do nothing, since nothing else supports MSI-X */ | |
892 | break; | |
893 | } /* switch (hw->mac.type) */ | |
047e0030 AD |
894 | |
895 | adapter->eims_enable_mask |= adapter->eims_other; | |
896 | ||
26b39276 AD |
897 | for (i = 0; i < adapter->num_q_vectors; i++) |
898 | igb_assign_vector(adapter->q_vector[i], vector++); | |
047e0030 | 899 | |
9d5c8243 AK |
900 | wrfl(); |
901 | } | |
902 | ||
903 | /** | |
904 | * igb_request_msix - Initialize MSI-X interrupts | |
905 | * | |
906 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the | |
907 | * kernel. | |
908 | **/ | |
909 | static int igb_request_msix(struct igb_adapter *adapter) | |
910 | { | |
911 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 912 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
913 | int i, err = 0, vector = 0; |
914 | ||
047e0030 | 915 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 916 | igb_msix_other, 0, netdev->name, adapter); |
047e0030 AD |
917 | if (err) |
918 | goto out; | |
919 | vector++; | |
920 | ||
921 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
922 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
923 | ||
924 | q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); | |
925 | ||
926 | if (q_vector->rx_ring && q_vector->tx_ring) | |
927 | sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, | |
928 | q_vector->rx_ring->queue_index); | |
929 | else if (q_vector->tx_ring) | |
930 | sprintf(q_vector->name, "%s-tx-%u", netdev->name, | |
931 | q_vector->tx_ring->queue_index); | |
932 | else if (q_vector->rx_ring) | |
933 | sprintf(q_vector->name, "%s-rx-%u", netdev->name, | |
934 | q_vector->rx_ring->queue_index); | |
9d5c8243 | 935 | else |
047e0030 AD |
936 | sprintf(q_vector->name, "%s-unused", netdev->name); |
937 | ||
9d5c8243 | 938 | err = request_irq(adapter->msix_entries[vector].vector, |
a0607fd3 | 939 | igb_msix_ring, 0, q_vector->name, |
047e0030 | 940 | q_vector); |
9d5c8243 AK |
941 | if (err) |
942 | goto out; | |
9d5c8243 AK |
943 | vector++; |
944 | } | |
945 | ||
9d5c8243 AK |
946 | igb_configure_msix(adapter); |
947 | return 0; | |
948 | out: | |
949 | return err; | |
950 | } | |
951 | ||
952 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
953 | { | |
954 | if (adapter->msix_entries) { | |
955 | pci_disable_msix(adapter->pdev); | |
956 | kfree(adapter->msix_entries); | |
957 | adapter->msix_entries = NULL; | |
047e0030 | 958 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 959 | pci_disable_msi(adapter->pdev); |
047e0030 | 960 | } |
9d5c8243 AK |
961 | } |
962 | ||
047e0030 AD |
963 | /** |
964 | * igb_free_q_vectors - Free memory allocated for interrupt vectors | |
965 | * @adapter: board private structure to initialize | |
966 | * | |
967 | * This function frees the memory allocated to the q_vectors. In addition if | |
968 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
969 | * to freeing the q_vector. | |
970 | **/ | |
971 | static void igb_free_q_vectors(struct igb_adapter *adapter) | |
972 | { | |
973 | int v_idx; | |
974 | ||
975 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { | |
976 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | |
977 | adapter->q_vector[v_idx] = NULL; | |
fe0592b4 NN |
978 | if (!q_vector) |
979 | continue; | |
047e0030 AD |
980 | netif_napi_del(&q_vector->napi); |
981 | kfree(q_vector); | |
982 | } | |
983 | adapter->num_q_vectors = 0; | |
984 | } | |
985 | ||
986 | /** | |
987 | * igb_clear_interrupt_scheme - reset the device to a state of no interrupts | |
988 | * | |
989 | * This function resets the device so that it has 0 rx queues, tx queues, and | |
990 | * MSI-X interrupts allocated. | |
991 | */ | |
992 | static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) | |
993 | { | |
994 | igb_free_queues(adapter); | |
995 | igb_free_q_vectors(adapter); | |
996 | igb_reset_interrupt_capability(adapter); | |
997 | } | |
9d5c8243 AK |
998 | |
999 | /** | |
1000 | * igb_set_interrupt_capability - set MSI or MSI-X if supported | |
1001 | * | |
1002 | * Attempt to configure interrupts using the best available | |
1003 | * capabilities of the hardware and kernel. | |
1004 | **/ | |
21adef3e | 1005 | static int igb_set_interrupt_capability(struct igb_adapter *adapter) |
9d5c8243 AK |
1006 | { |
1007 | int err; | |
1008 | int numvecs, i; | |
1009 | ||
83b7180d | 1010 | /* Number of supported queues. */ |
a99955fc | 1011 | adapter->num_rx_queues = adapter->rss_queues; |
5fa8517f GR |
1012 | if (adapter->vfs_allocated_count) |
1013 | adapter->num_tx_queues = 1; | |
1014 | else | |
1015 | adapter->num_tx_queues = adapter->rss_queues; | |
83b7180d | 1016 | |
047e0030 AD |
1017 | /* start with one vector for every rx queue */ |
1018 | numvecs = adapter->num_rx_queues; | |
1019 | ||
3ad2f3fb | 1020 | /* if tx handler is separate add 1 for every tx queue */ |
a99955fc AD |
1021 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) |
1022 | numvecs += adapter->num_tx_queues; | |
047e0030 AD |
1023 | |
1024 | /* store the number of vectors reserved for queues */ | |
1025 | adapter->num_q_vectors = numvecs; | |
1026 | ||
1027 | /* add 1 vector for link status interrupts */ | |
1028 | numvecs++; | |
9d5c8243 AK |
1029 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), |
1030 | GFP_KERNEL); | |
1031 | if (!adapter->msix_entries) | |
1032 | goto msi_only; | |
1033 | ||
1034 | for (i = 0; i < numvecs; i++) | |
1035 | adapter->msix_entries[i].entry = i; | |
1036 | ||
1037 | err = pci_enable_msix(adapter->pdev, | |
1038 | adapter->msix_entries, | |
1039 | numvecs); | |
1040 | if (err == 0) | |
34a20e89 | 1041 | goto out; |
9d5c8243 AK |
1042 | |
1043 | igb_reset_interrupt_capability(adapter); | |
1044 | ||
1045 | /* If we can't do MSI-X, try MSI */ | |
1046 | msi_only: | |
2a3abf6d AD |
1047 | #ifdef CONFIG_PCI_IOV |
1048 | /* disable SR-IOV for non MSI-X configurations */ | |
1049 | if (adapter->vf_data) { | |
1050 | struct e1000_hw *hw = &adapter->hw; | |
1051 | /* disable iov and allow time for transactions to clear */ | |
1052 | pci_disable_sriov(adapter->pdev); | |
1053 | msleep(500); | |
1054 | ||
1055 | kfree(adapter->vf_data); | |
1056 | adapter->vf_data = NULL; | |
1057 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
945a5151 | 1058 | wrfl(); |
2a3abf6d AD |
1059 | msleep(100); |
1060 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); | |
1061 | } | |
1062 | #endif | |
4fc82adf | 1063 | adapter->vfs_allocated_count = 0; |
a99955fc | 1064 | adapter->rss_queues = 1; |
4fc82adf | 1065 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
9d5c8243 | 1066 | adapter->num_rx_queues = 1; |
661086df | 1067 | adapter->num_tx_queues = 1; |
047e0030 | 1068 | adapter->num_q_vectors = 1; |
9d5c8243 | 1069 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 1070 | adapter->flags |= IGB_FLAG_HAS_MSI; |
34a20e89 | 1071 | out: |
21adef3e BH |
1072 | /* Notify the stack of the (possibly) reduced queue counts. */ |
1073 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); | |
1074 | return netif_set_real_num_rx_queues(adapter->netdev, | |
1075 | adapter->num_rx_queues); | |
9d5c8243 AK |
1076 | } |
1077 | ||
047e0030 AD |
1078 | /** |
1079 | * igb_alloc_q_vectors - Allocate memory for interrupt vectors | |
1080 | * @adapter: board private structure to initialize | |
1081 | * | |
1082 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
1083 | * return -ENOMEM. | |
1084 | **/ | |
1085 | static int igb_alloc_q_vectors(struct igb_adapter *adapter) | |
1086 | { | |
1087 | struct igb_q_vector *q_vector; | |
1088 | struct e1000_hw *hw = &adapter->hw; | |
1089 | int v_idx; | |
1090 | ||
1091 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { | |
1092 | q_vector = kzalloc(sizeof(struct igb_q_vector), GFP_KERNEL); | |
1093 | if (!q_vector) | |
1094 | goto err_out; | |
1095 | q_vector->adapter = adapter; | |
047e0030 AD |
1096 | q_vector->itr_register = hw->hw_addr + E1000_EITR(0); |
1097 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
1098 | netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64); |
1099 | adapter->q_vector[v_idx] = q_vector; | |
1100 | } | |
1101 | return 0; | |
1102 | ||
1103 | err_out: | |
fe0592b4 | 1104 | igb_free_q_vectors(adapter); |
047e0030 AD |
1105 | return -ENOMEM; |
1106 | } | |
1107 | ||
1108 | static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter, | |
1109 | int ring_idx, int v_idx) | |
1110 | { | |
3025a446 | 1111 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; |
047e0030 | 1112 | |
3025a446 | 1113 | q_vector->rx_ring = adapter->rx_ring[ring_idx]; |
047e0030 | 1114 | q_vector->rx_ring->q_vector = q_vector; |
4fc82adf AD |
1115 | q_vector->itr_val = adapter->rx_itr_setting; |
1116 | if (q_vector->itr_val && q_vector->itr_val <= 3) | |
1117 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
1118 | } |
1119 | ||
1120 | static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter, | |
1121 | int ring_idx, int v_idx) | |
1122 | { | |
3025a446 | 1123 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; |
047e0030 | 1124 | |
3025a446 | 1125 | q_vector->tx_ring = adapter->tx_ring[ring_idx]; |
047e0030 | 1126 | q_vector->tx_ring->q_vector = q_vector; |
4fc82adf | 1127 | q_vector->itr_val = adapter->tx_itr_setting; |
13fde97a | 1128 | q_vector->tx_work_limit = adapter->tx_work_limit; |
4fc82adf AD |
1129 | if (q_vector->itr_val && q_vector->itr_val <= 3) |
1130 | q_vector->itr_val = IGB_START_ITR; | |
047e0030 AD |
1131 | } |
1132 | ||
1133 | /** | |
1134 | * igb_map_ring_to_vector - maps allocated queues to vectors | |
1135 | * | |
1136 | * This function maps the recently allocated queues to vectors. | |
1137 | **/ | |
1138 | static int igb_map_ring_to_vector(struct igb_adapter *adapter) | |
1139 | { | |
1140 | int i; | |
1141 | int v_idx = 0; | |
1142 | ||
1143 | if ((adapter->num_q_vectors < adapter->num_rx_queues) || | |
1144 | (adapter->num_q_vectors < adapter->num_tx_queues)) | |
1145 | return -ENOMEM; | |
1146 | ||
1147 | if (adapter->num_q_vectors >= | |
1148 | (adapter->num_rx_queues + adapter->num_tx_queues)) { | |
1149 | for (i = 0; i < adapter->num_rx_queues; i++) | |
1150 | igb_map_rx_ring_to_vector(adapter, i, v_idx++); | |
1151 | for (i = 0; i < adapter->num_tx_queues; i++) | |
1152 | igb_map_tx_ring_to_vector(adapter, i, v_idx++); | |
1153 | } else { | |
1154 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1155 | if (i < adapter->num_tx_queues) | |
1156 | igb_map_tx_ring_to_vector(adapter, i, v_idx); | |
1157 | igb_map_rx_ring_to_vector(adapter, i, v_idx++); | |
1158 | } | |
1159 | for (; i < adapter->num_tx_queues; i++) | |
1160 | igb_map_tx_ring_to_vector(adapter, i, v_idx++); | |
1161 | } | |
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | /** | |
1166 | * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors | |
1167 | * | |
1168 | * This function initializes the interrupts and allocates all of the queues. | |
1169 | **/ | |
1170 | static int igb_init_interrupt_scheme(struct igb_adapter *adapter) | |
1171 | { | |
1172 | struct pci_dev *pdev = adapter->pdev; | |
1173 | int err; | |
1174 | ||
21adef3e BH |
1175 | err = igb_set_interrupt_capability(adapter); |
1176 | if (err) | |
1177 | return err; | |
047e0030 AD |
1178 | |
1179 | err = igb_alloc_q_vectors(adapter); | |
1180 | if (err) { | |
1181 | dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); | |
1182 | goto err_alloc_q_vectors; | |
1183 | } | |
1184 | ||
1185 | err = igb_alloc_queues(adapter); | |
1186 | if (err) { | |
1187 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
1188 | goto err_alloc_queues; | |
1189 | } | |
1190 | ||
1191 | err = igb_map_ring_to_vector(adapter); | |
1192 | if (err) { | |
1193 | dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n"); | |
1194 | goto err_map_queues; | |
1195 | } | |
1196 | ||
1197 | ||
1198 | return 0; | |
1199 | err_map_queues: | |
1200 | igb_free_queues(adapter); | |
1201 | err_alloc_queues: | |
1202 | igb_free_q_vectors(adapter); | |
1203 | err_alloc_q_vectors: | |
1204 | igb_reset_interrupt_capability(adapter); | |
1205 | return err; | |
1206 | } | |
1207 | ||
9d5c8243 AK |
1208 | /** |
1209 | * igb_request_irq - initialize interrupts | |
1210 | * | |
1211 | * Attempts to configure interrupts using the best available | |
1212 | * capabilities of the hardware and kernel. | |
1213 | **/ | |
1214 | static int igb_request_irq(struct igb_adapter *adapter) | |
1215 | { | |
1216 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 1217 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
1218 | int err = 0; |
1219 | ||
1220 | if (adapter->msix_entries) { | |
1221 | err = igb_request_msix(adapter); | |
844290e5 | 1222 | if (!err) |
9d5c8243 | 1223 | goto request_done; |
9d5c8243 | 1224 | /* fall back to MSI */ |
047e0030 | 1225 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 1226 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 1227 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1228 | igb_free_all_tx_resources(adapter); |
1229 | igb_free_all_rx_resources(adapter); | |
047e0030 | 1230 | adapter->num_tx_queues = 1; |
9d5c8243 | 1231 | adapter->num_rx_queues = 1; |
047e0030 AD |
1232 | adapter->num_q_vectors = 1; |
1233 | err = igb_alloc_q_vectors(adapter); | |
1234 | if (err) { | |
1235 | dev_err(&pdev->dev, | |
1236 | "Unable to allocate memory for vectors\n"); | |
1237 | goto request_done; | |
1238 | } | |
1239 | err = igb_alloc_queues(adapter); | |
1240 | if (err) { | |
1241 | dev_err(&pdev->dev, | |
1242 | "Unable to allocate memory for queues\n"); | |
1243 | igb_free_q_vectors(adapter); | |
1244 | goto request_done; | |
1245 | } | |
1246 | igb_setup_all_tx_resources(adapter); | |
1247 | igb_setup_all_rx_resources(adapter); | |
844290e5 | 1248 | } else { |
feeb2721 | 1249 | igb_assign_vector(adapter->q_vector[0], 0); |
9d5c8243 | 1250 | } |
844290e5 | 1251 | |
7dfc16fa | 1252 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
a0607fd3 | 1253 | err = request_irq(adapter->pdev->irq, igb_intr_msi, 0, |
047e0030 | 1254 | netdev->name, adapter); |
9d5c8243 AK |
1255 | if (!err) |
1256 | goto request_done; | |
047e0030 | 1257 | |
9d5c8243 AK |
1258 | /* fall back to legacy interrupts */ |
1259 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 1260 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1261 | } |
1262 | ||
a0607fd3 | 1263 | err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED, |
047e0030 | 1264 | netdev->name, adapter); |
9d5c8243 | 1265 | |
6cb5e577 | 1266 | if (err) |
9d5c8243 AK |
1267 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
1268 | err); | |
9d5c8243 AK |
1269 | |
1270 | request_done: | |
1271 | return err; | |
1272 | } | |
1273 | ||
1274 | static void igb_free_irq(struct igb_adapter *adapter) | |
1275 | { | |
9d5c8243 AK |
1276 | if (adapter->msix_entries) { |
1277 | int vector = 0, i; | |
1278 | ||
047e0030 | 1279 | free_irq(adapter->msix_entries[vector++].vector, adapter); |
9d5c8243 | 1280 | |
047e0030 AD |
1281 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1282 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
1283 | free_irq(adapter->msix_entries[vector++].vector, | |
1284 | q_vector); | |
1285 | } | |
1286 | } else { | |
1287 | free_irq(adapter->pdev->irq, adapter); | |
9d5c8243 | 1288 | } |
9d5c8243 AK |
1289 | } |
1290 | ||
1291 | /** | |
1292 | * igb_irq_disable - Mask off interrupt generation on the NIC | |
1293 | * @adapter: board private structure | |
1294 | **/ | |
1295 | static void igb_irq_disable(struct igb_adapter *adapter) | |
1296 | { | |
1297 | struct e1000_hw *hw = &adapter->hw; | |
1298 | ||
25568a53 AD |
1299 | /* |
1300 | * we need to be careful when disabling interrupts. The VFs are also | |
1301 | * mapped into these registers and so clearing the bits can cause | |
1302 | * issues on the VF drivers so we only need to clear what we set | |
1303 | */ | |
9d5c8243 | 1304 | if (adapter->msix_entries) { |
2dfd1212 AD |
1305 | u32 regval = rd32(E1000_EIAM); |
1306 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); | |
1307 | wr32(E1000_EIMC, adapter->eims_enable_mask); | |
1308 | regval = rd32(E1000_EIAC); | |
1309 | wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); | |
9d5c8243 | 1310 | } |
844290e5 PW |
1311 | |
1312 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
1313 | wr32(E1000_IMC, ~0); |
1314 | wrfl(); | |
81a61859 ET |
1315 | if (adapter->msix_entries) { |
1316 | int i; | |
1317 | for (i = 0; i < adapter->num_q_vectors; i++) | |
1318 | synchronize_irq(adapter->msix_entries[i].vector); | |
1319 | } else { | |
1320 | synchronize_irq(adapter->pdev->irq); | |
1321 | } | |
9d5c8243 AK |
1322 | } |
1323 | ||
1324 | /** | |
1325 | * igb_irq_enable - Enable default interrupt generation settings | |
1326 | * @adapter: board private structure | |
1327 | **/ | |
1328 | static void igb_irq_enable(struct igb_adapter *adapter) | |
1329 | { | |
1330 | struct e1000_hw *hw = &adapter->hw; | |
1331 | ||
1332 | if (adapter->msix_entries) { | |
25568a53 | 1333 | u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC; |
2dfd1212 AD |
1334 | u32 regval = rd32(E1000_EIAC); |
1335 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); | |
1336 | regval = rd32(E1000_EIAM); | |
1337 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); | |
844290e5 | 1338 | wr32(E1000_EIMS, adapter->eims_enable_mask); |
25568a53 | 1339 | if (adapter->vfs_allocated_count) { |
4ae196df | 1340 | wr32(E1000_MBVFIMR, 0xFF); |
25568a53 AD |
1341 | ims |= E1000_IMS_VMMB; |
1342 | } | |
55cac248 AD |
1343 | if (adapter->hw.mac.type == e1000_82580) |
1344 | ims |= E1000_IMS_DRSTA; | |
1345 | ||
25568a53 | 1346 | wr32(E1000_IMS, ims); |
844290e5 | 1347 | } else { |
55cac248 AD |
1348 | wr32(E1000_IMS, IMS_ENABLE_MASK | |
1349 | E1000_IMS_DRSTA); | |
1350 | wr32(E1000_IAM, IMS_ENABLE_MASK | | |
1351 | E1000_IMS_DRSTA); | |
844290e5 | 1352 | } |
9d5c8243 AK |
1353 | } |
1354 | ||
1355 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
1356 | { | |
51466239 | 1357 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1358 | u16 vid = adapter->hw.mng_cookie.vlan_id; |
1359 | u16 old_vid = adapter->mng_vlan_id; | |
51466239 AD |
1360 | |
1361 | if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
1362 | /* add VID to filter table */ | |
1363 | igb_vfta_set(hw, vid, true); | |
1364 | adapter->mng_vlan_id = vid; | |
1365 | } else { | |
1366 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1367 | } | |
1368 | ||
1369 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
1370 | (vid != old_vid) && | |
b2cb09b1 | 1371 | !test_bit(old_vid, adapter->active_vlans)) { |
51466239 AD |
1372 | /* remove VID from filter table */ |
1373 | igb_vfta_set(hw, old_vid, false); | |
9d5c8243 AK |
1374 | } |
1375 | } | |
1376 | ||
1377 | /** | |
1378 | * igb_release_hw_control - release control of the h/w to f/w | |
1379 | * @adapter: address of board private structure | |
1380 | * | |
1381 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. | |
1382 | * For ASF and Pass Through versions of f/w this means that the | |
1383 | * driver is no longer loaded. | |
1384 | * | |
1385 | **/ | |
1386 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
1387 | { | |
1388 | struct e1000_hw *hw = &adapter->hw; | |
1389 | u32 ctrl_ext; | |
1390 | ||
1391 | /* Let firmware take over control of h/w */ | |
1392 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1393 | wr32(E1000_CTRL_EXT, | |
1394 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
1395 | } | |
1396 | ||
9d5c8243 AK |
1397 | /** |
1398 | * igb_get_hw_control - get control of the h/w from f/w | |
1399 | * @adapter: address of board private structure | |
1400 | * | |
1401 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. | |
1402 | * For ASF and Pass Through versions of f/w this means that | |
1403 | * the driver is loaded. | |
1404 | * | |
1405 | **/ | |
1406 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
1407 | { | |
1408 | struct e1000_hw *hw = &adapter->hw; | |
1409 | u32 ctrl_ext; | |
1410 | ||
1411 | /* Let firmware know the driver has taken over */ | |
1412 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1413 | wr32(E1000_CTRL_EXT, | |
1414 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
1415 | } | |
1416 | ||
9d5c8243 AK |
1417 | /** |
1418 | * igb_configure - configure the hardware for RX and TX | |
1419 | * @adapter: private board structure | |
1420 | **/ | |
1421 | static void igb_configure(struct igb_adapter *adapter) | |
1422 | { | |
1423 | struct net_device *netdev = adapter->netdev; | |
1424 | int i; | |
1425 | ||
1426 | igb_get_hw_control(adapter); | |
ff41f8dc | 1427 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
1428 | |
1429 | igb_restore_vlan(adapter); | |
9d5c8243 | 1430 | |
85b430b4 | 1431 | igb_setup_tctl(adapter); |
06cf2666 | 1432 | igb_setup_mrqc(adapter); |
9d5c8243 | 1433 | igb_setup_rctl(adapter); |
85b430b4 AD |
1434 | |
1435 | igb_configure_tx(adapter); | |
9d5c8243 | 1436 | igb_configure_rx(adapter); |
662d7205 AD |
1437 | |
1438 | igb_rx_fifo_flush_82575(&adapter->hw); | |
1439 | ||
c493ea45 | 1440 | /* call igb_desc_unused which always leaves |
9d5c8243 AK |
1441 | * at least 1 descriptor unused to make sure |
1442 | * next_to_use != next_to_clean */ | |
1443 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 1444 | struct igb_ring *ring = adapter->rx_ring[i]; |
cd392f5c | 1445 | igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); |
9d5c8243 | 1446 | } |
9d5c8243 AK |
1447 | } |
1448 | ||
88a268c1 NN |
1449 | /** |
1450 | * igb_power_up_link - Power up the phy/serdes link | |
1451 | * @adapter: address of board private structure | |
1452 | **/ | |
1453 | void igb_power_up_link(struct igb_adapter *adapter) | |
1454 | { | |
1455 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | |
1456 | igb_power_up_phy_copper(&adapter->hw); | |
1457 | else | |
1458 | igb_power_up_serdes_link_82575(&adapter->hw); | |
1459 | } | |
1460 | ||
1461 | /** | |
1462 | * igb_power_down_link - Power down the phy/serdes link | |
1463 | * @adapter: address of board private structure | |
1464 | */ | |
1465 | static void igb_power_down_link(struct igb_adapter *adapter) | |
1466 | { | |
1467 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | |
1468 | igb_power_down_phy_copper_82575(&adapter->hw); | |
1469 | else | |
1470 | igb_shutdown_serdes_link_82575(&adapter->hw); | |
1471 | } | |
9d5c8243 AK |
1472 | |
1473 | /** | |
1474 | * igb_up - Open the interface and prepare it to handle traffic | |
1475 | * @adapter: board private structure | |
1476 | **/ | |
9d5c8243 AK |
1477 | int igb_up(struct igb_adapter *adapter) |
1478 | { | |
1479 | struct e1000_hw *hw = &adapter->hw; | |
1480 | int i; | |
1481 | ||
1482 | /* hardware has been reset, we need to reload some things */ | |
1483 | igb_configure(adapter); | |
1484 | ||
1485 | clear_bit(__IGB_DOWN, &adapter->state); | |
1486 | ||
047e0030 AD |
1487 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1488 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
1489 | napi_enable(&q_vector->napi); | |
1490 | } | |
844290e5 | 1491 | if (adapter->msix_entries) |
9d5c8243 | 1492 | igb_configure_msix(adapter); |
feeb2721 AD |
1493 | else |
1494 | igb_assign_vector(adapter->q_vector[0], 0); | |
9d5c8243 AK |
1495 | |
1496 | /* Clear any pending interrupts. */ | |
1497 | rd32(E1000_ICR); | |
1498 | igb_irq_enable(adapter); | |
1499 | ||
d4960307 AD |
1500 | /* notify VFs that reset has been completed */ |
1501 | if (adapter->vfs_allocated_count) { | |
1502 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
1503 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
1504 | wr32(E1000_CTRL_EXT, reg_data); | |
1505 | } | |
1506 | ||
4cb9be7a JB |
1507 | netif_tx_start_all_queues(adapter->netdev); |
1508 | ||
25568a53 AD |
1509 | /* start the watchdog. */ |
1510 | hw->mac.get_link_status = 1; | |
1511 | schedule_work(&adapter->watchdog_task); | |
1512 | ||
9d5c8243 AK |
1513 | return 0; |
1514 | } | |
1515 | ||
1516 | void igb_down(struct igb_adapter *adapter) | |
1517 | { | |
9d5c8243 | 1518 | struct net_device *netdev = adapter->netdev; |
330a6d6a | 1519 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1520 | u32 tctl, rctl; |
1521 | int i; | |
1522 | ||
1523 | /* signal that we're down so the interrupt handler does not | |
1524 | * reschedule our watchdog timer */ | |
1525 | set_bit(__IGB_DOWN, &adapter->state); | |
1526 | ||
1527 | /* disable receives in the hardware */ | |
1528 | rctl = rd32(E1000_RCTL); | |
1529 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1530 | /* flush and sleep below */ | |
1531 | ||
fd2ea0a7 | 1532 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1533 | |
1534 | /* disable transmits in the hardware */ | |
1535 | tctl = rd32(E1000_TCTL); | |
1536 | tctl &= ~E1000_TCTL_EN; | |
1537 | wr32(E1000_TCTL, tctl); | |
1538 | /* flush both disables and wait for them to finish */ | |
1539 | wrfl(); | |
1540 | msleep(10); | |
1541 | ||
047e0030 AD |
1542 | for (i = 0; i < adapter->num_q_vectors; i++) { |
1543 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
1544 | napi_disable(&q_vector->napi); | |
1545 | } | |
9d5c8243 | 1546 | |
9d5c8243 AK |
1547 | igb_irq_disable(adapter); |
1548 | ||
1549 | del_timer_sync(&adapter->watchdog_timer); | |
1550 | del_timer_sync(&adapter->phy_info_timer); | |
1551 | ||
9d5c8243 | 1552 | netif_carrier_off(netdev); |
04fe6358 AD |
1553 | |
1554 | /* record the stats before reset*/ | |
12dcd86b ED |
1555 | spin_lock(&adapter->stats64_lock); |
1556 | igb_update_stats(adapter, &adapter->stats64); | |
1557 | spin_unlock(&adapter->stats64_lock); | |
04fe6358 | 1558 | |
9d5c8243 AK |
1559 | adapter->link_speed = 0; |
1560 | adapter->link_duplex = 0; | |
1561 | ||
3023682e JK |
1562 | if (!pci_channel_offline(adapter->pdev)) |
1563 | igb_reset(adapter); | |
9d5c8243 AK |
1564 | igb_clean_all_tx_rings(adapter); |
1565 | igb_clean_all_rx_rings(adapter); | |
7e0e99ef AD |
1566 | #ifdef CONFIG_IGB_DCA |
1567 | ||
1568 | /* since we reset the hardware DCA settings were cleared */ | |
1569 | igb_setup_dca(adapter); | |
1570 | #endif | |
9d5c8243 AK |
1571 | } |
1572 | ||
1573 | void igb_reinit_locked(struct igb_adapter *adapter) | |
1574 | { | |
1575 | WARN_ON(in_interrupt()); | |
1576 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
1577 | msleep(1); | |
1578 | igb_down(adapter); | |
1579 | igb_up(adapter); | |
1580 | clear_bit(__IGB_RESETTING, &adapter->state); | |
1581 | } | |
1582 | ||
1583 | void igb_reset(struct igb_adapter *adapter) | |
1584 | { | |
090b1795 | 1585 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 1586 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 AD |
1587 | struct e1000_mac_info *mac = &hw->mac; |
1588 | struct e1000_fc_info *fc = &hw->fc; | |
9d5c8243 AK |
1589 | u32 pba = 0, tx_space, min_tx_space, min_rx_space; |
1590 | u16 hwm; | |
1591 | ||
1592 | /* Repartition Pba for greater than 9k mtu | |
1593 | * To take effect CTRL.RST is required. | |
1594 | */ | |
fa4dfae0 | 1595 | switch (mac->type) { |
d2ba2ed8 | 1596 | case e1000_i350: |
55cac248 AD |
1597 | case e1000_82580: |
1598 | pba = rd32(E1000_RXPBS); | |
1599 | pba = igb_rxpbs_adjust_82580(pba); | |
1600 | break; | |
fa4dfae0 | 1601 | case e1000_82576: |
d249be54 AD |
1602 | pba = rd32(E1000_RXPBS); |
1603 | pba &= E1000_RXPBS_SIZE_MASK_82576; | |
fa4dfae0 AD |
1604 | break; |
1605 | case e1000_82575: | |
1606 | default: | |
1607 | pba = E1000_PBA_34K; | |
1608 | break; | |
2d064c06 | 1609 | } |
9d5c8243 | 1610 | |
2d064c06 AD |
1611 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
1612 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
1613 | /* adjust PBA for jumbo frames */ |
1614 | wr32(E1000_PBA, pba); | |
1615 | ||
1616 | /* To maintain wire speed transmits, the Tx FIFO should be | |
1617 | * large enough to accommodate two full transmit packets, | |
1618 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
1619 | * the Rx FIFO should be large enough to accommodate at least | |
1620 | * one full receive packet and is similarly rounded up and | |
1621 | * expressed in KB. */ | |
1622 | pba = rd32(E1000_PBA); | |
1623 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
1624 | tx_space = pba >> 16; | |
1625 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
1626 | pba &= 0xffff; | |
1627 | /* the tx fifo also stores 16 bytes of information about the tx | |
1628 | * but don't include ethernet FCS because hardware appends it */ | |
1629 | min_tx_space = (adapter->max_frame_size + | |
85e8d004 | 1630 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1631 | ETH_FCS_LEN) * 2; |
1632 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1633 | min_tx_space >>= 10; | |
1634 | /* software strips receive CRC, so leave room for it */ | |
1635 | min_rx_space = adapter->max_frame_size; | |
1636 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1637 | min_rx_space >>= 10; | |
1638 | ||
1639 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1640 | * and the min Tx FIFO size is less than the current Rx FIFO | |
1641 | * allocation, take space away from current Rx allocation */ | |
1642 | if (tx_space < min_tx_space && | |
1643 | ((min_tx_space - tx_space) < pba)) { | |
1644 | pba = pba - (min_tx_space - tx_space); | |
1645 | ||
1646 | /* if short on rx space, rx wins and must trump tx | |
1647 | * adjustment */ | |
1648 | if (pba < min_rx_space) | |
1649 | pba = min_rx_space; | |
1650 | } | |
2d064c06 | 1651 | wr32(E1000_PBA, pba); |
9d5c8243 | 1652 | } |
9d5c8243 AK |
1653 | |
1654 | /* flow control settings */ | |
1655 | /* The high water mark must be low enough to fit one full frame | |
1656 | * (or the size used for early receive) above it in the Rx FIFO. | |
1657 | * Set it to the lower of: | |
1658 | * - 90% of the Rx FIFO size, or | |
1659 | * - the full Rx FIFO size minus one full frame */ | |
1660 | hwm = min(((pba << 10) * 9 / 10), | |
2d064c06 | 1661 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1662 | |
d405ea3e AD |
1663 | fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ |
1664 | fc->low_water = fc->high_water - 16; | |
9d5c8243 AK |
1665 | fc->pause_time = 0xFFFF; |
1666 | fc->send_xon = 1; | |
0cce119a | 1667 | fc->current_mode = fc->requested_mode; |
9d5c8243 | 1668 | |
4ae196df AD |
1669 | /* disable receive for all VFs and wait one second */ |
1670 | if (adapter->vfs_allocated_count) { | |
1671 | int i; | |
1672 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | |
8fa7e0f7 | 1673 | adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; |
4ae196df AD |
1674 | |
1675 | /* ping all the active vfs to let them know we are going down */ | |
f2ca0dbe | 1676 | igb_ping_all_vfs(adapter); |
4ae196df AD |
1677 | |
1678 | /* disable transmits and receives */ | |
1679 | wr32(E1000_VFRE, 0); | |
1680 | wr32(E1000_VFTE, 0); | |
1681 | } | |
1682 | ||
9d5c8243 | 1683 | /* Allow time for pending master requests to run */ |
330a6d6a | 1684 | hw->mac.ops.reset_hw(hw); |
9d5c8243 AK |
1685 | wr32(E1000_WUC, 0); |
1686 | ||
330a6d6a | 1687 | if (hw->mac.ops.init_hw(hw)) |
090b1795 | 1688 | dev_err(&pdev->dev, "Hardware Error\n"); |
831ec0b4 CW |
1689 | if (hw->mac.type > e1000_82580) { |
1690 | if (adapter->flags & IGB_FLAG_DMAC) { | |
1691 | u32 reg; | |
1692 | ||
1693 | /* | |
1694 | * DMA Coalescing high water mark needs to be higher | |
1695 | * than * the * Rx threshold. The Rx threshold is | |
1696 | * currently * pba - 6, so we * should use a high water | |
1697 | * mark of pba * - 4. */ | |
1698 | hwm = (pba - 4) << 10; | |
1699 | ||
1700 | reg = (((pba-6) << E1000_DMACR_DMACTHR_SHIFT) | |
1701 | & E1000_DMACR_DMACTHR_MASK); | |
1702 | ||
1703 | /* transition to L0x or L1 if available..*/ | |
1704 | reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); | |
1705 | ||
1706 | /* watchdog timer= +-1000 usec in 32usec intervals */ | |
1707 | reg |= (1000 >> 5); | |
1708 | wr32(E1000_DMACR, reg); | |
1709 | ||
1710 | /* no lower threshold to disable coalescing(smart fifb) | |
1711 | * -UTRESH=0*/ | |
1712 | wr32(E1000_DMCRTRH, 0); | |
1713 | ||
1714 | /* set hwm to PBA - 2 * max frame size */ | |
1715 | wr32(E1000_FCRTC, hwm); | |
1716 | ||
1717 | /* | |
1718 | * This sets the time to wait before requesting tran- | |
1719 | * sition to * low power state to number of usecs needed | |
1720 | * to receive 1 512 * byte frame at gigabit line rate | |
1721 | */ | |
1722 | reg = rd32(E1000_DMCTLX); | |
1723 | reg |= IGB_DMCTLX_DCFLUSH_DIS; | |
1724 | ||
1725 | /* Delay 255 usec before entering Lx state. */ | |
1726 | reg |= 0xFF; | |
1727 | wr32(E1000_DMCTLX, reg); | |
1728 | ||
1729 | /* free space in Tx packet buffer to wake from DMAC */ | |
1730 | wr32(E1000_DMCTXTH, | |
1731 | (IGB_MIN_TXPBSIZE - | |
1732 | (IGB_TX_BUF_4096 + adapter->max_frame_size)) | |
1733 | >> 6); | |
1734 | ||
1735 | /* make low power state decision controlled by DMAC */ | |
1736 | reg = rd32(E1000_PCIEMISC); | |
1737 | reg |= E1000_PCIEMISC_LX_DECISION; | |
1738 | wr32(E1000_PCIEMISC, reg); | |
1739 | } /* end if IGB_FLAG_DMAC set */ | |
1740 | } | |
55cac248 AD |
1741 | if (hw->mac.type == e1000_82580) { |
1742 | u32 reg = rd32(E1000_PCIEMISC); | |
1743 | wr32(E1000_PCIEMISC, | |
1744 | reg & ~E1000_PCIEMISC_LX_DECISION); | |
1745 | } | |
88a268c1 NN |
1746 | if (!netif_running(adapter->netdev)) |
1747 | igb_power_down_link(adapter); | |
1748 | ||
9d5c8243 AK |
1749 | igb_update_mng_vlan(adapter); |
1750 | ||
1751 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1752 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1753 | ||
330a6d6a | 1754 | igb_get_phy_info(hw); |
9d5c8243 AK |
1755 | } |
1756 | ||
b2cb09b1 JP |
1757 | static u32 igb_fix_features(struct net_device *netdev, u32 features) |
1758 | { | |
1759 | /* | |
1760 | * Since there is no support for separate rx/tx vlan accel | |
1761 | * enable/disable make sure tx flag is always in same state as rx. | |
1762 | */ | |
1763 | if (features & NETIF_F_HW_VLAN_RX) | |
1764 | features |= NETIF_F_HW_VLAN_TX; | |
1765 | else | |
1766 | features &= ~NETIF_F_HW_VLAN_TX; | |
1767 | ||
1768 | return features; | |
1769 | } | |
1770 | ||
ac52caa3 MM |
1771 | static int igb_set_features(struct net_device *netdev, u32 features) |
1772 | { | |
1773 | struct igb_adapter *adapter = netdev_priv(netdev); | |
1774 | int i; | |
b2cb09b1 | 1775 | u32 changed = netdev->features ^ features; |
ac52caa3 MM |
1776 | |
1777 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1778 | if (features & NETIF_F_RXCSUM) | |
1779 | adapter->rx_ring[i]->flags |= IGB_RING_FLAG_RX_CSUM; | |
1780 | else | |
1781 | adapter->rx_ring[i]->flags &= ~IGB_RING_FLAG_RX_CSUM; | |
1782 | } | |
1783 | ||
b2cb09b1 JP |
1784 | if (changed & NETIF_F_HW_VLAN_RX) |
1785 | igb_vlan_mode(netdev, features); | |
1786 | ||
ac52caa3 MM |
1787 | return 0; |
1788 | } | |
1789 | ||
2e5c6922 | 1790 | static const struct net_device_ops igb_netdev_ops = { |
559e9c49 | 1791 | .ndo_open = igb_open, |
2e5c6922 | 1792 | .ndo_stop = igb_close, |
cd392f5c | 1793 | .ndo_start_xmit = igb_xmit_frame, |
12dcd86b | 1794 | .ndo_get_stats64 = igb_get_stats64, |
ff41f8dc | 1795 | .ndo_set_rx_mode = igb_set_rx_mode, |
2e5c6922 SH |
1796 | .ndo_set_mac_address = igb_set_mac, |
1797 | .ndo_change_mtu = igb_change_mtu, | |
1798 | .ndo_do_ioctl = igb_ioctl, | |
1799 | .ndo_tx_timeout = igb_tx_timeout, | |
1800 | .ndo_validate_addr = eth_validate_addr, | |
2e5c6922 SH |
1801 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, |
1802 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
8151d294 WM |
1803 | .ndo_set_vf_mac = igb_ndo_set_vf_mac, |
1804 | .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, | |
1805 | .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, | |
1806 | .ndo_get_vf_config = igb_ndo_get_vf_config, | |
2e5c6922 SH |
1807 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1808 | .ndo_poll_controller = igb_netpoll, | |
1809 | #endif | |
b2cb09b1 JP |
1810 | .ndo_fix_features = igb_fix_features, |
1811 | .ndo_set_features = igb_set_features, | |
2e5c6922 SH |
1812 | }; |
1813 | ||
9d5c8243 AK |
1814 | /** |
1815 | * igb_probe - Device Initialization Routine | |
1816 | * @pdev: PCI device information struct | |
1817 | * @ent: entry in igb_pci_tbl | |
1818 | * | |
1819 | * Returns 0 on success, negative on failure | |
1820 | * | |
1821 | * igb_probe initializes an adapter identified by a pci_dev structure. | |
1822 | * The OS initialization, configuring of the adapter private structure, | |
1823 | * and a hardware reset occur. | |
1824 | **/ | |
1825 | static int __devinit igb_probe(struct pci_dev *pdev, | |
1826 | const struct pci_device_id *ent) | |
1827 | { | |
1828 | struct net_device *netdev; | |
1829 | struct igb_adapter *adapter; | |
1830 | struct e1000_hw *hw; | |
4337e993 | 1831 | u16 eeprom_data = 0; |
9835fd73 | 1832 | s32 ret_val; |
4337e993 | 1833 | static int global_quad_port_a; /* global quad port a indication */ |
9d5c8243 AK |
1834 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
1835 | unsigned long mmio_start, mmio_len; | |
2d6a5e95 | 1836 | int err, pci_using_dac; |
9d5c8243 | 1837 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
9835fd73 | 1838 | u8 part_str[E1000_PBANUM_LENGTH]; |
9d5c8243 | 1839 | |
bded64a7 AG |
1840 | /* Catch broken hardware that put the wrong VF device ID in |
1841 | * the PCIe SR-IOV capability. | |
1842 | */ | |
1843 | if (pdev->is_virtfn) { | |
1844 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
1845 | pci_name(pdev), pdev->vendor, pdev->device); | |
1846 | return -EINVAL; | |
1847 | } | |
1848 | ||
aed5dec3 | 1849 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
1850 | if (err) |
1851 | return err; | |
1852 | ||
1853 | pci_using_dac = 0; | |
59d71989 | 1854 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 | 1855 | if (!err) { |
59d71989 | 1856 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 AK |
1857 | if (!err) |
1858 | pci_using_dac = 1; | |
1859 | } else { | |
59d71989 | 1860 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 | 1861 | if (err) { |
59d71989 | 1862 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 AK |
1863 | if (err) { |
1864 | dev_err(&pdev->dev, "No usable DMA " | |
1865 | "configuration, aborting\n"); | |
1866 | goto err_dma; | |
1867 | } | |
1868 | } | |
1869 | } | |
1870 | ||
aed5dec3 AD |
1871 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
1872 | IORESOURCE_MEM), | |
1873 | igb_driver_name); | |
9d5c8243 AK |
1874 | if (err) |
1875 | goto err_pci_reg; | |
1876 | ||
19d5afd4 | 1877 | pci_enable_pcie_error_reporting(pdev); |
40a914fa | 1878 | |
9d5c8243 | 1879 | pci_set_master(pdev); |
c682fc23 | 1880 | pci_save_state(pdev); |
9d5c8243 AK |
1881 | |
1882 | err = -ENOMEM; | |
1bfaf07b | 1883 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1cc3bd87 | 1884 | IGB_MAX_TX_QUEUES); |
9d5c8243 AK |
1885 | if (!netdev) |
1886 | goto err_alloc_etherdev; | |
1887 | ||
1888 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1889 | ||
1890 | pci_set_drvdata(pdev, netdev); | |
1891 | adapter = netdev_priv(netdev); | |
1892 | adapter->netdev = netdev; | |
1893 | adapter->pdev = pdev; | |
1894 | hw = &adapter->hw; | |
1895 | hw->back = adapter; | |
1896 | adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE; | |
1897 | ||
1898 | mmio_start = pci_resource_start(pdev, 0); | |
1899 | mmio_len = pci_resource_len(pdev, 0); | |
1900 | ||
1901 | err = -EIO; | |
28b0759c AD |
1902 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
1903 | if (!hw->hw_addr) | |
9d5c8243 AK |
1904 | goto err_ioremap; |
1905 | ||
2e5c6922 | 1906 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 1907 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 1908 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
1909 | |
1910 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
1911 | ||
1912 | netdev->mem_start = mmio_start; | |
1913 | netdev->mem_end = mmio_start + mmio_len; | |
1914 | ||
9d5c8243 AK |
1915 | /* PCI config space info */ |
1916 | hw->vendor_id = pdev->vendor; | |
1917 | hw->device_id = pdev->device; | |
1918 | hw->revision_id = pdev->revision; | |
1919 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1920 | hw->subsystem_device_id = pdev->subsystem_device; | |
1921 | ||
9d5c8243 AK |
1922 | /* Copy the default MAC, PHY and NVM function pointers */ |
1923 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
1924 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
1925 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
1926 | /* Initialize skew-specific constants */ | |
1927 | err = ei->get_invariants(hw); | |
1928 | if (err) | |
450c87c8 | 1929 | goto err_sw_init; |
9d5c8243 | 1930 | |
450c87c8 | 1931 | /* setup the private structure */ |
9d5c8243 AK |
1932 | err = igb_sw_init(adapter); |
1933 | if (err) | |
1934 | goto err_sw_init; | |
1935 | ||
1936 | igb_get_bus_info_pcie(hw); | |
1937 | ||
1938 | hw->phy.autoneg_wait_to_complete = false; | |
9d5c8243 AK |
1939 | |
1940 | /* Copper options */ | |
1941 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1942 | hw->phy.mdix = AUTO_ALL_MODES; | |
1943 | hw->phy.disable_polarity_correction = false; | |
1944 | hw->phy.ms_type = e1000_ms_hw_default; | |
1945 | } | |
1946 | ||
1947 | if (igb_check_reset_block(hw)) | |
1948 | dev_info(&pdev->dev, | |
1949 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
1950 | ||
ac52caa3 | 1951 | netdev->hw_features = NETIF_F_SG | |
7d8eb29e | 1952 | NETIF_F_IP_CSUM | |
ac52caa3 MM |
1953 | NETIF_F_IPV6_CSUM | |
1954 | NETIF_F_TSO | | |
1955 | NETIF_F_TSO6 | | |
b2cb09b1 JP |
1956 | NETIF_F_RXCSUM | |
1957 | NETIF_F_HW_VLAN_RX; | |
ac52caa3 MM |
1958 | |
1959 | netdev->features = netdev->hw_features | | |
9d5c8243 | 1960 | NETIF_F_HW_VLAN_TX | |
9d5c8243 AK |
1961 | NETIF_F_HW_VLAN_FILTER; |
1962 | ||
48f29ffc JK |
1963 | netdev->vlan_features |= NETIF_F_TSO; |
1964 | netdev->vlan_features |= NETIF_F_TSO6; | |
7d8eb29e | 1965 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 1966 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
48f29ffc JK |
1967 | netdev->vlan_features |= NETIF_F_SG; |
1968 | ||
7b872a55 | 1969 | if (pci_using_dac) { |
9d5c8243 | 1970 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
1971 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
1972 | } | |
9d5c8243 | 1973 | |
ac52caa3 MM |
1974 | if (hw->mac.type >= e1000_82576) { |
1975 | netdev->hw_features |= NETIF_F_SCTP_CSUM; | |
b9473560 | 1976 | netdev->features |= NETIF_F_SCTP_CSUM; |
ac52caa3 | 1977 | } |
b9473560 | 1978 | |
01789349 JP |
1979 | netdev->priv_flags |= IFF_UNICAST_FLT; |
1980 | ||
330a6d6a | 1981 | adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
9d5c8243 AK |
1982 | |
1983 | /* before reading the NVM, reset the controller to put the device in a | |
1984 | * known good starting state */ | |
1985 | hw->mac.ops.reset_hw(hw); | |
1986 | ||
1987 | /* make sure the NVM is good */ | |
4322e561 | 1988 | if (hw->nvm.ops.validate(hw) < 0) { |
9d5c8243 AK |
1989 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); |
1990 | err = -EIO; | |
1991 | goto err_eeprom; | |
1992 | } | |
1993 | ||
1994 | /* copy the MAC address out of the NVM */ | |
1995 | if (hw->mac.ops.read_mac_addr(hw)) | |
1996 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
1997 | ||
1998 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
1999 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
2000 | ||
2001 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
2002 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
2003 | err = -EIO; | |
2004 | goto err_eeprom; | |
2005 | } | |
2006 | ||
c061b18d | 2007 | setup_timer(&adapter->watchdog_timer, igb_watchdog, |
0e340485 | 2008 | (unsigned long) adapter); |
c061b18d | 2009 | setup_timer(&adapter->phy_info_timer, igb_update_phy_info, |
0e340485 | 2010 | (unsigned long) adapter); |
9d5c8243 AK |
2011 | |
2012 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
2013 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
2014 | ||
450c87c8 | 2015 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
2016 | adapter->fc_autoneg = true; |
2017 | hw->mac.autoneg = true; | |
2018 | hw->phy.autoneg_advertised = 0x2f; | |
2019 | ||
0cce119a AD |
2020 | hw->fc.requested_mode = e1000_fc_default; |
2021 | hw->fc.current_mode = e1000_fc_default; | |
9d5c8243 | 2022 | |
9d5c8243 AK |
2023 | igb_validate_mdi_setting(hw); |
2024 | ||
9d5c8243 AK |
2025 | /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, |
2026 | * enable the ACPI Magic Packet filter | |
2027 | */ | |
2028 | ||
a2cf8b6c | 2029 | if (hw->bus.func == 0) |
312c75ae | 2030 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); |
6d337dce | 2031 | else if (hw->mac.type >= e1000_82580) |
55cac248 AD |
2032 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + |
2033 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, | |
2034 | &eeprom_data); | |
a2cf8b6c AD |
2035 | else if (hw->bus.func == 1) |
2036 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | |
9d5c8243 AK |
2037 | |
2038 | if (eeprom_data & eeprom_apme_mask) | |
2039 | adapter->eeprom_wol |= E1000_WUFC_MAG; | |
2040 | ||
2041 | /* now that we have the eeprom settings, apply the special cases where | |
2042 | * the eeprom may be wrong or the board simply won't support wake on | |
2043 | * lan on a particular port */ | |
2044 | switch (pdev->device) { | |
2045 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
2046 | adapter->eeprom_wol = 0; | |
2047 | break; | |
2048 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
2049 | case E1000_DEV_ID_82576_FIBER: |
2050 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 AK |
2051 | /* Wake events only supported on port A for dual fiber |
2052 | * regardless of eeprom setting */ | |
2053 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) | |
2054 | adapter->eeprom_wol = 0; | |
2055 | break; | |
c8ea5ea9 | 2056 | case E1000_DEV_ID_82576_QUAD_COPPER: |
d5aa2252 | 2057 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
c8ea5ea9 AD |
2058 | /* if quad port adapter, disable WoL on all but port A */ |
2059 | if (global_quad_port_a != 0) | |
2060 | adapter->eeprom_wol = 0; | |
2061 | else | |
2062 | adapter->flags |= IGB_FLAG_QUAD_PORT_A; | |
2063 | /* Reset for multiple quad port adapters */ | |
2064 | if (++global_quad_port_a == 4) | |
2065 | global_quad_port_a = 0; | |
2066 | break; | |
9d5c8243 AK |
2067 | } |
2068 | ||
2069 | /* initialize the wol settings based on the eeprom settings */ | |
2070 | adapter->wol = adapter->eeprom_wol; | |
e1b86d84 | 2071 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9d5c8243 AK |
2072 | |
2073 | /* reset the hardware with the new settings */ | |
2074 | igb_reset(adapter); | |
2075 | ||
2076 | /* let the f/w know that the h/w is now under the control of the | |
2077 | * driver. */ | |
2078 | igb_get_hw_control(adapter); | |
2079 | ||
9d5c8243 AK |
2080 | strcpy(netdev->name, "eth%d"); |
2081 | err = register_netdev(netdev); | |
2082 | if (err) | |
2083 | goto err_register; | |
2084 | ||
b2cb09b1 JP |
2085 | igb_vlan_mode(netdev, netdev->features); |
2086 | ||
b168dfc5 JB |
2087 | /* carrier off reporting is important to ethtool even BEFORE open */ |
2088 | netif_carrier_off(netdev); | |
2089 | ||
421e02f0 | 2090 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 2091 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 2092 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 | 2093 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
2094 | igb_setup_dca(adapter); |
2095 | } | |
fe4506b6 | 2096 | |
38c845c7 | 2097 | #endif |
673b8b70 AB |
2098 | /* do hw tstamp init after resetting */ |
2099 | igb_init_hw_timer(adapter); | |
2100 | ||
9d5c8243 AK |
2101 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
2102 | /* print bus type/speed/width info */ | |
7c510e4b | 2103 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", |
9d5c8243 | 2104 | netdev->name, |
559e9c49 | 2105 | ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : |
ff846f52 | 2106 | (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : |
559e9c49 | 2107 | "unknown"), |
59c3de89 AD |
2108 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : |
2109 | (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : | |
2110 | (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : | |
2111 | "unknown"), | |
7c510e4b | 2112 | netdev->dev_addr); |
9d5c8243 | 2113 | |
9835fd73 CW |
2114 | ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); |
2115 | if (ret_val) | |
2116 | strcpy(part_str, "Unknown"); | |
2117 | dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); | |
9d5c8243 AK |
2118 | dev_info(&pdev->dev, |
2119 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
2120 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 2121 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 | 2122 | adapter->num_rx_queues, adapter->num_tx_queues); |
09b068d4 CW |
2123 | switch (hw->mac.type) { |
2124 | case e1000_i350: | |
2125 | igb_set_eee_i350(hw); | |
2126 | break; | |
2127 | default: | |
2128 | break; | |
2129 | } | |
9d5c8243 AK |
2130 | return 0; |
2131 | ||
2132 | err_register: | |
2133 | igb_release_hw_control(adapter); | |
2134 | err_eeprom: | |
2135 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 2136 | igb_reset_phy(hw); |
9d5c8243 AK |
2137 | |
2138 | if (hw->flash_address) | |
2139 | iounmap(hw->flash_address); | |
9d5c8243 | 2140 | err_sw_init: |
047e0030 | 2141 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
2142 | iounmap(hw->hw_addr); |
2143 | err_ioremap: | |
2144 | free_netdev(netdev); | |
2145 | err_alloc_etherdev: | |
559e9c49 AD |
2146 | pci_release_selected_regions(pdev, |
2147 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 AK |
2148 | err_pci_reg: |
2149 | err_dma: | |
2150 | pci_disable_device(pdev); | |
2151 | return err; | |
2152 | } | |
2153 | ||
2154 | /** | |
2155 | * igb_remove - Device Removal Routine | |
2156 | * @pdev: PCI device information struct | |
2157 | * | |
2158 | * igb_remove is called by the PCI subsystem to alert the driver | |
2159 | * that it should release a PCI device. The could be caused by a | |
2160 | * Hot-Plug event, or because the driver is going to be removed from | |
2161 | * memory. | |
2162 | **/ | |
2163 | static void __devexit igb_remove(struct pci_dev *pdev) | |
2164 | { | |
2165 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2166 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 2167 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 2168 | |
760141a5 TH |
2169 | /* |
2170 | * The watchdog timer may be rescheduled, so explicitly | |
2171 | * disable watchdog from being rescheduled. | |
2172 | */ | |
9d5c8243 AK |
2173 | set_bit(__IGB_DOWN, &adapter->state); |
2174 | del_timer_sync(&adapter->watchdog_timer); | |
2175 | del_timer_sync(&adapter->phy_info_timer); | |
2176 | ||
760141a5 TH |
2177 | cancel_work_sync(&adapter->reset_task); |
2178 | cancel_work_sync(&adapter->watchdog_task); | |
9d5c8243 | 2179 | |
421e02f0 | 2180 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 2181 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
2182 | dev_info(&pdev->dev, "DCA disabled\n"); |
2183 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 2184 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 2185 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
2186 | } |
2187 | #endif | |
2188 | ||
9d5c8243 AK |
2189 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
2190 | * would have already happened in close and is redundant. */ | |
2191 | igb_release_hw_control(adapter); | |
2192 | ||
2193 | unregister_netdev(netdev); | |
2194 | ||
047e0030 | 2195 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 2196 | |
37680117 AD |
2197 | #ifdef CONFIG_PCI_IOV |
2198 | /* reclaim resources allocated to VFs */ | |
2199 | if (adapter->vf_data) { | |
2200 | /* disable iov and allow time for transactions to clear */ | |
2201 | pci_disable_sriov(pdev); | |
2202 | msleep(500); | |
2203 | ||
2204 | kfree(adapter->vf_data); | |
2205 | adapter->vf_data = NULL; | |
2206 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
945a5151 | 2207 | wrfl(); |
37680117 AD |
2208 | msleep(100); |
2209 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
2210 | } | |
2211 | #endif | |
559e9c49 | 2212 | |
28b0759c AD |
2213 | iounmap(hw->hw_addr); |
2214 | if (hw->flash_address) | |
2215 | iounmap(hw->flash_address); | |
559e9c49 AD |
2216 | pci_release_selected_regions(pdev, |
2217 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9d5c8243 AK |
2218 | |
2219 | free_netdev(netdev); | |
2220 | ||
19d5afd4 | 2221 | pci_disable_pcie_error_reporting(pdev); |
40a914fa | 2222 | |
9d5c8243 AK |
2223 | pci_disable_device(pdev); |
2224 | } | |
2225 | ||
a6b623e0 AD |
2226 | /** |
2227 | * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space | |
2228 | * @adapter: board private structure to initialize | |
2229 | * | |
2230 | * This function initializes the vf specific data storage and then attempts to | |
2231 | * allocate the VFs. The reason for ordering it this way is because it is much | |
2232 | * mor expensive time wise to disable SR-IOV than it is to allocate and free | |
2233 | * the memory for the VFs. | |
2234 | **/ | |
2235 | static void __devinit igb_probe_vfs(struct igb_adapter * adapter) | |
2236 | { | |
2237 | #ifdef CONFIG_PCI_IOV | |
2238 | struct pci_dev *pdev = adapter->pdev; | |
2239 | ||
a6b623e0 AD |
2240 | if (adapter->vfs_allocated_count) { |
2241 | adapter->vf_data = kcalloc(adapter->vfs_allocated_count, | |
2242 | sizeof(struct vf_data_storage), | |
2243 | GFP_KERNEL); | |
2244 | /* if allocation failed then we do not support SR-IOV */ | |
2245 | if (!adapter->vf_data) { | |
2246 | adapter->vfs_allocated_count = 0; | |
2247 | dev_err(&pdev->dev, "Unable to allocate memory for VF " | |
2248 | "Data Storage\n"); | |
2249 | } | |
2250 | } | |
2251 | ||
2252 | if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) { | |
2253 | kfree(adapter->vf_data); | |
2254 | adapter->vf_data = NULL; | |
2255 | #endif /* CONFIG_PCI_IOV */ | |
2256 | adapter->vfs_allocated_count = 0; | |
2257 | #ifdef CONFIG_PCI_IOV | |
2258 | } else { | |
2259 | unsigned char mac_addr[ETH_ALEN]; | |
2260 | int i; | |
2261 | dev_info(&pdev->dev, "%d vfs allocated\n", | |
2262 | adapter->vfs_allocated_count); | |
2263 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
2264 | random_ether_addr(mac_addr); | |
2265 | igb_set_vf_mac(adapter, i, mac_addr); | |
2266 | } | |
831ec0b4 CW |
2267 | /* DMA Coalescing is not supported in IOV mode. */ |
2268 | if (adapter->flags & IGB_FLAG_DMAC) | |
2269 | adapter->flags &= ~IGB_FLAG_DMAC; | |
a6b623e0 AD |
2270 | } |
2271 | #endif /* CONFIG_PCI_IOV */ | |
2272 | } | |
2273 | ||
115f459a AD |
2274 | |
2275 | /** | |
2276 | * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp | |
2277 | * @adapter: board private structure to initialize | |
2278 | * | |
2279 | * igb_init_hw_timer initializes the function pointer and values for the hw | |
2280 | * timer found in hardware. | |
2281 | **/ | |
2282 | static void igb_init_hw_timer(struct igb_adapter *adapter) | |
2283 | { | |
2284 | struct e1000_hw *hw = &adapter->hw; | |
2285 | ||
2286 | switch (hw->mac.type) { | |
d2ba2ed8 | 2287 | case e1000_i350: |
55cac248 AD |
2288 | case e1000_82580: |
2289 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
2290 | adapter->cycles.read = igb_read_clock; | |
2291 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
2292 | adapter->cycles.mult = 1; | |
2293 | /* | |
2294 | * The 82580 timesync updates the system timer every 8ns by 8ns | |
2295 | * and the value cannot be shifted. Instead we need to shift | |
2296 | * the registers to generate a 64bit timer value. As a result | |
2297 | * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by | |
2298 | * 24 in order to generate a larger value for synchronization. | |
2299 | */ | |
2300 | adapter->cycles.shift = IGB_82580_TSYNC_SHIFT; | |
2301 | /* disable system timer temporarily by setting bit 31 */ | |
2302 | wr32(E1000_TSAUXC, 0x80000000); | |
2303 | wrfl(); | |
2304 | ||
2305 | /* Set registers so that rollover occurs soon to test this. */ | |
2306 | wr32(E1000_SYSTIMR, 0x00000000); | |
2307 | wr32(E1000_SYSTIML, 0x80000000); | |
2308 | wr32(E1000_SYSTIMH, 0x000000FF); | |
2309 | wrfl(); | |
2310 | ||
2311 | /* enable system timer by clearing bit 31 */ | |
2312 | wr32(E1000_TSAUXC, 0x0); | |
2313 | wrfl(); | |
2314 | ||
2315 | timecounter_init(&adapter->clock, | |
2316 | &adapter->cycles, | |
2317 | ktime_to_ns(ktime_get_real())); | |
2318 | /* | |
2319 | * Synchronize our NIC clock against system wall clock. NIC | |
2320 | * time stamp reading requires ~3us per sample, each sample | |
2321 | * was pretty stable even under load => only require 10 | |
2322 | * samples for each offset comparison. | |
2323 | */ | |
2324 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
2325 | adapter->compare.source = &adapter->clock; | |
2326 | adapter->compare.target = ktime_get_real; | |
2327 | adapter->compare.num_samples = 10; | |
2328 | timecompare_update(&adapter->compare, 0); | |
2329 | break; | |
115f459a AD |
2330 | case e1000_82576: |
2331 | /* | |
2332 | * Initialize hardware timer: we keep it running just in case | |
2333 | * that some program needs it later on. | |
2334 | */ | |
2335 | memset(&adapter->cycles, 0, sizeof(adapter->cycles)); | |
2336 | adapter->cycles.read = igb_read_clock; | |
2337 | adapter->cycles.mask = CLOCKSOURCE_MASK(64); | |
2338 | adapter->cycles.mult = 1; | |
2339 | /** | |
2340 | * Scale the NIC clock cycle by a large factor so that | |
2341 | * relatively small clock corrections can be added or | |
25985edc | 2342 | * subtracted at each clock tick. The drawbacks of a large |
115f459a AD |
2343 | * factor are a) that the clock register overflows more quickly |
2344 | * (not such a big deal) and b) that the increment per tick has | |
2345 | * to fit into 24 bits. As a result we need to use a shift of | |
2346 | * 19 so we can fit a value of 16 into the TIMINCA register. | |
2347 | */ | |
2348 | adapter->cycles.shift = IGB_82576_TSYNC_SHIFT; | |
2349 | wr32(E1000_TIMINCA, | |
2350 | (1 << E1000_TIMINCA_16NS_SHIFT) | | |
2351 | (16 << IGB_82576_TSYNC_SHIFT)); | |
2352 | ||
2353 | /* Set registers so that rollover occurs soon to test this. */ | |
2354 | wr32(E1000_SYSTIML, 0x00000000); | |
2355 | wr32(E1000_SYSTIMH, 0xFF800000); | |
2356 | wrfl(); | |
2357 | ||
2358 | timecounter_init(&adapter->clock, | |
2359 | &adapter->cycles, | |
2360 | ktime_to_ns(ktime_get_real())); | |
2361 | /* | |
2362 | * Synchronize our NIC clock against system wall clock. NIC | |
2363 | * time stamp reading requires ~3us per sample, each sample | |
2364 | * was pretty stable even under load => only require 10 | |
2365 | * samples for each offset comparison. | |
2366 | */ | |
2367 | memset(&adapter->compare, 0, sizeof(adapter->compare)); | |
2368 | adapter->compare.source = &adapter->clock; | |
2369 | adapter->compare.target = ktime_get_real; | |
2370 | adapter->compare.num_samples = 10; | |
2371 | timecompare_update(&adapter->compare, 0); | |
2372 | break; | |
2373 | case e1000_82575: | |
2374 | /* 82575 does not support timesync */ | |
2375 | default: | |
2376 | break; | |
2377 | } | |
2378 | ||
2379 | } | |
2380 | ||
9d5c8243 AK |
2381 | /** |
2382 | * igb_sw_init - Initialize general software structures (struct igb_adapter) | |
2383 | * @adapter: board private structure to initialize | |
2384 | * | |
2385 | * igb_sw_init initializes the Adapter private data structure. | |
2386 | * Fields are initialized based on PCI device information and | |
2387 | * OS network device settings (MTU size). | |
2388 | **/ | |
2389 | static int __devinit igb_sw_init(struct igb_adapter *adapter) | |
2390 | { | |
2391 | struct e1000_hw *hw = &adapter->hw; | |
2392 | struct net_device *netdev = adapter->netdev; | |
2393 | struct pci_dev *pdev = adapter->pdev; | |
2394 | ||
2395 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
2396 | ||
13fde97a | 2397 | /* set default ring sizes */ |
68fd9910 AD |
2398 | adapter->tx_ring_count = IGB_DEFAULT_TXD; |
2399 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
13fde97a AD |
2400 | |
2401 | /* set default ITR values */ | |
4fc82adf AD |
2402 | adapter->rx_itr_setting = IGB_DEFAULT_ITR; |
2403 | adapter->tx_itr_setting = IGB_DEFAULT_ITR; | |
2404 | ||
13fde97a AD |
2405 | /* set default work limits */ |
2406 | adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; | |
2407 | ||
153285f9 AD |
2408 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + |
2409 | VLAN_HLEN; | |
9d5c8243 AK |
2410 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; |
2411 | ||
12dcd86b | 2412 | spin_lock_init(&adapter->stats64_lock); |
a6b623e0 | 2413 | #ifdef CONFIG_PCI_IOV |
6b78bb1d CW |
2414 | switch (hw->mac.type) { |
2415 | case e1000_82576: | |
2416 | case e1000_i350: | |
9b082d73 SA |
2417 | if (max_vfs > 7) { |
2418 | dev_warn(&pdev->dev, | |
2419 | "Maximum of 7 VFs per PF, using max\n"); | |
2420 | adapter->vfs_allocated_count = 7; | |
2421 | } else | |
2422 | adapter->vfs_allocated_count = max_vfs; | |
6b78bb1d CW |
2423 | break; |
2424 | default: | |
2425 | break; | |
2426 | } | |
a6b623e0 | 2427 | #endif /* CONFIG_PCI_IOV */ |
a99955fc | 2428 | adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus()); |
665c8c8e WM |
2429 | /* i350 cannot do RSS and SR-IOV at the same time */ |
2430 | if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count) | |
2431 | adapter->rss_queues = 1; | |
a99955fc AD |
2432 | |
2433 | /* | |
2434 | * if rss_queues > 4 or vfs are going to be allocated with rss_queues | |
2435 | * then we should combine the queues into a queue pair in order to | |
2436 | * conserve interrupts due to limited supply | |
2437 | */ | |
2438 | if ((adapter->rss_queues > 4) || | |
2439 | ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6))) | |
2440 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
2441 | ||
a6b623e0 | 2442 | /* This call may decrease the number of queues */ |
047e0030 | 2443 | if (igb_init_interrupt_scheme(adapter)) { |
9d5c8243 AK |
2444 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
2445 | return -ENOMEM; | |
2446 | } | |
2447 | ||
a6b623e0 AD |
2448 | igb_probe_vfs(adapter); |
2449 | ||
9d5c8243 AK |
2450 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
2451 | igb_irq_disable(adapter); | |
2452 | ||
831ec0b4 CW |
2453 | if (hw->mac.type == e1000_i350) |
2454 | adapter->flags &= ~IGB_FLAG_DMAC; | |
2455 | ||
9d5c8243 AK |
2456 | set_bit(__IGB_DOWN, &adapter->state); |
2457 | return 0; | |
2458 | } | |
2459 | ||
2460 | /** | |
2461 | * igb_open - Called when a network interface is made active | |
2462 | * @netdev: network interface device structure | |
2463 | * | |
2464 | * Returns 0 on success, negative value on failure | |
2465 | * | |
2466 | * The open entry point is called when a network interface is made | |
2467 | * active by the system (IFF_UP). At this point all resources needed | |
2468 | * for transmit and receive operations are allocated, the interrupt | |
2469 | * handler is registered with the OS, the watchdog timer is started, | |
2470 | * and the stack is notified that the interface is ready. | |
2471 | **/ | |
2472 | static int igb_open(struct net_device *netdev) | |
2473 | { | |
2474 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2475 | struct e1000_hw *hw = &adapter->hw; | |
2476 | int err; | |
2477 | int i; | |
2478 | ||
2479 | /* disallow open during test */ | |
2480 | if (test_bit(__IGB_TESTING, &adapter->state)) | |
2481 | return -EBUSY; | |
2482 | ||
b168dfc5 JB |
2483 | netif_carrier_off(netdev); |
2484 | ||
9d5c8243 AK |
2485 | /* allocate transmit descriptors */ |
2486 | err = igb_setup_all_tx_resources(adapter); | |
2487 | if (err) | |
2488 | goto err_setup_tx; | |
2489 | ||
2490 | /* allocate receive descriptors */ | |
2491 | err = igb_setup_all_rx_resources(adapter); | |
2492 | if (err) | |
2493 | goto err_setup_rx; | |
2494 | ||
88a268c1 | 2495 | igb_power_up_link(adapter); |
9d5c8243 | 2496 | |
9d5c8243 AK |
2497 | /* before we allocate an interrupt, we must be ready to handle it. |
2498 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
2499 | * as soon as we call pci_request_irq, so we have to setup our | |
2500 | * clean_rx handler before we do so. */ | |
2501 | igb_configure(adapter); | |
2502 | ||
2503 | err = igb_request_irq(adapter); | |
2504 | if (err) | |
2505 | goto err_req_irq; | |
2506 | ||
2507 | /* From here on the code is the same as igb_up() */ | |
2508 | clear_bit(__IGB_DOWN, &adapter->state); | |
2509 | ||
047e0030 AD |
2510 | for (i = 0; i < adapter->num_q_vectors; i++) { |
2511 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
2512 | napi_enable(&q_vector->napi); | |
2513 | } | |
9d5c8243 AK |
2514 | |
2515 | /* Clear any pending interrupts. */ | |
2516 | rd32(E1000_ICR); | |
844290e5 PW |
2517 | |
2518 | igb_irq_enable(adapter); | |
2519 | ||
d4960307 AD |
2520 | /* notify VFs that reset has been completed */ |
2521 | if (adapter->vfs_allocated_count) { | |
2522 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
2523 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
2524 | wr32(E1000_CTRL_EXT, reg_data); | |
2525 | } | |
2526 | ||
d55b53ff JK |
2527 | netif_tx_start_all_queues(netdev); |
2528 | ||
25568a53 AD |
2529 | /* start the watchdog. */ |
2530 | hw->mac.get_link_status = 1; | |
2531 | schedule_work(&adapter->watchdog_task); | |
9d5c8243 AK |
2532 | |
2533 | return 0; | |
2534 | ||
2535 | err_req_irq: | |
2536 | igb_release_hw_control(adapter); | |
88a268c1 | 2537 | igb_power_down_link(adapter); |
9d5c8243 AK |
2538 | igb_free_all_rx_resources(adapter); |
2539 | err_setup_rx: | |
2540 | igb_free_all_tx_resources(adapter); | |
2541 | err_setup_tx: | |
2542 | igb_reset(adapter); | |
2543 | ||
2544 | return err; | |
2545 | } | |
2546 | ||
2547 | /** | |
2548 | * igb_close - Disables a network interface | |
2549 | * @netdev: network interface device structure | |
2550 | * | |
2551 | * Returns 0, this is not allowed to fail | |
2552 | * | |
2553 | * The close entry point is called when an interface is de-activated | |
2554 | * by the OS. The hardware is still under the driver's control, but | |
2555 | * needs to be disabled. A global MAC reset is issued to stop the | |
2556 | * hardware, and all transmit and receive resources are freed. | |
2557 | **/ | |
2558 | static int igb_close(struct net_device *netdev) | |
2559 | { | |
2560 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2561 | ||
2562 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
2563 | igb_down(adapter); | |
2564 | ||
2565 | igb_free_irq(adapter); | |
2566 | ||
2567 | igb_free_all_tx_resources(adapter); | |
2568 | igb_free_all_rx_resources(adapter); | |
2569 | ||
9d5c8243 AK |
2570 | return 0; |
2571 | } | |
2572 | ||
2573 | /** | |
2574 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
9d5c8243 AK |
2575 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
2576 | * | |
2577 | * Return 0 on success, negative on failure | |
2578 | **/ | |
80785298 | 2579 | int igb_setup_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2580 | { |
59d71989 | 2581 | struct device *dev = tx_ring->dev; |
9d5c8243 AK |
2582 | int size; |
2583 | ||
06034649 AD |
2584 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
2585 | tx_ring->tx_buffer_info = vzalloc(size); | |
2586 | if (!tx_ring->tx_buffer_info) | |
9d5c8243 | 2587 | goto err; |
9d5c8243 AK |
2588 | |
2589 | /* round up to nearest 4K */ | |
85e8d004 | 2590 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
2591 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
2592 | ||
59d71989 AD |
2593 | tx_ring->desc = dma_alloc_coherent(dev, |
2594 | tx_ring->size, | |
2595 | &tx_ring->dma, | |
2596 | GFP_KERNEL); | |
9d5c8243 AK |
2597 | |
2598 | if (!tx_ring->desc) | |
2599 | goto err; | |
2600 | ||
9d5c8243 AK |
2601 | tx_ring->next_to_use = 0; |
2602 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
2603 | return 0; |
2604 | ||
2605 | err: | |
06034649 | 2606 | vfree(tx_ring->tx_buffer_info); |
59d71989 | 2607 | dev_err(dev, |
9d5c8243 AK |
2608 | "Unable to allocate memory for the transmit descriptor ring\n"); |
2609 | return -ENOMEM; | |
2610 | } | |
2611 | ||
2612 | /** | |
2613 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources | |
2614 | * (Descriptors) for all queues | |
2615 | * @adapter: board private structure | |
2616 | * | |
2617 | * Return 0 on success, negative on failure | |
2618 | **/ | |
2619 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
2620 | { | |
439705e1 | 2621 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2622 | int i, err = 0; |
2623 | ||
2624 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 2625 | err = igb_setup_tx_resources(adapter->tx_ring[i]); |
9d5c8243 | 2626 | if (err) { |
439705e1 | 2627 | dev_err(&pdev->dev, |
9d5c8243 AK |
2628 | "Allocation for Tx Queue %u failed\n", i); |
2629 | for (i--; i >= 0; i--) | |
3025a446 | 2630 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
2631 | break; |
2632 | } | |
2633 | } | |
2634 | ||
2635 | return err; | |
2636 | } | |
2637 | ||
2638 | /** | |
85b430b4 AD |
2639 | * igb_setup_tctl - configure the transmit control registers |
2640 | * @adapter: Board private structure | |
9d5c8243 | 2641 | **/ |
d7ee5b3a | 2642 | void igb_setup_tctl(struct igb_adapter *adapter) |
9d5c8243 | 2643 | { |
9d5c8243 AK |
2644 | struct e1000_hw *hw = &adapter->hw; |
2645 | u32 tctl; | |
9d5c8243 | 2646 | |
85b430b4 AD |
2647 | /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
2648 | wr32(E1000_TXDCTL(0), 0); | |
9d5c8243 AK |
2649 | |
2650 | /* Program the Transmit Control Register */ | |
9d5c8243 AK |
2651 | tctl = rd32(E1000_TCTL); |
2652 | tctl &= ~E1000_TCTL_CT; | |
2653 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
2654 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
2655 | ||
2656 | igb_config_collision_dist(hw); | |
2657 | ||
9d5c8243 AK |
2658 | /* Enable transmits */ |
2659 | tctl |= E1000_TCTL_EN; | |
2660 | ||
2661 | wr32(E1000_TCTL, tctl); | |
2662 | } | |
2663 | ||
85b430b4 AD |
2664 | /** |
2665 | * igb_configure_tx_ring - Configure transmit ring after Reset | |
2666 | * @adapter: board private structure | |
2667 | * @ring: tx ring to configure | |
2668 | * | |
2669 | * Configure a transmit ring after a reset. | |
2670 | **/ | |
d7ee5b3a AD |
2671 | void igb_configure_tx_ring(struct igb_adapter *adapter, |
2672 | struct igb_ring *ring) | |
85b430b4 AD |
2673 | { |
2674 | struct e1000_hw *hw = &adapter->hw; | |
a74420e0 | 2675 | u32 txdctl = 0; |
85b430b4 AD |
2676 | u64 tdba = ring->dma; |
2677 | int reg_idx = ring->reg_idx; | |
2678 | ||
2679 | /* disable the queue */ | |
a74420e0 | 2680 | wr32(E1000_TXDCTL(reg_idx), 0); |
85b430b4 AD |
2681 | wrfl(); |
2682 | mdelay(10); | |
2683 | ||
2684 | wr32(E1000_TDLEN(reg_idx), | |
2685 | ring->count * sizeof(union e1000_adv_tx_desc)); | |
2686 | wr32(E1000_TDBAL(reg_idx), | |
2687 | tdba & 0x00000000ffffffffULL); | |
2688 | wr32(E1000_TDBAH(reg_idx), tdba >> 32); | |
2689 | ||
fce99e34 | 2690 | ring->tail = hw->hw_addr + E1000_TDT(reg_idx); |
a74420e0 | 2691 | wr32(E1000_TDH(reg_idx), 0); |
fce99e34 | 2692 | writel(0, ring->tail); |
85b430b4 AD |
2693 | |
2694 | txdctl |= IGB_TX_PTHRESH; | |
2695 | txdctl |= IGB_TX_HTHRESH << 8; | |
2696 | txdctl |= IGB_TX_WTHRESH << 16; | |
2697 | ||
2698 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | |
2699 | wr32(E1000_TXDCTL(reg_idx), txdctl); | |
2700 | } | |
2701 | ||
2702 | /** | |
2703 | * igb_configure_tx - Configure transmit Unit after Reset | |
2704 | * @adapter: board private structure | |
2705 | * | |
2706 | * Configure the Tx unit of the MAC after a reset. | |
2707 | **/ | |
2708 | static void igb_configure_tx(struct igb_adapter *adapter) | |
2709 | { | |
2710 | int i; | |
2711 | ||
2712 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 2713 | igb_configure_tx_ring(adapter, adapter->tx_ring[i]); |
85b430b4 AD |
2714 | } |
2715 | ||
9d5c8243 AK |
2716 | /** |
2717 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
9d5c8243 AK |
2718 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
2719 | * | |
2720 | * Returns 0 on success, negative on failure | |
2721 | **/ | |
80785298 | 2722 | int igb_setup_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 2723 | { |
59d71989 | 2724 | struct device *dev = rx_ring->dev; |
9d5c8243 AK |
2725 | int size, desc_len; |
2726 | ||
06034649 AD |
2727 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
2728 | rx_ring->rx_buffer_info = vzalloc(size); | |
2729 | if (!rx_ring->rx_buffer_info) | |
9d5c8243 | 2730 | goto err; |
9d5c8243 AK |
2731 | |
2732 | desc_len = sizeof(union e1000_adv_rx_desc); | |
2733 | ||
2734 | /* Round up to nearest 4K */ | |
2735 | rx_ring->size = rx_ring->count * desc_len; | |
2736 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
2737 | ||
59d71989 AD |
2738 | rx_ring->desc = dma_alloc_coherent(dev, |
2739 | rx_ring->size, | |
2740 | &rx_ring->dma, | |
2741 | GFP_KERNEL); | |
9d5c8243 AK |
2742 | |
2743 | if (!rx_ring->desc) | |
2744 | goto err; | |
2745 | ||
2746 | rx_ring->next_to_clean = 0; | |
2747 | rx_ring->next_to_use = 0; | |
9d5c8243 | 2748 | |
9d5c8243 AK |
2749 | return 0; |
2750 | ||
2751 | err: | |
06034649 AD |
2752 | vfree(rx_ring->rx_buffer_info); |
2753 | rx_ring->rx_buffer_info = NULL; | |
59d71989 AD |
2754 | dev_err(dev, "Unable to allocate memory for the receive descriptor" |
2755 | " ring\n"); | |
9d5c8243 AK |
2756 | return -ENOMEM; |
2757 | } | |
2758 | ||
2759 | /** | |
2760 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources | |
2761 | * (Descriptors) for all queues | |
2762 | * @adapter: board private structure | |
2763 | * | |
2764 | * Return 0 on success, negative on failure | |
2765 | **/ | |
2766 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
2767 | { | |
439705e1 | 2768 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2769 | int i, err = 0; |
2770 | ||
2771 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 2772 | err = igb_setup_rx_resources(adapter->rx_ring[i]); |
9d5c8243 | 2773 | if (err) { |
439705e1 | 2774 | dev_err(&pdev->dev, |
9d5c8243 AK |
2775 | "Allocation for Rx Queue %u failed\n", i); |
2776 | for (i--; i >= 0; i--) | |
3025a446 | 2777 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
2778 | break; |
2779 | } | |
2780 | } | |
2781 | ||
2782 | return err; | |
2783 | } | |
2784 | ||
06cf2666 AD |
2785 | /** |
2786 | * igb_setup_mrqc - configure the multiple receive queue control registers | |
2787 | * @adapter: Board private structure | |
2788 | **/ | |
2789 | static void igb_setup_mrqc(struct igb_adapter *adapter) | |
2790 | { | |
2791 | struct e1000_hw *hw = &adapter->hw; | |
2792 | u32 mrqc, rxcsum; | |
2793 | u32 j, num_rx_queues, shift = 0, shift2 = 0; | |
2794 | union e1000_reta { | |
2795 | u32 dword; | |
2796 | u8 bytes[4]; | |
2797 | } reta; | |
2798 | static const u8 rsshash[40] = { | |
2799 | 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67, | |
2800 | 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb, | |
2801 | 0xae, 0x7b, 0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, | |
2802 | 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa }; | |
2803 | ||
2804 | /* Fill out hash function seeds */ | |
2805 | for (j = 0; j < 10; j++) { | |
2806 | u32 rsskey = rsshash[(j * 4)]; | |
2807 | rsskey |= rsshash[(j * 4) + 1] << 8; | |
2808 | rsskey |= rsshash[(j * 4) + 2] << 16; | |
2809 | rsskey |= rsshash[(j * 4) + 3] << 24; | |
2810 | array_wr32(E1000_RSSRK(0), j, rsskey); | |
2811 | } | |
2812 | ||
a99955fc | 2813 | num_rx_queues = adapter->rss_queues; |
06cf2666 AD |
2814 | |
2815 | if (adapter->vfs_allocated_count) { | |
2816 | /* 82575 and 82576 supports 2 RSS queues for VMDq */ | |
2817 | switch (hw->mac.type) { | |
d2ba2ed8 | 2818 | case e1000_i350: |
55cac248 AD |
2819 | case e1000_82580: |
2820 | num_rx_queues = 1; | |
2821 | shift = 0; | |
2822 | break; | |
06cf2666 AD |
2823 | case e1000_82576: |
2824 | shift = 3; | |
2825 | num_rx_queues = 2; | |
2826 | break; | |
2827 | case e1000_82575: | |
2828 | shift = 2; | |
2829 | shift2 = 6; | |
2830 | default: | |
2831 | break; | |
2832 | } | |
2833 | } else { | |
2834 | if (hw->mac.type == e1000_82575) | |
2835 | shift = 6; | |
2836 | } | |
2837 | ||
2838 | for (j = 0; j < (32 * 4); j++) { | |
2839 | reta.bytes[j & 3] = (j % num_rx_queues) << shift; | |
2840 | if (shift2) | |
2841 | reta.bytes[j & 3] |= num_rx_queues << shift2; | |
2842 | if ((j & 3) == 3) | |
2843 | wr32(E1000_RETA(j >> 2), reta.dword); | |
2844 | } | |
2845 | ||
2846 | /* | |
2847 | * Disable raw packet checksumming so that RSS hash is placed in | |
2848 | * descriptor on writeback. No need to enable TCP/UDP/IP checksum | |
2849 | * offloads as they are enabled by default | |
2850 | */ | |
2851 | rxcsum = rd32(E1000_RXCSUM); | |
2852 | rxcsum |= E1000_RXCSUM_PCSD; | |
2853 | ||
2854 | if (adapter->hw.mac.type >= e1000_82576) | |
2855 | /* Enable Receive Checksum Offload for SCTP */ | |
2856 | rxcsum |= E1000_RXCSUM_CRCOFL; | |
2857 | ||
2858 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | |
2859 | wr32(E1000_RXCSUM, rxcsum); | |
2860 | ||
2861 | /* If VMDq is enabled then we set the appropriate mode for that, else | |
2862 | * we default to RSS so that an RSS hash is calculated per packet even | |
2863 | * if we are only using one queue */ | |
2864 | if (adapter->vfs_allocated_count) { | |
2865 | if (hw->mac.type > e1000_82575) { | |
2866 | /* Set the default pool for the PF's first queue */ | |
2867 | u32 vtctl = rd32(E1000_VT_CTL); | |
2868 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | |
2869 | E1000_VT_CTL_DISABLE_DEF_POOL); | |
2870 | vtctl |= adapter->vfs_allocated_count << | |
2871 | E1000_VT_CTL_DEFAULT_POOL_SHIFT; | |
2872 | wr32(E1000_VT_CTL, vtctl); | |
2873 | } | |
a99955fc | 2874 | if (adapter->rss_queues > 1) |
06cf2666 AD |
2875 | mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q; |
2876 | else | |
2877 | mrqc = E1000_MRQC_ENABLE_VMDQ; | |
2878 | } else { | |
2879 | mrqc = E1000_MRQC_ENABLE_RSS_4Q; | |
2880 | } | |
2881 | igb_vmm_control(adapter); | |
2882 | ||
4478a9cd AD |
2883 | /* |
2884 | * Generate RSS hash based on TCP port numbers and/or | |
2885 | * IPv4/v6 src and dst addresses since UDP cannot be | |
2886 | * hashed reliably due to IP fragmentation | |
2887 | */ | |
2888 | mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | | |
2889 | E1000_MRQC_RSS_FIELD_IPV4_TCP | | |
2890 | E1000_MRQC_RSS_FIELD_IPV6 | | |
2891 | E1000_MRQC_RSS_FIELD_IPV6_TCP | | |
2892 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; | |
06cf2666 AD |
2893 | |
2894 | wr32(E1000_MRQC, mrqc); | |
2895 | } | |
2896 | ||
9d5c8243 AK |
2897 | /** |
2898 | * igb_setup_rctl - configure the receive control registers | |
2899 | * @adapter: Board private structure | |
2900 | **/ | |
d7ee5b3a | 2901 | void igb_setup_rctl(struct igb_adapter *adapter) |
9d5c8243 AK |
2902 | { |
2903 | struct e1000_hw *hw = &adapter->hw; | |
2904 | u32 rctl; | |
9d5c8243 AK |
2905 | |
2906 | rctl = rd32(E1000_RCTL); | |
2907 | ||
2908 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 2909 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 2910 | |
69d728ba | 2911 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 2912 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 2913 | |
87cb7e8c AK |
2914 | /* |
2915 | * enable stripping of CRC. It's unlikely this will break BMC | |
2916 | * redirection as it did with e1000. Newer features require | |
2917 | * that the HW strips the CRC. | |
73cd78f1 | 2918 | */ |
87cb7e8c | 2919 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 2920 | |
559e9c49 | 2921 | /* disable store bad packets and clear size bits. */ |
ec54d7d6 | 2922 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 2923 | |
6ec43fe6 AD |
2924 | /* enable LPE to prevent packets larger than max_frame_size */ |
2925 | rctl |= E1000_RCTL_LPE; | |
9d5c8243 | 2926 | |
952f72a8 AD |
2927 | /* disable queue 0 to prevent tail write w/o re-config */ |
2928 | wr32(E1000_RXDCTL(0), 0); | |
9d5c8243 | 2929 | |
e1739522 AD |
2930 | /* Attention!!! For SR-IOV PF driver operations you must enable |
2931 | * queue drop for all VF and PF queues to prevent head of line blocking | |
2932 | * if an un-trusted VF does not provide descriptors to hardware. | |
2933 | */ | |
2934 | if (adapter->vfs_allocated_count) { | |
e1739522 AD |
2935 | /* set all queue drop enable bits */ |
2936 | wr32(E1000_QDE, ALL_QUEUES); | |
e1739522 AD |
2937 | } |
2938 | ||
9d5c8243 AK |
2939 | wr32(E1000_RCTL, rctl); |
2940 | } | |
2941 | ||
7d5753f0 AD |
2942 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
2943 | int vfn) | |
2944 | { | |
2945 | struct e1000_hw *hw = &adapter->hw; | |
2946 | u32 vmolr; | |
2947 | ||
2948 | /* if it isn't the PF check to see if VFs are enabled and | |
2949 | * increase the size to support vlan tags */ | |
2950 | if (vfn < adapter->vfs_allocated_count && | |
2951 | adapter->vf_data[vfn].vlans_enabled) | |
2952 | size += VLAN_TAG_SIZE; | |
2953 | ||
2954 | vmolr = rd32(E1000_VMOLR(vfn)); | |
2955 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | |
2956 | vmolr |= size | E1000_VMOLR_LPE; | |
2957 | wr32(E1000_VMOLR(vfn), vmolr); | |
2958 | ||
2959 | return 0; | |
2960 | } | |
2961 | ||
e1739522 AD |
2962 | /** |
2963 | * igb_rlpml_set - set maximum receive packet size | |
2964 | * @adapter: board private structure | |
2965 | * | |
2966 | * Configure maximum receivable packet size. | |
2967 | **/ | |
2968 | static void igb_rlpml_set(struct igb_adapter *adapter) | |
2969 | { | |
153285f9 | 2970 | u32 max_frame_size = adapter->max_frame_size; |
e1739522 AD |
2971 | struct e1000_hw *hw = &adapter->hw; |
2972 | u16 pf_id = adapter->vfs_allocated_count; | |
2973 | ||
e1739522 AD |
2974 | if (pf_id) { |
2975 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | |
153285f9 AD |
2976 | /* |
2977 | * If we're in VMDQ or SR-IOV mode, then set global RLPML | |
2978 | * to our max jumbo frame size, in case we need to enable | |
2979 | * jumbo frames on one of the rings later. | |
2980 | * This will not pass over-length frames into the default | |
2981 | * queue because it's gated by the VMOLR.RLPML. | |
2982 | */ | |
7d5753f0 | 2983 | max_frame_size = MAX_JUMBO_FRAME_SIZE; |
e1739522 AD |
2984 | } |
2985 | ||
2986 | wr32(E1000_RLPML, max_frame_size); | |
2987 | } | |
2988 | ||
8151d294 WM |
2989 | static inline void igb_set_vmolr(struct igb_adapter *adapter, |
2990 | int vfn, bool aupe) | |
7d5753f0 AD |
2991 | { |
2992 | struct e1000_hw *hw = &adapter->hw; | |
2993 | u32 vmolr; | |
2994 | ||
2995 | /* | |
2996 | * This register exists only on 82576 and newer so if we are older then | |
2997 | * we should exit and do nothing | |
2998 | */ | |
2999 | if (hw->mac.type < e1000_82576) | |
3000 | return; | |
3001 | ||
3002 | vmolr = rd32(E1000_VMOLR(vfn)); | |
8151d294 WM |
3003 | vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ |
3004 | if (aupe) | |
3005 | vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ | |
3006 | else | |
3007 | vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ | |
7d5753f0 AD |
3008 | |
3009 | /* clear all bits that might not be set */ | |
3010 | vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); | |
3011 | ||
a99955fc | 3012 | if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) |
7d5753f0 AD |
3013 | vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ |
3014 | /* | |
3015 | * for VMDq only allow the VFs and pool 0 to accept broadcast and | |
3016 | * multicast packets | |
3017 | */ | |
3018 | if (vfn <= adapter->vfs_allocated_count) | |
3019 | vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ | |
3020 | ||
3021 | wr32(E1000_VMOLR(vfn), vmolr); | |
3022 | } | |
3023 | ||
85b430b4 AD |
3024 | /** |
3025 | * igb_configure_rx_ring - Configure a receive ring after Reset | |
3026 | * @adapter: board private structure | |
3027 | * @ring: receive ring to be configured | |
3028 | * | |
3029 | * Configure the Rx unit of the MAC after a reset. | |
3030 | **/ | |
d7ee5b3a AD |
3031 | void igb_configure_rx_ring(struct igb_adapter *adapter, |
3032 | struct igb_ring *ring) | |
85b430b4 AD |
3033 | { |
3034 | struct e1000_hw *hw = &adapter->hw; | |
3035 | u64 rdba = ring->dma; | |
3036 | int reg_idx = ring->reg_idx; | |
a74420e0 | 3037 | u32 srrctl = 0, rxdctl = 0; |
85b430b4 AD |
3038 | |
3039 | /* disable the queue */ | |
a74420e0 | 3040 | wr32(E1000_RXDCTL(reg_idx), 0); |
85b430b4 AD |
3041 | |
3042 | /* Set DMA base address registers */ | |
3043 | wr32(E1000_RDBAL(reg_idx), | |
3044 | rdba & 0x00000000ffffffffULL); | |
3045 | wr32(E1000_RDBAH(reg_idx), rdba >> 32); | |
3046 | wr32(E1000_RDLEN(reg_idx), | |
3047 | ring->count * sizeof(union e1000_adv_rx_desc)); | |
3048 | ||
3049 | /* initialize head and tail */ | |
fce99e34 | 3050 | ring->tail = hw->hw_addr + E1000_RDT(reg_idx); |
a74420e0 | 3051 | wr32(E1000_RDH(reg_idx), 0); |
fce99e34 | 3052 | writel(0, ring->tail); |
85b430b4 | 3053 | |
952f72a8 | 3054 | /* set descriptor configuration */ |
44390ca6 | 3055 | srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
952f72a8 | 3056 | #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 |
44390ca6 | 3057 | srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT; |
952f72a8 | 3058 | #else |
44390ca6 | 3059 | srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT; |
952f72a8 | 3060 | #endif |
44390ca6 | 3061 | srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
757b77e2 NN |
3062 | if (hw->mac.type == e1000_82580) |
3063 | srrctl |= E1000_SRRCTL_TIMESTAMP; | |
e6bdb6fe NN |
3064 | /* Only set Drop Enable if we are supporting multiple queues */ |
3065 | if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) | |
3066 | srrctl |= E1000_SRRCTL_DROP_EN; | |
952f72a8 AD |
3067 | |
3068 | wr32(E1000_SRRCTL(reg_idx), srrctl); | |
3069 | ||
7d5753f0 | 3070 | /* set filtering for VMDQ pools */ |
8151d294 | 3071 | igb_set_vmolr(adapter, reg_idx & 0x7, true); |
7d5753f0 | 3072 | |
85b430b4 AD |
3073 | rxdctl |= IGB_RX_PTHRESH; |
3074 | rxdctl |= IGB_RX_HTHRESH << 8; | |
3075 | rxdctl |= IGB_RX_WTHRESH << 16; | |
a74420e0 AD |
3076 | |
3077 | /* enable receive descriptor fetching */ | |
3078 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | |
85b430b4 AD |
3079 | wr32(E1000_RXDCTL(reg_idx), rxdctl); |
3080 | } | |
3081 | ||
9d5c8243 AK |
3082 | /** |
3083 | * igb_configure_rx - Configure receive Unit after Reset | |
3084 | * @adapter: board private structure | |
3085 | * | |
3086 | * Configure the Rx unit of the MAC after a reset. | |
3087 | **/ | |
3088 | static void igb_configure_rx(struct igb_adapter *adapter) | |
3089 | { | |
9107584e | 3090 | int i; |
9d5c8243 | 3091 | |
68d480c4 AD |
3092 | /* set UTA to appropriate mode */ |
3093 | igb_set_uta(adapter); | |
3094 | ||
26ad9178 AD |
3095 | /* set the correct pool for the PF default MAC address in entry 0 */ |
3096 | igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, | |
3097 | adapter->vfs_allocated_count); | |
3098 | ||
06cf2666 AD |
3099 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
3100 | * the Base and Length of the Rx Descriptor Ring */ | |
3101 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3102 | igb_configure_rx_ring(adapter, adapter->rx_ring[i]); |
9d5c8243 AK |
3103 | } |
3104 | ||
3105 | /** | |
3106 | * igb_free_tx_resources - Free Tx Resources per Queue | |
9d5c8243 AK |
3107 | * @tx_ring: Tx descriptor ring for a specific queue |
3108 | * | |
3109 | * Free all transmit software resources | |
3110 | **/ | |
68fd9910 | 3111 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 3112 | { |
3b644cf6 | 3113 | igb_clean_tx_ring(tx_ring); |
9d5c8243 | 3114 | |
06034649 AD |
3115 | vfree(tx_ring->tx_buffer_info); |
3116 | tx_ring->tx_buffer_info = NULL; | |
9d5c8243 | 3117 | |
439705e1 AD |
3118 | /* if not set, then don't free */ |
3119 | if (!tx_ring->desc) | |
3120 | return; | |
3121 | ||
59d71989 AD |
3122 | dma_free_coherent(tx_ring->dev, tx_ring->size, |
3123 | tx_ring->desc, tx_ring->dma); | |
9d5c8243 AK |
3124 | |
3125 | tx_ring->desc = NULL; | |
3126 | } | |
3127 | ||
3128 | /** | |
3129 | * igb_free_all_tx_resources - Free Tx Resources for All Queues | |
3130 | * @adapter: board private structure | |
3131 | * | |
3132 | * Free all transmit software resources | |
3133 | **/ | |
3134 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
3135 | { | |
3136 | int i; | |
3137 | ||
3138 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3139 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
3140 | } |
3141 | ||
ebe42d16 AD |
3142 | void igb_unmap_and_free_tx_resource(struct igb_ring *ring, |
3143 | struct igb_tx_buffer *tx_buffer) | |
3144 | { | |
3145 | if (tx_buffer->skb) { | |
3146 | dev_kfree_skb_any(tx_buffer->skb); | |
3147 | if (tx_buffer->dma) | |
3148 | dma_unmap_single(ring->dev, | |
3149 | tx_buffer->dma, | |
3150 | tx_buffer->length, | |
3151 | DMA_TO_DEVICE); | |
3152 | } else if (tx_buffer->dma) { | |
3153 | dma_unmap_page(ring->dev, | |
3154 | tx_buffer->dma, | |
3155 | tx_buffer->length, | |
3156 | DMA_TO_DEVICE); | |
3157 | } | |
3158 | tx_buffer->next_to_watch = NULL; | |
3159 | tx_buffer->skb = NULL; | |
3160 | tx_buffer->dma = 0; | |
3161 | /* buffer_info must be completely set up in the transmit path */ | |
9d5c8243 AK |
3162 | } |
3163 | ||
3164 | /** | |
3165 | * igb_clean_tx_ring - Free Tx Buffers | |
9d5c8243 AK |
3166 | * @tx_ring: ring to be cleaned |
3167 | **/ | |
3b644cf6 | 3168 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 3169 | { |
06034649 | 3170 | struct igb_tx_buffer *buffer_info; |
9d5c8243 AK |
3171 | unsigned long size; |
3172 | unsigned int i; | |
3173 | ||
06034649 | 3174 | if (!tx_ring->tx_buffer_info) |
9d5c8243 AK |
3175 | return; |
3176 | /* Free all the Tx ring sk_buffs */ | |
3177 | ||
3178 | for (i = 0; i < tx_ring->count; i++) { | |
06034649 | 3179 | buffer_info = &tx_ring->tx_buffer_info[i]; |
80785298 | 3180 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
9d5c8243 AK |
3181 | } |
3182 | ||
06034649 AD |
3183 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
3184 | memset(tx_ring->tx_buffer_info, 0, size); | |
9d5c8243 AK |
3185 | |
3186 | /* Zero out the descriptor ring */ | |
9d5c8243 AK |
3187 | memset(tx_ring->desc, 0, tx_ring->size); |
3188 | ||
3189 | tx_ring->next_to_use = 0; | |
3190 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
3191 | } |
3192 | ||
3193 | /** | |
3194 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues | |
3195 | * @adapter: board private structure | |
3196 | **/ | |
3197 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
3198 | { | |
3199 | int i; | |
3200 | ||
3201 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3202 | igb_clean_tx_ring(adapter->tx_ring[i]); |
9d5c8243 AK |
3203 | } |
3204 | ||
3205 | /** | |
3206 | * igb_free_rx_resources - Free Rx Resources | |
9d5c8243 AK |
3207 | * @rx_ring: ring to clean the resources from |
3208 | * | |
3209 | * Free all receive software resources | |
3210 | **/ | |
68fd9910 | 3211 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 3212 | { |
3b644cf6 | 3213 | igb_clean_rx_ring(rx_ring); |
9d5c8243 | 3214 | |
06034649 AD |
3215 | vfree(rx_ring->rx_buffer_info); |
3216 | rx_ring->rx_buffer_info = NULL; | |
9d5c8243 | 3217 | |
439705e1 AD |
3218 | /* if not set, then don't free */ |
3219 | if (!rx_ring->desc) | |
3220 | return; | |
3221 | ||
59d71989 AD |
3222 | dma_free_coherent(rx_ring->dev, rx_ring->size, |
3223 | rx_ring->desc, rx_ring->dma); | |
9d5c8243 AK |
3224 | |
3225 | rx_ring->desc = NULL; | |
3226 | } | |
3227 | ||
3228 | /** | |
3229 | * igb_free_all_rx_resources - Free Rx Resources for All Queues | |
3230 | * @adapter: board private structure | |
3231 | * | |
3232 | * Free all receive software resources | |
3233 | **/ | |
3234 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
3235 | { | |
3236 | int i; | |
3237 | ||
3238 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3239 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3240 | } |
3241 | ||
3242 | /** | |
3243 | * igb_clean_rx_ring - Free Rx Buffers per Queue | |
9d5c8243 AK |
3244 | * @rx_ring: ring to free buffers from |
3245 | **/ | |
3b644cf6 | 3246 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 3247 | { |
9d5c8243 | 3248 | unsigned long size; |
c023cd88 | 3249 | u16 i; |
9d5c8243 | 3250 | |
06034649 | 3251 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 3252 | return; |
439705e1 | 3253 | |
9d5c8243 AK |
3254 | /* Free all the Rx ring sk_buffs */ |
3255 | for (i = 0; i < rx_ring->count; i++) { | |
06034649 | 3256 | struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; |
9d5c8243 | 3257 | if (buffer_info->dma) { |
59d71989 | 3258 | dma_unmap_single(rx_ring->dev, |
80785298 | 3259 | buffer_info->dma, |
44390ca6 | 3260 | IGB_RX_HDR_LEN, |
59d71989 | 3261 | DMA_FROM_DEVICE); |
9d5c8243 AK |
3262 | buffer_info->dma = 0; |
3263 | } | |
3264 | ||
3265 | if (buffer_info->skb) { | |
3266 | dev_kfree_skb(buffer_info->skb); | |
3267 | buffer_info->skb = NULL; | |
3268 | } | |
6ec43fe6 | 3269 | if (buffer_info->page_dma) { |
59d71989 | 3270 | dma_unmap_page(rx_ring->dev, |
80785298 | 3271 | buffer_info->page_dma, |
6ec43fe6 | 3272 | PAGE_SIZE / 2, |
59d71989 | 3273 | DMA_FROM_DEVICE); |
6ec43fe6 AD |
3274 | buffer_info->page_dma = 0; |
3275 | } | |
9d5c8243 | 3276 | if (buffer_info->page) { |
9d5c8243 AK |
3277 | put_page(buffer_info->page); |
3278 | buffer_info->page = NULL; | |
bf36c1a0 | 3279 | buffer_info->page_offset = 0; |
9d5c8243 AK |
3280 | } |
3281 | } | |
3282 | ||
06034649 AD |
3283 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
3284 | memset(rx_ring->rx_buffer_info, 0, size); | |
9d5c8243 AK |
3285 | |
3286 | /* Zero out the descriptor ring */ | |
3287 | memset(rx_ring->desc, 0, rx_ring->size); | |
3288 | ||
3289 | rx_ring->next_to_clean = 0; | |
3290 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
3291 | } |
3292 | ||
3293 | /** | |
3294 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues | |
3295 | * @adapter: board private structure | |
3296 | **/ | |
3297 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
3298 | { | |
3299 | int i; | |
3300 | ||
3301 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3302 | igb_clean_rx_ring(adapter->rx_ring[i]); |
9d5c8243 AK |
3303 | } |
3304 | ||
3305 | /** | |
3306 | * igb_set_mac - Change the Ethernet Address of the NIC | |
3307 | * @netdev: network interface device structure | |
3308 | * @p: pointer to an address structure | |
3309 | * | |
3310 | * Returns 0 on success, negative on failure | |
3311 | **/ | |
3312 | static int igb_set_mac(struct net_device *netdev, void *p) | |
3313 | { | |
3314 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 3315 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3316 | struct sockaddr *addr = p; |
3317 | ||
3318 | if (!is_valid_ether_addr(addr->sa_data)) | |
3319 | return -EADDRNOTAVAIL; | |
3320 | ||
3321 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 3322 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 3323 | |
26ad9178 AD |
3324 | /* set the correct pool for the new PF MAC address in entry 0 */ |
3325 | igb_rar_set_qsel(adapter, hw->mac.addr, 0, | |
3326 | adapter->vfs_allocated_count); | |
e1739522 | 3327 | |
9d5c8243 AK |
3328 | return 0; |
3329 | } | |
3330 | ||
3331 | /** | |
68d480c4 | 3332 | * igb_write_mc_addr_list - write multicast addresses to MTA |
9d5c8243 AK |
3333 | * @netdev: network interface device structure |
3334 | * | |
68d480c4 AD |
3335 | * Writes multicast address list to the MTA hash table. |
3336 | * Returns: -ENOMEM on failure | |
3337 | * 0 on no addresses written | |
3338 | * X on writing X addresses to MTA | |
9d5c8243 | 3339 | **/ |
68d480c4 | 3340 | static int igb_write_mc_addr_list(struct net_device *netdev) |
9d5c8243 AK |
3341 | { |
3342 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3343 | struct e1000_hw *hw = &adapter->hw; | |
22bedad3 | 3344 | struct netdev_hw_addr *ha; |
68d480c4 | 3345 | u8 *mta_list; |
9d5c8243 AK |
3346 | int i; |
3347 | ||
4cd24eaf | 3348 | if (netdev_mc_empty(netdev)) { |
68d480c4 AD |
3349 | /* nothing to program, so clear mc list */ |
3350 | igb_update_mc_addr_list(hw, NULL, 0); | |
3351 | igb_restore_vf_multicasts(adapter); | |
3352 | return 0; | |
3353 | } | |
9d5c8243 | 3354 | |
4cd24eaf | 3355 | mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); |
68d480c4 AD |
3356 | if (!mta_list) |
3357 | return -ENOMEM; | |
ff41f8dc | 3358 | |
68d480c4 | 3359 | /* The shared function expects a packed array of only addresses. */ |
48e2f183 | 3360 | i = 0; |
22bedad3 JP |
3361 | netdev_for_each_mc_addr(ha, netdev) |
3362 | memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); | |
68d480c4 | 3363 | |
68d480c4 AD |
3364 | igb_update_mc_addr_list(hw, mta_list, i); |
3365 | kfree(mta_list); | |
3366 | ||
4cd24eaf | 3367 | return netdev_mc_count(netdev); |
68d480c4 AD |
3368 | } |
3369 | ||
3370 | /** | |
3371 | * igb_write_uc_addr_list - write unicast addresses to RAR table | |
3372 | * @netdev: network interface device structure | |
3373 | * | |
3374 | * Writes unicast address list to the RAR table. | |
3375 | * Returns: -ENOMEM on failure/insufficient address space | |
3376 | * 0 on no addresses written | |
3377 | * X on writing X addresses to the RAR table | |
3378 | **/ | |
3379 | static int igb_write_uc_addr_list(struct net_device *netdev) | |
3380 | { | |
3381 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3382 | struct e1000_hw *hw = &adapter->hw; | |
3383 | unsigned int vfn = adapter->vfs_allocated_count; | |
3384 | unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); | |
3385 | int count = 0; | |
3386 | ||
3387 | /* return ENOMEM indicating insufficient memory for addresses */ | |
32e7bfc4 | 3388 | if (netdev_uc_count(netdev) > rar_entries) |
68d480c4 | 3389 | return -ENOMEM; |
9d5c8243 | 3390 | |
32e7bfc4 | 3391 | if (!netdev_uc_empty(netdev) && rar_entries) { |
ff41f8dc | 3392 | struct netdev_hw_addr *ha; |
32e7bfc4 JP |
3393 | |
3394 | netdev_for_each_uc_addr(ha, netdev) { | |
ff41f8dc AD |
3395 | if (!rar_entries) |
3396 | break; | |
26ad9178 AD |
3397 | igb_rar_set_qsel(adapter, ha->addr, |
3398 | rar_entries--, | |
68d480c4 AD |
3399 | vfn); |
3400 | count++; | |
ff41f8dc AD |
3401 | } |
3402 | } | |
3403 | /* write the addresses in reverse order to avoid write combining */ | |
3404 | for (; rar_entries > 0 ; rar_entries--) { | |
3405 | wr32(E1000_RAH(rar_entries), 0); | |
3406 | wr32(E1000_RAL(rar_entries), 0); | |
3407 | } | |
3408 | wrfl(); | |
3409 | ||
68d480c4 AD |
3410 | return count; |
3411 | } | |
3412 | ||
3413 | /** | |
3414 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set | |
3415 | * @netdev: network interface device structure | |
3416 | * | |
3417 | * The set_rx_mode entry point is called whenever the unicast or multicast | |
3418 | * address lists or the network interface flags are updated. This routine is | |
3419 | * responsible for configuring the hardware for proper unicast, multicast, | |
3420 | * promiscuous mode, and all-multi behavior. | |
3421 | **/ | |
3422 | static void igb_set_rx_mode(struct net_device *netdev) | |
3423 | { | |
3424 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3425 | struct e1000_hw *hw = &adapter->hw; | |
3426 | unsigned int vfn = adapter->vfs_allocated_count; | |
3427 | u32 rctl, vmolr = 0; | |
3428 | int count; | |
3429 | ||
3430 | /* Check for Promiscuous and All Multicast modes */ | |
3431 | rctl = rd32(E1000_RCTL); | |
3432 | ||
3433 | /* clear the effected bits */ | |
3434 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); | |
3435 | ||
3436 | if (netdev->flags & IFF_PROMISC) { | |
3437 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | |
3438 | vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); | |
3439 | } else { | |
3440 | if (netdev->flags & IFF_ALLMULTI) { | |
3441 | rctl |= E1000_RCTL_MPE; | |
3442 | vmolr |= E1000_VMOLR_MPME; | |
3443 | } else { | |
3444 | /* | |
3445 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3446 | * then we should just turn on promiscuous mode so |
68d480c4 AD |
3447 | * that we can at least receive multicast traffic |
3448 | */ | |
3449 | count = igb_write_mc_addr_list(netdev); | |
3450 | if (count < 0) { | |
3451 | rctl |= E1000_RCTL_MPE; | |
3452 | vmolr |= E1000_VMOLR_MPME; | |
3453 | } else if (count) { | |
3454 | vmolr |= E1000_VMOLR_ROMPE; | |
3455 | } | |
3456 | } | |
3457 | /* | |
3458 | * Write addresses to available RAR registers, if there is not | |
3459 | * sufficient space to store all the addresses then enable | |
25985edc | 3460 | * unicast promiscuous mode |
68d480c4 AD |
3461 | */ |
3462 | count = igb_write_uc_addr_list(netdev); | |
3463 | if (count < 0) { | |
3464 | rctl |= E1000_RCTL_UPE; | |
3465 | vmolr |= E1000_VMOLR_ROPE; | |
3466 | } | |
3467 | rctl |= E1000_RCTL_VFE; | |
28fc06f5 | 3468 | } |
68d480c4 | 3469 | wr32(E1000_RCTL, rctl); |
28fc06f5 | 3470 | |
68d480c4 AD |
3471 | /* |
3472 | * In order to support SR-IOV and eventually VMDq it is necessary to set | |
3473 | * the VMOLR to enable the appropriate modes. Without this workaround | |
3474 | * we will have issues with VLAN tag stripping not being done for frames | |
3475 | * that are only arriving because we are the default pool | |
3476 | */ | |
3477 | if (hw->mac.type < e1000_82576) | |
28fc06f5 | 3478 | return; |
9d5c8243 | 3479 | |
68d480c4 AD |
3480 | vmolr |= rd32(E1000_VMOLR(vfn)) & |
3481 | ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); | |
3482 | wr32(E1000_VMOLR(vfn), vmolr); | |
28fc06f5 | 3483 | igb_restore_vf_multicasts(adapter); |
9d5c8243 AK |
3484 | } |
3485 | ||
13800469 GR |
3486 | static void igb_check_wvbr(struct igb_adapter *adapter) |
3487 | { | |
3488 | struct e1000_hw *hw = &adapter->hw; | |
3489 | u32 wvbr = 0; | |
3490 | ||
3491 | switch (hw->mac.type) { | |
3492 | case e1000_82576: | |
3493 | case e1000_i350: | |
3494 | if (!(wvbr = rd32(E1000_WVBR))) | |
3495 | return; | |
3496 | break; | |
3497 | default: | |
3498 | break; | |
3499 | } | |
3500 | ||
3501 | adapter->wvbr |= wvbr; | |
3502 | } | |
3503 | ||
3504 | #define IGB_STAGGERED_QUEUE_OFFSET 8 | |
3505 | ||
3506 | static void igb_spoof_check(struct igb_adapter *adapter) | |
3507 | { | |
3508 | int j; | |
3509 | ||
3510 | if (!adapter->wvbr) | |
3511 | return; | |
3512 | ||
3513 | for(j = 0; j < adapter->vfs_allocated_count; j++) { | |
3514 | if (adapter->wvbr & (1 << j) || | |
3515 | adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { | |
3516 | dev_warn(&adapter->pdev->dev, | |
3517 | "Spoof event(s) detected on VF %d\n", j); | |
3518 | adapter->wvbr &= | |
3519 | ~((1 << j) | | |
3520 | (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); | |
3521 | } | |
3522 | } | |
3523 | } | |
3524 | ||
9d5c8243 AK |
3525 | /* Need to wait a few seconds after link up to get diagnostic information from |
3526 | * the phy */ | |
3527 | static void igb_update_phy_info(unsigned long data) | |
3528 | { | |
3529 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 3530 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
3531 | } |
3532 | ||
4d6b725e AD |
3533 | /** |
3534 | * igb_has_link - check shared code for link and determine up/down | |
3535 | * @adapter: pointer to driver private info | |
3536 | **/ | |
3145535a | 3537 | bool igb_has_link(struct igb_adapter *adapter) |
4d6b725e AD |
3538 | { |
3539 | struct e1000_hw *hw = &adapter->hw; | |
3540 | bool link_active = false; | |
3541 | s32 ret_val = 0; | |
3542 | ||
3543 | /* get_link_status is set on LSC (link status) interrupt or | |
3544 | * rx sequence error interrupt. get_link_status will stay | |
3545 | * false until the e1000_check_for_link establishes link | |
3546 | * for copper adapters ONLY | |
3547 | */ | |
3548 | switch (hw->phy.media_type) { | |
3549 | case e1000_media_type_copper: | |
3550 | if (hw->mac.get_link_status) { | |
3551 | ret_val = hw->mac.ops.check_for_link(hw); | |
3552 | link_active = !hw->mac.get_link_status; | |
3553 | } else { | |
3554 | link_active = true; | |
3555 | } | |
3556 | break; | |
4d6b725e AD |
3557 | case e1000_media_type_internal_serdes: |
3558 | ret_val = hw->mac.ops.check_for_link(hw); | |
3559 | link_active = hw->mac.serdes_has_link; | |
3560 | break; | |
3561 | default: | |
3562 | case e1000_media_type_unknown: | |
3563 | break; | |
3564 | } | |
3565 | ||
3566 | return link_active; | |
3567 | } | |
3568 | ||
563988dc SA |
3569 | static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) |
3570 | { | |
3571 | bool ret = false; | |
3572 | u32 ctrl_ext, thstat; | |
3573 | ||
3574 | /* check for thermal sensor event on i350, copper only */ | |
3575 | if (hw->mac.type == e1000_i350) { | |
3576 | thstat = rd32(E1000_THSTAT); | |
3577 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
3578 | ||
3579 | if ((hw->phy.media_type == e1000_media_type_copper) && | |
3580 | !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) { | |
3581 | ret = !!(thstat & event); | |
3582 | } | |
3583 | } | |
3584 | ||
3585 | return ret; | |
3586 | } | |
3587 | ||
9d5c8243 AK |
3588 | /** |
3589 | * igb_watchdog - Timer Call-back | |
3590 | * @data: pointer to adapter cast into an unsigned long | |
3591 | **/ | |
3592 | static void igb_watchdog(unsigned long data) | |
3593 | { | |
3594 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
3595 | /* Do the rest outside of interrupt context */ | |
3596 | schedule_work(&adapter->watchdog_task); | |
3597 | } | |
3598 | ||
3599 | static void igb_watchdog_task(struct work_struct *work) | |
3600 | { | |
3601 | struct igb_adapter *adapter = container_of(work, | |
559e9c49 AD |
3602 | struct igb_adapter, |
3603 | watchdog_task); | |
9d5c8243 | 3604 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 3605 | struct net_device *netdev = adapter->netdev; |
563988dc | 3606 | u32 link; |
7a6ea550 | 3607 | int i; |
9d5c8243 | 3608 | |
4d6b725e | 3609 | link = igb_has_link(adapter); |
9d5c8243 AK |
3610 | if (link) { |
3611 | if (!netif_carrier_ok(netdev)) { | |
3612 | u32 ctrl; | |
330a6d6a AD |
3613 | hw->mac.ops.get_speed_and_duplex(hw, |
3614 | &adapter->link_speed, | |
3615 | &adapter->link_duplex); | |
9d5c8243 AK |
3616 | |
3617 | ctrl = rd32(E1000_CTRL); | |
527d47c1 AD |
3618 | /* Links status message must follow this format */ |
3619 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, " | |
9d5c8243 | 3620 | "Flow Control: %s\n", |
559e9c49 AD |
3621 | netdev->name, |
3622 | adapter->link_speed, | |
3623 | adapter->link_duplex == FULL_DUPLEX ? | |
9d5c8243 | 3624 | "Full Duplex" : "Half Duplex", |
559e9c49 AD |
3625 | ((ctrl & E1000_CTRL_TFCE) && |
3626 | (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" : | |
3627 | ((ctrl & E1000_CTRL_RFCE) ? "RX" : | |
3628 | ((ctrl & E1000_CTRL_TFCE) ? "TX" : "None"))); | |
9d5c8243 | 3629 | |
563988dc SA |
3630 | /* check for thermal sensor event */ |
3631 | if (igb_thermal_sensor_event(hw, E1000_THSTAT_LINK_THROTTLE)) { | |
3632 | printk(KERN_INFO "igb: %s The network adapter " | |
3633 | "link speed was downshifted " | |
3634 | "because it overheated.\n", | |
3635 | netdev->name); | |
7ef5ed1c | 3636 | } |
563988dc | 3637 | |
d07f3e37 | 3638 | /* adjust timeout factor according to speed/duplex */ |
9d5c8243 AK |
3639 | adapter->tx_timeout_factor = 1; |
3640 | switch (adapter->link_speed) { | |
3641 | case SPEED_10: | |
9d5c8243 AK |
3642 | adapter->tx_timeout_factor = 14; |
3643 | break; | |
3644 | case SPEED_100: | |
9d5c8243 AK |
3645 | /* maybe add some timeout factor ? */ |
3646 | break; | |
3647 | } | |
3648 | ||
3649 | netif_carrier_on(netdev); | |
9d5c8243 | 3650 | |
4ae196df | 3651 | igb_ping_all_vfs(adapter); |
17dc566c | 3652 | igb_check_vf_rate_limit(adapter); |
4ae196df | 3653 | |
4b1a9877 | 3654 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3655 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3656 | mod_timer(&adapter->phy_info_timer, | |
3657 | round_jiffies(jiffies + 2 * HZ)); | |
3658 | } | |
3659 | } else { | |
3660 | if (netif_carrier_ok(netdev)) { | |
3661 | adapter->link_speed = 0; | |
3662 | adapter->link_duplex = 0; | |
563988dc SA |
3663 | |
3664 | /* check for thermal sensor event */ | |
3665 | if (igb_thermal_sensor_event(hw, E1000_THSTAT_PWR_DOWN)) { | |
3666 | printk(KERN_ERR "igb: %s The network adapter " | |
3667 | "was stopped because it " | |
3668 | "overheated.\n", | |
7ef5ed1c | 3669 | netdev->name); |
7ef5ed1c | 3670 | } |
563988dc | 3671 | |
527d47c1 AD |
3672 | /* Links status message must follow this format */ |
3673 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
3674 | netdev->name); | |
9d5c8243 | 3675 | netif_carrier_off(netdev); |
4b1a9877 | 3676 | |
4ae196df AD |
3677 | igb_ping_all_vfs(adapter); |
3678 | ||
4b1a9877 | 3679 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3680 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3681 | mod_timer(&adapter->phy_info_timer, | |
3682 | round_jiffies(jiffies + 2 * HZ)); | |
3683 | } | |
3684 | } | |
3685 | ||
12dcd86b ED |
3686 | spin_lock(&adapter->stats64_lock); |
3687 | igb_update_stats(adapter, &adapter->stats64); | |
3688 | spin_unlock(&adapter->stats64_lock); | |
9d5c8243 | 3689 | |
dbabb065 | 3690 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 | 3691 | struct igb_ring *tx_ring = adapter->tx_ring[i]; |
dbabb065 | 3692 | if (!netif_carrier_ok(netdev)) { |
9d5c8243 AK |
3693 | /* We've lost link, so the controller stops DMA, |
3694 | * but we've got queued Tx work that's never going | |
3695 | * to get done, so reset controller to flush Tx. | |
3696 | * (Do the reset outside of interrupt context). */ | |
dbabb065 AD |
3697 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
3698 | adapter->tx_timeout_count++; | |
3699 | schedule_work(&adapter->reset_task); | |
3700 | /* return immediately since reset is imminent */ | |
3701 | return; | |
3702 | } | |
9d5c8243 | 3703 | } |
9d5c8243 | 3704 | |
dbabb065 AD |
3705 | /* Force detection of hung controller every watchdog period */ |
3706 | tx_ring->detect_tx_hung = true; | |
3707 | } | |
f7ba205e | 3708 | |
9d5c8243 | 3709 | /* Cause software interrupt to ensure rx ring is cleaned */ |
7a6ea550 | 3710 | if (adapter->msix_entries) { |
047e0030 AD |
3711 | u32 eics = 0; |
3712 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
3713 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
3714 | eics |= q_vector->eims_value; | |
3715 | } | |
7a6ea550 AD |
3716 | wr32(E1000_EICS, eics); |
3717 | } else { | |
3718 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
3719 | } | |
9d5c8243 | 3720 | |
13800469 GR |
3721 | igb_spoof_check(adapter); |
3722 | ||
9d5c8243 AK |
3723 | /* Reset the timer */ |
3724 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
3725 | mod_timer(&adapter->watchdog_timer, | |
3726 | round_jiffies(jiffies + 2 * HZ)); | |
3727 | } | |
3728 | ||
3729 | enum latency_range { | |
3730 | lowest_latency = 0, | |
3731 | low_latency = 1, | |
3732 | bulk_latency = 2, | |
3733 | latency_invalid = 255 | |
3734 | }; | |
3735 | ||
6eb5a7f1 AD |
3736 | /** |
3737 | * igb_update_ring_itr - update the dynamic ITR value based on packet size | |
3738 | * | |
3739 | * Stores a new ITR value based on strictly on packet size. This | |
3740 | * algorithm is less sophisticated than that used in igb_update_itr, | |
3741 | * due to the difficulty of synchronizing statistics across multiple | |
eef35c2d | 3742 | * receive rings. The divisors and thresholds used by this function |
6eb5a7f1 AD |
3743 | * were determined based on theoretical maximum wire speed and testing |
3744 | * data, in order to minimize response time while increasing bulk | |
3745 | * throughput. | |
3746 | * This functionality is controlled by the InterruptThrottleRate module | |
3747 | * parameter (see igb_param.c) | |
3748 | * NOTE: This function is called only when operating in a multiqueue | |
3749 | * receive environment. | |
047e0030 | 3750 | * @q_vector: pointer to q_vector |
6eb5a7f1 | 3751 | **/ |
047e0030 | 3752 | static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 3753 | { |
047e0030 | 3754 | int new_val = q_vector->itr_val; |
6eb5a7f1 | 3755 | int avg_wire_size = 0; |
047e0030 | 3756 | struct igb_adapter *adapter = q_vector->adapter; |
12dcd86b ED |
3757 | struct igb_ring *ring; |
3758 | unsigned int packets; | |
9d5c8243 | 3759 | |
6eb5a7f1 AD |
3760 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
3761 | * ints/sec - ITR timer value of 120 ticks. | |
3762 | */ | |
3763 | if (adapter->link_speed != SPEED_1000) { | |
047e0030 | 3764 | new_val = 976; |
6eb5a7f1 | 3765 | goto set_itr_val; |
9d5c8243 | 3766 | } |
047e0030 | 3767 | |
12dcd86b ED |
3768 | ring = q_vector->rx_ring; |
3769 | if (ring) { | |
3770 | packets = ACCESS_ONCE(ring->total_packets); | |
3771 | ||
3772 | if (packets) | |
3773 | avg_wire_size = ring->total_bytes / packets; | |
047e0030 AD |
3774 | } |
3775 | ||
12dcd86b ED |
3776 | ring = q_vector->tx_ring; |
3777 | if (ring) { | |
3778 | packets = ACCESS_ONCE(ring->total_packets); | |
3779 | ||
3780 | if (packets) | |
3781 | avg_wire_size = max_t(u32, avg_wire_size, | |
3782 | ring->total_bytes / packets); | |
047e0030 AD |
3783 | } |
3784 | ||
3785 | /* if avg_wire_size isn't set no work was done */ | |
3786 | if (!avg_wire_size) | |
3787 | goto clear_counts; | |
9d5c8243 | 3788 | |
6eb5a7f1 AD |
3789 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
3790 | avg_wire_size += 24; | |
3791 | ||
3792 | /* Don't starve jumbo frames */ | |
3793 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 3794 | |
6eb5a7f1 AD |
3795 | /* Give a little boost to mid-size frames */ |
3796 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
3797 | new_val = avg_wire_size / 3; | |
3798 | else | |
3799 | new_val = avg_wire_size / 2; | |
9d5c8243 | 3800 | |
abe1c363 NN |
3801 | /* when in itr mode 3 do not exceed 20K ints/sec */ |
3802 | if (adapter->rx_itr_setting == 3 && new_val < 196) | |
3803 | new_val = 196; | |
3804 | ||
6eb5a7f1 | 3805 | set_itr_val: |
047e0030 AD |
3806 | if (new_val != q_vector->itr_val) { |
3807 | q_vector->itr_val = new_val; | |
3808 | q_vector->set_itr = 1; | |
9d5c8243 | 3809 | } |
6eb5a7f1 | 3810 | clear_counts: |
047e0030 AD |
3811 | if (q_vector->rx_ring) { |
3812 | q_vector->rx_ring->total_bytes = 0; | |
3813 | q_vector->rx_ring->total_packets = 0; | |
3814 | } | |
3815 | if (q_vector->tx_ring) { | |
3816 | q_vector->tx_ring->total_bytes = 0; | |
3817 | q_vector->tx_ring->total_packets = 0; | |
3818 | } | |
9d5c8243 AK |
3819 | } |
3820 | ||
3821 | /** | |
3822 | * igb_update_itr - update the dynamic ITR value based on statistics | |
3823 | * Stores a new ITR value based on packets and byte | |
3824 | * counts during the last interrupt. The advantage of per interrupt | |
3825 | * computation is faster updates and more accurate ITR for the current | |
3826 | * traffic pattern. Constants in this function were computed | |
3827 | * based on theoretical maximum wire speed and thresholds were set based | |
3828 | * on testing data as well as attempting to minimize response time | |
3829 | * while increasing bulk throughput. | |
3830 | * this functionality is controlled by the InterruptThrottleRate module | |
3831 | * parameter (see igb_param.c) | |
3832 | * NOTE: These calculations are only valid when operating in a single- | |
3833 | * queue environment. | |
3834 | * @adapter: pointer to adapter | |
047e0030 | 3835 | * @itr_setting: current q_vector->itr_val |
9d5c8243 AK |
3836 | * @packets: the number of packets during this measurement interval |
3837 | * @bytes: the number of bytes during this measurement interval | |
3838 | **/ | |
3839 | static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting, | |
3840 | int packets, int bytes) | |
3841 | { | |
3842 | unsigned int retval = itr_setting; | |
3843 | ||
3844 | if (packets == 0) | |
3845 | goto update_itr_done; | |
3846 | ||
3847 | switch (itr_setting) { | |
3848 | case lowest_latency: | |
3849 | /* handle TSO and jumbo frames */ | |
3850 | if (bytes/packets > 8000) | |
3851 | retval = bulk_latency; | |
3852 | else if ((packets < 5) && (bytes > 512)) | |
3853 | retval = low_latency; | |
3854 | break; | |
3855 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
3856 | if (bytes > 10000) { | |
3857 | /* this if handles the TSO accounting */ | |
3858 | if (bytes/packets > 8000) { | |
3859 | retval = bulk_latency; | |
3860 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { | |
3861 | retval = bulk_latency; | |
3862 | } else if ((packets > 35)) { | |
3863 | retval = lowest_latency; | |
3864 | } | |
3865 | } else if (bytes/packets > 2000) { | |
3866 | retval = bulk_latency; | |
3867 | } else if (packets <= 2 && bytes < 512) { | |
3868 | retval = lowest_latency; | |
3869 | } | |
3870 | break; | |
3871 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
3872 | if (bytes > 25000) { | |
3873 | if (packets > 35) | |
3874 | retval = low_latency; | |
1e5c3d21 | 3875 | } else if (bytes < 1500) { |
9d5c8243 AK |
3876 | retval = low_latency; |
3877 | } | |
3878 | break; | |
3879 | } | |
3880 | ||
3881 | update_itr_done: | |
3882 | return retval; | |
3883 | } | |
3884 | ||
6eb5a7f1 | 3885 | static void igb_set_itr(struct igb_adapter *adapter) |
9d5c8243 | 3886 | { |
047e0030 | 3887 | struct igb_q_vector *q_vector = adapter->q_vector[0]; |
9d5c8243 | 3888 | u16 current_itr; |
047e0030 | 3889 | u32 new_itr = q_vector->itr_val; |
9d5c8243 AK |
3890 | |
3891 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
3892 | if (adapter->link_speed != SPEED_1000) { | |
3893 | current_itr = 0; | |
3894 | new_itr = 4000; | |
3895 | goto set_itr_now; | |
3896 | } | |
3897 | ||
3898 | adapter->rx_itr = igb_update_itr(adapter, | |
3899 | adapter->rx_itr, | |
3025a446 AD |
3900 | q_vector->rx_ring->total_packets, |
3901 | q_vector->rx_ring->total_bytes); | |
9d5c8243 | 3902 | |
047e0030 AD |
3903 | adapter->tx_itr = igb_update_itr(adapter, |
3904 | adapter->tx_itr, | |
3025a446 AD |
3905 | q_vector->tx_ring->total_packets, |
3906 | q_vector->tx_ring->total_bytes); | |
047e0030 | 3907 | current_itr = max(adapter->rx_itr, adapter->tx_itr); |
9d5c8243 | 3908 | |
6eb5a7f1 | 3909 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
4fc82adf | 3910 | if (adapter->rx_itr_setting == 3 && current_itr == lowest_latency) |
6eb5a7f1 AD |
3911 | current_itr = low_latency; |
3912 | ||
9d5c8243 AK |
3913 | switch (current_itr) { |
3914 | /* counts and packets in update_itr are dependent on these numbers */ | |
3915 | case lowest_latency: | |
78b1f607 | 3916 | new_itr = 56; /* aka 70,000 ints/sec */ |
9d5c8243 AK |
3917 | break; |
3918 | case low_latency: | |
78b1f607 | 3919 | new_itr = 196; /* aka 20,000 ints/sec */ |
9d5c8243 AK |
3920 | break; |
3921 | case bulk_latency: | |
78b1f607 | 3922 | new_itr = 980; /* aka 4,000 ints/sec */ |
9d5c8243 AK |
3923 | break; |
3924 | default: | |
3925 | break; | |
3926 | } | |
3927 | ||
3928 | set_itr_now: | |
3025a446 AD |
3929 | q_vector->rx_ring->total_bytes = 0; |
3930 | q_vector->rx_ring->total_packets = 0; | |
3931 | q_vector->tx_ring->total_bytes = 0; | |
3932 | q_vector->tx_ring->total_packets = 0; | |
6eb5a7f1 | 3933 | |
047e0030 | 3934 | if (new_itr != q_vector->itr_val) { |
9d5c8243 AK |
3935 | /* this attempts to bias the interrupt rate towards Bulk |
3936 | * by adding intermediate steps when interrupt rate is | |
3937 | * increasing */ | |
047e0030 AD |
3938 | new_itr = new_itr > q_vector->itr_val ? |
3939 | max((new_itr * q_vector->itr_val) / | |
3940 | (new_itr + (q_vector->itr_val >> 2)), | |
3941 | new_itr) : | |
9d5c8243 AK |
3942 | new_itr; |
3943 | /* Don't write the value here; it resets the adapter's | |
3944 | * internal timer, and causes us to delay far longer than | |
3945 | * we should between interrupts. Instead, we write the ITR | |
3946 | * value at the beginning of the next interrupt so the timing | |
3947 | * ends up being correct. | |
3948 | */ | |
047e0030 AD |
3949 | q_vector->itr_val = new_itr; |
3950 | q_vector->set_itr = 1; | |
9d5c8243 | 3951 | } |
9d5c8243 AK |
3952 | } |
3953 | ||
7d13a7d0 AD |
3954 | void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, |
3955 | u32 type_tucmd, u32 mss_l4len_idx) | |
3956 | { | |
3957 | struct e1000_adv_tx_context_desc *context_desc; | |
3958 | u16 i = tx_ring->next_to_use; | |
3959 | ||
3960 | context_desc = IGB_TX_CTXTDESC(tx_ring, i); | |
3961 | ||
3962 | i++; | |
3963 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
3964 | ||
3965 | /* set bits to identify this as an advanced context descriptor */ | |
3966 | type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; | |
3967 | ||
3968 | /* For 82575, context index must be unique per ring. */ | |
3969 | if (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX) | |
3970 | mss_l4len_idx |= tx_ring->reg_idx << 4; | |
3971 | ||
3972 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
3973 | context_desc->seqnum_seed = 0; | |
3974 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
3975 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
3976 | } | |
3977 | ||
7af40ad9 AD |
3978 | static int igb_tso(struct igb_ring *tx_ring, |
3979 | struct igb_tx_buffer *first, | |
3980 | u8 *hdr_len) | |
9d5c8243 | 3981 | { |
7af40ad9 | 3982 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
3983 | u32 vlan_macip_lens, type_tucmd; |
3984 | u32 mss_l4len_idx, l4len; | |
3985 | ||
3986 | if (!skb_is_gso(skb)) | |
3987 | return 0; | |
9d5c8243 AK |
3988 | |
3989 | if (skb_header_cloned(skb)) { | |
7af40ad9 | 3990 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
9d5c8243 AK |
3991 | if (err) |
3992 | return err; | |
3993 | } | |
3994 | ||
7d13a7d0 AD |
3995 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
3996 | type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; | |
9d5c8243 | 3997 | |
7af40ad9 | 3998 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
9d5c8243 AK |
3999 | struct iphdr *iph = ip_hdr(skb); |
4000 | iph->tot_len = 0; | |
4001 | iph->check = 0; | |
4002 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
4003 | iph->daddr, 0, | |
4004 | IPPROTO_TCP, | |
4005 | 0); | |
7d13a7d0 | 4006 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; |
7af40ad9 AD |
4007 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4008 | IGB_TX_FLAGS_CSUM | | |
4009 | IGB_TX_FLAGS_IPV4; | |
8e1e8a47 | 4010 | } else if (skb_is_gso_v6(skb)) { |
9d5c8243 AK |
4011 | ipv6_hdr(skb)->payload_len = 0; |
4012 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
4013 | &ipv6_hdr(skb)->daddr, | |
4014 | 0, IPPROTO_TCP, 0); | |
7af40ad9 AD |
4015 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4016 | IGB_TX_FLAGS_CSUM; | |
9d5c8243 AK |
4017 | } |
4018 | ||
7af40ad9 | 4019 | /* compute header lengths */ |
7d13a7d0 AD |
4020 | l4len = tcp_hdrlen(skb); |
4021 | *hdr_len = skb_transport_offset(skb) + l4len; | |
9d5c8243 | 4022 | |
7af40ad9 AD |
4023 | /* update gso size and bytecount with header size */ |
4024 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
4025 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
4026 | ||
9d5c8243 | 4027 | /* MSS L4LEN IDX */ |
7d13a7d0 AD |
4028 | mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; |
4029 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; | |
9d5c8243 | 4030 | |
7d13a7d0 AD |
4031 | /* VLAN MACLEN IPLEN */ |
4032 | vlan_macip_lens = skb_network_header_len(skb); | |
4033 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; | |
7af40ad9 | 4034 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4035 | |
7d13a7d0 | 4036 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 | 4037 | |
7d13a7d0 | 4038 | return 1; |
9d5c8243 AK |
4039 | } |
4040 | ||
7af40ad9 | 4041 | static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) |
9d5c8243 | 4042 | { |
7af40ad9 | 4043 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
4044 | u32 vlan_macip_lens = 0; |
4045 | u32 mss_l4len_idx = 0; | |
4046 | u32 type_tucmd = 0; | |
9d5c8243 | 4047 | |
7d13a7d0 | 4048 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
7af40ad9 AD |
4049 | if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) |
4050 | return; | |
7d13a7d0 AD |
4051 | } else { |
4052 | u8 l4_hdr = 0; | |
7af40ad9 | 4053 | switch (first->protocol) { |
7d13a7d0 AD |
4054 | case __constant_htons(ETH_P_IP): |
4055 | vlan_macip_lens |= skb_network_header_len(skb); | |
4056 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; | |
4057 | l4_hdr = ip_hdr(skb)->protocol; | |
4058 | break; | |
4059 | case __constant_htons(ETH_P_IPV6): | |
4060 | vlan_macip_lens |= skb_network_header_len(skb); | |
4061 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
4062 | break; | |
4063 | default: | |
4064 | if (unlikely(net_ratelimit())) { | |
4065 | dev_warn(tx_ring->dev, | |
4066 | "partial checksum but proto=%x!\n", | |
7af40ad9 | 4067 | first->protocol); |
fa4a7ef3 | 4068 | } |
7d13a7d0 AD |
4069 | break; |
4070 | } | |
fa4a7ef3 | 4071 | |
7d13a7d0 AD |
4072 | switch (l4_hdr) { |
4073 | case IPPROTO_TCP: | |
4074 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
4075 | mss_l4len_idx = tcp_hdrlen(skb) << | |
4076 | E1000_ADVTXD_L4LEN_SHIFT; | |
4077 | break; | |
4078 | case IPPROTO_SCTP: | |
4079 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
4080 | mss_l4len_idx = sizeof(struct sctphdr) << | |
4081 | E1000_ADVTXD_L4LEN_SHIFT; | |
4082 | break; | |
4083 | case IPPROTO_UDP: | |
4084 | mss_l4len_idx = sizeof(struct udphdr) << | |
4085 | E1000_ADVTXD_L4LEN_SHIFT; | |
4086 | break; | |
4087 | default: | |
4088 | if (unlikely(net_ratelimit())) { | |
4089 | dev_warn(tx_ring->dev, | |
4090 | "partial checksum but l4 proto=%x!\n", | |
4091 | l4_hdr); | |
44b0cda3 | 4092 | } |
7d13a7d0 | 4093 | break; |
9d5c8243 | 4094 | } |
7af40ad9 AD |
4095 | |
4096 | /* update TX checksum flag */ | |
4097 | first->tx_flags |= IGB_TX_FLAGS_CSUM; | |
7d13a7d0 | 4098 | } |
9d5c8243 | 4099 | |
7d13a7d0 | 4100 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; |
7af40ad9 | 4101 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4102 | |
7d13a7d0 | 4103 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 AK |
4104 | } |
4105 | ||
e032afc8 AD |
4106 | static __le32 igb_tx_cmd_type(u32 tx_flags) |
4107 | { | |
4108 | /* set type for advanced descriptor with frame checksum insertion */ | |
4109 | __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA | | |
4110 | E1000_ADVTXD_DCMD_IFCS | | |
4111 | E1000_ADVTXD_DCMD_DEXT); | |
4112 | ||
4113 | /* set HW vlan bit if vlan is present */ | |
4114 | if (tx_flags & IGB_TX_FLAGS_VLAN) | |
4115 | cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE); | |
4116 | ||
4117 | /* set timestamp bit if present */ | |
4118 | if (tx_flags & IGB_TX_FLAGS_TSTAMP) | |
4119 | cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP); | |
4120 | ||
4121 | /* set segmentation bits for TSO */ | |
4122 | if (tx_flags & IGB_TX_FLAGS_TSO) | |
4123 | cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE); | |
4124 | ||
4125 | return cmd_type; | |
4126 | } | |
4127 | ||
7af40ad9 AD |
4128 | static void igb_tx_olinfo_status(struct igb_ring *tx_ring, |
4129 | union e1000_adv_tx_desc *tx_desc, | |
4130 | u32 tx_flags, unsigned int paylen) | |
e032afc8 AD |
4131 | { |
4132 | u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; | |
4133 | ||
4134 | /* 82575 requires a unique index per ring if any offload is enabled */ | |
4135 | if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) && | |
4136 | (tx_ring->flags & IGB_RING_FLAG_TX_CTX_IDX)) | |
4137 | olinfo_status |= tx_ring->reg_idx << 4; | |
4138 | ||
4139 | /* insert L4 checksum */ | |
4140 | if (tx_flags & IGB_TX_FLAGS_CSUM) { | |
4141 | olinfo_status |= E1000_TXD_POPTS_TXSM << 8; | |
4142 | ||
4143 | /* insert IPv4 checksum */ | |
4144 | if (tx_flags & IGB_TX_FLAGS_IPV4) | |
4145 | olinfo_status |= E1000_TXD_POPTS_IXSM << 8; | |
4146 | } | |
4147 | ||
7af40ad9 | 4148 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
e032afc8 AD |
4149 | } |
4150 | ||
ebe42d16 AD |
4151 | /* |
4152 | * The largest size we can write to the descriptor is 65535. In order to | |
4153 | * maintain a power of two alignment we have to limit ourselves to 32K. | |
4154 | */ | |
4155 | #define IGB_MAX_TXD_PWR 15 | |
7af40ad9 | 4156 | #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) |
9d5c8243 | 4157 | |
7af40ad9 AD |
4158 | static void igb_tx_map(struct igb_ring *tx_ring, |
4159 | struct igb_tx_buffer *first, | |
ebe42d16 | 4160 | const u8 hdr_len) |
9d5c8243 | 4161 | { |
7af40ad9 | 4162 | struct sk_buff *skb = first->skb; |
ebe42d16 AD |
4163 | struct igb_tx_buffer *tx_buffer_info; |
4164 | union e1000_adv_tx_desc *tx_desc; | |
4165 | dma_addr_t dma; | |
4166 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
4167 | unsigned int data_len = skb->data_len; | |
4168 | unsigned int size = skb_headlen(skb); | |
4169 | unsigned int paylen = skb->len - hdr_len; | |
4170 | __le32 cmd_type; | |
7af40ad9 | 4171 | u32 tx_flags = first->tx_flags; |
ebe42d16 | 4172 | u16 i = tx_ring->next_to_use; |
ebe42d16 AD |
4173 | |
4174 | tx_desc = IGB_TX_DESC(tx_ring, i); | |
4175 | ||
7af40ad9 | 4176 | igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen); |
ebe42d16 AD |
4177 | cmd_type = igb_tx_cmd_type(tx_flags); |
4178 | ||
4179 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
4180 | if (dma_mapping_error(tx_ring->dev, dma)) | |
6366ad33 | 4181 | goto dma_error; |
9d5c8243 | 4182 | |
ebe42d16 AD |
4183 | /* record length, and DMA address */ |
4184 | first->length = size; | |
4185 | first->dma = dma; | |
ebe42d16 AD |
4186 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
4187 | ||
4188 | for (;;) { | |
4189 | while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { | |
4190 | tx_desc->read.cmd_type_len = | |
4191 | cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD); | |
4192 | ||
4193 | i++; | |
4194 | tx_desc++; | |
4195 | if (i == tx_ring->count) { | |
4196 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
4197 | i = 0; | |
4198 | } | |
4199 | ||
4200 | dma += IGB_MAX_DATA_PER_TXD; | |
4201 | size -= IGB_MAX_DATA_PER_TXD; | |
4202 | ||
4203 | tx_desc->read.olinfo_status = 0; | |
4204 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
4205 | } | |
4206 | ||
4207 | if (likely(!data_len)) | |
4208 | break; | |
2bbfebe2 | 4209 | |
ebe42d16 | 4210 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9d5c8243 | 4211 | |
65689fef | 4212 | i++; |
ebe42d16 AD |
4213 | tx_desc++; |
4214 | if (i == tx_ring->count) { | |
4215 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
65689fef | 4216 | i = 0; |
ebe42d16 | 4217 | } |
65689fef | 4218 | |
ebe42d16 AD |
4219 | size = frag->size; |
4220 | data_len -= size; | |
4221 | ||
4222 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, | |
4223 | size, DMA_TO_DEVICE); | |
4224 | if (dma_mapping_error(tx_ring->dev, dma)) | |
6366ad33 AD |
4225 | goto dma_error; |
4226 | ||
ebe42d16 AD |
4227 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
4228 | tx_buffer_info->length = size; | |
4229 | tx_buffer_info->dma = dma; | |
4230 | ||
4231 | tx_desc->read.olinfo_status = 0; | |
4232 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
4233 | ||
4234 | frag++; | |
9d5c8243 AK |
4235 | } |
4236 | ||
ebe42d16 AD |
4237 | /* write last descriptor with RS and EOP bits */ |
4238 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD); | |
4239 | tx_desc->read.cmd_type_len = cmd_type; | |
8542db05 AD |
4240 | |
4241 | /* set the timestamp */ | |
4242 | first->time_stamp = jiffies; | |
4243 | ||
ebe42d16 AD |
4244 | /* |
4245 | * Force memory writes to complete before letting h/w know there | |
4246 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
4247 | * memory model archs, such as IA-64). | |
4248 | * | |
4249 | * We also need this memory barrier to make certain all of the | |
4250 | * status bits have been updated before next_to_watch is written. | |
4251 | */ | |
4252 | wmb(); | |
4253 | ||
8542db05 | 4254 | /* set next_to_watch value indicating a packet is present */ |
ebe42d16 | 4255 | first->next_to_watch = tx_desc; |
9d5c8243 | 4256 | |
ebe42d16 AD |
4257 | i++; |
4258 | if (i == tx_ring->count) | |
4259 | i = 0; | |
6366ad33 | 4260 | |
ebe42d16 | 4261 | tx_ring->next_to_use = i; |
6366ad33 | 4262 | |
ebe42d16 | 4263 | writel(i, tx_ring->tail); |
6366ad33 | 4264 | |
ebe42d16 AD |
4265 | /* we need this if more than one processor can write to our tail |
4266 | * at a time, it syncronizes IO on IA64/Altix systems */ | |
4267 | mmiowb(); | |
4268 | ||
4269 | return; | |
4270 | ||
4271 | dma_error: | |
4272 | dev_err(tx_ring->dev, "TX DMA map failed\n"); | |
4273 | ||
4274 | /* clear dma mappings for failed tx_buffer_info map */ | |
4275 | for (;;) { | |
4276 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
4277 | igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); | |
4278 | if (tx_buffer_info == first) | |
4279 | break; | |
a77ff709 NN |
4280 | if (i == 0) |
4281 | i = tx_ring->count; | |
6366ad33 | 4282 | i--; |
6366ad33 AD |
4283 | } |
4284 | ||
9d5c8243 | 4285 | tx_ring->next_to_use = i; |
9d5c8243 AK |
4286 | } |
4287 | ||
e694e964 | 4288 | static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, int size) |
9d5c8243 | 4289 | { |
e694e964 AD |
4290 | struct net_device *netdev = tx_ring->netdev; |
4291 | ||
661086df | 4292 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 4293 | |
9d5c8243 AK |
4294 | /* Herbert's original patch had: |
4295 | * smp_mb__after_netif_stop_queue(); | |
4296 | * but since that doesn't exist yet, just open code it. */ | |
4297 | smp_mb(); | |
4298 | ||
4299 | /* We need to check again in a case another CPU has just | |
4300 | * made room available. */ | |
c493ea45 | 4301 | if (igb_desc_unused(tx_ring) < size) |
9d5c8243 AK |
4302 | return -EBUSY; |
4303 | ||
4304 | /* A reprieve! */ | |
661086df | 4305 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
12dcd86b ED |
4306 | |
4307 | u64_stats_update_begin(&tx_ring->tx_syncp2); | |
4308 | tx_ring->tx_stats.restart_queue2++; | |
4309 | u64_stats_update_end(&tx_ring->tx_syncp2); | |
4310 | ||
9d5c8243 AK |
4311 | return 0; |
4312 | } | |
4313 | ||
717ba089 | 4314 | static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, int size) |
9d5c8243 | 4315 | { |
c493ea45 | 4316 | if (igb_desc_unused(tx_ring) >= size) |
9d5c8243 | 4317 | return 0; |
e694e964 | 4318 | return __igb_maybe_stop_tx(tx_ring, size); |
9d5c8243 AK |
4319 | } |
4320 | ||
cd392f5c AD |
4321 | netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, |
4322 | struct igb_ring *tx_ring) | |
9d5c8243 | 4323 | { |
8542db05 | 4324 | struct igb_tx_buffer *first; |
ebe42d16 | 4325 | int tso; |
91d4ee33 | 4326 | u32 tx_flags = 0; |
31f6adbb | 4327 | __be16 protocol = vlan_get_protocol(skb); |
91d4ee33 | 4328 | u8 hdr_len = 0; |
9d5c8243 | 4329 | |
9d5c8243 AK |
4330 | /* need: 1 descriptor per page, |
4331 | * + 2 desc gap to keep tail from touching head, | |
4332 | * + 1 desc for skb->data, | |
4333 | * + 1 desc for context descriptor, | |
4334 | * otherwise try next time */ | |
e694e964 | 4335 | if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { |
9d5c8243 | 4336 | /* this is a hard error */ |
9d5c8243 AK |
4337 | return NETDEV_TX_BUSY; |
4338 | } | |
33af6bcc | 4339 | |
7af40ad9 AD |
4340 | /* record the location of the first descriptor for this packet */ |
4341 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
4342 | first->skb = skb; | |
4343 | first->bytecount = skb->len; | |
4344 | first->gso_segs = 1; | |
4345 | ||
2244d07b OH |
4346 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { |
4347 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
33af6bcc | 4348 | tx_flags |= IGB_TX_FLAGS_TSTAMP; |
33af6bcc | 4349 | } |
9d5c8243 | 4350 | |
eab6d18d | 4351 | if (vlan_tx_tag_present(skb)) { |
9d5c8243 AK |
4352 | tx_flags |= IGB_TX_FLAGS_VLAN; |
4353 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
4354 | } | |
4355 | ||
7af40ad9 AD |
4356 | /* record initial flags and protocol */ |
4357 | first->tx_flags = tx_flags; | |
4358 | first->protocol = protocol; | |
cdfd01fc | 4359 | |
7af40ad9 AD |
4360 | tso = igb_tso(tx_ring, first, &hdr_len); |
4361 | if (tso < 0) | |
7d13a7d0 | 4362 | goto out_drop; |
7af40ad9 AD |
4363 | else if (!tso) |
4364 | igb_tx_csum(tx_ring, first); | |
9d5c8243 | 4365 | |
7af40ad9 | 4366 | igb_tx_map(tx_ring, first, hdr_len); |
85ad76b2 AD |
4367 | |
4368 | /* Make sure there is space in the ring for the next send. */ | |
e694e964 | 4369 | igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); |
85ad76b2 | 4370 | |
9d5c8243 | 4371 | return NETDEV_TX_OK; |
7d13a7d0 AD |
4372 | |
4373 | out_drop: | |
7af40ad9 AD |
4374 | igb_unmap_and_free_tx_resource(tx_ring, first); |
4375 | ||
7d13a7d0 | 4376 | return NETDEV_TX_OK; |
9d5c8243 AK |
4377 | } |
4378 | ||
1cc3bd87 AD |
4379 | static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, |
4380 | struct sk_buff *skb) | |
4381 | { | |
4382 | unsigned int r_idx = skb->queue_mapping; | |
4383 | ||
4384 | if (r_idx >= adapter->num_tx_queues) | |
4385 | r_idx = r_idx % adapter->num_tx_queues; | |
4386 | ||
4387 | return adapter->tx_ring[r_idx]; | |
4388 | } | |
4389 | ||
cd392f5c AD |
4390 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, |
4391 | struct net_device *netdev) | |
9d5c8243 AK |
4392 | { |
4393 | struct igb_adapter *adapter = netdev_priv(netdev); | |
b1a436c3 AD |
4394 | |
4395 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
4396 | dev_kfree_skb_any(skb); | |
4397 | return NETDEV_TX_OK; | |
4398 | } | |
4399 | ||
4400 | if (skb->len <= 0) { | |
4401 | dev_kfree_skb_any(skb); | |
4402 | return NETDEV_TX_OK; | |
4403 | } | |
4404 | ||
1cc3bd87 AD |
4405 | /* |
4406 | * The minimum packet size with TCTL.PSP set is 17 so pad the skb | |
4407 | * in order to meet this minimum size requirement. | |
4408 | */ | |
4409 | if (skb->len < 17) { | |
4410 | if (skb_padto(skb, 17)) | |
4411 | return NETDEV_TX_OK; | |
4412 | skb->len = 17; | |
4413 | } | |
9d5c8243 | 4414 | |
1cc3bd87 | 4415 | return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); |
9d5c8243 AK |
4416 | } |
4417 | ||
4418 | /** | |
4419 | * igb_tx_timeout - Respond to a Tx Hang | |
4420 | * @netdev: network interface device structure | |
4421 | **/ | |
4422 | static void igb_tx_timeout(struct net_device *netdev) | |
4423 | { | |
4424 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4425 | struct e1000_hw *hw = &adapter->hw; | |
4426 | ||
4427 | /* Do the reset outside of interrupt context */ | |
4428 | adapter->tx_timeout_count++; | |
f7ba205e | 4429 | |
55cac248 AD |
4430 | if (hw->mac.type == e1000_82580) |
4431 | hw->dev_spec._82575.global_device_reset = true; | |
4432 | ||
9d5c8243 | 4433 | schedule_work(&adapter->reset_task); |
265de409 AD |
4434 | wr32(E1000_EICS, |
4435 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
4436 | } |
4437 | ||
4438 | static void igb_reset_task(struct work_struct *work) | |
4439 | { | |
4440 | struct igb_adapter *adapter; | |
4441 | adapter = container_of(work, struct igb_adapter, reset_task); | |
4442 | ||
c97ec42a TI |
4443 | igb_dump(adapter); |
4444 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
9d5c8243 AK |
4445 | igb_reinit_locked(adapter); |
4446 | } | |
4447 | ||
4448 | /** | |
12dcd86b | 4449 | * igb_get_stats64 - Get System Network Statistics |
9d5c8243 | 4450 | * @netdev: network interface device structure |
12dcd86b | 4451 | * @stats: rtnl_link_stats64 pointer |
9d5c8243 | 4452 | * |
9d5c8243 | 4453 | **/ |
12dcd86b ED |
4454 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, |
4455 | struct rtnl_link_stats64 *stats) | |
9d5c8243 | 4456 | { |
12dcd86b ED |
4457 | struct igb_adapter *adapter = netdev_priv(netdev); |
4458 | ||
4459 | spin_lock(&adapter->stats64_lock); | |
4460 | igb_update_stats(adapter, &adapter->stats64); | |
4461 | memcpy(stats, &adapter->stats64, sizeof(*stats)); | |
4462 | spin_unlock(&adapter->stats64_lock); | |
4463 | ||
4464 | return stats; | |
9d5c8243 AK |
4465 | } |
4466 | ||
4467 | /** | |
4468 | * igb_change_mtu - Change the Maximum Transfer Unit | |
4469 | * @netdev: network interface device structure | |
4470 | * @new_mtu: new value for maximum frame size | |
4471 | * | |
4472 | * Returns 0 on success, negative on failure | |
4473 | **/ | |
4474 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
4475 | { | |
4476 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4477 | struct pci_dev *pdev = adapter->pdev; |
153285f9 | 4478 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
9d5c8243 | 4479 | |
c809d227 | 4480 | if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
090b1795 | 4481 | dev_err(&pdev->dev, "Invalid MTU setting\n"); |
9d5c8243 AK |
4482 | return -EINVAL; |
4483 | } | |
4484 | ||
153285f9 | 4485 | #define MAX_STD_JUMBO_FRAME_SIZE 9238 |
9d5c8243 | 4486 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
090b1795 | 4487 | dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
9d5c8243 AK |
4488 | return -EINVAL; |
4489 | } | |
4490 | ||
4491 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
4492 | msleep(1); | |
73cd78f1 | 4493 | |
9d5c8243 AK |
4494 | /* igb_down has a dependency on max_frame_size */ |
4495 | adapter->max_frame_size = max_frame; | |
559e9c49 | 4496 | |
4c844851 AD |
4497 | if (netif_running(netdev)) |
4498 | igb_down(adapter); | |
9d5c8243 | 4499 | |
090b1795 | 4500 | dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
9d5c8243 AK |
4501 | netdev->mtu, new_mtu); |
4502 | netdev->mtu = new_mtu; | |
4503 | ||
4504 | if (netif_running(netdev)) | |
4505 | igb_up(adapter); | |
4506 | else | |
4507 | igb_reset(adapter); | |
4508 | ||
4509 | clear_bit(__IGB_RESETTING, &adapter->state); | |
4510 | ||
4511 | return 0; | |
4512 | } | |
4513 | ||
4514 | /** | |
4515 | * igb_update_stats - Update the board statistics counters | |
4516 | * @adapter: board private structure | |
4517 | **/ | |
4518 | ||
12dcd86b ED |
4519 | void igb_update_stats(struct igb_adapter *adapter, |
4520 | struct rtnl_link_stats64 *net_stats) | |
9d5c8243 AK |
4521 | { |
4522 | struct e1000_hw *hw = &adapter->hw; | |
4523 | struct pci_dev *pdev = adapter->pdev; | |
fa3d9a6d | 4524 | u32 reg, mpc; |
9d5c8243 | 4525 | u16 phy_tmp; |
3f9c0164 AD |
4526 | int i; |
4527 | u64 bytes, packets; | |
12dcd86b ED |
4528 | unsigned int start; |
4529 | u64 _bytes, _packets; | |
9d5c8243 AK |
4530 | |
4531 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
4532 | ||
4533 | /* | |
4534 | * Prevent stats update while adapter is being reset, or if the pci | |
4535 | * connection is down. | |
4536 | */ | |
4537 | if (adapter->link_speed == 0) | |
4538 | return; | |
4539 | if (pci_channel_offline(pdev)) | |
4540 | return; | |
4541 | ||
3f9c0164 AD |
4542 | bytes = 0; |
4543 | packets = 0; | |
4544 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
4545 | u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF; | |
3025a446 | 4546 | struct igb_ring *ring = adapter->rx_ring[i]; |
12dcd86b | 4547 | |
3025a446 | 4548 | ring->rx_stats.drops += rqdpc_tmp; |
128e45eb | 4549 | net_stats->rx_fifo_errors += rqdpc_tmp; |
12dcd86b ED |
4550 | |
4551 | do { | |
4552 | start = u64_stats_fetch_begin_bh(&ring->rx_syncp); | |
4553 | _bytes = ring->rx_stats.bytes; | |
4554 | _packets = ring->rx_stats.packets; | |
4555 | } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); | |
4556 | bytes += _bytes; | |
4557 | packets += _packets; | |
3f9c0164 AD |
4558 | } |
4559 | ||
128e45eb AD |
4560 | net_stats->rx_bytes = bytes; |
4561 | net_stats->rx_packets = packets; | |
3f9c0164 AD |
4562 | |
4563 | bytes = 0; | |
4564 | packets = 0; | |
4565 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 4566 | struct igb_ring *ring = adapter->tx_ring[i]; |
12dcd86b ED |
4567 | do { |
4568 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp); | |
4569 | _bytes = ring->tx_stats.bytes; | |
4570 | _packets = ring->tx_stats.packets; | |
4571 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); | |
4572 | bytes += _bytes; | |
4573 | packets += _packets; | |
3f9c0164 | 4574 | } |
128e45eb AD |
4575 | net_stats->tx_bytes = bytes; |
4576 | net_stats->tx_packets = packets; | |
3f9c0164 AD |
4577 | |
4578 | /* read stats registers */ | |
9d5c8243 AK |
4579 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
4580 | adapter->stats.gprc += rd32(E1000_GPRC); | |
4581 | adapter->stats.gorc += rd32(E1000_GORCL); | |
4582 | rd32(E1000_GORCH); /* clear GORCL */ | |
4583 | adapter->stats.bprc += rd32(E1000_BPRC); | |
4584 | adapter->stats.mprc += rd32(E1000_MPRC); | |
4585 | adapter->stats.roc += rd32(E1000_ROC); | |
4586 | ||
4587 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
4588 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
4589 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
4590 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
4591 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
4592 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
4593 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
4594 | adapter->stats.sec += rd32(E1000_SEC); | |
4595 | ||
fa3d9a6d MW |
4596 | mpc = rd32(E1000_MPC); |
4597 | adapter->stats.mpc += mpc; | |
4598 | net_stats->rx_fifo_errors += mpc; | |
9d5c8243 AK |
4599 | adapter->stats.scc += rd32(E1000_SCC); |
4600 | adapter->stats.ecol += rd32(E1000_ECOL); | |
4601 | adapter->stats.mcc += rd32(E1000_MCC); | |
4602 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
4603 | adapter->stats.dc += rd32(E1000_DC); | |
4604 | adapter->stats.rlec += rd32(E1000_RLEC); | |
4605 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
4606 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
4607 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
4608 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
4609 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
4610 | adapter->stats.gptc += rd32(E1000_GPTC); | |
4611 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
4612 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
fa3d9a6d | 4613 | adapter->stats.rnbc += rd32(E1000_RNBC); |
9d5c8243 AK |
4614 | adapter->stats.ruc += rd32(E1000_RUC); |
4615 | adapter->stats.rfc += rd32(E1000_RFC); | |
4616 | adapter->stats.rjc += rd32(E1000_RJC); | |
4617 | adapter->stats.tor += rd32(E1000_TORH); | |
4618 | adapter->stats.tot += rd32(E1000_TOTH); | |
4619 | adapter->stats.tpr += rd32(E1000_TPR); | |
4620 | ||
4621 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
4622 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
4623 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
4624 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
4625 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
4626 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
4627 | ||
4628 | adapter->stats.mptc += rd32(E1000_MPTC); | |
4629 | adapter->stats.bptc += rd32(E1000_BPTC); | |
4630 | ||
2d0b0f69 NN |
4631 | adapter->stats.tpt += rd32(E1000_TPT); |
4632 | adapter->stats.colc += rd32(E1000_COLC); | |
9d5c8243 AK |
4633 | |
4634 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
43915c7c NN |
4635 | /* read internal phy specific stats */ |
4636 | reg = rd32(E1000_CTRL_EXT); | |
4637 | if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { | |
4638 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
4639 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
4640 | } | |
4641 | ||
9d5c8243 AK |
4642 | adapter->stats.tsctc += rd32(E1000_TSCTC); |
4643 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
4644 | ||
4645 | adapter->stats.iac += rd32(E1000_IAC); | |
4646 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
4647 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
4648 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
4649 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
4650 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
4651 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
4652 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
4653 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
4654 | ||
4655 | /* Fill out the OS statistics structure */ | |
128e45eb AD |
4656 | net_stats->multicast = adapter->stats.mprc; |
4657 | net_stats->collisions = adapter->stats.colc; | |
9d5c8243 AK |
4658 | |
4659 | /* Rx Errors */ | |
4660 | ||
4661 | /* RLEC on some newer hardware can be incorrect so build | |
8c0ab70a | 4662 | * our own version based on RUC and ROC */ |
128e45eb | 4663 | net_stats->rx_errors = adapter->stats.rxerrc + |
9d5c8243 AK |
4664 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
4665 | adapter->stats.ruc + adapter->stats.roc + | |
4666 | adapter->stats.cexterr; | |
128e45eb AD |
4667 | net_stats->rx_length_errors = adapter->stats.ruc + |
4668 | adapter->stats.roc; | |
4669 | net_stats->rx_crc_errors = adapter->stats.crcerrs; | |
4670 | net_stats->rx_frame_errors = adapter->stats.algnerrc; | |
4671 | net_stats->rx_missed_errors = adapter->stats.mpc; | |
9d5c8243 AK |
4672 | |
4673 | /* Tx Errors */ | |
128e45eb AD |
4674 | net_stats->tx_errors = adapter->stats.ecol + |
4675 | adapter->stats.latecol; | |
4676 | net_stats->tx_aborted_errors = adapter->stats.ecol; | |
4677 | net_stats->tx_window_errors = adapter->stats.latecol; | |
4678 | net_stats->tx_carrier_errors = adapter->stats.tncrs; | |
9d5c8243 AK |
4679 | |
4680 | /* Tx Dropped needs to be maintained elsewhere */ | |
4681 | ||
4682 | /* Phy Stats */ | |
4683 | if (hw->phy.media_type == e1000_media_type_copper) { | |
4684 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 4685 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
4686 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
4687 | adapter->phy_stats.idle_errors += phy_tmp; | |
4688 | } | |
4689 | } | |
4690 | ||
4691 | /* Management Stats */ | |
4692 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
4693 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
4694 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
0a915b95 CW |
4695 | |
4696 | /* OS2BMC Stats */ | |
4697 | reg = rd32(E1000_MANC); | |
4698 | if (reg & E1000_MANC_EN_BMC2OS) { | |
4699 | adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); | |
4700 | adapter->stats.o2bspc += rd32(E1000_O2BSPC); | |
4701 | adapter->stats.b2ospc += rd32(E1000_B2OSPC); | |
4702 | adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); | |
4703 | } | |
9d5c8243 AK |
4704 | } |
4705 | ||
9d5c8243 AK |
4706 | static irqreturn_t igb_msix_other(int irq, void *data) |
4707 | { | |
047e0030 | 4708 | struct igb_adapter *adapter = data; |
9d5c8243 | 4709 | struct e1000_hw *hw = &adapter->hw; |
844290e5 | 4710 | u32 icr = rd32(E1000_ICR); |
844290e5 | 4711 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 | 4712 | |
7f081d40 AD |
4713 | if (icr & E1000_ICR_DRSTA) |
4714 | schedule_work(&adapter->reset_task); | |
4715 | ||
047e0030 | 4716 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
4717 | /* HW is reporting DMA is out of sync */ |
4718 | adapter->stats.doosync++; | |
13800469 GR |
4719 | /* The DMA Out of Sync is also indication of a spoof event |
4720 | * in IOV mode. Check the Wrong VM Behavior register to | |
4721 | * see if it is really a spoof event. */ | |
4722 | igb_check_wvbr(adapter); | |
dda0e083 | 4723 | } |
eebbbdba | 4724 | |
4ae196df AD |
4725 | /* Check for a mailbox event */ |
4726 | if (icr & E1000_ICR_VMMB) | |
4727 | igb_msg_task(adapter); | |
4728 | ||
4729 | if (icr & E1000_ICR_LSC) { | |
4730 | hw->mac.get_link_status = 1; | |
4731 | /* guard against interrupt when we're going down */ | |
4732 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4733 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
4734 | } | |
4735 | ||
25568a53 AD |
4736 | if (adapter->vfs_allocated_count) |
4737 | wr32(E1000_IMS, E1000_IMS_LSC | | |
4738 | E1000_IMS_VMMB | | |
4739 | E1000_IMS_DOUTSYNC); | |
4740 | else | |
4741 | wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC); | |
844290e5 | 4742 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
4743 | |
4744 | return IRQ_HANDLED; | |
4745 | } | |
4746 | ||
047e0030 | 4747 | static void igb_write_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4748 | { |
26b39276 | 4749 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 4750 | u32 itr_val = q_vector->itr_val & 0x7FFC; |
9d5c8243 | 4751 | |
047e0030 AD |
4752 | if (!q_vector->set_itr) |
4753 | return; | |
73cd78f1 | 4754 | |
047e0030 AD |
4755 | if (!itr_val) |
4756 | itr_val = 0x4; | |
661086df | 4757 | |
26b39276 AD |
4758 | if (adapter->hw.mac.type == e1000_82575) |
4759 | itr_val |= itr_val << 16; | |
661086df | 4760 | else |
047e0030 | 4761 | itr_val |= 0x8000000; |
661086df | 4762 | |
047e0030 AD |
4763 | writel(itr_val, q_vector->itr_register); |
4764 | q_vector->set_itr = 0; | |
6eb5a7f1 AD |
4765 | } |
4766 | ||
047e0030 | 4767 | static irqreturn_t igb_msix_ring(int irq, void *data) |
9d5c8243 | 4768 | { |
047e0030 | 4769 | struct igb_q_vector *q_vector = data; |
9d5c8243 | 4770 | |
047e0030 AD |
4771 | /* Write the ITR value calculated from the previous interrupt. */ |
4772 | igb_write_itr(q_vector); | |
9d5c8243 | 4773 | |
047e0030 | 4774 | napi_schedule(&q_vector->napi); |
844290e5 | 4775 | |
047e0030 | 4776 | return IRQ_HANDLED; |
fe4506b6 JC |
4777 | } |
4778 | ||
421e02f0 | 4779 | #ifdef CONFIG_IGB_DCA |
047e0030 | 4780 | static void igb_update_dca(struct igb_q_vector *q_vector) |
fe4506b6 | 4781 | { |
047e0030 | 4782 | struct igb_adapter *adapter = q_vector->adapter; |
fe4506b6 JC |
4783 | struct e1000_hw *hw = &adapter->hw; |
4784 | int cpu = get_cpu(); | |
fe4506b6 | 4785 | |
047e0030 AD |
4786 | if (q_vector->cpu == cpu) |
4787 | goto out_no_update; | |
4788 | ||
4789 | if (q_vector->tx_ring) { | |
4790 | int q = q_vector->tx_ring->reg_idx; | |
4791 | u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); | |
4792 | if (hw->mac.type == e1000_82575) { | |
4793 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; | |
4794 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); | |
2d064c06 | 4795 | } else { |
047e0030 AD |
4796 | dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; |
4797 | dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | |
4798 | E1000_DCA_TXCTRL_CPUID_SHIFT; | |
4799 | } | |
4800 | dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; | |
4801 | wr32(E1000_DCA_TXCTRL(q), dca_txctrl); | |
4802 | } | |
4803 | if (q_vector->rx_ring) { | |
4804 | int q = q_vector->rx_ring->reg_idx; | |
4805 | u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); | |
4806 | if (hw->mac.type == e1000_82575) { | |
2d064c06 | 4807 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; |
92be7917 | 4808 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); |
047e0030 AD |
4809 | } else { |
4810 | dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; | |
4811 | dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << | |
4812 | E1000_DCA_RXCTRL_CPUID_SHIFT; | |
2d064c06 | 4813 | } |
fe4506b6 JC |
4814 | dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; |
4815 | dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; | |
4816 | dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; | |
4817 | wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); | |
fe4506b6 | 4818 | } |
047e0030 AD |
4819 | q_vector->cpu = cpu; |
4820 | out_no_update: | |
fe4506b6 JC |
4821 | put_cpu(); |
4822 | } | |
4823 | ||
4824 | static void igb_setup_dca(struct igb_adapter *adapter) | |
4825 | { | |
7e0e99ef | 4826 | struct e1000_hw *hw = &adapter->hw; |
fe4506b6 JC |
4827 | int i; |
4828 | ||
7dfc16fa | 4829 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
4830 | return; |
4831 | ||
7e0e99ef AD |
4832 | /* Always use CB2 mode, difference is masked in the CB driver. */ |
4833 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | |
4834 | ||
047e0030 | 4835 | for (i = 0; i < adapter->num_q_vectors; i++) { |
26b39276 AD |
4836 | adapter->q_vector[i]->cpu = -1; |
4837 | igb_update_dca(adapter->q_vector[i]); | |
fe4506b6 JC |
4838 | } |
4839 | } | |
4840 | ||
4841 | static int __igb_notify_dca(struct device *dev, void *data) | |
4842 | { | |
4843 | struct net_device *netdev = dev_get_drvdata(dev); | |
4844 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4845 | struct pci_dev *pdev = adapter->pdev; |
fe4506b6 JC |
4846 | struct e1000_hw *hw = &adapter->hw; |
4847 | unsigned long event = *(unsigned long *)data; | |
4848 | ||
4849 | switch (event) { | |
4850 | case DCA_PROVIDER_ADD: | |
4851 | /* if already enabled, don't do it again */ | |
7dfc16fa | 4852 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 4853 | break; |
fe4506b6 | 4854 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 4855 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
090b1795 | 4856 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
4857 | igb_setup_dca(adapter); |
4858 | break; | |
4859 | } | |
4860 | /* Fall Through since DCA is disabled. */ | |
4861 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 4862 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 | 4863 | /* without this a class_device is left |
047e0030 | 4864 | * hanging around in the sysfs model */ |
fe4506b6 | 4865 | dca_remove_requester(dev); |
090b1795 | 4866 | dev_info(&pdev->dev, "DCA disabled\n"); |
7dfc16fa | 4867 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 4868 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
4869 | } |
4870 | break; | |
4871 | } | |
bbd98fe4 | 4872 | |
fe4506b6 | 4873 | return 0; |
9d5c8243 AK |
4874 | } |
4875 | ||
fe4506b6 JC |
4876 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
4877 | void *p) | |
4878 | { | |
4879 | int ret_val; | |
4880 | ||
4881 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
4882 | __igb_notify_dca); | |
4883 | ||
4884 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
4885 | } | |
421e02f0 | 4886 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 | 4887 | |
4ae196df AD |
4888 | static void igb_ping_all_vfs(struct igb_adapter *adapter) |
4889 | { | |
4890 | struct e1000_hw *hw = &adapter->hw; | |
4891 | u32 ping; | |
4892 | int i; | |
4893 | ||
4894 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | |
4895 | ping = E1000_PF_CONTROL_MSG; | |
f2ca0dbe | 4896 | if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
4ae196df AD |
4897 | ping |= E1000_VT_MSGTYPE_CTS; |
4898 | igb_write_mbx(hw, &ping, 1, i); | |
4899 | } | |
4900 | } | |
4901 | ||
7d5753f0 AD |
4902 | static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
4903 | { | |
4904 | struct e1000_hw *hw = &adapter->hw; | |
4905 | u32 vmolr = rd32(E1000_VMOLR(vf)); | |
4906 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
4907 | ||
d85b9004 | 4908 | vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | |
7d5753f0 AD |
4909 | IGB_VF_FLAG_MULTI_PROMISC); |
4910 | vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
4911 | ||
4912 | if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { | |
4913 | vmolr |= E1000_VMOLR_MPME; | |
d85b9004 | 4914 | vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; |
7d5753f0 AD |
4915 | *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; |
4916 | } else { | |
4917 | /* | |
4918 | * if we have hashes and we are clearing a multicast promisc | |
4919 | * flag we need to write the hashes to the MTA as this step | |
4920 | * was previously skipped | |
4921 | */ | |
4922 | if (vf_data->num_vf_mc_hashes > 30) { | |
4923 | vmolr |= E1000_VMOLR_MPME; | |
4924 | } else if (vf_data->num_vf_mc_hashes) { | |
4925 | int j; | |
4926 | vmolr |= E1000_VMOLR_ROMPE; | |
4927 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
4928 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
4929 | } | |
4930 | } | |
4931 | ||
4932 | wr32(E1000_VMOLR(vf), vmolr); | |
4933 | ||
4934 | /* there are flags left unprocessed, likely not supported */ | |
4935 | if (*msgbuf & E1000_VT_MSGINFO_MASK) | |
4936 | return -EINVAL; | |
4937 | ||
4938 | return 0; | |
4939 | ||
4940 | } | |
4941 | ||
4ae196df AD |
4942 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
4943 | u32 *msgbuf, u32 vf) | |
4944 | { | |
4945 | int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
4946 | u16 *hash_list = (u16 *)&msgbuf[1]; | |
4947 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
4948 | int i; | |
4949 | ||
7d5753f0 | 4950 | /* salt away the number of multicast addresses assigned |
4ae196df AD |
4951 | * to this VF for later use to restore when the PF multi cast |
4952 | * list changes | |
4953 | */ | |
4954 | vf_data->num_vf_mc_hashes = n; | |
4955 | ||
7d5753f0 AD |
4956 | /* only up to 30 hash values supported */ |
4957 | if (n > 30) | |
4958 | n = 30; | |
4959 | ||
4960 | /* store the hashes for later use */ | |
4ae196df | 4961 | for (i = 0; i < n; i++) |
a419aef8 | 4962 | vf_data->vf_mc_hashes[i] = hash_list[i]; |
4ae196df AD |
4963 | |
4964 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 4965 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
4966 | |
4967 | return 0; | |
4968 | } | |
4969 | ||
4970 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |
4971 | { | |
4972 | struct e1000_hw *hw = &adapter->hw; | |
4973 | struct vf_data_storage *vf_data; | |
4974 | int i, j; | |
4975 | ||
4976 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7d5753f0 AD |
4977 | u32 vmolr = rd32(E1000_VMOLR(i)); |
4978 | vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
4979 | ||
4ae196df | 4980 | vf_data = &adapter->vf_data[i]; |
7d5753f0 AD |
4981 | |
4982 | if ((vf_data->num_vf_mc_hashes > 30) || | |
4983 | (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { | |
4984 | vmolr |= E1000_VMOLR_MPME; | |
4985 | } else if (vf_data->num_vf_mc_hashes) { | |
4986 | vmolr |= E1000_VMOLR_ROMPE; | |
4987 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
4988 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
4989 | } | |
4990 | wr32(E1000_VMOLR(i), vmolr); | |
4ae196df AD |
4991 | } |
4992 | } | |
4993 | ||
4994 | static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) | |
4995 | { | |
4996 | struct e1000_hw *hw = &adapter->hw; | |
4997 | u32 pool_mask, reg, vid; | |
4998 | int i; | |
4999 | ||
5000 | pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5001 | ||
5002 | /* Find the vlan filter for this id */ | |
5003 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5004 | reg = rd32(E1000_VLVF(i)); | |
5005 | ||
5006 | /* remove the vf from the pool */ | |
5007 | reg &= ~pool_mask; | |
5008 | ||
5009 | /* if pool is empty then remove entry from vfta */ | |
5010 | if (!(reg & E1000_VLVF_POOLSEL_MASK) && | |
5011 | (reg & E1000_VLVF_VLANID_ENABLE)) { | |
5012 | reg = 0; | |
5013 | vid = reg & E1000_VLVF_VLANID_MASK; | |
5014 | igb_vfta_set(hw, vid, false); | |
5015 | } | |
5016 | ||
5017 | wr32(E1000_VLVF(i), reg); | |
5018 | } | |
ae641bdc AD |
5019 | |
5020 | adapter->vf_data[vf].vlans_enabled = 0; | |
4ae196df AD |
5021 | } |
5022 | ||
5023 | static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |
5024 | { | |
5025 | struct e1000_hw *hw = &adapter->hw; | |
5026 | u32 reg, i; | |
5027 | ||
51466239 AD |
5028 | /* The vlvf table only exists on 82576 hardware and newer */ |
5029 | if (hw->mac.type < e1000_82576) | |
5030 | return -1; | |
5031 | ||
5032 | /* we only need to do this if VMDq is enabled */ | |
4ae196df AD |
5033 | if (!adapter->vfs_allocated_count) |
5034 | return -1; | |
5035 | ||
5036 | /* Find the vlan filter for this id */ | |
5037 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5038 | reg = rd32(E1000_VLVF(i)); | |
5039 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
5040 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
5041 | break; | |
5042 | } | |
5043 | ||
5044 | if (add) { | |
5045 | if (i == E1000_VLVF_ARRAY_SIZE) { | |
5046 | /* Did not find a matching VLAN ID entry that was | |
5047 | * enabled. Search for a free filter entry, i.e. | |
5048 | * one without the enable bit set | |
5049 | */ | |
5050 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5051 | reg = rd32(E1000_VLVF(i)); | |
5052 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) | |
5053 | break; | |
5054 | } | |
5055 | } | |
5056 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5057 | /* Found an enabled/available entry */ | |
5058 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5059 | ||
5060 | /* if !enabled we need to set this up in vfta */ | |
5061 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | |
51466239 AD |
5062 | /* add VID to filter table */ |
5063 | igb_vfta_set(hw, vid, true); | |
4ae196df AD |
5064 | reg |= E1000_VLVF_VLANID_ENABLE; |
5065 | } | |
cad6d05f AD |
5066 | reg &= ~E1000_VLVF_VLANID_MASK; |
5067 | reg |= vid; | |
4ae196df | 5068 | wr32(E1000_VLVF(i), reg); |
ae641bdc AD |
5069 | |
5070 | /* do not modify RLPML for PF devices */ | |
5071 | if (vf >= adapter->vfs_allocated_count) | |
5072 | return 0; | |
5073 | ||
5074 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5075 | u32 size; | |
5076 | reg = rd32(E1000_VMOLR(vf)); | |
5077 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5078 | size += 4; | |
5079 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5080 | reg |= size; | |
5081 | wr32(E1000_VMOLR(vf), reg); | |
5082 | } | |
ae641bdc | 5083 | |
51466239 | 5084 | adapter->vf_data[vf].vlans_enabled++; |
4ae196df AD |
5085 | return 0; |
5086 | } | |
5087 | } else { | |
5088 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5089 | /* remove vf from the pool */ | |
5090 | reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); | |
5091 | /* if pool is empty then remove entry from vfta */ | |
5092 | if (!(reg & E1000_VLVF_POOLSEL_MASK)) { | |
5093 | reg = 0; | |
5094 | igb_vfta_set(hw, vid, false); | |
5095 | } | |
5096 | wr32(E1000_VLVF(i), reg); | |
ae641bdc AD |
5097 | |
5098 | /* do not modify RLPML for PF devices */ | |
5099 | if (vf >= adapter->vfs_allocated_count) | |
5100 | return 0; | |
5101 | ||
5102 | adapter->vf_data[vf].vlans_enabled--; | |
5103 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5104 | u32 size; | |
5105 | reg = rd32(E1000_VMOLR(vf)); | |
5106 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5107 | size -= 4; | |
5108 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5109 | reg |= size; | |
5110 | wr32(E1000_VMOLR(vf), reg); | |
5111 | } | |
4ae196df AD |
5112 | } |
5113 | } | |
8151d294 WM |
5114 | return 0; |
5115 | } | |
5116 | ||
5117 | static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) | |
5118 | { | |
5119 | struct e1000_hw *hw = &adapter->hw; | |
5120 | ||
5121 | if (vid) | |
5122 | wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); | |
5123 | else | |
5124 | wr32(E1000_VMVIR(vf), 0); | |
5125 | } | |
5126 | ||
5127 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
5128 | int vf, u16 vlan, u8 qos) | |
5129 | { | |
5130 | int err = 0; | |
5131 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5132 | ||
5133 | if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) | |
5134 | return -EINVAL; | |
5135 | if (vlan || qos) { | |
5136 | err = igb_vlvf_set(adapter, vlan, !!vlan, vf); | |
5137 | if (err) | |
5138 | goto out; | |
5139 | igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); | |
5140 | igb_set_vmolr(adapter, vf, !vlan); | |
5141 | adapter->vf_data[vf].pf_vlan = vlan; | |
5142 | adapter->vf_data[vf].pf_qos = qos; | |
5143 | dev_info(&adapter->pdev->dev, | |
5144 | "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); | |
5145 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
5146 | dev_warn(&adapter->pdev->dev, | |
5147 | "The VF VLAN has been set," | |
5148 | " but the PF device is not up.\n"); | |
5149 | dev_warn(&adapter->pdev->dev, | |
5150 | "Bring the PF device up before" | |
5151 | " attempting to use the VF device.\n"); | |
5152 | } | |
5153 | } else { | |
5154 | igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, | |
5155 | false, vf); | |
5156 | igb_set_vmvir(adapter, vlan, vf); | |
5157 | igb_set_vmolr(adapter, vf, true); | |
5158 | adapter->vf_data[vf].pf_vlan = 0; | |
5159 | adapter->vf_data[vf].pf_qos = 0; | |
5160 | } | |
5161 | out: | |
5162 | return err; | |
4ae196df AD |
5163 | } |
5164 | ||
5165 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) | |
5166 | { | |
5167 | int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
5168 | int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); | |
5169 | ||
5170 | return igb_vlvf_set(adapter, vid, add, vf); | |
5171 | } | |
5172 | ||
f2ca0dbe | 5173 | static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5174 | { |
8fa7e0f7 GR |
5175 | /* clear flags - except flag that indicates PF has set the MAC */ |
5176 | adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; | |
f2ca0dbe | 5177 | adapter->vf_data[vf].last_nack = jiffies; |
4ae196df AD |
5178 | |
5179 | /* reset offloads to defaults */ | |
8151d294 | 5180 | igb_set_vmolr(adapter, vf, true); |
4ae196df AD |
5181 | |
5182 | /* reset vlans for device */ | |
5183 | igb_clear_vf_vfta(adapter, vf); | |
8151d294 WM |
5184 | if (adapter->vf_data[vf].pf_vlan) |
5185 | igb_ndo_set_vf_vlan(adapter->netdev, vf, | |
5186 | adapter->vf_data[vf].pf_vlan, | |
5187 | adapter->vf_data[vf].pf_qos); | |
5188 | else | |
5189 | igb_clear_vf_vfta(adapter, vf); | |
4ae196df AD |
5190 | |
5191 | /* reset multicast table array for vf */ | |
5192 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | |
5193 | ||
5194 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5195 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5196 | } |
5197 | ||
f2ca0dbe AD |
5198 | static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
5199 | { | |
5200 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
5201 | ||
5202 | /* generate a new mac address as we were hotplug removed/added */ | |
8151d294 WM |
5203 | if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) |
5204 | random_ether_addr(vf_mac); | |
f2ca0dbe AD |
5205 | |
5206 | /* process remaining reset events */ | |
5207 | igb_vf_reset(adapter, vf); | |
5208 | } | |
5209 | ||
5210 | static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |
4ae196df AD |
5211 | { |
5212 | struct e1000_hw *hw = &adapter->hw; | |
5213 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
ff41f8dc | 5214 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df AD |
5215 | u32 reg, msgbuf[3]; |
5216 | u8 *addr = (u8 *)(&msgbuf[1]); | |
5217 | ||
5218 | /* process all the same items cleared in a function level reset */ | |
f2ca0dbe | 5219 | igb_vf_reset(adapter, vf); |
4ae196df AD |
5220 | |
5221 | /* set vf mac address */ | |
26ad9178 | 5222 | igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
4ae196df AD |
5223 | |
5224 | /* enable transmit and receive for vf */ | |
5225 | reg = rd32(E1000_VFTE); | |
5226 | wr32(E1000_VFTE, reg | (1 << vf)); | |
5227 | reg = rd32(E1000_VFRE); | |
5228 | wr32(E1000_VFRE, reg | (1 << vf)); | |
5229 | ||
8fa7e0f7 | 5230 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; |
4ae196df AD |
5231 | |
5232 | /* reply to reset with ack and vf mac address */ | |
5233 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | |
5234 | memcpy(addr, vf_mac, 6); | |
5235 | igb_write_mbx(hw, msgbuf, 3, vf); | |
5236 | } | |
5237 | ||
5238 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | |
5239 | { | |
de42edde GR |
5240 | /* |
5241 | * The VF MAC Address is stored in a packed array of bytes | |
5242 | * starting at the second 32 bit word of the msg array | |
5243 | */ | |
f2ca0dbe AD |
5244 | unsigned char *addr = (char *)&msg[1]; |
5245 | int err = -1; | |
4ae196df | 5246 | |
f2ca0dbe AD |
5247 | if (is_valid_ether_addr(addr)) |
5248 | err = igb_set_vf_mac(adapter, vf, addr); | |
4ae196df | 5249 | |
f2ca0dbe | 5250 | return err; |
4ae196df AD |
5251 | } |
5252 | ||
5253 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | |
5254 | { | |
5255 | struct e1000_hw *hw = &adapter->hw; | |
f2ca0dbe | 5256 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5257 | u32 msg = E1000_VT_MSGTYPE_NACK; |
5258 | ||
5259 | /* if device isn't clear to send it shouldn't be reading either */ | |
f2ca0dbe AD |
5260 | if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
5261 | time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | |
4ae196df | 5262 | igb_write_mbx(hw, &msg, 1, vf); |
f2ca0dbe | 5263 | vf_data->last_nack = jiffies; |
4ae196df AD |
5264 | } |
5265 | } | |
5266 | ||
f2ca0dbe | 5267 | static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5268 | { |
f2ca0dbe AD |
5269 | struct pci_dev *pdev = adapter->pdev; |
5270 | u32 msgbuf[E1000_VFMAILBOX_SIZE]; | |
4ae196df | 5271 | struct e1000_hw *hw = &adapter->hw; |
f2ca0dbe | 5272 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5273 | s32 retval; |
5274 | ||
f2ca0dbe | 5275 | retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
4ae196df | 5276 | |
fef45f4c AD |
5277 | if (retval) { |
5278 | /* if receive failed revoke VF CTS stats and restart init */ | |
f2ca0dbe | 5279 | dev_err(&pdev->dev, "Error receiving message from VF\n"); |
fef45f4c AD |
5280 | vf_data->flags &= ~IGB_VF_FLAG_CTS; |
5281 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) | |
5282 | return; | |
5283 | goto out; | |
5284 | } | |
4ae196df AD |
5285 | |
5286 | /* this is a message we already processed, do nothing */ | |
5287 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | |
f2ca0dbe | 5288 | return; |
4ae196df AD |
5289 | |
5290 | /* | |
5291 | * until the vf completes a reset it should not be | |
5292 | * allowed to start any configuration. | |
5293 | */ | |
5294 | ||
5295 | if (msgbuf[0] == E1000_VF_RESET) { | |
5296 | igb_vf_reset_msg(adapter, vf); | |
f2ca0dbe | 5297 | return; |
4ae196df AD |
5298 | } |
5299 | ||
f2ca0dbe | 5300 | if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
fef45f4c AD |
5301 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
5302 | return; | |
5303 | retval = -1; | |
5304 | goto out; | |
4ae196df AD |
5305 | } |
5306 | ||
5307 | switch ((msgbuf[0] & 0xFFFF)) { | |
5308 | case E1000_VF_SET_MAC_ADDR: | |
a6b5ea35 GR |
5309 | retval = -EINVAL; |
5310 | if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) | |
5311 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | |
5312 | else | |
5313 | dev_warn(&pdev->dev, | |
5314 | "VF %d attempted to override administratively " | |
5315 | "set MAC address\nReload the VF driver to " | |
5316 | "resume operations\n", vf); | |
4ae196df | 5317 | break; |
7d5753f0 AD |
5318 | case E1000_VF_SET_PROMISC: |
5319 | retval = igb_set_vf_promisc(adapter, msgbuf, vf); | |
5320 | break; | |
4ae196df AD |
5321 | case E1000_VF_SET_MULTICAST: |
5322 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | |
5323 | break; | |
5324 | case E1000_VF_SET_LPE: | |
5325 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | |
5326 | break; | |
5327 | case E1000_VF_SET_VLAN: | |
a6b5ea35 GR |
5328 | retval = -1; |
5329 | if (vf_data->pf_vlan) | |
5330 | dev_warn(&pdev->dev, | |
5331 | "VF %d attempted to override administratively " | |
5332 | "set VLAN tag\nReload the VF driver to " | |
5333 | "resume operations\n", vf); | |
8151d294 WM |
5334 | else |
5335 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | |
4ae196df AD |
5336 | break; |
5337 | default: | |
090b1795 | 5338 | dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
4ae196df AD |
5339 | retval = -1; |
5340 | break; | |
5341 | } | |
5342 | ||
fef45f4c AD |
5343 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; |
5344 | out: | |
4ae196df AD |
5345 | /* notify the VF of the results of what it sent us */ |
5346 | if (retval) | |
5347 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
5348 | else | |
5349 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | |
5350 | ||
4ae196df | 5351 | igb_write_mbx(hw, msgbuf, 1, vf); |
f2ca0dbe | 5352 | } |
4ae196df | 5353 | |
f2ca0dbe AD |
5354 | static void igb_msg_task(struct igb_adapter *adapter) |
5355 | { | |
5356 | struct e1000_hw *hw = &adapter->hw; | |
5357 | u32 vf; | |
5358 | ||
5359 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | |
5360 | /* process any reset requests */ | |
5361 | if (!igb_check_for_rst(hw, vf)) | |
5362 | igb_vf_reset_event(adapter, vf); | |
5363 | ||
5364 | /* process any messages pending */ | |
5365 | if (!igb_check_for_msg(hw, vf)) | |
5366 | igb_rcv_msg_from_vf(adapter, vf); | |
5367 | ||
5368 | /* process any acks */ | |
5369 | if (!igb_check_for_ack(hw, vf)) | |
5370 | igb_rcv_ack_from_vf(adapter, vf); | |
5371 | } | |
4ae196df AD |
5372 | } |
5373 | ||
68d480c4 AD |
5374 | /** |
5375 | * igb_set_uta - Set unicast filter table address | |
5376 | * @adapter: board private structure | |
5377 | * | |
5378 | * The unicast table address is a register array of 32-bit registers. | |
5379 | * The table is meant to be used in a way similar to how the MTA is used | |
5380 | * however due to certain limitations in the hardware it is necessary to | |
25985edc LDM |
5381 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous |
5382 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
68d480c4 AD |
5383 | **/ |
5384 | static void igb_set_uta(struct igb_adapter *adapter) | |
5385 | { | |
5386 | struct e1000_hw *hw = &adapter->hw; | |
5387 | int i; | |
5388 | ||
5389 | /* The UTA table only exists on 82576 hardware and newer */ | |
5390 | if (hw->mac.type < e1000_82576) | |
5391 | return; | |
5392 | ||
5393 | /* we only need to do this if VMDq is enabled */ | |
5394 | if (!adapter->vfs_allocated_count) | |
5395 | return; | |
5396 | ||
5397 | for (i = 0; i < hw->mac.uta_reg_count; i++) | |
5398 | array_wr32(E1000_UTA, i, ~0); | |
5399 | } | |
5400 | ||
9d5c8243 AK |
5401 | /** |
5402 | * igb_intr_msi - Interrupt Handler | |
5403 | * @irq: interrupt number | |
5404 | * @data: pointer to a network interface device structure | |
5405 | **/ | |
5406 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
5407 | { | |
047e0030 AD |
5408 | struct igb_adapter *adapter = data; |
5409 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5410 | struct e1000_hw *hw = &adapter->hw; |
5411 | /* read ICR disables interrupts using IAM */ | |
5412 | u32 icr = rd32(E1000_ICR); | |
5413 | ||
047e0030 | 5414 | igb_write_itr(q_vector); |
9d5c8243 | 5415 | |
7f081d40 AD |
5416 | if (icr & E1000_ICR_DRSTA) |
5417 | schedule_work(&adapter->reset_task); | |
5418 | ||
047e0030 | 5419 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5420 | /* HW is reporting DMA is out of sync */ |
5421 | adapter->stats.doosync++; | |
5422 | } | |
5423 | ||
9d5c8243 AK |
5424 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5425 | hw->mac.get_link_status = 1; | |
5426 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5427 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5428 | } | |
5429 | ||
047e0030 | 5430 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5431 | |
5432 | return IRQ_HANDLED; | |
5433 | } | |
5434 | ||
5435 | /** | |
4a3c6433 | 5436 | * igb_intr - Legacy Interrupt Handler |
9d5c8243 AK |
5437 | * @irq: interrupt number |
5438 | * @data: pointer to a network interface device structure | |
5439 | **/ | |
5440 | static irqreturn_t igb_intr(int irq, void *data) | |
5441 | { | |
047e0030 AD |
5442 | struct igb_adapter *adapter = data; |
5443 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5444 | struct e1000_hw *hw = &adapter->hw; |
5445 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
5446 | * need for the IMC write */ | |
5447 | u32 icr = rd32(E1000_ICR); | |
9d5c8243 AK |
5448 | if (!icr) |
5449 | return IRQ_NONE; /* Not our interrupt */ | |
5450 | ||
047e0030 | 5451 | igb_write_itr(q_vector); |
9d5c8243 AK |
5452 | |
5453 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
5454 | * not set, then the adapter didn't send an interrupt */ | |
5455 | if (!(icr & E1000_ICR_INT_ASSERTED)) | |
5456 | return IRQ_NONE; | |
5457 | ||
7f081d40 AD |
5458 | if (icr & E1000_ICR_DRSTA) |
5459 | schedule_work(&adapter->reset_task); | |
5460 | ||
047e0030 | 5461 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5462 | /* HW is reporting DMA is out of sync */ |
5463 | adapter->stats.doosync++; | |
5464 | } | |
5465 | ||
9d5c8243 AK |
5466 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5467 | hw->mac.get_link_status = 1; | |
5468 | /* guard against interrupt when we're going down */ | |
5469 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5470 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5471 | } | |
5472 | ||
047e0030 | 5473 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5474 | |
5475 | return IRQ_HANDLED; | |
5476 | } | |
5477 | ||
047e0030 | 5478 | static inline void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
9d5c8243 | 5479 | { |
047e0030 | 5480 | struct igb_adapter *adapter = q_vector->adapter; |
46544258 | 5481 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5482 | |
4fc82adf AD |
5483 | if ((q_vector->rx_ring && (adapter->rx_itr_setting & 3)) || |
5484 | (!q_vector->rx_ring && (adapter->tx_itr_setting & 3))) { | |
047e0030 | 5485 | if (!adapter->msix_entries) |
6eb5a7f1 | 5486 | igb_set_itr(adapter); |
46544258 | 5487 | else |
047e0030 | 5488 | igb_update_ring_itr(q_vector); |
9d5c8243 AK |
5489 | } |
5490 | ||
46544258 AD |
5491 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
5492 | if (adapter->msix_entries) | |
047e0030 | 5493 | wr32(E1000_EIMS, q_vector->eims_value); |
46544258 AD |
5494 | else |
5495 | igb_irq_enable(adapter); | |
5496 | } | |
9d5c8243 AK |
5497 | } |
5498 | ||
46544258 AD |
5499 | /** |
5500 | * igb_poll - NAPI Rx polling callback | |
5501 | * @napi: napi polling structure | |
5502 | * @budget: count of how many packets we should handle | |
5503 | **/ | |
5504 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 | 5505 | { |
047e0030 AD |
5506 | struct igb_q_vector *q_vector = container_of(napi, |
5507 | struct igb_q_vector, | |
5508 | napi); | |
16eb8815 | 5509 | bool clean_complete = true; |
9d5c8243 | 5510 | |
421e02f0 | 5511 | #ifdef CONFIG_IGB_DCA |
047e0030 AD |
5512 | if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
5513 | igb_update_dca(q_vector); | |
fe4506b6 | 5514 | #endif |
047e0030 | 5515 | if (q_vector->tx_ring) |
13fde97a | 5516 | clean_complete = igb_clean_tx_irq(q_vector); |
9d5c8243 | 5517 | |
047e0030 | 5518 | if (q_vector->rx_ring) |
cd392f5c | 5519 | clean_complete &= igb_clean_rx_irq(q_vector, budget); |
047e0030 | 5520 | |
16eb8815 AD |
5521 | /* If all work not completed, return budget and keep polling */ |
5522 | if (!clean_complete) | |
5523 | return budget; | |
46544258 | 5524 | |
9d5c8243 | 5525 | /* If not enough Rx work done, exit the polling mode */ |
16eb8815 AD |
5526 | napi_complete(napi); |
5527 | igb_ring_irq_enable(q_vector); | |
9d5c8243 | 5528 | |
16eb8815 | 5529 | return 0; |
9d5c8243 | 5530 | } |
6d8126f9 | 5531 | |
33af6bcc | 5532 | /** |
c5b9bd5e | 5533 | * igb_systim_to_hwtstamp - convert system time value to hw timestamp |
33af6bcc | 5534 | * @adapter: board private structure |
c5b9bd5e AD |
5535 | * @shhwtstamps: timestamp structure to update |
5536 | * @regval: unsigned 64bit system time value. | |
5537 | * | |
5538 | * We need to convert the system time value stored in the RX/TXSTMP registers | |
5539 | * into a hwtstamp which can be used by the upper level timestamping functions | |
5540 | */ | |
5541 | static void igb_systim_to_hwtstamp(struct igb_adapter *adapter, | |
5542 | struct skb_shared_hwtstamps *shhwtstamps, | |
5543 | u64 regval) | |
5544 | { | |
5545 | u64 ns; | |
5546 | ||
55cac248 AD |
5547 | /* |
5548 | * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to | |
5549 | * 24 to match clock shift we setup earlier. | |
5550 | */ | |
5551 | if (adapter->hw.mac.type == e1000_82580) | |
5552 | regval <<= IGB_82580_TSYNC_SHIFT; | |
5553 | ||
c5b9bd5e AD |
5554 | ns = timecounter_cyc2time(&adapter->clock, regval); |
5555 | timecompare_update(&adapter->compare, ns); | |
5556 | memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); | |
5557 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
5558 | shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns); | |
5559 | } | |
5560 | ||
5561 | /** | |
5562 | * igb_tx_hwtstamp - utility function which checks for TX time stamp | |
5563 | * @q_vector: pointer to q_vector containing needed info | |
06034649 | 5564 | * @buffer: pointer to igb_tx_buffer structure |
33af6bcc PO |
5565 | * |
5566 | * If we were asked to do hardware stamping and such a time stamp is | |
5567 | * available, then it must have been for this skb here because we only | |
5568 | * allow only one such packet into the queue. | |
5569 | */ | |
06034649 AD |
5570 | static void igb_tx_hwtstamp(struct igb_q_vector *q_vector, |
5571 | struct igb_tx_buffer *buffer_info) | |
33af6bcc | 5572 | { |
c5b9bd5e | 5573 | struct igb_adapter *adapter = q_vector->adapter; |
33af6bcc | 5574 | struct e1000_hw *hw = &adapter->hw; |
c5b9bd5e AD |
5575 | struct skb_shared_hwtstamps shhwtstamps; |
5576 | u64 regval; | |
33af6bcc | 5577 | |
c5b9bd5e | 5578 | /* if skb does not support hw timestamp or TX stamp not valid exit */ |
2bbfebe2 | 5579 | if (likely(!(buffer_info->tx_flags & IGB_TX_FLAGS_TSTAMP)) || |
c5b9bd5e AD |
5580 | !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID)) |
5581 | return; | |
5582 | ||
5583 | regval = rd32(E1000_TXSTMPL); | |
5584 | regval |= (u64)rd32(E1000_TXSTMPH) << 32; | |
5585 | ||
5586 | igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval); | |
2873957d | 5587 | skb_tstamp_tx(buffer_info->skb, &shhwtstamps); |
33af6bcc PO |
5588 | } |
5589 | ||
9d5c8243 AK |
5590 | /** |
5591 | * igb_clean_tx_irq - Reclaim resources after transmit completes | |
047e0030 | 5592 | * @q_vector: pointer to q_vector containing needed info |
9d5c8243 AK |
5593 | * returns true if ring is completely cleaned |
5594 | **/ | |
047e0030 | 5595 | static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
9d5c8243 | 5596 | { |
047e0030 AD |
5597 | struct igb_adapter *adapter = q_vector->adapter; |
5598 | struct igb_ring *tx_ring = q_vector->tx_ring; | |
06034649 | 5599 | struct igb_tx_buffer *tx_buffer; |
8542db05 | 5600 | union e1000_adv_tx_desc *tx_desc, *eop_desc; |
9d5c8243 | 5601 | unsigned int total_bytes = 0, total_packets = 0; |
13fde97a | 5602 | unsigned int budget = q_vector->tx_work_limit; |
8542db05 | 5603 | unsigned int i = tx_ring->next_to_clean; |
9d5c8243 | 5604 | |
13fde97a AD |
5605 | if (test_bit(__IGB_DOWN, &adapter->state)) |
5606 | return true; | |
0e014cb1 | 5607 | |
06034649 | 5608 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
13fde97a | 5609 | tx_desc = IGB_TX_DESC(tx_ring, i); |
8542db05 | 5610 | i -= tx_ring->count; |
9d5c8243 | 5611 | |
13fde97a | 5612 | for (; budget; budget--) { |
8542db05 | 5613 | eop_desc = tx_buffer->next_to_watch; |
13fde97a | 5614 | |
8542db05 AD |
5615 | /* prevent any other reads prior to eop_desc */ |
5616 | rmb(); | |
5617 | ||
5618 | /* if next_to_watch is not set then there is no work pending */ | |
5619 | if (!eop_desc) | |
5620 | break; | |
13fde97a AD |
5621 | |
5622 | /* if DD is not set pending work has not been completed */ | |
5623 | if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) | |
5624 | break; | |
5625 | ||
8542db05 AD |
5626 | /* clear next_to_watch to prevent false hangs */ |
5627 | tx_buffer->next_to_watch = NULL; | |
9d5c8243 | 5628 | |
ebe42d16 AD |
5629 | /* update the statistics for this packet */ |
5630 | total_bytes += tx_buffer->bytecount; | |
5631 | total_packets += tx_buffer->gso_segs; | |
13fde97a | 5632 | |
ebe42d16 AD |
5633 | /* retrieve hardware timestamp */ |
5634 | igb_tx_hwtstamp(q_vector, tx_buffer); | |
5635 | ||
5636 | /* free the skb */ | |
5637 | dev_kfree_skb_any(tx_buffer->skb); | |
5638 | tx_buffer->skb = NULL; | |
13fde97a | 5639 | |
ebe42d16 AD |
5640 | /* unmap skb header data */ |
5641 | dma_unmap_single(tx_ring->dev, | |
5642 | tx_buffer->dma, | |
5643 | tx_buffer->length, | |
5644 | DMA_TO_DEVICE); | |
5645 | ||
5646 | /* clear last DMA location and unmap remaining buffers */ | |
5647 | while (tx_desc != eop_desc) { | |
5648 | tx_buffer->dma = 0; | |
9d5c8243 | 5649 | |
13fde97a AD |
5650 | tx_buffer++; |
5651 | tx_desc++; | |
9d5c8243 | 5652 | i++; |
8542db05 AD |
5653 | if (unlikely(!i)) { |
5654 | i -= tx_ring->count; | |
06034649 | 5655 | tx_buffer = tx_ring->tx_buffer_info; |
13fde97a AD |
5656 | tx_desc = IGB_TX_DESC(tx_ring, 0); |
5657 | } | |
ebe42d16 AD |
5658 | |
5659 | /* unmap any remaining paged data */ | |
5660 | if (tx_buffer->dma) { | |
5661 | dma_unmap_page(tx_ring->dev, | |
5662 | tx_buffer->dma, | |
5663 | tx_buffer->length, | |
5664 | DMA_TO_DEVICE); | |
5665 | } | |
5666 | } | |
5667 | ||
5668 | /* clear last DMA location */ | |
5669 | tx_buffer->dma = 0; | |
5670 | ||
5671 | /* move us one more past the eop_desc for start of next pkt */ | |
5672 | tx_buffer++; | |
5673 | tx_desc++; | |
5674 | i++; | |
5675 | if (unlikely(!i)) { | |
5676 | i -= tx_ring->count; | |
5677 | tx_buffer = tx_ring->tx_buffer_info; | |
5678 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
5679 | } | |
0e014cb1 AD |
5680 | } |
5681 | ||
8542db05 | 5682 | i += tx_ring->count; |
9d5c8243 | 5683 | tx_ring->next_to_clean = i; |
13fde97a AD |
5684 | u64_stats_update_begin(&tx_ring->tx_syncp); |
5685 | tx_ring->tx_stats.bytes += total_bytes; | |
5686 | tx_ring->tx_stats.packets += total_packets; | |
5687 | u64_stats_update_end(&tx_ring->tx_syncp); | |
5688 | tx_ring->total_bytes += total_bytes; | |
5689 | tx_ring->total_packets += total_packets; | |
9d5c8243 | 5690 | |
13fde97a AD |
5691 | if (tx_ring->detect_tx_hung) { |
5692 | struct e1000_hw *hw = &adapter->hw; | |
12dcd86b | 5693 | |
8542db05 | 5694 | eop_desc = tx_buffer->next_to_watch; |
9d5c8243 | 5695 | |
9d5c8243 AK |
5696 | /* Detect a transmit hang in hardware, this serializes the |
5697 | * check with the clearing of time_stamp and movement of i */ | |
5698 | tx_ring->detect_tx_hung = false; | |
8542db05 AD |
5699 | if (eop_desc && |
5700 | time_after(jiffies, tx_buffer->time_stamp + | |
8e95a202 JP |
5701 | (adapter->tx_timeout_factor * HZ)) && |
5702 | !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { | |
9d5c8243 | 5703 | |
9d5c8243 | 5704 | /* detected Tx unit hang */ |
59d71989 | 5705 | dev_err(tx_ring->dev, |
9d5c8243 | 5706 | "Detected Tx Unit Hang\n" |
2d064c06 | 5707 | " Tx Queue <%d>\n" |
9d5c8243 AK |
5708 | " TDH <%x>\n" |
5709 | " TDT <%x>\n" | |
5710 | " next_to_use <%x>\n" | |
5711 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
5712 | "buffer_info[next_to_clean]\n" |
5713 | " time_stamp <%lx>\n" | |
8542db05 | 5714 | " next_to_watch <%p>\n" |
9d5c8243 AK |
5715 | " jiffies <%lx>\n" |
5716 | " desc.status <%x>\n", | |
2d064c06 | 5717 | tx_ring->queue_index, |
238ac817 | 5718 | rd32(E1000_TDH(tx_ring->reg_idx)), |
fce99e34 | 5719 | readl(tx_ring->tail), |
9d5c8243 AK |
5720 | tx_ring->next_to_use, |
5721 | tx_ring->next_to_clean, | |
8542db05 AD |
5722 | tx_buffer->time_stamp, |
5723 | eop_desc, | |
9d5c8243 | 5724 | jiffies, |
0e014cb1 | 5725 | eop_desc->wb.status); |
13fde97a AD |
5726 | netif_stop_subqueue(tx_ring->netdev, |
5727 | tx_ring->queue_index); | |
5728 | ||
5729 | /* we are about to reset, no point in enabling stuff */ | |
5730 | return true; | |
9d5c8243 AK |
5731 | } |
5732 | } | |
13fde97a AD |
5733 | |
5734 | if (unlikely(total_packets && | |
5735 | netif_carrier_ok(tx_ring->netdev) && | |
5736 | igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { | |
5737 | /* Make sure that anybody stopping the queue after this | |
5738 | * sees the new next_to_clean. | |
5739 | */ | |
5740 | smp_mb(); | |
5741 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
5742 | tx_ring->queue_index) && | |
5743 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
5744 | netif_wake_subqueue(tx_ring->netdev, | |
5745 | tx_ring->queue_index); | |
5746 | ||
5747 | u64_stats_update_begin(&tx_ring->tx_syncp); | |
5748 | tx_ring->tx_stats.restart_queue++; | |
5749 | u64_stats_update_end(&tx_ring->tx_syncp); | |
5750 | } | |
5751 | } | |
5752 | ||
5753 | return !!budget; | |
9d5c8243 AK |
5754 | } |
5755 | ||
cd392f5c AD |
5756 | static inline void igb_rx_checksum(struct igb_ring *ring, |
5757 | u32 status_err, struct sk_buff *skb) | |
9d5c8243 | 5758 | { |
bc8acf2c | 5759 | skb_checksum_none_assert(skb); |
9d5c8243 AK |
5760 | |
5761 | /* Ignore Checksum bit is set or checksum is disabled through ethtool */ | |
85ad76b2 AD |
5762 | if (!(ring->flags & IGB_RING_FLAG_RX_CSUM) || |
5763 | (status_err & E1000_RXD_STAT_IXSM)) | |
9d5c8243 | 5764 | return; |
85ad76b2 | 5765 | |
9d5c8243 AK |
5766 | /* TCP/UDP checksum error bit is set */ |
5767 | if (status_err & | |
5768 | (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) { | |
b9473560 JB |
5769 | /* |
5770 | * work around errata with sctp packets where the TCPE aka | |
5771 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) | |
5772 | * packets, (aka let the stack check the crc32c) | |
5773 | */ | |
85ad76b2 | 5774 | if ((skb->len == 60) && |
12dcd86b ED |
5775 | (ring->flags & IGB_RING_FLAG_RX_SCTP_CSUM)) { |
5776 | u64_stats_update_begin(&ring->rx_syncp); | |
04a5fcaa | 5777 | ring->rx_stats.csum_err++; |
12dcd86b ED |
5778 | u64_stats_update_end(&ring->rx_syncp); |
5779 | } | |
9d5c8243 | 5780 | /* let the stack verify checksum errors */ |
9d5c8243 AK |
5781 | return; |
5782 | } | |
5783 | /* It must be a TCP or UDP packet with a valid checksum */ | |
5784 | if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) | |
5785 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
5786 | ||
59d71989 | 5787 | dev_dbg(ring->dev, "cksum success: bits %08X\n", status_err); |
9d5c8243 AK |
5788 | } |
5789 | ||
757b77e2 | 5790 | static void igb_rx_hwtstamp(struct igb_q_vector *q_vector, u32 staterr, |
c5b9bd5e AD |
5791 | struct sk_buff *skb) |
5792 | { | |
5793 | struct igb_adapter *adapter = q_vector->adapter; | |
5794 | struct e1000_hw *hw = &adapter->hw; | |
5795 | u64 regval; | |
5796 | ||
5797 | /* | |
5798 | * If this bit is set, then the RX registers contain the time stamp. No | |
5799 | * other packet will be time stamped until we read these registers, so | |
5800 | * read the registers to make them available again. Because only one | |
5801 | * packet can be time stamped at a time, we know that the register | |
5802 | * values must belong to this one here and therefore we don't need to | |
5803 | * compare any of the additional attributes stored for it. | |
5804 | * | |
2244d07b | 5805 | * If nothing went wrong, then it should have a shared tx_flags that we |
c5b9bd5e AD |
5806 | * can turn into a skb_shared_hwtstamps. |
5807 | */ | |
757b77e2 NN |
5808 | if (staterr & E1000_RXDADV_STAT_TSIP) { |
5809 | u32 *stamp = (u32 *)skb->data; | |
5810 | regval = le32_to_cpu(*(stamp + 2)); | |
5811 | regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32; | |
5812 | skb_pull(skb, IGB_TS_HDR_LEN); | |
5813 | } else { | |
5814 | if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) | |
5815 | return; | |
c5b9bd5e | 5816 | |
757b77e2 NN |
5817 | regval = rd32(E1000_RXSTMPL); |
5818 | regval |= (u64)rd32(E1000_RXSTMPH) << 32; | |
5819 | } | |
c5b9bd5e AD |
5820 | |
5821 | igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); | |
5822 | } | |
44390ca6 | 5823 | static inline u16 igb_get_hlen(union e1000_adv_rx_desc *rx_desc) |
2d94d8ab AD |
5824 | { |
5825 | /* HW will not DMA in data larger than the given buffer, even if it | |
5826 | * parses the (NFS, of course) header to be larger. In that case, it | |
5827 | * fills the header buffer and spills the rest into the page. | |
5828 | */ | |
5829 | u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & | |
5830 | E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; | |
44390ca6 AD |
5831 | if (hlen > IGB_RX_HDR_LEN) |
5832 | hlen = IGB_RX_HDR_LEN; | |
2d94d8ab AD |
5833 | return hlen; |
5834 | } | |
5835 | ||
cd392f5c | 5836 | static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget) |
9d5c8243 | 5837 | { |
047e0030 | 5838 | struct igb_ring *rx_ring = q_vector->rx_ring; |
16eb8815 AD |
5839 | union e1000_adv_rx_desc *rx_desc; |
5840 | const int current_node = numa_node_id(); | |
9d5c8243 | 5841 | unsigned int total_bytes = 0, total_packets = 0; |
2d94d8ab | 5842 | u32 staterr; |
16eb8815 AD |
5843 | u16 cleaned_count = igb_desc_unused(rx_ring); |
5844 | u16 i = rx_ring->next_to_clean; | |
9d5c8243 | 5845 | |
60136906 | 5846 | rx_desc = IGB_RX_DESC(rx_ring, i); |
9d5c8243 AK |
5847 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
5848 | ||
5849 | while (staterr & E1000_RXD_STAT_DD) { | |
06034649 | 5850 | struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; |
16eb8815 AD |
5851 | struct sk_buff *skb = buffer_info->skb; |
5852 | union e1000_adv_rx_desc *next_rxd; | |
9d5c8243 | 5853 | |
69d3ca53 | 5854 | buffer_info->skb = NULL; |
16eb8815 | 5855 | prefetch(skb->data); |
69d3ca53 AD |
5856 | |
5857 | i++; | |
5858 | if (i == rx_ring->count) | |
5859 | i = 0; | |
42d0781a | 5860 | |
60136906 | 5861 | next_rxd = IGB_RX_DESC(rx_ring, i); |
69d3ca53 | 5862 | prefetch(next_rxd); |
9d5c8243 | 5863 | |
16eb8815 AD |
5864 | /* |
5865 | * This memory barrier is needed to keep us from reading | |
5866 | * any other fields out of the rx_desc until we know the | |
5867 | * RXD_STAT_DD bit is set | |
5868 | */ | |
5869 | rmb(); | |
9d5c8243 | 5870 | |
16eb8815 AD |
5871 | if (!skb_is_nonlinear(skb)) { |
5872 | __skb_put(skb, igb_get_hlen(rx_desc)); | |
5873 | dma_unmap_single(rx_ring->dev, buffer_info->dma, | |
44390ca6 | 5874 | IGB_RX_HDR_LEN, |
59d71989 | 5875 | DMA_FROM_DEVICE); |
91615f76 | 5876 | buffer_info->dma = 0; |
bf36c1a0 AD |
5877 | } |
5878 | ||
16eb8815 AD |
5879 | if (rx_desc->wb.upper.length) { |
5880 | u16 length = le16_to_cpu(rx_desc->wb.upper.length); | |
bf36c1a0 | 5881 | |
aa913403 | 5882 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, |
bf36c1a0 AD |
5883 | buffer_info->page, |
5884 | buffer_info->page_offset, | |
5885 | length); | |
5886 | ||
16eb8815 AD |
5887 | skb->len += length; |
5888 | skb->data_len += length; | |
5889 | skb->truesize += length; | |
5890 | ||
d1eff350 AD |
5891 | if ((page_count(buffer_info->page) != 1) || |
5892 | (page_to_nid(buffer_info->page) != current_node)) | |
bf36c1a0 AD |
5893 | buffer_info->page = NULL; |
5894 | else | |
5895 | get_page(buffer_info->page); | |
9d5c8243 | 5896 | |
16eb8815 AD |
5897 | dma_unmap_page(rx_ring->dev, buffer_info->page_dma, |
5898 | PAGE_SIZE / 2, DMA_FROM_DEVICE); | |
5899 | buffer_info->page_dma = 0; | |
9d5c8243 | 5900 | } |
9d5c8243 | 5901 | |
bf36c1a0 | 5902 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
06034649 AD |
5903 | struct igb_rx_buffer *next_buffer; |
5904 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
b2d56536 AD |
5905 | buffer_info->skb = next_buffer->skb; |
5906 | buffer_info->dma = next_buffer->dma; | |
5907 | next_buffer->skb = skb; | |
5908 | next_buffer->dma = 0; | |
bf36c1a0 AD |
5909 | goto next_desc; |
5910 | } | |
44390ca6 | 5911 | |
9d5c8243 | 5912 | if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) { |
16eb8815 | 5913 | dev_kfree_skb_any(skb); |
9d5c8243 AK |
5914 | goto next_desc; |
5915 | } | |
9d5c8243 | 5916 | |
757b77e2 NN |
5917 | if (staterr & (E1000_RXDADV_STAT_TSIP | E1000_RXDADV_STAT_TS)) |
5918 | igb_rx_hwtstamp(q_vector, staterr, skb); | |
9d5c8243 AK |
5919 | total_bytes += skb->len; |
5920 | total_packets++; | |
5921 | ||
cd392f5c | 5922 | igb_rx_checksum(rx_ring, staterr, skb); |
9d5c8243 | 5923 | |
16eb8815 | 5924 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
047e0030 | 5925 | |
b2cb09b1 JP |
5926 | if (staterr & E1000_RXD_STAT_VP) { |
5927 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9d5c8243 | 5928 | |
b2cb09b1 JP |
5929 | __vlan_hwaccel_put_tag(skb, vid); |
5930 | } | |
5931 | napi_gro_receive(&q_vector->napi, skb); | |
9d5c8243 | 5932 | |
16eb8815 | 5933 | budget--; |
9d5c8243 | 5934 | next_desc: |
16eb8815 AD |
5935 | if (!budget) |
5936 | break; | |
5937 | ||
5938 | cleaned_count++; | |
9d5c8243 AK |
5939 | /* return some buffers to hardware, one at a time is too slow */ |
5940 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
cd392f5c | 5941 | igb_alloc_rx_buffers(rx_ring, cleaned_count); |
9d5c8243 AK |
5942 | cleaned_count = 0; |
5943 | } | |
5944 | ||
5945 | /* use prefetched values */ | |
5946 | rx_desc = next_rxd; | |
9d5c8243 AK |
5947 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
5948 | } | |
bf36c1a0 | 5949 | |
9d5c8243 | 5950 | rx_ring->next_to_clean = i; |
12dcd86b | 5951 | u64_stats_update_begin(&rx_ring->rx_syncp); |
9d5c8243 AK |
5952 | rx_ring->rx_stats.packets += total_packets; |
5953 | rx_ring->rx_stats.bytes += total_bytes; | |
12dcd86b | 5954 | u64_stats_update_end(&rx_ring->rx_syncp); |
c023cd88 AD |
5955 | rx_ring->total_packets += total_packets; |
5956 | rx_ring->total_bytes += total_bytes; | |
5957 | ||
5958 | if (cleaned_count) | |
cd392f5c | 5959 | igb_alloc_rx_buffers(rx_ring, cleaned_count); |
c023cd88 | 5960 | |
16eb8815 | 5961 | return !!budget; |
9d5c8243 AK |
5962 | } |
5963 | ||
c023cd88 | 5964 | static bool igb_alloc_mapped_skb(struct igb_ring *rx_ring, |
06034649 | 5965 | struct igb_rx_buffer *bi) |
c023cd88 AD |
5966 | { |
5967 | struct sk_buff *skb = bi->skb; | |
5968 | dma_addr_t dma = bi->dma; | |
5969 | ||
5970 | if (dma) | |
5971 | return true; | |
5972 | ||
5973 | if (likely(!skb)) { | |
5974 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
5975 | IGB_RX_HDR_LEN); | |
5976 | bi->skb = skb; | |
5977 | if (!skb) { | |
5978 | rx_ring->rx_stats.alloc_failed++; | |
5979 | return false; | |
5980 | } | |
5981 | ||
5982 | /* initialize skb for ring */ | |
5983 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
5984 | } | |
5985 | ||
5986 | dma = dma_map_single(rx_ring->dev, skb->data, | |
5987 | IGB_RX_HDR_LEN, DMA_FROM_DEVICE); | |
5988 | ||
5989 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
5990 | rx_ring->rx_stats.alloc_failed++; | |
5991 | return false; | |
5992 | } | |
5993 | ||
5994 | bi->dma = dma; | |
5995 | return true; | |
5996 | } | |
5997 | ||
5998 | static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, | |
06034649 | 5999 | struct igb_rx_buffer *bi) |
c023cd88 AD |
6000 | { |
6001 | struct page *page = bi->page; | |
6002 | dma_addr_t page_dma = bi->page_dma; | |
6003 | unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2); | |
6004 | ||
6005 | if (page_dma) | |
6006 | return true; | |
6007 | ||
6008 | if (!page) { | |
6009 | page = netdev_alloc_page(rx_ring->netdev); | |
6010 | bi->page = page; | |
6011 | if (unlikely(!page)) { | |
6012 | rx_ring->rx_stats.alloc_failed++; | |
6013 | return false; | |
6014 | } | |
6015 | } | |
6016 | ||
6017 | page_dma = dma_map_page(rx_ring->dev, page, | |
6018 | page_offset, PAGE_SIZE / 2, | |
6019 | DMA_FROM_DEVICE); | |
6020 | ||
6021 | if (dma_mapping_error(rx_ring->dev, page_dma)) { | |
6022 | rx_ring->rx_stats.alloc_failed++; | |
6023 | return false; | |
6024 | } | |
6025 | ||
6026 | bi->page_dma = page_dma; | |
6027 | bi->page_offset = page_offset; | |
6028 | return true; | |
6029 | } | |
6030 | ||
9d5c8243 | 6031 | /** |
cd392f5c | 6032 | * igb_alloc_rx_buffers - Replace used receive buffers; packet split |
9d5c8243 AK |
6033 | * @adapter: address of board private structure |
6034 | **/ | |
cd392f5c | 6035 | void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) |
9d5c8243 | 6036 | { |
9d5c8243 | 6037 | union e1000_adv_rx_desc *rx_desc; |
06034649 | 6038 | struct igb_rx_buffer *bi; |
c023cd88 | 6039 | u16 i = rx_ring->next_to_use; |
9d5c8243 | 6040 | |
60136906 | 6041 | rx_desc = IGB_RX_DESC(rx_ring, i); |
06034649 | 6042 | bi = &rx_ring->rx_buffer_info[i]; |
c023cd88 | 6043 | i -= rx_ring->count; |
9d5c8243 AK |
6044 | |
6045 | while (cleaned_count--) { | |
c023cd88 AD |
6046 | if (!igb_alloc_mapped_skb(rx_ring, bi)) |
6047 | break; | |
9d5c8243 | 6048 | |
c023cd88 AD |
6049 | /* Refresh the desc even if buffer_addrs didn't change |
6050 | * because each write-back erases this info. */ | |
6051 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9d5c8243 | 6052 | |
c023cd88 AD |
6053 | if (!igb_alloc_mapped_page(rx_ring, bi)) |
6054 | break; | |
6055 | ||
6056 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); | |
9d5c8243 | 6057 | |
c023cd88 AD |
6058 | rx_desc++; |
6059 | bi++; | |
9d5c8243 | 6060 | i++; |
c023cd88 | 6061 | if (unlikely(!i)) { |
60136906 | 6062 | rx_desc = IGB_RX_DESC(rx_ring, 0); |
06034649 | 6063 | bi = rx_ring->rx_buffer_info; |
c023cd88 AD |
6064 | i -= rx_ring->count; |
6065 | } | |
6066 | ||
6067 | /* clear the hdr_addr for the next_to_use descriptor */ | |
6068 | rx_desc->read.hdr_addr = 0; | |
9d5c8243 AK |
6069 | } |
6070 | ||
c023cd88 AD |
6071 | i += rx_ring->count; |
6072 | ||
9d5c8243 AK |
6073 | if (rx_ring->next_to_use != i) { |
6074 | rx_ring->next_to_use = i; | |
9d5c8243 AK |
6075 | |
6076 | /* Force memory writes to complete before letting h/w | |
6077 | * know there are new descriptors to fetch. (Only | |
6078 | * applicable for weak-ordered memory model archs, | |
6079 | * such as IA-64). */ | |
6080 | wmb(); | |
fce99e34 | 6081 | writel(i, rx_ring->tail); |
9d5c8243 AK |
6082 | } |
6083 | } | |
6084 | ||
6085 | /** | |
6086 | * igb_mii_ioctl - | |
6087 | * @netdev: | |
6088 | * @ifreq: | |
6089 | * @cmd: | |
6090 | **/ | |
6091 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6092 | { | |
6093 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6094 | struct mii_ioctl_data *data = if_mii(ifr); | |
6095 | ||
6096 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
6097 | return -EOPNOTSUPP; | |
6098 | ||
6099 | switch (cmd) { | |
6100 | case SIOCGMIIPHY: | |
6101 | data->phy_id = adapter->hw.phy.addr; | |
6102 | break; | |
6103 | case SIOCGMIIREG: | |
f5f4cf08 AD |
6104 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
6105 | &data->val_out)) | |
9d5c8243 AK |
6106 | return -EIO; |
6107 | break; | |
6108 | case SIOCSMIIREG: | |
6109 | default: | |
6110 | return -EOPNOTSUPP; | |
6111 | } | |
6112 | return 0; | |
6113 | } | |
6114 | ||
c6cb090b PO |
6115 | /** |
6116 | * igb_hwtstamp_ioctl - control hardware time stamping | |
6117 | * @netdev: | |
6118 | * @ifreq: | |
6119 | * @cmd: | |
6120 | * | |
33af6bcc PO |
6121 | * Outgoing time stamping can be enabled and disabled. Play nice and |
6122 | * disable it when requested, although it shouldn't case any overhead | |
6123 | * when no packet needs it. At most one packet in the queue may be | |
6124 | * marked for time stamping, otherwise it would be impossible to tell | |
6125 | * for sure to which packet the hardware time stamp belongs. | |
6126 | * | |
6127 | * Incoming time stamping has to be configured via the hardware | |
6128 | * filters. Not all combinations are supported, in particular event | |
6129 | * type has to be specified. Matching the kind of event packet is | |
6130 | * not supported, with the exception of "all V2 events regardless of | |
6131 | * level 2 or 4". | |
6132 | * | |
c6cb090b PO |
6133 | **/ |
6134 | static int igb_hwtstamp_ioctl(struct net_device *netdev, | |
6135 | struct ifreq *ifr, int cmd) | |
6136 | { | |
33af6bcc PO |
6137 | struct igb_adapter *adapter = netdev_priv(netdev); |
6138 | struct e1000_hw *hw = &adapter->hw; | |
c6cb090b | 6139 | struct hwtstamp_config config; |
c5b9bd5e AD |
6140 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
6141 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
33af6bcc | 6142 | u32 tsync_rx_cfg = 0; |
c5b9bd5e AD |
6143 | bool is_l4 = false; |
6144 | bool is_l2 = false; | |
33af6bcc | 6145 | u32 regval; |
c6cb090b PO |
6146 | |
6147 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
6148 | return -EFAULT; | |
6149 | ||
6150 | /* reserved for future extensions */ | |
6151 | if (config.flags) | |
6152 | return -EINVAL; | |
6153 | ||
33af6bcc PO |
6154 | switch (config.tx_type) { |
6155 | case HWTSTAMP_TX_OFF: | |
c5b9bd5e | 6156 | tsync_tx_ctl = 0; |
33af6bcc | 6157 | case HWTSTAMP_TX_ON: |
33af6bcc PO |
6158 | break; |
6159 | default: | |
6160 | return -ERANGE; | |
6161 | } | |
6162 | ||
6163 | switch (config.rx_filter) { | |
6164 | case HWTSTAMP_FILTER_NONE: | |
c5b9bd5e | 6165 | tsync_rx_ctl = 0; |
33af6bcc PO |
6166 | break; |
6167 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
6168 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
6169 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
6170 | case HWTSTAMP_FILTER_ALL: | |
6171 | /* | |
6172 | * register TSYNCRXCFG must be set, therefore it is not | |
6173 | * possible to time stamp both Sync and Delay_Req messages | |
6174 | * => fall back to time stamping all packets | |
6175 | */ | |
c5b9bd5e | 6176 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; |
33af6bcc PO |
6177 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
6178 | break; | |
6179 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
c5b9bd5e | 6180 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
33af6bcc | 6181 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; |
c5b9bd5e | 6182 | is_l4 = true; |
33af6bcc PO |
6183 | break; |
6184 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
c5b9bd5e | 6185 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; |
33af6bcc | 6186 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; |
c5b9bd5e | 6187 | is_l4 = true; |
33af6bcc PO |
6188 | break; |
6189 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
6190 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
c5b9bd5e | 6191 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; |
33af6bcc | 6192 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE; |
c5b9bd5e AD |
6193 | is_l2 = true; |
6194 | is_l4 = true; | |
33af6bcc PO |
6195 | config.rx_filter = HWTSTAMP_FILTER_SOME; |
6196 | break; | |
6197 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
6198 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
c5b9bd5e | 6199 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; |
33af6bcc | 6200 | tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE; |
c5b9bd5e AD |
6201 | is_l2 = true; |
6202 | is_l4 = true; | |
33af6bcc PO |
6203 | config.rx_filter = HWTSTAMP_FILTER_SOME; |
6204 | break; | |
6205 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
6206 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
6207 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
c5b9bd5e | 6208 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; |
33af6bcc | 6209 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; |
c5b9bd5e | 6210 | is_l2 = true; |
33af6bcc PO |
6211 | break; |
6212 | default: | |
6213 | return -ERANGE; | |
6214 | } | |
6215 | ||
c5b9bd5e AD |
6216 | if (hw->mac.type == e1000_82575) { |
6217 | if (tsync_rx_ctl | tsync_tx_ctl) | |
6218 | return -EINVAL; | |
6219 | return 0; | |
6220 | } | |
6221 | ||
757b77e2 NN |
6222 | /* |
6223 | * Per-packet timestamping only works if all packets are | |
6224 | * timestamped, so enable timestamping in all packets as | |
6225 | * long as one rx filter was configured. | |
6226 | */ | |
6227 | if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) { | |
6228 | tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
6229 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; | |
6230 | } | |
6231 | ||
33af6bcc PO |
6232 | /* enable/disable TX */ |
6233 | regval = rd32(E1000_TSYNCTXCTL); | |
c5b9bd5e AD |
6234 | regval &= ~E1000_TSYNCTXCTL_ENABLED; |
6235 | regval |= tsync_tx_ctl; | |
33af6bcc PO |
6236 | wr32(E1000_TSYNCTXCTL, regval); |
6237 | ||
c5b9bd5e | 6238 | /* enable/disable RX */ |
33af6bcc | 6239 | regval = rd32(E1000_TSYNCRXCTL); |
c5b9bd5e AD |
6240 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); |
6241 | regval |= tsync_rx_ctl; | |
33af6bcc | 6242 | wr32(E1000_TSYNCRXCTL, regval); |
33af6bcc | 6243 | |
c5b9bd5e AD |
6244 | /* define which PTP packets are time stamped */ |
6245 | wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); | |
33af6bcc | 6246 | |
c5b9bd5e AD |
6247 | /* define ethertype filter for timestamped packets */ |
6248 | if (is_l2) | |
6249 | wr32(E1000_ETQF(3), | |
6250 | (E1000_ETQF_FILTER_ENABLE | /* enable filter */ | |
6251 | E1000_ETQF_1588 | /* enable timestamping */ | |
6252 | ETH_P_1588)); /* 1588 eth protocol type */ | |
6253 | else | |
6254 | wr32(E1000_ETQF(3), 0); | |
6255 | ||
6256 | #define PTP_PORT 319 | |
6257 | /* L4 Queue Filter[3]: filter by destination port and protocol */ | |
6258 | if (is_l4) { | |
6259 | u32 ftqf = (IPPROTO_UDP /* UDP */ | |
6260 | | E1000_FTQF_VF_BP /* VF not compared */ | |
6261 | | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ | |
6262 | | E1000_FTQF_MASK); /* mask all inputs */ | |
6263 | ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ | |
6264 | ||
6265 | wr32(E1000_IMIR(3), htons(PTP_PORT)); | |
6266 | wr32(E1000_IMIREXT(3), | |
6267 | (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); | |
6268 | if (hw->mac.type == e1000_82576) { | |
6269 | /* enable source port check */ | |
6270 | wr32(E1000_SPQF(3), htons(PTP_PORT)); | |
6271 | ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; | |
6272 | } | |
6273 | wr32(E1000_FTQF(3), ftqf); | |
6274 | } else { | |
6275 | wr32(E1000_FTQF(3), E1000_FTQF_MASK); | |
6276 | } | |
33af6bcc PO |
6277 | wrfl(); |
6278 | ||
6279 | adapter->hwtstamp_config = config; | |
6280 | ||
6281 | /* clear TX/RX time stamp registers, just to be sure */ | |
6282 | regval = rd32(E1000_TXSTMPH); | |
6283 | regval = rd32(E1000_RXSTMPH); | |
c6cb090b | 6284 | |
33af6bcc PO |
6285 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? |
6286 | -EFAULT : 0; | |
c6cb090b PO |
6287 | } |
6288 | ||
9d5c8243 AK |
6289 | /** |
6290 | * igb_ioctl - | |
6291 | * @netdev: | |
6292 | * @ifreq: | |
6293 | * @cmd: | |
6294 | **/ | |
6295 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6296 | { | |
6297 | switch (cmd) { | |
6298 | case SIOCGMIIPHY: | |
6299 | case SIOCGMIIREG: | |
6300 | case SIOCSMIIREG: | |
6301 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b PO |
6302 | case SIOCSHWTSTAMP: |
6303 | return igb_hwtstamp_ioctl(netdev, ifr, cmd); | |
9d5c8243 AK |
6304 | default: |
6305 | return -EOPNOTSUPP; | |
6306 | } | |
6307 | } | |
6308 | ||
009bc06e AD |
6309 | s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
6310 | { | |
6311 | struct igb_adapter *adapter = hw->back; | |
6312 | u16 cap_offset; | |
6313 | ||
bdaae04c | 6314 | cap_offset = adapter->pdev->pcie_cap; |
009bc06e AD |
6315 | if (!cap_offset) |
6316 | return -E1000_ERR_CONFIG; | |
6317 | ||
6318 | pci_read_config_word(adapter->pdev, cap_offset + reg, value); | |
6319 | ||
6320 | return 0; | |
6321 | } | |
6322 | ||
6323 | s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) | |
6324 | { | |
6325 | struct igb_adapter *adapter = hw->back; | |
6326 | u16 cap_offset; | |
6327 | ||
bdaae04c | 6328 | cap_offset = adapter->pdev->pcie_cap; |
009bc06e AD |
6329 | if (!cap_offset) |
6330 | return -E1000_ERR_CONFIG; | |
6331 | ||
6332 | pci_write_config_word(adapter->pdev, cap_offset + reg, *value); | |
6333 | ||
6334 | return 0; | |
6335 | } | |
6336 | ||
b2cb09b1 | 6337 | static void igb_vlan_mode(struct net_device *netdev, u32 features) |
9d5c8243 AK |
6338 | { |
6339 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6340 | struct e1000_hw *hw = &adapter->hw; | |
6341 | u32 ctrl, rctl; | |
6342 | ||
6343 | igb_irq_disable(adapter); | |
9d5c8243 | 6344 | |
b2cb09b1 | 6345 | if (features & NETIF_F_HW_VLAN_RX) { |
9d5c8243 AK |
6346 | /* enable VLAN tag insert/strip */ |
6347 | ctrl = rd32(E1000_CTRL); | |
6348 | ctrl |= E1000_CTRL_VME; | |
6349 | wr32(E1000_CTRL, ctrl); | |
6350 | ||
51466239 | 6351 | /* Disable CFI check */ |
9d5c8243 | 6352 | rctl = rd32(E1000_RCTL); |
9d5c8243 AK |
6353 | rctl &= ~E1000_RCTL_CFIEN; |
6354 | wr32(E1000_RCTL, rctl); | |
9d5c8243 AK |
6355 | } else { |
6356 | /* disable VLAN tag insert/strip */ | |
6357 | ctrl = rd32(E1000_CTRL); | |
6358 | ctrl &= ~E1000_CTRL_VME; | |
6359 | wr32(E1000_CTRL, ctrl); | |
9d5c8243 AK |
6360 | } |
6361 | ||
e1739522 AD |
6362 | igb_rlpml_set(adapter); |
6363 | ||
9d5c8243 AK |
6364 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
6365 | igb_irq_enable(adapter); | |
6366 | } | |
6367 | ||
6368 | static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) | |
6369 | { | |
6370 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6371 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6372 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 | 6373 | |
51466239 AD |
6374 | /* attempt to add filter to vlvf array */ |
6375 | igb_vlvf_set(adapter, vid, true, pf_id); | |
4ae196df | 6376 | |
51466239 AD |
6377 | /* add the filter since PF can receive vlans w/o entry in vlvf */ |
6378 | igb_vfta_set(hw, vid, true); | |
b2cb09b1 JP |
6379 | |
6380 | set_bit(vid, adapter->active_vlans); | |
9d5c8243 AK |
6381 | } |
6382 | ||
6383 | static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
6384 | { | |
6385 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6386 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6387 | int pf_id = adapter->vfs_allocated_count; |
51466239 | 6388 | s32 err; |
9d5c8243 AK |
6389 | |
6390 | igb_irq_disable(adapter); | |
9d5c8243 AK |
6391 | |
6392 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
6393 | igb_irq_enable(adapter); | |
6394 | ||
51466239 AD |
6395 | /* remove vlan from VLVF table array */ |
6396 | err = igb_vlvf_set(adapter, vid, false, pf_id); | |
9d5c8243 | 6397 | |
51466239 AD |
6398 | /* if vid was not present in VLVF just remove it from table */ |
6399 | if (err) | |
4ae196df | 6400 | igb_vfta_set(hw, vid, false); |
b2cb09b1 JP |
6401 | |
6402 | clear_bit(vid, adapter->active_vlans); | |
9d5c8243 AK |
6403 | } |
6404 | ||
6405 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
6406 | { | |
b2cb09b1 | 6407 | u16 vid; |
9d5c8243 | 6408 | |
b2cb09b1 JP |
6409 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
6410 | igb_vlan_rx_add_vid(adapter->netdev, vid); | |
9d5c8243 AK |
6411 | } |
6412 | ||
14ad2513 | 6413 | int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) |
9d5c8243 | 6414 | { |
090b1795 | 6415 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
6416 | struct e1000_mac_info *mac = &adapter->hw.mac; |
6417 | ||
6418 | mac->autoneg = 0; | |
6419 | ||
14ad2513 DD |
6420 | /* Make sure dplx is at most 1 bit and lsb of speed is not set |
6421 | * for the switch() below to work */ | |
6422 | if ((spd & 1) || (dplx & ~1)) | |
6423 | goto err_inval; | |
6424 | ||
cd2638a8 CW |
6425 | /* Fiber NIC's only allow 1000 Gbps Full duplex */ |
6426 | if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) && | |
14ad2513 DD |
6427 | spd != SPEED_1000 && |
6428 | dplx != DUPLEX_FULL) | |
6429 | goto err_inval; | |
cd2638a8 | 6430 | |
14ad2513 | 6431 | switch (spd + dplx) { |
9d5c8243 AK |
6432 | case SPEED_10 + DUPLEX_HALF: |
6433 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
6434 | break; | |
6435 | case SPEED_10 + DUPLEX_FULL: | |
6436 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
6437 | break; | |
6438 | case SPEED_100 + DUPLEX_HALF: | |
6439 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
6440 | break; | |
6441 | case SPEED_100 + DUPLEX_FULL: | |
6442 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
6443 | break; | |
6444 | case SPEED_1000 + DUPLEX_FULL: | |
6445 | mac->autoneg = 1; | |
6446 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
6447 | break; | |
6448 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
6449 | default: | |
14ad2513 | 6450 | goto err_inval; |
9d5c8243 AK |
6451 | } |
6452 | return 0; | |
14ad2513 DD |
6453 | |
6454 | err_inval: | |
6455 | dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); | |
6456 | return -EINVAL; | |
9d5c8243 AK |
6457 | } |
6458 | ||
3fe7c4c9 | 6459 | static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake) |
9d5c8243 AK |
6460 | { |
6461 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6462 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6463 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 6464 | u32 ctrl, rctl, status; |
9d5c8243 AK |
6465 | u32 wufc = adapter->wol; |
6466 | #ifdef CONFIG_PM | |
6467 | int retval = 0; | |
6468 | #endif | |
6469 | ||
6470 | netif_device_detach(netdev); | |
6471 | ||
a88f10ec AD |
6472 | if (netif_running(netdev)) |
6473 | igb_close(netdev); | |
6474 | ||
047e0030 | 6475 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
6476 | |
6477 | #ifdef CONFIG_PM | |
6478 | retval = pci_save_state(pdev); | |
6479 | if (retval) | |
6480 | return retval; | |
6481 | #endif | |
6482 | ||
6483 | status = rd32(E1000_STATUS); | |
6484 | if (status & E1000_STATUS_LU) | |
6485 | wufc &= ~E1000_WUFC_LNKC; | |
6486 | ||
6487 | if (wufc) { | |
6488 | igb_setup_rctl(adapter); | |
ff41f8dc | 6489 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
6490 | |
6491 | /* turn on all-multi mode if wake on multicast is enabled */ | |
6492 | if (wufc & E1000_WUFC_MC) { | |
6493 | rctl = rd32(E1000_RCTL); | |
6494 | rctl |= E1000_RCTL_MPE; | |
6495 | wr32(E1000_RCTL, rctl); | |
6496 | } | |
6497 | ||
6498 | ctrl = rd32(E1000_CTRL); | |
6499 | /* advertise wake from D3Cold */ | |
6500 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
6501 | /* phy power management enable */ | |
6502 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
6503 | ctrl |= E1000_CTRL_ADVD3WUC; | |
6504 | wr32(E1000_CTRL, ctrl); | |
6505 | ||
9d5c8243 | 6506 | /* Allow time for pending master requests to run */ |
330a6d6a | 6507 | igb_disable_pcie_master(hw); |
9d5c8243 AK |
6508 | |
6509 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
6510 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
6511 | } else { |
6512 | wr32(E1000_WUC, 0); | |
6513 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
6514 | } |
6515 | ||
3fe7c4c9 RW |
6516 | *enable_wake = wufc || adapter->en_mng_pt; |
6517 | if (!*enable_wake) | |
88a268c1 NN |
6518 | igb_power_down_link(adapter); |
6519 | else | |
6520 | igb_power_up_link(adapter); | |
9d5c8243 AK |
6521 | |
6522 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
6523 | * would have already happened in close and is redundant. */ | |
6524 | igb_release_hw_control(adapter); | |
6525 | ||
6526 | pci_disable_device(pdev); | |
6527 | ||
9d5c8243 AK |
6528 | return 0; |
6529 | } | |
6530 | ||
6531 | #ifdef CONFIG_PM | |
3fe7c4c9 RW |
6532 | static int igb_suspend(struct pci_dev *pdev, pm_message_t state) |
6533 | { | |
6534 | int retval; | |
6535 | bool wake; | |
6536 | ||
6537 | retval = __igb_shutdown(pdev, &wake); | |
6538 | if (retval) | |
6539 | return retval; | |
6540 | ||
6541 | if (wake) { | |
6542 | pci_prepare_to_sleep(pdev); | |
6543 | } else { | |
6544 | pci_wake_from_d3(pdev, false); | |
6545 | pci_set_power_state(pdev, PCI_D3hot); | |
6546 | } | |
6547 | ||
6548 | return 0; | |
6549 | } | |
6550 | ||
9d5c8243 AK |
6551 | static int igb_resume(struct pci_dev *pdev) |
6552 | { | |
6553 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6554 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6555 | struct e1000_hw *hw = &adapter->hw; | |
6556 | u32 err; | |
6557 | ||
6558 | pci_set_power_state(pdev, PCI_D0); | |
6559 | pci_restore_state(pdev); | |
b94f2d77 | 6560 | pci_save_state(pdev); |
42bfd33a | 6561 | |
aed5dec3 | 6562 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
6563 | if (err) { |
6564 | dev_err(&pdev->dev, | |
6565 | "igb: Cannot enable PCI device from suspend\n"); | |
6566 | return err; | |
6567 | } | |
6568 | pci_set_master(pdev); | |
6569 | ||
6570 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
6571 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
6572 | ||
047e0030 | 6573 | if (igb_init_interrupt_scheme(adapter)) { |
a88f10ec AD |
6574 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
6575 | return -ENOMEM; | |
9d5c8243 AK |
6576 | } |
6577 | ||
9d5c8243 | 6578 | igb_reset(adapter); |
a8564f03 AD |
6579 | |
6580 | /* let the f/w know that the h/w is now under the control of the | |
6581 | * driver. */ | |
6582 | igb_get_hw_control(adapter); | |
6583 | ||
9d5c8243 AK |
6584 | wr32(E1000_WUS, ~0); |
6585 | ||
a88f10ec AD |
6586 | if (netif_running(netdev)) { |
6587 | err = igb_open(netdev); | |
6588 | if (err) | |
6589 | return err; | |
6590 | } | |
9d5c8243 AK |
6591 | |
6592 | netif_device_attach(netdev); | |
6593 | ||
9d5c8243 AK |
6594 | return 0; |
6595 | } | |
6596 | #endif | |
6597 | ||
6598 | static void igb_shutdown(struct pci_dev *pdev) | |
6599 | { | |
3fe7c4c9 RW |
6600 | bool wake; |
6601 | ||
6602 | __igb_shutdown(pdev, &wake); | |
6603 | ||
6604 | if (system_state == SYSTEM_POWER_OFF) { | |
6605 | pci_wake_from_d3(pdev, wake); | |
6606 | pci_set_power_state(pdev, PCI_D3hot); | |
6607 | } | |
9d5c8243 AK |
6608 | } |
6609 | ||
6610 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
6611 | /* | |
6612 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6613 | * without having to re-enable interrupts. It's not called while | |
6614 | * the interrupt routine is executing. | |
6615 | */ | |
6616 | static void igb_netpoll(struct net_device *netdev) | |
6617 | { | |
6618 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 6619 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 6620 | int i; |
9d5c8243 | 6621 | |
eebbbdba | 6622 | if (!adapter->msix_entries) { |
047e0030 | 6623 | struct igb_q_vector *q_vector = adapter->q_vector[0]; |
eebbbdba | 6624 | igb_irq_disable(adapter); |
047e0030 | 6625 | napi_schedule(&q_vector->napi); |
eebbbdba AD |
6626 | return; |
6627 | } | |
9d5c8243 | 6628 | |
047e0030 AD |
6629 | for (i = 0; i < adapter->num_q_vectors; i++) { |
6630 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
6631 | wr32(E1000_EIMC, q_vector->eims_value); | |
6632 | napi_schedule(&q_vector->napi); | |
eebbbdba | 6633 | } |
9d5c8243 AK |
6634 | } |
6635 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
6636 | ||
6637 | /** | |
6638 | * igb_io_error_detected - called when PCI error is detected | |
6639 | * @pdev: Pointer to PCI device | |
6640 | * @state: The current pci connection state | |
6641 | * | |
6642 | * This function is called after a PCI bus error affecting | |
6643 | * this device has been detected. | |
6644 | */ | |
6645 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, | |
6646 | pci_channel_state_t state) | |
6647 | { | |
6648 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6649 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6650 | ||
6651 | netif_device_detach(netdev); | |
6652 | ||
59ed6eec AD |
6653 | if (state == pci_channel_io_perm_failure) |
6654 | return PCI_ERS_RESULT_DISCONNECT; | |
6655 | ||
9d5c8243 AK |
6656 | if (netif_running(netdev)) |
6657 | igb_down(adapter); | |
6658 | pci_disable_device(pdev); | |
6659 | ||
6660 | /* Request a slot slot reset. */ | |
6661 | return PCI_ERS_RESULT_NEED_RESET; | |
6662 | } | |
6663 | ||
6664 | /** | |
6665 | * igb_io_slot_reset - called after the pci bus has been reset. | |
6666 | * @pdev: Pointer to PCI device | |
6667 | * | |
6668 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
6669 | * resembles the first-half of the igb_resume routine. | |
6670 | */ | |
6671 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) | |
6672 | { | |
6673 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6674 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6675 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 6676 | pci_ers_result_t result; |
42bfd33a | 6677 | int err; |
9d5c8243 | 6678 | |
aed5dec3 | 6679 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
6680 | dev_err(&pdev->dev, |
6681 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
6682 | result = PCI_ERS_RESULT_DISCONNECT; |
6683 | } else { | |
6684 | pci_set_master(pdev); | |
6685 | pci_restore_state(pdev); | |
b94f2d77 | 6686 | pci_save_state(pdev); |
9d5c8243 | 6687 | |
40a914fa AD |
6688 | pci_enable_wake(pdev, PCI_D3hot, 0); |
6689 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 6690 | |
40a914fa AD |
6691 | igb_reset(adapter); |
6692 | wr32(E1000_WUS, ~0); | |
6693 | result = PCI_ERS_RESULT_RECOVERED; | |
6694 | } | |
9d5c8243 | 6695 | |
ea943d41 JK |
6696 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
6697 | if (err) { | |
6698 | dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " | |
6699 | "failed 0x%0x\n", err); | |
6700 | /* non-fatal, continue */ | |
6701 | } | |
40a914fa AD |
6702 | |
6703 | return result; | |
9d5c8243 AK |
6704 | } |
6705 | ||
6706 | /** | |
6707 | * igb_io_resume - called when traffic can start flowing again. | |
6708 | * @pdev: Pointer to PCI device | |
6709 | * | |
6710 | * This callback is called when the error recovery driver tells us that | |
6711 | * its OK to resume normal operation. Implementation resembles the | |
6712 | * second-half of the igb_resume routine. | |
6713 | */ | |
6714 | static void igb_io_resume(struct pci_dev *pdev) | |
6715 | { | |
6716 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6717 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6718 | ||
9d5c8243 AK |
6719 | if (netif_running(netdev)) { |
6720 | if (igb_up(adapter)) { | |
6721 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
6722 | return; | |
6723 | } | |
6724 | } | |
6725 | ||
6726 | netif_device_attach(netdev); | |
6727 | ||
6728 | /* let the f/w know that the h/w is now under the control of the | |
6729 | * driver. */ | |
6730 | igb_get_hw_control(adapter); | |
9d5c8243 AK |
6731 | } |
6732 | ||
26ad9178 AD |
6733 | static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, |
6734 | u8 qsel) | |
6735 | { | |
6736 | u32 rar_low, rar_high; | |
6737 | struct e1000_hw *hw = &adapter->hw; | |
6738 | ||
6739 | /* HW expects these in little endian so we reverse the byte order | |
6740 | * from network order (big endian) to little endian | |
6741 | */ | |
6742 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
6743 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); | |
6744 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); | |
6745 | ||
6746 | /* Indicate to hardware the Address is Valid. */ | |
6747 | rar_high |= E1000_RAH_AV; | |
6748 | ||
6749 | if (hw->mac.type == e1000_82575) | |
6750 | rar_high |= E1000_RAH_POOL_1 * qsel; | |
6751 | else | |
6752 | rar_high |= E1000_RAH_POOL_1 << qsel; | |
6753 | ||
6754 | wr32(E1000_RAL(index), rar_low); | |
6755 | wrfl(); | |
6756 | wr32(E1000_RAH(index), rar_high); | |
6757 | wrfl(); | |
6758 | } | |
6759 | ||
4ae196df AD |
6760 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
6761 | int vf, unsigned char *mac_addr) | |
6762 | { | |
6763 | struct e1000_hw *hw = &adapter->hw; | |
ff41f8dc AD |
6764 | /* VF MAC addresses start at end of receive addresses and moves |
6765 | * torwards the first, as a result a collision should not be possible */ | |
6766 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); | |
4ae196df | 6767 | |
37680117 | 6768 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
4ae196df | 6769 | |
26ad9178 | 6770 | igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
4ae196df AD |
6771 | |
6772 | return 0; | |
6773 | } | |
6774 | ||
8151d294 WM |
6775 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
6776 | { | |
6777 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6778 | if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) | |
6779 | return -EINVAL; | |
6780 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; | |
6781 | dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); | |
6782 | dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" | |
6783 | " change effective."); | |
6784 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
6785 | dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," | |
6786 | " but the PF device is not up.\n"); | |
6787 | dev_warn(&adapter->pdev->dev, "Bring the PF device up before" | |
6788 | " attempting to use the VF device.\n"); | |
6789 | } | |
6790 | return igb_set_vf_mac(adapter, vf, mac); | |
6791 | } | |
6792 | ||
17dc566c LL |
6793 | static int igb_link_mbps(int internal_link_speed) |
6794 | { | |
6795 | switch (internal_link_speed) { | |
6796 | case SPEED_100: | |
6797 | return 100; | |
6798 | case SPEED_1000: | |
6799 | return 1000; | |
6800 | default: | |
6801 | return 0; | |
6802 | } | |
6803 | } | |
6804 | ||
6805 | static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, | |
6806 | int link_speed) | |
6807 | { | |
6808 | int rf_dec, rf_int; | |
6809 | u32 bcnrc_val; | |
6810 | ||
6811 | if (tx_rate != 0) { | |
6812 | /* Calculate the rate factor values to set */ | |
6813 | rf_int = link_speed / tx_rate; | |
6814 | rf_dec = (link_speed - (rf_int * tx_rate)); | |
6815 | rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate; | |
6816 | ||
6817 | bcnrc_val = E1000_RTTBCNRC_RS_ENA; | |
6818 | bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) & | |
6819 | E1000_RTTBCNRC_RF_INT_MASK); | |
6820 | bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); | |
6821 | } else { | |
6822 | bcnrc_val = 0; | |
6823 | } | |
6824 | ||
6825 | wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ | |
6826 | wr32(E1000_RTTBCNRC, bcnrc_val); | |
6827 | } | |
6828 | ||
6829 | static void igb_check_vf_rate_limit(struct igb_adapter *adapter) | |
6830 | { | |
6831 | int actual_link_speed, i; | |
6832 | bool reset_rate = false; | |
6833 | ||
6834 | /* VF TX rate limit was not set or not supported */ | |
6835 | if ((adapter->vf_rate_link_speed == 0) || | |
6836 | (adapter->hw.mac.type != e1000_82576)) | |
6837 | return; | |
6838 | ||
6839 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
6840 | if (actual_link_speed != adapter->vf_rate_link_speed) { | |
6841 | reset_rate = true; | |
6842 | adapter->vf_rate_link_speed = 0; | |
6843 | dev_info(&adapter->pdev->dev, | |
6844 | "Link speed has been changed. VF Transmit " | |
6845 | "rate is disabled\n"); | |
6846 | } | |
6847 | ||
6848 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
6849 | if (reset_rate) | |
6850 | adapter->vf_data[i].tx_rate = 0; | |
6851 | ||
6852 | igb_set_vf_rate_limit(&adapter->hw, i, | |
6853 | adapter->vf_data[i].tx_rate, | |
6854 | actual_link_speed); | |
6855 | } | |
6856 | } | |
6857 | ||
8151d294 WM |
6858 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) |
6859 | { | |
17dc566c LL |
6860 | struct igb_adapter *adapter = netdev_priv(netdev); |
6861 | struct e1000_hw *hw = &adapter->hw; | |
6862 | int actual_link_speed; | |
6863 | ||
6864 | if (hw->mac.type != e1000_82576) | |
6865 | return -EOPNOTSUPP; | |
6866 | ||
6867 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
6868 | if ((vf >= adapter->vfs_allocated_count) || | |
6869 | (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || | |
6870 | (tx_rate < 0) || (tx_rate > actual_link_speed)) | |
6871 | return -EINVAL; | |
6872 | ||
6873 | adapter->vf_rate_link_speed = actual_link_speed; | |
6874 | adapter->vf_data[vf].tx_rate = (u16)tx_rate; | |
6875 | igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); | |
6876 | ||
6877 | return 0; | |
8151d294 WM |
6878 | } |
6879 | ||
6880 | static int igb_ndo_get_vf_config(struct net_device *netdev, | |
6881 | int vf, struct ifla_vf_info *ivi) | |
6882 | { | |
6883 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6884 | if (vf >= adapter->vfs_allocated_count) | |
6885 | return -EINVAL; | |
6886 | ivi->vf = vf; | |
6887 | memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); | |
17dc566c | 6888 | ivi->tx_rate = adapter->vf_data[vf].tx_rate; |
8151d294 WM |
6889 | ivi->vlan = adapter->vf_data[vf].pf_vlan; |
6890 | ivi->qos = adapter->vf_data[vf].pf_qos; | |
6891 | return 0; | |
6892 | } | |
6893 | ||
4ae196df AD |
6894 | static void igb_vmm_control(struct igb_adapter *adapter) |
6895 | { | |
6896 | struct e1000_hw *hw = &adapter->hw; | |
10d8e907 | 6897 | u32 reg; |
4ae196df | 6898 | |
52a1dd4d AD |
6899 | switch (hw->mac.type) { |
6900 | case e1000_82575: | |
6901 | default: | |
6902 | /* replication is not supported for 82575 */ | |
4ae196df | 6903 | return; |
52a1dd4d AD |
6904 | case e1000_82576: |
6905 | /* notify HW that the MAC is adding vlan tags */ | |
6906 | reg = rd32(E1000_DTXCTL); | |
6907 | reg |= E1000_DTXCTL_VLAN_ADDED; | |
6908 | wr32(E1000_DTXCTL, reg); | |
6909 | case e1000_82580: | |
6910 | /* enable replication vlan tag stripping */ | |
6911 | reg = rd32(E1000_RPLOLR); | |
6912 | reg |= E1000_RPLOLR_STRVLAN; | |
6913 | wr32(E1000_RPLOLR, reg); | |
d2ba2ed8 AD |
6914 | case e1000_i350: |
6915 | /* none of the above registers are supported by i350 */ | |
52a1dd4d AD |
6916 | break; |
6917 | } | |
10d8e907 | 6918 | |
d4960307 AD |
6919 | if (adapter->vfs_allocated_count) { |
6920 | igb_vmdq_set_loopback_pf(hw, true); | |
6921 | igb_vmdq_set_replication_pf(hw, true); | |
13800469 GR |
6922 | igb_vmdq_set_anti_spoofing_pf(hw, true, |
6923 | adapter->vfs_allocated_count); | |
d4960307 AD |
6924 | } else { |
6925 | igb_vmdq_set_loopback_pf(hw, false); | |
6926 | igb_vmdq_set_replication_pf(hw, false); | |
6927 | } | |
4ae196df AD |
6928 | } |
6929 | ||
9d5c8243 | 6930 | /* igb_main.c */ |