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igb: Support ports mapped in 64-bit PCI space
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
66f40b8a 65#define BUILD 5
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 126static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 128static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
53c7d064 132static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 139static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
cd392f5c 143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
68d480c4 148static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
047e0030 152static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 153#ifdef CONFIG_IGB_DCA
047e0030 154static void igb_update_dca(struct igb_q_vector *);
fe4506b6 155static void igb_setup_dca(struct igb_adapter *);
421e02f0 156#endif /* CONFIG_IGB_DCA */
661086df 157static int igb_poll(struct napi_struct *, int);
13fde97a 158static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
c8f44aff 163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 166static void igb_restore_vlan(struct igb_adapter *);
26ad9178 167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
4ae196df 170static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
8151d294
WM		 179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
17dc566c 181static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 185static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 186#endif
9d5c8243 187
9d5c8243 188#ifdef CONFIG_PM
d9dd966d 189#ifdef CONFIG_PM_SLEEP
749ab2cd 190static int igb_suspend(struct device *);
d9dd966d 191#endif
749ab2cd
YZ		 192static int igb_resume(struct device *);
193#ifdef CONFIG_PM_RUNTIME
194static int igb_runtime_suspend(struct device *dev);
195static int igb_runtime_resume(struct device *dev);
196static int igb_runtime_idle(struct device *dev);
197#endif
198static const struct dev_pm_ops igb_pm_ops = {
199 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
200 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
201 igb_runtime_idle)
202};
9d5c8243
AK		 203#endif
204static void igb_shutdown(struct pci_dev *);
fa44f2f1 205static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 206#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 207static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
208static struct notifier_block dca_notifier = {
209 .notifier_call = igb_notify_dca,
210 .next = NULL,
211 .priority = 0
212};
213#endif
9d5c8243
AK		 214#ifdef CONFIG_NET_POLL_CONTROLLER
215/* for netdump / net console */
216static void igb_netpoll(struct net_device *);
217#endif
37680117 218#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 219static unsigned int max_vfs = 0;
220module_param(max_vfs, uint, 0);
221MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
222 "per physical function");
223#endif /* CONFIG_PCI_IOV */
224
9d5c8243
AK		 225static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
226 pci_channel_state_t);
227static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
228static void igb_io_resume(struct pci_dev *);
229
3646f0e5 230static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 231 .error_detected = igb_io_error_detected,
232 .slot_reset = igb_io_slot_reset,
233 .resume = igb_io_resume,
234};
235
b6e0c419 236static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 237
238static struct pci_driver igb_driver = {
239 .name = igb_driver_name,
240 .id_table = igb_pci_tbl,
241 .probe = igb_probe,
9f9a12f8 242 .remove = igb_remove,
9d5c8243 243#ifdef CONFIG_PM
749ab2cd 244 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 245#endif
246 .shutdown = igb_shutdown,
fa44f2f1 247 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 248 .err_handler = &igb_err_handler
249};
250
251MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
252MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
253MODULE_LICENSE("GPL");
254MODULE_VERSION(DRV_VERSION);
255
b3f4d599 256#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
257static int debug = -1;
258module_param(debug, int, 0);
259MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
260
c97ec42a
TI		 261struct igb_reg_info {
262 u32 ofs;
263 char *name;
264};
265
266static const struct igb_reg_info igb_reg_info_tbl[] = {
267
268 /* General Registers */
269 {E1000_CTRL, "CTRL"},
270 {E1000_STATUS, "STATUS"},
271 {E1000_CTRL_EXT, "CTRL_EXT"},
272
273 /* Interrupt Registers */
274 {E1000_ICR, "ICR"},
275
276 /* RX Registers */
277 {E1000_RCTL, "RCTL"},
278 {E1000_RDLEN(0), "RDLEN"},
279 {E1000_RDH(0), "RDH"},
280 {E1000_RDT(0), "RDT"},
281 {E1000_RXDCTL(0), "RXDCTL"},
282 {E1000_RDBAL(0), "RDBAL"},
283 {E1000_RDBAH(0), "RDBAH"},
284
285 /* TX Registers */
286 {E1000_TCTL, "TCTL"},
287 {E1000_TDBAL(0), "TDBAL"},
288 {E1000_TDBAH(0), "TDBAH"},
289 {E1000_TDLEN(0), "TDLEN"},
290 {E1000_TDH(0), "TDH"},
291 {E1000_TDT(0), "TDT"},
292 {E1000_TXDCTL(0), "TXDCTL"},
293 {E1000_TDFH, "TDFH"},
294 {E1000_TDFT, "TDFT"},
295 {E1000_TDFHS, "TDFHS"},
296 {E1000_TDFPC, "TDFPC"},
297
298 /* List Terminator */
299 {}
300};
301
b980ac18 302/* igb_regdump - register printout routine */
c97ec42a
TI		 303static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
304{
305 int n = 0;
306 char rname[16];
307 u32 regs[8];
308
309 switch (reginfo->ofs) {
310 case E1000_RDLEN(0):
311 for (n = 0; n < 4; n++)
312 regs[n] = rd32(E1000_RDLEN(n));
313 break;
314 case E1000_RDH(0):
315 for (n = 0; n < 4; n++)
316 regs[n] = rd32(E1000_RDH(n));
317 break;
318 case E1000_RDT(0):
319 for (n = 0; n < 4; n++)
320 regs[n] = rd32(E1000_RDT(n));
321 break;
322 case E1000_RXDCTL(0):
323 for (n = 0; n < 4; n++)
324 regs[n] = rd32(E1000_RXDCTL(n));
325 break;
326 case E1000_RDBAL(0):
327 for (n = 0; n < 4; n++)
328 regs[n] = rd32(E1000_RDBAL(n));
329 break;
330 case E1000_RDBAH(0):
331 for (n = 0; n < 4; n++)
332 regs[n] = rd32(E1000_RDBAH(n));
333 break;
334 case E1000_TDBAL(0):
335 for (n = 0; n < 4; n++)
336 regs[n] = rd32(E1000_RDBAL(n));
337 break;
338 case E1000_TDBAH(0):
339 for (n = 0; n < 4; n++)
340 regs[n] = rd32(E1000_TDBAH(n));
341 break;
342 case E1000_TDLEN(0):
343 for (n = 0; n < 4; n++)
344 regs[n] = rd32(E1000_TDLEN(n));
345 break;
346 case E1000_TDH(0):
347 for (n = 0; n < 4; n++)
348 regs[n] = rd32(E1000_TDH(n));
349 break;
350 case E1000_TDT(0):
351 for (n = 0; n < 4; n++)
352 regs[n] = rd32(E1000_TDT(n));
353 break;
354 case E1000_TXDCTL(0):
355 for (n = 0; n < 4; n++)
356 regs[n] = rd32(E1000_TXDCTL(n));
357 break;
358 default:
876d2d6f 359 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 360 return;
361 }
362
363 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 364 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
365 regs[2], regs[3]);
c97ec42a
TI		 366}
367
b980ac18 368/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 369static void igb_dump(struct igb_adapter *adapter)
370{
371 struct net_device *netdev = adapter->netdev;
372 struct e1000_hw *hw = &adapter->hw;
373 struct igb_reg_info *reginfo;
c97ec42a
TI		 374 struct igb_ring *tx_ring;
375 union e1000_adv_tx_desc *tx_desc;
376 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 377 struct igb_ring *rx_ring;
378 union e1000_adv_rx_desc *rx_desc;
379 u32 staterr;
6ad4edfc 380 u16 i, n;
c97ec42a
TI		 381
382 if (!netif_msg_hw(adapter))
383 return;
384
385 /* Print netdevice Info */
386 if (netdev) {
387 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 388 pr_info("Device Name state trans_start "
389 "last_rx\n");
390 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
391 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 392 }
393
394 /* Print Registers */
395 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 396 pr_info(" Register Name Value\n");
c97ec42a
TI		 397 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
398 reginfo->name; reginfo++) {
399 igb_regdump(hw, reginfo);
400 }
401
402 /* Print TX Ring Summary */
403 if (!netdev || !netif_running(netdev))
404 goto exit;
405
406 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 407 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 408 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 409 struct igb_tx_buffer *buffer_info;
c97ec42a 410 tx_ring = adapter->tx_ring[n];
06034649 411 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 412 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
413 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 414 (u64)dma_unmap_addr(buffer_info, dma),
415 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 416 buffer_info->next_to_watch,
417 (u64)buffer_info->time_stamp);
c97ec42a
TI		 418 }
419
420 /* Print TX Rings */
421 if (!netif_msg_tx_done(adapter))
422 goto rx_ring_summary;
423
424 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
425
426 /* Transmit Descriptor Formats
427 *
428 * Advanced Transmit Descriptor
429 * +--------------------------------------------------------------+
430 * 0 | Buffer Address [63:0] |
431 * +--------------------------------------------------------------+
432 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
433 * +--------------------------------------------------------------+
434 * 63 46 45 40 39 38 36 35 32 31 24 15 0
435 */
436
437 for (n = 0; n < adapter->num_tx_queues; n++) {
438 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 439 pr_info("------------------------------------\n");
440 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
441 pr_info("------------------------------------\n");
442 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
443 "[bi->dma ] leng ntw timestamp "
444 "bi->skb\n");
c97ec42a
TI		 445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 447 const char *next_desc;
06034649 448 struct igb_tx_buffer *buffer_info;
60136906 449 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 450 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 451 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 452 if (i == tx_ring->next_to_use &&
453 i == tx_ring->next_to_clean)
454 next_desc = " NTC/U";
455 else if (i == tx_ring->next_to_use)
456 next_desc = " NTU";
457 else if (i == tx_ring->next_to_clean)
458 next_desc = " NTC";
459 else
460 next_desc = "";
461
462 pr_info("T [0x%03X] %016llX %016llX %016llX"
463 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 464 le64_to_cpu(u0->a),
465 le64_to_cpu(u0->b),
c9f14bf3
AD		 466 (u64)dma_unmap_addr(buffer_info, dma),
467 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 468 buffer_info->next_to_watch,
469 (u64)buffer_info->time_stamp,
876d2d6f 470 buffer_info->skb, next_desc);
c97ec42a 471
b669588a 472 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 473 print_hex_dump(KERN_INFO, "",
474 DUMP_PREFIX_ADDRESS,
b669588a 475 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 476 dma_unmap_len(buffer_info, len),
477 true);
c97ec42a
TI		 478 }
479 }
480
481 /* Print RX Rings Summary */
482rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 484 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 487 pr_info(" %5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
497 /* Advanced Receive Descriptor (Read) Format
498 * 63 1 0
499 * +-----------------------------------------------------+
500 * 0 | Packet Buffer Address [63:1] |A0/NSE|
501 * +----------------------------------------------+------+
502 * 8 | Header Buffer Address [63:1] | DD |
503 * +-----------------------------------------------------+
504 *
505 *
506 * Advanced Receive Descriptor (Write-Back) Format
507 *
508 * 63 48 47 32 31 30 21 20 17 16 4 3 0
509 * +------------------------------------------------------+
510 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
511 * | Checksum Ident | | | | Type | Type |
512 * +------------------------------------------------------+
513 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
514 * +------------------------------------------------------+
515 * 63 48 47 32 31 20 19 0
516 */
517
518 for (n = 0; n < adapter->num_rx_queues; n++) {
519 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 520 pr_info("------------------------------------\n");
521 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
522 pr_info("------------------------------------\n");
523 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
524 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
525 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
526 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 527
528 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 529 const char *next_desc;
06034649
AD		 530 struct igb_rx_buffer *buffer_info;
531 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 532 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 533 u0 = (struct my_u0 *)rx_desc;
534 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 535
536 if (i == rx_ring->next_to_use)
537 next_desc = " NTU";
538 else if (i == rx_ring->next_to_clean)
539 next_desc = " NTC";
540 else
541 next_desc = "";
542
c97ec42a
TI		 543 if (staterr & E1000_RXD_STAT_DD) {
544 /* Descriptor Done */
1a1c225b
AD		 545 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
546 "RWB", i,
c97ec42a
TI		 547 le64_to_cpu(u0->a),
548 le64_to_cpu(u0->b),
1a1c225b 549 next_desc);
c97ec42a 550 } else {
1a1c225b
AD		 551 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
552 "R ", i,
c97ec42a
TI		 553 le64_to_cpu(u0->a),
554 le64_to_cpu(u0->b),
555 (u64)buffer_info->dma,
1a1c225b 556 next_desc);
c97ec42a 557
b669588a 558 if (netif_msg_pktdata(adapter) &&
1a1c225b 559 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 560 print_hex_dump(KERN_INFO, "",
561 DUMP_PREFIX_ADDRESS,
562 16, 1,
b669588a
ET		 563 page_address(buffer_info->page) +
564 buffer_info->page_offset,
de78d1f9 565 IGB_RX_BUFSZ, true);
c97ec42a
TI		 566 }
567 }
c97ec42a
TI		 568 }
569 }
570
571exit:
572 return;
573}
574
b980ac18
JK		 575/**
576 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 577 * @hw: pointer to hardware structure
578 * @i2cctl: Current value of I2CCTL register
579 *
580 * Returns the I2C data bit value
b980ac18 581 **/
441fc6fd
CW		 582static int igb_get_i2c_data(void *data)
583{
584 struct igb_adapter *adapter = (struct igb_adapter *)data;
585 struct e1000_hw *hw = &adapter->hw;
586 s32 i2cctl = rd32(E1000_I2CPARAMS);
587
588 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
589}
590
b980ac18
JK		 591/**
592 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 593 * @data: pointer to hardware structure
594 * @state: I2C data value (0 or 1) to set
595 *
596 * Sets the I2C data bit
b980ac18 597 **/
441fc6fd
CW		 598static void igb_set_i2c_data(void *data, int state)
599{
600 struct igb_adapter *adapter = (struct igb_adapter *)data;
601 struct e1000_hw *hw = &adapter->hw;
602 s32 i2cctl = rd32(E1000_I2CPARAMS);
603
604 if (state)
605 i2cctl |= E1000_I2C_DATA_OUT;
606 else
607 i2cctl &= ~E1000_I2C_DATA_OUT;
608
609 i2cctl &= ~E1000_I2C_DATA_OE_N;
610 i2cctl |= E1000_I2C_CLK_OE_N;
611 wr32(E1000_I2CPARAMS, i2cctl);
612 wrfl();
613
614}
615
b980ac18
JK		 616/**
617 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 618 * @data: pointer to hardware structure
619 * @state: state to set clock
620 *
621 * Sets the I2C clock line to state
b980ac18 622 **/
441fc6fd
CW		 623static void igb_set_i2c_clk(void *data, int state)
624{
625 struct igb_adapter *adapter = (struct igb_adapter *)data;
626 struct e1000_hw *hw = &adapter->hw;
627 s32 i2cctl = rd32(E1000_I2CPARAMS);
628
629 if (state) {
630 i2cctl |= E1000_I2C_CLK_OUT;
631 i2cctl &= ~E1000_I2C_CLK_OE_N;
632 } else {
633 i2cctl &= ~E1000_I2C_CLK_OUT;
634 i2cctl &= ~E1000_I2C_CLK_OE_N;
635 }
636 wr32(E1000_I2CPARAMS, i2cctl);
637 wrfl();
638}
639
b980ac18
JK		 640/**
641 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 642 * @data: pointer to hardware structure
643 *
644 * Gets the I2C clock state
b980ac18 645 **/
441fc6fd
CW		 646static int igb_get_i2c_clk(void *data)
647{
648 struct igb_adapter *adapter = (struct igb_adapter *)data;
649 struct e1000_hw *hw = &adapter->hw;
650 s32 i2cctl = rd32(E1000_I2CPARAMS);
651
652 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
653}
654
655static const struct i2c_algo_bit_data igb_i2c_algo = {
656 .setsda = igb_set_i2c_data,
657 .setscl = igb_set_i2c_clk,
658 .getsda = igb_get_i2c_data,
659 .getscl = igb_get_i2c_clk,
660 .udelay = 5,
661 .timeout = 20,
662};
663
9d5c8243 664/**
b980ac18
JK		 665 * igb_get_hw_dev - return device
666 * @hw: pointer to hardware structure
667 *
668 * used by hardware layer to print debugging information
9d5c8243 669 **/
c041076a 670struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 671{
672 struct igb_adapter *adapter = hw->back;
c041076a 673 return adapter->netdev;
9d5c8243 674}
38c845c7 675
9d5c8243 676/**
b980ac18 677 * igb_init_module - Driver Registration Routine
9d5c8243 678 *
b980ac18
JK		 679 * igb_init_module is the first routine called when the driver is
680 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 681 **/
682static int __init igb_init_module(void)
683{
684 int ret;
876d2d6f 685 pr_info("%s - version %s\n",
9d5c8243
AK		 686 igb_driver_string, igb_driver_version);
687
876d2d6f 688 pr_info("%s\n", igb_copyright);
9d5c8243 689
421e02f0 690#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 691 dca_register_notify(&dca_notifier);
692#endif
bbd98fe4 693 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 694 return ret;
695}
696
697module_init(igb_init_module);
698
699/**
b980ac18 700 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 701 *
b980ac18
JK		 702 * igb_exit_module is called just before the driver is removed
703 * from memory.
9d5c8243
AK		 704 **/
705static void __exit igb_exit_module(void)
706{
421e02f0 707#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 708 dca_unregister_notify(&dca_notifier);
709#endif
9d5c8243
AK		 710 pci_unregister_driver(&igb_driver);
711}
712
713module_exit(igb_exit_module);
714
26bc19ec
AD		 715#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
716/**
b980ac18
JK		 717 * igb_cache_ring_register - Descriptor ring to register mapping
718 * @adapter: board private structure to initialize
26bc19ec 719 *
b980ac18
JK		 720 * Once we know the feature-set enabled for the device, we'll cache
721 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 722 **/
723static void igb_cache_ring_register(struct igb_adapter *adapter)
724{
ee1b9f06 725 int i = 0, j = 0;
047e0030 726 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 727
728 switch (adapter->hw.mac.type) {
729 case e1000_82576:
730 /* The queues are allocated for virtualization such that VF 0
731 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
732 * In order to avoid collision we start at the first free queue
733 * and continue consuming queues in the same sequence
734 */
ee1b9f06 735 if (adapter->vfs_allocated_count) {
a99955fc 736 for (; i < adapter->rss_queues; i++)
3025a446 737 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 738 Q_IDX_82576(i);
ee1b9f06 739 }
26bc19ec 740 case e1000_82575:
55cac248 741 case e1000_82580:
d2ba2ed8 742 case e1000_i350:
ceb5f13b 743 case e1000_i354:
f96a8a0b
CW		 744 case e1000_i210:
745 case e1000_i211:
26bc19ec 746 default:
ee1b9f06 747 for (; i < adapter->num_rx_queues; i++)
3025a446 748 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 749 for (; j < adapter->num_tx_queues; j++)
3025a446 750 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 751 break;
752 }
753}
754
4be000c8
AD		 755/**
756 * igb_write_ivar - configure ivar for given MSI-X vector
757 * @hw: pointer to the HW structure
758 * @msix_vector: vector number we are allocating to a given ring
759 * @index: row index of IVAR register to write within IVAR table
760 * @offset: column offset of in IVAR, should be multiple of 8
761 *
762 * This function is intended to handle the writing of the IVAR register
763 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
764 * each containing an cause allocation for an Rx and Tx ring, and a
765 * variable number of rows depending on the number of queues supported.
766 **/
767static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
768 int index, int offset)
769{
770 u32 ivar = array_rd32(E1000_IVAR0, index);
771
772 /* clear any bits that are currently set */
773 ivar &= ~((u32)0xFF << offset);
774
775 /* write vector and valid bit */
776 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
777
778 array_wr32(E1000_IVAR0, index, ivar);
779}
780
9d5c8243 781#define IGB_N0_QUEUE -1
047e0030 782static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 783{
047e0030 784 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 785 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 786 int rx_queue = IGB_N0_QUEUE;
787 int tx_queue = IGB_N0_QUEUE;
4be000c8 788 u32 msixbm = 0;
047e0030 789
0ba82994
AD		 790 if (q_vector->rx.ring)
791 rx_queue = q_vector->rx.ring->reg_idx;
792 if (q_vector->tx.ring)
793 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 794
795 switch (hw->mac.type) {
796 case e1000_82575:
9d5c8243 797 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 798 * bitmask for the EICR/EIMS/EIMC registers. To assign one
799 * or more queues to a vector, we write the appropriate bits
800 * into the MSIXBM register for that vector.
801 */
047e0030 802 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 803 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 804 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 805 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 806 if (!adapter->msix_entries && msix_vector == 0)
807 msixbm |= E1000_EIMS_OTHER;
9d5c8243 808 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 809 q_vector->eims_value = msixbm;
2d064c06
AD		 810 break;
811 case e1000_82576:
b980ac18 812 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 813 * with 8 rows. The ordering is column-major so we use the
814 * lower 3 bits as the row index, and the 4th bit as the
815 * column offset.
816 */
817 if (rx_queue > IGB_N0_QUEUE)
818 igb_write_ivar(hw, msix_vector,
819 rx_queue & 0x7,
820 (rx_queue & 0x8) << 1);
821 if (tx_queue > IGB_N0_QUEUE)
822 igb_write_ivar(hw, msix_vector,
823 tx_queue & 0x7,
824 ((tx_queue & 0x8) << 1) + 8);
047e0030 825 q_vector->eims_value = 1 << msix_vector;
2d064c06 826 break;
55cac248 827 case e1000_82580:
d2ba2ed8 828 case e1000_i350:
ceb5f13b 829 case e1000_i354:
f96a8a0b
CW		 830 case e1000_i210:
831 case e1000_i211:
b980ac18 832 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 833 * however instead of ordering column-major we have things
834 * ordered row-major. So we traverse the table by using
835 * bit 0 as the column offset, and the remaining bits as the
836 * row index.
837 */
838 if (rx_queue > IGB_N0_QUEUE)
839 igb_write_ivar(hw, msix_vector,
840 rx_queue >> 1,
841 (rx_queue & 0x1) << 4);
842 if (tx_queue > IGB_N0_QUEUE)
843 igb_write_ivar(hw, msix_vector,
844 tx_queue >> 1,
845 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 846 q_vector->eims_value = 1 << msix_vector;
847 break;
2d064c06
AD		 848 default:
849 BUG();
850 break;
851 }
26b39276
AD		 852
853 /* add q_vector eims value to global eims_enable_mask */
854 adapter->eims_enable_mask |= q_vector->eims_value;
855
856 /* configure q_vector to set itr on first interrupt */
857 q_vector->set_itr = 1;
9d5c8243
AK		 858}
859
860/**
b980ac18
JK		 861 * igb_configure_msix - Configure MSI-X hardware
862 * @adapter: board private structure to initialize
9d5c8243 863 *
b980ac18
JK		 864 * igb_configure_msix sets up the hardware to properly
865 * generate MSI-X interrupts.
9d5c8243
AK		 866 **/
867static void igb_configure_msix(struct igb_adapter *adapter)
868{
869 u32 tmp;
870 int i, vector = 0;
871 struct e1000_hw *hw = &adapter->hw;
872
873 adapter->eims_enable_mask = 0;
9d5c8243
AK		 874
875 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 876 switch (hw->mac.type) {
877 case e1000_82575:
9d5c8243
AK		 878 tmp = rd32(E1000_CTRL_EXT);
879 /* enable MSI-X PBA support*/
880 tmp |= E1000_CTRL_EXT_PBA_CLR;
881
882 /* Auto-Mask interrupts upon ICR read. */
883 tmp |= E1000_CTRL_EXT_EIAME;
884 tmp |= E1000_CTRL_EXT_IRCA;
885
886 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 887
888 /* enable msix_other interrupt */
b980ac18 889 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 890 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 891
2d064c06
AD		 892 break;
893
894 case e1000_82576:
55cac248 895 case e1000_82580:
d2ba2ed8 896 case e1000_i350:
ceb5f13b 897 case e1000_i354:
f96a8a0b
CW		 898 case e1000_i210:
899 case e1000_i211:
047e0030 900 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 901 * won't stick. And it will take days to debug.
902 */
047e0030 903 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 904 E1000_GPIE_PBA | E1000_GPIE_EIAME |
905 E1000_GPIE_NSICR);
047e0030
AD		 906
907 /* enable msix_other interrupt */
908 adapter->eims_other = 1 << vector;
2d064c06 909 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 910
047e0030 911 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 912 break;
913 default:
914 /* do nothing, since nothing else supports MSI-X */
915 break;
916 } /* switch (hw->mac.type) */
047e0030
AD		 917
918 adapter->eims_enable_mask |= adapter->eims_other;
919
26b39276
AD		 920 for (i = 0; i < adapter->num_q_vectors; i++)
921 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 922
9d5c8243
AK		 923 wrfl();
924}
925
926/**
b980ac18
JK		 927 * igb_request_msix - Initialize MSI-X interrupts
928 * @adapter: board private structure to initialize
9d5c8243 929 *
b980ac18
JK		 930 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
931 * kernel.
9d5c8243
AK		 932 **/
933static int igb_request_msix(struct igb_adapter *adapter)
934{
935 struct net_device *netdev = adapter->netdev;
047e0030 936 struct e1000_hw *hw = &adapter->hw;
52285b76 937 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 938
047e0030 939 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 940 igb_msix_other, 0, netdev->name, adapter);
047e0030 941 if (err)
52285b76 942 goto err_out;
047e0030
AD		 943
944 for (i = 0; i < adapter->num_q_vectors; i++) {
945 struct igb_q_vector *q_vector = adapter->q_vector[i];
946
52285b76
SA		 947 vector++;
948
047e0030
AD		 949 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
950
0ba82994 951 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 952 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 953 q_vector->rx.ring->queue_index);
954 else if (q_vector->tx.ring)
047e0030 955 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 956 q_vector->tx.ring->queue_index);
957 else if (q_vector->rx.ring)
047e0030 958 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 959 q_vector->rx.ring->queue_index);
9d5c8243 960 else
047e0030
AD		 961 sprintf(q_vector->name, "%s-unused", netdev->name);
962
9d5c8243 963 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 964 igb_msix_ring, 0, q_vector->name,
965 q_vector);
9d5c8243 966 if (err)
52285b76 967 goto err_free;
9d5c8243
AK		 968 }
969
9d5c8243
AK		 970 igb_configure_msix(adapter);
971 return 0;
52285b76
SA		 972
973err_free:
974 /* free already assigned IRQs */
975 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
976
977 vector--;
978 for (i = 0; i < vector; i++) {
979 free_irq(adapter->msix_entries[free_vector++].vector,
980 adapter->q_vector[i]);
981 }
982err_out:
9d5c8243
AK		 983 return err;
984}
985
986static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
987{
988 if (adapter->msix_entries) {
989 pci_disable_msix(adapter->pdev);
990 kfree(adapter->msix_entries);
991 adapter->msix_entries = NULL;
047e0030 992 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 993 pci_disable_msi(adapter->pdev);
047e0030 994 }
9d5c8243
AK		 995}
996
5536d210 997/**
b980ac18
JK		 998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
5536d210 1001 *
b980ac18
JK		 1002 * This function frees the memory allocated to the q_vector. In addition if
1003 * NAPI is enabled it will delete any references to the NAPI struct prior
1004 * to freeing the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
1010 if (q_vector->tx.ring)
1011 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1012
1013 if (q_vector->rx.ring)
1014 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1015
1016 adapter->q_vector[v_idx] = NULL;
1017 netif_napi_del(&q_vector->napi);
1018
7f90128e 1019 /* igb_get_stats64() might access the rings on this vector,
5536d210
AD		 1020 * we must wait a grace period before freeing it.
1021 */
1022 kfree_rcu(q_vector, rcu);
1023}
1024
047e0030 1025/**
b980ac18
JK		 1026 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1027 * @adapter: board private structure to initialize
047e0030 1028 *
b980ac18
JK		 1029 * This function frees the memory allocated to the q_vectors. In addition if
1030 * NAPI is enabled it will delete any references to the NAPI struct prior
1031 * to freeing the q_vector.
047e0030
AD		 1032 **/
1033static void igb_free_q_vectors(struct igb_adapter *adapter)
1034{
5536d210
AD		 1035 int v_idx = adapter->num_q_vectors;
1036
1037 adapter->num_tx_queues = 0;
1038 adapter->num_rx_queues = 0;
047e0030 1039 adapter->num_q_vectors = 0;
5536d210
AD		 1040
1041 while (v_idx--)
1042 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1043}
1044
1045/**
b980ac18
JK		 1046 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1047 * @adapter: board private structure to initialize
047e0030 1048 *
b980ac18
JK		 1049 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1050 * MSI-X interrupts allocated.
047e0030
AD		 1051 */
1052static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1053{
047e0030
AD		 1054 igb_free_q_vectors(adapter);
1055 igb_reset_interrupt_capability(adapter);
1056}
9d5c8243
AK		 1057
1058/**
b980ac18
JK		 1059 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1060 * @adapter: board private structure to initialize
1061 * @msix: boolean value of MSIX capability
9d5c8243 1062 *
b980ac18
JK		 1063 * Attempt to configure interrupts using the best available
1064 * capabilities of the hardware and kernel.
9d5c8243 1065 **/
53c7d064 1066static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1067{
1068 int err;
1069 int numvecs, i;
1070
53c7d064
SA		 1071 if (!msix)
1072 goto msi_only;
1073
83b7180d 1074 /* Number of supported queues. */
a99955fc 1075 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1076 if (adapter->vfs_allocated_count)
1077 adapter->num_tx_queues = 1;
1078 else
1079 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1080
b980ac18 1081 /* start with one vector for every Rx queue */
047e0030
AD		 1082 numvecs = adapter->num_rx_queues;
1083
b980ac18 1084 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1085 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1086 numvecs += adapter->num_tx_queues;
047e0030
AD		 1087
1088 /* store the number of vectors reserved for queues */
1089 adapter->num_q_vectors = numvecs;
1090
1091 /* add 1 vector for link status interrupts */
1092 numvecs++;
9d5c8243
AK		 1093 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1094 GFP_KERNEL);
f96a8a0b 1095
9d5c8243
AK		 1096 if (!adapter->msix_entries)
1097 goto msi_only;
1098
1099 for (i = 0; i < numvecs; i++)
1100 adapter->msix_entries[i].entry = i;
1101
1102 err = pci_enable_msix(adapter->pdev,
1103 adapter->msix_entries,
1104 numvecs);
1105 if (err == 0)
0c2cc02e 1106 return;
9d5c8243
AK		 1107
1108 igb_reset_interrupt_capability(adapter);
1109
1110 /* If we can't do MSI-X, try MSI */
1111msi_only:
2a3abf6d
AD		 1112#ifdef CONFIG_PCI_IOV
1113 /* disable SR-IOV for non MSI-X configurations */
1114 if (adapter->vf_data) {
1115 struct e1000_hw *hw = &adapter->hw;
1116 /* disable iov and allow time for transactions to clear */
1117 pci_disable_sriov(adapter->pdev);
1118 msleep(500);
1119
1120 kfree(adapter->vf_data);
1121 adapter->vf_data = NULL;
1122 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1123 wrfl();
2a3abf6d
AD		 1124 msleep(100);
1125 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1126 }
1127#endif
4fc82adf 1128 adapter->vfs_allocated_count = 0;
a99955fc 1129 adapter->rss_queues = 1;
4fc82adf 1130 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1131 adapter->num_rx_queues = 1;
661086df 1132 adapter->num_tx_queues = 1;
047e0030 1133 adapter->num_q_vectors = 1;
9d5c8243 1134 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1135 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1136}
1137
5536d210
AD		 1138static void igb_add_ring(struct igb_ring *ring,
1139 struct igb_ring_container *head)
1140{
1141 head->ring = ring;
1142 head->count++;
1143}
1144
047e0030 1145/**
b980ac18
JK		 1146 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1147 * @adapter: board private structure to initialize
1148 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1149 * @v_idx: index of vector in adapter struct
1150 * @txr_count: total number of Tx rings to allocate
1151 * @txr_idx: index of first Tx ring to allocate
1152 * @rxr_count: total number of Rx rings to allocate
1153 * @rxr_idx: index of first Rx ring to allocate
047e0030 1154 *
b980ac18 1155 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1156 **/
5536d210
AD		 1157static int igb_alloc_q_vector(struct igb_adapter *adapter,
1158 int v_count, int v_idx,
1159 int txr_count, int txr_idx,
1160 int rxr_count, int rxr_idx)
047e0030
AD		 1161{
1162 struct igb_q_vector *q_vector;
5536d210
AD		 1163 struct igb_ring *ring;
1164 int ring_count, size;
047e0030 1165
5536d210
AD		 1166 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1167 if (txr_count > 1 || rxr_count > 1)
1168 return -ENOMEM;
1169
1170 ring_count = txr_count + rxr_count;
1171 size = sizeof(struct igb_q_vector) +
1172 (sizeof(struct igb_ring) * ring_count);
1173
1174 /* allocate q_vector and rings */
1175 q_vector = kzalloc(size, GFP_KERNEL);
1176 if (!q_vector)
1177 return -ENOMEM;
1178
1179 /* initialize NAPI */
1180 netif_napi_add(adapter->netdev, &q_vector->napi,
1181 igb_poll, 64);
1182
1183 /* tie q_vector and adapter together */
1184 adapter->q_vector[v_idx] = q_vector;
1185 q_vector->adapter = adapter;
1186
1187 /* initialize work limits */
1188 q_vector->tx.work_limit = adapter->tx_work_limit;
1189
1190 /* initialize ITR configuration */
1191 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1192 q_vector->itr_val = IGB_START_ITR;
1193
1194 /* initialize pointer to rings */
1195 ring = q_vector->ring;
1196
4e227667
AD		 1197 /* intialize ITR */
1198 if (rxr_count) {
1199 /* rx or rx/tx vector */
1200 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1201 q_vector->itr_val = adapter->rx_itr_setting;
1202 } else {
1203 /* tx only vector */
1204 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1205 q_vector->itr_val = adapter->tx_itr_setting;
1206 }
1207
5536d210
AD		 1208 if (txr_count) {
1209 /* assign generic ring traits */
1210 ring->dev = &adapter->pdev->dev;
1211 ring->netdev = adapter->netdev;
1212
1213 /* configure backlink on ring */
1214 ring->q_vector = q_vector;
1215
1216 /* update q_vector Tx values */
1217 igb_add_ring(ring, &q_vector->tx);
1218
1219 /* For 82575, context index must be unique per ring. */
1220 if (adapter->hw.mac.type == e1000_82575)
1221 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1222
1223 /* apply Tx specific ring traits */
1224 ring->count = adapter->tx_ring_count;
1225 ring->queue_index = txr_idx;
1226
827da44c
JS		 1227 u64_stats_init(&ring->tx_syncp);
1228 u64_stats_init(&ring->tx_syncp2);
1229
5536d210
AD		 1230 /* assign ring to adapter */
1231 adapter->tx_ring[txr_idx] = ring;
1232
1233 /* push pointer to next ring */
1234 ring++;
047e0030 1235 }
81c2fc22 1236
5536d210
AD		 1237 if (rxr_count) {
1238 /* assign generic ring traits */
1239 ring->dev = &adapter->pdev->dev;
1240 ring->netdev = adapter->netdev;
047e0030 1241
5536d210
AD		 1242 /* configure backlink on ring */
1243 ring->q_vector = q_vector;
047e0030 1244
5536d210
AD		 1245 /* update q_vector Rx values */
1246 igb_add_ring(ring, &q_vector->rx);
047e0030 1247
5536d210
AD		 1248 /* set flag indicating ring supports SCTP checksum offload */
1249 if (adapter->hw.mac.type >= e1000_82576)
1250 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1251
ceb5f13b
CW		 1252 /*
1253 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1254 * have the tag byte-swapped.
b980ac18 1255 */
5536d210
AD		 1256 if (adapter->hw.mac.type >= e1000_i350)
1257 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1258
5536d210
AD		 1259 /* apply Rx specific ring traits */
1260 ring->count = adapter->rx_ring_count;
1261 ring->queue_index = rxr_idx;
1262
827da44c
JS		 1263 u64_stats_init(&ring->rx_syncp);
1264
5536d210
AD		 1265 /* assign ring to adapter */
1266 adapter->rx_ring[rxr_idx] = ring;
1267 }
1268
1269 return 0;
047e0030
AD		 1270}
1271
5536d210 1272
047e0030 1273/**
b980ac18
JK		 1274 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1275 * @adapter: board private structure to initialize
047e0030 1276 *
b980ac18
JK		 1277 * We allocate one q_vector per queue interrupt. If allocation fails we
1278 * return -ENOMEM.
047e0030 1279 **/
5536d210 1280static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1281{
5536d210
AD		 1282 int q_vectors = adapter->num_q_vectors;
1283 int rxr_remaining = adapter->num_rx_queues;
1284 int txr_remaining = adapter->num_tx_queues;
1285 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1286 int err;
047e0030 1287
5536d210
AD		 1288 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1289 for (; rxr_remaining; v_idx++) {
1290 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1291 0, 0, 1, rxr_idx);
047e0030 1292
5536d210
AD		 1293 if (err)
1294 goto err_out;
1295
1296 /* update counts and index */
1297 rxr_remaining--;
1298 rxr_idx++;
047e0030 1299 }
047e0030 1300 }
5536d210
AD		 1301
1302 for (; v_idx < q_vectors; v_idx++) {
1303 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1304 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1305 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1306 tqpv, txr_idx, rqpv, rxr_idx);
1307
1308 if (err)
1309 goto err_out;
1310
1311 /* update counts and index */
1312 rxr_remaining -= rqpv;
1313 txr_remaining -= tqpv;
1314 rxr_idx++;
1315 txr_idx++;
1316 }
1317
047e0030 1318 return 0;
5536d210
AD		 1319
1320err_out:
1321 adapter->num_tx_queues = 0;
1322 adapter->num_rx_queues = 0;
1323 adapter->num_q_vectors = 0;
1324
1325 while (v_idx--)
1326 igb_free_q_vector(adapter, v_idx);
1327
1328 return -ENOMEM;
047e0030
AD		 1329}
1330
1331/**
b980ac18
JK		 1332 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1333 * @adapter: board private structure to initialize
1334 * @msix: boolean value of MSIX capability
047e0030 1335 *
b980ac18 1336 * This function initializes the interrupts and allocates all of the queues.
047e0030 1337 **/
53c7d064 1338static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1339{
1340 struct pci_dev *pdev = adapter->pdev;
1341 int err;
1342
53c7d064 1343 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1344
1345 err = igb_alloc_q_vectors(adapter);
1346 if (err) {
1347 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1348 goto err_alloc_q_vectors;
1349 }
1350
5536d210 1351 igb_cache_ring_register(adapter);
047e0030
AD		 1352
1353 return 0;
5536d210 1354
047e0030
AD		 1355err_alloc_q_vectors:
1356 igb_reset_interrupt_capability(adapter);
1357 return err;
1358}
1359
9d5c8243 1360/**
b980ac18
JK		 1361 * igb_request_irq - initialize interrupts
1362 * @adapter: board private structure to initialize
9d5c8243 1363 *
b980ac18
JK		 1364 * Attempts to configure interrupts using the best available
1365 * capabilities of the hardware and kernel.
9d5c8243
AK		 1366 **/
1367static int igb_request_irq(struct igb_adapter *adapter)
1368{
1369 struct net_device *netdev = adapter->netdev;
047e0030 1370 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1371 int err = 0;
1372
1373 if (adapter->msix_entries) {
1374 err = igb_request_msix(adapter);
844290e5 1375 if (!err)
9d5c8243 1376 goto request_done;
9d5c8243 1377 /* fall back to MSI */
5536d210
AD		 1378 igb_free_all_tx_resources(adapter);
1379 igb_free_all_rx_resources(adapter);
53c7d064 1380
047e0030 1381 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1382 err = igb_init_interrupt_scheme(adapter, false);
1383 if (err)
047e0030 1384 goto request_done;
53c7d064 1385
047e0030
AD		 1386 igb_setup_all_tx_resources(adapter);
1387 igb_setup_all_rx_resources(adapter);
53c7d064 1388 igb_configure(adapter);
9d5c8243 1389 }
844290e5 1390
c74d588e
AD		 1391 igb_assign_vector(adapter->q_vector[0], 0);
1392
7dfc16fa 1393 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1394 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1395 netdev->name, adapter);
9d5c8243
AK		 1396 if (!err)
1397 goto request_done;
047e0030 1398
9d5c8243
AK		 1399 /* fall back to legacy interrupts */
1400 igb_reset_interrupt_capability(adapter);
7dfc16fa 1401 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1402 }
1403
c74d588e 1404 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1405 netdev->name, adapter);
9d5c8243 1406
6cb5e577 1407 if (err)
c74d588e 1408 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1409 err);
9d5c8243
AK		 1410
1411request_done:
1412 return err;
1413}
1414
1415static void igb_free_irq(struct igb_adapter *adapter)
1416{
9d5c8243
AK		 1417 if (adapter->msix_entries) {
1418 int vector = 0, i;
1419
047e0030 1420 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1421
0d1ae7f4 1422 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1423 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1424 adapter->q_vector[i]);
047e0030
AD		 1425 } else {
1426 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1427 }
9d5c8243
AK		 1428}
1429
1430/**
b980ac18
JK		 1431 * igb_irq_disable - Mask off interrupt generation on the NIC
1432 * @adapter: board private structure
9d5c8243
AK		 1433 **/
1434static void igb_irq_disable(struct igb_adapter *adapter)
1435{
1436 struct e1000_hw *hw = &adapter->hw;
1437
b980ac18 1438 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1439 * mapped into these registers and so clearing the bits can cause
1440 * issues on the VF drivers so we only need to clear what we set
1441 */
9d5c8243 1442 if (adapter->msix_entries) {
2dfd1212
AD		 1443 u32 regval = rd32(E1000_EIAM);
1444 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1445 wr32(E1000_EIMC, adapter->eims_enable_mask);
1446 regval = rd32(E1000_EIAC);
1447 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1448 }
844290e5
PW		 1449
1450 wr32(E1000_IAM, 0);
9d5c8243
AK		 1451 wr32(E1000_IMC, ~0);
1452 wrfl();
81a61859
ET		 1453 if (adapter->msix_entries) {
1454 int i;
1455 for (i = 0; i < adapter->num_q_vectors; i++)
1456 synchronize_irq(adapter->msix_entries[i].vector);
1457 } else {
1458 synchronize_irq(adapter->pdev->irq);
1459 }
9d5c8243
AK		 1460}
1461
1462/**
b980ac18
JK		 1463 * igb_irq_enable - Enable default interrupt generation settings
1464 * @adapter: board private structure
9d5c8243
AK		 1465 **/
1466static void igb_irq_enable(struct igb_adapter *adapter)
1467{
1468 struct e1000_hw *hw = &adapter->hw;
1469
1470 if (adapter->msix_entries) {
06218a8d 1471 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1472 u32 regval = rd32(E1000_EIAC);
1473 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1474 regval = rd32(E1000_EIAM);
1475 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1476 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1477 if (adapter->vfs_allocated_count) {
4ae196df 1478 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1479 ims |= E1000_IMS_VMMB;
1480 }
1481 wr32(E1000_IMS, ims);
844290e5 1482 } else {
55cac248
AD		 1483 wr32(E1000_IMS, IMS_ENABLE_MASK |
1484 E1000_IMS_DRSTA);
1485 wr32(E1000_IAM, IMS_ENABLE_MASK |
1486 E1000_IMS_DRSTA);
844290e5 1487 }
9d5c8243
AK		 1488}
1489
1490static void igb_update_mng_vlan(struct igb_adapter *adapter)
1491{
51466239 1492 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1493 u16 vid = adapter->hw.mng_cookie.vlan_id;
1494 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1495
1496 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1497 /* add VID to filter table */
1498 igb_vfta_set(hw, vid, true);
1499 adapter->mng_vlan_id = vid;
1500 } else {
1501 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1502 }
1503
1504 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1505 (vid != old_vid) &&
b2cb09b1 1506 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1507 /* remove VID from filter table */
1508 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1509 }
1510}
1511
1512/**
b980ac18
JK		 1513 * igb_release_hw_control - release control of the h/w to f/w
1514 * @adapter: address of board private structure
9d5c8243 1515 *
b980ac18
JK		 1516 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1517 * For ASF and Pass Through versions of f/w this means that the
1518 * driver is no longer loaded.
9d5c8243
AK		 1519 **/
1520static void igb_release_hw_control(struct igb_adapter *adapter)
1521{
1522 struct e1000_hw *hw = &adapter->hw;
1523 u32 ctrl_ext;
1524
1525 /* Let firmware take over control of h/w */
1526 ctrl_ext = rd32(E1000_CTRL_EXT);
1527 wr32(E1000_CTRL_EXT,
1528 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1529}
1530
9d5c8243 1531/**
b980ac18
JK		 1532 * igb_get_hw_control - get control of the h/w from f/w
1533 * @adapter: address of board private structure
9d5c8243 1534 *
b980ac18
JK		 1535 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1536 * For ASF and Pass Through versions of f/w this means that
1537 * the driver is loaded.
9d5c8243
AK		 1538 **/
1539static void igb_get_hw_control(struct igb_adapter *adapter)
1540{
1541 struct e1000_hw *hw = &adapter->hw;
1542 u32 ctrl_ext;
1543
1544 /* Let firmware know the driver has taken over */
1545 ctrl_ext = rd32(E1000_CTRL_EXT);
1546 wr32(E1000_CTRL_EXT,
1547 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1548}
1549
9d5c8243 1550/**
b980ac18
JK		 1551 * igb_configure - configure the hardware for RX and TX
1552 * @adapter: private board structure
9d5c8243
AK		 1553 **/
1554static void igb_configure(struct igb_adapter *adapter)
1555{
1556 struct net_device *netdev = adapter->netdev;
1557 int i;
1558
1559 igb_get_hw_control(adapter);
ff41f8dc 1560 igb_set_rx_mode(netdev);
9d5c8243
AK		 1561
1562 igb_restore_vlan(adapter);
9d5c8243 1563
85b430b4 1564 igb_setup_tctl(adapter);
06cf2666 1565 igb_setup_mrqc(adapter);
9d5c8243 1566 igb_setup_rctl(adapter);
85b430b4
AD		 1567
1568 igb_configure_tx(adapter);
9d5c8243 1569 igb_configure_rx(adapter);
662d7205
AD		 1570
1571 igb_rx_fifo_flush_82575(&adapter->hw);
1572
c493ea45 1573 /* call igb_desc_unused which always leaves
9d5c8243 1574 * at least 1 descriptor unused to make sure
b980ac18
JK		 1575 * next_to_use != next_to_clean
1576 */
9d5c8243 1577 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1578 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1579 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1580 }
9d5c8243
AK		 1581}
1582
88a268c1 1583/**
b980ac18
JK		 1584 * igb_power_up_link - Power up the phy/serdes link
1585 * @adapter: address of board private structure
88a268c1
NN		 1586 **/
1587void igb_power_up_link(struct igb_adapter *adapter)
1588{
76886596
AA		 1589 igb_reset_phy(&adapter->hw);
1590
88a268c1
NN		 1591 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1592 igb_power_up_phy_copper(&adapter->hw);
1593 else
1594 igb_power_up_serdes_link_82575(&adapter->hw);
1595}
1596
1597/**
b980ac18
JK		 1598 * igb_power_down_link - Power down the phy/serdes link
1599 * @adapter: address of board private structure
88a268c1
NN		 1600 */
1601static void igb_power_down_link(struct igb_adapter *adapter)
1602{
1603 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1604 igb_power_down_phy_copper_82575(&adapter->hw);
1605 else
1606 igb_shutdown_serdes_link_82575(&adapter->hw);
1607}
9d5c8243
AK		 1608
1609/**
b980ac18
JK		 1610 * igb_up - Open the interface and prepare it to handle traffic
1611 * @adapter: board private structure
9d5c8243 1612 **/
9d5c8243
AK		 1613int igb_up(struct igb_adapter *adapter)
1614{
1615 struct e1000_hw *hw = &adapter->hw;
1616 int i;
1617
1618 /* hardware has been reset, we need to reload some things */
1619 igb_configure(adapter);
1620
1621 clear_bit(__IGB_DOWN, &adapter->state);
1622
0d1ae7f4
AD		 1623 for (i = 0; i < adapter->num_q_vectors; i++)
1624 napi_enable(&(adapter->q_vector[i]->napi));
1625
844290e5 1626 if (adapter->msix_entries)
9d5c8243 1627 igb_configure_msix(adapter);
feeb2721
AD		 1628 else
1629 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1630
1631 /* Clear any pending interrupts. */
1632 rd32(E1000_ICR);
1633 igb_irq_enable(adapter);
1634
d4960307
AD		 1635 /* notify VFs that reset has been completed */
1636 if (adapter->vfs_allocated_count) {
1637 u32 reg_data = rd32(E1000_CTRL_EXT);
1638 reg_data |= E1000_CTRL_EXT_PFRSTD;
1639 wr32(E1000_CTRL_EXT, reg_data);
1640 }
1641
4cb9be7a
JB		 1642 netif_tx_start_all_queues(adapter->netdev);
1643
25568a53
AD		 1644 /* start the watchdog. */
1645 hw->mac.get_link_status = 1;
1646 schedule_work(&adapter->watchdog_task);
1647
9d5c8243
AK		 1648 return 0;
1649}
1650
1651void igb_down(struct igb_adapter *adapter)
1652{
9d5c8243 1653 struct net_device *netdev = adapter->netdev;
330a6d6a 1654 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1655 u32 tctl, rctl;
1656 int i;
1657
1658 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1659 * reschedule our watchdog timer
1660 */
9d5c8243
AK		 1661 set_bit(__IGB_DOWN, &adapter->state);
1662
1663 /* disable receives in the hardware */
1664 rctl = rd32(E1000_RCTL);
1665 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1666 /* flush and sleep below */
1667
fd2ea0a7 1668 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1669
1670 /* disable transmits in the hardware */
1671 tctl = rd32(E1000_TCTL);
1672 tctl &= ~E1000_TCTL_EN;
1673 wr32(E1000_TCTL, tctl);
1674 /* flush both disables and wait for them to finish */
1675 wrfl();
1676 msleep(10);
1677
41f149a2
CW		 1678 igb_irq_disable(adapter);
1679
aa9b8cc4
AA		 1680 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1681
41f149a2
CW		 1682 for (i = 0; i < adapter->num_q_vectors; i++) {
1683 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1684 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1685 }
9d5c8243 1686
9d5c8243
AK		 1687
1688 del_timer_sync(&adapter->watchdog_timer);
1689 del_timer_sync(&adapter->phy_info_timer);
1690
9d5c8243 1691 netif_carrier_off(netdev);
04fe6358
AD		 1692
1693 /* record the stats before reset*/
12dcd86b
ED		 1694 spin_lock(&adapter->stats64_lock);
1695 igb_update_stats(adapter, &adapter->stats64);
1696 spin_unlock(&adapter->stats64_lock);
04fe6358 1697
9d5c8243
AK		 1698 adapter->link_speed = 0;
1699 adapter->link_duplex = 0;
1700
3023682e
JK		 1701 if (!pci_channel_offline(adapter->pdev))
1702 igb_reset(adapter);
9d5c8243
AK		 1703 igb_clean_all_tx_rings(adapter);
1704 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1705#ifdef CONFIG_IGB_DCA
1706
1707 /* since we reset the hardware DCA settings were cleared */
1708 igb_setup_dca(adapter);
1709#endif
9d5c8243
AK		 1710}
1711
1712void igb_reinit_locked(struct igb_adapter *adapter)
1713{
1714 WARN_ON(in_interrupt());
1715 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1716 msleep(1);
1717 igb_down(adapter);
1718 igb_up(adapter);
1719 clear_bit(__IGB_RESETTING, &adapter->state);
1720}
1721
1722void igb_reset(struct igb_adapter *adapter)
1723{
090b1795 1724 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1725 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1726 struct e1000_mac_info *mac = &hw->mac;
1727 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1728 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1729
1730 /* Repartition Pba for greater than 9k mtu
1731 * To take effect CTRL.RST is required.
1732 */
fa4dfae0 1733 switch (mac->type) {
d2ba2ed8 1734 case e1000_i350:
ceb5f13b 1735 case e1000_i354:
55cac248
AD		 1736 case e1000_82580:
1737 pba = rd32(E1000_RXPBS);
1738 pba = igb_rxpbs_adjust_82580(pba);
1739 break;
fa4dfae0 1740 case e1000_82576:
d249be54
AD		 1741 pba = rd32(E1000_RXPBS);
1742 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1743 break;
1744 case e1000_82575:
f96a8a0b
CW		 1745 case e1000_i210:
1746 case e1000_i211:
fa4dfae0
AD		 1747 default:
1748 pba = E1000_PBA_34K;
1749 break;
2d064c06 1750 }
9d5c8243 1751
2d064c06
AD		 1752 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1753 (mac->type < e1000_82576)) {
9d5c8243
AK		 1754 /* adjust PBA for jumbo frames */
1755 wr32(E1000_PBA, pba);
1756
1757 /* To maintain wire speed transmits, the Tx FIFO should be
1758 * large enough to accommodate two full transmit packets,
1759 * rounded up to the next 1KB and expressed in KB. Likewise,
1760 * the Rx FIFO should be large enough to accommodate at least
1761 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1762 * expressed in KB.
1763 */
9d5c8243
AK		 1764 pba = rd32(E1000_PBA);
1765 /* upper 16 bits has Tx packet buffer allocation size in KB */
1766 tx_space = pba >> 16;
1767 /* lower 16 bits has Rx packet buffer allocation size in KB */
1768 pba &= 0xffff;
b980ac18
JK		 1769 /* the Tx fifo also stores 16 bytes of information about the Tx
1770 * but don't include ethernet FCS because hardware appends it
1771 */
9d5c8243 1772 min_tx_space = (adapter->max_frame_size +
85e8d004 1773 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1774 ETH_FCS_LEN) * 2;
1775 min_tx_space = ALIGN(min_tx_space, 1024);
1776 min_tx_space >>= 10;
1777 /* software strips receive CRC, so leave room for it */
1778 min_rx_space = adapter->max_frame_size;
1779 min_rx_space = ALIGN(min_rx_space, 1024);
1780 min_rx_space >>= 10;
1781
1782 /* If current Tx allocation is less than the min Tx FIFO size,
1783 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1784 * allocation, take space away from current Rx allocation
1785 */
9d5c8243
AK		 1786 if (tx_space < min_tx_space &&
1787 ((min_tx_space - tx_space) < pba)) {
1788 pba = pba - (min_tx_space - tx_space);
1789
b980ac18
JK		 1790 /* if short on Rx space, Rx wins and must trump Tx
1791 * adjustment
1792 */
9d5c8243
AK		 1793 if (pba < min_rx_space)
1794 pba = min_rx_space;
1795 }
2d064c06 1796 wr32(E1000_PBA, pba);
9d5c8243 1797 }
9d5c8243
AK		 1798
1799 /* flow control settings */
1800 /* The high water mark must be low enough to fit one full frame
1801 * (or the size used for early receive) above it in the Rx FIFO.
1802 * Set it to the lower of:
1803 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1804 * - the full Rx FIFO size minus one full frame
1805 */
9d5c8243 1806 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1807 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1808
d48507fe 1809 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1810 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1811 fc->pause_time = 0xFFFF;
1812 fc->send_xon = 1;
0cce119a 1813 fc->current_mode = fc->requested_mode;
9d5c8243 1814
4ae196df
AD		 1815 /* disable receive for all VFs and wait one second */
1816 if (adapter->vfs_allocated_count) {
1817 int i;
1818 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1819 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1820
1821 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1822 igb_ping_all_vfs(adapter);
4ae196df
AD		 1823
1824 /* disable transmits and receives */
1825 wr32(E1000_VFRE, 0);
1826 wr32(E1000_VFTE, 0);
1827 }
1828
9d5c8243 1829 /* Allow time for pending master requests to run */
330a6d6a 1830 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1831 wr32(E1000_WUC, 0);
1832
330a6d6a 1833 if (hw->mac.ops.init_hw(hw))
090b1795 1834 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1835
b980ac18 1836 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1837 * control is off when forcing speed.
1838 */
1839 if (!hw->mac.autoneg)
1840 igb_force_mac_fc(hw);
1841
b6e0c419 1842 igb_init_dmac(adapter, pba);
e428893b
CW		 1843#ifdef CONFIG_IGB_HWMON
1844 /* Re-initialize the thermal sensor on i350 devices. */
1845 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1846 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1847 /* If present, re-initialize the external thermal sensor
1848 * interface.
1849 */
1850 if (adapter->ets)
1851 mac->ops.init_thermal_sensor_thresh(hw);
1852 }
1853 }
1854#endif
88a268c1
NN		 1855 if (!netif_running(adapter->netdev))
1856 igb_power_down_link(adapter);
1857
9d5c8243
AK		 1858 igb_update_mng_vlan(adapter);
1859
1860 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1861 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1862
1f6e8178
MV		 1863 /* Re-enable PTP, where applicable. */
1864 igb_ptp_reset(adapter);
1f6e8178 1865
330a6d6a 1866 igb_get_phy_info(hw);
9d5c8243
AK		 1867}
1868
c8f44aff
MM		 1869static netdev_features_t igb_fix_features(struct net_device *netdev,
1870 netdev_features_t features)
b2cb09b1 1871{
b980ac18
JK		 1872 /* Since there is no support for separate Rx/Tx vlan accel
1873 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1874 */
f646968f
PM		 1875 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1876 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1877 else
f646968f 1878 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1879
1880 return features;
1881}
1882
c8f44aff
MM		 1883static int igb_set_features(struct net_device *netdev,
1884 netdev_features_t features)
ac52caa3 1885{
c8f44aff 1886 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1887 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1888
f646968f 1889 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1890 igb_vlan_mode(netdev, features);
1891
89eaefb6
BG		 1892 if (!(changed & NETIF_F_RXALL))
1893 return 0;
1894
1895 netdev->features = features;
1896
1897 if (netif_running(netdev))
1898 igb_reinit_locked(adapter);
1899 else
1900 igb_reset(adapter);
1901
ac52caa3
MM		 1902 return 0;
1903}
1904
2e5c6922 1905static const struct net_device_ops igb_netdev_ops = {
559e9c49 1906 .ndo_open = igb_open,
2e5c6922 1907 .ndo_stop = igb_close,
cd392f5c 1908 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1909 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1910 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1911 .ndo_set_mac_address = igb_set_mac,
1912 .ndo_change_mtu = igb_change_mtu,
1913 .ndo_do_ioctl = igb_ioctl,
1914 .ndo_tx_timeout = igb_tx_timeout,
1915 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1916 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1917 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1918 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1919 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1920 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1921 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1922 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1923#ifdef CONFIG_NET_POLL_CONTROLLER
1924 .ndo_poll_controller = igb_netpoll,
1925#endif
b2cb09b1
JP		 1926 .ndo_fix_features = igb_fix_features,
1927 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1928};
1929
d67974f0
CW		 1930/**
1931 * igb_set_fw_version - Configure version string for ethtool
1932 * @adapter: adapter struct
d67974f0
CW		 1933 **/
1934void igb_set_fw_version(struct igb_adapter *adapter)
1935{
1936 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1937 struct e1000_fw_version fw;
1938
1939 igb_get_fw_version(hw, &fw);
1940
1941 switch (hw->mac.type) {
7dc98a62 1942 case e1000_i210:
0b1a6f2e 1943 case e1000_i211:
7dc98a62
CW		 1944 if (!(igb_get_flash_presence_i210(hw))) {
1945 snprintf(adapter->fw_version,
1946 sizeof(adapter->fw_version),
1947 "%2d.%2d-%d",
1948 fw.invm_major, fw.invm_minor,
1949 fw.invm_img_type);
1950 break;
1951 }
1952 /* fall through */
0b1a6f2e
CW		 1953 default:
1954 /* if option is rom valid, display its version too */
1955 if (fw.or_valid) {
1956 snprintf(adapter->fw_version,
1957 sizeof(adapter->fw_version),
1958 "%d.%d, 0x%08x, %d.%d.%d",
1959 fw.eep_major, fw.eep_minor, fw.etrack_id,
1960 fw.or_major, fw.or_build, fw.or_patch);
1961 /* no option rom */
7dc98a62 1962 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 1963 snprintf(adapter->fw_version,
7dc98a62
CW		 1964 sizeof(adapter->fw_version),
1965 "%d.%d, 0x%08x",
1966 fw.eep_major, fw.eep_minor, fw.etrack_id);
1967 } else {
1968 snprintf(adapter->fw_version,
1969 sizeof(adapter->fw_version),
1970 "%d.%d.%d",
1971 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 1972 }
1973 break;
d67974f0 1974 }
d67974f0
CW		 1975 return;
1976}
1977
b980ac18
JK		 1978/**
1979 * igb_init_i2c - Init I2C interface
441fc6fd 1980 * @adapter: pointer to adapter structure
b980ac18 1981 **/
441fc6fd
CW		 1982static s32 igb_init_i2c(struct igb_adapter *adapter)
1983{
1984 s32 status = E1000_SUCCESS;
1985
1986 /* I2C interface supported on i350 devices */
1987 if (adapter->hw.mac.type != e1000_i350)
1988 return E1000_SUCCESS;
1989
1990 /* Initialize the i2c bus which is controlled by the registers.
1991 * This bus will use the i2c_algo_bit structue that implements
1992 * the protocol through toggling of the 4 bits in the register.
1993 */
1994 adapter->i2c_adap.owner = THIS_MODULE;
1995 adapter->i2c_algo = igb_i2c_algo;
1996 adapter->i2c_algo.data = adapter;
1997 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1998 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1999 strlcpy(adapter->i2c_adap.name, "igb BB",
2000 sizeof(adapter->i2c_adap.name));
2001 status = i2c_bit_add_bus(&adapter->i2c_adap);
2002 return status;
2003}
2004
9d5c8243 2005/**
b980ac18
JK		 2006 * igb_probe - Device Initialization Routine
2007 * @pdev: PCI device information struct
2008 * @ent: entry in igb_pci_tbl
9d5c8243 2009 *
b980ac18 2010 * Returns 0 on success, negative on failure
9d5c8243 2011 *
b980ac18
JK		 2012 * igb_probe initializes an adapter identified by a pci_dev structure.
2013 * The OS initialization, configuring of the adapter private structure,
2014 * and a hardware reset occur.
9d5c8243 2015 **/
1dd06ae8 2016static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2017{
2018 struct net_device *netdev;
2019 struct igb_adapter *adapter;
2020 struct e1000_hw *hw;
4337e993 2021 u16 eeprom_data = 0;
9835fd73 2022 s32 ret_val;
4337e993 2023 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2024 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2025 int err, pci_using_dac;
9835fd73 2026 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2027
bded64a7
AG		 2028 /* Catch broken hardware that put the wrong VF device ID in
2029 * the PCIe SR-IOV capability.
2030 */
2031 if (pdev->is_virtfn) {
2032 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2033 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2034 return -EINVAL;
2035 }
2036
aed5dec3 2037 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2038 if (err)
2039 return err;
2040
2041 pci_using_dac = 0;
dc4ff9bb 2042 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2043 if (!err) {
dc4ff9bb 2044 pci_using_dac = 1;
9d5c8243 2045 } else {
dc4ff9bb 2046 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2047 if (err) {
dc4ff9bb
RK		 2048 dev_err(&pdev->dev,
2049 "No usable DMA configuration, aborting\n");
2050 goto err_dma;
9d5c8243
AK		 2051 }
2052 }
2053
aed5dec3 2054 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2055 IORESOURCE_MEM),
2056 igb_driver_name);
9d5c8243
AK		 2057 if (err)
2058 goto err_pci_reg;
2059
19d5afd4 2060 pci_enable_pcie_error_reporting(pdev);
40a914fa 2061
9d5c8243 2062 pci_set_master(pdev);
c682fc23 2063 pci_save_state(pdev);
9d5c8243
AK		 2064
2065 err = -ENOMEM;
1bfaf07b 2066 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2067 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2068 if (!netdev)
2069 goto err_alloc_etherdev;
2070
2071 SET_NETDEV_DEV(netdev, &pdev->dev);
2072
2073 pci_set_drvdata(pdev, netdev);
2074 adapter = netdev_priv(netdev);
2075 adapter->netdev = netdev;
2076 adapter->pdev = pdev;
2077 hw = &adapter->hw;
2078 hw->back = adapter;
b3f4d599 2079 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2080
9d5c8243 2081 err = -EIO;
89dbefb2 2082 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2083 if (!hw->hw_addr)
9d5c8243
AK		 2084 goto err_ioremap;
2085
2e5c6922 2086 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2087 igb_set_ethtool_ops(netdev);
9d5c8243 2088 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2089
2090 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2091
89dbefb2
AS		 2092 netdev->mem_start = pci_resource_start(pdev, 0);
2093 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2094
9d5c8243
AK		 2095 /* PCI config space info */
2096 hw->vendor_id = pdev->vendor;
2097 hw->device_id = pdev->device;
2098 hw->revision_id = pdev->revision;
2099 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2100 hw->subsystem_device_id = pdev->subsystem_device;
2101
9d5c8243
AK		 2102 /* Copy the default MAC, PHY and NVM function pointers */
2103 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2104 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2105 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2106 /* Initialize skew-specific constants */
2107 err = ei->get_invariants(hw);
2108 if (err)
450c87c8 2109 goto err_sw_init;
9d5c8243 2110
450c87c8 2111 /* setup the private structure */
9d5c8243
AK		 2112 err = igb_sw_init(adapter);
2113 if (err)
2114 goto err_sw_init;
2115
2116 igb_get_bus_info_pcie(hw);
2117
2118 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2119
2120 /* Copper options */
2121 if (hw->phy.media_type == e1000_media_type_copper) {
2122 hw->phy.mdix = AUTO_ALL_MODES;
2123 hw->phy.disable_polarity_correction = false;
2124 hw->phy.ms_type = e1000_ms_hw_default;
2125 }
2126
2127 if (igb_check_reset_block(hw))
2128 dev_info(&pdev->dev,
2129 "PHY reset is blocked due to SOL/IDER session.\n");
2130
b980ac18 2131 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2132 * set by igb_sw_init so we should use an or instead of an
2133 * assignment.
2134 */
2135 netdev->features |= NETIF_F_SG |
2136 NETIF_F_IP_CSUM |
2137 NETIF_F_IPV6_CSUM |
2138 NETIF_F_TSO |
2139 NETIF_F_TSO6 |
2140 NETIF_F_RXHASH |
2141 NETIF_F_RXCSUM |
f646968f
PM		 2142 NETIF_F_HW_VLAN_CTAG_RX |
2143 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2144
2145 /* copy netdev features into list of user selectable features */
2146 netdev->hw_features |= netdev->features;
89eaefb6 2147 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2148
2149 /* set this bit last since it cannot be part of hw_features */
f646968f 2150 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2151
2152 netdev->vlan_features |= NETIF_F_TSO |
2153 NETIF_F_TSO6 |
2154 NETIF_F_IP_CSUM |
2155 NETIF_F_IPV6_CSUM |
2156 NETIF_F_SG;
48f29ffc 2157
6b8f0922
BG		 2158 netdev->priv_flags |= IFF_SUPP_NOFCS;
2159
7b872a55 2160 if (pci_using_dac) {
9d5c8243 2161 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2162 netdev->vlan_features |= NETIF_F_HIGHDMA;
2163 }
9d5c8243 2164
ac52caa3
MM		 2165 if (hw->mac.type >= e1000_82576) {
2166 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2167 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2168 }
b9473560 2169
01789349
JP		 2170 netdev->priv_flags |= IFF_UNICAST_FLT;
2171
330a6d6a 2172 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2173
2174 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2175 * known good starting state
2176 */
9d5c8243
AK		 2177 hw->mac.ops.reset_hw(hw);
2178
ef3a0092
CW		 2179 /* make sure the NVM is good , i211/i210 parts can have special NVM
2180 * that doesn't contain a checksum
f96a8a0b 2181 */
ef3a0092
CW		 2182 switch (hw->mac.type) {
2183 case e1000_i210:
2184 case e1000_i211:
2185 if (igb_get_flash_presence_i210(hw)) {
2186 if (hw->nvm.ops.validate(hw) < 0) {
2187 dev_err(&pdev->dev,
2188 "The NVM Checksum Is Not Valid\n");
2189 err = -EIO;
2190 goto err_eeprom;
2191 }
2192 }
2193 break;
2194 default:
f96a8a0b
CW		 2195 if (hw->nvm.ops.validate(hw) < 0) {
2196 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2197 err = -EIO;
2198 goto err_eeprom;
2199 }
ef3a0092 2200 break;
9d5c8243
AK		 2201 }
2202
2203 /* copy the MAC address out of the NVM */
2204 if (hw->mac.ops.read_mac_addr(hw))
2205 dev_err(&pdev->dev, "NVM Read Error\n");
2206
2207 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2208
aaeb6cdf 2209 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2210 dev_err(&pdev->dev, "Invalid MAC Address\n");
2211 err = -EIO;
2212 goto err_eeprom;
2213 }
2214
d67974f0
CW		 2215 /* get firmware version for ethtool -i */
2216 igb_set_fw_version(adapter);
2217
c061b18d 2218 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2219 (unsigned long) adapter);
c061b18d 2220 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2221 (unsigned long) adapter);
9d5c8243
AK		 2222
2223 INIT_WORK(&adapter->reset_task, igb_reset_task);
2224 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2225
450c87c8 2226 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2227 adapter->fc_autoneg = true;
2228 hw->mac.autoneg = true;
2229 hw->phy.autoneg_advertised = 0x2f;
2230
0cce119a
AD		 2231 hw->fc.requested_mode = e1000_fc_default;
2232 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2233
9d5c8243
AK		 2234 igb_validate_mdi_setting(hw);
2235
63d4a8f9 2236 /* By default, support wake on port A */
a2cf8b6c 2237 if (hw->bus.func == 0)
63d4a8f9
MV		 2238 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2239
2240 /* Check the NVM for wake support on non-port A ports */
2241 if (hw->mac.type >= e1000_82580)
55cac248 2242 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2243 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2244 &eeprom_data);
a2cf8b6c
AD		 2245 else if (hw->bus.func == 1)
2246 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2247
63d4a8f9
MV		 2248 if (eeprom_data & IGB_EEPROM_APME)
2249 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2250
2251 /* now that we have the eeprom settings, apply the special cases where
2252 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2253 * lan on a particular port
2254 */
9d5c8243
AK		 2255 switch (pdev->device) {
2256 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2257 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2258 break;
2259 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2260 case E1000_DEV_ID_82576_FIBER:
2261 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2262 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2263 * regardless of eeprom setting
2264 */
9d5c8243 2265 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2266 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2267 break;
c8ea5ea9 2268 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2269 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2270 /* if quad port adapter, disable WoL on all but port A */
2271 if (global_quad_port_a != 0)
63d4a8f9 2272 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2273 else
2274 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2275 /* Reset for multiple quad port adapters */
2276 if (++global_quad_port_a == 4)
2277 global_quad_port_a = 0;
2278 break;
63d4a8f9
MV		 2279 default:
2280 /* If the device can't wake, don't set software support */
2281 if (!device_can_wakeup(&adapter->pdev->dev))
2282 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2283 }
2284
2285 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2286 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2287 adapter->wol |= E1000_WUFC_MAG;
2288
2289 /* Some vendors want WoL disabled by default, but still supported */
2290 if ((hw->mac.type == e1000_i350) &&
2291 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2292 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2293 adapter->wol = 0;
2294 }
2295
2296 device_set_wakeup_enable(&adapter->pdev->dev,
2297 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2298
2299 /* reset the hardware with the new settings */
2300 igb_reset(adapter);
2301
441fc6fd
CW		 2302 /* Init the I2C interface */
2303 err = igb_init_i2c(adapter);
2304 if (err) {
2305 dev_err(&pdev->dev, "failed to init i2c interface\n");
2306 goto err_eeprom;
2307 }
2308
9d5c8243
AK		 2309 /* let the f/w know that the h/w is now under the control of the
2310 * driver. */
2311 igb_get_hw_control(adapter);
2312
9d5c8243
AK		 2313 strcpy(netdev->name, "eth%d");
2314 err = register_netdev(netdev);
2315 if (err)
2316 goto err_register;
2317
b168dfc5
JB		 2318 /* carrier off reporting is important to ethtool even BEFORE open */
2319 netif_carrier_off(netdev);
2320
421e02f0 2321#ifdef CONFIG_IGB_DCA
bbd98fe4 2322 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2323 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2324 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2325 igb_setup_dca(adapter);
2326 }
fe4506b6 2327
38c845c7 2328#endif
e428893b
CW		 2329#ifdef CONFIG_IGB_HWMON
2330 /* Initialize the thermal sensor on i350 devices. */
2331 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2332 u16 ets_word;
3c89f6d0 2333
b980ac18 2334 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2335 * external thermal sensor.
2336 */
2337 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2338 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2339 adapter->ets = true;
2340 else
2341 adapter->ets = false;
2342 if (igb_sysfs_init(adapter))
2343 dev_err(&pdev->dev,
2344 "failed to allocate sysfs resources\n");
2345 } else {
2346 adapter->ets = false;
2347 }
2348#endif
673b8b70 2349 /* do hw tstamp init after resetting */
7ebae817 2350 igb_ptp_init(adapter);
673b8b70 2351
9d5c8243 2352 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2353 /* print bus type/speed/width info, not applicable to i354 */
2354 if (hw->mac.type != e1000_i354) {
2355 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2356 netdev->name,
2357 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2358 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2359 "unknown"),
2360 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2361 "Width x4" :
2362 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2363 "Width x2" :
2364 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2365 "Width x1" : "unknown"), netdev->dev_addr);
2366 }
9d5c8243 2367
53ea6c7e
TF		 2368 if ((hw->mac.type >= e1000_i210 ||
2369 igb_get_flash_presence_i210(hw))) {
2370 ret_val = igb_read_part_string(hw, part_str,
2371 E1000_PBANUM_LENGTH);
2372 } else {
2373 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2374 }
2375
9835fd73
CW		 2376 if (ret_val)
2377 strcpy(part_str, "Unknown");
2378 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2379 dev_info(&pdev->dev,
2380 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2381 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2382 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2383 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2384 switch (hw->mac.type) {
2385 case e1000_i350:
f96a8a0b
CW		 2386 case e1000_i210:
2387 case e1000_i211:
09b068d4
CW		 2388 igb_set_eee_i350(hw);
2389 break;
ceb5f13b
CW		 2390 case e1000_i354:
2391 if (hw->phy.media_type == e1000_media_type_copper) {
2392 if ((rd32(E1000_CTRL_EXT) &
2393 E1000_CTRL_EXT_LINK_MODE_SGMII))
2394 igb_set_eee_i354(hw);
2395 }
2396 break;
09b068d4
CW		 2397 default:
2398 break;
2399 }
749ab2cd
YZ		 2400
2401 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2402 return 0;
2403
2404err_register:
2405 igb_release_hw_control(adapter);
441fc6fd 2406 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2407err_eeprom:
2408 if (!igb_check_reset_block(hw))
f5f4cf08 2409 igb_reset_phy(hw);
9d5c8243
AK		 2410
2411 if (hw->flash_address)
2412 iounmap(hw->flash_address);
9d5c8243 2413err_sw_init:
047e0030 2414 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2415 iounmap(hw->hw_addr);
2416err_ioremap:
2417 free_netdev(netdev);
2418err_alloc_etherdev:
559e9c49 2419 pci_release_selected_regions(pdev,
b980ac18 2420 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2421err_pci_reg:
2422err_dma:
2423 pci_disable_device(pdev);
2424 return err;
2425}
2426
fa44f2f1 2427#ifdef CONFIG_PCI_IOV
781798a1 2428static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2429{
2430 struct net_device *netdev = pci_get_drvdata(pdev);
2431 struct igb_adapter *adapter = netdev_priv(netdev);
2432 struct e1000_hw *hw = &adapter->hw;
2433
2434 /* reclaim resources allocated to VFs */
2435 if (adapter->vf_data) {
2436 /* disable iov and allow time for transactions to clear */
b09186d2 2437 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2438 dev_warn(&pdev->dev,
2439 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2440 return -EPERM;
2441 } else {
2442 pci_disable_sriov(pdev);
2443 msleep(500);
2444 }
2445
2446 kfree(adapter->vf_data);
2447 adapter->vf_data = NULL;
2448 adapter->vfs_allocated_count = 0;
2449 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2450 wrfl();
2451 msleep(100);
2452 dev_info(&pdev->dev, "IOV Disabled\n");
2453
2454 /* Re-enable DMA Coalescing flag since IOV is turned off */
2455 adapter->flags |= IGB_FLAG_DMAC;
2456 }
2457
2458 return 0;
2459}
2460
2461static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2462{
2463 struct net_device *netdev = pci_get_drvdata(pdev);
2464 struct igb_adapter *adapter = netdev_priv(netdev);
2465 int old_vfs = pci_num_vf(pdev);
2466 int err = 0;
2467 int i;
2468
781798a1 2469 if (!adapter->msix_entries || num_vfs > 7) {
50267196
MW		 2470 err = -EPERM;
2471 goto out;
2472 }
fa44f2f1
GR		 2473 if (!num_vfs)
2474 goto out;
fa44f2f1 2475
781798a1
SA		 2476 if (old_vfs) {
2477 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2478 old_vfs, max_vfs);
2479 adapter->vfs_allocated_count = old_vfs;
2480 } else
2481 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2482
2483 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2484 sizeof(struct vf_data_storage), GFP_KERNEL);
2485
2486 /* if allocation failed then we do not support SR-IOV */
2487 if (!adapter->vf_data) {
2488 adapter->vfs_allocated_count = 0;
2489 dev_err(&pdev->dev,
2490 "Unable to allocate memory for VF Data Storage\n");
2491 err = -ENOMEM;
2492 goto out;
2493 }
2494
781798a1
SA		 2495 /* only call pci_enable_sriov() if no VFs are allocated already */
2496 if (!old_vfs) {
2497 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2498 if (err)
2499 goto err_out;
2500 }
fa44f2f1
GR		 2501 dev_info(&pdev->dev, "%d VFs allocated\n",
2502 adapter->vfs_allocated_count);
2503 for (i = 0; i < adapter->vfs_allocated_count; i++)
2504 igb_vf_configure(adapter, i);
2505
2506 /* DMA Coalescing is not supported in IOV mode. */
2507 adapter->flags &= ~IGB_FLAG_DMAC;
2508 goto out;
2509
2510err_out:
2511 kfree(adapter->vf_data);
2512 adapter->vf_data = NULL;
2513 adapter->vfs_allocated_count = 0;
2514out:
2515 return err;
2516}
2517
2518#endif
b980ac18 2519/**
441fc6fd
CW		 2520 * igb_remove_i2c - Cleanup I2C interface
2521 * @adapter: pointer to adapter structure
b980ac18 2522 **/
441fc6fd
CW		 2523static void igb_remove_i2c(struct igb_adapter *adapter)
2524{
441fc6fd
CW		 2525 /* free the adapter bus structure */
2526 i2c_del_adapter(&adapter->i2c_adap);
2527}
2528
9d5c8243 2529/**
b980ac18
JK		 2530 * igb_remove - Device Removal Routine
2531 * @pdev: PCI device information struct
9d5c8243 2532 *
b980ac18
JK		 2533 * igb_remove is called by the PCI subsystem to alert the driver
2534 * that it should release a PCI device. The could be caused by a
2535 * Hot-Plug event, or because the driver is going to be removed from
2536 * memory.
9d5c8243 2537 **/
9f9a12f8 2538static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2539{
2540 struct net_device *netdev = pci_get_drvdata(pdev);
2541 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2542 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2543
749ab2cd 2544 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2545#ifdef CONFIG_IGB_HWMON
2546 igb_sysfs_exit(adapter);
2547#endif
441fc6fd 2548 igb_remove_i2c(adapter);
a79f4f88 2549 igb_ptp_stop(adapter);
b980ac18 2550 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2551 * disable watchdog from being rescheduled.
2552 */
9d5c8243
AK		 2553 set_bit(__IGB_DOWN, &adapter->state);
2554 del_timer_sync(&adapter->watchdog_timer);
2555 del_timer_sync(&adapter->phy_info_timer);
2556
760141a5
TH		 2557 cancel_work_sync(&adapter->reset_task);
2558 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2559
421e02f0 2560#ifdef CONFIG_IGB_DCA
7dfc16fa 2561 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2562 dev_info(&pdev->dev, "DCA disabled\n");
2563 dca_remove_requester(&pdev->dev);
7dfc16fa 2564 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2565 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2566 }
2567#endif
2568
9d5c8243 2569 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2570 * would have already happened in close and is redundant.
2571 */
9d5c8243
AK		 2572 igb_release_hw_control(adapter);
2573
2574 unregister_netdev(netdev);
2575
047e0030 2576 igb_clear_interrupt_scheme(adapter);
9d5c8243 2577
37680117 2578#ifdef CONFIG_PCI_IOV
fa44f2f1 2579 igb_disable_sriov(pdev);
37680117 2580#endif
559e9c49 2581
28b0759c
AD		 2582 iounmap(hw->hw_addr);
2583 if (hw->flash_address)
2584 iounmap(hw->flash_address);
559e9c49 2585 pci_release_selected_regions(pdev,
b980ac18 2586 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2587
1128c756 2588 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2589 free_netdev(netdev);
2590
19d5afd4 2591 pci_disable_pcie_error_reporting(pdev);
40a914fa 2592
9d5c8243
AK		 2593 pci_disable_device(pdev);
2594}
2595
a6b623e0 2596/**
b980ac18
JK		 2597 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2598 * @adapter: board private structure to initialize
a6b623e0 2599 *
b980ac18
JK		 2600 * This function initializes the vf specific data storage and then attempts to
2601 * allocate the VFs. The reason for ordering it this way is because it is much
2602 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2603 * the memory for the VFs.
a6b623e0 2604 **/
9f9a12f8 2605static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2606{
2607#ifdef CONFIG_PCI_IOV
2608 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2609 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2610
f96a8a0b
CW		 2611 /* Virtualization features not supported on i210 family. */
2612 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2613 return;
2614
fa44f2f1 2615 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2616 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2617
a6b623e0
AD		 2618#endif /* CONFIG_PCI_IOV */
2619}
2620
fa44f2f1 2621static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2622{
2623 struct e1000_hw *hw = &adapter->hw;
374a542d 2624 u32 max_rss_queues;
9d5c8243 2625
374a542d 2626 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2627 switch (hw->mac.type) {
374a542d
MV		 2628 case e1000_i211:
2629 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2630 break;
2631 case e1000_82575:
f96a8a0b 2632 case e1000_i210:
374a542d
MV		 2633 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2634 break;
2635 case e1000_i350:
2636 /* I350 cannot do RSS and SR-IOV at the same time */
2637 if (!!adapter->vfs_allocated_count) {
2638 max_rss_queues = 1;
2639 break;
2640 }
2641 /* fall through */
2642 case e1000_82576:
2643 if (!!adapter->vfs_allocated_count) {
2644 max_rss_queues = 2;
2645 break;
2646 }
2647 /* fall through */
2648 case e1000_82580:
ceb5f13b 2649 case e1000_i354:
374a542d
MV		 2650 default:
2651 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2652 break;
374a542d
MV		 2653 }
2654
2655 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2656
2657 /* Determine if we need to pair queues. */
2658 switch (hw->mac.type) {
2659 case e1000_82575:
f96a8a0b 2660 case e1000_i211:
374a542d 2661 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2662 break;
374a542d 2663 case e1000_82576:
b980ac18 2664 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2665 * should pair the queues in order to conserve interrupts due
2666 * to limited supply.
2667 */
2668 if ((adapter->rss_queues > 1) &&
2669 (adapter->vfs_allocated_count > 6))
2670 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2671 /* fall through */
2672 case e1000_82580:
2673 case e1000_i350:
ceb5f13b 2674 case e1000_i354:
374a542d 2675 case e1000_i210:
f96a8a0b 2676 default:
b980ac18 2677 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2678 * order to conserve interrupts due to limited supply.
2679 */
2680 if (adapter->rss_queues > (max_rss_queues / 2))
2681 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2682 break;
2683 }
fa44f2f1
GR		 2684}
2685
2686/**
b980ac18
JK		 2687 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2688 * @adapter: board private structure to initialize
fa44f2f1 2689 *
b980ac18
JK		 2690 * igb_sw_init initializes the Adapter private data structure.
2691 * Fields are initialized based on PCI device information and
2692 * OS network device settings (MTU size).
fa44f2f1
GR		 2693 **/
2694static int igb_sw_init(struct igb_adapter *adapter)
2695{
2696 struct e1000_hw *hw = &adapter->hw;
2697 struct net_device *netdev = adapter->netdev;
2698 struct pci_dev *pdev = adapter->pdev;
2699
2700 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2701
2702 /* set default ring sizes */
2703 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2704 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2705
2706 /* set default ITR values */
2707 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2708 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2709
2710 /* set default work limits */
2711 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2712
2713 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2714 VLAN_HLEN;
2715 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2716
2717 spin_lock_init(&adapter->stats64_lock);
2718#ifdef CONFIG_PCI_IOV
2719 switch (hw->mac.type) {
2720 case e1000_82576:
2721 case e1000_i350:
2722 if (max_vfs > 7) {
2723 dev_warn(&pdev->dev,
2724 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2725 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2726 } else
2727 adapter->vfs_allocated_count = max_vfs;
2728 if (adapter->vfs_allocated_count)
2729 dev_warn(&pdev->dev,
2730 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2731 break;
2732 default:
2733 break;
2734 }
2735#endif /* CONFIG_PCI_IOV */
2736
2737 igb_init_queue_configuration(adapter);
a99955fc 2738
1128c756 2739 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2740 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2741 GFP_ATOMIC);
1128c756 2742
a6b623e0 2743 /* This call may decrease the number of queues */
53c7d064 2744 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2745 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2746 return -ENOMEM;
2747 }
2748
a6b623e0
AD		 2749 igb_probe_vfs(adapter);
2750
9d5c8243
AK		 2751 /* Explicitly disable IRQ since the NIC can be in any state. */
2752 igb_irq_disable(adapter);
2753
f96a8a0b 2754 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2755 adapter->flags &= ~IGB_FLAG_DMAC;
2756
9d5c8243
AK		 2757 set_bit(__IGB_DOWN, &adapter->state);
2758 return 0;
2759}
2760
2761/**
b980ac18
JK		 2762 * igb_open - Called when a network interface is made active
2763 * @netdev: network interface device structure
9d5c8243 2764 *
b980ac18 2765 * Returns 0 on success, negative value on failure
9d5c8243 2766 *
b980ac18
JK		 2767 * The open entry point is called when a network interface is made
2768 * active by the system (IFF_UP). At this point all resources needed
2769 * for transmit and receive operations are allocated, the interrupt
2770 * handler is registered with the OS, the watchdog timer is started,
2771 * and the stack is notified that the interface is ready.
9d5c8243 2772 **/
749ab2cd 2773static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2774{
2775 struct igb_adapter *adapter = netdev_priv(netdev);
2776 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2777 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2778 int err;
2779 int i;
2780
2781 /* disallow open during test */
749ab2cd
YZ		 2782 if (test_bit(__IGB_TESTING, &adapter->state)) {
2783 WARN_ON(resuming);
9d5c8243 2784 return -EBUSY;
749ab2cd
YZ		 2785 }
2786
2787 if (!resuming)
2788 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2789
b168dfc5
JB		 2790 netif_carrier_off(netdev);
2791
9d5c8243
AK		 2792 /* allocate transmit descriptors */
2793 err = igb_setup_all_tx_resources(adapter);
2794 if (err)
2795 goto err_setup_tx;
2796
2797 /* allocate receive descriptors */
2798 err = igb_setup_all_rx_resources(adapter);
2799 if (err)
2800 goto err_setup_rx;
2801
88a268c1 2802 igb_power_up_link(adapter);
9d5c8243 2803
9d5c8243
AK		 2804 /* before we allocate an interrupt, we must be ready to handle it.
2805 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2806 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2807 * clean_rx handler before we do so.
2808 */
9d5c8243
AK		 2809 igb_configure(adapter);
2810
2811 err = igb_request_irq(adapter);
2812 if (err)
2813 goto err_req_irq;
2814
0c2cc02e
AD		 2815 /* Notify the stack of the actual queue counts. */
2816 err = netif_set_real_num_tx_queues(adapter->netdev,
2817 adapter->num_tx_queues);
2818 if (err)
2819 goto err_set_queues;
2820
2821 err = netif_set_real_num_rx_queues(adapter->netdev,
2822 adapter->num_rx_queues);
2823 if (err)
2824 goto err_set_queues;
2825
9d5c8243
AK		 2826 /* From here on the code is the same as igb_up() */
2827 clear_bit(__IGB_DOWN, &adapter->state);
2828
0d1ae7f4
AD		 2829 for (i = 0; i < adapter->num_q_vectors; i++)
2830 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2831
2832 /* Clear any pending interrupts. */
2833 rd32(E1000_ICR);
844290e5
PW		 2834
2835 igb_irq_enable(adapter);
2836
d4960307
AD		 2837 /* notify VFs that reset has been completed */
2838 if (adapter->vfs_allocated_count) {
2839 u32 reg_data = rd32(E1000_CTRL_EXT);
2840 reg_data |= E1000_CTRL_EXT_PFRSTD;
2841 wr32(E1000_CTRL_EXT, reg_data);
2842 }
2843
d55b53ff
JK		 2844 netif_tx_start_all_queues(netdev);
2845
749ab2cd
YZ		 2846 if (!resuming)
2847 pm_runtime_put(&pdev->dev);
2848
25568a53
AD		 2849 /* start the watchdog. */
2850 hw->mac.get_link_status = 1;
2851 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2852
2853 return 0;
2854
0c2cc02e
AD		 2855err_set_queues:
2856 igb_free_irq(adapter);
9d5c8243
AK		 2857err_req_irq:
2858 igb_release_hw_control(adapter);
88a268c1 2859 igb_power_down_link(adapter);
9d5c8243
AK		 2860 igb_free_all_rx_resources(adapter);
2861err_setup_rx:
2862 igb_free_all_tx_resources(adapter);
2863err_setup_tx:
2864 igb_reset(adapter);
749ab2cd
YZ		 2865 if (!resuming)
2866 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2867
2868 return err;
2869}
2870
749ab2cd
YZ		 2871static int igb_open(struct net_device *netdev)
2872{
2873 return __igb_open(netdev, false);
2874}
2875
9d5c8243 2876/**
b980ac18
JK		 2877 * igb_close - Disables a network interface
2878 * @netdev: network interface device structure
9d5c8243 2879 *
b980ac18 2880 * Returns 0, this is not allowed to fail
9d5c8243 2881 *
b980ac18
JK		 2882 * The close entry point is called when an interface is de-activated
2883 * by the OS. The hardware is still under the driver's control, but
2884 * needs to be disabled. A global MAC reset is issued to stop the
2885 * hardware, and all transmit and receive resources are freed.
9d5c8243 2886 **/
749ab2cd 2887static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2888{
2889 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2890 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2891
2892 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2893
749ab2cd
YZ		 2894 if (!suspending)
2895 pm_runtime_get_sync(&pdev->dev);
2896
2897 igb_down(adapter);
9d5c8243
AK		 2898 igb_free_irq(adapter);
2899
2900 igb_free_all_tx_resources(adapter);
2901 igb_free_all_rx_resources(adapter);
2902
749ab2cd
YZ		 2903 if (!suspending)
2904 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2905 return 0;
2906}
2907
749ab2cd
YZ		 2908static int igb_close(struct net_device *netdev)
2909{
2910 return __igb_close(netdev, false);
2911}
2912
9d5c8243 2913/**
b980ac18
JK		 2914 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2915 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2916 *
b980ac18 2917 * Return 0 on success, negative on failure
9d5c8243 2918 **/
80785298 2919int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2920{
59d71989 2921 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2922 int size;
2923
06034649 2924 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2925
2926 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2927 if (!tx_ring->tx_buffer_info)
9d5c8243 2928 goto err;
9d5c8243
AK		 2929
2930 /* round up to nearest 4K */
85e8d004 2931 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2932 tx_ring->size = ALIGN(tx_ring->size, 4096);
2933
5536d210
AD		 2934 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2935 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2936 if (!tx_ring->desc)
2937 goto err;
2938
9d5c8243
AK		 2939 tx_ring->next_to_use = 0;
2940 tx_ring->next_to_clean = 0;
81c2fc22 2941
9d5c8243
AK		 2942 return 0;
2943
2944err:
06034649 2945 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2946 tx_ring->tx_buffer_info = NULL;
2947 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2948 return -ENOMEM;
2949}
2950
2951/**
b980ac18
JK		 2952 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2953 * (Descriptors) for all queues
2954 * @adapter: board private structure
9d5c8243 2955 *
b980ac18 2956 * Return 0 on success, negative on failure
9d5c8243
AK		 2957 **/
2958static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2959{
439705e1 2960 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2961 int i, err = 0;
2962
2963 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2964 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2965 if (err) {
439705e1 2966 dev_err(&pdev->dev,
9d5c8243
AK		 2967 "Allocation for Tx Queue %u failed\n", i);
2968 for (i--; i >= 0; i--)
3025a446 2969 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2970 break;
2971 }
2972 }
2973
2974 return err;
2975}
2976
2977/**
b980ac18
JK		 2978 * igb_setup_tctl - configure the transmit control registers
2979 * @adapter: Board private structure
9d5c8243 2980 **/
d7ee5b3a 2981void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2982{
9d5c8243
AK		 2983 struct e1000_hw *hw = &adapter->hw;
2984 u32 tctl;
9d5c8243 2985
85b430b4
AD		 2986 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2987 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2988
2989 /* Program the Transmit Control Register */
9d5c8243
AK		 2990 tctl = rd32(E1000_TCTL);
2991 tctl &= ~E1000_TCTL_CT;
2992 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2993 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2994
2995 igb_config_collision_dist(hw);
2996
9d5c8243
AK		 2997 /* Enable transmits */
2998 tctl |= E1000_TCTL_EN;
2999
3000 wr32(E1000_TCTL, tctl);
3001}
3002
85b430b4 3003/**
b980ac18
JK		 3004 * igb_configure_tx_ring - Configure transmit ring after Reset
3005 * @adapter: board private structure
3006 * @ring: tx ring to configure
85b430b4 3007 *
b980ac18 3008 * Configure a transmit ring after a reset.
85b430b4 3009 **/
d7ee5b3a
AD		 3010void igb_configure_tx_ring(struct igb_adapter *adapter,
3011 struct igb_ring *ring)
85b430b4
AD		 3012{
3013 struct e1000_hw *hw = &adapter->hw;
a74420e0 3014 u32 txdctl = 0;
85b430b4
AD		 3015 u64 tdba = ring->dma;
3016 int reg_idx = ring->reg_idx;
3017
3018 /* disable the queue */
a74420e0 3019 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3020 wrfl();
3021 mdelay(10);
3022
3023 wr32(E1000_TDLEN(reg_idx),
b980ac18 3024 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3025 wr32(E1000_TDBAL(reg_idx),
b980ac18 3026 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3027 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3028
fce99e34 3029 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3030 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3031 writel(0, ring->tail);
85b430b4
AD		 3032
3033 txdctl |= IGB_TX_PTHRESH;
3034 txdctl |= IGB_TX_HTHRESH << 8;
3035 txdctl |= IGB_TX_WTHRESH << 16;
3036
3037 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3038 wr32(E1000_TXDCTL(reg_idx), txdctl);
3039}
3040
3041/**
b980ac18
JK		 3042 * igb_configure_tx - Configure transmit Unit after Reset
3043 * @adapter: board private structure
85b430b4 3044 *
b980ac18 3045 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3046 **/
3047static void igb_configure_tx(struct igb_adapter *adapter)
3048{
3049 int i;
3050
3051 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3052 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3053}
3054
9d5c8243 3055/**
b980ac18
JK		 3056 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3057 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3058 *
b980ac18 3059 * Returns 0 on success, negative on failure
9d5c8243 3060 **/
80785298 3061int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3062{
59d71989 3063 struct device *dev = rx_ring->dev;
f33005a6 3064 int size;
9d5c8243 3065
06034649 3066 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3067
3068 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3069 if (!rx_ring->rx_buffer_info)
9d5c8243 3070 goto err;
9d5c8243 3071
9d5c8243 3072 /* Round up to nearest 4K */
f33005a6 3073 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3074 rx_ring->size = ALIGN(rx_ring->size, 4096);
3075
5536d210
AD		 3076 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3077 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3078 if (!rx_ring->desc)
3079 goto err;
3080
cbc8e55f 3081 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3082 rx_ring->next_to_clean = 0;
3083 rx_ring->next_to_use = 0;
9d5c8243 3084
9d5c8243
AK		 3085 return 0;
3086
3087err:
06034649
AD		 3088 vfree(rx_ring->rx_buffer_info);
3089 rx_ring->rx_buffer_info = NULL;
f33005a6 3090 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3091 return -ENOMEM;
3092}
3093
3094/**
b980ac18
JK		 3095 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3096 * (Descriptors) for all queues
3097 * @adapter: board private structure
9d5c8243 3098 *
b980ac18 3099 * Return 0 on success, negative on failure
9d5c8243
AK		 3100 **/
3101static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3102{
439705e1 3103 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3104 int i, err = 0;
3105
3106 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3107 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3108 if (err) {
439705e1 3109 dev_err(&pdev->dev,
9d5c8243
AK		 3110 "Allocation for Rx Queue %u failed\n", i);
3111 for (i--; i >= 0; i--)
3025a446 3112 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3113 break;
3114 }
3115 }
3116
3117 return err;
3118}
3119
06cf2666 3120/**
b980ac18
JK		 3121 * igb_setup_mrqc - configure the multiple receive queue control registers
3122 * @adapter: Board private structure
06cf2666
AD		 3123 **/
3124static void igb_setup_mrqc(struct igb_adapter *adapter)
3125{
3126 struct e1000_hw *hw = &adapter->hw;
3127 u32 mrqc, rxcsum;
ed12cc9a 3128 u32 j, num_rx_queues;
a57fe23e
AD		 3129 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3130 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3131 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3132 0xFA01ACBE };
06cf2666
AD		 3133
3134 /* Fill out hash function seeds */
a57fe23e
AD		 3135 for (j = 0; j < 10; j++)
3136 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3137
a99955fc 3138 num_rx_queues = adapter->rss_queues;
06cf2666 3139
797fd4be 3140 switch (hw->mac.type) {
797fd4be
AD		 3141 case e1000_82576:
3142 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3143 if (adapter->vfs_allocated_count)
06cf2666 3144 num_rx_queues = 2;
797fd4be
AD		 3145 break;
3146 default:
3147 break;
06cf2666
AD		 3148 }
3149
ed12cc9a
LMV		 3150 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3151 for (j = 0; j < IGB_RETA_SIZE; j++)
3152 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3153 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3154 }
ed12cc9a 3155 igb_write_rss_indir_tbl(adapter);
06cf2666 3156
b980ac18 3157 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3158 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3159 * offloads as they are enabled by default
3160 */
3161 rxcsum = rd32(E1000_RXCSUM);
3162 rxcsum |= E1000_RXCSUM_PCSD;
3163
3164 if (adapter->hw.mac.type >= e1000_82576)
3165 /* Enable Receive Checksum Offload for SCTP */
3166 rxcsum |= E1000_RXCSUM_CRCOFL;
3167
3168 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3169 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3170
039454a8
AA		 3171 /* Generate RSS hash based on packet types, TCP/UDP
3172 * port numbers and/or IPv4/v6 src and dst addresses
3173 */
f96a8a0b
CW		 3174 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3175 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3176 E1000_MRQC_RSS_FIELD_IPV6 |
3177 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3178 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3179
039454a8
AA		 3180 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3181 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3182 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3183 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3184
06cf2666
AD		 3185 /* If VMDq is enabled then we set the appropriate mode for that, else
3186 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3187 * if we are only using one queue
3188 */
06cf2666
AD		 3189 if (adapter->vfs_allocated_count) {
3190 if (hw->mac.type > e1000_82575) {
3191 /* Set the default pool for the PF's first queue */
3192 u32 vtctl = rd32(E1000_VT_CTL);
3193 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3194 E1000_VT_CTL_DISABLE_DEF_POOL);
3195 vtctl |= adapter->vfs_allocated_count <<
3196 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3197 wr32(E1000_VT_CTL, vtctl);
3198 }
a99955fc 3199 if (adapter->rss_queues > 1)
f96a8a0b 3200 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3201 else
f96a8a0b 3202 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3203 } else {
f96a8a0b
CW		 3204 if (hw->mac.type != e1000_i211)
3205 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3206 }
3207 igb_vmm_control(adapter);
3208
06cf2666
AD		 3209 wr32(E1000_MRQC, mrqc);
3210}
3211
9d5c8243 3212/**
b980ac18
JK		 3213 * igb_setup_rctl - configure the receive control registers
3214 * @adapter: Board private structure
9d5c8243 3215 **/
d7ee5b3a 3216void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3217{
3218 struct e1000_hw *hw = &adapter->hw;
3219 u32 rctl;
9d5c8243
AK		 3220
3221 rctl = rd32(E1000_RCTL);
3222
3223 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3224 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3225
69d728ba 3226 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3227 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3228
b980ac18 3229 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3230 * redirection as it did with e1000. Newer features require
3231 * that the HW strips the CRC.
73cd78f1 3232 */
87cb7e8c 3233 rctl |= E1000_RCTL_SECRC;
9d5c8243 3234
559e9c49 3235 /* disable store bad packets and clear size bits. */
ec54d7d6 3236 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3237
6ec43fe6
AD		 3238 /* enable LPE to prevent packets larger than max_frame_size */
3239 rctl |= E1000_RCTL_LPE;
9d5c8243 3240
952f72a8
AD		 3241 /* disable queue 0 to prevent tail write w/o re-config */
3242 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3243
e1739522
AD		 3244 /* Attention!!! For SR-IOV PF driver operations you must enable
3245 * queue drop for all VF and PF queues to prevent head of line blocking
3246 * if an un-trusted VF does not provide descriptors to hardware.
3247 */
3248 if (adapter->vfs_allocated_count) {
e1739522
AD		 3249 /* set all queue drop enable bits */
3250 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3251 }
3252
89eaefb6
BG		 3253 /* This is useful for sniffing bad packets. */
3254 if (adapter->netdev->features & NETIF_F_RXALL) {
3255 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3256 * in e1000e_set_rx_mode
3257 */
89eaefb6
BG		 3258 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3259 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3260 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3261
3262 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3263 E1000_RCTL_DPF | /* Allow filtered pause */
3264 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3265 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3266 * and that breaks VLANs.
3267 */
3268 }
3269
9d5c8243
AK		 3270 wr32(E1000_RCTL, rctl);
3271}
3272
7d5753f0
AD		 3273static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3274 int vfn)
3275{
3276 struct e1000_hw *hw = &adapter->hw;
3277 u32 vmolr;
3278
3279 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3280 * increase the size to support vlan tags
3281 */
7d5753f0
AD		 3282 if (vfn < adapter->vfs_allocated_count &&
3283 adapter->vf_data[vfn].vlans_enabled)
3284 size += VLAN_TAG_SIZE;
3285
3286 vmolr = rd32(E1000_VMOLR(vfn));
3287 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3288 vmolr |= size | E1000_VMOLR_LPE;
3289 wr32(E1000_VMOLR(vfn), vmolr);
3290
3291 return 0;
3292}
3293
e1739522 3294/**
b980ac18
JK		 3295 * igb_rlpml_set - set maximum receive packet size
3296 * @adapter: board private structure
e1739522 3297 *
b980ac18 3298 * Configure maximum receivable packet size.
e1739522
AD		 3299 **/
3300static void igb_rlpml_set(struct igb_adapter *adapter)
3301{
153285f9 3302 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3303 struct e1000_hw *hw = &adapter->hw;
3304 u16 pf_id = adapter->vfs_allocated_count;
3305
e1739522
AD		 3306 if (pf_id) {
3307 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3308 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3309 * to our max jumbo frame size, in case we need to enable
3310 * jumbo frames on one of the rings later.
3311 * This will not pass over-length frames into the default
3312 * queue because it's gated by the VMOLR.RLPML.
3313 */
7d5753f0 3314 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3315 }
3316
3317 wr32(E1000_RLPML, max_frame_size);
3318}
3319
8151d294
WM		 3320static inline void igb_set_vmolr(struct igb_adapter *adapter,
3321 int vfn, bool aupe)
7d5753f0
AD		 3322{
3323 struct e1000_hw *hw = &adapter->hw;
3324 u32 vmolr;
3325
b980ac18 3326 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3327 * we should exit and do nothing
3328 */
3329 if (hw->mac.type < e1000_82576)
3330 return;
3331
3332 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3333 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3334 if (aupe)
b980ac18 3335 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3336 else
3337 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3338
3339 /* clear all bits that might not be set */
3340 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3341
a99955fc 3342 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3343 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3344 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3345 * multicast packets
3346 */
3347 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3348 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3349
3350 wr32(E1000_VMOLR(vfn), vmolr);
3351}
3352
85b430b4 3353/**
b980ac18
JK		 3354 * igb_configure_rx_ring - Configure a receive ring after Reset
3355 * @adapter: board private structure
3356 * @ring: receive ring to be configured
85b430b4 3357 *
b980ac18 3358 * Configure the Rx unit of the MAC after a reset.
85b430b4 3359 **/
d7ee5b3a 3360void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3361 struct igb_ring *ring)
85b430b4
AD		 3362{
3363 struct e1000_hw *hw = &adapter->hw;
3364 u64 rdba = ring->dma;
3365 int reg_idx = ring->reg_idx;
a74420e0 3366 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3367
3368 /* disable the queue */
a74420e0 3369 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3370
3371 /* Set DMA base address registers */
3372 wr32(E1000_RDBAL(reg_idx),
3373 rdba & 0x00000000ffffffffULL);
3374 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3375 wr32(E1000_RDLEN(reg_idx),
b980ac18 3376 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3377
3378 /* initialize head and tail */
fce99e34 3379 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3380 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3381 writel(0, ring->tail);
85b430b4 3382
952f72a8 3383 /* set descriptor configuration */
44390ca6 3384 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3385 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3386 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3387 if (hw->mac.type >= e1000_82580)
757b77e2 3388 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3389 /* Only set Drop Enable if we are supporting multiple queues */
3390 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3391 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3392
3393 wr32(E1000_SRRCTL(reg_idx), srrctl);
3394
7d5753f0 3395 /* set filtering for VMDQ pools */
8151d294 3396 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3397
85b430b4
AD		 3398 rxdctl |= IGB_RX_PTHRESH;
3399 rxdctl |= IGB_RX_HTHRESH << 8;
3400 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3401
3402 /* enable receive descriptor fetching */
3403 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3404 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3405}
3406
9d5c8243 3407/**
b980ac18
JK		 3408 * igb_configure_rx - Configure receive Unit after Reset
3409 * @adapter: board private structure
9d5c8243 3410 *
b980ac18 3411 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3412 **/
3413static void igb_configure_rx(struct igb_adapter *adapter)
3414{
9107584e 3415 int i;
9d5c8243 3416
68d480c4
AD		 3417 /* set UTA to appropriate mode */
3418 igb_set_uta(adapter);
3419
26ad9178
AD		 3420 /* set the correct pool for the PF default MAC address in entry 0 */
3421 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3422 adapter->vfs_allocated_count);
26ad9178 3423
06cf2666 3424 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3425 * the Base and Length of the Rx Descriptor Ring
3426 */
f9d40f6a
AD		 3427 for (i = 0; i < adapter->num_rx_queues; i++)
3428 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3429}
3430
3431/**
b980ac18
JK		 3432 * igb_free_tx_resources - Free Tx Resources per Queue
3433 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3434 *
b980ac18 3435 * Free all transmit software resources
9d5c8243 3436 **/
68fd9910 3437void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3438{
3b644cf6 3439 igb_clean_tx_ring(tx_ring);
9d5c8243 3440
06034649
AD		 3441 vfree(tx_ring->tx_buffer_info);
3442 tx_ring->tx_buffer_info = NULL;
9d5c8243 3443
439705e1
AD		 3444 /* if not set, then don't free */
3445 if (!tx_ring->desc)
3446 return;
3447
59d71989
AD		 3448 dma_free_coherent(tx_ring->dev, tx_ring->size,
3449 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3450
3451 tx_ring->desc = NULL;
3452}
3453
3454/**
b980ac18
JK		 3455 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3456 * @adapter: board private structure
9d5c8243 3457 *
b980ac18 3458 * Free all transmit software resources
9d5c8243
AK		 3459 **/
3460static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3461{
3462 int i;
3463
3464 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3465 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3466}
3467
ebe42d16
AD		 3468void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3469 struct igb_tx_buffer *tx_buffer)
3470{
3471 if (tx_buffer->skb) {
3472 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3473 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3474 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3475 dma_unmap_addr(tx_buffer, dma),
3476 dma_unmap_len(tx_buffer, len),
ebe42d16 3477 DMA_TO_DEVICE);
c9f14bf3 3478 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3479 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3480 dma_unmap_addr(tx_buffer, dma),
3481 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3482 DMA_TO_DEVICE);
3483 }
3484 tx_buffer->next_to_watch = NULL;
3485 tx_buffer->skb = NULL;
c9f14bf3 3486 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3487 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3488}
3489
3490/**
b980ac18
JK		 3491 * igb_clean_tx_ring - Free Tx Buffers
3492 * @tx_ring: ring to be cleaned
9d5c8243 3493 **/
3b644cf6 3494static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3495{
06034649 3496 struct igb_tx_buffer *buffer_info;
9d5c8243 3497 unsigned long size;
6ad4edfc 3498 u16 i;
9d5c8243 3499
06034649 3500 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3501 return;
3502 /* Free all the Tx ring sk_buffs */
3503
3504 for (i = 0; i < tx_ring->count; i++) {
06034649 3505 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3506 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3507 }
3508
dad8a3b3
JF		 3509 netdev_tx_reset_queue(txring_txq(tx_ring));
3510
06034649
AD		 3511 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3512 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3513
3514 /* Zero out the descriptor ring */
9d5c8243
AK		 3515 memset(tx_ring->desc, 0, tx_ring->size);
3516
3517 tx_ring->next_to_use = 0;
3518 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3519}
3520
3521/**
b980ac18
JK		 3522 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3523 * @adapter: board private structure
9d5c8243
AK		 3524 **/
3525static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3526{
3527 int i;
3528
3529 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3530 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3531}
3532
3533/**
b980ac18
JK		 3534 * igb_free_rx_resources - Free Rx Resources
3535 * @rx_ring: ring to clean the resources from
9d5c8243 3536 *
b980ac18 3537 * Free all receive software resources
9d5c8243 3538 **/
68fd9910 3539void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3540{
3b644cf6 3541 igb_clean_rx_ring(rx_ring);
9d5c8243 3542
06034649
AD		 3543 vfree(rx_ring->rx_buffer_info);
3544 rx_ring->rx_buffer_info = NULL;
9d5c8243 3545
439705e1
AD		 3546 /* if not set, then don't free */
3547 if (!rx_ring->desc)
3548 return;
3549
59d71989
AD		 3550 dma_free_coherent(rx_ring->dev, rx_ring->size,
3551 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3552
3553 rx_ring->desc = NULL;
3554}
3555
3556/**
b980ac18
JK		 3557 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3558 * @adapter: board private structure
9d5c8243 3559 *
b980ac18 3560 * Free all receive software resources
9d5c8243
AK		 3561 **/
3562static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3563{
3564 int i;
3565
3566 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3567 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3568}
3569
3570/**
b980ac18
JK		 3571 * igb_clean_rx_ring - Free Rx Buffers per Queue
3572 * @rx_ring: ring to free buffers from
9d5c8243 3573 **/
3b644cf6 3574static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3575{
9d5c8243 3576 unsigned long size;
c023cd88 3577 u16 i;
9d5c8243 3578
1a1c225b
AD		 3579 if (rx_ring->skb)
3580 dev_kfree_skb(rx_ring->skb);
3581 rx_ring->skb = NULL;
3582
06034649 3583 if (!rx_ring->rx_buffer_info)
9d5c8243 3584 return;
439705e1 3585
9d5c8243
AK		 3586 /* Free all the Rx ring sk_buffs */
3587 for (i = 0; i < rx_ring->count; i++) {
06034649 3588 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3589
cbc8e55f
AD		 3590 if (!buffer_info->page)
3591 continue;
3592
3593 dma_unmap_page(rx_ring->dev,
3594 buffer_info->dma,
3595 PAGE_SIZE,
3596 DMA_FROM_DEVICE);
3597 __free_page(buffer_info->page);
3598
1a1c225b 3599 buffer_info->page = NULL;
9d5c8243
AK		 3600 }
3601
06034649
AD		 3602 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3603 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3604
3605 /* Zero out the descriptor ring */
3606 memset(rx_ring->desc, 0, rx_ring->size);
3607
cbc8e55f 3608 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3609 rx_ring->next_to_clean = 0;
3610 rx_ring->next_to_use = 0;
9d5c8243
AK		 3611}
3612
3613/**
b980ac18
JK		 3614 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3615 * @adapter: board private structure
9d5c8243
AK		 3616 **/
3617static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3618{
3619 int i;
3620
3621 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3622 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3623}
3624
3625/**
b980ac18
JK		 3626 * igb_set_mac - Change the Ethernet Address of the NIC
3627 * @netdev: network interface device structure
3628 * @p: pointer to an address structure
9d5c8243 3629 *
b980ac18 3630 * Returns 0 on success, negative on failure
9d5c8243
AK		 3631 **/
3632static int igb_set_mac(struct net_device *netdev, void *p)
3633{
3634 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3635 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3636 struct sockaddr *addr = p;
3637
3638 if (!is_valid_ether_addr(addr->sa_data))
3639 return -EADDRNOTAVAIL;
3640
3641 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3642 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3643
26ad9178
AD		 3644 /* set the correct pool for the new PF MAC address in entry 0 */
3645 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3646 adapter->vfs_allocated_count);
e1739522 3647
9d5c8243
AK		 3648 return 0;
3649}
3650
3651/**
b980ac18
JK		 3652 * igb_write_mc_addr_list - write multicast addresses to MTA
3653 * @netdev: network interface device structure
9d5c8243 3654 *
b980ac18
JK		 3655 * Writes multicast address list to the MTA hash table.
3656 * Returns: -ENOMEM on failure
3657 * 0 on no addresses written
3658 * X on writing X addresses to MTA
9d5c8243 3659 **/
68d480c4 3660static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3661{
3662 struct igb_adapter *adapter = netdev_priv(netdev);
3663 struct e1000_hw *hw = &adapter->hw;
22bedad3 3664 struct netdev_hw_addr *ha;
68d480c4 3665 u8 *mta_list;
9d5c8243
AK		 3666 int i;
3667
4cd24eaf 3668 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3669 /* nothing to program, so clear mc list */
3670 igb_update_mc_addr_list(hw, NULL, 0);
3671 igb_restore_vf_multicasts(adapter);
3672 return 0;
3673 }
9d5c8243 3674
4cd24eaf 3675 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3676 if (!mta_list)
3677 return -ENOMEM;
ff41f8dc 3678
68d480c4 3679 /* The shared function expects a packed array of only addresses. */
48e2f183 3680 i = 0;
22bedad3
JP		 3681 netdev_for_each_mc_addr(ha, netdev)
3682 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3683
68d480c4
AD		 3684 igb_update_mc_addr_list(hw, mta_list, i);
3685 kfree(mta_list);
3686
4cd24eaf 3687 return netdev_mc_count(netdev);
68d480c4
AD		 3688}
3689
3690/**
b980ac18
JK		 3691 * igb_write_uc_addr_list - write unicast addresses to RAR table
3692 * @netdev: network interface device structure
68d480c4 3693 *
b980ac18
JK		 3694 * Writes unicast address list to the RAR table.
3695 * Returns: -ENOMEM on failure/insufficient address space
3696 * 0 on no addresses written
3697 * X on writing X addresses to the RAR table
68d480c4
AD		 3698 **/
3699static int igb_write_uc_addr_list(struct net_device *netdev)
3700{
3701 struct igb_adapter *adapter = netdev_priv(netdev);
3702 struct e1000_hw *hw = &adapter->hw;
3703 unsigned int vfn = adapter->vfs_allocated_count;
3704 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3705 int count = 0;
3706
3707 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3708 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3709 return -ENOMEM;
9d5c8243 3710
32e7bfc4 3711 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3712 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3713
3714 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3715 if (!rar_entries)
3716 break;
26ad9178 3717 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3718 rar_entries--,
3719 vfn);
68d480c4 3720 count++;
ff41f8dc
AD		 3721 }
3722 }
3723 /* write the addresses in reverse order to avoid write combining */
3724 for (; rar_entries > 0 ; rar_entries--) {
3725 wr32(E1000_RAH(rar_entries), 0);
3726 wr32(E1000_RAL(rar_entries), 0);
3727 }
3728 wrfl();
3729
68d480c4
AD		 3730 return count;
3731}
3732
3733/**
b980ac18
JK		 3734 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3735 * @netdev: network interface device structure
68d480c4 3736 *
b980ac18
JK		 3737 * The set_rx_mode entry point is called whenever the unicast or multicast
3738 * address lists or the network interface flags are updated. This routine is
3739 * responsible for configuring the hardware for proper unicast, multicast,
3740 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3741 **/
3742static void igb_set_rx_mode(struct net_device *netdev)
3743{
3744 struct igb_adapter *adapter = netdev_priv(netdev);
3745 struct e1000_hw *hw = &adapter->hw;
3746 unsigned int vfn = adapter->vfs_allocated_count;
3747 u32 rctl, vmolr = 0;
3748 int count;
3749
3750 /* Check for Promiscuous and All Multicast modes */
3751 rctl = rd32(E1000_RCTL);
3752
3753 /* clear the effected bits */
3754 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3755
3756 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3757 /* retain VLAN HW filtering if in VT mode */
7e44892c 3758 if (adapter->vfs_allocated_count)
6f3dc319 3759 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3760 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3761 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3762 } else {
3763 if (netdev->flags & IFF_ALLMULTI) {
3764 rctl |= E1000_RCTL_MPE;
3765 vmolr |= E1000_VMOLR_MPME;
3766 } else {
b980ac18 3767 /* Write addresses to the MTA, if the attempt fails
25985edc 3768 * then we should just turn on promiscuous mode so
68d480c4
AD		 3769 * that we can at least receive multicast traffic
3770 */
3771 count = igb_write_mc_addr_list(netdev);
3772 if (count < 0) {
3773 rctl |= E1000_RCTL_MPE;
3774 vmolr |= E1000_VMOLR_MPME;
3775 } else if (count) {
3776 vmolr |= E1000_VMOLR_ROMPE;
3777 }
3778 }
b980ac18 3779 /* Write addresses to available RAR registers, if there is not
68d480c4 3780 * sufficient space to store all the addresses then enable
25985edc 3781 * unicast promiscuous mode
68d480c4
AD		 3782 */
3783 count = igb_write_uc_addr_list(netdev);
3784 if (count < 0) {
3785 rctl |= E1000_RCTL_UPE;
3786 vmolr |= E1000_VMOLR_ROPE;
3787 }
3788 rctl |= E1000_RCTL_VFE;
28fc06f5 3789 }
68d480c4 3790 wr32(E1000_RCTL, rctl);
28fc06f5 3791
b980ac18 3792 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3793 * the VMOLR to enable the appropriate modes. Without this workaround
3794 * we will have issues with VLAN tag stripping not being done for frames
3795 * that are only arriving because we are the default pool
3796 */
f96a8a0b 3797 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3798 return;
9d5c8243 3799
68d480c4 3800 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3801 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3802 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3803 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3804}
3805
13800469
GR		 3806static void igb_check_wvbr(struct igb_adapter *adapter)
3807{
3808 struct e1000_hw *hw = &adapter->hw;
3809 u32 wvbr = 0;
3810
3811 switch (hw->mac.type) {
3812 case e1000_82576:
3813 case e1000_i350:
3814 if (!(wvbr = rd32(E1000_WVBR)))
3815 return;
3816 break;
3817 default:
3818 break;
3819 }
3820
3821 adapter->wvbr |= wvbr;
3822}
3823
3824#define IGB_STAGGERED_QUEUE_OFFSET 8
3825
3826static void igb_spoof_check(struct igb_adapter *adapter)
3827{
3828 int j;
3829
3830 if (!adapter->wvbr)
3831 return;
3832
3833 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3834 if (adapter->wvbr & (1 << j) ||
3835 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3836 dev_warn(&adapter->pdev->dev,
3837 "Spoof event(s) detected on VF %d\n", j);
3838 adapter->wvbr &=
3839 ~((1 << j) |
3840 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3841 }
3842 }
3843}
3844
9d5c8243 3845/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3846 * the phy
3847 */
9d5c8243
AK		 3848static void igb_update_phy_info(unsigned long data)
3849{
3850 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3851 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3852}
3853
4d6b725e 3854/**
b980ac18
JK		 3855 * igb_has_link - check shared code for link and determine up/down
3856 * @adapter: pointer to driver private info
4d6b725e 3857 **/
3145535a 3858bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3859{
3860 struct e1000_hw *hw = &adapter->hw;
3861 bool link_active = false;
4d6b725e
AD		 3862
3863 /* get_link_status is set on LSC (link status) interrupt or
3864 * rx sequence error interrupt. get_link_status will stay
3865 * false until the e1000_check_for_link establishes link
3866 * for copper adapters ONLY
3867 */
3868 switch (hw->phy.media_type) {
3869 case e1000_media_type_copper:
e5c3370f
AA		 3870 if (!hw->mac.get_link_status)
3871 return true;
4d6b725e 3872 case e1000_media_type_internal_serdes:
e5c3370f
AA		 3873 hw->mac.ops.check_for_link(hw);
3874 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 3875 break;
3876 default:
3877 case e1000_media_type_unknown:
3878 break;
3879 }
3880
aa9b8cc4
AA		 3881 if (((hw->mac.type == e1000_i210) ||
3882 (hw->mac.type == e1000_i211)) &&
3883 (hw->phy.id == I210_I_PHY_ID)) {
3884 if (!netif_carrier_ok(adapter->netdev)) {
3885 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3886 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
3887 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
3888 adapter->link_check_timeout = jiffies;
3889 }
3890 }
3891
4d6b725e
AD		 3892 return link_active;
3893}
3894
563988dc
SA		 3895static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3896{
3897 bool ret = false;
3898 u32 ctrl_ext, thstat;
3899
f96a8a0b 3900 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3901 if (hw->mac.type == e1000_i350) {
3902 thstat = rd32(E1000_THSTAT);
3903 ctrl_ext = rd32(E1000_CTRL_EXT);
3904
3905 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3906 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3907 ret = !!(thstat & event);
563988dc
SA		 3908 }
3909
3910 return ret;
3911}
3912
9d5c8243 3913/**
b980ac18
JK		 3914 * igb_watchdog - Timer Call-back
3915 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3916 **/
3917static void igb_watchdog(unsigned long data)
3918{
3919 struct igb_adapter *adapter = (struct igb_adapter *)data;
3920 /* Do the rest outside of interrupt context */
3921 schedule_work(&adapter->watchdog_task);
3922}
3923
3924static void igb_watchdog_task(struct work_struct *work)
3925{
3926 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3927 struct igb_adapter,
3928 watchdog_task);
9d5c8243 3929 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3930 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3931 struct net_device *netdev = adapter->netdev;
563988dc 3932 u32 link;
7a6ea550 3933 int i;
9d5c8243 3934
4d6b725e 3935 link = igb_has_link(adapter);
aa9b8cc4
AA		 3936
3937 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
3938 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
3939 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3940 else
3941 link = false;
3942 }
3943
9d5c8243 3944 if (link) {
2bdfc4e2
CW		 3945 /* Perform a reset if the media type changed. */
3946 if (hw->dev_spec._82575.media_changed) {
3947 hw->dev_spec._82575.media_changed = false;
3948 adapter->flags |= IGB_FLAG_MEDIA_RESET;
3949 igb_reset(adapter);
3950 }
749ab2cd
YZ		 3951 /* Cancel scheduled suspend requests. */
3952 pm_runtime_resume(netdev->dev.parent);
3953
9d5c8243
AK		 3954 if (!netif_carrier_ok(netdev)) {
3955 u32 ctrl;
330a6d6a 3956 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3957 &adapter->link_speed,
3958 &adapter->link_duplex);
9d5c8243
AK		 3959
3960 ctrl = rd32(E1000_CTRL);
527d47c1 3961 /* Links status message must follow this format */
876d2d6f
JK		 3962 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3963 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3964 netdev->name,
3965 adapter->link_speed,
3966 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3967 "Full" : "Half",
3968 (ctrl & E1000_CTRL_TFCE) &&
3969 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3970 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3971 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3972
c0ba4778
KS		 3973 /* check if SmartSpeed worked */
3974 igb_check_downshift(hw);
3975 if (phy->speed_downgraded)
3976 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3977
563988dc 3978 /* check for thermal sensor event */
876d2d6f
JK		 3979 if (igb_thermal_sensor_event(hw,
3980 E1000_THSTAT_LINK_THROTTLE)) {
3981 netdev_info(netdev, "The network adapter link "
3982 "speed was downshifted because it "
3983 "overheated\n");
7ef5ed1c 3984 }
563988dc 3985
d07f3e37 3986 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3987 adapter->tx_timeout_factor = 1;
3988 switch (adapter->link_speed) {
3989 case SPEED_10:
9d5c8243
AK		 3990 adapter->tx_timeout_factor = 14;
3991 break;
3992 case SPEED_100:
9d5c8243
AK		 3993 /* maybe add some timeout factor ? */
3994 break;
3995 }
3996
3997 netif_carrier_on(netdev);
9d5c8243 3998
4ae196df 3999 igb_ping_all_vfs(adapter);
17dc566c 4000 igb_check_vf_rate_limit(adapter);
4ae196df 4001
4b1a9877 4002 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4003 if (!test_bit(__IGB_DOWN, &adapter->state))
4004 mod_timer(&adapter->phy_info_timer,
4005 round_jiffies(jiffies + 2 * HZ));
4006 }
4007 } else {
4008 if (netif_carrier_ok(netdev)) {
4009 adapter->link_speed = 0;
4010 adapter->link_duplex = 0;
563988dc
SA		 4011
4012 /* check for thermal sensor event */
876d2d6f
JK		 4013 if (igb_thermal_sensor_event(hw,
4014 E1000_THSTAT_PWR_DOWN)) {
4015 netdev_err(netdev, "The network adapter was "
4016 "stopped because it overheated\n");
7ef5ed1c 4017 }
563988dc 4018
527d47c1
AD		 4019 /* Links status message must follow this format */
4020 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4021 netdev->name);
9d5c8243 4022 netif_carrier_off(netdev);
4b1a9877 4023
4ae196df
AD		 4024 igb_ping_all_vfs(adapter);
4025
4b1a9877 4026 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4027 if (!test_bit(__IGB_DOWN, &adapter->state))
4028 mod_timer(&adapter->phy_info_timer,
4029 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 4030
4031 pm_schedule_suspend(netdev->dev.parent,
4032 MSEC_PER_SEC * 5);
9d5c8243
AK		 4033 }
4034 }
4035
12dcd86b
ED		 4036 spin_lock(&adapter->stats64_lock);
4037 igb_update_stats(adapter, &adapter->stats64);
4038 spin_unlock(&adapter->stats64_lock);
9d5c8243 4039
dbabb065 4040 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4041 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4042 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4043 /* We've lost link, so the controller stops DMA,
4044 * but we've got queued Tx work that's never going
4045 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4046 * (Do the reset outside of interrupt context).
4047 */
dbabb065
AD		 4048 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4049 adapter->tx_timeout_count++;
4050 schedule_work(&adapter->reset_task);
4051 /* return immediately since reset is imminent */
4052 return;
4053 }
9d5c8243 4054 }
9d5c8243 4055
dbabb065 4056 /* Force detection of hung controller every watchdog period */
6d095fa8 4057 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4058 }
f7ba205e 4059
b980ac18 4060 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4061 if (adapter->msix_entries) {
047e0030 4062 u32 eics = 0;
0d1ae7f4
AD		 4063 for (i = 0; i < adapter->num_q_vectors; i++)
4064 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4065 wr32(E1000_EICS, eics);
4066 } else {
4067 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4068 }
9d5c8243 4069
13800469 4070 igb_spoof_check(adapter);
fc580751 4071 igb_ptp_rx_hang(adapter);
13800469 4072
9d5c8243 4073 /* Reset the timer */
aa9b8cc4
AA		 4074 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4075 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4076 mod_timer(&adapter->watchdog_timer,
4077 round_jiffies(jiffies + HZ));
4078 else
4079 mod_timer(&adapter->watchdog_timer,
4080 round_jiffies(jiffies + 2 * HZ));
4081 }
9d5c8243
AK		 4082}
4083
4084enum latency_range {
4085 lowest_latency = 0,
4086 low_latency = 1,
4087 bulk_latency = 2,
4088 latency_invalid = 255
4089};
4090
6eb5a7f1 4091/**
b980ac18
JK		 4092 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4093 * @q_vector: pointer to q_vector
6eb5a7f1 4094 *
b980ac18
JK		 4095 * Stores a new ITR value based on strictly on packet size. This
4096 * algorithm is less sophisticated than that used in igb_update_itr,
4097 * due to the difficulty of synchronizing statistics across multiple
4098 * receive rings. The divisors and thresholds used by this function
4099 * were determined based on theoretical maximum wire speed and testing
4100 * data, in order to minimize response time while increasing bulk
4101 * throughput.
4102 * This functionality is controlled by the InterruptThrottleRate module
4103 * parameter (see igb_param.c)
4104 * NOTE: This function is called only when operating in a multiqueue
4105 * receive environment.
6eb5a7f1 4106 **/
047e0030 4107static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4108{
047e0030 4109 int new_val = q_vector->itr_val;
6eb5a7f1 4110 int avg_wire_size = 0;
047e0030 4111 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4112 unsigned int packets;
9d5c8243 4113
6eb5a7f1
AD		 4114 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4115 * ints/sec - ITR timer value of 120 ticks.
4116 */
4117 if (adapter->link_speed != SPEED_1000) {
0ba82994 4118 new_val = IGB_4K_ITR;
6eb5a7f1 4119 goto set_itr_val;
9d5c8243 4120 }
047e0030 4121
0ba82994
AD		 4122 packets = q_vector->rx.total_packets;
4123 if (packets)
4124 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4125
0ba82994
AD		 4126 packets = q_vector->tx.total_packets;
4127 if (packets)
4128 avg_wire_size = max_t(u32, avg_wire_size,
4129 q_vector->tx.total_bytes / packets);
047e0030
AD		 4130
4131 /* if avg_wire_size isn't set no work was done */
4132 if (!avg_wire_size)
4133 goto clear_counts;
9d5c8243 4134
6eb5a7f1
AD		 4135 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4136 avg_wire_size += 24;
4137
4138 /* Don't starve jumbo frames */
4139 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4140
6eb5a7f1
AD		 4141 /* Give a little boost to mid-size frames */
4142 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4143 new_val = avg_wire_size / 3;
4144 else
4145 new_val = avg_wire_size / 2;
9d5c8243 4146
0ba82994
AD		 4147 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4148 if (new_val < IGB_20K_ITR &&
4149 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4150 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4151 new_val = IGB_20K_ITR;
abe1c363 4152
6eb5a7f1 4153set_itr_val:
047e0030
AD		 4154 if (new_val != q_vector->itr_val) {
4155 q_vector->itr_val = new_val;
4156 q_vector->set_itr = 1;
9d5c8243 4157 }
6eb5a7f1 4158clear_counts:
0ba82994
AD		 4159 q_vector->rx.total_bytes = 0;
4160 q_vector->rx.total_packets = 0;
4161 q_vector->tx.total_bytes = 0;
4162 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4163}
4164
4165/**
b980ac18
JK		 4166 * igb_update_itr - update the dynamic ITR value based on statistics
4167 * @q_vector: pointer to q_vector
4168 * @ring_container: ring info to update the itr for
4169 *
4170 * Stores a new ITR value based on packets and byte
4171 * counts during the last interrupt. The advantage of per interrupt
4172 * computation is faster updates and more accurate ITR for the current
4173 * traffic pattern. Constants in this function were computed
4174 * based on theoretical maximum wire speed and thresholds were set based
4175 * on testing data as well as attempting to minimize response time
4176 * while increasing bulk throughput.
4177 * this functionality is controlled by the InterruptThrottleRate module
4178 * parameter (see igb_param.c)
4179 * NOTE: These calculations are only valid when operating in a single-
4180 * queue environment.
9d5c8243 4181 **/
0ba82994
AD		 4182static void igb_update_itr(struct igb_q_vector *q_vector,
4183 struct igb_ring_container *ring_container)
9d5c8243 4184{
0ba82994
AD		 4185 unsigned int packets = ring_container->total_packets;
4186 unsigned int bytes = ring_container->total_bytes;
4187 u8 itrval = ring_container->itr;
9d5c8243 4188
0ba82994 4189 /* no packets, exit with status unchanged */
9d5c8243 4190 if (packets == 0)
0ba82994 4191 return;
9d5c8243 4192
0ba82994 4193 switch (itrval) {
9d5c8243
AK		 4194 case lowest_latency:
4195 /* handle TSO and jumbo frames */
4196 if (bytes/packets > 8000)
0ba82994 4197 itrval = bulk_latency;
9d5c8243 4198 else if ((packets < 5) && (bytes > 512))
0ba82994 4199 itrval = low_latency;
9d5c8243
AK		 4200 break;
4201 case low_latency: /* 50 usec aka 20000 ints/s */
4202 if (bytes > 10000) {
4203 /* this if handles the TSO accounting */
4204 if (bytes/packets > 8000) {
0ba82994 4205 itrval = bulk_latency;
9d5c8243 4206 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4207 itrval = bulk_latency;
9d5c8243 4208 } else if ((packets > 35)) {
0ba82994 4209 itrval = lowest_latency;
9d5c8243
AK		 4210 }
4211 } else if (bytes/packets > 2000) {
0ba82994 4212 itrval = bulk_latency;
9d5c8243 4213 } else if (packets <= 2 && bytes < 512) {
0ba82994 4214 itrval = lowest_latency;
9d5c8243
AK		 4215 }
4216 break;
4217 case bulk_latency: /* 250 usec aka 4000 ints/s */
4218 if (bytes > 25000) {
4219 if (packets > 35)
0ba82994 4220 itrval = low_latency;
1e5c3d21 4221 } else if (bytes < 1500) {
0ba82994 4222 itrval = low_latency;
9d5c8243
AK		 4223 }
4224 break;
4225 }
4226
0ba82994
AD		 4227 /* clear work counters since we have the values we need */
4228 ring_container->total_bytes = 0;
4229 ring_container->total_packets = 0;
4230
4231 /* write updated itr to ring container */
4232 ring_container->itr = itrval;
9d5c8243
AK		 4233}
4234
0ba82994 4235static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4236{
0ba82994 4237 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4238 u32 new_itr = q_vector->itr_val;
0ba82994 4239 u8 current_itr = 0;
9d5c8243
AK		 4240
4241 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4242 if (adapter->link_speed != SPEED_1000) {
4243 current_itr = 0;
0ba82994 4244 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4245 goto set_itr_now;
4246 }
4247
0ba82994
AD		 4248 igb_update_itr(q_vector, &q_vector->tx);
4249 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4250
0ba82994 4251 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4252
6eb5a7f1 4253 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4254 if (current_itr == lowest_latency &&
4255 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4256 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4257 current_itr = low_latency;
4258
9d5c8243
AK		 4259 switch (current_itr) {
4260 /* counts and packets in update_itr are dependent on these numbers */
4261 case lowest_latency:
0ba82994 4262 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4263 break;
4264 case low_latency:
0ba82994 4265 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4266 break;
4267 case bulk_latency:
0ba82994 4268 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4269 break;
4270 default:
4271 break;
4272 }
4273
4274set_itr_now:
047e0030 4275 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4276 /* this attempts to bias the interrupt rate towards Bulk
4277 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4278 * increasing
4279 */
047e0030 4280 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4281 max((new_itr * q_vector->itr_val) /
4282 (new_itr + (q_vector->itr_val >> 2)),
4283 new_itr) : new_itr;
9d5c8243
AK		 4284 /* Don't write the value here; it resets the adapter's
4285 * internal timer, and causes us to delay far longer than
4286 * we should between interrupts. Instead, we write the ITR
4287 * value at the beginning of the next interrupt so the timing
4288 * ends up being correct.
4289 */
047e0030
AD		 4290 q_vector->itr_val = new_itr;
4291 q_vector->set_itr = 1;
9d5c8243 4292 }
9d5c8243
AK		 4293}
4294
c50b52a0
SH		 4295static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4296 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4297{
4298 struct e1000_adv_tx_context_desc *context_desc;
4299 u16 i = tx_ring->next_to_use;
4300
4301 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4302
4303 i++;
4304 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4305
4306 /* set bits to identify this as an advanced context descriptor */
4307 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4308
4309 /* For 82575, context index must be unique per ring. */
866cff06 4310 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4311 mss_l4len_idx |= tx_ring->reg_idx << 4;
4312
4313 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4314 context_desc->seqnum_seed = 0;
4315 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4316 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4317}
4318
7af40ad9
AD		 4319static int igb_tso(struct igb_ring *tx_ring,
4320 struct igb_tx_buffer *first,
4321 u8 *hdr_len)
9d5c8243 4322{
7af40ad9 4323 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4324 u32 vlan_macip_lens, type_tucmd;
4325 u32 mss_l4len_idx, l4len;
4326
ed6aa105
AD		 4327 if (skb->ip_summed != CHECKSUM_PARTIAL)
4328 return 0;
4329
7d13a7d0
AD		 4330 if (!skb_is_gso(skb))
4331 return 0;
9d5c8243
AK		 4332
4333 if (skb_header_cloned(skb)) {
7af40ad9 4334 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4335 if (err)
4336 return err;
4337 }
4338
7d13a7d0
AD		 4339 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4340 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4341
7af40ad9 4342 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4343 struct iphdr *iph = ip_hdr(skb);
4344 iph->tot_len = 0;
4345 iph->check = 0;
4346 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4347 iph->daddr, 0,
4348 IPPROTO_TCP,
4349 0);
7d13a7d0 4350 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4351 first->tx_flags |= IGB_TX_FLAGS_TSO |
4352 IGB_TX_FLAGS_CSUM |
4353 IGB_TX_FLAGS_IPV4;
8e1e8a47 4354 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4355 ipv6_hdr(skb)->payload_len = 0;
4356 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4357 &ipv6_hdr(skb)->daddr,
4358 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4359 first->tx_flags |= IGB_TX_FLAGS_TSO |
4360 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4361 }
4362
7af40ad9 4363 /* compute header lengths */
7d13a7d0
AD		 4364 l4len = tcp_hdrlen(skb);
4365 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4366
7af40ad9
AD		 4367 /* update gso size and bytecount with header size */
4368 first->gso_segs = skb_shinfo(skb)->gso_segs;
4369 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4370
9d5c8243 4371 /* MSS L4LEN IDX */
7d13a7d0
AD		 4372 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4373 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4374
7d13a7d0
AD		 4375 /* VLAN MACLEN IPLEN */
4376 vlan_macip_lens = skb_network_header_len(skb);
4377 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4378 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4379
7d13a7d0 4380 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4381
7d13a7d0 4382 return 1;
9d5c8243
AK		 4383}
4384
7af40ad9 4385static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4386{
7af40ad9 4387 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4388 u32 vlan_macip_lens = 0;
4389 u32 mss_l4len_idx = 0;
4390 u32 type_tucmd = 0;
9d5c8243 4391
7d13a7d0 4392 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4393 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4394 return;
7d13a7d0
AD		 4395 } else {
4396 u8 l4_hdr = 0;
7af40ad9 4397 switch (first->protocol) {
7d13a7d0
AD		 4398 case __constant_htons(ETH_P_IP):
4399 vlan_macip_lens |= skb_network_header_len(skb);
4400 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4401 l4_hdr = ip_hdr(skb)->protocol;
4402 break;
4403 case __constant_htons(ETH_P_IPV6):
4404 vlan_macip_lens |= skb_network_header_len(skb);
4405 l4_hdr = ipv6_hdr(skb)->nexthdr;
4406 break;
4407 default:
4408 if (unlikely(net_ratelimit())) {
4409 dev_warn(tx_ring->dev,
b980ac18
JK		 4410 "partial checksum but proto=%x!\n",
4411 first->protocol);
fa4a7ef3 4412 }
7d13a7d0
AD		 4413 break;
4414 }
fa4a7ef3 4415
7d13a7d0
AD		 4416 switch (l4_hdr) {
4417 case IPPROTO_TCP:
4418 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4419 mss_l4len_idx = tcp_hdrlen(skb) <<
4420 E1000_ADVTXD_L4LEN_SHIFT;
4421 break;
4422 case IPPROTO_SCTP:
4423 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4424 mss_l4len_idx = sizeof(struct sctphdr) <<
4425 E1000_ADVTXD_L4LEN_SHIFT;
4426 break;
4427 case IPPROTO_UDP:
4428 mss_l4len_idx = sizeof(struct udphdr) <<
4429 E1000_ADVTXD_L4LEN_SHIFT;
4430 break;
4431 default:
4432 if (unlikely(net_ratelimit())) {
4433 dev_warn(tx_ring->dev,
b980ac18
JK		 4434 "partial checksum but l4 proto=%x!\n",
4435 l4_hdr);
44b0cda3 4436 }
7d13a7d0 4437 break;
9d5c8243 4438 }
7af40ad9
AD		 4439
4440 /* update TX checksum flag */
4441 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4442 }
9d5c8243 4443
7d13a7d0 4444 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4445 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4446
7d13a7d0 4447 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4448}
4449
1d9daf45
AD		 4450#define IGB_SET_FLAG(_input, _flag, _result) \
4451 ((_flag <= _result) ? \
4452 ((u32)(_input & _flag) * (_result / _flag)) : \
4453 ((u32)(_input & _flag) / (_flag / _result)))
4454
4455static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4456{
4457 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4458 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4459 E1000_ADVTXD_DCMD_DEXT |
4460 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4461
4462 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4463 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4464 (E1000_ADVTXD_DCMD_VLE));
4465
4466 /* set segmentation bits for TSO */
4467 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4468 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4469
4470 /* set timestamp bit if present */
1d9daf45
AD		 4471 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4472 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4473
1d9daf45
AD		 4474 /* insert frame checksum */
4475 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4476
4477 return cmd_type;
4478}
4479
7af40ad9
AD		 4480static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4481 union e1000_adv_tx_desc *tx_desc,
4482 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4483{
4484 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4485
1d9daf45
AD		 4486 /* 82575 requires a unique index per ring */
4487 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4488 olinfo_status |= tx_ring->reg_idx << 4;
4489
4490 /* insert L4 checksum */
1d9daf45
AD		 4491 olinfo_status |= IGB_SET_FLAG(tx_flags,
4492 IGB_TX_FLAGS_CSUM,
4493 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4494
1d9daf45
AD		 4495 /* insert IPv4 checksum */
4496 olinfo_status |= IGB_SET_FLAG(tx_flags,
4497 IGB_TX_FLAGS_IPV4,
4498 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4499
7af40ad9 4500 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4501}
4502
7af40ad9
AD		 4503static void igb_tx_map(struct igb_ring *tx_ring,
4504 struct igb_tx_buffer *first,
ebe42d16 4505 const u8 hdr_len)
9d5c8243 4506{
7af40ad9 4507 struct sk_buff *skb = first->skb;
c9f14bf3 4508 struct igb_tx_buffer *tx_buffer;
ebe42d16 4509 union e1000_adv_tx_desc *tx_desc;
80d0759e 4510 struct skb_frag_struct *frag;
ebe42d16 4511 dma_addr_t dma;
80d0759e 4512 unsigned int data_len, size;
7af40ad9 4513 u32 tx_flags = first->tx_flags;
1d9daf45 4514 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4515 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4516
4517 tx_desc = IGB_TX_DESC(tx_ring, i);
4518
80d0759e
AD		 4519 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4520
4521 size = skb_headlen(skb);
4522 data_len = skb->data_len;
ebe42d16
AD		 4523
4524 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4525
80d0759e
AD		 4526 tx_buffer = first;
4527
4528 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4529 if (dma_mapping_error(tx_ring->dev, dma))
4530 goto dma_error;
4531
4532 /* record length, and DMA address */
4533 dma_unmap_len_set(tx_buffer, len, size);
4534 dma_unmap_addr_set(tx_buffer, dma, dma);
4535
4536 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4537
ebe42d16
AD		 4538 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4539 tx_desc->read.cmd_type_len =
1d9daf45 4540 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4541
4542 i++;
4543 tx_desc++;
4544 if (i == tx_ring->count) {
4545 tx_desc = IGB_TX_DESC(tx_ring, 0);
4546 i = 0;
4547 }
80d0759e 4548 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4549
4550 dma += IGB_MAX_DATA_PER_TXD;
4551 size -= IGB_MAX_DATA_PER_TXD;
4552
ebe42d16
AD		 4553 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4554 }
4555
4556 if (likely(!data_len))
4557 break;
2bbfebe2 4558
1d9daf45 4559 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4560
65689fef 4561 i++;
ebe42d16
AD		 4562 tx_desc++;
4563 if (i == tx_ring->count) {
4564 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4565 i = 0;
ebe42d16 4566 }
80d0759e 4567 tx_desc->read.olinfo_status = 0;
65689fef 4568
9e903e08 4569 size = skb_frag_size(frag);
ebe42d16
AD		 4570 data_len -= size;
4571
4572 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4573 size, DMA_TO_DEVICE);
6366ad33 4574
c9f14bf3 4575 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4576 }
4577
ebe42d16 4578 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4579 cmd_type |= size | IGB_TXD_DCMD;
4580 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4581
80d0759e
AD		 4582 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4583
8542db05
AD		 4584 /* set the timestamp */
4585 first->time_stamp = jiffies;
4586
b980ac18 4587 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4588 * are new descriptors to fetch. (Only applicable for weak-ordered
4589 * memory model archs, such as IA-64).
4590 *
4591 * We also need this memory barrier to make certain all of the
4592 * status bits have been updated before next_to_watch is written.
4593 */
4594 wmb();
4595
8542db05 4596 /* set next_to_watch value indicating a packet is present */
ebe42d16 4597 first->next_to_watch = tx_desc;
9d5c8243 4598
ebe42d16
AD		 4599 i++;
4600 if (i == tx_ring->count)
4601 i = 0;
6366ad33 4602
ebe42d16 4603 tx_ring->next_to_use = i;
6366ad33 4604
ebe42d16 4605 writel(i, tx_ring->tail);
6366ad33 4606
ebe42d16 4607 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4608 * at a time, it synchronizes IO on IA64/Altix systems
4609 */
ebe42d16
AD		 4610 mmiowb();
4611
4612 return;
4613
4614dma_error:
4615 dev_err(tx_ring->dev, "TX DMA map failed\n");
4616
4617 /* clear dma mappings for failed tx_buffer_info map */
4618 for (;;) {
c9f14bf3
AD		 4619 tx_buffer = &tx_ring->tx_buffer_info[i];
4620 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4621 if (tx_buffer == first)
ebe42d16 4622 break;
a77ff709
NN		 4623 if (i == 0)
4624 i = tx_ring->count;
6366ad33 4625 i--;
6366ad33
AD		 4626 }
4627
9d5c8243 4628 tx_ring->next_to_use = i;
9d5c8243
AK		 4629}
4630
6ad4edfc 4631static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4632{
e694e964
AD		 4633 struct net_device *netdev = tx_ring->netdev;
4634
661086df 4635 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4636
9d5c8243
AK		 4637 /* Herbert's original patch had:
4638 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4639 * but since that doesn't exist yet, just open code it.
4640 */
9d5c8243
AK		 4641 smp_mb();
4642
4643 /* We need to check again in a case another CPU has just
b980ac18
JK		 4644 * made room available.
4645 */
c493ea45 4646 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4647 return -EBUSY;
4648
4649 /* A reprieve! */
661086df 4650 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4651
4652 u64_stats_update_begin(&tx_ring->tx_syncp2);
4653 tx_ring->tx_stats.restart_queue2++;
4654 u64_stats_update_end(&tx_ring->tx_syncp2);
4655
9d5c8243
AK		 4656 return 0;
4657}
4658
6ad4edfc 4659static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4660{
c493ea45 4661 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4662 return 0;
e694e964 4663 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4664}
4665
cd392f5c
AD		 4666netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4667 struct igb_ring *tx_ring)
9d5c8243 4668{
8542db05 4669 struct igb_tx_buffer *first;
ebe42d16 4670 int tso;
91d4ee33 4671 u32 tx_flags = 0;
21ba6fe1 4672 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4673 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4674 u8 hdr_len = 0;
9d5c8243 4675
21ba6fe1
AD		 4676 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4677 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4678 * + 2 desc gap to keep tail from touching head,
9d5c8243 4679 * + 1 desc for context descriptor,
21ba6fe1
AD		 4680 * otherwise try next time
4681 */
4682 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4683 unsigned short f;
4684 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4685 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4686 } else {
4687 count += skb_shinfo(skb)->nr_frags;
4688 }
4689
4690 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4691 /* this is a hard error */
9d5c8243
AK		 4692 return NETDEV_TX_BUSY;
4693 }
33af6bcc 4694
7af40ad9
AD		 4695 /* record the location of the first descriptor for this packet */
4696 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4697 first->skb = skb;
4698 first->bytecount = skb->len;
4699 first->gso_segs = 1;
4700
b66e2397
MV		 4701 skb_tx_timestamp(skb);
4702
b646c22e
AD		 4703 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4704 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4705
b646c22e
AD		 4706 if (!(adapter->ptp_tx_skb)) {
4707 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4708 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4709
4710 adapter->ptp_tx_skb = skb_get(skb);
4711 adapter->ptp_tx_start = jiffies;
4712 if (adapter->hw.mac.type == e1000_82576)
4713 schedule_work(&adapter->ptp_tx_work);
4714 }
33af6bcc 4715 }
9d5c8243 4716
eab6d18d 4717 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4718 tx_flags |= IGB_TX_FLAGS_VLAN;
4719 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4720 }
4721
7af40ad9
AD		 4722 /* record initial flags and protocol */
4723 first->tx_flags = tx_flags;
4724 first->protocol = protocol;
cdfd01fc 4725
7af40ad9
AD		 4726 tso = igb_tso(tx_ring, first, &hdr_len);
4727 if (tso < 0)
7d13a7d0 4728 goto out_drop;
7af40ad9
AD		 4729 else if (!tso)
4730 igb_tx_csum(tx_ring, first);
9d5c8243 4731
7af40ad9 4732 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4733
4734 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4735 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4736
9d5c8243 4737 return NETDEV_TX_OK;
7d13a7d0
AD		 4738
4739out_drop:
7af40ad9
AD		 4740 igb_unmap_and_free_tx_resource(tx_ring, first);
4741
7d13a7d0 4742 return NETDEV_TX_OK;
9d5c8243
AK		 4743}
4744
1cc3bd87
AD		 4745static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4746 struct sk_buff *skb)
4747{
4748 unsigned int r_idx = skb->queue_mapping;
4749
4750 if (r_idx >= adapter->num_tx_queues)
4751 r_idx = r_idx % adapter->num_tx_queues;
4752
4753 return adapter->tx_ring[r_idx];
4754}
4755
cd392f5c
AD		 4756static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4757 struct net_device *netdev)
9d5c8243
AK		 4758{
4759 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4760
4761 if (test_bit(__IGB_DOWN, &adapter->state)) {
4762 dev_kfree_skb_any(skb);
4763 return NETDEV_TX_OK;
4764 }
4765
4766 if (skb->len <= 0) {
4767 dev_kfree_skb_any(skb);
4768 return NETDEV_TX_OK;
4769 }
4770
b980ac18 4771 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4772 * in order to meet this minimum size requirement.
4773 */
ea5ceeab
TD		 4774 if (unlikely(skb->len < 17)) {
4775 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4776 return NETDEV_TX_OK;
4777 skb->len = 17;
ea5ceeab 4778 skb_set_tail_pointer(skb, 17);
1cc3bd87 4779 }
9d5c8243 4780
1cc3bd87 4781 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4782}
4783
4784/**
b980ac18
JK		 4785 * igb_tx_timeout - Respond to a Tx Hang
4786 * @netdev: network interface device structure
9d5c8243
AK		 4787 **/
4788static void igb_tx_timeout(struct net_device *netdev)
4789{
4790 struct igb_adapter *adapter = netdev_priv(netdev);
4791 struct e1000_hw *hw = &adapter->hw;
4792
4793 /* Do the reset outside of interrupt context */
4794 adapter->tx_timeout_count++;
f7ba205e 4795
06218a8d 4796 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4797 hw->dev_spec._82575.global_device_reset = true;
4798
9d5c8243 4799 schedule_work(&adapter->reset_task);
265de409
AD		 4800 wr32(E1000_EICS,
4801 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4802}
4803
4804static void igb_reset_task(struct work_struct *work)
4805{
4806 struct igb_adapter *adapter;
4807 adapter = container_of(work, struct igb_adapter, reset_task);
4808
c97ec42a
TI		 4809 igb_dump(adapter);
4810 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4811 igb_reinit_locked(adapter);
4812}
4813
4814/**
b980ac18
JK		 4815 * igb_get_stats64 - Get System Network Statistics
4816 * @netdev: network interface device structure
4817 * @stats: rtnl_link_stats64 pointer
9d5c8243 4818 **/
12dcd86b 4819static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4820 struct rtnl_link_stats64 *stats)
9d5c8243 4821{
12dcd86b
ED		 4822 struct igb_adapter *adapter = netdev_priv(netdev);
4823
4824 spin_lock(&adapter->stats64_lock);
4825 igb_update_stats(adapter, &adapter->stats64);
4826 memcpy(stats, &adapter->stats64, sizeof(*stats));
4827 spin_unlock(&adapter->stats64_lock);
4828
4829 return stats;
9d5c8243
AK		 4830}
4831
4832/**
b980ac18
JK		 4833 * igb_change_mtu - Change the Maximum Transfer Unit
4834 * @netdev: network interface device structure
4835 * @new_mtu: new value for maximum frame size
9d5c8243 4836 *
b980ac18 4837 * Returns 0 on success, negative on failure
9d5c8243
AK		 4838 **/
4839static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4840{
4841 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4842 struct pci_dev *pdev = adapter->pdev;
153285f9 4843 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4844
c809d227 4845 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4846 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4847 return -EINVAL;
4848 }
4849
153285f9 4850#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4851 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4852 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4853 return -EINVAL;
4854 }
4855
2ccd994c
AD		 4856 /* adjust max frame to be at least the size of a standard frame */
4857 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4858 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4859
9d5c8243
AK		 4860 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4861 msleep(1);
73cd78f1 4862
9d5c8243
AK		 4863 /* igb_down has a dependency on max_frame_size */
4864 adapter->max_frame_size = max_frame;
559e9c49 4865
4c844851
AD		 4866 if (netif_running(netdev))
4867 igb_down(adapter);
9d5c8243 4868
090b1795 4869 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4870 netdev->mtu, new_mtu);
4871 netdev->mtu = new_mtu;
4872
4873 if (netif_running(netdev))
4874 igb_up(adapter);
4875 else
4876 igb_reset(adapter);
4877
4878 clear_bit(__IGB_RESETTING, &adapter->state);
4879
4880 return 0;
4881}
4882
4883/**
b980ac18
JK		 4884 * igb_update_stats - Update the board statistics counters
4885 * @adapter: board private structure
9d5c8243 4886 **/
12dcd86b
ED		 4887void igb_update_stats(struct igb_adapter *adapter,
4888 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4889{
4890 struct e1000_hw *hw = &adapter->hw;
4891 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4892 u32 reg, mpc;
9d5c8243 4893 u16 phy_tmp;
3f9c0164
AD		 4894 int i;
4895 u64 bytes, packets;
12dcd86b
ED		 4896 unsigned int start;
4897 u64 _bytes, _packets;
9d5c8243
AK		 4898
4899#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4900
b980ac18 4901 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4902 * connection is down.
4903 */
4904 if (adapter->link_speed == 0)
4905 return;
4906 if (pci_channel_offline(pdev))
4907 return;
4908
3f9c0164
AD		 4909 bytes = 0;
4910 packets = 0;
7f90128e
AA		 4911
4912 rcu_read_lock();
3f9c0164 4913 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4914 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4915 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4916
ae1c07a6
AD		 4917 if (rqdpc) {
4918 ring->rx_stats.drops += rqdpc;
4919 net_stats->rx_fifo_errors += rqdpc;
4920 }
12dcd86b
ED		 4921
4922 do {
4923 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4924 _bytes = ring->rx_stats.bytes;
4925 _packets = ring->rx_stats.packets;
4926 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4927 bytes += _bytes;
4928 packets += _packets;
3f9c0164
AD		 4929 }
4930
128e45eb
AD		 4931 net_stats->rx_bytes = bytes;
4932 net_stats->rx_packets = packets;
3f9c0164
AD		 4933
4934 bytes = 0;
4935 packets = 0;
4936 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4937 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4938 do {
4939 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4940 _bytes = ring->tx_stats.bytes;
4941 _packets = ring->tx_stats.packets;
4942 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4943 bytes += _bytes;
4944 packets += _packets;
3f9c0164 4945 }
128e45eb
AD		 4946 net_stats->tx_bytes = bytes;
4947 net_stats->tx_packets = packets;
7f90128e 4948 rcu_read_unlock();
3f9c0164
AD		 4949
4950 /* read stats registers */
9d5c8243
AK		 4951 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4952 adapter->stats.gprc += rd32(E1000_GPRC);
4953 adapter->stats.gorc += rd32(E1000_GORCL);
4954 rd32(E1000_GORCH); /* clear GORCL */
4955 adapter->stats.bprc += rd32(E1000_BPRC);
4956 adapter->stats.mprc += rd32(E1000_MPRC);
4957 adapter->stats.roc += rd32(E1000_ROC);
4958
4959 adapter->stats.prc64 += rd32(E1000_PRC64);
4960 adapter->stats.prc127 += rd32(E1000_PRC127);
4961 adapter->stats.prc255 += rd32(E1000_PRC255);
4962 adapter->stats.prc511 += rd32(E1000_PRC511);
4963 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4964 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4965 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4966 adapter->stats.sec += rd32(E1000_SEC);
4967
fa3d9a6d
MW		 4968 mpc = rd32(E1000_MPC);
4969 adapter->stats.mpc += mpc;
4970 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4971 adapter->stats.scc += rd32(E1000_SCC);
4972 adapter->stats.ecol += rd32(E1000_ECOL);
4973 adapter->stats.mcc += rd32(E1000_MCC);
4974 adapter->stats.latecol += rd32(E1000_LATECOL);
4975 adapter->stats.dc += rd32(E1000_DC);
4976 adapter->stats.rlec += rd32(E1000_RLEC);
4977 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4978 adapter->stats.xontxc += rd32(E1000_XONTXC);
4979 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4980 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4981 adapter->stats.fcruc += rd32(E1000_FCRUC);
4982 adapter->stats.gptc += rd32(E1000_GPTC);
4983 adapter->stats.gotc += rd32(E1000_GOTCL);
4984 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4985 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4986 adapter->stats.ruc += rd32(E1000_RUC);
4987 adapter->stats.rfc += rd32(E1000_RFC);
4988 adapter->stats.rjc += rd32(E1000_RJC);
4989 adapter->stats.tor += rd32(E1000_TORH);
4990 adapter->stats.tot += rd32(E1000_TOTH);
4991 adapter->stats.tpr += rd32(E1000_TPR);
4992
4993 adapter->stats.ptc64 += rd32(E1000_PTC64);
4994 adapter->stats.ptc127 += rd32(E1000_PTC127);
4995 adapter->stats.ptc255 += rd32(E1000_PTC255);
4996 adapter->stats.ptc511 += rd32(E1000_PTC511);
4997 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4998 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4999
5000 adapter->stats.mptc += rd32(E1000_MPTC);
5001 adapter->stats.bptc += rd32(E1000_BPTC);
5002
2d0b0f69
NN		 5003 adapter->stats.tpt += rd32(E1000_TPT);
5004 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5005
5006 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5007 /* read internal phy specific stats */
5008 reg = rd32(E1000_CTRL_EXT);
5009 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5010 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5011
5012 /* this stat has invalid values on i210/i211 */
5013 if ((hw->mac.type != e1000_i210) &&
5014 (hw->mac.type != e1000_i211))
5015 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5016 }
5017
9d5c8243
AK		 5018 adapter->stats.tsctc += rd32(E1000_TSCTC);
5019 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5020
5021 adapter->stats.iac += rd32(E1000_IAC);
5022 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5023 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5024 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5025 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5026 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5027 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5028 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5029 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5030
5031 /* Fill out the OS statistics structure */
128e45eb
AD		 5032 net_stats->multicast = adapter->stats.mprc;
5033 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5034
5035 /* Rx Errors */
5036
5037 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5038 * our own version based on RUC and ROC
5039 */
128e45eb 5040 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5041 adapter->stats.crcerrs + adapter->stats.algnerrc +
5042 adapter->stats.ruc + adapter->stats.roc +
5043 adapter->stats.cexterr;
128e45eb
AD		 5044 net_stats->rx_length_errors = adapter->stats.ruc +
5045 adapter->stats.roc;
5046 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5047 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5048 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5049
5050 /* Tx Errors */
128e45eb
AD		 5051 net_stats->tx_errors = adapter->stats.ecol +
5052 adapter->stats.latecol;
5053 net_stats->tx_aborted_errors = adapter->stats.ecol;
5054 net_stats->tx_window_errors = adapter->stats.latecol;
5055 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5056
5057 /* Tx Dropped needs to be maintained elsewhere */
5058
5059 /* Phy Stats */
5060 if (hw->phy.media_type == e1000_media_type_copper) {
5061 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5062 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5063 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5064 adapter->phy_stats.idle_errors += phy_tmp;
5065 }
5066 }
5067
5068 /* Management Stats */
5069 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5070 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5071 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5072
5073 /* OS2BMC Stats */
5074 reg = rd32(E1000_MANC);
5075 if (reg & E1000_MANC_EN_BMC2OS) {
5076 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5077 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5078 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5079 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5080 }
9d5c8243
AK		 5081}
5082
9d5c8243
AK		 5083static irqreturn_t igb_msix_other(int irq, void *data)
5084{
047e0030 5085 struct igb_adapter *adapter = data;
9d5c8243 5086 struct e1000_hw *hw = &adapter->hw;
844290e5 5087 u32 icr = rd32(E1000_ICR);
844290e5 5088 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5089
7f081d40
AD		 5090 if (icr & E1000_ICR_DRSTA)
5091 schedule_work(&adapter->reset_task);
5092
047e0030 5093 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5094 /* HW is reporting DMA is out of sync */
5095 adapter->stats.doosync++;
13800469
GR		 5096 /* The DMA Out of Sync is also indication of a spoof event
5097 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5098 * see if it is really a spoof event.
5099 */
13800469 5100 igb_check_wvbr(adapter);
dda0e083 5101 }
eebbbdba 5102
4ae196df
AD		 5103 /* Check for a mailbox event */
5104 if (icr & E1000_ICR_VMMB)
5105 igb_msg_task(adapter);
5106
5107 if (icr & E1000_ICR_LSC) {
5108 hw->mac.get_link_status = 1;
5109 /* guard against interrupt when we're going down */
5110 if (!test_bit(__IGB_DOWN, &adapter->state))
5111 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5112 }
5113
1f6e8178
MV		 5114 if (icr & E1000_ICR_TS) {
5115 u32 tsicr = rd32(E1000_TSICR);
5116
5117 if (tsicr & E1000_TSICR_TXTS) {
5118 /* acknowledge the interrupt */
5119 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5120 /* retrieve hardware timestamp */
5121 schedule_work(&adapter->ptp_tx_work);
5122 }
5123 }
1f6e8178 5124
844290e5 5125 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5126
5127 return IRQ_HANDLED;
5128}
5129
047e0030 5130static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5131{
26b39276 5132 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5133 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5134
047e0030
AD		 5135 if (!q_vector->set_itr)
5136 return;
73cd78f1 5137
047e0030
AD		 5138 if (!itr_val)
5139 itr_val = 0x4;
661086df 5140
26b39276
AD		 5141 if (adapter->hw.mac.type == e1000_82575)
5142 itr_val |= itr_val << 16;
661086df 5143 else
0ba82994 5144 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5145
047e0030
AD		 5146 writel(itr_val, q_vector->itr_register);
5147 q_vector->set_itr = 0;
6eb5a7f1
AD		 5148}
5149
047e0030 5150static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5151{
047e0030 5152 struct igb_q_vector *q_vector = data;
9d5c8243 5153
047e0030
AD		 5154 /* Write the ITR value calculated from the previous interrupt. */
5155 igb_write_itr(q_vector);
9d5c8243 5156
047e0030 5157 napi_schedule(&q_vector->napi);
844290e5 5158
047e0030 5159 return IRQ_HANDLED;
fe4506b6
JC		 5160}
5161
421e02f0 5162#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5163static void igb_update_tx_dca(struct igb_adapter *adapter,
5164 struct igb_ring *tx_ring,
5165 int cpu)
5166{
5167 struct e1000_hw *hw = &adapter->hw;
5168 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5169
5170 if (hw->mac.type != e1000_82575)
5171 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5172
b980ac18 5173 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5174 * DCA is enabled. This is due to a known issue in some chipsets
5175 * which will cause the DCA tag to be cleared.
5176 */
5177 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5178 E1000_DCA_TXCTRL_DATA_RRO_EN |
5179 E1000_DCA_TXCTRL_DESC_DCA_EN;
5180
5181 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5182}
5183
5184static void igb_update_rx_dca(struct igb_adapter *adapter,
5185 struct igb_ring *rx_ring,
5186 int cpu)
5187{
5188 struct e1000_hw *hw = &adapter->hw;
5189 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5190
5191 if (hw->mac.type != e1000_82575)
5192 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5193
b980ac18 5194 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5195 * DCA is enabled. This is due to a known issue in some chipsets
5196 * which will cause the DCA tag to be cleared.
5197 */
5198 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5199 E1000_DCA_RXCTRL_DESC_DCA_EN;
5200
5201 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5202}
5203
047e0030 5204static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5205{
047e0030 5206 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5207 int cpu = get_cpu();
fe4506b6 5208
047e0030
AD		 5209 if (q_vector->cpu == cpu)
5210 goto out_no_update;
5211
6a05004a
AD		 5212 if (q_vector->tx.ring)
5213 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5214
5215 if (q_vector->rx.ring)
5216 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5217
047e0030
AD		 5218 q_vector->cpu = cpu;
5219out_no_update:
fe4506b6
JC		 5220 put_cpu();
5221}
5222
5223static void igb_setup_dca(struct igb_adapter *adapter)
5224{
7e0e99ef 5225 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5226 int i;
5227
7dfc16fa 5228 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5229 return;
5230
7e0e99ef
AD		 5231 /* Always use CB2 mode, difference is masked in the CB driver. */
5232 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5233
047e0030 5234 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5235 adapter->q_vector[i]->cpu = -1;
5236 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5237 }
5238}
5239
5240static int __igb_notify_dca(struct device *dev, void *data)
5241{
5242 struct net_device *netdev = dev_get_drvdata(dev);
5243 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5244 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5245 struct e1000_hw *hw = &adapter->hw;
5246 unsigned long event = *(unsigned long *)data;
5247
5248 switch (event) {
5249 case DCA_PROVIDER_ADD:
5250 /* if already enabled, don't do it again */
7dfc16fa 5251 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5252 break;
fe4506b6 5253 if (dca_add_requester(dev) == 0) {
bbd98fe4 5254 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5255 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5256 igb_setup_dca(adapter);
5257 break;
5258 }
5259 /* Fall Through since DCA is disabled. */
5260 case DCA_PROVIDER_REMOVE:
7dfc16fa 5261 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5262 /* without this a class_device is left
b980ac18
JK		 5263 * hanging around in the sysfs model
5264 */
fe4506b6 5265 dca_remove_requester(dev);
090b1795 5266 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5267 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5268 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5269 }
5270 break;
5271 }
bbd98fe4 5272
fe4506b6 5273 return 0;
9d5c8243
AK		 5274}
5275
fe4506b6 5276static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5277 void *p)
fe4506b6
JC		 5278{
5279 int ret_val;
5280
5281 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5282 __igb_notify_dca);
fe4506b6
JC		 5283
5284 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5285}
421e02f0 5286#endif /* CONFIG_IGB_DCA */
9d5c8243 5287
0224d663
GR		 5288#ifdef CONFIG_PCI_IOV
5289static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5290{
5291 unsigned char mac_addr[ETH_ALEN];
0224d663 5292
5ac6f91d 5293 eth_zero_addr(mac_addr);
0224d663
GR		 5294 igb_set_vf_mac(adapter, vf, mac_addr);
5295
70ea4783
LL		 5296 /* By default spoof check is enabled for all VFs */
5297 adapter->vf_data[vf].spoofchk_enabled = true;
5298
f557147c 5299 return 0;
0224d663
GR		 5300}
5301
0224d663 5302#endif
4ae196df
AD		 5303static void igb_ping_all_vfs(struct igb_adapter *adapter)
5304{
5305 struct e1000_hw *hw = &adapter->hw;
5306 u32 ping;
5307 int i;
5308
5309 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5310 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5311 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5312 ping |= E1000_VT_MSGTYPE_CTS;
5313 igb_write_mbx(hw, &ping, 1, i);
5314 }
5315}
5316
7d5753f0
AD		 5317static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5318{
5319 struct e1000_hw *hw = &adapter->hw;
5320 u32 vmolr = rd32(E1000_VMOLR(vf));
5321 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5322
d85b9004 5323 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5324 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5325 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5326
5327 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5328 vmolr |= E1000_VMOLR_MPME;
d85b9004 5329 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5330 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5331 } else {
b980ac18 5332 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5333 * flag we need to write the hashes to the MTA as this step
5334 * was previously skipped
5335 */
5336 if (vf_data->num_vf_mc_hashes > 30) {
5337 vmolr |= E1000_VMOLR_MPME;
5338 } else if (vf_data->num_vf_mc_hashes) {
5339 int j;
5340 vmolr |= E1000_VMOLR_ROMPE;
5341 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5342 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5343 }
5344 }
5345
5346 wr32(E1000_VMOLR(vf), vmolr);
5347
5348 /* there are flags left unprocessed, likely not supported */
5349 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5350 return -EINVAL;
5351
5352 return 0;
7d5753f0
AD		 5353}
5354
4ae196df
AD		 5355static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5356 u32 *msgbuf, u32 vf)
5357{
5358 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5359 u16 *hash_list = (u16 *)&msgbuf[1];
5360 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5361 int i;
5362
7d5753f0 5363 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5364 * to this VF for later use to restore when the PF multi cast
5365 * list changes
5366 */
5367 vf_data->num_vf_mc_hashes = n;
5368
7d5753f0
AD		 5369 /* only up to 30 hash values supported */
5370 if (n > 30)
5371 n = 30;
5372
5373 /* store the hashes for later use */
4ae196df 5374 for (i = 0; i < n; i++)
a419aef8 5375 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5376
5377 /* Flush and reset the mta with the new values */
ff41f8dc 5378 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5379
5380 return 0;
5381}
5382
5383static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5384{
5385 struct e1000_hw *hw = &adapter->hw;
5386 struct vf_data_storage *vf_data;
5387 int i, j;
5388
5389 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5390 u32 vmolr = rd32(E1000_VMOLR(i));
5391 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5392
4ae196df 5393 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5394
5395 if ((vf_data->num_vf_mc_hashes > 30) ||
5396 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5397 vmolr |= E1000_VMOLR_MPME;
5398 } else if (vf_data->num_vf_mc_hashes) {
5399 vmolr |= E1000_VMOLR_ROMPE;
5400 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5401 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5402 }
5403 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5404 }
5405}
5406
5407static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5408{
5409 struct e1000_hw *hw = &adapter->hw;
5410 u32 pool_mask, reg, vid;
5411 int i;
5412
5413 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5414
5415 /* Find the vlan filter for this id */
5416 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5417 reg = rd32(E1000_VLVF(i));
5418
5419 /* remove the vf from the pool */
5420 reg &= ~pool_mask;
5421
5422 /* if pool is empty then remove entry from vfta */
5423 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5424 (reg & E1000_VLVF_VLANID_ENABLE)) {
5425 reg = 0;
5426 vid = reg & E1000_VLVF_VLANID_MASK;
5427 igb_vfta_set(hw, vid, false);
5428 }
5429
5430 wr32(E1000_VLVF(i), reg);
5431 }
ae641bdc
AD		 5432
5433 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5434}
5435
5436static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5437{
5438 struct e1000_hw *hw = &adapter->hw;
5439 u32 reg, i;
5440
51466239
AD		 5441 /* The vlvf table only exists on 82576 hardware and newer */
5442 if (hw->mac.type < e1000_82576)
5443 return -1;
5444
5445 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5446 if (!adapter->vfs_allocated_count)
5447 return -1;
5448
5449 /* Find the vlan filter for this id */
5450 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5451 reg = rd32(E1000_VLVF(i));
5452 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5453 vid == (reg & E1000_VLVF_VLANID_MASK))
5454 break;
5455 }
5456
5457 if (add) {
5458 if (i == E1000_VLVF_ARRAY_SIZE) {
5459 /* Did not find a matching VLAN ID entry that was
5460 * enabled. Search for a free filter entry, i.e.
5461 * one without the enable bit set
5462 */
5463 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5464 reg = rd32(E1000_VLVF(i));
5465 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5466 break;
5467 }
5468 }
5469 if (i < E1000_VLVF_ARRAY_SIZE) {
5470 /* Found an enabled/available entry */
5471 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5472
5473 /* if !enabled we need to set this up in vfta */
5474 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5475 /* add VID to filter table */
5476 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5477 reg |= E1000_VLVF_VLANID_ENABLE;
5478 }
cad6d05f
AD		 5479 reg &= ~E1000_VLVF_VLANID_MASK;
5480 reg |= vid;
4ae196df 5481 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5482
5483 /* do not modify RLPML for PF devices */
5484 if (vf >= adapter->vfs_allocated_count)
5485 return 0;
5486
5487 if (!adapter->vf_data[vf].vlans_enabled) {
5488 u32 size;
5489 reg = rd32(E1000_VMOLR(vf));
5490 size = reg & E1000_VMOLR_RLPML_MASK;
5491 size += 4;
5492 reg &= ~E1000_VMOLR_RLPML_MASK;
5493 reg |= size;
5494 wr32(E1000_VMOLR(vf), reg);
5495 }
ae641bdc 5496
51466239 5497 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5498 }
5499 } else {
5500 if (i < E1000_VLVF_ARRAY_SIZE) {
5501 /* remove vf from the pool */
5502 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5503 /* if pool is empty then remove entry from vfta */
5504 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5505 reg = 0;
5506 igb_vfta_set(hw, vid, false);
5507 }
5508 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5509
5510 /* do not modify RLPML for PF devices */
5511 if (vf >= adapter->vfs_allocated_count)
5512 return 0;
5513
5514 adapter->vf_data[vf].vlans_enabled--;
5515 if (!adapter->vf_data[vf].vlans_enabled) {
5516 u32 size;
5517 reg = rd32(E1000_VMOLR(vf));
5518 size = reg & E1000_VMOLR_RLPML_MASK;
5519 size -= 4;
5520 reg &= ~E1000_VMOLR_RLPML_MASK;
5521 reg |= size;
5522 wr32(E1000_VMOLR(vf), reg);
5523 }
4ae196df
AD		 5524 }
5525 }
8151d294
WM		 5526 return 0;
5527}
5528
5529static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5530{
5531 struct e1000_hw *hw = &adapter->hw;
5532
5533 if (vid)
5534 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5535 else
5536 wr32(E1000_VMVIR(vf), 0);
5537}
5538
5539static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5540 int vf, u16 vlan, u8 qos)
5541{
5542 int err = 0;
5543 struct igb_adapter *adapter = netdev_priv(netdev);
5544
5545 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5546 return -EINVAL;
5547 if (vlan || qos) {
5548 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5549 if (err)
5550 goto out;
5551 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5552 igb_set_vmolr(adapter, vf, !vlan);
5553 adapter->vf_data[vf].pf_vlan = vlan;
5554 adapter->vf_data[vf].pf_qos = qos;
5555 dev_info(&adapter->pdev->dev,
5556 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5557 if (test_bit(__IGB_DOWN, &adapter->state)) {
5558 dev_warn(&adapter->pdev->dev,
b980ac18 5559 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5560 dev_warn(&adapter->pdev->dev,
b980ac18 5561 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5562 }
5563 } else {
5564 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5565 false, vf);
8151d294
WM		 5566 igb_set_vmvir(adapter, vlan, vf);
5567 igb_set_vmolr(adapter, vf, true);
5568 adapter->vf_data[vf].pf_vlan = 0;
5569 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5570 }
8151d294 5571out:
b980ac18 5572 return err;
4ae196df
AD		 5573}
5574
6f3dc319
GR		 5575static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5576{
5577 struct e1000_hw *hw = &adapter->hw;
5578 int i;
5579 u32 reg;
5580
5581 /* Find the vlan filter for this id */
5582 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5583 reg = rd32(E1000_VLVF(i));
5584 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5585 vid == (reg & E1000_VLVF_VLANID_MASK))
5586 break;
5587 }
5588
5589 if (i >= E1000_VLVF_ARRAY_SIZE)
5590 i = -1;
5591
5592 return i;
5593}
5594
4ae196df
AD		 5595static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5596{
6f3dc319 5597 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5598 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5599 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5600 int err = 0;
4ae196df 5601
6f3dc319
GR		 5602 /* If in promiscuous mode we need to make sure the PF also has
5603 * the VLAN filter set.
5604 */
5605 if (add && (adapter->netdev->flags & IFF_PROMISC))
5606 err = igb_vlvf_set(adapter, vid, add,
5607 adapter->vfs_allocated_count);
5608 if (err)
5609 goto out;
5610
5611 err = igb_vlvf_set(adapter, vid, add, vf);
5612
5613 if (err)
5614 goto out;
5615
5616 /* Go through all the checks to see if the VLAN filter should
5617 * be wiped completely.
5618 */
5619 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5620 u32 vlvf, bits;
5621
5622 int regndx = igb_find_vlvf_entry(adapter, vid);
5623 if (regndx < 0)
5624 goto out;
5625 /* See if any other pools are set for this VLAN filter
5626 * entry other than the PF.
5627 */
5628 vlvf = bits = rd32(E1000_VLVF(regndx));
5629 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5630 adapter->vfs_allocated_count);
5631 /* If the filter was removed then ensure PF pool bit
5632 * is cleared if the PF only added itself to the pool
5633 * because the PF is in promiscuous mode.
5634 */
5635 if ((vlvf & VLAN_VID_MASK) == vid &&
5636 !test_bit(vid, adapter->active_vlans) &&
5637 !bits)
5638 igb_vlvf_set(adapter, vid, add,
5639 adapter->vfs_allocated_count);
5640 }
5641
5642out:
5643 return err;
4ae196df
AD		 5644}
5645
f2ca0dbe 5646static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5647{
8fa7e0f7
GR		 5648 /* clear flags - except flag that indicates PF has set the MAC */
5649 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5650 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5651
5652 /* reset offloads to defaults */
8151d294 5653 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5654
5655 /* reset vlans for device */
5656 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5657 if (adapter->vf_data[vf].pf_vlan)
5658 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5659 adapter->vf_data[vf].pf_vlan,
5660 adapter->vf_data[vf].pf_qos);
5661 else
5662 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5663
5664 /* reset multicast table array for vf */
5665 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5666
5667 /* Flush and reset the mta with the new values */
ff41f8dc 5668 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5669}
5670
f2ca0dbe
AD		 5671static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5672{
5673 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5674
5ac6f91d 5675 /* clear mac address as we were hotplug removed/added */
8151d294 5676 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5677 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5678
5679 /* process remaining reset events */
5680 igb_vf_reset(adapter, vf);
5681}
5682
5683static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5684{
5685 struct e1000_hw *hw = &adapter->hw;
5686 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5687 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5688 u32 reg, msgbuf[3];
5689 u8 *addr = (u8 *)(&msgbuf[1]);
5690
5691 /* process all the same items cleared in a function level reset */
f2ca0dbe 5692 igb_vf_reset(adapter, vf);
4ae196df
AD		 5693
5694 /* set vf mac address */
26ad9178 5695 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5696
5697 /* enable transmit and receive for vf */
5698 reg = rd32(E1000_VFTE);
5699 wr32(E1000_VFTE, reg | (1 << vf));
5700 reg = rd32(E1000_VFRE);
5701 wr32(E1000_VFRE, reg | (1 << vf));
5702
8fa7e0f7 5703 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5704
5705 /* reply to reset with ack and vf mac address */
5706 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5707 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5708 igb_write_mbx(hw, msgbuf, 3, vf);
5709}
5710
5711static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5712{
b980ac18 5713 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5714 * starting at the second 32 bit word of the msg array
5715 */
f2ca0dbe
AD		 5716 unsigned char *addr = (char *)&msg[1];
5717 int err = -1;
4ae196df 5718
f2ca0dbe
AD		 5719 if (is_valid_ether_addr(addr))
5720 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5721
f2ca0dbe 5722 return err;
4ae196df
AD		 5723}
5724
5725static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5726{
5727 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5728 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5729 u32 msg = E1000_VT_MSGTYPE_NACK;
5730
5731 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5732 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5733 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5734 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5735 vf_data->last_nack = jiffies;
4ae196df
AD		 5736 }
5737}
5738
f2ca0dbe 5739static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5740{
f2ca0dbe
AD		 5741 struct pci_dev *pdev = adapter->pdev;
5742 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5743 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5744 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5745 s32 retval;
5746
f2ca0dbe 5747 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5748
fef45f4c
AD		 5749 if (retval) {
5750 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5751 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5752 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5753 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5754 return;
5755 goto out;
5756 }
4ae196df
AD		 5757
5758 /* this is a message we already processed, do nothing */
5759 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5760 return;
4ae196df 5761
b980ac18 5762 /* until the vf completes a reset it should not be
4ae196df
AD		 5763 * allowed to start any configuration.
5764 */
4ae196df
AD		 5765 if (msgbuf[0] == E1000_VF_RESET) {
5766 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5767 return;
4ae196df
AD		 5768 }
5769
f2ca0dbe 5770 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5771 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5772 return;
5773 retval = -1;
5774 goto out;
4ae196df
AD		 5775 }
5776
5777 switch ((msgbuf[0] & 0xFFFF)) {
5778 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5779 retval = -EINVAL;
5780 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5781 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5782 else
5783 dev_warn(&pdev->dev,
b980ac18
JK		 5784 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5785 vf);
4ae196df 5786 break;
7d5753f0
AD		 5787 case E1000_VF_SET_PROMISC:
5788 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5789 break;
4ae196df
AD		 5790 case E1000_VF_SET_MULTICAST:
5791 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5792 break;
5793 case E1000_VF_SET_LPE:
5794 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5795 break;
5796 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5797 retval = -1;
5798 if (vf_data->pf_vlan)
5799 dev_warn(&pdev->dev,
b980ac18
JK		 5800 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5801 vf);
8151d294
WM		 5802 else
5803 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5804 break;
5805 default:
090b1795 5806 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5807 retval = -1;
5808 break;
5809 }
5810
fef45f4c
AD		 5811 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5812out:
4ae196df
AD		 5813 /* notify the VF of the results of what it sent us */
5814 if (retval)
5815 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5816 else
5817 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5818
4ae196df 5819 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5820}
4ae196df 5821
f2ca0dbe
AD		 5822static void igb_msg_task(struct igb_adapter *adapter)
5823{
5824 struct e1000_hw *hw = &adapter->hw;
5825 u32 vf;
5826
5827 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5828 /* process any reset requests */
5829 if (!igb_check_for_rst(hw, vf))
5830 igb_vf_reset_event(adapter, vf);
5831
5832 /* process any messages pending */
5833 if (!igb_check_for_msg(hw, vf))
5834 igb_rcv_msg_from_vf(adapter, vf);
5835
5836 /* process any acks */
5837 if (!igb_check_for_ack(hw, vf))
5838 igb_rcv_ack_from_vf(adapter, vf);
5839 }
4ae196df
AD		 5840}
5841
68d480c4
AD		 5842/**
5843 * igb_set_uta - Set unicast filter table address
5844 * @adapter: board private structure
5845 *
5846 * The unicast table address is a register array of 32-bit registers.
5847 * The table is meant to be used in a way similar to how the MTA is used
5848 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5849 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5850 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5851 **/
5852static void igb_set_uta(struct igb_adapter *adapter)
5853{
5854 struct e1000_hw *hw = &adapter->hw;
5855 int i;
5856
5857 /* The UTA table only exists on 82576 hardware and newer */
5858 if (hw->mac.type < e1000_82576)
5859 return;
5860
5861 /* we only need to do this if VMDq is enabled */
5862 if (!adapter->vfs_allocated_count)
5863 return;
5864
5865 for (i = 0; i < hw->mac.uta_reg_count; i++)
5866 array_wr32(E1000_UTA, i, ~0);
5867}
5868
9d5c8243 5869/**
b980ac18
JK		 5870 * igb_intr_msi - Interrupt Handler
5871 * @irq: interrupt number
5872 * @data: pointer to a network interface device structure
9d5c8243
AK		 5873 **/
5874static irqreturn_t igb_intr_msi(int irq, void *data)
5875{
047e0030
AD		 5876 struct igb_adapter *adapter = data;
5877 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5878 struct e1000_hw *hw = &adapter->hw;
5879 /* read ICR disables interrupts using IAM */
5880 u32 icr = rd32(E1000_ICR);
5881
047e0030 5882 igb_write_itr(q_vector);
9d5c8243 5883
7f081d40
AD		 5884 if (icr & E1000_ICR_DRSTA)
5885 schedule_work(&adapter->reset_task);
5886
047e0030 5887 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5888 /* HW is reporting DMA is out of sync */
5889 adapter->stats.doosync++;
5890 }
5891
9d5c8243
AK		 5892 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5893 hw->mac.get_link_status = 1;
5894 if (!test_bit(__IGB_DOWN, &adapter->state))
5895 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5896 }
5897
1f6e8178
MV		 5898 if (icr & E1000_ICR_TS) {
5899 u32 tsicr = rd32(E1000_TSICR);
5900
5901 if (tsicr & E1000_TSICR_TXTS) {
5902 /* acknowledge the interrupt */
5903 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5904 /* retrieve hardware timestamp */
5905 schedule_work(&adapter->ptp_tx_work);
5906 }
5907 }
1f6e8178 5908
047e0030 5909 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5910
5911 return IRQ_HANDLED;
5912}
5913
5914/**
b980ac18
JK		 5915 * igb_intr - Legacy Interrupt Handler
5916 * @irq: interrupt number
5917 * @data: pointer to a network interface device structure
9d5c8243
AK		 5918 **/
5919static irqreturn_t igb_intr(int irq, void *data)
5920{
047e0030
AD		 5921 struct igb_adapter *adapter = data;
5922 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5923 struct e1000_hw *hw = &adapter->hw;
5924 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5925 * need for the IMC write
5926 */
9d5c8243 5927 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5928
5929 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5930 * not set, then the adapter didn't send an interrupt
5931 */
9d5c8243
AK		 5932 if (!(icr & E1000_ICR_INT_ASSERTED))
5933 return IRQ_NONE;
5934
0ba82994
AD		 5935 igb_write_itr(q_vector);
5936
7f081d40
AD		 5937 if (icr & E1000_ICR_DRSTA)
5938 schedule_work(&adapter->reset_task);
5939
047e0030 5940 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5941 /* HW is reporting DMA is out of sync */
5942 adapter->stats.doosync++;
5943 }
5944
9d5c8243
AK		 5945 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5946 hw->mac.get_link_status = 1;
5947 /* guard against interrupt when we're going down */
5948 if (!test_bit(__IGB_DOWN, &adapter->state))
5949 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5950 }
5951
1f6e8178
MV		 5952 if (icr & E1000_ICR_TS) {
5953 u32 tsicr = rd32(E1000_TSICR);
5954
5955 if (tsicr & E1000_TSICR_TXTS) {
5956 /* acknowledge the interrupt */
5957 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5958 /* retrieve hardware timestamp */
5959 schedule_work(&adapter->ptp_tx_work);
5960 }
5961 }
1f6e8178 5962
047e0030 5963 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5964
5965 return IRQ_HANDLED;
5966}
5967
c50b52a0 5968static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5969{
047e0030 5970 struct igb_adapter *adapter = q_vector->adapter;
46544258 5971 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5972
0ba82994
AD		 5973 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5974 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5975 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5976 igb_set_itr(q_vector);
46544258 5977 else
047e0030 5978 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5979 }
5980
46544258
AD		 5981 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5982 if (adapter->msix_entries)
047e0030 5983 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5984 else
5985 igb_irq_enable(adapter);
5986 }
9d5c8243
AK		 5987}
5988
46544258 5989/**
b980ac18
JK		 5990 * igb_poll - NAPI Rx polling callback
5991 * @napi: napi polling structure
5992 * @budget: count of how many packets we should handle
46544258
AD		 5993 **/
5994static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5995{
047e0030 5996 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 5997 struct igb_q_vector,
5998 napi);
16eb8815 5999 bool clean_complete = true;
9d5c8243 6000
421e02f0 6001#ifdef CONFIG_IGB_DCA
047e0030
AD		 6002 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6003 igb_update_dca(q_vector);
fe4506b6 6004#endif
0ba82994 6005 if (q_vector->tx.ring)
13fde97a 6006 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6007
0ba82994 6008 if (q_vector->rx.ring)
cd392f5c 6009 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6010
16eb8815
AD		 6011 /* If all work not completed, return budget and keep polling */
6012 if (!clean_complete)
6013 return budget;
46544258 6014
9d5c8243 6015 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6016 napi_complete(napi);
6017 igb_ring_irq_enable(q_vector);
9d5c8243 6018
16eb8815 6019 return 0;
9d5c8243 6020}
6d8126f9 6021
9d5c8243 6022/**
b980ac18
JK		 6023 * igb_clean_tx_irq - Reclaim resources after transmit completes
6024 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6025 *
b980ac18 6026 * returns true if ring is completely cleaned
9d5c8243 6027 **/
047e0030 6028static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6029{
047e0030 6030 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6031 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6032 struct igb_tx_buffer *tx_buffer;
f4128785 6033 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6034 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6035 unsigned int budget = q_vector->tx.work_limit;
8542db05 6036 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6037
13fde97a
AD		 6038 if (test_bit(__IGB_DOWN, &adapter->state))
6039 return true;
0e014cb1 6040
06034649 6041 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6042 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6043 i -= tx_ring->count;
9d5c8243 6044
f4128785
AD		 6045 do {
6046 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6047
6048 /* if next_to_watch is not set then there is no work pending */
6049 if (!eop_desc)
6050 break;
13fde97a 6051
f4128785 6052 /* prevent any other reads prior to eop_desc */
70d289bc 6053 read_barrier_depends();
f4128785 6054
13fde97a
AD		 6055 /* if DD is not set pending work has not been completed */
6056 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6057 break;
6058
8542db05
AD		 6059 /* clear next_to_watch to prevent false hangs */
6060 tx_buffer->next_to_watch = NULL;
9d5c8243 6061
ebe42d16
AD		 6062 /* update the statistics for this packet */
6063 total_bytes += tx_buffer->bytecount;
6064 total_packets += tx_buffer->gso_segs;
13fde97a 6065
ebe42d16
AD		 6066 /* free the skb */
6067 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6068
ebe42d16
AD		 6069 /* unmap skb header data */
6070 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6071 dma_unmap_addr(tx_buffer, dma),
6072 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6073 DMA_TO_DEVICE);
6074
c9f14bf3
AD		 6075 /* clear tx_buffer data */
6076 tx_buffer->skb = NULL;
6077 dma_unmap_len_set(tx_buffer, len, 0);
6078
ebe42d16
AD		 6079 /* clear last DMA location and unmap remaining buffers */
6080 while (tx_desc != eop_desc) {
13fde97a
AD		 6081 tx_buffer++;
6082 tx_desc++;
9d5c8243 6083 i++;
8542db05
AD		 6084 if (unlikely(!i)) {
6085 i -= tx_ring->count;
06034649 6086 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6087 tx_desc = IGB_TX_DESC(tx_ring, 0);
6088 }
ebe42d16
AD		 6089
6090 /* unmap any remaining paged data */
c9f14bf3 6091 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6092 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6093 dma_unmap_addr(tx_buffer, dma),
6094 dma_unmap_len(tx_buffer, len),
ebe42d16 6095 DMA_TO_DEVICE);
c9f14bf3 6096 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6097 }
6098 }
6099
ebe42d16
AD		 6100 /* move us one more past the eop_desc for start of next pkt */
6101 tx_buffer++;
6102 tx_desc++;
6103 i++;
6104 if (unlikely(!i)) {
6105 i -= tx_ring->count;
6106 tx_buffer = tx_ring->tx_buffer_info;
6107 tx_desc = IGB_TX_DESC(tx_ring, 0);
6108 }
f4128785
AD		 6109
6110 /* issue prefetch for next Tx descriptor */
6111 prefetch(tx_desc);
6112
6113 /* update budget accounting */
6114 budget--;
6115 } while (likely(budget));
0e014cb1 6116
bdbc0631
ED		 6117 netdev_tx_completed_queue(txring_txq(tx_ring),
6118 total_packets, total_bytes);
8542db05 6119 i += tx_ring->count;
9d5c8243 6120 tx_ring->next_to_clean = i;
13fde97a
AD		 6121 u64_stats_update_begin(&tx_ring->tx_syncp);
6122 tx_ring->tx_stats.bytes += total_bytes;
6123 tx_ring->tx_stats.packets += total_packets;
6124 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6125 q_vector->tx.total_bytes += total_bytes;
6126 q_vector->tx.total_packets += total_packets;
9d5c8243 6127
6d095fa8 6128 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6129 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6130
9d5c8243 6131 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6132 * check with the clearing of time_stamp and movement of i
6133 */
6d095fa8 6134 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6135 if (tx_buffer->next_to_watch &&
8542db05 6136 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6137 (adapter->tx_timeout_factor * HZ)) &&
6138 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6139
9d5c8243 6140 /* detected Tx unit hang */
59d71989 6141 dev_err(tx_ring->dev,
9d5c8243 6142 "Detected Tx Unit Hang\n"
2d064c06 6143 " Tx Queue <%d>\n"
9d5c8243
AK		 6144 " TDH <%x>\n"
6145 " TDT <%x>\n"
6146 " next_to_use <%x>\n"
6147 " next_to_clean <%x>\n"
9d5c8243
AK		 6148 "buffer_info[next_to_clean]\n"
6149 " time_stamp <%lx>\n"
8542db05 6150 " next_to_watch <%p>\n"
9d5c8243
AK		 6151 " jiffies <%lx>\n"
6152 " desc.status <%x>\n",
2d064c06 6153 tx_ring->queue_index,
238ac817 6154 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6155 readl(tx_ring->tail),
9d5c8243
AK		 6156 tx_ring->next_to_use,
6157 tx_ring->next_to_clean,
8542db05 6158 tx_buffer->time_stamp,
f4128785 6159 tx_buffer->next_to_watch,
9d5c8243 6160 jiffies,
f4128785 6161 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6162 netif_stop_subqueue(tx_ring->netdev,
6163 tx_ring->queue_index);
6164
6165 /* we are about to reset, no point in enabling stuff */
6166 return true;
9d5c8243
AK		 6167 }
6168 }
13fde97a 6169
21ba6fe1 6170#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6171 if (unlikely(total_packets &&
b980ac18
JK		 6172 netif_carrier_ok(tx_ring->netdev) &&
6173 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6174 /* Make sure that anybody stopping the queue after this
6175 * sees the new next_to_clean.
6176 */
6177 smp_mb();
6178 if (__netif_subqueue_stopped(tx_ring->netdev,
6179 tx_ring->queue_index) &&
6180 !(test_bit(__IGB_DOWN, &adapter->state))) {
6181 netif_wake_subqueue(tx_ring->netdev,
6182 tx_ring->queue_index);
6183
6184 u64_stats_update_begin(&tx_ring->tx_syncp);
6185 tx_ring->tx_stats.restart_queue++;
6186 u64_stats_update_end(&tx_ring->tx_syncp);
6187 }
6188 }
6189
6190 return !!budget;
9d5c8243
AK		 6191}
6192
cbc8e55f 6193/**
b980ac18
JK		 6194 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6195 * @rx_ring: rx descriptor ring to store buffers on
6196 * @old_buff: donor buffer to have page reused
cbc8e55f 6197 *
b980ac18 6198 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6199 **/
6200static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6201 struct igb_rx_buffer *old_buff)
6202{
6203 struct igb_rx_buffer *new_buff;
6204 u16 nta = rx_ring->next_to_alloc;
6205
6206 new_buff = &rx_ring->rx_buffer_info[nta];
6207
6208 /* update, and store next to alloc */
6209 nta++;
6210 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6211
6212 /* transfer page from old buffer to new buffer */
6213 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6214
6215 /* sync the buffer for use by the device */
6216 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6217 old_buff->page_offset,
de78d1f9 6218 IGB_RX_BUFSZ,
cbc8e55f
AD		 6219 DMA_FROM_DEVICE);
6220}
6221
74e238ea
AD		 6222static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6223 struct page *page,
6224 unsigned int truesize)
6225{
6226 /* avoid re-using remote pages */
6227 if (unlikely(page_to_nid(page) != numa_node_id()))
6228 return false;
6229
6230#if (PAGE_SIZE < 8192)
6231 /* if we are only owner of page we can reuse it */
6232 if (unlikely(page_count(page) != 1))
6233 return false;
6234
6235 /* flip page offset to other buffer */
6236 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6237
6238 /* since we are the only owner of the page and we need to
6239 * increment it, just set the value to 2 in order to avoid
6240 * an unnecessary locked operation
6241 */
6242 atomic_set(&page->_count, 2);
6243#else
6244 /* move offset up to the next cache line */
6245 rx_buffer->page_offset += truesize;
6246
6247 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6248 return false;
6249
6250 /* bump ref count on page before it is given to the stack */
6251 get_page(page);
6252#endif
6253
6254 return true;
6255}
6256
cbc8e55f 6257/**
b980ac18
JK		 6258 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6259 * @rx_ring: rx descriptor ring to transact packets on
6260 * @rx_buffer: buffer containing page to add
6261 * @rx_desc: descriptor containing length of buffer written by hardware
6262 * @skb: sk_buff to place the data into
cbc8e55f 6263 *
b980ac18
JK		 6264 * This function will add the data contained in rx_buffer->page to the skb.
6265 * This is done either through a direct copy if the data in the buffer is
6266 * less than the skb header size, otherwise it will just attach the page as
6267 * a frag to the skb.
cbc8e55f 6268 *
b980ac18
JK		 6269 * The function will then update the page offset if necessary and return
6270 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6271 **/
6272static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6273 struct igb_rx_buffer *rx_buffer,
6274 union e1000_adv_rx_desc *rx_desc,
6275 struct sk_buff *skb)
6276{
6277 struct page *page = rx_buffer->page;
6278 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6279#if (PAGE_SIZE < 8192)
6280 unsigned int truesize = IGB_RX_BUFSZ;
6281#else
6282 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6283#endif
cbc8e55f
AD		 6284
6285 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6286 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6287
cbc8e55f
AD		 6288 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6289 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6290 va += IGB_TS_HDR_LEN;
6291 size -= IGB_TS_HDR_LEN;
6292 }
6293
cbc8e55f
AD		 6294 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6295
6296 /* we can reuse buffer as-is, just make sure it is local */
6297 if (likely(page_to_nid(page) == numa_node_id()))
6298 return true;
6299
6300 /* this page cannot be reused so discard it */
6301 put_page(page);
6302 return false;
6303 }
6304
6305 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6306 rx_buffer->page_offset, size, truesize);
cbc8e55f 6307
74e238ea
AD		 6308 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6309}
cbc8e55f 6310
2e334eee
AD		 6311static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6312 union e1000_adv_rx_desc *rx_desc,
6313 struct sk_buff *skb)
6314{
6315 struct igb_rx_buffer *rx_buffer;
6316 struct page *page;
6317
6318 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6319
2e334eee
AD		 6320 page = rx_buffer->page;
6321 prefetchw(page);
6322
6323 if (likely(!skb)) {
6324 void *page_addr = page_address(page) +
6325 rx_buffer->page_offset;
6326
6327 /* prefetch first cache line of first page */
6328 prefetch(page_addr);
6329#if L1_CACHE_BYTES < 128
6330 prefetch(page_addr + L1_CACHE_BYTES);
6331#endif
6332
6333 /* allocate a skb to store the frags */
6334 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6335 IGB_RX_HDR_LEN);
6336 if (unlikely(!skb)) {
6337 rx_ring->rx_stats.alloc_failed++;
6338 return NULL;
6339 }
6340
b980ac18 6341 /* we will be copying header into skb->data in
2e334eee
AD		 6342 * pskb_may_pull so it is in our interest to prefetch
6343 * it now to avoid a possible cache miss
6344 */
6345 prefetchw(skb->data);
6346 }
6347
6348 /* we are reusing so sync this buffer for CPU use */
6349 dma_sync_single_range_for_cpu(rx_ring->dev,
6350 rx_buffer->dma,
6351 rx_buffer->page_offset,
de78d1f9 6352 IGB_RX_BUFSZ,
2e334eee
AD		 6353 DMA_FROM_DEVICE);
6354
6355 /* pull page into skb */
6356 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6357 /* hand second half of page back to the ring */
6358 igb_reuse_rx_page(rx_ring, rx_buffer);
6359 } else {
6360 /* we are not reusing the buffer so unmap it */
6361 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6362 PAGE_SIZE, DMA_FROM_DEVICE);
6363 }
6364
6365 /* clear contents of rx_buffer */
6366 rx_buffer->page = NULL;
6367
6368 return skb;
6369}
6370
cd392f5c 6371static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6372 union e1000_adv_rx_desc *rx_desc,
6373 struct sk_buff *skb)
9d5c8243 6374{
bc8acf2c 6375 skb_checksum_none_assert(skb);
9d5c8243 6376
294e7d78 6377 /* Ignore Checksum bit is set */
3ceb90fd 6378 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6379 return;
6380
6381 /* Rx checksum disabled via ethtool */
6382 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6383 return;
85ad76b2 6384
9d5c8243 6385 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6386 if (igb_test_staterr(rx_desc,
6387 E1000_RXDEXT_STATERR_TCPE |
6388 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6389 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6390 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6391 * packets, (aka let the stack check the crc32c)
6392 */
866cff06
AD		 6393 if (!((skb->len == 60) &&
6394 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6395 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6396 ring->rx_stats.csum_err++;
12dcd86b
ED		 6397 u64_stats_update_end(&ring->rx_syncp);
6398 }
9d5c8243 6399 /* let the stack verify checksum errors */
9d5c8243
AK		 6400 return;
6401 }
6402 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6403 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6404 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6405 skb->ip_summed = CHECKSUM_UNNECESSARY;
6406
3ceb90fd
AD		 6407 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6408 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6409}
6410
077887c3
AD		 6411static inline void igb_rx_hash(struct igb_ring *ring,
6412 union e1000_adv_rx_desc *rx_desc,
6413 struct sk_buff *skb)
6414{
6415 if (ring->netdev->features & NETIF_F_RXHASH)
6416 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6417}
6418
2e334eee 6419/**
b980ac18
JK		 6420 * igb_is_non_eop - process handling of non-EOP buffers
6421 * @rx_ring: Rx ring being processed
6422 * @rx_desc: Rx descriptor for current buffer
6423 * @skb: current socket buffer containing buffer in progress
2e334eee 6424 *
b980ac18
JK		 6425 * This function updates next to clean. If the buffer is an EOP buffer
6426 * this function exits returning false, otherwise it will place the
6427 * sk_buff in the next buffer to be chained and return true indicating
6428 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6429 **/
6430static bool igb_is_non_eop(struct igb_ring *rx_ring,
6431 union e1000_adv_rx_desc *rx_desc)
6432{
6433 u32 ntc = rx_ring->next_to_clean + 1;
6434
6435 /* fetch, update, and store next to clean */
6436 ntc = (ntc < rx_ring->count) ? ntc : 0;
6437 rx_ring->next_to_clean = ntc;
6438
6439 prefetch(IGB_RX_DESC(rx_ring, ntc));
6440
6441 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6442 return false;
6443
6444 return true;
6445}
6446
1a1c225b 6447/**
b980ac18
JK		 6448 * igb_get_headlen - determine size of header for LRO/GRO
6449 * @data: pointer to the start of the headers
6450 * @max_len: total length of section to find headers in
1a1c225b 6451 *
b980ac18
JK		 6452 * This function is meant to determine the length of headers that will
6453 * be recognized by hardware for LRO, and GRO offloads. The main
6454 * motivation of doing this is to only perform one pull for IPv4 TCP
6455 * packets so that we can do basic things like calculating the gso_size
6456 * based on the average data per packet.
1a1c225b
AD		 6457 **/
6458static unsigned int igb_get_headlen(unsigned char *data,
6459 unsigned int max_len)
6460{
6461 union {
6462 unsigned char *network;
6463 /* l2 headers */
6464 struct ethhdr *eth;
6465 struct vlan_hdr *vlan;
6466 /* l3 headers */
6467 struct iphdr *ipv4;
6468 struct ipv6hdr *ipv6;
6469 } hdr;
6470 __be16 protocol;
6471 u8 nexthdr = 0; /* default to not TCP */
6472 u8 hlen;
6473
6474 /* this should never happen, but better safe than sorry */
6475 if (max_len < ETH_HLEN)
6476 return max_len;
6477
6478 /* initialize network frame pointer */
6479 hdr.network = data;
6480
6481 /* set first protocol and move network header forward */
6482 protocol = hdr.eth->h_proto;
6483 hdr.network += ETH_HLEN;
6484
6485 /* handle any vlan tag if present */
6486 if (protocol == __constant_htons(ETH_P_8021Q)) {
6487 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6488 return max_len;
6489
6490 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6491 hdr.network += VLAN_HLEN;
6492 }
6493
6494 /* handle L3 protocols */
6495 if (protocol == __constant_htons(ETH_P_IP)) {
6496 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6497 return max_len;
6498
6499 /* access ihl as a u8 to avoid unaligned access on ia64 */
6500 hlen = (hdr.network[0] & 0x0F) << 2;
6501
6502 /* verify hlen meets minimum size requirements */
6503 if (hlen < sizeof(struct iphdr))
6504 return hdr.network - data;
6505
f2fb4ab2 6506 /* record next protocol if header is present */
b9555f66 6507 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6508 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6509 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6510 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6511 return max_len;
6512
6513 /* record next protocol */
6514 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6515 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6516 } else {
6517 return hdr.network - data;
6518 }
6519
f2fb4ab2
AD		 6520 /* relocate pointer to start of L4 header */
6521 hdr.network += hlen;
6522
1a1c225b
AD		 6523 /* finally sort out TCP */
6524 if (nexthdr == IPPROTO_TCP) {
6525 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6526 return max_len;
6527
6528 /* access doff as a u8 to avoid unaligned access on ia64 */
6529 hlen = (hdr.network[12] & 0xF0) >> 2;
6530
6531 /* verify hlen meets minimum size requirements */
6532 if (hlen < sizeof(struct tcphdr))
6533 return hdr.network - data;
6534
6535 hdr.network += hlen;
6536 } else if (nexthdr == IPPROTO_UDP) {
6537 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6538 return max_len;
6539
6540 hdr.network += sizeof(struct udphdr);
6541 }
6542
b980ac18 6543 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6544 * data section of the packet and will be the end of the header.
6545 * If not then it probably represents the end of the last recognized
6546 * header.
6547 */
6548 if ((hdr.network - data) < max_len)
6549 return hdr.network - data;
6550 else
6551 return max_len;
6552}
6553
6554/**
b980ac18
JK		 6555 * igb_pull_tail - igb specific version of skb_pull_tail
6556 * @rx_ring: rx descriptor ring packet is being transacted on
6557 * @rx_desc: pointer to the EOP Rx descriptor
6558 * @skb: pointer to current skb being adjusted
1a1c225b 6559 *
b980ac18
JK		 6560 * This function is an igb specific version of __pskb_pull_tail. The
6561 * main difference between this version and the original function is that
6562 * this function can make several assumptions about the state of things
6563 * that allow for significant optimizations versus the standard function.
6564 * As a result we can do things like drop a frag and maintain an accurate
6565 * truesize for the skb.
1a1c225b
AD		 6566 */
6567static void igb_pull_tail(struct igb_ring *rx_ring,
6568 union e1000_adv_rx_desc *rx_desc,
6569 struct sk_buff *skb)
2d94d8ab 6570{
1a1c225b
AD		 6571 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6572 unsigned char *va;
6573 unsigned int pull_len;
6574
b980ac18 6575 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6576 * working with pages allocated out of the lomem pool per
6577 * alloc_page(GFP_ATOMIC)
2d94d8ab 6578 */
1a1c225b
AD		 6579 va = skb_frag_address(frag);
6580
1a1c225b
AD		 6581 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6582 /* retrieve timestamp from buffer */
6583 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6584
6585 /* update pointers to remove timestamp header */
6586 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6587 frag->page_offset += IGB_TS_HDR_LEN;
6588 skb->data_len -= IGB_TS_HDR_LEN;
6589 skb->len -= IGB_TS_HDR_LEN;
6590
6591 /* move va to start of packet data */
6592 va += IGB_TS_HDR_LEN;
6593 }
6594
b980ac18 6595 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6596 * 60 bytes if the skb->len is less than 60 for skb_pad.
6597 */
6598 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6599
6600 /* align pull length to size of long to optimize memcpy performance */
6601 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6602
6603 /* update all of the pointers */
6604 skb_frag_size_sub(frag, pull_len);
6605 frag->page_offset += pull_len;
6606 skb->data_len -= pull_len;
6607 skb->tail += pull_len;
6608}
6609
6610/**
b980ac18
JK		 6611 * igb_cleanup_headers - Correct corrupted or empty headers
6612 * @rx_ring: rx descriptor ring packet is being transacted on
6613 * @rx_desc: pointer to the EOP Rx descriptor
6614 * @skb: pointer to current skb being fixed
1a1c225b 6615 *
b980ac18
JK		 6616 * Address the case where we are pulling data in on pages only
6617 * and as such no data is present in the skb header.
1a1c225b 6618 *
b980ac18
JK		 6619 * In addition if skb is not at least 60 bytes we need to pad it so that
6620 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6621 *
b980ac18 6622 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6623 **/
6624static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6625 union e1000_adv_rx_desc *rx_desc,
6626 struct sk_buff *skb)
6627{
1a1c225b
AD		 6628 if (unlikely((igb_test_staterr(rx_desc,
6629 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6630 struct net_device *netdev = rx_ring->netdev;
6631 if (!(netdev->features & NETIF_F_RXALL)) {
6632 dev_kfree_skb_any(skb);
6633 return true;
6634 }
6635 }
6636
6637 /* place header in linear portion of buffer */
6638 if (skb_is_nonlinear(skb))
6639 igb_pull_tail(rx_ring, rx_desc, skb);
6640
6641 /* if skb_pad returns an error the skb was freed */
6642 if (unlikely(skb->len < 60)) {
6643 int pad_len = 60 - skb->len;
6644
6645 if (skb_pad(skb, pad_len))
6646 return true;
6647 __skb_put(skb, pad_len);
6648 }
6649
6650 return false;
2d94d8ab
AD		 6651}
6652
db2ee5bd 6653/**
b980ac18
JK		 6654 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6655 * @rx_ring: rx descriptor ring packet is being transacted on
6656 * @rx_desc: pointer to the EOP Rx descriptor
6657 * @skb: pointer to current skb being populated
db2ee5bd 6658 *
b980ac18
JK		 6659 * This function checks the ring, descriptor, and packet information in
6660 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6661 * other fields within the skb.
db2ee5bd
AD		 6662 **/
6663static void igb_process_skb_fields(struct igb_ring *rx_ring,
6664 union e1000_adv_rx_desc *rx_desc,
6665 struct sk_buff *skb)
6666{
6667 struct net_device *dev = rx_ring->netdev;
6668
6669 igb_rx_hash(rx_ring, rx_desc, skb);
6670
6671 igb_rx_checksum(rx_ring, rx_desc, skb);
6672
20a48412 6673 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6674
f646968f 6675 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6676 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6677 u16 vid;
6678 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6679 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6680 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6681 else
6682 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6683
86a9bad3 6684 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6685 }
6686
6687 skb_record_rx_queue(skb, rx_ring->queue_index);
6688
6689 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6690}
6691
2e334eee 6692static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6693{
0ba82994 6694 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6695 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6696 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6697 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6698
2e334eee
AD		 6699 do {
6700 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6701
2e334eee
AD		 6702 /* return some buffers to hardware, one at a time is too slow */
6703 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6704 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6705 cleaned_count = 0;
6706 }
bf36c1a0 6707
2e334eee 6708 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6709
2e334eee
AD		 6710 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6711 break;
9d5c8243 6712
74e238ea
AD		 6713 /* This memory barrier is needed to keep us from reading
6714 * any other fields out of the rx_desc until we know the
6715 * RXD_STAT_DD bit is set
6716 */
6717 rmb();
6718
2e334eee 6719 /* retrieve a buffer from the ring */
f9d40f6a 6720 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6721
2e334eee
AD		 6722 /* exit if we failed to retrieve a buffer */
6723 if (!skb)
6724 break;
1a1c225b 6725
2e334eee 6726 cleaned_count++;
1a1c225b 6727
2e334eee
AD		 6728 /* fetch next buffer in frame if non-eop */
6729 if (igb_is_non_eop(rx_ring, rx_desc))
6730 continue;
1a1c225b
AD		 6731
6732 /* verify the packet layout is correct */
6733 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6734 skb = NULL;
6735 continue;
9d5c8243 6736 }
9d5c8243 6737
db2ee5bd 6738 /* probably a little skewed due to removing CRC */
3ceb90fd 6739 total_bytes += skb->len;
3ceb90fd 6740
db2ee5bd
AD		 6741 /* populate checksum, timestamp, VLAN, and protocol */
6742 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6743
b2cb09b1 6744 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6745
1a1c225b
AD		 6746 /* reset skb pointer */
6747 skb = NULL;
6748
2e334eee
AD		 6749 /* update budget accounting */
6750 total_packets++;
6751 } while (likely(total_packets < budget));
bf36c1a0 6752
1a1c225b
AD		 6753 /* place incomplete frames back on ring for completion */
6754 rx_ring->skb = skb;
6755
12dcd86b 6756 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6757 rx_ring->rx_stats.packets += total_packets;
6758 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6759 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6760 q_vector->rx.total_packets += total_packets;
6761 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6762
6763 if (cleaned_count)
cd392f5c 6764 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6765
2e334eee 6766 return (total_packets < budget);
9d5c8243
AK		 6767}
6768
c023cd88 6769static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6770 struct igb_rx_buffer *bi)
c023cd88
AD		 6771{
6772 struct page *page = bi->page;
cbc8e55f 6773 dma_addr_t dma;
c023cd88 6774
cbc8e55f
AD		 6775 /* since we are recycling buffers we should seldom need to alloc */
6776 if (likely(page))
c023cd88
AD		 6777 return true;
6778
cbc8e55f
AD		 6779 /* alloc new page for storage */
6780 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6781 if (unlikely(!page)) {
6782 rx_ring->rx_stats.alloc_failed++;
6783 return false;
c023cd88
AD		 6784 }
6785
cbc8e55f
AD		 6786 /* map page for use */
6787 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6788
b980ac18 6789 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6790 * there isn't much point in holding memory we can't use
6791 */
1a1c225b 6792 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6793 __free_page(page);
6794
c023cd88
AD		 6795 rx_ring->rx_stats.alloc_failed++;
6796 return false;
6797 }
6798
1a1c225b 6799 bi->dma = dma;
cbc8e55f
AD		 6800 bi->page = page;
6801 bi->page_offset = 0;
1a1c225b 6802
c023cd88
AD		 6803 return true;
6804}
6805
9d5c8243 6806/**
b980ac18
JK		 6807 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6808 * @adapter: address of board private structure
9d5c8243 6809 **/
cd392f5c 6810void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6811{
9d5c8243 6812 union e1000_adv_rx_desc *rx_desc;
06034649 6813 struct igb_rx_buffer *bi;
c023cd88 6814 u16 i = rx_ring->next_to_use;
9d5c8243 6815
cbc8e55f
AD		 6816 /* nothing to do */
6817 if (!cleaned_count)
6818 return;
6819
60136906 6820 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6821 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6822 i -= rx_ring->count;
9d5c8243 6823
cbc8e55f 6824 do {
1a1c225b 6825 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6826 break;
9d5c8243 6827
b980ac18 6828 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6829 * because each write-back erases this info.
6830 */
f9d40f6a 6831 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6832
c023cd88
AD		 6833 rx_desc++;
6834 bi++;
9d5c8243 6835 i++;
c023cd88 6836 if (unlikely(!i)) {
60136906 6837 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6838 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6839 i -= rx_ring->count;
6840 }
6841
6842 /* clear the hdr_addr for the next_to_use descriptor */
6843 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6844
6845 cleaned_count--;
6846 } while (cleaned_count);
9d5c8243 6847
c023cd88
AD		 6848 i += rx_ring->count;
6849
9d5c8243 6850 if (rx_ring->next_to_use != i) {
cbc8e55f 6851 /* record the next descriptor to use */
9d5c8243 6852 rx_ring->next_to_use = i;
9d5c8243 6853
cbc8e55f
AD		 6854 /* update next to alloc since we have filled the ring */
6855 rx_ring->next_to_alloc = i;
6856
b980ac18 6857 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6858 * know there are new descriptors to fetch. (Only
6859 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6860 * such as IA-64).
6861 */
9d5c8243 6862 wmb();
fce99e34 6863 writel(i, rx_ring->tail);
9d5c8243
AK		 6864 }
6865}
6866
6867/**
6868 * igb_mii_ioctl -
6869 * @netdev:
6870 * @ifreq:
6871 * @cmd:
6872 **/
6873static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6874{
6875 struct igb_adapter *adapter = netdev_priv(netdev);
6876 struct mii_ioctl_data *data = if_mii(ifr);
6877
6878 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6879 return -EOPNOTSUPP;
6880
6881 switch (cmd) {
6882 case SIOCGMIIPHY:
6883 data->phy_id = adapter->hw.phy.addr;
6884 break;
6885 case SIOCGMIIREG:
f5f4cf08
AD		 6886 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6887 &data->val_out))
9d5c8243
AK		 6888 return -EIO;
6889 break;
6890 case SIOCSMIIREG:
6891 default:
6892 return -EOPNOTSUPP;
6893 }
6894 return 0;
6895}
6896
6897/**
6898 * igb_ioctl -
6899 * @netdev:
6900 * @ifreq:
6901 * @cmd:
6902 **/
6903static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6904{
6905 switch (cmd) {
6906 case SIOCGMIIPHY:
6907 case SIOCGMIIREG:
6908 case SIOCSMIIREG:
6909 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6910 case SIOCSHWTSTAMP:
a79f4f88 6911 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6912 default:
6913 return -EOPNOTSUPP;
6914 }
6915}
6916
009bc06e
AD		 6917s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6918{
6919 struct igb_adapter *adapter = hw->back;
009bc06e 6920
23d028cc 6921 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6922 return -E1000_ERR_CONFIG;
6923
009bc06e
AD		 6924 return 0;
6925}
6926
6927s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6928{
6929 struct igb_adapter *adapter = hw->back;
009bc06e 6930
23d028cc 6931 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6932 return -E1000_ERR_CONFIG;
6933
009bc06e
AD		 6934 return 0;
6935}
6936
c8f44aff 6937static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6938{
6939 struct igb_adapter *adapter = netdev_priv(netdev);
6940 struct e1000_hw *hw = &adapter->hw;
6941 u32 ctrl, rctl;
f646968f 6942 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6943
5faf030c 6944 if (enable) {
9d5c8243
AK		 6945 /* enable VLAN tag insert/strip */
6946 ctrl = rd32(E1000_CTRL);
6947 ctrl |= E1000_CTRL_VME;
6948 wr32(E1000_CTRL, ctrl);
6949
51466239 6950 /* Disable CFI check */
9d5c8243 6951 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6952 rctl &= ~E1000_RCTL_CFIEN;
6953 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6954 } else {
6955 /* disable VLAN tag insert/strip */
6956 ctrl = rd32(E1000_CTRL);
6957 ctrl &= ~E1000_CTRL_VME;
6958 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6959 }
6960
e1739522 6961 igb_rlpml_set(adapter);
9d5c8243
AK		 6962}
6963
80d5c368
PM		 6964static int igb_vlan_rx_add_vid(struct net_device *netdev,
6965 __be16 proto, u16 vid)
9d5c8243
AK		 6966{
6967 struct igb_adapter *adapter = netdev_priv(netdev);
6968 struct e1000_hw *hw = &adapter->hw;
4ae196df 6969 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6970
51466239
AD		 6971 /* attempt to add filter to vlvf array */
6972 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6973
51466239
AD		 6974 /* add the filter since PF can receive vlans w/o entry in vlvf */
6975 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6976
6977 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6978
6979 return 0;
9d5c8243
AK		 6980}
6981
80d5c368
PM		 6982static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6983 __be16 proto, u16 vid)
9d5c8243
AK		 6984{
6985 struct igb_adapter *adapter = netdev_priv(netdev);
6986 struct e1000_hw *hw = &adapter->hw;
4ae196df 6987 int pf_id = adapter->vfs_allocated_count;
51466239 6988 s32 err;
9d5c8243 6989
51466239
AD		 6990 /* remove vlan from VLVF table array */
6991 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6992
51466239
AD		 6993 /* if vid was not present in VLVF just remove it from table */
6994 if (err)
4ae196df 6995 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 6996
6997 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 6998
6999 return 0;
9d5c8243
AK		 7000}
7001
7002static void igb_restore_vlan(struct igb_adapter *adapter)
7003{
b2cb09b1 7004 u16 vid;
9d5c8243 7005
5faf030c
AD		 7006 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7007
b2cb09b1 7008 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7009 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7010}
7011
14ad2513 7012int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7013{
090b1795 7014 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7015 struct e1000_mac_info *mac = &adapter->hw.mac;
7016
7017 mac->autoneg = 0;
7018
14ad2513 7019 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7020 * for the switch() below to work
7021 */
14ad2513
DD		 7022 if ((spd & 1) || (dplx & ~1))
7023 goto err_inval;
7024
f502ef7d
AA		 7025 /* Fiber NIC's only allow 1000 gbps Full duplex
7026 * and 100Mbps Full duplex for 100baseFx sfp
7027 */
7028 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7029 switch (spd + dplx) {
7030 case SPEED_10 + DUPLEX_HALF:
7031 case SPEED_10 + DUPLEX_FULL:
7032 case SPEED_100 + DUPLEX_HALF:
7033 goto err_inval;
7034 default:
7035 break;
7036 }
7037 }
cd2638a8 7038
14ad2513 7039 switch (spd + dplx) {
9d5c8243
AK		 7040 case SPEED_10 + DUPLEX_HALF:
7041 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7042 break;
7043 case SPEED_10 + DUPLEX_FULL:
7044 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7045 break;
7046 case SPEED_100 + DUPLEX_HALF:
7047 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7048 break;
7049 case SPEED_100 + DUPLEX_FULL:
7050 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7051 break;
7052 case SPEED_1000 + DUPLEX_FULL:
7053 mac->autoneg = 1;
7054 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7055 break;
7056 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7057 default:
14ad2513 7058 goto err_inval;
9d5c8243 7059 }
8376dad0
JB		 7060
7061 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7062 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7063
9d5c8243 7064 return 0;
14ad2513
DD		 7065
7066err_inval:
7067 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7068 return -EINVAL;
9d5c8243
AK		 7069}
7070
749ab2cd
YZ		 7071static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7072 bool runtime)
9d5c8243
AK		 7073{
7074 struct net_device *netdev = pci_get_drvdata(pdev);
7075 struct igb_adapter *adapter = netdev_priv(netdev);
7076 struct e1000_hw *hw = &adapter->hw;
2d064c06 7077 u32 ctrl, rctl, status;
749ab2cd 7078 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7079#ifdef CONFIG_PM
7080 int retval = 0;
7081#endif
7082
7083 netif_device_detach(netdev);
7084
a88f10ec 7085 if (netif_running(netdev))
749ab2cd 7086 __igb_close(netdev, true);
a88f10ec 7087
047e0030 7088 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7089
7090#ifdef CONFIG_PM
7091 retval = pci_save_state(pdev);
7092 if (retval)
7093 return retval;
7094#endif
7095
7096 status = rd32(E1000_STATUS);
7097 if (status & E1000_STATUS_LU)
7098 wufc &= ~E1000_WUFC_LNKC;
7099
7100 if (wufc) {
7101 igb_setup_rctl(adapter);
ff41f8dc 7102 igb_set_rx_mode(netdev);
9d5c8243
AK		 7103
7104 /* turn on all-multi mode if wake on multicast is enabled */
7105 if (wufc & E1000_WUFC_MC) {
7106 rctl = rd32(E1000_RCTL);
7107 rctl |= E1000_RCTL_MPE;
7108 wr32(E1000_RCTL, rctl);
7109 }
7110
7111 ctrl = rd32(E1000_CTRL);
7112 /* advertise wake from D3Cold */
7113 #define E1000_CTRL_ADVD3WUC 0x00100000
7114 /* phy power management enable */
7115 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7116 ctrl |= E1000_CTRL_ADVD3WUC;
7117 wr32(E1000_CTRL, ctrl);
7118
9d5c8243 7119 /* Allow time for pending master requests to run */
330a6d6a 7120 igb_disable_pcie_master(hw);
9d5c8243
AK		 7121
7122 wr32(E1000_WUC, E1000_WUC_PME_EN);
7123 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7124 } else {
7125 wr32(E1000_WUC, 0);
7126 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7127 }
7128
3fe7c4c9
RW		 7129 *enable_wake = wufc || adapter->en_mng_pt;
7130 if (!*enable_wake)
88a268c1
NN		 7131 igb_power_down_link(adapter);
7132 else
7133 igb_power_up_link(adapter);
9d5c8243
AK		 7134
7135 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7136 * would have already happened in close and is redundant.
7137 */
9d5c8243
AK		 7138 igb_release_hw_control(adapter);
7139
7140 pci_disable_device(pdev);
7141
9d5c8243
AK		 7142 return 0;
7143}
7144
7145#ifdef CONFIG_PM
d9dd966d 7146#ifdef CONFIG_PM_SLEEP
749ab2cd 7147static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7148{
7149 int retval;
7150 bool wake;
749ab2cd 7151 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7152
749ab2cd 7153 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7154 if (retval)
7155 return retval;
7156
7157 if (wake) {
7158 pci_prepare_to_sleep(pdev);
7159 } else {
7160 pci_wake_from_d3(pdev, false);
7161 pci_set_power_state(pdev, PCI_D3hot);
7162 }
7163
7164 return 0;
7165}
d9dd966d 7166#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7167
749ab2cd 7168static int igb_resume(struct device *dev)
9d5c8243 7169{
749ab2cd 7170 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7171 struct net_device *netdev = pci_get_drvdata(pdev);
7172 struct igb_adapter *adapter = netdev_priv(netdev);
7173 struct e1000_hw *hw = &adapter->hw;
7174 u32 err;
7175
7176 pci_set_power_state(pdev, PCI_D0);
7177 pci_restore_state(pdev);
b94f2d77 7178 pci_save_state(pdev);
42bfd33a 7179
aed5dec3 7180 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7181 if (err) {
7182 dev_err(&pdev->dev,
7183 "igb: Cannot enable PCI device from suspend\n");
7184 return err;
7185 }
7186 pci_set_master(pdev);
7187
7188 pci_enable_wake(pdev, PCI_D3hot, 0);
7189 pci_enable_wake(pdev, PCI_D3cold, 0);
7190
53c7d064 7191 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7192 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7193 return -ENOMEM;
9d5c8243
AK		 7194 }
7195
9d5c8243 7196 igb_reset(adapter);
a8564f03
AD		 7197
7198 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7199 * driver.
7200 */
a8564f03
AD		 7201 igb_get_hw_control(adapter);
7202
9d5c8243
AK		 7203 wr32(E1000_WUS, ~0);
7204
749ab2cd 7205 if (netdev->flags & IFF_UP) {
0c2cc02e 7206 rtnl_lock();
749ab2cd 7207 err = __igb_open(netdev, true);
0c2cc02e 7208 rtnl_unlock();
a88f10ec
AD		 7209 if (err)
7210 return err;
7211 }
9d5c8243
AK		 7212
7213 netif_device_attach(netdev);
749ab2cd
YZ		 7214 return 0;
7215}
7216
7217#ifdef CONFIG_PM_RUNTIME
7218static int igb_runtime_idle(struct device *dev)
7219{
7220 struct pci_dev *pdev = to_pci_dev(dev);
7221 struct net_device *netdev = pci_get_drvdata(pdev);
7222 struct igb_adapter *adapter = netdev_priv(netdev);
7223
7224 if (!igb_has_link(adapter))
7225 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7226
7227 return -EBUSY;
7228}
7229
7230static int igb_runtime_suspend(struct device *dev)
7231{
7232 struct pci_dev *pdev = to_pci_dev(dev);
7233 int retval;
7234 bool wake;
7235
7236 retval = __igb_shutdown(pdev, &wake, 1);
7237 if (retval)
7238 return retval;
7239
7240 if (wake) {
7241 pci_prepare_to_sleep(pdev);
7242 } else {
7243 pci_wake_from_d3(pdev, false);
7244 pci_set_power_state(pdev, PCI_D3hot);
7245 }
9d5c8243 7246
9d5c8243
AK		 7247 return 0;
7248}
749ab2cd
YZ		 7249
7250static int igb_runtime_resume(struct device *dev)
7251{
7252 return igb_resume(dev);
7253}
7254#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7255#endif
7256
7257static void igb_shutdown(struct pci_dev *pdev)
7258{
3fe7c4c9
RW		 7259 bool wake;
7260
749ab2cd 7261 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7262
7263 if (system_state == SYSTEM_POWER_OFF) {
7264 pci_wake_from_d3(pdev, wake);
7265 pci_set_power_state(pdev, PCI_D3hot);
7266 }
9d5c8243
AK		 7267}
7268
fa44f2f1
GR		 7269#ifdef CONFIG_PCI_IOV
7270static int igb_sriov_reinit(struct pci_dev *dev)
7271{
7272 struct net_device *netdev = pci_get_drvdata(dev);
7273 struct igb_adapter *adapter = netdev_priv(netdev);
7274 struct pci_dev *pdev = adapter->pdev;
7275
7276 rtnl_lock();
7277
7278 if (netif_running(netdev))
7279 igb_close(netdev);
7280
7281 igb_clear_interrupt_scheme(adapter);
7282
7283 igb_init_queue_configuration(adapter);
7284
7285 if (igb_init_interrupt_scheme(adapter, true)) {
7286 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7287 return -ENOMEM;
7288 }
7289
7290 if (netif_running(netdev))
7291 igb_open(netdev);
7292
7293 rtnl_unlock();
7294
7295 return 0;
7296}
7297
7298static int igb_pci_disable_sriov(struct pci_dev *dev)
7299{
7300 int err = igb_disable_sriov(dev);
7301
7302 if (!err)
7303 err = igb_sriov_reinit(dev);
7304
7305 return err;
7306}
7307
7308static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7309{
7310 int err = igb_enable_sriov(dev, num_vfs);
7311
7312 if (err)
7313 goto out;
7314
7315 err = igb_sriov_reinit(dev);
7316 if (!err)
7317 return num_vfs;
7318
7319out:
7320 return err;
7321}
7322
7323#endif
7324static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7325{
7326#ifdef CONFIG_PCI_IOV
7327 if (num_vfs == 0)
7328 return igb_pci_disable_sriov(dev);
7329 else
7330 return igb_pci_enable_sriov(dev, num_vfs);
7331#endif
7332 return 0;
7333}
7334
9d5c8243 7335#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7336/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7337 * without having to re-enable interrupts. It's not called while
7338 * the interrupt routine is executing.
7339 */
7340static void igb_netpoll(struct net_device *netdev)
7341{
7342 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7343 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7344 struct igb_q_vector *q_vector;
9d5c8243 7345 int i;
9d5c8243 7346
047e0030 7347 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7348 q_vector = adapter->q_vector[i];
7349 if (adapter->msix_entries)
7350 wr32(E1000_EIMC, q_vector->eims_value);
7351 else
7352 igb_irq_disable(adapter);
047e0030 7353 napi_schedule(&q_vector->napi);
eebbbdba 7354 }
9d5c8243
AK		 7355}
7356#endif /* CONFIG_NET_POLL_CONTROLLER */
7357
7358/**
b980ac18
JK		 7359 * igb_io_error_detected - called when PCI error is detected
7360 * @pdev: Pointer to PCI device
7361 * @state: The current pci connection state
9d5c8243 7362 *
b980ac18
JK		 7363 * This function is called after a PCI bus error affecting
7364 * this device has been detected.
7365 **/
9d5c8243
AK		 7366static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7367 pci_channel_state_t state)
7368{
7369 struct net_device *netdev = pci_get_drvdata(pdev);
7370 struct igb_adapter *adapter = netdev_priv(netdev);
7371
7372 netif_device_detach(netdev);
7373
59ed6eec
AD		 7374 if (state == pci_channel_io_perm_failure)
7375 return PCI_ERS_RESULT_DISCONNECT;
7376
9d5c8243
AK		 7377 if (netif_running(netdev))
7378 igb_down(adapter);
7379 pci_disable_device(pdev);
7380
7381 /* Request a slot slot reset. */
7382 return PCI_ERS_RESULT_NEED_RESET;
7383}
7384
7385/**
b980ac18
JK		 7386 * igb_io_slot_reset - called after the pci bus has been reset.
7387 * @pdev: Pointer to PCI device
9d5c8243 7388 *
b980ac18
JK		 7389 * Restart the card from scratch, as if from a cold-boot. Implementation
7390 * resembles the first-half of the igb_resume routine.
7391 **/
9d5c8243
AK		 7392static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7393{
7394 struct net_device *netdev = pci_get_drvdata(pdev);
7395 struct igb_adapter *adapter = netdev_priv(netdev);
7396 struct e1000_hw *hw = &adapter->hw;
40a914fa 7397 pci_ers_result_t result;
42bfd33a 7398 int err;
9d5c8243 7399
aed5dec3 7400 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7401 dev_err(&pdev->dev,
7402 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7403 result = PCI_ERS_RESULT_DISCONNECT;
7404 } else {
7405 pci_set_master(pdev);
7406 pci_restore_state(pdev);
b94f2d77 7407 pci_save_state(pdev);
9d5c8243 7408
40a914fa
AD		 7409 pci_enable_wake(pdev, PCI_D3hot, 0);
7410 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7411
40a914fa
AD		 7412 igb_reset(adapter);
7413 wr32(E1000_WUS, ~0);
7414 result = PCI_ERS_RESULT_RECOVERED;
7415 }
9d5c8243 7416
ea943d41
JK		 7417 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7418 if (err) {
b980ac18
JK		 7419 dev_err(&pdev->dev,
7420 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7421 err);
ea943d41
JK		 7422 /* non-fatal, continue */
7423 }
40a914fa
AD		 7424
7425 return result;
9d5c8243
AK		 7426}
7427
7428/**
b980ac18
JK		 7429 * igb_io_resume - called when traffic can start flowing again.
7430 * @pdev: Pointer to PCI device
9d5c8243 7431 *
b980ac18
JK		 7432 * This callback is called when the error recovery driver tells us that
7433 * its OK to resume normal operation. Implementation resembles the
7434 * second-half of the igb_resume routine.
9d5c8243
AK		 7435 */
7436static void igb_io_resume(struct pci_dev *pdev)
7437{
7438 struct net_device *netdev = pci_get_drvdata(pdev);
7439 struct igb_adapter *adapter = netdev_priv(netdev);
7440
9d5c8243
AK		 7441 if (netif_running(netdev)) {
7442 if (igb_up(adapter)) {
7443 dev_err(&pdev->dev, "igb_up failed after reset\n");
7444 return;
7445 }
7446 }
7447
7448 netif_device_attach(netdev);
7449
7450 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7451 * driver.
7452 */
9d5c8243 7453 igb_get_hw_control(adapter);
9d5c8243
AK		 7454}
7455
26ad9178 7456static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7457 u8 qsel)
26ad9178
AD		 7458{
7459 u32 rar_low, rar_high;
7460 struct e1000_hw *hw = &adapter->hw;
7461
7462 /* HW expects these in little endian so we reverse the byte order
7463 * from network order (big endian) to little endian
7464 */
7465 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7466 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7467 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7468
7469 /* Indicate to hardware the Address is Valid. */
7470 rar_high |= E1000_RAH_AV;
7471
7472 if (hw->mac.type == e1000_82575)
7473 rar_high |= E1000_RAH_POOL_1 * qsel;
7474 else
7475 rar_high |= E1000_RAH_POOL_1 << qsel;
7476
7477 wr32(E1000_RAL(index), rar_low);
7478 wrfl();
7479 wr32(E1000_RAH(index), rar_high);
7480 wrfl();
7481}
7482
4ae196df 7483static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7484 int vf, unsigned char *mac_addr)
4ae196df
AD		 7485{
7486 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7487 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7488 * towards the first, as a result a collision should not be possible
7489 */
ff41f8dc 7490 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7491
37680117 7492 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7493
26ad9178 7494 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7495
7496 return 0;
7497}
7498
8151d294
WM		 7499static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7500{
7501 struct igb_adapter *adapter = netdev_priv(netdev);
7502 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7503 return -EINVAL;
7504 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7505 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7506 dev_info(&adapter->pdev->dev,
7507 "Reload the VF driver to make this change effective.");
8151d294 7508 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7509 dev_warn(&adapter->pdev->dev,
7510 "The VF MAC address has been set, but the PF device is not up.\n");
7511 dev_warn(&adapter->pdev->dev,
7512 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7513 }
7514 return igb_set_vf_mac(adapter, vf, mac);
7515}
7516
17dc566c
LL		 7517static int igb_link_mbps(int internal_link_speed)
7518{
7519 switch (internal_link_speed) {
7520 case SPEED_100:
7521 return 100;
7522 case SPEED_1000:
7523 return 1000;
7524 default:
7525 return 0;
7526 }
7527}
7528
7529static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7530 int link_speed)
7531{
7532 int rf_dec, rf_int;
7533 u32 bcnrc_val;
7534
7535 if (tx_rate != 0) {
7536 /* Calculate the rate factor values to set */
7537 rf_int = link_speed / tx_rate;
7538 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7539 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7540 tx_rate;
17dc566c
LL		 7541
7542 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7543 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7544 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7545 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7546 } else {
7547 bcnrc_val = 0;
7548 }
7549
7550 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7551 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7552 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7553 */
7554 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7555 wr32(E1000_RTTBCNRC, bcnrc_val);
7556}
7557
7558static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7559{
7560 int actual_link_speed, i;
7561 bool reset_rate = false;
7562
7563 /* VF TX rate limit was not set or not supported */
7564 if ((adapter->vf_rate_link_speed == 0) ||
7565 (adapter->hw.mac.type != e1000_82576))
7566 return;
7567
7568 actual_link_speed = igb_link_mbps(adapter->link_speed);
7569 if (actual_link_speed != adapter->vf_rate_link_speed) {
7570 reset_rate = true;
7571 adapter->vf_rate_link_speed = 0;
7572 dev_info(&adapter->pdev->dev,
b980ac18 7573 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7574 }
7575
7576 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7577 if (reset_rate)
7578 adapter->vf_data[i].tx_rate = 0;
7579
7580 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7581 adapter->vf_data[i].tx_rate,
7582 actual_link_speed);
17dc566c
LL		 7583 }
7584}
7585
8151d294
WM		 7586static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7587{
17dc566c
LL		 7588 struct igb_adapter *adapter = netdev_priv(netdev);
7589 struct e1000_hw *hw = &adapter->hw;
7590 int actual_link_speed;
7591
7592 if (hw->mac.type != e1000_82576)
7593 return -EOPNOTSUPP;
7594
7595 actual_link_speed = igb_link_mbps(adapter->link_speed);
7596 if ((vf >= adapter->vfs_allocated_count) ||
7597 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7598 (tx_rate < 0) || (tx_rate > actual_link_speed))
7599 return -EINVAL;
7600
7601 adapter->vf_rate_link_speed = actual_link_speed;
7602 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7603 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7604
7605 return 0;
8151d294
WM		 7606}
7607
70ea4783
LL		 7608static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7609 bool setting)
7610{
7611 struct igb_adapter *adapter = netdev_priv(netdev);
7612 struct e1000_hw *hw = &adapter->hw;
7613 u32 reg_val, reg_offset;
7614
7615 if (!adapter->vfs_allocated_count)
7616 return -EOPNOTSUPP;
7617
7618 if (vf >= adapter->vfs_allocated_count)
7619 return -EINVAL;
7620
7621 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7622 reg_val = rd32(reg_offset);
7623 if (setting)
7624 reg_val |= ((1 << vf) |
7625 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7626 else
7627 reg_val &= ~((1 << vf) |
7628 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7629 wr32(reg_offset, reg_val);
7630
7631 adapter->vf_data[vf].spoofchk_enabled = setting;
7632 return E1000_SUCCESS;
7633}
7634
8151d294
WM		 7635static int igb_ndo_get_vf_config(struct net_device *netdev,
7636 int vf, struct ifla_vf_info *ivi)
7637{
7638 struct igb_adapter *adapter = netdev_priv(netdev);
7639 if (vf >= adapter->vfs_allocated_count)
7640 return -EINVAL;
7641 ivi->vf = vf;
7642 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7643 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7644 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7645 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7646 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7647 return 0;
7648}
7649
4ae196df
AD		 7650static void igb_vmm_control(struct igb_adapter *adapter)
7651{
7652 struct e1000_hw *hw = &adapter->hw;
10d8e907 7653 u32 reg;
4ae196df 7654
52a1dd4d
AD		 7655 switch (hw->mac.type) {
7656 case e1000_82575:
f96a8a0b
CW		 7657 case e1000_i210:
7658 case e1000_i211:
ceb5f13b 7659 case e1000_i354:
52a1dd4d
AD		 7660 default:
7661 /* replication is not supported for 82575 */
4ae196df 7662 return;
52a1dd4d
AD		 7663 case e1000_82576:
7664 /* notify HW that the MAC is adding vlan tags */
7665 reg = rd32(E1000_DTXCTL);
7666 reg |= E1000_DTXCTL_VLAN_ADDED;
7667 wr32(E1000_DTXCTL, reg);
7668 case e1000_82580:
7669 /* enable replication vlan tag stripping */
7670 reg = rd32(E1000_RPLOLR);
7671 reg |= E1000_RPLOLR_STRVLAN;
7672 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7673 case e1000_i350:
7674 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7675 break;
7676 }
10d8e907 7677
d4960307
AD		 7678 if (adapter->vfs_allocated_count) {
7679 igb_vmdq_set_loopback_pf(hw, true);
7680 igb_vmdq_set_replication_pf(hw, true);
13800469 7681 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7682 adapter->vfs_allocated_count);
d4960307
AD		 7683 } else {
7684 igb_vmdq_set_loopback_pf(hw, false);
7685 igb_vmdq_set_replication_pf(hw, false);
7686 }
4ae196df
AD		 7687}
7688
b6e0c419
CW		 7689static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7690{
7691 struct e1000_hw *hw = &adapter->hw;
7692 u32 dmac_thr;
7693 u16 hwm;
7694
7695 if (hw->mac.type > e1000_82580) {
7696 if (adapter->flags & IGB_FLAG_DMAC) {
7697 u32 reg;
7698
7699 /* force threshold to 0. */
7700 wr32(E1000_DMCTXTH, 0);
7701
b980ac18 7702 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7703 * than the Rx threshold. Set hwm to PBA - max frame
7704 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7705 */
e8c626e9
MV		 7706 hwm = 64 * pba - adapter->max_frame_size / 16;
7707 if (hwm < 64 * (pba - 6))
7708 hwm = 64 * (pba - 6);
7709 reg = rd32(E1000_FCRTC);
7710 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7711 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7712 & E1000_FCRTC_RTH_COAL_MASK);
7713 wr32(E1000_FCRTC, reg);
7714
b980ac18 7715 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7716 * frame size, capping it at PBA - 10KB.
7717 */
7718 dmac_thr = pba - adapter->max_frame_size / 512;
7719 if (dmac_thr < pba - 10)
7720 dmac_thr = pba - 10;
b6e0c419
CW		 7721 reg = rd32(E1000_DMACR);
7722 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7723 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7724 & E1000_DMACR_DMACTHR_MASK);
7725
7726 /* transition to L0x or L1 if available..*/
7727 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7728
7729 /* watchdog timer= +-1000 usec in 32usec intervals */
7730 reg |= (1000 >> 5);
0c02dd98
MV		 7731
7732 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7733 if (hw->mac.type != e1000_i354)
7734 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7735
b6e0c419
CW		 7736 wr32(E1000_DMACR, reg);
7737
b980ac18 7738 /* no lower threshold to disable
b6e0c419
CW		 7739 * coalescing(smart fifb)-UTRESH=0
7740 */
7741 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7742
7743 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7744
7745 wr32(E1000_DMCTLX, reg);
7746
b980ac18 7747 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7748 * DMA coal
7749 */
7750 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7751 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7752
b980ac18 7753 /* make low power state decision controlled
b6e0c419
CW		 7754 * by DMA coal
7755 */
7756 reg = rd32(E1000_PCIEMISC);
7757 reg &= ~E1000_PCIEMISC_LX_DECISION;
7758 wr32(E1000_PCIEMISC, reg);
7759 } /* endif adapter->dmac is not disabled */
7760 } else if (hw->mac.type == e1000_82580) {
7761 u32 reg = rd32(E1000_PCIEMISC);
7762 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7763 wr32(E1000_DMACR, 0);
7764 }
7765}
7766
b980ac18
JK		 7767/**
7768 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7769 * @hw: pointer to hardware structure
7770 * @byte_offset: byte offset to read
7771 * @dev_addr: device address
7772 * @data: value read
7773 *
7774 * Performs byte read operation over I2C interface at
7775 * a specified device address.
b980ac18 7776 **/
441fc6fd 7777s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7778 u8 dev_addr, u8 *data)
441fc6fd
CW		 7779{
7780 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7781 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7782 s32 status;
7783 u16 swfw_mask = 0;
7784
7785 if (!this_client)
7786 return E1000_ERR_I2C;
7787
7788 swfw_mask = E1000_SWFW_PHY0_SM;
7789
7790 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7791 != E1000_SUCCESS)
7792 return E1000_ERR_SWFW_SYNC;
7793
7794 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7795 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7796
7797 if (status < 0)
7798 return E1000_ERR_I2C;
7799 else {
7800 *data = status;
7801 return E1000_SUCCESS;
7802 }
7803}
7804
b980ac18
JK		 7805/**
7806 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7807 * @hw: pointer to hardware structure
7808 * @byte_offset: byte offset to write
7809 * @dev_addr: device address
7810 * @data: value to write
7811 *
7812 * Performs byte write operation over I2C interface at
7813 * a specified device address.
b980ac18 7814 **/
441fc6fd 7815s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7816 u8 dev_addr, u8 data)
441fc6fd
CW		 7817{
7818 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7819 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7820 s32 status;
7821 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7822
7823 if (!this_client)
7824 return E1000_ERR_I2C;
7825
7826 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7827 return E1000_ERR_SWFW_SYNC;
7828 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7829 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7830
7831 if (status)
7832 return E1000_ERR_I2C;
7833 else
7834 return E1000_SUCCESS;
7835
7836}
907b7835
LMV		 7837
7838int igb_reinit_queues(struct igb_adapter *adapter)
7839{
7840 struct net_device *netdev = adapter->netdev;
7841 struct pci_dev *pdev = adapter->pdev;
7842 int err = 0;
7843
7844 if (netif_running(netdev))
7845 igb_close(netdev);
7846
7847 igb_clear_interrupt_scheme(adapter);
7848
7849 if (igb_init_interrupt_scheme(adapter, true)) {
7850 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7851 return -ENOMEM;
7852 }
7853
7854 if (netif_running(netdev))
7855 err = igb_open(netdev);
7856
7857 return err;
7858}
9d5c8243 7859/* igb_main.c */
Linux kernel - Deliverables
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