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igb: Add ethtool offline tests for i354
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
876d2d6f
JK		 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
9d5c8243
AK		 30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/init.h>
b2cb09b1 33#include <linux/bitops.h>
9d5c8243
AK		 34#include <linux/vmalloc.h>
35#include <linux/pagemap.h>
36#include <linux/netdevice.h>
9d5c8243 37#include <linux/ipv6.h>
5a0e3ad6 38#include <linux/slab.h>
9d5c8243
AK		 39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
c6cb090b 41#include <linux/net_tstamp.h>
9d5c8243
AK		 42#include <linux/mii.h>
43#include <linux/ethtool.h>
01789349 44#include <linux/if.h>
9d5c8243
AK		 45#include <linux/if_vlan.h>
46#include <linux/pci.h>
c54106bb 47#include <linux/pci-aspm.h>
9d5c8243
AK		 48#include <linux/delay.h>
49#include <linux/interrupt.h>
7d13a7d0
AD		 50#include <linux/ip.h>
51#include <linux/tcp.h>
52#include <linux/sctp.h>
9d5c8243 53#include <linux/if_ether.h>
40a914fa 54#include <linux/aer.h>
70c71606 55#include <linux/prefetch.h>
749ab2cd 56#include <linux/pm_runtime.h>
421e02f0 57#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 58#include <linux/dca.h>
59#endif
441fc6fd 60#include <linux/i2c.h>
9d5c8243
AK		 61#include "igb.h"
62
67b1b903
CW		 63#define MAJ 5
64#define MIN 0
66f40b8a 65#define BUILD 5
0d1fe82d 66#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 67__stringify(BUILD) "-k"
9d5c8243
AK		 68char igb_driver_name[] = "igb";
69char igb_driver_version[] = DRV_VERSION;
70static const char igb_driver_string[] =
71 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462
AA		 72static const char igb_copyright[] =
73 "Copyright (c) 2007-2013 Intel Corporation.";
9d5c8243 74
9d5c8243
AK		 75static const struct e1000_info *igb_info_tbl[] = {
76 [board_82575] = &e1000_82575_info,
77};
78
a3aa1884 79static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
115 /* required last entry */
116 {0, }
117};
118
119MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
120
121void igb_reset(struct igb_adapter *);
122static int igb_setup_all_tx_resources(struct igb_adapter *);
123static int igb_setup_all_rx_resources(struct igb_adapter *);
124static void igb_free_all_tx_resources(struct igb_adapter *);
125static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 126static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 127static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 128static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 129static int igb_sw_init(struct igb_adapter *);
130static int igb_open(struct net_device *);
131static int igb_close(struct net_device *);
53c7d064 132static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 133static void igb_configure_tx(struct igb_adapter *);
134static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 135static void igb_clean_all_tx_rings(struct igb_adapter *);
136static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 137static void igb_clean_tx_ring(struct igb_ring *);
138static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 139static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 140static void igb_update_phy_info(unsigned long);
141static void igb_watchdog(unsigned long);
142static void igb_watchdog_task(struct work_struct *);
cd392f5c 143static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 144static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
145 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 146static int igb_change_mtu(struct net_device *, int);
147static int igb_set_mac(struct net_device *, void *);
68d480c4 148static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 149static irqreturn_t igb_intr(int irq, void *);
150static irqreturn_t igb_intr_msi(int irq, void *);
151static irqreturn_t igb_msix_other(int irq, void *);
047e0030 152static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 153#ifdef CONFIG_IGB_DCA
047e0030 154static void igb_update_dca(struct igb_q_vector *);
fe4506b6 155static void igb_setup_dca(struct igb_adapter *);
421e02f0 156#endif /* CONFIG_IGB_DCA */
661086df 157static int igb_poll(struct napi_struct *, int);
13fde97a 158static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 159static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 160static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
161static void igb_tx_timeout(struct net_device *);
162static void igb_reset_task(struct work_struct *);
c8f44aff 163static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 164static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
165static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 166static void igb_restore_vlan(struct igb_adapter *);
26ad9178 167static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 168static void igb_ping_all_vfs(struct igb_adapter *);
169static void igb_msg_task(struct igb_adapter *);
4ae196df 170static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 171static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 172static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 173static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
174static int igb_ndo_set_vf_vlan(struct net_device *netdev,
175 int vf, u16 vlan, u8 qos);
176static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 177static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
178 bool setting);
8151d294
WM		 179static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
180 struct ifla_vf_info *ivi);
17dc566c 181static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 182
183#ifdef CONFIG_PCI_IOV
0224d663 184static int igb_vf_configure(struct igb_adapter *adapter, int vf);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd
YZ		 191static int igb_resume(struct device *);
192#ifdef CONFIG_PM_RUNTIME
193static int igb_runtime_suspend(struct device *dev);
194static int igb_runtime_resume(struct device *dev);
195static int igb_runtime_idle(struct device *dev);
196#endif
197static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201};
9d5c8243
AK		 202#endif
203static void igb_shutdown(struct pci_dev *);
fa44f2f1 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 205#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211};
212#endif
9d5c8243
AK		 213#ifdef CONFIG_NET_POLL_CONTROLLER
214/* for netdump / net console */
215static void igb_netpoll(struct net_device *);
216#endif
37680117 217#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 218static unsigned int max_vfs = 0;
219module_param(max_vfs, uint, 0);
220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
221 "per physical function");
222#endif /* CONFIG_PCI_IOV */
223
9d5c8243
AK		 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227static void igb_io_resume(struct pci_dev *);
228
3646f0e5 229static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233};
234
b6e0c419 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 236
237static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
9f9a12f8 241 .remove = igb_remove,
9d5c8243 242#ifdef CONFIG_PM
749ab2cd 243 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 244#endif
245 .shutdown = igb_shutdown,
fa44f2f1 246 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 247 .err_handler = &igb_err_handler
248};
249
250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252MODULE_LICENSE("GPL");
253MODULE_VERSION(DRV_VERSION);
254
b3f4d599 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256static int debug = -1;
257module_param(debug, int, 0);
258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
c97ec42a
TI		 260struct igb_reg_info {
261 u32 ofs;
262 char *name;
263};
264
265static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299};
300
b980ac18 301/* igb_regdump - register printout routine */
c97ec42a
TI		 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303{
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
876d2d6f 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
c97ec42a
TI		 365}
366
b980ac18 367/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 368static void igb_dump(struct igb_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
c97ec42a
TI		 373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
6ad4edfc 379 u16 i, n;
c97ec42a
TI		 380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 387 pr_info("Device Name state trans_start "
388 "last_rx\n");
389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
390 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 391 }
392
393 /* Print Registers */
394 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 395 pr_info(" Register Name Value\n");
c97ec42a
TI		 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
397 reginfo->name; reginfo++) {
398 igb_regdump(hw, reginfo);
399 }
400
401 /* Print TX Ring Summary */
402 if (!netdev || !netif_running(netdev))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 407 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 408 struct igb_tx_buffer *buffer_info;
c97ec42a 409 tx_ring = adapter->tx_ring[n];
06034649 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
412 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 413 (u64)dma_unmap_addr(buffer_info, dma),
414 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 415 buffer_info->next_to_watch,
416 (u64)buffer_info->time_stamp);
c97ec42a
TI		 417 }
418
419 /* Print TX Rings */
420 if (!netif_msg_tx_done(adapter))
421 goto rx_ring_summary;
422
423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
424
425 /* Transmit Descriptor Formats
426 *
427 * Advanced Transmit Descriptor
428 * +--------------------------------------------------------------+
429 * 0 | Buffer Address [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
432 * +--------------------------------------------------------------+
433 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
442 "[bi->dma ] leng ntw timestamp "
443 "bi->skb\n");
c97ec42a
TI		 444
445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 446 const char *next_desc;
06034649 447 struct igb_tx_buffer *buffer_info;
60136906 448 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 449 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 450 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 451 if (i == tx_ring->next_to_use &&
452 i == tx_ring->next_to_clean)
453 next_desc = " NTC/U";
454 else if (i == tx_ring->next_to_use)
455 next_desc = " NTU";
456 else if (i == tx_ring->next_to_clean)
457 next_desc = " NTC";
458 else
459 next_desc = "";
460
461 pr_info("T [0x%03X] %016llX %016llX %016llX"
462 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
c9f14bf3
AD		 465 (u64)dma_unmap_addr(buffer_info, dma),
466 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 467 buffer_info->next_to_watch,
468 (u64)buffer_info->time_stamp,
876d2d6f 469 buffer_info->skb, next_desc);
c97ec42a 470
b669588a 471 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS,
b669588a 474 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 475 dma_unmap_len(buffer_info, len),
476 true);
c97ec42a
TI		 477 }
478 }
479
480 /* Print RX Rings Summary */
481rx_ring_summary:
482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 483 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 486 pr_info(" %5d %5X %5X\n",
487 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 488 }
489
490 /* Print RX Rings */
491 if (!netif_msg_rx_status(adapter))
492 goto exit;
493
494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
495
496 /* Advanced Receive Descriptor (Read) Format
497 * 63 1 0
498 * +-----------------------------------------------------+
499 * 0 | Packet Buffer Address [63:1] |A0/NSE|
500 * +----------------------------------------------+------+
501 * 8 | Header Buffer Address [63:1] | DD |
502 * +-----------------------------------------------------+
503 *
504 *
505 * Advanced Receive Descriptor (Write-Back) Format
506 *
507 * 63 48 47 32 31 30 21 20 17 16 4 3 0
508 * +------------------------------------------------------+
509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
510 * | Checksum Ident | | | | Type | Type |
511 * +------------------------------------------------------+
512 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
513 * +------------------------------------------------------+
514 * 63 48 47 32 31 20 19 0
515 */
516
517 for (n = 0; n < adapter->num_rx_queues; n++) {
518 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 519 pr_info("------------------------------------\n");
520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 526
527 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 528 const char *next_desc;
06034649
AD		 529 struct igb_rx_buffer *buffer_info;
530 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 531 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 532 u0 = (struct my_u0 *)rx_desc;
533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 534
535 if (i == rx_ring->next_to_use)
536 next_desc = " NTU";
537 else if (i == rx_ring->next_to_clean)
538 next_desc = " NTC";
539 else
540 next_desc = "";
541
c97ec42a
TI		 542 if (staterr & E1000_RXD_STAT_DD) {
543 /* Descriptor Done */
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
545 "RWB", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
1a1c225b 548 next_desc);
c97ec42a 549 } else {
1a1c225b
AD		 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
551 "R ", i,
c97ec42a
TI		 552 le64_to_cpu(u0->a),
553 le64_to_cpu(u0->b),
554 (u64)buffer_info->dma,
1a1c225b 555 next_desc);
c97ec42a 556
b669588a 557 if (netif_msg_pktdata(adapter) &&
1a1c225b 558 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 559 print_hex_dump(KERN_INFO, "",
560 DUMP_PREFIX_ADDRESS,
561 16, 1,
b669588a
ET		 562 page_address(buffer_info->page) +
563 buffer_info->page_offset,
de78d1f9 564 IGB_RX_BUFSZ, true);
c97ec42a
TI		 565 }
566 }
c97ec42a
TI		 567 }
568 }
569
570exit:
571 return;
572}
573
b980ac18
JK		 574/**
575 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 576 * @hw: pointer to hardware structure
577 * @i2cctl: Current value of I2CCTL register
578 *
579 * Returns the I2C data bit value
b980ac18 580 **/
441fc6fd
CW		 581static int igb_get_i2c_data(void *data)
582{
583 struct igb_adapter *adapter = (struct igb_adapter *)data;
584 struct e1000_hw *hw = &adapter->hw;
585 s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
588}
589
b980ac18
JK		 590/**
591 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 592 * @data: pointer to hardware structure
593 * @state: I2C data value (0 or 1) to set
594 *
595 * Sets the I2C data bit
b980ac18 596 **/
441fc6fd
CW		 597static void igb_set_i2c_data(void *data, int state)
598{
599 struct igb_adapter *adapter = (struct igb_adapter *)data;
600 struct e1000_hw *hw = &adapter->hw;
601 s32 i2cctl = rd32(E1000_I2CPARAMS);
602
603 if (state)
604 i2cctl |= E1000_I2C_DATA_OUT;
605 else
606 i2cctl &= ~E1000_I2C_DATA_OUT;
607
608 i2cctl &= ~E1000_I2C_DATA_OE_N;
609 i2cctl |= E1000_I2C_CLK_OE_N;
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612
613}
614
b980ac18
JK		 615/**
616 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 617 * @data: pointer to hardware structure
618 * @state: state to set clock
619 *
620 * Sets the I2C clock line to state
b980ac18 621 **/
441fc6fd
CW		 622static void igb_set_i2c_clk(void *data, int state)
623{
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 if (state) {
629 i2cctl |= E1000_I2C_CLK_OUT;
630 i2cctl &= ~E1000_I2C_CLK_OE_N;
631 } else {
632 i2cctl &= ~E1000_I2C_CLK_OUT;
633 i2cctl &= ~E1000_I2C_CLK_OE_N;
634 }
635 wr32(E1000_I2CPARAMS, i2cctl);
636 wrfl();
637}
638
b980ac18
JK		 639/**
640 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 641 * @data: pointer to hardware structure
642 *
643 * Gets the I2C clock state
b980ac18 644 **/
441fc6fd
CW		 645static int igb_get_i2c_clk(void *data)
646{
647 struct igb_adapter *adapter = (struct igb_adapter *)data;
648 struct e1000_hw *hw = &adapter->hw;
649 s32 i2cctl = rd32(E1000_I2CPARAMS);
650
651 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
652}
653
654static const struct i2c_algo_bit_data igb_i2c_algo = {
655 .setsda = igb_set_i2c_data,
656 .setscl = igb_set_i2c_clk,
657 .getsda = igb_get_i2c_data,
658 .getscl = igb_get_i2c_clk,
659 .udelay = 5,
660 .timeout = 20,
661};
662
9d5c8243 663/**
b980ac18
JK		 664 * igb_get_hw_dev - return device
665 * @hw: pointer to hardware structure
666 *
667 * used by hardware layer to print debugging information
9d5c8243 668 **/
c041076a 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 670{
671 struct igb_adapter *adapter = hw->back;
c041076a 672 return adapter->netdev;
9d5c8243 673}
38c845c7 674
9d5c8243 675/**
b980ac18 676 * igb_init_module - Driver Registration Routine
9d5c8243 677 *
b980ac18
JK		 678 * igb_init_module is the first routine called when the driver is
679 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 680 **/
681static int __init igb_init_module(void)
682{
683 int ret;
876d2d6f 684 pr_info("%s - version %s\n",
9d5c8243
AK		 685 igb_driver_string, igb_driver_version);
686
876d2d6f 687 pr_info("%s\n", igb_copyright);
9d5c8243 688
421e02f0 689#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 690 dca_register_notify(&dca_notifier);
691#endif
bbd98fe4 692 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 693 return ret;
694}
695
696module_init(igb_init_module);
697
698/**
b980ac18 699 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 700 *
b980ac18
JK		 701 * igb_exit_module is called just before the driver is removed
702 * from memory.
9d5c8243
AK		 703 **/
704static void __exit igb_exit_module(void)
705{
421e02f0 706#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 707 dca_unregister_notify(&dca_notifier);
708#endif
9d5c8243
AK		 709 pci_unregister_driver(&igb_driver);
710}
711
712module_exit(igb_exit_module);
713
26bc19ec
AD		 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
715/**
b980ac18
JK		 716 * igb_cache_ring_register - Descriptor ring to register mapping
717 * @adapter: board private structure to initialize
26bc19ec 718 *
b980ac18
JK		 719 * Once we know the feature-set enabled for the device, we'll cache
720 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 721 **/
722static void igb_cache_ring_register(struct igb_adapter *adapter)
723{
ee1b9f06 724 int i = 0, j = 0;
047e0030 725 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 726
727 switch (adapter->hw.mac.type) {
728 case e1000_82576:
729 /* The queues are allocated for virtualization such that VF 0
730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
731 * In order to avoid collision we start at the first free queue
732 * and continue consuming queues in the same sequence
733 */
ee1b9f06 734 if (adapter->vfs_allocated_count) {
a99955fc 735 for (; i < adapter->rss_queues; i++)
3025a446 736 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 737 Q_IDX_82576(i);
ee1b9f06 738 }
26bc19ec 739 case e1000_82575:
55cac248 740 case e1000_82580:
d2ba2ed8 741 case e1000_i350:
ceb5f13b 742 case e1000_i354:
f96a8a0b
CW		 743 case e1000_i210:
744 case e1000_i211:
26bc19ec 745 default:
ee1b9f06 746 for (; i < adapter->num_rx_queues; i++)
3025a446 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 748 for (; j < adapter->num_tx_queues; j++)
3025a446 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 750 break;
751 }
752}
753
4be000c8
AD		 754/**
755 * igb_write_ivar - configure ivar for given MSI-X vector
756 * @hw: pointer to the HW structure
757 * @msix_vector: vector number we are allocating to a given ring
758 * @index: row index of IVAR register to write within IVAR table
759 * @offset: column offset of in IVAR, should be multiple of 8
760 *
761 * This function is intended to handle the writing of the IVAR register
762 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
763 * each containing an cause allocation for an Rx and Tx ring, and a
764 * variable number of rows depending on the number of queues supported.
765 **/
766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
767 int index, int offset)
768{
769 u32 ivar = array_rd32(E1000_IVAR0, index);
770
771 /* clear any bits that are currently set */
772 ivar &= ~((u32)0xFF << offset);
773
774 /* write vector and valid bit */
775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
776
777 array_wr32(E1000_IVAR0, index, ivar);
778}
779
9d5c8243 780#define IGB_N0_QUEUE -1
047e0030 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 782{
047e0030 783 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 784 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 785 int rx_queue = IGB_N0_QUEUE;
786 int tx_queue = IGB_N0_QUEUE;
4be000c8 787 u32 msixbm = 0;
047e0030 788
0ba82994
AD		 789 if (q_vector->rx.ring)
790 rx_queue = q_vector->rx.ring->reg_idx;
791 if (q_vector->tx.ring)
792 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 793
794 switch (hw->mac.type) {
795 case e1000_82575:
9d5c8243 796 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one
798 * or more queues to a vector, we write the appropriate bits
799 * into the MSIXBM register for that vector.
800 */
047e0030 801 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 803 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
feeb2721
AD		 805 if (!adapter->msix_entries && msix_vector == 0)
806 msixbm |= E1000_EIMS_OTHER;
9d5c8243 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 808 q_vector->eims_value = msixbm;
2d064c06
AD		 809 break;
810 case e1000_82576:
b980ac18 811 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 812 * with 8 rows. The ordering is column-major so we use the
813 * lower 3 bits as the row index, and the 4th bit as the
814 * column offset.
815 */
816 if (rx_queue > IGB_N0_QUEUE)
817 igb_write_ivar(hw, msix_vector,
818 rx_queue & 0x7,
819 (rx_queue & 0x8) << 1);
820 if (tx_queue > IGB_N0_QUEUE)
821 igb_write_ivar(hw, msix_vector,
822 tx_queue & 0x7,
823 ((tx_queue & 0x8) << 1) + 8);
047e0030 824 q_vector->eims_value = 1 << msix_vector;
2d064c06 825 break;
55cac248 826 case e1000_82580:
d2ba2ed8 827 case e1000_i350:
ceb5f13b 828 case e1000_i354:
f96a8a0b
CW		 829 case e1000_i210:
830 case e1000_i211:
b980ac18 831 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 832 * however instead of ordering column-major we have things
833 * ordered row-major. So we traverse the table by using
834 * bit 0 as the column offset, and the remaining bits as the
835 * row index.
836 */
837 if (rx_queue > IGB_N0_QUEUE)
838 igb_write_ivar(hw, msix_vector,
839 rx_queue >> 1,
840 (rx_queue & 0x1) << 4);
841 if (tx_queue > IGB_N0_QUEUE)
842 igb_write_ivar(hw, msix_vector,
843 tx_queue >> 1,
844 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 845 q_vector->eims_value = 1 << msix_vector;
846 break;
2d064c06
AD		 847 default:
848 BUG();
849 break;
850 }
26b39276
AD		 851
852 /* add q_vector eims value to global eims_enable_mask */
853 adapter->eims_enable_mask |= q_vector->eims_value;
854
855 /* configure q_vector to set itr on first interrupt */
856 q_vector->set_itr = 1;
9d5c8243
AK		 857}
858
859/**
b980ac18
JK		 860 * igb_configure_msix - Configure MSI-X hardware
861 * @adapter: board private structure to initialize
9d5c8243 862 *
b980ac18
JK		 863 * igb_configure_msix sets up the hardware to properly
864 * generate MSI-X interrupts.
9d5c8243
AK		 865 **/
866static void igb_configure_msix(struct igb_adapter *adapter)
867{
868 u32 tmp;
869 int i, vector = 0;
870 struct e1000_hw *hw = &adapter->hw;
871
872 adapter->eims_enable_mask = 0;
9d5c8243
AK		 873
874 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 875 switch (hw->mac.type) {
876 case e1000_82575:
9d5c8243
AK		 877 tmp = rd32(E1000_CTRL_EXT);
878 /* enable MSI-X PBA support*/
879 tmp |= E1000_CTRL_EXT_PBA_CLR;
880
881 /* Auto-Mask interrupts upon ICR read. */
882 tmp |= E1000_CTRL_EXT_EIAME;
883 tmp |= E1000_CTRL_EXT_IRCA;
884
885 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 886
887 /* enable msix_other interrupt */
b980ac18 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 889 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 890
2d064c06
AD		 891 break;
892
893 case e1000_82576:
55cac248 894 case e1000_82580:
d2ba2ed8 895 case e1000_i350:
ceb5f13b 896 case e1000_i354:
f96a8a0b
CW		 897 case e1000_i210:
898 case e1000_i211:
047e0030 899 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 900 * won't stick. And it will take days to debug.
901 */
047e0030 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 903 E1000_GPIE_PBA | E1000_GPIE_EIAME |
904 E1000_GPIE_NSICR);
047e0030
AD		 905
906 /* enable msix_other interrupt */
907 adapter->eims_other = 1 << vector;
2d064c06 908 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 909
047e0030 910 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 911 break;
912 default:
913 /* do nothing, since nothing else supports MSI-X */
914 break;
915 } /* switch (hw->mac.type) */
047e0030
AD		 916
917 adapter->eims_enable_mask |= adapter->eims_other;
918
26b39276
AD		 919 for (i = 0; i < adapter->num_q_vectors; i++)
920 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 921
9d5c8243
AK		 922 wrfl();
923}
924
925/**
b980ac18
JK		 926 * igb_request_msix - Initialize MSI-X interrupts
927 * @adapter: board private structure to initialize
9d5c8243 928 *
b980ac18
JK		 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
930 * kernel.
9d5c8243
AK		 931 **/
932static int igb_request_msix(struct igb_adapter *adapter)
933{
934 struct net_device *netdev = adapter->netdev;
047e0030 935 struct e1000_hw *hw = &adapter->hw;
52285b76 936 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 937
047e0030 938 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 939 igb_msix_other, 0, netdev->name, adapter);
047e0030 940 if (err)
52285b76 941 goto err_out;
047e0030
AD		 942
943 for (i = 0; i < adapter->num_q_vectors; i++) {
944 struct igb_q_vector *q_vector = adapter->q_vector[i];
945
52285b76
SA		 946 vector++;
947
047e0030
AD		 948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
949
0ba82994 950 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 952 q_vector->rx.ring->queue_index);
953 else if (q_vector->tx.ring)
047e0030 954 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 955 q_vector->tx.ring->queue_index);
956 else if (q_vector->rx.ring)
047e0030 957 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 958 q_vector->rx.ring->queue_index);
9d5c8243 959 else
047e0030
AD		 960 sprintf(q_vector->name, "%s-unused", netdev->name);
961
9d5c8243 962 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 963 igb_msix_ring, 0, q_vector->name,
964 q_vector);
9d5c8243 965 if (err)
52285b76 966 goto err_free;
9d5c8243
AK		 967 }
968
9d5c8243
AK		 969 igb_configure_msix(adapter);
970 return 0;
52285b76
SA		 971
972err_free:
973 /* free already assigned IRQs */
974 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
975
976 vector--;
977 for (i = 0; i < vector; i++) {
978 free_irq(adapter->msix_entries[free_vector++].vector,
979 adapter->q_vector[i]);
980 }
981err_out:
9d5c8243
AK		 982 return err;
983}
984
985static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
986{
987 if (adapter->msix_entries) {
988 pci_disable_msix(adapter->pdev);
989 kfree(adapter->msix_entries);
990 adapter->msix_entries = NULL;
047e0030 991 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 992 pci_disable_msi(adapter->pdev);
047e0030 993 }
9d5c8243
AK		 994}
995
5536d210 996/**
b980ac18
JK		 997 * igb_free_q_vector - Free memory allocated for specific interrupt vector
998 * @adapter: board private structure to initialize
999 * @v_idx: Index of vector to be freed
5536d210 1000 *
b980ac18
JK		 1001 * This function frees the memory allocated to the q_vector. In addition if
1002 * NAPI is enabled it will delete any references to the NAPI struct prior
1003 * to freeing the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
1009 if (q_vector->tx.ring)
1010 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1011
1012 if (q_vector->rx.ring)
1013 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1014
1015 adapter->q_vector[v_idx] = NULL;
1016 netif_napi_del(&q_vector->napi);
1017
7f90128e 1018 /* igb_get_stats64() might access the rings on this vector,
5536d210
AD		 1019 * we must wait a grace period before freeing it.
1020 */
1021 kfree_rcu(q_vector, rcu);
1022}
1023
047e0030 1024/**
b980ac18
JK		 1025 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1026 * @adapter: board private structure to initialize
047e0030 1027 *
b980ac18
JK		 1028 * This function frees the memory allocated to the q_vectors. In addition if
1029 * NAPI is enabled it will delete any references to the NAPI struct prior
1030 * to freeing the q_vector.
047e0030
AD		 1031 **/
1032static void igb_free_q_vectors(struct igb_adapter *adapter)
1033{
5536d210
AD		 1034 int v_idx = adapter->num_q_vectors;
1035
1036 adapter->num_tx_queues = 0;
1037 adapter->num_rx_queues = 0;
047e0030 1038 adapter->num_q_vectors = 0;
5536d210
AD		 1039
1040 while (v_idx--)
1041 igb_free_q_vector(adapter, v_idx);
047e0030
AD		 1042}
1043
1044/**
b980ac18
JK		 1045 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1046 * @adapter: board private structure to initialize
047e0030 1047 *
b980ac18
JK		 1048 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1049 * MSI-X interrupts allocated.
047e0030
AD		 1050 */
1051static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1052{
047e0030
AD		 1053 igb_free_q_vectors(adapter);
1054 igb_reset_interrupt_capability(adapter);
1055}
9d5c8243
AK		 1056
1057/**
b980ac18
JK		 1058 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1059 * @adapter: board private structure to initialize
1060 * @msix: boolean value of MSIX capability
9d5c8243 1061 *
b980ac18
JK		 1062 * Attempt to configure interrupts using the best available
1063 * capabilities of the hardware and kernel.
9d5c8243 1064 **/
53c7d064 1065static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1066{
1067 int err;
1068 int numvecs, i;
1069
53c7d064
SA		 1070 if (!msix)
1071 goto msi_only;
1072
83b7180d 1073 /* Number of supported queues. */
a99955fc 1074 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1075 if (adapter->vfs_allocated_count)
1076 adapter->num_tx_queues = 1;
1077 else
1078 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1079
b980ac18 1080 /* start with one vector for every Rx queue */
047e0030
AD		 1081 numvecs = adapter->num_rx_queues;
1082
b980ac18 1083 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1084 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1085 numvecs += adapter->num_tx_queues;
047e0030
AD		 1086
1087 /* store the number of vectors reserved for queues */
1088 adapter->num_q_vectors = numvecs;
1089
1090 /* add 1 vector for link status interrupts */
1091 numvecs++;
9d5c8243
AK		 1092 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1093 GFP_KERNEL);
f96a8a0b 1094
9d5c8243
AK		 1095 if (!adapter->msix_entries)
1096 goto msi_only;
1097
1098 for (i = 0; i < numvecs; i++)
1099 adapter->msix_entries[i].entry = i;
1100
1101 err = pci_enable_msix(adapter->pdev,
1102 adapter->msix_entries,
1103 numvecs);
1104 if (err == 0)
0c2cc02e 1105 return;
9d5c8243
AK		 1106
1107 igb_reset_interrupt_capability(adapter);
1108
1109 /* If we can't do MSI-X, try MSI */
1110msi_only:
2a3abf6d
AD		 1111#ifdef CONFIG_PCI_IOV
1112 /* disable SR-IOV for non MSI-X configurations */
1113 if (adapter->vf_data) {
1114 struct e1000_hw *hw = &adapter->hw;
1115 /* disable iov and allow time for transactions to clear */
1116 pci_disable_sriov(adapter->pdev);
1117 msleep(500);
1118
1119 kfree(adapter->vf_data);
1120 adapter->vf_data = NULL;
1121 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1122 wrfl();
2a3abf6d
AD		 1123 msleep(100);
1124 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1125 }
1126#endif
4fc82adf 1127 adapter->vfs_allocated_count = 0;
a99955fc 1128 adapter->rss_queues = 1;
4fc82adf 1129 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1130 adapter->num_rx_queues = 1;
661086df 1131 adapter->num_tx_queues = 1;
047e0030 1132 adapter->num_q_vectors = 1;
9d5c8243 1133 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1134 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1135}
1136
5536d210
AD		 1137static void igb_add_ring(struct igb_ring *ring,
1138 struct igb_ring_container *head)
1139{
1140 head->ring = ring;
1141 head->count++;
1142}
1143
047e0030 1144/**
b980ac18
JK		 1145 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1146 * @adapter: board private structure to initialize
1147 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1148 * @v_idx: index of vector in adapter struct
1149 * @txr_count: total number of Tx rings to allocate
1150 * @txr_idx: index of first Tx ring to allocate
1151 * @rxr_count: total number of Rx rings to allocate
1152 * @rxr_idx: index of first Rx ring to allocate
047e0030 1153 *
b980ac18 1154 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1155 **/
5536d210
AD		 1156static int igb_alloc_q_vector(struct igb_adapter *adapter,
1157 int v_count, int v_idx,
1158 int txr_count, int txr_idx,
1159 int rxr_count, int rxr_idx)
047e0030
AD		 1160{
1161 struct igb_q_vector *q_vector;
5536d210
AD		 1162 struct igb_ring *ring;
1163 int ring_count, size;
047e0030 1164
5536d210
AD		 1165 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1166 if (txr_count > 1 || rxr_count > 1)
1167 return -ENOMEM;
1168
1169 ring_count = txr_count + rxr_count;
1170 size = sizeof(struct igb_q_vector) +
1171 (sizeof(struct igb_ring) * ring_count);
1172
1173 /* allocate q_vector and rings */
1174 q_vector = kzalloc(size, GFP_KERNEL);
1175 if (!q_vector)
1176 return -ENOMEM;
1177
1178 /* initialize NAPI */
1179 netif_napi_add(adapter->netdev, &q_vector->napi,
1180 igb_poll, 64);
1181
1182 /* tie q_vector and adapter together */
1183 adapter->q_vector[v_idx] = q_vector;
1184 q_vector->adapter = adapter;
1185
1186 /* initialize work limits */
1187 q_vector->tx.work_limit = adapter->tx_work_limit;
1188
1189 /* initialize ITR configuration */
1190 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1191 q_vector->itr_val = IGB_START_ITR;
1192
1193 /* initialize pointer to rings */
1194 ring = q_vector->ring;
1195
4e227667
AD		 1196 /* intialize ITR */
1197 if (rxr_count) {
1198 /* rx or rx/tx vector */
1199 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1200 q_vector->itr_val = adapter->rx_itr_setting;
1201 } else {
1202 /* tx only vector */
1203 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1204 q_vector->itr_val = adapter->tx_itr_setting;
1205 }
1206
5536d210
AD		 1207 if (txr_count) {
1208 /* assign generic ring traits */
1209 ring->dev = &adapter->pdev->dev;
1210 ring->netdev = adapter->netdev;
1211
1212 /* configure backlink on ring */
1213 ring->q_vector = q_vector;
1214
1215 /* update q_vector Tx values */
1216 igb_add_ring(ring, &q_vector->tx);
1217
1218 /* For 82575, context index must be unique per ring. */
1219 if (adapter->hw.mac.type == e1000_82575)
1220 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1221
1222 /* apply Tx specific ring traits */
1223 ring->count = adapter->tx_ring_count;
1224 ring->queue_index = txr_idx;
1225
1226 /* assign ring to adapter */
1227 adapter->tx_ring[txr_idx] = ring;
1228
1229 /* push pointer to next ring */
1230 ring++;
047e0030 1231 }
81c2fc22 1232
5536d210
AD		 1233 if (rxr_count) {
1234 /* assign generic ring traits */
1235 ring->dev = &adapter->pdev->dev;
1236 ring->netdev = adapter->netdev;
047e0030 1237
5536d210
AD		 1238 /* configure backlink on ring */
1239 ring->q_vector = q_vector;
047e0030 1240
5536d210
AD		 1241 /* update q_vector Rx values */
1242 igb_add_ring(ring, &q_vector->rx);
047e0030 1243
5536d210
AD		 1244 /* set flag indicating ring supports SCTP checksum offload */
1245 if (adapter->hw.mac.type >= e1000_82576)
1246 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1247
ceb5f13b
CW		 1248 /*
1249 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1250 * have the tag byte-swapped.
b980ac18 1251 */
5536d210
AD		 1252 if (adapter->hw.mac.type >= e1000_i350)
1253 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1254
5536d210
AD		 1255 /* apply Rx specific ring traits */
1256 ring->count = adapter->rx_ring_count;
1257 ring->queue_index = rxr_idx;
1258
1259 /* assign ring to adapter */
1260 adapter->rx_ring[rxr_idx] = ring;
1261 }
1262
1263 return 0;
047e0030
AD		 1264}
1265
5536d210 1266
047e0030 1267/**
b980ac18
JK		 1268 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1269 * @adapter: board private structure to initialize
047e0030 1270 *
b980ac18
JK		 1271 * We allocate one q_vector per queue interrupt. If allocation fails we
1272 * return -ENOMEM.
047e0030 1273 **/
5536d210 1274static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1275{
5536d210
AD		 1276 int q_vectors = adapter->num_q_vectors;
1277 int rxr_remaining = adapter->num_rx_queues;
1278 int txr_remaining = adapter->num_tx_queues;
1279 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1280 int err;
047e0030 1281
5536d210
AD		 1282 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1283 for (; rxr_remaining; v_idx++) {
1284 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1285 0, 0, 1, rxr_idx);
047e0030 1286
5536d210
AD		 1287 if (err)
1288 goto err_out;
1289
1290 /* update counts and index */
1291 rxr_remaining--;
1292 rxr_idx++;
047e0030 1293 }
047e0030 1294 }
5536d210
AD		 1295
1296 for (; v_idx < q_vectors; v_idx++) {
1297 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1298 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1299 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1300 tqpv, txr_idx, rqpv, rxr_idx);
1301
1302 if (err)
1303 goto err_out;
1304
1305 /* update counts and index */
1306 rxr_remaining -= rqpv;
1307 txr_remaining -= tqpv;
1308 rxr_idx++;
1309 txr_idx++;
1310 }
1311
047e0030 1312 return 0;
5536d210
AD		 1313
1314err_out:
1315 adapter->num_tx_queues = 0;
1316 adapter->num_rx_queues = 0;
1317 adapter->num_q_vectors = 0;
1318
1319 while (v_idx--)
1320 igb_free_q_vector(adapter, v_idx);
1321
1322 return -ENOMEM;
047e0030
AD		 1323}
1324
1325/**
b980ac18
JK		 1326 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1327 * @adapter: board private structure to initialize
1328 * @msix: boolean value of MSIX capability
047e0030 1329 *
b980ac18 1330 * This function initializes the interrupts and allocates all of the queues.
047e0030 1331 **/
53c7d064 1332static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1333{
1334 struct pci_dev *pdev = adapter->pdev;
1335 int err;
1336
53c7d064 1337 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1338
1339 err = igb_alloc_q_vectors(adapter);
1340 if (err) {
1341 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1342 goto err_alloc_q_vectors;
1343 }
1344
5536d210 1345 igb_cache_ring_register(adapter);
047e0030
AD		 1346
1347 return 0;
5536d210 1348
047e0030
AD		 1349err_alloc_q_vectors:
1350 igb_reset_interrupt_capability(adapter);
1351 return err;
1352}
1353
9d5c8243 1354/**
b980ac18
JK		 1355 * igb_request_irq - initialize interrupts
1356 * @adapter: board private structure to initialize
9d5c8243 1357 *
b980ac18
JK		 1358 * Attempts to configure interrupts using the best available
1359 * capabilities of the hardware and kernel.
9d5c8243
AK		 1360 **/
1361static int igb_request_irq(struct igb_adapter *adapter)
1362{
1363 struct net_device *netdev = adapter->netdev;
047e0030 1364 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1365 int err = 0;
1366
1367 if (adapter->msix_entries) {
1368 err = igb_request_msix(adapter);
844290e5 1369 if (!err)
9d5c8243 1370 goto request_done;
9d5c8243 1371 /* fall back to MSI */
5536d210
AD		 1372 igb_free_all_tx_resources(adapter);
1373 igb_free_all_rx_resources(adapter);
53c7d064 1374
047e0030 1375 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1376 err = igb_init_interrupt_scheme(adapter, false);
1377 if (err)
047e0030 1378 goto request_done;
53c7d064 1379
047e0030
AD		 1380 igb_setup_all_tx_resources(adapter);
1381 igb_setup_all_rx_resources(adapter);
53c7d064 1382 igb_configure(adapter);
9d5c8243 1383 }
844290e5 1384
c74d588e
AD		 1385 igb_assign_vector(adapter->q_vector[0], 0);
1386
7dfc16fa 1387 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1388 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1389 netdev->name, adapter);
9d5c8243
AK		 1390 if (!err)
1391 goto request_done;
047e0030 1392
9d5c8243
AK		 1393 /* fall back to legacy interrupts */
1394 igb_reset_interrupt_capability(adapter);
7dfc16fa 1395 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1396 }
1397
c74d588e 1398 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1399 netdev->name, adapter);
9d5c8243 1400
6cb5e577 1401 if (err)
c74d588e 1402 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1403 err);
9d5c8243
AK		 1404
1405request_done:
1406 return err;
1407}
1408
1409static void igb_free_irq(struct igb_adapter *adapter)
1410{
9d5c8243
AK		 1411 if (adapter->msix_entries) {
1412 int vector = 0, i;
1413
047e0030 1414 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1415
0d1ae7f4 1416 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1417 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1418 adapter->q_vector[i]);
047e0030
AD		 1419 } else {
1420 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1421 }
9d5c8243
AK		 1422}
1423
1424/**
b980ac18
JK		 1425 * igb_irq_disable - Mask off interrupt generation on the NIC
1426 * @adapter: board private structure
9d5c8243
AK		 1427 **/
1428static void igb_irq_disable(struct igb_adapter *adapter)
1429{
1430 struct e1000_hw *hw = &adapter->hw;
1431
b980ac18 1432 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1433 * mapped into these registers and so clearing the bits can cause
1434 * issues on the VF drivers so we only need to clear what we set
1435 */
9d5c8243 1436 if (adapter->msix_entries) {
2dfd1212
AD		 1437 u32 regval = rd32(E1000_EIAM);
1438 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1439 wr32(E1000_EIMC, adapter->eims_enable_mask);
1440 regval = rd32(E1000_EIAC);
1441 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1442 }
844290e5
PW		 1443
1444 wr32(E1000_IAM, 0);
9d5c8243
AK		 1445 wr32(E1000_IMC, ~0);
1446 wrfl();
81a61859
ET		 1447 if (adapter->msix_entries) {
1448 int i;
1449 for (i = 0; i < adapter->num_q_vectors; i++)
1450 synchronize_irq(adapter->msix_entries[i].vector);
1451 } else {
1452 synchronize_irq(adapter->pdev->irq);
1453 }
9d5c8243
AK		 1454}
1455
1456/**
b980ac18
JK		 1457 * igb_irq_enable - Enable default interrupt generation settings
1458 * @adapter: board private structure
9d5c8243
AK		 1459 **/
1460static void igb_irq_enable(struct igb_adapter *adapter)
1461{
1462 struct e1000_hw *hw = &adapter->hw;
1463
1464 if (adapter->msix_entries) {
06218a8d 1465 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1466 u32 regval = rd32(E1000_EIAC);
1467 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1468 regval = rd32(E1000_EIAM);
1469 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1470 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1471 if (adapter->vfs_allocated_count) {
4ae196df 1472 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1473 ims |= E1000_IMS_VMMB;
1474 }
1475 wr32(E1000_IMS, ims);
844290e5 1476 } else {
55cac248
AD		 1477 wr32(E1000_IMS, IMS_ENABLE_MASK |
1478 E1000_IMS_DRSTA);
1479 wr32(E1000_IAM, IMS_ENABLE_MASK |
1480 E1000_IMS_DRSTA);
844290e5 1481 }
9d5c8243
AK		 1482}
1483
1484static void igb_update_mng_vlan(struct igb_adapter *adapter)
1485{
51466239 1486 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1487 u16 vid = adapter->hw.mng_cookie.vlan_id;
1488 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1489
1490 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1491 /* add VID to filter table */
1492 igb_vfta_set(hw, vid, true);
1493 adapter->mng_vlan_id = vid;
1494 } else {
1495 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1496 }
1497
1498 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1499 (vid != old_vid) &&
b2cb09b1 1500 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1501 /* remove VID from filter table */
1502 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1503 }
1504}
1505
1506/**
b980ac18
JK		 1507 * igb_release_hw_control - release control of the h/w to f/w
1508 * @adapter: address of board private structure
9d5c8243 1509 *
b980ac18
JK		 1510 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1511 * For ASF and Pass Through versions of f/w this means that the
1512 * driver is no longer loaded.
9d5c8243
AK		 1513 **/
1514static void igb_release_hw_control(struct igb_adapter *adapter)
1515{
1516 struct e1000_hw *hw = &adapter->hw;
1517 u32 ctrl_ext;
1518
1519 /* Let firmware take over control of h/w */
1520 ctrl_ext = rd32(E1000_CTRL_EXT);
1521 wr32(E1000_CTRL_EXT,
1522 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1523}
1524
9d5c8243 1525/**
b980ac18
JK		 1526 * igb_get_hw_control - get control of the h/w from f/w
1527 * @adapter: address of board private structure
9d5c8243 1528 *
b980ac18
JK		 1529 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1530 * For ASF and Pass Through versions of f/w this means that
1531 * the driver is loaded.
9d5c8243
AK		 1532 **/
1533static void igb_get_hw_control(struct igb_adapter *adapter)
1534{
1535 struct e1000_hw *hw = &adapter->hw;
1536 u32 ctrl_ext;
1537
1538 /* Let firmware know the driver has taken over */
1539 ctrl_ext = rd32(E1000_CTRL_EXT);
1540 wr32(E1000_CTRL_EXT,
1541 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1542}
1543
9d5c8243 1544/**
b980ac18
JK		 1545 * igb_configure - configure the hardware for RX and TX
1546 * @adapter: private board structure
9d5c8243
AK		 1547 **/
1548static void igb_configure(struct igb_adapter *adapter)
1549{
1550 struct net_device *netdev = adapter->netdev;
1551 int i;
1552
1553 igb_get_hw_control(adapter);
ff41f8dc 1554 igb_set_rx_mode(netdev);
9d5c8243
AK		 1555
1556 igb_restore_vlan(adapter);
9d5c8243 1557
85b430b4 1558 igb_setup_tctl(adapter);
06cf2666 1559 igb_setup_mrqc(adapter);
9d5c8243 1560 igb_setup_rctl(adapter);
85b430b4
AD		 1561
1562 igb_configure_tx(adapter);
9d5c8243 1563 igb_configure_rx(adapter);
662d7205
AD		 1564
1565 igb_rx_fifo_flush_82575(&adapter->hw);
1566
c493ea45 1567 /* call igb_desc_unused which always leaves
9d5c8243 1568 * at least 1 descriptor unused to make sure
b980ac18
JK		 1569 * next_to_use != next_to_clean
1570 */
9d5c8243 1571 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1572 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1573 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1574 }
9d5c8243
AK		 1575}
1576
88a268c1 1577/**
b980ac18
JK		 1578 * igb_power_up_link - Power up the phy/serdes link
1579 * @adapter: address of board private structure
88a268c1
NN		 1580 **/
1581void igb_power_up_link(struct igb_adapter *adapter)
1582{
76886596
AA		 1583 igb_reset_phy(&adapter->hw);
1584
88a268c1
NN		 1585 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1586 igb_power_up_phy_copper(&adapter->hw);
1587 else
1588 igb_power_up_serdes_link_82575(&adapter->hw);
1589}
1590
1591/**
b980ac18
JK		 1592 * igb_power_down_link - Power down the phy/serdes link
1593 * @adapter: address of board private structure
88a268c1
NN		 1594 */
1595static void igb_power_down_link(struct igb_adapter *adapter)
1596{
1597 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1598 igb_power_down_phy_copper_82575(&adapter->hw);
1599 else
1600 igb_shutdown_serdes_link_82575(&adapter->hw);
1601}
9d5c8243
AK		 1602
1603/**
b980ac18
JK		 1604 * igb_up - Open the interface and prepare it to handle traffic
1605 * @adapter: board private structure
9d5c8243 1606 **/
9d5c8243
AK		 1607int igb_up(struct igb_adapter *adapter)
1608{
1609 struct e1000_hw *hw = &adapter->hw;
1610 int i;
1611
1612 /* hardware has been reset, we need to reload some things */
1613 igb_configure(adapter);
1614
1615 clear_bit(__IGB_DOWN, &adapter->state);
1616
0d1ae7f4
AD		 1617 for (i = 0; i < adapter->num_q_vectors; i++)
1618 napi_enable(&(adapter->q_vector[i]->napi));
1619
844290e5 1620 if (adapter->msix_entries)
9d5c8243 1621 igb_configure_msix(adapter);
feeb2721
AD		 1622 else
1623 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1624
1625 /* Clear any pending interrupts. */
1626 rd32(E1000_ICR);
1627 igb_irq_enable(adapter);
1628
d4960307
AD		 1629 /* notify VFs that reset has been completed */
1630 if (adapter->vfs_allocated_count) {
1631 u32 reg_data = rd32(E1000_CTRL_EXT);
1632 reg_data |= E1000_CTRL_EXT_PFRSTD;
1633 wr32(E1000_CTRL_EXT, reg_data);
1634 }
1635
4cb9be7a
JB		 1636 netif_tx_start_all_queues(adapter->netdev);
1637
25568a53
AD		 1638 /* start the watchdog. */
1639 hw->mac.get_link_status = 1;
1640 schedule_work(&adapter->watchdog_task);
1641
9d5c8243
AK		 1642 return 0;
1643}
1644
1645void igb_down(struct igb_adapter *adapter)
1646{
9d5c8243 1647 struct net_device *netdev = adapter->netdev;
330a6d6a 1648 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1649 u32 tctl, rctl;
1650 int i;
1651
1652 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1653 * reschedule our watchdog timer
1654 */
9d5c8243
AK		 1655 set_bit(__IGB_DOWN, &adapter->state);
1656
1657 /* disable receives in the hardware */
1658 rctl = rd32(E1000_RCTL);
1659 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1660 /* flush and sleep below */
1661
fd2ea0a7 1662 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1663
1664 /* disable transmits in the hardware */
1665 tctl = rd32(E1000_TCTL);
1666 tctl &= ~E1000_TCTL_EN;
1667 wr32(E1000_TCTL, tctl);
1668 /* flush both disables and wait for them to finish */
1669 wrfl();
1670 msleep(10);
1671
41f149a2
CW		 1672 igb_irq_disable(adapter);
1673
aa9b8cc4
AA		 1674 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1675
41f149a2
CW		 1676 for (i = 0; i < adapter->num_q_vectors; i++) {
1677 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1678 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1679 }
9d5c8243 1680
9d5c8243
AK		 1681
1682 del_timer_sync(&adapter->watchdog_timer);
1683 del_timer_sync(&adapter->phy_info_timer);
1684
9d5c8243 1685 netif_carrier_off(netdev);
04fe6358
AD		 1686
1687 /* record the stats before reset*/
12dcd86b
ED		 1688 spin_lock(&adapter->stats64_lock);
1689 igb_update_stats(adapter, &adapter->stats64);
1690 spin_unlock(&adapter->stats64_lock);
04fe6358 1691
9d5c8243
AK		 1692 adapter->link_speed = 0;
1693 adapter->link_duplex = 0;
1694
3023682e
JK		 1695 if (!pci_channel_offline(adapter->pdev))
1696 igb_reset(adapter);
9d5c8243
AK		 1697 igb_clean_all_tx_rings(adapter);
1698 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1699#ifdef CONFIG_IGB_DCA
1700
1701 /* since we reset the hardware DCA settings were cleared */
1702 igb_setup_dca(adapter);
1703#endif
9d5c8243
AK		 1704}
1705
1706void igb_reinit_locked(struct igb_adapter *adapter)
1707{
1708 WARN_ON(in_interrupt());
1709 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1710 msleep(1);
1711 igb_down(adapter);
1712 igb_up(adapter);
1713 clear_bit(__IGB_RESETTING, &adapter->state);
1714}
1715
1716void igb_reset(struct igb_adapter *adapter)
1717{
090b1795 1718 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1719 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1720 struct e1000_mac_info *mac = &hw->mac;
1721 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1722 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1723
1724 /* Repartition Pba for greater than 9k mtu
1725 * To take effect CTRL.RST is required.
1726 */
fa4dfae0 1727 switch (mac->type) {
d2ba2ed8 1728 case e1000_i350:
ceb5f13b 1729 case e1000_i354:
55cac248
AD		 1730 case e1000_82580:
1731 pba = rd32(E1000_RXPBS);
1732 pba = igb_rxpbs_adjust_82580(pba);
1733 break;
fa4dfae0 1734 case e1000_82576:
d249be54
AD		 1735 pba = rd32(E1000_RXPBS);
1736 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1737 break;
1738 case e1000_82575:
f96a8a0b
CW		 1739 case e1000_i210:
1740 case e1000_i211:
fa4dfae0
AD		 1741 default:
1742 pba = E1000_PBA_34K;
1743 break;
2d064c06 1744 }
9d5c8243 1745
2d064c06
AD		 1746 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1747 (mac->type < e1000_82576)) {
9d5c8243
AK		 1748 /* adjust PBA for jumbo frames */
1749 wr32(E1000_PBA, pba);
1750
1751 /* To maintain wire speed transmits, the Tx FIFO should be
1752 * large enough to accommodate two full transmit packets,
1753 * rounded up to the next 1KB and expressed in KB. Likewise,
1754 * the Rx FIFO should be large enough to accommodate at least
1755 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1756 * expressed in KB.
1757 */
9d5c8243
AK		 1758 pba = rd32(E1000_PBA);
1759 /* upper 16 bits has Tx packet buffer allocation size in KB */
1760 tx_space = pba >> 16;
1761 /* lower 16 bits has Rx packet buffer allocation size in KB */
1762 pba &= 0xffff;
b980ac18
JK		 1763 /* the Tx fifo also stores 16 bytes of information about the Tx
1764 * but don't include ethernet FCS because hardware appends it
1765 */
9d5c8243 1766 min_tx_space = (adapter->max_frame_size +
85e8d004 1767 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1768 ETH_FCS_LEN) * 2;
1769 min_tx_space = ALIGN(min_tx_space, 1024);
1770 min_tx_space >>= 10;
1771 /* software strips receive CRC, so leave room for it */
1772 min_rx_space = adapter->max_frame_size;
1773 min_rx_space = ALIGN(min_rx_space, 1024);
1774 min_rx_space >>= 10;
1775
1776 /* If current Tx allocation is less than the min Tx FIFO size,
1777 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1778 * allocation, take space away from current Rx allocation
1779 */
9d5c8243
AK		 1780 if (tx_space < min_tx_space &&
1781 ((min_tx_space - tx_space) < pba)) {
1782 pba = pba - (min_tx_space - tx_space);
1783
b980ac18
JK		 1784 /* if short on Rx space, Rx wins and must trump Tx
1785 * adjustment
1786 */
9d5c8243
AK		 1787 if (pba < min_rx_space)
1788 pba = min_rx_space;
1789 }
2d064c06 1790 wr32(E1000_PBA, pba);
9d5c8243 1791 }
9d5c8243
AK		 1792
1793 /* flow control settings */
1794 /* The high water mark must be low enough to fit one full frame
1795 * (or the size used for early receive) above it in the Rx FIFO.
1796 * Set it to the lower of:
1797 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1798 * - the full Rx FIFO size minus one full frame
1799 */
9d5c8243 1800 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1801 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1802
d48507fe 1803 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1804 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1805 fc->pause_time = 0xFFFF;
1806 fc->send_xon = 1;
0cce119a 1807 fc->current_mode = fc->requested_mode;
9d5c8243 1808
4ae196df
AD		 1809 /* disable receive for all VFs and wait one second */
1810 if (adapter->vfs_allocated_count) {
1811 int i;
1812 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1813 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1814
1815 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1816 igb_ping_all_vfs(adapter);
4ae196df
AD		 1817
1818 /* disable transmits and receives */
1819 wr32(E1000_VFRE, 0);
1820 wr32(E1000_VFTE, 0);
1821 }
1822
9d5c8243 1823 /* Allow time for pending master requests to run */
330a6d6a 1824 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1825 wr32(E1000_WUC, 0);
1826
330a6d6a 1827 if (hw->mac.ops.init_hw(hw))
090b1795 1828 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1829
b980ac18 1830 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1831 * control is off when forcing speed.
1832 */
1833 if (!hw->mac.autoneg)
1834 igb_force_mac_fc(hw);
1835
b6e0c419 1836 igb_init_dmac(adapter, pba);
e428893b
CW		 1837#ifdef CONFIG_IGB_HWMON
1838 /* Re-initialize the thermal sensor on i350 devices. */
1839 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1840 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1841 /* If present, re-initialize the external thermal sensor
1842 * interface.
1843 */
1844 if (adapter->ets)
1845 mac->ops.init_thermal_sensor_thresh(hw);
1846 }
1847 }
1848#endif
88a268c1
NN		 1849 if (!netif_running(adapter->netdev))
1850 igb_power_down_link(adapter);
1851
9d5c8243
AK		 1852 igb_update_mng_vlan(adapter);
1853
1854 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1855 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1856
1f6e8178
MV		 1857 /* Re-enable PTP, where applicable. */
1858 igb_ptp_reset(adapter);
1f6e8178 1859
330a6d6a 1860 igb_get_phy_info(hw);
9d5c8243
AK		 1861}
1862
c8f44aff
MM		 1863static netdev_features_t igb_fix_features(struct net_device *netdev,
1864 netdev_features_t features)
b2cb09b1 1865{
b980ac18
JK		 1866 /* Since there is no support for separate Rx/Tx vlan accel
1867 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 1868 */
f646968f
PM		 1869 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1870 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 1871 else
f646968f 1872 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 1873
1874 return features;
1875}
1876
c8f44aff
MM		 1877static int igb_set_features(struct net_device *netdev,
1878 netdev_features_t features)
ac52caa3 1879{
c8f44aff 1880 netdev_features_t changed = netdev->features ^ features;
89eaefb6 1881 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 1882
f646968f 1883 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 1884 igb_vlan_mode(netdev, features);
1885
89eaefb6
BG		 1886 if (!(changed & NETIF_F_RXALL))
1887 return 0;
1888
1889 netdev->features = features;
1890
1891 if (netif_running(netdev))
1892 igb_reinit_locked(adapter);
1893 else
1894 igb_reset(adapter);
1895
ac52caa3
MM		 1896 return 0;
1897}
1898
2e5c6922 1899static const struct net_device_ops igb_netdev_ops = {
559e9c49 1900 .ndo_open = igb_open,
2e5c6922 1901 .ndo_stop = igb_close,
cd392f5c 1902 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 1903 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 1904 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 1905 .ndo_set_mac_address = igb_set_mac,
1906 .ndo_change_mtu = igb_change_mtu,
1907 .ndo_do_ioctl = igb_ioctl,
1908 .ndo_tx_timeout = igb_tx_timeout,
1909 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 1910 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
1911 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 1912 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
1913 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
1914 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 1915 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 1916 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 1917#ifdef CONFIG_NET_POLL_CONTROLLER
1918 .ndo_poll_controller = igb_netpoll,
1919#endif
b2cb09b1
JP		 1920 .ndo_fix_features = igb_fix_features,
1921 .ndo_set_features = igb_set_features,
2e5c6922
SH		 1922};
1923
d67974f0
CW		 1924/**
1925 * igb_set_fw_version - Configure version string for ethtool
1926 * @adapter: adapter struct
d67974f0
CW		 1927 **/
1928void igb_set_fw_version(struct igb_adapter *adapter)
1929{
1930 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 1931 struct e1000_fw_version fw;
1932
1933 igb_get_fw_version(hw, &fw);
1934
1935 switch (hw->mac.type) {
7dc98a62 1936 case e1000_i210:
0b1a6f2e 1937 case e1000_i211:
7dc98a62
CW		 1938 if (!(igb_get_flash_presence_i210(hw))) {
1939 snprintf(adapter->fw_version,
1940 sizeof(adapter->fw_version),
1941 "%2d.%2d-%d",
1942 fw.invm_major, fw.invm_minor,
1943 fw.invm_img_type);
1944 break;
1945 }
1946 /* fall through */
0b1a6f2e
CW		 1947 default:
1948 /* if option is rom valid, display its version too */
1949 if (fw.or_valid) {
1950 snprintf(adapter->fw_version,
1951 sizeof(adapter->fw_version),
1952 "%d.%d, 0x%08x, %d.%d.%d",
1953 fw.eep_major, fw.eep_minor, fw.etrack_id,
1954 fw.or_major, fw.or_build, fw.or_patch);
1955 /* no option rom */
7dc98a62 1956 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 1957 snprintf(adapter->fw_version,
7dc98a62
CW		 1958 sizeof(adapter->fw_version),
1959 "%d.%d, 0x%08x",
1960 fw.eep_major, fw.eep_minor, fw.etrack_id);
1961 } else {
1962 snprintf(adapter->fw_version,
1963 sizeof(adapter->fw_version),
1964 "%d.%d.%d",
1965 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 1966 }
1967 break;
d67974f0 1968 }
d67974f0
CW		 1969 return;
1970}
1971
b980ac18
JK		 1972/**
1973 * igb_init_i2c - Init I2C interface
441fc6fd 1974 * @adapter: pointer to adapter structure
b980ac18 1975 **/
441fc6fd
CW		 1976static s32 igb_init_i2c(struct igb_adapter *adapter)
1977{
1978 s32 status = E1000_SUCCESS;
1979
1980 /* I2C interface supported on i350 devices */
1981 if (adapter->hw.mac.type != e1000_i350)
1982 return E1000_SUCCESS;
1983
1984 /* Initialize the i2c bus which is controlled by the registers.
1985 * This bus will use the i2c_algo_bit structue that implements
1986 * the protocol through toggling of the 4 bits in the register.
1987 */
1988 adapter->i2c_adap.owner = THIS_MODULE;
1989 adapter->i2c_algo = igb_i2c_algo;
1990 adapter->i2c_algo.data = adapter;
1991 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1992 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1993 strlcpy(adapter->i2c_adap.name, "igb BB",
1994 sizeof(adapter->i2c_adap.name));
1995 status = i2c_bit_add_bus(&adapter->i2c_adap);
1996 return status;
1997}
1998
9d5c8243 1999/**
b980ac18
JK		 2000 * igb_probe - Device Initialization Routine
2001 * @pdev: PCI device information struct
2002 * @ent: entry in igb_pci_tbl
9d5c8243 2003 *
b980ac18 2004 * Returns 0 on success, negative on failure
9d5c8243 2005 *
b980ac18
JK		 2006 * igb_probe initializes an adapter identified by a pci_dev structure.
2007 * The OS initialization, configuring of the adapter private structure,
2008 * and a hardware reset occur.
9d5c8243 2009 **/
1dd06ae8 2010static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2011{
2012 struct net_device *netdev;
2013 struct igb_adapter *adapter;
2014 struct e1000_hw *hw;
4337e993 2015 u16 eeprom_data = 0;
9835fd73 2016 s32 ret_val;
4337e993 2017 static int global_quad_port_a; /* global quad port a indication */
9d5c8243
AK		 2018 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2019 unsigned long mmio_start, mmio_len;
2d6a5e95 2020 int err, pci_using_dac;
9835fd73 2021 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2022
bded64a7
AG		 2023 /* Catch broken hardware that put the wrong VF device ID in
2024 * the PCIe SR-IOV capability.
2025 */
2026 if (pdev->is_virtfn) {
2027 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2028 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2029 return -EINVAL;
2030 }
2031
aed5dec3 2032 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2033 if (err)
2034 return err;
2035
2036 pci_using_dac = 0;
59d71989 2037 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2038 if (!err) {
59d71989 2039 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243
AK		 2040 if (!err)
2041 pci_using_dac = 1;
2042 } else {
59d71989 2043 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2044 if (err) {
b980ac18
JK		 2045 err = dma_set_coherent_mask(&pdev->dev,
2046 DMA_BIT_MASK(32));
9d5c8243 2047 if (err) {
b980ac18
JK		 2048 dev_err(&pdev->dev,
2049 "No usable DMA configuration, aborting\n");
9d5c8243
AK		 2050 goto err_dma;
2051 }
2052 }
2053 }
2054
aed5dec3 2055 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2056 IORESOURCE_MEM),
2057 igb_driver_name);
9d5c8243
AK		 2058 if (err)
2059 goto err_pci_reg;
2060
19d5afd4 2061 pci_enable_pcie_error_reporting(pdev);
40a914fa 2062
9d5c8243 2063 pci_set_master(pdev);
c682fc23 2064 pci_save_state(pdev);
9d5c8243
AK		 2065
2066 err = -ENOMEM;
1bfaf07b 2067 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2068 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2069 if (!netdev)
2070 goto err_alloc_etherdev;
2071
2072 SET_NETDEV_DEV(netdev, &pdev->dev);
2073
2074 pci_set_drvdata(pdev, netdev);
2075 adapter = netdev_priv(netdev);
2076 adapter->netdev = netdev;
2077 adapter->pdev = pdev;
2078 hw = &adapter->hw;
2079 hw->back = adapter;
b3f4d599 2080 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243
AK		 2081
2082 mmio_start = pci_resource_start(pdev, 0);
2083 mmio_len = pci_resource_len(pdev, 0);
2084
2085 err = -EIO;
28b0759c
AD		 2086 hw->hw_addr = ioremap(mmio_start, mmio_len);
2087 if (!hw->hw_addr)
9d5c8243
AK		 2088 goto err_ioremap;
2089
2e5c6922 2090 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2091 igb_set_ethtool_ops(netdev);
9d5c8243 2092 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2093
2094 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2095
2096 netdev->mem_start = mmio_start;
2097 netdev->mem_end = mmio_start + mmio_len;
2098
9d5c8243
AK		 2099 /* PCI config space info */
2100 hw->vendor_id = pdev->vendor;
2101 hw->device_id = pdev->device;
2102 hw->revision_id = pdev->revision;
2103 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2104 hw->subsystem_device_id = pdev->subsystem_device;
2105
9d5c8243
AK		 2106 /* Copy the default MAC, PHY and NVM function pointers */
2107 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2108 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2109 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2110 /* Initialize skew-specific constants */
2111 err = ei->get_invariants(hw);
2112 if (err)
450c87c8 2113 goto err_sw_init;
9d5c8243 2114
450c87c8 2115 /* setup the private structure */
9d5c8243
AK		 2116 err = igb_sw_init(adapter);
2117 if (err)
2118 goto err_sw_init;
2119
2120 igb_get_bus_info_pcie(hw);
2121
2122 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2123
2124 /* Copper options */
2125 if (hw->phy.media_type == e1000_media_type_copper) {
2126 hw->phy.mdix = AUTO_ALL_MODES;
2127 hw->phy.disable_polarity_correction = false;
2128 hw->phy.ms_type = e1000_ms_hw_default;
2129 }
2130
2131 if (igb_check_reset_block(hw))
2132 dev_info(&pdev->dev,
2133 "PHY reset is blocked due to SOL/IDER session.\n");
2134
b980ac18 2135 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2136 * set by igb_sw_init so we should use an or instead of an
2137 * assignment.
2138 */
2139 netdev->features |= NETIF_F_SG |
2140 NETIF_F_IP_CSUM |
2141 NETIF_F_IPV6_CSUM |
2142 NETIF_F_TSO |
2143 NETIF_F_TSO6 |
2144 NETIF_F_RXHASH |
2145 NETIF_F_RXCSUM |
f646968f
PM		 2146 NETIF_F_HW_VLAN_CTAG_RX |
2147 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2148
2149 /* copy netdev features into list of user selectable features */
2150 netdev->hw_features |= netdev->features;
89eaefb6 2151 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2152
2153 /* set this bit last since it cannot be part of hw_features */
f646968f 2154 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2155
2156 netdev->vlan_features |= NETIF_F_TSO |
2157 NETIF_F_TSO6 |
2158 NETIF_F_IP_CSUM |
2159 NETIF_F_IPV6_CSUM |
2160 NETIF_F_SG;
48f29ffc 2161
6b8f0922
BG		 2162 netdev->priv_flags |= IFF_SUPP_NOFCS;
2163
7b872a55 2164 if (pci_using_dac) {
9d5c8243 2165 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2166 netdev->vlan_features |= NETIF_F_HIGHDMA;
2167 }
9d5c8243 2168
ac52caa3
MM		 2169 if (hw->mac.type >= e1000_82576) {
2170 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2171 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2172 }
b9473560 2173
01789349
JP		 2174 netdev->priv_flags |= IFF_UNICAST_FLT;
2175
330a6d6a 2176 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2177
2178 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2179 * known good starting state
2180 */
9d5c8243
AK		 2181 hw->mac.ops.reset_hw(hw);
2182
ef3a0092
CW		 2183 /* make sure the NVM is good , i211/i210 parts can have special NVM
2184 * that doesn't contain a checksum
f96a8a0b 2185 */
ef3a0092
CW		 2186 switch (hw->mac.type) {
2187 case e1000_i210:
2188 case e1000_i211:
2189 if (igb_get_flash_presence_i210(hw)) {
2190 if (hw->nvm.ops.validate(hw) < 0) {
2191 dev_err(&pdev->dev,
2192 "The NVM Checksum Is Not Valid\n");
2193 err = -EIO;
2194 goto err_eeprom;
2195 }
2196 }
2197 break;
2198 default:
f96a8a0b
CW		 2199 if (hw->nvm.ops.validate(hw) < 0) {
2200 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2201 err = -EIO;
2202 goto err_eeprom;
2203 }
ef3a0092 2204 break;
9d5c8243
AK		 2205 }
2206
2207 /* copy the MAC address out of the NVM */
2208 if (hw->mac.ops.read_mac_addr(hw))
2209 dev_err(&pdev->dev, "NVM Read Error\n");
2210
2211 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2212
aaeb6cdf 2213 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2214 dev_err(&pdev->dev, "Invalid MAC Address\n");
2215 err = -EIO;
2216 goto err_eeprom;
2217 }
2218
d67974f0
CW		 2219 /* get firmware version for ethtool -i */
2220 igb_set_fw_version(adapter);
2221
c061b18d 2222 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2223 (unsigned long) adapter);
c061b18d 2224 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2225 (unsigned long) adapter);
9d5c8243
AK		 2226
2227 INIT_WORK(&adapter->reset_task, igb_reset_task);
2228 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2229
450c87c8 2230 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2231 adapter->fc_autoneg = true;
2232 hw->mac.autoneg = true;
2233 hw->phy.autoneg_advertised = 0x2f;
2234
0cce119a
AD		 2235 hw->fc.requested_mode = e1000_fc_default;
2236 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2237
9d5c8243
AK		 2238 igb_validate_mdi_setting(hw);
2239
63d4a8f9 2240 /* By default, support wake on port A */
a2cf8b6c 2241 if (hw->bus.func == 0)
63d4a8f9
MV		 2242 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2243
2244 /* Check the NVM for wake support on non-port A ports */
2245 if (hw->mac.type >= e1000_82580)
55cac248 2246 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2247 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2248 &eeprom_data);
a2cf8b6c
AD		 2249 else if (hw->bus.func == 1)
2250 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2251
63d4a8f9
MV		 2252 if (eeprom_data & IGB_EEPROM_APME)
2253 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2254
2255 /* now that we have the eeprom settings, apply the special cases where
2256 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2257 * lan on a particular port
2258 */
9d5c8243
AK		 2259 switch (pdev->device) {
2260 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2261 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2262 break;
2263 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2264 case E1000_DEV_ID_82576_FIBER:
2265 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2266 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2267 * regardless of eeprom setting
2268 */
9d5c8243 2269 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2270 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2271 break;
c8ea5ea9 2272 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2273 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2274 /* if quad port adapter, disable WoL on all but port A */
2275 if (global_quad_port_a != 0)
63d4a8f9 2276 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2277 else
2278 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2279 /* Reset for multiple quad port adapters */
2280 if (++global_quad_port_a == 4)
2281 global_quad_port_a = 0;
2282 break;
63d4a8f9
MV		 2283 default:
2284 /* If the device can't wake, don't set software support */
2285 if (!device_can_wakeup(&adapter->pdev->dev))
2286 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2287 }
2288
2289 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2290 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2291 adapter->wol |= E1000_WUFC_MAG;
2292
2293 /* Some vendors want WoL disabled by default, but still supported */
2294 if ((hw->mac.type == e1000_i350) &&
2295 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2296 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2297 adapter->wol = 0;
2298 }
2299
2300 device_set_wakeup_enable(&adapter->pdev->dev,
2301 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2302
2303 /* reset the hardware with the new settings */
2304 igb_reset(adapter);
2305
441fc6fd
CW		 2306 /* Init the I2C interface */
2307 err = igb_init_i2c(adapter);
2308 if (err) {
2309 dev_err(&pdev->dev, "failed to init i2c interface\n");
2310 goto err_eeprom;
2311 }
2312
9d5c8243
AK		 2313 /* let the f/w know that the h/w is now under the control of the
2314 * driver. */
2315 igb_get_hw_control(adapter);
2316
9d5c8243
AK		 2317 strcpy(netdev->name, "eth%d");
2318 err = register_netdev(netdev);
2319 if (err)
2320 goto err_register;
2321
b168dfc5
JB		 2322 /* carrier off reporting is important to ethtool even BEFORE open */
2323 netif_carrier_off(netdev);
2324
421e02f0 2325#ifdef CONFIG_IGB_DCA
bbd98fe4 2326 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2327 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2328 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2329 igb_setup_dca(adapter);
2330 }
fe4506b6 2331
38c845c7 2332#endif
e428893b
CW		 2333#ifdef CONFIG_IGB_HWMON
2334 /* Initialize the thermal sensor on i350 devices. */
2335 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2336 u16 ets_word;
3c89f6d0 2337
b980ac18 2338 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2339 * external thermal sensor.
2340 */
2341 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2342 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2343 adapter->ets = true;
2344 else
2345 adapter->ets = false;
2346 if (igb_sysfs_init(adapter))
2347 dev_err(&pdev->dev,
2348 "failed to allocate sysfs resources\n");
2349 } else {
2350 adapter->ets = false;
2351 }
2352#endif
673b8b70 2353 /* do hw tstamp init after resetting */
7ebae817 2354 igb_ptp_init(adapter);
673b8b70 2355
9d5c8243 2356 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2357 /* print bus type/speed/width info, not applicable to i354 */
2358 if (hw->mac.type != e1000_i354) {
2359 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2360 netdev->name,
2361 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2362 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2363 "unknown"),
2364 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2365 "Width x4" :
2366 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2367 "Width x2" :
2368 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2369 "Width x1" : "unknown"), netdev->dev_addr);
2370 }
9d5c8243 2371
53ea6c7e
TF		 2372 if ((hw->mac.type >= e1000_i210 ||
2373 igb_get_flash_presence_i210(hw))) {
2374 ret_val = igb_read_part_string(hw, part_str,
2375 E1000_PBANUM_LENGTH);
2376 } else {
2377 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2378 }
2379
9835fd73
CW		 2380 if (ret_val)
2381 strcpy(part_str, "Unknown");
2382 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2383 dev_info(&pdev->dev,
2384 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2385 adapter->msix_entries ? "MSI-X" :
7dfc16fa 2386 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2387 adapter->num_rx_queues, adapter->num_tx_queues);
09b068d4
CW		 2388 switch (hw->mac.type) {
2389 case e1000_i350:
f96a8a0b
CW		 2390 case e1000_i210:
2391 case e1000_i211:
09b068d4
CW		 2392 igb_set_eee_i350(hw);
2393 break;
ceb5f13b
CW		 2394 case e1000_i354:
2395 if (hw->phy.media_type == e1000_media_type_copper) {
2396 if ((rd32(E1000_CTRL_EXT) &
2397 E1000_CTRL_EXT_LINK_MODE_SGMII))
2398 igb_set_eee_i354(hw);
2399 }
2400 break;
09b068d4
CW		 2401 default:
2402 break;
2403 }
749ab2cd
YZ		 2404
2405 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2406 return 0;
2407
2408err_register:
2409 igb_release_hw_control(adapter);
441fc6fd 2410 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2411err_eeprom:
2412 if (!igb_check_reset_block(hw))
f5f4cf08 2413 igb_reset_phy(hw);
9d5c8243
AK		 2414
2415 if (hw->flash_address)
2416 iounmap(hw->flash_address);
9d5c8243 2417err_sw_init:
047e0030 2418 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2419 iounmap(hw->hw_addr);
2420err_ioremap:
2421 free_netdev(netdev);
2422err_alloc_etherdev:
559e9c49 2423 pci_release_selected_regions(pdev,
b980ac18 2424 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2425err_pci_reg:
2426err_dma:
2427 pci_disable_device(pdev);
2428 return err;
2429}
2430
fa44f2f1
GR		 2431#ifdef CONFIG_PCI_IOV
2432static int igb_disable_sriov(struct pci_dev *pdev)
2433{
2434 struct net_device *netdev = pci_get_drvdata(pdev);
2435 struct igb_adapter *adapter = netdev_priv(netdev);
2436 struct e1000_hw *hw = &adapter->hw;
2437
2438 /* reclaim resources allocated to VFs */
2439 if (adapter->vf_data) {
2440 /* disable iov and allow time for transactions to clear */
b09186d2 2441 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2442 dev_warn(&pdev->dev,
2443 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2444 return -EPERM;
2445 } else {
2446 pci_disable_sriov(pdev);
2447 msleep(500);
2448 }
2449
2450 kfree(adapter->vf_data);
2451 adapter->vf_data = NULL;
2452 adapter->vfs_allocated_count = 0;
2453 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2454 wrfl();
2455 msleep(100);
2456 dev_info(&pdev->dev, "IOV Disabled\n");
2457
2458 /* Re-enable DMA Coalescing flag since IOV is turned off */
2459 adapter->flags |= IGB_FLAG_DMAC;
2460 }
2461
2462 return 0;
2463}
2464
2465static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2466{
2467 struct net_device *netdev = pci_get_drvdata(pdev);
2468 struct igb_adapter *adapter = netdev_priv(netdev);
2469 int old_vfs = pci_num_vf(pdev);
2470 int err = 0;
2471 int i;
2472
50267196
MW		 2473 if (!adapter->msix_entries) {
2474 err = -EPERM;
2475 goto out;
2476 }
2477
fa44f2f1
GR		 2478 if (!num_vfs)
2479 goto out;
2480 else if (old_vfs && old_vfs == num_vfs)
2481 goto out;
2482 else if (old_vfs && old_vfs != num_vfs)
2483 err = igb_disable_sriov(pdev);
2484
2485 if (err)
2486 goto out;
2487
2488 if (num_vfs > 7) {
2489 err = -EPERM;
2490 goto out;
2491 }
2492
2493 adapter->vfs_allocated_count = num_vfs;
2494
2495 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2496 sizeof(struct vf_data_storage), GFP_KERNEL);
2497
2498 /* if allocation failed then we do not support SR-IOV */
2499 if (!adapter->vf_data) {
2500 adapter->vfs_allocated_count = 0;
2501 dev_err(&pdev->dev,
2502 "Unable to allocate memory for VF Data Storage\n");
2503 err = -ENOMEM;
2504 goto out;
2505 }
2506
2507 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2508 if (err)
2509 goto err_out;
2510
2511 dev_info(&pdev->dev, "%d VFs allocated\n",
2512 adapter->vfs_allocated_count);
2513 for (i = 0; i < adapter->vfs_allocated_count; i++)
2514 igb_vf_configure(adapter, i);
2515
2516 /* DMA Coalescing is not supported in IOV mode. */
2517 adapter->flags &= ~IGB_FLAG_DMAC;
2518 goto out;
2519
2520err_out:
2521 kfree(adapter->vf_data);
2522 adapter->vf_data = NULL;
2523 adapter->vfs_allocated_count = 0;
2524out:
2525 return err;
2526}
2527
2528#endif
b980ac18 2529/**
441fc6fd
CW		 2530 * igb_remove_i2c - Cleanup I2C interface
2531 * @adapter: pointer to adapter structure
b980ac18 2532 **/
441fc6fd
CW		 2533static void igb_remove_i2c(struct igb_adapter *adapter)
2534{
441fc6fd
CW		 2535 /* free the adapter bus structure */
2536 i2c_del_adapter(&adapter->i2c_adap);
2537}
2538
9d5c8243 2539/**
b980ac18
JK		 2540 * igb_remove - Device Removal Routine
2541 * @pdev: PCI device information struct
9d5c8243 2542 *
b980ac18
JK		 2543 * igb_remove is called by the PCI subsystem to alert the driver
2544 * that it should release a PCI device. The could be caused by a
2545 * Hot-Plug event, or because the driver is going to be removed from
2546 * memory.
9d5c8243 2547 **/
9f9a12f8 2548static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2549{
2550 struct net_device *netdev = pci_get_drvdata(pdev);
2551 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2552 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2553
749ab2cd 2554 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2555#ifdef CONFIG_IGB_HWMON
2556 igb_sysfs_exit(adapter);
2557#endif
441fc6fd 2558 igb_remove_i2c(adapter);
a79f4f88 2559 igb_ptp_stop(adapter);
b980ac18 2560 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2561 * disable watchdog from being rescheduled.
2562 */
9d5c8243
AK		 2563 set_bit(__IGB_DOWN, &adapter->state);
2564 del_timer_sync(&adapter->watchdog_timer);
2565 del_timer_sync(&adapter->phy_info_timer);
2566
760141a5
TH		 2567 cancel_work_sync(&adapter->reset_task);
2568 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2569
421e02f0 2570#ifdef CONFIG_IGB_DCA
7dfc16fa 2571 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2572 dev_info(&pdev->dev, "DCA disabled\n");
2573 dca_remove_requester(&pdev->dev);
7dfc16fa 2574 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2575 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2576 }
2577#endif
2578
9d5c8243 2579 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2580 * would have already happened in close and is redundant.
2581 */
9d5c8243
AK		 2582 igb_release_hw_control(adapter);
2583
2584 unregister_netdev(netdev);
2585
047e0030 2586 igb_clear_interrupt_scheme(adapter);
9d5c8243 2587
37680117 2588#ifdef CONFIG_PCI_IOV
fa44f2f1 2589 igb_disable_sriov(pdev);
37680117 2590#endif
559e9c49 2591
28b0759c
AD		 2592 iounmap(hw->hw_addr);
2593 if (hw->flash_address)
2594 iounmap(hw->flash_address);
559e9c49 2595 pci_release_selected_regions(pdev,
b980ac18 2596 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2597
1128c756 2598 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2599 free_netdev(netdev);
2600
19d5afd4 2601 pci_disable_pcie_error_reporting(pdev);
40a914fa 2602
9d5c8243
AK		 2603 pci_disable_device(pdev);
2604}
2605
a6b623e0 2606/**
b980ac18
JK		 2607 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2608 * @adapter: board private structure to initialize
a6b623e0 2609 *
b980ac18
JK		 2610 * This function initializes the vf specific data storage and then attempts to
2611 * allocate the VFs. The reason for ordering it this way is because it is much
2612 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2613 * the memory for the VFs.
a6b623e0 2614 **/
9f9a12f8 2615static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2616{
2617#ifdef CONFIG_PCI_IOV
2618 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2619 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2620
f96a8a0b
CW		 2621 /* Virtualization features not supported on i210 family. */
2622 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2623 return;
2624
fa44f2f1 2625 pci_sriov_set_totalvfs(pdev, 7);
d5e51a10 2626 igb_enable_sriov(pdev, max_vfs);
0224d663 2627
a6b623e0
AD		 2628#endif /* CONFIG_PCI_IOV */
2629}
2630
fa44f2f1 2631static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2632{
2633 struct e1000_hw *hw = &adapter->hw;
374a542d 2634 u32 max_rss_queues;
9d5c8243 2635
374a542d 2636 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2637 switch (hw->mac.type) {
374a542d
MV		 2638 case e1000_i211:
2639 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2640 break;
2641 case e1000_82575:
f96a8a0b 2642 case e1000_i210:
374a542d
MV		 2643 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2644 break;
2645 case e1000_i350:
2646 /* I350 cannot do RSS and SR-IOV at the same time */
2647 if (!!adapter->vfs_allocated_count) {
2648 max_rss_queues = 1;
2649 break;
2650 }
2651 /* fall through */
2652 case e1000_82576:
2653 if (!!adapter->vfs_allocated_count) {
2654 max_rss_queues = 2;
2655 break;
2656 }
2657 /* fall through */
2658 case e1000_82580:
ceb5f13b 2659 case e1000_i354:
374a542d
MV		 2660 default:
2661 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2662 break;
374a542d
MV		 2663 }
2664
2665 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2666
2667 /* Determine if we need to pair queues. */
2668 switch (hw->mac.type) {
2669 case e1000_82575:
f96a8a0b 2670 case e1000_i211:
374a542d 2671 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2672 break;
374a542d 2673 case e1000_82576:
b980ac18 2674 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2675 * should pair the queues in order to conserve interrupts due
2676 * to limited supply.
2677 */
2678 if ((adapter->rss_queues > 1) &&
2679 (adapter->vfs_allocated_count > 6))
2680 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2681 /* fall through */
2682 case e1000_82580:
2683 case e1000_i350:
ceb5f13b 2684 case e1000_i354:
374a542d 2685 case e1000_i210:
f96a8a0b 2686 default:
b980ac18 2687 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2688 * order to conserve interrupts due to limited supply.
2689 */
2690 if (adapter->rss_queues > (max_rss_queues / 2))
2691 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2692 break;
2693 }
fa44f2f1
GR		 2694}
2695
2696/**
b980ac18
JK		 2697 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2698 * @adapter: board private structure to initialize
fa44f2f1 2699 *
b980ac18
JK		 2700 * igb_sw_init initializes the Adapter private data structure.
2701 * Fields are initialized based on PCI device information and
2702 * OS network device settings (MTU size).
fa44f2f1
GR		 2703 **/
2704static int igb_sw_init(struct igb_adapter *adapter)
2705{
2706 struct e1000_hw *hw = &adapter->hw;
2707 struct net_device *netdev = adapter->netdev;
2708 struct pci_dev *pdev = adapter->pdev;
2709
2710 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2711
2712 /* set default ring sizes */
2713 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2714 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2715
2716 /* set default ITR values */
2717 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2718 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2719
2720 /* set default work limits */
2721 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2722
2723 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2724 VLAN_HLEN;
2725 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2726
2727 spin_lock_init(&adapter->stats64_lock);
2728#ifdef CONFIG_PCI_IOV
2729 switch (hw->mac.type) {
2730 case e1000_82576:
2731 case e1000_i350:
2732 if (max_vfs > 7) {
2733 dev_warn(&pdev->dev,
2734 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2735 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2736 } else
2737 adapter->vfs_allocated_count = max_vfs;
2738 if (adapter->vfs_allocated_count)
2739 dev_warn(&pdev->dev,
2740 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2741 break;
2742 default:
2743 break;
2744 }
2745#endif /* CONFIG_PCI_IOV */
2746
2747 igb_init_queue_configuration(adapter);
a99955fc 2748
1128c756 2749 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2750 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2751 GFP_ATOMIC);
1128c756 2752
a6b623e0 2753 /* This call may decrease the number of queues */
53c7d064 2754 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2755 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2756 return -ENOMEM;
2757 }
2758
a6b623e0
AD		 2759 igb_probe_vfs(adapter);
2760
9d5c8243
AK		 2761 /* Explicitly disable IRQ since the NIC can be in any state. */
2762 igb_irq_disable(adapter);
2763
f96a8a0b 2764 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2765 adapter->flags &= ~IGB_FLAG_DMAC;
2766
9d5c8243
AK		 2767 set_bit(__IGB_DOWN, &adapter->state);
2768 return 0;
2769}
2770
2771/**
b980ac18
JK		 2772 * igb_open - Called when a network interface is made active
2773 * @netdev: network interface device structure
9d5c8243 2774 *
b980ac18 2775 * Returns 0 on success, negative value on failure
9d5c8243 2776 *
b980ac18
JK		 2777 * The open entry point is called when a network interface is made
2778 * active by the system (IFF_UP). At this point all resources needed
2779 * for transmit and receive operations are allocated, the interrupt
2780 * handler is registered with the OS, the watchdog timer is started,
2781 * and the stack is notified that the interface is ready.
9d5c8243 2782 **/
749ab2cd 2783static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 2784{
2785 struct igb_adapter *adapter = netdev_priv(netdev);
2786 struct e1000_hw *hw = &adapter->hw;
749ab2cd 2787 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2788 int err;
2789 int i;
2790
2791 /* disallow open during test */
749ab2cd
YZ		 2792 if (test_bit(__IGB_TESTING, &adapter->state)) {
2793 WARN_ON(resuming);
9d5c8243 2794 return -EBUSY;
749ab2cd
YZ		 2795 }
2796
2797 if (!resuming)
2798 pm_runtime_get_sync(&pdev->dev);
9d5c8243 2799
b168dfc5
JB		 2800 netif_carrier_off(netdev);
2801
9d5c8243
AK		 2802 /* allocate transmit descriptors */
2803 err = igb_setup_all_tx_resources(adapter);
2804 if (err)
2805 goto err_setup_tx;
2806
2807 /* allocate receive descriptors */
2808 err = igb_setup_all_rx_resources(adapter);
2809 if (err)
2810 goto err_setup_rx;
2811
88a268c1 2812 igb_power_up_link(adapter);
9d5c8243 2813
9d5c8243
AK		 2814 /* before we allocate an interrupt, we must be ready to handle it.
2815 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2816 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 2817 * clean_rx handler before we do so.
2818 */
9d5c8243
AK		 2819 igb_configure(adapter);
2820
2821 err = igb_request_irq(adapter);
2822 if (err)
2823 goto err_req_irq;
2824
0c2cc02e
AD		 2825 /* Notify the stack of the actual queue counts. */
2826 err = netif_set_real_num_tx_queues(adapter->netdev,
2827 adapter->num_tx_queues);
2828 if (err)
2829 goto err_set_queues;
2830
2831 err = netif_set_real_num_rx_queues(adapter->netdev,
2832 adapter->num_rx_queues);
2833 if (err)
2834 goto err_set_queues;
2835
9d5c8243
AK		 2836 /* From here on the code is the same as igb_up() */
2837 clear_bit(__IGB_DOWN, &adapter->state);
2838
0d1ae7f4
AD		 2839 for (i = 0; i < adapter->num_q_vectors; i++)
2840 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 2841
2842 /* Clear any pending interrupts. */
2843 rd32(E1000_ICR);
844290e5
PW		 2844
2845 igb_irq_enable(adapter);
2846
d4960307
AD		 2847 /* notify VFs that reset has been completed */
2848 if (adapter->vfs_allocated_count) {
2849 u32 reg_data = rd32(E1000_CTRL_EXT);
2850 reg_data |= E1000_CTRL_EXT_PFRSTD;
2851 wr32(E1000_CTRL_EXT, reg_data);
2852 }
2853
d55b53ff
JK		 2854 netif_tx_start_all_queues(netdev);
2855
749ab2cd
YZ		 2856 if (!resuming)
2857 pm_runtime_put(&pdev->dev);
2858
25568a53
AD		 2859 /* start the watchdog. */
2860 hw->mac.get_link_status = 1;
2861 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 2862
2863 return 0;
2864
0c2cc02e
AD		 2865err_set_queues:
2866 igb_free_irq(adapter);
9d5c8243
AK		 2867err_req_irq:
2868 igb_release_hw_control(adapter);
88a268c1 2869 igb_power_down_link(adapter);
9d5c8243
AK		 2870 igb_free_all_rx_resources(adapter);
2871err_setup_rx:
2872 igb_free_all_tx_resources(adapter);
2873err_setup_tx:
2874 igb_reset(adapter);
749ab2cd
YZ		 2875 if (!resuming)
2876 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 2877
2878 return err;
2879}
2880
749ab2cd
YZ		 2881static int igb_open(struct net_device *netdev)
2882{
2883 return __igb_open(netdev, false);
2884}
2885
9d5c8243 2886/**
b980ac18
JK		 2887 * igb_close - Disables a network interface
2888 * @netdev: network interface device structure
9d5c8243 2889 *
b980ac18 2890 * Returns 0, this is not allowed to fail
9d5c8243 2891 *
b980ac18
JK		 2892 * The close entry point is called when an interface is de-activated
2893 * by the OS. The hardware is still under the driver's control, but
2894 * needs to be disabled. A global MAC reset is issued to stop the
2895 * hardware, and all transmit and receive resources are freed.
9d5c8243 2896 **/
749ab2cd 2897static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 2898{
2899 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 2900 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2901
2902 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 2903
749ab2cd
YZ		 2904 if (!suspending)
2905 pm_runtime_get_sync(&pdev->dev);
2906
2907 igb_down(adapter);
9d5c8243
AK		 2908 igb_free_irq(adapter);
2909
2910 igb_free_all_tx_resources(adapter);
2911 igb_free_all_rx_resources(adapter);
2912
749ab2cd
YZ		 2913 if (!suspending)
2914 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 2915 return 0;
2916}
2917
749ab2cd
YZ		 2918static int igb_close(struct net_device *netdev)
2919{
2920 return __igb_close(netdev, false);
2921}
2922
9d5c8243 2923/**
b980ac18
JK		 2924 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2925 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 2926 *
b980ac18 2927 * Return 0 on success, negative on failure
9d5c8243 2928 **/
80785298 2929int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 2930{
59d71989 2931 struct device *dev = tx_ring->dev;
9d5c8243
AK		 2932 int size;
2933
06034649 2934 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 2935
2936 tx_ring->tx_buffer_info = vzalloc(size);
06034649 2937 if (!tx_ring->tx_buffer_info)
9d5c8243 2938 goto err;
9d5c8243
AK		 2939
2940 /* round up to nearest 4K */
85e8d004 2941 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 2942 tx_ring->size = ALIGN(tx_ring->size, 4096);
2943
5536d210
AD		 2944 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2945 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 2946 if (!tx_ring->desc)
2947 goto err;
2948
9d5c8243
AK		 2949 tx_ring->next_to_use = 0;
2950 tx_ring->next_to_clean = 0;
81c2fc22 2951
9d5c8243
AK		 2952 return 0;
2953
2954err:
06034649 2955 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 2956 tx_ring->tx_buffer_info = NULL;
2957 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 2958 return -ENOMEM;
2959}
2960
2961/**
b980ac18
JK		 2962 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2963 * (Descriptors) for all queues
2964 * @adapter: board private structure
9d5c8243 2965 *
b980ac18 2966 * Return 0 on success, negative on failure
9d5c8243
AK		 2967 **/
2968static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2969{
439705e1 2970 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 2971 int i, err = 0;
2972
2973 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 2974 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 2975 if (err) {
439705e1 2976 dev_err(&pdev->dev,
9d5c8243
AK		 2977 "Allocation for Tx Queue %u failed\n", i);
2978 for (i--; i >= 0; i--)
3025a446 2979 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 2980 break;
2981 }
2982 }
2983
2984 return err;
2985}
2986
2987/**
b980ac18
JK		 2988 * igb_setup_tctl - configure the transmit control registers
2989 * @adapter: Board private structure
9d5c8243 2990 **/
d7ee5b3a 2991void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 2992{
9d5c8243
AK		 2993 struct e1000_hw *hw = &adapter->hw;
2994 u32 tctl;
9d5c8243 2995
85b430b4
AD		 2996 /* disable queue 0 which is enabled by default on 82575 and 82576 */
2997 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 2998
2999 /* Program the Transmit Control Register */
9d5c8243
AK		 3000 tctl = rd32(E1000_TCTL);
3001 tctl &= ~E1000_TCTL_CT;
3002 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3003 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3004
3005 igb_config_collision_dist(hw);
3006
9d5c8243
AK		 3007 /* Enable transmits */
3008 tctl |= E1000_TCTL_EN;
3009
3010 wr32(E1000_TCTL, tctl);
3011}
3012
85b430b4 3013/**
b980ac18
JK		 3014 * igb_configure_tx_ring - Configure transmit ring after Reset
3015 * @adapter: board private structure
3016 * @ring: tx ring to configure
85b430b4 3017 *
b980ac18 3018 * Configure a transmit ring after a reset.
85b430b4 3019 **/
d7ee5b3a
AD		 3020void igb_configure_tx_ring(struct igb_adapter *adapter,
3021 struct igb_ring *ring)
85b430b4
AD		 3022{
3023 struct e1000_hw *hw = &adapter->hw;
a74420e0 3024 u32 txdctl = 0;
85b430b4
AD		 3025 u64 tdba = ring->dma;
3026 int reg_idx = ring->reg_idx;
3027
3028 /* disable the queue */
a74420e0 3029 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3030 wrfl();
3031 mdelay(10);
3032
3033 wr32(E1000_TDLEN(reg_idx),
b980ac18 3034 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3035 wr32(E1000_TDBAL(reg_idx),
b980ac18 3036 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3037 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3038
fce99e34 3039 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3040 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3041 writel(0, ring->tail);
85b430b4
AD		 3042
3043 txdctl |= IGB_TX_PTHRESH;
3044 txdctl |= IGB_TX_HTHRESH << 8;
3045 txdctl |= IGB_TX_WTHRESH << 16;
3046
3047 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3048 wr32(E1000_TXDCTL(reg_idx), txdctl);
3049}
3050
3051/**
b980ac18
JK		 3052 * igb_configure_tx - Configure transmit Unit after Reset
3053 * @adapter: board private structure
85b430b4 3054 *
b980ac18 3055 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3056 **/
3057static void igb_configure_tx(struct igb_adapter *adapter)
3058{
3059 int i;
3060
3061 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3062 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3063}
3064
9d5c8243 3065/**
b980ac18
JK		 3066 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3067 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3068 *
b980ac18 3069 * Returns 0 on success, negative on failure
9d5c8243 3070 **/
80785298 3071int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3072{
59d71989 3073 struct device *dev = rx_ring->dev;
f33005a6 3074 int size;
9d5c8243 3075
06034649 3076 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3077
3078 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3079 if (!rx_ring->rx_buffer_info)
9d5c8243 3080 goto err;
9d5c8243 3081
9d5c8243 3082 /* Round up to nearest 4K */
f33005a6 3083 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3084 rx_ring->size = ALIGN(rx_ring->size, 4096);
3085
5536d210
AD		 3086 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3087 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3088 if (!rx_ring->desc)
3089 goto err;
3090
cbc8e55f 3091 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3092 rx_ring->next_to_clean = 0;
3093 rx_ring->next_to_use = 0;
9d5c8243 3094
9d5c8243
AK		 3095 return 0;
3096
3097err:
06034649
AD		 3098 vfree(rx_ring->rx_buffer_info);
3099 rx_ring->rx_buffer_info = NULL;
f33005a6 3100 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3101 return -ENOMEM;
3102}
3103
3104/**
b980ac18
JK		 3105 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3106 * (Descriptors) for all queues
3107 * @adapter: board private structure
9d5c8243 3108 *
b980ac18 3109 * Return 0 on success, negative on failure
9d5c8243
AK		 3110 **/
3111static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3112{
439705e1 3113 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3114 int i, err = 0;
3115
3116 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3117 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3118 if (err) {
439705e1 3119 dev_err(&pdev->dev,
9d5c8243
AK		 3120 "Allocation for Rx Queue %u failed\n", i);
3121 for (i--; i >= 0; i--)
3025a446 3122 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3123 break;
3124 }
3125 }
3126
3127 return err;
3128}
3129
06cf2666 3130/**
b980ac18
JK		 3131 * igb_setup_mrqc - configure the multiple receive queue control registers
3132 * @adapter: Board private structure
06cf2666
AD		 3133 **/
3134static void igb_setup_mrqc(struct igb_adapter *adapter)
3135{
3136 struct e1000_hw *hw = &adapter->hw;
3137 u32 mrqc, rxcsum;
ed12cc9a 3138 u32 j, num_rx_queues;
a57fe23e
AD		 3139 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3140 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3141 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3142 0xFA01ACBE };
06cf2666
AD		 3143
3144 /* Fill out hash function seeds */
a57fe23e
AD		 3145 for (j = 0; j < 10; j++)
3146 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3147
a99955fc 3148 num_rx_queues = adapter->rss_queues;
06cf2666 3149
797fd4be 3150 switch (hw->mac.type) {
797fd4be
AD		 3151 case e1000_82576:
3152 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3153 if (adapter->vfs_allocated_count)
06cf2666 3154 num_rx_queues = 2;
797fd4be
AD		 3155 break;
3156 default:
3157 break;
06cf2666
AD		 3158 }
3159
ed12cc9a
LMV		 3160 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3161 for (j = 0; j < IGB_RETA_SIZE; j++)
3162 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3163 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3164 }
ed12cc9a 3165 igb_write_rss_indir_tbl(adapter);
06cf2666 3166
b980ac18 3167 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3168 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3169 * offloads as they are enabled by default
3170 */
3171 rxcsum = rd32(E1000_RXCSUM);
3172 rxcsum |= E1000_RXCSUM_PCSD;
3173
3174 if (adapter->hw.mac.type >= e1000_82576)
3175 /* Enable Receive Checksum Offload for SCTP */
3176 rxcsum |= E1000_RXCSUM_CRCOFL;
3177
3178 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3179 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3180
039454a8
AA		 3181 /* Generate RSS hash based on packet types, TCP/UDP
3182 * port numbers and/or IPv4/v6 src and dst addresses
3183 */
f96a8a0b
CW		 3184 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3185 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3186 E1000_MRQC_RSS_FIELD_IPV6 |
3187 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3188 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3189
039454a8
AA		 3190 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3191 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3192 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3193 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3194
06cf2666
AD		 3195 /* If VMDq is enabled then we set the appropriate mode for that, else
3196 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3197 * if we are only using one queue
3198 */
06cf2666
AD		 3199 if (adapter->vfs_allocated_count) {
3200 if (hw->mac.type > e1000_82575) {
3201 /* Set the default pool for the PF's first queue */
3202 u32 vtctl = rd32(E1000_VT_CTL);
3203 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3204 E1000_VT_CTL_DISABLE_DEF_POOL);
3205 vtctl |= adapter->vfs_allocated_count <<
3206 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3207 wr32(E1000_VT_CTL, vtctl);
3208 }
a99955fc 3209 if (adapter->rss_queues > 1)
f96a8a0b 3210 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3211 else
f96a8a0b 3212 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3213 } else {
f96a8a0b
CW		 3214 if (hw->mac.type != e1000_i211)
3215 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3216 }
3217 igb_vmm_control(adapter);
3218
06cf2666
AD		 3219 wr32(E1000_MRQC, mrqc);
3220}
3221
9d5c8243 3222/**
b980ac18
JK		 3223 * igb_setup_rctl - configure the receive control registers
3224 * @adapter: Board private structure
9d5c8243 3225 **/
d7ee5b3a 3226void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3227{
3228 struct e1000_hw *hw = &adapter->hw;
3229 u32 rctl;
9d5c8243
AK		 3230
3231 rctl = rd32(E1000_RCTL);
3232
3233 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3234 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3235
69d728ba 3236 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3237 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3238
b980ac18 3239 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3240 * redirection as it did with e1000. Newer features require
3241 * that the HW strips the CRC.
73cd78f1 3242 */
87cb7e8c 3243 rctl |= E1000_RCTL_SECRC;
9d5c8243 3244
559e9c49 3245 /* disable store bad packets and clear size bits. */
ec54d7d6 3246 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3247
6ec43fe6
AD		 3248 /* enable LPE to prevent packets larger than max_frame_size */
3249 rctl |= E1000_RCTL_LPE;
9d5c8243 3250
952f72a8
AD		 3251 /* disable queue 0 to prevent tail write w/o re-config */
3252 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3253
e1739522
AD		 3254 /* Attention!!! For SR-IOV PF driver operations you must enable
3255 * queue drop for all VF and PF queues to prevent head of line blocking
3256 * if an un-trusted VF does not provide descriptors to hardware.
3257 */
3258 if (adapter->vfs_allocated_count) {
e1739522
AD		 3259 /* set all queue drop enable bits */
3260 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3261 }
3262
89eaefb6
BG		 3263 /* This is useful for sniffing bad packets. */
3264 if (adapter->netdev->features & NETIF_F_RXALL) {
3265 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3266 * in e1000e_set_rx_mode
3267 */
89eaefb6
BG		 3268 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3269 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3270 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3271
3272 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3273 E1000_RCTL_DPF | /* Allow filtered pause */
3274 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3275 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3276 * and that breaks VLANs.
3277 */
3278 }
3279
9d5c8243
AK		 3280 wr32(E1000_RCTL, rctl);
3281}
3282
7d5753f0
AD		 3283static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3284 int vfn)
3285{
3286 struct e1000_hw *hw = &adapter->hw;
3287 u32 vmolr;
3288
3289 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3290 * increase the size to support vlan tags
3291 */
7d5753f0
AD		 3292 if (vfn < adapter->vfs_allocated_count &&
3293 adapter->vf_data[vfn].vlans_enabled)
3294 size += VLAN_TAG_SIZE;
3295
3296 vmolr = rd32(E1000_VMOLR(vfn));
3297 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3298 vmolr |= size | E1000_VMOLR_LPE;
3299 wr32(E1000_VMOLR(vfn), vmolr);
3300
3301 return 0;
3302}
3303
e1739522 3304/**
b980ac18
JK		 3305 * igb_rlpml_set - set maximum receive packet size
3306 * @adapter: board private structure
e1739522 3307 *
b980ac18 3308 * Configure maximum receivable packet size.
e1739522
AD		 3309 **/
3310static void igb_rlpml_set(struct igb_adapter *adapter)
3311{
153285f9 3312 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3313 struct e1000_hw *hw = &adapter->hw;
3314 u16 pf_id = adapter->vfs_allocated_count;
3315
e1739522
AD		 3316 if (pf_id) {
3317 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3318 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3319 * to our max jumbo frame size, in case we need to enable
3320 * jumbo frames on one of the rings later.
3321 * This will not pass over-length frames into the default
3322 * queue because it's gated by the VMOLR.RLPML.
3323 */
7d5753f0 3324 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3325 }
3326
3327 wr32(E1000_RLPML, max_frame_size);
3328}
3329
8151d294
WM		 3330static inline void igb_set_vmolr(struct igb_adapter *adapter,
3331 int vfn, bool aupe)
7d5753f0
AD		 3332{
3333 struct e1000_hw *hw = &adapter->hw;
3334 u32 vmolr;
3335
b980ac18 3336 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3337 * we should exit and do nothing
3338 */
3339 if (hw->mac.type < e1000_82576)
3340 return;
3341
3342 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3343 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
8151d294 3344 if (aupe)
b980ac18 3345 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3346 else
3347 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3348
3349 /* clear all bits that might not be set */
3350 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3351
a99955fc 3352 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3353 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3354 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3355 * multicast packets
3356 */
3357 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3358 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3359
3360 wr32(E1000_VMOLR(vfn), vmolr);
3361}
3362
85b430b4 3363/**
b980ac18
JK		 3364 * igb_configure_rx_ring - Configure a receive ring after Reset
3365 * @adapter: board private structure
3366 * @ring: receive ring to be configured
85b430b4 3367 *
b980ac18 3368 * Configure the Rx unit of the MAC after a reset.
85b430b4 3369 **/
d7ee5b3a 3370void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3371 struct igb_ring *ring)
85b430b4
AD		 3372{
3373 struct e1000_hw *hw = &adapter->hw;
3374 u64 rdba = ring->dma;
3375 int reg_idx = ring->reg_idx;
a74420e0 3376 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3377
3378 /* disable the queue */
a74420e0 3379 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3380
3381 /* Set DMA base address registers */
3382 wr32(E1000_RDBAL(reg_idx),
3383 rdba & 0x00000000ffffffffULL);
3384 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3385 wr32(E1000_RDLEN(reg_idx),
b980ac18 3386 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3387
3388 /* initialize head and tail */
fce99e34 3389 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3390 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3391 writel(0, ring->tail);
85b430b4 3392
952f72a8 3393 /* set descriptor configuration */
44390ca6 3394 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3395 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3396 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3397 if (hw->mac.type >= e1000_82580)
757b77e2 3398 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3399 /* Only set Drop Enable if we are supporting multiple queues */
3400 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3401 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3402
3403 wr32(E1000_SRRCTL(reg_idx), srrctl);
3404
7d5753f0 3405 /* set filtering for VMDQ pools */
8151d294 3406 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3407
85b430b4
AD		 3408 rxdctl |= IGB_RX_PTHRESH;
3409 rxdctl |= IGB_RX_HTHRESH << 8;
3410 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3411
3412 /* enable receive descriptor fetching */
3413 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3414 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3415}
3416
9d5c8243 3417/**
b980ac18
JK		 3418 * igb_configure_rx - Configure receive Unit after Reset
3419 * @adapter: board private structure
9d5c8243 3420 *
b980ac18 3421 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3422 **/
3423static void igb_configure_rx(struct igb_adapter *adapter)
3424{
9107584e 3425 int i;
9d5c8243 3426
68d480c4
AD		 3427 /* set UTA to appropriate mode */
3428 igb_set_uta(adapter);
3429
26ad9178
AD		 3430 /* set the correct pool for the PF default MAC address in entry 0 */
3431 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3432 adapter->vfs_allocated_count);
26ad9178 3433
06cf2666 3434 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3435 * the Base and Length of the Rx Descriptor Ring
3436 */
f9d40f6a
AD		 3437 for (i = 0; i < adapter->num_rx_queues; i++)
3438 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3439}
3440
3441/**
b980ac18
JK		 3442 * igb_free_tx_resources - Free Tx Resources per Queue
3443 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3444 *
b980ac18 3445 * Free all transmit software resources
9d5c8243 3446 **/
68fd9910 3447void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3448{
3b644cf6 3449 igb_clean_tx_ring(tx_ring);
9d5c8243 3450
06034649
AD		 3451 vfree(tx_ring->tx_buffer_info);
3452 tx_ring->tx_buffer_info = NULL;
9d5c8243 3453
439705e1
AD		 3454 /* if not set, then don't free */
3455 if (!tx_ring->desc)
3456 return;
3457
59d71989
AD		 3458 dma_free_coherent(tx_ring->dev, tx_ring->size,
3459 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3460
3461 tx_ring->desc = NULL;
3462}
3463
3464/**
b980ac18
JK		 3465 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3466 * @adapter: board private structure
9d5c8243 3467 *
b980ac18 3468 * Free all transmit software resources
9d5c8243
AK		 3469 **/
3470static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3471{
3472 int i;
3473
3474 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3475 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3476}
3477
ebe42d16
AD		 3478void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3479 struct igb_tx_buffer *tx_buffer)
3480{
3481 if (tx_buffer->skb) {
3482 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3483 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3484 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3485 dma_unmap_addr(tx_buffer, dma),
3486 dma_unmap_len(tx_buffer, len),
ebe42d16 3487 DMA_TO_DEVICE);
c9f14bf3 3488 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3489 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3490 dma_unmap_addr(tx_buffer, dma),
3491 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3492 DMA_TO_DEVICE);
3493 }
3494 tx_buffer->next_to_watch = NULL;
3495 tx_buffer->skb = NULL;
c9f14bf3 3496 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3497 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3498}
3499
3500/**
b980ac18
JK		 3501 * igb_clean_tx_ring - Free Tx Buffers
3502 * @tx_ring: ring to be cleaned
9d5c8243 3503 **/
3b644cf6 3504static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3505{
06034649 3506 struct igb_tx_buffer *buffer_info;
9d5c8243 3507 unsigned long size;
6ad4edfc 3508 u16 i;
9d5c8243 3509
06034649 3510 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3511 return;
3512 /* Free all the Tx ring sk_buffs */
3513
3514 for (i = 0; i < tx_ring->count; i++) {
06034649 3515 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3516 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3517 }
3518
dad8a3b3
JF		 3519 netdev_tx_reset_queue(txring_txq(tx_ring));
3520
06034649
AD		 3521 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3522 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3523
3524 /* Zero out the descriptor ring */
9d5c8243
AK		 3525 memset(tx_ring->desc, 0, tx_ring->size);
3526
3527 tx_ring->next_to_use = 0;
3528 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3529}
3530
3531/**
b980ac18
JK		 3532 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3533 * @adapter: board private structure
9d5c8243
AK		 3534 **/
3535static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3536{
3537 int i;
3538
3539 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3540 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3541}
3542
3543/**
b980ac18
JK		 3544 * igb_free_rx_resources - Free Rx Resources
3545 * @rx_ring: ring to clean the resources from
9d5c8243 3546 *
b980ac18 3547 * Free all receive software resources
9d5c8243 3548 **/
68fd9910 3549void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3550{
3b644cf6 3551 igb_clean_rx_ring(rx_ring);
9d5c8243 3552
06034649
AD		 3553 vfree(rx_ring->rx_buffer_info);
3554 rx_ring->rx_buffer_info = NULL;
9d5c8243 3555
439705e1
AD		 3556 /* if not set, then don't free */
3557 if (!rx_ring->desc)
3558 return;
3559
59d71989
AD		 3560 dma_free_coherent(rx_ring->dev, rx_ring->size,
3561 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3562
3563 rx_ring->desc = NULL;
3564}
3565
3566/**
b980ac18
JK		 3567 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3568 * @adapter: board private structure
9d5c8243 3569 *
b980ac18 3570 * Free all receive software resources
9d5c8243
AK		 3571 **/
3572static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3573{
3574 int i;
3575
3576 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3577 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3578}
3579
3580/**
b980ac18
JK		 3581 * igb_clean_rx_ring - Free Rx Buffers per Queue
3582 * @rx_ring: ring to free buffers from
9d5c8243 3583 **/
3b644cf6 3584static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3585{
9d5c8243 3586 unsigned long size;
c023cd88 3587 u16 i;
9d5c8243 3588
1a1c225b
AD		 3589 if (rx_ring->skb)
3590 dev_kfree_skb(rx_ring->skb);
3591 rx_ring->skb = NULL;
3592
06034649 3593 if (!rx_ring->rx_buffer_info)
9d5c8243 3594 return;
439705e1 3595
9d5c8243
AK		 3596 /* Free all the Rx ring sk_buffs */
3597 for (i = 0; i < rx_ring->count; i++) {
06034649 3598 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3599
cbc8e55f
AD		 3600 if (!buffer_info->page)
3601 continue;
3602
3603 dma_unmap_page(rx_ring->dev,
3604 buffer_info->dma,
3605 PAGE_SIZE,
3606 DMA_FROM_DEVICE);
3607 __free_page(buffer_info->page);
3608
1a1c225b 3609 buffer_info->page = NULL;
9d5c8243
AK		 3610 }
3611
06034649
AD		 3612 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3613 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3614
3615 /* Zero out the descriptor ring */
3616 memset(rx_ring->desc, 0, rx_ring->size);
3617
cbc8e55f 3618 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3619 rx_ring->next_to_clean = 0;
3620 rx_ring->next_to_use = 0;
9d5c8243
AK		 3621}
3622
3623/**
b980ac18
JK		 3624 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3625 * @adapter: board private structure
9d5c8243
AK		 3626 **/
3627static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3628{
3629 int i;
3630
3631 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3632 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3633}
3634
3635/**
b980ac18
JK		 3636 * igb_set_mac - Change the Ethernet Address of the NIC
3637 * @netdev: network interface device structure
3638 * @p: pointer to an address structure
9d5c8243 3639 *
b980ac18 3640 * Returns 0 on success, negative on failure
9d5c8243
AK		 3641 **/
3642static int igb_set_mac(struct net_device *netdev, void *p)
3643{
3644 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3645 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3646 struct sockaddr *addr = p;
3647
3648 if (!is_valid_ether_addr(addr->sa_data))
3649 return -EADDRNOTAVAIL;
3650
3651 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3652 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3653
26ad9178
AD		 3654 /* set the correct pool for the new PF MAC address in entry 0 */
3655 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3656 adapter->vfs_allocated_count);
e1739522 3657
9d5c8243
AK		 3658 return 0;
3659}
3660
3661/**
b980ac18
JK		 3662 * igb_write_mc_addr_list - write multicast addresses to MTA
3663 * @netdev: network interface device structure
9d5c8243 3664 *
b980ac18
JK		 3665 * Writes multicast address list to the MTA hash table.
3666 * Returns: -ENOMEM on failure
3667 * 0 on no addresses written
3668 * X on writing X addresses to MTA
9d5c8243 3669 **/
68d480c4 3670static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3671{
3672 struct igb_adapter *adapter = netdev_priv(netdev);
3673 struct e1000_hw *hw = &adapter->hw;
22bedad3 3674 struct netdev_hw_addr *ha;
68d480c4 3675 u8 *mta_list;
9d5c8243
AK		 3676 int i;
3677
4cd24eaf 3678 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3679 /* nothing to program, so clear mc list */
3680 igb_update_mc_addr_list(hw, NULL, 0);
3681 igb_restore_vf_multicasts(adapter);
3682 return 0;
3683 }
9d5c8243 3684
4cd24eaf 3685 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3686 if (!mta_list)
3687 return -ENOMEM;
ff41f8dc 3688
68d480c4 3689 /* The shared function expects a packed array of only addresses. */
48e2f183 3690 i = 0;
22bedad3
JP		 3691 netdev_for_each_mc_addr(ha, netdev)
3692 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3693
68d480c4
AD		 3694 igb_update_mc_addr_list(hw, mta_list, i);
3695 kfree(mta_list);
3696
4cd24eaf 3697 return netdev_mc_count(netdev);
68d480c4
AD		 3698}
3699
3700/**
b980ac18
JK		 3701 * igb_write_uc_addr_list - write unicast addresses to RAR table
3702 * @netdev: network interface device structure
68d480c4 3703 *
b980ac18
JK		 3704 * Writes unicast address list to the RAR table.
3705 * Returns: -ENOMEM on failure/insufficient address space
3706 * 0 on no addresses written
3707 * X on writing X addresses to the RAR table
68d480c4
AD		 3708 **/
3709static int igb_write_uc_addr_list(struct net_device *netdev)
3710{
3711 struct igb_adapter *adapter = netdev_priv(netdev);
3712 struct e1000_hw *hw = &adapter->hw;
3713 unsigned int vfn = adapter->vfs_allocated_count;
3714 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3715 int count = 0;
3716
3717 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3718 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3719 return -ENOMEM;
9d5c8243 3720
32e7bfc4 3721 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3722 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3723
3724 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3725 if (!rar_entries)
3726 break;
26ad9178 3727 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3728 rar_entries--,
3729 vfn);
68d480c4 3730 count++;
ff41f8dc
AD		 3731 }
3732 }
3733 /* write the addresses in reverse order to avoid write combining */
3734 for (; rar_entries > 0 ; rar_entries--) {
3735 wr32(E1000_RAH(rar_entries), 0);
3736 wr32(E1000_RAL(rar_entries), 0);
3737 }
3738 wrfl();
3739
68d480c4
AD		 3740 return count;
3741}
3742
3743/**
b980ac18
JK		 3744 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3745 * @netdev: network interface device structure
68d480c4 3746 *
b980ac18
JK		 3747 * The set_rx_mode entry point is called whenever the unicast or multicast
3748 * address lists or the network interface flags are updated. This routine is
3749 * responsible for configuring the hardware for proper unicast, multicast,
3750 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3751 **/
3752static void igb_set_rx_mode(struct net_device *netdev)
3753{
3754 struct igb_adapter *adapter = netdev_priv(netdev);
3755 struct e1000_hw *hw = &adapter->hw;
3756 unsigned int vfn = adapter->vfs_allocated_count;
3757 u32 rctl, vmolr = 0;
3758 int count;
3759
3760 /* Check for Promiscuous and All Multicast modes */
3761 rctl = rd32(E1000_RCTL);
3762
3763 /* clear the effected bits */
3764 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3765
3766 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3767 /* retain VLAN HW filtering if in VT mode */
7e44892c 3768 if (adapter->vfs_allocated_count)
6f3dc319 3769 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 3770 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3771 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3772 } else {
3773 if (netdev->flags & IFF_ALLMULTI) {
3774 rctl |= E1000_RCTL_MPE;
3775 vmolr |= E1000_VMOLR_MPME;
3776 } else {
b980ac18 3777 /* Write addresses to the MTA, if the attempt fails
25985edc 3778 * then we should just turn on promiscuous mode so
68d480c4
AD		 3779 * that we can at least receive multicast traffic
3780 */
3781 count = igb_write_mc_addr_list(netdev);
3782 if (count < 0) {
3783 rctl |= E1000_RCTL_MPE;
3784 vmolr |= E1000_VMOLR_MPME;
3785 } else if (count) {
3786 vmolr |= E1000_VMOLR_ROMPE;
3787 }
3788 }
b980ac18 3789 /* Write addresses to available RAR registers, if there is not
68d480c4 3790 * sufficient space to store all the addresses then enable
25985edc 3791 * unicast promiscuous mode
68d480c4
AD		 3792 */
3793 count = igb_write_uc_addr_list(netdev);
3794 if (count < 0) {
3795 rctl |= E1000_RCTL_UPE;
3796 vmolr |= E1000_VMOLR_ROPE;
3797 }
3798 rctl |= E1000_RCTL_VFE;
28fc06f5 3799 }
68d480c4 3800 wr32(E1000_RCTL, rctl);
28fc06f5 3801
b980ac18 3802 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 3803 * the VMOLR to enable the appropriate modes. Without this workaround
3804 * we will have issues with VLAN tag stripping not being done for frames
3805 * that are only arriving because we are the default pool
3806 */
f96a8a0b 3807 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 3808 return;
9d5c8243 3809
68d480c4 3810 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 3811 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 3812 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 3813 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 3814}
3815
13800469
GR		 3816static void igb_check_wvbr(struct igb_adapter *adapter)
3817{
3818 struct e1000_hw *hw = &adapter->hw;
3819 u32 wvbr = 0;
3820
3821 switch (hw->mac.type) {
3822 case e1000_82576:
3823 case e1000_i350:
3824 if (!(wvbr = rd32(E1000_WVBR)))
3825 return;
3826 break;
3827 default:
3828 break;
3829 }
3830
3831 adapter->wvbr |= wvbr;
3832}
3833
3834#define IGB_STAGGERED_QUEUE_OFFSET 8
3835
3836static void igb_spoof_check(struct igb_adapter *adapter)
3837{
3838 int j;
3839
3840 if (!adapter->wvbr)
3841 return;
3842
3843 for(j = 0; j < adapter->vfs_allocated_count; j++) {
3844 if (adapter->wvbr & (1 << j) ||
3845 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3846 dev_warn(&adapter->pdev->dev,
3847 "Spoof event(s) detected on VF %d\n", j);
3848 adapter->wvbr &=
3849 ~((1 << j) |
3850 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3851 }
3852 }
3853}
3854
9d5c8243 3855/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 3856 * the phy
3857 */
9d5c8243
AK		 3858static void igb_update_phy_info(unsigned long data)
3859{
3860 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 3861 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 3862}
3863
4d6b725e 3864/**
b980ac18
JK		 3865 * igb_has_link - check shared code for link and determine up/down
3866 * @adapter: pointer to driver private info
4d6b725e 3867 **/
3145535a 3868bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 3869{
3870 struct e1000_hw *hw = &adapter->hw;
3871 bool link_active = false;
4d6b725e
AD		 3872
3873 /* get_link_status is set on LSC (link status) interrupt or
3874 * rx sequence error interrupt. get_link_status will stay
3875 * false until the e1000_check_for_link establishes link
3876 * for copper adapters ONLY
3877 */
3878 switch (hw->phy.media_type) {
3879 case e1000_media_type_copper:
e5c3370f
AA		 3880 if (!hw->mac.get_link_status)
3881 return true;
4d6b725e 3882 case e1000_media_type_internal_serdes:
e5c3370f
AA		 3883 hw->mac.ops.check_for_link(hw);
3884 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 3885 break;
3886 default:
3887 case e1000_media_type_unknown:
3888 break;
3889 }
3890
aa9b8cc4
AA		 3891 if (((hw->mac.type == e1000_i210) ||
3892 (hw->mac.type == e1000_i211)) &&
3893 (hw->phy.id == I210_I_PHY_ID)) {
3894 if (!netif_carrier_ok(adapter->netdev)) {
3895 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3896 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
3897 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
3898 adapter->link_check_timeout = jiffies;
3899 }
3900 }
3901
4d6b725e
AD		 3902 return link_active;
3903}
3904
563988dc
SA		 3905static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3906{
3907 bool ret = false;
3908 u32 ctrl_ext, thstat;
3909
f96a8a0b 3910 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 3911 if (hw->mac.type == e1000_i350) {
3912 thstat = rd32(E1000_THSTAT);
3913 ctrl_ext = rd32(E1000_CTRL_EXT);
3914
3915 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 3916 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 3917 ret = !!(thstat & event);
563988dc
SA		 3918 }
3919
3920 return ret;
3921}
3922
9d5c8243 3923/**
b980ac18
JK		 3924 * igb_watchdog - Timer Call-back
3925 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 3926 **/
3927static void igb_watchdog(unsigned long data)
3928{
3929 struct igb_adapter *adapter = (struct igb_adapter *)data;
3930 /* Do the rest outside of interrupt context */
3931 schedule_work(&adapter->watchdog_task);
3932}
3933
3934static void igb_watchdog_task(struct work_struct *work)
3935{
3936 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 3937 struct igb_adapter,
3938 watchdog_task);
9d5c8243 3939 struct e1000_hw *hw = &adapter->hw;
c0ba4778 3940 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 3941 struct net_device *netdev = adapter->netdev;
563988dc 3942 u32 link;
7a6ea550 3943 int i;
9d5c8243 3944
4d6b725e 3945 link = igb_has_link(adapter);
aa9b8cc4
AA		 3946
3947 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
3948 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
3949 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
3950 else
3951 link = false;
3952 }
3953
9d5c8243 3954 if (link) {
749ab2cd
YZ		 3955 /* Cancel scheduled suspend requests. */
3956 pm_runtime_resume(netdev->dev.parent);
3957
9d5c8243
AK		 3958 if (!netif_carrier_ok(netdev)) {
3959 u32 ctrl;
330a6d6a 3960 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 3961 &adapter->link_speed,
3962 &adapter->link_duplex);
9d5c8243
AK		 3963
3964 ctrl = rd32(E1000_CTRL);
527d47c1 3965 /* Links status message must follow this format */
876d2d6f
JK		 3966 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3967 "Duplex, Flow Control: %s\n",
559e9c49
AD		 3968 netdev->name,
3969 adapter->link_speed,
3970 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 3971 "Full" : "Half",
3972 (ctrl & E1000_CTRL_TFCE) &&
3973 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3974 (ctrl & E1000_CTRL_RFCE) ? "RX" :
3975 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 3976
c0ba4778
KS		 3977 /* check if SmartSpeed worked */
3978 igb_check_downshift(hw);
3979 if (phy->speed_downgraded)
3980 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
3981
563988dc 3982 /* check for thermal sensor event */
876d2d6f
JK		 3983 if (igb_thermal_sensor_event(hw,
3984 E1000_THSTAT_LINK_THROTTLE)) {
3985 netdev_info(netdev, "The network adapter link "
3986 "speed was downshifted because it "
3987 "overheated\n");
7ef5ed1c 3988 }
563988dc 3989
d07f3e37 3990 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 3991 adapter->tx_timeout_factor = 1;
3992 switch (adapter->link_speed) {
3993 case SPEED_10:
9d5c8243
AK		 3994 adapter->tx_timeout_factor = 14;
3995 break;
3996 case SPEED_100:
9d5c8243
AK		 3997 /* maybe add some timeout factor ? */
3998 break;
3999 }
4000
4001 netif_carrier_on(netdev);
9d5c8243 4002
4ae196df 4003 igb_ping_all_vfs(adapter);
17dc566c 4004 igb_check_vf_rate_limit(adapter);
4ae196df 4005
4b1a9877 4006 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4007 if (!test_bit(__IGB_DOWN, &adapter->state))
4008 mod_timer(&adapter->phy_info_timer,
4009 round_jiffies(jiffies + 2 * HZ));
4010 }
4011 } else {
4012 if (netif_carrier_ok(netdev)) {
4013 adapter->link_speed = 0;
4014 adapter->link_duplex = 0;
563988dc
SA		 4015
4016 /* check for thermal sensor event */
876d2d6f
JK		 4017 if (igb_thermal_sensor_event(hw,
4018 E1000_THSTAT_PWR_DOWN)) {
4019 netdev_err(netdev, "The network adapter was "
4020 "stopped because it overheated\n");
7ef5ed1c 4021 }
563988dc 4022
527d47c1
AD		 4023 /* Links status message must follow this format */
4024 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4025 netdev->name);
9d5c8243 4026 netif_carrier_off(netdev);
4b1a9877 4027
4ae196df
AD		 4028 igb_ping_all_vfs(adapter);
4029
4b1a9877 4030 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4031 if (!test_bit(__IGB_DOWN, &adapter->state))
4032 mod_timer(&adapter->phy_info_timer,
4033 round_jiffies(jiffies + 2 * HZ));
749ab2cd
YZ		 4034
4035 pm_schedule_suspend(netdev->dev.parent,
4036 MSEC_PER_SEC * 5);
9d5c8243
AK		 4037 }
4038 }
4039
12dcd86b
ED		 4040 spin_lock(&adapter->stats64_lock);
4041 igb_update_stats(adapter, &adapter->stats64);
4042 spin_unlock(&adapter->stats64_lock);
9d5c8243 4043
dbabb065 4044 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4045 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4046 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4047 /* We've lost link, so the controller stops DMA,
4048 * but we've got queued Tx work that's never going
4049 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4050 * (Do the reset outside of interrupt context).
4051 */
dbabb065
AD		 4052 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4053 adapter->tx_timeout_count++;
4054 schedule_work(&adapter->reset_task);
4055 /* return immediately since reset is imminent */
4056 return;
4057 }
9d5c8243 4058 }
9d5c8243 4059
dbabb065 4060 /* Force detection of hung controller every watchdog period */
6d095fa8 4061 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4062 }
f7ba205e 4063
b980ac18 4064 /* Cause software interrupt to ensure Rx ring is cleaned */
7a6ea550 4065 if (adapter->msix_entries) {
047e0030 4066 u32 eics = 0;
0d1ae7f4
AD		 4067 for (i = 0; i < adapter->num_q_vectors; i++)
4068 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4069 wr32(E1000_EICS, eics);
4070 } else {
4071 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4072 }
9d5c8243 4073
13800469 4074 igb_spoof_check(adapter);
fc580751 4075 igb_ptp_rx_hang(adapter);
13800469 4076
9d5c8243 4077 /* Reset the timer */
aa9b8cc4
AA		 4078 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4079 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4080 mod_timer(&adapter->watchdog_timer,
4081 round_jiffies(jiffies + HZ));
4082 else
4083 mod_timer(&adapter->watchdog_timer,
4084 round_jiffies(jiffies + 2 * HZ));
4085 }
9d5c8243
AK		 4086}
4087
4088enum latency_range {
4089 lowest_latency = 0,
4090 low_latency = 1,
4091 bulk_latency = 2,
4092 latency_invalid = 255
4093};
4094
6eb5a7f1 4095/**
b980ac18
JK		 4096 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4097 * @q_vector: pointer to q_vector
6eb5a7f1 4098 *
b980ac18
JK		 4099 * Stores a new ITR value based on strictly on packet size. This
4100 * algorithm is less sophisticated than that used in igb_update_itr,
4101 * due to the difficulty of synchronizing statistics across multiple
4102 * receive rings. The divisors and thresholds used by this function
4103 * were determined based on theoretical maximum wire speed and testing
4104 * data, in order to minimize response time while increasing bulk
4105 * throughput.
4106 * This functionality is controlled by the InterruptThrottleRate module
4107 * parameter (see igb_param.c)
4108 * NOTE: This function is called only when operating in a multiqueue
4109 * receive environment.
6eb5a7f1 4110 **/
047e0030 4111static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4112{
047e0030 4113 int new_val = q_vector->itr_val;
6eb5a7f1 4114 int avg_wire_size = 0;
047e0030 4115 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4116 unsigned int packets;
9d5c8243 4117
6eb5a7f1
AD		 4118 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4119 * ints/sec - ITR timer value of 120 ticks.
4120 */
4121 if (adapter->link_speed != SPEED_1000) {
0ba82994 4122 new_val = IGB_4K_ITR;
6eb5a7f1 4123 goto set_itr_val;
9d5c8243 4124 }
047e0030 4125
0ba82994
AD		 4126 packets = q_vector->rx.total_packets;
4127 if (packets)
4128 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4129
0ba82994
AD		 4130 packets = q_vector->tx.total_packets;
4131 if (packets)
4132 avg_wire_size = max_t(u32, avg_wire_size,
4133 q_vector->tx.total_bytes / packets);
047e0030
AD		 4134
4135 /* if avg_wire_size isn't set no work was done */
4136 if (!avg_wire_size)
4137 goto clear_counts;
9d5c8243 4138
6eb5a7f1
AD		 4139 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4140 avg_wire_size += 24;
4141
4142 /* Don't starve jumbo frames */
4143 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4144
6eb5a7f1
AD		 4145 /* Give a little boost to mid-size frames */
4146 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4147 new_val = avg_wire_size / 3;
4148 else
4149 new_val = avg_wire_size / 2;
9d5c8243 4150
0ba82994
AD		 4151 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4152 if (new_val < IGB_20K_ITR &&
4153 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4154 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4155 new_val = IGB_20K_ITR;
abe1c363 4156
6eb5a7f1 4157set_itr_val:
047e0030
AD		 4158 if (new_val != q_vector->itr_val) {
4159 q_vector->itr_val = new_val;
4160 q_vector->set_itr = 1;
9d5c8243 4161 }
6eb5a7f1 4162clear_counts:
0ba82994
AD		 4163 q_vector->rx.total_bytes = 0;
4164 q_vector->rx.total_packets = 0;
4165 q_vector->tx.total_bytes = 0;
4166 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4167}
4168
4169/**
b980ac18
JK		 4170 * igb_update_itr - update the dynamic ITR value based on statistics
4171 * @q_vector: pointer to q_vector
4172 * @ring_container: ring info to update the itr for
4173 *
4174 * Stores a new ITR value based on packets and byte
4175 * counts during the last interrupt. The advantage of per interrupt
4176 * computation is faster updates and more accurate ITR for the current
4177 * traffic pattern. Constants in this function were computed
4178 * based on theoretical maximum wire speed and thresholds were set based
4179 * on testing data as well as attempting to minimize response time
4180 * while increasing bulk throughput.
4181 * this functionality is controlled by the InterruptThrottleRate module
4182 * parameter (see igb_param.c)
4183 * NOTE: These calculations are only valid when operating in a single-
4184 * queue environment.
9d5c8243 4185 **/
0ba82994
AD		 4186static void igb_update_itr(struct igb_q_vector *q_vector,
4187 struct igb_ring_container *ring_container)
9d5c8243 4188{
0ba82994
AD		 4189 unsigned int packets = ring_container->total_packets;
4190 unsigned int bytes = ring_container->total_bytes;
4191 u8 itrval = ring_container->itr;
9d5c8243 4192
0ba82994 4193 /* no packets, exit with status unchanged */
9d5c8243 4194 if (packets == 0)
0ba82994 4195 return;
9d5c8243 4196
0ba82994 4197 switch (itrval) {
9d5c8243
AK		 4198 case lowest_latency:
4199 /* handle TSO and jumbo frames */
4200 if (bytes/packets > 8000)
0ba82994 4201 itrval = bulk_latency;
9d5c8243 4202 else if ((packets < 5) && (bytes > 512))
0ba82994 4203 itrval = low_latency;
9d5c8243
AK		 4204 break;
4205 case low_latency: /* 50 usec aka 20000 ints/s */
4206 if (bytes > 10000) {
4207 /* this if handles the TSO accounting */
4208 if (bytes/packets > 8000) {
0ba82994 4209 itrval = bulk_latency;
9d5c8243 4210 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4211 itrval = bulk_latency;
9d5c8243 4212 } else if ((packets > 35)) {
0ba82994 4213 itrval = lowest_latency;
9d5c8243
AK		 4214 }
4215 } else if (bytes/packets > 2000) {
0ba82994 4216 itrval = bulk_latency;
9d5c8243 4217 } else if (packets <= 2 && bytes < 512) {
0ba82994 4218 itrval = lowest_latency;
9d5c8243
AK		 4219 }
4220 break;
4221 case bulk_latency: /* 250 usec aka 4000 ints/s */
4222 if (bytes > 25000) {
4223 if (packets > 35)
0ba82994 4224 itrval = low_latency;
1e5c3d21 4225 } else if (bytes < 1500) {
0ba82994 4226 itrval = low_latency;
9d5c8243
AK		 4227 }
4228 break;
4229 }
4230
0ba82994
AD		 4231 /* clear work counters since we have the values we need */
4232 ring_container->total_bytes = 0;
4233 ring_container->total_packets = 0;
4234
4235 /* write updated itr to ring container */
4236 ring_container->itr = itrval;
9d5c8243
AK		 4237}
4238
0ba82994 4239static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4240{
0ba82994 4241 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4242 u32 new_itr = q_vector->itr_val;
0ba82994 4243 u8 current_itr = 0;
9d5c8243
AK		 4244
4245 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4246 if (adapter->link_speed != SPEED_1000) {
4247 current_itr = 0;
0ba82994 4248 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4249 goto set_itr_now;
4250 }
4251
0ba82994
AD		 4252 igb_update_itr(q_vector, &q_vector->tx);
4253 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4254
0ba82994 4255 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4256
6eb5a7f1 4257 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4258 if (current_itr == lowest_latency &&
4259 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4260 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4261 current_itr = low_latency;
4262
9d5c8243
AK		 4263 switch (current_itr) {
4264 /* counts and packets in update_itr are dependent on these numbers */
4265 case lowest_latency:
0ba82994 4266 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4267 break;
4268 case low_latency:
0ba82994 4269 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4270 break;
4271 case bulk_latency:
0ba82994 4272 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4273 break;
4274 default:
4275 break;
4276 }
4277
4278set_itr_now:
047e0030 4279 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4280 /* this attempts to bias the interrupt rate towards Bulk
4281 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4282 * increasing
4283 */
047e0030 4284 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4285 max((new_itr * q_vector->itr_val) /
4286 (new_itr + (q_vector->itr_val >> 2)),
4287 new_itr) : new_itr;
9d5c8243
AK		 4288 /* Don't write the value here; it resets the adapter's
4289 * internal timer, and causes us to delay far longer than
4290 * we should between interrupts. Instead, we write the ITR
4291 * value at the beginning of the next interrupt so the timing
4292 * ends up being correct.
4293 */
047e0030
AD		 4294 q_vector->itr_val = new_itr;
4295 q_vector->set_itr = 1;
9d5c8243 4296 }
9d5c8243
AK		 4297}
4298
c50b52a0
SH		 4299static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4300 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4301{
4302 struct e1000_adv_tx_context_desc *context_desc;
4303 u16 i = tx_ring->next_to_use;
4304
4305 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4306
4307 i++;
4308 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4309
4310 /* set bits to identify this as an advanced context descriptor */
4311 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4312
4313 /* For 82575, context index must be unique per ring. */
866cff06 4314 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4315 mss_l4len_idx |= tx_ring->reg_idx << 4;
4316
4317 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4318 context_desc->seqnum_seed = 0;
4319 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4320 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4321}
4322
7af40ad9
AD		 4323static int igb_tso(struct igb_ring *tx_ring,
4324 struct igb_tx_buffer *first,
4325 u8 *hdr_len)
9d5c8243 4326{
7af40ad9 4327 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4328 u32 vlan_macip_lens, type_tucmd;
4329 u32 mss_l4len_idx, l4len;
4330
ed6aa105
AD		 4331 if (skb->ip_summed != CHECKSUM_PARTIAL)
4332 return 0;
4333
7d13a7d0
AD		 4334 if (!skb_is_gso(skb))
4335 return 0;
9d5c8243
AK		 4336
4337 if (skb_header_cloned(skb)) {
7af40ad9 4338 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4339 if (err)
4340 return err;
4341 }
4342
7d13a7d0
AD		 4343 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4344 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4345
7af40ad9 4346 if (first->protocol == __constant_htons(ETH_P_IP)) {
9d5c8243
AK		 4347 struct iphdr *iph = ip_hdr(skb);
4348 iph->tot_len = 0;
4349 iph->check = 0;
4350 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4351 iph->daddr, 0,
4352 IPPROTO_TCP,
4353 0);
7d13a7d0 4354 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4355 first->tx_flags |= IGB_TX_FLAGS_TSO |
4356 IGB_TX_FLAGS_CSUM |
4357 IGB_TX_FLAGS_IPV4;
8e1e8a47 4358 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4359 ipv6_hdr(skb)->payload_len = 0;
4360 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4361 &ipv6_hdr(skb)->daddr,
4362 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4363 first->tx_flags |= IGB_TX_FLAGS_TSO |
4364 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4365 }
4366
7af40ad9 4367 /* compute header lengths */
7d13a7d0
AD		 4368 l4len = tcp_hdrlen(skb);
4369 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4370
7af40ad9
AD		 4371 /* update gso size and bytecount with header size */
4372 first->gso_segs = skb_shinfo(skb)->gso_segs;
4373 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4374
9d5c8243 4375 /* MSS L4LEN IDX */
7d13a7d0
AD		 4376 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4377 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4378
7d13a7d0
AD		 4379 /* VLAN MACLEN IPLEN */
4380 vlan_macip_lens = skb_network_header_len(skb);
4381 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4382 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4383
7d13a7d0 4384 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4385
7d13a7d0 4386 return 1;
9d5c8243
AK		 4387}
4388
7af40ad9 4389static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4390{
7af40ad9 4391 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4392 u32 vlan_macip_lens = 0;
4393 u32 mss_l4len_idx = 0;
4394 u32 type_tucmd = 0;
9d5c8243 4395
7d13a7d0 4396 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4397 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4398 return;
7d13a7d0
AD		 4399 } else {
4400 u8 l4_hdr = 0;
7af40ad9 4401 switch (first->protocol) {
7d13a7d0
AD		 4402 case __constant_htons(ETH_P_IP):
4403 vlan_macip_lens |= skb_network_header_len(skb);
4404 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4405 l4_hdr = ip_hdr(skb)->protocol;
4406 break;
4407 case __constant_htons(ETH_P_IPV6):
4408 vlan_macip_lens |= skb_network_header_len(skb);
4409 l4_hdr = ipv6_hdr(skb)->nexthdr;
4410 break;
4411 default:
4412 if (unlikely(net_ratelimit())) {
4413 dev_warn(tx_ring->dev,
b980ac18
JK		 4414 "partial checksum but proto=%x!\n",
4415 first->protocol);
fa4a7ef3 4416 }
7d13a7d0
AD		 4417 break;
4418 }
fa4a7ef3 4419
7d13a7d0
AD		 4420 switch (l4_hdr) {
4421 case IPPROTO_TCP:
4422 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4423 mss_l4len_idx = tcp_hdrlen(skb) <<
4424 E1000_ADVTXD_L4LEN_SHIFT;
4425 break;
4426 case IPPROTO_SCTP:
4427 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4428 mss_l4len_idx = sizeof(struct sctphdr) <<
4429 E1000_ADVTXD_L4LEN_SHIFT;
4430 break;
4431 case IPPROTO_UDP:
4432 mss_l4len_idx = sizeof(struct udphdr) <<
4433 E1000_ADVTXD_L4LEN_SHIFT;
4434 break;
4435 default:
4436 if (unlikely(net_ratelimit())) {
4437 dev_warn(tx_ring->dev,
b980ac18
JK		 4438 "partial checksum but l4 proto=%x!\n",
4439 l4_hdr);
44b0cda3 4440 }
7d13a7d0 4441 break;
9d5c8243 4442 }
7af40ad9
AD		 4443
4444 /* update TX checksum flag */
4445 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4446 }
9d5c8243 4447
7d13a7d0 4448 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4449 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4450
7d13a7d0 4451 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4452}
4453
1d9daf45
AD		 4454#define IGB_SET_FLAG(_input, _flag, _result) \
4455 ((_flag <= _result) ? \
4456 ((u32)(_input & _flag) * (_result / _flag)) : \
4457 ((u32)(_input & _flag) / (_flag / _result)))
4458
4459static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4460{
4461 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4462 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4463 E1000_ADVTXD_DCMD_DEXT |
4464 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4465
4466 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4467 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4468 (E1000_ADVTXD_DCMD_VLE));
4469
4470 /* set segmentation bits for TSO */
4471 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4472 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4473
4474 /* set timestamp bit if present */
1d9daf45
AD		 4475 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4476 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4477
1d9daf45
AD		 4478 /* insert frame checksum */
4479 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4480
4481 return cmd_type;
4482}
4483
7af40ad9
AD		 4484static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4485 union e1000_adv_tx_desc *tx_desc,
4486 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4487{
4488 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4489
1d9daf45
AD		 4490 /* 82575 requires a unique index per ring */
4491 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4492 olinfo_status |= tx_ring->reg_idx << 4;
4493
4494 /* insert L4 checksum */
1d9daf45
AD		 4495 olinfo_status |= IGB_SET_FLAG(tx_flags,
4496 IGB_TX_FLAGS_CSUM,
4497 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4498
1d9daf45
AD		 4499 /* insert IPv4 checksum */
4500 olinfo_status |= IGB_SET_FLAG(tx_flags,
4501 IGB_TX_FLAGS_IPV4,
4502 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4503
7af40ad9 4504 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4505}
4506
7af40ad9
AD		 4507static void igb_tx_map(struct igb_ring *tx_ring,
4508 struct igb_tx_buffer *first,
ebe42d16 4509 const u8 hdr_len)
9d5c8243 4510{
7af40ad9 4511 struct sk_buff *skb = first->skb;
c9f14bf3 4512 struct igb_tx_buffer *tx_buffer;
ebe42d16 4513 union e1000_adv_tx_desc *tx_desc;
80d0759e 4514 struct skb_frag_struct *frag;
ebe42d16 4515 dma_addr_t dma;
80d0759e 4516 unsigned int data_len, size;
7af40ad9 4517 u32 tx_flags = first->tx_flags;
1d9daf45 4518 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4519 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4520
4521 tx_desc = IGB_TX_DESC(tx_ring, i);
4522
80d0759e
AD		 4523 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4524
4525 size = skb_headlen(skb);
4526 data_len = skb->data_len;
ebe42d16
AD		 4527
4528 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4529
80d0759e
AD		 4530 tx_buffer = first;
4531
4532 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4533 if (dma_mapping_error(tx_ring->dev, dma))
4534 goto dma_error;
4535
4536 /* record length, and DMA address */
4537 dma_unmap_len_set(tx_buffer, len, size);
4538 dma_unmap_addr_set(tx_buffer, dma, dma);
4539
4540 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4541
ebe42d16
AD		 4542 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4543 tx_desc->read.cmd_type_len =
1d9daf45 4544 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4545
4546 i++;
4547 tx_desc++;
4548 if (i == tx_ring->count) {
4549 tx_desc = IGB_TX_DESC(tx_ring, 0);
4550 i = 0;
4551 }
80d0759e 4552 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4553
4554 dma += IGB_MAX_DATA_PER_TXD;
4555 size -= IGB_MAX_DATA_PER_TXD;
4556
ebe42d16
AD		 4557 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4558 }
4559
4560 if (likely(!data_len))
4561 break;
2bbfebe2 4562
1d9daf45 4563 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4564
65689fef 4565 i++;
ebe42d16
AD		 4566 tx_desc++;
4567 if (i == tx_ring->count) {
4568 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4569 i = 0;
ebe42d16 4570 }
80d0759e 4571 tx_desc->read.olinfo_status = 0;
65689fef 4572
9e903e08 4573 size = skb_frag_size(frag);
ebe42d16
AD		 4574 data_len -= size;
4575
4576 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4577 size, DMA_TO_DEVICE);
6366ad33 4578
c9f14bf3 4579 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4580 }
4581
ebe42d16 4582 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4583 cmd_type |= size | IGB_TXD_DCMD;
4584 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4585
80d0759e
AD		 4586 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4587
8542db05
AD		 4588 /* set the timestamp */
4589 first->time_stamp = jiffies;
4590
b980ac18 4591 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4592 * are new descriptors to fetch. (Only applicable for weak-ordered
4593 * memory model archs, such as IA-64).
4594 *
4595 * We also need this memory barrier to make certain all of the
4596 * status bits have been updated before next_to_watch is written.
4597 */
4598 wmb();
4599
8542db05 4600 /* set next_to_watch value indicating a packet is present */
ebe42d16 4601 first->next_to_watch = tx_desc;
9d5c8243 4602
ebe42d16
AD		 4603 i++;
4604 if (i == tx_ring->count)
4605 i = 0;
6366ad33 4606
ebe42d16 4607 tx_ring->next_to_use = i;
6366ad33 4608
ebe42d16 4609 writel(i, tx_ring->tail);
6366ad33 4610
ebe42d16 4611 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4612 * at a time, it synchronizes IO on IA64/Altix systems
4613 */
ebe42d16
AD		 4614 mmiowb();
4615
4616 return;
4617
4618dma_error:
4619 dev_err(tx_ring->dev, "TX DMA map failed\n");
4620
4621 /* clear dma mappings for failed tx_buffer_info map */
4622 for (;;) {
c9f14bf3
AD		 4623 tx_buffer = &tx_ring->tx_buffer_info[i];
4624 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4625 if (tx_buffer == first)
ebe42d16 4626 break;
a77ff709
NN		 4627 if (i == 0)
4628 i = tx_ring->count;
6366ad33 4629 i--;
6366ad33
AD		 4630 }
4631
9d5c8243 4632 tx_ring->next_to_use = i;
9d5c8243
AK		 4633}
4634
6ad4edfc 4635static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4636{
e694e964
AD		 4637 struct net_device *netdev = tx_ring->netdev;
4638
661086df 4639 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4640
9d5c8243
AK		 4641 /* Herbert's original patch had:
4642 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4643 * but since that doesn't exist yet, just open code it.
4644 */
9d5c8243
AK		 4645 smp_mb();
4646
4647 /* We need to check again in a case another CPU has just
b980ac18
JK		 4648 * made room available.
4649 */
c493ea45 4650 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4651 return -EBUSY;
4652
4653 /* A reprieve! */
661086df 4654 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4655
4656 u64_stats_update_begin(&tx_ring->tx_syncp2);
4657 tx_ring->tx_stats.restart_queue2++;
4658 u64_stats_update_end(&tx_ring->tx_syncp2);
4659
9d5c8243
AK		 4660 return 0;
4661}
4662
6ad4edfc 4663static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4664{
c493ea45 4665 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4666 return 0;
e694e964 4667 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4668}
4669
cd392f5c
AD		 4670netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4671 struct igb_ring *tx_ring)
9d5c8243 4672{
8542db05 4673 struct igb_tx_buffer *first;
ebe42d16 4674 int tso;
91d4ee33 4675 u32 tx_flags = 0;
21ba6fe1 4676 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4677 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4678 u8 hdr_len = 0;
9d5c8243 4679
21ba6fe1
AD		 4680 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4681 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4682 * + 2 desc gap to keep tail from touching head,
9d5c8243 4683 * + 1 desc for context descriptor,
21ba6fe1
AD		 4684 * otherwise try next time
4685 */
4686 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4687 unsigned short f;
4688 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4689 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4690 } else {
4691 count += skb_shinfo(skb)->nr_frags;
4692 }
4693
4694 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4695 /* this is a hard error */
9d5c8243
AK		 4696 return NETDEV_TX_BUSY;
4697 }
33af6bcc 4698
7af40ad9
AD		 4699 /* record the location of the first descriptor for this packet */
4700 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4701 first->skb = skb;
4702 first->bytecount = skb->len;
4703 first->gso_segs = 1;
4704
b66e2397
MV		 4705 skb_tx_timestamp(skb);
4706
b646c22e
AD		 4707 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4708 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4709
b646c22e
AD		 4710 if (!(adapter->ptp_tx_skb)) {
4711 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4712 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4713
4714 adapter->ptp_tx_skb = skb_get(skb);
4715 adapter->ptp_tx_start = jiffies;
4716 if (adapter->hw.mac.type == e1000_82576)
4717 schedule_work(&adapter->ptp_tx_work);
4718 }
33af6bcc 4719 }
9d5c8243 4720
eab6d18d 4721 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4722 tx_flags |= IGB_TX_FLAGS_VLAN;
4723 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4724 }
4725
7af40ad9
AD		 4726 /* record initial flags and protocol */
4727 first->tx_flags = tx_flags;
4728 first->protocol = protocol;
cdfd01fc 4729
7af40ad9
AD		 4730 tso = igb_tso(tx_ring, first, &hdr_len);
4731 if (tso < 0)
7d13a7d0 4732 goto out_drop;
7af40ad9
AD		 4733 else if (!tso)
4734 igb_tx_csum(tx_ring, first);
9d5c8243 4735
7af40ad9 4736 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 4737
4738 /* Make sure there is space in the ring for the next send. */
21ba6fe1 4739 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 4740
9d5c8243 4741 return NETDEV_TX_OK;
7d13a7d0
AD		 4742
4743out_drop:
7af40ad9
AD		 4744 igb_unmap_and_free_tx_resource(tx_ring, first);
4745
7d13a7d0 4746 return NETDEV_TX_OK;
9d5c8243
AK		 4747}
4748
1cc3bd87
AD		 4749static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4750 struct sk_buff *skb)
4751{
4752 unsigned int r_idx = skb->queue_mapping;
4753
4754 if (r_idx >= adapter->num_tx_queues)
4755 r_idx = r_idx % adapter->num_tx_queues;
4756
4757 return adapter->tx_ring[r_idx];
4758}
4759
cd392f5c
AD		 4760static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4761 struct net_device *netdev)
9d5c8243
AK		 4762{
4763 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 4764
4765 if (test_bit(__IGB_DOWN, &adapter->state)) {
4766 dev_kfree_skb_any(skb);
4767 return NETDEV_TX_OK;
4768 }
4769
4770 if (skb->len <= 0) {
4771 dev_kfree_skb_any(skb);
4772 return NETDEV_TX_OK;
4773 }
4774
b980ac18 4775 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 4776 * in order to meet this minimum size requirement.
4777 */
ea5ceeab
TD		 4778 if (unlikely(skb->len < 17)) {
4779 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 4780 return NETDEV_TX_OK;
4781 skb->len = 17;
ea5ceeab 4782 skb_set_tail_pointer(skb, 17);
1cc3bd87 4783 }
9d5c8243 4784
1cc3bd87 4785 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 4786}
4787
4788/**
b980ac18
JK		 4789 * igb_tx_timeout - Respond to a Tx Hang
4790 * @netdev: network interface device structure
9d5c8243
AK		 4791 **/
4792static void igb_tx_timeout(struct net_device *netdev)
4793{
4794 struct igb_adapter *adapter = netdev_priv(netdev);
4795 struct e1000_hw *hw = &adapter->hw;
4796
4797 /* Do the reset outside of interrupt context */
4798 adapter->tx_timeout_count++;
f7ba205e 4799
06218a8d 4800 if (hw->mac.type >= e1000_82580)
55cac248
AD		 4801 hw->dev_spec._82575.global_device_reset = true;
4802
9d5c8243 4803 schedule_work(&adapter->reset_task);
265de409
AD		 4804 wr32(E1000_EICS,
4805 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 4806}
4807
4808static void igb_reset_task(struct work_struct *work)
4809{
4810 struct igb_adapter *adapter;
4811 adapter = container_of(work, struct igb_adapter, reset_task);
4812
c97ec42a
TI		 4813 igb_dump(adapter);
4814 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 4815 igb_reinit_locked(adapter);
4816}
4817
4818/**
b980ac18
JK		 4819 * igb_get_stats64 - Get System Network Statistics
4820 * @netdev: network interface device structure
4821 * @stats: rtnl_link_stats64 pointer
9d5c8243 4822 **/
12dcd86b 4823static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 4824 struct rtnl_link_stats64 *stats)
9d5c8243 4825{
12dcd86b
ED		 4826 struct igb_adapter *adapter = netdev_priv(netdev);
4827
4828 spin_lock(&adapter->stats64_lock);
4829 igb_update_stats(adapter, &adapter->stats64);
4830 memcpy(stats, &adapter->stats64, sizeof(*stats));
4831 spin_unlock(&adapter->stats64_lock);
4832
4833 return stats;
9d5c8243
AK		 4834}
4835
4836/**
b980ac18
JK		 4837 * igb_change_mtu - Change the Maximum Transfer Unit
4838 * @netdev: network interface device structure
4839 * @new_mtu: new value for maximum frame size
9d5c8243 4840 *
b980ac18 4841 * Returns 0 on success, negative on failure
9d5c8243
AK		 4842 **/
4843static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4844{
4845 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 4846 struct pci_dev *pdev = adapter->pdev;
153285f9 4847 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 4848
c809d227 4849 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 4850 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 4851 return -EINVAL;
4852 }
4853
153285f9 4854#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 4855 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 4856 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 4857 return -EINVAL;
4858 }
4859
2ccd994c
AD		 4860 /* adjust max frame to be at least the size of a standard frame */
4861 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4862 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
4863
9d5c8243
AK		 4864 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4865 msleep(1);
73cd78f1 4866
9d5c8243
AK		 4867 /* igb_down has a dependency on max_frame_size */
4868 adapter->max_frame_size = max_frame;
559e9c49 4869
4c844851
AD		 4870 if (netif_running(netdev))
4871 igb_down(adapter);
9d5c8243 4872
090b1795 4873 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 4874 netdev->mtu, new_mtu);
4875 netdev->mtu = new_mtu;
4876
4877 if (netif_running(netdev))
4878 igb_up(adapter);
4879 else
4880 igb_reset(adapter);
4881
4882 clear_bit(__IGB_RESETTING, &adapter->state);
4883
4884 return 0;
4885}
4886
4887/**
b980ac18
JK		 4888 * igb_update_stats - Update the board statistics counters
4889 * @adapter: board private structure
9d5c8243 4890 **/
12dcd86b
ED		 4891void igb_update_stats(struct igb_adapter *adapter,
4892 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 4893{
4894 struct e1000_hw *hw = &adapter->hw;
4895 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 4896 u32 reg, mpc;
9d5c8243 4897 u16 phy_tmp;
3f9c0164
AD		 4898 int i;
4899 u64 bytes, packets;
12dcd86b
ED		 4900 unsigned int start;
4901 u64 _bytes, _packets;
9d5c8243
AK		 4902
4903#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4904
b980ac18 4905 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 4906 * connection is down.
4907 */
4908 if (adapter->link_speed == 0)
4909 return;
4910 if (pci_channel_offline(pdev))
4911 return;
4912
3f9c0164
AD		 4913 bytes = 0;
4914 packets = 0;
7f90128e
AA		 4915
4916 rcu_read_lock();
3f9c0164 4917 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 4918 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 4919 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 4920
ae1c07a6
AD		 4921 if (rqdpc) {
4922 ring->rx_stats.drops += rqdpc;
4923 net_stats->rx_fifo_errors += rqdpc;
4924 }
12dcd86b
ED		 4925
4926 do {
4927 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4928 _bytes = ring->rx_stats.bytes;
4929 _packets = ring->rx_stats.packets;
4930 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4931 bytes += _bytes;
4932 packets += _packets;
3f9c0164
AD		 4933 }
4934
128e45eb
AD		 4935 net_stats->rx_bytes = bytes;
4936 net_stats->rx_packets = packets;
3f9c0164
AD		 4937
4938 bytes = 0;
4939 packets = 0;
4940 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4941 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b
ED		 4942 do {
4943 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4944 _bytes = ring->tx_stats.bytes;
4945 _packets = ring->tx_stats.packets;
4946 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4947 bytes += _bytes;
4948 packets += _packets;
3f9c0164 4949 }
128e45eb
AD		 4950 net_stats->tx_bytes = bytes;
4951 net_stats->tx_packets = packets;
7f90128e 4952 rcu_read_unlock();
3f9c0164
AD		 4953
4954 /* read stats registers */
9d5c8243
AK		 4955 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4956 adapter->stats.gprc += rd32(E1000_GPRC);
4957 adapter->stats.gorc += rd32(E1000_GORCL);
4958 rd32(E1000_GORCH); /* clear GORCL */
4959 adapter->stats.bprc += rd32(E1000_BPRC);
4960 adapter->stats.mprc += rd32(E1000_MPRC);
4961 adapter->stats.roc += rd32(E1000_ROC);
4962
4963 adapter->stats.prc64 += rd32(E1000_PRC64);
4964 adapter->stats.prc127 += rd32(E1000_PRC127);
4965 adapter->stats.prc255 += rd32(E1000_PRC255);
4966 adapter->stats.prc511 += rd32(E1000_PRC511);
4967 adapter->stats.prc1023 += rd32(E1000_PRC1023);
4968 adapter->stats.prc1522 += rd32(E1000_PRC1522);
4969 adapter->stats.symerrs += rd32(E1000_SYMERRS);
4970 adapter->stats.sec += rd32(E1000_SEC);
4971
fa3d9a6d
MW		 4972 mpc = rd32(E1000_MPC);
4973 adapter->stats.mpc += mpc;
4974 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 4975 adapter->stats.scc += rd32(E1000_SCC);
4976 adapter->stats.ecol += rd32(E1000_ECOL);
4977 adapter->stats.mcc += rd32(E1000_MCC);
4978 adapter->stats.latecol += rd32(E1000_LATECOL);
4979 adapter->stats.dc += rd32(E1000_DC);
4980 adapter->stats.rlec += rd32(E1000_RLEC);
4981 adapter->stats.xonrxc += rd32(E1000_XONRXC);
4982 adapter->stats.xontxc += rd32(E1000_XONTXC);
4983 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4984 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4985 adapter->stats.fcruc += rd32(E1000_FCRUC);
4986 adapter->stats.gptc += rd32(E1000_GPTC);
4987 adapter->stats.gotc += rd32(E1000_GOTCL);
4988 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 4989 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 4990 adapter->stats.ruc += rd32(E1000_RUC);
4991 adapter->stats.rfc += rd32(E1000_RFC);
4992 adapter->stats.rjc += rd32(E1000_RJC);
4993 adapter->stats.tor += rd32(E1000_TORH);
4994 adapter->stats.tot += rd32(E1000_TOTH);
4995 adapter->stats.tpr += rd32(E1000_TPR);
4996
4997 adapter->stats.ptc64 += rd32(E1000_PTC64);
4998 adapter->stats.ptc127 += rd32(E1000_PTC127);
4999 adapter->stats.ptc255 += rd32(E1000_PTC255);
5000 adapter->stats.ptc511 += rd32(E1000_PTC511);
5001 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5002 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5003
5004 adapter->stats.mptc += rd32(E1000_MPTC);
5005 adapter->stats.bptc += rd32(E1000_BPTC);
5006
2d0b0f69
NN		 5007 adapter->stats.tpt += rd32(E1000_TPT);
5008 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5009
5010 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5011 /* read internal phy specific stats */
5012 reg = rd32(E1000_CTRL_EXT);
5013 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5014 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5015
5016 /* this stat has invalid values on i210/i211 */
5017 if ((hw->mac.type != e1000_i210) &&
5018 (hw->mac.type != e1000_i211))
5019 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5020 }
5021
9d5c8243
AK		 5022 adapter->stats.tsctc += rd32(E1000_TSCTC);
5023 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5024
5025 adapter->stats.iac += rd32(E1000_IAC);
5026 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5027 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5028 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5029 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5030 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5031 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5032 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5033 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5034
5035 /* Fill out the OS statistics structure */
128e45eb
AD		 5036 net_stats->multicast = adapter->stats.mprc;
5037 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5038
5039 /* Rx Errors */
5040
5041 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5042 * our own version based on RUC and ROC
5043 */
128e45eb 5044 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5045 adapter->stats.crcerrs + adapter->stats.algnerrc +
5046 adapter->stats.ruc + adapter->stats.roc +
5047 adapter->stats.cexterr;
128e45eb
AD		 5048 net_stats->rx_length_errors = adapter->stats.ruc +
5049 adapter->stats.roc;
5050 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5051 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5052 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5053
5054 /* Tx Errors */
128e45eb
AD		 5055 net_stats->tx_errors = adapter->stats.ecol +
5056 adapter->stats.latecol;
5057 net_stats->tx_aborted_errors = adapter->stats.ecol;
5058 net_stats->tx_window_errors = adapter->stats.latecol;
5059 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5060
5061 /* Tx Dropped needs to be maintained elsewhere */
5062
5063 /* Phy Stats */
5064 if (hw->phy.media_type == e1000_media_type_copper) {
5065 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5066 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5067 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5068 adapter->phy_stats.idle_errors += phy_tmp;
5069 }
5070 }
5071
5072 /* Management Stats */
5073 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5074 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5075 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5076
5077 /* OS2BMC Stats */
5078 reg = rd32(E1000_MANC);
5079 if (reg & E1000_MANC_EN_BMC2OS) {
5080 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5081 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5082 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5083 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5084 }
9d5c8243
AK		 5085}
5086
9d5c8243
AK		 5087static irqreturn_t igb_msix_other(int irq, void *data)
5088{
047e0030 5089 struct igb_adapter *adapter = data;
9d5c8243 5090 struct e1000_hw *hw = &adapter->hw;
844290e5 5091 u32 icr = rd32(E1000_ICR);
844290e5 5092 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5093
7f081d40
AD		 5094 if (icr & E1000_ICR_DRSTA)
5095 schedule_work(&adapter->reset_task);
5096
047e0030 5097 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5098 /* HW is reporting DMA is out of sync */
5099 adapter->stats.doosync++;
13800469
GR		 5100 /* The DMA Out of Sync is also indication of a spoof event
5101 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5102 * see if it is really a spoof event.
5103 */
13800469 5104 igb_check_wvbr(adapter);
dda0e083 5105 }
eebbbdba 5106
4ae196df
AD		 5107 /* Check for a mailbox event */
5108 if (icr & E1000_ICR_VMMB)
5109 igb_msg_task(adapter);
5110
5111 if (icr & E1000_ICR_LSC) {
5112 hw->mac.get_link_status = 1;
5113 /* guard against interrupt when we're going down */
5114 if (!test_bit(__IGB_DOWN, &adapter->state))
5115 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5116 }
5117
1f6e8178
MV		 5118 if (icr & E1000_ICR_TS) {
5119 u32 tsicr = rd32(E1000_TSICR);
5120
5121 if (tsicr & E1000_TSICR_TXTS) {
5122 /* acknowledge the interrupt */
5123 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5124 /* retrieve hardware timestamp */
5125 schedule_work(&adapter->ptp_tx_work);
5126 }
5127 }
1f6e8178 5128
844290e5 5129 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5130
5131 return IRQ_HANDLED;
5132}
5133
047e0030 5134static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5135{
26b39276 5136 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5137 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5138
047e0030
AD		 5139 if (!q_vector->set_itr)
5140 return;
73cd78f1 5141
047e0030
AD		 5142 if (!itr_val)
5143 itr_val = 0x4;
661086df 5144
26b39276
AD		 5145 if (adapter->hw.mac.type == e1000_82575)
5146 itr_val |= itr_val << 16;
661086df 5147 else
0ba82994 5148 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5149
047e0030
AD		 5150 writel(itr_val, q_vector->itr_register);
5151 q_vector->set_itr = 0;
6eb5a7f1
AD		 5152}
5153
047e0030 5154static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5155{
047e0030 5156 struct igb_q_vector *q_vector = data;
9d5c8243 5157
047e0030
AD		 5158 /* Write the ITR value calculated from the previous interrupt. */
5159 igb_write_itr(q_vector);
9d5c8243 5160
047e0030 5161 napi_schedule(&q_vector->napi);
844290e5 5162
047e0030 5163 return IRQ_HANDLED;
fe4506b6
JC		 5164}
5165
421e02f0 5166#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5167static void igb_update_tx_dca(struct igb_adapter *adapter,
5168 struct igb_ring *tx_ring,
5169 int cpu)
5170{
5171 struct e1000_hw *hw = &adapter->hw;
5172 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5173
5174 if (hw->mac.type != e1000_82575)
5175 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5176
b980ac18 5177 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5178 * DCA is enabled. This is due to a known issue in some chipsets
5179 * which will cause the DCA tag to be cleared.
5180 */
5181 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5182 E1000_DCA_TXCTRL_DATA_RRO_EN |
5183 E1000_DCA_TXCTRL_DESC_DCA_EN;
5184
5185 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5186}
5187
5188static void igb_update_rx_dca(struct igb_adapter *adapter,
5189 struct igb_ring *rx_ring,
5190 int cpu)
5191{
5192 struct e1000_hw *hw = &adapter->hw;
5193 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5194
5195 if (hw->mac.type != e1000_82575)
5196 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5197
b980ac18 5198 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5199 * DCA is enabled. This is due to a known issue in some chipsets
5200 * which will cause the DCA tag to be cleared.
5201 */
5202 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5203 E1000_DCA_RXCTRL_DESC_DCA_EN;
5204
5205 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5206}
5207
047e0030 5208static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5209{
047e0030 5210 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5211 int cpu = get_cpu();
fe4506b6 5212
047e0030
AD		 5213 if (q_vector->cpu == cpu)
5214 goto out_no_update;
5215
6a05004a
AD		 5216 if (q_vector->tx.ring)
5217 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5218
5219 if (q_vector->rx.ring)
5220 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5221
047e0030
AD		 5222 q_vector->cpu = cpu;
5223out_no_update:
fe4506b6
JC		 5224 put_cpu();
5225}
5226
5227static void igb_setup_dca(struct igb_adapter *adapter)
5228{
7e0e99ef 5229 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5230 int i;
5231
7dfc16fa 5232 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5233 return;
5234
7e0e99ef
AD		 5235 /* Always use CB2 mode, difference is masked in the CB driver. */
5236 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5237
047e0030 5238 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5239 adapter->q_vector[i]->cpu = -1;
5240 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5241 }
5242}
5243
5244static int __igb_notify_dca(struct device *dev, void *data)
5245{
5246 struct net_device *netdev = dev_get_drvdata(dev);
5247 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5248 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5249 struct e1000_hw *hw = &adapter->hw;
5250 unsigned long event = *(unsigned long *)data;
5251
5252 switch (event) {
5253 case DCA_PROVIDER_ADD:
5254 /* if already enabled, don't do it again */
7dfc16fa 5255 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5256 break;
fe4506b6 5257 if (dca_add_requester(dev) == 0) {
bbd98fe4 5258 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5259 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5260 igb_setup_dca(adapter);
5261 break;
5262 }
5263 /* Fall Through since DCA is disabled. */
5264 case DCA_PROVIDER_REMOVE:
7dfc16fa 5265 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5266 /* without this a class_device is left
b980ac18
JK		 5267 * hanging around in the sysfs model
5268 */
fe4506b6 5269 dca_remove_requester(dev);
090b1795 5270 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5271 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5272 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5273 }
5274 break;
5275 }
bbd98fe4 5276
fe4506b6 5277 return 0;
9d5c8243
AK		 5278}
5279
fe4506b6 5280static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5281 void *p)
fe4506b6
JC		 5282{
5283 int ret_val;
5284
5285 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5286 __igb_notify_dca);
fe4506b6
JC		 5287
5288 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5289}
421e02f0 5290#endif /* CONFIG_IGB_DCA */
9d5c8243 5291
0224d663
GR		 5292#ifdef CONFIG_PCI_IOV
5293static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5294{
5295 unsigned char mac_addr[ETH_ALEN];
0224d663 5296
5ac6f91d 5297 eth_zero_addr(mac_addr);
0224d663
GR		 5298 igb_set_vf_mac(adapter, vf, mac_addr);
5299
70ea4783
LL		 5300 /* By default spoof check is enabled for all VFs */
5301 adapter->vf_data[vf].spoofchk_enabled = true;
5302
f557147c 5303 return 0;
0224d663
GR		 5304}
5305
0224d663 5306#endif
4ae196df
AD		 5307static void igb_ping_all_vfs(struct igb_adapter *adapter)
5308{
5309 struct e1000_hw *hw = &adapter->hw;
5310 u32 ping;
5311 int i;
5312
5313 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5314 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5315 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5316 ping |= E1000_VT_MSGTYPE_CTS;
5317 igb_write_mbx(hw, &ping, 1, i);
5318 }
5319}
5320
7d5753f0
AD		 5321static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5322{
5323 struct e1000_hw *hw = &adapter->hw;
5324 u32 vmolr = rd32(E1000_VMOLR(vf));
5325 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5326
d85b9004 5327 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5328 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5329 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5330
5331 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5332 vmolr |= E1000_VMOLR_MPME;
d85b9004 5333 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5334 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5335 } else {
b980ac18 5336 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5337 * flag we need to write the hashes to the MTA as this step
5338 * was previously skipped
5339 */
5340 if (vf_data->num_vf_mc_hashes > 30) {
5341 vmolr |= E1000_VMOLR_MPME;
5342 } else if (vf_data->num_vf_mc_hashes) {
5343 int j;
5344 vmolr |= E1000_VMOLR_ROMPE;
5345 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5346 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5347 }
5348 }
5349
5350 wr32(E1000_VMOLR(vf), vmolr);
5351
5352 /* there are flags left unprocessed, likely not supported */
5353 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5354 return -EINVAL;
5355
5356 return 0;
7d5753f0
AD		 5357}
5358
4ae196df
AD		 5359static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5360 u32 *msgbuf, u32 vf)
5361{
5362 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5363 u16 *hash_list = (u16 *)&msgbuf[1];
5364 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5365 int i;
5366
7d5753f0 5367 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5368 * to this VF for later use to restore when the PF multi cast
5369 * list changes
5370 */
5371 vf_data->num_vf_mc_hashes = n;
5372
7d5753f0
AD		 5373 /* only up to 30 hash values supported */
5374 if (n > 30)
5375 n = 30;
5376
5377 /* store the hashes for later use */
4ae196df 5378 for (i = 0; i < n; i++)
a419aef8 5379 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5380
5381 /* Flush and reset the mta with the new values */
ff41f8dc 5382 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5383
5384 return 0;
5385}
5386
5387static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5388{
5389 struct e1000_hw *hw = &adapter->hw;
5390 struct vf_data_storage *vf_data;
5391 int i, j;
5392
5393 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5394 u32 vmolr = rd32(E1000_VMOLR(i));
5395 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5396
4ae196df 5397 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5398
5399 if ((vf_data->num_vf_mc_hashes > 30) ||
5400 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5401 vmolr |= E1000_VMOLR_MPME;
5402 } else if (vf_data->num_vf_mc_hashes) {
5403 vmolr |= E1000_VMOLR_ROMPE;
5404 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5405 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5406 }
5407 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5408 }
5409}
5410
5411static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5412{
5413 struct e1000_hw *hw = &adapter->hw;
5414 u32 pool_mask, reg, vid;
5415 int i;
5416
5417 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5418
5419 /* Find the vlan filter for this id */
5420 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5421 reg = rd32(E1000_VLVF(i));
5422
5423 /* remove the vf from the pool */
5424 reg &= ~pool_mask;
5425
5426 /* if pool is empty then remove entry from vfta */
5427 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5428 (reg & E1000_VLVF_VLANID_ENABLE)) {
5429 reg = 0;
5430 vid = reg & E1000_VLVF_VLANID_MASK;
5431 igb_vfta_set(hw, vid, false);
5432 }
5433
5434 wr32(E1000_VLVF(i), reg);
5435 }
ae641bdc
AD		 5436
5437 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5438}
5439
5440static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5441{
5442 struct e1000_hw *hw = &adapter->hw;
5443 u32 reg, i;
5444
51466239
AD		 5445 /* The vlvf table only exists on 82576 hardware and newer */
5446 if (hw->mac.type < e1000_82576)
5447 return -1;
5448
5449 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5450 if (!adapter->vfs_allocated_count)
5451 return -1;
5452
5453 /* Find the vlan filter for this id */
5454 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5455 reg = rd32(E1000_VLVF(i));
5456 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5457 vid == (reg & E1000_VLVF_VLANID_MASK))
5458 break;
5459 }
5460
5461 if (add) {
5462 if (i == E1000_VLVF_ARRAY_SIZE) {
5463 /* Did not find a matching VLAN ID entry that was
5464 * enabled. Search for a free filter entry, i.e.
5465 * one without the enable bit set
5466 */
5467 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5468 reg = rd32(E1000_VLVF(i));
5469 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5470 break;
5471 }
5472 }
5473 if (i < E1000_VLVF_ARRAY_SIZE) {
5474 /* Found an enabled/available entry */
5475 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5476
5477 /* if !enabled we need to set this up in vfta */
5478 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5479 /* add VID to filter table */
5480 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5481 reg |= E1000_VLVF_VLANID_ENABLE;
5482 }
cad6d05f
AD		 5483 reg &= ~E1000_VLVF_VLANID_MASK;
5484 reg |= vid;
4ae196df 5485 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5486
5487 /* do not modify RLPML for PF devices */
5488 if (vf >= adapter->vfs_allocated_count)
5489 return 0;
5490
5491 if (!adapter->vf_data[vf].vlans_enabled) {
5492 u32 size;
5493 reg = rd32(E1000_VMOLR(vf));
5494 size = reg & E1000_VMOLR_RLPML_MASK;
5495 size += 4;
5496 reg &= ~E1000_VMOLR_RLPML_MASK;
5497 reg |= size;
5498 wr32(E1000_VMOLR(vf), reg);
5499 }
ae641bdc 5500
51466239 5501 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5502 }
5503 } else {
5504 if (i < E1000_VLVF_ARRAY_SIZE) {
5505 /* remove vf from the pool */
5506 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5507 /* if pool is empty then remove entry from vfta */
5508 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5509 reg = 0;
5510 igb_vfta_set(hw, vid, false);
5511 }
5512 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5513
5514 /* do not modify RLPML for PF devices */
5515 if (vf >= adapter->vfs_allocated_count)
5516 return 0;
5517
5518 adapter->vf_data[vf].vlans_enabled--;
5519 if (!adapter->vf_data[vf].vlans_enabled) {
5520 u32 size;
5521 reg = rd32(E1000_VMOLR(vf));
5522 size = reg & E1000_VMOLR_RLPML_MASK;
5523 size -= 4;
5524 reg &= ~E1000_VMOLR_RLPML_MASK;
5525 reg |= size;
5526 wr32(E1000_VMOLR(vf), reg);
5527 }
4ae196df
AD		 5528 }
5529 }
8151d294
WM		 5530 return 0;
5531}
5532
5533static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5534{
5535 struct e1000_hw *hw = &adapter->hw;
5536
5537 if (vid)
5538 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5539 else
5540 wr32(E1000_VMVIR(vf), 0);
5541}
5542
5543static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5544 int vf, u16 vlan, u8 qos)
5545{
5546 int err = 0;
5547 struct igb_adapter *adapter = netdev_priv(netdev);
5548
5549 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5550 return -EINVAL;
5551 if (vlan || qos) {
5552 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5553 if (err)
5554 goto out;
5555 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5556 igb_set_vmolr(adapter, vf, !vlan);
5557 adapter->vf_data[vf].pf_vlan = vlan;
5558 adapter->vf_data[vf].pf_qos = qos;
5559 dev_info(&adapter->pdev->dev,
5560 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5561 if (test_bit(__IGB_DOWN, &adapter->state)) {
5562 dev_warn(&adapter->pdev->dev,
b980ac18 5563 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5564 dev_warn(&adapter->pdev->dev,
b980ac18 5565 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5566 }
5567 } else {
5568 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5569 false, vf);
8151d294
WM		 5570 igb_set_vmvir(adapter, vlan, vf);
5571 igb_set_vmolr(adapter, vf, true);
5572 adapter->vf_data[vf].pf_vlan = 0;
5573 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5574 }
8151d294 5575out:
b980ac18 5576 return err;
4ae196df
AD		 5577}
5578
6f3dc319
GR		 5579static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5580{
5581 struct e1000_hw *hw = &adapter->hw;
5582 int i;
5583 u32 reg;
5584
5585 /* Find the vlan filter for this id */
5586 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5587 reg = rd32(E1000_VLVF(i));
5588 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5589 vid == (reg & E1000_VLVF_VLANID_MASK))
5590 break;
5591 }
5592
5593 if (i >= E1000_VLVF_ARRAY_SIZE)
5594 i = -1;
5595
5596 return i;
5597}
5598
4ae196df
AD		 5599static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5600{
6f3dc319 5601 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5602 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5603 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5604 int err = 0;
4ae196df 5605
6f3dc319
GR		 5606 /* If in promiscuous mode we need to make sure the PF also has
5607 * the VLAN filter set.
5608 */
5609 if (add && (adapter->netdev->flags & IFF_PROMISC))
5610 err = igb_vlvf_set(adapter, vid, add,
5611 adapter->vfs_allocated_count);
5612 if (err)
5613 goto out;
5614
5615 err = igb_vlvf_set(adapter, vid, add, vf);
5616
5617 if (err)
5618 goto out;
5619
5620 /* Go through all the checks to see if the VLAN filter should
5621 * be wiped completely.
5622 */
5623 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5624 u32 vlvf, bits;
5625
5626 int regndx = igb_find_vlvf_entry(adapter, vid);
5627 if (regndx < 0)
5628 goto out;
5629 /* See if any other pools are set for this VLAN filter
5630 * entry other than the PF.
5631 */
5632 vlvf = bits = rd32(E1000_VLVF(regndx));
5633 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5634 adapter->vfs_allocated_count);
5635 /* If the filter was removed then ensure PF pool bit
5636 * is cleared if the PF only added itself to the pool
5637 * because the PF is in promiscuous mode.
5638 */
5639 if ((vlvf & VLAN_VID_MASK) == vid &&
5640 !test_bit(vid, adapter->active_vlans) &&
5641 !bits)
5642 igb_vlvf_set(adapter, vid, add,
5643 adapter->vfs_allocated_count);
5644 }
5645
5646out:
5647 return err;
4ae196df
AD		 5648}
5649
f2ca0dbe 5650static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5651{
8fa7e0f7
GR		 5652 /* clear flags - except flag that indicates PF has set the MAC */
5653 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5654 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5655
5656 /* reset offloads to defaults */
8151d294 5657 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5658
5659 /* reset vlans for device */
5660 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5661 if (adapter->vf_data[vf].pf_vlan)
5662 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5663 adapter->vf_data[vf].pf_vlan,
5664 adapter->vf_data[vf].pf_qos);
5665 else
5666 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5667
5668 /* reset multicast table array for vf */
5669 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5670
5671 /* Flush and reset the mta with the new values */
ff41f8dc 5672 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5673}
5674
f2ca0dbe
AD		 5675static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5676{
5677 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5678
5ac6f91d 5679 /* clear mac address as we were hotplug removed/added */
8151d294 5680 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5681 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5682
5683 /* process remaining reset events */
5684 igb_vf_reset(adapter, vf);
5685}
5686
5687static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5688{
5689 struct e1000_hw *hw = &adapter->hw;
5690 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5691 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5692 u32 reg, msgbuf[3];
5693 u8 *addr = (u8 *)(&msgbuf[1]);
5694
5695 /* process all the same items cleared in a function level reset */
f2ca0dbe 5696 igb_vf_reset(adapter, vf);
4ae196df
AD		 5697
5698 /* set vf mac address */
26ad9178 5699 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5700
5701 /* enable transmit and receive for vf */
5702 reg = rd32(E1000_VFTE);
5703 wr32(E1000_VFTE, reg | (1 << vf));
5704 reg = rd32(E1000_VFRE);
5705 wr32(E1000_VFRE, reg | (1 << vf));
5706
8fa7e0f7 5707 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5708
5709 /* reply to reset with ack and vf mac address */
5710 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5711 memcpy(addr, vf_mac, 6);
5712 igb_write_mbx(hw, msgbuf, 3, vf);
5713}
5714
5715static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5716{
b980ac18 5717 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5718 * starting at the second 32 bit word of the msg array
5719 */
f2ca0dbe
AD		 5720 unsigned char *addr = (char *)&msg[1];
5721 int err = -1;
4ae196df 5722
f2ca0dbe
AD		 5723 if (is_valid_ether_addr(addr))
5724 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5725
f2ca0dbe 5726 return err;
4ae196df
AD		 5727}
5728
5729static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5730{
5731 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5732 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5733 u32 msg = E1000_VT_MSGTYPE_NACK;
5734
5735 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 5736 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5737 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 5738 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 5739 vf_data->last_nack = jiffies;
4ae196df
AD		 5740 }
5741}
5742
f2ca0dbe 5743static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 5744{
f2ca0dbe
AD		 5745 struct pci_dev *pdev = adapter->pdev;
5746 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 5747 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5748 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5749 s32 retval;
5750
f2ca0dbe 5751 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 5752
fef45f4c
AD		 5753 if (retval) {
5754 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 5755 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 5756 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5757 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5758 return;
5759 goto out;
5760 }
4ae196df
AD		 5761
5762 /* this is a message we already processed, do nothing */
5763 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 5764 return;
4ae196df 5765
b980ac18 5766 /* until the vf completes a reset it should not be
4ae196df
AD		 5767 * allowed to start any configuration.
5768 */
4ae196df
AD		 5769 if (msgbuf[0] == E1000_VF_RESET) {
5770 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 5771 return;
4ae196df
AD		 5772 }
5773
f2ca0dbe 5774 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 5775 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5776 return;
5777 retval = -1;
5778 goto out;
4ae196df
AD		 5779 }
5780
5781 switch ((msgbuf[0] & 0xFFFF)) {
5782 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 5783 retval = -EINVAL;
5784 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5785 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5786 else
5787 dev_warn(&pdev->dev,
b980ac18
JK		 5788 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
5789 vf);
4ae196df 5790 break;
7d5753f0
AD		 5791 case E1000_VF_SET_PROMISC:
5792 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5793 break;
4ae196df
AD		 5794 case E1000_VF_SET_MULTICAST:
5795 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5796 break;
5797 case E1000_VF_SET_LPE:
5798 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5799 break;
5800 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 5801 retval = -1;
5802 if (vf_data->pf_vlan)
5803 dev_warn(&pdev->dev,
b980ac18
JK		 5804 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
5805 vf);
8151d294
WM		 5806 else
5807 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 5808 break;
5809 default:
090b1795 5810 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 5811 retval = -1;
5812 break;
5813 }
5814
fef45f4c
AD		 5815 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5816out:
4ae196df
AD		 5817 /* notify the VF of the results of what it sent us */
5818 if (retval)
5819 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5820 else
5821 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5822
4ae196df 5823 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 5824}
4ae196df 5825
f2ca0dbe
AD		 5826static void igb_msg_task(struct igb_adapter *adapter)
5827{
5828 struct e1000_hw *hw = &adapter->hw;
5829 u32 vf;
5830
5831 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5832 /* process any reset requests */
5833 if (!igb_check_for_rst(hw, vf))
5834 igb_vf_reset_event(adapter, vf);
5835
5836 /* process any messages pending */
5837 if (!igb_check_for_msg(hw, vf))
5838 igb_rcv_msg_from_vf(adapter, vf);
5839
5840 /* process any acks */
5841 if (!igb_check_for_ack(hw, vf))
5842 igb_rcv_ack_from_vf(adapter, vf);
5843 }
4ae196df
AD		 5844}
5845
68d480c4
AD		 5846/**
5847 * igb_set_uta - Set unicast filter table address
5848 * @adapter: board private structure
5849 *
5850 * The unicast table address is a register array of 32-bit registers.
5851 * The table is meant to be used in a way similar to how the MTA is used
5852 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 5853 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5854 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 5855 **/
5856static void igb_set_uta(struct igb_adapter *adapter)
5857{
5858 struct e1000_hw *hw = &adapter->hw;
5859 int i;
5860
5861 /* The UTA table only exists on 82576 hardware and newer */
5862 if (hw->mac.type < e1000_82576)
5863 return;
5864
5865 /* we only need to do this if VMDq is enabled */
5866 if (!adapter->vfs_allocated_count)
5867 return;
5868
5869 for (i = 0; i < hw->mac.uta_reg_count; i++)
5870 array_wr32(E1000_UTA, i, ~0);
5871}
5872
9d5c8243 5873/**
b980ac18
JK		 5874 * igb_intr_msi - Interrupt Handler
5875 * @irq: interrupt number
5876 * @data: pointer to a network interface device structure
9d5c8243
AK		 5877 **/
5878static irqreturn_t igb_intr_msi(int irq, void *data)
5879{
047e0030
AD		 5880 struct igb_adapter *adapter = data;
5881 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5882 struct e1000_hw *hw = &adapter->hw;
5883 /* read ICR disables interrupts using IAM */
5884 u32 icr = rd32(E1000_ICR);
5885
047e0030 5886 igb_write_itr(q_vector);
9d5c8243 5887
7f081d40
AD		 5888 if (icr & E1000_ICR_DRSTA)
5889 schedule_work(&adapter->reset_task);
5890
047e0030 5891 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5892 /* HW is reporting DMA is out of sync */
5893 adapter->stats.doosync++;
5894 }
5895
9d5c8243
AK		 5896 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5897 hw->mac.get_link_status = 1;
5898 if (!test_bit(__IGB_DOWN, &adapter->state))
5899 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5900 }
5901
1f6e8178
MV		 5902 if (icr & E1000_ICR_TS) {
5903 u32 tsicr = rd32(E1000_TSICR);
5904
5905 if (tsicr & E1000_TSICR_TXTS) {
5906 /* acknowledge the interrupt */
5907 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5908 /* retrieve hardware timestamp */
5909 schedule_work(&adapter->ptp_tx_work);
5910 }
5911 }
1f6e8178 5912
047e0030 5913 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5914
5915 return IRQ_HANDLED;
5916}
5917
5918/**
b980ac18
JK		 5919 * igb_intr - Legacy Interrupt Handler
5920 * @irq: interrupt number
5921 * @data: pointer to a network interface device structure
9d5c8243
AK		 5922 **/
5923static irqreturn_t igb_intr(int irq, void *data)
5924{
047e0030
AD		 5925 struct igb_adapter *adapter = data;
5926 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 5927 struct e1000_hw *hw = &adapter->hw;
5928 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 5929 * need for the IMC write
5930 */
9d5c8243 5931 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 5932
5933 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 5934 * not set, then the adapter didn't send an interrupt
5935 */
9d5c8243
AK		 5936 if (!(icr & E1000_ICR_INT_ASSERTED))
5937 return IRQ_NONE;
5938
0ba82994
AD		 5939 igb_write_itr(q_vector);
5940
7f081d40
AD		 5941 if (icr & E1000_ICR_DRSTA)
5942 schedule_work(&adapter->reset_task);
5943
047e0030 5944 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5945 /* HW is reporting DMA is out of sync */
5946 adapter->stats.doosync++;
5947 }
5948
9d5c8243
AK		 5949 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5950 hw->mac.get_link_status = 1;
5951 /* guard against interrupt when we're going down */
5952 if (!test_bit(__IGB_DOWN, &adapter->state))
5953 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5954 }
5955
1f6e8178
MV		 5956 if (icr & E1000_ICR_TS) {
5957 u32 tsicr = rd32(E1000_TSICR);
5958
5959 if (tsicr & E1000_TSICR_TXTS) {
5960 /* acknowledge the interrupt */
5961 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5962 /* retrieve hardware timestamp */
5963 schedule_work(&adapter->ptp_tx_work);
5964 }
5965 }
1f6e8178 5966
047e0030 5967 napi_schedule(&q_vector->napi);
9d5c8243
AK		 5968
5969 return IRQ_HANDLED;
5970}
5971
c50b52a0 5972static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 5973{
047e0030 5974 struct igb_adapter *adapter = q_vector->adapter;
46544258 5975 struct e1000_hw *hw = &adapter->hw;
9d5c8243 5976
0ba82994
AD		 5977 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5978 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5979 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5980 igb_set_itr(q_vector);
46544258 5981 else
047e0030 5982 igb_update_ring_itr(q_vector);
9d5c8243
AK		 5983 }
5984
46544258
AD		 5985 if (!test_bit(__IGB_DOWN, &adapter->state)) {
5986 if (adapter->msix_entries)
047e0030 5987 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 5988 else
5989 igb_irq_enable(adapter);
5990 }
9d5c8243
AK		 5991}
5992
46544258 5993/**
b980ac18
JK		 5994 * igb_poll - NAPI Rx polling callback
5995 * @napi: napi polling structure
5996 * @budget: count of how many packets we should handle
46544258
AD		 5997 **/
5998static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 5999{
047e0030 6000 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6001 struct igb_q_vector,
6002 napi);
16eb8815 6003 bool clean_complete = true;
9d5c8243 6004
421e02f0 6005#ifdef CONFIG_IGB_DCA
047e0030
AD		 6006 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6007 igb_update_dca(q_vector);
fe4506b6 6008#endif
0ba82994 6009 if (q_vector->tx.ring)
13fde97a 6010 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6011
0ba82994 6012 if (q_vector->rx.ring)
cd392f5c 6013 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6014
16eb8815
AD		 6015 /* If all work not completed, return budget and keep polling */
6016 if (!clean_complete)
6017 return budget;
46544258 6018
9d5c8243 6019 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6020 napi_complete(napi);
6021 igb_ring_irq_enable(q_vector);
9d5c8243 6022
16eb8815 6023 return 0;
9d5c8243 6024}
6d8126f9 6025
9d5c8243 6026/**
b980ac18
JK		 6027 * igb_clean_tx_irq - Reclaim resources after transmit completes
6028 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6029 *
b980ac18 6030 * returns true if ring is completely cleaned
9d5c8243 6031 **/
047e0030 6032static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6033{
047e0030 6034 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6035 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6036 struct igb_tx_buffer *tx_buffer;
f4128785 6037 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6038 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6039 unsigned int budget = q_vector->tx.work_limit;
8542db05 6040 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6041
13fde97a
AD		 6042 if (test_bit(__IGB_DOWN, &adapter->state))
6043 return true;
0e014cb1 6044
06034649 6045 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6046 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6047 i -= tx_ring->count;
9d5c8243 6048
f4128785
AD		 6049 do {
6050 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6051
6052 /* if next_to_watch is not set then there is no work pending */
6053 if (!eop_desc)
6054 break;
13fde97a 6055
f4128785 6056 /* prevent any other reads prior to eop_desc */
70d289bc 6057 read_barrier_depends();
f4128785 6058
13fde97a
AD		 6059 /* if DD is not set pending work has not been completed */
6060 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6061 break;
6062
8542db05
AD		 6063 /* clear next_to_watch to prevent false hangs */
6064 tx_buffer->next_to_watch = NULL;
9d5c8243 6065
ebe42d16
AD		 6066 /* update the statistics for this packet */
6067 total_bytes += tx_buffer->bytecount;
6068 total_packets += tx_buffer->gso_segs;
13fde97a 6069
ebe42d16
AD		 6070 /* free the skb */
6071 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6072
ebe42d16
AD		 6073 /* unmap skb header data */
6074 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6075 dma_unmap_addr(tx_buffer, dma),
6076 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6077 DMA_TO_DEVICE);
6078
c9f14bf3
AD		 6079 /* clear tx_buffer data */
6080 tx_buffer->skb = NULL;
6081 dma_unmap_len_set(tx_buffer, len, 0);
6082
ebe42d16
AD		 6083 /* clear last DMA location and unmap remaining buffers */
6084 while (tx_desc != eop_desc) {
13fde97a
AD		 6085 tx_buffer++;
6086 tx_desc++;
9d5c8243 6087 i++;
8542db05
AD		 6088 if (unlikely(!i)) {
6089 i -= tx_ring->count;
06034649 6090 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6091 tx_desc = IGB_TX_DESC(tx_ring, 0);
6092 }
ebe42d16
AD		 6093
6094 /* unmap any remaining paged data */
c9f14bf3 6095 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6096 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6097 dma_unmap_addr(tx_buffer, dma),
6098 dma_unmap_len(tx_buffer, len),
ebe42d16 6099 DMA_TO_DEVICE);
c9f14bf3 6100 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6101 }
6102 }
6103
ebe42d16
AD		 6104 /* move us one more past the eop_desc for start of next pkt */
6105 tx_buffer++;
6106 tx_desc++;
6107 i++;
6108 if (unlikely(!i)) {
6109 i -= tx_ring->count;
6110 tx_buffer = tx_ring->tx_buffer_info;
6111 tx_desc = IGB_TX_DESC(tx_ring, 0);
6112 }
f4128785
AD		 6113
6114 /* issue prefetch for next Tx descriptor */
6115 prefetch(tx_desc);
6116
6117 /* update budget accounting */
6118 budget--;
6119 } while (likely(budget));
0e014cb1 6120
bdbc0631
ED		 6121 netdev_tx_completed_queue(txring_txq(tx_ring),
6122 total_packets, total_bytes);
8542db05 6123 i += tx_ring->count;
9d5c8243 6124 tx_ring->next_to_clean = i;
13fde97a
AD		 6125 u64_stats_update_begin(&tx_ring->tx_syncp);
6126 tx_ring->tx_stats.bytes += total_bytes;
6127 tx_ring->tx_stats.packets += total_packets;
6128 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6129 q_vector->tx.total_bytes += total_bytes;
6130 q_vector->tx.total_packets += total_packets;
9d5c8243 6131
6d095fa8 6132 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6133 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6134
9d5c8243 6135 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6136 * check with the clearing of time_stamp and movement of i
6137 */
6d095fa8 6138 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6139 if (tx_buffer->next_to_watch &&
8542db05 6140 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6141 (adapter->tx_timeout_factor * HZ)) &&
6142 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6143
9d5c8243 6144 /* detected Tx unit hang */
59d71989 6145 dev_err(tx_ring->dev,
9d5c8243 6146 "Detected Tx Unit Hang\n"
2d064c06 6147 " Tx Queue <%d>\n"
9d5c8243
AK		 6148 " TDH <%x>\n"
6149 " TDT <%x>\n"
6150 " next_to_use <%x>\n"
6151 " next_to_clean <%x>\n"
9d5c8243
AK		 6152 "buffer_info[next_to_clean]\n"
6153 " time_stamp <%lx>\n"
8542db05 6154 " next_to_watch <%p>\n"
9d5c8243
AK		 6155 " jiffies <%lx>\n"
6156 " desc.status <%x>\n",
2d064c06 6157 tx_ring->queue_index,
238ac817 6158 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6159 readl(tx_ring->tail),
9d5c8243
AK		 6160 tx_ring->next_to_use,
6161 tx_ring->next_to_clean,
8542db05 6162 tx_buffer->time_stamp,
f4128785 6163 tx_buffer->next_to_watch,
9d5c8243 6164 jiffies,
f4128785 6165 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6166 netif_stop_subqueue(tx_ring->netdev,
6167 tx_ring->queue_index);
6168
6169 /* we are about to reset, no point in enabling stuff */
6170 return true;
9d5c8243
AK		 6171 }
6172 }
13fde97a 6173
21ba6fe1 6174#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6175 if (unlikely(total_packets &&
b980ac18
JK		 6176 netif_carrier_ok(tx_ring->netdev) &&
6177 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6178 /* Make sure that anybody stopping the queue after this
6179 * sees the new next_to_clean.
6180 */
6181 smp_mb();
6182 if (__netif_subqueue_stopped(tx_ring->netdev,
6183 tx_ring->queue_index) &&
6184 !(test_bit(__IGB_DOWN, &adapter->state))) {
6185 netif_wake_subqueue(tx_ring->netdev,
6186 tx_ring->queue_index);
6187
6188 u64_stats_update_begin(&tx_ring->tx_syncp);
6189 tx_ring->tx_stats.restart_queue++;
6190 u64_stats_update_end(&tx_ring->tx_syncp);
6191 }
6192 }
6193
6194 return !!budget;
9d5c8243
AK		 6195}
6196
cbc8e55f 6197/**
b980ac18
JK		 6198 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6199 * @rx_ring: rx descriptor ring to store buffers on
6200 * @old_buff: donor buffer to have page reused
cbc8e55f 6201 *
b980ac18 6202 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6203 **/
6204static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6205 struct igb_rx_buffer *old_buff)
6206{
6207 struct igb_rx_buffer *new_buff;
6208 u16 nta = rx_ring->next_to_alloc;
6209
6210 new_buff = &rx_ring->rx_buffer_info[nta];
6211
6212 /* update, and store next to alloc */
6213 nta++;
6214 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6215
6216 /* transfer page from old buffer to new buffer */
6217 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6218
6219 /* sync the buffer for use by the device */
6220 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6221 old_buff->page_offset,
de78d1f9 6222 IGB_RX_BUFSZ,
cbc8e55f
AD		 6223 DMA_FROM_DEVICE);
6224}
6225
74e238ea
AD		 6226static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6227 struct page *page,
6228 unsigned int truesize)
6229{
6230 /* avoid re-using remote pages */
6231 if (unlikely(page_to_nid(page) != numa_node_id()))
6232 return false;
6233
6234#if (PAGE_SIZE < 8192)
6235 /* if we are only owner of page we can reuse it */
6236 if (unlikely(page_count(page) != 1))
6237 return false;
6238
6239 /* flip page offset to other buffer */
6240 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6241
6242 /* since we are the only owner of the page and we need to
6243 * increment it, just set the value to 2 in order to avoid
6244 * an unnecessary locked operation
6245 */
6246 atomic_set(&page->_count, 2);
6247#else
6248 /* move offset up to the next cache line */
6249 rx_buffer->page_offset += truesize;
6250
6251 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6252 return false;
6253
6254 /* bump ref count on page before it is given to the stack */
6255 get_page(page);
6256#endif
6257
6258 return true;
6259}
6260
cbc8e55f 6261/**
b980ac18
JK		 6262 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6263 * @rx_ring: rx descriptor ring to transact packets on
6264 * @rx_buffer: buffer containing page to add
6265 * @rx_desc: descriptor containing length of buffer written by hardware
6266 * @skb: sk_buff to place the data into
cbc8e55f 6267 *
b980ac18
JK		 6268 * This function will add the data contained in rx_buffer->page to the skb.
6269 * This is done either through a direct copy if the data in the buffer is
6270 * less than the skb header size, otherwise it will just attach the page as
6271 * a frag to the skb.
cbc8e55f 6272 *
b980ac18
JK		 6273 * The function will then update the page offset if necessary and return
6274 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6275 **/
6276static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6277 struct igb_rx_buffer *rx_buffer,
6278 union e1000_adv_rx_desc *rx_desc,
6279 struct sk_buff *skb)
6280{
6281 struct page *page = rx_buffer->page;
6282 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6283#if (PAGE_SIZE < 8192)
6284 unsigned int truesize = IGB_RX_BUFSZ;
6285#else
6286 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6287#endif
cbc8e55f
AD		 6288
6289 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6290 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6291
cbc8e55f
AD		 6292 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6293 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6294 va += IGB_TS_HDR_LEN;
6295 size -= IGB_TS_HDR_LEN;
6296 }
6297
cbc8e55f
AD		 6298 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6299
6300 /* we can reuse buffer as-is, just make sure it is local */
6301 if (likely(page_to_nid(page) == numa_node_id()))
6302 return true;
6303
6304 /* this page cannot be reused so discard it */
6305 put_page(page);
6306 return false;
6307 }
6308
6309 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6310 rx_buffer->page_offset, size, truesize);
cbc8e55f 6311
74e238ea
AD		 6312 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6313}
cbc8e55f 6314
2e334eee
AD		 6315static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6316 union e1000_adv_rx_desc *rx_desc,
6317 struct sk_buff *skb)
6318{
6319 struct igb_rx_buffer *rx_buffer;
6320 struct page *page;
6321
6322 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6323
2e334eee
AD		 6324 page = rx_buffer->page;
6325 prefetchw(page);
6326
6327 if (likely(!skb)) {
6328 void *page_addr = page_address(page) +
6329 rx_buffer->page_offset;
6330
6331 /* prefetch first cache line of first page */
6332 prefetch(page_addr);
6333#if L1_CACHE_BYTES < 128
6334 prefetch(page_addr + L1_CACHE_BYTES);
6335#endif
6336
6337 /* allocate a skb to store the frags */
6338 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6339 IGB_RX_HDR_LEN);
6340 if (unlikely(!skb)) {
6341 rx_ring->rx_stats.alloc_failed++;
6342 return NULL;
6343 }
6344
b980ac18 6345 /* we will be copying header into skb->data in
2e334eee
AD		 6346 * pskb_may_pull so it is in our interest to prefetch
6347 * it now to avoid a possible cache miss
6348 */
6349 prefetchw(skb->data);
6350 }
6351
6352 /* we are reusing so sync this buffer for CPU use */
6353 dma_sync_single_range_for_cpu(rx_ring->dev,
6354 rx_buffer->dma,
6355 rx_buffer->page_offset,
de78d1f9 6356 IGB_RX_BUFSZ,
2e334eee
AD		 6357 DMA_FROM_DEVICE);
6358
6359 /* pull page into skb */
6360 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6361 /* hand second half of page back to the ring */
6362 igb_reuse_rx_page(rx_ring, rx_buffer);
6363 } else {
6364 /* we are not reusing the buffer so unmap it */
6365 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6366 PAGE_SIZE, DMA_FROM_DEVICE);
6367 }
6368
6369 /* clear contents of rx_buffer */
6370 rx_buffer->page = NULL;
6371
6372 return skb;
6373}
6374
cd392f5c 6375static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6376 union e1000_adv_rx_desc *rx_desc,
6377 struct sk_buff *skb)
9d5c8243 6378{
bc8acf2c 6379 skb_checksum_none_assert(skb);
9d5c8243 6380
294e7d78 6381 /* Ignore Checksum bit is set */
3ceb90fd 6382 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6383 return;
6384
6385 /* Rx checksum disabled via ethtool */
6386 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6387 return;
85ad76b2 6388
9d5c8243 6389 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6390 if (igb_test_staterr(rx_desc,
6391 E1000_RXDEXT_STATERR_TCPE |
6392 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6393 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6394 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6395 * packets, (aka let the stack check the crc32c)
6396 */
866cff06
AD		 6397 if (!((skb->len == 60) &&
6398 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6399 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6400 ring->rx_stats.csum_err++;
12dcd86b
ED		 6401 u64_stats_update_end(&ring->rx_syncp);
6402 }
9d5c8243 6403 /* let the stack verify checksum errors */
9d5c8243
AK		 6404 return;
6405 }
6406 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6407 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6408 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6409 skb->ip_summed = CHECKSUM_UNNECESSARY;
6410
3ceb90fd
AD		 6411 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6412 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6413}
6414
077887c3
AD		 6415static inline void igb_rx_hash(struct igb_ring *ring,
6416 union e1000_adv_rx_desc *rx_desc,
6417 struct sk_buff *skb)
6418{
6419 if (ring->netdev->features & NETIF_F_RXHASH)
6420 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6421}
6422
2e334eee 6423/**
b980ac18
JK		 6424 * igb_is_non_eop - process handling of non-EOP buffers
6425 * @rx_ring: Rx ring being processed
6426 * @rx_desc: Rx descriptor for current buffer
6427 * @skb: current socket buffer containing buffer in progress
2e334eee 6428 *
b980ac18
JK		 6429 * This function updates next to clean. If the buffer is an EOP buffer
6430 * this function exits returning false, otherwise it will place the
6431 * sk_buff in the next buffer to be chained and return true indicating
6432 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6433 **/
6434static bool igb_is_non_eop(struct igb_ring *rx_ring,
6435 union e1000_adv_rx_desc *rx_desc)
6436{
6437 u32 ntc = rx_ring->next_to_clean + 1;
6438
6439 /* fetch, update, and store next to clean */
6440 ntc = (ntc < rx_ring->count) ? ntc : 0;
6441 rx_ring->next_to_clean = ntc;
6442
6443 prefetch(IGB_RX_DESC(rx_ring, ntc));
6444
6445 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6446 return false;
6447
6448 return true;
6449}
6450
1a1c225b 6451/**
b980ac18
JK		 6452 * igb_get_headlen - determine size of header for LRO/GRO
6453 * @data: pointer to the start of the headers
6454 * @max_len: total length of section to find headers in
1a1c225b 6455 *
b980ac18
JK		 6456 * This function is meant to determine the length of headers that will
6457 * be recognized by hardware for LRO, and GRO offloads. The main
6458 * motivation of doing this is to only perform one pull for IPv4 TCP
6459 * packets so that we can do basic things like calculating the gso_size
6460 * based on the average data per packet.
1a1c225b
AD		 6461 **/
6462static unsigned int igb_get_headlen(unsigned char *data,
6463 unsigned int max_len)
6464{
6465 union {
6466 unsigned char *network;
6467 /* l2 headers */
6468 struct ethhdr *eth;
6469 struct vlan_hdr *vlan;
6470 /* l3 headers */
6471 struct iphdr *ipv4;
6472 struct ipv6hdr *ipv6;
6473 } hdr;
6474 __be16 protocol;
6475 u8 nexthdr = 0; /* default to not TCP */
6476 u8 hlen;
6477
6478 /* this should never happen, but better safe than sorry */
6479 if (max_len < ETH_HLEN)
6480 return max_len;
6481
6482 /* initialize network frame pointer */
6483 hdr.network = data;
6484
6485 /* set first protocol and move network header forward */
6486 protocol = hdr.eth->h_proto;
6487 hdr.network += ETH_HLEN;
6488
6489 /* handle any vlan tag if present */
6490 if (protocol == __constant_htons(ETH_P_8021Q)) {
6491 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6492 return max_len;
6493
6494 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6495 hdr.network += VLAN_HLEN;
6496 }
6497
6498 /* handle L3 protocols */
6499 if (protocol == __constant_htons(ETH_P_IP)) {
6500 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6501 return max_len;
6502
6503 /* access ihl as a u8 to avoid unaligned access on ia64 */
6504 hlen = (hdr.network[0] & 0x0F) << 2;
6505
6506 /* verify hlen meets minimum size requirements */
6507 if (hlen < sizeof(struct iphdr))
6508 return hdr.network - data;
6509
f2fb4ab2 6510 /* record next protocol if header is present */
b9555f66 6511 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6512 nexthdr = hdr.ipv4->protocol;
1a1c225b
AD		 6513 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6514 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6515 return max_len;
6516
6517 /* record next protocol */
6518 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6519 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6520 } else {
6521 return hdr.network - data;
6522 }
6523
f2fb4ab2
AD		 6524 /* relocate pointer to start of L4 header */
6525 hdr.network += hlen;
6526
1a1c225b
AD		 6527 /* finally sort out TCP */
6528 if (nexthdr == IPPROTO_TCP) {
6529 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6530 return max_len;
6531
6532 /* access doff as a u8 to avoid unaligned access on ia64 */
6533 hlen = (hdr.network[12] & 0xF0) >> 2;
6534
6535 /* verify hlen meets minimum size requirements */
6536 if (hlen < sizeof(struct tcphdr))
6537 return hdr.network - data;
6538
6539 hdr.network += hlen;
6540 } else if (nexthdr == IPPROTO_UDP) {
6541 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6542 return max_len;
6543
6544 hdr.network += sizeof(struct udphdr);
6545 }
6546
b980ac18 6547 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6548 * data section of the packet and will be the end of the header.
6549 * If not then it probably represents the end of the last recognized
6550 * header.
6551 */
6552 if ((hdr.network - data) < max_len)
6553 return hdr.network - data;
6554 else
6555 return max_len;
6556}
6557
6558/**
b980ac18
JK		 6559 * igb_pull_tail - igb specific version of skb_pull_tail
6560 * @rx_ring: rx descriptor ring packet is being transacted on
6561 * @rx_desc: pointer to the EOP Rx descriptor
6562 * @skb: pointer to current skb being adjusted
1a1c225b 6563 *
b980ac18
JK		 6564 * This function is an igb specific version of __pskb_pull_tail. The
6565 * main difference between this version and the original function is that
6566 * this function can make several assumptions about the state of things
6567 * that allow for significant optimizations versus the standard function.
6568 * As a result we can do things like drop a frag and maintain an accurate
6569 * truesize for the skb.
1a1c225b
AD		 6570 */
6571static void igb_pull_tail(struct igb_ring *rx_ring,
6572 union e1000_adv_rx_desc *rx_desc,
6573 struct sk_buff *skb)
2d94d8ab 6574{
1a1c225b
AD		 6575 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6576 unsigned char *va;
6577 unsigned int pull_len;
6578
b980ac18 6579 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6580 * working with pages allocated out of the lomem pool per
6581 * alloc_page(GFP_ATOMIC)
2d94d8ab 6582 */
1a1c225b
AD		 6583 va = skb_frag_address(frag);
6584
1a1c225b
AD		 6585 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6586 /* retrieve timestamp from buffer */
6587 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6588
6589 /* update pointers to remove timestamp header */
6590 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6591 frag->page_offset += IGB_TS_HDR_LEN;
6592 skb->data_len -= IGB_TS_HDR_LEN;
6593 skb->len -= IGB_TS_HDR_LEN;
6594
6595 /* move va to start of packet data */
6596 va += IGB_TS_HDR_LEN;
6597 }
6598
b980ac18 6599 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6600 * 60 bytes if the skb->len is less than 60 for skb_pad.
6601 */
6602 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6603
6604 /* align pull length to size of long to optimize memcpy performance */
6605 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6606
6607 /* update all of the pointers */
6608 skb_frag_size_sub(frag, pull_len);
6609 frag->page_offset += pull_len;
6610 skb->data_len -= pull_len;
6611 skb->tail += pull_len;
6612}
6613
6614/**
b980ac18
JK		 6615 * igb_cleanup_headers - Correct corrupted or empty headers
6616 * @rx_ring: rx descriptor ring packet is being transacted on
6617 * @rx_desc: pointer to the EOP Rx descriptor
6618 * @skb: pointer to current skb being fixed
1a1c225b 6619 *
b980ac18
JK		 6620 * Address the case where we are pulling data in on pages only
6621 * and as such no data is present in the skb header.
1a1c225b 6622 *
b980ac18
JK		 6623 * In addition if skb is not at least 60 bytes we need to pad it so that
6624 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6625 *
b980ac18 6626 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6627 **/
6628static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6629 union e1000_adv_rx_desc *rx_desc,
6630 struct sk_buff *skb)
6631{
1a1c225b
AD		 6632 if (unlikely((igb_test_staterr(rx_desc,
6633 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6634 struct net_device *netdev = rx_ring->netdev;
6635 if (!(netdev->features & NETIF_F_RXALL)) {
6636 dev_kfree_skb_any(skb);
6637 return true;
6638 }
6639 }
6640
6641 /* place header in linear portion of buffer */
6642 if (skb_is_nonlinear(skb))
6643 igb_pull_tail(rx_ring, rx_desc, skb);
6644
6645 /* if skb_pad returns an error the skb was freed */
6646 if (unlikely(skb->len < 60)) {
6647 int pad_len = 60 - skb->len;
6648
6649 if (skb_pad(skb, pad_len))
6650 return true;
6651 __skb_put(skb, pad_len);
6652 }
6653
6654 return false;
2d94d8ab
AD		 6655}
6656
db2ee5bd 6657/**
b980ac18
JK		 6658 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6659 * @rx_ring: rx descriptor ring packet is being transacted on
6660 * @rx_desc: pointer to the EOP Rx descriptor
6661 * @skb: pointer to current skb being populated
db2ee5bd 6662 *
b980ac18
JK		 6663 * This function checks the ring, descriptor, and packet information in
6664 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6665 * other fields within the skb.
db2ee5bd
AD		 6666 **/
6667static void igb_process_skb_fields(struct igb_ring *rx_ring,
6668 union e1000_adv_rx_desc *rx_desc,
6669 struct sk_buff *skb)
6670{
6671 struct net_device *dev = rx_ring->netdev;
6672
6673 igb_rx_hash(rx_ring, rx_desc, skb);
6674
6675 igb_rx_checksum(rx_ring, rx_desc, skb);
6676
20a48412 6677 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6678
f646968f 6679 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6680 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6681 u16 vid;
6682 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6683 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6684 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6685 else
6686 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6687
86a9bad3 6688 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6689 }
6690
6691 skb_record_rx_queue(skb, rx_ring->queue_index);
6692
6693 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6694}
6695
2e334eee 6696static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6697{
0ba82994 6698 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6699 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6700 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6701 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6702
2e334eee
AD		 6703 do {
6704 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6705
2e334eee
AD		 6706 /* return some buffers to hardware, one at a time is too slow */
6707 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6708 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6709 cleaned_count = 0;
6710 }
bf36c1a0 6711
2e334eee 6712 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6713
2e334eee
AD		 6714 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6715 break;
9d5c8243 6716
74e238ea
AD		 6717 /* This memory barrier is needed to keep us from reading
6718 * any other fields out of the rx_desc until we know the
6719 * RXD_STAT_DD bit is set
6720 */
6721 rmb();
6722
2e334eee 6723 /* retrieve a buffer from the ring */
f9d40f6a 6724 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6725
2e334eee
AD		 6726 /* exit if we failed to retrieve a buffer */
6727 if (!skb)
6728 break;
1a1c225b 6729
2e334eee 6730 cleaned_count++;
1a1c225b 6731
2e334eee
AD		 6732 /* fetch next buffer in frame if non-eop */
6733 if (igb_is_non_eop(rx_ring, rx_desc))
6734 continue;
1a1c225b
AD		 6735
6736 /* verify the packet layout is correct */
6737 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6738 skb = NULL;
6739 continue;
9d5c8243 6740 }
9d5c8243 6741
db2ee5bd 6742 /* probably a little skewed due to removing CRC */
3ceb90fd 6743 total_bytes += skb->len;
3ceb90fd 6744
db2ee5bd
AD		 6745 /* populate checksum, timestamp, VLAN, and protocol */
6746 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6747
b2cb09b1 6748 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6749
1a1c225b
AD		 6750 /* reset skb pointer */
6751 skb = NULL;
6752
2e334eee
AD		 6753 /* update budget accounting */
6754 total_packets++;
6755 } while (likely(total_packets < budget));
bf36c1a0 6756
1a1c225b
AD		 6757 /* place incomplete frames back on ring for completion */
6758 rx_ring->skb = skb;
6759
12dcd86b 6760 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6761 rx_ring->rx_stats.packets += total_packets;
6762 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6763 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6764 q_vector->rx.total_packets += total_packets;
6765 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6766
6767 if (cleaned_count)
cd392f5c 6768 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6769
2e334eee 6770 return (total_packets < budget);
9d5c8243
AK		 6771}
6772
c023cd88 6773static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6774 struct igb_rx_buffer *bi)
c023cd88
AD		 6775{
6776 struct page *page = bi->page;
cbc8e55f 6777 dma_addr_t dma;
c023cd88 6778
cbc8e55f
AD		 6779 /* since we are recycling buffers we should seldom need to alloc */
6780 if (likely(page))
c023cd88
AD		 6781 return true;
6782
cbc8e55f
AD		 6783 /* alloc new page for storage */
6784 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6785 if (unlikely(!page)) {
6786 rx_ring->rx_stats.alloc_failed++;
6787 return false;
c023cd88
AD		 6788 }
6789
cbc8e55f
AD		 6790 /* map page for use */
6791 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6792
b980ac18 6793 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6794 * there isn't much point in holding memory we can't use
6795 */
1a1c225b 6796 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6797 __free_page(page);
6798
c023cd88
AD		 6799 rx_ring->rx_stats.alloc_failed++;
6800 return false;
6801 }
6802
1a1c225b 6803 bi->dma = dma;
cbc8e55f
AD		 6804 bi->page = page;
6805 bi->page_offset = 0;
1a1c225b 6806
c023cd88
AD		 6807 return true;
6808}
6809
9d5c8243 6810/**
b980ac18
JK		 6811 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6812 * @adapter: address of board private structure
9d5c8243 6813 **/
cd392f5c 6814void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 6815{
9d5c8243 6816 union e1000_adv_rx_desc *rx_desc;
06034649 6817 struct igb_rx_buffer *bi;
c023cd88 6818 u16 i = rx_ring->next_to_use;
9d5c8243 6819
cbc8e55f
AD		 6820 /* nothing to do */
6821 if (!cleaned_count)
6822 return;
6823
60136906 6824 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 6825 bi = &rx_ring->rx_buffer_info[i];
c023cd88 6826 i -= rx_ring->count;
9d5c8243 6827
cbc8e55f 6828 do {
1a1c225b 6829 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 6830 break;
9d5c8243 6831
b980ac18 6832 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 6833 * because each write-back erases this info.
6834 */
f9d40f6a 6835 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 6836
c023cd88
AD		 6837 rx_desc++;
6838 bi++;
9d5c8243 6839 i++;
c023cd88 6840 if (unlikely(!i)) {
60136906 6841 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 6842 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 6843 i -= rx_ring->count;
6844 }
6845
6846 /* clear the hdr_addr for the next_to_use descriptor */
6847 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 6848
6849 cleaned_count--;
6850 } while (cleaned_count);
9d5c8243 6851
c023cd88
AD		 6852 i += rx_ring->count;
6853
9d5c8243 6854 if (rx_ring->next_to_use != i) {
cbc8e55f 6855 /* record the next descriptor to use */
9d5c8243 6856 rx_ring->next_to_use = i;
9d5c8243 6857
cbc8e55f
AD		 6858 /* update next to alloc since we have filled the ring */
6859 rx_ring->next_to_alloc = i;
6860
b980ac18 6861 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 6862 * know there are new descriptors to fetch. (Only
6863 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 6864 * such as IA-64).
6865 */
9d5c8243 6866 wmb();
fce99e34 6867 writel(i, rx_ring->tail);
9d5c8243
AK		 6868 }
6869}
6870
6871/**
6872 * igb_mii_ioctl -
6873 * @netdev:
6874 * @ifreq:
6875 * @cmd:
6876 **/
6877static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6878{
6879 struct igb_adapter *adapter = netdev_priv(netdev);
6880 struct mii_ioctl_data *data = if_mii(ifr);
6881
6882 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6883 return -EOPNOTSUPP;
6884
6885 switch (cmd) {
6886 case SIOCGMIIPHY:
6887 data->phy_id = adapter->hw.phy.addr;
6888 break;
6889 case SIOCGMIIREG:
f5f4cf08
AD		 6890 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6891 &data->val_out))
9d5c8243
AK		 6892 return -EIO;
6893 break;
6894 case SIOCSMIIREG:
6895 default:
6896 return -EOPNOTSUPP;
6897 }
6898 return 0;
6899}
6900
6901/**
6902 * igb_ioctl -
6903 * @netdev:
6904 * @ifreq:
6905 * @cmd:
6906 **/
6907static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6908{
6909 switch (cmd) {
6910 case SIOCGMIIPHY:
6911 case SIOCGMIIREG:
6912 case SIOCSMIIREG:
6913 return igb_mii_ioctl(netdev, ifr, cmd);
c6cb090b 6914 case SIOCSHWTSTAMP:
a79f4f88 6915 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
9d5c8243
AK		 6916 default:
6917 return -EOPNOTSUPP;
6918 }
6919}
6920
009bc06e
AD		 6921s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6922{
6923 struct igb_adapter *adapter = hw->back;
009bc06e 6924
23d028cc 6925 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 6926 return -E1000_ERR_CONFIG;
6927
009bc06e
AD		 6928 return 0;
6929}
6930
6931s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6932{
6933 struct igb_adapter *adapter = hw->back;
009bc06e 6934
23d028cc 6935 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 6936 return -E1000_ERR_CONFIG;
6937
009bc06e
AD		 6938 return 0;
6939}
6940
c8f44aff 6941static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 6942{
6943 struct igb_adapter *adapter = netdev_priv(netdev);
6944 struct e1000_hw *hw = &adapter->hw;
6945 u32 ctrl, rctl;
f646968f 6946 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 6947
5faf030c 6948 if (enable) {
9d5c8243
AK		 6949 /* enable VLAN tag insert/strip */
6950 ctrl = rd32(E1000_CTRL);
6951 ctrl |= E1000_CTRL_VME;
6952 wr32(E1000_CTRL, ctrl);
6953
51466239 6954 /* Disable CFI check */
9d5c8243 6955 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 6956 rctl &= ~E1000_RCTL_CFIEN;
6957 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 6958 } else {
6959 /* disable VLAN tag insert/strip */
6960 ctrl = rd32(E1000_CTRL);
6961 ctrl &= ~E1000_CTRL_VME;
6962 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 6963 }
6964
e1739522 6965 igb_rlpml_set(adapter);
9d5c8243
AK		 6966}
6967
80d5c368
PM		 6968static int igb_vlan_rx_add_vid(struct net_device *netdev,
6969 __be16 proto, u16 vid)
9d5c8243
AK		 6970{
6971 struct igb_adapter *adapter = netdev_priv(netdev);
6972 struct e1000_hw *hw = &adapter->hw;
4ae196df 6973 int pf_id = adapter->vfs_allocated_count;
9d5c8243 6974
51466239
AD		 6975 /* attempt to add filter to vlvf array */
6976 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 6977
51466239
AD		 6978 /* add the filter since PF can receive vlans w/o entry in vlvf */
6979 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 6980
6981 set_bit(vid, adapter->active_vlans);
8e586137
JP		 6982
6983 return 0;
9d5c8243
AK		 6984}
6985
80d5c368
PM		 6986static int igb_vlan_rx_kill_vid(struct net_device *netdev,
6987 __be16 proto, u16 vid)
9d5c8243
AK		 6988{
6989 struct igb_adapter *adapter = netdev_priv(netdev);
6990 struct e1000_hw *hw = &adapter->hw;
4ae196df 6991 int pf_id = adapter->vfs_allocated_count;
51466239 6992 s32 err;
9d5c8243 6993
51466239
AD		 6994 /* remove vlan from VLVF table array */
6995 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 6996
51466239
AD		 6997 /* if vid was not present in VLVF just remove it from table */
6998 if (err)
4ae196df 6999 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7000
7001 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7002
7003 return 0;
9d5c8243
AK		 7004}
7005
7006static void igb_restore_vlan(struct igb_adapter *adapter)
7007{
b2cb09b1 7008 u16 vid;
9d5c8243 7009
5faf030c
AD		 7010 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7011
b2cb09b1 7012 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7013 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7014}
7015
14ad2513 7016int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7017{
090b1795 7018 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7019 struct e1000_mac_info *mac = &adapter->hw.mac;
7020
7021 mac->autoneg = 0;
7022
14ad2513 7023 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7024 * for the switch() below to work
7025 */
14ad2513
DD		 7026 if ((spd & 1) || (dplx & ~1))
7027 goto err_inval;
7028
f502ef7d
AA		 7029 /* Fiber NIC's only allow 1000 gbps Full duplex
7030 * and 100Mbps Full duplex for 100baseFx sfp
7031 */
7032 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7033 switch (spd + dplx) {
7034 case SPEED_10 + DUPLEX_HALF:
7035 case SPEED_10 + DUPLEX_FULL:
7036 case SPEED_100 + DUPLEX_HALF:
7037 goto err_inval;
7038 default:
7039 break;
7040 }
7041 }
cd2638a8 7042
14ad2513 7043 switch (spd + dplx) {
9d5c8243
AK		 7044 case SPEED_10 + DUPLEX_HALF:
7045 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7046 break;
7047 case SPEED_10 + DUPLEX_FULL:
7048 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7049 break;
7050 case SPEED_100 + DUPLEX_HALF:
7051 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7052 break;
7053 case SPEED_100 + DUPLEX_FULL:
7054 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7055 break;
7056 case SPEED_1000 + DUPLEX_FULL:
7057 mac->autoneg = 1;
7058 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7059 break;
7060 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7061 default:
14ad2513 7062 goto err_inval;
9d5c8243 7063 }
8376dad0
JB		 7064
7065 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7066 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7067
9d5c8243 7068 return 0;
14ad2513
DD		 7069
7070err_inval:
7071 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7072 return -EINVAL;
9d5c8243
AK		 7073}
7074
749ab2cd
YZ		 7075static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7076 bool runtime)
9d5c8243
AK		 7077{
7078 struct net_device *netdev = pci_get_drvdata(pdev);
7079 struct igb_adapter *adapter = netdev_priv(netdev);
7080 struct e1000_hw *hw = &adapter->hw;
2d064c06 7081 u32 ctrl, rctl, status;
749ab2cd 7082 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7083#ifdef CONFIG_PM
7084 int retval = 0;
7085#endif
7086
7087 netif_device_detach(netdev);
7088
a88f10ec 7089 if (netif_running(netdev))
749ab2cd 7090 __igb_close(netdev, true);
a88f10ec 7091
047e0030 7092 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7093
7094#ifdef CONFIG_PM
7095 retval = pci_save_state(pdev);
7096 if (retval)
7097 return retval;
7098#endif
7099
7100 status = rd32(E1000_STATUS);
7101 if (status & E1000_STATUS_LU)
7102 wufc &= ~E1000_WUFC_LNKC;
7103
7104 if (wufc) {
7105 igb_setup_rctl(adapter);
ff41f8dc 7106 igb_set_rx_mode(netdev);
9d5c8243
AK		 7107
7108 /* turn on all-multi mode if wake on multicast is enabled */
7109 if (wufc & E1000_WUFC_MC) {
7110 rctl = rd32(E1000_RCTL);
7111 rctl |= E1000_RCTL_MPE;
7112 wr32(E1000_RCTL, rctl);
7113 }
7114
7115 ctrl = rd32(E1000_CTRL);
7116 /* advertise wake from D3Cold */
7117 #define E1000_CTRL_ADVD3WUC 0x00100000
7118 /* phy power management enable */
7119 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7120 ctrl |= E1000_CTRL_ADVD3WUC;
7121 wr32(E1000_CTRL, ctrl);
7122
9d5c8243 7123 /* Allow time for pending master requests to run */
330a6d6a 7124 igb_disable_pcie_master(hw);
9d5c8243
AK		 7125
7126 wr32(E1000_WUC, E1000_WUC_PME_EN);
7127 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7128 } else {
7129 wr32(E1000_WUC, 0);
7130 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7131 }
7132
3fe7c4c9
RW		 7133 *enable_wake = wufc || adapter->en_mng_pt;
7134 if (!*enable_wake)
88a268c1
NN		 7135 igb_power_down_link(adapter);
7136 else
7137 igb_power_up_link(adapter);
9d5c8243
AK		 7138
7139 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7140 * would have already happened in close and is redundant.
7141 */
9d5c8243
AK		 7142 igb_release_hw_control(adapter);
7143
7144 pci_disable_device(pdev);
7145
9d5c8243
AK		 7146 return 0;
7147}
7148
7149#ifdef CONFIG_PM
d9dd966d 7150#ifdef CONFIG_PM_SLEEP
749ab2cd 7151static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7152{
7153 int retval;
7154 bool wake;
749ab2cd 7155 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7156
749ab2cd 7157 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7158 if (retval)
7159 return retval;
7160
7161 if (wake) {
7162 pci_prepare_to_sleep(pdev);
7163 } else {
7164 pci_wake_from_d3(pdev, false);
7165 pci_set_power_state(pdev, PCI_D3hot);
7166 }
7167
7168 return 0;
7169}
d9dd966d 7170#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7171
749ab2cd 7172static int igb_resume(struct device *dev)
9d5c8243 7173{
749ab2cd 7174 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7175 struct net_device *netdev = pci_get_drvdata(pdev);
7176 struct igb_adapter *adapter = netdev_priv(netdev);
7177 struct e1000_hw *hw = &adapter->hw;
7178 u32 err;
7179
7180 pci_set_power_state(pdev, PCI_D0);
7181 pci_restore_state(pdev);
b94f2d77 7182 pci_save_state(pdev);
42bfd33a 7183
aed5dec3 7184 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7185 if (err) {
7186 dev_err(&pdev->dev,
7187 "igb: Cannot enable PCI device from suspend\n");
7188 return err;
7189 }
7190 pci_set_master(pdev);
7191
7192 pci_enable_wake(pdev, PCI_D3hot, 0);
7193 pci_enable_wake(pdev, PCI_D3cold, 0);
7194
53c7d064 7195 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7196 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7197 return -ENOMEM;
9d5c8243
AK		 7198 }
7199
9d5c8243 7200 igb_reset(adapter);
a8564f03
AD		 7201
7202 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7203 * driver.
7204 */
a8564f03
AD		 7205 igb_get_hw_control(adapter);
7206
9d5c8243
AK		 7207 wr32(E1000_WUS, ~0);
7208
749ab2cd 7209 if (netdev->flags & IFF_UP) {
0c2cc02e 7210 rtnl_lock();
749ab2cd 7211 err = __igb_open(netdev, true);
0c2cc02e 7212 rtnl_unlock();
a88f10ec
AD		 7213 if (err)
7214 return err;
7215 }
9d5c8243
AK		 7216
7217 netif_device_attach(netdev);
749ab2cd
YZ		 7218 return 0;
7219}
7220
7221#ifdef CONFIG_PM_RUNTIME
7222static int igb_runtime_idle(struct device *dev)
7223{
7224 struct pci_dev *pdev = to_pci_dev(dev);
7225 struct net_device *netdev = pci_get_drvdata(pdev);
7226 struct igb_adapter *adapter = netdev_priv(netdev);
7227
7228 if (!igb_has_link(adapter))
7229 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7230
7231 return -EBUSY;
7232}
7233
7234static int igb_runtime_suspend(struct device *dev)
7235{
7236 struct pci_dev *pdev = to_pci_dev(dev);
7237 int retval;
7238 bool wake;
7239
7240 retval = __igb_shutdown(pdev, &wake, 1);
7241 if (retval)
7242 return retval;
7243
7244 if (wake) {
7245 pci_prepare_to_sleep(pdev);
7246 } else {
7247 pci_wake_from_d3(pdev, false);
7248 pci_set_power_state(pdev, PCI_D3hot);
7249 }
9d5c8243 7250
9d5c8243
AK		 7251 return 0;
7252}
749ab2cd
YZ		 7253
7254static int igb_runtime_resume(struct device *dev)
7255{
7256 return igb_resume(dev);
7257}
7258#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7259#endif
7260
7261static void igb_shutdown(struct pci_dev *pdev)
7262{
3fe7c4c9
RW		 7263 bool wake;
7264
749ab2cd 7265 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7266
7267 if (system_state == SYSTEM_POWER_OFF) {
7268 pci_wake_from_d3(pdev, wake);
7269 pci_set_power_state(pdev, PCI_D3hot);
7270 }
9d5c8243
AK		 7271}
7272
fa44f2f1
GR		 7273#ifdef CONFIG_PCI_IOV
7274static int igb_sriov_reinit(struct pci_dev *dev)
7275{
7276 struct net_device *netdev = pci_get_drvdata(dev);
7277 struct igb_adapter *adapter = netdev_priv(netdev);
7278 struct pci_dev *pdev = adapter->pdev;
7279
7280 rtnl_lock();
7281
7282 if (netif_running(netdev))
7283 igb_close(netdev);
7284
7285 igb_clear_interrupt_scheme(adapter);
7286
7287 igb_init_queue_configuration(adapter);
7288
7289 if (igb_init_interrupt_scheme(adapter, true)) {
7290 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7291 return -ENOMEM;
7292 }
7293
7294 if (netif_running(netdev))
7295 igb_open(netdev);
7296
7297 rtnl_unlock();
7298
7299 return 0;
7300}
7301
7302static int igb_pci_disable_sriov(struct pci_dev *dev)
7303{
7304 int err = igb_disable_sriov(dev);
7305
7306 if (!err)
7307 err = igb_sriov_reinit(dev);
7308
7309 return err;
7310}
7311
7312static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7313{
7314 int err = igb_enable_sriov(dev, num_vfs);
7315
7316 if (err)
7317 goto out;
7318
7319 err = igb_sriov_reinit(dev);
7320 if (!err)
7321 return num_vfs;
7322
7323out:
7324 return err;
7325}
7326
7327#endif
7328static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7329{
7330#ifdef CONFIG_PCI_IOV
7331 if (num_vfs == 0)
7332 return igb_pci_disable_sriov(dev);
7333 else
7334 return igb_pci_enable_sriov(dev, num_vfs);
7335#endif
7336 return 0;
7337}
7338
9d5c8243 7339#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7340/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7341 * without having to re-enable interrupts. It's not called while
7342 * the interrupt routine is executing.
7343 */
7344static void igb_netpoll(struct net_device *netdev)
7345{
7346 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7347 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7348 struct igb_q_vector *q_vector;
9d5c8243 7349 int i;
9d5c8243 7350
047e0030 7351 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4
AD		 7352 q_vector = adapter->q_vector[i];
7353 if (adapter->msix_entries)
7354 wr32(E1000_EIMC, q_vector->eims_value);
7355 else
7356 igb_irq_disable(adapter);
047e0030 7357 napi_schedule(&q_vector->napi);
eebbbdba 7358 }
9d5c8243
AK		 7359}
7360#endif /* CONFIG_NET_POLL_CONTROLLER */
7361
7362/**
b980ac18
JK		 7363 * igb_io_error_detected - called when PCI error is detected
7364 * @pdev: Pointer to PCI device
7365 * @state: The current pci connection state
9d5c8243 7366 *
b980ac18
JK		 7367 * This function is called after a PCI bus error affecting
7368 * this device has been detected.
7369 **/
9d5c8243
AK		 7370static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7371 pci_channel_state_t state)
7372{
7373 struct net_device *netdev = pci_get_drvdata(pdev);
7374 struct igb_adapter *adapter = netdev_priv(netdev);
7375
7376 netif_device_detach(netdev);
7377
59ed6eec
AD		 7378 if (state == pci_channel_io_perm_failure)
7379 return PCI_ERS_RESULT_DISCONNECT;
7380
9d5c8243
AK		 7381 if (netif_running(netdev))
7382 igb_down(adapter);
7383 pci_disable_device(pdev);
7384
7385 /* Request a slot slot reset. */
7386 return PCI_ERS_RESULT_NEED_RESET;
7387}
7388
7389/**
b980ac18
JK		 7390 * igb_io_slot_reset - called after the pci bus has been reset.
7391 * @pdev: Pointer to PCI device
9d5c8243 7392 *
b980ac18
JK		 7393 * Restart the card from scratch, as if from a cold-boot. Implementation
7394 * resembles the first-half of the igb_resume routine.
7395 **/
9d5c8243
AK		 7396static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7397{
7398 struct net_device *netdev = pci_get_drvdata(pdev);
7399 struct igb_adapter *adapter = netdev_priv(netdev);
7400 struct e1000_hw *hw = &adapter->hw;
40a914fa 7401 pci_ers_result_t result;
42bfd33a 7402 int err;
9d5c8243 7403
aed5dec3 7404 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7405 dev_err(&pdev->dev,
7406 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7407 result = PCI_ERS_RESULT_DISCONNECT;
7408 } else {
7409 pci_set_master(pdev);
7410 pci_restore_state(pdev);
b94f2d77 7411 pci_save_state(pdev);
9d5c8243 7412
40a914fa
AD		 7413 pci_enable_wake(pdev, PCI_D3hot, 0);
7414 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7415
40a914fa
AD		 7416 igb_reset(adapter);
7417 wr32(E1000_WUS, ~0);
7418 result = PCI_ERS_RESULT_RECOVERED;
7419 }
9d5c8243 7420
ea943d41
JK		 7421 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7422 if (err) {
b980ac18
JK		 7423 dev_err(&pdev->dev,
7424 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7425 err);
ea943d41
JK		 7426 /* non-fatal, continue */
7427 }
40a914fa
AD		 7428
7429 return result;
9d5c8243
AK		 7430}
7431
7432/**
b980ac18
JK		 7433 * igb_io_resume - called when traffic can start flowing again.
7434 * @pdev: Pointer to PCI device
9d5c8243 7435 *
b980ac18
JK		 7436 * This callback is called when the error recovery driver tells us that
7437 * its OK to resume normal operation. Implementation resembles the
7438 * second-half of the igb_resume routine.
9d5c8243
AK		 7439 */
7440static void igb_io_resume(struct pci_dev *pdev)
7441{
7442 struct net_device *netdev = pci_get_drvdata(pdev);
7443 struct igb_adapter *adapter = netdev_priv(netdev);
7444
9d5c8243
AK		 7445 if (netif_running(netdev)) {
7446 if (igb_up(adapter)) {
7447 dev_err(&pdev->dev, "igb_up failed after reset\n");
7448 return;
7449 }
7450 }
7451
7452 netif_device_attach(netdev);
7453
7454 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7455 * driver.
7456 */
9d5c8243 7457 igb_get_hw_control(adapter);
9d5c8243
AK		 7458}
7459
26ad9178 7460static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7461 u8 qsel)
26ad9178
AD		 7462{
7463 u32 rar_low, rar_high;
7464 struct e1000_hw *hw = &adapter->hw;
7465
7466 /* HW expects these in little endian so we reverse the byte order
7467 * from network order (big endian) to little endian
7468 */
7469 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7470 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7471 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7472
7473 /* Indicate to hardware the Address is Valid. */
7474 rar_high |= E1000_RAH_AV;
7475
7476 if (hw->mac.type == e1000_82575)
7477 rar_high |= E1000_RAH_POOL_1 * qsel;
7478 else
7479 rar_high |= E1000_RAH_POOL_1 << qsel;
7480
7481 wr32(E1000_RAL(index), rar_low);
7482 wrfl();
7483 wr32(E1000_RAH(index), rar_high);
7484 wrfl();
7485}
7486
4ae196df 7487static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7488 int vf, unsigned char *mac_addr)
4ae196df
AD		 7489{
7490 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7491 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7492 * towards the first, as a result a collision should not be possible
7493 */
ff41f8dc 7494 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7495
37680117 7496 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7497
26ad9178 7498 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7499
7500 return 0;
7501}
7502
8151d294
WM		 7503static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7504{
7505 struct igb_adapter *adapter = netdev_priv(netdev);
7506 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7507 return -EINVAL;
7508 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7509 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7510 dev_info(&adapter->pdev->dev,
7511 "Reload the VF driver to make this change effective.");
8151d294 7512 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7513 dev_warn(&adapter->pdev->dev,
7514 "The VF MAC address has been set, but the PF device is not up.\n");
7515 dev_warn(&adapter->pdev->dev,
7516 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7517 }
7518 return igb_set_vf_mac(adapter, vf, mac);
7519}
7520
17dc566c
LL		 7521static int igb_link_mbps(int internal_link_speed)
7522{
7523 switch (internal_link_speed) {
7524 case SPEED_100:
7525 return 100;
7526 case SPEED_1000:
7527 return 1000;
7528 default:
7529 return 0;
7530 }
7531}
7532
7533static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7534 int link_speed)
7535{
7536 int rf_dec, rf_int;
7537 u32 bcnrc_val;
7538
7539 if (tx_rate != 0) {
7540 /* Calculate the rate factor values to set */
7541 rf_int = link_speed / tx_rate;
7542 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7543 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7544 tx_rate;
17dc566c
LL		 7545
7546 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7547 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7548 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7549 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7550 } else {
7551 bcnrc_val = 0;
7552 }
7553
7554 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7555 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7556 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7557 */
7558 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7559 wr32(E1000_RTTBCNRC, bcnrc_val);
7560}
7561
7562static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7563{
7564 int actual_link_speed, i;
7565 bool reset_rate = false;
7566
7567 /* VF TX rate limit was not set or not supported */
7568 if ((adapter->vf_rate_link_speed == 0) ||
7569 (adapter->hw.mac.type != e1000_82576))
7570 return;
7571
7572 actual_link_speed = igb_link_mbps(adapter->link_speed);
7573 if (actual_link_speed != adapter->vf_rate_link_speed) {
7574 reset_rate = true;
7575 adapter->vf_rate_link_speed = 0;
7576 dev_info(&adapter->pdev->dev,
b980ac18 7577 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7578 }
7579
7580 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7581 if (reset_rate)
7582 adapter->vf_data[i].tx_rate = 0;
7583
7584 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7585 adapter->vf_data[i].tx_rate,
7586 actual_link_speed);
17dc566c
LL		 7587 }
7588}
7589
8151d294
WM		 7590static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7591{
17dc566c
LL		 7592 struct igb_adapter *adapter = netdev_priv(netdev);
7593 struct e1000_hw *hw = &adapter->hw;
7594 int actual_link_speed;
7595
7596 if (hw->mac.type != e1000_82576)
7597 return -EOPNOTSUPP;
7598
7599 actual_link_speed = igb_link_mbps(adapter->link_speed);
7600 if ((vf >= adapter->vfs_allocated_count) ||
7601 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7602 (tx_rate < 0) || (tx_rate > actual_link_speed))
7603 return -EINVAL;
7604
7605 adapter->vf_rate_link_speed = actual_link_speed;
7606 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7607 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7608
7609 return 0;
8151d294
WM		 7610}
7611
70ea4783
LL		 7612static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7613 bool setting)
7614{
7615 struct igb_adapter *adapter = netdev_priv(netdev);
7616 struct e1000_hw *hw = &adapter->hw;
7617 u32 reg_val, reg_offset;
7618
7619 if (!adapter->vfs_allocated_count)
7620 return -EOPNOTSUPP;
7621
7622 if (vf >= adapter->vfs_allocated_count)
7623 return -EINVAL;
7624
7625 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7626 reg_val = rd32(reg_offset);
7627 if (setting)
7628 reg_val |= ((1 << vf) |
7629 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7630 else
7631 reg_val &= ~((1 << vf) |
7632 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7633 wr32(reg_offset, reg_val);
7634
7635 adapter->vf_data[vf].spoofchk_enabled = setting;
7636 return E1000_SUCCESS;
7637}
7638
8151d294
WM		 7639static int igb_ndo_get_vf_config(struct net_device *netdev,
7640 int vf, struct ifla_vf_info *ivi)
7641{
7642 struct igb_adapter *adapter = netdev_priv(netdev);
7643 if (vf >= adapter->vfs_allocated_count)
7644 return -EINVAL;
7645 ivi->vf = vf;
7646 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7647 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7648 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7649 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7650 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7651 return 0;
7652}
7653
4ae196df
AD		 7654static void igb_vmm_control(struct igb_adapter *adapter)
7655{
7656 struct e1000_hw *hw = &adapter->hw;
10d8e907 7657 u32 reg;
4ae196df 7658
52a1dd4d
AD		 7659 switch (hw->mac.type) {
7660 case e1000_82575:
f96a8a0b
CW		 7661 case e1000_i210:
7662 case e1000_i211:
ceb5f13b 7663 case e1000_i354:
52a1dd4d
AD		 7664 default:
7665 /* replication is not supported for 82575 */
4ae196df 7666 return;
52a1dd4d
AD		 7667 case e1000_82576:
7668 /* notify HW that the MAC is adding vlan tags */
7669 reg = rd32(E1000_DTXCTL);
7670 reg |= E1000_DTXCTL_VLAN_ADDED;
7671 wr32(E1000_DTXCTL, reg);
7672 case e1000_82580:
7673 /* enable replication vlan tag stripping */
7674 reg = rd32(E1000_RPLOLR);
7675 reg |= E1000_RPLOLR_STRVLAN;
7676 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7677 case e1000_i350:
7678 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7679 break;
7680 }
10d8e907 7681
d4960307
AD		 7682 if (adapter->vfs_allocated_count) {
7683 igb_vmdq_set_loopback_pf(hw, true);
7684 igb_vmdq_set_replication_pf(hw, true);
13800469 7685 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7686 adapter->vfs_allocated_count);
d4960307
AD		 7687 } else {
7688 igb_vmdq_set_loopback_pf(hw, false);
7689 igb_vmdq_set_replication_pf(hw, false);
7690 }
4ae196df
AD		 7691}
7692
b6e0c419
CW		 7693static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7694{
7695 struct e1000_hw *hw = &adapter->hw;
7696 u32 dmac_thr;
7697 u16 hwm;
7698
7699 if (hw->mac.type > e1000_82580) {
7700 if (adapter->flags & IGB_FLAG_DMAC) {
7701 u32 reg;
7702
7703 /* force threshold to 0. */
7704 wr32(E1000_DMCTXTH, 0);
7705
b980ac18 7706 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7707 * than the Rx threshold. Set hwm to PBA - max frame
7708 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7709 */
e8c626e9
MV		 7710 hwm = 64 * pba - adapter->max_frame_size / 16;
7711 if (hwm < 64 * (pba - 6))
7712 hwm = 64 * (pba - 6);
7713 reg = rd32(E1000_FCRTC);
7714 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7715 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7716 & E1000_FCRTC_RTH_COAL_MASK);
7717 wr32(E1000_FCRTC, reg);
7718
b980ac18 7719 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7720 * frame size, capping it at PBA - 10KB.
7721 */
7722 dmac_thr = pba - adapter->max_frame_size / 512;
7723 if (dmac_thr < pba - 10)
7724 dmac_thr = pba - 10;
b6e0c419
CW		 7725 reg = rd32(E1000_DMACR);
7726 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7727 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7728 & E1000_DMACR_DMACTHR_MASK);
7729
7730 /* transition to L0x or L1 if available..*/
7731 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7732
7733 /* watchdog timer= +-1000 usec in 32usec intervals */
7734 reg |= (1000 >> 5);
0c02dd98
MV		 7735
7736 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7737 if (hw->mac.type != e1000_i354)
7738 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7739
b6e0c419
CW		 7740 wr32(E1000_DMACR, reg);
7741
b980ac18 7742 /* no lower threshold to disable
b6e0c419
CW		 7743 * coalescing(smart fifb)-UTRESH=0
7744 */
7745 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7746
7747 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7748
7749 wr32(E1000_DMCTLX, reg);
7750
b980ac18 7751 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7752 * DMA coal
7753 */
7754 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7755 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7756
b980ac18 7757 /* make low power state decision controlled
b6e0c419
CW		 7758 * by DMA coal
7759 */
7760 reg = rd32(E1000_PCIEMISC);
7761 reg &= ~E1000_PCIEMISC_LX_DECISION;
7762 wr32(E1000_PCIEMISC, reg);
7763 } /* endif adapter->dmac is not disabled */
7764 } else if (hw->mac.type == e1000_82580) {
7765 u32 reg = rd32(E1000_PCIEMISC);
7766 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7767 wr32(E1000_DMACR, 0);
7768 }
7769}
7770
b980ac18
JK		 7771/**
7772 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 7773 * @hw: pointer to hardware structure
7774 * @byte_offset: byte offset to read
7775 * @dev_addr: device address
7776 * @data: value read
7777 *
7778 * Performs byte read operation over I2C interface at
7779 * a specified device address.
b980ac18 7780 **/
441fc6fd 7781s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7782 u8 dev_addr, u8 *data)
441fc6fd
CW		 7783{
7784 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7785 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7786 s32 status;
7787 u16 swfw_mask = 0;
7788
7789 if (!this_client)
7790 return E1000_ERR_I2C;
7791
7792 swfw_mask = E1000_SWFW_PHY0_SM;
7793
7794 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7795 != E1000_SUCCESS)
7796 return E1000_ERR_SWFW_SYNC;
7797
7798 status = i2c_smbus_read_byte_data(this_client, byte_offset);
7799 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7800
7801 if (status < 0)
7802 return E1000_ERR_I2C;
7803 else {
7804 *data = status;
7805 return E1000_SUCCESS;
7806 }
7807}
7808
b980ac18
JK		 7809/**
7810 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 7811 * @hw: pointer to hardware structure
7812 * @byte_offset: byte offset to write
7813 * @dev_addr: device address
7814 * @data: value to write
7815 *
7816 * Performs byte write operation over I2C interface at
7817 * a specified device address.
b980ac18 7818 **/
441fc6fd 7819s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 7820 u8 dev_addr, u8 data)
441fc6fd
CW		 7821{
7822 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 7823 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 7824 s32 status;
7825 u16 swfw_mask = E1000_SWFW_PHY0_SM;
7826
7827 if (!this_client)
7828 return E1000_ERR_I2C;
7829
7830 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7831 return E1000_ERR_SWFW_SYNC;
7832 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7833 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7834
7835 if (status)
7836 return E1000_ERR_I2C;
7837 else
7838 return E1000_SUCCESS;
7839
7840}
9d5c8243 7841/* igb_main.c */
Linux kernel - Deliverables
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