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fm10k: Increase the timeout for the data path reset
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
bf22a6bd 60#define MIN 2
b5d130c4 61#define BUILD 15
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 182#endif
9d5c8243 183
9d5c8243 184#ifdef CONFIG_PM
d9dd966d 185#ifdef CONFIG_PM_SLEEP
749ab2cd 186static int igb_suspend(struct device *);
d9dd966d 187#endif
749ab2cd 188static int igb_resume(struct device *);
749ab2cd
YZ		 189static int igb_runtime_suspend(struct device *dev);
190static int igb_runtime_resume(struct device *dev);
191static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 192static const struct dev_pm_ops igb_pm_ops = {
193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
195 igb_runtime_idle)
196};
9d5c8243
AK		 197#endif
198static void igb_shutdown(struct pci_dev *);
fa44f2f1 199static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 200#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 201static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202static struct notifier_block dca_notifier = {
203 .notifier_call = igb_notify_dca,
204 .next = NULL,
205 .priority = 0
206};
207#endif
9d5c8243
AK		 208#ifdef CONFIG_NET_POLL_CONTROLLER
209/* for netdump / net console */
210static void igb_netpoll(struct net_device *);
211#endif
37680117 212#ifdef CONFIG_PCI_IOV
6dd6d2b7 213static unsigned int max_vfs;
2a3abf6d 214module_param(max_vfs, uint, 0);
c75c4edf 215MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 216#endif /* CONFIG_PCI_IOV */
217
9d5c8243
AK		 218static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221static void igb_io_resume(struct pci_dev *);
222
3646f0e5 223static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227};
228
b6e0c419 229static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 230
231static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
9f9a12f8 235 .remove = igb_remove,
9d5c8243 236#ifdef CONFIG_PM
749ab2cd 237 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 238#endif
239 .shutdown = igb_shutdown,
fa44f2f1 240 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 241 .err_handler = &igb_err_handler
242};
243
244MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246MODULE_LICENSE("GPL");
247MODULE_VERSION(DRV_VERSION);
248
b3f4d599 249#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250static int debug = -1;
251module_param(debug, int, 0);
252MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
c97ec42a
TI		 254struct igb_reg_info {
255 u32 ofs;
256 char *name;
257};
258
259static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293};
294
b980ac18 295/* igb_regdump - register printout routine */
c97ec42a
TI		 296static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297{
298 int n = 0;
299 char rname[16];
300 u32 regs[8];
301
302 switch (reginfo->ofs) {
303 case E1000_RDLEN(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_RDLEN(n));
306 break;
307 case E1000_RDH(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDH(n));
310 break;
311 case E1000_RDT(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDT(n));
314 break;
315 case E1000_RXDCTL(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RXDCTL(n));
318 break;
319 case E1000_RDBAL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RDBAL(n));
322 break;
323 case E1000_RDBAH(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAH(n));
326 break;
327 case E1000_TDBAL(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAL(n));
330 break;
331 case E1000_TDBAH(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_TDBAH(n));
334 break;
335 case E1000_TDLEN(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDLEN(n));
338 break;
339 case E1000_TDH(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDH(n));
342 break;
343 case E1000_TDT(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDT(n));
346 break;
347 case E1000_TXDCTL(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TXDCTL(n));
350 break;
351 default:
876d2d6f 352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 353 return;
354 }
355
356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 regs[2], regs[3]);
c97ec42a
TI		 359}
360
b980ac18 361/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 362static void igb_dump(struct igb_adapter *adapter)
363{
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
c97ec42a
TI		 367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
6ad4edfc 373 u16 i, n;
c97ec42a
TI		 374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 381 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 388 pr_info(" Register Name Value\n");
c97ec42a
TI		 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 400 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 401 struct igb_tx_buffer *buffer_info;
c97ec42a 402 tx_ring = adapter->tx_ring[n];
06034649 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
c97ec42a
TI		 410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
c75c4edf 434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 435
436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 437 const char *next_desc;
06034649 438 struct igb_tx_buffer *buffer_info;
60136906 439 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 440 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 441 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 442 if (i == tx_ring->next_to_use &&
443 i == tx_ring->next_to_clean)
444 next_desc = " NTC/U";
445 else if (i == tx_ring->next_to_use)
446 next_desc = " NTU";
447 else if (i == tx_ring->next_to_clean)
448 next_desc = " NTC";
449 else
450 next_desc = "";
451
c75c4edf
CW		 452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
453 i, le64_to_cpu(u0->a),
c97ec42a 454 le64_to_cpu(u0->b),
c9f14bf3
AD		 455 (u64)dma_unmap_addr(buffer_info, dma),
456 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 457 buffer_info->next_to_watch,
458 (u64)buffer_info->time_stamp,
876d2d6f 459 buffer_info->skb, next_desc);
c97ec42a 460
b669588a 461 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 462 print_hex_dump(KERN_INFO, "",
463 DUMP_PREFIX_ADDRESS,
b669588a 464 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 465 dma_unmap_len(buffer_info, len),
466 true);
c97ec42a
TI		 467 }
468 }
469
470 /* Print RX Rings Summary */
471rx_ring_summary:
472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 473 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 474 for (n = 0; n < adapter->num_rx_queues; n++) {
475 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 476 pr_info(" %5d %5X %5X\n",
477 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 478 }
479
480 /* Print RX Rings */
481 if (!netif_msg_rx_status(adapter))
482 goto exit;
483
484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
485
486 /* Advanced Receive Descriptor (Read) Format
487 * 63 1 0
488 * +-----------------------------------------------------+
489 * 0 | Packet Buffer Address [63:1] |A0/NSE|
490 * +----------------------------------------------+------+
491 * 8 | Header Buffer Address [63:1] | DD |
492 * +-----------------------------------------------------+
493 *
494 *
495 * Advanced Receive Descriptor (Write-Back) Format
496 *
497 * 63 48 47 32 31 30 21 20 17 16 4 3 0
498 * +------------------------------------------------------+
499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
500 * | Checksum Ident | | | | Type | Type |
501 * +------------------------------------------------------+
502 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 * +------------------------------------------------------+
504 * 63 48 47 32 31 20 19 0
505 */
506
507 for (n = 0; n < adapter->num_rx_queues; n++) {
508 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 509 pr_info("------------------------------------\n");
510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
511 pr_info("------------------------------------\n");
c75c4edf
CW		 512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 514
515 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 516 const char *next_desc;
06034649
AD		 517 struct igb_rx_buffer *buffer_info;
518 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 519 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 520 u0 = (struct my_u0 *)rx_desc;
521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 522
523 if (i == rx_ring->next_to_use)
524 next_desc = " NTU";
525 else if (i == rx_ring->next_to_clean)
526 next_desc = " NTC";
527 else
528 next_desc = "";
529
c97ec42a
TI		 530 if (staterr & E1000_RXD_STAT_DD) {
531 /* Descriptor Done */
1a1c225b
AD		 532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
533 "RWB", i,
c97ec42a
TI		 534 le64_to_cpu(u0->a),
535 le64_to_cpu(u0->b),
1a1c225b 536 next_desc);
c97ec42a 537 } else {
1a1c225b
AD		 538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
539 "R ", i,
c97ec42a
TI		 540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
542 (u64)buffer_info->dma,
1a1c225b 543 next_desc);
c97ec42a 544
b669588a 545 if (netif_msg_pktdata(adapter) &&
1a1c225b 546 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 547 print_hex_dump(KERN_INFO, "",
548 DUMP_PREFIX_ADDRESS,
549 16, 1,
b669588a
ET		 550 page_address(buffer_info->page) +
551 buffer_info->page_offset,
de78d1f9 552 IGB_RX_BUFSZ, true);
c97ec42a
TI		 553 }
554 }
c97ec42a
TI		 555 }
556 }
557
558exit:
559 return;
560}
561
b980ac18
JK		 562/**
563 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 564 * @hw: pointer to hardware structure
565 * @i2cctl: Current value of I2CCTL register
566 *
567 * Returns the I2C data bit value
b980ac18 568 **/
441fc6fd
CW		 569static int igb_get_i2c_data(void *data)
570{
571 struct igb_adapter *adapter = (struct igb_adapter *)data;
572 struct e1000_hw *hw = &adapter->hw;
573 s32 i2cctl = rd32(E1000_I2CPARAMS);
574
da1f1dfe 575 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 576}
577
b980ac18
JK		 578/**
579 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 580 * @data: pointer to hardware structure
581 * @state: I2C data value (0 or 1) to set
582 *
583 * Sets the I2C data bit
b980ac18 584 **/
441fc6fd
CW		 585static void igb_set_i2c_data(void *data, int state)
586{
587 struct igb_adapter *adapter = (struct igb_adapter *)data;
588 struct e1000_hw *hw = &adapter->hw;
589 s32 i2cctl = rd32(E1000_I2CPARAMS);
590
591 if (state)
592 i2cctl |= E1000_I2C_DATA_OUT;
593 else
594 i2cctl &= ~E1000_I2C_DATA_OUT;
595
596 i2cctl &= ~E1000_I2C_DATA_OE_N;
597 i2cctl |= E1000_I2C_CLK_OE_N;
598 wr32(E1000_I2CPARAMS, i2cctl);
599 wrfl();
600
601}
602
b980ac18
JK		 603/**
604 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 605 * @data: pointer to hardware structure
606 * @state: state to set clock
607 *
608 * Sets the I2C clock line to state
b980ac18 609 **/
441fc6fd
CW		 610static void igb_set_i2c_clk(void *data, int state)
611{
612 struct igb_adapter *adapter = (struct igb_adapter *)data;
613 struct e1000_hw *hw = &adapter->hw;
614 s32 i2cctl = rd32(E1000_I2CPARAMS);
615
616 if (state) {
617 i2cctl |= E1000_I2C_CLK_OUT;
618 i2cctl &= ~E1000_I2C_CLK_OE_N;
619 } else {
620 i2cctl &= ~E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 }
623 wr32(E1000_I2CPARAMS, i2cctl);
624 wrfl();
625}
626
b980ac18
JK		 627/**
628 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 629 * @data: pointer to hardware structure
630 *
631 * Gets the I2C clock state
b980ac18 632 **/
441fc6fd
CW		 633static int igb_get_i2c_clk(void *data)
634{
635 struct igb_adapter *adapter = (struct igb_adapter *)data;
636 struct e1000_hw *hw = &adapter->hw;
637 s32 i2cctl = rd32(E1000_I2CPARAMS);
638
da1f1dfe 639 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 640}
641
642static const struct i2c_algo_bit_data igb_i2c_algo = {
643 .setsda = igb_set_i2c_data,
644 .setscl = igb_set_i2c_clk,
645 .getsda = igb_get_i2c_data,
646 .getscl = igb_get_i2c_clk,
647 .udelay = 5,
648 .timeout = 20,
649};
650
9d5c8243 651/**
b980ac18
JK		 652 * igb_get_hw_dev - return device
653 * @hw: pointer to hardware structure
654 *
655 * used by hardware layer to print debugging information
9d5c8243 656 **/
c041076a 657struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 658{
659 struct igb_adapter *adapter = hw->back;
c041076a 660 return adapter->netdev;
9d5c8243 661}
38c845c7 662
9d5c8243 663/**
b980ac18 664 * igb_init_module - Driver Registration Routine
9d5c8243 665 *
b980ac18
JK		 666 * igb_init_module is the first routine called when the driver is
667 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 668 **/
669static int __init igb_init_module(void)
670{
671 int ret;
9005df38 672
876d2d6f 673 pr_info("%s - version %s\n",
9d5c8243 674 igb_driver_string, igb_driver_version);
876d2d6f 675 pr_info("%s\n", igb_copyright);
9d5c8243 676
421e02f0 677#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 678 dca_register_notify(&dca_notifier);
679#endif
bbd98fe4 680 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 681 return ret;
682}
683
684module_init(igb_init_module);
685
686/**
b980ac18 687 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 688 *
b980ac18
JK		 689 * igb_exit_module is called just before the driver is removed
690 * from memory.
9d5c8243
AK		 691 **/
692static void __exit igb_exit_module(void)
693{
421e02f0 694#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 695 dca_unregister_notify(&dca_notifier);
696#endif
9d5c8243
AK		 697 pci_unregister_driver(&igb_driver);
698}
699
700module_exit(igb_exit_module);
701
26bc19ec
AD		 702#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703/**
b980ac18
JK		 704 * igb_cache_ring_register - Descriptor ring to register mapping
705 * @adapter: board private structure to initialize
26bc19ec 706 *
b980ac18
JK		 707 * Once we know the feature-set enabled for the device, we'll cache
708 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 709 **/
710static void igb_cache_ring_register(struct igb_adapter *adapter)
711{
ee1b9f06 712 int i = 0, j = 0;
047e0030 713 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 714
715 switch (adapter->hw.mac.type) {
716 case e1000_82576:
717 /* The queues are allocated for virtualization such that VF 0
718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 * In order to avoid collision we start at the first free queue
720 * and continue consuming queues in the same sequence
721 */
ee1b9f06 722 if (adapter->vfs_allocated_count) {
a99955fc 723 for (; i < adapter->rss_queues; i++)
3025a446 724 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 725 Q_IDX_82576(i);
ee1b9f06 726 }
b26141d4 727 /* Fall through */
26bc19ec 728 case e1000_82575:
55cac248 729 case e1000_82580:
d2ba2ed8 730 case e1000_i350:
ceb5f13b 731 case e1000_i354:
f96a8a0b
CW		 732 case e1000_i210:
733 case e1000_i211:
b26141d4 734 /* Fall through */
26bc19ec 735 default:
ee1b9f06 736 for (; i < adapter->num_rx_queues; i++)
3025a446 737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 738 for (; j < adapter->num_tx_queues; j++)
3025a446 739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 740 break;
741 }
742}
743
22a8b291
FT		 744u32 igb_rd32(struct e1000_hw *hw, u32 reg)
745{
746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
748 u32 value = 0;
749
750 if (E1000_REMOVED(hw_addr))
751 return ~value;
752
753 value = readl(&hw_addr[reg]);
754
755 /* reads should not return all F's */
756 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
757 struct net_device *netdev = igb->netdev;
758 hw->hw_addr = NULL;
759 netif_device_detach(netdev);
760 netdev_err(netdev, "PCIe link lost, device now detached\n");
761 }
762
763 return value;
764}
765
4be000c8
AD		 766/**
767 * igb_write_ivar - configure ivar for given MSI-X vector
768 * @hw: pointer to the HW structure
769 * @msix_vector: vector number we are allocating to a given ring
770 * @index: row index of IVAR register to write within IVAR table
771 * @offset: column offset of in IVAR, should be multiple of 8
772 *
773 * This function is intended to handle the writing of the IVAR register
774 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
775 * each containing an cause allocation for an Rx and Tx ring, and a
776 * variable number of rows depending on the number of queues supported.
777 **/
778static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
779 int index, int offset)
780{
781 u32 ivar = array_rd32(E1000_IVAR0, index);
782
783 /* clear any bits that are currently set */
784 ivar &= ~((u32)0xFF << offset);
785
786 /* write vector and valid bit */
787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
788
789 array_wr32(E1000_IVAR0, index, ivar);
790}
791
9d5c8243 792#define IGB_N0_QUEUE -1
047e0030 793static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 794{
047e0030 795 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 796 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 797 int rx_queue = IGB_N0_QUEUE;
798 int tx_queue = IGB_N0_QUEUE;
4be000c8 799 u32 msixbm = 0;
047e0030 800
0ba82994
AD		 801 if (q_vector->rx.ring)
802 rx_queue = q_vector->rx.ring->reg_idx;
803 if (q_vector->tx.ring)
804 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 805
806 switch (hw->mac.type) {
807 case e1000_82575:
9d5c8243 808 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 809 * bitmask for the EICR/EIMS/EIMC registers. To assign one
810 * or more queues to a vector, we write the appropriate bits
811 * into the MSIXBM register for that vector.
812 */
047e0030 813 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 815 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 818 msixbm |= E1000_EIMS_OTHER;
9d5c8243 819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 820 q_vector->eims_value = msixbm;
2d064c06
AD		 821 break;
822 case e1000_82576:
b980ac18 823 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 824 * with 8 rows. The ordering is column-major so we use the
825 * lower 3 bits as the row index, and the 4th bit as the
826 * column offset.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue & 0x7,
831 (rx_queue & 0x8) << 1);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue & 0x7,
835 ((tx_queue & 0x8) << 1) + 8);
047e0030 836 q_vector->eims_value = 1 << msix_vector;
2d064c06 837 break;
55cac248 838 case e1000_82580:
d2ba2ed8 839 case e1000_i350:
ceb5f13b 840 case e1000_i354:
f96a8a0b
CW		 841 case e1000_i210:
842 case e1000_i211:
b980ac18 843 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 844 * however instead of ordering column-major we have things
845 * ordered row-major. So we traverse the table by using
846 * bit 0 as the column offset, and the remaining bits as the
847 * row index.
848 */
849 if (rx_queue > IGB_N0_QUEUE)
850 igb_write_ivar(hw, msix_vector,
851 rx_queue >> 1,
852 (rx_queue & 0x1) << 4);
853 if (tx_queue > IGB_N0_QUEUE)
854 igb_write_ivar(hw, msix_vector,
855 tx_queue >> 1,
856 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 857 q_vector->eims_value = 1 << msix_vector;
858 break;
2d064c06
AD		 859 default:
860 BUG();
861 break;
862 }
26b39276
AD		 863
864 /* add q_vector eims value to global eims_enable_mask */
865 adapter->eims_enable_mask |= q_vector->eims_value;
866
867 /* configure q_vector to set itr on first interrupt */
868 q_vector->set_itr = 1;
9d5c8243
AK		 869}
870
871/**
b980ac18
JK		 872 * igb_configure_msix - Configure MSI-X hardware
873 * @adapter: board private structure to initialize
9d5c8243 874 *
b980ac18
JK		 875 * igb_configure_msix sets up the hardware to properly
876 * generate MSI-X interrupts.
9d5c8243
AK		 877 **/
878static void igb_configure_msix(struct igb_adapter *adapter)
879{
880 u32 tmp;
881 int i, vector = 0;
882 struct e1000_hw *hw = &adapter->hw;
883
884 adapter->eims_enable_mask = 0;
9d5c8243
AK		 885
886 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 887 switch (hw->mac.type) {
888 case e1000_82575:
9d5c8243
AK		 889 tmp = rd32(E1000_CTRL_EXT);
890 /* enable MSI-X PBA support*/
891 tmp |= E1000_CTRL_EXT_PBA_CLR;
892
893 /* Auto-Mask interrupts upon ICR read. */
894 tmp |= E1000_CTRL_EXT_EIAME;
895 tmp |= E1000_CTRL_EXT_IRCA;
896
897 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 898
899 /* enable msix_other interrupt */
b980ac18 900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 901 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 902
2d064c06
AD		 903 break;
904
905 case e1000_82576:
55cac248 906 case e1000_82580:
d2ba2ed8 907 case e1000_i350:
ceb5f13b 908 case e1000_i354:
f96a8a0b
CW		 909 case e1000_i210:
910 case e1000_i211:
047e0030 911 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 912 * won't stick. And it will take days to debug.
913 */
047e0030 914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 915 E1000_GPIE_PBA | E1000_GPIE_EIAME |
916 E1000_GPIE_NSICR);
047e0030
AD		 917
918 /* enable msix_other interrupt */
919 adapter->eims_other = 1 << vector;
2d064c06 920 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 921
047e0030 922 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 923 break;
924 default:
925 /* do nothing, since nothing else supports MSI-X */
926 break;
927 } /* switch (hw->mac.type) */
047e0030
AD		 928
929 adapter->eims_enable_mask |= adapter->eims_other;
930
26b39276
AD		 931 for (i = 0; i < adapter->num_q_vectors; i++)
932 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 933
9d5c8243
AK		 934 wrfl();
935}
936
937/**
b980ac18
JK		 938 * igb_request_msix - Initialize MSI-X interrupts
939 * @adapter: board private structure to initialize
9d5c8243 940 *
b980ac18
JK		 941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
942 * kernel.
9d5c8243
AK		 943 **/
944static int igb_request_msix(struct igb_adapter *adapter)
945{
946 struct net_device *netdev = adapter->netdev;
047e0030 947 struct e1000_hw *hw = &adapter->hw;
52285b76 948 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 949
047e0030 950 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 951 igb_msix_other, 0, netdev->name, adapter);
047e0030 952 if (err)
52285b76 953 goto err_out;
047e0030
AD		 954
955 for (i = 0; i < adapter->num_q_vectors; i++) {
956 struct igb_q_vector *q_vector = adapter->q_vector[i];
957
52285b76
SA		 958 vector++;
959
047e0030
AD		 960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
961
0ba82994 962 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 964 q_vector->rx.ring->queue_index);
965 else if (q_vector->tx.ring)
047e0030 966 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 967 q_vector->tx.ring->queue_index);
968 else if (q_vector->rx.ring)
047e0030 969 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 970 q_vector->rx.ring->queue_index);
9d5c8243 971 else
047e0030
AD		 972 sprintf(q_vector->name, "%s-unused", netdev->name);
973
9d5c8243 974 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 975 igb_msix_ring, 0, q_vector->name,
976 q_vector);
9d5c8243 977 if (err)
52285b76 978 goto err_free;
9d5c8243
AK		 979 }
980
9d5c8243
AK		 981 igb_configure_msix(adapter);
982 return 0;
52285b76
SA		 983
984err_free:
985 /* free already assigned IRQs */
986 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
987
988 vector--;
989 for (i = 0; i < vector; i++) {
990 free_irq(adapter->msix_entries[free_vector++].vector,
991 adapter->q_vector[i]);
992 }
993err_out:
9d5c8243
AK		 994 return err;
995}
996
5536d210 997/**
b980ac18
JK		 998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
5536d210 1001 *
02ef6e1d 1002 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1003 **/
1004static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005{
1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007
02ef6e1d
CW		 1008 adapter->q_vector[v_idx] = NULL;
1009
1010 /* igb_get_stats64() might access the rings on this vector,
1011 * we must wait a grace period before freeing it.
1012 */
17a402a0
CW		 1013 if (q_vector)
1014 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1015}
1016
1017/**
1018 * igb_reset_q_vector - Reset config for interrupt vector
1019 * @adapter: board private structure to initialize
1020 * @v_idx: Index of vector to be reset
1021 *
1022 * If NAPI is enabled it will delete any references to the
1023 * NAPI struct. This is preparation for igb_free_q_vector.
1024 **/
1025static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1026{
1027 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1028
cb06d102
CP		 1029 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1030 * allocated. So, q_vector is NULL so we should stop here.
1031 */
1032 if (!q_vector)
1033 return;
1034
5536d210
AD		 1035 if (q_vector->tx.ring)
1036 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1037
1038 if (q_vector->rx.ring)
1039 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1040
5536d210
AD		 1041 netif_napi_del(&q_vector->napi);
1042
02ef6e1d
CW		 1043}
1044
1045static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1046{
1047 int v_idx = adapter->num_q_vectors;
1048
cd14ef54 1049 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1050 pci_disable_msix(adapter->pdev);
cd14ef54 1051 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1052 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1053
1054 while (v_idx--)
1055 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1056}
1057
047e0030 1058/**
b980ac18
JK		 1059 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1060 * @adapter: board private structure to initialize
047e0030 1061 *
b980ac18
JK		 1062 * This function frees the memory allocated to the q_vectors. In addition if
1063 * NAPI is enabled it will delete any references to the NAPI struct prior
1064 * to freeing the q_vector.
047e0030
AD		 1065 **/
1066static void igb_free_q_vectors(struct igb_adapter *adapter)
1067{
5536d210
AD		 1068 int v_idx = adapter->num_q_vectors;
1069
1070 adapter->num_tx_queues = 0;
1071 adapter->num_rx_queues = 0;
047e0030 1072 adapter->num_q_vectors = 0;
5536d210 1073
02ef6e1d
CW		 1074 while (v_idx--) {
1075 igb_reset_q_vector(adapter, v_idx);
5536d210 1076 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1077 }
047e0030
AD		 1078}
1079
1080/**
b980ac18
JK		 1081 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1082 * @adapter: board private structure to initialize
047e0030 1083 *
b980ac18
JK		 1084 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1085 * MSI-X interrupts allocated.
047e0030
AD		 1086 */
1087static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1088{
047e0030
AD		 1089 igb_free_q_vectors(adapter);
1090 igb_reset_interrupt_capability(adapter);
1091}
9d5c8243
AK		 1092
1093/**
b980ac18
JK		 1094 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1095 * @adapter: board private structure to initialize
1096 * @msix: boolean value of MSIX capability
9d5c8243 1097 *
b980ac18
JK		 1098 * Attempt to configure interrupts using the best available
1099 * capabilities of the hardware and kernel.
9d5c8243 1100 **/
53c7d064 1101static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1102{
1103 int err;
1104 int numvecs, i;
1105
53c7d064
SA		 1106 if (!msix)
1107 goto msi_only;
cd14ef54 1108 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1109
83b7180d 1110 /* Number of supported queues. */
a99955fc 1111 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1112 if (adapter->vfs_allocated_count)
1113 adapter->num_tx_queues = 1;
1114 else
1115 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1116
b980ac18 1117 /* start with one vector for every Rx queue */
047e0030
AD		 1118 numvecs = adapter->num_rx_queues;
1119
b980ac18 1120 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1121 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1122 numvecs += adapter->num_tx_queues;
047e0030
AD		 1123
1124 /* store the number of vectors reserved for queues */
1125 adapter->num_q_vectors = numvecs;
1126
1127 /* add 1 vector for link status interrupts */
1128 numvecs++;
9d5c8243
AK		 1129 for (i = 0; i < numvecs; i++)
1130 adapter->msix_entries[i].entry = i;
1131
479d02df
AG		 1132 err = pci_enable_msix_range(adapter->pdev,
1133 adapter->msix_entries,
1134 numvecs,
1135 numvecs);
1136 if (err > 0)
0c2cc02e 1137 return;
9d5c8243
AK		 1138
1139 igb_reset_interrupt_capability(adapter);
1140
1141 /* If we can't do MSI-X, try MSI */
1142msi_only:
b709323d 1143 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1144#ifdef CONFIG_PCI_IOV
1145 /* disable SR-IOV for non MSI-X configurations */
1146 if (adapter->vf_data) {
1147 struct e1000_hw *hw = &adapter->hw;
1148 /* disable iov and allow time for transactions to clear */
1149 pci_disable_sriov(adapter->pdev);
1150 msleep(500);
1151
1152 kfree(adapter->vf_data);
1153 adapter->vf_data = NULL;
1154 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1155 wrfl();
2a3abf6d
AD		 1156 msleep(100);
1157 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1158 }
1159#endif
4fc82adf 1160 adapter->vfs_allocated_count = 0;
a99955fc 1161 adapter->rss_queues = 1;
4fc82adf 1162 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1163 adapter->num_rx_queues = 1;
661086df 1164 adapter->num_tx_queues = 1;
047e0030 1165 adapter->num_q_vectors = 1;
9d5c8243 1166 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1167 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1168}
1169
5536d210
AD		 1170static void igb_add_ring(struct igb_ring *ring,
1171 struct igb_ring_container *head)
1172{
1173 head->ring = ring;
1174 head->count++;
1175}
1176
047e0030 1177/**
b980ac18
JK		 1178 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1179 * @adapter: board private structure to initialize
1180 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1181 * @v_idx: index of vector in adapter struct
1182 * @txr_count: total number of Tx rings to allocate
1183 * @txr_idx: index of first Tx ring to allocate
1184 * @rxr_count: total number of Rx rings to allocate
1185 * @rxr_idx: index of first Rx ring to allocate
047e0030 1186 *
b980ac18 1187 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1188 **/
5536d210
AD		 1189static int igb_alloc_q_vector(struct igb_adapter *adapter,
1190 int v_count, int v_idx,
1191 int txr_count, int txr_idx,
1192 int rxr_count, int rxr_idx)
047e0030
AD		 1193{
1194 struct igb_q_vector *q_vector;
5536d210
AD		 1195 struct igb_ring *ring;
1196 int ring_count, size;
047e0030 1197
5536d210
AD		 1198 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1199 if (txr_count > 1 || rxr_count > 1)
1200 return -ENOMEM;
1201
1202 ring_count = txr_count + rxr_count;
1203 size = sizeof(struct igb_q_vector) +
1204 (sizeof(struct igb_ring) * ring_count);
1205
1206 /* allocate q_vector and rings */
02ef6e1d
CW		 1207 q_vector = adapter->q_vector[v_idx];
1208 if (!q_vector)
1209 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1210 if (!q_vector)
1211 return -ENOMEM;
1212
1213 /* initialize NAPI */
1214 netif_napi_add(adapter->netdev, &q_vector->napi,
1215 igb_poll, 64);
1216
1217 /* tie q_vector and adapter together */
1218 adapter->q_vector[v_idx] = q_vector;
1219 q_vector->adapter = adapter;
1220
1221 /* initialize work limits */
1222 q_vector->tx.work_limit = adapter->tx_work_limit;
1223
1224 /* initialize ITR configuration */
1225 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1226 q_vector->itr_val = IGB_START_ITR;
1227
1228 /* initialize pointer to rings */
1229 ring = q_vector->ring;
1230
4e227667
AD		 1231 /* intialize ITR */
1232 if (rxr_count) {
1233 /* rx or rx/tx vector */
1234 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1235 q_vector->itr_val = adapter->rx_itr_setting;
1236 } else {
1237 /* tx only vector */
1238 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1239 q_vector->itr_val = adapter->tx_itr_setting;
1240 }
1241
5536d210
AD		 1242 if (txr_count) {
1243 /* assign generic ring traits */
1244 ring->dev = &adapter->pdev->dev;
1245 ring->netdev = adapter->netdev;
1246
1247 /* configure backlink on ring */
1248 ring->q_vector = q_vector;
1249
1250 /* update q_vector Tx values */
1251 igb_add_ring(ring, &q_vector->tx);
1252
1253 /* For 82575, context index must be unique per ring. */
1254 if (adapter->hw.mac.type == e1000_82575)
1255 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1256
1257 /* apply Tx specific ring traits */
1258 ring->count = adapter->tx_ring_count;
1259 ring->queue_index = txr_idx;
1260
827da44c
JS		 1261 u64_stats_init(&ring->tx_syncp);
1262 u64_stats_init(&ring->tx_syncp2);
1263
5536d210
AD		 1264 /* assign ring to adapter */
1265 adapter->tx_ring[txr_idx] = ring;
1266
1267 /* push pointer to next ring */
1268 ring++;
047e0030 1269 }
81c2fc22 1270
5536d210
AD		 1271 if (rxr_count) {
1272 /* assign generic ring traits */
1273 ring->dev = &adapter->pdev->dev;
1274 ring->netdev = adapter->netdev;
047e0030 1275
5536d210
AD		 1276 /* configure backlink on ring */
1277 ring->q_vector = q_vector;
047e0030 1278
5536d210
AD		 1279 /* update q_vector Rx values */
1280 igb_add_ring(ring, &q_vector->rx);
047e0030 1281
5536d210
AD		 1282 /* set flag indicating ring supports SCTP checksum offload */
1283 if (adapter->hw.mac.type >= e1000_82576)
1284 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1285
e52c0f96 1286 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1287 * have the tag byte-swapped.
b980ac18 1288 */
5536d210
AD		 1289 if (adapter->hw.mac.type >= e1000_i350)
1290 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1291
5536d210
AD		 1292 /* apply Rx specific ring traits */
1293 ring->count = adapter->rx_ring_count;
1294 ring->queue_index = rxr_idx;
1295
827da44c
JS		 1296 u64_stats_init(&ring->rx_syncp);
1297
5536d210
AD		 1298 /* assign ring to adapter */
1299 adapter->rx_ring[rxr_idx] = ring;
1300 }
1301
1302 return 0;
047e0030
AD		 1303}
1304
5536d210 1305
047e0030 1306/**
b980ac18
JK		 1307 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1308 * @adapter: board private structure to initialize
047e0030 1309 *
b980ac18
JK		 1310 * We allocate one q_vector per queue interrupt. If allocation fails we
1311 * return -ENOMEM.
047e0030 1312 **/
5536d210 1313static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1314{
5536d210
AD		 1315 int q_vectors = adapter->num_q_vectors;
1316 int rxr_remaining = adapter->num_rx_queues;
1317 int txr_remaining = adapter->num_tx_queues;
1318 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1319 int err;
047e0030 1320
5536d210
AD		 1321 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1322 for (; rxr_remaining; v_idx++) {
1323 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1324 0, 0, 1, rxr_idx);
047e0030 1325
5536d210
AD		 1326 if (err)
1327 goto err_out;
1328
1329 /* update counts and index */
1330 rxr_remaining--;
1331 rxr_idx++;
047e0030 1332 }
047e0030 1333 }
5536d210
AD		 1334
1335 for (; v_idx < q_vectors; v_idx++) {
1336 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1337 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1338
5536d210
AD		 1339 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1340 tqpv, txr_idx, rqpv, rxr_idx);
1341
1342 if (err)
1343 goto err_out;
1344
1345 /* update counts and index */
1346 rxr_remaining -= rqpv;
1347 txr_remaining -= tqpv;
1348 rxr_idx++;
1349 txr_idx++;
1350 }
1351
047e0030 1352 return 0;
5536d210
AD		 1353
1354err_out:
1355 adapter->num_tx_queues = 0;
1356 adapter->num_rx_queues = 0;
1357 adapter->num_q_vectors = 0;
1358
1359 while (v_idx--)
1360 igb_free_q_vector(adapter, v_idx);
1361
1362 return -ENOMEM;
047e0030
AD		 1363}
1364
1365/**
b980ac18
JK		 1366 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1367 * @adapter: board private structure to initialize
1368 * @msix: boolean value of MSIX capability
047e0030 1369 *
b980ac18 1370 * This function initializes the interrupts and allocates all of the queues.
047e0030 1371 **/
53c7d064 1372static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1373{
1374 struct pci_dev *pdev = adapter->pdev;
1375 int err;
1376
53c7d064 1377 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1378
1379 err = igb_alloc_q_vectors(adapter);
1380 if (err) {
1381 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1382 goto err_alloc_q_vectors;
1383 }
1384
5536d210 1385 igb_cache_ring_register(adapter);
047e0030
AD		 1386
1387 return 0;
5536d210 1388
047e0030
AD		 1389err_alloc_q_vectors:
1390 igb_reset_interrupt_capability(adapter);
1391 return err;
1392}
1393
9d5c8243 1394/**
b980ac18
JK		 1395 * igb_request_irq - initialize interrupts
1396 * @adapter: board private structure to initialize
9d5c8243 1397 *
b980ac18
JK		 1398 * Attempts to configure interrupts using the best available
1399 * capabilities of the hardware and kernel.
9d5c8243
AK		 1400 **/
1401static int igb_request_irq(struct igb_adapter *adapter)
1402{
1403 struct net_device *netdev = adapter->netdev;
047e0030 1404 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1405 int err = 0;
1406
cd14ef54 1407 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1408 err = igb_request_msix(adapter);
844290e5 1409 if (!err)
9d5c8243 1410 goto request_done;
9d5c8243 1411 /* fall back to MSI */
5536d210
AD		 1412 igb_free_all_tx_resources(adapter);
1413 igb_free_all_rx_resources(adapter);
53c7d064 1414
047e0030 1415 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1416 err = igb_init_interrupt_scheme(adapter, false);
1417 if (err)
047e0030 1418 goto request_done;
53c7d064 1419
047e0030
AD		 1420 igb_setup_all_tx_resources(adapter);
1421 igb_setup_all_rx_resources(adapter);
53c7d064 1422 igb_configure(adapter);
9d5c8243 1423 }
844290e5 1424
c74d588e
AD		 1425 igb_assign_vector(adapter->q_vector[0], 0);
1426
7dfc16fa 1427 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1428 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1429 netdev->name, adapter);
9d5c8243
AK		 1430 if (!err)
1431 goto request_done;
047e0030 1432
9d5c8243
AK		 1433 /* fall back to legacy interrupts */
1434 igb_reset_interrupt_capability(adapter);
7dfc16fa 1435 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1436 }
1437
c74d588e 1438 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1439 netdev->name, adapter);
9d5c8243 1440
6cb5e577 1441 if (err)
c74d588e 1442 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1443 err);
9d5c8243
AK		 1444
1445request_done:
1446 return err;
1447}
1448
1449static void igb_free_irq(struct igb_adapter *adapter)
1450{
cd14ef54 1451 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1452 int vector = 0, i;
1453
047e0030 1454 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1455
0d1ae7f4 1456 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1457 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1458 adapter->q_vector[i]);
047e0030
AD		 1459 } else {
1460 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1461 }
9d5c8243
AK		 1462}
1463
1464/**
b980ac18
JK		 1465 * igb_irq_disable - Mask off interrupt generation on the NIC
1466 * @adapter: board private structure
9d5c8243
AK		 1467 **/
1468static void igb_irq_disable(struct igb_adapter *adapter)
1469{
1470 struct e1000_hw *hw = &adapter->hw;
1471
b980ac18 1472 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1473 * mapped into these registers and so clearing the bits can cause
1474 * issues on the VF drivers so we only need to clear what we set
1475 */
cd14ef54 1476 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1477 u32 regval = rd32(E1000_EIAM);
9005df38 1478
2dfd1212
AD		 1479 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1480 wr32(E1000_EIMC, adapter->eims_enable_mask);
1481 regval = rd32(E1000_EIAC);
1482 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1483 }
844290e5
PW		 1484
1485 wr32(E1000_IAM, 0);
9d5c8243
AK		 1486 wr32(E1000_IMC, ~0);
1487 wrfl();
cd14ef54 1488 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1489 int i;
9005df38 1490
81a61859
ET		 1491 for (i = 0; i < adapter->num_q_vectors; i++)
1492 synchronize_irq(adapter->msix_entries[i].vector);
1493 } else {
1494 synchronize_irq(adapter->pdev->irq);
1495 }
9d5c8243
AK		 1496}
1497
1498/**
b980ac18
JK		 1499 * igb_irq_enable - Enable default interrupt generation settings
1500 * @adapter: board private structure
9d5c8243
AK		 1501 **/
1502static void igb_irq_enable(struct igb_adapter *adapter)
1503{
1504 struct e1000_hw *hw = &adapter->hw;
1505
cd14ef54 1506 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1507 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1508 u32 regval = rd32(E1000_EIAC);
9005df38 1509
2dfd1212
AD		 1510 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1511 regval = rd32(E1000_EIAM);
1512 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1513 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1514 if (adapter->vfs_allocated_count) {
4ae196df 1515 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1516 ims |= E1000_IMS_VMMB;
1517 }
1518 wr32(E1000_IMS, ims);
844290e5 1519 } else {
55cac248
AD		 1520 wr32(E1000_IMS, IMS_ENABLE_MASK |
1521 E1000_IMS_DRSTA);
1522 wr32(E1000_IAM, IMS_ENABLE_MASK |
1523 E1000_IMS_DRSTA);
844290e5 1524 }
9d5c8243
AK		 1525}
1526
1527static void igb_update_mng_vlan(struct igb_adapter *adapter)
1528{
51466239 1529 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1530 u16 vid = adapter->hw.mng_cookie.vlan_id;
1531 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1532
1533 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1534 /* add VID to filter table */
1535 igb_vfta_set(hw, vid, true);
1536 adapter->mng_vlan_id = vid;
1537 } else {
1538 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1539 }
1540
1541 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1542 (vid != old_vid) &&
b2cb09b1 1543 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1544 /* remove VID from filter table */
1545 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1546 }
1547}
1548
1549/**
b980ac18
JK		 1550 * igb_release_hw_control - release control of the h/w to f/w
1551 * @adapter: address of board private structure
9d5c8243 1552 *
b980ac18
JK		 1553 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1554 * For ASF and Pass Through versions of f/w this means that the
1555 * driver is no longer loaded.
9d5c8243
AK		 1556 **/
1557static void igb_release_hw_control(struct igb_adapter *adapter)
1558{
1559 struct e1000_hw *hw = &adapter->hw;
1560 u32 ctrl_ext;
1561
1562 /* Let firmware take over control of h/w */
1563 ctrl_ext = rd32(E1000_CTRL_EXT);
1564 wr32(E1000_CTRL_EXT,
1565 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1566}
1567
9d5c8243 1568/**
b980ac18
JK		 1569 * igb_get_hw_control - get control of the h/w from f/w
1570 * @adapter: address of board private structure
9d5c8243 1571 *
b980ac18
JK		 1572 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1573 * For ASF and Pass Through versions of f/w this means that
1574 * the driver is loaded.
9d5c8243
AK		 1575 **/
1576static void igb_get_hw_control(struct igb_adapter *adapter)
1577{
1578 struct e1000_hw *hw = &adapter->hw;
1579 u32 ctrl_ext;
1580
1581 /* Let firmware know the driver has taken over */
1582 ctrl_ext = rd32(E1000_CTRL_EXT);
1583 wr32(E1000_CTRL_EXT,
1584 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1585}
1586
9d5c8243 1587/**
b980ac18
JK		 1588 * igb_configure - configure the hardware for RX and TX
1589 * @adapter: private board structure
9d5c8243
AK		 1590 **/
1591static void igb_configure(struct igb_adapter *adapter)
1592{
1593 struct net_device *netdev = adapter->netdev;
1594 int i;
1595
1596 igb_get_hw_control(adapter);
ff41f8dc 1597 igb_set_rx_mode(netdev);
9d5c8243
AK		 1598
1599 igb_restore_vlan(adapter);
9d5c8243 1600
85b430b4 1601 igb_setup_tctl(adapter);
06cf2666 1602 igb_setup_mrqc(adapter);
9d5c8243 1603 igb_setup_rctl(adapter);
85b430b4
AD		 1604
1605 igb_configure_tx(adapter);
9d5c8243 1606 igb_configure_rx(adapter);
662d7205
AD		 1607
1608 igb_rx_fifo_flush_82575(&adapter->hw);
1609
c493ea45 1610 /* call igb_desc_unused which always leaves
9d5c8243 1611 * at least 1 descriptor unused to make sure
b980ac18
JK		 1612 * next_to_use != next_to_clean
1613 */
9d5c8243 1614 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1615 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1616 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1617 }
9d5c8243
AK		 1618}
1619
88a268c1 1620/**
b980ac18
JK		 1621 * igb_power_up_link - Power up the phy/serdes link
1622 * @adapter: address of board private structure
88a268c1
NN		 1623 **/
1624void igb_power_up_link(struct igb_adapter *adapter)
1625{
76886596
AA		 1626 igb_reset_phy(&adapter->hw);
1627
88a268c1
NN		 1628 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1629 igb_power_up_phy_copper(&adapter->hw);
1630 else
1631 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1632
1633 igb_setup_link(&adapter->hw);
88a268c1
NN		 1634}
1635
1636/**
b980ac18
JK		 1637 * igb_power_down_link - Power down the phy/serdes link
1638 * @adapter: address of board private structure
88a268c1
NN		 1639 */
1640static void igb_power_down_link(struct igb_adapter *adapter)
1641{
1642 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1643 igb_power_down_phy_copper_82575(&adapter->hw);
1644 else
1645 igb_shutdown_serdes_link_82575(&adapter->hw);
1646}
9d5c8243 1647
56cec249
CW		 1648/**
1649 * Detect and switch function for Media Auto Sense
1650 * @adapter: address of the board private structure
1651 **/
1652static void igb_check_swap_media(struct igb_adapter *adapter)
1653{
1654 struct e1000_hw *hw = &adapter->hw;
1655 u32 ctrl_ext, connsw;
1656 bool swap_now = false;
1657
1658 ctrl_ext = rd32(E1000_CTRL_EXT);
1659 connsw = rd32(E1000_CONNSW);
1660
1661 /* need to live swap if current media is copper and we have fiber/serdes
1662 * to go to.
1663 */
1664
1665 if ((hw->phy.media_type == e1000_media_type_copper) &&
1666 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1667 swap_now = true;
1668 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1669 /* copper signal takes time to appear */
1670 if (adapter->copper_tries < 4) {
1671 adapter->copper_tries++;
1672 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1673 wr32(E1000_CONNSW, connsw);
1674 return;
1675 } else {
1676 adapter->copper_tries = 0;
1677 if ((connsw & E1000_CONNSW_PHYSD) &&
1678 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1679 swap_now = true;
1680 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 }
1683 }
1684 }
1685
1686 if (!swap_now)
1687 return;
1688
1689 switch (hw->phy.media_type) {
1690 case e1000_media_type_copper:
1691 netdev_info(adapter->netdev,
1692 "MAS: changing media to fiber/serdes\n");
1693 ctrl_ext |=
1694 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1695 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1696 adapter->copper_tries = 0;
1697 break;
1698 case e1000_media_type_internal_serdes:
1699 case e1000_media_type_fiber:
1700 netdev_info(adapter->netdev,
1701 "MAS: changing media to copper\n");
1702 ctrl_ext &=
1703 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1704 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1705 break;
1706 default:
1707 /* shouldn't get here during regular operation */
1708 netdev_err(adapter->netdev,
1709 "AMS: Invalid media type found, returning\n");
1710 break;
1711 }
1712 wr32(E1000_CTRL_EXT, ctrl_ext);
1713}
1714
9d5c8243 1715/**
b980ac18
JK		 1716 * igb_up - Open the interface and prepare it to handle traffic
1717 * @adapter: board private structure
9d5c8243 1718 **/
9d5c8243
AK		 1719int igb_up(struct igb_adapter *adapter)
1720{
1721 struct e1000_hw *hw = &adapter->hw;
1722 int i;
1723
1724 /* hardware has been reset, we need to reload some things */
1725 igb_configure(adapter);
1726
1727 clear_bit(__IGB_DOWN, &adapter->state);
1728
0d1ae7f4
AD		 1729 for (i = 0; i < adapter->num_q_vectors; i++)
1730 napi_enable(&(adapter->q_vector[i]->napi));
1731
cd14ef54 1732 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1733 igb_configure_msix(adapter);
feeb2721
AD		 1734 else
1735 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1736
1737 /* Clear any pending interrupts. */
1738 rd32(E1000_ICR);
1739 igb_irq_enable(adapter);
1740
d4960307
AD		 1741 /* notify VFs that reset has been completed */
1742 if (adapter->vfs_allocated_count) {
1743 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1744
d4960307
AD		 1745 reg_data |= E1000_CTRL_EXT_PFRSTD;
1746 wr32(E1000_CTRL_EXT, reg_data);
1747 }
1748
4cb9be7a
JB		 1749 netif_tx_start_all_queues(adapter->netdev);
1750
25568a53
AD		 1751 /* start the watchdog. */
1752 hw->mac.get_link_status = 1;
1753 schedule_work(&adapter->watchdog_task);
1754
f4c01e96
CW		 1755 if ((adapter->flags & IGB_FLAG_EEE) &&
1756 (!hw->dev_spec._82575.eee_disable))
1757 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1758
9d5c8243
AK		 1759 return 0;
1760}
1761
1762void igb_down(struct igb_adapter *adapter)
1763{
9d5c8243 1764 struct net_device *netdev = adapter->netdev;
330a6d6a 1765 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1766 u32 tctl, rctl;
1767 int i;
1768
1769 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1770 * reschedule our watchdog timer
1771 */
9d5c8243
AK		 1772 set_bit(__IGB_DOWN, &adapter->state);
1773
1774 /* disable receives in the hardware */
1775 rctl = rd32(E1000_RCTL);
1776 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1777 /* flush and sleep below */
1778
fd2ea0a7 1779 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1780
1781 /* disable transmits in the hardware */
1782 tctl = rd32(E1000_TCTL);
1783 tctl &= ~E1000_TCTL_EN;
1784 wr32(E1000_TCTL, tctl);
1785 /* flush both disables and wait for them to finish */
1786 wrfl();
0d451e79 1787 usleep_range(10000, 11000);
9d5c8243 1788
41f149a2
CW		 1789 igb_irq_disable(adapter);
1790
aa9b8cc4
AA		 1791 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1792
41f149a2 1793 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1794 if (adapter->q_vector[i]) {
1795 napi_synchronize(&adapter->q_vector[i]->napi);
1796 napi_disable(&adapter->q_vector[i]->napi);
1797 }
41f149a2 1798 }
9d5c8243 1799
9d5c8243
AK		 1800
1801 del_timer_sync(&adapter->watchdog_timer);
1802 del_timer_sync(&adapter->phy_info_timer);
1803
9d5c8243 1804 netif_carrier_off(netdev);
04fe6358
AD		 1805
1806 /* record the stats before reset*/
12dcd86b
ED		 1807 spin_lock(&adapter->stats64_lock);
1808 igb_update_stats(adapter, &adapter->stats64);
1809 spin_unlock(&adapter->stats64_lock);
04fe6358 1810
9d5c8243
AK		 1811 adapter->link_speed = 0;
1812 adapter->link_duplex = 0;
1813
3023682e
JK		 1814 if (!pci_channel_offline(adapter->pdev))
1815 igb_reset(adapter);
9d5c8243
AK		 1816 igb_clean_all_tx_rings(adapter);
1817 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1818#ifdef CONFIG_IGB_DCA
1819
1820 /* since we reset the hardware DCA settings were cleared */
1821 igb_setup_dca(adapter);
1822#endif
9d5c8243
AK		 1823}
1824
1825void igb_reinit_locked(struct igb_adapter *adapter)
1826{
1827 WARN_ON(in_interrupt());
1828 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1829 usleep_range(1000, 2000);
9d5c8243
AK		 1830 igb_down(adapter);
1831 igb_up(adapter);
1832 clear_bit(__IGB_RESETTING, &adapter->state);
1833}
1834
56cec249
CW		 1835/** igb_enable_mas - Media Autosense re-enable after swap
1836 *
1837 * @adapter: adapter struct
1838 **/
1839static s32 igb_enable_mas(struct igb_adapter *adapter)
1840{
1841 struct e1000_hw *hw = &adapter->hw;
1842 u32 connsw;
1843 s32 ret_val = 0;
1844
1845 connsw = rd32(E1000_CONNSW);
1846 if (!(hw->phy.media_type == e1000_media_type_copper))
1847 return ret_val;
1848
1849 /* configure for SerDes media detect */
1850 if (!(connsw & E1000_CONNSW_SERDESD)) {
1851 connsw |= E1000_CONNSW_ENRGSRC;
1852 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1853 wr32(E1000_CONNSW, connsw);
1854 wrfl();
1855 } else if (connsw & E1000_CONNSW_SERDESD) {
1856 /* already SerDes, no need to enable anything */
1857 return ret_val;
1858 } else {
1859 netdev_info(adapter->netdev,
1860 "MAS: Unable to configure feature, disabling..\n");
1861 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1862 }
1863 return ret_val;
1864}
1865
9d5c8243
AK		 1866void igb_reset(struct igb_adapter *adapter)
1867{
090b1795 1868 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1869 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1870 struct e1000_mac_info *mac = &hw->mac;
1871 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1872 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1873
1874 /* Repartition Pba for greater than 9k mtu
1875 * To take effect CTRL.RST is required.
1876 */
fa4dfae0 1877 switch (mac->type) {
d2ba2ed8 1878 case e1000_i350:
ceb5f13b 1879 case e1000_i354:
55cac248
AD		 1880 case e1000_82580:
1881 pba = rd32(E1000_RXPBS);
1882 pba = igb_rxpbs_adjust_82580(pba);
1883 break;
fa4dfae0 1884 case e1000_82576:
d249be54
AD		 1885 pba = rd32(E1000_RXPBS);
1886 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1887 break;
1888 case e1000_82575:
f96a8a0b
CW		 1889 case e1000_i210:
1890 case e1000_i211:
fa4dfae0
AD		 1891 default:
1892 pba = E1000_PBA_34K;
1893 break;
2d064c06 1894 }
9d5c8243 1895
2d064c06
AD		 1896 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1897 (mac->type < e1000_82576)) {
9d5c8243
AK		 1898 /* adjust PBA for jumbo frames */
1899 wr32(E1000_PBA, pba);
1900
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1906 * expressed in KB.
1907 */
9d5c8243
AK		 1908 pba = rd32(E1000_PBA);
1909 /* upper 16 bits has Tx packet buffer allocation size in KB */
1910 tx_space = pba >> 16;
1911 /* lower 16 bits has Rx packet buffer allocation size in KB */
1912 pba &= 0xffff;
b980ac18
JK		 1913 /* the Tx fifo also stores 16 bytes of information about the Tx
1914 * but don't include ethernet FCS because hardware appends it
1915 */
9d5c8243 1916 min_tx_space = (adapter->max_frame_size +
85e8d004 1917 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1918 ETH_FCS_LEN) * 2;
1919 min_tx_space = ALIGN(min_tx_space, 1024);
1920 min_tx_space >>= 10;
1921 /* software strips receive CRC, so leave room for it */
1922 min_rx_space = adapter->max_frame_size;
1923 min_rx_space = ALIGN(min_rx_space, 1024);
1924 min_rx_space >>= 10;
1925
1926 /* If current Tx allocation is less than the min Tx FIFO size,
1927 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1928 * allocation, take space away from current Rx allocation
1929 */
9d5c8243
AK		 1930 if (tx_space < min_tx_space &&
1931 ((min_tx_space - tx_space) < pba)) {
1932 pba = pba - (min_tx_space - tx_space);
1933
b980ac18
JK		 1934 /* if short on Rx space, Rx wins and must trump Tx
1935 * adjustment
1936 */
9d5c8243
AK		 1937 if (pba < min_rx_space)
1938 pba = min_rx_space;
1939 }
2d064c06 1940 wr32(E1000_PBA, pba);
9d5c8243 1941 }
9d5c8243
AK		 1942
1943 /* flow control settings */
1944 /* The high water mark must be low enough to fit one full frame
1945 * (or the size used for early receive) above it in the Rx FIFO.
1946 * Set it to the lower of:
1947 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1948 * - the full Rx FIFO size minus one full frame
1949 */
9d5c8243 1950 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1951 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1952
d48507fe 1953 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1954 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1955 fc->pause_time = 0xFFFF;
1956 fc->send_xon = 1;
0cce119a 1957 fc->current_mode = fc->requested_mode;
9d5c8243 1958
4ae196df
AD		 1959 /* disable receive for all VFs and wait one second */
1960 if (adapter->vfs_allocated_count) {
1961 int i;
9005df38 1962
4ae196df 1963 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1964 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1965
1966 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1967 igb_ping_all_vfs(adapter);
4ae196df
AD		 1968
1969 /* disable transmits and receives */
1970 wr32(E1000_VFRE, 0);
1971 wr32(E1000_VFTE, 0);
1972 }
1973
9d5c8243 1974 /* Allow time for pending master requests to run */
330a6d6a 1975 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1976 wr32(E1000_WUC, 0);
1977
56cec249
CW		 1978 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1979 /* need to resetup here after media swap */
1980 adapter->ei.get_invariants(hw);
1981 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1982 }
1983 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1984 if (igb_enable_mas(adapter))
1985 dev_err(&pdev->dev,
1986 "Error enabling Media Auto Sense\n");
1987 }
330a6d6a 1988 if (hw->mac.ops.init_hw(hw))
090b1795 1989 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1990
b980ac18 1991 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1992 * control is off when forcing speed.
1993 */
1994 if (!hw->mac.autoneg)
1995 igb_force_mac_fc(hw);
1996
b6e0c419 1997 igb_init_dmac(adapter, pba);
e428893b
CW		 1998#ifdef CONFIG_IGB_HWMON
1999 /* Re-initialize the thermal sensor on i350 devices. */
2000 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2001 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2002 /* If present, re-initialize the external thermal sensor
2003 * interface.
2004 */
2005 if (adapter->ets)
2006 mac->ops.init_thermal_sensor_thresh(hw);
2007 }
2008 }
2009#endif
b936136d 2010 /* Re-establish EEE setting */
f4c01e96
CW		 2011 if (hw->phy.media_type == e1000_media_type_copper) {
2012 switch (mac->type) {
2013 case e1000_i350:
2014 case e1000_i210:
2015 case e1000_i211:
c4c112f1 2016 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2017 break;
2018 case e1000_i354:
c4c112f1 2019 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2020 break;
2021 default:
2022 break;
2023 }
2024 }
88a268c1
NN		 2025 if (!netif_running(adapter->netdev))
2026 igb_power_down_link(adapter);
2027
9d5c8243
AK		 2028 igb_update_mng_vlan(adapter);
2029
2030 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2031 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2032
1f6e8178
MV		 2033 /* Re-enable PTP, where applicable. */
2034 igb_ptp_reset(adapter);
1f6e8178 2035
330a6d6a 2036 igb_get_phy_info(hw);
9d5c8243
AK		 2037}
2038
c8f44aff
MM		 2039static netdev_features_t igb_fix_features(struct net_device *netdev,
2040 netdev_features_t features)
b2cb09b1 2041{
b980ac18
JK		 2042 /* Since there is no support for separate Rx/Tx vlan accel
2043 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2044 */
f646968f
PM		 2045 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2046 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2047 else
f646968f 2048 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2049
2050 return features;
2051}
2052
c8f44aff
MM		 2053static int igb_set_features(struct net_device *netdev,
2054 netdev_features_t features)
ac52caa3 2055{
c8f44aff 2056 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2057 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2058
f646968f 2059 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2060 igb_vlan_mode(netdev, features);
2061
89eaefb6
BG		 2062 if (!(changed & NETIF_F_RXALL))
2063 return 0;
2064
2065 netdev->features = features;
2066
2067 if (netif_running(netdev))
2068 igb_reinit_locked(adapter);
2069 else
2070 igb_reset(adapter);
2071
ac52caa3
MM		 2072 return 0;
2073}
2074
2e5c6922 2075static const struct net_device_ops igb_netdev_ops = {
559e9c49 2076 .ndo_open = igb_open,
2e5c6922 2077 .ndo_stop = igb_close,
cd392f5c 2078 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2079 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2080 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2081 .ndo_set_mac_address = igb_set_mac,
2082 .ndo_change_mtu = igb_change_mtu,
2083 .ndo_do_ioctl = igb_ioctl,
2084 .ndo_tx_timeout = igb_tx_timeout,
2085 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2086 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2087 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2088 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2089 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2090 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2091 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2092 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2093#ifdef CONFIG_NET_POLL_CONTROLLER
2094 .ndo_poll_controller = igb_netpoll,
2095#endif
b2cb09b1
JP		 2096 .ndo_fix_features = igb_fix_features,
2097 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2098};
2099
d67974f0
CW		 2100/**
2101 * igb_set_fw_version - Configure version string for ethtool
2102 * @adapter: adapter struct
d67974f0
CW		 2103 **/
2104void igb_set_fw_version(struct igb_adapter *adapter)
2105{
2106 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2107 struct e1000_fw_version fw;
2108
2109 igb_get_fw_version(hw, &fw);
2110
2111 switch (hw->mac.type) {
7dc98a62 2112 case e1000_i210:
0b1a6f2e 2113 case e1000_i211:
7dc98a62
CW		 2114 if (!(igb_get_flash_presence_i210(hw))) {
2115 snprintf(adapter->fw_version,
2116 sizeof(adapter->fw_version),
2117 "%2d.%2d-%d",
2118 fw.invm_major, fw.invm_minor,
2119 fw.invm_img_type);
2120 break;
2121 }
2122 /* fall through */
0b1a6f2e
CW		 2123 default:
2124 /* if option is rom valid, display its version too */
2125 if (fw.or_valid) {
2126 snprintf(adapter->fw_version,
2127 sizeof(adapter->fw_version),
2128 "%d.%d, 0x%08x, %d.%d.%d",
2129 fw.eep_major, fw.eep_minor, fw.etrack_id,
2130 fw.or_major, fw.or_build, fw.or_patch);
2131 /* no option rom */
7dc98a62 2132 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2133 snprintf(adapter->fw_version,
7dc98a62
CW		 2134 sizeof(adapter->fw_version),
2135 "%d.%d, 0x%08x",
2136 fw.eep_major, fw.eep_minor, fw.etrack_id);
2137 } else {
2138 snprintf(adapter->fw_version,
2139 sizeof(adapter->fw_version),
2140 "%d.%d.%d",
2141 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2142 }
2143 break;
d67974f0 2144 }
d67974f0
CW		 2145}
2146
56cec249
CW		 2147/**
2148 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2149 *
2150 * @adapter: adapter struct
2151 **/
2152static void igb_init_mas(struct igb_adapter *adapter)
2153{
2154 struct e1000_hw *hw = &adapter->hw;
2155 u16 eeprom_data;
2156
2157 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2158 switch (hw->bus.func) {
2159 case E1000_FUNC_0:
2160 if (eeprom_data & IGB_MAS_ENABLE_0) {
2161 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2162 netdev_info(adapter->netdev,
2163 "MAS: Enabling Media Autosense for port %d\n",
2164 hw->bus.func);
2165 }
2166 break;
2167 case E1000_FUNC_1:
2168 if (eeprom_data & IGB_MAS_ENABLE_1) {
2169 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2170 netdev_info(adapter->netdev,
2171 "MAS: Enabling Media Autosense for port %d\n",
2172 hw->bus.func);
2173 }
2174 break;
2175 case E1000_FUNC_2:
2176 if (eeprom_data & IGB_MAS_ENABLE_2) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 case E1000_FUNC_3:
2184 if (eeprom_data & IGB_MAS_ENABLE_3) {
2185 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2186 netdev_info(adapter->netdev,
2187 "MAS: Enabling Media Autosense for port %d\n",
2188 hw->bus.func);
2189 }
2190 break;
2191 default:
2192 /* Shouldn't get here */
2193 netdev_err(adapter->netdev,
2194 "MAS: Invalid port configuration, returning\n");
2195 break;
2196 }
2197}
2198
b980ac18
JK		 2199/**
2200 * igb_init_i2c - Init I2C interface
441fc6fd 2201 * @adapter: pointer to adapter structure
b980ac18 2202 **/
441fc6fd
CW		 2203static s32 igb_init_i2c(struct igb_adapter *adapter)
2204{
23d87824 2205 s32 status = 0;
441fc6fd
CW		 2206
2207 /* I2C interface supported on i350 devices */
2208 if (adapter->hw.mac.type != e1000_i350)
23d87824 2209 return 0;
441fc6fd
CW		 2210
2211 /* Initialize the i2c bus which is controlled by the registers.
2212 * This bus will use the i2c_algo_bit structue that implements
2213 * the protocol through toggling of the 4 bits in the register.
2214 */
2215 adapter->i2c_adap.owner = THIS_MODULE;
2216 adapter->i2c_algo = igb_i2c_algo;
2217 adapter->i2c_algo.data = adapter;
2218 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2219 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2220 strlcpy(adapter->i2c_adap.name, "igb BB",
2221 sizeof(adapter->i2c_adap.name));
2222 status = i2c_bit_add_bus(&adapter->i2c_adap);
2223 return status;
2224}
2225
9d5c8243 2226/**
b980ac18
JK		 2227 * igb_probe - Device Initialization Routine
2228 * @pdev: PCI device information struct
2229 * @ent: entry in igb_pci_tbl
9d5c8243 2230 *
b980ac18 2231 * Returns 0 on success, negative on failure
9d5c8243 2232 *
b980ac18
JK		 2233 * igb_probe initializes an adapter identified by a pci_dev structure.
2234 * The OS initialization, configuring of the adapter private structure,
2235 * and a hardware reset occur.
9d5c8243 2236 **/
1dd06ae8 2237static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2238{
2239 struct net_device *netdev;
2240 struct igb_adapter *adapter;
2241 struct e1000_hw *hw;
4337e993 2242 u16 eeprom_data = 0;
9835fd73 2243 s32 ret_val;
4337e993 2244 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2245 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2246 int err, pci_using_dac;
9835fd73 2247 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2248
bded64a7
AG		 2249 /* Catch broken hardware that put the wrong VF device ID in
2250 * the PCIe SR-IOV capability.
2251 */
2252 if (pdev->is_virtfn) {
2253 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2254 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2255 return -EINVAL;
2256 }
2257
aed5dec3 2258 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2259 if (err)
2260 return err;
2261
2262 pci_using_dac = 0;
dc4ff9bb 2263 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2264 if (!err) {
dc4ff9bb 2265 pci_using_dac = 1;
9d5c8243 2266 } else {
dc4ff9bb 2267 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2268 if (err) {
dc4ff9bb
RK		 2269 dev_err(&pdev->dev,
2270 "No usable DMA configuration, aborting\n");
2271 goto err_dma;
9d5c8243
AK		 2272 }
2273 }
2274
aed5dec3 2275 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2276 IORESOURCE_MEM),
2277 igb_driver_name);
9d5c8243
AK		 2278 if (err)
2279 goto err_pci_reg;
2280
19d5afd4 2281 pci_enable_pcie_error_reporting(pdev);
40a914fa 2282
9d5c8243 2283 pci_set_master(pdev);
c682fc23 2284 pci_save_state(pdev);
9d5c8243
AK		 2285
2286 err = -ENOMEM;
1bfaf07b 2287 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2288 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2289 if (!netdev)
2290 goto err_alloc_etherdev;
2291
2292 SET_NETDEV_DEV(netdev, &pdev->dev);
2293
2294 pci_set_drvdata(pdev, netdev);
2295 adapter = netdev_priv(netdev);
2296 adapter->netdev = netdev;
2297 adapter->pdev = pdev;
2298 hw = &adapter->hw;
2299 hw->back = adapter;
b3f4d599 2300 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2301
9d5c8243 2302 err = -EIO;
89dbefb2 2303 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2304 if (!hw->hw_addr)
9d5c8243
AK		 2305 goto err_ioremap;
2306
2e5c6922 2307 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2308 igb_set_ethtool_ops(netdev);
9d5c8243 2309 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2310
2311 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2312
89dbefb2
AS		 2313 netdev->mem_start = pci_resource_start(pdev, 0);
2314 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2315
9d5c8243
AK		 2316 /* PCI config space info */
2317 hw->vendor_id = pdev->vendor;
2318 hw->device_id = pdev->device;
2319 hw->revision_id = pdev->revision;
2320 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2321 hw->subsystem_device_id = pdev->subsystem_device;
2322
9d5c8243
AK		 2323 /* Copy the default MAC, PHY and NVM function pointers */
2324 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2325 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2326 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2327 /* Initialize skew-specific constants */
2328 err = ei->get_invariants(hw);
2329 if (err)
450c87c8 2330 goto err_sw_init;
9d5c8243 2331
450c87c8 2332 /* setup the private structure */
9d5c8243
AK		 2333 err = igb_sw_init(adapter);
2334 if (err)
2335 goto err_sw_init;
2336
2337 igb_get_bus_info_pcie(hw);
2338
2339 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2340
2341 /* Copper options */
2342 if (hw->phy.media_type == e1000_media_type_copper) {
2343 hw->phy.mdix = AUTO_ALL_MODES;
2344 hw->phy.disable_polarity_correction = false;
2345 hw->phy.ms_type = e1000_ms_hw_default;
2346 }
2347
2348 if (igb_check_reset_block(hw))
2349 dev_info(&pdev->dev,
2350 "PHY reset is blocked due to SOL/IDER session.\n");
2351
b980ac18 2352 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2353 * set by igb_sw_init so we should use an or instead of an
2354 * assignment.
2355 */
2356 netdev->features |= NETIF_F_SG |
2357 NETIF_F_IP_CSUM |
2358 NETIF_F_IPV6_CSUM |
2359 NETIF_F_TSO |
2360 NETIF_F_TSO6 |
2361 NETIF_F_RXHASH |
2362 NETIF_F_RXCSUM |
f646968f
PM		 2363 NETIF_F_HW_VLAN_CTAG_RX |
2364 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2365
2366 /* copy netdev features into list of user selectable features */
2367 netdev->hw_features |= netdev->features;
89eaefb6 2368 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2369
2370 /* set this bit last since it cannot be part of hw_features */
f646968f 2371 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2372
2373 netdev->vlan_features |= NETIF_F_TSO |
2374 NETIF_F_TSO6 |
2375 NETIF_F_IP_CSUM |
2376 NETIF_F_IPV6_CSUM |
2377 NETIF_F_SG;
48f29ffc 2378
6b8f0922
BG		 2379 netdev->priv_flags |= IFF_SUPP_NOFCS;
2380
7b872a55 2381 if (pci_using_dac) {
9d5c8243 2382 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2383 netdev->vlan_features |= NETIF_F_HIGHDMA;
2384 }
9d5c8243 2385
ac52caa3
MM		 2386 if (hw->mac.type >= e1000_82576) {
2387 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2388 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2389 }
b9473560 2390
01789349
JP		 2391 netdev->priv_flags |= IFF_UNICAST_FLT;
2392
330a6d6a 2393 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2394
2395 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2396 * known good starting state
2397 */
9d5c8243
AK		 2398 hw->mac.ops.reset_hw(hw);
2399
ef3a0092
CW		 2400 /* make sure the NVM is good , i211/i210 parts can have special NVM
2401 * that doesn't contain a checksum
f96a8a0b 2402 */
ef3a0092
CW		 2403 switch (hw->mac.type) {
2404 case e1000_i210:
2405 case e1000_i211:
2406 if (igb_get_flash_presence_i210(hw)) {
2407 if (hw->nvm.ops.validate(hw) < 0) {
2408 dev_err(&pdev->dev,
2409 "The NVM Checksum Is Not Valid\n");
2410 err = -EIO;
2411 goto err_eeprom;
2412 }
2413 }
2414 break;
2415 default:
f96a8a0b
CW		 2416 if (hw->nvm.ops.validate(hw) < 0) {
2417 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2418 err = -EIO;
2419 goto err_eeprom;
2420 }
ef3a0092 2421 break;
9d5c8243
AK		 2422 }
2423
2424 /* copy the MAC address out of the NVM */
2425 if (hw->mac.ops.read_mac_addr(hw))
2426 dev_err(&pdev->dev, "NVM Read Error\n");
2427
2428 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2429
aaeb6cdf 2430 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2431 dev_err(&pdev->dev, "Invalid MAC Address\n");
2432 err = -EIO;
2433 goto err_eeprom;
2434 }
2435
d67974f0
CW		 2436 /* get firmware version for ethtool -i */
2437 igb_set_fw_version(adapter);
2438
27dff8b2
TF		 2439 /* configure RXPBSIZE and TXPBSIZE */
2440 if (hw->mac.type == e1000_i210) {
2441 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2442 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2443 }
2444
c061b18d 2445 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2446 (unsigned long) adapter);
c061b18d 2447 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2448 (unsigned long) adapter);
9d5c8243
AK		 2449
2450 INIT_WORK(&adapter->reset_task, igb_reset_task);
2451 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2452
450c87c8 2453 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2454 adapter->fc_autoneg = true;
2455 hw->mac.autoneg = true;
2456 hw->phy.autoneg_advertised = 0x2f;
2457
0cce119a
AD		 2458 hw->fc.requested_mode = e1000_fc_default;
2459 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2460
9d5c8243
AK		 2461 igb_validate_mdi_setting(hw);
2462
63d4a8f9 2463 /* By default, support wake on port A */
a2cf8b6c 2464 if (hw->bus.func == 0)
63d4a8f9
MV		 2465 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2466
2467 /* Check the NVM for wake support on non-port A ports */
2468 if (hw->mac.type >= e1000_82580)
55cac248 2469 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2470 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2471 &eeprom_data);
a2cf8b6c
AD		 2472 else if (hw->bus.func == 1)
2473 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2474
63d4a8f9
MV		 2475 if (eeprom_data & IGB_EEPROM_APME)
2476 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2477
2478 /* now that we have the eeprom settings, apply the special cases where
2479 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2480 * lan on a particular port
2481 */
9d5c8243
AK		 2482 switch (pdev->device) {
2483 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2484 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2485 break;
2486 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2487 case E1000_DEV_ID_82576_FIBER:
2488 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2489 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2490 * regardless of eeprom setting
2491 */
9d5c8243 2492 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2493 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2494 break;
c8ea5ea9 2495 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2496 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2497 /* if quad port adapter, disable WoL on all but port A */
2498 if (global_quad_port_a != 0)
63d4a8f9 2499 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2500 else
2501 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2502 /* Reset for multiple quad port adapters */
2503 if (++global_quad_port_a == 4)
2504 global_quad_port_a = 0;
2505 break;
63d4a8f9
MV		 2506 default:
2507 /* If the device can't wake, don't set software support */
2508 if (!device_can_wakeup(&adapter->pdev->dev))
2509 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2510 }
2511
2512 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2513 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2514 adapter->wol |= E1000_WUFC_MAG;
2515
2516 /* Some vendors want WoL disabled by default, but still supported */
2517 if ((hw->mac.type == e1000_i350) &&
2518 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2519 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2520 adapter->wol = 0;
2521 }
2522
2523 device_set_wakeup_enable(&adapter->pdev->dev,
2524 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2525
2526 /* reset the hardware with the new settings */
2527 igb_reset(adapter);
2528
441fc6fd
CW		 2529 /* Init the I2C interface */
2530 err = igb_init_i2c(adapter);
2531 if (err) {
2532 dev_err(&pdev->dev, "failed to init i2c interface\n");
2533 goto err_eeprom;
2534 }
2535
9d5c8243 2536 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2537 * driver.
2538 */
9d5c8243
AK		 2539 igb_get_hw_control(adapter);
2540
9d5c8243
AK		 2541 strcpy(netdev->name, "eth%d");
2542 err = register_netdev(netdev);
2543 if (err)
2544 goto err_register;
2545
b168dfc5
JB		 2546 /* carrier off reporting is important to ethtool even BEFORE open */
2547 netif_carrier_off(netdev);
2548
421e02f0 2549#ifdef CONFIG_IGB_DCA
bbd98fe4 2550 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2551 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2552 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2553 igb_setup_dca(adapter);
2554 }
fe4506b6 2555
38c845c7 2556#endif
e428893b
CW		 2557#ifdef CONFIG_IGB_HWMON
2558 /* Initialize the thermal sensor on i350 devices. */
2559 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2560 u16 ets_word;
3c89f6d0 2561
b980ac18 2562 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2563 * external thermal sensor.
2564 */
2565 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2566 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2567 adapter->ets = true;
2568 else
2569 adapter->ets = false;
2570 if (igb_sysfs_init(adapter))
2571 dev_err(&pdev->dev,
2572 "failed to allocate sysfs resources\n");
2573 } else {
2574 adapter->ets = false;
2575 }
2576#endif
56cec249
CW		 2577 /* Check if Media Autosense is enabled */
2578 adapter->ei = *ei;
2579 if (hw->dev_spec._82575.mas_capable)
2580 igb_init_mas(adapter);
2581
673b8b70 2582 /* do hw tstamp init after resetting */
7ebae817 2583 igb_ptp_init(adapter);
673b8b70 2584
9d5c8243 2585 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2586 /* print bus type/speed/width info, not applicable to i354 */
2587 if (hw->mac.type != e1000_i354) {
2588 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2589 netdev->name,
2590 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2591 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2592 "unknown"),
2593 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2594 "Width x4" :
2595 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2596 "Width x2" :
2597 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2598 "Width x1" : "unknown"), netdev->dev_addr);
2599 }
9d5c8243 2600
53ea6c7e
TF		 2601 if ((hw->mac.type >= e1000_i210 ||
2602 igb_get_flash_presence_i210(hw))) {
2603 ret_val = igb_read_part_string(hw, part_str,
2604 E1000_PBANUM_LENGTH);
2605 } else {
2606 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2607 }
2608
9835fd73
CW		 2609 if (ret_val)
2610 strcpy(part_str, "Unknown");
2611 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2612 dev_info(&pdev->dev,
2613 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2614 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2615 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2616 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2617 if (hw->phy.media_type == e1000_media_type_copper) {
2618 switch (hw->mac.type) {
2619 case e1000_i350:
2620 case e1000_i210:
2621 case e1000_i211:
2622 /* Enable EEE for internal copper PHY devices */
c4c112f1 2623 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2624 if ((!err) &&
2625 (!hw->dev_spec._82575.eee_disable)) {
2626 adapter->eee_advert =
2627 MDIO_EEE_100TX | MDIO_EEE_1000T;
2628 adapter->flags |= IGB_FLAG_EEE;
2629 }
2630 break;
2631 case e1000_i354:
ceb5f13b 2632 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2633 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2634 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2635 if ((!err) &&
2636 (!hw->dev_spec._82575.eee_disable)) {
2637 adapter->eee_advert =
2638 MDIO_EEE_100TX | MDIO_EEE_1000T;
2639 adapter->flags |= IGB_FLAG_EEE;
2640 }
2641 }
2642 break;
2643 default:
2644 break;
ceb5f13b 2645 }
09b068d4 2646 }
749ab2cd 2647 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2648 return 0;
2649
2650err_register:
2651 igb_release_hw_control(adapter);
441fc6fd 2652 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2653err_eeprom:
2654 if (!igb_check_reset_block(hw))
f5f4cf08 2655 igb_reset_phy(hw);
9d5c8243
AK		 2656
2657 if (hw->flash_address)
2658 iounmap(hw->flash_address);
9d5c8243 2659err_sw_init:
047e0030 2660 igb_clear_interrupt_scheme(adapter);
75009b3a 2661 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2662err_ioremap:
2663 free_netdev(netdev);
2664err_alloc_etherdev:
559e9c49 2665 pci_release_selected_regions(pdev,
b980ac18 2666 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2667err_pci_reg:
2668err_dma:
2669 pci_disable_device(pdev);
2670 return err;
2671}
2672
fa44f2f1 2673#ifdef CONFIG_PCI_IOV
781798a1 2674static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2675{
2676 struct net_device *netdev = pci_get_drvdata(pdev);
2677 struct igb_adapter *adapter = netdev_priv(netdev);
2678 struct e1000_hw *hw = &adapter->hw;
2679
2680 /* reclaim resources allocated to VFs */
2681 if (adapter->vf_data) {
2682 /* disable iov and allow time for transactions to clear */
b09186d2 2683 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2684 dev_warn(&pdev->dev,
2685 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2686 return -EPERM;
2687 } else {
2688 pci_disable_sriov(pdev);
2689 msleep(500);
2690 }
2691
2692 kfree(adapter->vf_data);
2693 adapter->vf_data = NULL;
2694 adapter->vfs_allocated_count = 0;
2695 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2696 wrfl();
2697 msleep(100);
2698 dev_info(&pdev->dev, "IOV Disabled\n");
2699
2700 /* Re-enable DMA Coalescing flag since IOV is turned off */
2701 adapter->flags |= IGB_FLAG_DMAC;
2702 }
2703
2704 return 0;
2705}
2706
2707static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2708{
2709 struct net_device *netdev = pci_get_drvdata(pdev);
2710 struct igb_adapter *adapter = netdev_priv(netdev);
2711 int old_vfs = pci_num_vf(pdev);
2712 int err = 0;
2713 int i;
2714
cd14ef54 2715 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2716 err = -EPERM;
2717 goto out;
2718 }
fa44f2f1
GR		 2719 if (!num_vfs)
2720 goto out;
fa44f2f1 2721
781798a1
SA		 2722 if (old_vfs) {
2723 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2724 old_vfs, max_vfs);
2725 adapter->vfs_allocated_count = old_vfs;
2726 } else
2727 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2728
2729 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2730 sizeof(struct vf_data_storage), GFP_KERNEL);
2731
2732 /* if allocation failed then we do not support SR-IOV */
2733 if (!adapter->vf_data) {
2734 adapter->vfs_allocated_count = 0;
2735 dev_err(&pdev->dev,
2736 "Unable to allocate memory for VF Data Storage\n");
2737 err = -ENOMEM;
2738 goto out;
2739 }
2740
781798a1
SA		 2741 /* only call pci_enable_sriov() if no VFs are allocated already */
2742 if (!old_vfs) {
2743 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2744 if (err)
2745 goto err_out;
2746 }
fa44f2f1
GR		 2747 dev_info(&pdev->dev, "%d VFs allocated\n",
2748 adapter->vfs_allocated_count);
2749 for (i = 0; i < adapter->vfs_allocated_count; i++)
2750 igb_vf_configure(adapter, i);
2751
2752 /* DMA Coalescing is not supported in IOV mode. */
2753 adapter->flags &= ~IGB_FLAG_DMAC;
2754 goto out;
2755
2756err_out:
2757 kfree(adapter->vf_data);
2758 adapter->vf_data = NULL;
2759 adapter->vfs_allocated_count = 0;
2760out:
2761 return err;
2762}
2763
2764#endif
b980ac18 2765/**
441fc6fd
CW		 2766 * igb_remove_i2c - Cleanup I2C interface
2767 * @adapter: pointer to adapter structure
b980ac18 2768 **/
441fc6fd
CW		 2769static void igb_remove_i2c(struct igb_adapter *adapter)
2770{
441fc6fd
CW		 2771 /* free the adapter bus structure */
2772 i2c_del_adapter(&adapter->i2c_adap);
2773}
2774
9d5c8243 2775/**
b980ac18
JK		 2776 * igb_remove - Device Removal Routine
2777 * @pdev: PCI device information struct
9d5c8243 2778 *
b980ac18
JK		 2779 * igb_remove is called by the PCI subsystem to alert the driver
2780 * that it should release a PCI device. The could be caused by a
2781 * Hot-Plug event, or because the driver is going to be removed from
2782 * memory.
9d5c8243 2783 **/
9f9a12f8 2784static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2785{
2786 struct net_device *netdev = pci_get_drvdata(pdev);
2787 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2788 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2789
749ab2cd 2790 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2791#ifdef CONFIG_IGB_HWMON
2792 igb_sysfs_exit(adapter);
2793#endif
441fc6fd 2794 igb_remove_i2c(adapter);
a79f4f88 2795 igb_ptp_stop(adapter);
b980ac18 2796 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2797 * disable watchdog from being rescheduled.
2798 */
9d5c8243
AK		 2799 set_bit(__IGB_DOWN, &adapter->state);
2800 del_timer_sync(&adapter->watchdog_timer);
2801 del_timer_sync(&adapter->phy_info_timer);
2802
760141a5
TH		 2803 cancel_work_sync(&adapter->reset_task);
2804 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2805
421e02f0 2806#ifdef CONFIG_IGB_DCA
7dfc16fa 2807 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2808 dev_info(&pdev->dev, "DCA disabled\n");
2809 dca_remove_requester(&pdev->dev);
7dfc16fa 2810 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2811 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2812 }
2813#endif
2814
9d5c8243 2815 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2816 * would have already happened in close and is redundant.
2817 */
9d5c8243
AK		 2818 igb_release_hw_control(adapter);
2819
2820 unregister_netdev(netdev);
2821
047e0030 2822 igb_clear_interrupt_scheme(adapter);
9d5c8243 2823
37680117 2824#ifdef CONFIG_PCI_IOV
fa44f2f1 2825 igb_disable_sriov(pdev);
37680117 2826#endif
559e9c49 2827
75009b3a 2828 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2829 if (hw->flash_address)
2830 iounmap(hw->flash_address);
559e9c49 2831 pci_release_selected_regions(pdev,
b980ac18 2832 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2833
1128c756 2834 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2835 free_netdev(netdev);
2836
19d5afd4 2837 pci_disable_pcie_error_reporting(pdev);
40a914fa 2838
9d5c8243
AK		 2839 pci_disable_device(pdev);
2840}
2841
a6b623e0 2842/**
b980ac18
JK		 2843 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2844 * @adapter: board private structure to initialize
a6b623e0 2845 *
b980ac18
JK		 2846 * This function initializes the vf specific data storage and then attempts to
2847 * allocate the VFs. The reason for ordering it this way is because it is much
2848 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2849 * the memory for the VFs.
a6b623e0 2850 **/
9f9a12f8 2851static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2852{
2853#ifdef CONFIG_PCI_IOV
2854 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2855 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2856
f96a8a0b
CW		 2857 /* Virtualization features not supported on i210 family. */
2858 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2859 return;
2860
fa44f2f1 2861 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2862 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2863
a6b623e0
AD		 2864#endif /* CONFIG_PCI_IOV */
2865}
2866
fa44f2f1 2867static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2868{
2869 struct e1000_hw *hw = &adapter->hw;
374a542d 2870 u32 max_rss_queues;
9d5c8243 2871
374a542d 2872 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2873 switch (hw->mac.type) {
374a542d
MV		 2874 case e1000_i211:
2875 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2876 break;
2877 case e1000_82575:
f96a8a0b 2878 case e1000_i210:
374a542d
MV		 2879 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2880 break;
2881 case e1000_i350:
2882 /* I350 cannot do RSS and SR-IOV at the same time */
2883 if (!!adapter->vfs_allocated_count) {
2884 max_rss_queues = 1;
2885 break;
2886 }
2887 /* fall through */
2888 case e1000_82576:
2889 if (!!adapter->vfs_allocated_count) {
2890 max_rss_queues = 2;
2891 break;
2892 }
2893 /* fall through */
2894 case e1000_82580:
ceb5f13b 2895 case e1000_i354:
374a542d
MV		 2896 default:
2897 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2898 break;
374a542d
MV		 2899 }
2900
2901 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2902
2903 /* Determine if we need to pair queues. */
2904 switch (hw->mac.type) {
2905 case e1000_82575:
f96a8a0b 2906 case e1000_i211:
374a542d 2907 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2908 break;
374a542d 2909 case e1000_82576:
b980ac18 2910 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2911 * should pair the queues in order to conserve interrupts due
2912 * to limited supply.
2913 */
2914 if ((adapter->rss_queues > 1) &&
2915 (adapter->vfs_allocated_count > 6))
2916 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2917 /* fall through */
2918 case e1000_82580:
2919 case e1000_i350:
ceb5f13b 2920 case e1000_i354:
374a542d 2921 case e1000_i210:
f96a8a0b 2922 default:
b980ac18 2923 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2924 * order to conserve interrupts due to limited supply.
2925 */
2926 if (adapter->rss_queues > (max_rss_queues / 2))
2927 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2928 break;
2929 }
fa44f2f1
GR		 2930}
2931
2932/**
b980ac18
JK		 2933 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2934 * @adapter: board private structure to initialize
fa44f2f1 2935 *
b980ac18
JK		 2936 * igb_sw_init initializes the Adapter private data structure.
2937 * Fields are initialized based on PCI device information and
2938 * OS network device settings (MTU size).
fa44f2f1
GR		 2939 **/
2940static int igb_sw_init(struct igb_adapter *adapter)
2941{
2942 struct e1000_hw *hw = &adapter->hw;
2943 struct net_device *netdev = adapter->netdev;
2944 struct pci_dev *pdev = adapter->pdev;
2945
2946 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2947
2948 /* set default ring sizes */
2949 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2950 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2951
2952 /* set default ITR values */
2953 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2954 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2955
2956 /* set default work limits */
2957 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2958
2959 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2960 VLAN_HLEN;
2961 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2962
2963 spin_lock_init(&adapter->stats64_lock);
2964#ifdef CONFIG_PCI_IOV
2965 switch (hw->mac.type) {
2966 case e1000_82576:
2967 case e1000_i350:
2968 if (max_vfs > 7) {
2969 dev_warn(&pdev->dev,
2970 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2971 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2972 } else
2973 adapter->vfs_allocated_count = max_vfs;
2974 if (adapter->vfs_allocated_count)
2975 dev_warn(&pdev->dev,
2976 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2977 break;
2978 default:
2979 break;
2980 }
2981#endif /* CONFIG_PCI_IOV */
2982
2983 igb_init_queue_configuration(adapter);
a99955fc 2984
1128c756 2985 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2986 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2987 GFP_ATOMIC);
1128c756 2988
a6b623e0 2989 /* This call may decrease the number of queues */
53c7d064 2990 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2991 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2992 return -ENOMEM;
2993 }
2994
a6b623e0
AD		 2995 igb_probe_vfs(adapter);
2996
9d5c8243
AK		 2997 /* Explicitly disable IRQ since the NIC can be in any state. */
2998 igb_irq_disable(adapter);
2999
f96a8a0b 3000 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3001 adapter->flags &= ~IGB_FLAG_DMAC;
3002
9d5c8243
AK		 3003 set_bit(__IGB_DOWN, &adapter->state);
3004 return 0;
3005}
3006
3007/**
b980ac18
JK		 3008 * igb_open - Called when a network interface is made active
3009 * @netdev: network interface device structure
9d5c8243 3010 *
b980ac18 3011 * Returns 0 on success, negative value on failure
9d5c8243 3012 *
b980ac18
JK		 3013 * The open entry point is called when a network interface is made
3014 * active by the system (IFF_UP). At this point all resources needed
3015 * for transmit and receive operations are allocated, the interrupt
3016 * handler is registered with the OS, the watchdog timer is started,
3017 * and the stack is notified that the interface is ready.
9d5c8243 3018 **/
749ab2cd 3019static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3020{
3021 struct igb_adapter *adapter = netdev_priv(netdev);
3022 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3023 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3024 int err;
3025 int i;
3026
3027 /* disallow open during test */
749ab2cd
YZ		 3028 if (test_bit(__IGB_TESTING, &adapter->state)) {
3029 WARN_ON(resuming);
9d5c8243 3030 return -EBUSY;
749ab2cd
YZ		 3031 }
3032
3033 if (!resuming)
3034 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3035
b168dfc5
JB		 3036 netif_carrier_off(netdev);
3037
9d5c8243
AK		 3038 /* allocate transmit descriptors */
3039 err = igb_setup_all_tx_resources(adapter);
3040 if (err)
3041 goto err_setup_tx;
3042
3043 /* allocate receive descriptors */
3044 err = igb_setup_all_rx_resources(adapter);
3045 if (err)
3046 goto err_setup_rx;
3047
88a268c1 3048 igb_power_up_link(adapter);
9d5c8243 3049
9d5c8243
AK		 3050 /* before we allocate an interrupt, we must be ready to handle it.
3051 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3052 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3053 * clean_rx handler before we do so.
3054 */
9d5c8243
AK		 3055 igb_configure(adapter);
3056
3057 err = igb_request_irq(adapter);
3058 if (err)
3059 goto err_req_irq;
3060
0c2cc02e
AD		 3061 /* Notify the stack of the actual queue counts. */
3062 err = netif_set_real_num_tx_queues(adapter->netdev,
3063 adapter->num_tx_queues);
3064 if (err)
3065 goto err_set_queues;
3066
3067 err = netif_set_real_num_rx_queues(adapter->netdev,
3068 adapter->num_rx_queues);
3069 if (err)
3070 goto err_set_queues;
3071
9d5c8243
AK		 3072 /* From here on the code is the same as igb_up() */
3073 clear_bit(__IGB_DOWN, &adapter->state);
3074
0d1ae7f4
AD		 3075 for (i = 0; i < adapter->num_q_vectors; i++)
3076 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3077
3078 /* Clear any pending interrupts. */
3079 rd32(E1000_ICR);
844290e5
PW		 3080
3081 igb_irq_enable(adapter);
3082
d4960307
AD		 3083 /* notify VFs that reset has been completed */
3084 if (adapter->vfs_allocated_count) {
3085 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3086
d4960307
AD		 3087 reg_data |= E1000_CTRL_EXT_PFRSTD;
3088 wr32(E1000_CTRL_EXT, reg_data);
3089 }
3090
d55b53ff
JK		 3091 netif_tx_start_all_queues(netdev);
3092
749ab2cd
YZ		 3093 if (!resuming)
3094 pm_runtime_put(&pdev->dev);
3095
25568a53
AD		 3096 /* start the watchdog. */
3097 hw->mac.get_link_status = 1;
3098 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3099
3100 return 0;
3101
0c2cc02e
AD		 3102err_set_queues:
3103 igb_free_irq(adapter);
9d5c8243
AK		 3104err_req_irq:
3105 igb_release_hw_control(adapter);
88a268c1 3106 igb_power_down_link(adapter);
9d5c8243
AK		 3107 igb_free_all_rx_resources(adapter);
3108err_setup_rx:
3109 igb_free_all_tx_resources(adapter);
3110err_setup_tx:
3111 igb_reset(adapter);
749ab2cd
YZ		 3112 if (!resuming)
3113 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3114
3115 return err;
3116}
3117
749ab2cd
YZ		 3118static int igb_open(struct net_device *netdev)
3119{
3120 return __igb_open(netdev, false);
3121}
3122
9d5c8243 3123/**
b980ac18
JK		 3124 * igb_close - Disables a network interface
3125 * @netdev: network interface device structure
9d5c8243 3126 *
b980ac18 3127 * Returns 0, this is not allowed to fail
9d5c8243 3128 *
b980ac18
JK		 3129 * The close entry point is called when an interface is de-activated
3130 * by the OS. The hardware is still under the driver's control, but
3131 * needs to be disabled. A global MAC reset is issued to stop the
3132 * hardware, and all transmit and receive resources are freed.
9d5c8243 3133 **/
749ab2cd 3134static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3135{
3136 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3137 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3138
3139 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3140
749ab2cd
YZ		 3141 if (!suspending)
3142 pm_runtime_get_sync(&pdev->dev);
3143
3144 igb_down(adapter);
9d5c8243
AK		 3145 igb_free_irq(adapter);
3146
3147 igb_free_all_tx_resources(adapter);
3148 igb_free_all_rx_resources(adapter);
3149
749ab2cd
YZ		 3150 if (!suspending)
3151 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3152 return 0;
3153}
3154
749ab2cd
YZ		 3155static int igb_close(struct net_device *netdev)
3156{
3157 return __igb_close(netdev, false);
3158}
3159
9d5c8243 3160/**
b980ac18
JK		 3161 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3162 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3163 *
b980ac18 3164 * Return 0 on success, negative on failure
9d5c8243 3165 **/
80785298 3166int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3167{
59d71989 3168 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3169 int size;
3170
06034649 3171 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3172
3173 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3174 if (!tx_ring->tx_buffer_info)
9d5c8243 3175 goto err;
9d5c8243
AK		 3176
3177 /* round up to nearest 4K */
85e8d004 3178 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3179 tx_ring->size = ALIGN(tx_ring->size, 4096);
3180
5536d210
AD		 3181 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3182 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3183 if (!tx_ring->desc)
3184 goto err;
3185
9d5c8243
AK		 3186 tx_ring->next_to_use = 0;
3187 tx_ring->next_to_clean = 0;
81c2fc22 3188
9d5c8243
AK		 3189 return 0;
3190
3191err:
06034649 3192 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3193 tx_ring->tx_buffer_info = NULL;
3194 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3195 return -ENOMEM;
3196}
3197
3198/**
b980ac18
JK		 3199 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3200 * (Descriptors) for all queues
3201 * @adapter: board private structure
9d5c8243 3202 *
b980ac18 3203 * Return 0 on success, negative on failure
9d5c8243
AK		 3204 **/
3205static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3206{
439705e1 3207 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3208 int i, err = 0;
3209
3210 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3211 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3212 if (err) {
439705e1 3213 dev_err(&pdev->dev,
9d5c8243
AK		 3214 "Allocation for Tx Queue %u failed\n", i);
3215 for (i--; i >= 0; i--)
3025a446 3216 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3217 break;
3218 }
3219 }
3220
3221 return err;
3222}
3223
3224/**
b980ac18
JK		 3225 * igb_setup_tctl - configure the transmit control registers
3226 * @adapter: Board private structure
9d5c8243 3227 **/
d7ee5b3a 3228void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3229{
9d5c8243
AK		 3230 struct e1000_hw *hw = &adapter->hw;
3231 u32 tctl;
9d5c8243 3232
85b430b4
AD		 3233 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3234 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3235
3236 /* Program the Transmit Control Register */
9d5c8243
AK		 3237 tctl = rd32(E1000_TCTL);
3238 tctl &= ~E1000_TCTL_CT;
3239 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3240 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3241
3242 igb_config_collision_dist(hw);
3243
9d5c8243
AK		 3244 /* Enable transmits */
3245 tctl |= E1000_TCTL_EN;
3246
3247 wr32(E1000_TCTL, tctl);
3248}
3249
85b430b4 3250/**
b980ac18
JK		 3251 * igb_configure_tx_ring - Configure transmit ring after Reset
3252 * @adapter: board private structure
3253 * @ring: tx ring to configure
85b430b4 3254 *
b980ac18 3255 * Configure a transmit ring after a reset.
85b430b4 3256 **/
d7ee5b3a 3257void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3258 struct igb_ring *ring)
85b430b4
AD		 3259{
3260 struct e1000_hw *hw = &adapter->hw;
a74420e0 3261 u32 txdctl = 0;
85b430b4
AD		 3262 u64 tdba = ring->dma;
3263 int reg_idx = ring->reg_idx;
3264
3265 /* disable the queue */
a74420e0 3266 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3267 wrfl();
3268 mdelay(10);
3269
3270 wr32(E1000_TDLEN(reg_idx),
b980ac18 3271 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3272 wr32(E1000_TDBAL(reg_idx),
b980ac18 3273 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3274 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3275
fce99e34 3276 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3277 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3278 writel(0, ring->tail);
85b430b4
AD		 3279
3280 txdctl |= IGB_TX_PTHRESH;
3281 txdctl |= IGB_TX_HTHRESH << 8;
3282 txdctl |= IGB_TX_WTHRESH << 16;
3283
3284 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3285 wr32(E1000_TXDCTL(reg_idx), txdctl);
3286}
3287
3288/**
b980ac18
JK		 3289 * igb_configure_tx - Configure transmit Unit after Reset
3290 * @adapter: board private structure
85b430b4 3291 *
b980ac18 3292 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3293 **/
3294static void igb_configure_tx(struct igb_adapter *adapter)
3295{
3296 int i;
3297
3298 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3299 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3300}
3301
9d5c8243 3302/**
b980ac18
JK		 3303 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3304 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3305 *
b980ac18 3306 * Returns 0 on success, negative on failure
9d5c8243 3307 **/
80785298 3308int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3309{
59d71989 3310 struct device *dev = rx_ring->dev;
f33005a6 3311 int size;
9d5c8243 3312
06034649 3313 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3314
3315 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3316 if (!rx_ring->rx_buffer_info)
9d5c8243 3317 goto err;
9d5c8243 3318
9d5c8243 3319 /* Round up to nearest 4K */
f33005a6 3320 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3321 rx_ring->size = ALIGN(rx_ring->size, 4096);
3322
5536d210
AD		 3323 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3324 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3325 if (!rx_ring->desc)
3326 goto err;
3327
cbc8e55f 3328 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3329 rx_ring->next_to_clean = 0;
3330 rx_ring->next_to_use = 0;
9d5c8243 3331
9d5c8243
AK		 3332 return 0;
3333
3334err:
06034649
AD		 3335 vfree(rx_ring->rx_buffer_info);
3336 rx_ring->rx_buffer_info = NULL;
f33005a6 3337 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3338 return -ENOMEM;
3339}
3340
3341/**
b980ac18
JK		 3342 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3343 * (Descriptors) for all queues
3344 * @adapter: board private structure
9d5c8243 3345 *
b980ac18 3346 * Return 0 on success, negative on failure
9d5c8243
AK		 3347 **/
3348static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3349{
439705e1 3350 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3351 int i, err = 0;
3352
3353 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3354 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3355 if (err) {
439705e1 3356 dev_err(&pdev->dev,
9d5c8243
AK		 3357 "Allocation for Rx Queue %u failed\n", i);
3358 for (i--; i >= 0; i--)
3025a446 3359 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3360 break;
3361 }
3362 }
3363
3364 return err;
3365}
3366
06cf2666 3367/**
b980ac18
JK		 3368 * igb_setup_mrqc - configure the multiple receive queue control registers
3369 * @adapter: Board private structure
06cf2666
AD		 3370 **/
3371static void igb_setup_mrqc(struct igb_adapter *adapter)
3372{
3373 struct e1000_hw *hw = &adapter->hw;
3374 u32 mrqc, rxcsum;
ed12cc9a 3375 u32 j, num_rx_queues;
eb31f849 3376 u32 rss_key[10];
06cf2666 3377
eb31f849 3378 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3379 for (j = 0; j < 10; j++)
eb31f849 3380 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3381
a99955fc 3382 num_rx_queues = adapter->rss_queues;
06cf2666 3383
797fd4be 3384 switch (hw->mac.type) {
797fd4be
AD		 3385 case e1000_82576:
3386 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3387 if (adapter->vfs_allocated_count)
06cf2666 3388 num_rx_queues = 2;
797fd4be
AD		 3389 break;
3390 default:
3391 break;
06cf2666
AD		 3392 }
3393
ed12cc9a
LMV		 3394 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3395 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3396 adapter->rss_indir_tbl[j] =
3397 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3398 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3399 }
ed12cc9a 3400 igb_write_rss_indir_tbl(adapter);
06cf2666 3401
b980ac18 3402 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3403 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3404 * offloads as they are enabled by default
3405 */
3406 rxcsum = rd32(E1000_RXCSUM);
3407 rxcsum |= E1000_RXCSUM_PCSD;
3408
3409 if (adapter->hw.mac.type >= e1000_82576)
3410 /* Enable Receive Checksum Offload for SCTP */
3411 rxcsum |= E1000_RXCSUM_CRCOFL;
3412
3413 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3414 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3415
039454a8
AA		 3416 /* Generate RSS hash based on packet types, TCP/UDP
3417 * port numbers and/or IPv4/v6 src and dst addresses
3418 */
f96a8a0b
CW		 3419 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3420 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3421 E1000_MRQC_RSS_FIELD_IPV6 |
3422 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3424
039454a8
AA		 3425 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3426 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3427 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3428 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3429
06cf2666
AD		 3430 /* If VMDq is enabled then we set the appropriate mode for that, else
3431 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3432 * if we are only using one queue
3433 */
06cf2666
AD		 3434 if (adapter->vfs_allocated_count) {
3435 if (hw->mac.type > e1000_82575) {
3436 /* Set the default pool for the PF's first queue */
3437 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3438
06cf2666
AD		 3439 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3440 E1000_VT_CTL_DISABLE_DEF_POOL);
3441 vtctl |= adapter->vfs_allocated_count <<
3442 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3443 wr32(E1000_VT_CTL, vtctl);
3444 }
a99955fc 3445 if (adapter->rss_queues > 1)
f96a8a0b 3446 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3447 else
f96a8a0b 3448 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3449 } else {
f96a8a0b
CW		 3450 if (hw->mac.type != e1000_i211)
3451 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3452 }
3453 igb_vmm_control(adapter);
3454
06cf2666
AD		 3455 wr32(E1000_MRQC, mrqc);
3456}
3457
9d5c8243 3458/**
b980ac18
JK		 3459 * igb_setup_rctl - configure the receive control registers
3460 * @adapter: Board private structure
9d5c8243 3461 **/
d7ee5b3a 3462void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3463{
3464 struct e1000_hw *hw = &adapter->hw;
3465 u32 rctl;
9d5c8243
AK		 3466
3467 rctl = rd32(E1000_RCTL);
3468
3469 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3470 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3471
69d728ba 3472 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3473 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3474
b980ac18 3475 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3476 * redirection as it did with e1000. Newer features require
3477 * that the HW strips the CRC.
73cd78f1 3478 */
87cb7e8c 3479 rctl |= E1000_RCTL_SECRC;
9d5c8243 3480
559e9c49 3481 /* disable store bad packets and clear size bits. */
ec54d7d6 3482 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3483
6ec43fe6
AD		 3484 /* enable LPE to prevent packets larger than max_frame_size */
3485 rctl |= E1000_RCTL_LPE;
9d5c8243 3486
952f72a8
AD		 3487 /* disable queue 0 to prevent tail write w/o re-config */
3488 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3489
e1739522
AD		 3490 /* Attention!!! For SR-IOV PF driver operations you must enable
3491 * queue drop for all VF and PF queues to prevent head of line blocking
3492 * if an un-trusted VF does not provide descriptors to hardware.
3493 */
3494 if (adapter->vfs_allocated_count) {
e1739522
AD		 3495 /* set all queue drop enable bits */
3496 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3497 }
3498
89eaefb6
BG		 3499 /* This is useful for sniffing bad packets. */
3500 if (adapter->netdev->features & NETIF_F_RXALL) {
3501 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3502 * in e1000e_set_rx_mode
3503 */
89eaefb6
BG		 3504 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3505 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3506 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3507
3508 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3509 E1000_RCTL_DPF | /* Allow filtered pause */
3510 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3511 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3512 * and that breaks VLANs.
3513 */
3514 }
3515
9d5c8243
AK		 3516 wr32(E1000_RCTL, rctl);
3517}
3518
7d5753f0 3519static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3520 int vfn)
7d5753f0
AD		 3521{
3522 struct e1000_hw *hw = &adapter->hw;
3523 u32 vmolr;
3524
3525 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3526 * increase the size to support vlan tags
3527 */
7d5753f0
AD		 3528 if (vfn < adapter->vfs_allocated_count &&
3529 adapter->vf_data[vfn].vlans_enabled)
3530 size += VLAN_TAG_SIZE;
3531
3532 vmolr = rd32(E1000_VMOLR(vfn));
3533 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3534 vmolr |= size | E1000_VMOLR_LPE;
3535 wr32(E1000_VMOLR(vfn), vmolr);
3536
3537 return 0;
3538}
3539
e1739522 3540/**
b980ac18
JK		 3541 * igb_rlpml_set - set maximum receive packet size
3542 * @adapter: board private structure
e1739522 3543 *
b980ac18 3544 * Configure maximum receivable packet size.
e1739522
AD		 3545 **/
3546static void igb_rlpml_set(struct igb_adapter *adapter)
3547{
153285f9 3548 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3549 struct e1000_hw *hw = &adapter->hw;
3550 u16 pf_id = adapter->vfs_allocated_count;
3551
e1739522
AD		 3552 if (pf_id) {
3553 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3554 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3555 * to our max jumbo frame size, in case we need to enable
3556 * jumbo frames on one of the rings later.
3557 * This will not pass over-length frames into the default
3558 * queue because it's gated by the VMOLR.RLPML.
3559 */
7d5753f0 3560 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3561 }
3562
3563 wr32(E1000_RLPML, max_frame_size);
3564}
3565
8151d294
WM		 3566static inline void igb_set_vmolr(struct igb_adapter *adapter,
3567 int vfn, bool aupe)
7d5753f0
AD		 3568{
3569 struct e1000_hw *hw = &adapter->hw;
3570 u32 vmolr;
3571
b980ac18 3572 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3573 * we should exit and do nothing
3574 */
3575 if (hw->mac.type < e1000_82576)
3576 return;
3577
3578 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3579 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3580 if (hw->mac.type == e1000_i350) {
3581 u32 dvmolr;
3582
3583 dvmolr = rd32(E1000_DVMOLR(vfn));
3584 dvmolr |= E1000_DVMOLR_STRVLAN;
3585 wr32(E1000_DVMOLR(vfn), dvmolr);
3586 }
8151d294 3587 if (aupe)
b980ac18 3588 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3589 else
3590 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3591
3592 /* clear all bits that might not be set */
3593 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3594
a99955fc 3595 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3596 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3597 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3598 * multicast packets
3599 */
3600 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3601 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3602
3603 wr32(E1000_VMOLR(vfn), vmolr);
3604}
3605
85b430b4 3606/**
b980ac18
JK		 3607 * igb_configure_rx_ring - Configure a receive ring after Reset
3608 * @adapter: board private structure
3609 * @ring: receive ring to be configured
85b430b4 3610 *
b980ac18 3611 * Configure the Rx unit of the MAC after a reset.
85b430b4 3612 **/
d7ee5b3a 3613void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3614 struct igb_ring *ring)
85b430b4
AD		 3615{
3616 struct e1000_hw *hw = &adapter->hw;
3617 u64 rdba = ring->dma;
3618 int reg_idx = ring->reg_idx;
a74420e0 3619 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3620
3621 /* disable the queue */
a74420e0 3622 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3623
3624 /* Set DMA base address registers */
3625 wr32(E1000_RDBAL(reg_idx),
3626 rdba & 0x00000000ffffffffULL);
3627 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3628 wr32(E1000_RDLEN(reg_idx),
b980ac18 3629 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3630
3631 /* initialize head and tail */
fce99e34 3632 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3633 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3634 writel(0, ring->tail);
85b430b4 3635
952f72a8 3636 /* set descriptor configuration */
44390ca6 3637 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3638 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3639 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3640 if (hw->mac.type >= e1000_82580)
757b77e2 3641 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3642 /* Only set Drop Enable if we are supporting multiple queues */
3643 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3644 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3645
3646 wr32(E1000_SRRCTL(reg_idx), srrctl);
3647
7d5753f0 3648 /* set filtering for VMDQ pools */
8151d294 3649 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3650
85b430b4
AD		 3651 rxdctl |= IGB_RX_PTHRESH;
3652 rxdctl |= IGB_RX_HTHRESH << 8;
3653 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3654
3655 /* enable receive descriptor fetching */
3656 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3657 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3658}
3659
9d5c8243 3660/**
b980ac18
JK		 3661 * igb_configure_rx - Configure receive Unit after Reset
3662 * @adapter: board private structure
9d5c8243 3663 *
b980ac18 3664 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3665 **/
3666static void igb_configure_rx(struct igb_adapter *adapter)
3667{
9107584e 3668 int i;
9d5c8243 3669
68d480c4
AD		 3670 /* set UTA to appropriate mode */
3671 igb_set_uta(adapter);
3672
26ad9178
AD		 3673 /* set the correct pool for the PF default MAC address in entry 0 */
3674 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3675 adapter->vfs_allocated_count);
26ad9178 3676
06cf2666 3677 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3678 * the Base and Length of the Rx Descriptor Ring
3679 */
f9d40f6a
AD		 3680 for (i = 0; i < adapter->num_rx_queues; i++)
3681 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3682}
3683
3684/**
b980ac18
JK		 3685 * igb_free_tx_resources - Free Tx Resources per Queue
3686 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3687 *
b980ac18 3688 * Free all transmit software resources
9d5c8243 3689 **/
68fd9910 3690void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3691{
3b644cf6 3692 igb_clean_tx_ring(tx_ring);
9d5c8243 3693
06034649
AD		 3694 vfree(tx_ring->tx_buffer_info);
3695 tx_ring->tx_buffer_info = NULL;
9d5c8243 3696
439705e1
AD		 3697 /* if not set, then don't free */
3698 if (!tx_ring->desc)
3699 return;
3700
59d71989
AD		 3701 dma_free_coherent(tx_ring->dev, tx_ring->size,
3702 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3703
3704 tx_ring->desc = NULL;
3705}
3706
3707/**
b980ac18
JK		 3708 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3709 * @adapter: board private structure
9d5c8243 3710 *
b980ac18 3711 * Free all transmit software resources
9d5c8243
AK		 3712 **/
3713static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3714{
3715 int i;
3716
3717 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3718 if (adapter->tx_ring[i])
3719 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3720}
3721
ebe42d16
AD		 3722void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3723 struct igb_tx_buffer *tx_buffer)
3724{
3725 if (tx_buffer->skb) {
3726 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3727 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3728 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3729 dma_unmap_addr(tx_buffer, dma),
3730 dma_unmap_len(tx_buffer, len),
ebe42d16 3731 DMA_TO_DEVICE);
c9f14bf3 3732 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3733 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3734 dma_unmap_addr(tx_buffer, dma),
3735 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3736 DMA_TO_DEVICE);
3737 }
3738 tx_buffer->next_to_watch = NULL;
3739 tx_buffer->skb = NULL;
c9f14bf3 3740 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3741 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3742}
3743
3744/**
b980ac18
JK		 3745 * igb_clean_tx_ring - Free Tx Buffers
3746 * @tx_ring: ring to be cleaned
9d5c8243 3747 **/
3b644cf6 3748static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3749{
06034649 3750 struct igb_tx_buffer *buffer_info;
9d5c8243 3751 unsigned long size;
6ad4edfc 3752 u16 i;
9d5c8243 3753
06034649 3754 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3755 return;
3756 /* Free all the Tx ring sk_buffs */
3757
3758 for (i = 0; i < tx_ring->count; i++) {
06034649 3759 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3760 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3761 }
3762
dad8a3b3
JF		 3763 netdev_tx_reset_queue(txring_txq(tx_ring));
3764
06034649
AD		 3765 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3766 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3767
3768 /* Zero out the descriptor ring */
9d5c8243
AK		 3769 memset(tx_ring->desc, 0, tx_ring->size);
3770
3771 tx_ring->next_to_use = 0;
3772 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3773}
3774
3775/**
b980ac18
JK		 3776 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3777 * @adapter: board private structure
9d5c8243
AK		 3778 **/
3779static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3780{
3781 int i;
3782
3783 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3784 if (adapter->tx_ring[i])
3785 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3786}
3787
3788/**
b980ac18
JK		 3789 * igb_free_rx_resources - Free Rx Resources
3790 * @rx_ring: ring to clean the resources from
9d5c8243 3791 *
b980ac18 3792 * Free all receive software resources
9d5c8243 3793 **/
68fd9910 3794void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3795{
3b644cf6 3796 igb_clean_rx_ring(rx_ring);
9d5c8243 3797
06034649
AD		 3798 vfree(rx_ring->rx_buffer_info);
3799 rx_ring->rx_buffer_info = NULL;
9d5c8243 3800
439705e1
AD		 3801 /* if not set, then don't free */
3802 if (!rx_ring->desc)
3803 return;
3804
59d71989
AD		 3805 dma_free_coherent(rx_ring->dev, rx_ring->size,
3806 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3807
3808 rx_ring->desc = NULL;
3809}
3810
3811/**
b980ac18
JK		 3812 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3813 * @adapter: board private structure
9d5c8243 3814 *
b980ac18 3815 * Free all receive software resources
9d5c8243
AK		 3816 **/
3817static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3818{
3819 int i;
3820
3821 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3822 if (adapter->rx_ring[i])
3823 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3824}
3825
3826/**
b980ac18
JK		 3827 * igb_clean_rx_ring - Free Rx Buffers per Queue
3828 * @rx_ring: ring to free buffers from
9d5c8243 3829 **/
3b644cf6 3830static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3831{
9d5c8243 3832 unsigned long size;
c023cd88 3833 u16 i;
9d5c8243 3834
1a1c225b
AD		 3835 if (rx_ring->skb)
3836 dev_kfree_skb(rx_ring->skb);
3837 rx_ring->skb = NULL;
3838
06034649 3839 if (!rx_ring->rx_buffer_info)
9d5c8243 3840 return;
439705e1 3841
9d5c8243
AK		 3842 /* Free all the Rx ring sk_buffs */
3843 for (i = 0; i < rx_ring->count; i++) {
06034649 3844 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3845
cbc8e55f
AD		 3846 if (!buffer_info->page)
3847 continue;
3848
3849 dma_unmap_page(rx_ring->dev,
3850 buffer_info->dma,
3851 PAGE_SIZE,
3852 DMA_FROM_DEVICE);
3853 __free_page(buffer_info->page);
3854
1a1c225b 3855 buffer_info->page = NULL;
9d5c8243
AK		 3856 }
3857
06034649
AD		 3858 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3859 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3860
3861 /* Zero out the descriptor ring */
3862 memset(rx_ring->desc, 0, rx_ring->size);
3863
cbc8e55f 3864 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3865 rx_ring->next_to_clean = 0;
3866 rx_ring->next_to_use = 0;
9d5c8243
AK		 3867}
3868
3869/**
b980ac18
JK		 3870 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3871 * @adapter: board private structure
9d5c8243
AK		 3872 **/
3873static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3874{
3875 int i;
3876
3877 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3878 if (adapter->rx_ring[i])
3879 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3880}
3881
3882/**
b980ac18
JK		 3883 * igb_set_mac - Change the Ethernet Address of the NIC
3884 * @netdev: network interface device structure
3885 * @p: pointer to an address structure
9d5c8243 3886 *
b980ac18 3887 * Returns 0 on success, negative on failure
9d5c8243
AK		 3888 **/
3889static int igb_set_mac(struct net_device *netdev, void *p)
3890{
3891 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3892 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3893 struct sockaddr *addr = p;
3894
3895 if (!is_valid_ether_addr(addr->sa_data))
3896 return -EADDRNOTAVAIL;
3897
3898 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3899 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3900
26ad9178
AD		 3901 /* set the correct pool for the new PF MAC address in entry 0 */
3902 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3903 adapter->vfs_allocated_count);
e1739522 3904
9d5c8243
AK		 3905 return 0;
3906}
3907
3908/**
b980ac18
JK		 3909 * igb_write_mc_addr_list - write multicast addresses to MTA
3910 * @netdev: network interface device structure
9d5c8243 3911 *
b980ac18
JK		 3912 * Writes multicast address list to the MTA hash table.
3913 * Returns: -ENOMEM on failure
3914 * 0 on no addresses written
3915 * X on writing X addresses to MTA
9d5c8243 3916 **/
68d480c4 3917static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3918{
3919 struct igb_adapter *adapter = netdev_priv(netdev);
3920 struct e1000_hw *hw = &adapter->hw;
22bedad3 3921 struct netdev_hw_addr *ha;
68d480c4 3922 u8 *mta_list;
9d5c8243
AK		 3923 int i;
3924
4cd24eaf 3925 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3926 /* nothing to program, so clear mc list */
3927 igb_update_mc_addr_list(hw, NULL, 0);
3928 igb_restore_vf_multicasts(adapter);
3929 return 0;
3930 }
9d5c8243 3931
4cd24eaf 3932 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3933 if (!mta_list)
3934 return -ENOMEM;
ff41f8dc 3935
68d480c4 3936 /* The shared function expects a packed array of only addresses. */
48e2f183 3937 i = 0;
22bedad3
JP		 3938 netdev_for_each_mc_addr(ha, netdev)
3939 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3940
68d480c4
AD		 3941 igb_update_mc_addr_list(hw, mta_list, i);
3942 kfree(mta_list);
3943
4cd24eaf 3944 return netdev_mc_count(netdev);
68d480c4
AD		 3945}
3946
3947/**
b980ac18
JK		 3948 * igb_write_uc_addr_list - write unicast addresses to RAR table
3949 * @netdev: network interface device structure
68d480c4 3950 *
b980ac18
JK		 3951 * Writes unicast address list to the RAR table.
3952 * Returns: -ENOMEM on failure/insufficient address space
3953 * 0 on no addresses written
3954 * X on writing X addresses to the RAR table
68d480c4
AD		 3955 **/
3956static int igb_write_uc_addr_list(struct net_device *netdev)
3957{
3958 struct igb_adapter *adapter = netdev_priv(netdev);
3959 struct e1000_hw *hw = &adapter->hw;
3960 unsigned int vfn = adapter->vfs_allocated_count;
3961 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3962 int count = 0;
3963
3964 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3965 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3966 return -ENOMEM;
9d5c8243 3967
32e7bfc4 3968 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3969 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3970
3971 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3972 if (!rar_entries)
3973 break;
26ad9178 3974 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3975 rar_entries--,
3976 vfn);
68d480c4 3977 count++;
ff41f8dc
AD		 3978 }
3979 }
3980 /* write the addresses in reverse order to avoid write combining */
3981 for (; rar_entries > 0 ; rar_entries--) {
3982 wr32(E1000_RAH(rar_entries), 0);
3983 wr32(E1000_RAL(rar_entries), 0);
3984 }
3985 wrfl();
3986
68d480c4
AD		 3987 return count;
3988}
3989
3990/**
b980ac18
JK		 3991 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3992 * @netdev: network interface device structure
68d480c4 3993 *
b980ac18
JK		 3994 * The set_rx_mode entry point is called whenever the unicast or multicast
3995 * address lists or the network interface flags are updated. This routine is
3996 * responsible for configuring the hardware for proper unicast, multicast,
3997 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3998 **/
3999static void igb_set_rx_mode(struct net_device *netdev)
4000{
4001 struct igb_adapter *adapter = netdev_priv(netdev);
4002 struct e1000_hw *hw = &adapter->hw;
4003 unsigned int vfn = adapter->vfs_allocated_count;
4004 u32 rctl, vmolr = 0;
4005 int count;
4006
4007 /* Check for Promiscuous and All Multicast modes */
4008 rctl = rd32(E1000_RCTL);
4009
4010 /* clear the effected bits */
4011 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4012
4013 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4014 /* retain VLAN HW filtering if in VT mode */
7e44892c 4015 if (adapter->vfs_allocated_count)
6f3dc319 4016 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4017 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4018 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4019 } else {
4020 if (netdev->flags & IFF_ALLMULTI) {
4021 rctl |= E1000_RCTL_MPE;
4022 vmolr |= E1000_VMOLR_MPME;
4023 } else {
b980ac18 4024 /* Write addresses to the MTA, if the attempt fails
25985edc 4025 * then we should just turn on promiscuous mode so
68d480c4
AD		 4026 * that we can at least receive multicast traffic
4027 */
4028 count = igb_write_mc_addr_list(netdev);
4029 if (count < 0) {
4030 rctl |= E1000_RCTL_MPE;
4031 vmolr |= E1000_VMOLR_MPME;
4032 } else if (count) {
4033 vmolr |= E1000_VMOLR_ROMPE;
4034 }
4035 }
b980ac18 4036 /* Write addresses to available RAR registers, if there is not
68d480c4 4037 * sufficient space to store all the addresses then enable
25985edc 4038 * unicast promiscuous mode
68d480c4
AD		 4039 */
4040 count = igb_write_uc_addr_list(netdev);
4041 if (count < 0) {
4042 rctl |= E1000_RCTL_UPE;
4043 vmolr |= E1000_VMOLR_ROPE;
4044 }
4045 rctl |= E1000_RCTL_VFE;
28fc06f5 4046 }
68d480c4 4047 wr32(E1000_RCTL, rctl);
28fc06f5 4048
b980ac18 4049 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4050 * the VMOLR to enable the appropriate modes. Without this workaround
4051 * we will have issues with VLAN tag stripping not being done for frames
4052 * that are only arriving because we are the default pool
4053 */
f96a8a0b 4054 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4055 return;
9d5c8243 4056
68d480c4 4057 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4058 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4059 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4060 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4061}
4062
13800469
GR		 4063static void igb_check_wvbr(struct igb_adapter *adapter)
4064{
4065 struct e1000_hw *hw = &adapter->hw;
4066 u32 wvbr = 0;
4067
4068 switch (hw->mac.type) {
4069 case e1000_82576:
4070 case e1000_i350:
81ad807b
CW		 4071 wvbr = rd32(E1000_WVBR);
4072 if (!wvbr)
13800469
GR		 4073 return;
4074 break;
4075 default:
4076 break;
4077 }
4078
4079 adapter->wvbr |= wvbr;
4080}
4081
4082#define IGB_STAGGERED_QUEUE_OFFSET 8
4083
4084static void igb_spoof_check(struct igb_adapter *adapter)
4085{
4086 int j;
4087
4088 if (!adapter->wvbr)
4089 return;
4090
9005df38 4091 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4092 if (adapter->wvbr & (1 << j) ||
4093 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4094 dev_warn(&adapter->pdev->dev,
4095 "Spoof event(s) detected on VF %d\n", j);
4096 adapter->wvbr &=
4097 ~((1 << j) |
4098 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4099 }
4100 }
4101}
4102
9d5c8243 4103/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4104 * the phy
4105 */
9d5c8243
AK		 4106static void igb_update_phy_info(unsigned long data)
4107{
4108 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4109 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4110}
4111
4d6b725e 4112/**
b980ac18
JK		 4113 * igb_has_link - check shared code for link and determine up/down
4114 * @adapter: pointer to driver private info
4d6b725e 4115 **/
3145535a 4116bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4117{
4118 struct e1000_hw *hw = &adapter->hw;
4119 bool link_active = false;
4d6b725e
AD		 4120
4121 /* get_link_status is set on LSC (link status) interrupt or
4122 * rx sequence error interrupt. get_link_status will stay
4123 * false until the e1000_check_for_link establishes link
4124 * for copper adapters ONLY
4125 */
4126 switch (hw->phy.media_type) {
4127 case e1000_media_type_copper:
e5c3370f
AA		 4128 if (!hw->mac.get_link_status)
4129 return true;
4d6b725e 4130 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4131 hw->mac.ops.check_for_link(hw);
4132 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4133 break;
4134 default:
4135 case e1000_media_type_unknown:
4136 break;
4137 }
4138
aa9b8cc4
AA		 4139 if (((hw->mac.type == e1000_i210) ||
4140 (hw->mac.type == e1000_i211)) &&
4141 (hw->phy.id == I210_I_PHY_ID)) {
4142 if (!netif_carrier_ok(adapter->netdev)) {
4143 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4144 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4145 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4146 adapter->link_check_timeout = jiffies;
4147 }
4148 }
4149
4d6b725e
AD		 4150 return link_active;
4151}
4152
563988dc
SA		 4153static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4154{
4155 bool ret = false;
4156 u32 ctrl_ext, thstat;
4157
f96a8a0b 4158 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4159 if (hw->mac.type == e1000_i350) {
4160 thstat = rd32(E1000_THSTAT);
4161 ctrl_ext = rd32(E1000_CTRL_EXT);
4162
4163 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4164 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4165 ret = !!(thstat & event);
563988dc
SA		 4166 }
4167
4168 return ret;
4169}
4170
1516f0a6
CW		 4171/**
4172 * igb_check_lvmmc - check for malformed packets received
4173 * and indicated in LVMMC register
4174 * @adapter: pointer to adapter
4175 **/
4176static void igb_check_lvmmc(struct igb_adapter *adapter)
4177{
4178 struct e1000_hw *hw = &adapter->hw;
4179 u32 lvmmc;
4180
4181 lvmmc = rd32(E1000_LVMMC);
4182 if (lvmmc) {
4183 if (unlikely(net_ratelimit())) {
4184 netdev_warn(adapter->netdev,
4185 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4186 lvmmc);
4187 }
4188 }
4189}
4190
9d5c8243 4191/**
b980ac18
JK		 4192 * igb_watchdog - Timer Call-back
4193 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4194 **/
4195static void igb_watchdog(unsigned long data)
4196{
4197 struct igb_adapter *adapter = (struct igb_adapter *)data;
4198 /* Do the rest outside of interrupt context */
4199 schedule_work(&adapter->watchdog_task);
4200}
4201
4202static void igb_watchdog_task(struct work_struct *work)
4203{
4204 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4205 struct igb_adapter,
4206 watchdog_task);
9d5c8243 4207 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4208 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4209 struct net_device *netdev = adapter->netdev;
563988dc 4210 u32 link;
7a6ea550 4211 int i;
56cec249 4212 u32 connsw;
9d5c8243 4213
4d6b725e 4214 link = igb_has_link(adapter);
aa9b8cc4
AA		 4215
4216 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4217 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4218 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4219 else
4220 link = false;
4221 }
4222
56cec249
CW		 4223 /* Force link down if we have fiber to swap to */
4224 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4225 if (hw->phy.media_type == e1000_media_type_copper) {
4226 connsw = rd32(E1000_CONNSW);
4227 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4228 link = 0;
4229 }
4230 }
9d5c8243 4231 if (link) {
2bdfc4e2
CW		 4232 /* Perform a reset if the media type changed. */
4233 if (hw->dev_spec._82575.media_changed) {
4234 hw->dev_spec._82575.media_changed = false;
4235 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4236 igb_reset(adapter);
4237 }
749ab2cd
YZ		 4238 /* Cancel scheduled suspend requests. */
4239 pm_runtime_resume(netdev->dev.parent);
4240
9d5c8243
AK		 4241 if (!netif_carrier_ok(netdev)) {
4242 u32 ctrl;
9005df38 4243
330a6d6a 4244 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4245 &adapter->link_speed,
4246 &adapter->link_duplex);
9d5c8243
AK		 4247
4248 ctrl = rd32(E1000_CTRL);
527d47c1 4249 /* Links status message must follow this format */
c75c4edf
CW		 4250 netdev_info(netdev,
4251 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4252 netdev->name,
4253 adapter->link_speed,
4254 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4255 "Full" : "Half",
4256 (ctrl & E1000_CTRL_TFCE) &&
4257 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4258 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4259 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4260
f4c01e96
CW		 4261 /* disable EEE if enabled */
4262 if ((adapter->flags & IGB_FLAG_EEE) &&
4263 (adapter->link_duplex == HALF_DUPLEX)) {
4264 dev_info(&adapter->pdev->dev,
4265 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4266 adapter->hw.dev_spec._82575.eee_disable = true;
4267 adapter->flags &= ~IGB_FLAG_EEE;
4268 }
4269
c0ba4778
KS		 4270 /* check if SmartSpeed worked */
4271 igb_check_downshift(hw);
4272 if (phy->speed_downgraded)
4273 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4274
563988dc 4275 /* check for thermal sensor event */
876d2d6f 4276 if (igb_thermal_sensor_event(hw,
d34a15ab 4277 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4278 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4279
d07f3e37 4280 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4281 adapter->tx_timeout_factor = 1;
4282 switch (adapter->link_speed) {
4283 case SPEED_10:
9d5c8243
AK		 4284 adapter->tx_timeout_factor = 14;
4285 break;
4286 case SPEED_100:
9d5c8243
AK		 4287 /* maybe add some timeout factor ? */
4288 break;
4289 }
4290
4291 netif_carrier_on(netdev);
9d5c8243 4292
4ae196df 4293 igb_ping_all_vfs(adapter);
17dc566c 4294 igb_check_vf_rate_limit(adapter);
4ae196df 4295
4b1a9877 4296 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4297 if (!test_bit(__IGB_DOWN, &adapter->state))
4298 mod_timer(&adapter->phy_info_timer,
4299 round_jiffies(jiffies + 2 * HZ));
4300 }
4301 } else {
4302 if (netif_carrier_ok(netdev)) {
4303 adapter->link_speed = 0;
4304 adapter->link_duplex = 0;
563988dc
SA		 4305
4306 /* check for thermal sensor event */
876d2d6f
JK		 4307 if (igb_thermal_sensor_event(hw,
4308 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4309 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4310 }
563988dc 4311
527d47c1 4312 /* Links status message must follow this format */
c75c4edf 4313 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4314 netdev->name);
9d5c8243 4315 netif_carrier_off(netdev);
4b1a9877 4316
4ae196df
AD		 4317 igb_ping_all_vfs(adapter);
4318
4b1a9877 4319 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4320 if (!test_bit(__IGB_DOWN, &adapter->state))
4321 mod_timer(&adapter->phy_info_timer,
4322 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4323
56cec249
CW		 4324 /* link is down, time to check for alternate media */
4325 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4326 igb_check_swap_media(adapter);
4327 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4328 schedule_work(&adapter->reset_task);
4329 /* return immediately */
4330 return;
4331 }
4332 }
749ab2cd
YZ		 4333 pm_schedule_suspend(netdev->dev.parent,
4334 MSEC_PER_SEC * 5);
56cec249
CW		 4335
4336 /* also check for alternate media here */
4337 } else if (!netif_carrier_ok(netdev) &&
4338 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4339 igb_check_swap_media(adapter);
4340 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4341 schedule_work(&adapter->reset_task);
4342 /* return immediately */
4343 return;
4344 }
9d5c8243
AK		 4345 }
4346 }
4347
12dcd86b
ED		 4348 spin_lock(&adapter->stats64_lock);
4349 igb_update_stats(adapter, &adapter->stats64);
4350 spin_unlock(&adapter->stats64_lock);
9d5c8243 4351
dbabb065 4352 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4353 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4354 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4355 /* We've lost link, so the controller stops DMA,
4356 * but we've got queued Tx work that's never going
4357 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4358 * (Do the reset outside of interrupt context).
4359 */
dbabb065
AD		 4360 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4361 adapter->tx_timeout_count++;
4362 schedule_work(&adapter->reset_task);
4363 /* return immediately since reset is imminent */
4364 return;
4365 }
9d5c8243 4366 }
9d5c8243 4367
dbabb065 4368 /* Force detection of hung controller every watchdog period */
6d095fa8 4369 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4370 }
f7ba205e 4371
b980ac18 4372 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4373 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4374 u32 eics = 0;
9005df38 4375
0d1ae7f4
AD		 4376 for (i = 0; i < adapter->num_q_vectors; i++)
4377 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4378 wr32(E1000_EICS, eics);
4379 } else {
4380 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4381 }
9d5c8243 4382
13800469 4383 igb_spoof_check(adapter);
fc580751 4384 igb_ptp_rx_hang(adapter);
13800469 4385
1516f0a6
CW		 4386 /* Check LVMMC register on i350/i354 only */
4387 if ((adapter->hw.mac.type == e1000_i350) ||
4388 (adapter->hw.mac.type == e1000_i354))
4389 igb_check_lvmmc(adapter);
4390
9d5c8243 4391 /* Reset the timer */
aa9b8cc4
AA		 4392 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4393 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4394 mod_timer(&adapter->watchdog_timer,
4395 round_jiffies(jiffies + HZ));
4396 else
4397 mod_timer(&adapter->watchdog_timer,
4398 round_jiffies(jiffies + 2 * HZ));
4399 }
9d5c8243
AK		 4400}
4401
4402enum latency_range {
4403 lowest_latency = 0,
4404 low_latency = 1,
4405 bulk_latency = 2,
4406 latency_invalid = 255
4407};
4408
6eb5a7f1 4409/**
b980ac18
JK		 4410 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4411 * @q_vector: pointer to q_vector
6eb5a7f1 4412 *
b980ac18
JK		 4413 * Stores a new ITR value based on strictly on packet size. This
4414 * algorithm is less sophisticated than that used in igb_update_itr,
4415 * due to the difficulty of synchronizing statistics across multiple
4416 * receive rings. The divisors and thresholds used by this function
4417 * were determined based on theoretical maximum wire speed and testing
4418 * data, in order to minimize response time while increasing bulk
4419 * throughput.
406d4965 4420 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4421 * NOTE: This function is called only when operating in a multiqueue
4422 * receive environment.
6eb5a7f1 4423 **/
047e0030 4424static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4425{
047e0030 4426 int new_val = q_vector->itr_val;
6eb5a7f1 4427 int avg_wire_size = 0;
047e0030 4428 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4429 unsigned int packets;
9d5c8243 4430
6eb5a7f1
AD		 4431 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4432 * ints/sec - ITR timer value of 120 ticks.
4433 */
4434 if (adapter->link_speed != SPEED_1000) {
0ba82994 4435 new_val = IGB_4K_ITR;
6eb5a7f1 4436 goto set_itr_val;
9d5c8243 4437 }
047e0030 4438
0ba82994
AD		 4439 packets = q_vector->rx.total_packets;
4440 if (packets)
4441 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4442
0ba82994
AD		 4443 packets = q_vector->tx.total_packets;
4444 if (packets)
4445 avg_wire_size = max_t(u32, avg_wire_size,
4446 q_vector->tx.total_bytes / packets);
047e0030
AD		 4447
4448 /* if avg_wire_size isn't set no work was done */
4449 if (!avg_wire_size)
4450 goto clear_counts;
9d5c8243 4451
6eb5a7f1
AD		 4452 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4453 avg_wire_size += 24;
4454
4455 /* Don't starve jumbo frames */
4456 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4457
6eb5a7f1
AD		 4458 /* Give a little boost to mid-size frames */
4459 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4460 new_val = avg_wire_size / 3;
4461 else
4462 new_val = avg_wire_size / 2;
9d5c8243 4463
0ba82994
AD		 4464 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4465 if (new_val < IGB_20K_ITR &&
4466 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4467 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4468 new_val = IGB_20K_ITR;
abe1c363 4469
6eb5a7f1 4470set_itr_val:
047e0030
AD		 4471 if (new_val != q_vector->itr_val) {
4472 q_vector->itr_val = new_val;
4473 q_vector->set_itr = 1;
9d5c8243 4474 }
6eb5a7f1 4475clear_counts:
0ba82994
AD		 4476 q_vector->rx.total_bytes = 0;
4477 q_vector->rx.total_packets = 0;
4478 q_vector->tx.total_bytes = 0;
4479 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4480}
4481
4482/**
b980ac18
JK		 4483 * igb_update_itr - update the dynamic ITR value based on statistics
4484 * @q_vector: pointer to q_vector
4485 * @ring_container: ring info to update the itr for
4486 *
4487 * Stores a new ITR value based on packets and byte
4488 * counts during the last interrupt. The advantage of per interrupt
4489 * computation is faster updates and more accurate ITR for the current
4490 * traffic pattern. Constants in this function were computed
4491 * based on theoretical maximum wire speed and thresholds were set based
4492 * on testing data as well as attempting to minimize response time
4493 * while increasing bulk throughput.
406d4965 4494 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4495 * NOTE: These calculations are only valid when operating in a single-
4496 * queue environment.
9d5c8243 4497 **/
0ba82994
AD		 4498static void igb_update_itr(struct igb_q_vector *q_vector,
4499 struct igb_ring_container *ring_container)
9d5c8243 4500{
0ba82994
AD		 4501 unsigned int packets = ring_container->total_packets;
4502 unsigned int bytes = ring_container->total_bytes;
4503 u8 itrval = ring_container->itr;
9d5c8243 4504
0ba82994 4505 /* no packets, exit with status unchanged */
9d5c8243 4506 if (packets == 0)
0ba82994 4507 return;
9d5c8243 4508
0ba82994 4509 switch (itrval) {
9d5c8243
AK		 4510 case lowest_latency:
4511 /* handle TSO and jumbo frames */
4512 if (bytes/packets > 8000)
0ba82994 4513 itrval = bulk_latency;
9d5c8243 4514 else if ((packets < 5) && (bytes > 512))
0ba82994 4515 itrval = low_latency;
9d5c8243
AK		 4516 break;
4517 case low_latency: /* 50 usec aka 20000 ints/s */
4518 if (bytes > 10000) {
4519 /* this if handles the TSO accounting */
d34a15ab 4520 if (bytes/packets > 8000)
0ba82994 4521 itrval = bulk_latency;
d34a15ab 4522 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4523 itrval = bulk_latency;
d34a15ab 4524 else if ((packets > 35))
0ba82994 4525 itrval = lowest_latency;
9d5c8243 4526 } else if (bytes/packets > 2000) {
0ba82994 4527 itrval = bulk_latency;
9d5c8243 4528 } else if (packets <= 2 && bytes < 512) {
0ba82994 4529 itrval = lowest_latency;
9d5c8243
AK		 4530 }
4531 break;
4532 case bulk_latency: /* 250 usec aka 4000 ints/s */
4533 if (bytes > 25000) {
4534 if (packets > 35)
0ba82994 4535 itrval = low_latency;
1e5c3d21 4536 } else if (bytes < 1500) {
0ba82994 4537 itrval = low_latency;
9d5c8243
AK		 4538 }
4539 break;
4540 }
4541
0ba82994
AD		 4542 /* clear work counters since we have the values we need */
4543 ring_container->total_bytes = 0;
4544 ring_container->total_packets = 0;
4545
4546 /* write updated itr to ring container */
4547 ring_container->itr = itrval;
9d5c8243
AK		 4548}
4549
0ba82994 4550static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4551{
0ba82994 4552 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4553 u32 new_itr = q_vector->itr_val;
0ba82994 4554 u8 current_itr = 0;
9d5c8243
AK		 4555
4556 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4557 if (adapter->link_speed != SPEED_1000) {
4558 current_itr = 0;
0ba82994 4559 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4560 goto set_itr_now;
4561 }
4562
0ba82994
AD		 4563 igb_update_itr(q_vector, &q_vector->tx);
4564 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4565
0ba82994 4566 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4567
6eb5a7f1 4568 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4569 if (current_itr == lowest_latency &&
4570 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4571 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4572 current_itr = low_latency;
4573
9d5c8243
AK		 4574 switch (current_itr) {
4575 /* counts and packets in update_itr are dependent on these numbers */
4576 case lowest_latency:
0ba82994 4577 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4578 break;
4579 case low_latency:
0ba82994 4580 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4581 break;
4582 case bulk_latency:
0ba82994 4583 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4584 break;
4585 default:
4586 break;
4587 }
4588
4589set_itr_now:
047e0030 4590 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4591 /* this attempts to bias the interrupt rate towards Bulk
4592 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4593 * increasing
4594 */
047e0030 4595 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4596 max((new_itr * q_vector->itr_val) /
4597 (new_itr + (q_vector->itr_val >> 2)),
4598 new_itr) : new_itr;
9d5c8243
AK		 4599 /* Don't write the value here; it resets the adapter's
4600 * internal timer, and causes us to delay far longer than
4601 * we should between interrupts. Instead, we write the ITR
4602 * value at the beginning of the next interrupt so the timing
4603 * ends up being correct.
4604 */
047e0030
AD		 4605 q_vector->itr_val = new_itr;
4606 q_vector->set_itr = 1;
9d5c8243 4607 }
9d5c8243
AK		 4608}
4609
c50b52a0
SH		 4610static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4611 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4612{
4613 struct e1000_adv_tx_context_desc *context_desc;
4614 u16 i = tx_ring->next_to_use;
4615
4616 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4617
4618 i++;
4619 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4620
4621 /* set bits to identify this as an advanced context descriptor */
4622 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4623
4624 /* For 82575, context index must be unique per ring. */
866cff06 4625 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4626 mss_l4len_idx |= tx_ring->reg_idx << 4;
4627
4628 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4629 context_desc->seqnum_seed = 0;
4630 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4631 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4632}
4633
7af40ad9
AD		 4634static int igb_tso(struct igb_ring *tx_ring,
4635 struct igb_tx_buffer *first,
4636 u8 *hdr_len)
9d5c8243 4637{
7af40ad9 4638 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4639 u32 vlan_macip_lens, type_tucmd;
4640 u32 mss_l4len_idx, l4len;
06c14e5a 4641 int err;
7d13a7d0 4642
ed6aa105
AD		 4643 if (skb->ip_summed != CHECKSUM_PARTIAL)
4644 return 0;
4645
7d13a7d0
AD		 4646 if (!skb_is_gso(skb))
4647 return 0;
9d5c8243 4648
06c14e5a
FR		 4649 err = skb_cow_head(skb, 0);
4650 if (err < 0)
4651 return err;
9d5c8243 4652
7d13a7d0
AD		 4653 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4654 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4655
7c4d16ff 4656 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4657 struct iphdr *iph = ip_hdr(skb);
4658 iph->tot_len = 0;
4659 iph->check = 0;
4660 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4661 iph->daddr, 0,
4662 IPPROTO_TCP,
4663 0);
7d13a7d0 4664 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4665 first->tx_flags |= IGB_TX_FLAGS_TSO |
4666 IGB_TX_FLAGS_CSUM |
4667 IGB_TX_FLAGS_IPV4;
8e1e8a47 4668 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4669 ipv6_hdr(skb)->payload_len = 0;
4670 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4671 &ipv6_hdr(skb)->daddr,
4672 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4673 first->tx_flags |= IGB_TX_FLAGS_TSO |
4674 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4675 }
4676
7af40ad9 4677 /* compute header lengths */
7d13a7d0
AD		 4678 l4len = tcp_hdrlen(skb);
4679 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4680
7af40ad9
AD		 4681 /* update gso size and bytecount with header size */
4682 first->gso_segs = skb_shinfo(skb)->gso_segs;
4683 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4684
9d5c8243 4685 /* MSS L4LEN IDX */
7d13a7d0
AD		 4686 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4687 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4688
7d13a7d0
AD		 4689 /* VLAN MACLEN IPLEN */
4690 vlan_macip_lens = skb_network_header_len(skb);
4691 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4692 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4693
7d13a7d0 4694 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4695
7d13a7d0 4696 return 1;
9d5c8243
AK		 4697}
4698
7af40ad9 4699static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4700{
7af40ad9 4701 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4702 u32 vlan_macip_lens = 0;
4703 u32 mss_l4len_idx = 0;
4704 u32 type_tucmd = 0;
9d5c8243 4705
7d13a7d0 4706 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4707 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4708 return;
7d13a7d0
AD		 4709 } else {
4710 u8 l4_hdr = 0;
9005df38 4711
7af40ad9 4712 switch (first->protocol) {
7c4d16ff 4713 case htons(ETH_P_IP):
7d13a7d0
AD		 4714 vlan_macip_lens |= skb_network_header_len(skb);
4715 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4716 l4_hdr = ip_hdr(skb)->protocol;
4717 break;
7c4d16ff 4718 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4719 vlan_macip_lens |= skb_network_header_len(skb);
4720 l4_hdr = ipv6_hdr(skb)->nexthdr;
4721 break;
4722 default:
4723 if (unlikely(net_ratelimit())) {
4724 dev_warn(tx_ring->dev,
b980ac18
JK		 4725 "partial checksum but proto=%x!\n",
4726 first->protocol);
fa4a7ef3 4727 }
7d13a7d0
AD		 4728 break;
4729 }
fa4a7ef3 4730
7d13a7d0
AD		 4731 switch (l4_hdr) {
4732 case IPPROTO_TCP:
4733 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4734 mss_l4len_idx = tcp_hdrlen(skb) <<
4735 E1000_ADVTXD_L4LEN_SHIFT;
4736 break;
4737 case IPPROTO_SCTP:
4738 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4739 mss_l4len_idx = sizeof(struct sctphdr) <<
4740 E1000_ADVTXD_L4LEN_SHIFT;
4741 break;
4742 case IPPROTO_UDP:
4743 mss_l4len_idx = sizeof(struct udphdr) <<
4744 E1000_ADVTXD_L4LEN_SHIFT;
4745 break;
4746 default:
4747 if (unlikely(net_ratelimit())) {
4748 dev_warn(tx_ring->dev,
b980ac18
JK		 4749 "partial checksum but l4 proto=%x!\n",
4750 l4_hdr);
44b0cda3 4751 }
7d13a7d0 4752 break;
9d5c8243 4753 }
7af40ad9
AD		 4754
4755 /* update TX checksum flag */
4756 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4757 }
9d5c8243 4758
7d13a7d0 4759 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4760 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4761
7d13a7d0 4762 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4763}
4764
1d9daf45
AD		 4765#define IGB_SET_FLAG(_input, _flag, _result) \
4766 ((_flag <= _result) ? \
4767 ((u32)(_input & _flag) * (_result / _flag)) : \
4768 ((u32)(_input & _flag) / (_flag / _result)))
4769
4770static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4771{
4772 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4773 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4774 E1000_ADVTXD_DCMD_DEXT |
4775 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4776
4777 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4778 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4779 (E1000_ADVTXD_DCMD_VLE));
4780
4781 /* set segmentation bits for TSO */
4782 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4783 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4784
4785 /* set timestamp bit if present */
1d9daf45
AD		 4786 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4787 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4788
1d9daf45
AD		 4789 /* insert frame checksum */
4790 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4791
4792 return cmd_type;
4793}
4794
7af40ad9
AD		 4795static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4796 union e1000_adv_tx_desc *tx_desc,
4797 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4798{
4799 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4800
1d9daf45
AD		 4801 /* 82575 requires a unique index per ring */
4802 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4803 olinfo_status |= tx_ring->reg_idx << 4;
4804
4805 /* insert L4 checksum */
1d9daf45
AD		 4806 olinfo_status |= IGB_SET_FLAG(tx_flags,
4807 IGB_TX_FLAGS_CSUM,
4808 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4809
1d9daf45
AD		 4810 /* insert IPv4 checksum */
4811 olinfo_status |= IGB_SET_FLAG(tx_flags,
4812 IGB_TX_FLAGS_IPV4,
4813 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4814
7af40ad9 4815 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4816}
4817
6f19e12f
DM		 4818static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4819{
4820 struct net_device *netdev = tx_ring->netdev;
4821
4822 netif_stop_subqueue(netdev, tx_ring->queue_index);
4823
4824 /* Herbert's original patch had:
4825 * smp_mb__after_netif_stop_queue();
4826 * but since that doesn't exist yet, just open code it.
4827 */
4828 smp_mb();
4829
4830 /* We need to check again in a case another CPU has just
4831 * made room available.
4832 */
4833 if (igb_desc_unused(tx_ring) < size)
4834 return -EBUSY;
4835
4836 /* A reprieve! */
4837 netif_wake_subqueue(netdev, tx_ring->queue_index);
4838
4839 u64_stats_update_begin(&tx_ring->tx_syncp2);
4840 tx_ring->tx_stats.restart_queue2++;
4841 u64_stats_update_end(&tx_ring->tx_syncp2);
4842
4843 return 0;
4844}
4845
4846static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4847{
4848 if (igb_desc_unused(tx_ring) >= size)
4849 return 0;
4850 return __igb_maybe_stop_tx(tx_ring, size);
4851}
4852
7af40ad9
AD		 4853static void igb_tx_map(struct igb_ring *tx_ring,
4854 struct igb_tx_buffer *first,
ebe42d16 4855 const u8 hdr_len)
9d5c8243 4856{
7af40ad9 4857 struct sk_buff *skb = first->skb;
c9f14bf3 4858 struct igb_tx_buffer *tx_buffer;
ebe42d16 4859 union e1000_adv_tx_desc *tx_desc;
80d0759e 4860 struct skb_frag_struct *frag;
ebe42d16 4861 dma_addr_t dma;
80d0759e 4862 unsigned int data_len, size;
7af40ad9 4863 u32 tx_flags = first->tx_flags;
1d9daf45 4864 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4865 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4866
4867 tx_desc = IGB_TX_DESC(tx_ring, i);
4868
80d0759e
AD		 4869 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4870
4871 size = skb_headlen(skb);
4872 data_len = skb->data_len;
ebe42d16
AD		 4873
4874 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4875
80d0759e
AD		 4876 tx_buffer = first;
4877
4878 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4879 if (dma_mapping_error(tx_ring->dev, dma))
4880 goto dma_error;
4881
4882 /* record length, and DMA address */
4883 dma_unmap_len_set(tx_buffer, len, size);
4884 dma_unmap_addr_set(tx_buffer, dma, dma);
4885
4886 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4887
ebe42d16
AD		 4888 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4889 tx_desc->read.cmd_type_len =
1d9daf45 4890 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4891
4892 i++;
4893 tx_desc++;
4894 if (i == tx_ring->count) {
4895 tx_desc = IGB_TX_DESC(tx_ring, 0);
4896 i = 0;
4897 }
80d0759e 4898 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4899
4900 dma += IGB_MAX_DATA_PER_TXD;
4901 size -= IGB_MAX_DATA_PER_TXD;
4902
ebe42d16
AD		 4903 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4904 }
4905
4906 if (likely(!data_len))
4907 break;
2bbfebe2 4908
1d9daf45 4909 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4910
65689fef 4911 i++;
ebe42d16
AD		 4912 tx_desc++;
4913 if (i == tx_ring->count) {
4914 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4915 i = 0;
ebe42d16 4916 }
80d0759e 4917 tx_desc->read.olinfo_status = 0;
65689fef 4918
9e903e08 4919 size = skb_frag_size(frag);
ebe42d16
AD		 4920 data_len -= size;
4921
4922 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4923 size, DMA_TO_DEVICE);
6366ad33 4924
c9f14bf3 4925 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4926 }
4927
ebe42d16 4928 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4929 cmd_type |= size | IGB_TXD_DCMD;
4930 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4931
80d0759e
AD		 4932 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4933
8542db05
AD		 4934 /* set the timestamp */
4935 first->time_stamp = jiffies;
4936
b980ac18 4937 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4938 * are new descriptors to fetch. (Only applicable for weak-ordered
4939 * memory model archs, such as IA-64).
4940 *
4941 * We also need this memory barrier to make certain all of the
4942 * status bits have been updated before next_to_watch is written.
4943 */
4944 wmb();
4945
8542db05 4946 /* set next_to_watch value indicating a packet is present */
ebe42d16 4947 first->next_to_watch = tx_desc;
9d5c8243 4948
ebe42d16
AD		 4949 i++;
4950 if (i == tx_ring->count)
4951 i = 0;
6366ad33 4952
ebe42d16 4953 tx_ring->next_to_use = i;
6366ad33 4954
6f19e12f
DM		 4955 /* Make sure there is space in the ring for the next send. */
4956 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4957
4958 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 4959 writel(i, tx_ring->tail);
4960
4961 /* we need this if more than one processor can write to our tail
4962 * at a time, it synchronizes IO on IA64/Altix systems
4963 */
4964 mmiowb();
4965 }
ebe42d16
AD		 4966 return;
4967
4968dma_error:
4969 dev_err(tx_ring->dev, "TX DMA map failed\n");
4970
4971 /* clear dma mappings for failed tx_buffer_info map */
4972 for (;;) {
c9f14bf3
AD		 4973 tx_buffer = &tx_ring->tx_buffer_info[i];
4974 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4975 if (tx_buffer == first)
ebe42d16 4976 break;
a77ff709
NN		 4977 if (i == 0)
4978 i = tx_ring->count;
6366ad33 4979 i--;
6366ad33
AD		 4980 }
4981
9d5c8243 4982 tx_ring->next_to_use = i;
9d5c8243
AK		 4983}
4984
cd392f5c
AD		 4985netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4986 struct igb_ring *tx_ring)
9d5c8243 4987{
8542db05 4988 struct igb_tx_buffer *first;
ebe42d16 4989 int tso;
91d4ee33 4990 u32 tx_flags = 0;
21ba6fe1 4991 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4992 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4993 u8 hdr_len = 0;
9d5c8243 4994
21ba6fe1
AD		 4995 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4996 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4997 * + 2 desc gap to keep tail from touching head,
9d5c8243 4998 * + 1 desc for context descriptor,
21ba6fe1
AD		 4999 * otherwise try next time
5000 */
5001 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
5002 unsigned short f;
9005df38 5003
21ba6fe1
AD		 5004 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5005 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5006 } else {
5007 count += skb_shinfo(skb)->nr_frags;
5008 }
5009
5010 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5011 /* this is a hard error */
9d5c8243
AK		 5012 return NETDEV_TX_BUSY;
5013 }
33af6bcc 5014
7af40ad9
AD		 5015 /* record the location of the first descriptor for this packet */
5016 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5017 first->skb = skb;
5018 first->bytecount = skb->len;
5019 first->gso_segs = 1;
5020
b646c22e
AD		 5021 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5022 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5023
ed4420a3
JK		 5024 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5025 &adapter->state)) {
b646c22e
AD		 5026 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5027 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5028
5029 adapter->ptp_tx_skb = skb_get(skb);
5030 adapter->ptp_tx_start = jiffies;
5031 if (adapter->hw.mac.type == e1000_82576)
5032 schedule_work(&adapter->ptp_tx_work);
5033 }
33af6bcc 5034 }
9d5c8243 5035
afc835d1
JK		 5036 skb_tx_timestamp(skb);
5037
df8a39de 5038 if (skb_vlan_tag_present(skb)) {
9d5c8243 5039 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5040 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5041 }
5042
7af40ad9
AD		 5043 /* record initial flags and protocol */
5044 first->tx_flags = tx_flags;
5045 first->protocol = protocol;
cdfd01fc 5046
7af40ad9
AD		 5047 tso = igb_tso(tx_ring, first, &hdr_len);
5048 if (tso < 0)
7d13a7d0 5049 goto out_drop;
7af40ad9
AD		 5050 else if (!tso)
5051 igb_tx_csum(tx_ring, first);
9d5c8243 5052
7af40ad9 5053 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5054
9d5c8243 5055 return NETDEV_TX_OK;
7d13a7d0
AD		 5056
5057out_drop:
7af40ad9
AD		 5058 igb_unmap_and_free_tx_resource(tx_ring, first);
5059
7d13a7d0 5060 return NETDEV_TX_OK;
9d5c8243
AK		 5061}
5062
0b725a2c
DM		 5063static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5064 struct sk_buff *skb)
1cc3bd87 5065{
0b725a2c
DM		 5066 unsigned int r_idx = skb->queue_mapping;
5067
1cc3bd87
AD		 5068 if (r_idx >= adapter->num_tx_queues)
5069 r_idx = r_idx % adapter->num_tx_queues;
5070
5071 return adapter->tx_ring[r_idx];
5072}
5073
cd392f5c
AD		 5074static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5075 struct net_device *netdev)
9d5c8243
AK		 5076{
5077 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5078
5079 if (test_bit(__IGB_DOWN, &adapter->state)) {
5080 dev_kfree_skb_any(skb);
5081 return NETDEV_TX_OK;
5082 }
5083
5084 if (skb->len <= 0) {
5085 dev_kfree_skb_any(skb);
5086 return NETDEV_TX_OK;
5087 }
5088
b980ac18 5089 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5090 * in order to meet this minimum size requirement.
5091 */
a94d9e22
AD		 5092 if (skb_put_padto(skb, 17))
5093 return NETDEV_TX_OK;
9d5c8243 5094
1cc3bd87 5095 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5096}
5097
5098/**
b980ac18
JK		 5099 * igb_tx_timeout - Respond to a Tx Hang
5100 * @netdev: network interface device structure
9d5c8243
AK		 5101 **/
5102static void igb_tx_timeout(struct net_device *netdev)
5103{
5104 struct igb_adapter *adapter = netdev_priv(netdev);
5105 struct e1000_hw *hw = &adapter->hw;
5106
5107 /* Do the reset outside of interrupt context */
5108 adapter->tx_timeout_count++;
f7ba205e 5109
06218a8d 5110 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5111 hw->dev_spec._82575.global_device_reset = true;
5112
9d5c8243 5113 schedule_work(&adapter->reset_task);
265de409
AD		 5114 wr32(E1000_EICS,
5115 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5116}
5117
5118static void igb_reset_task(struct work_struct *work)
5119{
5120 struct igb_adapter *adapter;
5121 adapter = container_of(work, struct igb_adapter, reset_task);
5122
c97ec42a
TI		 5123 igb_dump(adapter);
5124 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5125 igb_reinit_locked(adapter);
5126}
5127
5128/**
b980ac18
JK		 5129 * igb_get_stats64 - Get System Network Statistics
5130 * @netdev: network interface device structure
5131 * @stats: rtnl_link_stats64 pointer
9d5c8243 5132 **/
12dcd86b 5133static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5134 struct rtnl_link_stats64 *stats)
9d5c8243 5135{
12dcd86b
ED		 5136 struct igb_adapter *adapter = netdev_priv(netdev);
5137
5138 spin_lock(&adapter->stats64_lock);
5139 igb_update_stats(adapter, &adapter->stats64);
5140 memcpy(stats, &adapter->stats64, sizeof(*stats));
5141 spin_unlock(&adapter->stats64_lock);
5142
5143 return stats;
9d5c8243
AK		 5144}
5145
5146/**
b980ac18
JK		 5147 * igb_change_mtu - Change the Maximum Transfer Unit
5148 * @netdev: network interface device structure
5149 * @new_mtu: new value for maximum frame size
9d5c8243 5150 *
b980ac18 5151 * Returns 0 on success, negative on failure
9d5c8243
AK		 5152 **/
5153static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5154{
5155 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5156 struct pci_dev *pdev = adapter->pdev;
153285f9 5157 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5158
c809d227 5159 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5160 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5161 return -EINVAL;
5162 }
5163
153285f9 5164#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5165 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5166 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5167 return -EINVAL;
5168 }
5169
2ccd994c
AD		 5170 /* adjust max frame to be at least the size of a standard frame */
5171 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5172 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5173
9d5c8243 5174 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5175 usleep_range(1000, 2000);
73cd78f1 5176
9d5c8243
AK		 5177 /* igb_down has a dependency on max_frame_size */
5178 adapter->max_frame_size = max_frame;
559e9c49 5179
4c844851
AD		 5180 if (netif_running(netdev))
5181 igb_down(adapter);
9d5c8243 5182
090b1795 5183 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5184 netdev->mtu, new_mtu);
5185 netdev->mtu = new_mtu;
5186
5187 if (netif_running(netdev))
5188 igb_up(adapter);
5189 else
5190 igb_reset(adapter);
5191
5192 clear_bit(__IGB_RESETTING, &adapter->state);
5193
5194 return 0;
5195}
5196
5197/**
b980ac18
JK		 5198 * igb_update_stats - Update the board statistics counters
5199 * @adapter: board private structure
9d5c8243 5200 **/
12dcd86b
ED		 5201void igb_update_stats(struct igb_adapter *adapter,
5202 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5203{
5204 struct e1000_hw *hw = &adapter->hw;
5205 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5206 u32 reg, mpc;
3f9c0164
AD		 5207 int i;
5208 u64 bytes, packets;
12dcd86b
ED		 5209 unsigned int start;
5210 u64 _bytes, _packets;
9d5c8243 5211
b980ac18 5212 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5213 * connection is down.
5214 */
5215 if (adapter->link_speed == 0)
5216 return;
5217 if (pci_channel_offline(pdev))
5218 return;
5219
3f9c0164
AD		 5220 bytes = 0;
5221 packets = 0;
7f90128e
AA		 5222
5223 rcu_read_lock();
3f9c0164 5224 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5225 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5226 u32 rqdpc = rd32(E1000_RQDPC(i));
5227 if (hw->mac.type >= e1000_i210)
5228 wr32(E1000_RQDPC(i), 0);
12dcd86b 5229
ae1c07a6
AD		 5230 if (rqdpc) {
5231 ring->rx_stats.drops += rqdpc;
5232 net_stats->rx_fifo_errors += rqdpc;
5233 }
12dcd86b
ED		 5234
5235 do {
57a7744e 5236 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5237 _bytes = ring->rx_stats.bytes;
5238 _packets = ring->rx_stats.packets;
57a7744e 5239 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5240 bytes += _bytes;
5241 packets += _packets;
3f9c0164
AD		 5242 }
5243
128e45eb
AD		 5244 net_stats->rx_bytes = bytes;
5245 net_stats->rx_packets = packets;
3f9c0164
AD		 5246
5247 bytes = 0;
5248 packets = 0;
5249 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5250 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5251 do {
57a7744e 5252 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5253 _bytes = ring->tx_stats.bytes;
5254 _packets = ring->tx_stats.packets;
57a7744e 5255 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5256 bytes += _bytes;
5257 packets += _packets;
3f9c0164 5258 }
128e45eb
AD		 5259 net_stats->tx_bytes = bytes;
5260 net_stats->tx_packets = packets;
7f90128e 5261 rcu_read_unlock();
3f9c0164
AD		 5262
5263 /* read stats registers */
9d5c8243
AK		 5264 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5265 adapter->stats.gprc += rd32(E1000_GPRC);
5266 adapter->stats.gorc += rd32(E1000_GORCL);
5267 rd32(E1000_GORCH); /* clear GORCL */
5268 adapter->stats.bprc += rd32(E1000_BPRC);
5269 adapter->stats.mprc += rd32(E1000_MPRC);
5270 adapter->stats.roc += rd32(E1000_ROC);
5271
5272 adapter->stats.prc64 += rd32(E1000_PRC64);
5273 adapter->stats.prc127 += rd32(E1000_PRC127);
5274 adapter->stats.prc255 += rd32(E1000_PRC255);
5275 adapter->stats.prc511 += rd32(E1000_PRC511);
5276 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5277 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5278 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5279 adapter->stats.sec += rd32(E1000_SEC);
5280
fa3d9a6d
MW		 5281 mpc = rd32(E1000_MPC);
5282 adapter->stats.mpc += mpc;
5283 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5284 adapter->stats.scc += rd32(E1000_SCC);
5285 adapter->stats.ecol += rd32(E1000_ECOL);
5286 adapter->stats.mcc += rd32(E1000_MCC);
5287 adapter->stats.latecol += rd32(E1000_LATECOL);
5288 adapter->stats.dc += rd32(E1000_DC);
5289 adapter->stats.rlec += rd32(E1000_RLEC);
5290 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5291 adapter->stats.xontxc += rd32(E1000_XONTXC);
5292 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5293 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5294 adapter->stats.fcruc += rd32(E1000_FCRUC);
5295 adapter->stats.gptc += rd32(E1000_GPTC);
5296 adapter->stats.gotc += rd32(E1000_GOTCL);
5297 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5298 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5299 adapter->stats.ruc += rd32(E1000_RUC);
5300 adapter->stats.rfc += rd32(E1000_RFC);
5301 adapter->stats.rjc += rd32(E1000_RJC);
5302 adapter->stats.tor += rd32(E1000_TORH);
5303 adapter->stats.tot += rd32(E1000_TOTH);
5304 adapter->stats.tpr += rd32(E1000_TPR);
5305
5306 adapter->stats.ptc64 += rd32(E1000_PTC64);
5307 adapter->stats.ptc127 += rd32(E1000_PTC127);
5308 adapter->stats.ptc255 += rd32(E1000_PTC255);
5309 adapter->stats.ptc511 += rd32(E1000_PTC511);
5310 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5311 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5312
5313 adapter->stats.mptc += rd32(E1000_MPTC);
5314 adapter->stats.bptc += rd32(E1000_BPTC);
5315
2d0b0f69
NN		 5316 adapter->stats.tpt += rd32(E1000_TPT);
5317 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5318
5319 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5320 /* read internal phy specific stats */
5321 reg = rd32(E1000_CTRL_EXT);
5322 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5323 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5324
5325 /* this stat has invalid values on i210/i211 */
5326 if ((hw->mac.type != e1000_i210) &&
5327 (hw->mac.type != e1000_i211))
5328 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5329 }
5330
9d5c8243
AK		 5331 adapter->stats.tsctc += rd32(E1000_TSCTC);
5332 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5333
5334 adapter->stats.iac += rd32(E1000_IAC);
5335 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5336 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5337 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5338 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5339 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5340 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5341 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5342 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5343
5344 /* Fill out the OS statistics structure */
128e45eb
AD		 5345 net_stats->multicast = adapter->stats.mprc;
5346 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5347
5348 /* Rx Errors */
5349
5350 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5351 * our own version based on RUC and ROC
5352 */
128e45eb 5353 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5354 adapter->stats.crcerrs + adapter->stats.algnerrc +
5355 adapter->stats.ruc + adapter->stats.roc +
5356 adapter->stats.cexterr;
128e45eb
AD		 5357 net_stats->rx_length_errors = adapter->stats.ruc +
5358 adapter->stats.roc;
5359 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5360 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5361 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5362
5363 /* Tx Errors */
128e45eb
AD		 5364 net_stats->tx_errors = adapter->stats.ecol +
5365 adapter->stats.latecol;
5366 net_stats->tx_aborted_errors = adapter->stats.ecol;
5367 net_stats->tx_window_errors = adapter->stats.latecol;
5368 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5369
5370 /* Tx Dropped needs to be maintained elsewhere */
5371
9d5c8243
AK		 5372 /* Management Stats */
5373 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5374 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5375 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5376
5377 /* OS2BMC Stats */
5378 reg = rd32(E1000_MANC);
5379 if (reg & E1000_MANC_EN_BMC2OS) {
5380 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5381 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5382 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5383 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5384 }
9d5c8243
AK		 5385}
5386
61d7f75f
RC		 5387static void igb_tsync_interrupt(struct igb_adapter *adapter)
5388{
5389 struct e1000_hw *hw = &adapter->hw;
00c65578 5390 struct ptp_clock_event event;
720db4ff
RC		 5391 struct timespec ts;
5392 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5393
5394 if (tsicr & TSINTR_SYS_WRAP) {
5395 event.type = PTP_CLOCK_PPS;
5396 if (adapter->ptp_caps.pps)
5397 ptp_clock_event(adapter->ptp_clock, &event);
5398 else
5399 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5400 ack |= TSINTR_SYS_WRAP;
5401 }
61d7f75f
RC		 5402
5403 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5404 /* retrieve hardware timestamp */
5405 schedule_work(&adapter->ptp_tx_work);
00c65578 5406 ack |= E1000_TSICR_TXTS;
61d7f75f 5407 }
00c65578 5408
720db4ff
RC		 5409 if (tsicr & TSINTR_TT0) {
5410 spin_lock(&adapter->tmreg_lock);
5411 ts = timespec_add(adapter->perout[0].start,
5412 adapter->perout[0].period);
5413 wr32(E1000_TRGTTIML0, ts.tv_nsec);
5414 wr32(E1000_TRGTTIMH0, ts.tv_sec);
5415 tsauxc = rd32(E1000_TSAUXC);
5416 tsauxc |= TSAUXC_EN_TT0;
5417 wr32(E1000_TSAUXC, tsauxc);
5418 adapter->perout[0].start = ts;
5419 spin_unlock(&adapter->tmreg_lock);
5420 ack |= TSINTR_TT0;
5421 }
5422
5423 if (tsicr & TSINTR_TT1) {
5424 spin_lock(&adapter->tmreg_lock);
5425 ts = timespec_add(adapter->perout[1].start,
5426 adapter->perout[1].period);
5427 wr32(E1000_TRGTTIML1, ts.tv_nsec);
5428 wr32(E1000_TRGTTIMH1, ts.tv_sec);
5429 tsauxc = rd32(E1000_TSAUXC);
5430 tsauxc |= TSAUXC_EN_TT1;
5431 wr32(E1000_TSAUXC, tsauxc);
5432 adapter->perout[1].start = ts;
5433 spin_unlock(&adapter->tmreg_lock);
5434 ack |= TSINTR_TT1;
5435 }
5436
5437 if (tsicr & TSINTR_AUTT0) {
5438 nsec = rd32(E1000_AUXSTMPL0);
5439 sec = rd32(E1000_AUXSTMPH0);
5440 event.type = PTP_CLOCK_EXTTS;
5441 event.index = 0;
5442 event.timestamp = sec * 1000000000ULL + nsec;
5443 ptp_clock_event(adapter->ptp_clock, &event);
5444 ack |= TSINTR_AUTT0;
5445 }
5446
5447 if (tsicr & TSINTR_AUTT1) {
5448 nsec = rd32(E1000_AUXSTMPL1);
5449 sec = rd32(E1000_AUXSTMPH1);
5450 event.type = PTP_CLOCK_EXTTS;
5451 event.index = 1;
5452 event.timestamp = sec * 1000000000ULL + nsec;
5453 ptp_clock_event(adapter->ptp_clock, &event);
5454 ack |= TSINTR_AUTT1;
5455 }
5456
00c65578
RC		 5457 /* acknowledge the interrupts */
5458 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5459}
5460
9d5c8243
AK		 5461static irqreturn_t igb_msix_other(int irq, void *data)
5462{
047e0030 5463 struct igb_adapter *adapter = data;
9d5c8243 5464 struct e1000_hw *hw = &adapter->hw;
844290e5 5465 u32 icr = rd32(E1000_ICR);
844290e5 5466 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5467
7f081d40
AD		 5468 if (icr & E1000_ICR_DRSTA)
5469 schedule_work(&adapter->reset_task);
5470
047e0030 5471 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5472 /* HW is reporting DMA is out of sync */
5473 adapter->stats.doosync++;
13800469
GR		 5474 /* The DMA Out of Sync is also indication of a spoof event
5475 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5476 * see if it is really a spoof event.
5477 */
13800469 5478 igb_check_wvbr(adapter);
dda0e083 5479 }
eebbbdba 5480
4ae196df
AD		 5481 /* Check for a mailbox event */
5482 if (icr & E1000_ICR_VMMB)
5483 igb_msg_task(adapter);
5484
5485 if (icr & E1000_ICR_LSC) {
5486 hw->mac.get_link_status = 1;
5487 /* guard against interrupt when we're going down */
5488 if (!test_bit(__IGB_DOWN, &adapter->state))
5489 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5490 }
5491
61d7f75f
RC		 5492 if (icr & E1000_ICR_TS)
5493 igb_tsync_interrupt(adapter);
1f6e8178 5494
844290e5 5495 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5496
5497 return IRQ_HANDLED;
5498}
5499
047e0030 5500static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5501{
26b39276 5502 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5503 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5504
047e0030
AD		 5505 if (!q_vector->set_itr)
5506 return;
73cd78f1 5507
047e0030
AD		 5508 if (!itr_val)
5509 itr_val = 0x4;
661086df 5510
26b39276
AD		 5511 if (adapter->hw.mac.type == e1000_82575)
5512 itr_val |= itr_val << 16;
661086df 5513 else
0ba82994 5514 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5515
047e0030
AD		 5516 writel(itr_val, q_vector->itr_register);
5517 q_vector->set_itr = 0;
6eb5a7f1
AD		 5518}
5519
047e0030 5520static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5521{
047e0030 5522 struct igb_q_vector *q_vector = data;
9d5c8243 5523
047e0030
AD		 5524 /* Write the ITR value calculated from the previous interrupt. */
5525 igb_write_itr(q_vector);
9d5c8243 5526
047e0030 5527 napi_schedule(&q_vector->napi);
844290e5 5528
047e0030 5529 return IRQ_HANDLED;
fe4506b6
JC		 5530}
5531
421e02f0 5532#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5533static void igb_update_tx_dca(struct igb_adapter *adapter,
5534 struct igb_ring *tx_ring,
5535 int cpu)
5536{
5537 struct e1000_hw *hw = &adapter->hw;
5538 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5539
5540 if (hw->mac.type != e1000_82575)
5541 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5542
b980ac18 5543 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5544 * DCA is enabled. This is due to a known issue in some chipsets
5545 * which will cause the DCA tag to be cleared.
5546 */
5547 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5548 E1000_DCA_TXCTRL_DATA_RRO_EN |
5549 E1000_DCA_TXCTRL_DESC_DCA_EN;
5550
5551 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5552}
5553
5554static void igb_update_rx_dca(struct igb_adapter *adapter,
5555 struct igb_ring *rx_ring,
5556 int cpu)
5557{
5558 struct e1000_hw *hw = &adapter->hw;
5559 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5560
5561 if (hw->mac.type != e1000_82575)
5562 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5563
b980ac18 5564 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5565 * DCA is enabled. This is due to a known issue in some chipsets
5566 * which will cause the DCA tag to be cleared.
5567 */
5568 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5569 E1000_DCA_RXCTRL_DESC_DCA_EN;
5570
5571 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5572}
5573
047e0030 5574static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5575{
047e0030 5576 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5577 int cpu = get_cpu();
fe4506b6 5578
047e0030
AD		 5579 if (q_vector->cpu == cpu)
5580 goto out_no_update;
5581
6a05004a
AD		 5582 if (q_vector->tx.ring)
5583 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5584
5585 if (q_vector->rx.ring)
5586 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5587
047e0030
AD		 5588 q_vector->cpu = cpu;
5589out_no_update:
fe4506b6
JC		 5590 put_cpu();
5591}
5592
5593static void igb_setup_dca(struct igb_adapter *adapter)
5594{
7e0e99ef 5595 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5596 int i;
5597
7dfc16fa 5598 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5599 return;
5600
7e0e99ef
AD		 5601 /* Always use CB2 mode, difference is masked in the CB driver. */
5602 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5603
047e0030 5604 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5605 adapter->q_vector[i]->cpu = -1;
5606 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5607 }
5608}
5609
5610static int __igb_notify_dca(struct device *dev, void *data)
5611{
5612 struct net_device *netdev = dev_get_drvdata(dev);
5613 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5614 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5615 struct e1000_hw *hw = &adapter->hw;
5616 unsigned long event = *(unsigned long *)data;
5617
5618 switch (event) {
5619 case DCA_PROVIDER_ADD:
5620 /* if already enabled, don't do it again */
7dfc16fa 5621 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5622 break;
fe4506b6 5623 if (dca_add_requester(dev) == 0) {
bbd98fe4 5624 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5625 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5626 igb_setup_dca(adapter);
5627 break;
5628 }
5629 /* Fall Through since DCA is disabled. */
5630 case DCA_PROVIDER_REMOVE:
7dfc16fa 5631 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5632 /* without this a class_device is left
b980ac18
JK		 5633 * hanging around in the sysfs model
5634 */
fe4506b6 5635 dca_remove_requester(dev);
090b1795 5636 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5637 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5638 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5639 }
5640 break;
5641 }
bbd98fe4 5642
fe4506b6 5643 return 0;
9d5c8243
AK		 5644}
5645
fe4506b6 5646static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5647 void *p)
fe4506b6
JC		 5648{
5649 int ret_val;
5650
5651 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5652 __igb_notify_dca);
fe4506b6
JC		 5653
5654 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5655}
421e02f0 5656#endif /* CONFIG_IGB_DCA */
9d5c8243 5657
0224d663
GR		 5658#ifdef CONFIG_PCI_IOV
5659static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5660{
5661 unsigned char mac_addr[ETH_ALEN];
0224d663 5662
5ac6f91d 5663 eth_zero_addr(mac_addr);
0224d663
GR		 5664 igb_set_vf_mac(adapter, vf, mac_addr);
5665
70ea4783
LL		 5666 /* By default spoof check is enabled for all VFs */
5667 adapter->vf_data[vf].spoofchk_enabled = true;
5668
f557147c 5669 return 0;
0224d663
GR		 5670}
5671
0224d663 5672#endif
4ae196df
AD		 5673static void igb_ping_all_vfs(struct igb_adapter *adapter)
5674{
5675 struct e1000_hw *hw = &adapter->hw;
5676 u32 ping;
5677 int i;
5678
5679 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5680 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5681 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5682 ping |= E1000_VT_MSGTYPE_CTS;
5683 igb_write_mbx(hw, &ping, 1, i);
5684 }
5685}
5686
7d5753f0
AD		 5687static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5688{
5689 struct e1000_hw *hw = &adapter->hw;
5690 u32 vmolr = rd32(E1000_VMOLR(vf));
5691 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5692
d85b9004 5693 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5694 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5695 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5696
5697 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5698 vmolr |= E1000_VMOLR_MPME;
d85b9004 5699 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5700 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5701 } else {
b980ac18 5702 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5703 * flag we need to write the hashes to the MTA as this step
5704 * was previously skipped
5705 */
5706 if (vf_data->num_vf_mc_hashes > 30) {
5707 vmolr |= E1000_VMOLR_MPME;
5708 } else if (vf_data->num_vf_mc_hashes) {
5709 int j;
9005df38 5710
7d5753f0
AD		 5711 vmolr |= E1000_VMOLR_ROMPE;
5712 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5713 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5714 }
5715 }
5716
5717 wr32(E1000_VMOLR(vf), vmolr);
5718
5719 /* there are flags left unprocessed, likely not supported */
5720 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5721 return -EINVAL;
5722
5723 return 0;
7d5753f0
AD		 5724}
5725
4ae196df
AD		 5726static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5727 u32 *msgbuf, u32 vf)
5728{
5729 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5730 u16 *hash_list = (u16 *)&msgbuf[1];
5731 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5732 int i;
5733
7d5753f0 5734 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5735 * to this VF for later use to restore when the PF multi cast
5736 * list changes
5737 */
5738 vf_data->num_vf_mc_hashes = n;
5739
7d5753f0
AD		 5740 /* only up to 30 hash values supported */
5741 if (n > 30)
5742 n = 30;
5743
5744 /* store the hashes for later use */
4ae196df 5745 for (i = 0; i < n; i++)
a419aef8 5746 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5747
5748 /* Flush and reset the mta with the new values */
ff41f8dc 5749 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5750
5751 return 0;
5752}
5753
5754static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5755{
5756 struct e1000_hw *hw = &adapter->hw;
5757 struct vf_data_storage *vf_data;
5758 int i, j;
5759
5760 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5761 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5762
7d5753f0
AD		 5763 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5764
4ae196df 5765 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5766
5767 if ((vf_data->num_vf_mc_hashes > 30) ||
5768 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5769 vmolr |= E1000_VMOLR_MPME;
5770 } else if (vf_data->num_vf_mc_hashes) {
5771 vmolr |= E1000_VMOLR_ROMPE;
5772 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5773 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5774 }
5775 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5776 }
5777}
5778
5779static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5780{
5781 struct e1000_hw *hw = &adapter->hw;
5782 u32 pool_mask, reg, vid;
5783 int i;
5784
5785 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5786
5787 /* Find the vlan filter for this id */
5788 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5789 reg = rd32(E1000_VLVF(i));
5790
5791 /* remove the vf from the pool */
5792 reg &= ~pool_mask;
5793
5794 /* if pool is empty then remove entry from vfta */
5795 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5796 (reg & E1000_VLVF_VLANID_ENABLE)) {
5797 reg = 0;
5798 vid = reg & E1000_VLVF_VLANID_MASK;
5799 igb_vfta_set(hw, vid, false);
5800 }
5801
5802 wr32(E1000_VLVF(i), reg);
5803 }
ae641bdc
AD		 5804
5805 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5806}
5807
5808static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5809{
5810 struct e1000_hw *hw = &adapter->hw;
5811 u32 reg, i;
5812
51466239
AD		 5813 /* The vlvf table only exists on 82576 hardware and newer */
5814 if (hw->mac.type < e1000_82576)
5815 return -1;
5816
5817 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5818 if (!adapter->vfs_allocated_count)
5819 return -1;
5820
5821 /* Find the vlan filter for this id */
5822 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5823 reg = rd32(E1000_VLVF(i));
5824 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5825 vid == (reg & E1000_VLVF_VLANID_MASK))
5826 break;
5827 }
5828
5829 if (add) {
5830 if (i == E1000_VLVF_ARRAY_SIZE) {
5831 /* Did not find a matching VLAN ID entry that was
5832 * enabled. Search for a free filter entry, i.e.
5833 * one without the enable bit set
5834 */
5835 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5836 reg = rd32(E1000_VLVF(i));
5837 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5838 break;
5839 }
5840 }
5841 if (i < E1000_VLVF_ARRAY_SIZE) {
5842 /* Found an enabled/available entry */
5843 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5844
5845 /* if !enabled we need to set this up in vfta */
5846 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5847 /* add VID to filter table */
5848 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5849 reg |= E1000_VLVF_VLANID_ENABLE;
5850 }
cad6d05f
AD		 5851 reg &= ~E1000_VLVF_VLANID_MASK;
5852 reg |= vid;
4ae196df 5853 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5854
5855 /* do not modify RLPML for PF devices */
5856 if (vf >= adapter->vfs_allocated_count)
5857 return 0;
5858
5859 if (!adapter->vf_data[vf].vlans_enabled) {
5860 u32 size;
9005df38 5861
ae641bdc
AD		 5862 reg = rd32(E1000_VMOLR(vf));
5863 size = reg & E1000_VMOLR_RLPML_MASK;
5864 size += 4;
5865 reg &= ~E1000_VMOLR_RLPML_MASK;
5866 reg |= size;
5867 wr32(E1000_VMOLR(vf), reg);
5868 }
ae641bdc 5869
51466239 5870 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5871 }
5872 } else {
5873 if (i < E1000_VLVF_ARRAY_SIZE) {
5874 /* remove vf from the pool */
5875 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5876 /* if pool is empty then remove entry from vfta */
5877 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5878 reg = 0;
5879 igb_vfta_set(hw, vid, false);
5880 }
5881 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5882
5883 /* do not modify RLPML for PF devices */
5884 if (vf >= adapter->vfs_allocated_count)
5885 return 0;
5886
5887 adapter->vf_data[vf].vlans_enabled--;
5888 if (!adapter->vf_data[vf].vlans_enabled) {
5889 u32 size;
9005df38 5890
ae641bdc
AD		 5891 reg = rd32(E1000_VMOLR(vf));
5892 size = reg & E1000_VMOLR_RLPML_MASK;
5893 size -= 4;
5894 reg &= ~E1000_VMOLR_RLPML_MASK;
5895 reg |= size;
5896 wr32(E1000_VMOLR(vf), reg);
5897 }
4ae196df
AD		 5898 }
5899 }
8151d294
WM		 5900 return 0;
5901}
5902
5903static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5904{
5905 struct e1000_hw *hw = &adapter->hw;
5906
5907 if (vid)
5908 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5909 else
5910 wr32(E1000_VMVIR(vf), 0);
5911}
5912
5913static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5914 int vf, u16 vlan, u8 qos)
5915{
5916 int err = 0;
5917 struct igb_adapter *adapter = netdev_priv(netdev);
5918
5919 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5920 return -EINVAL;
5921 if (vlan || qos) {
5922 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5923 if (err)
5924 goto out;
5925 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5926 igb_set_vmolr(adapter, vf, !vlan);
5927 adapter->vf_data[vf].pf_vlan = vlan;
5928 adapter->vf_data[vf].pf_qos = qos;
5929 dev_info(&adapter->pdev->dev,
5930 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5931 if (test_bit(__IGB_DOWN, &adapter->state)) {
5932 dev_warn(&adapter->pdev->dev,
b980ac18 5933 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5934 dev_warn(&adapter->pdev->dev,
b980ac18 5935 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5936 }
5937 } else {
5938 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5939 false, vf);
8151d294
WM		 5940 igb_set_vmvir(adapter, vlan, vf);
5941 igb_set_vmolr(adapter, vf, true);
5942 adapter->vf_data[vf].pf_vlan = 0;
5943 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5944 }
8151d294 5945out:
b980ac18 5946 return err;
4ae196df
AD		 5947}
5948
6f3dc319
GR		 5949static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5950{
5951 struct e1000_hw *hw = &adapter->hw;
5952 int i;
5953 u32 reg;
5954
5955 /* Find the vlan filter for this id */
5956 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5957 reg = rd32(E1000_VLVF(i));
5958 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5959 vid == (reg & E1000_VLVF_VLANID_MASK))
5960 break;
5961 }
5962
5963 if (i >= E1000_VLVF_ARRAY_SIZE)
5964 i = -1;
5965
5966 return i;
5967}
5968
4ae196df
AD		 5969static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5970{
6f3dc319 5971 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5972 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5973 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5974 int err = 0;
4ae196df 5975
6f3dc319
GR		 5976 /* If in promiscuous mode we need to make sure the PF also has
5977 * the VLAN filter set.
5978 */
5979 if (add && (adapter->netdev->flags & IFF_PROMISC))
5980 err = igb_vlvf_set(adapter, vid, add,
5981 adapter->vfs_allocated_count);
5982 if (err)
5983 goto out;
5984
5985 err = igb_vlvf_set(adapter, vid, add, vf);
5986
5987 if (err)
5988 goto out;
5989
5990 /* Go through all the checks to see if the VLAN filter should
5991 * be wiped completely.
5992 */
5993 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5994 u32 vlvf, bits;
6f3dc319 5995 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 5996
6f3dc319
GR		 5997 if (regndx < 0)
5998 goto out;
5999 /* See if any other pools are set for this VLAN filter
6000 * entry other than the PF.
6001 */
6002 vlvf = bits = rd32(E1000_VLVF(regndx));
6003 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6004 adapter->vfs_allocated_count);
6005 /* If the filter was removed then ensure PF pool bit
6006 * is cleared if the PF only added itself to the pool
6007 * because the PF is in promiscuous mode.
6008 */
6009 if ((vlvf & VLAN_VID_MASK) == vid &&
6010 !test_bit(vid, adapter->active_vlans) &&
6011 !bits)
6012 igb_vlvf_set(adapter, vid, add,
6013 adapter->vfs_allocated_count);
6014 }
6015
6016out:
6017 return err;
4ae196df
AD		 6018}
6019
f2ca0dbe 6020static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 6021{
8fa7e0f7
GR		 6022 /* clear flags - except flag that indicates PF has set the MAC */
6023 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 6024 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 6025
6026 /* reset offloads to defaults */
8151d294 6027 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 6028
6029 /* reset vlans for device */
6030 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 6031 if (adapter->vf_data[vf].pf_vlan)
6032 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6033 adapter->vf_data[vf].pf_vlan,
6034 adapter->vf_data[vf].pf_qos);
6035 else
6036 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 6037
6038 /* reset multicast table array for vf */
6039 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6040
6041 /* Flush and reset the mta with the new values */
ff41f8dc 6042 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6043}
6044
f2ca0dbe
AD		 6045static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6046{
6047 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6048
5ac6f91d 6049 /* clear mac address as we were hotplug removed/added */
8151d294 6050 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6051 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6052
6053 /* process remaining reset events */
6054 igb_vf_reset(adapter, vf);
6055}
6056
6057static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6058{
6059 struct e1000_hw *hw = &adapter->hw;
6060 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6061 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6062 u32 reg, msgbuf[3];
6063 u8 *addr = (u8 *)(&msgbuf[1]);
6064
6065 /* process all the same items cleared in a function level reset */
f2ca0dbe 6066 igb_vf_reset(adapter, vf);
4ae196df
AD		 6067
6068 /* set vf mac address */
26ad9178 6069 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6070
6071 /* enable transmit and receive for vf */
6072 reg = rd32(E1000_VFTE);
6073 wr32(E1000_VFTE, reg | (1 << vf));
6074 reg = rd32(E1000_VFRE);
6075 wr32(E1000_VFRE, reg | (1 << vf));
6076
8fa7e0f7 6077 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6078
6079 /* reply to reset with ack and vf mac address */
6080 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 6081 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 6082 igb_write_mbx(hw, msgbuf, 3, vf);
6083}
6084
6085static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6086{
b980ac18 6087 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6088 * starting at the second 32 bit word of the msg array
6089 */
f2ca0dbe
AD		 6090 unsigned char *addr = (char *)&msg[1];
6091 int err = -1;
4ae196df 6092
f2ca0dbe
AD		 6093 if (is_valid_ether_addr(addr))
6094 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6095
f2ca0dbe 6096 return err;
4ae196df
AD		 6097}
6098
6099static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6100{
6101 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6102 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6103 u32 msg = E1000_VT_MSGTYPE_NACK;
6104
6105 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6106 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6107 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6108 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6109 vf_data->last_nack = jiffies;
4ae196df
AD		 6110 }
6111}
6112
f2ca0dbe 6113static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6114{
f2ca0dbe
AD		 6115 struct pci_dev *pdev = adapter->pdev;
6116 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6117 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6118 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6119 s32 retval;
6120
f2ca0dbe 6121 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6122
fef45f4c
AD		 6123 if (retval) {
6124 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6125 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6126 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6127 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6128 return;
6129 goto out;
6130 }
4ae196df
AD		 6131
6132 /* this is a message we already processed, do nothing */
6133 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6134 return;
4ae196df 6135
b980ac18 6136 /* until the vf completes a reset it should not be
4ae196df
AD		 6137 * allowed to start any configuration.
6138 */
4ae196df
AD		 6139 if (msgbuf[0] == E1000_VF_RESET) {
6140 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6141 return;
4ae196df
AD		 6142 }
6143
f2ca0dbe 6144 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6145 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6146 return;
6147 retval = -1;
6148 goto out;
4ae196df
AD		 6149 }
6150
6151 switch ((msgbuf[0] & 0xFFFF)) {
6152 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6153 retval = -EINVAL;
6154 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6155 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6156 else
6157 dev_warn(&pdev->dev,
b980ac18
JK		 6158 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6159 vf);
4ae196df 6160 break;
7d5753f0
AD		 6161 case E1000_VF_SET_PROMISC:
6162 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6163 break;
4ae196df
AD		 6164 case E1000_VF_SET_MULTICAST:
6165 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6166 break;
6167 case E1000_VF_SET_LPE:
6168 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6169 break;
6170 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6171 retval = -1;
6172 if (vf_data->pf_vlan)
6173 dev_warn(&pdev->dev,
b980ac18
JK		 6174 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6175 vf);
8151d294
WM		 6176 else
6177 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6178 break;
6179 default:
090b1795 6180 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6181 retval = -1;
6182 break;
6183 }
6184
fef45f4c
AD		 6185 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6186out:
4ae196df
AD		 6187 /* notify the VF of the results of what it sent us */
6188 if (retval)
6189 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6190 else
6191 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6192
4ae196df 6193 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6194}
4ae196df 6195
f2ca0dbe
AD		 6196static void igb_msg_task(struct igb_adapter *adapter)
6197{
6198 struct e1000_hw *hw = &adapter->hw;
6199 u32 vf;
6200
6201 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6202 /* process any reset requests */
6203 if (!igb_check_for_rst(hw, vf))
6204 igb_vf_reset_event(adapter, vf);
6205
6206 /* process any messages pending */
6207 if (!igb_check_for_msg(hw, vf))
6208 igb_rcv_msg_from_vf(adapter, vf);
6209
6210 /* process any acks */
6211 if (!igb_check_for_ack(hw, vf))
6212 igb_rcv_ack_from_vf(adapter, vf);
6213 }
4ae196df
AD		 6214}
6215
68d480c4
AD		 6216/**
6217 * igb_set_uta - Set unicast filter table address
6218 * @adapter: board private structure
6219 *
6220 * The unicast table address is a register array of 32-bit registers.
6221 * The table is meant to be used in a way similar to how the MTA is used
6222 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6223 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6224 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6225 **/
6226static void igb_set_uta(struct igb_adapter *adapter)
6227{
6228 struct e1000_hw *hw = &adapter->hw;
6229 int i;
6230
6231 /* The UTA table only exists on 82576 hardware and newer */
6232 if (hw->mac.type < e1000_82576)
6233 return;
6234
6235 /* we only need to do this if VMDq is enabled */
6236 if (!adapter->vfs_allocated_count)
6237 return;
6238
6239 for (i = 0; i < hw->mac.uta_reg_count; i++)
6240 array_wr32(E1000_UTA, i, ~0);
6241}
6242
9d5c8243 6243/**
b980ac18
JK		 6244 * igb_intr_msi - Interrupt Handler
6245 * @irq: interrupt number
6246 * @data: pointer to a network interface device structure
9d5c8243
AK		 6247 **/
6248static irqreturn_t igb_intr_msi(int irq, void *data)
6249{
047e0030
AD		 6250 struct igb_adapter *adapter = data;
6251 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6252 struct e1000_hw *hw = &adapter->hw;
6253 /* read ICR disables interrupts using IAM */
6254 u32 icr = rd32(E1000_ICR);
6255
047e0030 6256 igb_write_itr(q_vector);
9d5c8243 6257
7f081d40
AD		 6258 if (icr & E1000_ICR_DRSTA)
6259 schedule_work(&adapter->reset_task);
6260
047e0030 6261 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6262 /* HW is reporting DMA is out of sync */
6263 adapter->stats.doosync++;
6264 }
6265
9d5c8243
AK		 6266 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6267 hw->mac.get_link_status = 1;
6268 if (!test_bit(__IGB_DOWN, &adapter->state))
6269 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6270 }
6271
61d7f75f
RC		 6272 if (icr & E1000_ICR_TS)
6273 igb_tsync_interrupt(adapter);
1f6e8178 6274
047e0030 6275 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6276
6277 return IRQ_HANDLED;
6278}
6279
6280/**
b980ac18
JK		 6281 * igb_intr - Legacy Interrupt Handler
6282 * @irq: interrupt number
6283 * @data: pointer to a network interface device structure
9d5c8243
AK		 6284 **/
6285static irqreturn_t igb_intr(int irq, void *data)
6286{
047e0030
AD		 6287 struct igb_adapter *adapter = data;
6288 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6289 struct e1000_hw *hw = &adapter->hw;
6290 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6291 * need for the IMC write
6292 */
9d5c8243 6293 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6294
6295 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6296 * not set, then the adapter didn't send an interrupt
6297 */
9d5c8243
AK		 6298 if (!(icr & E1000_ICR_INT_ASSERTED))
6299 return IRQ_NONE;
6300
0ba82994
AD		 6301 igb_write_itr(q_vector);
6302
7f081d40
AD		 6303 if (icr & E1000_ICR_DRSTA)
6304 schedule_work(&adapter->reset_task);
6305
047e0030 6306 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6307 /* HW is reporting DMA is out of sync */
6308 adapter->stats.doosync++;
6309 }
6310
9d5c8243
AK		 6311 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6312 hw->mac.get_link_status = 1;
6313 /* guard against interrupt when we're going down */
6314 if (!test_bit(__IGB_DOWN, &adapter->state))
6315 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6316 }
6317
61d7f75f
RC		 6318 if (icr & E1000_ICR_TS)
6319 igb_tsync_interrupt(adapter);
1f6e8178 6320
047e0030 6321 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6322
6323 return IRQ_HANDLED;
6324}
6325
c50b52a0 6326static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6327{
047e0030 6328 struct igb_adapter *adapter = q_vector->adapter;
46544258 6329 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6330
0ba82994
AD		 6331 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6332 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6333 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6334 igb_set_itr(q_vector);
46544258 6335 else
047e0030 6336 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6337 }
6338
46544258 6339 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6340 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6341 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6342 else
6343 igb_irq_enable(adapter);
6344 }
9d5c8243
AK		 6345}
6346
46544258 6347/**
b980ac18
JK		 6348 * igb_poll - NAPI Rx polling callback
6349 * @napi: napi polling structure
6350 * @budget: count of how many packets we should handle
46544258
AD		 6351 **/
6352static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6353{
047e0030 6354 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6355 struct igb_q_vector,
6356 napi);
16eb8815 6357 bool clean_complete = true;
9d5c8243 6358
421e02f0 6359#ifdef CONFIG_IGB_DCA
047e0030
AD		 6360 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6361 igb_update_dca(q_vector);
fe4506b6 6362#endif
0ba82994 6363 if (q_vector->tx.ring)
13fde97a 6364 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6365
0ba82994 6366 if (q_vector->rx.ring)
cd392f5c 6367 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6368
16eb8815
AD		 6369 /* If all work not completed, return budget and keep polling */
6370 if (!clean_complete)
6371 return budget;
46544258 6372
9d5c8243 6373 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6374 napi_complete(napi);
6375 igb_ring_irq_enable(q_vector);
9d5c8243 6376
16eb8815 6377 return 0;
9d5c8243 6378}
6d8126f9 6379
9d5c8243 6380/**
b980ac18
JK		 6381 * igb_clean_tx_irq - Reclaim resources after transmit completes
6382 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6383 *
b980ac18 6384 * returns true if ring is completely cleaned
9d5c8243 6385 **/
047e0030 6386static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6387{
047e0030 6388 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6389 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6390 struct igb_tx_buffer *tx_buffer;
f4128785 6391 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6392 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6393 unsigned int budget = q_vector->tx.work_limit;
8542db05 6394 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6395
13fde97a
AD		 6396 if (test_bit(__IGB_DOWN, &adapter->state))
6397 return true;
0e014cb1 6398
06034649 6399 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6400 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6401 i -= tx_ring->count;
9d5c8243 6402
f4128785
AD		 6403 do {
6404 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6405
6406 /* if next_to_watch is not set then there is no work pending */
6407 if (!eop_desc)
6408 break;
13fde97a 6409
f4128785 6410 /* prevent any other reads prior to eop_desc */
70d289bc 6411 read_barrier_depends();
f4128785 6412
13fde97a
AD		 6413 /* if DD is not set pending work has not been completed */
6414 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6415 break;
6416
8542db05
AD		 6417 /* clear next_to_watch to prevent false hangs */
6418 tx_buffer->next_to_watch = NULL;
9d5c8243 6419
ebe42d16
AD		 6420 /* update the statistics for this packet */
6421 total_bytes += tx_buffer->bytecount;
6422 total_packets += tx_buffer->gso_segs;
13fde97a 6423
ebe42d16 6424 /* free the skb */
a81fb049 6425 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6426
ebe42d16
AD		 6427 /* unmap skb header data */
6428 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6429 dma_unmap_addr(tx_buffer, dma),
6430 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6431 DMA_TO_DEVICE);
6432
c9f14bf3
AD		 6433 /* clear tx_buffer data */
6434 tx_buffer->skb = NULL;
6435 dma_unmap_len_set(tx_buffer, len, 0);
6436
ebe42d16
AD		 6437 /* clear last DMA location and unmap remaining buffers */
6438 while (tx_desc != eop_desc) {
13fde97a
AD		 6439 tx_buffer++;
6440 tx_desc++;
9d5c8243 6441 i++;
8542db05
AD		 6442 if (unlikely(!i)) {
6443 i -= tx_ring->count;
06034649 6444 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6445 tx_desc = IGB_TX_DESC(tx_ring, 0);
6446 }
ebe42d16
AD		 6447
6448 /* unmap any remaining paged data */
c9f14bf3 6449 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6450 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6451 dma_unmap_addr(tx_buffer, dma),
6452 dma_unmap_len(tx_buffer, len),
ebe42d16 6453 DMA_TO_DEVICE);
c9f14bf3 6454 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6455 }
6456 }
6457
ebe42d16
AD		 6458 /* move us one more past the eop_desc for start of next pkt */
6459 tx_buffer++;
6460 tx_desc++;
6461 i++;
6462 if (unlikely(!i)) {
6463 i -= tx_ring->count;
6464 tx_buffer = tx_ring->tx_buffer_info;
6465 tx_desc = IGB_TX_DESC(tx_ring, 0);
6466 }
f4128785
AD		 6467
6468 /* issue prefetch for next Tx descriptor */
6469 prefetch(tx_desc);
6470
6471 /* update budget accounting */
6472 budget--;
6473 } while (likely(budget));
0e014cb1 6474
bdbc0631
ED		 6475 netdev_tx_completed_queue(txring_txq(tx_ring),
6476 total_packets, total_bytes);
8542db05 6477 i += tx_ring->count;
9d5c8243 6478 tx_ring->next_to_clean = i;
13fde97a
AD		 6479 u64_stats_update_begin(&tx_ring->tx_syncp);
6480 tx_ring->tx_stats.bytes += total_bytes;
6481 tx_ring->tx_stats.packets += total_packets;
6482 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6483 q_vector->tx.total_bytes += total_bytes;
6484 q_vector->tx.total_packets += total_packets;
9d5c8243 6485
6d095fa8 6486 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6487 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6488
9d5c8243 6489 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6490 * check with the clearing of time_stamp and movement of i
6491 */
6d095fa8 6492 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6493 if (tx_buffer->next_to_watch &&
8542db05 6494 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6495 (adapter->tx_timeout_factor * HZ)) &&
6496 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6497
9d5c8243 6498 /* detected Tx unit hang */
59d71989 6499 dev_err(tx_ring->dev,
9d5c8243 6500 "Detected Tx Unit Hang\n"
2d064c06 6501 " Tx Queue <%d>\n"
9d5c8243
AK		 6502 " TDH <%x>\n"
6503 " TDT <%x>\n"
6504 " next_to_use <%x>\n"
6505 " next_to_clean <%x>\n"
9d5c8243
AK		 6506 "buffer_info[next_to_clean]\n"
6507 " time_stamp <%lx>\n"
8542db05 6508 " next_to_watch <%p>\n"
9d5c8243
AK		 6509 " jiffies <%lx>\n"
6510 " desc.status <%x>\n",
2d064c06 6511 tx_ring->queue_index,
238ac817 6512 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6513 readl(tx_ring->tail),
9d5c8243
AK		 6514 tx_ring->next_to_use,
6515 tx_ring->next_to_clean,
8542db05 6516 tx_buffer->time_stamp,
f4128785 6517 tx_buffer->next_to_watch,
9d5c8243 6518 jiffies,
f4128785 6519 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6520 netif_stop_subqueue(tx_ring->netdev,
6521 tx_ring->queue_index);
6522
6523 /* we are about to reset, no point in enabling stuff */
6524 return true;
9d5c8243
AK		 6525 }
6526 }
13fde97a 6527
21ba6fe1 6528#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6529 if (unlikely(total_packets &&
b980ac18
JK		 6530 netif_carrier_ok(tx_ring->netdev) &&
6531 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6532 /* Make sure that anybody stopping the queue after this
6533 * sees the new next_to_clean.
6534 */
6535 smp_mb();
6536 if (__netif_subqueue_stopped(tx_ring->netdev,
6537 tx_ring->queue_index) &&
6538 !(test_bit(__IGB_DOWN, &adapter->state))) {
6539 netif_wake_subqueue(tx_ring->netdev,
6540 tx_ring->queue_index);
6541
6542 u64_stats_update_begin(&tx_ring->tx_syncp);
6543 tx_ring->tx_stats.restart_queue++;
6544 u64_stats_update_end(&tx_ring->tx_syncp);
6545 }
6546 }
6547
6548 return !!budget;
9d5c8243
AK		 6549}
6550
cbc8e55f 6551/**
b980ac18
JK		 6552 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6553 * @rx_ring: rx descriptor ring to store buffers on
6554 * @old_buff: donor buffer to have page reused
cbc8e55f 6555 *
b980ac18 6556 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6557 **/
6558static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6559 struct igb_rx_buffer *old_buff)
6560{
6561 struct igb_rx_buffer *new_buff;
6562 u16 nta = rx_ring->next_to_alloc;
6563
6564 new_buff = &rx_ring->rx_buffer_info[nta];
6565
6566 /* update, and store next to alloc */
6567 nta++;
6568 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6569
6570 /* transfer page from old buffer to new buffer */
a1f63473 6571 *new_buff = *old_buff;
cbc8e55f
AD		 6572
6573 /* sync the buffer for use by the device */
6574 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6575 old_buff->page_offset,
de78d1f9 6576 IGB_RX_BUFSZ,
cbc8e55f
AD		 6577 DMA_FROM_DEVICE);
6578}
6579
95dd44b4
AD		 6580static inline bool igb_page_is_reserved(struct page *page)
6581{
6582 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
6583}
6584
74e238ea
AD		 6585static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6586 struct page *page,
6587 unsigned int truesize)
6588{
6589 /* avoid re-using remote pages */
95dd44b4 6590 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6591 return false;
6592
74e238ea
AD		 6593#if (PAGE_SIZE < 8192)
6594 /* if we are only owner of page we can reuse it */
6595 if (unlikely(page_count(page) != 1))
6596 return false;
6597
6598 /* flip page offset to other buffer */
6599 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6600#else
6601 /* move offset up to the next cache line */
6602 rx_buffer->page_offset += truesize;
6603
6604 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6605 return false;
74e238ea
AD		 6606#endif
6607
95dd44b4
AD		 6608 /* Even if we own the page, we are not allowed to use atomic_set()
6609 * This would break get_page_unless_zero() users.
6610 */
6611 atomic_inc(&page->_count);
6612
74e238ea
AD		 6613 return true;
6614}
6615
cbc8e55f 6616/**
b980ac18
JK		 6617 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6618 * @rx_ring: rx descriptor ring to transact packets on
6619 * @rx_buffer: buffer containing page to add
6620 * @rx_desc: descriptor containing length of buffer written by hardware
6621 * @skb: sk_buff to place the data into
cbc8e55f 6622 *
b980ac18
JK		 6623 * This function will add the data contained in rx_buffer->page to the skb.
6624 * This is done either through a direct copy if the data in the buffer is
6625 * less than the skb header size, otherwise it will just attach the page as
6626 * a frag to the skb.
cbc8e55f 6627 *
b980ac18
JK		 6628 * The function will then update the page offset if necessary and return
6629 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6630 **/
6631static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6632 struct igb_rx_buffer *rx_buffer,
6633 union e1000_adv_rx_desc *rx_desc,
6634 struct sk_buff *skb)
6635{
6636 struct page *page = rx_buffer->page;
6637 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6638#if (PAGE_SIZE < 8192)
6639 unsigned int truesize = IGB_RX_BUFSZ;
6640#else
6641 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6642#endif
cbc8e55f
AD		 6643
6644 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6645 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6646
cbc8e55f
AD		 6647 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6648 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6649 va += IGB_TS_HDR_LEN;
6650 size -= IGB_TS_HDR_LEN;
6651 }
6652
cbc8e55f
AD		 6653 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6654
95dd44b4
AD		 6655 /* page is not reserved, we can reuse buffer as-is */
6656 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6657 return true;
6658
6659 /* this page cannot be reused so discard it */
95dd44b4 6660 __free_page(page);
cbc8e55f
AD		 6661 return false;
6662 }
6663
6664 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6665 rx_buffer->page_offset, size, truesize);
cbc8e55f 6666
74e238ea
AD		 6667 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6668}
cbc8e55f 6669
2e334eee
AD		 6670static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6671 union e1000_adv_rx_desc *rx_desc,
6672 struct sk_buff *skb)
6673{
6674 struct igb_rx_buffer *rx_buffer;
6675 struct page *page;
6676
6677 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6678 page = rx_buffer->page;
6679 prefetchw(page);
6680
6681 if (likely(!skb)) {
6682 void *page_addr = page_address(page) +
6683 rx_buffer->page_offset;
6684
6685 /* prefetch first cache line of first page */
6686 prefetch(page_addr);
6687#if L1_CACHE_BYTES < 128
6688 prefetch(page_addr + L1_CACHE_BYTES);
6689#endif
6690
6691 /* allocate a skb to store the frags */
67fd893e 6692 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6693 if (unlikely(!skb)) {
6694 rx_ring->rx_stats.alloc_failed++;
6695 return NULL;
6696 }
6697
b980ac18 6698 /* we will be copying header into skb->data in
2e334eee
AD		 6699 * pskb_may_pull so it is in our interest to prefetch
6700 * it now to avoid a possible cache miss
6701 */
6702 prefetchw(skb->data);
6703 }
6704
6705 /* we are reusing so sync this buffer for CPU use */
6706 dma_sync_single_range_for_cpu(rx_ring->dev,
6707 rx_buffer->dma,
6708 rx_buffer->page_offset,
de78d1f9 6709 IGB_RX_BUFSZ,
2e334eee
AD		 6710 DMA_FROM_DEVICE);
6711
6712 /* pull page into skb */
6713 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6714 /* hand second half of page back to the ring */
6715 igb_reuse_rx_page(rx_ring, rx_buffer);
6716 } else {
6717 /* we are not reusing the buffer so unmap it */
6718 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6719 PAGE_SIZE, DMA_FROM_DEVICE);
6720 }
6721
6722 /* clear contents of rx_buffer */
6723 rx_buffer->page = NULL;
6724
6725 return skb;
6726}
6727
cd392f5c 6728static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6729 union e1000_adv_rx_desc *rx_desc,
6730 struct sk_buff *skb)
9d5c8243 6731{
bc8acf2c 6732 skb_checksum_none_assert(skb);
9d5c8243 6733
294e7d78 6734 /* Ignore Checksum bit is set */
3ceb90fd 6735 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6736 return;
6737
6738 /* Rx checksum disabled via ethtool */
6739 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6740 return;
85ad76b2 6741
9d5c8243 6742 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6743 if (igb_test_staterr(rx_desc,
6744 E1000_RXDEXT_STATERR_TCPE |
6745 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6746 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6747 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6748 * packets, (aka let the stack check the crc32c)
6749 */
866cff06
AD		 6750 if (!((skb->len == 60) &&
6751 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6752 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6753 ring->rx_stats.csum_err++;
12dcd86b
ED		 6754 u64_stats_update_end(&ring->rx_syncp);
6755 }
9d5c8243 6756 /* let the stack verify checksum errors */
9d5c8243
AK		 6757 return;
6758 }
6759 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6760 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6761 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6762 skb->ip_summed = CHECKSUM_UNNECESSARY;
6763
3ceb90fd
AD		 6764 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6765 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6766}
6767
077887c3
AD		 6768static inline void igb_rx_hash(struct igb_ring *ring,
6769 union e1000_adv_rx_desc *rx_desc,
6770 struct sk_buff *skb)
6771{
6772 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6773 skb_set_hash(skb,
6774 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6775 PKT_HASH_TYPE_L3);
077887c3
AD		 6776}
6777
2e334eee 6778/**
b980ac18
JK		 6779 * igb_is_non_eop - process handling of non-EOP buffers
6780 * @rx_ring: Rx ring being processed
6781 * @rx_desc: Rx descriptor for current buffer
6782 * @skb: current socket buffer containing buffer in progress
2e334eee 6783 *
b980ac18
JK		 6784 * This function updates next to clean. If the buffer is an EOP buffer
6785 * this function exits returning false, otherwise it will place the
6786 * sk_buff in the next buffer to be chained and return true indicating
6787 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6788 **/
6789static bool igb_is_non_eop(struct igb_ring *rx_ring,
6790 union e1000_adv_rx_desc *rx_desc)
6791{
6792 u32 ntc = rx_ring->next_to_clean + 1;
6793
6794 /* fetch, update, and store next to clean */
6795 ntc = (ntc < rx_ring->count) ? ntc : 0;
6796 rx_ring->next_to_clean = ntc;
6797
6798 prefetch(IGB_RX_DESC(rx_ring, ntc));
6799
6800 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6801 return false;
6802
6803 return true;
6804}
6805
1a1c225b 6806/**
b980ac18
JK		 6807 * igb_pull_tail - igb specific version of skb_pull_tail
6808 * @rx_ring: rx descriptor ring packet is being transacted on
6809 * @rx_desc: pointer to the EOP Rx descriptor
6810 * @skb: pointer to current skb being adjusted
1a1c225b 6811 *
b980ac18
JK		 6812 * This function is an igb specific version of __pskb_pull_tail. The
6813 * main difference between this version and the original function is that
6814 * this function can make several assumptions about the state of things
6815 * that allow for significant optimizations versus the standard function.
6816 * As a result we can do things like drop a frag and maintain an accurate
6817 * truesize for the skb.
1a1c225b
AD		 6818 */
6819static void igb_pull_tail(struct igb_ring *rx_ring,
6820 union e1000_adv_rx_desc *rx_desc,
6821 struct sk_buff *skb)
2d94d8ab 6822{
1a1c225b
AD		 6823 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6824 unsigned char *va;
6825 unsigned int pull_len;
6826
b980ac18 6827 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6828 * working with pages allocated out of the lomem pool per
6829 * alloc_page(GFP_ATOMIC)
2d94d8ab 6830 */
1a1c225b
AD		 6831 va = skb_frag_address(frag);
6832
1a1c225b
AD		 6833 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6834 /* retrieve timestamp from buffer */
6835 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6836
6837 /* update pointers to remove timestamp header */
6838 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6839 frag->page_offset += IGB_TS_HDR_LEN;
6840 skb->data_len -= IGB_TS_HDR_LEN;
6841 skb->len -= IGB_TS_HDR_LEN;
6842
6843 /* move va to start of packet data */
6844 va += IGB_TS_HDR_LEN;
6845 }
6846
b980ac18 6847 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6848 * 60 bytes if the skb->len is less than 60 for skb_pad.
6849 */
24cd23d3 6850 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
1a1c225b
AD		 6851
6852 /* align pull length to size of long to optimize memcpy performance */
6853 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6854
6855 /* update all of the pointers */
6856 skb_frag_size_sub(frag, pull_len);
6857 frag->page_offset += pull_len;
6858 skb->data_len -= pull_len;
6859 skb->tail += pull_len;
6860}
6861
6862/**
b980ac18
JK		 6863 * igb_cleanup_headers - Correct corrupted or empty headers
6864 * @rx_ring: rx descriptor ring packet is being transacted on
6865 * @rx_desc: pointer to the EOP Rx descriptor
6866 * @skb: pointer to current skb being fixed
1a1c225b 6867 *
b980ac18
JK		 6868 * Address the case where we are pulling data in on pages only
6869 * and as such no data is present in the skb header.
1a1c225b 6870 *
b980ac18
JK		 6871 * In addition if skb is not at least 60 bytes we need to pad it so that
6872 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6873 *
b980ac18 6874 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6875 **/
6876static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6877 union e1000_adv_rx_desc *rx_desc,
6878 struct sk_buff *skb)
6879{
1a1c225b
AD		 6880 if (unlikely((igb_test_staterr(rx_desc,
6881 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6882 struct net_device *netdev = rx_ring->netdev;
6883 if (!(netdev->features & NETIF_F_RXALL)) {
6884 dev_kfree_skb_any(skb);
6885 return true;
6886 }
6887 }
6888
6889 /* place header in linear portion of buffer */
6890 if (skb_is_nonlinear(skb))
6891 igb_pull_tail(rx_ring, rx_desc, skb);
6892
a94d9e22
AD		 6893 /* if eth_skb_pad returns an error the skb was freed */
6894 if (eth_skb_pad(skb))
6895 return true;
1a1c225b
AD		 6896
6897 return false;
2d94d8ab
AD		 6898}
6899
db2ee5bd 6900/**
b980ac18
JK		 6901 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6902 * @rx_ring: rx descriptor ring packet is being transacted on
6903 * @rx_desc: pointer to the EOP Rx descriptor
6904 * @skb: pointer to current skb being populated
db2ee5bd 6905 *
b980ac18
JK		 6906 * This function checks the ring, descriptor, and packet information in
6907 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6908 * other fields within the skb.
db2ee5bd
AD		 6909 **/
6910static void igb_process_skb_fields(struct igb_ring *rx_ring,
6911 union e1000_adv_rx_desc *rx_desc,
6912 struct sk_buff *skb)
6913{
6914 struct net_device *dev = rx_ring->netdev;
6915
6916 igb_rx_hash(rx_ring, rx_desc, skb);
6917
6918 igb_rx_checksum(rx_ring, rx_desc, skb);
6919
5499a968
JK		 6920 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6921 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6922 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6923
f646968f 6924 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6925 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6926 u16 vid;
9005df38 6927
db2ee5bd
AD		 6928 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6929 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6930 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6931 else
6932 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6933
86a9bad3 6934 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6935 }
6936
6937 skb_record_rx_queue(skb, rx_ring->queue_index);
6938
6939 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6940}
6941
2e334eee 6942static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6943{
0ba82994 6944 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6945 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6946 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6947 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6948
57ba34c9 6949 while (likely(total_packets < budget)) {
2e334eee 6950 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6951
2e334eee
AD		 6952 /* return some buffers to hardware, one at a time is too slow */
6953 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6954 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6955 cleaned_count = 0;
6956 }
bf36c1a0 6957
2e334eee 6958 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6959
124b74c1 6960 if (!rx_desc->wb.upper.status_error)
2e334eee 6961 break;
9d5c8243 6962
74e238ea
AD		 6963 /* This memory barrier is needed to keep us from reading
6964 * any other fields out of the rx_desc until we know the
124b74c1 6965 * descriptor has been written back
74e238ea 6966 */
124b74c1 6967 dma_rmb();
74e238ea 6968
2e334eee 6969 /* retrieve a buffer from the ring */
f9d40f6a 6970 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6971
2e334eee
AD		 6972 /* exit if we failed to retrieve a buffer */
6973 if (!skb)
6974 break;
1a1c225b 6975
2e334eee 6976 cleaned_count++;
1a1c225b 6977
2e334eee
AD		 6978 /* fetch next buffer in frame if non-eop */
6979 if (igb_is_non_eop(rx_ring, rx_desc))
6980 continue;
1a1c225b
AD		 6981
6982 /* verify the packet layout is correct */
6983 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6984 skb = NULL;
6985 continue;
9d5c8243 6986 }
9d5c8243 6987
db2ee5bd 6988 /* probably a little skewed due to removing CRC */
3ceb90fd 6989 total_bytes += skb->len;
3ceb90fd 6990
db2ee5bd
AD		 6991 /* populate checksum, timestamp, VLAN, and protocol */
6992 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6993
b2cb09b1 6994 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6995
1a1c225b
AD		 6996 /* reset skb pointer */
6997 skb = NULL;
6998
2e334eee
AD		 6999 /* update budget accounting */
7000 total_packets++;
57ba34c9 7001 }
bf36c1a0 7002
1a1c225b
AD		 7003 /* place incomplete frames back on ring for completion */
7004 rx_ring->skb = skb;
7005
12dcd86b 7006 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7007 rx_ring->rx_stats.packets += total_packets;
7008 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7009 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7010 q_vector->rx.total_packets += total_packets;
7011 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7012
7013 if (cleaned_count)
cd392f5c 7014 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7015
da1f1dfe 7016 return total_packets < budget;
9d5c8243
AK		 7017}
7018
c023cd88 7019static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7020 struct igb_rx_buffer *bi)
c023cd88
AD		 7021{
7022 struct page *page = bi->page;
cbc8e55f 7023 dma_addr_t dma;
c023cd88 7024
cbc8e55f
AD		 7025 /* since we are recycling buffers we should seldom need to alloc */
7026 if (likely(page))
c023cd88
AD		 7027 return true;
7028
cbc8e55f 7029 /* alloc new page for storage */
42b17f09 7030 page = dev_alloc_page();
cbc8e55f
AD		 7031 if (unlikely(!page)) {
7032 rx_ring->rx_stats.alloc_failed++;
7033 return false;
c023cd88
AD		 7034 }
7035
cbc8e55f
AD		 7036 /* map page for use */
7037 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7038
b980ac18 7039 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7040 * there isn't much point in holding memory we can't use
7041 */
1a1c225b 7042 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7043 __free_page(page);
7044
c023cd88
AD		 7045 rx_ring->rx_stats.alloc_failed++;
7046 return false;
7047 }
7048
1a1c225b 7049 bi->dma = dma;
cbc8e55f
AD		 7050 bi->page = page;
7051 bi->page_offset = 0;
1a1c225b 7052
c023cd88
AD		 7053 return true;
7054}
7055
9d5c8243 7056/**
b980ac18
JK		 7057 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7058 * @adapter: address of board private structure
9d5c8243 7059 **/
cd392f5c 7060void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7061{
9d5c8243 7062 union e1000_adv_rx_desc *rx_desc;
06034649 7063 struct igb_rx_buffer *bi;
c023cd88 7064 u16 i = rx_ring->next_to_use;
9d5c8243 7065
cbc8e55f
AD		 7066 /* nothing to do */
7067 if (!cleaned_count)
7068 return;
7069
60136906 7070 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7071 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7072 i -= rx_ring->count;
9d5c8243 7073
cbc8e55f 7074 do {
1a1c225b 7075 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7076 break;
9d5c8243 7077
b980ac18 7078 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7079 * because each write-back erases this info.
7080 */
f9d40f6a 7081 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7082
c023cd88
AD		 7083 rx_desc++;
7084 bi++;
9d5c8243 7085 i++;
c023cd88 7086 if (unlikely(!i)) {
60136906 7087 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7088 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7089 i -= rx_ring->count;
7090 }
7091
95dd44b4
AD		 7092 /* clear the status bits for the next_to_use descriptor */
7093 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7094
7095 cleaned_count--;
7096 } while (cleaned_count);
9d5c8243 7097
c023cd88
AD		 7098 i += rx_ring->count;
7099
9d5c8243 7100 if (rx_ring->next_to_use != i) {
cbc8e55f 7101 /* record the next descriptor to use */
9d5c8243 7102 rx_ring->next_to_use = i;
9d5c8243 7103
cbc8e55f
AD		 7104 /* update next to alloc since we have filled the ring */
7105 rx_ring->next_to_alloc = i;
7106
b980ac18 7107 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7108 * know there are new descriptors to fetch. (Only
7109 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7110 * such as IA-64).
7111 */
9d5c8243 7112 wmb();
fce99e34 7113 writel(i, rx_ring->tail);
9d5c8243
AK		 7114 }
7115}
7116
7117/**
7118 * igb_mii_ioctl -
7119 * @netdev:
7120 * @ifreq:
7121 * @cmd:
7122 **/
7123static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7124{
7125 struct igb_adapter *adapter = netdev_priv(netdev);
7126 struct mii_ioctl_data *data = if_mii(ifr);
7127
7128 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7129 return -EOPNOTSUPP;
7130
7131 switch (cmd) {
7132 case SIOCGMIIPHY:
7133 data->phy_id = adapter->hw.phy.addr;
7134 break;
7135 case SIOCGMIIREG:
f5f4cf08 7136 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7137 &data->val_out))
9d5c8243
AK		 7138 return -EIO;
7139 break;
7140 case SIOCSMIIREG:
7141 default:
7142 return -EOPNOTSUPP;
7143 }
7144 return 0;
7145}
7146
7147/**
7148 * igb_ioctl -
7149 * @netdev:
7150 * @ifreq:
7151 * @cmd:
7152 **/
7153static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7154{
7155 switch (cmd) {
7156 case SIOCGMIIPHY:
7157 case SIOCGMIIREG:
7158 case SIOCSMIIREG:
7159 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7160 case SIOCGHWTSTAMP:
7161 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7162 case SIOCSHWTSTAMP:
6ab5f7b2 7163 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7164 default:
7165 return -EOPNOTSUPP;
7166 }
7167}
7168
94826487
TF		 7169void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7170{
7171 struct igb_adapter *adapter = hw->back;
7172
7173 pci_read_config_word(adapter->pdev, reg, value);
7174}
7175
7176void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7177{
7178 struct igb_adapter *adapter = hw->back;
7179
7180 pci_write_config_word(adapter->pdev, reg, *value);
7181}
7182
009bc06e
AD		 7183s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7184{
7185 struct igb_adapter *adapter = hw->back;
009bc06e 7186
23d028cc 7187 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7188 return -E1000_ERR_CONFIG;
7189
009bc06e
AD		 7190 return 0;
7191}
7192
7193s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7194{
7195 struct igb_adapter *adapter = hw->back;
009bc06e 7196
23d028cc 7197 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7198 return -E1000_ERR_CONFIG;
7199
009bc06e
AD		 7200 return 0;
7201}
7202
c8f44aff 7203static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7204{
7205 struct igb_adapter *adapter = netdev_priv(netdev);
7206 struct e1000_hw *hw = &adapter->hw;
7207 u32 ctrl, rctl;
f646968f 7208 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7209
5faf030c 7210 if (enable) {
9d5c8243
AK		 7211 /* enable VLAN tag insert/strip */
7212 ctrl = rd32(E1000_CTRL);
7213 ctrl |= E1000_CTRL_VME;
7214 wr32(E1000_CTRL, ctrl);
7215
51466239 7216 /* Disable CFI check */
9d5c8243 7217 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7218 rctl &= ~E1000_RCTL_CFIEN;
7219 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7220 } else {
7221 /* disable VLAN tag insert/strip */
7222 ctrl = rd32(E1000_CTRL);
7223 ctrl &= ~E1000_CTRL_VME;
7224 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7225 }
7226
e1739522 7227 igb_rlpml_set(adapter);
9d5c8243
AK		 7228}
7229
80d5c368
PM		 7230static int igb_vlan_rx_add_vid(struct net_device *netdev,
7231 __be16 proto, u16 vid)
9d5c8243
AK		 7232{
7233 struct igb_adapter *adapter = netdev_priv(netdev);
7234 struct e1000_hw *hw = &adapter->hw;
4ae196df 7235 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7236
51466239
AD		 7237 /* attempt to add filter to vlvf array */
7238 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7239
51466239
AD		 7240 /* add the filter since PF can receive vlans w/o entry in vlvf */
7241 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7242
7243 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7244
7245 return 0;
9d5c8243
AK		 7246}
7247
80d5c368
PM		 7248static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7249 __be16 proto, u16 vid)
9d5c8243
AK		 7250{
7251 struct igb_adapter *adapter = netdev_priv(netdev);
7252 struct e1000_hw *hw = &adapter->hw;
4ae196df 7253 int pf_id = adapter->vfs_allocated_count;
51466239 7254 s32 err;
9d5c8243 7255
51466239
AD		 7256 /* remove vlan from VLVF table array */
7257 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7258
51466239
AD		 7259 /* if vid was not present in VLVF just remove it from table */
7260 if (err)
4ae196df 7261 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7262
7263 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7264
7265 return 0;
9d5c8243
AK		 7266}
7267
7268static void igb_restore_vlan(struct igb_adapter *adapter)
7269{
b2cb09b1 7270 u16 vid;
9d5c8243 7271
5faf030c
AD		 7272 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7273
b2cb09b1 7274 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7275 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7276}
7277
14ad2513 7278int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7279{
090b1795 7280 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7281 struct e1000_mac_info *mac = &adapter->hw.mac;
7282
7283 mac->autoneg = 0;
7284
14ad2513 7285 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7286 * for the switch() below to work
7287 */
14ad2513
DD		 7288 if ((spd & 1) || (dplx & ~1))
7289 goto err_inval;
7290
f502ef7d
AA		 7291 /* Fiber NIC's only allow 1000 gbps Full duplex
7292 * and 100Mbps Full duplex for 100baseFx sfp
7293 */
7294 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7295 switch (spd + dplx) {
7296 case SPEED_10 + DUPLEX_HALF:
7297 case SPEED_10 + DUPLEX_FULL:
7298 case SPEED_100 + DUPLEX_HALF:
7299 goto err_inval;
7300 default:
7301 break;
7302 }
7303 }
cd2638a8 7304
14ad2513 7305 switch (spd + dplx) {
9d5c8243
AK		 7306 case SPEED_10 + DUPLEX_HALF:
7307 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7308 break;
7309 case SPEED_10 + DUPLEX_FULL:
7310 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7311 break;
7312 case SPEED_100 + DUPLEX_HALF:
7313 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7314 break;
7315 case SPEED_100 + DUPLEX_FULL:
7316 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7317 break;
7318 case SPEED_1000 + DUPLEX_FULL:
7319 mac->autoneg = 1;
7320 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7321 break;
7322 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7323 default:
14ad2513 7324 goto err_inval;
9d5c8243 7325 }
8376dad0
JB		 7326
7327 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7328 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7329
9d5c8243 7330 return 0;
14ad2513
DD		 7331
7332err_inval:
7333 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7334 return -EINVAL;
9d5c8243
AK		 7335}
7336
749ab2cd
YZ		 7337static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7338 bool runtime)
9d5c8243
AK		 7339{
7340 struct net_device *netdev = pci_get_drvdata(pdev);
7341 struct igb_adapter *adapter = netdev_priv(netdev);
7342 struct e1000_hw *hw = &adapter->hw;
2d064c06 7343 u32 ctrl, rctl, status;
749ab2cd 7344 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7345#ifdef CONFIG_PM
7346 int retval = 0;
7347#endif
7348
7349 netif_device_detach(netdev);
7350
a88f10ec 7351 if (netif_running(netdev))
749ab2cd 7352 __igb_close(netdev, true);
a88f10ec 7353
047e0030 7354 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7355
7356#ifdef CONFIG_PM
7357 retval = pci_save_state(pdev);
7358 if (retval)
7359 return retval;
7360#endif
7361
7362 status = rd32(E1000_STATUS);
7363 if (status & E1000_STATUS_LU)
7364 wufc &= ~E1000_WUFC_LNKC;
7365
7366 if (wufc) {
7367 igb_setup_rctl(adapter);
ff41f8dc 7368 igb_set_rx_mode(netdev);
9d5c8243
AK		 7369
7370 /* turn on all-multi mode if wake on multicast is enabled */
7371 if (wufc & E1000_WUFC_MC) {
7372 rctl = rd32(E1000_RCTL);
7373 rctl |= E1000_RCTL_MPE;
7374 wr32(E1000_RCTL, rctl);
7375 }
7376
7377 ctrl = rd32(E1000_CTRL);
7378 /* advertise wake from D3Cold */
7379 #define E1000_CTRL_ADVD3WUC 0x00100000
7380 /* phy power management enable */
7381 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7382 ctrl |= E1000_CTRL_ADVD3WUC;
7383 wr32(E1000_CTRL, ctrl);
7384
9d5c8243 7385 /* Allow time for pending master requests to run */
330a6d6a 7386 igb_disable_pcie_master(hw);
9d5c8243
AK		 7387
7388 wr32(E1000_WUC, E1000_WUC_PME_EN);
7389 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7390 } else {
7391 wr32(E1000_WUC, 0);
7392 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7393 }
7394
3fe7c4c9
RW		 7395 *enable_wake = wufc || adapter->en_mng_pt;
7396 if (!*enable_wake)
88a268c1
NN		 7397 igb_power_down_link(adapter);
7398 else
7399 igb_power_up_link(adapter);
9d5c8243
AK		 7400
7401 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7402 * would have already happened in close and is redundant.
7403 */
9d5c8243
AK		 7404 igb_release_hw_control(adapter);
7405
7406 pci_disable_device(pdev);
7407
9d5c8243
AK		 7408 return 0;
7409}
7410
7411#ifdef CONFIG_PM
d9dd966d 7412#ifdef CONFIG_PM_SLEEP
749ab2cd 7413static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7414{
7415 int retval;
7416 bool wake;
749ab2cd 7417 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7418
749ab2cd 7419 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7420 if (retval)
7421 return retval;
7422
7423 if (wake) {
7424 pci_prepare_to_sleep(pdev);
7425 } else {
7426 pci_wake_from_d3(pdev, false);
7427 pci_set_power_state(pdev, PCI_D3hot);
7428 }
7429
7430 return 0;
7431}
d9dd966d 7432#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7433
749ab2cd 7434static int igb_resume(struct device *dev)
9d5c8243 7435{
749ab2cd 7436 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7437 struct net_device *netdev = pci_get_drvdata(pdev);
7438 struct igb_adapter *adapter = netdev_priv(netdev);
7439 struct e1000_hw *hw = &adapter->hw;
7440 u32 err;
7441
7442 pci_set_power_state(pdev, PCI_D0);
7443 pci_restore_state(pdev);
b94f2d77 7444 pci_save_state(pdev);
42bfd33a 7445
17a402a0
CW		 7446 if (!pci_device_is_present(pdev))
7447 return -ENODEV;
aed5dec3 7448 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7449 if (err) {
7450 dev_err(&pdev->dev,
7451 "igb: Cannot enable PCI device from suspend\n");
7452 return err;
7453 }
7454 pci_set_master(pdev);
7455
7456 pci_enable_wake(pdev, PCI_D3hot, 0);
7457 pci_enable_wake(pdev, PCI_D3cold, 0);
7458
53c7d064 7459 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7460 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7461 return -ENOMEM;
9d5c8243
AK		 7462 }
7463
9d5c8243 7464 igb_reset(adapter);
a8564f03
AD		 7465
7466 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7467 * driver.
7468 */
a8564f03
AD		 7469 igb_get_hw_control(adapter);
7470
9d5c8243
AK		 7471 wr32(E1000_WUS, ~0);
7472
749ab2cd 7473 if (netdev->flags & IFF_UP) {
0c2cc02e 7474 rtnl_lock();
749ab2cd 7475 err = __igb_open(netdev, true);
0c2cc02e 7476 rtnl_unlock();
a88f10ec
AD		 7477 if (err)
7478 return err;
7479 }
9d5c8243
AK		 7480
7481 netif_device_attach(netdev);
749ab2cd
YZ		 7482 return 0;
7483}
7484
749ab2cd
YZ		 7485static int igb_runtime_idle(struct device *dev)
7486{
7487 struct pci_dev *pdev = to_pci_dev(dev);
7488 struct net_device *netdev = pci_get_drvdata(pdev);
7489 struct igb_adapter *adapter = netdev_priv(netdev);
7490
7491 if (!igb_has_link(adapter))
7492 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7493
7494 return -EBUSY;
7495}
7496
7497static int igb_runtime_suspend(struct device *dev)
7498{
7499 struct pci_dev *pdev = to_pci_dev(dev);
7500 int retval;
7501 bool wake;
7502
7503 retval = __igb_shutdown(pdev, &wake, 1);
7504 if (retval)
7505 return retval;
7506
7507 if (wake) {
7508 pci_prepare_to_sleep(pdev);
7509 } else {
7510 pci_wake_from_d3(pdev, false);
7511 pci_set_power_state(pdev, PCI_D3hot);
7512 }
9d5c8243 7513
9d5c8243
AK		 7514 return 0;
7515}
749ab2cd
YZ		 7516
7517static int igb_runtime_resume(struct device *dev)
7518{
7519 return igb_resume(dev);
7520}
d61c81cb 7521#endif /* CONFIG_PM */
9d5c8243
AK		 7522
7523static void igb_shutdown(struct pci_dev *pdev)
7524{
3fe7c4c9
RW		 7525 bool wake;
7526
749ab2cd 7527 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7528
7529 if (system_state == SYSTEM_POWER_OFF) {
7530 pci_wake_from_d3(pdev, wake);
7531 pci_set_power_state(pdev, PCI_D3hot);
7532 }
9d5c8243
AK		 7533}
7534
fa44f2f1
GR		 7535#ifdef CONFIG_PCI_IOV
7536static int igb_sriov_reinit(struct pci_dev *dev)
7537{
7538 struct net_device *netdev = pci_get_drvdata(dev);
7539 struct igb_adapter *adapter = netdev_priv(netdev);
7540 struct pci_dev *pdev = adapter->pdev;
7541
7542 rtnl_lock();
7543
7544 if (netif_running(netdev))
7545 igb_close(netdev);
76252723
SA		 7546 else
7547 igb_reset(adapter);
fa44f2f1
GR		 7548
7549 igb_clear_interrupt_scheme(adapter);
7550
7551 igb_init_queue_configuration(adapter);
7552
7553 if (igb_init_interrupt_scheme(adapter, true)) {
7554 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7555 return -ENOMEM;
7556 }
7557
7558 if (netif_running(netdev))
7559 igb_open(netdev);
7560
7561 rtnl_unlock();
7562
7563 return 0;
7564}
7565
7566static int igb_pci_disable_sriov(struct pci_dev *dev)
7567{
7568 int err = igb_disable_sriov(dev);
7569
7570 if (!err)
7571 err = igb_sriov_reinit(dev);
7572
7573 return err;
7574}
7575
7576static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7577{
7578 int err = igb_enable_sriov(dev, num_vfs);
7579
7580 if (err)
7581 goto out;
7582
7583 err = igb_sriov_reinit(dev);
7584 if (!err)
7585 return num_vfs;
7586
7587out:
7588 return err;
7589}
7590
7591#endif
7592static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7593{
7594#ifdef CONFIG_PCI_IOV
7595 if (num_vfs == 0)
7596 return igb_pci_disable_sriov(dev);
7597 else
7598 return igb_pci_enable_sriov(dev, num_vfs);
7599#endif
7600 return 0;
7601}
7602
9d5c8243 7603#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7604/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7605 * without having to re-enable interrupts. It's not called while
7606 * the interrupt routine is executing.
7607 */
7608static void igb_netpoll(struct net_device *netdev)
7609{
7610 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7611 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7612 struct igb_q_vector *q_vector;
9d5c8243 7613 int i;
9d5c8243 7614
047e0030 7615 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7616 q_vector = adapter->q_vector[i];
cd14ef54 7617 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7618 wr32(E1000_EIMC, q_vector->eims_value);
7619 else
7620 igb_irq_disable(adapter);
047e0030 7621 napi_schedule(&q_vector->napi);
eebbbdba 7622 }
9d5c8243
AK		 7623}
7624#endif /* CONFIG_NET_POLL_CONTROLLER */
7625
7626/**
b980ac18
JK		 7627 * igb_io_error_detected - called when PCI error is detected
7628 * @pdev: Pointer to PCI device
7629 * @state: The current pci connection state
9d5c8243 7630 *
b980ac18
JK		 7631 * This function is called after a PCI bus error affecting
7632 * this device has been detected.
7633 **/
9d5c8243
AK		 7634static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7635 pci_channel_state_t state)
7636{
7637 struct net_device *netdev = pci_get_drvdata(pdev);
7638 struct igb_adapter *adapter = netdev_priv(netdev);
7639
7640 netif_device_detach(netdev);
7641
59ed6eec
AD		 7642 if (state == pci_channel_io_perm_failure)
7643 return PCI_ERS_RESULT_DISCONNECT;
7644
9d5c8243
AK		 7645 if (netif_running(netdev))
7646 igb_down(adapter);
7647 pci_disable_device(pdev);
7648
7649 /* Request a slot slot reset. */
7650 return PCI_ERS_RESULT_NEED_RESET;
7651}
7652
7653/**
b980ac18
JK		 7654 * igb_io_slot_reset - called after the pci bus has been reset.
7655 * @pdev: Pointer to PCI device
9d5c8243 7656 *
b980ac18
JK		 7657 * Restart the card from scratch, as if from a cold-boot. Implementation
7658 * resembles the first-half of the igb_resume routine.
7659 **/
9d5c8243
AK		 7660static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7661{
7662 struct net_device *netdev = pci_get_drvdata(pdev);
7663 struct igb_adapter *adapter = netdev_priv(netdev);
7664 struct e1000_hw *hw = &adapter->hw;
40a914fa 7665 pci_ers_result_t result;
42bfd33a 7666 int err;
9d5c8243 7667
aed5dec3 7668 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7669 dev_err(&pdev->dev,
7670 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7671 result = PCI_ERS_RESULT_DISCONNECT;
7672 } else {
7673 pci_set_master(pdev);
7674 pci_restore_state(pdev);
b94f2d77 7675 pci_save_state(pdev);
9d5c8243 7676
40a914fa
AD		 7677 pci_enable_wake(pdev, PCI_D3hot, 0);
7678 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7679
40a914fa
AD		 7680 igb_reset(adapter);
7681 wr32(E1000_WUS, ~0);
7682 result = PCI_ERS_RESULT_RECOVERED;
7683 }
9d5c8243 7684
ea943d41
JK		 7685 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7686 if (err) {
b980ac18
JK		 7687 dev_err(&pdev->dev,
7688 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7689 err);
ea943d41
JK		 7690 /* non-fatal, continue */
7691 }
40a914fa
AD		 7692
7693 return result;
9d5c8243
AK		 7694}
7695
7696/**
b980ac18
JK		 7697 * igb_io_resume - called when traffic can start flowing again.
7698 * @pdev: Pointer to PCI device
9d5c8243 7699 *
b980ac18
JK		 7700 * This callback is called when the error recovery driver tells us that
7701 * its OK to resume normal operation. Implementation resembles the
7702 * second-half of the igb_resume routine.
9d5c8243
AK		 7703 */
7704static void igb_io_resume(struct pci_dev *pdev)
7705{
7706 struct net_device *netdev = pci_get_drvdata(pdev);
7707 struct igb_adapter *adapter = netdev_priv(netdev);
7708
9d5c8243
AK		 7709 if (netif_running(netdev)) {
7710 if (igb_up(adapter)) {
7711 dev_err(&pdev->dev, "igb_up failed after reset\n");
7712 return;
7713 }
7714 }
7715
7716 netif_device_attach(netdev);
7717
7718 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7719 * driver.
7720 */
9d5c8243 7721 igb_get_hw_control(adapter);
9d5c8243
AK		 7722}
7723
26ad9178 7724static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7725 u8 qsel)
26ad9178
AD		 7726{
7727 u32 rar_low, rar_high;
7728 struct e1000_hw *hw = &adapter->hw;
7729
7730 /* HW expects these in little endian so we reverse the byte order
7731 * from network order (big endian) to little endian
7732 */
7733 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7734 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7735 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7736
7737 /* Indicate to hardware the Address is Valid. */
7738 rar_high |= E1000_RAH_AV;
7739
7740 if (hw->mac.type == e1000_82575)
7741 rar_high |= E1000_RAH_POOL_1 * qsel;
7742 else
7743 rar_high |= E1000_RAH_POOL_1 << qsel;
7744
7745 wr32(E1000_RAL(index), rar_low);
7746 wrfl();
7747 wr32(E1000_RAH(index), rar_high);
7748 wrfl();
7749}
7750
4ae196df 7751static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7752 int vf, unsigned char *mac_addr)
4ae196df
AD		 7753{
7754 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7755 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7756 * towards the first, as a result a collision should not be possible
7757 */
ff41f8dc 7758 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7759
37680117 7760 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7761
26ad9178 7762 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7763
7764 return 0;
7765}
7766
8151d294
WM		 7767static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7768{
7769 struct igb_adapter *adapter = netdev_priv(netdev);
7770 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7771 return -EINVAL;
7772 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7773 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7774 dev_info(&adapter->pdev->dev,
7775 "Reload the VF driver to make this change effective.");
8151d294 7776 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7777 dev_warn(&adapter->pdev->dev,
7778 "The VF MAC address has been set, but the PF device is not up.\n");
7779 dev_warn(&adapter->pdev->dev,
7780 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7781 }
7782 return igb_set_vf_mac(adapter, vf, mac);
7783}
7784
17dc566c
LL		 7785static int igb_link_mbps(int internal_link_speed)
7786{
7787 switch (internal_link_speed) {
7788 case SPEED_100:
7789 return 100;
7790 case SPEED_1000:
7791 return 1000;
7792 default:
7793 return 0;
7794 }
7795}
7796
7797static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7798 int link_speed)
7799{
7800 int rf_dec, rf_int;
7801 u32 bcnrc_val;
7802
7803 if (tx_rate != 0) {
7804 /* Calculate the rate factor values to set */
7805 rf_int = link_speed / tx_rate;
7806 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7807 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7808 tx_rate;
17dc566c
LL		 7809
7810 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7811 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7812 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7813 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7814 } else {
7815 bcnrc_val = 0;
7816 }
7817
7818 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7819 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7820 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7821 */
7822 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7823 wr32(E1000_RTTBCNRC, bcnrc_val);
7824}
7825
7826static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7827{
7828 int actual_link_speed, i;
7829 bool reset_rate = false;
7830
7831 /* VF TX rate limit was not set or not supported */
7832 if ((adapter->vf_rate_link_speed == 0) ||
7833 (adapter->hw.mac.type != e1000_82576))
7834 return;
7835
7836 actual_link_speed = igb_link_mbps(adapter->link_speed);
7837 if (actual_link_speed != adapter->vf_rate_link_speed) {
7838 reset_rate = true;
7839 adapter->vf_rate_link_speed = 0;
7840 dev_info(&adapter->pdev->dev,
b980ac18 7841 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7842 }
7843
7844 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7845 if (reset_rate)
7846 adapter->vf_data[i].tx_rate = 0;
7847
7848 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7849 adapter->vf_data[i].tx_rate,
7850 actual_link_speed);
17dc566c
LL		 7851 }
7852}
7853
ed616689
SC		 7854static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7855 int min_tx_rate, int max_tx_rate)
8151d294 7856{
17dc566c
LL		 7857 struct igb_adapter *adapter = netdev_priv(netdev);
7858 struct e1000_hw *hw = &adapter->hw;
7859 int actual_link_speed;
7860
7861 if (hw->mac.type != e1000_82576)
7862 return -EOPNOTSUPP;
7863
ed616689
SC		 7864 if (min_tx_rate)
7865 return -EINVAL;
7866
17dc566c
LL		 7867 actual_link_speed = igb_link_mbps(adapter->link_speed);
7868 if ((vf >= adapter->vfs_allocated_count) ||
7869 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7870 (max_tx_rate < 0) ||
7871 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7872 return -EINVAL;
7873
7874 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7875 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7876 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7877
7878 return 0;
8151d294
WM		 7879}
7880
70ea4783
LL		 7881static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7882 bool setting)
7883{
7884 struct igb_adapter *adapter = netdev_priv(netdev);
7885 struct e1000_hw *hw = &adapter->hw;
7886 u32 reg_val, reg_offset;
7887
7888 if (!adapter->vfs_allocated_count)
7889 return -EOPNOTSUPP;
7890
7891 if (vf >= adapter->vfs_allocated_count)
7892 return -EINVAL;
7893
7894 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7895 reg_val = rd32(reg_offset);
7896 if (setting)
7897 reg_val |= ((1 << vf) |
7898 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7899 else
7900 reg_val &= ~((1 << vf) |
7901 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7902 wr32(reg_offset, reg_val);
7903
7904 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7905 return 0;
70ea4783
LL		 7906}
7907
8151d294
WM		 7908static int igb_ndo_get_vf_config(struct net_device *netdev,
7909 int vf, struct ifla_vf_info *ivi)
7910{
7911 struct igb_adapter *adapter = netdev_priv(netdev);
7912 if (vf >= adapter->vfs_allocated_count)
7913 return -EINVAL;
7914 ivi->vf = vf;
7915 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7916 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7917 ivi->min_tx_rate = 0;
8151d294
WM		 7918 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7919 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7920 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7921 return 0;
7922}
7923
4ae196df
AD		 7924static void igb_vmm_control(struct igb_adapter *adapter)
7925{
7926 struct e1000_hw *hw = &adapter->hw;
10d8e907 7927 u32 reg;
4ae196df 7928
52a1dd4d
AD		 7929 switch (hw->mac.type) {
7930 case e1000_82575:
f96a8a0b
CW		 7931 case e1000_i210:
7932 case e1000_i211:
ceb5f13b 7933 case e1000_i354:
52a1dd4d
AD		 7934 default:
7935 /* replication is not supported for 82575 */
4ae196df 7936 return;
52a1dd4d
AD		 7937 case e1000_82576:
7938 /* notify HW that the MAC is adding vlan tags */
7939 reg = rd32(E1000_DTXCTL);
7940 reg |= E1000_DTXCTL_VLAN_ADDED;
7941 wr32(E1000_DTXCTL, reg);
b26141d4 7942 /* Fall through */
52a1dd4d
AD		 7943 case e1000_82580:
7944 /* enable replication vlan tag stripping */
7945 reg = rd32(E1000_RPLOLR);
7946 reg |= E1000_RPLOLR_STRVLAN;
7947 wr32(E1000_RPLOLR, reg);
b26141d4 7948 /* Fall through */
d2ba2ed8
AD		 7949 case e1000_i350:
7950 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7951 break;
7952 }
10d8e907 7953
d4960307
AD		 7954 if (adapter->vfs_allocated_count) {
7955 igb_vmdq_set_loopback_pf(hw, true);
7956 igb_vmdq_set_replication_pf(hw, true);
13800469 7957 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7958 adapter->vfs_allocated_count);
d4960307
AD		 7959 } else {
7960 igb_vmdq_set_loopback_pf(hw, false);
7961 igb_vmdq_set_replication_pf(hw, false);
7962 }
4ae196df
AD		 7963}
7964
b6e0c419
CW		 7965static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7966{
7967 struct e1000_hw *hw = &adapter->hw;
7968 u32 dmac_thr;
7969 u16 hwm;
7970
7971 if (hw->mac.type > e1000_82580) {
7972 if (adapter->flags & IGB_FLAG_DMAC) {
7973 u32 reg;
7974
7975 /* force threshold to 0. */
7976 wr32(E1000_DMCTXTH, 0);
7977
b980ac18 7978 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7979 * than the Rx threshold. Set hwm to PBA - max frame
7980 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7981 */
e8c626e9
MV		 7982 hwm = 64 * pba - adapter->max_frame_size / 16;
7983 if (hwm < 64 * (pba - 6))
7984 hwm = 64 * (pba - 6);
7985 reg = rd32(E1000_FCRTC);
7986 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7987 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7988 & E1000_FCRTC_RTH_COAL_MASK);
7989 wr32(E1000_FCRTC, reg);
7990
b980ac18 7991 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7992 * frame size, capping it at PBA - 10KB.
7993 */
7994 dmac_thr = pba - adapter->max_frame_size / 512;
7995 if (dmac_thr < pba - 10)
7996 dmac_thr = pba - 10;
b6e0c419
CW		 7997 reg = rd32(E1000_DMACR);
7998 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7999 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8000 & E1000_DMACR_DMACTHR_MASK);
8001
8002 /* transition to L0x or L1 if available..*/
8003 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8004
8005 /* watchdog timer= +-1000 usec in 32usec intervals */
8006 reg |= (1000 >> 5);
0c02dd98
MV		 8007
8008 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8009 if (hw->mac.type != e1000_i354)
8010 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8011
b6e0c419
CW		 8012 wr32(E1000_DMACR, reg);
8013
b980ac18 8014 /* no lower threshold to disable
b6e0c419
CW		 8015 * coalescing(smart fifb)-UTRESH=0
8016 */
8017 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8018
8019 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8020
8021 wr32(E1000_DMCTLX, reg);
8022
b980ac18 8023 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8024 * DMA coal
8025 */
8026 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8027 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8028
b980ac18 8029 /* make low power state decision controlled
b6e0c419
CW		 8030 * by DMA coal
8031 */
8032 reg = rd32(E1000_PCIEMISC);
8033 reg &= ~E1000_PCIEMISC_LX_DECISION;
8034 wr32(E1000_PCIEMISC, reg);
8035 } /* endif adapter->dmac is not disabled */
8036 } else if (hw->mac.type == e1000_82580) {
8037 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8038
b6e0c419
CW		 8039 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8040 wr32(E1000_DMACR, 0);
8041 }
8042}
8043
b980ac18
JK		 8044/**
8045 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8046 * @hw: pointer to hardware structure
8047 * @byte_offset: byte offset to read
8048 * @dev_addr: device address
8049 * @data: value read
8050 *
8051 * Performs byte read operation over I2C interface at
8052 * a specified device address.
b980ac18 8053 **/
441fc6fd 8054s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8055 u8 dev_addr, u8 *data)
441fc6fd
CW		 8056{
8057 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8058 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8059 s32 status;
8060 u16 swfw_mask = 0;
8061
8062 if (!this_client)
8063 return E1000_ERR_I2C;
8064
8065 swfw_mask = E1000_SWFW_PHY0_SM;
8066
23d87824 8067 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8068 return E1000_ERR_SWFW_SYNC;
8069
8070 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8071 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8072
8073 if (status < 0)
8074 return E1000_ERR_I2C;
8075 else {
8076 *data = status;
23d87824 8077 return 0;
441fc6fd
CW		 8078 }
8079}
8080
b980ac18
JK		 8081/**
8082 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8083 * @hw: pointer to hardware structure
8084 * @byte_offset: byte offset to write
8085 * @dev_addr: device address
8086 * @data: value to write
8087 *
8088 * Performs byte write operation over I2C interface at
8089 * a specified device address.
b980ac18 8090 **/
441fc6fd 8091s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8092 u8 dev_addr, u8 data)
441fc6fd
CW		 8093{
8094 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8095 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8096 s32 status;
8097 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8098
8099 if (!this_client)
8100 return E1000_ERR_I2C;
8101
23d87824 8102 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8103 return E1000_ERR_SWFW_SYNC;
8104 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8105 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8106
8107 if (status)
8108 return E1000_ERR_I2C;
8109 else
23d87824 8110 return 0;
441fc6fd
CW		 8111
8112}
907b7835
LMV		 8113
8114int igb_reinit_queues(struct igb_adapter *adapter)
8115{
8116 struct net_device *netdev = adapter->netdev;
8117 struct pci_dev *pdev = adapter->pdev;
8118 int err = 0;
8119
8120 if (netif_running(netdev))
8121 igb_close(netdev);
8122
02ef6e1d 8123 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8124
8125 if (igb_init_interrupt_scheme(adapter, true)) {
8126 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8127 return -ENOMEM;
8128 }
8129
8130 if (netif_running(netdev))
8131 err = igb_open(netdev);
8132
8133 return err;
8134}
9d5c8243 8135/* igb_main.c */
Linux kernel - Deliverables
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