Commit | Line | Data |
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9d5c8243 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel(R) Gigabit Ethernet Linux driver | |
4b9ea462 | 4 | Copyright(c) 2007-2013 Intel Corporation. |
9d5c8243 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
876d2d6f JK |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
9d5c8243 AK |
30 | #include <linux/module.h> |
31 | #include <linux/types.h> | |
32 | #include <linux/init.h> | |
b2cb09b1 | 33 | #include <linux/bitops.h> |
9d5c8243 AK |
34 | #include <linux/vmalloc.h> |
35 | #include <linux/pagemap.h> | |
36 | #include <linux/netdevice.h> | |
9d5c8243 | 37 | #include <linux/ipv6.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
9d5c8243 AK |
39 | #include <net/checksum.h> |
40 | #include <net/ip6_checksum.h> | |
c6cb090b | 41 | #include <linux/net_tstamp.h> |
9d5c8243 AK |
42 | #include <linux/mii.h> |
43 | #include <linux/ethtool.h> | |
01789349 | 44 | #include <linux/if.h> |
9d5c8243 AK |
45 | #include <linux/if_vlan.h> |
46 | #include <linux/pci.h> | |
c54106bb | 47 | #include <linux/pci-aspm.h> |
9d5c8243 AK |
48 | #include <linux/delay.h> |
49 | #include <linux/interrupt.h> | |
7d13a7d0 AD |
50 | #include <linux/ip.h> |
51 | #include <linux/tcp.h> | |
52 | #include <linux/sctp.h> | |
9d5c8243 | 53 | #include <linux/if_ether.h> |
40a914fa | 54 | #include <linux/aer.h> |
70c71606 | 55 | #include <linux/prefetch.h> |
749ab2cd | 56 | #include <linux/pm_runtime.h> |
421e02f0 | 57 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
58 | #include <linux/dca.h> |
59 | #endif | |
441fc6fd | 60 | #include <linux/i2c.h> |
9d5c8243 AK |
61 | #include "igb.h" |
62 | ||
67b1b903 CW |
63 | #define MAJ 5 |
64 | #define MIN 0 | |
65 | #define BUILD 3 | |
0d1fe82d | 66 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
929dd047 | 67 | __stringify(BUILD) "-k" |
9d5c8243 AK |
68 | char igb_driver_name[] = "igb"; |
69 | char igb_driver_version[] = DRV_VERSION; | |
70 | static const char igb_driver_string[] = | |
71 | "Intel(R) Gigabit Ethernet Network Driver"; | |
4b9ea462 AA |
72 | static const char igb_copyright[] = |
73 | "Copyright (c) 2007-2013 Intel Corporation."; | |
9d5c8243 | 74 | |
9d5c8243 AK |
75 | static const struct e1000_info *igb_info_tbl[] = { |
76 | [board_82575] = &e1000_82575_info, | |
77 | }; | |
78 | ||
a3aa1884 | 79 | static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { |
ceb5f13b CW |
80 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, |
81 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, | |
82 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, | |
f96a8a0b CW |
83 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, |
84 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, | |
85 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, | |
86 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, | |
87 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, | |
53b87ce3 CW |
88 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, |
89 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, | |
d2ba2ed8 AD |
90 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, |
91 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, | |
92 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, | |
93 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, | |
55cac248 AD |
94 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, |
95 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, | |
6493d24f | 96 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, |
55cac248 AD |
97 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, |
98 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, | |
99 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, | |
308fb39a JG |
100 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, |
101 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, | |
1b5dda33 GJ |
102 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, |
103 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, | |
2d064c06 | 104 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, |
9eb2341d | 105 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, |
747d49ba | 106 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, |
2d064c06 AD |
107 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, |
108 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, | |
4703bf73 | 109 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, |
b894fa26 | 110 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, |
c8ea5ea9 | 111 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, |
9d5c8243 AK |
112 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, |
113 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, | |
114 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, | |
115 | /* required last entry */ | |
116 | {0, } | |
117 | }; | |
118 | ||
119 | MODULE_DEVICE_TABLE(pci, igb_pci_tbl); | |
120 | ||
121 | void igb_reset(struct igb_adapter *); | |
122 | static int igb_setup_all_tx_resources(struct igb_adapter *); | |
123 | static int igb_setup_all_rx_resources(struct igb_adapter *); | |
124 | static void igb_free_all_tx_resources(struct igb_adapter *); | |
125 | static void igb_free_all_rx_resources(struct igb_adapter *); | |
06cf2666 | 126 | static void igb_setup_mrqc(struct igb_adapter *); |
9d5c8243 | 127 | static int igb_probe(struct pci_dev *, const struct pci_device_id *); |
9f9a12f8 | 128 | static void igb_remove(struct pci_dev *pdev); |
9d5c8243 AK |
129 | static int igb_sw_init(struct igb_adapter *); |
130 | static int igb_open(struct net_device *); | |
131 | static int igb_close(struct net_device *); | |
53c7d064 | 132 | static void igb_configure(struct igb_adapter *); |
9d5c8243 AK |
133 | static void igb_configure_tx(struct igb_adapter *); |
134 | static void igb_configure_rx(struct igb_adapter *); | |
9d5c8243 AK |
135 | static void igb_clean_all_tx_rings(struct igb_adapter *); |
136 | static void igb_clean_all_rx_rings(struct igb_adapter *); | |
3b644cf6 MW |
137 | static void igb_clean_tx_ring(struct igb_ring *); |
138 | static void igb_clean_rx_ring(struct igb_ring *); | |
ff41f8dc | 139 | static void igb_set_rx_mode(struct net_device *); |
9d5c8243 AK |
140 | static void igb_update_phy_info(unsigned long); |
141 | static void igb_watchdog(unsigned long); | |
142 | static void igb_watchdog_task(struct work_struct *); | |
cd392f5c | 143 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); |
12dcd86b ED |
144 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, |
145 | struct rtnl_link_stats64 *stats); | |
9d5c8243 AK |
146 | static int igb_change_mtu(struct net_device *, int); |
147 | static int igb_set_mac(struct net_device *, void *); | |
68d480c4 | 148 | static void igb_set_uta(struct igb_adapter *adapter); |
9d5c8243 AK |
149 | static irqreturn_t igb_intr(int irq, void *); |
150 | static irqreturn_t igb_intr_msi(int irq, void *); | |
151 | static irqreturn_t igb_msix_other(int irq, void *); | |
047e0030 | 152 | static irqreturn_t igb_msix_ring(int irq, void *); |
421e02f0 | 153 | #ifdef CONFIG_IGB_DCA |
047e0030 | 154 | static void igb_update_dca(struct igb_q_vector *); |
fe4506b6 | 155 | static void igb_setup_dca(struct igb_adapter *); |
421e02f0 | 156 | #endif /* CONFIG_IGB_DCA */ |
661086df | 157 | static int igb_poll(struct napi_struct *, int); |
13fde97a | 158 | static bool igb_clean_tx_irq(struct igb_q_vector *); |
cd392f5c | 159 | static bool igb_clean_rx_irq(struct igb_q_vector *, int); |
9d5c8243 AK |
160 | static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); |
161 | static void igb_tx_timeout(struct net_device *); | |
162 | static void igb_reset_task(struct work_struct *); | |
c8f44aff | 163 | static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); |
80d5c368 PM |
164 | static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); |
165 | static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); | |
9d5c8243 | 166 | static void igb_restore_vlan(struct igb_adapter *); |
26ad9178 | 167 | static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); |
4ae196df AD |
168 | static void igb_ping_all_vfs(struct igb_adapter *); |
169 | static void igb_msg_task(struct igb_adapter *); | |
4ae196df | 170 | static void igb_vmm_control(struct igb_adapter *); |
f2ca0dbe | 171 | static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); |
4ae196df | 172 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter); |
8151d294 WM |
173 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); |
174 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
175 | int vf, u16 vlan, u8 qos); | |
176 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); | |
70ea4783 LL |
177 | static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, |
178 | bool setting); | |
8151d294 WM |
179 | static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, |
180 | struct ifla_vf_info *ivi); | |
17dc566c | 181 | static void igb_check_vf_rate_limit(struct igb_adapter *); |
46a01698 RL |
182 | |
183 | #ifdef CONFIG_PCI_IOV | |
0224d663 | 184 | static int igb_vf_configure(struct igb_adapter *adapter, int vf); |
46a01698 | 185 | #endif |
9d5c8243 | 186 | |
9d5c8243 | 187 | #ifdef CONFIG_PM |
d9dd966d | 188 | #ifdef CONFIG_PM_SLEEP |
749ab2cd | 189 | static int igb_suspend(struct device *); |
d9dd966d | 190 | #endif |
749ab2cd YZ |
191 | static int igb_resume(struct device *); |
192 | #ifdef CONFIG_PM_RUNTIME | |
193 | static int igb_runtime_suspend(struct device *dev); | |
194 | static int igb_runtime_resume(struct device *dev); | |
195 | static int igb_runtime_idle(struct device *dev); | |
196 | #endif | |
197 | static const struct dev_pm_ops igb_pm_ops = { | |
198 | SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) | |
199 | SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, | |
200 | igb_runtime_idle) | |
201 | }; | |
9d5c8243 AK |
202 | #endif |
203 | static void igb_shutdown(struct pci_dev *); | |
fa44f2f1 | 204 | static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); |
421e02f0 | 205 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
206 | static int igb_notify_dca(struct notifier_block *, unsigned long, void *); |
207 | static struct notifier_block dca_notifier = { | |
208 | .notifier_call = igb_notify_dca, | |
209 | .next = NULL, | |
210 | .priority = 0 | |
211 | }; | |
212 | #endif | |
9d5c8243 AK |
213 | #ifdef CONFIG_NET_POLL_CONTROLLER |
214 | /* for netdump / net console */ | |
215 | static void igb_netpoll(struct net_device *); | |
216 | #endif | |
37680117 | 217 | #ifdef CONFIG_PCI_IOV |
2a3abf6d AD |
218 | static unsigned int max_vfs = 0; |
219 | module_param(max_vfs, uint, 0); | |
220 | MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " | |
221 | "per physical function"); | |
222 | #endif /* CONFIG_PCI_IOV */ | |
223 | ||
9d5c8243 AK |
224 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *, |
225 | pci_channel_state_t); | |
226 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); | |
227 | static void igb_io_resume(struct pci_dev *); | |
228 | ||
3646f0e5 | 229 | static const struct pci_error_handlers igb_err_handler = { |
9d5c8243 AK |
230 | .error_detected = igb_io_error_detected, |
231 | .slot_reset = igb_io_slot_reset, | |
232 | .resume = igb_io_resume, | |
233 | }; | |
234 | ||
b6e0c419 | 235 | static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); |
9d5c8243 AK |
236 | |
237 | static struct pci_driver igb_driver = { | |
238 | .name = igb_driver_name, | |
239 | .id_table = igb_pci_tbl, | |
240 | .probe = igb_probe, | |
9f9a12f8 | 241 | .remove = igb_remove, |
9d5c8243 | 242 | #ifdef CONFIG_PM |
749ab2cd | 243 | .driver.pm = &igb_pm_ops, |
9d5c8243 AK |
244 | #endif |
245 | .shutdown = igb_shutdown, | |
fa44f2f1 | 246 | .sriov_configure = igb_pci_sriov_configure, |
9d5c8243 AK |
247 | .err_handler = &igb_err_handler |
248 | }; | |
249 | ||
250 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
251 | MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); | |
252 | MODULE_LICENSE("GPL"); | |
253 | MODULE_VERSION(DRV_VERSION); | |
254 | ||
b3f4d599 | 255 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
256 | static int debug = -1; | |
257 | module_param(debug, int, 0); | |
258 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
259 | ||
c97ec42a TI |
260 | struct igb_reg_info { |
261 | u32 ofs; | |
262 | char *name; | |
263 | }; | |
264 | ||
265 | static const struct igb_reg_info igb_reg_info_tbl[] = { | |
266 | ||
267 | /* General Registers */ | |
268 | {E1000_CTRL, "CTRL"}, | |
269 | {E1000_STATUS, "STATUS"}, | |
270 | {E1000_CTRL_EXT, "CTRL_EXT"}, | |
271 | ||
272 | /* Interrupt Registers */ | |
273 | {E1000_ICR, "ICR"}, | |
274 | ||
275 | /* RX Registers */ | |
276 | {E1000_RCTL, "RCTL"}, | |
277 | {E1000_RDLEN(0), "RDLEN"}, | |
278 | {E1000_RDH(0), "RDH"}, | |
279 | {E1000_RDT(0), "RDT"}, | |
280 | {E1000_RXDCTL(0), "RXDCTL"}, | |
281 | {E1000_RDBAL(0), "RDBAL"}, | |
282 | {E1000_RDBAH(0), "RDBAH"}, | |
283 | ||
284 | /* TX Registers */ | |
285 | {E1000_TCTL, "TCTL"}, | |
286 | {E1000_TDBAL(0), "TDBAL"}, | |
287 | {E1000_TDBAH(0), "TDBAH"}, | |
288 | {E1000_TDLEN(0), "TDLEN"}, | |
289 | {E1000_TDH(0), "TDH"}, | |
290 | {E1000_TDT(0), "TDT"}, | |
291 | {E1000_TXDCTL(0), "TXDCTL"}, | |
292 | {E1000_TDFH, "TDFH"}, | |
293 | {E1000_TDFT, "TDFT"}, | |
294 | {E1000_TDFHS, "TDFHS"}, | |
295 | {E1000_TDFPC, "TDFPC"}, | |
296 | ||
297 | /* List Terminator */ | |
298 | {} | |
299 | }; | |
300 | ||
b980ac18 | 301 | /* igb_regdump - register printout routine */ |
c97ec42a TI |
302 | static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) |
303 | { | |
304 | int n = 0; | |
305 | char rname[16]; | |
306 | u32 regs[8]; | |
307 | ||
308 | switch (reginfo->ofs) { | |
309 | case E1000_RDLEN(0): | |
310 | for (n = 0; n < 4; n++) | |
311 | regs[n] = rd32(E1000_RDLEN(n)); | |
312 | break; | |
313 | case E1000_RDH(0): | |
314 | for (n = 0; n < 4; n++) | |
315 | regs[n] = rd32(E1000_RDH(n)); | |
316 | break; | |
317 | case E1000_RDT(0): | |
318 | for (n = 0; n < 4; n++) | |
319 | regs[n] = rd32(E1000_RDT(n)); | |
320 | break; | |
321 | case E1000_RXDCTL(0): | |
322 | for (n = 0; n < 4; n++) | |
323 | regs[n] = rd32(E1000_RXDCTL(n)); | |
324 | break; | |
325 | case E1000_RDBAL(0): | |
326 | for (n = 0; n < 4; n++) | |
327 | regs[n] = rd32(E1000_RDBAL(n)); | |
328 | break; | |
329 | case E1000_RDBAH(0): | |
330 | for (n = 0; n < 4; n++) | |
331 | regs[n] = rd32(E1000_RDBAH(n)); | |
332 | break; | |
333 | case E1000_TDBAL(0): | |
334 | for (n = 0; n < 4; n++) | |
335 | regs[n] = rd32(E1000_RDBAL(n)); | |
336 | break; | |
337 | case E1000_TDBAH(0): | |
338 | for (n = 0; n < 4; n++) | |
339 | regs[n] = rd32(E1000_TDBAH(n)); | |
340 | break; | |
341 | case E1000_TDLEN(0): | |
342 | for (n = 0; n < 4; n++) | |
343 | regs[n] = rd32(E1000_TDLEN(n)); | |
344 | break; | |
345 | case E1000_TDH(0): | |
346 | for (n = 0; n < 4; n++) | |
347 | regs[n] = rd32(E1000_TDH(n)); | |
348 | break; | |
349 | case E1000_TDT(0): | |
350 | for (n = 0; n < 4; n++) | |
351 | regs[n] = rd32(E1000_TDT(n)); | |
352 | break; | |
353 | case E1000_TXDCTL(0): | |
354 | for (n = 0; n < 4; n++) | |
355 | regs[n] = rd32(E1000_TXDCTL(n)); | |
356 | break; | |
357 | default: | |
876d2d6f | 358 | pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); |
c97ec42a TI |
359 | return; |
360 | } | |
361 | ||
362 | snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); | |
876d2d6f JK |
363 | pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], |
364 | regs[2], regs[3]); | |
c97ec42a TI |
365 | } |
366 | ||
b980ac18 | 367 | /* igb_dump - Print registers, Tx-rings and Rx-rings */ |
c97ec42a TI |
368 | static void igb_dump(struct igb_adapter *adapter) |
369 | { | |
370 | struct net_device *netdev = adapter->netdev; | |
371 | struct e1000_hw *hw = &adapter->hw; | |
372 | struct igb_reg_info *reginfo; | |
c97ec42a TI |
373 | struct igb_ring *tx_ring; |
374 | union e1000_adv_tx_desc *tx_desc; | |
375 | struct my_u0 { u64 a; u64 b; } *u0; | |
c97ec42a TI |
376 | struct igb_ring *rx_ring; |
377 | union e1000_adv_rx_desc *rx_desc; | |
378 | u32 staterr; | |
6ad4edfc | 379 | u16 i, n; |
c97ec42a TI |
380 | |
381 | if (!netif_msg_hw(adapter)) | |
382 | return; | |
383 | ||
384 | /* Print netdevice Info */ | |
385 | if (netdev) { | |
386 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
876d2d6f JK |
387 | pr_info("Device Name state trans_start " |
388 | "last_rx\n"); | |
389 | pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, | |
390 | netdev->state, netdev->trans_start, netdev->last_rx); | |
c97ec42a TI |
391 | } |
392 | ||
393 | /* Print Registers */ | |
394 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
876d2d6f | 395 | pr_info(" Register Name Value\n"); |
c97ec42a TI |
396 | for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; |
397 | reginfo->name; reginfo++) { | |
398 | igb_regdump(hw, reginfo); | |
399 | } | |
400 | ||
401 | /* Print TX Ring Summary */ | |
402 | if (!netdev || !netif_running(netdev)) | |
403 | goto exit; | |
404 | ||
405 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
876d2d6f | 406 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
c97ec42a | 407 | for (n = 0; n < adapter->num_tx_queues; n++) { |
06034649 | 408 | struct igb_tx_buffer *buffer_info; |
c97ec42a | 409 | tx_ring = adapter->tx_ring[n]; |
06034649 | 410 | buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
876d2d6f JK |
411 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
412 | n, tx_ring->next_to_use, tx_ring->next_to_clean, | |
c9f14bf3 AD |
413 | (u64)dma_unmap_addr(buffer_info, dma), |
414 | dma_unmap_len(buffer_info, len), | |
876d2d6f JK |
415 | buffer_info->next_to_watch, |
416 | (u64)buffer_info->time_stamp); | |
c97ec42a TI |
417 | } |
418 | ||
419 | /* Print TX Rings */ | |
420 | if (!netif_msg_tx_done(adapter)) | |
421 | goto rx_ring_summary; | |
422 | ||
423 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
424 | ||
425 | /* Transmit Descriptor Formats | |
426 | * | |
427 | * Advanced Transmit Descriptor | |
428 | * +--------------------------------------------------------------+ | |
429 | * 0 | Buffer Address [63:0] | | |
430 | * +--------------------------------------------------------------+ | |
431 | * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | | |
432 | * +--------------------------------------------------------------+ | |
433 | * 63 46 45 40 39 38 36 35 32 31 24 15 0 | |
434 | */ | |
435 | ||
436 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
437 | tx_ring = adapter->tx_ring[n]; | |
876d2d6f JK |
438 | pr_info("------------------------------------\n"); |
439 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
440 | pr_info("------------------------------------\n"); | |
441 | pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " | |
442 | "[bi->dma ] leng ntw timestamp " | |
443 | "bi->skb\n"); | |
c97ec42a TI |
444 | |
445 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
876d2d6f | 446 | const char *next_desc; |
06034649 | 447 | struct igb_tx_buffer *buffer_info; |
60136906 | 448 | tx_desc = IGB_TX_DESC(tx_ring, i); |
06034649 | 449 | buffer_info = &tx_ring->tx_buffer_info[i]; |
c97ec42a | 450 | u0 = (struct my_u0 *)tx_desc; |
876d2d6f JK |
451 | if (i == tx_ring->next_to_use && |
452 | i == tx_ring->next_to_clean) | |
453 | next_desc = " NTC/U"; | |
454 | else if (i == tx_ring->next_to_use) | |
455 | next_desc = " NTU"; | |
456 | else if (i == tx_ring->next_to_clean) | |
457 | next_desc = " NTC"; | |
458 | else | |
459 | next_desc = ""; | |
460 | ||
461 | pr_info("T [0x%03X] %016llX %016llX %016llX" | |
462 | " %04X %p %016llX %p%s\n", i, | |
c97ec42a TI |
463 | le64_to_cpu(u0->a), |
464 | le64_to_cpu(u0->b), | |
c9f14bf3 AD |
465 | (u64)dma_unmap_addr(buffer_info, dma), |
466 | dma_unmap_len(buffer_info, len), | |
c97ec42a TI |
467 | buffer_info->next_to_watch, |
468 | (u64)buffer_info->time_stamp, | |
876d2d6f | 469 | buffer_info->skb, next_desc); |
c97ec42a | 470 | |
b669588a | 471 | if (netif_msg_pktdata(adapter) && buffer_info->skb) |
c97ec42a TI |
472 | print_hex_dump(KERN_INFO, "", |
473 | DUMP_PREFIX_ADDRESS, | |
b669588a | 474 | 16, 1, buffer_info->skb->data, |
c9f14bf3 AD |
475 | dma_unmap_len(buffer_info, len), |
476 | true); | |
c97ec42a TI |
477 | } |
478 | } | |
479 | ||
480 | /* Print RX Rings Summary */ | |
481 | rx_ring_summary: | |
482 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
876d2d6f | 483 | pr_info("Queue [NTU] [NTC]\n"); |
c97ec42a TI |
484 | for (n = 0; n < adapter->num_rx_queues; n++) { |
485 | rx_ring = adapter->rx_ring[n]; | |
876d2d6f JK |
486 | pr_info(" %5d %5X %5X\n", |
487 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
c97ec42a TI |
488 | } |
489 | ||
490 | /* Print RX Rings */ | |
491 | if (!netif_msg_rx_status(adapter)) | |
492 | goto exit; | |
493 | ||
494 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
495 | ||
496 | /* Advanced Receive Descriptor (Read) Format | |
497 | * 63 1 0 | |
498 | * +-----------------------------------------------------+ | |
499 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
500 | * +----------------------------------------------+------+ | |
501 | * 8 | Header Buffer Address [63:1] | DD | | |
502 | * +-----------------------------------------------------+ | |
503 | * | |
504 | * | |
505 | * Advanced Receive Descriptor (Write-Back) Format | |
506 | * | |
507 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
508 | * +------------------------------------------------------+ | |
509 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
510 | * | Checksum Ident | | | | Type | Type | | |
511 | * +------------------------------------------------------+ | |
512 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
513 | * +------------------------------------------------------+ | |
514 | * 63 48 47 32 31 20 19 0 | |
515 | */ | |
516 | ||
517 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
518 | rx_ring = adapter->rx_ring[n]; | |
876d2d6f JK |
519 | pr_info("------------------------------------\n"); |
520 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
521 | pr_info("------------------------------------\n"); | |
522 | pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " | |
523 | "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); | |
524 | pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" | |
525 | "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); | |
c97ec42a TI |
526 | |
527 | for (i = 0; i < rx_ring->count; i++) { | |
876d2d6f | 528 | const char *next_desc; |
06034649 AD |
529 | struct igb_rx_buffer *buffer_info; |
530 | buffer_info = &rx_ring->rx_buffer_info[i]; | |
60136906 | 531 | rx_desc = IGB_RX_DESC(rx_ring, i); |
c97ec42a TI |
532 | u0 = (struct my_u0 *)rx_desc; |
533 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
876d2d6f JK |
534 | |
535 | if (i == rx_ring->next_to_use) | |
536 | next_desc = " NTU"; | |
537 | else if (i == rx_ring->next_to_clean) | |
538 | next_desc = " NTC"; | |
539 | else | |
540 | next_desc = ""; | |
541 | ||
c97ec42a TI |
542 | if (staterr & E1000_RXD_STAT_DD) { |
543 | /* Descriptor Done */ | |
1a1c225b AD |
544 | pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", |
545 | "RWB", i, | |
c97ec42a TI |
546 | le64_to_cpu(u0->a), |
547 | le64_to_cpu(u0->b), | |
1a1c225b | 548 | next_desc); |
c97ec42a | 549 | } else { |
1a1c225b AD |
550 | pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", |
551 | "R ", i, | |
c97ec42a TI |
552 | le64_to_cpu(u0->a), |
553 | le64_to_cpu(u0->b), | |
554 | (u64)buffer_info->dma, | |
1a1c225b | 555 | next_desc); |
c97ec42a | 556 | |
b669588a | 557 | if (netif_msg_pktdata(adapter) && |
1a1c225b | 558 | buffer_info->dma && buffer_info->page) { |
44390ca6 AD |
559 | print_hex_dump(KERN_INFO, "", |
560 | DUMP_PREFIX_ADDRESS, | |
561 | 16, 1, | |
b669588a ET |
562 | page_address(buffer_info->page) + |
563 | buffer_info->page_offset, | |
de78d1f9 | 564 | IGB_RX_BUFSZ, true); |
c97ec42a TI |
565 | } |
566 | } | |
c97ec42a TI |
567 | } |
568 | } | |
569 | ||
570 | exit: | |
571 | return; | |
572 | } | |
573 | ||
b980ac18 JK |
574 | /** |
575 | * igb_get_i2c_data - Reads the I2C SDA data bit | |
441fc6fd CW |
576 | * @hw: pointer to hardware structure |
577 | * @i2cctl: Current value of I2CCTL register | |
578 | * | |
579 | * Returns the I2C data bit value | |
b980ac18 | 580 | **/ |
441fc6fd CW |
581 | static int igb_get_i2c_data(void *data) |
582 | { | |
583 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
584 | struct e1000_hw *hw = &adapter->hw; | |
585 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
586 | ||
587 | return ((i2cctl & E1000_I2C_DATA_IN) != 0); | |
588 | } | |
589 | ||
b980ac18 JK |
590 | /** |
591 | * igb_set_i2c_data - Sets the I2C data bit | |
441fc6fd CW |
592 | * @data: pointer to hardware structure |
593 | * @state: I2C data value (0 or 1) to set | |
594 | * | |
595 | * Sets the I2C data bit | |
b980ac18 | 596 | **/ |
441fc6fd CW |
597 | static void igb_set_i2c_data(void *data, int state) |
598 | { | |
599 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
600 | struct e1000_hw *hw = &adapter->hw; | |
601 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
602 | ||
603 | if (state) | |
604 | i2cctl |= E1000_I2C_DATA_OUT; | |
605 | else | |
606 | i2cctl &= ~E1000_I2C_DATA_OUT; | |
607 | ||
608 | i2cctl &= ~E1000_I2C_DATA_OE_N; | |
609 | i2cctl |= E1000_I2C_CLK_OE_N; | |
610 | wr32(E1000_I2CPARAMS, i2cctl); | |
611 | wrfl(); | |
612 | ||
613 | } | |
614 | ||
b980ac18 JK |
615 | /** |
616 | * igb_set_i2c_clk - Sets the I2C SCL clock | |
441fc6fd CW |
617 | * @data: pointer to hardware structure |
618 | * @state: state to set clock | |
619 | * | |
620 | * Sets the I2C clock line to state | |
b980ac18 | 621 | **/ |
441fc6fd CW |
622 | static void igb_set_i2c_clk(void *data, int state) |
623 | { | |
624 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
625 | struct e1000_hw *hw = &adapter->hw; | |
626 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
627 | ||
628 | if (state) { | |
629 | i2cctl |= E1000_I2C_CLK_OUT; | |
630 | i2cctl &= ~E1000_I2C_CLK_OE_N; | |
631 | } else { | |
632 | i2cctl &= ~E1000_I2C_CLK_OUT; | |
633 | i2cctl &= ~E1000_I2C_CLK_OE_N; | |
634 | } | |
635 | wr32(E1000_I2CPARAMS, i2cctl); | |
636 | wrfl(); | |
637 | } | |
638 | ||
b980ac18 JK |
639 | /** |
640 | * igb_get_i2c_clk - Gets the I2C SCL clock state | |
441fc6fd CW |
641 | * @data: pointer to hardware structure |
642 | * | |
643 | * Gets the I2C clock state | |
b980ac18 | 644 | **/ |
441fc6fd CW |
645 | static int igb_get_i2c_clk(void *data) |
646 | { | |
647 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
648 | struct e1000_hw *hw = &adapter->hw; | |
649 | s32 i2cctl = rd32(E1000_I2CPARAMS); | |
650 | ||
651 | return ((i2cctl & E1000_I2C_CLK_IN) != 0); | |
652 | } | |
653 | ||
654 | static const struct i2c_algo_bit_data igb_i2c_algo = { | |
655 | .setsda = igb_set_i2c_data, | |
656 | .setscl = igb_set_i2c_clk, | |
657 | .getsda = igb_get_i2c_data, | |
658 | .getscl = igb_get_i2c_clk, | |
659 | .udelay = 5, | |
660 | .timeout = 20, | |
661 | }; | |
662 | ||
9d5c8243 | 663 | /** |
b980ac18 JK |
664 | * igb_get_hw_dev - return device |
665 | * @hw: pointer to hardware structure | |
666 | * | |
667 | * used by hardware layer to print debugging information | |
9d5c8243 | 668 | **/ |
c041076a | 669 | struct net_device *igb_get_hw_dev(struct e1000_hw *hw) |
9d5c8243 AK |
670 | { |
671 | struct igb_adapter *adapter = hw->back; | |
c041076a | 672 | return adapter->netdev; |
9d5c8243 | 673 | } |
38c845c7 | 674 | |
9d5c8243 | 675 | /** |
b980ac18 | 676 | * igb_init_module - Driver Registration Routine |
9d5c8243 | 677 | * |
b980ac18 JK |
678 | * igb_init_module is the first routine called when the driver is |
679 | * loaded. All it does is register with the PCI subsystem. | |
9d5c8243 AK |
680 | **/ |
681 | static int __init igb_init_module(void) | |
682 | { | |
683 | int ret; | |
876d2d6f | 684 | pr_info("%s - version %s\n", |
9d5c8243 AK |
685 | igb_driver_string, igb_driver_version); |
686 | ||
876d2d6f | 687 | pr_info("%s\n", igb_copyright); |
9d5c8243 | 688 | |
421e02f0 | 689 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
690 | dca_register_notify(&dca_notifier); |
691 | #endif | |
bbd98fe4 | 692 | ret = pci_register_driver(&igb_driver); |
9d5c8243 AK |
693 | return ret; |
694 | } | |
695 | ||
696 | module_init(igb_init_module); | |
697 | ||
698 | /** | |
b980ac18 | 699 | * igb_exit_module - Driver Exit Cleanup Routine |
9d5c8243 | 700 | * |
b980ac18 JK |
701 | * igb_exit_module is called just before the driver is removed |
702 | * from memory. | |
9d5c8243 AK |
703 | **/ |
704 | static void __exit igb_exit_module(void) | |
705 | { | |
421e02f0 | 706 | #ifdef CONFIG_IGB_DCA |
fe4506b6 JC |
707 | dca_unregister_notify(&dca_notifier); |
708 | #endif | |
9d5c8243 AK |
709 | pci_unregister_driver(&igb_driver); |
710 | } | |
711 | ||
712 | module_exit(igb_exit_module); | |
713 | ||
26bc19ec AD |
714 | #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) |
715 | /** | |
b980ac18 JK |
716 | * igb_cache_ring_register - Descriptor ring to register mapping |
717 | * @adapter: board private structure to initialize | |
26bc19ec | 718 | * |
b980ac18 JK |
719 | * Once we know the feature-set enabled for the device, we'll cache |
720 | * the register offset the descriptor ring is assigned to. | |
26bc19ec AD |
721 | **/ |
722 | static void igb_cache_ring_register(struct igb_adapter *adapter) | |
723 | { | |
ee1b9f06 | 724 | int i = 0, j = 0; |
047e0030 | 725 | u32 rbase_offset = adapter->vfs_allocated_count; |
26bc19ec AD |
726 | |
727 | switch (adapter->hw.mac.type) { | |
728 | case e1000_82576: | |
729 | /* The queues are allocated for virtualization such that VF 0 | |
730 | * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. | |
731 | * In order to avoid collision we start at the first free queue | |
732 | * and continue consuming queues in the same sequence | |
733 | */ | |
ee1b9f06 | 734 | if (adapter->vfs_allocated_count) { |
a99955fc | 735 | for (; i < adapter->rss_queues; i++) |
3025a446 | 736 | adapter->rx_ring[i]->reg_idx = rbase_offset + |
b980ac18 | 737 | Q_IDX_82576(i); |
ee1b9f06 | 738 | } |
26bc19ec | 739 | case e1000_82575: |
55cac248 | 740 | case e1000_82580: |
d2ba2ed8 | 741 | case e1000_i350: |
ceb5f13b | 742 | case e1000_i354: |
f96a8a0b CW |
743 | case e1000_i210: |
744 | case e1000_i211: | |
26bc19ec | 745 | default: |
ee1b9f06 | 746 | for (; i < adapter->num_rx_queues; i++) |
3025a446 | 747 | adapter->rx_ring[i]->reg_idx = rbase_offset + i; |
ee1b9f06 | 748 | for (; j < adapter->num_tx_queues; j++) |
3025a446 | 749 | adapter->tx_ring[j]->reg_idx = rbase_offset + j; |
26bc19ec AD |
750 | break; |
751 | } | |
752 | } | |
753 | ||
4be000c8 AD |
754 | /** |
755 | * igb_write_ivar - configure ivar for given MSI-X vector | |
756 | * @hw: pointer to the HW structure | |
757 | * @msix_vector: vector number we are allocating to a given ring | |
758 | * @index: row index of IVAR register to write within IVAR table | |
759 | * @offset: column offset of in IVAR, should be multiple of 8 | |
760 | * | |
761 | * This function is intended to handle the writing of the IVAR register | |
762 | * for adapters 82576 and newer. The IVAR table consists of 2 columns, | |
763 | * each containing an cause allocation for an Rx and Tx ring, and a | |
764 | * variable number of rows depending on the number of queues supported. | |
765 | **/ | |
766 | static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, | |
767 | int index, int offset) | |
768 | { | |
769 | u32 ivar = array_rd32(E1000_IVAR0, index); | |
770 | ||
771 | /* clear any bits that are currently set */ | |
772 | ivar &= ~((u32)0xFF << offset); | |
773 | ||
774 | /* write vector and valid bit */ | |
775 | ivar |= (msix_vector | E1000_IVAR_VALID) << offset; | |
776 | ||
777 | array_wr32(E1000_IVAR0, index, ivar); | |
778 | } | |
779 | ||
9d5c8243 | 780 | #define IGB_N0_QUEUE -1 |
047e0030 | 781 | static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) |
9d5c8243 | 782 | { |
047e0030 | 783 | struct igb_adapter *adapter = q_vector->adapter; |
9d5c8243 | 784 | struct e1000_hw *hw = &adapter->hw; |
047e0030 AD |
785 | int rx_queue = IGB_N0_QUEUE; |
786 | int tx_queue = IGB_N0_QUEUE; | |
4be000c8 | 787 | u32 msixbm = 0; |
047e0030 | 788 | |
0ba82994 AD |
789 | if (q_vector->rx.ring) |
790 | rx_queue = q_vector->rx.ring->reg_idx; | |
791 | if (q_vector->tx.ring) | |
792 | tx_queue = q_vector->tx.ring->reg_idx; | |
2d064c06 AD |
793 | |
794 | switch (hw->mac.type) { | |
795 | case e1000_82575: | |
9d5c8243 | 796 | /* The 82575 assigns vectors using a bitmask, which matches the |
b980ac18 JK |
797 | * bitmask for the EICR/EIMS/EIMC registers. To assign one |
798 | * or more queues to a vector, we write the appropriate bits | |
799 | * into the MSIXBM register for that vector. | |
800 | */ | |
047e0030 | 801 | if (rx_queue > IGB_N0_QUEUE) |
9d5c8243 | 802 | msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; |
047e0030 | 803 | if (tx_queue > IGB_N0_QUEUE) |
9d5c8243 | 804 | msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; |
feeb2721 AD |
805 | if (!adapter->msix_entries && msix_vector == 0) |
806 | msixbm |= E1000_EIMS_OTHER; | |
9d5c8243 | 807 | array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); |
047e0030 | 808 | q_vector->eims_value = msixbm; |
2d064c06 AD |
809 | break; |
810 | case e1000_82576: | |
b980ac18 | 811 | /* 82576 uses a table that essentially consists of 2 columns |
4be000c8 AD |
812 | * with 8 rows. The ordering is column-major so we use the |
813 | * lower 3 bits as the row index, and the 4th bit as the | |
814 | * column offset. | |
815 | */ | |
816 | if (rx_queue > IGB_N0_QUEUE) | |
817 | igb_write_ivar(hw, msix_vector, | |
818 | rx_queue & 0x7, | |
819 | (rx_queue & 0x8) << 1); | |
820 | if (tx_queue > IGB_N0_QUEUE) | |
821 | igb_write_ivar(hw, msix_vector, | |
822 | tx_queue & 0x7, | |
823 | ((tx_queue & 0x8) << 1) + 8); | |
047e0030 | 824 | q_vector->eims_value = 1 << msix_vector; |
2d064c06 | 825 | break; |
55cac248 | 826 | case e1000_82580: |
d2ba2ed8 | 827 | case e1000_i350: |
ceb5f13b | 828 | case e1000_i354: |
f96a8a0b CW |
829 | case e1000_i210: |
830 | case e1000_i211: | |
b980ac18 | 831 | /* On 82580 and newer adapters the scheme is similar to 82576 |
4be000c8 AD |
832 | * however instead of ordering column-major we have things |
833 | * ordered row-major. So we traverse the table by using | |
834 | * bit 0 as the column offset, and the remaining bits as the | |
835 | * row index. | |
836 | */ | |
837 | if (rx_queue > IGB_N0_QUEUE) | |
838 | igb_write_ivar(hw, msix_vector, | |
839 | rx_queue >> 1, | |
840 | (rx_queue & 0x1) << 4); | |
841 | if (tx_queue > IGB_N0_QUEUE) | |
842 | igb_write_ivar(hw, msix_vector, | |
843 | tx_queue >> 1, | |
844 | ((tx_queue & 0x1) << 4) + 8); | |
55cac248 AD |
845 | q_vector->eims_value = 1 << msix_vector; |
846 | break; | |
2d064c06 AD |
847 | default: |
848 | BUG(); | |
849 | break; | |
850 | } | |
26b39276 AD |
851 | |
852 | /* add q_vector eims value to global eims_enable_mask */ | |
853 | adapter->eims_enable_mask |= q_vector->eims_value; | |
854 | ||
855 | /* configure q_vector to set itr on first interrupt */ | |
856 | q_vector->set_itr = 1; | |
9d5c8243 AK |
857 | } |
858 | ||
859 | /** | |
b980ac18 JK |
860 | * igb_configure_msix - Configure MSI-X hardware |
861 | * @adapter: board private structure to initialize | |
9d5c8243 | 862 | * |
b980ac18 JK |
863 | * igb_configure_msix sets up the hardware to properly |
864 | * generate MSI-X interrupts. | |
9d5c8243 AK |
865 | **/ |
866 | static void igb_configure_msix(struct igb_adapter *adapter) | |
867 | { | |
868 | u32 tmp; | |
869 | int i, vector = 0; | |
870 | struct e1000_hw *hw = &adapter->hw; | |
871 | ||
872 | adapter->eims_enable_mask = 0; | |
9d5c8243 AK |
873 | |
874 | /* set vector for other causes, i.e. link changes */ | |
2d064c06 AD |
875 | switch (hw->mac.type) { |
876 | case e1000_82575: | |
9d5c8243 AK |
877 | tmp = rd32(E1000_CTRL_EXT); |
878 | /* enable MSI-X PBA support*/ | |
879 | tmp |= E1000_CTRL_EXT_PBA_CLR; | |
880 | ||
881 | /* Auto-Mask interrupts upon ICR read. */ | |
882 | tmp |= E1000_CTRL_EXT_EIAME; | |
883 | tmp |= E1000_CTRL_EXT_IRCA; | |
884 | ||
885 | wr32(E1000_CTRL_EXT, tmp); | |
047e0030 AD |
886 | |
887 | /* enable msix_other interrupt */ | |
b980ac18 | 888 | array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); |
844290e5 | 889 | adapter->eims_other = E1000_EIMS_OTHER; |
9d5c8243 | 890 | |
2d064c06 AD |
891 | break; |
892 | ||
893 | case e1000_82576: | |
55cac248 | 894 | case e1000_82580: |
d2ba2ed8 | 895 | case e1000_i350: |
ceb5f13b | 896 | case e1000_i354: |
f96a8a0b CW |
897 | case e1000_i210: |
898 | case e1000_i211: | |
047e0030 | 899 | /* Turn on MSI-X capability first, or our settings |
b980ac18 JK |
900 | * won't stick. And it will take days to debug. |
901 | */ | |
047e0030 | 902 | wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | |
b980ac18 JK |
903 | E1000_GPIE_PBA | E1000_GPIE_EIAME | |
904 | E1000_GPIE_NSICR); | |
047e0030 AD |
905 | |
906 | /* enable msix_other interrupt */ | |
907 | adapter->eims_other = 1 << vector; | |
2d064c06 | 908 | tmp = (vector++ | E1000_IVAR_VALID) << 8; |
2d064c06 | 909 | |
047e0030 | 910 | wr32(E1000_IVAR_MISC, tmp); |
2d064c06 AD |
911 | break; |
912 | default: | |
913 | /* do nothing, since nothing else supports MSI-X */ | |
914 | break; | |
915 | } /* switch (hw->mac.type) */ | |
047e0030 AD |
916 | |
917 | adapter->eims_enable_mask |= adapter->eims_other; | |
918 | ||
26b39276 AD |
919 | for (i = 0; i < adapter->num_q_vectors; i++) |
920 | igb_assign_vector(adapter->q_vector[i], vector++); | |
047e0030 | 921 | |
9d5c8243 AK |
922 | wrfl(); |
923 | } | |
924 | ||
925 | /** | |
b980ac18 JK |
926 | * igb_request_msix - Initialize MSI-X interrupts |
927 | * @adapter: board private structure to initialize | |
9d5c8243 | 928 | * |
b980ac18 JK |
929 | * igb_request_msix allocates MSI-X vectors and requests interrupts from the |
930 | * kernel. | |
9d5c8243 AK |
931 | **/ |
932 | static int igb_request_msix(struct igb_adapter *adapter) | |
933 | { | |
934 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 935 | struct e1000_hw *hw = &adapter->hw; |
52285b76 | 936 | int i, err = 0, vector = 0, free_vector = 0; |
9d5c8243 | 937 | |
047e0030 | 938 | err = request_irq(adapter->msix_entries[vector].vector, |
b980ac18 | 939 | igb_msix_other, 0, netdev->name, adapter); |
047e0030 | 940 | if (err) |
52285b76 | 941 | goto err_out; |
047e0030 AD |
942 | |
943 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
944 | struct igb_q_vector *q_vector = adapter->q_vector[i]; | |
945 | ||
52285b76 SA |
946 | vector++; |
947 | ||
047e0030 AD |
948 | q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); |
949 | ||
0ba82994 | 950 | if (q_vector->rx.ring && q_vector->tx.ring) |
047e0030 | 951 | sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, |
0ba82994 AD |
952 | q_vector->rx.ring->queue_index); |
953 | else if (q_vector->tx.ring) | |
047e0030 | 954 | sprintf(q_vector->name, "%s-tx-%u", netdev->name, |
0ba82994 AD |
955 | q_vector->tx.ring->queue_index); |
956 | else if (q_vector->rx.ring) | |
047e0030 | 957 | sprintf(q_vector->name, "%s-rx-%u", netdev->name, |
0ba82994 | 958 | q_vector->rx.ring->queue_index); |
9d5c8243 | 959 | else |
047e0030 AD |
960 | sprintf(q_vector->name, "%s-unused", netdev->name); |
961 | ||
9d5c8243 | 962 | err = request_irq(adapter->msix_entries[vector].vector, |
b980ac18 JK |
963 | igb_msix_ring, 0, q_vector->name, |
964 | q_vector); | |
9d5c8243 | 965 | if (err) |
52285b76 | 966 | goto err_free; |
9d5c8243 AK |
967 | } |
968 | ||
9d5c8243 AK |
969 | igb_configure_msix(adapter); |
970 | return 0; | |
52285b76 SA |
971 | |
972 | err_free: | |
973 | /* free already assigned IRQs */ | |
974 | free_irq(adapter->msix_entries[free_vector++].vector, adapter); | |
975 | ||
976 | vector--; | |
977 | for (i = 0; i < vector; i++) { | |
978 | free_irq(adapter->msix_entries[free_vector++].vector, | |
979 | adapter->q_vector[i]); | |
980 | } | |
981 | err_out: | |
9d5c8243 AK |
982 | return err; |
983 | } | |
984 | ||
985 | static void igb_reset_interrupt_capability(struct igb_adapter *adapter) | |
986 | { | |
987 | if (adapter->msix_entries) { | |
988 | pci_disable_msix(adapter->pdev); | |
989 | kfree(adapter->msix_entries); | |
990 | adapter->msix_entries = NULL; | |
047e0030 | 991 | } else if (adapter->flags & IGB_FLAG_HAS_MSI) { |
9d5c8243 | 992 | pci_disable_msi(adapter->pdev); |
047e0030 | 993 | } |
9d5c8243 AK |
994 | } |
995 | ||
5536d210 | 996 | /** |
b980ac18 JK |
997 | * igb_free_q_vector - Free memory allocated for specific interrupt vector |
998 | * @adapter: board private structure to initialize | |
999 | * @v_idx: Index of vector to be freed | |
5536d210 | 1000 | * |
b980ac18 JK |
1001 | * This function frees the memory allocated to the q_vector. In addition if |
1002 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
1003 | * to freeing the q_vector. | |
5536d210 AD |
1004 | **/ |
1005 | static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) | |
1006 | { | |
1007 | struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; | |
1008 | ||
1009 | if (q_vector->tx.ring) | |
1010 | adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; | |
1011 | ||
1012 | if (q_vector->rx.ring) | |
1013 | adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; | |
1014 | ||
1015 | adapter->q_vector[v_idx] = NULL; | |
1016 | netif_napi_del(&q_vector->napi); | |
1017 | ||
7f90128e | 1018 | /* igb_get_stats64() might access the rings on this vector, |
5536d210 AD |
1019 | * we must wait a grace period before freeing it. |
1020 | */ | |
1021 | kfree_rcu(q_vector, rcu); | |
1022 | } | |
1023 | ||
047e0030 | 1024 | /** |
b980ac18 JK |
1025 | * igb_free_q_vectors - Free memory allocated for interrupt vectors |
1026 | * @adapter: board private structure to initialize | |
047e0030 | 1027 | * |
b980ac18 JK |
1028 | * This function frees the memory allocated to the q_vectors. In addition if |
1029 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
1030 | * to freeing the q_vector. | |
047e0030 AD |
1031 | **/ |
1032 | static void igb_free_q_vectors(struct igb_adapter *adapter) | |
1033 | { | |
5536d210 AD |
1034 | int v_idx = adapter->num_q_vectors; |
1035 | ||
1036 | adapter->num_tx_queues = 0; | |
1037 | adapter->num_rx_queues = 0; | |
047e0030 | 1038 | adapter->num_q_vectors = 0; |
5536d210 AD |
1039 | |
1040 | while (v_idx--) | |
1041 | igb_free_q_vector(adapter, v_idx); | |
047e0030 AD |
1042 | } |
1043 | ||
1044 | /** | |
b980ac18 JK |
1045 | * igb_clear_interrupt_scheme - reset the device to a state of no interrupts |
1046 | * @adapter: board private structure to initialize | |
047e0030 | 1047 | * |
b980ac18 JK |
1048 | * This function resets the device so that it has 0 Rx queues, Tx queues, and |
1049 | * MSI-X interrupts allocated. | |
047e0030 AD |
1050 | */ |
1051 | static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) | |
1052 | { | |
047e0030 AD |
1053 | igb_free_q_vectors(adapter); |
1054 | igb_reset_interrupt_capability(adapter); | |
1055 | } | |
9d5c8243 AK |
1056 | |
1057 | /** | |
b980ac18 JK |
1058 | * igb_set_interrupt_capability - set MSI or MSI-X if supported |
1059 | * @adapter: board private structure to initialize | |
1060 | * @msix: boolean value of MSIX capability | |
9d5c8243 | 1061 | * |
b980ac18 JK |
1062 | * Attempt to configure interrupts using the best available |
1063 | * capabilities of the hardware and kernel. | |
9d5c8243 | 1064 | **/ |
53c7d064 | 1065 | static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) |
9d5c8243 AK |
1066 | { |
1067 | int err; | |
1068 | int numvecs, i; | |
1069 | ||
53c7d064 SA |
1070 | if (!msix) |
1071 | goto msi_only; | |
1072 | ||
83b7180d | 1073 | /* Number of supported queues. */ |
a99955fc | 1074 | adapter->num_rx_queues = adapter->rss_queues; |
5fa8517f GR |
1075 | if (adapter->vfs_allocated_count) |
1076 | adapter->num_tx_queues = 1; | |
1077 | else | |
1078 | adapter->num_tx_queues = adapter->rss_queues; | |
83b7180d | 1079 | |
b980ac18 | 1080 | /* start with one vector for every Rx queue */ |
047e0030 AD |
1081 | numvecs = adapter->num_rx_queues; |
1082 | ||
b980ac18 | 1083 | /* if Tx handler is separate add 1 for every Tx queue */ |
a99955fc AD |
1084 | if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) |
1085 | numvecs += adapter->num_tx_queues; | |
047e0030 AD |
1086 | |
1087 | /* store the number of vectors reserved for queues */ | |
1088 | adapter->num_q_vectors = numvecs; | |
1089 | ||
1090 | /* add 1 vector for link status interrupts */ | |
1091 | numvecs++; | |
9d5c8243 AK |
1092 | adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), |
1093 | GFP_KERNEL); | |
f96a8a0b | 1094 | |
9d5c8243 AK |
1095 | if (!adapter->msix_entries) |
1096 | goto msi_only; | |
1097 | ||
1098 | for (i = 0; i < numvecs; i++) | |
1099 | adapter->msix_entries[i].entry = i; | |
1100 | ||
1101 | err = pci_enable_msix(adapter->pdev, | |
1102 | adapter->msix_entries, | |
1103 | numvecs); | |
1104 | if (err == 0) | |
0c2cc02e | 1105 | return; |
9d5c8243 AK |
1106 | |
1107 | igb_reset_interrupt_capability(adapter); | |
1108 | ||
1109 | /* If we can't do MSI-X, try MSI */ | |
1110 | msi_only: | |
2a3abf6d AD |
1111 | #ifdef CONFIG_PCI_IOV |
1112 | /* disable SR-IOV for non MSI-X configurations */ | |
1113 | if (adapter->vf_data) { | |
1114 | struct e1000_hw *hw = &adapter->hw; | |
1115 | /* disable iov and allow time for transactions to clear */ | |
1116 | pci_disable_sriov(adapter->pdev); | |
1117 | msleep(500); | |
1118 | ||
1119 | kfree(adapter->vf_data); | |
1120 | adapter->vf_data = NULL; | |
1121 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
945a5151 | 1122 | wrfl(); |
2a3abf6d AD |
1123 | msleep(100); |
1124 | dev_info(&adapter->pdev->dev, "IOV Disabled\n"); | |
1125 | } | |
1126 | #endif | |
4fc82adf | 1127 | adapter->vfs_allocated_count = 0; |
a99955fc | 1128 | adapter->rss_queues = 1; |
4fc82adf | 1129 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; |
9d5c8243 | 1130 | adapter->num_rx_queues = 1; |
661086df | 1131 | adapter->num_tx_queues = 1; |
047e0030 | 1132 | adapter->num_q_vectors = 1; |
9d5c8243 | 1133 | if (!pci_enable_msi(adapter->pdev)) |
7dfc16fa | 1134 | adapter->flags |= IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1135 | } |
1136 | ||
5536d210 AD |
1137 | static void igb_add_ring(struct igb_ring *ring, |
1138 | struct igb_ring_container *head) | |
1139 | { | |
1140 | head->ring = ring; | |
1141 | head->count++; | |
1142 | } | |
1143 | ||
047e0030 | 1144 | /** |
b980ac18 JK |
1145 | * igb_alloc_q_vector - Allocate memory for a single interrupt vector |
1146 | * @adapter: board private structure to initialize | |
1147 | * @v_count: q_vectors allocated on adapter, used for ring interleaving | |
1148 | * @v_idx: index of vector in adapter struct | |
1149 | * @txr_count: total number of Tx rings to allocate | |
1150 | * @txr_idx: index of first Tx ring to allocate | |
1151 | * @rxr_count: total number of Rx rings to allocate | |
1152 | * @rxr_idx: index of first Rx ring to allocate | |
047e0030 | 1153 | * |
b980ac18 | 1154 | * We allocate one q_vector. If allocation fails we return -ENOMEM. |
047e0030 | 1155 | **/ |
5536d210 AD |
1156 | static int igb_alloc_q_vector(struct igb_adapter *adapter, |
1157 | int v_count, int v_idx, | |
1158 | int txr_count, int txr_idx, | |
1159 | int rxr_count, int rxr_idx) | |
047e0030 AD |
1160 | { |
1161 | struct igb_q_vector *q_vector; | |
5536d210 AD |
1162 | struct igb_ring *ring; |
1163 | int ring_count, size; | |
047e0030 | 1164 | |
5536d210 AD |
1165 | /* igb only supports 1 Tx and/or 1 Rx queue per vector */ |
1166 | if (txr_count > 1 || rxr_count > 1) | |
1167 | return -ENOMEM; | |
1168 | ||
1169 | ring_count = txr_count + rxr_count; | |
1170 | size = sizeof(struct igb_q_vector) + | |
1171 | (sizeof(struct igb_ring) * ring_count); | |
1172 | ||
1173 | /* allocate q_vector and rings */ | |
1174 | q_vector = kzalloc(size, GFP_KERNEL); | |
1175 | if (!q_vector) | |
1176 | return -ENOMEM; | |
1177 | ||
1178 | /* initialize NAPI */ | |
1179 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
1180 | igb_poll, 64); | |
1181 | ||
1182 | /* tie q_vector and adapter together */ | |
1183 | adapter->q_vector[v_idx] = q_vector; | |
1184 | q_vector->adapter = adapter; | |
1185 | ||
1186 | /* initialize work limits */ | |
1187 | q_vector->tx.work_limit = adapter->tx_work_limit; | |
1188 | ||
1189 | /* initialize ITR configuration */ | |
1190 | q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); | |
1191 | q_vector->itr_val = IGB_START_ITR; | |
1192 | ||
1193 | /* initialize pointer to rings */ | |
1194 | ring = q_vector->ring; | |
1195 | ||
4e227667 AD |
1196 | /* intialize ITR */ |
1197 | if (rxr_count) { | |
1198 | /* rx or rx/tx vector */ | |
1199 | if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) | |
1200 | q_vector->itr_val = adapter->rx_itr_setting; | |
1201 | } else { | |
1202 | /* tx only vector */ | |
1203 | if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) | |
1204 | q_vector->itr_val = adapter->tx_itr_setting; | |
1205 | } | |
1206 | ||
5536d210 AD |
1207 | if (txr_count) { |
1208 | /* assign generic ring traits */ | |
1209 | ring->dev = &adapter->pdev->dev; | |
1210 | ring->netdev = adapter->netdev; | |
1211 | ||
1212 | /* configure backlink on ring */ | |
1213 | ring->q_vector = q_vector; | |
1214 | ||
1215 | /* update q_vector Tx values */ | |
1216 | igb_add_ring(ring, &q_vector->tx); | |
1217 | ||
1218 | /* For 82575, context index must be unique per ring. */ | |
1219 | if (adapter->hw.mac.type == e1000_82575) | |
1220 | set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); | |
1221 | ||
1222 | /* apply Tx specific ring traits */ | |
1223 | ring->count = adapter->tx_ring_count; | |
1224 | ring->queue_index = txr_idx; | |
1225 | ||
1226 | /* assign ring to adapter */ | |
1227 | adapter->tx_ring[txr_idx] = ring; | |
1228 | ||
1229 | /* push pointer to next ring */ | |
1230 | ring++; | |
047e0030 | 1231 | } |
81c2fc22 | 1232 | |
5536d210 AD |
1233 | if (rxr_count) { |
1234 | /* assign generic ring traits */ | |
1235 | ring->dev = &adapter->pdev->dev; | |
1236 | ring->netdev = adapter->netdev; | |
047e0030 | 1237 | |
5536d210 AD |
1238 | /* configure backlink on ring */ |
1239 | ring->q_vector = q_vector; | |
047e0030 | 1240 | |
5536d210 AD |
1241 | /* update q_vector Rx values */ |
1242 | igb_add_ring(ring, &q_vector->rx); | |
047e0030 | 1243 | |
5536d210 AD |
1244 | /* set flag indicating ring supports SCTP checksum offload */ |
1245 | if (adapter->hw.mac.type >= e1000_82576) | |
1246 | set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); | |
047e0030 | 1247 | |
ceb5f13b CW |
1248 | /* |
1249 | * On i350, i354, i210, and i211, loopback VLAN packets | |
5536d210 | 1250 | * have the tag byte-swapped. |
b980ac18 | 1251 | */ |
5536d210 AD |
1252 | if (adapter->hw.mac.type >= e1000_i350) |
1253 | set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); | |
047e0030 | 1254 | |
5536d210 AD |
1255 | /* apply Rx specific ring traits */ |
1256 | ring->count = adapter->rx_ring_count; | |
1257 | ring->queue_index = rxr_idx; | |
1258 | ||
1259 | /* assign ring to adapter */ | |
1260 | adapter->rx_ring[rxr_idx] = ring; | |
1261 | } | |
1262 | ||
1263 | return 0; | |
047e0030 AD |
1264 | } |
1265 | ||
5536d210 | 1266 | |
047e0030 | 1267 | /** |
b980ac18 JK |
1268 | * igb_alloc_q_vectors - Allocate memory for interrupt vectors |
1269 | * @adapter: board private structure to initialize | |
047e0030 | 1270 | * |
b980ac18 JK |
1271 | * We allocate one q_vector per queue interrupt. If allocation fails we |
1272 | * return -ENOMEM. | |
047e0030 | 1273 | **/ |
5536d210 | 1274 | static int igb_alloc_q_vectors(struct igb_adapter *adapter) |
047e0030 | 1275 | { |
5536d210 AD |
1276 | int q_vectors = adapter->num_q_vectors; |
1277 | int rxr_remaining = adapter->num_rx_queues; | |
1278 | int txr_remaining = adapter->num_tx_queues; | |
1279 | int rxr_idx = 0, txr_idx = 0, v_idx = 0; | |
1280 | int err; | |
047e0030 | 1281 | |
5536d210 AD |
1282 | if (q_vectors >= (rxr_remaining + txr_remaining)) { |
1283 | for (; rxr_remaining; v_idx++) { | |
1284 | err = igb_alloc_q_vector(adapter, q_vectors, v_idx, | |
1285 | 0, 0, 1, rxr_idx); | |
047e0030 | 1286 | |
5536d210 AD |
1287 | if (err) |
1288 | goto err_out; | |
1289 | ||
1290 | /* update counts and index */ | |
1291 | rxr_remaining--; | |
1292 | rxr_idx++; | |
047e0030 | 1293 | } |
047e0030 | 1294 | } |
5536d210 AD |
1295 | |
1296 | for (; v_idx < q_vectors; v_idx++) { | |
1297 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); | |
1298 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); | |
1299 | err = igb_alloc_q_vector(adapter, q_vectors, v_idx, | |
1300 | tqpv, txr_idx, rqpv, rxr_idx); | |
1301 | ||
1302 | if (err) | |
1303 | goto err_out; | |
1304 | ||
1305 | /* update counts and index */ | |
1306 | rxr_remaining -= rqpv; | |
1307 | txr_remaining -= tqpv; | |
1308 | rxr_idx++; | |
1309 | txr_idx++; | |
1310 | } | |
1311 | ||
047e0030 | 1312 | return 0; |
5536d210 AD |
1313 | |
1314 | err_out: | |
1315 | adapter->num_tx_queues = 0; | |
1316 | adapter->num_rx_queues = 0; | |
1317 | adapter->num_q_vectors = 0; | |
1318 | ||
1319 | while (v_idx--) | |
1320 | igb_free_q_vector(adapter, v_idx); | |
1321 | ||
1322 | return -ENOMEM; | |
047e0030 AD |
1323 | } |
1324 | ||
1325 | /** | |
b980ac18 JK |
1326 | * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors |
1327 | * @adapter: board private structure to initialize | |
1328 | * @msix: boolean value of MSIX capability | |
047e0030 | 1329 | * |
b980ac18 | 1330 | * This function initializes the interrupts and allocates all of the queues. |
047e0030 | 1331 | **/ |
53c7d064 | 1332 | static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) |
047e0030 AD |
1333 | { |
1334 | struct pci_dev *pdev = adapter->pdev; | |
1335 | int err; | |
1336 | ||
53c7d064 | 1337 | igb_set_interrupt_capability(adapter, msix); |
047e0030 AD |
1338 | |
1339 | err = igb_alloc_q_vectors(adapter); | |
1340 | if (err) { | |
1341 | dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); | |
1342 | goto err_alloc_q_vectors; | |
1343 | } | |
1344 | ||
5536d210 | 1345 | igb_cache_ring_register(adapter); |
047e0030 AD |
1346 | |
1347 | return 0; | |
5536d210 | 1348 | |
047e0030 AD |
1349 | err_alloc_q_vectors: |
1350 | igb_reset_interrupt_capability(adapter); | |
1351 | return err; | |
1352 | } | |
1353 | ||
9d5c8243 | 1354 | /** |
b980ac18 JK |
1355 | * igb_request_irq - initialize interrupts |
1356 | * @adapter: board private structure to initialize | |
9d5c8243 | 1357 | * |
b980ac18 JK |
1358 | * Attempts to configure interrupts using the best available |
1359 | * capabilities of the hardware and kernel. | |
9d5c8243 AK |
1360 | **/ |
1361 | static int igb_request_irq(struct igb_adapter *adapter) | |
1362 | { | |
1363 | struct net_device *netdev = adapter->netdev; | |
047e0030 | 1364 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
1365 | int err = 0; |
1366 | ||
1367 | if (adapter->msix_entries) { | |
1368 | err = igb_request_msix(adapter); | |
844290e5 | 1369 | if (!err) |
9d5c8243 | 1370 | goto request_done; |
9d5c8243 | 1371 | /* fall back to MSI */ |
5536d210 AD |
1372 | igb_free_all_tx_resources(adapter); |
1373 | igb_free_all_rx_resources(adapter); | |
53c7d064 | 1374 | |
047e0030 | 1375 | igb_clear_interrupt_scheme(adapter); |
53c7d064 SA |
1376 | err = igb_init_interrupt_scheme(adapter, false); |
1377 | if (err) | |
047e0030 | 1378 | goto request_done; |
53c7d064 | 1379 | |
047e0030 AD |
1380 | igb_setup_all_tx_resources(adapter); |
1381 | igb_setup_all_rx_resources(adapter); | |
53c7d064 | 1382 | igb_configure(adapter); |
9d5c8243 | 1383 | } |
844290e5 | 1384 | |
c74d588e AD |
1385 | igb_assign_vector(adapter->q_vector[0], 0); |
1386 | ||
7dfc16fa | 1387 | if (adapter->flags & IGB_FLAG_HAS_MSI) { |
c74d588e | 1388 | err = request_irq(pdev->irq, igb_intr_msi, 0, |
047e0030 | 1389 | netdev->name, adapter); |
9d5c8243 AK |
1390 | if (!err) |
1391 | goto request_done; | |
047e0030 | 1392 | |
9d5c8243 AK |
1393 | /* fall back to legacy interrupts */ |
1394 | igb_reset_interrupt_capability(adapter); | |
7dfc16fa | 1395 | adapter->flags &= ~IGB_FLAG_HAS_MSI; |
9d5c8243 AK |
1396 | } |
1397 | ||
c74d588e | 1398 | err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, |
047e0030 | 1399 | netdev->name, adapter); |
9d5c8243 | 1400 | |
6cb5e577 | 1401 | if (err) |
c74d588e | 1402 | dev_err(&pdev->dev, "Error %d getting interrupt\n", |
9d5c8243 | 1403 | err); |
9d5c8243 AK |
1404 | |
1405 | request_done: | |
1406 | return err; | |
1407 | } | |
1408 | ||
1409 | static void igb_free_irq(struct igb_adapter *adapter) | |
1410 | { | |
9d5c8243 AK |
1411 | if (adapter->msix_entries) { |
1412 | int vector = 0, i; | |
1413 | ||
047e0030 | 1414 | free_irq(adapter->msix_entries[vector++].vector, adapter); |
9d5c8243 | 1415 | |
0d1ae7f4 | 1416 | for (i = 0; i < adapter->num_q_vectors; i++) |
047e0030 | 1417 | free_irq(adapter->msix_entries[vector++].vector, |
0d1ae7f4 | 1418 | adapter->q_vector[i]); |
047e0030 AD |
1419 | } else { |
1420 | free_irq(adapter->pdev->irq, adapter); | |
9d5c8243 | 1421 | } |
9d5c8243 AK |
1422 | } |
1423 | ||
1424 | /** | |
b980ac18 JK |
1425 | * igb_irq_disable - Mask off interrupt generation on the NIC |
1426 | * @adapter: board private structure | |
9d5c8243 AK |
1427 | **/ |
1428 | static void igb_irq_disable(struct igb_adapter *adapter) | |
1429 | { | |
1430 | struct e1000_hw *hw = &adapter->hw; | |
1431 | ||
b980ac18 | 1432 | /* we need to be careful when disabling interrupts. The VFs are also |
25568a53 AD |
1433 | * mapped into these registers and so clearing the bits can cause |
1434 | * issues on the VF drivers so we only need to clear what we set | |
1435 | */ | |
9d5c8243 | 1436 | if (adapter->msix_entries) { |
2dfd1212 AD |
1437 | u32 regval = rd32(E1000_EIAM); |
1438 | wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); | |
1439 | wr32(E1000_EIMC, adapter->eims_enable_mask); | |
1440 | regval = rd32(E1000_EIAC); | |
1441 | wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); | |
9d5c8243 | 1442 | } |
844290e5 PW |
1443 | |
1444 | wr32(E1000_IAM, 0); | |
9d5c8243 AK |
1445 | wr32(E1000_IMC, ~0); |
1446 | wrfl(); | |
81a61859 ET |
1447 | if (adapter->msix_entries) { |
1448 | int i; | |
1449 | for (i = 0; i < adapter->num_q_vectors; i++) | |
1450 | synchronize_irq(adapter->msix_entries[i].vector); | |
1451 | } else { | |
1452 | synchronize_irq(adapter->pdev->irq); | |
1453 | } | |
9d5c8243 AK |
1454 | } |
1455 | ||
1456 | /** | |
b980ac18 JK |
1457 | * igb_irq_enable - Enable default interrupt generation settings |
1458 | * @adapter: board private structure | |
9d5c8243 AK |
1459 | **/ |
1460 | static void igb_irq_enable(struct igb_adapter *adapter) | |
1461 | { | |
1462 | struct e1000_hw *hw = &adapter->hw; | |
1463 | ||
1464 | if (adapter->msix_entries) { | |
06218a8d | 1465 | u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; |
2dfd1212 AD |
1466 | u32 regval = rd32(E1000_EIAC); |
1467 | wr32(E1000_EIAC, regval | adapter->eims_enable_mask); | |
1468 | regval = rd32(E1000_EIAM); | |
1469 | wr32(E1000_EIAM, regval | adapter->eims_enable_mask); | |
844290e5 | 1470 | wr32(E1000_EIMS, adapter->eims_enable_mask); |
25568a53 | 1471 | if (adapter->vfs_allocated_count) { |
4ae196df | 1472 | wr32(E1000_MBVFIMR, 0xFF); |
25568a53 AD |
1473 | ims |= E1000_IMS_VMMB; |
1474 | } | |
1475 | wr32(E1000_IMS, ims); | |
844290e5 | 1476 | } else { |
55cac248 AD |
1477 | wr32(E1000_IMS, IMS_ENABLE_MASK | |
1478 | E1000_IMS_DRSTA); | |
1479 | wr32(E1000_IAM, IMS_ENABLE_MASK | | |
1480 | E1000_IMS_DRSTA); | |
844290e5 | 1481 | } |
9d5c8243 AK |
1482 | } |
1483 | ||
1484 | static void igb_update_mng_vlan(struct igb_adapter *adapter) | |
1485 | { | |
51466239 | 1486 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1487 | u16 vid = adapter->hw.mng_cookie.vlan_id; |
1488 | u16 old_vid = adapter->mng_vlan_id; | |
51466239 AD |
1489 | |
1490 | if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { | |
1491 | /* add VID to filter table */ | |
1492 | igb_vfta_set(hw, vid, true); | |
1493 | adapter->mng_vlan_id = vid; | |
1494 | } else { | |
1495 | adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; | |
1496 | } | |
1497 | ||
1498 | if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && | |
1499 | (vid != old_vid) && | |
b2cb09b1 | 1500 | !test_bit(old_vid, adapter->active_vlans)) { |
51466239 AD |
1501 | /* remove VID from filter table */ |
1502 | igb_vfta_set(hw, old_vid, false); | |
9d5c8243 AK |
1503 | } |
1504 | } | |
1505 | ||
1506 | /** | |
b980ac18 JK |
1507 | * igb_release_hw_control - release control of the h/w to f/w |
1508 | * @adapter: address of board private structure | |
9d5c8243 | 1509 | * |
b980ac18 JK |
1510 | * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. |
1511 | * For ASF and Pass Through versions of f/w this means that the | |
1512 | * driver is no longer loaded. | |
9d5c8243 AK |
1513 | **/ |
1514 | static void igb_release_hw_control(struct igb_adapter *adapter) | |
1515 | { | |
1516 | struct e1000_hw *hw = &adapter->hw; | |
1517 | u32 ctrl_ext; | |
1518 | ||
1519 | /* Let firmware take over control of h/w */ | |
1520 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1521 | wr32(E1000_CTRL_EXT, | |
1522 | ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); | |
1523 | } | |
1524 | ||
9d5c8243 | 1525 | /** |
b980ac18 JK |
1526 | * igb_get_hw_control - get control of the h/w from f/w |
1527 | * @adapter: address of board private structure | |
9d5c8243 | 1528 | * |
b980ac18 JK |
1529 | * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. |
1530 | * For ASF and Pass Through versions of f/w this means that | |
1531 | * the driver is loaded. | |
9d5c8243 AK |
1532 | **/ |
1533 | static void igb_get_hw_control(struct igb_adapter *adapter) | |
1534 | { | |
1535 | struct e1000_hw *hw = &adapter->hw; | |
1536 | u32 ctrl_ext; | |
1537 | ||
1538 | /* Let firmware know the driver has taken over */ | |
1539 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
1540 | wr32(E1000_CTRL_EXT, | |
1541 | ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); | |
1542 | } | |
1543 | ||
9d5c8243 | 1544 | /** |
b980ac18 JK |
1545 | * igb_configure - configure the hardware for RX and TX |
1546 | * @adapter: private board structure | |
9d5c8243 AK |
1547 | **/ |
1548 | static void igb_configure(struct igb_adapter *adapter) | |
1549 | { | |
1550 | struct net_device *netdev = adapter->netdev; | |
1551 | int i; | |
1552 | ||
1553 | igb_get_hw_control(adapter); | |
ff41f8dc | 1554 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
1555 | |
1556 | igb_restore_vlan(adapter); | |
9d5c8243 | 1557 | |
85b430b4 | 1558 | igb_setup_tctl(adapter); |
06cf2666 | 1559 | igb_setup_mrqc(adapter); |
9d5c8243 | 1560 | igb_setup_rctl(adapter); |
85b430b4 AD |
1561 | |
1562 | igb_configure_tx(adapter); | |
9d5c8243 | 1563 | igb_configure_rx(adapter); |
662d7205 AD |
1564 | |
1565 | igb_rx_fifo_flush_82575(&adapter->hw); | |
1566 | ||
c493ea45 | 1567 | /* call igb_desc_unused which always leaves |
9d5c8243 | 1568 | * at least 1 descriptor unused to make sure |
b980ac18 JK |
1569 | * next_to_use != next_to_clean |
1570 | */ | |
9d5c8243 | 1571 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3025a446 | 1572 | struct igb_ring *ring = adapter->rx_ring[i]; |
cd392f5c | 1573 | igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); |
9d5c8243 | 1574 | } |
9d5c8243 AK |
1575 | } |
1576 | ||
88a268c1 | 1577 | /** |
b980ac18 JK |
1578 | * igb_power_up_link - Power up the phy/serdes link |
1579 | * @adapter: address of board private structure | |
88a268c1 NN |
1580 | **/ |
1581 | void igb_power_up_link(struct igb_adapter *adapter) | |
1582 | { | |
76886596 AA |
1583 | igb_reset_phy(&adapter->hw); |
1584 | ||
88a268c1 NN |
1585 | if (adapter->hw.phy.media_type == e1000_media_type_copper) |
1586 | igb_power_up_phy_copper(&adapter->hw); | |
1587 | else | |
1588 | igb_power_up_serdes_link_82575(&adapter->hw); | |
1589 | } | |
1590 | ||
1591 | /** | |
b980ac18 JK |
1592 | * igb_power_down_link - Power down the phy/serdes link |
1593 | * @adapter: address of board private structure | |
88a268c1 NN |
1594 | */ |
1595 | static void igb_power_down_link(struct igb_adapter *adapter) | |
1596 | { | |
1597 | if (adapter->hw.phy.media_type == e1000_media_type_copper) | |
1598 | igb_power_down_phy_copper_82575(&adapter->hw); | |
1599 | else | |
1600 | igb_shutdown_serdes_link_82575(&adapter->hw); | |
1601 | } | |
9d5c8243 AK |
1602 | |
1603 | /** | |
b980ac18 JK |
1604 | * igb_up - Open the interface and prepare it to handle traffic |
1605 | * @adapter: board private structure | |
9d5c8243 | 1606 | **/ |
9d5c8243 AK |
1607 | int igb_up(struct igb_adapter *adapter) |
1608 | { | |
1609 | struct e1000_hw *hw = &adapter->hw; | |
1610 | int i; | |
1611 | ||
1612 | /* hardware has been reset, we need to reload some things */ | |
1613 | igb_configure(adapter); | |
1614 | ||
1615 | clear_bit(__IGB_DOWN, &adapter->state); | |
1616 | ||
0d1ae7f4 AD |
1617 | for (i = 0; i < adapter->num_q_vectors; i++) |
1618 | napi_enable(&(adapter->q_vector[i]->napi)); | |
1619 | ||
844290e5 | 1620 | if (adapter->msix_entries) |
9d5c8243 | 1621 | igb_configure_msix(adapter); |
feeb2721 AD |
1622 | else |
1623 | igb_assign_vector(adapter->q_vector[0], 0); | |
9d5c8243 AK |
1624 | |
1625 | /* Clear any pending interrupts. */ | |
1626 | rd32(E1000_ICR); | |
1627 | igb_irq_enable(adapter); | |
1628 | ||
d4960307 AD |
1629 | /* notify VFs that reset has been completed */ |
1630 | if (adapter->vfs_allocated_count) { | |
1631 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
1632 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
1633 | wr32(E1000_CTRL_EXT, reg_data); | |
1634 | } | |
1635 | ||
4cb9be7a JB |
1636 | netif_tx_start_all_queues(adapter->netdev); |
1637 | ||
25568a53 AD |
1638 | /* start the watchdog. */ |
1639 | hw->mac.get_link_status = 1; | |
1640 | schedule_work(&adapter->watchdog_task); | |
1641 | ||
9d5c8243 AK |
1642 | return 0; |
1643 | } | |
1644 | ||
1645 | void igb_down(struct igb_adapter *adapter) | |
1646 | { | |
9d5c8243 | 1647 | struct net_device *netdev = adapter->netdev; |
330a6d6a | 1648 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
1649 | u32 tctl, rctl; |
1650 | int i; | |
1651 | ||
1652 | /* signal that we're down so the interrupt handler does not | |
b980ac18 JK |
1653 | * reschedule our watchdog timer |
1654 | */ | |
9d5c8243 AK |
1655 | set_bit(__IGB_DOWN, &adapter->state); |
1656 | ||
1657 | /* disable receives in the hardware */ | |
1658 | rctl = rd32(E1000_RCTL); | |
1659 | wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); | |
1660 | /* flush and sleep below */ | |
1661 | ||
fd2ea0a7 | 1662 | netif_tx_stop_all_queues(netdev); |
9d5c8243 AK |
1663 | |
1664 | /* disable transmits in the hardware */ | |
1665 | tctl = rd32(E1000_TCTL); | |
1666 | tctl &= ~E1000_TCTL_EN; | |
1667 | wr32(E1000_TCTL, tctl); | |
1668 | /* flush both disables and wait for them to finish */ | |
1669 | wrfl(); | |
1670 | msleep(10); | |
1671 | ||
41f149a2 CW |
1672 | igb_irq_disable(adapter); |
1673 | ||
1674 | for (i = 0; i < adapter->num_q_vectors; i++) { | |
1675 | napi_synchronize(&(adapter->q_vector[i]->napi)); | |
0d1ae7f4 | 1676 | napi_disable(&(adapter->q_vector[i]->napi)); |
41f149a2 | 1677 | } |
9d5c8243 | 1678 | |
9d5c8243 AK |
1679 | |
1680 | del_timer_sync(&adapter->watchdog_timer); | |
1681 | del_timer_sync(&adapter->phy_info_timer); | |
1682 | ||
9d5c8243 | 1683 | netif_carrier_off(netdev); |
04fe6358 AD |
1684 | |
1685 | /* record the stats before reset*/ | |
12dcd86b ED |
1686 | spin_lock(&adapter->stats64_lock); |
1687 | igb_update_stats(adapter, &adapter->stats64); | |
1688 | spin_unlock(&adapter->stats64_lock); | |
04fe6358 | 1689 | |
9d5c8243 AK |
1690 | adapter->link_speed = 0; |
1691 | adapter->link_duplex = 0; | |
1692 | ||
3023682e JK |
1693 | if (!pci_channel_offline(adapter->pdev)) |
1694 | igb_reset(adapter); | |
9d5c8243 AK |
1695 | igb_clean_all_tx_rings(adapter); |
1696 | igb_clean_all_rx_rings(adapter); | |
7e0e99ef AD |
1697 | #ifdef CONFIG_IGB_DCA |
1698 | ||
1699 | /* since we reset the hardware DCA settings were cleared */ | |
1700 | igb_setup_dca(adapter); | |
1701 | #endif | |
9d5c8243 AK |
1702 | } |
1703 | ||
1704 | void igb_reinit_locked(struct igb_adapter *adapter) | |
1705 | { | |
1706 | WARN_ON(in_interrupt()); | |
1707 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) | |
1708 | msleep(1); | |
1709 | igb_down(adapter); | |
1710 | igb_up(adapter); | |
1711 | clear_bit(__IGB_RESETTING, &adapter->state); | |
1712 | } | |
1713 | ||
1714 | void igb_reset(struct igb_adapter *adapter) | |
1715 | { | |
090b1795 | 1716 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 | 1717 | struct e1000_hw *hw = &adapter->hw; |
2d064c06 AD |
1718 | struct e1000_mac_info *mac = &hw->mac; |
1719 | struct e1000_fc_info *fc = &hw->fc; | |
d48507fe | 1720 | u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; |
9d5c8243 AK |
1721 | |
1722 | /* Repartition Pba for greater than 9k mtu | |
1723 | * To take effect CTRL.RST is required. | |
1724 | */ | |
fa4dfae0 | 1725 | switch (mac->type) { |
d2ba2ed8 | 1726 | case e1000_i350: |
ceb5f13b | 1727 | case e1000_i354: |
55cac248 AD |
1728 | case e1000_82580: |
1729 | pba = rd32(E1000_RXPBS); | |
1730 | pba = igb_rxpbs_adjust_82580(pba); | |
1731 | break; | |
fa4dfae0 | 1732 | case e1000_82576: |
d249be54 AD |
1733 | pba = rd32(E1000_RXPBS); |
1734 | pba &= E1000_RXPBS_SIZE_MASK_82576; | |
fa4dfae0 AD |
1735 | break; |
1736 | case e1000_82575: | |
f96a8a0b CW |
1737 | case e1000_i210: |
1738 | case e1000_i211: | |
fa4dfae0 AD |
1739 | default: |
1740 | pba = E1000_PBA_34K; | |
1741 | break; | |
2d064c06 | 1742 | } |
9d5c8243 | 1743 | |
2d064c06 AD |
1744 | if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && |
1745 | (mac->type < e1000_82576)) { | |
9d5c8243 AK |
1746 | /* adjust PBA for jumbo frames */ |
1747 | wr32(E1000_PBA, pba); | |
1748 | ||
1749 | /* To maintain wire speed transmits, the Tx FIFO should be | |
1750 | * large enough to accommodate two full transmit packets, | |
1751 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
1752 | * the Rx FIFO should be large enough to accommodate at least | |
1753 | * one full receive packet and is similarly rounded up and | |
b980ac18 JK |
1754 | * expressed in KB. |
1755 | */ | |
9d5c8243 AK |
1756 | pba = rd32(E1000_PBA); |
1757 | /* upper 16 bits has Tx packet buffer allocation size in KB */ | |
1758 | tx_space = pba >> 16; | |
1759 | /* lower 16 bits has Rx packet buffer allocation size in KB */ | |
1760 | pba &= 0xffff; | |
b980ac18 JK |
1761 | /* the Tx fifo also stores 16 bytes of information about the Tx |
1762 | * but don't include ethernet FCS because hardware appends it | |
1763 | */ | |
9d5c8243 | 1764 | min_tx_space = (adapter->max_frame_size + |
85e8d004 | 1765 | sizeof(union e1000_adv_tx_desc) - |
9d5c8243 AK |
1766 | ETH_FCS_LEN) * 2; |
1767 | min_tx_space = ALIGN(min_tx_space, 1024); | |
1768 | min_tx_space >>= 10; | |
1769 | /* software strips receive CRC, so leave room for it */ | |
1770 | min_rx_space = adapter->max_frame_size; | |
1771 | min_rx_space = ALIGN(min_rx_space, 1024); | |
1772 | min_rx_space >>= 10; | |
1773 | ||
1774 | /* If current Tx allocation is less than the min Tx FIFO size, | |
1775 | * and the min Tx FIFO size is less than the current Rx FIFO | |
b980ac18 JK |
1776 | * allocation, take space away from current Rx allocation |
1777 | */ | |
9d5c8243 AK |
1778 | if (tx_space < min_tx_space && |
1779 | ((min_tx_space - tx_space) < pba)) { | |
1780 | pba = pba - (min_tx_space - tx_space); | |
1781 | ||
b980ac18 JK |
1782 | /* if short on Rx space, Rx wins and must trump Tx |
1783 | * adjustment | |
1784 | */ | |
9d5c8243 AK |
1785 | if (pba < min_rx_space) |
1786 | pba = min_rx_space; | |
1787 | } | |
2d064c06 | 1788 | wr32(E1000_PBA, pba); |
9d5c8243 | 1789 | } |
9d5c8243 AK |
1790 | |
1791 | /* flow control settings */ | |
1792 | /* The high water mark must be low enough to fit one full frame | |
1793 | * (or the size used for early receive) above it in the Rx FIFO. | |
1794 | * Set it to the lower of: | |
1795 | * - 90% of the Rx FIFO size, or | |
b980ac18 JK |
1796 | * - the full Rx FIFO size minus one full frame |
1797 | */ | |
9d5c8243 | 1798 | hwm = min(((pba << 10) * 9 / 10), |
2d064c06 | 1799 | ((pba << 10) - 2 * adapter->max_frame_size)); |
9d5c8243 | 1800 | |
d48507fe | 1801 | fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ |
d405ea3e | 1802 | fc->low_water = fc->high_water - 16; |
9d5c8243 AK |
1803 | fc->pause_time = 0xFFFF; |
1804 | fc->send_xon = 1; | |
0cce119a | 1805 | fc->current_mode = fc->requested_mode; |
9d5c8243 | 1806 | |
4ae196df AD |
1807 | /* disable receive for all VFs and wait one second */ |
1808 | if (adapter->vfs_allocated_count) { | |
1809 | int i; | |
1810 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) | |
8fa7e0f7 | 1811 | adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; |
4ae196df AD |
1812 | |
1813 | /* ping all the active vfs to let them know we are going down */ | |
f2ca0dbe | 1814 | igb_ping_all_vfs(adapter); |
4ae196df AD |
1815 | |
1816 | /* disable transmits and receives */ | |
1817 | wr32(E1000_VFRE, 0); | |
1818 | wr32(E1000_VFTE, 0); | |
1819 | } | |
1820 | ||
9d5c8243 | 1821 | /* Allow time for pending master requests to run */ |
330a6d6a | 1822 | hw->mac.ops.reset_hw(hw); |
9d5c8243 AK |
1823 | wr32(E1000_WUC, 0); |
1824 | ||
330a6d6a | 1825 | if (hw->mac.ops.init_hw(hw)) |
090b1795 | 1826 | dev_err(&pdev->dev, "Hardware Error\n"); |
831ec0b4 | 1827 | |
b980ac18 | 1828 | /* Flow control settings reset on hardware reset, so guarantee flow |
a27416bb MV |
1829 | * control is off when forcing speed. |
1830 | */ | |
1831 | if (!hw->mac.autoneg) | |
1832 | igb_force_mac_fc(hw); | |
1833 | ||
b6e0c419 | 1834 | igb_init_dmac(adapter, pba); |
e428893b CW |
1835 | #ifdef CONFIG_IGB_HWMON |
1836 | /* Re-initialize the thermal sensor on i350 devices. */ | |
1837 | if (!test_bit(__IGB_DOWN, &adapter->state)) { | |
1838 | if (mac->type == e1000_i350 && hw->bus.func == 0) { | |
1839 | /* If present, re-initialize the external thermal sensor | |
1840 | * interface. | |
1841 | */ | |
1842 | if (adapter->ets) | |
1843 | mac->ops.init_thermal_sensor_thresh(hw); | |
1844 | } | |
1845 | } | |
1846 | #endif | |
88a268c1 NN |
1847 | if (!netif_running(adapter->netdev)) |
1848 | igb_power_down_link(adapter); | |
1849 | ||
9d5c8243 AK |
1850 | igb_update_mng_vlan(adapter); |
1851 | ||
1852 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
1853 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | |
1854 | ||
1f6e8178 MV |
1855 | /* Re-enable PTP, where applicable. */ |
1856 | igb_ptp_reset(adapter); | |
1f6e8178 | 1857 | |
330a6d6a | 1858 | igb_get_phy_info(hw); |
9d5c8243 AK |
1859 | } |
1860 | ||
c8f44aff MM |
1861 | static netdev_features_t igb_fix_features(struct net_device *netdev, |
1862 | netdev_features_t features) | |
b2cb09b1 | 1863 | { |
b980ac18 JK |
1864 | /* Since there is no support for separate Rx/Tx vlan accel |
1865 | * enable/disable make sure Tx flag is always in same state as Rx. | |
b2cb09b1 | 1866 | */ |
f646968f PM |
1867 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
1868 | features |= NETIF_F_HW_VLAN_CTAG_TX; | |
b2cb09b1 | 1869 | else |
f646968f | 1870 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
b2cb09b1 JP |
1871 | |
1872 | return features; | |
1873 | } | |
1874 | ||
c8f44aff MM |
1875 | static int igb_set_features(struct net_device *netdev, |
1876 | netdev_features_t features) | |
ac52caa3 | 1877 | { |
c8f44aff | 1878 | netdev_features_t changed = netdev->features ^ features; |
89eaefb6 | 1879 | struct igb_adapter *adapter = netdev_priv(netdev); |
ac52caa3 | 1880 | |
f646968f | 1881 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
b2cb09b1 JP |
1882 | igb_vlan_mode(netdev, features); |
1883 | ||
89eaefb6 BG |
1884 | if (!(changed & NETIF_F_RXALL)) |
1885 | return 0; | |
1886 | ||
1887 | netdev->features = features; | |
1888 | ||
1889 | if (netif_running(netdev)) | |
1890 | igb_reinit_locked(adapter); | |
1891 | else | |
1892 | igb_reset(adapter); | |
1893 | ||
ac52caa3 MM |
1894 | return 0; |
1895 | } | |
1896 | ||
2e5c6922 | 1897 | static const struct net_device_ops igb_netdev_ops = { |
559e9c49 | 1898 | .ndo_open = igb_open, |
2e5c6922 | 1899 | .ndo_stop = igb_close, |
cd392f5c | 1900 | .ndo_start_xmit = igb_xmit_frame, |
12dcd86b | 1901 | .ndo_get_stats64 = igb_get_stats64, |
ff41f8dc | 1902 | .ndo_set_rx_mode = igb_set_rx_mode, |
2e5c6922 SH |
1903 | .ndo_set_mac_address = igb_set_mac, |
1904 | .ndo_change_mtu = igb_change_mtu, | |
1905 | .ndo_do_ioctl = igb_ioctl, | |
1906 | .ndo_tx_timeout = igb_tx_timeout, | |
1907 | .ndo_validate_addr = eth_validate_addr, | |
2e5c6922 SH |
1908 | .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, |
1909 | .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, | |
8151d294 WM |
1910 | .ndo_set_vf_mac = igb_ndo_set_vf_mac, |
1911 | .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, | |
1912 | .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, | |
70ea4783 | 1913 | .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, |
8151d294 | 1914 | .ndo_get_vf_config = igb_ndo_get_vf_config, |
2e5c6922 SH |
1915 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1916 | .ndo_poll_controller = igb_netpoll, | |
1917 | #endif | |
b2cb09b1 JP |
1918 | .ndo_fix_features = igb_fix_features, |
1919 | .ndo_set_features = igb_set_features, | |
2e5c6922 SH |
1920 | }; |
1921 | ||
d67974f0 CW |
1922 | /** |
1923 | * igb_set_fw_version - Configure version string for ethtool | |
1924 | * @adapter: adapter struct | |
d67974f0 CW |
1925 | **/ |
1926 | void igb_set_fw_version(struct igb_adapter *adapter) | |
1927 | { | |
1928 | struct e1000_hw *hw = &adapter->hw; | |
0b1a6f2e CW |
1929 | struct e1000_fw_version fw; |
1930 | ||
1931 | igb_get_fw_version(hw, &fw); | |
1932 | ||
1933 | switch (hw->mac.type) { | |
7dc98a62 | 1934 | case e1000_i210: |
0b1a6f2e | 1935 | case e1000_i211: |
7dc98a62 CW |
1936 | if (!(igb_get_flash_presence_i210(hw))) { |
1937 | snprintf(adapter->fw_version, | |
1938 | sizeof(adapter->fw_version), | |
1939 | "%2d.%2d-%d", | |
1940 | fw.invm_major, fw.invm_minor, | |
1941 | fw.invm_img_type); | |
1942 | break; | |
1943 | } | |
1944 | /* fall through */ | |
0b1a6f2e CW |
1945 | default: |
1946 | /* if option is rom valid, display its version too */ | |
1947 | if (fw.or_valid) { | |
1948 | snprintf(adapter->fw_version, | |
1949 | sizeof(adapter->fw_version), | |
1950 | "%d.%d, 0x%08x, %d.%d.%d", | |
1951 | fw.eep_major, fw.eep_minor, fw.etrack_id, | |
1952 | fw.or_major, fw.or_build, fw.or_patch); | |
1953 | /* no option rom */ | |
7dc98a62 | 1954 | } else if (fw.etrack_id != 0X0000) { |
0b1a6f2e | 1955 | snprintf(adapter->fw_version, |
7dc98a62 CW |
1956 | sizeof(adapter->fw_version), |
1957 | "%d.%d, 0x%08x", | |
1958 | fw.eep_major, fw.eep_minor, fw.etrack_id); | |
1959 | } else { | |
1960 | snprintf(adapter->fw_version, | |
1961 | sizeof(adapter->fw_version), | |
1962 | "%d.%d.%d", | |
1963 | fw.eep_major, fw.eep_minor, fw.eep_build); | |
0b1a6f2e CW |
1964 | } |
1965 | break; | |
d67974f0 | 1966 | } |
d67974f0 CW |
1967 | return; |
1968 | } | |
1969 | ||
b980ac18 JK |
1970 | /** |
1971 | * igb_init_i2c - Init I2C interface | |
441fc6fd | 1972 | * @adapter: pointer to adapter structure |
b980ac18 | 1973 | **/ |
441fc6fd CW |
1974 | static s32 igb_init_i2c(struct igb_adapter *adapter) |
1975 | { | |
1976 | s32 status = E1000_SUCCESS; | |
1977 | ||
1978 | /* I2C interface supported on i350 devices */ | |
1979 | if (adapter->hw.mac.type != e1000_i350) | |
1980 | return E1000_SUCCESS; | |
1981 | ||
1982 | /* Initialize the i2c bus which is controlled by the registers. | |
1983 | * This bus will use the i2c_algo_bit structue that implements | |
1984 | * the protocol through toggling of the 4 bits in the register. | |
1985 | */ | |
1986 | adapter->i2c_adap.owner = THIS_MODULE; | |
1987 | adapter->i2c_algo = igb_i2c_algo; | |
1988 | adapter->i2c_algo.data = adapter; | |
1989 | adapter->i2c_adap.algo_data = &adapter->i2c_algo; | |
1990 | adapter->i2c_adap.dev.parent = &adapter->pdev->dev; | |
1991 | strlcpy(adapter->i2c_adap.name, "igb BB", | |
1992 | sizeof(adapter->i2c_adap.name)); | |
1993 | status = i2c_bit_add_bus(&adapter->i2c_adap); | |
1994 | return status; | |
1995 | } | |
1996 | ||
9d5c8243 | 1997 | /** |
b980ac18 JK |
1998 | * igb_probe - Device Initialization Routine |
1999 | * @pdev: PCI device information struct | |
2000 | * @ent: entry in igb_pci_tbl | |
9d5c8243 | 2001 | * |
b980ac18 | 2002 | * Returns 0 on success, negative on failure |
9d5c8243 | 2003 | * |
b980ac18 JK |
2004 | * igb_probe initializes an adapter identified by a pci_dev structure. |
2005 | * The OS initialization, configuring of the adapter private structure, | |
2006 | * and a hardware reset occur. | |
9d5c8243 | 2007 | **/ |
1dd06ae8 | 2008 | static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
9d5c8243 AK |
2009 | { |
2010 | struct net_device *netdev; | |
2011 | struct igb_adapter *adapter; | |
2012 | struct e1000_hw *hw; | |
4337e993 | 2013 | u16 eeprom_data = 0; |
9835fd73 | 2014 | s32 ret_val; |
4337e993 | 2015 | static int global_quad_port_a; /* global quad port a indication */ |
9d5c8243 AK |
2016 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
2017 | unsigned long mmio_start, mmio_len; | |
2d6a5e95 | 2018 | int err, pci_using_dac; |
9835fd73 | 2019 | u8 part_str[E1000_PBANUM_LENGTH]; |
9d5c8243 | 2020 | |
bded64a7 AG |
2021 | /* Catch broken hardware that put the wrong VF device ID in |
2022 | * the PCIe SR-IOV capability. | |
2023 | */ | |
2024 | if (pdev->is_virtfn) { | |
2025 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
f96a8a0b | 2026 | pci_name(pdev), pdev->vendor, pdev->device); |
bded64a7 AG |
2027 | return -EINVAL; |
2028 | } | |
2029 | ||
aed5dec3 | 2030 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
2031 | if (err) |
2032 | return err; | |
2033 | ||
2034 | pci_using_dac = 0; | |
59d71989 | 2035 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 | 2036 | if (!err) { |
59d71989 | 2037 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
9d5c8243 AK |
2038 | if (!err) |
2039 | pci_using_dac = 1; | |
2040 | } else { | |
59d71989 | 2041 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9d5c8243 | 2042 | if (err) { |
b980ac18 JK |
2043 | err = dma_set_coherent_mask(&pdev->dev, |
2044 | DMA_BIT_MASK(32)); | |
9d5c8243 | 2045 | if (err) { |
b980ac18 JK |
2046 | dev_err(&pdev->dev, |
2047 | "No usable DMA configuration, aborting\n"); | |
9d5c8243 AK |
2048 | goto err_dma; |
2049 | } | |
2050 | } | |
2051 | } | |
2052 | ||
aed5dec3 | 2053 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
b980ac18 JK |
2054 | IORESOURCE_MEM), |
2055 | igb_driver_name); | |
9d5c8243 AK |
2056 | if (err) |
2057 | goto err_pci_reg; | |
2058 | ||
19d5afd4 | 2059 | pci_enable_pcie_error_reporting(pdev); |
40a914fa | 2060 | |
9d5c8243 | 2061 | pci_set_master(pdev); |
c682fc23 | 2062 | pci_save_state(pdev); |
9d5c8243 AK |
2063 | |
2064 | err = -ENOMEM; | |
1bfaf07b | 2065 | netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), |
1cc3bd87 | 2066 | IGB_MAX_TX_QUEUES); |
9d5c8243 AK |
2067 | if (!netdev) |
2068 | goto err_alloc_etherdev; | |
2069 | ||
2070 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
2071 | ||
2072 | pci_set_drvdata(pdev, netdev); | |
2073 | adapter = netdev_priv(netdev); | |
2074 | adapter->netdev = netdev; | |
2075 | adapter->pdev = pdev; | |
2076 | hw = &adapter->hw; | |
2077 | hw->back = adapter; | |
b3f4d599 | 2078 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9d5c8243 AK |
2079 | |
2080 | mmio_start = pci_resource_start(pdev, 0); | |
2081 | mmio_len = pci_resource_len(pdev, 0); | |
2082 | ||
2083 | err = -EIO; | |
28b0759c AD |
2084 | hw->hw_addr = ioremap(mmio_start, mmio_len); |
2085 | if (!hw->hw_addr) | |
9d5c8243 AK |
2086 | goto err_ioremap; |
2087 | ||
2e5c6922 | 2088 | netdev->netdev_ops = &igb_netdev_ops; |
9d5c8243 | 2089 | igb_set_ethtool_ops(netdev); |
9d5c8243 | 2090 | netdev->watchdog_timeo = 5 * HZ; |
9d5c8243 AK |
2091 | |
2092 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); | |
2093 | ||
2094 | netdev->mem_start = mmio_start; | |
2095 | netdev->mem_end = mmio_start + mmio_len; | |
2096 | ||
9d5c8243 AK |
2097 | /* PCI config space info */ |
2098 | hw->vendor_id = pdev->vendor; | |
2099 | hw->device_id = pdev->device; | |
2100 | hw->revision_id = pdev->revision; | |
2101 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
2102 | hw->subsystem_device_id = pdev->subsystem_device; | |
2103 | ||
9d5c8243 AK |
2104 | /* Copy the default MAC, PHY and NVM function pointers */ |
2105 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); | |
2106 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
2107 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
2108 | /* Initialize skew-specific constants */ | |
2109 | err = ei->get_invariants(hw); | |
2110 | if (err) | |
450c87c8 | 2111 | goto err_sw_init; |
9d5c8243 | 2112 | |
450c87c8 | 2113 | /* setup the private structure */ |
9d5c8243 AK |
2114 | err = igb_sw_init(adapter); |
2115 | if (err) | |
2116 | goto err_sw_init; | |
2117 | ||
2118 | igb_get_bus_info_pcie(hw); | |
2119 | ||
2120 | hw->phy.autoneg_wait_to_complete = false; | |
9d5c8243 AK |
2121 | |
2122 | /* Copper options */ | |
2123 | if (hw->phy.media_type == e1000_media_type_copper) { | |
2124 | hw->phy.mdix = AUTO_ALL_MODES; | |
2125 | hw->phy.disable_polarity_correction = false; | |
2126 | hw->phy.ms_type = e1000_ms_hw_default; | |
2127 | } | |
2128 | ||
2129 | if (igb_check_reset_block(hw)) | |
2130 | dev_info(&pdev->dev, | |
2131 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
2132 | ||
b980ac18 | 2133 | /* features is initialized to 0 in allocation, it might have bits |
077887c3 AD |
2134 | * set by igb_sw_init so we should use an or instead of an |
2135 | * assignment. | |
2136 | */ | |
2137 | netdev->features |= NETIF_F_SG | | |
2138 | NETIF_F_IP_CSUM | | |
2139 | NETIF_F_IPV6_CSUM | | |
2140 | NETIF_F_TSO | | |
2141 | NETIF_F_TSO6 | | |
2142 | NETIF_F_RXHASH | | |
2143 | NETIF_F_RXCSUM | | |
f646968f PM |
2144 | NETIF_F_HW_VLAN_CTAG_RX | |
2145 | NETIF_F_HW_VLAN_CTAG_TX; | |
077887c3 AD |
2146 | |
2147 | /* copy netdev features into list of user selectable features */ | |
2148 | netdev->hw_features |= netdev->features; | |
89eaefb6 | 2149 | netdev->hw_features |= NETIF_F_RXALL; |
077887c3 AD |
2150 | |
2151 | /* set this bit last since it cannot be part of hw_features */ | |
f646968f | 2152 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
077887c3 AD |
2153 | |
2154 | netdev->vlan_features |= NETIF_F_TSO | | |
2155 | NETIF_F_TSO6 | | |
2156 | NETIF_F_IP_CSUM | | |
2157 | NETIF_F_IPV6_CSUM | | |
2158 | NETIF_F_SG; | |
48f29ffc | 2159 | |
6b8f0922 BG |
2160 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
2161 | ||
7b872a55 | 2162 | if (pci_using_dac) { |
9d5c8243 | 2163 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
2164 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
2165 | } | |
9d5c8243 | 2166 | |
ac52caa3 MM |
2167 | if (hw->mac.type >= e1000_82576) { |
2168 | netdev->hw_features |= NETIF_F_SCTP_CSUM; | |
b9473560 | 2169 | netdev->features |= NETIF_F_SCTP_CSUM; |
ac52caa3 | 2170 | } |
b9473560 | 2171 | |
01789349 JP |
2172 | netdev->priv_flags |= IFF_UNICAST_FLT; |
2173 | ||
330a6d6a | 2174 | adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); |
9d5c8243 AK |
2175 | |
2176 | /* before reading the NVM, reset the controller to put the device in a | |
b980ac18 JK |
2177 | * known good starting state |
2178 | */ | |
9d5c8243 AK |
2179 | hw->mac.ops.reset_hw(hw); |
2180 | ||
ef3a0092 CW |
2181 | /* make sure the NVM is good , i211/i210 parts can have special NVM |
2182 | * that doesn't contain a checksum | |
f96a8a0b | 2183 | */ |
ef3a0092 CW |
2184 | switch (hw->mac.type) { |
2185 | case e1000_i210: | |
2186 | case e1000_i211: | |
2187 | if (igb_get_flash_presence_i210(hw)) { | |
2188 | if (hw->nvm.ops.validate(hw) < 0) { | |
2189 | dev_err(&pdev->dev, | |
2190 | "The NVM Checksum Is Not Valid\n"); | |
2191 | err = -EIO; | |
2192 | goto err_eeprom; | |
2193 | } | |
2194 | } | |
2195 | break; | |
2196 | default: | |
f96a8a0b CW |
2197 | if (hw->nvm.ops.validate(hw) < 0) { |
2198 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); | |
2199 | err = -EIO; | |
2200 | goto err_eeprom; | |
2201 | } | |
ef3a0092 | 2202 | break; |
9d5c8243 AK |
2203 | } |
2204 | ||
2205 | /* copy the MAC address out of the NVM */ | |
2206 | if (hw->mac.ops.read_mac_addr(hw)) | |
2207 | dev_err(&pdev->dev, "NVM Read Error\n"); | |
2208 | ||
2209 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
9d5c8243 | 2210 | |
aaeb6cdf | 2211 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
9d5c8243 AK |
2212 | dev_err(&pdev->dev, "Invalid MAC Address\n"); |
2213 | err = -EIO; | |
2214 | goto err_eeprom; | |
2215 | } | |
2216 | ||
d67974f0 CW |
2217 | /* get firmware version for ethtool -i */ |
2218 | igb_set_fw_version(adapter); | |
2219 | ||
c061b18d | 2220 | setup_timer(&adapter->watchdog_timer, igb_watchdog, |
b980ac18 | 2221 | (unsigned long) adapter); |
c061b18d | 2222 | setup_timer(&adapter->phy_info_timer, igb_update_phy_info, |
b980ac18 | 2223 | (unsigned long) adapter); |
9d5c8243 AK |
2224 | |
2225 | INIT_WORK(&adapter->reset_task, igb_reset_task); | |
2226 | INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); | |
2227 | ||
450c87c8 | 2228 | /* Initialize link properties that are user-changeable */ |
9d5c8243 AK |
2229 | adapter->fc_autoneg = true; |
2230 | hw->mac.autoneg = true; | |
2231 | hw->phy.autoneg_advertised = 0x2f; | |
2232 | ||
0cce119a AD |
2233 | hw->fc.requested_mode = e1000_fc_default; |
2234 | hw->fc.current_mode = e1000_fc_default; | |
9d5c8243 | 2235 | |
9d5c8243 AK |
2236 | igb_validate_mdi_setting(hw); |
2237 | ||
63d4a8f9 | 2238 | /* By default, support wake on port A */ |
a2cf8b6c | 2239 | if (hw->bus.func == 0) |
63d4a8f9 MV |
2240 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; |
2241 | ||
2242 | /* Check the NVM for wake support on non-port A ports */ | |
2243 | if (hw->mac.type >= e1000_82580) | |
55cac248 | 2244 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + |
b980ac18 JK |
2245 | NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, |
2246 | &eeprom_data); | |
a2cf8b6c AD |
2247 | else if (hw->bus.func == 1) |
2248 | hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); | |
9d5c8243 | 2249 | |
63d4a8f9 MV |
2250 | if (eeprom_data & IGB_EEPROM_APME) |
2251 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; | |
9d5c8243 AK |
2252 | |
2253 | /* now that we have the eeprom settings, apply the special cases where | |
2254 | * the eeprom may be wrong or the board simply won't support wake on | |
b980ac18 JK |
2255 | * lan on a particular port |
2256 | */ | |
9d5c8243 AK |
2257 | switch (pdev->device) { |
2258 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | |
63d4a8f9 | 2259 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
9d5c8243 AK |
2260 | break; |
2261 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | |
2d064c06 AD |
2262 | case E1000_DEV_ID_82576_FIBER: |
2263 | case E1000_DEV_ID_82576_SERDES: | |
9d5c8243 | 2264 | /* Wake events only supported on port A for dual fiber |
b980ac18 JK |
2265 | * regardless of eeprom setting |
2266 | */ | |
9d5c8243 | 2267 | if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) |
63d4a8f9 | 2268 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
9d5c8243 | 2269 | break; |
c8ea5ea9 | 2270 | case E1000_DEV_ID_82576_QUAD_COPPER: |
d5aa2252 | 2271 | case E1000_DEV_ID_82576_QUAD_COPPER_ET2: |
c8ea5ea9 AD |
2272 | /* if quad port adapter, disable WoL on all but port A */ |
2273 | if (global_quad_port_a != 0) | |
63d4a8f9 | 2274 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; |
c8ea5ea9 AD |
2275 | else |
2276 | adapter->flags |= IGB_FLAG_QUAD_PORT_A; | |
2277 | /* Reset for multiple quad port adapters */ | |
2278 | if (++global_quad_port_a == 4) | |
2279 | global_quad_port_a = 0; | |
2280 | break; | |
63d4a8f9 MV |
2281 | default: |
2282 | /* If the device can't wake, don't set software support */ | |
2283 | if (!device_can_wakeup(&adapter->pdev->dev)) | |
2284 | adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; | |
9d5c8243 AK |
2285 | } |
2286 | ||
2287 | /* initialize the wol settings based on the eeprom settings */ | |
63d4a8f9 MV |
2288 | if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) |
2289 | adapter->wol |= E1000_WUFC_MAG; | |
2290 | ||
2291 | /* Some vendors want WoL disabled by default, but still supported */ | |
2292 | if ((hw->mac.type == e1000_i350) && | |
2293 | (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { | |
2294 | adapter->flags |= IGB_FLAG_WOL_SUPPORTED; | |
2295 | adapter->wol = 0; | |
2296 | } | |
2297 | ||
2298 | device_set_wakeup_enable(&adapter->pdev->dev, | |
2299 | adapter->flags & IGB_FLAG_WOL_SUPPORTED); | |
9d5c8243 AK |
2300 | |
2301 | /* reset the hardware with the new settings */ | |
2302 | igb_reset(adapter); | |
2303 | ||
441fc6fd CW |
2304 | /* Init the I2C interface */ |
2305 | err = igb_init_i2c(adapter); | |
2306 | if (err) { | |
2307 | dev_err(&pdev->dev, "failed to init i2c interface\n"); | |
2308 | goto err_eeprom; | |
2309 | } | |
2310 | ||
9d5c8243 AK |
2311 | /* let the f/w know that the h/w is now under the control of the |
2312 | * driver. */ | |
2313 | igb_get_hw_control(adapter); | |
2314 | ||
9d5c8243 AK |
2315 | strcpy(netdev->name, "eth%d"); |
2316 | err = register_netdev(netdev); | |
2317 | if (err) | |
2318 | goto err_register; | |
2319 | ||
b168dfc5 JB |
2320 | /* carrier off reporting is important to ethtool even BEFORE open */ |
2321 | netif_carrier_off(netdev); | |
2322 | ||
421e02f0 | 2323 | #ifdef CONFIG_IGB_DCA |
bbd98fe4 | 2324 | if (dca_add_requester(&pdev->dev) == 0) { |
7dfc16fa | 2325 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
fe4506b6 | 2326 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
2327 | igb_setup_dca(adapter); |
2328 | } | |
fe4506b6 | 2329 | |
38c845c7 | 2330 | #endif |
e428893b CW |
2331 | #ifdef CONFIG_IGB_HWMON |
2332 | /* Initialize the thermal sensor on i350 devices. */ | |
2333 | if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { | |
2334 | u16 ets_word; | |
3c89f6d0 | 2335 | |
b980ac18 | 2336 | /* Read the NVM to determine if this i350 device supports an |
e428893b CW |
2337 | * external thermal sensor. |
2338 | */ | |
2339 | hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); | |
2340 | if (ets_word != 0x0000 && ets_word != 0xFFFF) | |
2341 | adapter->ets = true; | |
2342 | else | |
2343 | adapter->ets = false; | |
2344 | if (igb_sysfs_init(adapter)) | |
2345 | dev_err(&pdev->dev, | |
2346 | "failed to allocate sysfs resources\n"); | |
2347 | } else { | |
2348 | adapter->ets = false; | |
2349 | } | |
2350 | #endif | |
673b8b70 | 2351 | /* do hw tstamp init after resetting */ |
7ebae817 | 2352 | igb_ptp_init(adapter); |
673b8b70 | 2353 | |
9d5c8243 | 2354 | dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); |
ceb5f13b CW |
2355 | /* print bus type/speed/width info, not applicable to i354 */ |
2356 | if (hw->mac.type != e1000_i354) { | |
2357 | dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", | |
2358 | netdev->name, | |
2359 | ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : | |
2360 | (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : | |
2361 | "unknown"), | |
2362 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? | |
2363 | "Width x4" : | |
2364 | (hw->bus.width == e1000_bus_width_pcie_x2) ? | |
2365 | "Width x2" : | |
2366 | (hw->bus.width == e1000_bus_width_pcie_x1) ? | |
2367 | "Width x1" : "unknown"), netdev->dev_addr); | |
2368 | } | |
9d5c8243 | 2369 | |
9835fd73 CW |
2370 | ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); |
2371 | if (ret_val) | |
2372 | strcpy(part_str, "Unknown"); | |
2373 | dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); | |
9d5c8243 AK |
2374 | dev_info(&pdev->dev, |
2375 | "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", | |
2376 | adapter->msix_entries ? "MSI-X" : | |
7dfc16fa | 2377 | (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", |
9d5c8243 | 2378 | adapter->num_rx_queues, adapter->num_tx_queues); |
09b068d4 CW |
2379 | switch (hw->mac.type) { |
2380 | case e1000_i350: | |
f96a8a0b CW |
2381 | case e1000_i210: |
2382 | case e1000_i211: | |
09b068d4 CW |
2383 | igb_set_eee_i350(hw); |
2384 | break; | |
ceb5f13b CW |
2385 | case e1000_i354: |
2386 | if (hw->phy.media_type == e1000_media_type_copper) { | |
2387 | if ((rd32(E1000_CTRL_EXT) & | |
2388 | E1000_CTRL_EXT_LINK_MODE_SGMII)) | |
2389 | igb_set_eee_i354(hw); | |
2390 | } | |
2391 | break; | |
09b068d4 CW |
2392 | default: |
2393 | break; | |
2394 | } | |
749ab2cd YZ |
2395 | |
2396 | pm_runtime_put_noidle(&pdev->dev); | |
9d5c8243 AK |
2397 | return 0; |
2398 | ||
2399 | err_register: | |
2400 | igb_release_hw_control(adapter); | |
441fc6fd | 2401 | memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); |
9d5c8243 AK |
2402 | err_eeprom: |
2403 | if (!igb_check_reset_block(hw)) | |
f5f4cf08 | 2404 | igb_reset_phy(hw); |
9d5c8243 AK |
2405 | |
2406 | if (hw->flash_address) | |
2407 | iounmap(hw->flash_address); | |
9d5c8243 | 2408 | err_sw_init: |
047e0030 | 2409 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
2410 | iounmap(hw->hw_addr); |
2411 | err_ioremap: | |
2412 | free_netdev(netdev); | |
2413 | err_alloc_etherdev: | |
559e9c49 | 2414 | pci_release_selected_regions(pdev, |
b980ac18 | 2415 | pci_select_bars(pdev, IORESOURCE_MEM)); |
9d5c8243 AK |
2416 | err_pci_reg: |
2417 | err_dma: | |
2418 | pci_disable_device(pdev); | |
2419 | return err; | |
2420 | } | |
2421 | ||
fa44f2f1 GR |
2422 | #ifdef CONFIG_PCI_IOV |
2423 | static int igb_disable_sriov(struct pci_dev *pdev) | |
2424 | { | |
2425 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2426 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2427 | struct e1000_hw *hw = &adapter->hw; | |
2428 | ||
2429 | /* reclaim resources allocated to VFs */ | |
2430 | if (adapter->vf_data) { | |
2431 | /* disable iov and allow time for transactions to clear */ | |
b09186d2 | 2432 | if (pci_vfs_assigned(pdev)) { |
fa44f2f1 GR |
2433 | dev_warn(&pdev->dev, |
2434 | "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); | |
2435 | return -EPERM; | |
2436 | } else { | |
2437 | pci_disable_sriov(pdev); | |
2438 | msleep(500); | |
2439 | } | |
2440 | ||
2441 | kfree(adapter->vf_data); | |
2442 | adapter->vf_data = NULL; | |
2443 | adapter->vfs_allocated_count = 0; | |
2444 | wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); | |
2445 | wrfl(); | |
2446 | msleep(100); | |
2447 | dev_info(&pdev->dev, "IOV Disabled\n"); | |
2448 | ||
2449 | /* Re-enable DMA Coalescing flag since IOV is turned off */ | |
2450 | adapter->flags |= IGB_FLAG_DMAC; | |
2451 | } | |
2452 | ||
2453 | return 0; | |
2454 | } | |
2455 | ||
2456 | static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) | |
2457 | { | |
2458 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2459 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2460 | int old_vfs = pci_num_vf(pdev); | |
2461 | int err = 0; | |
2462 | int i; | |
2463 | ||
50267196 MW |
2464 | if (!adapter->msix_entries) { |
2465 | err = -EPERM; | |
2466 | goto out; | |
2467 | } | |
2468 | ||
fa44f2f1 GR |
2469 | if (!num_vfs) |
2470 | goto out; | |
2471 | else if (old_vfs && old_vfs == num_vfs) | |
2472 | goto out; | |
2473 | else if (old_vfs && old_vfs != num_vfs) | |
2474 | err = igb_disable_sriov(pdev); | |
2475 | ||
2476 | if (err) | |
2477 | goto out; | |
2478 | ||
2479 | if (num_vfs > 7) { | |
2480 | err = -EPERM; | |
2481 | goto out; | |
2482 | } | |
2483 | ||
2484 | adapter->vfs_allocated_count = num_vfs; | |
2485 | ||
2486 | adapter->vf_data = kcalloc(adapter->vfs_allocated_count, | |
2487 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
2488 | ||
2489 | /* if allocation failed then we do not support SR-IOV */ | |
2490 | if (!adapter->vf_data) { | |
2491 | adapter->vfs_allocated_count = 0; | |
2492 | dev_err(&pdev->dev, | |
2493 | "Unable to allocate memory for VF Data Storage\n"); | |
2494 | err = -ENOMEM; | |
2495 | goto out; | |
2496 | } | |
2497 | ||
2498 | err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); | |
2499 | if (err) | |
2500 | goto err_out; | |
2501 | ||
2502 | dev_info(&pdev->dev, "%d VFs allocated\n", | |
2503 | adapter->vfs_allocated_count); | |
2504 | for (i = 0; i < adapter->vfs_allocated_count; i++) | |
2505 | igb_vf_configure(adapter, i); | |
2506 | ||
2507 | /* DMA Coalescing is not supported in IOV mode. */ | |
2508 | adapter->flags &= ~IGB_FLAG_DMAC; | |
2509 | goto out; | |
2510 | ||
2511 | err_out: | |
2512 | kfree(adapter->vf_data); | |
2513 | adapter->vf_data = NULL; | |
2514 | adapter->vfs_allocated_count = 0; | |
2515 | out: | |
2516 | return err; | |
2517 | } | |
2518 | ||
2519 | #endif | |
b980ac18 | 2520 | /** |
441fc6fd CW |
2521 | * igb_remove_i2c - Cleanup I2C interface |
2522 | * @adapter: pointer to adapter structure | |
b980ac18 | 2523 | **/ |
441fc6fd CW |
2524 | static void igb_remove_i2c(struct igb_adapter *adapter) |
2525 | { | |
441fc6fd CW |
2526 | /* free the adapter bus structure */ |
2527 | i2c_del_adapter(&adapter->i2c_adap); | |
2528 | } | |
2529 | ||
9d5c8243 | 2530 | /** |
b980ac18 JK |
2531 | * igb_remove - Device Removal Routine |
2532 | * @pdev: PCI device information struct | |
9d5c8243 | 2533 | * |
b980ac18 JK |
2534 | * igb_remove is called by the PCI subsystem to alert the driver |
2535 | * that it should release a PCI device. The could be caused by a | |
2536 | * Hot-Plug event, or because the driver is going to be removed from | |
2537 | * memory. | |
9d5c8243 | 2538 | **/ |
9f9a12f8 | 2539 | static void igb_remove(struct pci_dev *pdev) |
9d5c8243 AK |
2540 | { |
2541 | struct net_device *netdev = pci_get_drvdata(pdev); | |
2542 | struct igb_adapter *adapter = netdev_priv(netdev); | |
fe4506b6 | 2543 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 2544 | |
749ab2cd | 2545 | pm_runtime_get_noresume(&pdev->dev); |
e428893b CW |
2546 | #ifdef CONFIG_IGB_HWMON |
2547 | igb_sysfs_exit(adapter); | |
2548 | #endif | |
441fc6fd | 2549 | igb_remove_i2c(adapter); |
a79f4f88 | 2550 | igb_ptp_stop(adapter); |
b980ac18 | 2551 | /* The watchdog timer may be rescheduled, so explicitly |
760141a5 TH |
2552 | * disable watchdog from being rescheduled. |
2553 | */ | |
9d5c8243 AK |
2554 | set_bit(__IGB_DOWN, &adapter->state); |
2555 | del_timer_sync(&adapter->watchdog_timer); | |
2556 | del_timer_sync(&adapter->phy_info_timer); | |
2557 | ||
760141a5 TH |
2558 | cancel_work_sync(&adapter->reset_task); |
2559 | cancel_work_sync(&adapter->watchdog_task); | |
9d5c8243 | 2560 | |
421e02f0 | 2561 | #ifdef CONFIG_IGB_DCA |
7dfc16fa | 2562 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 JC |
2563 | dev_info(&pdev->dev, "DCA disabled\n"); |
2564 | dca_remove_requester(&pdev->dev); | |
7dfc16fa | 2565 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 2566 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
2567 | } |
2568 | #endif | |
2569 | ||
9d5c8243 | 2570 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
b980ac18 JK |
2571 | * would have already happened in close and is redundant. |
2572 | */ | |
9d5c8243 AK |
2573 | igb_release_hw_control(adapter); |
2574 | ||
2575 | unregister_netdev(netdev); | |
2576 | ||
047e0030 | 2577 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 | 2578 | |
37680117 | 2579 | #ifdef CONFIG_PCI_IOV |
fa44f2f1 | 2580 | igb_disable_sriov(pdev); |
37680117 | 2581 | #endif |
559e9c49 | 2582 | |
28b0759c AD |
2583 | iounmap(hw->hw_addr); |
2584 | if (hw->flash_address) | |
2585 | iounmap(hw->flash_address); | |
559e9c49 | 2586 | pci_release_selected_regions(pdev, |
b980ac18 | 2587 | pci_select_bars(pdev, IORESOURCE_MEM)); |
9d5c8243 | 2588 | |
1128c756 | 2589 | kfree(adapter->shadow_vfta); |
9d5c8243 AK |
2590 | free_netdev(netdev); |
2591 | ||
19d5afd4 | 2592 | pci_disable_pcie_error_reporting(pdev); |
40a914fa | 2593 | |
9d5c8243 AK |
2594 | pci_disable_device(pdev); |
2595 | } | |
2596 | ||
a6b623e0 | 2597 | /** |
b980ac18 JK |
2598 | * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space |
2599 | * @adapter: board private structure to initialize | |
a6b623e0 | 2600 | * |
b980ac18 JK |
2601 | * This function initializes the vf specific data storage and then attempts to |
2602 | * allocate the VFs. The reason for ordering it this way is because it is much | |
2603 | * mor expensive time wise to disable SR-IOV than it is to allocate and free | |
2604 | * the memory for the VFs. | |
a6b623e0 | 2605 | **/ |
9f9a12f8 | 2606 | static void igb_probe_vfs(struct igb_adapter *adapter) |
a6b623e0 AD |
2607 | { |
2608 | #ifdef CONFIG_PCI_IOV | |
2609 | struct pci_dev *pdev = adapter->pdev; | |
f96a8a0b | 2610 | struct e1000_hw *hw = &adapter->hw; |
a6b623e0 | 2611 | |
f96a8a0b CW |
2612 | /* Virtualization features not supported on i210 family. */ |
2613 | if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) | |
2614 | return; | |
2615 | ||
fa44f2f1 | 2616 | pci_sriov_set_totalvfs(pdev, 7); |
d5e51a10 | 2617 | igb_enable_sriov(pdev, max_vfs); |
0224d663 | 2618 | |
a6b623e0 AD |
2619 | #endif /* CONFIG_PCI_IOV */ |
2620 | } | |
2621 | ||
fa44f2f1 | 2622 | static void igb_init_queue_configuration(struct igb_adapter *adapter) |
9d5c8243 AK |
2623 | { |
2624 | struct e1000_hw *hw = &adapter->hw; | |
374a542d | 2625 | u32 max_rss_queues; |
9d5c8243 | 2626 | |
374a542d | 2627 | /* Determine the maximum number of RSS queues supported. */ |
f96a8a0b | 2628 | switch (hw->mac.type) { |
374a542d MV |
2629 | case e1000_i211: |
2630 | max_rss_queues = IGB_MAX_RX_QUEUES_I211; | |
2631 | break; | |
2632 | case e1000_82575: | |
f96a8a0b | 2633 | case e1000_i210: |
374a542d MV |
2634 | max_rss_queues = IGB_MAX_RX_QUEUES_82575; |
2635 | break; | |
2636 | case e1000_i350: | |
2637 | /* I350 cannot do RSS and SR-IOV at the same time */ | |
2638 | if (!!adapter->vfs_allocated_count) { | |
2639 | max_rss_queues = 1; | |
2640 | break; | |
2641 | } | |
2642 | /* fall through */ | |
2643 | case e1000_82576: | |
2644 | if (!!adapter->vfs_allocated_count) { | |
2645 | max_rss_queues = 2; | |
2646 | break; | |
2647 | } | |
2648 | /* fall through */ | |
2649 | case e1000_82580: | |
ceb5f13b | 2650 | case e1000_i354: |
374a542d MV |
2651 | default: |
2652 | max_rss_queues = IGB_MAX_RX_QUEUES; | |
f96a8a0b | 2653 | break; |
374a542d MV |
2654 | } |
2655 | ||
2656 | adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); | |
2657 | ||
2658 | /* Determine if we need to pair queues. */ | |
2659 | switch (hw->mac.type) { | |
2660 | case e1000_82575: | |
f96a8a0b | 2661 | case e1000_i211: |
374a542d | 2662 | /* Device supports enough interrupts without queue pairing. */ |
f96a8a0b | 2663 | break; |
374a542d | 2664 | case e1000_82576: |
b980ac18 | 2665 | /* If VFs are going to be allocated with RSS queues then we |
374a542d MV |
2666 | * should pair the queues in order to conserve interrupts due |
2667 | * to limited supply. | |
2668 | */ | |
2669 | if ((adapter->rss_queues > 1) && | |
2670 | (adapter->vfs_allocated_count > 6)) | |
2671 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
2672 | /* fall through */ | |
2673 | case e1000_82580: | |
2674 | case e1000_i350: | |
ceb5f13b | 2675 | case e1000_i354: |
374a542d | 2676 | case e1000_i210: |
f96a8a0b | 2677 | default: |
b980ac18 | 2678 | /* If rss_queues > half of max_rss_queues, pair the queues in |
374a542d MV |
2679 | * order to conserve interrupts due to limited supply. |
2680 | */ | |
2681 | if (adapter->rss_queues > (max_rss_queues / 2)) | |
2682 | adapter->flags |= IGB_FLAG_QUEUE_PAIRS; | |
f96a8a0b CW |
2683 | break; |
2684 | } | |
fa44f2f1 GR |
2685 | } |
2686 | ||
2687 | /** | |
b980ac18 JK |
2688 | * igb_sw_init - Initialize general software structures (struct igb_adapter) |
2689 | * @adapter: board private structure to initialize | |
fa44f2f1 | 2690 | * |
b980ac18 JK |
2691 | * igb_sw_init initializes the Adapter private data structure. |
2692 | * Fields are initialized based on PCI device information and | |
2693 | * OS network device settings (MTU size). | |
fa44f2f1 GR |
2694 | **/ |
2695 | static int igb_sw_init(struct igb_adapter *adapter) | |
2696 | { | |
2697 | struct e1000_hw *hw = &adapter->hw; | |
2698 | struct net_device *netdev = adapter->netdev; | |
2699 | struct pci_dev *pdev = adapter->pdev; | |
2700 | ||
2701 | pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); | |
2702 | ||
2703 | /* set default ring sizes */ | |
2704 | adapter->tx_ring_count = IGB_DEFAULT_TXD; | |
2705 | adapter->rx_ring_count = IGB_DEFAULT_RXD; | |
2706 | ||
2707 | /* set default ITR values */ | |
2708 | adapter->rx_itr_setting = IGB_DEFAULT_ITR; | |
2709 | adapter->tx_itr_setting = IGB_DEFAULT_ITR; | |
2710 | ||
2711 | /* set default work limits */ | |
2712 | adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; | |
2713 | ||
2714 | adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + | |
2715 | VLAN_HLEN; | |
2716 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; | |
2717 | ||
2718 | spin_lock_init(&adapter->stats64_lock); | |
2719 | #ifdef CONFIG_PCI_IOV | |
2720 | switch (hw->mac.type) { | |
2721 | case e1000_82576: | |
2722 | case e1000_i350: | |
2723 | if (max_vfs > 7) { | |
2724 | dev_warn(&pdev->dev, | |
2725 | "Maximum of 7 VFs per PF, using max\n"); | |
d0f63acc | 2726 | max_vfs = adapter->vfs_allocated_count = 7; |
fa44f2f1 GR |
2727 | } else |
2728 | adapter->vfs_allocated_count = max_vfs; | |
2729 | if (adapter->vfs_allocated_count) | |
2730 | dev_warn(&pdev->dev, | |
2731 | "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); | |
2732 | break; | |
2733 | default: | |
2734 | break; | |
2735 | } | |
2736 | #endif /* CONFIG_PCI_IOV */ | |
2737 | ||
2738 | igb_init_queue_configuration(adapter); | |
a99955fc | 2739 | |
1128c756 | 2740 | /* Setup and initialize a copy of the hw vlan table array */ |
b2adaca9 JP |
2741 | adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), |
2742 | GFP_ATOMIC); | |
1128c756 | 2743 | |
a6b623e0 | 2744 | /* This call may decrease the number of queues */ |
53c7d064 | 2745 | if (igb_init_interrupt_scheme(adapter, true)) { |
9d5c8243 AK |
2746 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
2747 | return -ENOMEM; | |
2748 | } | |
2749 | ||
a6b623e0 AD |
2750 | igb_probe_vfs(adapter); |
2751 | ||
9d5c8243 AK |
2752 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
2753 | igb_irq_disable(adapter); | |
2754 | ||
f96a8a0b | 2755 | if (hw->mac.type >= e1000_i350) |
831ec0b4 CW |
2756 | adapter->flags &= ~IGB_FLAG_DMAC; |
2757 | ||
9d5c8243 AK |
2758 | set_bit(__IGB_DOWN, &adapter->state); |
2759 | return 0; | |
2760 | } | |
2761 | ||
2762 | /** | |
b980ac18 JK |
2763 | * igb_open - Called when a network interface is made active |
2764 | * @netdev: network interface device structure | |
9d5c8243 | 2765 | * |
b980ac18 | 2766 | * Returns 0 on success, negative value on failure |
9d5c8243 | 2767 | * |
b980ac18 JK |
2768 | * The open entry point is called when a network interface is made |
2769 | * active by the system (IFF_UP). At this point all resources needed | |
2770 | * for transmit and receive operations are allocated, the interrupt | |
2771 | * handler is registered with the OS, the watchdog timer is started, | |
2772 | * and the stack is notified that the interface is ready. | |
9d5c8243 | 2773 | **/ |
749ab2cd | 2774 | static int __igb_open(struct net_device *netdev, bool resuming) |
9d5c8243 AK |
2775 | { |
2776 | struct igb_adapter *adapter = netdev_priv(netdev); | |
2777 | struct e1000_hw *hw = &adapter->hw; | |
749ab2cd | 2778 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2779 | int err; |
2780 | int i; | |
2781 | ||
2782 | /* disallow open during test */ | |
749ab2cd YZ |
2783 | if (test_bit(__IGB_TESTING, &adapter->state)) { |
2784 | WARN_ON(resuming); | |
9d5c8243 | 2785 | return -EBUSY; |
749ab2cd YZ |
2786 | } |
2787 | ||
2788 | if (!resuming) | |
2789 | pm_runtime_get_sync(&pdev->dev); | |
9d5c8243 | 2790 | |
b168dfc5 JB |
2791 | netif_carrier_off(netdev); |
2792 | ||
9d5c8243 AK |
2793 | /* allocate transmit descriptors */ |
2794 | err = igb_setup_all_tx_resources(adapter); | |
2795 | if (err) | |
2796 | goto err_setup_tx; | |
2797 | ||
2798 | /* allocate receive descriptors */ | |
2799 | err = igb_setup_all_rx_resources(adapter); | |
2800 | if (err) | |
2801 | goto err_setup_rx; | |
2802 | ||
88a268c1 | 2803 | igb_power_up_link(adapter); |
9d5c8243 | 2804 | |
9d5c8243 AK |
2805 | /* before we allocate an interrupt, we must be ready to handle it. |
2806 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt | |
2807 | * as soon as we call pci_request_irq, so we have to setup our | |
b980ac18 JK |
2808 | * clean_rx handler before we do so. |
2809 | */ | |
9d5c8243 AK |
2810 | igb_configure(adapter); |
2811 | ||
2812 | err = igb_request_irq(adapter); | |
2813 | if (err) | |
2814 | goto err_req_irq; | |
2815 | ||
0c2cc02e AD |
2816 | /* Notify the stack of the actual queue counts. */ |
2817 | err = netif_set_real_num_tx_queues(adapter->netdev, | |
2818 | adapter->num_tx_queues); | |
2819 | if (err) | |
2820 | goto err_set_queues; | |
2821 | ||
2822 | err = netif_set_real_num_rx_queues(adapter->netdev, | |
2823 | adapter->num_rx_queues); | |
2824 | if (err) | |
2825 | goto err_set_queues; | |
2826 | ||
9d5c8243 AK |
2827 | /* From here on the code is the same as igb_up() */ |
2828 | clear_bit(__IGB_DOWN, &adapter->state); | |
2829 | ||
0d1ae7f4 AD |
2830 | for (i = 0; i < adapter->num_q_vectors; i++) |
2831 | napi_enable(&(adapter->q_vector[i]->napi)); | |
9d5c8243 AK |
2832 | |
2833 | /* Clear any pending interrupts. */ | |
2834 | rd32(E1000_ICR); | |
844290e5 PW |
2835 | |
2836 | igb_irq_enable(adapter); | |
2837 | ||
d4960307 AD |
2838 | /* notify VFs that reset has been completed */ |
2839 | if (adapter->vfs_allocated_count) { | |
2840 | u32 reg_data = rd32(E1000_CTRL_EXT); | |
2841 | reg_data |= E1000_CTRL_EXT_PFRSTD; | |
2842 | wr32(E1000_CTRL_EXT, reg_data); | |
2843 | } | |
2844 | ||
d55b53ff JK |
2845 | netif_tx_start_all_queues(netdev); |
2846 | ||
749ab2cd YZ |
2847 | if (!resuming) |
2848 | pm_runtime_put(&pdev->dev); | |
2849 | ||
25568a53 AD |
2850 | /* start the watchdog. */ |
2851 | hw->mac.get_link_status = 1; | |
2852 | schedule_work(&adapter->watchdog_task); | |
9d5c8243 AK |
2853 | |
2854 | return 0; | |
2855 | ||
0c2cc02e AD |
2856 | err_set_queues: |
2857 | igb_free_irq(adapter); | |
9d5c8243 AK |
2858 | err_req_irq: |
2859 | igb_release_hw_control(adapter); | |
88a268c1 | 2860 | igb_power_down_link(adapter); |
9d5c8243 AK |
2861 | igb_free_all_rx_resources(adapter); |
2862 | err_setup_rx: | |
2863 | igb_free_all_tx_resources(adapter); | |
2864 | err_setup_tx: | |
2865 | igb_reset(adapter); | |
749ab2cd YZ |
2866 | if (!resuming) |
2867 | pm_runtime_put(&pdev->dev); | |
9d5c8243 AK |
2868 | |
2869 | return err; | |
2870 | } | |
2871 | ||
749ab2cd YZ |
2872 | static int igb_open(struct net_device *netdev) |
2873 | { | |
2874 | return __igb_open(netdev, false); | |
2875 | } | |
2876 | ||
9d5c8243 | 2877 | /** |
b980ac18 JK |
2878 | * igb_close - Disables a network interface |
2879 | * @netdev: network interface device structure | |
9d5c8243 | 2880 | * |
b980ac18 | 2881 | * Returns 0, this is not allowed to fail |
9d5c8243 | 2882 | * |
b980ac18 JK |
2883 | * The close entry point is called when an interface is de-activated |
2884 | * by the OS. The hardware is still under the driver's control, but | |
2885 | * needs to be disabled. A global MAC reset is issued to stop the | |
2886 | * hardware, and all transmit and receive resources are freed. | |
9d5c8243 | 2887 | **/ |
749ab2cd | 2888 | static int __igb_close(struct net_device *netdev, bool suspending) |
9d5c8243 AK |
2889 | { |
2890 | struct igb_adapter *adapter = netdev_priv(netdev); | |
749ab2cd | 2891 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2892 | |
2893 | WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); | |
9d5c8243 | 2894 | |
749ab2cd YZ |
2895 | if (!suspending) |
2896 | pm_runtime_get_sync(&pdev->dev); | |
2897 | ||
2898 | igb_down(adapter); | |
9d5c8243 AK |
2899 | igb_free_irq(adapter); |
2900 | ||
2901 | igb_free_all_tx_resources(adapter); | |
2902 | igb_free_all_rx_resources(adapter); | |
2903 | ||
749ab2cd YZ |
2904 | if (!suspending) |
2905 | pm_runtime_put_sync(&pdev->dev); | |
9d5c8243 AK |
2906 | return 0; |
2907 | } | |
2908 | ||
749ab2cd YZ |
2909 | static int igb_close(struct net_device *netdev) |
2910 | { | |
2911 | return __igb_close(netdev, false); | |
2912 | } | |
2913 | ||
9d5c8243 | 2914 | /** |
b980ac18 JK |
2915 | * igb_setup_tx_resources - allocate Tx resources (Descriptors) |
2916 | * @tx_ring: tx descriptor ring (for a specific queue) to setup | |
9d5c8243 | 2917 | * |
b980ac18 | 2918 | * Return 0 on success, negative on failure |
9d5c8243 | 2919 | **/ |
80785298 | 2920 | int igb_setup_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 2921 | { |
59d71989 | 2922 | struct device *dev = tx_ring->dev; |
9d5c8243 AK |
2923 | int size; |
2924 | ||
06034649 | 2925 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
f33005a6 AD |
2926 | |
2927 | tx_ring->tx_buffer_info = vzalloc(size); | |
06034649 | 2928 | if (!tx_ring->tx_buffer_info) |
9d5c8243 | 2929 | goto err; |
9d5c8243 AK |
2930 | |
2931 | /* round up to nearest 4K */ | |
85e8d004 | 2932 | tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); |
9d5c8243 AK |
2933 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
2934 | ||
5536d210 AD |
2935 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
2936 | &tx_ring->dma, GFP_KERNEL); | |
9d5c8243 AK |
2937 | if (!tx_ring->desc) |
2938 | goto err; | |
2939 | ||
9d5c8243 AK |
2940 | tx_ring->next_to_use = 0; |
2941 | tx_ring->next_to_clean = 0; | |
81c2fc22 | 2942 | |
9d5c8243 AK |
2943 | return 0; |
2944 | ||
2945 | err: | |
06034649 | 2946 | vfree(tx_ring->tx_buffer_info); |
f33005a6 AD |
2947 | tx_ring->tx_buffer_info = NULL; |
2948 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); | |
9d5c8243 AK |
2949 | return -ENOMEM; |
2950 | } | |
2951 | ||
2952 | /** | |
b980ac18 JK |
2953 | * igb_setup_all_tx_resources - wrapper to allocate Tx resources |
2954 | * (Descriptors) for all queues | |
2955 | * @adapter: board private structure | |
9d5c8243 | 2956 | * |
b980ac18 | 2957 | * Return 0 on success, negative on failure |
9d5c8243 AK |
2958 | **/ |
2959 | static int igb_setup_all_tx_resources(struct igb_adapter *adapter) | |
2960 | { | |
439705e1 | 2961 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
2962 | int i, err = 0; |
2963 | ||
2964 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 2965 | err = igb_setup_tx_resources(adapter->tx_ring[i]); |
9d5c8243 | 2966 | if (err) { |
439705e1 | 2967 | dev_err(&pdev->dev, |
9d5c8243 AK |
2968 | "Allocation for Tx Queue %u failed\n", i); |
2969 | for (i--; i >= 0; i--) | |
3025a446 | 2970 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
2971 | break; |
2972 | } | |
2973 | } | |
2974 | ||
2975 | return err; | |
2976 | } | |
2977 | ||
2978 | /** | |
b980ac18 JK |
2979 | * igb_setup_tctl - configure the transmit control registers |
2980 | * @adapter: Board private structure | |
9d5c8243 | 2981 | **/ |
d7ee5b3a | 2982 | void igb_setup_tctl(struct igb_adapter *adapter) |
9d5c8243 | 2983 | { |
9d5c8243 AK |
2984 | struct e1000_hw *hw = &adapter->hw; |
2985 | u32 tctl; | |
9d5c8243 | 2986 | |
85b430b4 AD |
2987 | /* disable queue 0 which is enabled by default on 82575 and 82576 */ |
2988 | wr32(E1000_TXDCTL(0), 0); | |
9d5c8243 AK |
2989 | |
2990 | /* Program the Transmit Control Register */ | |
9d5c8243 AK |
2991 | tctl = rd32(E1000_TCTL); |
2992 | tctl &= ~E1000_TCTL_CT; | |
2993 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
2994 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
2995 | ||
2996 | igb_config_collision_dist(hw); | |
2997 | ||
9d5c8243 AK |
2998 | /* Enable transmits */ |
2999 | tctl |= E1000_TCTL_EN; | |
3000 | ||
3001 | wr32(E1000_TCTL, tctl); | |
3002 | } | |
3003 | ||
85b430b4 | 3004 | /** |
b980ac18 JK |
3005 | * igb_configure_tx_ring - Configure transmit ring after Reset |
3006 | * @adapter: board private structure | |
3007 | * @ring: tx ring to configure | |
85b430b4 | 3008 | * |
b980ac18 | 3009 | * Configure a transmit ring after a reset. |
85b430b4 | 3010 | **/ |
d7ee5b3a AD |
3011 | void igb_configure_tx_ring(struct igb_adapter *adapter, |
3012 | struct igb_ring *ring) | |
85b430b4 AD |
3013 | { |
3014 | struct e1000_hw *hw = &adapter->hw; | |
a74420e0 | 3015 | u32 txdctl = 0; |
85b430b4 AD |
3016 | u64 tdba = ring->dma; |
3017 | int reg_idx = ring->reg_idx; | |
3018 | ||
3019 | /* disable the queue */ | |
a74420e0 | 3020 | wr32(E1000_TXDCTL(reg_idx), 0); |
85b430b4 AD |
3021 | wrfl(); |
3022 | mdelay(10); | |
3023 | ||
3024 | wr32(E1000_TDLEN(reg_idx), | |
b980ac18 | 3025 | ring->count * sizeof(union e1000_adv_tx_desc)); |
85b430b4 | 3026 | wr32(E1000_TDBAL(reg_idx), |
b980ac18 | 3027 | tdba & 0x00000000ffffffffULL); |
85b430b4 AD |
3028 | wr32(E1000_TDBAH(reg_idx), tdba >> 32); |
3029 | ||
fce99e34 | 3030 | ring->tail = hw->hw_addr + E1000_TDT(reg_idx); |
a74420e0 | 3031 | wr32(E1000_TDH(reg_idx), 0); |
fce99e34 | 3032 | writel(0, ring->tail); |
85b430b4 AD |
3033 | |
3034 | txdctl |= IGB_TX_PTHRESH; | |
3035 | txdctl |= IGB_TX_HTHRESH << 8; | |
3036 | txdctl |= IGB_TX_WTHRESH << 16; | |
3037 | ||
3038 | txdctl |= E1000_TXDCTL_QUEUE_ENABLE; | |
3039 | wr32(E1000_TXDCTL(reg_idx), txdctl); | |
3040 | } | |
3041 | ||
3042 | /** | |
b980ac18 JK |
3043 | * igb_configure_tx - Configure transmit Unit after Reset |
3044 | * @adapter: board private structure | |
85b430b4 | 3045 | * |
b980ac18 | 3046 | * Configure the Tx unit of the MAC after a reset. |
85b430b4 AD |
3047 | **/ |
3048 | static void igb_configure_tx(struct igb_adapter *adapter) | |
3049 | { | |
3050 | int i; | |
3051 | ||
3052 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3053 | igb_configure_tx_ring(adapter, adapter->tx_ring[i]); |
85b430b4 AD |
3054 | } |
3055 | ||
9d5c8243 | 3056 | /** |
b980ac18 JK |
3057 | * igb_setup_rx_resources - allocate Rx resources (Descriptors) |
3058 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
9d5c8243 | 3059 | * |
b980ac18 | 3060 | * Returns 0 on success, negative on failure |
9d5c8243 | 3061 | **/ |
80785298 | 3062 | int igb_setup_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 3063 | { |
59d71989 | 3064 | struct device *dev = rx_ring->dev; |
f33005a6 | 3065 | int size; |
9d5c8243 | 3066 | |
06034649 | 3067 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
f33005a6 AD |
3068 | |
3069 | rx_ring->rx_buffer_info = vzalloc(size); | |
06034649 | 3070 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 3071 | goto err; |
9d5c8243 | 3072 | |
9d5c8243 | 3073 | /* Round up to nearest 4K */ |
f33005a6 | 3074 | rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); |
9d5c8243 AK |
3075 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
3076 | ||
5536d210 AD |
3077 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
3078 | &rx_ring->dma, GFP_KERNEL); | |
9d5c8243 AK |
3079 | if (!rx_ring->desc) |
3080 | goto err; | |
3081 | ||
cbc8e55f | 3082 | rx_ring->next_to_alloc = 0; |
9d5c8243 AK |
3083 | rx_ring->next_to_clean = 0; |
3084 | rx_ring->next_to_use = 0; | |
9d5c8243 | 3085 | |
9d5c8243 AK |
3086 | return 0; |
3087 | ||
3088 | err: | |
06034649 AD |
3089 | vfree(rx_ring->rx_buffer_info); |
3090 | rx_ring->rx_buffer_info = NULL; | |
f33005a6 | 3091 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); |
9d5c8243 AK |
3092 | return -ENOMEM; |
3093 | } | |
3094 | ||
3095 | /** | |
b980ac18 JK |
3096 | * igb_setup_all_rx_resources - wrapper to allocate Rx resources |
3097 | * (Descriptors) for all queues | |
3098 | * @adapter: board private structure | |
9d5c8243 | 3099 | * |
b980ac18 | 3100 | * Return 0 on success, negative on failure |
9d5c8243 AK |
3101 | **/ |
3102 | static int igb_setup_all_rx_resources(struct igb_adapter *adapter) | |
3103 | { | |
439705e1 | 3104 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
3105 | int i, err = 0; |
3106 | ||
3107 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
3025a446 | 3108 | err = igb_setup_rx_resources(adapter->rx_ring[i]); |
9d5c8243 | 3109 | if (err) { |
439705e1 | 3110 | dev_err(&pdev->dev, |
9d5c8243 AK |
3111 | "Allocation for Rx Queue %u failed\n", i); |
3112 | for (i--; i >= 0; i--) | |
3025a446 | 3113 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3114 | break; |
3115 | } | |
3116 | } | |
3117 | ||
3118 | return err; | |
3119 | } | |
3120 | ||
06cf2666 | 3121 | /** |
b980ac18 JK |
3122 | * igb_setup_mrqc - configure the multiple receive queue control registers |
3123 | * @adapter: Board private structure | |
06cf2666 AD |
3124 | **/ |
3125 | static void igb_setup_mrqc(struct igb_adapter *adapter) | |
3126 | { | |
3127 | struct e1000_hw *hw = &adapter->hw; | |
3128 | u32 mrqc, rxcsum; | |
797fd4be | 3129 | u32 j, num_rx_queues, shift = 0; |
a57fe23e AD |
3130 | static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, |
3131 | 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, | |
3132 | 0xA32DCB77, 0x0CF23080, 0x3BB7426A, | |
3133 | 0xFA01ACBE }; | |
06cf2666 AD |
3134 | |
3135 | /* Fill out hash function seeds */ | |
a57fe23e AD |
3136 | for (j = 0; j < 10; j++) |
3137 | wr32(E1000_RSSRK(j), rsskey[j]); | |
06cf2666 | 3138 | |
a99955fc | 3139 | num_rx_queues = adapter->rss_queues; |
06cf2666 | 3140 | |
797fd4be AD |
3141 | switch (hw->mac.type) { |
3142 | case e1000_82575: | |
3143 | shift = 6; | |
3144 | break; | |
3145 | case e1000_82576: | |
3146 | /* 82576 supports 2 RSS queues for SR-IOV */ | |
3147 | if (adapter->vfs_allocated_count) { | |
06cf2666 AD |
3148 | shift = 3; |
3149 | num_rx_queues = 2; | |
06cf2666 | 3150 | } |
797fd4be AD |
3151 | break; |
3152 | default: | |
3153 | break; | |
06cf2666 AD |
3154 | } |
3155 | ||
b980ac18 | 3156 | /* Populate the indirection table 4 entries at a time. To do this |
797fd4be AD |
3157 | * we are generating the results for n and n+2 and then interleaving |
3158 | * those with the results with n+1 and n+3. | |
3159 | */ | |
c342b39e | 3160 | for (j = 0; j < IGB_RETA_SIZE / 4; j++) { |
797fd4be AD |
3161 | /* first pass generates n and n+2 */ |
3162 | u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; | |
3163 | u32 reta = (base & 0x07800780) >> (7 - shift); | |
3164 | ||
3165 | /* second pass generates n+1 and n+3 */ | |
3166 | base += 0x00010001 * num_rx_queues; | |
3167 | reta |= (base & 0x07800780) << (1 + shift); | |
3168 | ||
3169 | wr32(E1000_RETA(j), reta); | |
06cf2666 AD |
3170 | } |
3171 | ||
b980ac18 | 3172 | /* Disable raw packet checksumming so that RSS hash is placed in |
06cf2666 AD |
3173 | * descriptor on writeback. No need to enable TCP/UDP/IP checksum |
3174 | * offloads as they are enabled by default | |
3175 | */ | |
3176 | rxcsum = rd32(E1000_RXCSUM); | |
3177 | rxcsum |= E1000_RXCSUM_PCSD; | |
3178 | ||
3179 | if (adapter->hw.mac.type >= e1000_82576) | |
3180 | /* Enable Receive Checksum Offload for SCTP */ | |
3181 | rxcsum |= E1000_RXCSUM_CRCOFL; | |
3182 | ||
3183 | /* Don't need to set TUOFL or IPOFL, they default to 1 */ | |
3184 | wr32(E1000_RXCSUM, rxcsum); | |
f96a8a0b | 3185 | |
039454a8 AA |
3186 | /* Generate RSS hash based on packet types, TCP/UDP |
3187 | * port numbers and/or IPv4/v6 src and dst addresses | |
3188 | */ | |
f96a8a0b CW |
3189 | mrqc = E1000_MRQC_RSS_FIELD_IPV4 | |
3190 | E1000_MRQC_RSS_FIELD_IPV4_TCP | | |
3191 | E1000_MRQC_RSS_FIELD_IPV6 | | |
3192 | E1000_MRQC_RSS_FIELD_IPV6_TCP | | |
3193 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; | |
06cf2666 | 3194 | |
039454a8 AA |
3195 | if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) |
3196 | mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; | |
3197 | if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) | |
3198 | mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; | |
3199 | ||
06cf2666 AD |
3200 | /* If VMDq is enabled then we set the appropriate mode for that, else |
3201 | * we default to RSS so that an RSS hash is calculated per packet even | |
b980ac18 JK |
3202 | * if we are only using one queue |
3203 | */ | |
06cf2666 AD |
3204 | if (adapter->vfs_allocated_count) { |
3205 | if (hw->mac.type > e1000_82575) { | |
3206 | /* Set the default pool for the PF's first queue */ | |
3207 | u32 vtctl = rd32(E1000_VT_CTL); | |
3208 | vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | | |
3209 | E1000_VT_CTL_DISABLE_DEF_POOL); | |
3210 | vtctl |= adapter->vfs_allocated_count << | |
3211 | E1000_VT_CTL_DEFAULT_POOL_SHIFT; | |
3212 | wr32(E1000_VT_CTL, vtctl); | |
3213 | } | |
a99955fc | 3214 | if (adapter->rss_queues > 1) |
f96a8a0b | 3215 | mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; |
06cf2666 | 3216 | else |
f96a8a0b | 3217 | mrqc |= E1000_MRQC_ENABLE_VMDQ; |
06cf2666 | 3218 | } else { |
f96a8a0b CW |
3219 | if (hw->mac.type != e1000_i211) |
3220 | mrqc |= E1000_MRQC_ENABLE_RSS_4Q; | |
06cf2666 AD |
3221 | } |
3222 | igb_vmm_control(adapter); | |
3223 | ||
06cf2666 AD |
3224 | wr32(E1000_MRQC, mrqc); |
3225 | } | |
3226 | ||
9d5c8243 | 3227 | /** |
b980ac18 JK |
3228 | * igb_setup_rctl - configure the receive control registers |
3229 | * @adapter: Board private structure | |
9d5c8243 | 3230 | **/ |
d7ee5b3a | 3231 | void igb_setup_rctl(struct igb_adapter *adapter) |
9d5c8243 AK |
3232 | { |
3233 | struct e1000_hw *hw = &adapter->hw; | |
3234 | u32 rctl; | |
9d5c8243 AK |
3235 | |
3236 | rctl = rd32(E1000_RCTL); | |
3237 | ||
3238 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
69d728ba | 3239 | rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); |
9d5c8243 | 3240 | |
69d728ba | 3241 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | |
28b0759c | 3242 | (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); |
9d5c8243 | 3243 | |
b980ac18 | 3244 | /* enable stripping of CRC. It's unlikely this will break BMC |
87cb7e8c AK |
3245 | * redirection as it did with e1000. Newer features require |
3246 | * that the HW strips the CRC. | |
73cd78f1 | 3247 | */ |
87cb7e8c | 3248 | rctl |= E1000_RCTL_SECRC; |
9d5c8243 | 3249 | |
559e9c49 | 3250 | /* disable store bad packets and clear size bits. */ |
ec54d7d6 | 3251 | rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); |
9d5c8243 | 3252 | |
6ec43fe6 AD |
3253 | /* enable LPE to prevent packets larger than max_frame_size */ |
3254 | rctl |= E1000_RCTL_LPE; | |
9d5c8243 | 3255 | |
952f72a8 AD |
3256 | /* disable queue 0 to prevent tail write w/o re-config */ |
3257 | wr32(E1000_RXDCTL(0), 0); | |
9d5c8243 | 3258 | |
e1739522 AD |
3259 | /* Attention!!! For SR-IOV PF driver operations you must enable |
3260 | * queue drop for all VF and PF queues to prevent head of line blocking | |
3261 | * if an un-trusted VF does not provide descriptors to hardware. | |
3262 | */ | |
3263 | if (adapter->vfs_allocated_count) { | |
e1739522 AD |
3264 | /* set all queue drop enable bits */ |
3265 | wr32(E1000_QDE, ALL_QUEUES); | |
e1739522 AD |
3266 | } |
3267 | ||
89eaefb6 BG |
3268 | /* This is useful for sniffing bad packets. */ |
3269 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3270 | /* UPE and MPE will be handled by normal PROMISC logic | |
b980ac18 JK |
3271 | * in e1000e_set_rx_mode |
3272 | */ | |
89eaefb6 BG |
3273 | rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ |
3274 | E1000_RCTL_BAM | /* RX All Bcast Pkts */ | |
3275 | E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3276 | ||
3277 | rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ | |
3278 | E1000_RCTL_DPF | /* Allow filtered pause */ | |
3279 | E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ | |
3280 | /* Do not mess with E1000_CTRL_VME, it affects transmit as well, | |
3281 | * and that breaks VLANs. | |
3282 | */ | |
3283 | } | |
3284 | ||
9d5c8243 AK |
3285 | wr32(E1000_RCTL, rctl); |
3286 | } | |
3287 | ||
7d5753f0 AD |
3288 | static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, |
3289 | int vfn) | |
3290 | { | |
3291 | struct e1000_hw *hw = &adapter->hw; | |
3292 | u32 vmolr; | |
3293 | ||
3294 | /* if it isn't the PF check to see if VFs are enabled and | |
b980ac18 JK |
3295 | * increase the size to support vlan tags |
3296 | */ | |
7d5753f0 AD |
3297 | if (vfn < adapter->vfs_allocated_count && |
3298 | adapter->vf_data[vfn].vlans_enabled) | |
3299 | size += VLAN_TAG_SIZE; | |
3300 | ||
3301 | vmolr = rd32(E1000_VMOLR(vfn)); | |
3302 | vmolr &= ~E1000_VMOLR_RLPML_MASK; | |
3303 | vmolr |= size | E1000_VMOLR_LPE; | |
3304 | wr32(E1000_VMOLR(vfn), vmolr); | |
3305 | ||
3306 | return 0; | |
3307 | } | |
3308 | ||
e1739522 | 3309 | /** |
b980ac18 JK |
3310 | * igb_rlpml_set - set maximum receive packet size |
3311 | * @adapter: board private structure | |
e1739522 | 3312 | * |
b980ac18 | 3313 | * Configure maximum receivable packet size. |
e1739522 AD |
3314 | **/ |
3315 | static void igb_rlpml_set(struct igb_adapter *adapter) | |
3316 | { | |
153285f9 | 3317 | u32 max_frame_size = adapter->max_frame_size; |
e1739522 AD |
3318 | struct e1000_hw *hw = &adapter->hw; |
3319 | u16 pf_id = adapter->vfs_allocated_count; | |
3320 | ||
e1739522 AD |
3321 | if (pf_id) { |
3322 | igb_set_vf_rlpml(adapter, max_frame_size, pf_id); | |
b980ac18 | 3323 | /* If we're in VMDQ or SR-IOV mode, then set global RLPML |
153285f9 AD |
3324 | * to our max jumbo frame size, in case we need to enable |
3325 | * jumbo frames on one of the rings later. | |
3326 | * This will not pass over-length frames into the default | |
3327 | * queue because it's gated by the VMOLR.RLPML. | |
3328 | */ | |
7d5753f0 | 3329 | max_frame_size = MAX_JUMBO_FRAME_SIZE; |
e1739522 AD |
3330 | } |
3331 | ||
3332 | wr32(E1000_RLPML, max_frame_size); | |
3333 | } | |
3334 | ||
8151d294 WM |
3335 | static inline void igb_set_vmolr(struct igb_adapter *adapter, |
3336 | int vfn, bool aupe) | |
7d5753f0 AD |
3337 | { |
3338 | struct e1000_hw *hw = &adapter->hw; | |
3339 | u32 vmolr; | |
3340 | ||
b980ac18 | 3341 | /* This register exists only on 82576 and newer so if we are older then |
7d5753f0 AD |
3342 | * we should exit and do nothing |
3343 | */ | |
3344 | if (hw->mac.type < e1000_82576) | |
3345 | return; | |
3346 | ||
3347 | vmolr = rd32(E1000_VMOLR(vfn)); | |
b980ac18 | 3348 | vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ |
8151d294 | 3349 | if (aupe) |
b980ac18 | 3350 | vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ |
8151d294 WM |
3351 | else |
3352 | vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ | |
7d5753f0 AD |
3353 | |
3354 | /* clear all bits that might not be set */ | |
3355 | vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); | |
3356 | ||
a99955fc | 3357 | if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) |
7d5753f0 | 3358 | vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ |
b980ac18 | 3359 | /* for VMDq only allow the VFs and pool 0 to accept broadcast and |
7d5753f0 AD |
3360 | * multicast packets |
3361 | */ | |
3362 | if (vfn <= adapter->vfs_allocated_count) | |
b980ac18 | 3363 | vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ |
7d5753f0 AD |
3364 | |
3365 | wr32(E1000_VMOLR(vfn), vmolr); | |
3366 | } | |
3367 | ||
85b430b4 | 3368 | /** |
b980ac18 JK |
3369 | * igb_configure_rx_ring - Configure a receive ring after Reset |
3370 | * @adapter: board private structure | |
3371 | * @ring: receive ring to be configured | |
85b430b4 | 3372 | * |
b980ac18 | 3373 | * Configure the Rx unit of the MAC after a reset. |
85b430b4 | 3374 | **/ |
d7ee5b3a | 3375 | void igb_configure_rx_ring(struct igb_adapter *adapter, |
b980ac18 | 3376 | struct igb_ring *ring) |
85b430b4 AD |
3377 | { |
3378 | struct e1000_hw *hw = &adapter->hw; | |
3379 | u64 rdba = ring->dma; | |
3380 | int reg_idx = ring->reg_idx; | |
a74420e0 | 3381 | u32 srrctl = 0, rxdctl = 0; |
85b430b4 AD |
3382 | |
3383 | /* disable the queue */ | |
a74420e0 | 3384 | wr32(E1000_RXDCTL(reg_idx), 0); |
85b430b4 AD |
3385 | |
3386 | /* Set DMA base address registers */ | |
3387 | wr32(E1000_RDBAL(reg_idx), | |
3388 | rdba & 0x00000000ffffffffULL); | |
3389 | wr32(E1000_RDBAH(reg_idx), rdba >> 32); | |
3390 | wr32(E1000_RDLEN(reg_idx), | |
b980ac18 | 3391 | ring->count * sizeof(union e1000_adv_rx_desc)); |
85b430b4 AD |
3392 | |
3393 | /* initialize head and tail */ | |
fce99e34 | 3394 | ring->tail = hw->hw_addr + E1000_RDT(reg_idx); |
a74420e0 | 3395 | wr32(E1000_RDH(reg_idx), 0); |
fce99e34 | 3396 | writel(0, ring->tail); |
85b430b4 | 3397 | |
952f72a8 | 3398 | /* set descriptor configuration */ |
44390ca6 | 3399 | srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; |
de78d1f9 | 3400 | srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; |
1a1c225b | 3401 | srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; |
06218a8d | 3402 | if (hw->mac.type >= e1000_82580) |
757b77e2 | 3403 | srrctl |= E1000_SRRCTL_TIMESTAMP; |
e6bdb6fe NN |
3404 | /* Only set Drop Enable if we are supporting multiple queues */ |
3405 | if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) | |
3406 | srrctl |= E1000_SRRCTL_DROP_EN; | |
952f72a8 AD |
3407 | |
3408 | wr32(E1000_SRRCTL(reg_idx), srrctl); | |
3409 | ||
7d5753f0 | 3410 | /* set filtering for VMDQ pools */ |
8151d294 | 3411 | igb_set_vmolr(adapter, reg_idx & 0x7, true); |
7d5753f0 | 3412 | |
85b430b4 AD |
3413 | rxdctl |= IGB_RX_PTHRESH; |
3414 | rxdctl |= IGB_RX_HTHRESH << 8; | |
3415 | rxdctl |= IGB_RX_WTHRESH << 16; | |
a74420e0 AD |
3416 | |
3417 | /* enable receive descriptor fetching */ | |
3418 | rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; | |
85b430b4 AD |
3419 | wr32(E1000_RXDCTL(reg_idx), rxdctl); |
3420 | } | |
3421 | ||
9d5c8243 | 3422 | /** |
b980ac18 JK |
3423 | * igb_configure_rx - Configure receive Unit after Reset |
3424 | * @adapter: board private structure | |
9d5c8243 | 3425 | * |
b980ac18 | 3426 | * Configure the Rx unit of the MAC after a reset. |
9d5c8243 AK |
3427 | **/ |
3428 | static void igb_configure_rx(struct igb_adapter *adapter) | |
3429 | { | |
9107584e | 3430 | int i; |
9d5c8243 | 3431 | |
68d480c4 AD |
3432 | /* set UTA to appropriate mode */ |
3433 | igb_set_uta(adapter); | |
3434 | ||
26ad9178 AD |
3435 | /* set the correct pool for the PF default MAC address in entry 0 */ |
3436 | igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, | |
b980ac18 | 3437 | adapter->vfs_allocated_count); |
26ad9178 | 3438 | |
06cf2666 | 3439 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
b980ac18 JK |
3440 | * the Base and Length of the Rx Descriptor Ring |
3441 | */ | |
f9d40f6a AD |
3442 | for (i = 0; i < adapter->num_rx_queues; i++) |
3443 | igb_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
9d5c8243 AK |
3444 | } |
3445 | ||
3446 | /** | |
b980ac18 JK |
3447 | * igb_free_tx_resources - Free Tx Resources per Queue |
3448 | * @tx_ring: Tx descriptor ring for a specific queue | |
9d5c8243 | 3449 | * |
b980ac18 | 3450 | * Free all transmit software resources |
9d5c8243 | 3451 | **/ |
68fd9910 | 3452 | void igb_free_tx_resources(struct igb_ring *tx_ring) |
9d5c8243 | 3453 | { |
3b644cf6 | 3454 | igb_clean_tx_ring(tx_ring); |
9d5c8243 | 3455 | |
06034649 AD |
3456 | vfree(tx_ring->tx_buffer_info); |
3457 | tx_ring->tx_buffer_info = NULL; | |
9d5c8243 | 3458 | |
439705e1 AD |
3459 | /* if not set, then don't free */ |
3460 | if (!tx_ring->desc) | |
3461 | return; | |
3462 | ||
59d71989 AD |
3463 | dma_free_coherent(tx_ring->dev, tx_ring->size, |
3464 | tx_ring->desc, tx_ring->dma); | |
9d5c8243 AK |
3465 | |
3466 | tx_ring->desc = NULL; | |
3467 | } | |
3468 | ||
3469 | /** | |
b980ac18 JK |
3470 | * igb_free_all_tx_resources - Free Tx Resources for All Queues |
3471 | * @adapter: board private structure | |
9d5c8243 | 3472 | * |
b980ac18 | 3473 | * Free all transmit software resources |
9d5c8243 AK |
3474 | **/ |
3475 | static void igb_free_all_tx_resources(struct igb_adapter *adapter) | |
3476 | { | |
3477 | int i; | |
3478 | ||
3479 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3480 | igb_free_tx_resources(adapter->tx_ring[i]); |
9d5c8243 AK |
3481 | } |
3482 | ||
ebe42d16 AD |
3483 | void igb_unmap_and_free_tx_resource(struct igb_ring *ring, |
3484 | struct igb_tx_buffer *tx_buffer) | |
3485 | { | |
3486 | if (tx_buffer->skb) { | |
3487 | dev_kfree_skb_any(tx_buffer->skb); | |
c9f14bf3 | 3488 | if (dma_unmap_len(tx_buffer, len)) |
ebe42d16 | 3489 | dma_unmap_single(ring->dev, |
c9f14bf3 AD |
3490 | dma_unmap_addr(tx_buffer, dma), |
3491 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 | 3492 | DMA_TO_DEVICE); |
c9f14bf3 | 3493 | } else if (dma_unmap_len(tx_buffer, len)) { |
ebe42d16 | 3494 | dma_unmap_page(ring->dev, |
c9f14bf3 AD |
3495 | dma_unmap_addr(tx_buffer, dma), |
3496 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 AD |
3497 | DMA_TO_DEVICE); |
3498 | } | |
3499 | tx_buffer->next_to_watch = NULL; | |
3500 | tx_buffer->skb = NULL; | |
c9f14bf3 | 3501 | dma_unmap_len_set(tx_buffer, len, 0); |
ebe42d16 | 3502 | /* buffer_info must be completely set up in the transmit path */ |
9d5c8243 AK |
3503 | } |
3504 | ||
3505 | /** | |
b980ac18 JK |
3506 | * igb_clean_tx_ring - Free Tx Buffers |
3507 | * @tx_ring: ring to be cleaned | |
9d5c8243 | 3508 | **/ |
3b644cf6 | 3509 | static void igb_clean_tx_ring(struct igb_ring *tx_ring) |
9d5c8243 | 3510 | { |
06034649 | 3511 | struct igb_tx_buffer *buffer_info; |
9d5c8243 | 3512 | unsigned long size; |
6ad4edfc | 3513 | u16 i; |
9d5c8243 | 3514 | |
06034649 | 3515 | if (!tx_ring->tx_buffer_info) |
9d5c8243 AK |
3516 | return; |
3517 | /* Free all the Tx ring sk_buffs */ | |
3518 | ||
3519 | for (i = 0; i < tx_ring->count; i++) { | |
06034649 | 3520 | buffer_info = &tx_ring->tx_buffer_info[i]; |
80785298 | 3521 | igb_unmap_and_free_tx_resource(tx_ring, buffer_info); |
9d5c8243 AK |
3522 | } |
3523 | ||
dad8a3b3 JF |
3524 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
3525 | ||
06034649 AD |
3526 | size = sizeof(struct igb_tx_buffer) * tx_ring->count; |
3527 | memset(tx_ring->tx_buffer_info, 0, size); | |
9d5c8243 AK |
3528 | |
3529 | /* Zero out the descriptor ring */ | |
9d5c8243 AK |
3530 | memset(tx_ring->desc, 0, tx_ring->size); |
3531 | ||
3532 | tx_ring->next_to_use = 0; | |
3533 | tx_ring->next_to_clean = 0; | |
9d5c8243 AK |
3534 | } |
3535 | ||
3536 | /** | |
b980ac18 JK |
3537 | * igb_clean_all_tx_rings - Free Tx Buffers for all queues |
3538 | * @adapter: board private structure | |
9d5c8243 AK |
3539 | **/ |
3540 | static void igb_clean_all_tx_rings(struct igb_adapter *adapter) | |
3541 | { | |
3542 | int i; | |
3543 | ||
3544 | for (i = 0; i < adapter->num_tx_queues; i++) | |
3025a446 | 3545 | igb_clean_tx_ring(adapter->tx_ring[i]); |
9d5c8243 AK |
3546 | } |
3547 | ||
3548 | /** | |
b980ac18 JK |
3549 | * igb_free_rx_resources - Free Rx Resources |
3550 | * @rx_ring: ring to clean the resources from | |
9d5c8243 | 3551 | * |
b980ac18 | 3552 | * Free all receive software resources |
9d5c8243 | 3553 | **/ |
68fd9910 | 3554 | void igb_free_rx_resources(struct igb_ring *rx_ring) |
9d5c8243 | 3555 | { |
3b644cf6 | 3556 | igb_clean_rx_ring(rx_ring); |
9d5c8243 | 3557 | |
06034649 AD |
3558 | vfree(rx_ring->rx_buffer_info); |
3559 | rx_ring->rx_buffer_info = NULL; | |
9d5c8243 | 3560 | |
439705e1 AD |
3561 | /* if not set, then don't free */ |
3562 | if (!rx_ring->desc) | |
3563 | return; | |
3564 | ||
59d71989 AD |
3565 | dma_free_coherent(rx_ring->dev, rx_ring->size, |
3566 | rx_ring->desc, rx_ring->dma); | |
9d5c8243 AK |
3567 | |
3568 | rx_ring->desc = NULL; | |
3569 | } | |
3570 | ||
3571 | /** | |
b980ac18 JK |
3572 | * igb_free_all_rx_resources - Free Rx Resources for All Queues |
3573 | * @adapter: board private structure | |
9d5c8243 | 3574 | * |
b980ac18 | 3575 | * Free all receive software resources |
9d5c8243 AK |
3576 | **/ |
3577 | static void igb_free_all_rx_resources(struct igb_adapter *adapter) | |
3578 | { | |
3579 | int i; | |
3580 | ||
3581 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3582 | igb_free_rx_resources(adapter->rx_ring[i]); |
9d5c8243 AK |
3583 | } |
3584 | ||
3585 | /** | |
b980ac18 JK |
3586 | * igb_clean_rx_ring - Free Rx Buffers per Queue |
3587 | * @rx_ring: ring to free buffers from | |
9d5c8243 | 3588 | **/ |
3b644cf6 | 3589 | static void igb_clean_rx_ring(struct igb_ring *rx_ring) |
9d5c8243 | 3590 | { |
9d5c8243 | 3591 | unsigned long size; |
c023cd88 | 3592 | u16 i; |
9d5c8243 | 3593 | |
1a1c225b AD |
3594 | if (rx_ring->skb) |
3595 | dev_kfree_skb(rx_ring->skb); | |
3596 | rx_ring->skb = NULL; | |
3597 | ||
06034649 | 3598 | if (!rx_ring->rx_buffer_info) |
9d5c8243 | 3599 | return; |
439705e1 | 3600 | |
9d5c8243 AK |
3601 | /* Free all the Rx ring sk_buffs */ |
3602 | for (i = 0; i < rx_ring->count; i++) { | |
06034649 | 3603 | struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; |
9d5c8243 | 3604 | |
cbc8e55f AD |
3605 | if (!buffer_info->page) |
3606 | continue; | |
3607 | ||
3608 | dma_unmap_page(rx_ring->dev, | |
3609 | buffer_info->dma, | |
3610 | PAGE_SIZE, | |
3611 | DMA_FROM_DEVICE); | |
3612 | __free_page(buffer_info->page); | |
3613 | ||
1a1c225b | 3614 | buffer_info->page = NULL; |
9d5c8243 AK |
3615 | } |
3616 | ||
06034649 AD |
3617 | size = sizeof(struct igb_rx_buffer) * rx_ring->count; |
3618 | memset(rx_ring->rx_buffer_info, 0, size); | |
9d5c8243 AK |
3619 | |
3620 | /* Zero out the descriptor ring */ | |
3621 | memset(rx_ring->desc, 0, rx_ring->size); | |
3622 | ||
cbc8e55f | 3623 | rx_ring->next_to_alloc = 0; |
9d5c8243 AK |
3624 | rx_ring->next_to_clean = 0; |
3625 | rx_ring->next_to_use = 0; | |
9d5c8243 AK |
3626 | } |
3627 | ||
3628 | /** | |
b980ac18 JK |
3629 | * igb_clean_all_rx_rings - Free Rx Buffers for all queues |
3630 | * @adapter: board private structure | |
9d5c8243 AK |
3631 | **/ |
3632 | static void igb_clean_all_rx_rings(struct igb_adapter *adapter) | |
3633 | { | |
3634 | int i; | |
3635 | ||
3636 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3025a446 | 3637 | igb_clean_rx_ring(adapter->rx_ring[i]); |
9d5c8243 AK |
3638 | } |
3639 | ||
3640 | /** | |
b980ac18 JK |
3641 | * igb_set_mac - Change the Ethernet Address of the NIC |
3642 | * @netdev: network interface device structure | |
3643 | * @p: pointer to an address structure | |
9d5c8243 | 3644 | * |
b980ac18 | 3645 | * Returns 0 on success, negative on failure |
9d5c8243 AK |
3646 | **/ |
3647 | static int igb_set_mac(struct net_device *netdev, void *p) | |
3648 | { | |
3649 | struct igb_adapter *adapter = netdev_priv(netdev); | |
28b0759c | 3650 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 AK |
3651 | struct sockaddr *addr = p; |
3652 | ||
3653 | if (!is_valid_ether_addr(addr->sa_data)) | |
3654 | return -EADDRNOTAVAIL; | |
3655 | ||
3656 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
28b0759c | 3657 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9d5c8243 | 3658 | |
26ad9178 AD |
3659 | /* set the correct pool for the new PF MAC address in entry 0 */ |
3660 | igb_rar_set_qsel(adapter, hw->mac.addr, 0, | |
b980ac18 | 3661 | adapter->vfs_allocated_count); |
e1739522 | 3662 | |
9d5c8243 AK |
3663 | return 0; |
3664 | } | |
3665 | ||
3666 | /** | |
b980ac18 JK |
3667 | * igb_write_mc_addr_list - write multicast addresses to MTA |
3668 | * @netdev: network interface device structure | |
9d5c8243 | 3669 | * |
b980ac18 JK |
3670 | * Writes multicast address list to the MTA hash table. |
3671 | * Returns: -ENOMEM on failure | |
3672 | * 0 on no addresses written | |
3673 | * X on writing X addresses to MTA | |
9d5c8243 | 3674 | **/ |
68d480c4 | 3675 | static int igb_write_mc_addr_list(struct net_device *netdev) |
9d5c8243 AK |
3676 | { |
3677 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3678 | struct e1000_hw *hw = &adapter->hw; | |
22bedad3 | 3679 | struct netdev_hw_addr *ha; |
68d480c4 | 3680 | u8 *mta_list; |
9d5c8243 AK |
3681 | int i; |
3682 | ||
4cd24eaf | 3683 | if (netdev_mc_empty(netdev)) { |
68d480c4 AD |
3684 | /* nothing to program, so clear mc list */ |
3685 | igb_update_mc_addr_list(hw, NULL, 0); | |
3686 | igb_restore_vf_multicasts(adapter); | |
3687 | return 0; | |
3688 | } | |
9d5c8243 | 3689 | |
4cd24eaf | 3690 | mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); |
68d480c4 AD |
3691 | if (!mta_list) |
3692 | return -ENOMEM; | |
ff41f8dc | 3693 | |
68d480c4 | 3694 | /* The shared function expects a packed array of only addresses. */ |
48e2f183 | 3695 | i = 0; |
22bedad3 JP |
3696 | netdev_for_each_mc_addr(ha, netdev) |
3697 | memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); | |
68d480c4 | 3698 | |
68d480c4 AD |
3699 | igb_update_mc_addr_list(hw, mta_list, i); |
3700 | kfree(mta_list); | |
3701 | ||
4cd24eaf | 3702 | return netdev_mc_count(netdev); |
68d480c4 AD |
3703 | } |
3704 | ||
3705 | /** | |
b980ac18 JK |
3706 | * igb_write_uc_addr_list - write unicast addresses to RAR table |
3707 | * @netdev: network interface device structure | |
68d480c4 | 3708 | * |
b980ac18 JK |
3709 | * Writes unicast address list to the RAR table. |
3710 | * Returns: -ENOMEM on failure/insufficient address space | |
3711 | * 0 on no addresses written | |
3712 | * X on writing X addresses to the RAR table | |
68d480c4 AD |
3713 | **/ |
3714 | static int igb_write_uc_addr_list(struct net_device *netdev) | |
3715 | { | |
3716 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3717 | struct e1000_hw *hw = &adapter->hw; | |
3718 | unsigned int vfn = adapter->vfs_allocated_count; | |
3719 | unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); | |
3720 | int count = 0; | |
3721 | ||
3722 | /* return ENOMEM indicating insufficient memory for addresses */ | |
32e7bfc4 | 3723 | if (netdev_uc_count(netdev) > rar_entries) |
68d480c4 | 3724 | return -ENOMEM; |
9d5c8243 | 3725 | |
32e7bfc4 | 3726 | if (!netdev_uc_empty(netdev) && rar_entries) { |
ff41f8dc | 3727 | struct netdev_hw_addr *ha; |
32e7bfc4 JP |
3728 | |
3729 | netdev_for_each_uc_addr(ha, netdev) { | |
ff41f8dc AD |
3730 | if (!rar_entries) |
3731 | break; | |
26ad9178 | 3732 | igb_rar_set_qsel(adapter, ha->addr, |
b980ac18 JK |
3733 | rar_entries--, |
3734 | vfn); | |
68d480c4 | 3735 | count++; |
ff41f8dc AD |
3736 | } |
3737 | } | |
3738 | /* write the addresses in reverse order to avoid write combining */ | |
3739 | for (; rar_entries > 0 ; rar_entries--) { | |
3740 | wr32(E1000_RAH(rar_entries), 0); | |
3741 | wr32(E1000_RAL(rar_entries), 0); | |
3742 | } | |
3743 | wrfl(); | |
3744 | ||
68d480c4 AD |
3745 | return count; |
3746 | } | |
3747 | ||
3748 | /** | |
b980ac18 JK |
3749 | * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set |
3750 | * @netdev: network interface device structure | |
68d480c4 | 3751 | * |
b980ac18 JK |
3752 | * The set_rx_mode entry point is called whenever the unicast or multicast |
3753 | * address lists or the network interface flags are updated. This routine is | |
3754 | * responsible for configuring the hardware for proper unicast, multicast, | |
3755 | * promiscuous mode, and all-multi behavior. | |
68d480c4 AD |
3756 | **/ |
3757 | static void igb_set_rx_mode(struct net_device *netdev) | |
3758 | { | |
3759 | struct igb_adapter *adapter = netdev_priv(netdev); | |
3760 | struct e1000_hw *hw = &adapter->hw; | |
3761 | unsigned int vfn = adapter->vfs_allocated_count; | |
3762 | u32 rctl, vmolr = 0; | |
3763 | int count; | |
3764 | ||
3765 | /* Check for Promiscuous and All Multicast modes */ | |
3766 | rctl = rd32(E1000_RCTL); | |
3767 | ||
3768 | /* clear the effected bits */ | |
3769 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); | |
3770 | ||
3771 | if (netdev->flags & IFF_PROMISC) { | |
6f3dc319 | 3772 | /* retain VLAN HW filtering if in VT mode */ |
7e44892c | 3773 | if (adapter->vfs_allocated_count) |
6f3dc319 | 3774 | rctl |= E1000_RCTL_VFE; |
68d480c4 AD |
3775 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); |
3776 | vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); | |
3777 | } else { | |
3778 | if (netdev->flags & IFF_ALLMULTI) { | |
3779 | rctl |= E1000_RCTL_MPE; | |
3780 | vmolr |= E1000_VMOLR_MPME; | |
3781 | } else { | |
b980ac18 | 3782 | /* Write addresses to the MTA, if the attempt fails |
25985edc | 3783 | * then we should just turn on promiscuous mode so |
68d480c4 AD |
3784 | * that we can at least receive multicast traffic |
3785 | */ | |
3786 | count = igb_write_mc_addr_list(netdev); | |
3787 | if (count < 0) { | |
3788 | rctl |= E1000_RCTL_MPE; | |
3789 | vmolr |= E1000_VMOLR_MPME; | |
3790 | } else if (count) { | |
3791 | vmolr |= E1000_VMOLR_ROMPE; | |
3792 | } | |
3793 | } | |
b980ac18 | 3794 | /* Write addresses to available RAR registers, if there is not |
68d480c4 | 3795 | * sufficient space to store all the addresses then enable |
25985edc | 3796 | * unicast promiscuous mode |
68d480c4 AD |
3797 | */ |
3798 | count = igb_write_uc_addr_list(netdev); | |
3799 | if (count < 0) { | |
3800 | rctl |= E1000_RCTL_UPE; | |
3801 | vmolr |= E1000_VMOLR_ROPE; | |
3802 | } | |
3803 | rctl |= E1000_RCTL_VFE; | |
28fc06f5 | 3804 | } |
68d480c4 | 3805 | wr32(E1000_RCTL, rctl); |
28fc06f5 | 3806 | |
b980ac18 | 3807 | /* In order to support SR-IOV and eventually VMDq it is necessary to set |
68d480c4 AD |
3808 | * the VMOLR to enable the appropriate modes. Without this workaround |
3809 | * we will have issues with VLAN tag stripping not being done for frames | |
3810 | * that are only arriving because we are the default pool | |
3811 | */ | |
f96a8a0b | 3812 | if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) |
28fc06f5 | 3813 | return; |
9d5c8243 | 3814 | |
68d480c4 | 3815 | vmolr |= rd32(E1000_VMOLR(vfn)) & |
b980ac18 | 3816 | ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); |
68d480c4 | 3817 | wr32(E1000_VMOLR(vfn), vmolr); |
28fc06f5 | 3818 | igb_restore_vf_multicasts(adapter); |
9d5c8243 AK |
3819 | } |
3820 | ||
13800469 GR |
3821 | static void igb_check_wvbr(struct igb_adapter *adapter) |
3822 | { | |
3823 | struct e1000_hw *hw = &adapter->hw; | |
3824 | u32 wvbr = 0; | |
3825 | ||
3826 | switch (hw->mac.type) { | |
3827 | case e1000_82576: | |
3828 | case e1000_i350: | |
3829 | if (!(wvbr = rd32(E1000_WVBR))) | |
3830 | return; | |
3831 | break; | |
3832 | default: | |
3833 | break; | |
3834 | } | |
3835 | ||
3836 | adapter->wvbr |= wvbr; | |
3837 | } | |
3838 | ||
3839 | #define IGB_STAGGERED_QUEUE_OFFSET 8 | |
3840 | ||
3841 | static void igb_spoof_check(struct igb_adapter *adapter) | |
3842 | { | |
3843 | int j; | |
3844 | ||
3845 | if (!adapter->wvbr) | |
3846 | return; | |
3847 | ||
3848 | for(j = 0; j < adapter->vfs_allocated_count; j++) { | |
3849 | if (adapter->wvbr & (1 << j) || | |
3850 | adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { | |
3851 | dev_warn(&adapter->pdev->dev, | |
3852 | "Spoof event(s) detected on VF %d\n", j); | |
3853 | adapter->wvbr &= | |
3854 | ~((1 << j) | | |
3855 | (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); | |
3856 | } | |
3857 | } | |
3858 | } | |
3859 | ||
9d5c8243 | 3860 | /* Need to wait a few seconds after link up to get diagnostic information from |
b980ac18 JK |
3861 | * the phy |
3862 | */ | |
9d5c8243 AK |
3863 | static void igb_update_phy_info(unsigned long data) |
3864 | { | |
3865 | struct igb_adapter *adapter = (struct igb_adapter *) data; | |
f5f4cf08 | 3866 | igb_get_phy_info(&adapter->hw); |
9d5c8243 AK |
3867 | } |
3868 | ||
4d6b725e | 3869 | /** |
b980ac18 JK |
3870 | * igb_has_link - check shared code for link and determine up/down |
3871 | * @adapter: pointer to driver private info | |
4d6b725e | 3872 | **/ |
3145535a | 3873 | bool igb_has_link(struct igb_adapter *adapter) |
4d6b725e AD |
3874 | { |
3875 | struct e1000_hw *hw = &adapter->hw; | |
3876 | bool link_active = false; | |
4d6b725e AD |
3877 | |
3878 | /* get_link_status is set on LSC (link status) interrupt or | |
3879 | * rx sequence error interrupt. get_link_status will stay | |
3880 | * false until the e1000_check_for_link establishes link | |
3881 | * for copper adapters ONLY | |
3882 | */ | |
3883 | switch (hw->phy.media_type) { | |
3884 | case e1000_media_type_copper: | |
e5c3370f AA |
3885 | if (!hw->mac.get_link_status) |
3886 | return true; | |
4d6b725e | 3887 | case e1000_media_type_internal_serdes: |
e5c3370f AA |
3888 | hw->mac.ops.check_for_link(hw); |
3889 | link_active = !hw->mac.get_link_status; | |
4d6b725e AD |
3890 | break; |
3891 | default: | |
3892 | case e1000_media_type_unknown: | |
3893 | break; | |
3894 | } | |
3895 | ||
3896 | return link_active; | |
3897 | } | |
3898 | ||
563988dc SA |
3899 | static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) |
3900 | { | |
3901 | bool ret = false; | |
3902 | u32 ctrl_ext, thstat; | |
3903 | ||
f96a8a0b | 3904 | /* check for thermal sensor event on i350 copper only */ |
563988dc SA |
3905 | if (hw->mac.type == e1000_i350) { |
3906 | thstat = rd32(E1000_THSTAT); | |
3907 | ctrl_ext = rd32(E1000_CTRL_EXT); | |
3908 | ||
3909 | if ((hw->phy.media_type == e1000_media_type_copper) && | |
5c17a203 | 3910 | !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) |
563988dc | 3911 | ret = !!(thstat & event); |
563988dc SA |
3912 | } |
3913 | ||
3914 | return ret; | |
3915 | } | |
3916 | ||
9d5c8243 | 3917 | /** |
b980ac18 JK |
3918 | * igb_watchdog - Timer Call-back |
3919 | * @data: pointer to adapter cast into an unsigned long | |
9d5c8243 AK |
3920 | **/ |
3921 | static void igb_watchdog(unsigned long data) | |
3922 | { | |
3923 | struct igb_adapter *adapter = (struct igb_adapter *)data; | |
3924 | /* Do the rest outside of interrupt context */ | |
3925 | schedule_work(&adapter->watchdog_task); | |
3926 | } | |
3927 | ||
3928 | static void igb_watchdog_task(struct work_struct *work) | |
3929 | { | |
3930 | struct igb_adapter *adapter = container_of(work, | |
b980ac18 JK |
3931 | struct igb_adapter, |
3932 | watchdog_task); | |
9d5c8243 | 3933 | struct e1000_hw *hw = &adapter->hw; |
c0ba4778 | 3934 | struct e1000_phy_info *phy = &hw->phy; |
9d5c8243 | 3935 | struct net_device *netdev = adapter->netdev; |
563988dc | 3936 | u32 link; |
7a6ea550 | 3937 | int i; |
9d5c8243 | 3938 | |
4d6b725e | 3939 | link = igb_has_link(adapter); |
9d5c8243 | 3940 | if (link) { |
749ab2cd YZ |
3941 | /* Cancel scheduled suspend requests. */ |
3942 | pm_runtime_resume(netdev->dev.parent); | |
3943 | ||
9d5c8243 AK |
3944 | if (!netif_carrier_ok(netdev)) { |
3945 | u32 ctrl; | |
330a6d6a | 3946 | hw->mac.ops.get_speed_and_duplex(hw, |
b980ac18 JK |
3947 | &adapter->link_speed, |
3948 | &adapter->link_duplex); | |
9d5c8243 AK |
3949 | |
3950 | ctrl = rd32(E1000_CTRL); | |
527d47c1 | 3951 | /* Links status message must follow this format */ |
876d2d6f JK |
3952 | printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " |
3953 | "Duplex, Flow Control: %s\n", | |
559e9c49 AD |
3954 | netdev->name, |
3955 | adapter->link_speed, | |
3956 | adapter->link_duplex == FULL_DUPLEX ? | |
876d2d6f JK |
3957 | "Full" : "Half", |
3958 | (ctrl & E1000_CTRL_TFCE) && | |
3959 | (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : | |
3960 | (ctrl & E1000_CTRL_RFCE) ? "RX" : | |
3961 | (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); | |
9d5c8243 | 3962 | |
c0ba4778 KS |
3963 | /* check if SmartSpeed worked */ |
3964 | igb_check_downshift(hw); | |
3965 | if (phy->speed_downgraded) | |
3966 | netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); | |
3967 | ||
563988dc | 3968 | /* check for thermal sensor event */ |
876d2d6f JK |
3969 | if (igb_thermal_sensor_event(hw, |
3970 | E1000_THSTAT_LINK_THROTTLE)) { | |
3971 | netdev_info(netdev, "The network adapter link " | |
3972 | "speed was downshifted because it " | |
3973 | "overheated\n"); | |
7ef5ed1c | 3974 | } |
563988dc | 3975 | |
d07f3e37 | 3976 | /* adjust timeout factor according to speed/duplex */ |
9d5c8243 AK |
3977 | adapter->tx_timeout_factor = 1; |
3978 | switch (adapter->link_speed) { | |
3979 | case SPEED_10: | |
9d5c8243 AK |
3980 | adapter->tx_timeout_factor = 14; |
3981 | break; | |
3982 | case SPEED_100: | |
9d5c8243 AK |
3983 | /* maybe add some timeout factor ? */ |
3984 | break; | |
3985 | } | |
3986 | ||
3987 | netif_carrier_on(netdev); | |
9d5c8243 | 3988 | |
4ae196df | 3989 | igb_ping_all_vfs(adapter); |
17dc566c | 3990 | igb_check_vf_rate_limit(adapter); |
4ae196df | 3991 | |
4b1a9877 | 3992 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
3993 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
3994 | mod_timer(&adapter->phy_info_timer, | |
3995 | round_jiffies(jiffies + 2 * HZ)); | |
3996 | } | |
3997 | } else { | |
3998 | if (netif_carrier_ok(netdev)) { | |
3999 | adapter->link_speed = 0; | |
4000 | adapter->link_duplex = 0; | |
563988dc SA |
4001 | |
4002 | /* check for thermal sensor event */ | |
876d2d6f JK |
4003 | if (igb_thermal_sensor_event(hw, |
4004 | E1000_THSTAT_PWR_DOWN)) { | |
4005 | netdev_err(netdev, "The network adapter was " | |
4006 | "stopped because it overheated\n"); | |
7ef5ed1c | 4007 | } |
563988dc | 4008 | |
527d47c1 AD |
4009 | /* Links status message must follow this format */ |
4010 | printk(KERN_INFO "igb: %s NIC Link is Down\n", | |
4011 | netdev->name); | |
9d5c8243 | 4012 | netif_carrier_off(netdev); |
4b1a9877 | 4013 | |
4ae196df AD |
4014 | igb_ping_all_vfs(adapter); |
4015 | ||
4b1a9877 | 4016 | /* link state has changed, schedule phy info update */ |
9d5c8243 AK |
4017 | if (!test_bit(__IGB_DOWN, &adapter->state)) |
4018 | mod_timer(&adapter->phy_info_timer, | |
4019 | round_jiffies(jiffies + 2 * HZ)); | |
749ab2cd YZ |
4020 | |
4021 | pm_schedule_suspend(netdev->dev.parent, | |
4022 | MSEC_PER_SEC * 5); | |
9d5c8243 AK |
4023 | } |
4024 | } | |
4025 | ||
12dcd86b ED |
4026 | spin_lock(&adapter->stats64_lock); |
4027 | igb_update_stats(adapter, &adapter->stats64); | |
4028 | spin_unlock(&adapter->stats64_lock); | |
9d5c8243 | 4029 | |
dbabb065 | 4030 | for (i = 0; i < adapter->num_tx_queues; i++) { |
3025a446 | 4031 | struct igb_ring *tx_ring = adapter->tx_ring[i]; |
dbabb065 | 4032 | if (!netif_carrier_ok(netdev)) { |
9d5c8243 AK |
4033 | /* We've lost link, so the controller stops DMA, |
4034 | * but we've got queued Tx work that's never going | |
4035 | * to get done, so reset controller to flush Tx. | |
b980ac18 JK |
4036 | * (Do the reset outside of interrupt context). |
4037 | */ | |
dbabb065 AD |
4038 | if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { |
4039 | adapter->tx_timeout_count++; | |
4040 | schedule_work(&adapter->reset_task); | |
4041 | /* return immediately since reset is imminent */ | |
4042 | return; | |
4043 | } | |
9d5c8243 | 4044 | } |
9d5c8243 | 4045 | |
dbabb065 | 4046 | /* Force detection of hung controller every watchdog period */ |
6d095fa8 | 4047 | set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
dbabb065 | 4048 | } |
f7ba205e | 4049 | |
b980ac18 | 4050 | /* Cause software interrupt to ensure Rx ring is cleaned */ |
7a6ea550 | 4051 | if (adapter->msix_entries) { |
047e0030 | 4052 | u32 eics = 0; |
0d1ae7f4 AD |
4053 | for (i = 0; i < adapter->num_q_vectors; i++) |
4054 | eics |= adapter->q_vector[i]->eims_value; | |
7a6ea550 AD |
4055 | wr32(E1000_EICS, eics); |
4056 | } else { | |
4057 | wr32(E1000_ICS, E1000_ICS_RXDMT0); | |
4058 | } | |
9d5c8243 | 4059 | |
13800469 | 4060 | igb_spoof_check(adapter); |
fc580751 | 4061 | igb_ptp_rx_hang(adapter); |
13800469 | 4062 | |
9d5c8243 AK |
4063 | /* Reset the timer */ |
4064 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
4065 | mod_timer(&adapter->watchdog_timer, | |
4066 | round_jiffies(jiffies + 2 * HZ)); | |
4067 | } | |
4068 | ||
4069 | enum latency_range { | |
4070 | lowest_latency = 0, | |
4071 | low_latency = 1, | |
4072 | bulk_latency = 2, | |
4073 | latency_invalid = 255 | |
4074 | }; | |
4075 | ||
6eb5a7f1 | 4076 | /** |
b980ac18 JK |
4077 | * igb_update_ring_itr - update the dynamic ITR value based on packet size |
4078 | * @q_vector: pointer to q_vector | |
6eb5a7f1 | 4079 | * |
b980ac18 JK |
4080 | * Stores a new ITR value based on strictly on packet size. This |
4081 | * algorithm is less sophisticated than that used in igb_update_itr, | |
4082 | * due to the difficulty of synchronizing statistics across multiple | |
4083 | * receive rings. The divisors and thresholds used by this function | |
4084 | * were determined based on theoretical maximum wire speed and testing | |
4085 | * data, in order to minimize response time while increasing bulk | |
4086 | * throughput. | |
4087 | * This functionality is controlled by the InterruptThrottleRate module | |
4088 | * parameter (see igb_param.c) | |
4089 | * NOTE: This function is called only when operating in a multiqueue | |
4090 | * receive environment. | |
6eb5a7f1 | 4091 | **/ |
047e0030 | 4092 | static void igb_update_ring_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4093 | { |
047e0030 | 4094 | int new_val = q_vector->itr_val; |
6eb5a7f1 | 4095 | int avg_wire_size = 0; |
047e0030 | 4096 | struct igb_adapter *adapter = q_vector->adapter; |
12dcd86b | 4097 | unsigned int packets; |
9d5c8243 | 4098 | |
6eb5a7f1 AD |
4099 | /* For non-gigabit speeds, just fix the interrupt rate at 4000 |
4100 | * ints/sec - ITR timer value of 120 ticks. | |
4101 | */ | |
4102 | if (adapter->link_speed != SPEED_1000) { | |
0ba82994 | 4103 | new_val = IGB_4K_ITR; |
6eb5a7f1 | 4104 | goto set_itr_val; |
9d5c8243 | 4105 | } |
047e0030 | 4106 | |
0ba82994 AD |
4107 | packets = q_vector->rx.total_packets; |
4108 | if (packets) | |
4109 | avg_wire_size = q_vector->rx.total_bytes / packets; | |
047e0030 | 4110 | |
0ba82994 AD |
4111 | packets = q_vector->tx.total_packets; |
4112 | if (packets) | |
4113 | avg_wire_size = max_t(u32, avg_wire_size, | |
4114 | q_vector->tx.total_bytes / packets); | |
047e0030 AD |
4115 | |
4116 | /* if avg_wire_size isn't set no work was done */ | |
4117 | if (!avg_wire_size) | |
4118 | goto clear_counts; | |
9d5c8243 | 4119 | |
6eb5a7f1 AD |
4120 | /* Add 24 bytes to size to account for CRC, preamble, and gap */ |
4121 | avg_wire_size += 24; | |
4122 | ||
4123 | /* Don't starve jumbo frames */ | |
4124 | avg_wire_size = min(avg_wire_size, 3000); | |
9d5c8243 | 4125 | |
6eb5a7f1 AD |
4126 | /* Give a little boost to mid-size frames */ |
4127 | if ((avg_wire_size > 300) && (avg_wire_size < 1200)) | |
4128 | new_val = avg_wire_size / 3; | |
4129 | else | |
4130 | new_val = avg_wire_size / 2; | |
9d5c8243 | 4131 | |
0ba82994 AD |
4132 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
4133 | if (new_val < IGB_20K_ITR && | |
4134 | ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || | |
4135 | (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) | |
4136 | new_val = IGB_20K_ITR; | |
abe1c363 | 4137 | |
6eb5a7f1 | 4138 | set_itr_val: |
047e0030 AD |
4139 | if (new_val != q_vector->itr_val) { |
4140 | q_vector->itr_val = new_val; | |
4141 | q_vector->set_itr = 1; | |
9d5c8243 | 4142 | } |
6eb5a7f1 | 4143 | clear_counts: |
0ba82994 AD |
4144 | q_vector->rx.total_bytes = 0; |
4145 | q_vector->rx.total_packets = 0; | |
4146 | q_vector->tx.total_bytes = 0; | |
4147 | q_vector->tx.total_packets = 0; | |
9d5c8243 AK |
4148 | } |
4149 | ||
4150 | /** | |
b980ac18 JK |
4151 | * igb_update_itr - update the dynamic ITR value based on statistics |
4152 | * @q_vector: pointer to q_vector | |
4153 | * @ring_container: ring info to update the itr for | |
4154 | * | |
4155 | * Stores a new ITR value based on packets and byte | |
4156 | * counts during the last interrupt. The advantage of per interrupt | |
4157 | * computation is faster updates and more accurate ITR for the current | |
4158 | * traffic pattern. Constants in this function were computed | |
4159 | * based on theoretical maximum wire speed and thresholds were set based | |
4160 | * on testing data as well as attempting to minimize response time | |
4161 | * while increasing bulk throughput. | |
4162 | * this functionality is controlled by the InterruptThrottleRate module | |
4163 | * parameter (see igb_param.c) | |
4164 | * NOTE: These calculations are only valid when operating in a single- | |
4165 | * queue environment. | |
9d5c8243 | 4166 | **/ |
0ba82994 AD |
4167 | static void igb_update_itr(struct igb_q_vector *q_vector, |
4168 | struct igb_ring_container *ring_container) | |
9d5c8243 | 4169 | { |
0ba82994 AD |
4170 | unsigned int packets = ring_container->total_packets; |
4171 | unsigned int bytes = ring_container->total_bytes; | |
4172 | u8 itrval = ring_container->itr; | |
9d5c8243 | 4173 | |
0ba82994 | 4174 | /* no packets, exit with status unchanged */ |
9d5c8243 | 4175 | if (packets == 0) |
0ba82994 | 4176 | return; |
9d5c8243 | 4177 | |
0ba82994 | 4178 | switch (itrval) { |
9d5c8243 AK |
4179 | case lowest_latency: |
4180 | /* handle TSO and jumbo frames */ | |
4181 | if (bytes/packets > 8000) | |
0ba82994 | 4182 | itrval = bulk_latency; |
9d5c8243 | 4183 | else if ((packets < 5) && (bytes > 512)) |
0ba82994 | 4184 | itrval = low_latency; |
9d5c8243 AK |
4185 | break; |
4186 | case low_latency: /* 50 usec aka 20000 ints/s */ | |
4187 | if (bytes > 10000) { | |
4188 | /* this if handles the TSO accounting */ | |
4189 | if (bytes/packets > 8000) { | |
0ba82994 | 4190 | itrval = bulk_latency; |
9d5c8243 | 4191 | } else if ((packets < 10) || ((bytes/packets) > 1200)) { |
0ba82994 | 4192 | itrval = bulk_latency; |
9d5c8243 | 4193 | } else if ((packets > 35)) { |
0ba82994 | 4194 | itrval = lowest_latency; |
9d5c8243 AK |
4195 | } |
4196 | } else if (bytes/packets > 2000) { | |
0ba82994 | 4197 | itrval = bulk_latency; |
9d5c8243 | 4198 | } else if (packets <= 2 && bytes < 512) { |
0ba82994 | 4199 | itrval = lowest_latency; |
9d5c8243 AK |
4200 | } |
4201 | break; | |
4202 | case bulk_latency: /* 250 usec aka 4000 ints/s */ | |
4203 | if (bytes > 25000) { | |
4204 | if (packets > 35) | |
0ba82994 | 4205 | itrval = low_latency; |
1e5c3d21 | 4206 | } else if (bytes < 1500) { |
0ba82994 | 4207 | itrval = low_latency; |
9d5c8243 AK |
4208 | } |
4209 | break; | |
4210 | } | |
4211 | ||
0ba82994 AD |
4212 | /* clear work counters since we have the values we need */ |
4213 | ring_container->total_bytes = 0; | |
4214 | ring_container->total_packets = 0; | |
4215 | ||
4216 | /* write updated itr to ring container */ | |
4217 | ring_container->itr = itrval; | |
9d5c8243 AK |
4218 | } |
4219 | ||
0ba82994 | 4220 | static void igb_set_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 4221 | { |
0ba82994 | 4222 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 4223 | u32 new_itr = q_vector->itr_val; |
0ba82994 | 4224 | u8 current_itr = 0; |
9d5c8243 AK |
4225 | |
4226 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
4227 | if (adapter->link_speed != SPEED_1000) { | |
4228 | current_itr = 0; | |
0ba82994 | 4229 | new_itr = IGB_4K_ITR; |
9d5c8243 AK |
4230 | goto set_itr_now; |
4231 | } | |
4232 | ||
0ba82994 AD |
4233 | igb_update_itr(q_vector, &q_vector->tx); |
4234 | igb_update_itr(q_vector, &q_vector->rx); | |
9d5c8243 | 4235 | |
0ba82994 | 4236 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
9d5c8243 | 4237 | |
6eb5a7f1 | 4238 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
0ba82994 AD |
4239 | if (current_itr == lowest_latency && |
4240 | ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || | |
4241 | (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) | |
6eb5a7f1 AD |
4242 | current_itr = low_latency; |
4243 | ||
9d5c8243 AK |
4244 | switch (current_itr) { |
4245 | /* counts and packets in update_itr are dependent on these numbers */ | |
4246 | case lowest_latency: | |
0ba82994 | 4247 | new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ |
9d5c8243 AK |
4248 | break; |
4249 | case low_latency: | |
0ba82994 | 4250 | new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ |
9d5c8243 AK |
4251 | break; |
4252 | case bulk_latency: | |
0ba82994 | 4253 | new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ |
9d5c8243 AK |
4254 | break; |
4255 | default: | |
4256 | break; | |
4257 | } | |
4258 | ||
4259 | set_itr_now: | |
047e0030 | 4260 | if (new_itr != q_vector->itr_val) { |
9d5c8243 AK |
4261 | /* this attempts to bias the interrupt rate towards Bulk |
4262 | * by adding intermediate steps when interrupt rate is | |
b980ac18 JK |
4263 | * increasing |
4264 | */ | |
047e0030 | 4265 | new_itr = new_itr > q_vector->itr_val ? |
b980ac18 JK |
4266 | max((new_itr * q_vector->itr_val) / |
4267 | (new_itr + (q_vector->itr_val >> 2)), | |
4268 | new_itr) : new_itr; | |
9d5c8243 AK |
4269 | /* Don't write the value here; it resets the adapter's |
4270 | * internal timer, and causes us to delay far longer than | |
4271 | * we should between interrupts. Instead, we write the ITR | |
4272 | * value at the beginning of the next interrupt so the timing | |
4273 | * ends up being correct. | |
4274 | */ | |
047e0030 AD |
4275 | q_vector->itr_val = new_itr; |
4276 | q_vector->set_itr = 1; | |
9d5c8243 | 4277 | } |
9d5c8243 AK |
4278 | } |
4279 | ||
c50b52a0 SH |
4280 | static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, |
4281 | u32 type_tucmd, u32 mss_l4len_idx) | |
7d13a7d0 AD |
4282 | { |
4283 | struct e1000_adv_tx_context_desc *context_desc; | |
4284 | u16 i = tx_ring->next_to_use; | |
4285 | ||
4286 | context_desc = IGB_TX_CTXTDESC(tx_ring, i); | |
4287 | ||
4288 | i++; | |
4289 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
4290 | ||
4291 | /* set bits to identify this as an advanced context descriptor */ | |
4292 | type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; | |
4293 | ||
4294 | /* For 82575, context index must be unique per ring. */ | |
866cff06 | 4295 | if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) |
7d13a7d0 AD |
4296 | mss_l4len_idx |= tx_ring->reg_idx << 4; |
4297 | ||
4298 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); | |
4299 | context_desc->seqnum_seed = 0; | |
4300 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
4301 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
4302 | } | |
4303 | ||
7af40ad9 AD |
4304 | static int igb_tso(struct igb_ring *tx_ring, |
4305 | struct igb_tx_buffer *first, | |
4306 | u8 *hdr_len) | |
9d5c8243 | 4307 | { |
7af40ad9 | 4308 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
4309 | u32 vlan_macip_lens, type_tucmd; |
4310 | u32 mss_l4len_idx, l4len; | |
4311 | ||
ed6aa105 AD |
4312 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
4313 | return 0; | |
4314 | ||
7d13a7d0 AD |
4315 | if (!skb_is_gso(skb)) |
4316 | return 0; | |
9d5c8243 AK |
4317 | |
4318 | if (skb_header_cloned(skb)) { | |
7af40ad9 | 4319 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
9d5c8243 AK |
4320 | if (err) |
4321 | return err; | |
4322 | } | |
4323 | ||
7d13a7d0 AD |
4324 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
4325 | type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; | |
9d5c8243 | 4326 | |
7af40ad9 | 4327 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
9d5c8243 AK |
4328 | struct iphdr *iph = ip_hdr(skb); |
4329 | iph->tot_len = 0; | |
4330 | iph->check = 0; | |
4331 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
4332 | iph->daddr, 0, | |
4333 | IPPROTO_TCP, | |
4334 | 0); | |
7d13a7d0 | 4335 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; |
7af40ad9 AD |
4336 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4337 | IGB_TX_FLAGS_CSUM | | |
4338 | IGB_TX_FLAGS_IPV4; | |
8e1e8a47 | 4339 | } else if (skb_is_gso_v6(skb)) { |
9d5c8243 AK |
4340 | ipv6_hdr(skb)->payload_len = 0; |
4341 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
4342 | &ipv6_hdr(skb)->daddr, | |
4343 | 0, IPPROTO_TCP, 0); | |
7af40ad9 AD |
4344 | first->tx_flags |= IGB_TX_FLAGS_TSO | |
4345 | IGB_TX_FLAGS_CSUM; | |
9d5c8243 AK |
4346 | } |
4347 | ||
7af40ad9 | 4348 | /* compute header lengths */ |
7d13a7d0 AD |
4349 | l4len = tcp_hdrlen(skb); |
4350 | *hdr_len = skb_transport_offset(skb) + l4len; | |
9d5c8243 | 4351 | |
7af40ad9 AD |
4352 | /* update gso size and bytecount with header size */ |
4353 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
4354 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
4355 | ||
9d5c8243 | 4356 | /* MSS L4LEN IDX */ |
7d13a7d0 AD |
4357 | mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; |
4358 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; | |
9d5c8243 | 4359 | |
7d13a7d0 AD |
4360 | /* VLAN MACLEN IPLEN */ |
4361 | vlan_macip_lens = skb_network_header_len(skb); | |
4362 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; | |
7af40ad9 | 4363 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4364 | |
7d13a7d0 | 4365 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 | 4366 | |
7d13a7d0 | 4367 | return 1; |
9d5c8243 AK |
4368 | } |
4369 | ||
7af40ad9 | 4370 | static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) |
9d5c8243 | 4371 | { |
7af40ad9 | 4372 | struct sk_buff *skb = first->skb; |
7d13a7d0 AD |
4373 | u32 vlan_macip_lens = 0; |
4374 | u32 mss_l4len_idx = 0; | |
4375 | u32 type_tucmd = 0; | |
9d5c8243 | 4376 | |
7d13a7d0 | 4377 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
7af40ad9 AD |
4378 | if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) |
4379 | return; | |
7d13a7d0 AD |
4380 | } else { |
4381 | u8 l4_hdr = 0; | |
7af40ad9 | 4382 | switch (first->protocol) { |
7d13a7d0 AD |
4383 | case __constant_htons(ETH_P_IP): |
4384 | vlan_macip_lens |= skb_network_header_len(skb); | |
4385 | type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; | |
4386 | l4_hdr = ip_hdr(skb)->protocol; | |
4387 | break; | |
4388 | case __constant_htons(ETH_P_IPV6): | |
4389 | vlan_macip_lens |= skb_network_header_len(skb); | |
4390 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
4391 | break; | |
4392 | default: | |
4393 | if (unlikely(net_ratelimit())) { | |
4394 | dev_warn(tx_ring->dev, | |
b980ac18 JK |
4395 | "partial checksum but proto=%x!\n", |
4396 | first->protocol); | |
fa4a7ef3 | 4397 | } |
7d13a7d0 AD |
4398 | break; |
4399 | } | |
fa4a7ef3 | 4400 | |
7d13a7d0 AD |
4401 | switch (l4_hdr) { |
4402 | case IPPROTO_TCP: | |
4403 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; | |
4404 | mss_l4len_idx = tcp_hdrlen(skb) << | |
4405 | E1000_ADVTXD_L4LEN_SHIFT; | |
4406 | break; | |
4407 | case IPPROTO_SCTP: | |
4408 | type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; | |
4409 | mss_l4len_idx = sizeof(struct sctphdr) << | |
4410 | E1000_ADVTXD_L4LEN_SHIFT; | |
4411 | break; | |
4412 | case IPPROTO_UDP: | |
4413 | mss_l4len_idx = sizeof(struct udphdr) << | |
4414 | E1000_ADVTXD_L4LEN_SHIFT; | |
4415 | break; | |
4416 | default: | |
4417 | if (unlikely(net_ratelimit())) { | |
4418 | dev_warn(tx_ring->dev, | |
b980ac18 JK |
4419 | "partial checksum but l4 proto=%x!\n", |
4420 | l4_hdr); | |
44b0cda3 | 4421 | } |
7d13a7d0 | 4422 | break; |
9d5c8243 | 4423 | } |
7af40ad9 AD |
4424 | |
4425 | /* update TX checksum flag */ | |
4426 | first->tx_flags |= IGB_TX_FLAGS_CSUM; | |
7d13a7d0 | 4427 | } |
9d5c8243 | 4428 | |
7d13a7d0 | 4429 | vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; |
7af40ad9 | 4430 | vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; |
9d5c8243 | 4431 | |
7d13a7d0 | 4432 | igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); |
9d5c8243 AK |
4433 | } |
4434 | ||
1d9daf45 AD |
4435 | #define IGB_SET_FLAG(_input, _flag, _result) \ |
4436 | ((_flag <= _result) ? \ | |
4437 | ((u32)(_input & _flag) * (_result / _flag)) : \ | |
4438 | ((u32)(_input & _flag) / (_flag / _result))) | |
4439 | ||
4440 | static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) | |
e032afc8 AD |
4441 | { |
4442 | /* set type for advanced descriptor with frame checksum insertion */ | |
1d9daf45 AD |
4443 | u32 cmd_type = E1000_ADVTXD_DTYP_DATA | |
4444 | E1000_ADVTXD_DCMD_DEXT | | |
4445 | E1000_ADVTXD_DCMD_IFCS; | |
e032afc8 AD |
4446 | |
4447 | /* set HW vlan bit if vlan is present */ | |
1d9daf45 AD |
4448 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, |
4449 | (E1000_ADVTXD_DCMD_VLE)); | |
4450 | ||
4451 | /* set segmentation bits for TSO */ | |
4452 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, | |
4453 | (E1000_ADVTXD_DCMD_TSE)); | |
e032afc8 AD |
4454 | |
4455 | /* set timestamp bit if present */ | |
1d9daf45 AD |
4456 | cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, |
4457 | (E1000_ADVTXD_MAC_TSTAMP)); | |
e032afc8 | 4458 | |
1d9daf45 AD |
4459 | /* insert frame checksum */ |
4460 | cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); | |
e032afc8 AD |
4461 | |
4462 | return cmd_type; | |
4463 | } | |
4464 | ||
7af40ad9 AD |
4465 | static void igb_tx_olinfo_status(struct igb_ring *tx_ring, |
4466 | union e1000_adv_tx_desc *tx_desc, | |
4467 | u32 tx_flags, unsigned int paylen) | |
e032afc8 AD |
4468 | { |
4469 | u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; | |
4470 | ||
1d9daf45 AD |
4471 | /* 82575 requires a unique index per ring */ |
4472 | if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) | |
e032afc8 AD |
4473 | olinfo_status |= tx_ring->reg_idx << 4; |
4474 | ||
4475 | /* insert L4 checksum */ | |
1d9daf45 AD |
4476 | olinfo_status |= IGB_SET_FLAG(tx_flags, |
4477 | IGB_TX_FLAGS_CSUM, | |
4478 | (E1000_TXD_POPTS_TXSM << 8)); | |
e032afc8 | 4479 | |
1d9daf45 AD |
4480 | /* insert IPv4 checksum */ |
4481 | olinfo_status |= IGB_SET_FLAG(tx_flags, | |
4482 | IGB_TX_FLAGS_IPV4, | |
4483 | (E1000_TXD_POPTS_IXSM << 8)); | |
e032afc8 | 4484 | |
7af40ad9 | 4485 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
e032afc8 AD |
4486 | } |
4487 | ||
7af40ad9 AD |
4488 | static void igb_tx_map(struct igb_ring *tx_ring, |
4489 | struct igb_tx_buffer *first, | |
ebe42d16 | 4490 | const u8 hdr_len) |
9d5c8243 | 4491 | { |
7af40ad9 | 4492 | struct sk_buff *skb = first->skb; |
c9f14bf3 | 4493 | struct igb_tx_buffer *tx_buffer; |
ebe42d16 | 4494 | union e1000_adv_tx_desc *tx_desc; |
80d0759e | 4495 | struct skb_frag_struct *frag; |
ebe42d16 | 4496 | dma_addr_t dma; |
80d0759e | 4497 | unsigned int data_len, size; |
7af40ad9 | 4498 | u32 tx_flags = first->tx_flags; |
1d9daf45 | 4499 | u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); |
ebe42d16 | 4500 | u16 i = tx_ring->next_to_use; |
ebe42d16 AD |
4501 | |
4502 | tx_desc = IGB_TX_DESC(tx_ring, i); | |
4503 | ||
80d0759e AD |
4504 | igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); |
4505 | ||
4506 | size = skb_headlen(skb); | |
4507 | data_len = skb->data_len; | |
ebe42d16 AD |
4508 | |
4509 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
9d5c8243 | 4510 | |
80d0759e AD |
4511 | tx_buffer = first; |
4512 | ||
4513 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
4514 | if (dma_mapping_error(tx_ring->dev, dma)) | |
4515 | goto dma_error; | |
4516 | ||
4517 | /* record length, and DMA address */ | |
4518 | dma_unmap_len_set(tx_buffer, len, size); | |
4519 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
4520 | ||
4521 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
ebe42d16 | 4522 | |
ebe42d16 AD |
4523 | while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { |
4524 | tx_desc->read.cmd_type_len = | |
1d9daf45 | 4525 | cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); |
ebe42d16 AD |
4526 | |
4527 | i++; | |
4528 | tx_desc++; | |
4529 | if (i == tx_ring->count) { | |
4530 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
4531 | i = 0; | |
4532 | } | |
80d0759e | 4533 | tx_desc->read.olinfo_status = 0; |
ebe42d16 AD |
4534 | |
4535 | dma += IGB_MAX_DATA_PER_TXD; | |
4536 | size -= IGB_MAX_DATA_PER_TXD; | |
4537 | ||
ebe42d16 AD |
4538 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
4539 | } | |
4540 | ||
4541 | if (likely(!data_len)) | |
4542 | break; | |
2bbfebe2 | 4543 | |
1d9daf45 | 4544 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); |
9d5c8243 | 4545 | |
65689fef | 4546 | i++; |
ebe42d16 AD |
4547 | tx_desc++; |
4548 | if (i == tx_ring->count) { | |
4549 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
65689fef | 4550 | i = 0; |
ebe42d16 | 4551 | } |
80d0759e | 4552 | tx_desc->read.olinfo_status = 0; |
65689fef | 4553 | |
9e903e08 | 4554 | size = skb_frag_size(frag); |
ebe42d16 AD |
4555 | data_len -= size; |
4556 | ||
4557 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, | |
80d0759e | 4558 | size, DMA_TO_DEVICE); |
6366ad33 | 4559 | |
c9f14bf3 | 4560 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
9d5c8243 AK |
4561 | } |
4562 | ||
ebe42d16 | 4563 | /* write last descriptor with RS and EOP bits */ |
1d9daf45 AD |
4564 | cmd_type |= size | IGB_TXD_DCMD; |
4565 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); | |
8542db05 | 4566 | |
80d0759e AD |
4567 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
4568 | ||
8542db05 AD |
4569 | /* set the timestamp */ |
4570 | first->time_stamp = jiffies; | |
4571 | ||
b980ac18 | 4572 | /* Force memory writes to complete before letting h/w know there |
ebe42d16 AD |
4573 | * are new descriptors to fetch. (Only applicable for weak-ordered |
4574 | * memory model archs, such as IA-64). | |
4575 | * | |
4576 | * We also need this memory barrier to make certain all of the | |
4577 | * status bits have been updated before next_to_watch is written. | |
4578 | */ | |
4579 | wmb(); | |
4580 | ||
8542db05 | 4581 | /* set next_to_watch value indicating a packet is present */ |
ebe42d16 | 4582 | first->next_to_watch = tx_desc; |
9d5c8243 | 4583 | |
ebe42d16 AD |
4584 | i++; |
4585 | if (i == tx_ring->count) | |
4586 | i = 0; | |
6366ad33 | 4587 | |
ebe42d16 | 4588 | tx_ring->next_to_use = i; |
6366ad33 | 4589 | |
ebe42d16 | 4590 | writel(i, tx_ring->tail); |
6366ad33 | 4591 | |
ebe42d16 | 4592 | /* we need this if more than one processor can write to our tail |
b980ac18 JK |
4593 | * at a time, it synchronizes IO on IA64/Altix systems |
4594 | */ | |
ebe42d16 AD |
4595 | mmiowb(); |
4596 | ||
4597 | return; | |
4598 | ||
4599 | dma_error: | |
4600 | dev_err(tx_ring->dev, "TX DMA map failed\n"); | |
4601 | ||
4602 | /* clear dma mappings for failed tx_buffer_info map */ | |
4603 | for (;;) { | |
c9f14bf3 AD |
4604 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
4605 | igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
4606 | if (tx_buffer == first) | |
ebe42d16 | 4607 | break; |
a77ff709 NN |
4608 | if (i == 0) |
4609 | i = tx_ring->count; | |
6366ad33 | 4610 | i--; |
6366ad33 AD |
4611 | } |
4612 | ||
9d5c8243 | 4613 | tx_ring->next_to_use = i; |
9d5c8243 AK |
4614 | } |
4615 | ||
6ad4edfc | 4616 | static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
9d5c8243 | 4617 | { |
e694e964 AD |
4618 | struct net_device *netdev = tx_ring->netdev; |
4619 | ||
661086df | 4620 | netif_stop_subqueue(netdev, tx_ring->queue_index); |
661086df | 4621 | |
9d5c8243 AK |
4622 | /* Herbert's original patch had: |
4623 | * smp_mb__after_netif_stop_queue(); | |
b980ac18 JK |
4624 | * but since that doesn't exist yet, just open code it. |
4625 | */ | |
9d5c8243 AK |
4626 | smp_mb(); |
4627 | ||
4628 | /* We need to check again in a case another CPU has just | |
b980ac18 JK |
4629 | * made room available. |
4630 | */ | |
c493ea45 | 4631 | if (igb_desc_unused(tx_ring) < size) |
9d5c8243 AK |
4632 | return -EBUSY; |
4633 | ||
4634 | /* A reprieve! */ | |
661086df | 4635 | netif_wake_subqueue(netdev, tx_ring->queue_index); |
12dcd86b ED |
4636 | |
4637 | u64_stats_update_begin(&tx_ring->tx_syncp2); | |
4638 | tx_ring->tx_stats.restart_queue2++; | |
4639 | u64_stats_update_end(&tx_ring->tx_syncp2); | |
4640 | ||
9d5c8243 AK |
4641 | return 0; |
4642 | } | |
4643 | ||
6ad4edfc | 4644 | static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) |
9d5c8243 | 4645 | { |
c493ea45 | 4646 | if (igb_desc_unused(tx_ring) >= size) |
9d5c8243 | 4647 | return 0; |
e694e964 | 4648 | return __igb_maybe_stop_tx(tx_ring, size); |
9d5c8243 AK |
4649 | } |
4650 | ||
cd392f5c AD |
4651 | netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, |
4652 | struct igb_ring *tx_ring) | |
9d5c8243 | 4653 | { |
8542db05 | 4654 | struct igb_tx_buffer *first; |
ebe42d16 | 4655 | int tso; |
91d4ee33 | 4656 | u32 tx_flags = 0; |
21ba6fe1 | 4657 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
31f6adbb | 4658 | __be16 protocol = vlan_get_protocol(skb); |
91d4ee33 | 4659 | u8 hdr_len = 0; |
9d5c8243 | 4660 | |
21ba6fe1 AD |
4661 | /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, |
4662 | * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, | |
9d5c8243 | 4663 | * + 2 desc gap to keep tail from touching head, |
9d5c8243 | 4664 | * + 1 desc for context descriptor, |
21ba6fe1 AD |
4665 | * otherwise try next time |
4666 | */ | |
4667 | if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { | |
4668 | unsigned short f; | |
4669 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
4670 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
4671 | } else { | |
4672 | count += skb_shinfo(skb)->nr_frags; | |
4673 | } | |
4674 | ||
4675 | if (igb_maybe_stop_tx(tx_ring, count + 3)) { | |
9d5c8243 | 4676 | /* this is a hard error */ |
9d5c8243 AK |
4677 | return NETDEV_TX_BUSY; |
4678 | } | |
33af6bcc | 4679 | |
7af40ad9 AD |
4680 | /* record the location of the first descriptor for this packet */ |
4681 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
4682 | first->skb = skb; | |
4683 | first->bytecount = skb->len; | |
4684 | first->gso_segs = 1; | |
4685 | ||
b66e2397 MV |
4686 | skb_tx_timestamp(skb); |
4687 | ||
b646c22e AD |
4688 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { |
4689 | struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); | |
1f6e8178 | 4690 | |
b646c22e AD |
4691 | if (!(adapter->ptp_tx_skb)) { |
4692 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
4693 | tx_flags |= IGB_TX_FLAGS_TSTAMP; | |
4694 | ||
4695 | adapter->ptp_tx_skb = skb_get(skb); | |
4696 | adapter->ptp_tx_start = jiffies; | |
4697 | if (adapter->hw.mac.type == e1000_82576) | |
4698 | schedule_work(&adapter->ptp_tx_work); | |
4699 | } | |
33af6bcc | 4700 | } |
9d5c8243 | 4701 | |
eab6d18d | 4702 | if (vlan_tx_tag_present(skb)) { |
9d5c8243 AK |
4703 | tx_flags |= IGB_TX_FLAGS_VLAN; |
4704 | tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); | |
4705 | } | |
4706 | ||
7af40ad9 AD |
4707 | /* record initial flags and protocol */ |
4708 | first->tx_flags = tx_flags; | |
4709 | first->protocol = protocol; | |
cdfd01fc | 4710 | |
7af40ad9 AD |
4711 | tso = igb_tso(tx_ring, first, &hdr_len); |
4712 | if (tso < 0) | |
7d13a7d0 | 4713 | goto out_drop; |
7af40ad9 AD |
4714 | else if (!tso) |
4715 | igb_tx_csum(tx_ring, first); | |
9d5c8243 | 4716 | |
7af40ad9 | 4717 | igb_tx_map(tx_ring, first, hdr_len); |
85ad76b2 AD |
4718 | |
4719 | /* Make sure there is space in the ring for the next send. */ | |
21ba6fe1 | 4720 | igb_maybe_stop_tx(tx_ring, DESC_NEEDED); |
85ad76b2 | 4721 | |
9d5c8243 | 4722 | return NETDEV_TX_OK; |
7d13a7d0 AD |
4723 | |
4724 | out_drop: | |
7af40ad9 AD |
4725 | igb_unmap_and_free_tx_resource(tx_ring, first); |
4726 | ||
7d13a7d0 | 4727 | return NETDEV_TX_OK; |
9d5c8243 AK |
4728 | } |
4729 | ||
1cc3bd87 AD |
4730 | static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, |
4731 | struct sk_buff *skb) | |
4732 | { | |
4733 | unsigned int r_idx = skb->queue_mapping; | |
4734 | ||
4735 | if (r_idx >= adapter->num_tx_queues) | |
4736 | r_idx = r_idx % adapter->num_tx_queues; | |
4737 | ||
4738 | return adapter->tx_ring[r_idx]; | |
4739 | } | |
4740 | ||
cd392f5c AD |
4741 | static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, |
4742 | struct net_device *netdev) | |
9d5c8243 AK |
4743 | { |
4744 | struct igb_adapter *adapter = netdev_priv(netdev); | |
b1a436c3 AD |
4745 | |
4746 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
4747 | dev_kfree_skb_any(skb); | |
4748 | return NETDEV_TX_OK; | |
4749 | } | |
4750 | ||
4751 | if (skb->len <= 0) { | |
4752 | dev_kfree_skb_any(skb); | |
4753 | return NETDEV_TX_OK; | |
4754 | } | |
4755 | ||
b980ac18 | 4756 | /* The minimum packet size with TCTL.PSP set is 17 so pad the skb |
1cc3bd87 AD |
4757 | * in order to meet this minimum size requirement. |
4758 | */ | |
ea5ceeab TD |
4759 | if (unlikely(skb->len < 17)) { |
4760 | if (skb_pad(skb, 17 - skb->len)) | |
1cc3bd87 AD |
4761 | return NETDEV_TX_OK; |
4762 | skb->len = 17; | |
ea5ceeab | 4763 | skb_set_tail_pointer(skb, 17); |
1cc3bd87 | 4764 | } |
9d5c8243 | 4765 | |
1cc3bd87 | 4766 | return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); |
9d5c8243 AK |
4767 | } |
4768 | ||
4769 | /** | |
b980ac18 JK |
4770 | * igb_tx_timeout - Respond to a Tx Hang |
4771 | * @netdev: network interface device structure | |
9d5c8243 AK |
4772 | **/ |
4773 | static void igb_tx_timeout(struct net_device *netdev) | |
4774 | { | |
4775 | struct igb_adapter *adapter = netdev_priv(netdev); | |
4776 | struct e1000_hw *hw = &adapter->hw; | |
4777 | ||
4778 | /* Do the reset outside of interrupt context */ | |
4779 | adapter->tx_timeout_count++; | |
f7ba205e | 4780 | |
06218a8d | 4781 | if (hw->mac.type >= e1000_82580) |
55cac248 AD |
4782 | hw->dev_spec._82575.global_device_reset = true; |
4783 | ||
9d5c8243 | 4784 | schedule_work(&adapter->reset_task); |
265de409 AD |
4785 | wr32(E1000_EICS, |
4786 | (adapter->eims_enable_mask & ~adapter->eims_other)); | |
9d5c8243 AK |
4787 | } |
4788 | ||
4789 | static void igb_reset_task(struct work_struct *work) | |
4790 | { | |
4791 | struct igb_adapter *adapter; | |
4792 | adapter = container_of(work, struct igb_adapter, reset_task); | |
4793 | ||
c97ec42a TI |
4794 | igb_dump(adapter); |
4795 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
9d5c8243 AK |
4796 | igb_reinit_locked(adapter); |
4797 | } | |
4798 | ||
4799 | /** | |
b980ac18 JK |
4800 | * igb_get_stats64 - Get System Network Statistics |
4801 | * @netdev: network interface device structure | |
4802 | * @stats: rtnl_link_stats64 pointer | |
9d5c8243 | 4803 | **/ |
12dcd86b | 4804 | static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, |
b980ac18 | 4805 | struct rtnl_link_stats64 *stats) |
9d5c8243 | 4806 | { |
12dcd86b ED |
4807 | struct igb_adapter *adapter = netdev_priv(netdev); |
4808 | ||
4809 | spin_lock(&adapter->stats64_lock); | |
4810 | igb_update_stats(adapter, &adapter->stats64); | |
4811 | memcpy(stats, &adapter->stats64, sizeof(*stats)); | |
4812 | spin_unlock(&adapter->stats64_lock); | |
4813 | ||
4814 | return stats; | |
9d5c8243 AK |
4815 | } |
4816 | ||
4817 | /** | |
b980ac18 JK |
4818 | * igb_change_mtu - Change the Maximum Transfer Unit |
4819 | * @netdev: network interface device structure | |
4820 | * @new_mtu: new value for maximum frame size | |
9d5c8243 | 4821 | * |
b980ac18 | 4822 | * Returns 0 on success, negative on failure |
9d5c8243 AK |
4823 | **/ |
4824 | static int igb_change_mtu(struct net_device *netdev, int new_mtu) | |
4825 | { | |
4826 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 4827 | struct pci_dev *pdev = adapter->pdev; |
153285f9 | 4828 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
9d5c8243 | 4829 | |
c809d227 | 4830 | if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { |
090b1795 | 4831 | dev_err(&pdev->dev, "Invalid MTU setting\n"); |
9d5c8243 AK |
4832 | return -EINVAL; |
4833 | } | |
4834 | ||
153285f9 | 4835 | #define MAX_STD_JUMBO_FRAME_SIZE 9238 |
9d5c8243 | 4836 | if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { |
090b1795 | 4837 | dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); |
9d5c8243 AK |
4838 | return -EINVAL; |
4839 | } | |
4840 | ||
2ccd994c AD |
4841 | /* adjust max frame to be at least the size of a standard frame */ |
4842 | if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) | |
4843 | max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; | |
4844 | ||
9d5c8243 AK |
4845 | while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) |
4846 | msleep(1); | |
73cd78f1 | 4847 | |
9d5c8243 AK |
4848 | /* igb_down has a dependency on max_frame_size */ |
4849 | adapter->max_frame_size = max_frame; | |
559e9c49 | 4850 | |
4c844851 AD |
4851 | if (netif_running(netdev)) |
4852 | igb_down(adapter); | |
9d5c8243 | 4853 | |
090b1795 | 4854 | dev_info(&pdev->dev, "changing MTU from %d to %d\n", |
9d5c8243 AK |
4855 | netdev->mtu, new_mtu); |
4856 | netdev->mtu = new_mtu; | |
4857 | ||
4858 | if (netif_running(netdev)) | |
4859 | igb_up(adapter); | |
4860 | else | |
4861 | igb_reset(adapter); | |
4862 | ||
4863 | clear_bit(__IGB_RESETTING, &adapter->state); | |
4864 | ||
4865 | return 0; | |
4866 | } | |
4867 | ||
4868 | /** | |
b980ac18 JK |
4869 | * igb_update_stats - Update the board statistics counters |
4870 | * @adapter: board private structure | |
9d5c8243 | 4871 | **/ |
12dcd86b ED |
4872 | void igb_update_stats(struct igb_adapter *adapter, |
4873 | struct rtnl_link_stats64 *net_stats) | |
9d5c8243 AK |
4874 | { |
4875 | struct e1000_hw *hw = &adapter->hw; | |
4876 | struct pci_dev *pdev = adapter->pdev; | |
fa3d9a6d | 4877 | u32 reg, mpc; |
9d5c8243 | 4878 | u16 phy_tmp; |
3f9c0164 AD |
4879 | int i; |
4880 | u64 bytes, packets; | |
12dcd86b ED |
4881 | unsigned int start; |
4882 | u64 _bytes, _packets; | |
9d5c8243 AK |
4883 | |
4884 | #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF | |
4885 | ||
b980ac18 | 4886 | /* Prevent stats update while adapter is being reset, or if the pci |
9d5c8243 AK |
4887 | * connection is down. |
4888 | */ | |
4889 | if (adapter->link_speed == 0) | |
4890 | return; | |
4891 | if (pci_channel_offline(pdev)) | |
4892 | return; | |
4893 | ||
3f9c0164 AD |
4894 | bytes = 0; |
4895 | packets = 0; | |
7f90128e AA |
4896 | |
4897 | rcu_read_lock(); | |
3f9c0164 | 4898 | for (i = 0; i < adapter->num_rx_queues; i++) { |
ae1c07a6 | 4899 | u32 rqdpc = rd32(E1000_RQDPC(i)); |
3025a446 | 4900 | struct igb_ring *ring = adapter->rx_ring[i]; |
12dcd86b | 4901 | |
ae1c07a6 AD |
4902 | if (rqdpc) { |
4903 | ring->rx_stats.drops += rqdpc; | |
4904 | net_stats->rx_fifo_errors += rqdpc; | |
4905 | } | |
12dcd86b ED |
4906 | |
4907 | do { | |
4908 | start = u64_stats_fetch_begin_bh(&ring->rx_syncp); | |
4909 | _bytes = ring->rx_stats.bytes; | |
4910 | _packets = ring->rx_stats.packets; | |
4911 | } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); | |
4912 | bytes += _bytes; | |
4913 | packets += _packets; | |
3f9c0164 AD |
4914 | } |
4915 | ||
128e45eb AD |
4916 | net_stats->rx_bytes = bytes; |
4917 | net_stats->rx_packets = packets; | |
3f9c0164 AD |
4918 | |
4919 | bytes = 0; | |
4920 | packets = 0; | |
4921 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
3025a446 | 4922 | struct igb_ring *ring = adapter->tx_ring[i]; |
12dcd86b ED |
4923 | do { |
4924 | start = u64_stats_fetch_begin_bh(&ring->tx_syncp); | |
4925 | _bytes = ring->tx_stats.bytes; | |
4926 | _packets = ring->tx_stats.packets; | |
4927 | } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); | |
4928 | bytes += _bytes; | |
4929 | packets += _packets; | |
3f9c0164 | 4930 | } |
128e45eb AD |
4931 | net_stats->tx_bytes = bytes; |
4932 | net_stats->tx_packets = packets; | |
7f90128e | 4933 | rcu_read_unlock(); |
3f9c0164 AD |
4934 | |
4935 | /* read stats registers */ | |
9d5c8243 AK |
4936 | adapter->stats.crcerrs += rd32(E1000_CRCERRS); |
4937 | adapter->stats.gprc += rd32(E1000_GPRC); | |
4938 | adapter->stats.gorc += rd32(E1000_GORCL); | |
4939 | rd32(E1000_GORCH); /* clear GORCL */ | |
4940 | adapter->stats.bprc += rd32(E1000_BPRC); | |
4941 | adapter->stats.mprc += rd32(E1000_MPRC); | |
4942 | adapter->stats.roc += rd32(E1000_ROC); | |
4943 | ||
4944 | adapter->stats.prc64 += rd32(E1000_PRC64); | |
4945 | adapter->stats.prc127 += rd32(E1000_PRC127); | |
4946 | adapter->stats.prc255 += rd32(E1000_PRC255); | |
4947 | adapter->stats.prc511 += rd32(E1000_PRC511); | |
4948 | adapter->stats.prc1023 += rd32(E1000_PRC1023); | |
4949 | adapter->stats.prc1522 += rd32(E1000_PRC1522); | |
4950 | adapter->stats.symerrs += rd32(E1000_SYMERRS); | |
4951 | adapter->stats.sec += rd32(E1000_SEC); | |
4952 | ||
fa3d9a6d MW |
4953 | mpc = rd32(E1000_MPC); |
4954 | adapter->stats.mpc += mpc; | |
4955 | net_stats->rx_fifo_errors += mpc; | |
9d5c8243 AK |
4956 | adapter->stats.scc += rd32(E1000_SCC); |
4957 | adapter->stats.ecol += rd32(E1000_ECOL); | |
4958 | adapter->stats.mcc += rd32(E1000_MCC); | |
4959 | adapter->stats.latecol += rd32(E1000_LATECOL); | |
4960 | adapter->stats.dc += rd32(E1000_DC); | |
4961 | adapter->stats.rlec += rd32(E1000_RLEC); | |
4962 | adapter->stats.xonrxc += rd32(E1000_XONRXC); | |
4963 | adapter->stats.xontxc += rd32(E1000_XONTXC); | |
4964 | adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); | |
4965 | adapter->stats.xofftxc += rd32(E1000_XOFFTXC); | |
4966 | adapter->stats.fcruc += rd32(E1000_FCRUC); | |
4967 | adapter->stats.gptc += rd32(E1000_GPTC); | |
4968 | adapter->stats.gotc += rd32(E1000_GOTCL); | |
4969 | rd32(E1000_GOTCH); /* clear GOTCL */ | |
fa3d9a6d | 4970 | adapter->stats.rnbc += rd32(E1000_RNBC); |
9d5c8243 AK |
4971 | adapter->stats.ruc += rd32(E1000_RUC); |
4972 | adapter->stats.rfc += rd32(E1000_RFC); | |
4973 | adapter->stats.rjc += rd32(E1000_RJC); | |
4974 | adapter->stats.tor += rd32(E1000_TORH); | |
4975 | adapter->stats.tot += rd32(E1000_TOTH); | |
4976 | adapter->stats.tpr += rd32(E1000_TPR); | |
4977 | ||
4978 | adapter->stats.ptc64 += rd32(E1000_PTC64); | |
4979 | adapter->stats.ptc127 += rd32(E1000_PTC127); | |
4980 | adapter->stats.ptc255 += rd32(E1000_PTC255); | |
4981 | adapter->stats.ptc511 += rd32(E1000_PTC511); | |
4982 | adapter->stats.ptc1023 += rd32(E1000_PTC1023); | |
4983 | adapter->stats.ptc1522 += rd32(E1000_PTC1522); | |
4984 | ||
4985 | adapter->stats.mptc += rd32(E1000_MPTC); | |
4986 | adapter->stats.bptc += rd32(E1000_BPTC); | |
4987 | ||
2d0b0f69 NN |
4988 | adapter->stats.tpt += rd32(E1000_TPT); |
4989 | adapter->stats.colc += rd32(E1000_COLC); | |
9d5c8243 AK |
4990 | |
4991 | adapter->stats.algnerrc += rd32(E1000_ALGNERRC); | |
43915c7c NN |
4992 | /* read internal phy specific stats */ |
4993 | reg = rd32(E1000_CTRL_EXT); | |
4994 | if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { | |
4995 | adapter->stats.rxerrc += rd32(E1000_RXERRC); | |
3dbdf969 CW |
4996 | |
4997 | /* this stat has invalid values on i210/i211 */ | |
4998 | if ((hw->mac.type != e1000_i210) && | |
4999 | (hw->mac.type != e1000_i211)) | |
5000 | adapter->stats.tncrs += rd32(E1000_TNCRS); | |
43915c7c NN |
5001 | } |
5002 | ||
9d5c8243 AK |
5003 | adapter->stats.tsctc += rd32(E1000_TSCTC); |
5004 | adapter->stats.tsctfc += rd32(E1000_TSCTFC); | |
5005 | ||
5006 | adapter->stats.iac += rd32(E1000_IAC); | |
5007 | adapter->stats.icrxoc += rd32(E1000_ICRXOC); | |
5008 | adapter->stats.icrxptc += rd32(E1000_ICRXPTC); | |
5009 | adapter->stats.icrxatc += rd32(E1000_ICRXATC); | |
5010 | adapter->stats.ictxptc += rd32(E1000_ICTXPTC); | |
5011 | adapter->stats.ictxatc += rd32(E1000_ICTXATC); | |
5012 | adapter->stats.ictxqec += rd32(E1000_ICTXQEC); | |
5013 | adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); | |
5014 | adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); | |
5015 | ||
5016 | /* Fill out the OS statistics structure */ | |
128e45eb AD |
5017 | net_stats->multicast = adapter->stats.mprc; |
5018 | net_stats->collisions = adapter->stats.colc; | |
9d5c8243 AK |
5019 | |
5020 | /* Rx Errors */ | |
5021 | ||
5022 | /* RLEC on some newer hardware can be incorrect so build | |
b980ac18 JK |
5023 | * our own version based on RUC and ROC |
5024 | */ | |
128e45eb | 5025 | net_stats->rx_errors = adapter->stats.rxerrc + |
9d5c8243 AK |
5026 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
5027 | adapter->stats.ruc + adapter->stats.roc + | |
5028 | adapter->stats.cexterr; | |
128e45eb AD |
5029 | net_stats->rx_length_errors = adapter->stats.ruc + |
5030 | adapter->stats.roc; | |
5031 | net_stats->rx_crc_errors = adapter->stats.crcerrs; | |
5032 | net_stats->rx_frame_errors = adapter->stats.algnerrc; | |
5033 | net_stats->rx_missed_errors = adapter->stats.mpc; | |
9d5c8243 AK |
5034 | |
5035 | /* Tx Errors */ | |
128e45eb AD |
5036 | net_stats->tx_errors = adapter->stats.ecol + |
5037 | adapter->stats.latecol; | |
5038 | net_stats->tx_aborted_errors = adapter->stats.ecol; | |
5039 | net_stats->tx_window_errors = adapter->stats.latecol; | |
5040 | net_stats->tx_carrier_errors = adapter->stats.tncrs; | |
9d5c8243 AK |
5041 | |
5042 | /* Tx Dropped needs to be maintained elsewhere */ | |
5043 | ||
5044 | /* Phy Stats */ | |
5045 | if (hw->phy.media_type == e1000_media_type_copper) { | |
5046 | if ((adapter->link_speed == SPEED_1000) && | |
73cd78f1 | 5047 | (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { |
9d5c8243 AK |
5048 | phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; |
5049 | adapter->phy_stats.idle_errors += phy_tmp; | |
5050 | } | |
5051 | } | |
5052 | ||
5053 | /* Management Stats */ | |
5054 | adapter->stats.mgptc += rd32(E1000_MGTPTC); | |
5055 | adapter->stats.mgprc += rd32(E1000_MGTPRC); | |
5056 | adapter->stats.mgpdc += rd32(E1000_MGTPDC); | |
0a915b95 CW |
5057 | |
5058 | /* OS2BMC Stats */ | |
5059 | reg = rd32(E1000_MANC); | |
5060 | if (reg & E1000_MANC_EN_BMC2OS) { | |
5061 | adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); | |
5062 | adapter->stats.o2bspc += rd32(E1000_O2BSPC); | |
5063 | adapter->stats.b2ospc += rd32(E1000_B2OSPC); | |
5064 | adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); | |
5065 | } | |
9d5c8243 AK |
5066 | } |
5067 | ||
9d5c8243 AK |
5068 | static irqreturn_t igb_msix_other(int irq, void *data) |
5069 | { | |
047e0030 | 5070 | struct igb_adapter *adapter = data; |
9d5c8243 | 5071 | struct e1000_hw *hw = &adapter->hw; |
844290e5 | 5072 | u32 icr = rd32(E1000_ICR); |
844290e5 | 5073 | /* reading ICR causes bit 31 of EICR to be cleared */ |
dda0e083 | 5074 | |
7f081d40 AD |
5075 | if (icr & E1000_ICR_DRSTA) |
5076 | schedule_work(&adapter->reset_task); | |
5077 | ||
047e0030 | 5078 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5079 | /* HW is reporting DMA is out of sync */ |
5080 | adapter->stats.doosync++; | |
13800469 GR |
5081 | /* The DMA Out of Sync is also indication of a spoof event |
5082 | * in IOV mode. Check the Wrong VM Behavior register to | |
b980ac18 JK |
5083 | * see if it is really a spoof event. |
5084 | */ | |
13800469 | 5085 | igb_check_wvbr(adapter); |
dda0e083 | 5086 | } |
eebbbdba | 5087 | |
4ae196df AD |
5088 | /* Check for a mailbox event */ |
5089 | if (icr & E1000_ICR_VMMB) | |
5090 | igb_msg_task(adapter); | |
5091 | ||
5092 | if (icr & E1000_ICR_LSC) { | |
5093 | hw->mac.get_link_status = 1; | |
5094 | /* guard against interrupt when we're going down */ | |
5095 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5096 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5097 | } | |
5098 | ||
1f6e8178 MV |
5099 | if (icr & E1000_ICR_TS) { |
5100 | u32 tsicr = rd32(E1000_TSICR); | |
5101 | ||
5102 | if (tsicr & E1000_TSICR_TXTS) { | |
5103 | /* acknowledge the interrupt */ | |
5104 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5105 | /* retrieve hardware timestamp */ | |
5106 | schedule_work(&adapter->ptp_tx_work); | |
5107 | } | |
5108 | } | |
1f6e8178 | 5109 | |
844290e5 | 5110 | wr32(E1000_EIMS, adapter->eims_other); |
9d5c8243 AK |
5111 | |
5112 | return IRQ_HANDLED; | |
5113 | } | |
5114 | ||
047e0030 | 5115 | static void igb_write_itr(struct igb_q_vector *q_vector) |
9d5c8243 | 5116 | { |
26b39276 | 5117 | struct igb_adapter *adapter = q_vector->adapter; |
047e0030 | 5118 | u32 itr_val = q_vector->itr_val & 0x7FFC; |
9d5c8243 | 5119 | |
047e0030 AD |
5120 | if (!q_vector->set_itr) |
5121 | return; | |
73cd78f1 | 5122 | |
047e0030 AD |
5123 | if (!itr_val) |
5124 | itr_val = 0x4; | |
661086df | 5125 | |
26b39276 AD |
5126 | if (adapter->hw.mac.type == e1000_82575) |
5127 | itr_val |= itr_val << 16; | |
661086df | 5128 | else |
0ba82994 | 5129 | itr_val |= E1000_EITR_CNT_IGNR; |
661086df | 5130 | |
047e0030 AD |
5131 | writel(itr_val, q_vector->itr_register); |
5132 | q_vector->set_itr = 0; | |
6eb5a7f1 AD |
5133 | } |
5134 | ||
047e0030 | 5135 | static irqreturn_t igb_msix_ring(int irq, void *data) |
9d5c8243 | 5136 | { |
047e0030 | 5137 | struct igb_q_vector *q_vector = data; |
9d5c8243 | 5138 | |
047e0030 AD |
5139 | /* Write the ITR value calculated from the previous interrupt. */ |
5140 | igb_write_itr(q_vector); | |
9d5c8243 | 5141 | |
047e0030 | 5142 | napi_schedule(&q_vector->napi); |
844290e5 | 5143 | |
047e0030 | 5144 | return IRQ_HANDLED; |
fe4506b6 JC |
5145 | } |
5146 | ||
421e02f0 | 5147 | #ifdef CONFIG_IGB_DCA |
6a05004a AD |
5148 | static void igb_update_tx_dca(struct igb_adapter *adapter, |
5149 | struct igb_ring *tx_ring, | |
5150 | int cpu) | |
5151 | { | |
5152 | struct e1000_hw *hw = &adapter->hw; | |
5153 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); | |
5154 | ||
5155 | if (hw->mac.type != e1000_82575) | |
5156 | txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; | |
5157 | ||
b980ac18 | 5158 | /* We can enable relaxed ordering for reads, but not writes when |
6a05004a AD |
5159 | * DCA is enabled. This is due to a known issue in some chipsets |
5160 | * which will cause the DCA tag to be cleared. | |
5161 | */ | |
5162 | txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | | |
5163 | E1000_DCA_TXCTRL_DATA_RRO_EN | | |
5164 | E1000_DCA_TXCTRL_DESC_DCA_EN; | |
5165 | ||
5166 | wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); | |
5167 | } | |
5168 | ||
5169 | static void igb_update_rx_dca(struct igb_adapter *adapter, | |
5170 | struct igb_ring *rx_ring, | |
5171 | int cpu) | |
5172 | { | |
5173 | struct e1000_hw *hw = &adapter->hw; | |
5174 | u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); | |
5175 | ||
5176 | if (hw->mac.type != e1000_82575) | |
5177 | rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; | |
5178 | ||
b980ac18 | 5179 | /* We can enable relaxed ordering for reads, but not writes when |
6a05004a AD |
5180 | * DCA is enabled. This is due to a known issue in some chipsets |
5181 | * which will cause the DCA tag to be cleared. | |
5182 | */ | |
5183 | rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | | |
5184 | E1000_DCA_RXCTRL_DESC_DCA_EN; | |
5185 | ||
5186 | wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); | |
5187 | } | |
5188 | ||
047e0030 | 5189 | static void igb_update_dca(struct igb_q_vector *q_vector) |
fe4506b6 | 5190 | { |
047e0030 | 5191 | struct igb_adapter *adapter = q_vector->adapter; |
fe4506b6 | 5192 | int cpu = get_cpu(); |
fe4506b6 | 5193 | |
047e0030 AD |
5194 | if (q_vector->cpu == cpu) |
5195 | goto out_no_update; | |
5196 | ||
6a05004a AD |
5197 | if (q_vector->tx.ring) |
5198 | igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); | |
5199 | ||
5200 | if (q_vector->rx.ring) | |
5201 | igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); | |
5202 | ||
047e0030 AD |
5203 | q_vector->cpu = cpu; |
5204 | out_no_update: | |
fe4506b6 JC |
5205 | put_cpu(); |
5206 | } | |
5207 | ||
5208 | static void igb_setup_dca(struct igb_adapter *adapter) | |
5209 | { | |
7e0e99ef | 5210 | struct e1000_hw *hw = &adapter->hw; |
fe4506b6 JC |
5211 | int i; |
5212 | ||
7dfc16fa | 5213 | if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) |
fe4506b6 JC |
5214 | return; |
5215 | ||
7e0e99ef AD |
5216 | /* Always use CB2 mode, difference is masked in the CB driver. */ |
5217 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); | |
5218 | ||
047e0030 | 5219 | for (i = 0; i < adapter->num_q_vectors; i++) { |
26b39276 AD |
5220 | adapter->q_vector[i]->cpu = -1; |
5221 | igb_update_dca(adapter->q_vector[i]); | |
fe4506b6 JC |
5222 | } |
5223 | } | |
5224 | ||
5225 | static int __igb_notify_dca(struct device *dev, void *data) | |
5226 | { | |
5227 | struct net_device *netdev = dev_get_drvdata(dev); | |
5228 | struct igb_adapter *adapter = netdev_priv(netdev); | |
090b1795 | 5229 | struct pci_dev *pdev = adapter->pdev; |
fe4506b6 JC |
5230 | struct e1000_hw *hw = &adapter->hw; |
5231 | unsigned long event = *(unsigned long *)data; | |
5232 | ||
5233 | switch (event) { | |
5234 | case DCA_PROVIDER_ADD: | |
5235 | /* if already enabled, don't do it again */ | |
7dfc16fa | 5236 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) |
fe4506b6 | 5237 | break; |
fe4506b6 | 5238 | if (dca_add_requester(dev) == 0) { |
bbd98fe4 | 5239 | adapter->flags |= IGB_FLAG_DCA_ENABLED; |
090b1795 | 5240 | dev_info(&pdev->dev, "DCA enabled\n"); |
fe4506b6 JC |
5241 | igb_setup_dca(adapter); |
5242 | break; | |
5243 | } | |
5244 | /* Fall Through since DCA is disabled. */ | |
5245 | case DCA_PROVIDER_REMOVE: | |
7dfc16fa | 5246 | if (adapter->flags & IGB_FLAG_DCA_ENABLED) { |
fe4506b6 | 5247 | /* without this a class_device is left |
b980ac18 JK |
5248 | * hanging around in the sysfs model |
5249 | */ | |
fe4506b6 | 5250 | dca_remove_requester(dev); |
090b1795 | 5251 | dev_info(&pdev->dev, "DCA disabled\n"); |
7dfc16fa | 5252 | adapter->flags &= ~IGB_FLAG_DCA_ENABLED; |
cbd347ad | 5253 | wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); |
fe4506b6 JC |
5254 | } |
5255 | break; | |
5256 | } | |
bbd98fe4 | 5257 | |
fe4506b6 | 5258 | return 0; |
9d5c8243 AK |
5259 | } |
5260 | ||
fe4506b6 | 5261 | static int igb_notify_dca(struct notifier_block *nb, unsigned long event, |
b980ac18 | 5262 | void *p) |
fe4506b6 JC |
5263 | { |
5264 | int ret_val; | |
5265 | ||
5266 | ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, | |
b980ac18 | 5267 | __igb_notify_dca); |
fe4506b6 JC |
5268 | |
5269 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
5270 | } | |
421e02f0 | 5271 | #endif /* CONFIG_IGB_DCA */ |
9d5c8243 | 5272 | |
0224d663 GR |
5273 | #ifdef CONFIG_PCI_IOV |
5274 | static int igb_vf_configure(struct igb_adapter *adapter, int vf) | |
5275 | { | |
5276 | unsigned char mac_addr[ETH_ALEN]; | |
0224d663 | 5277 | |
5ac6f91d | 5278 | eth_zero_addr(mac_addr); |
0224d663 GR |
5279 | igb_set_vf_mac(adapter, vf, mac_addr); |
5280 | ||
70ea4783 LL |
5281 | /* By default spoof check is enabled for all VFs */ |
5282 | adapter->vf_data[vf].spoofchk_enabled = true; | |
5283 | ||
f557147c | 5284 | return 0; |
0224d663 GR |
5285 | } |
5286 | ||
0224d663 | 5287 | #endif |
4ae196df AD |
5288 | static void igb_ping_all_vfs(struct igb_adapter *adapter) |
5289 | { | |
5290 | struct e1000_hw *hw = &adapter->hw; | |
5291 | u32 ping; | |
5292 | int i; | |
5293 | ||
5294 | for (i = 0 ; i < adapter->vfs_allocated_count; i++) { | |
5295 | ping = E1000_PF_CONTROL_MSG; | |
f2ca0dbe | 5296 | if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) |
4ae196df AD |
5297 | ping |= E1000_VT_MSGTYPE_CTS; |
5298 | igb_write_mbx(hw, &ping, 1, i); | |
5299 | } | |
5300 | } | |
5301 | ||
7d5753f0 AD |
5302 | static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
5303 | { | |
5304 | struct e1000_hw *hw = &adapter->hw; | |
5305 | u32 vmolr = rd32(E1000_VMOLR(vf)); | |
5306 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
5307 | ||
d85b9004 | 5308 | vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | |
b980ac18 | 5309 | IGB_VF_FLAG_MULTI_PROMISC); |
7d5753f0 AD |
5310 | vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); |
5311 | ||
5312 | if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { | |
5313 | vmolr |= E1000_VMOLR_MPME; | |
d85b9004 | 5314 | vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; |
7d5753f0 AD |
5315 | *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; |
5316 | } else { | |
b980ac18 | 5317 | /* if we have hashes and we are clearing a multicast promisc |
7d5753f0 AD |
5318 | * flag we need to write the hashes to the MTA as this step |
5319 | * was previously skipped | |
5320 | */ | |
5321 | if (vf_data->num_vf_mc_hashes > 30) { | |
5322 | vmolr |= E1000_VMOLR_MPME; | |
5323 | } else if (vf_data->num_vf_mc_hashes) { | |
5324 | int j; | |
5325 | vmolr |= E1000_VMOLR_ROMPE; | |
5326 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
5327 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
5328 | } | |
5329 | } | |
5330 | ||
5331 | wr32(E1000_VMOLR(vf), vmolr); | |
5332 | ||
5333 | /* there are flags left unprocessed, likely not supported */ | |
5334 | if (*msgbuf & E1000_VT_MSGINFO_MASK) | |
5335 | return -EINVAL; | |
5336 | ||
5337 | return 0; | |
7d5753f0 AD |
5338 | } |
5339 | ||
4ae196df AD |
5340 | static int igb_set_vf_multicasts(struct igb_adapter *adapter, |
5341 | u32 *msgbuf, u32 vf) | |
5342 | { | |
5343 | int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; | |
5344 | u16 *hash_list = (u16 *)&msgbuf[1]; | |
5345 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; | |
5346 | int i; | |
5347 | ||
7d5753f0 | 5348 | /* salt away the number of multicast addresses assigned |
4ae196df AD |
5349 | * to this VF for later use to restore when the PF multi cast |
5350 | * list changes | |
5351 | */ | |
5352 | vf_data->num_vf_mc_hashes = n; | |
5353 | ||
7d5753f0 AD |
5354 | /* only up to 30 hash values supported */ |
5355 | if (n > 30) | |
5356 | n = 30; | |
5357 | ||
5358 | /* store the hashes for later use */ | |
4ae196df | 5359 | for (i = 0; i < n; i++) |
a419aef8 | 5360 | vf_data->vf_mc_hashes[i] = hash_list[i]; |
4ae196df AD |
5361 | |
5362 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5363 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5364 | |
5365 | return 0; | |
5366 | } | |
5367 | ||
5368 | static void igb_restore_vf_multicasts(struct igb_adapter *adapter) | |
5369 | { | |
5370 | struct e1000_hw *hw = &adapter->hw; | |
5371 | struct vf_data_storage *vf_data; | |
5372 | int i, j; | |
5373 | ||
5374 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7d5753f0 AD |
5375 | u32 vmolr = rd32(E1000_VMOLR(i)); |
5376 | vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); | |
5377 | ||
4ae196df | 5378 | vf_data = &adapter->vf_data[i]; |
7d5753f0 AD |
5379 | |
5380 | if ((vf_data->num_vf_mc_hashes > 30) || | |
5381 | (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { | |
5382 | vmolr |= E1000_VMOLR_MPME; | |
5383 | } else if (vf_data->num_vf_mc_hashes) { | |
5384 | vmolr |= E1000_VMOLR_ROMPE; | |
5385 | for (j = 0; j < vf_data->num_vf_mc_hashes; j++) | |
5386 | igb_mta_set(hw, vf_data->vf_mc_hashes[j]); | |
5387 | } | |
5388 | wr32(E1000_VMOLR(i), vmolr); | |
4ae196df AD |
5389 | } |
5390 | } | |
5391 | ||
5392 | static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) | |
5393 | { | |
5394 | struct e1000_hw *hw = &adapter->hw; | |
5395 | u32 pool_mask, reg, vid; | |
5396 | int i; | |
5397 | ||
5398 | pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5399 | ||
5400 | /* Find the vlan filter for this id */ | |
5401 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5402 | reg = rd32(E1000_VLVF(i)); | |
5403 | ||
5404 | /* remove the vf from the pool */ | |
5405 | reg &= ~pool_mask; | |
5406 | ||
5407 | /* if pool is empty then remove entry from vfta */ | |
5408 | if (!(reg & E1000_VLVF_POOLSEL_MASK) && | |
5409 | (reg & E1000_VLVF_VLANID_ENABLE)) { | |
5410 | reg = 0; | |
5411 | vid = reg & E1000_VLVF_VLANID_MASK; | |
5412 | igb_vfta_set(hw, vid, false); | |
5413 | } | |
5414 | ||
5415 | wr32(E1000_VLVF(i), reg); | |
5416 | } | |
ae641bdc AD |
5417 | |
5418 | adapter->vf_data[vf].vlans_enabled = 0; | |
4ae196df AD |
5419 | } |
5420 | ||
5421 | static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) | |
5422 | { | |
5423 | struct e1000_hw *hw = &adapter->hw; | |
5424 | u32 reg, i; | |
5425 | ||
51466239 AD |
5426 | /* The vlvf table only exists on 82576 hardware and newer */ |
5427 | if (hw->mac.type < e1000_82576) | |
5428 | return -1; | |
5429 | ||
5430 | /* we only need to do this if VMDq is enabled */ | |
4ae196df AD |
5431 | if (!adapter->vfs_allocated_count) |
5432 | return -1; | |
5433 | ||
5434 | /* Find the vlan filter for this id */ | |
5435 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5436 | reg = rd32(E1000_VLVF(i)); | |
5437 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
5438 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
5439 | break; | |
5440 | } | |
5441 | ||
5442 | if (add) { | |
5443 | if (i == E1000_VLVF_ARRAY_SIZE) { | |
5444 | /* Did not find a matching VLAN ID entry that was | |
5445 | * enabled. Search for a free filter entry, i.e. | |
5446 | * one without the enable bit set | |
5447 | */ | |
5448 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5449 | reg = rd32(E1000_VLVF(i)); | |
5450 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) | |
5451 | break; | |
5452 | } | |
5453 | } | |
5454 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5455 | /* Found an enabled/available entry */ | |
5456 | reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); | |
5457 | ||
5458 | /* if !enabled we need to set this up in vfta */ | |
5459 | if (!(reg & E1000_VLVF_VLANID_ENABLE)) { | |
51466239 AD |
5460 | /* add VID to filter table */ |
5461 | igb_vfta_set(hw, vid, true); | |
4ae196df AD |
5462 | reg |= E1000_VLVF_VLANID_ENABLE; |
5463 | } | |
cad6d05f AD |
5464 | reg &= ~E1000_VLVF_VLANID_MASK; |
5465 | reg |= vid; | |
4ae196df | 5466 | wr32(E1000_VLVF(i), reg); |
ae641bdc AD |
5467 | |
5468 | /* do not modify RLPML for PF devices */ | |
5469 | if (vf >= adapter->vfs_allocated_count) | |
5470 | return 0; | |
5471 | ||
5472 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5473 | u32 size; | |
5474 | reg = rd32(E1000_VMOLR(vf)); | |
5475 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5476 | size += 4; | |
5477 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5478 | reg |= size; | |
5479 | wr32(E1000_VMOLR(vf), reg); | |
5480 | } | |
ae641bdc | 5481 | |
51466239 | 5482 | adapter->vf_data[vf].vlans_enabled++; |
4ae196df AD |
5483 | } |
5484 | } else { | |
5485 | if (i < E1000_VLVF_ARRAY_SIZE) { | |
5486 | /* remove vf from the pool */ | |
5487 | reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); | |
5488 | /* if pool is empty then remove entry from vfta */ | |
5489 | if (!(reg & E1000_VLVF_POOLSEL_MASK)) { | |
5490 | reg = 0; | |
5491 | igb_vfta_set(hw, vid, false); | |
5492 | } | |
5493 | wr32(E1000_VLVF(i), reg); | |
ae641bdc AD |
5494 | |
5495 | /* do not modify RLPML for PF devices */ | |
5496 | if (vf >= adapter->vfs_allocated_count) | |
5497 | return 0; | |
5498 | ||
5499 | adapter->vf_data[vf].vlans_enabled--; | |
5500 | if (!adapter->vf_data[vf].vlans_enabled) { | |
5501 | u32 size; | |
5502 | reg = rd32(E1000_VMOLR(vf)); | |
5503 | size = reg & E1000_VMOLR_RLPML_MASK; | |
5504 | size -= 4; | |
5505 | reg &= ~E1000_VMOLR_RLPML_MASK; | |
5506 | reg |= size; | |
5507 | wr32(E1000_VMOLR(vf), reg); | |
5508 | } | |
4ae196df AD |
5509 | } |
5510 | } | |
8151d294 WM |
5511 | return 0; |
5512 | } | |
5513 | ||
5514 | static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) | |
5515 | { | |
5516 | struct e1000_hw *hw = &adapter->hw; | |
5517 | ||
5518 | if (vid) | |
5519 | wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); | |
5520 | else | |
5521 | wr32(E1000_VMVIR(vf), 0); | |
5522 | } | |
5523 | ||
5524 | static int igb_ndo_set_vf_vlan(struct net_device *netdev, | |
5525 | int vf, u16 vlan, u8 qos) | |
5526 | { | |
5527 | int err = 0; | |
5528 | struct igb_adapter *adapter = netdev_priv(netdev); | |
5529 | ||
5530 | if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) | |
5531 | return -EINVAL; | |
5532 | if (vlan || qos) { | |
5533 | err = igb_vlvf_set(adapter, vlan, !!vlan, vf); | |
5534 | if (err) | |
5535 | goto out; | |
5536 | igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); | |
5537 | igb_set_vmolr(adapter, vf, !vlan); | |
5538 | adapter->vf_data[vf].pf_vlan = vlan; | |
5539 | adapter->vf_data[vf].pf_qos = qos; | |
5540 | dev_info(&adapter->pdev->dev, | |
5541 | "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); | |
5542 | if (test_bit(__IGB_DOWN, &adapter->state)) { | |
5543 | dev_warn(&adapter->pdev->dev, | |
b980ac18 | 5544 | "The VF VLAN has been set, but the PF device is not up.\n"); |
8151d294 | 5545 | dev_warn(&adapter->pdev->dev, |
b980ac18 | 5546 | "Bring the PF device up before attempting to use the VF device.\n"); |
8151d294 WM |
5547 | } |
5548 | } else { | |
5549 | igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, | |
b980ac18 | 5550 | false, vf); |
8151d294 WM |
5551 | igb_set_vmvir(adapter, vlan, vf); |
5552 | igb_set_vmolr(adapter, vf, true); | |
5553 | adapter->vf_data[vf].pf_vlan = 0; | |
5554 | adapter->vf_data[vf].pf_qos = 0; | |
b980ac18 | 5555 | } |
8151d294 | 5556 | out: |
b980ac18 | 5557 | return err; |
4ae196df AD |
5558 | } |
5559 | ||
6f3dc319 GR |
5560 | static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) |
5561 | { | |
5562 | struct e1000_hw *hw = &adapter->hw; | |
5563 | int i; | |
5564 | u32 reg; | |
5565 | ||
5566 | /* Find the vlan filter for this id */ | |
5567 | for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { | |
5568 | reg = rd32(E1000_VLVF(i)); | |
5569 | if ((reg & E1000_VLVF_VLANID_ENABLE) && | |
5570 | vid == (reg & E1000_VLVF_VLANID_MASK)) | |
5571 | break; | |
5572 | } | |
5573 | ||
5574 | if (i >= E1000_VLVF_ARRAY_SIZE) | |
5575 | i = -1; | |
5576 | ||
5577 | return i; | |
5578 | } | |
5579 | ||
4ae196df AD |
5580 | static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) |
5581 | { | |
6f3dc319 | 5582 | struct e1000_hw *hw = &adapter->hw; |
4ae196df AD |
5583 | int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; |
5584 | int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); | |
6f3dc319 | 5585 | int err = 0; |
4ae196df | 5586 | |
6f3dc319 GR |
5587 | /* If in promiscuous mode we need to make sure the PF also has |
5588 | * the VLAN filter set. | |
5589 | */ | |
5590 | if (add && (adapter->netdev->flags & IFF_PROMISC)) | |
5591 | err = igb_vlvf_set(adapter, vid, add, | |
5592 | adapter->vfs_allocated_count); | |
5593 | if (err) | |
5594 | goto out; | |
5595 | ||
5596 | err = igb_vlvf_set(adapter, vid, add, vf); | |
5597 | ||
5598 | if (err) | |
5599 | goto out; | |
5600 | ||
5601 | /* Go through all the checks to see if the VLAN filter should | |
5602 | * be wiped completely. | |
5603 | */ | |
5604 | if (!add && (adapter->netdev->flags & IFF_PROMISC)) { | |
5605 | u32 vlvf, bits; | |
5606 | ||
5607 | int regndx = igb_find_vlvf_entry(adapter, vid); | |
5608 | if (regndx < 0) | |
5609 | goto out; | |
5610 | /* See if any other pools are set for this VLAN filter | |
5611 | * entry other than the PF. | |
5612 | */ | |
5613 | vlvf = bits = rd32(E1000_VLVF(regndx)); | |
5614 | bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + | |
5615 | adapter->vfs_allocated_count); | |
5616 | /* If the filter was removed then ensure PF pool bit | |
5617 | * is cleared if the PF only added itself to the pool | |
5618 | * because the PF is in promiscuous mode. | |
5619 | */ | |
5620 | if ((vlvf & VLAN_VID_MASK) == vid && | |
5621 | !test_bit(vid, adapter->active_vlans) && | |
5622 | !bits) | |
5623 | igb_vlvf_set(adapter, vid, add, | |
5624 | adapter->vfs_allocated_count); | |
5625 | } | |
5626 | ||
5627 | out: | |
5628 | return err; | |
4ae196df AD |
5629 | } |
5630 | ||
f2ca0dbe | 5631 | static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5632 | { |
8fa7e0f7 GR |
5633 | /* clear flags - except flag that indicates PF has set the MAC */ |
5634 | adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; | |
f2ca0dbe | 5635 | adapter->vf_data[vf].last_nack = jiffies; |
4ae196df AD |
5636 | |
5637 | /* reset offloads to defaults */ | |
8151d294 | 5638 | igb_set_vmolr(adapter, vf, true); |
4ae196df AD |
5639 | |
5640 | /* reset vlans for device */ | |
5641 | igb_clear_vf_vfta(adapter, vf); | |
8151d294 WM |
5642 | if (adapter->vf_data[vf].pf_vlan) |
5643 | igb_ndo_set_vf_vlan(adapter->netdev, vf, | |
5644 | adapter->vf_data[vf].pf_vlan, | |
5645 | adapter->vf_data[vf].pf_qos); | |
5646 | else | |
5647 | igb_clear_vf_vfta(adapter, vf); | |
4ae196df AD |
5648 | |
5649 | /* reset multicast table array for vf */ | |
5650 | adapter->vf_data[vf].num_vf_mc_hashes = 0; | |
5651 | ||
5652 | /* Flush and reset the mta with the new values */ | |
ff41f8dc | 5653 | igb_set_rx_mode(adapter->netdev); |
4ae196df AD |
5654 | } |
5655 | ||
f2ca0dbe AD |
5656 | static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) |
5657 | { | |
5658 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
5659 | ||
5ac6f91d | 5660 | /* clear mac address as we were hotplug removed/added */ |
8151d294 | 5661 | if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) |
5ac6f91d | 5662 | eth_zero_addr(vf_mac); |
f2ca0dbe AD |
5663 | |
5664 | /* process remaining reset events */ | |
5665 | igb_vf_reset(adapter, vf); | |
5666 | } | |
5667 | ||
5668 | static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) | |
4ae196df AD |
5669 | { |
5670 | struct e1000_hw *hw = &adapter->hw; | |
5671 | unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; | |
ff41f8dc | 5672 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df AD |
5673 | u32 reg, msgbuf[3]; |
5674 | u8 *addr = (u8 *)(&msgbuf[1]); | |
5675 | ||
5676 | /* process all the same items cleared in a function level reset */ | |
f2ca0dbe | 5677 | igb_vf_reset(adapter, vf); |
4ae196df AD |
5678 | |
5679 | /* set vf mac address */ | |
26ad9178 | 5680 | igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); |
4ae196df AD |
5681 | |
5682 | /* enable transmit and receive for vf */ | |
5683 | reg = rd32(E1000_VFTE); | |
5684 | wr32(E1000_VFTE, reg | (1 << vf)); | |
5685 | reg = rd32(E1000_VFRE); | |
5686 | wr32(E1000_VFRE, reg | (1 << vf)); | |
5687 | ||
8fa7e0f7 | 5688 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; |
4ae196df AD |
5689 | |
5690 | /* reply to reset with ack and vf mac address */ | |
5691 | msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; | |
5692 | memcpy(addr, vf_mac, 6); | |
5693 | igb_write_mbx(hw, msgbuf, 3, vf); | |
5694 | } | |
5695 | ||
5696 | static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) | |
5697 | { | |
b980ac18 | 5698 | /* The VF MAC Address is stored in a packed array of bytes |
de42edde GR |
5699 | * starting at the second 32 bit word of the msg array |
5700 | */ | |
f2ca0dbe AD |
5701 | unsigned char *addr = (char *)&msg[1]; |
5702 | int err = -1; | |
4ae196df | 5703 | |
f2ca0dbe AD |
5704 | if (is_valid_ether_addr(addr)) |
5705 | err = igb_set_vf_mac(adapter, vf, addr); | |
4ae196df | 5706 | |
f2ca0dbe | 5707 | return err; |
4ae196df AD |
5708 | } |
5709 | ||
5710 | static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) | |
5711 | { | |
5712 | struct e1000_hw *hw = &adapter->hw; | |
f2ca0dbe | 5713 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5714 | u32 msg = E1000_VT_MSGTYPE_NACK; |
5715 | ||
5716 | /* if device isn't clear to send it shouldn't be reading either */ | |
f2ca0dbe AD |
5717 | if (!(vf_data->flags & IGB_VF_FLAG_CTS) && |
5718 | time_after(jiffies, vf_data->last_nack + (2 * HZ))) { | |
4ae196df | 5719 | igb_write_mbx(hw, &msg, 1, vf); |
f2ca0dbe | 5720 | vf_data->last_nack = jiffies; |
4ae196df AD |
5721 | } |
5722 | } | |
5723 | ||
f2ca0dbe | 5724 | static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) |
4ae196df | 5725 | { |
f2ca0dbe AD |
5726 | struct pci_dev *pdev = adapter->pdev; |
5727 | u32 msgbuf[E1000_VFMAILBOX_SIZE]; | |
4ae196df | 5728 | struct e1000_hw *hw = &adapter->hw; |
f2ca0dbe | 5729 | struct vf_data_storage *vf_data = &adapter->vf_data[vf]; |
4ae196df AD |
5730 | s32 retval; |
5731 | ||
f2ca0dbe | 5732 | retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); |
4ae196df | 5733 | |
fef45f4c AD |
5734 | if (retval) { |
5735 | /* if receive failed revoke VF CTS stats and restart init */ | |
f2ca0dbe | 5736 | dev_err(&pdev->dev, "Error receiving message from VF\n"); |
fef45f4c AD |
5737 | vf_data->flags &= ~IGB_VF_FLAG_CTS; |
5738 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) | |
5739 | return; | |
5740 | goto out; | |
5741 | } | |
4ae196df AD |
5742 | |
5743 | /* this is a message we already processed, do nothing */ | |
5744 | if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) | |
f2ca0dbe | 5745 | return; |
4ae196df | 5746 | |
b980ac18 | 5747 | /* until the vf completes a reset it should not be |
4ae196df AD |
5748 | * allowed to start any configuration. |
5749 | */ | |
4ae196df AD |
5750 | if (msgbuf[0] == E1000_VF_RESET) { |
5751 | igb_vf_reset_msg(adapter, vf); | |
f2ca0dbe | 5752 | return; |
4ae196df AD |
5753 | } |
5754 | ||
f2ca0dbe | 5755 | if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { |
fef45f4c AD |
5756 | if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) |
5757 | return; | |
5758 | retval = -1; | |
5759 | goto out; | |
4ae196df AD |
5760 | } |
5761 | ||
5762 | switch ((msgbuf[0] & 0xFFFF)) { | |
5763 | case E1000_VF_SET_MAC_ADDR: | |
a6b5ea35 GR |
5764 | retval = -EINVAL; |
5765 | if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) | |
5766 | retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); | |
5767 | else | |
5768 | dev_warn(&pdev->dev, | |
b980ac18 JK |
5769 | "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", |
5770 | vf); | |
4ae196df | 5771 | break; |
7d5753f0 AD |
5772 | case E1000_VF_SET_PROMISC: |
5773 | retval = igb_set_vf_promisc(adapter, msgbuf, vf); | |
5774 | break; | |
4ae196df AD |
5775 | case E1000_VF_SET_MULTICAST: |
5776 | retval = igb_set_vf_multicasts(adapter, msgbuf, vf); | |
5777 | break; | |
5778 | case E1000_VF_SET_LPE: | |
5779 | retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); | |
5780 | break; | |
5781 | case E1000_VF_SET_VLAN: | |
a6b5ea35 GR |
5782 | retval = -1; |
5783 | if (vf_data->pf_vlan) | |
5784 | dev_warn(&pdev->dev, | |
b980ac18 JK |
5785 | "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", |
5786 | vf); | |
8151d294 WM |
5787 | else |
5788 | retval = igb_set_vf_vlan(adapter, msgbuf, vf); | |
4ae196df AD |
5789 | break; |
5790 | default: | |
090b1795 | 5791 | dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); |
4ae196df AD |
5792 | retval = -1; |
5793 | break; | |
5794 | } | |
5795 | ||
fef45f4c AD |
5796 | msgbuf[0] |= E1000_VT_MSGTYPE_CTS; |
5797 | out: | |
4ae196df AD |
5798 | /* notify the VF of the results of what it sent us */ |
5799 | if (retval) | |
5800 | msgbuf[0] |= E1000_VT_MSGTYPE_NACK; | |
5801 | else | |
5802 | msgbuf[0] |= E1000_VT_MSGTYPE_ACK; | |
5803 | ||
4ae196df | 5804 | igb_write_mbx(hw, msgbuf, 1, vf); |
f2ca0dbe | 5805 | } |
4ae196df | 5806 | |
f2ca0dbe AD |
5807 | static void igb_msg_task(struct igb_adapter *adapter) |
5808 | { | |
5809 | struct e1000_hw *hw = &adapter->hw; | |
5810 | u32 vf; | |
5811 | ||
5812 | for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { | |
5813 | /* process any reset requests */ | |
5814 | if (!igb_check_for_rst(hw, vf)) | |
5815 | igb_vf_reset_event(adapter, vf); | |
5816 | ||
5817 | /* process any messages pending */ | |
5818 | if (!igb_check_for_msg(hw, vf)) | |
5819 | igb_rcv_msg_from_vf(adapter, vf); | |
5820 | ||
5821 | /* process any acks */ | |
5822 | if (!igb_check_for_ack(hw, vf)) | |
5823 | igb_rcv_ack_from_vf(adapter, vf); | |
5824 | } | |
4ae196df AD |
5825 | } |
5826 | ||
68d480c4 AD |
5827 | /** |
5828 | * igb_set_uta - Set unicast filter table address | |
5829 | * @adapter: board private structure | |
5830 | * | |
5831 | * The unicast table address is a register array of 32-bit registers. | |
5832 | * The table is meant to be used in a way similar to how the MTA is used | |
5833 | * however due to certain limitations in the hardware it is necessary to | |
25985edc LDM |
5834 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous |
5835 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
68d480c4 AD |
5836 | **/ |
5837 | static void igb_set_uta(struct igb_adapter *adapter) | |
5838 | { | |
5839 | struct e1000_hw *hw = &adapter->hw; | |
5840 | int i; | |
5841 | ||
5842 | /* The UTA table only exists on 82576 hardware and newer */ | |
5843 | if (hw->mac.type < e1000_82576) | |
5844 | return; | |
5845 | ||
5846 | /* we only need to do this if VMDq is enabled */ | |
5847 | if (!adapter->vfs_allocated_count) | |
5848 | return; | |
5849 | ||
5850 | for (i = 0; i < hw->mac.uta_reg_count; i++) | |
5851 | array_wr32(E1000_UTA, i, ~0); | |
5852 | } | |
5853 | ||
9d5c8243 | 5854 | /** |
b980ac18 JK |
5855 | * igb_intr_msi - Interrupt Handler |
5856 | * @irq: interrupt number | |
5857 | * @data: pointer to a network interface device structure | |
9d5c8243 AK |
5858 | **/ |
5859 | static irqreturn_t igb_intr_msi(int irq, void *data) | |
5860 | { | |
047e0030 AD |
5861 | struct igb_adapter *adapter = data; |
5862 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5863 | struct e1000_hw *hw = &adapter->hw; |
5864 | /* read ICR disables interrupts using IAM */ | |
5865 | u32 icr = rd32(E1000_ICR); | |
5866 | ||
047e0030 | 5867 | igb_write_itr(q_vector); |
9d5c8243 | 5868 | |
7f081d40 AD |
5869 | if (icr & E1000_ICR_DRSTA) |
5870 | schedule_work(&adapter->reset_task); | |
5871 | ||
047e0030 | 5872 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5873 | /* HW is reporting DMA is out of sync */ |
5874 | adapter->stats.doosync++; | |
5875 | } | |
5876 | ||
9d5c8243 AK |
5877 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5878 | hw->mac.get_link_status = 1; | |
5879 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5880 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5881 | } | |
5882 | ||
1f6e8178 MV |
5883 | if (icr & E1000_ICR_TS) { |
5884 | u32 tsicr = rd32(E1000_TSICR); | |
5885 | ||
5886 | if (tsicr & E1000_TSICR_TXTS) { | |
5887 | /* acknowledge the interrupt */ | |
5888 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5889 | /* retrieve hardware timestamp */ | |
5890 | schedule_work(&adapter->ptp_tx_work); | |
5891 | } | |
5892 | } | |
1f6e8178 | 5893 | |
047e0030 | 5894 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5895 | |
5896 | return IRQ_HANDLED; | |
5897 | } | |
5898 | ||
5899 | /** | |
b980ac18 JK |
5900 | * igb_intr - Legacy Interrupt Handler |
5901 | * @irq: interrupt number | |
5902 | * @data: pointer to a network interface device structure | |
9d5c8243 AK |
5903 | **/ |
5904 | static irqreturn_t igb_intr(int irq, void *data) | |
5905 | { | |
047e0030 AD |
5906 | struct igb_adapter *adapter = data; |
5907 | struct igb_q_vector *q_vector = adapter->q_vector[0]; | |
9d5c8243 AK |
5908 | struct e1000_hw *hw = &adapter->hw; |
5909 | /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No | |
b980ac18 JK |
5910 | * need for the IMC write |
5911 | */ | |
9d5c8243 | 5912 | u32 icr = rd32(E1000_ICR); |
9d5c8243 AK |
5913 | |
5914 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is | |
b980ac18 JK |
5915 | * not set, then the adapter didn't send an interrupt |
5916 | */ | |
9d5c8243 AK |
5917 | if (!(icr & E1000_ICR_INT_ASSERTED)) |
5918 | return IRQ_NONE; | |
5919 | ||
0ba82994 AD |
5920 | igb_write_itr(q_vector); |
5921 | ||
7f081d40 AD |
5922 | if (icr & E1000_ICR_DRSTA) |
5923 | schedule_work(&adapter->reset_task); | |
5924 | ||
047e0030 | 5925 | if (icr & E1000_ICR_DOUTSYNC) { |
dda0e083 AD |
5926 | /* HW is reporting DMA is out of sync */ |
5927 | adapter->stats.doosync++; | |
5928 | } | |
5929 | ||
9d5c8243 AK |
5930 | if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { |
5931 | hw->mac.get_link_status = 1; | |
5932 | /* guard against interrupt when we're going down */ | |
5933 | if (!test_bit(__IGB_DOWN, &adapter->state)) | |
5934 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
5935 | } | |
5936 | ||
1f6e8178 MV |
5937 | if (icr & E1000_ICR_TS) { |
5938 | u32 tsicr = rd32(E1000_TSICR); | |
5939 | ||
5940 | if (tsicr & E1000_TSICR_TXTS) { | |
5941 | /* acknowledge the interrupt */ | |
5942 | wr32(E1000_TSICR, E1000_TSICR_TXTS); | |
5943 | /* retrieve hardware timestamp */ | |
5944 | schedule_work(&adapter->ptp_tx_work); | |
5945 | } | |
5946 | } | |
1f6e8178 | 5947 | |
047e0030 | 5948 | napi_schedule(&q_vector->napi); |
9d5c8243 AK |
5949 | |
5950 | return IRQ_HANDLED; | |
5951 | } | |
5952 | ||
c50b52a0 | 5953 | static void igb_ring_irq_enable(struct igb_q_vector *q_vector) |
9d5c8243 | 5954 | { |
047e0030 | 5955 | struct igb_adapter *adapter = q_vector->adapter; |
46544258 | 5956 | struct e1000_hw *hw = &adapter->hw; |
9d5c8243 | 5957 | |
0ba82994 AD |
5958 | if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || |
5959 | (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { | |
5960 | if ((adapter->num_q_vectors == 1) && !adapter->vf_data) | |
5961 | igb_set_itr(q_vector); | |
46544258 | 5962 | else |
047e0030 | 5963 | igb_update_ring_itr(q_vector); |
9d5c8243 AK |
5964 | } |
5965 | ||
46544258 AD |
5966 | if (!test_bit(__IGB_DOWN, &adapter->state)) { |
5967 | if (adapter->msix_entries) | |
047e0030 | 5968 | wr32(E1000_EIMS, q_vector->eims_value); |
46544258 AD |
5969 | else |
5970 | igb_irq_enable(adapter); | |
5971 | } | |
9d5c8243 AK |
5972 | } |
5973 | ||
46544258 | 5974 | /** |
b980ac18 JK |
5975 | * igb_poll - NAPI Rx polling callback |
5976 | * @napi: napi polling structure | |
5977 | * @budget: count of how many packets we should handle | |
46544258 AD |
5978 | **/ |
5979 | static int igb_poll(struct napi_struct *napi, int budget) | |
9d5c8243 | 5980 | { |
047e0030 | 5981 | struct igb_q_vector *q_vector = container_of(napi, |
b980ac18 JK |
5982 | struct igb_q_vector, |
5983 | napi); | |
16eb8815 | 5984 | bool clean_complete = true; |
9d5c8243 | 5985 | |
421e02f0 | 5986 | #ifdef CONFIG_IGB_DCA |
047e0030 AD |
5987 | if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) |
5988 | igb_update_dca(q_vector); | |
fe4506b6 | 5989 | #endif |
0ba82994 | 5990 | if (q_vector->tx.ring) |
13fde97a | 5991 | clean_complete = igb_clean_tx_irq(q_vector); |
9d5c8243 | 5992 | |
0ba82994 | 5993 | if (q_vector->rx.ring) |
cd392f5c | 5994 | clean_complete &= igb_clean_rx_irq(q_vector, budget); |
047e0030 | 5995 | |
16eb8815 AD |
5996 | /* If all work not completed, return budget and keep polling */ |
5997 | if (!clean_complete) | |
5998 | return budget; | |
46544258 | 5999 | |
9d5c8243 | 6000 | /* If not enough Rx work done, exit the polling mode */ |
16eb8815 AD |
6001 | napi_complete(napi); |
6002 | igb_ring_irq_enable(q_vector); | |
9d5c8243 | 6003 | |
16eb8815 | 6004 | return 0; |
9d5c8243 | 6005 | } |
6d8126f9 | 6006 | |
9d5c8243 | 6007 | /** |
b980ac18 JK |
6008 | * igb_clean_tx_irq - Reclaim resources after transmit completes |
6009 | * @q_vector: pointer to q_vector containing needed info | |
49ce9c2c | 6010 | * |
b980ac18 | 6011 | * returns true if ring is completely cleaned |
9d5c8243 | 6012 | **/ |
047e0030 | 6013 | static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) |
9d5c8243 | 6014 | { |
047e0030 | 6015 | struct igb_adapter *adapter = q_vector->adapter; |
0ba82994 | 6016 | struct igb_ring *tx_ring = q_vector->tx.ring; |
06034649 | 6017 | struct igb_tx_buffer *tx_buffer; |
f4128785 | 6018 | union e1000_adv_tx_desc *tx_desc; |
9d5c8243 | 6019 | unsigned int total_bytes = 0, total_packets = 0; |
0ba82994 | 6020 | unsigned int budget = q_vector->tx.work_limit; |
8542db05 | 6021 | unsigned int i = tx_ring->next_to_clean; |
9d5c8243 | 6022 | |
13fde97a AD |
6023 | if (test_bit(__IGB_DOWN, &adapter->state)) |
6024 | return true; | |
0e014cb1 | 6025 | |
06034649 | 6026 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
13fde97a | 6027 | tx_desc = IGB_TX_DESC(tx_ring, i); |
8542db05 | 6028 | i -= tx_ring->count; |
9d5c8243 | 6029 | |
f4128785 AD |
6030 | do { |
6031 | union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; | |
8542db05 AD |
6032 | |
6033 | /* if next_to_watch is not set then there is no work pending */ | |
6034 | if (!eop_desc) | |
6035 | break; | |
13fde97a | 6036 | |
f4128785 | 6037 | /* prevent any other reads prior to eop_desc */ |
70d289bc | 6038 | read_barrier_depends(); |
f4128785 | 6039 | |
13fde97a AD |
6040 | /* if DD is not set pending work has not been completed */ |
6041 | if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) | |
6042 | break; | |
6043 | ||
8542db05 AD |
6044 | /* clear next_to_watch to prevent false hangs */ |
6045 | tx_buffer->next_to_watch = NULL; | |
9d5c8243 | 6046 | |
ebe42d16 AD |
6047 | /* update the statistics for this packet */ |
6048 | total_bytes += tx_buffer->bytecount; | |
6049 | total_packets += tx_buffer->gso_segs; | |
13fde97a | 6050 | |
ebe42d16 AD |
6051 | /* free the skb */ |
6052 | dev_kfree_skb_any(tx_buffer->skb); | |
13fde97a | 6053 | |
ebe42d16 AD |
6054 | /* unmap skb header data */ |
6055 | dma_unmap_single(tx_ring->dev, | |
c9f14bf3 AD |
6056 | dma_unmap_addr(tx_buffer, dma), |
6057 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 AD |
6058 | DMA_TO_DEVICE); |
6059 | ||
c9f14bf3 AD |
6060 | /* clear tx_buffer data */ |
6061 | tx_buffer->skb = NULL; | |
6062 | dma_unmap_len_set(tx_buffer, len, 0); | |
6063 | ||
ebe42d16 AD |
6064 | /* clear last DMA location and unmap remaining buffers */ |
6065 | while (tx_desc != eop_desc) { | |
13fde97a AD |
6066 | tx_buffer++; |
6067 | tx_desc++; | |
9d5c8243 | 6068 | i++; |
8542db05 AD |
6069 | if (unlikely(!i)) { |
6070 | i -= tx_ring->count; | |
06034649 | 6071 | tx_buffer = tx_ring->tx_buffer_info; |
13fde97a AD |
6072 | tx_desc = IGB_TX_DESC(tx_ring, 0); |
6073 | } | |
ebe42d16 AD |
6074 | |
6075 | /* unmap any remaining paged data */ | |
c9f14bf3 | 6076 | if (dma_unmap_len(tx_buffer, len)) { |
ebe42d16 | 6077 | dma_unmap_page(tx_ring->dev, |
c9f14bf3 AD |
6078 | dma_unmap_addr(tx_buffer, dma), |
6079 | dma_unmap_len(tx_buffer, len), | |
ebe42d16 | 6080 | DMA_TO_DEVICE); |
c9f14bf3 | 6081 | dma_unmap_len_set(tx_buffer, len, 0); |
ebe42d16 AD |
6082 | } |
6083 | } | |
6084 | ||
ebe42d16 AD |
6085 | /* move us one more past the eop_desc for start of next pkt */ |
6086 | tx_buffer++; | |
6087 | tx_desc++; | |
6088 | i++; | |
6089 | if (unlikely(!i)) { | |
6090 | i -= tx_ring->count; | |
6091 | tx_buffer = tx_ring->tx_buffer_info; | |
6092 | tx_desc = IGB_TX_DESC(tx_ring, 0); | |
6093 | } | |
f4128785 AD |
6094 | |
6095 | /* issue prefetch for next Tx descriptor */ | |
6096 | prefetch(tx_desc); | |
6097 | ||
6098 | /* update budget accounting */ | |
6099 | budget--; | |
6100 | } while (likely(budget)); | |
0e014cb1 | 6101 | |
bdbc0631 ED |
6102 | netdev_tx_completed_queue(txring_txq(tx_ring), |
6103 | total_packets, total_bytes); | |
8542db05 | 6104 | i += tx_ring->count; |
9d5c8243 | 6105 | tx_ring->next_to_clean = i; |
13fde97a AD |
6106 | u64_stats_update_begin(&tx_ring->tx_syncp); |
6107 | tx_ring->tx_stats.bytes += total_bytes; | |
6108 | tx_ring->tx_stats.packets += total_packets; | |
6109 | u64_stats_update_end(&tx_ring->tx_syncp); | |
0ba82994 AD |
6110 | q_vector->tx.total_bytes += total_bytes; |
6111 | q_vector->tx.total_packets += total_packets; | |
9d5c8243 | 6112 | |
6d095fa8 | 6113 | if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { |
13fde97a | 6114 | struct e1000_hw *hw = &adapter->hw; |
12dcd86b | 6115 | |
9d5c8243 | 6116 | /* Detect a transmit hang in hardware, this serializes the |
b980ac18 JK |
6117 | * check with the clearing of time_stamp and movement of i |
6118 | */ | |
6d095fa8 | 6119 | clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); |
f4128785 | 6120 | if (tx_buffer->next_to_watch && |
8542db05 | 6121 | time_after(jiffies, tx_buffer->time_stamp + |
8e95a202 JP |
6122 | (adapter->tx_timeout_factor * HZ)) && |
6123 | !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { | |
9d5c8243 | 6124 | |
9d5c8243 | 6125 | /* detected Tx unit hang */ |
59d71989 | 6126 | dev_err(tx_ring->dev, |
9d5c8243 | 6127 | "Detected Tx Unit Hang\n" |
2d064c06 | 6128 | " Tx Queue <%d>\n" |
9d5c8243 AK |
6129 | " TDH <%x>\n" |
6130 | " TDT <%x>\n" | |
6131 | " next_to_use <%x>\n" | |
6132 | " next_to_clean <%x>\n" | |
9d5c8243 AK |
6133 | "buffer_info[next_to_clean]\n" |
6134 | " time_stamp <%lx>\n" | |
8542db05 | 6135 | " next_to_watch <%p>\n" |
9d5c8243 AK |
6136 | " jiffies <%lx>\n" |
6137 | " desc.status <%x>\n", | |
2d064c06 | 6138 | tx_ring->queue_index, |
238ac817 | 6139 | rd32(E1000_TDH(tx_ring->reg_idx)), |
fce99e34 | 6140 | readl(tx_ring->tail), |
9d5c8243 AK |
6141 | tx_ring->next_to_use, |
6142 | tx_ring->next_to_clean, | |
8542db05 | 6143 | tx_buffer->time_stamp, |
f4128785 | 6144 | tx_buffer->next_to_watch, |
9d5c8243 | 6145 | jiffies, |
f4128785 | 6146 | tx_buffer->next_to_watch->wb.status); |
13fde97a AD |
6147 | netif_stop_subqueue(tx_ring->netdev, |
6148 | tx_ring->queue_index); | |
6149 | ||
6150 | /* we are about to reset, no point in enabling stuff */ | |
6151 | return true; | |
9d5c8243 AK |
6152 | } |
6153 | } | |
13fde97a | 6154 | |
21ba6fe1 | 6155 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
13fde97a | 6156 | if (unlikely(total_packets && |
b980ac18 JK |
6157 | netif_carrier_ok(tx_ring->netdev) && |
6158 | igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { | |
13fde97a AD |
6159 | /* Make sure that anybody stopping the queue after this |
6160 | * sees the new next_to_clean. | |
6161 | */ | |
6162 | smp_mb(); | |
6163 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
6164 | tx_ring->queue_index) && | |
6165 | !(test_bit(__IGB_DOWN, &adapter->state))) { | |
6166 | netif_wake_subqueue(tx_ring->netdev, | |
6167 | tx_ring->queue_index); | |
6168 | ||
6169 | u64_stats_update_begin(&tx_ring->tx_syncp); | |
6170 | tx_ring->tx_stats.restart_queue++; | |
6171 | u64_stats_update_end(&tx_ring->tx_syncp); | |
6172 | } | |
6173 | } | |
6174 | ||
6175 | return !!budget; | |
9d5c8243 AK |
6176 | } |
6177 | ||
cbc8e55f | 6178 | /** |
b980ac18 JK |
6179 | * igb_reuse_rx_page - page flip buffer and store it back on the ring |
6180 | * @rx_ring: rx descriptor ring to store buffers on | |
6181 | * @old_buff: donor buffer to have page reused | |
cbc8e55f | 6182 | * |
b980ac18 | 6183 | * Synchronizes page for reuse by the adapter |
cbc8e55f AD |
6184 | **/ |
6185 | static void igb_reuse_rx_page(struct igb_ring *rx_ring, | |
6186 | struct igb_rx_buffer *old_buff) | |
6187 | { | |
6188 | struct igb_rx_buffer *new_buff; | |
6189 | u16 nta = rx_ring->next_to_alloc; | |
6190 | ||
6191 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
6192 | ||
6193 | /* update, and store next to alloc */ | |
6194 | nta++; | |
6195 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
6196 | ||
6197 | /* transfer page from old buffer to new buffer */ | |
6198 | memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); | |
6199 | ||
6200 | /* sync the buffer for use by the device */ | |
6201 | dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, | |
6202 | old_buff->page_offset, | |
de78d1f9 | 6203 | IGB_RX_BUFSZ, |
cbc8e55f AD |
6204 | DMA_FROM_DEVICE); |
6205 | } | |
6206 | ||
74e238ea AD |
6207 | static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, |
6208 | struct page *page, | |
6209 | unsigned int truesize) | |
6210 | { | |
6211 | /* avoid re-using remote pages */ | |
6212 | if (unlikely(page_to_nid(page) != numa_node_id())) | |
6213 | return false; | |
6214 | ||
6215 | #if (PAGE_SIZE < 8192) | |
6216 | /* if we are only owner of page we can reuse it */ | |
6217 | if (unlikely(page_count(page) != 1)) | |
6218 | return false; | |
6219 | ||
6220 | /* flip page offset to other buffer */ | |
6221 | rx_buffer->page_offset ^= IGB_RX_BUFSZ; | |
6222 | ||
6223 | /* since we are the only owner of the page and we need to | |
6224 | * increment it, just set the value to 2 in order to avoid | |
6225 | * an unnecessary locked operation | |
6226 | */ | |
6227 | atomic_set(&page->_count, 2); | |
6228 | #else | |
6229 | /* move offset up to the next cache line */ | |
6230 | rx_buffer->page_offset += truesize; | |
6231 | ||
6232 | if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) | |
6233 | return false; | |
6234 | ||
6235 | /* bump ref count on page before it is given to the stack */ | |
6236 | get_page(page); | |
6237 | #endif | |
6238 | ||
6239 | return true; | |
6240 | } | |
6241 | ||
cbc8e55f | 6242 | /** |
b980ac18 JK |
6243 | * igb_add_rx_frag - Add contents of Rx buffer to sk_buff |
6244 | * @rx_ring: rx descriptor ring to transact packets on | |
6245 | * @rx_buffer: buffer containing page to add | |
6246 | * @rx_desc: descriptor containing length of buffer written by hardware | |
6247 | * @skb: sk_buff to place the data into | |
cbc8e55f | 6248 | * |
b980ac18 JK |
6249 | * This function will add the data contained in rx_buffer->page to the skb. |
6250 | * This is done either through a direct copy if the data in the buffer is | |
6251 | * less than the skb header size, otherwise it will just attach the page as | |
6252 | * a frag to the skb. | |
cbc8e55f | 6253 | * |
b980ac18 JK |
6254 | * The function will then update the page offset if necessary and return |
6255 | * true if the buffer can be reused by the adapter. | |
cbc8e55f AD |
6256 | **/ |
6257 | static bool igb_add_rx_frag(struct igb_ring *rx_ring, | |
6258 | struct igb_rx_buffer *rx_buffer, | |
6259 | union e1000_adv_rx_desc *rx_desc, | |
6260 | struct sk_buff *skb) | |
6261 | { | |
6262 | struct page *page = rx_buffer->page; | |
6263 | unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); | |
74e238ea AD |
6264 | #if (PAGE_SIZE < 8192) |
6265 | unsigned int truesize = IGB_RX_BUFSZ; | |
6266 | #else | |
6267 | unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); | |
6268 | #endif | |
cbc8e55f AD |
6269 | |
6270 | if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { | |
6271 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
6272 | ||
cbc8e55f AD |
6273 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
6274 | igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); | |
6275 | va += IGB_TS_HDR_LEN; | |
6276 | size -= IGB_TS_HDR_LEN; | |
6277 | } | |
6278 | ||
cbc8e55f AD |
6279 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); |
6280 | ||
6281 | /* we can reuse buffer as-is, just make sure it is local */ | |
6282 | if (likely(page_to_nid(page) == numa_node_id())) | |
6283 | return true; | |
6284 | ||
6285 | /* this page cannot be reused so discard it */ | |
6286 | put_page(page); | |
6287 | return false; | |
6288 | } | |
6289 | ||
6290 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, | |
74e238ea | 6291 | rx_buffer->page_offset, size, truesize); |
cbc8e55f | 6292 | |
74e238ea AD |
6293 | return igb_can_reuse_rx_page(rx_buffer, page, truesize); |
6294 | } | |
cbc8e55f | 6295 | |
2e334eee AD |
6296 | static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, |
6297 | union e1000_adv_rx_desc *rx_desc, | |
6298 | struct sk_buff *skb) | |
6299 | { | |
6300 | struct igb_rx_buffer *rx_buffer; | |
6301 | struct page *page; | |
6302 | ||
6303 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
6304 | ||
2e334eee AD |
6305 | page = rx_buffer->page; |
6306 | prefetchw(page); | |
6307 | ||
6308 | if (likely(!skb)) { | |
6309 | void *page_addr = page_address(page) + | |
6310 | rx_buffer->page_offset; | |
6311 | ||
6312 | /* prefetch first cache line of first page */ | |
6313 | prefetch(page_addr); | |
6314 | #if L1_CACHE_BYTES < 128 | |
6315 | prefetch(page_addr + L1_CACHE_BYTES); | |
6316 | #endif | |
6317 | ||
6318 | /* allocate a skb to store the frags */ | |
6319 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
6320 | IGB_RX_HDR_LEN); | |
6321 | if (unlikely(!skb)) { | |
6322 | rx_ring->rx_stats.alloc_failed++; | |
6323 | return NULL; | |
6324 | } | |
6325 | ||
b980ac18 | 6326 | /* we will be copying header into skb->data in |
2e334eee AD |
6327 | * pskb_may_pull so it is in our interest to prefetch |
6328 | * it now to avoid a possible cache miss | |
6329 | */ | |
6330 | prefetchw(skb->data); | |
6331 | } | |
6332 | ||
6333 | /* we are reusing so sync this buffer for CPU use */ | |
6334 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
6335 | rx_buffer->dma, | |
6336 | rx_buffer->page_offset, | |
de78d1f9 | 6337 | IGB_RX_BUFSZ, |
2e334eee AD |
6338 | DMA_FROM_DEVICE); |
6339 | ||
6340 | /* pull page into skb */ | |
6341 | if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
6342 | /* hand second half of page back to the ring */ | |
6343 | igb_reuse_rx_page(rx_ring, rx_buffer); | |
6344 | } else { | |
6345 | /* we are not reusing the buffer so unmap it */ | |
6346 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
6347 | PAGE_SIZE, DMA_FROM_DEVICE); | |
6348 | } | |
6349 | ||
6350 | /* clear contents of rx_buffer */ | |
6351 | rx_buffer->page = NULL; | |
6352 | ||
6353 | return skb; | |
6354 | } | |
6355 | ||
cd392f5c | 6356 | static inline void igb_rx_checksum(struct igb_ring *ring, |
3ceb90fd AD |
6357 | union e1000_adv_rx_desc *rx_desc, |
6358 | struct sk_buff *skb) | |
9d5c8243 | 6359 | { |
bc8acf2c | 6360 | skb_checksum_none_assert(skb); |
9d5c8243 | 6361 | |
294e7d78 | 6362 | /* Ignore Checksum bit is set */ |
3ceb90fd | 6363 | if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) |
294e7d78 AD |
6364 | return; |
6365 | ||
6366 | /* Rx checksum disabled via ethtool */ | |
6367 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) | |
9d5c8243 | 6368 | return; |
85ad76b2 | 6369 | |
9d5c8243 | 6370 | /* TCP/UDP checksum error bit is set */ |
3ceb90fd AD |
6371 | if (igb_test_staterr(rx_desc, |
6372 | E1000_RXDEXT_STATERR_TCPE | | |
6373 | E1000_RXDEXT_STATERR_IPE)) { | |
b980ac18 | 6374 | /* work around errata with sctp packets where the TCPE aka |
b9473560 JB |
6375 | * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) |
6376 | * packets, (aka let the stack check the crc32c) | |
6377 | */ | |
866cff06 AD |
6378 | if (!((skb->len == 60) && |
6379 | test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { | |
12dcd86b | 6380 | u64_stats_update_begin(&ring->rx_syncp); |
04a5fcaa | 6381 | ring->rx_stats.csum_err++; |
12dcd86b ED |
6382 | u64_stats_update_end(&ring->rx_syncp); |
6383 | } | |
9d5c8243 | 6384 | /* let the stack verify checksum errors */ |
9d5c8243 AK |
6385 | return; |
6386 | } | |
6387 | /* It must be a TCP or UDP packet with a valid checksum */ | |
3ceb90fd AD |
6388 | if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | |
6389 | E1000_RXD_STAT_UDPCS)) | |
9d5c8243 AK |
6390 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
6391 | ||
3ceb90fd AD |
6392 | dev_dbg(ring->dev, "cksum success: bits %08X\n", |
6393 | le32_to_cpu(rx_desc->wb.upper.status_error)); | |
9d5c8243 AK |
6394 | } |
6395 | ||
077887c3 AD |
6396 | static inline void igb_rx_hash(struct igb_ring *ring, |
6397 | union e1000_adv_rx_desc *rx_desc, | |
6398 | struct sk_buff *skb) | |
6399 | { | |
6400 | if (ring->netdev->features & NETIF_F_RXHASH) | |
6401 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
6402 | } | |
6403 | ||
2e334eee | 6404 | /** |
b980ac18 JK |
6405 | * igb_is_non_eop - process handling of non-EOP buffers |
6406 | * @rx_ring: Rx ring being processed | |
6407 | * @rx_desc: Rx descriptor for current buffer | |
6408 | * @skb: current socket buffer containing buffer in progress | |
2e334eee | 6409 | * |
b980ac18 JK |
6410 | * This function updates next to clean. If the buffer is an EOP buffer |
6411 | * this function exits returning false, otherwise it will place the | |
6412 | * sk_buff in the next buffer to be chained and return true indicating | |
6413 | * that this is in fact a non-EOP buffer. | |
2e334eee AD |
6414 | **/ |
6415 | static bool igb_is_non_eop(struct igb_ring *rx_ring, | |
6416 | union e1000_adv_rx_desc *rx_desc) | |
6417 | { | |
6418 | u32 ntc = rx_ring->next_to_clean + 1; | |
6419 | ||
6420 | /* fetch, update, and store next to clean */ | |
6421 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
6422 | rx_ring->next_to_clean = ntc; | |
6423 | ||
6424 | prefetch(IGB_RX_DESC(rx_ring, ntc)); | |
6425 | ||
6426 | if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) | |
6427 | return false; | |
6428 | ||
6429 | return true; | |
6430 | } | |
6431 | ||
1a1c225b | 6432 | /** |
b980ac18 JK |
6433 | * igb_get_headlen - determine size of header for LRO/GRO |
6434 | * @data: pointer to the start of the headers | |
6435 | * @max_len: total length of section to find headers in | |
1a1c225b | 6436 | * |
b980ac18 JK |
6437 | * This function is meant to determine the length of headers that will |
6438 | * be recognized by hardware for LRO, and GRO offloads. The main | |
6439 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
6440 | * packets so that we can do basic things like calculating the gso_size | |
6441 | * based on the average data per packet. | |
1a1c225b AD |
6442 | **/ |
6443 | static unsigned int igb_get_headlen(unsigned char *data, | |
6444 | unsigned int max_len) | |
6445 | { | |
6446 | union { | |
6447 | unsigned char *network; | |
6448 | /* l2 headers */ | |
6449 | struct ethhdr *eth; | |
6450 | struct vlan_hdr *vlan; | |
6451 | /* l3 headers */ | |
6452 | struct iphdr *ipv4; | |
6453 | struct ipv6hdr *ipv6; | |
6454 | } hdr; | |
6455 | __be16 protocol; | |
6456 | u8 nexthdr = 0; /* default to not TCP */ | |
6457 | u8 hlen; | |
6458 | ||
6459 | /* this should never happen, but better safe than sorry */ | |
6460 | if (max_len < ETH_HLEN) | |
6461 | return max_len; | |
6462 | ||
6463 | /* initialize network frame pointer */ | |
6464 | hdr.network = data; | |
6465 | ||
6466 | /* set first protocol and move network header forward */ | |
6467 | protocol = hdr.eth->h_proto; | |
6468 | hdr.network += ETH_HLEN; | |
6469 | ||
6470 | /* handle any vlan tag if present */ | |
6471 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6472 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
6473 | return max_len; | |
6474 | ||
6475 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
6476 | hdr.network += VLAN_HLEN; | |
6477 | } | |
6478 | ||
6479 | /* handle L3 protocols */ | |
6480 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6481 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
6482 | return max_len; | |
6483 | ||
6484 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
6485 | hlen = (hdr.network[0] & 0x0F) << 2; | |
6486 | ||
6487 | /* verify hlen meets minimum size requirements */ | |
6488 | if (hlen < sizeof(struct iphdr)) | |
6489 | return hdr.network - data; | |
6490 | ||
f2fb4ab2 | 6491 | /* record next protocol if header is present */ |
b9555f66 | 6492 | if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) |
f2fb4ab2 | 6493 | nexthdr = hdr.ipv4->protocol; |
1a1c225b AD |
6494 | } else if (protocol == __constant_htons(ETH_P_IPV6)) { |
6495 | if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) | |
6496 | return max_len; | |
6497 | ||
6498 | /* record next protocol */ | |
6499 | nexthdr = hdr.ipv6->nexthdr; | |
f2fb4ab2 | 6500 | hlen = sizeof(struct ipv6hdr); |
1a1c225b AD |
6501 | } else { |
6502 | return hdr.network - data; | |
6503 | } | |
6504 | ||
f2fb4ab2 AD |
6505 | /* relocate pointer to start of L4 header */ |
6506 | hdr.network += hlen; | |
6507 | ||
1a1c225b AD |
6508 | /* finally sort out TCP */ |
6509 | if (nexthdr == IPPROTO_TCP) { | |
6510 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
6511 | return max_len; | |
6512 | ||
6513 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
6514 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
6515 | ||
6516 | /* verify hlen meets minimum size requirements */ | |
6517 | if (hlen < sizeof(struct tcphdr)) | |
6518 | return hdr.network - data; | |
6519 | ||
6520 | hdr.network += hlen; | |
6521 | } else if (nexthdr == IPPROTO_UDP) { | |
6522 | if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) | |
6523 | return max_len; | |
6524 | ||
6525 | hdr.network += sizeof(struct udphdr); | |
6526 | } | |
6527 | ||
b980ac18 | 6528 | /* If everything has gone correctly hdr.network should be the |
1a1c225b AD |
6529 | * data section of the packet and will be the end of the header. |
6530 | * If not then it probably represents the end of the last recognized | |
6531 | * header. | |
6532 | */ | |
6533 | if ((hdr.network - data) < max_len) | |
6534 | return hdr.network - data; | |
6535 | else | |
6536 | return max_len; | |
6537 | } | |
6538 | ||
6539 | /** | |
b980ac18 JK |
6540 | * igb_pull_tail - igb specific version of skb_pull_tail |
6541 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6542 | * @rx_desc: pointer to the EOP Rx descriptor | |
6543 | * @skb: pointer to current skb being adjusted | |
1a1c225b | 6544 | * |
b980ac18 JK |
6545 | * This function is an igb specific version of __pskb_pull_tail. The |
6546 | * main difference between this version and the original function is that | |
6547 | * this function can make several assumptions about the state of things | |
6548 | * that allow for significant optimizations versus the standard function. | |
6549 | * As a result we can do things like drop a frag and maintain an accurate | |
6550 | * truesize for the skb. | |
1a1c225b AD |
6551 | */ |
6552 | static void igb_pull_tail(struct igb_ring *rx_ring, | |
6553 | union e1000_adv_rx_desc *rx_desc, | |
6554 | struct sk_buff *skb) | |
2d94d8ab | 6555 | { |
1a1c225b AD |
6556 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
6557 | unsigned char *va; | |
6558 | unsigned int pull_len; | |
6559 | ||
b980ac18 | 6560 | /* it is valid to use page_address instead of kmap since we are |
1a1c225b AD |
6561 | * working with pages allocated out of the lomem pool per |
6562 | * alloc_page(GFP_ATOMIC) | |
2d94d8ab | 6563 | */ |
1a1c225b AD |
6564 | va = skb_frag_address(frag); |
6565 | ||
1a1c225b AD |
6566 | if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { |
6567 | /* retrieve timestamp from buffer */ | |
6568 | igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); | |
6569 | ||
6570 | /* update pointers to remove timestamp header */ | |
6571 | skb_frag_size_sub(frag, IGB_TS_HDR_LEN); | |
6572 | frag->page_offset += IGB_TS_HDR_LEN; | |
6573 | skb->data_len -= IGB_TS_HDR_LEN; | |
6574 | skb->len -= IGB_TS_HDR_LEN; | |
6575 | ||
6576 | /* move va to start of packet data */ | |
6577 | va += IGB_TS_HDR_LEN; | |
6578 | } | |
6579 | ||
b980ac18 | 6580 | /* we need the header to contain the greater of either ETH_HLEN or |
1a1c225b AD |
6581 | * 60 bytes if the skb->len is less than 60 for skb_pad. |
6582 | */ | |
6583 | pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); | |
6584 | ||
6585 | /* align pull length to size of long to optimize memcpy performance */ | |
6586 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
6587 | ||
6588 | /* update all of the pointers */ | |
6589 | skb_frag_size_sub(frag, pull_len); | |
6590 | frag->page_offset += pull_len; | |
6591 | skb->data_len -= pull_len; | |
6592 | skb->tail += pull_len; | |
6593 | } | |
6594 | ||
6595 | /** | |
b980ac18 JK |
6596 | * igb_cleanup_headers - Correct corrupted or empty headers |
6597 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6598 | * @rx_desc: pointer to the EOP Rx descriptor | |
6599 | * @skb: pointer to current skb being fixed | |
1a1c225b | 6600 | * |
b980ac18 JK |
6601 | * Address the case where we are pulling data in on pages only |
6602 | * and as such no data is present in the skb header. | |
1a1c225b | 6603 | * |
b980ac18 JK |
6604 | * In addition if skb is not at least 60 bytes we need to pad it so that |
6605 | * it is large enough to qualify as a valid Ethernet frame. | |
1a1c225b | 6606 | * |
b980ac18 | 6607 | * Returns true if an error was encountered and skb was freed. |
1a1c225b AD |
6608 | **/ |
6609 | static bool igb_cleanup_headers(struct igb_ring *rx_ring, | |
6610 | union e1000_adv_rx_desc *rx_desc, | |
6611 | struct sk_buff *skb) | |
6612 | { | |
1a1c225b AD |
6613 | if (unlikely((igb_test_staterr(rx_desc, |
6614 | E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { | |
6615 | struct net_device *netdev = rx_ring->netdev; | |
6616 | if (!(netdev->features & NETIF_F_RXALL)) { | |
6617 | dev_kfree_skb_any(skb); | |
6618 | return true; | |
6619 | } | |
6620 | } | |
6621 | ||
6622 | /* place header in linear portion of buffer */ | |
6623 | if (skb_is_nonlinear(skb)) | |
6624 | igb_pull_tail(rx_ring, rx_desc, skb); | |
6625 | ||
6626 | /* if skb_pad returns an error the skb was freed */ | |
6627 | if (unlikely(skb->len < 60)) { | |
6628 | int pad_len = 60 - skb->len; | |
6629 | ||
6630 | if (skb_pad(skb, pad_len)) | |
6631 | return true; | |
6632 | __skb_put(skb, pad_len); | |
6633 | } | |
6634 | ||
6635 | return false; | |
2d94d8ab AD |
6636 | } |
6637 | ||
db2ee5bd | 6638 | /** |
b980ac18 JK |
6639 | * igb_process_skb_fields - Populate skb header fields from Rx descriptor |
6640 | * @rx_ring: rx descriptor ring packet is being transacted on | |
6641 | * @rx_desc: pointer to the EOP Rx descriptor | |
6642 | * @skb: pointer to current skb being populated | |
db2ee5bd | 6643 | * |
b980ac18 JK |
6644 | * This function checks the ring, descriptor, and packet information in |
6645 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
6646 | * other fields within the skb. | |
db2ee5bd AD |
6647 | **/ |
6648 | static void igb_process_skb_fields(struct igb_ring *rx_ring, | |
6649 | union e1000_adv_rx_desc *rx_desc, | |
6650 | struct sk_buff *skb) | |
6651 | { | |
6652 | struct net_device *dev = rx_ring->netdev; | |
6653 | ||
6654 | igb_rx_hash(rx_ring, rx_desc, skb); | |
6655 | ||
6656 | igb_rx_checksum(rx_ring, rx_desc, skb); | |
6657 | ||
20a48412 | 6658 | igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); |
db2ee5bd | 6659 | |
f646968f | 6660 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
db2ee5bd AD |
6661 | igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { |
6662 | u16 vid; | |
6663 | if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && | |
6664 | test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) | |
6665 | vid = be16_to_cpu(rx_desc->wb.upper.vlan); | |
6666 | else | |
6667 | vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
6668 | ||
86a9bad3 | 6669 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
db2ee5bd AD |
6670 | } |
6671 | ||
6672 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
6673 | ||
6674 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
6675 | } | |
6676 | ||
2e334eee | 6677 | static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) |
9d5c8243 | 6678 | { |
0ba82994 | 6679 | struct igb_ring *rx_ring = q_vector->rx.ring; |
1a1c225b | 6680 | struct sk_buff *skb = rx_ring->skb; |
9d5c8243 | 6681 | unsigned int total_bytes = 0, total_packets = 0; |
16eb8815 | 6682 | u16 cleaned_count = igb_desc_unused(rx_ring); |
9d5c8243 | 6683 | |
2e334eee AD |
6684 | do { |
6685 | union e1000_adv_rx_desc *rx_desc; | |
bf36c1a0 | 6686 | |
2e334eee AD |
6687 | /* return some buffers to hardware, one at a time is too slow */ |
6688 | if (cleaned_count >= IGB_RX_BUFFER_WRITE) { | |
6689 | igb_alloc_rx_buffers(rx_ring, cleaned_count); | |
6690 | cleaned_count = 0; | |
6691 | } | |
bf36c1a0 | 6692 | |
2e334eee | 6693 | rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); |
16eb8815 | 6694 | |
2e334eee AD |
6695 | if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) |
6696 | break; | |
9d5c8243 | 6697 | |
74e238ea AD |
6698 | /* This memory barrier is needed to keep us from reading |
6699 | * any other fields out of the rx_desc until we know the | |
6700 | * RXD_STAT_DD bit is set | |
6701 | */ | |
6702 | rmb(); | |
6703 | ||
2e334eee | 6704 | /* retrieve a buffer from the ring */ |
f9d40f6a | 6705 | skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); |
9d5c8243 | 6706 | |
2e334eee AD |
6707 | /* exit if we failed to retrieve a buffer */ |
6708 | if (!skb) | |
6709 | break; | |
1a1c225b | 6710 | |
2e334eee | 6711 | cleaned_count++; |
1a1c225b | 6712 | |
2e334eee AD |
6713 | /* fetch next buffer in frame if non-eop */ |
6714 | if (igb_is_non_eop(rx_ring, rx_desc)) | |
6715 | continue; | |
1a1c225b AD |
6716 | |
6717 | /* verify the packet layout is correct */ | |
6718 | if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { | |
6719 | skb = NULL; | |
6720 | continue; | |
9d5c8243 | 6721 | } |
9d5c8243 | 6722 | |
db2ee5bd | 6723 | /* probably a little skewed due to removing CRC */ |
3ceb90fd | 6724 | total_bytes += skb->len; |
3ceb90fd | 6725 | |
db2ee5bd AD |
6726 | /* populate checksum, timestamp, VLAN, and protocol */ |
6727 | igb_process_skb_fields(rx_ring, rx_desc, skb); | |
3ceb90fd | 6728 | |
b2cb09b1 | 6729 | napi_gro_receive(&q_vector->napi, skb); |
9d5c8243 | 6730 | |
1a1c225b AD |
6731 | /* reset skb pointer */ |
6732 | skb = NULL; | |
6733 | ||
2e334eee AD |
6734 | /* update budget accounting */ |
6735 | total_packets++; | |
6736 | } while (likely(total_packets < budget)); | |
bf36c1a0 | 6737 | |
1a1c225b AD |
6738 | /* place incomplete frames back on ring for completion */ |
6739 | rx_ring->skb = skb; | |
6740 | ||
12dcd86b | 6741 | u64_stats_update_begin(&rx_ring->rx_syncp); |
9d5c8243 AK |
6742 | rx_ring->rx_stats.packets += total_packets; |
6743 | rx_ring->rx_stats.bytes += total_bytes; | |
12dcd86b | 6744 | u64_stats_update_end(&rx_ring->rx_syncp); |
0ba82994 AD |
6745 | q_vector->rx.total_packets += total_packets; |
6746 | q_vector->rx.total_bytes += total_bytes; | |
c023cd88 AD |
6747 | |
6748 | if (cleaned_count) | |
cd392f5c | 6749 | igb_alloc_rx_buffers(rx_ring, cleaned_count); |
c023cd88 | 6750 | |
2e334eee | 6751 | return (total_packets < budget); |
9d5c8243 AK |
6752 | } |
6753 | ||
c023cd88 | 6754 | static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, |
06034649 | 6755 | struct igb_rx_buffer *bi) |
c023cd88 AD |
6756 | { |
6757 | struct page *page = bi->page; | |
cbc8e55f | 6758 | dma_addr_t dma; |
c023cd88 | 6759 | |
cbc8e55f AD |
6760 | /* since we are recycling buffers we should seldom need to alloc */ |
6761 | if (likely(page)) | |
c023cd88 AD |
6762 | return true; |
6763 | ||
cbc8e55f AD |
6764 | /* alloc new page for storage */ |
6765 | page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); | |
6766 | if (unlikely(!page)) { | |
6767 | rx_ring->rx_stats.alloc_failed++; | |
6768 | return false; | |
c023cd88 AD |
6769 | } |
6770 | ||
cbc8e55f AD |
6771 | /* map page for use */ |
6772 | dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
c023cd88 | 6773 | |
b980ac18 | 6774 | /* if mapping failed free memory back to system since |
cbc8e55f AD |
6775 | * there isn't much point in holding memory we can't use |
6776 | */ | |
1a1c225b | 6777 | if (dma_mapping_error(rx_ring->dev, dma)) { |
cbc8e55f AD |
6778 | __free_page(page); |
6779 | ||
c023cd88 AD |
6780 | rx_ring->rx_stats.alloc_failed++; |
6781 | return false; | |
6782 | } | |
6783 | ||
1a1c225b | 6784 | bi->dma = dma; |
cbc8e55f AD |
6785 | bi->page = page; |
6786 | bi->page_offset = 0; | |
1a1c225b | 6787 | |
c023cd88 AD |
6788 | return true; |
6789 | } | |
6790 | ||
9d5c8243 | 6791 | /** |
b980ac18 JK |
6792 | * igb_alloc_rx_buffers - Replace used receive buffers; packet split |
6793 | * @adapter: address of board private structure | |
9d5c8243 | 6794 | **/ |
cd392f5c | 6795 | void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) |
9d5c8243 | 6796 | { |
9d5c8243 | 6797 | union e1000_adv_rx_desc *rx_desc; |
06034649 | 6798 | struct igb_rx_buffer *bi; |
c023cd88 | 6799 | u16 i = rx_ring->next_to_use; |
9d5c8243 | 6800 | |
cbc8e55f AD |
6801 | /* nothing to do */ |
6802 | if (!cleaned_count) | |
6803 | return; | |
6804 | ||
60136906 | 6805 | rx_desc = IGB_RX_DESC(rx_ring, i); |
06034649 | 6806 | bi = &rx_ring->rx_buffer_info[i]; |
c023cd88 | 6807 | i -= rx_ring->count; |
9d5c8243 | 6808 | |
cbc8e55f | 6809 | do { |
1a1c225b | 6810 | if (!igb_alloc_mapped_page(rx_ring, bi)) |
c023cd88 | 6811 | break; |
9d5c8243 | 6812 | |
b980ac18 | 6813 | /* Refresh the desc even if buffer_addrs didn't change |
cbc8e55f AD |
6814 | * because each write-back erases this info. |
6815 | */ | |
f9d40f6a | 6816 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); |
9d5c8243 | 6817 | |
c023cd88 AD |
6818 | rx_desc++; |
6819 | bi++; | |
9d5c8243 | 6820 | i++; |
c023cd88 | 6821 | if (unlikely(!i)) { |
60136906 | 6822 | rx_desc = IGB_RX_DESC(rx_ring, 0); |
06034649 | 6823 | bi = rx_ring->rx_buffer_info; |
c023cd88 AD |
6824 | i -= rx_ring->count; |
6825 | } | |
6826 | ||
6827 | /* clear the hdr_addr for the next_to_use descriptor */ | |
6828 | rx_desc->read.hdr_addr = 0; | |
cbc8e55f AD |
6829 | |
6830 | cleaned_count--; | |
6831 | } while (cleaned_count); | |
9d5c8243 | 6832 | |
c023cd88 AD |
6833 | i += rx_ring->count; |
6834 | ||
9d5c8243 | 6835 | if (rx_ring->next_to_use != i) { |
cbc8e55f | 6836 | /* record the next descriptor to use */ |
9d5c8243 | 6837 | rx_ring->next_to_use = i; |
9d5c8243 | 6838 | |
cbc8e55f AD |
6839 | /* update next to alloc since we have filled the ring */ |
6840 | rx_ring->next_to_alloc = i; | |
6841 | ||
b980ac18 | 6842 | /* Force memory writes to complete before letting h/w |
9d5c8243 AK |
6843 | * know there are new descriptors to fetch. (Only |
6844 | * applicable for weak-ordered memory model archs, | |
cbc8e55f AD |
6845 | * such as IA-64). |
6846 | */ | |
9d5c8243 | 6847 | wmb(); |
fce99e34 | 6848 | writel(i, rx_ring->tail); |
9d5c8243 AK |
6849 | } |
6850 | } | |
6851 | ||
6852 | /** | |
6853 | * igb_mii_ioctl - | |
6854 | * @netdev: | |
6855 | * @ifreq: | |
6856 | * @cmd: | |
6857 | **/ | |
6858 | static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6859 | { | |
6860 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6861 | struct mii_ioctl_data *data = if_mii(ifr); | |
6862 | ||
6863 | if (adapter->hw.phy.media_type != e1000_media_type_copper) | |
6864 | return -EOPNOTSUPP; | |
6865 | ||
6866 | switch (cmd) { | |
6867 | case SIOCGMIIPHY: | |
6868 | data->phy_id = adapter->hw.phy.addr; | |
6869 | break; | |
6870 | case SIOCGMIIREG: | |
f5f4cf08 AD |
6871 | if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, |
6872 | &data->val_out)) | |
9d5c8243 AK |
6873 | return -EIO; |
6874 | break; | |
6875 | case SIOCSMIIREG: | |
6876 | default: | |
6877 | return -EOPNOTSUPP; | |
6878 | } | |
6879 | return 0; | |
6880 | } | |
6881 | ||
6882 | /** | |
6883 | * igb_ioctl - | |
6884 | * @netdev: | |
6885 | * @ifreq: | |
6886 | * @cmd: | |
6887 | **/ | |
6888 | static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
6889 | { | |
6890 | switch (cmd) { | |
6891 | case SIOCGMIIPHY: | |
6892 | case SIOCGMIIREG: | |
6893 | case SIOCSMIIREG: | |
6894 | return igb_mii_ioctl(netdev, ifr, cmd); | |
c6cb090b | 6895 | case SIOCSHWTSTAMP: |
a79f4f88 | 6896 | return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); |
9d5c8243 AK |
6897 | default: |
6898 | return -EOPNOTSUPP; | |
6899 | } | |
6900 | } | |
6901 | ||
009bc06e AD |
6902 | s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) |
6903 | { | |
6904 | struct igb_adapter *adapter = hw->back; | |
009bc06e | 6905 | |
23d028cc | 6906 | if (pcie_capability_read_word(adapter->pdev, reg, value)) |
009bc06e AD |
6907 | return -E1000_ERR_CONFIG; |
6908 | ||
009bc06e AD |
6909 | return 0; |
6910 | } | |
6911 | ||
6912 | s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) | |
6913 | { | |
6914 | struct igb_adapter *adapter = hw->back; | |
009bc06e | 6915 | |
23d028cc | 6916 | if (pcie_capability_write_word(adapter->pdev, reg, *value)) |
009bc06e AD |
6917 | return -E1000_ERR_CONFIG; |
6918 | ||
009bc06e AD |
6919 | return 0; |
6920 | } | |
6921 | ||
c8f44aff | 6922 | static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) |
9d5c8243 AK |
6923 | { |
6924 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6925 | struct e1000_hw *hw = &adapter->hw; | |
6926 | u32 ctrl, rctl; | |
f646968f | 6927 | bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); |
9d5c8243 | 6928 | |
5faf030c | 6929 | if (enable) { |
9d5c8243 AK |
6930 | /* enable VLAN tag insert/strip */ |
6931 | ctrl = rd32(E1000_CTRL); | |
6932 | ctrl |= E1000_CTRL_VME; | |
6933 | wr32(E1000_CTRL, ctrl); | |
6934 | ||
51466239 | 6935 | /* Disable CFI check */ |
9d5c8243 | 6936 | rctl = rd32(E1000_RCTL); |
9d5c8243 AK |
6937 | rctl &= ~E1000_RCTL_CFIEN; |
6938 | wr32(E1000_RCTL, rctl); | |
9d5c8243 AK |
6939 | } else { |
6940 | /* disable VLAN tag insert/strip */ | |
6941 | ctrl = rd32(E1000_CTRL); | |
6942 | ctrl &= ~E1000_CTRL_VME; | |
6943 | wr32(E1000_CTRL, ctrl); | |
9d5c8243 AK |
6944 | } |
6945 | ||
e1739522 | 6946 | igb_rlpml_set(adapter); |
9d5c8243 AK |
6947 | } |
6948 | ||
80d5c368 PM |
6949 | static int igb_vlan_rx_add_vid(struct net_device *netdev, |
6950 | __be16 proto, u16 vid) | |
9d5c8243 AK |
6951 | { |
6952 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6953 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6954 | int pf_id = adapter->vfs_allocated_count; |
9d5c8243 | 6955 | |
51466239 AD |
6956 | /* attempt to add filter to vlvf array */ |
6957 | igb_vlvf_set(adapter, vid, true, pf_id); | |
4ae196df | 6958 | |
51466239 AD |
6959 | /* add the filter since PF can receive vlans w/o entry in vlvf */ |
6960 | igb_vfta_set(hw, vid, true); | |
b2cb09b1 JP |
6961 | |
6962 | set_bit(vid, adapter->active_vlans); | |
8e586137 JP |
6963 | |
6964 | return 0; | |
9d5c8243 AK |
6965 | } |
6966 | ||
80d5c368 PM |
6967 | static int igb_vlan_rx_kill_vid(struct net_device *netdev, |
6968 | __be16 proto, u16 vid) | |
9d5c8243 AK |
6969 | { |
6970 | struct igb_adapter *adapter = netdev_priv(netdev); | |
6971 | struct e1000_hw *hw = &adapter->hw; | |
4ae196df | 6972 | int pf_id = adapter->vfs_allocated_count; |
51466239 | 6973 | s32 err; |
9d5c8243 | 6974 | |
51466239 AD |
6975 | /* remove vlan from VLVF table array */ |
6976 | err = igb_vlvf_set(adapter, vid, false, pf_id); | |
9d5c8243 | 6977 | |
51466239 AD |
6978 | /* if vid was not present in VLVF just remove it from table */ |
6979 | if (err) | |
4ae196df | 6980 | igb_vfta_set(hw, vid, false); |
b2cb09b1 JP |
6981 | |
6982 | clear_bit(vid, adapter->active_vlans); | |
8e586137 JP |
6983 | |
6984 | return 0; | |
9d5c8243 AK |
6985 | } |
6986 | ||
6987 | static void igb_restore_vlan(struct igb_adapter *adapter) | |
6988 | { | |
b2cb09b1 | 6989 | u16 vid; |
9d5c8243 | 6990 | |
5faf030c AD |
6991 | igb_vlan_mode(adapter->netdev, adapter->netdev->features); |
6992 | ||
b2cb09b1 | 6993 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
80d5c368 | 6994 | igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); |
9d5c8243 AK |
6995 | } |
6996 | ||
14ad2513 | 6997 | int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) |
9d5c8243 | 6998 | { |
090b1795 | 6999 | struct pci_dev *pdev = adapter->pdev; |
9d5c8243 AK |
7000 | struct e1000_mac_info *mac = &adapter->hw.mac; |
7001 | ||
7002 | mac->autoneg = 0; | |
7003 | ||
14ad2513 | 7004 | /* Make sure dplx is at most 1 bit and lsb of speed is not set |
b980ac18 JK |
7005 | * for the switch() below to work |
7006 | */ | |
14ad2513 DD |
7007 | if ((spd & 1) || (dplx & ~1)) |
7008 | goto err_inval; | |
7009 | ||
f502ef7d AA |
7010 | /* Fiber NIC's only allow 1000 gbps Full duplex |
7011 | * and 100Mbps Full duplex for 100baseFx sfp | |
7012 | */ | |
7013 | if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { | |
7014 | switch (spd + dplx) { | |
7015 | case SPEED_10 + DUPLEX_HALF: | |
7016 | case SPEED_10 + DUPLEX_FULL: | |
7017 | case SPEED_100 + DUPLEX_HALF: | |
7018 | goto err_inval; | |
7019 | default: | |
7020 | break; | |
7021 | } | |
7022 | } | |
cd2638a8 | 7023 | |
14ad2513 | 7024 | switch (spd + dplx) { |
9d5c8243 AK |
7025 | case SPEED_10 + DUPLEX_HALF: |
7026 | mac->forced_speed_duplex = ADVERTISE_10_HALF; | |
7027 | break; | |
7028 | case SPEED_10 + DUPLEX_FULL: | |
7029 | mac->forced_speed_duplex = ADVERTISE_10_FULL; | |
7030 | break; | |
7031 | case SPEED_100 + DUPLEX_HALF: | |
7032 | mac->forced_speed_duplex = ADVERTISE_100_HALF; | |
7033 | break; | |
7034 | case SPEED_100 + DUPLEX_FULL: | |
7035 | mac->forced_speed_duplex = ADVERTISE_100_FULL; | |
7036 | break; | |
7037 | case SPEED_1000 + DUPLEX_FULL: | |
7038 | mac->autoneg = 1; | |
7039 | adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; | |
7040 | break; | |
7041 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | |
7042 | default: | |
14ad2513 | 7043 | goto err_inval; |
9d5c8243 | 7044 | } |
8376dad0 JB |
7045 | |
7046 | /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ | |
7047 | adapter->hw.phy.mdix = AUTO_ALL_MODES; | |
7048 | ||
9d5c8243 | 7049 | return 0; |
14ad2513 DD |
7050 | |
7051 | err_inval: | |
7052 | dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); | |
7053 | return -EINVAL; | |
9d5c8243 AK |
7054 | } |
7055 | ||
749ab2cd YZ |
7056 | static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, |
7057 | bool runtime) | |
9d5c8243 AK |
7058 | { |
7059 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7060 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7061 | struct e1000_hw *hw = &adapter->hw; | |
2d064c06 | 7062 | u32 ctrl, rctl, status; |
749ab2cd | 7063 | u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; |
9d5c8243 AK |
7064 | #ifdef CONFIG_PM |
7065 | int retval = 0; | |
7066 | #endif | |
7067 | ||
7068 | netif_device_detach(netdev); | |
7069 | ||
a88f10ec | 7070 | if (netif_running(netdev)) |
749ab2cd | 7071 | __igb_close(netdev, true); |
a88f10ec | 7072 | |
047e0030 | 7073 | igb_clear_interrupt_scheme(adapter); |
9d5c8243 AK |
7074 | |
7075 | #ifdef CONFIG_PM | |
7076 | retval = pci_save_state(pdev); | |
7077 | if (retval) | |
7078 | return retval; | |
7079 | #endif | |
7080 | ||
7081 | status = rd32(E1000_STATUS); | |
7082 | if (status & E1000_STATUS_LU) | |
7083 | wufc &= ~E1000_WUFC_LNKC; | |
7084 | ||
7085 | if (wufc) { | |
7086 | igb_setup_rctl(adapter); | |
ff41f8dc | 7087 | igb_set_rx_mode(netdev); |
9d5c8243 AK |
7088 | |
7089 | /* turn on all-multi mode if wake on multicast is enabled */ | |
7090 | if (wufc & E1000_WUFC_MC) { | |
7091 | rctl = rd32(E1000_RCTL); | |
7092 | rctl |= E1000_RCTL_MPE; | |
7093 | wr32(E1000_RCTL, rctl); | |
7094 | } | |
7095 | ||
7096 | ctrl = rd32(E1000_CTRL); | |
7097 | /* advertise wake from D3Cold */ | |
7098 | #define E1000_CTRL_ADVD3WUC 0x00100000 | |
7099 | /* phy power management enable */ | |
7100 | #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 | |
7101 | ctrl |= E1000_CTRL_ADVD3WUC; | |
7102 | wr32(E1000_CTRL, ctrl); | |
7103 | ||
9d5c8243 | 7104 | /* Allow time for pending master requests to run */ |
330a6d6a | 7105 | igb_disable_pcie_master(hw); |
9d5c8243 AK |
7106 | |
7107 | wr32(E1000_WUC, E1000_WUC_PME_EN); | |
7108 | wr32(E1000_WUFC, wufc); | |
9d5c8243 AK |
7109 | } else { |
7110 | wr32(E1000_WUC, 0); | |
7111 | wr32(E1000_WUFC, 0); | |
9d5c8243 AK |
7112 | } |
7113 | ||
3fe7c4c9 RW |
7114 | *enable_wake = wufc || adapter->en_mng_pt; |
7115 | if (!*enable_wake) | |
88a268c1 NN |
7116 | igb_power_down_link(adapter); |
7117 | else | |
7118 | igb_power_up_link(adapter); | |
9d5c8243 AK |
7119 | |
7120 | /* Release control of h/w to f/w. If f/w is AMT enabled, this | |
b980ac18 JK |
7121 | * would have already happened in close and is redundant. |
7122 | */ | |
9d5c8243 AK |
7123 | igb_release_hw_control(adapter); |
7124 | ||
7125 | pci_disable_device(pdev); | |
7126 | ||
9d5c8243 AK |
7127 | return 0; |
7128 | } | |
7129 | ||
7130 | #ifdef CONFIG_PM | |
d9dd966d | 7131 | #ifdef CONFIG_PM_SLEEP |
749ab2cd | 7132 | static int igb_suspend(struct device *dev) |
3fe7c4c9 RW |
7133 | { |
7134 | int retval; | |
7135 | bool wake; | |
749ab2cd | 7136 | struct pci_dev *pdev = to_pci_dev(dev); |
3fe7c4c9 | 7137 | |
749ab2cd | 7138 | retval = __igb_shutdown(pdev, &wake, 0); |
3fe7c4c9 RW |
7139 | if (retval) |
7140 | return retval; | |
7141 | ||
7142 | if (wake) { | |
7143 | pci_prepare_to_sleep(pdev); | |
7144 | } else { | |
7145 | pci_wake_from_d3(pdev, false); | |
7146 | pci_set_power_state(pdev, PCI_D3hot); | |
7147 | } | |
7148 | ||
7149 | return 0; | |
7150 | } | |
d9dd966d | 7151 | #endif /* CONFIG_PM_SLEEP */ |
3fe7c4c9 | 7152 | |
749ab2cd | 7153 | static int igb_resume(struct device *dev) |
9d5c8243 | 7154 | { |
749ab2cd | 7155 | struct pci_dev *pdev = to_pci_dev(dev); |
9d5c8243 AK |
7156 | struct net_device *netdev = pci_get_drvdata(pdev); |
7157 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7158 | struct e1000_hw *hw = &adapter->hw; | |
7159 | u32 err; | |
7160 | ||
7161 | pci_set_power_state(pdev, PCI_D0); | |
7162 | pci_restore_state(pdev); | |
b94f2d77 | 7163 | pci_save_state(pdev); |
42bfd33a | 7164 | |
aed5dec3 | 7165 | err = pci_enable_device_mem(pdev); |
9d5c8243 AK |
7166 | if (err) { |
7167 | dev_err(&pdev->dev, | |
7168 | "igb: Cannot enable PCI device from suspend\n"); | |
7169 | return err; | |
7170 | } | |
7171 | pci_set_master(pdev); | |
7172 | ||
7173 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
7174 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
7175 | ||
53c7d064 | 7176 | if (igb_init_interrupt_scheme(adapter, true)) { |
a88f10ec AD |
7177 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); |
7178 | return -ENOMEM; | |
9d5c8243 AK |
7179 | } |
7180 | ||
9d5c8243 | 7181 | igb_reset(adapter); |
a8564f03 AD |
7182 | |
7183 | /* let the f/w know that the h/w is now under the control of the | |
b980ac18 JK |
7184 | * driver. |
7185 | */ | |
a8564f03 AD |
7186 | igb_get_hw_control(adapter); |
7187 | ||
9d5c8243 AK |
7188 | wr32(E1000_WUS, ~0); |
7189 | ||
749ab2cd | 7190 | if (netdev->flags & IFF_UP) { |
0c2cc02e | 7191 | rtnl_lock(); |
749ab2cd | 7192 | err = __igb_open(netdev, true); |
0c2cc02e | 7193 | rtnl_unlock(); |
a88f10ec AD |
7194 | if (err) |
7195 | return err; | |
7196 | } | |
9d5c8243 AK |
7197 | |
7198 | netif_device_attach(netdev); | |
749ab2cd YZ |
7199 | return 0; |
7200 | } | |
7201 | ||
7202 | #ifdef CONFIG_PM_RUNTIME | |
7203 | static int igb_runtime_idle(struct device *dev) | |
7204 | { | |
7205 | struct pci_dev *pdev = to_pci_dev(dev); | |
7206 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7207 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7208 | ||
7209 | if (!igb_has_link(adapter)) | |
7210 | pm_schedule_suspend(dev, MSEC_PER_SEC * 5); | |
7211 | ||
7212 | return -EBUSY; | |
7213 | } | |
7214 | ||
7215 | static int igb_runtime_suspend(struct device *dev) | |
7216 | { | |
7217 | struct pci_dev *pdev = to_pci_dev(dev); | |
7218 | int retval; | |
7219 | bool wake; | |
7220 | ||
7221 | retval = __igb_shutdown(pdev, &wake, 1); | |
7222 | if (retval) | |
7223 | return retval; | |
7224 | ||
7225 | if (wake) { | |
7226 | pci_prepare_to_sleep(pdev); | |
7227 | } else { | |
7228 | pci_wake_from_d3(pdev, false); | |
7229 | pci_set_power_state(pdev, PCI_D3hot); | |
7230 | } | |
9d5c8243 | 7231 | |
9d5c8243 AK |
7232 | return 0; |
7233 | } | |
749ab2cd YZ |
7234 | |
7235 | static int igb_runtime_resume(struct device *dev) | |
7236 | { | |
7237 | return igb_resume(dev); | |
7238 | } | |
7239 | #endif /* CONFIG_PM_RUNTIME */ | |
9d5c8243 AK |
7240 | #endif |
7241 | ||
7242 | static void igb_shutdown(struct pci_dev *pdev) | |
7243 | { | |
3fe7c4c9 RW |
7244 | bool wake; |
7245 | ||
749ab2cd | 7246 | __igb_shutdown(pdev, &wake, 0); |
3fe7c4c9 RW |
7247 | |
7248 | if (system_state == SYSTEM_POWER_OFF) { | |
7249 | pci_wake_from_d3(pdev, wake); | |
7250 | pci_set_power_state(pdev, PCI_D3hot); | |
7251 | } | |
9d5c8243 AK |
7252 | } |
7253 | ||
fa44f2f1 GR |
7254 | #ifdef CONFIG_PCI_IOV |
7255 | static int igb_sriov_reinit(struct pci_dev *dev) | |
7256 | { | |
7257 | struct net_device *netdev = pci_get_drvdata(dev); | |
7258 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7259 | struct pci_dev *pdev = adapter->pdev; | |
7260 | ||
7261 | rtnl_lock(); | |
7262 | ||
7263 | if (netif_running(netdev)) | |
7264 | igb_close(netdev); | |
7265 | ||
7266 | igb_clear_interrupt_scheme(adapter); | |
7267 | ||
7268 | igb_init_queue_configuration(adapter); | |
7269 | ||
7270 | if (igb_init_interrupt_scheme(adapter, true)) { | |
7271 | dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); | |
7272 | return -ENOMEM; | |
7273 | } | |
7274 | ||
7275 | if (netif_running(netdev)) | |
7276 | igb_open(netdev); | |
7277 | ||
7278 | rtnl_unlock(); | |
7279 | ||
7280 | return 0; | |
7281 | } | |
7282 | ||
7283 | static int igb_pci_disable_sriov(struct pci_dev *dev) | |
7284 | { | |
7285 | int err = igb_disable_sriov(dev); | |
7286 | ||
7287 | if (!err) | |
7288 | err = igb_sriov_reinit(dev); | |
7289 | ||
7290 | return err; | |
7291 | } | |
7292 | ||
7293 | static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) | |
7294 | { | |
7295 | int err = igb_enable_sriov(dev, num_vfs); | |
7296 | ||
7297 | if (err) | |
7298 | goto out; | |
7299 | ||
7300 | err = igb_sriov_reinit(dev); | |
7301 | if (!err) | |
7302 | return num_vfs; | |
7303 | ||
7304 | out: | |
7305 | return err; | |
7306 | } | |
7307 | ||
7308 | #endif | |
7309 | static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) | |
7310 | { | |
7311 | #ifdef CONFIG_PCI_IOV | |
7312 | if (num_vfs == 0) | |
7313 | return igb_pci_disable_sriov(dev); | |
7314 | else | |
7315 | return igb_pci_enable_sriov(dev, num_vfs); | |
7316 | #endif | |
7317 | return 0; | |
7318 | } | |
7319 | ||
9d5c8243 | 7320 | #ifdef CONFIG_NET_POLL_CONTROLLER |
b980ac18 | 7321 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
9d5c8243 AK |
7322 | * without having to re-enable interrupts. It's not called while |
7323 | * the interrupt routine is executing. | |
7324 | */ | |
7325 | static void igb_netpoll(struct net_device *netdev) | |
7326 | { | |
7327 | struct igb_adapter *adapter = netdev_priv(netdev); | |
eebbbdba | 7328 | struct e1000_hw *hw = &adapter->hw; |
0d1ae7f4 | 7329 | struct igb_q_vector *q_vector; |
9d5c8243 | 7330 | int i; |
9d5c8243 | 7331 | |
047e0030 | 7332 | for (i = 0; i < adapter->num_q_vectors; i++) { |
0d1ae7f4 AD |
7333 | q_vector = adapter->q_vector[i]; |
7334 | if (adapter->msix_entries) | |
7335 | wr32(E1000_EIMC, q_vector->eims_value); | |
7336 | else | |
7337 | igb_irq_disable(adapter); | |
047e0030 | 7338 | napi_schedule(&q_vector->napi); |
eebbbdba | 7339 | } |
9d5c8243 AK |
7340 | } |
7341 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
7342 | ||
7343 | /** | |
b980ac18 JK |
7344 | * igb_io_error_detected - called when PCI error is detected |
7345 | * @pdev: Pointer to PCI device | |
7346 | * @state: The current pci connection state | |
9d5c8243 | 7347 | * |
b980ac18 JK |
7348 | * This function is called after a PCI bus error affecting |
7349 | * this device has been detected. | |
7350 | **/ | |
9d5c8243 AK |
7351 | static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, |
7352 | pci_channel_state_t state) | |
7353 | { | |
7354 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7355 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7356 | ||
7357 | netif_device_detach(netdev); | |
7358 | ||
59ed6eec AD |
7359 | if (state == pci_channel_io_perm_failure) |
7360 | return PCI_ERS_RESULT_DISCONNECT; | |
7361 | ||
9d5c8243 AK |
7362 | if (netif_running(netdev)) |
7363 | igb_down(adapter); | |
7364 | pci_disable_device(pdev); | |
7365 | ||
7366 | /* Request a slot slot reset. */ | |
7367 | return PCI_ERS_RESULT_NEED_RESET; | |
7368 | } | |
7369 | ||
7370 | /** | |
b980ac18 JK |
7371 | * igb_io_slot_reset - called after the pci bus has been reset. |
7372 | * @pdev: Pointer to PCI device | |
9d5c8243 | 7373 | * |
b980ac18 JK |
7374 | * Restart the card from scratch, as if from a cold-boot. Implementation |
7375 | * resembles the first-half of the igb_resume routine. | |
7376 | **/ | |
9d5c8243 AK |
7377 | static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) |
7378 | { | |
7379 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7380 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7381 | struct e1000_hw *hw = &adapter->hw; | |
40a914fa | 7382 | pci_ers_result_t result; |
42bfd33a | 7383 | int err; |
9d5c8243 | 7384 | |
aed5dec3 | 7385 | if (pci_enable_device_mem(pdev)) { |
9d5c8243 AK |
7386 | dev_err(&pdev->dev, |
7387 | "Cannot re-enable PCI device after reset.\n"); | |
40a914fa AD |
7388 | result = PCI_ERS_RESULT_DISCONNECT; |
7389 | } else { | |
7390 | pci_set_master(pdev); | |
7391 | pci_restore_state(pdev); | |
b94f2d77 | 7392 | pci_save_state(pdev); |
9d5c8243 | 7393 | |
40a914fa AD |
7394 | pci_enable_wake(pdev, PCI_D3hot, 0); |
7395 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
9d5c8243 | 7396 | |
40a914fa AD |
7397 | igb_reset(adapter); |
7398 | wr32(E1000_WUS, ~0); | |
7399 | result = PCI_ERS_RESULT_RECOVERED; | |
7400 | } | |
9d5c8243 | 7401 | |
ea943d41 JK |
7402 | err = pci_cleanup_aer_uncorrect_error_status(pdev); |
7403 | if (err) { | |
b980ac18 JK |
7404 | dev_err(&pdev->dev, |
7405 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", | |
7406 | err); | |
ea943d41 JK |
7407 | /* non-fatal, continue */ |
7408 | } | |
40a914fa AD |
7409 | |
7410 | return result; | |
9d5c8243 AK |
7411 | } |
7412 | ||
7413 | /** | |
b980ac18 JK |
7414 | * igb_io_resume - called when traffic can start flowing again. |
7415 | * @pdev: Pointer to PCI device | |
9d5c8243 | 7416 | * |
b980ac18 JK |
7417 | * This callback is called when the error recovery driver tells us that |
7418 | * its OK to resume normal operation. Implementation resembles the | |
7419 | * second-half of the igb_resume routine. | |
9d5c8243 AK |
7420 | */ |
7421 | static void igb_io_resume(struct pci_dev *pdev) | |
7422 | { | |
7423 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7424 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7425 | ||
9d5c8243 AK |
7426 | if (netif_running(netdev)) { |
7427 | if (igb_up(adapter)) { | |
7428 | dev_err(&pdev->dev, "igb_up failed after reset\n"); | |
7429 | return; | |
7430 | } | |
7431 | } | |
7432 | ||
7433 | netif_device_attach(netdev); | |
7434 | ||
7435 | /* let the f/w know that the h/w is now under the control of the | |
b980ac18 JK |
7436 | * driver. |
7437 | */ | |
9d5c8243 | 7438 | igb_get_hw_control(adapter); |
9d5c8243 AK |
7439 | } |
7440 | ||
26ad9178 | 7441 | static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, |
b980ac18 | 7442 | u8 qsel) |
26ad9178 AD |
7443 | { |
7444 | u32 rar_low, rar_high; | |
7445 | struct e1000_hw *hw = &adapter->hw; | |
7446 | ||
7447 | /* HW expects these in little endian so we reverse the byte order | |
7448 | * from network order (big endian) to little endian | |
7449 | */ | |
7450 | rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | | |
b980ac18 | 7451 | ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); |
26ad9178 AD |
7452 | rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); |
7453 | ||
7454 | /* Indicate to hardware the Address is Valid. */ | |
7455 | rar_high |= E1000_RAH_AV; | |
7456 | ||
7457 | if (hw->mac.type == e1000_82575) | |
7458 | rar_high |= E1000_RAH_POOL_1 * qsel; | |
7459 | else | |
7460 | rar_high |= E1000_RAH_POOL_1 << qsel; | |
7461 | ||
7462 | wr32(E1000_RAL(index), rar_low); | |
7463 | wrfl(); | |
7464 | wr32(E1000_RAH(index), rar_high); | |
7465 | wrfl(); | |
7466 | } | |
7467 | ||
4ae196df | 7468 | static int igb_set_vf_mac(struct igb_adapter *adapter, |
b980ac18 | 7469 | int vf, unsigned char *mac_addr) |
4ae196df AD |
7470 | { |
7471 | struct e1000_hw *hw = &adapter->hw; | |
ff41f8dc | 7472 | /* VF MAC addresses start at end of receive addresses and moves |
b980ac18 JK |
7473 | * towards the first, as a result a collision should not be possible |
7474 | */ | |
ff41f8dc | 7475 | int rar_entry = hw->mac.rar_entry_count - (vf + 1); |
4ae196df | 7476 | |
37680117 | 7477 | memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); |
4ae196df | 7478 | |
26ad9178 | 7479 | igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); |
4ae196df AD |
7480 | |
7481 | return 0; | |
7482 | } | |
7483 | ||
8151d294 WM |
7484 | static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) |
7485 | { | |
7486 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7487 | if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) | |
7488 | return -EINVAL; | |
7489 | adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; | |
7490 | dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); | |
b980ac18 JK |
7491 | dev_info(&adapter->pdev->dev, |
7492 | "Reload the VF driver to make this change effective."); | |
8151d294 | 7493 | if (test_bit(__IGB_DOWN, &adapter->state)) { |
b980ac18 JK |
7494 | dev_warn(&adapter->pdev->dev, |
7495 | "The VF MAC address has been set, but the PF device is not up.\n"); | |
7496 | dev_warn(&adapter->pdev->dev, | |
7497 | "Bring the PF device up before attempting to use the VF device.\n"); | |
8151d294 WM |
7498 | } |
7499 | return igb_set_vf_mac(adapter, vf, mac); | |
7500 | } | |
7501 | ||
17dc566c LL |
7502 | static int igb_link_mbps(int internal_link_speed) |
7503 | { | |
7504 | switch (internal_link_speed) { | |
7505 | case SPEED_100: | |
7506 | return 100; | |
7507 | case SPEED_1000: | |
7508 | return 1000; | |
7509 | default: | |
7510 | return 0; | |
7511 | } | |
7512 | } | |
7513 | ||
7514 | static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, | |
7515 | int link_speed) | |
7516 | { | |
7517 | int rf_dec, rf_int; | |
7518 | u32 bcnrc_val; | |
7519 | ||
7520 | if (tx_rate != 0) { | |
7521 | /* Calculate the rate factor values to set */ | |
7522 | rf_int = link_speed / tx_rate; | |
7523 | rf_dec = (link_speed - (rf_int * tx_rate)); | |
b980ac18 JK |
7524 | rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / |
7525 | tx_rate; | |
17dc566c LL |
7526 | |
7527 | bcnrc_val = E1000_RTTBCNRC_RS_ENA; | |
b980ac18 JK |
7528 | bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & |
7529 | E1000_RTTBCNRC_RF_INT_MASK); | |
17dc566c LL |
7530 | bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); |
7531 | } else { | |
7532 | bcnrc_val = 0; | |
7533 | } | |
7534 | ||
7535 | wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ | |
b980ac18 | 7536 | /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM |
f00b0da7 LL |
7537 | * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. |
7538 | */ | |
7539 | wr32(E1000_RTTBCNRM, 0x14); | |
17dc566c LL |
7540 | wr32(E1000_RTTBCNRC, bcnrc_val); |
7541 | } | |
7542 | ||
7543 | static void igb_check_vf_rate_limit(struct igb_adapter *adapter) | |
7544 | { | |
7545 | int actual_link_speed, i; | |
7546 | bool reset_rate = false; | |
7547 | ||
7548 | /* VF TX rate limit was not set or not supported */ | |
7549 | if ((adapter->vf_rate_link_speed == 0) || | |
7550 | (adapter->hw.mac.type != e1000_82576)) | |
7551 | return; | |
7552 | ||
7553 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
7554 | if (actual_link_speed != adapter->vf_rate_link_speed) { | |
7555 | reset_rate = true; | |
7556 | adapter->vf_rate_link_speed = 0; | |
7557 | dev_info(&adapter->pdev->dev, | |
b980ac18 | 7558 | "Link speed has been changed. VF Transmit rate is disabled\n"); |
17dc566c LL |
7559 | } |
7560 | ||
7561 | for (i = 0; i < adapter->vfs_allocated_count; i++) { | |
7562 | if (reset_rate) | |
7563 | adapter->vf_data[i].tx_rate = 0; | |
7564 | ||
7565 | igb_set_vf_rate_limit(&adapter->hw, i, | |
b980ac18 JK |
7566 | adapter->vf_data[i].tx_rate, |
7567 | actual_link_speed); | |
17dc566c LL |
7568 | } |
7569 | } | |
7570 | ||
8151d294 WM |
7571 | static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) |
7572 | { | |
17dc566c LL |
7573 | struct igb_adapter *adapter = netdev_priv(netdev); |
7574 | struct e1000_hw *hw = &adapter->hw; | |
7575 | int actual_link_speed; | |
7576 | ||
7577 | if (hw->mac.type != e1000_82576) | |
7578 | return -EOPNOTSUPP; | |
7579 | ||
7580 | actual_link_speed = igb_link_mbps(adapter->link_speed); | |
7581 | if ((vf >= adapter->vfs_allocated_count) || | |
7582 | (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || | |
7583 | (tx_rate < 0) || (tx_rate > actual_link_speed)) | |
7584 | return -EINVAL; | |
7585 | ||
7586 | adapter->vf_rate_link_speed = actual_link_speed; | |
7587 | adapter->vf_data[vf].tx_rate = (u16)tx_rate; | |
7588 | igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); | |
7589 | ||
7590 | return 0; | |
8151d294 WM |
7591 | } |
7592 | ||
70ea4783 LL |
7593 | static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, |
7594 | bool setting) | |
7595 | { | |
7596 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7597 | struct e1000_hw *hw = &adapter->hw; | |
7598 | u32 reg_val, reg_offset; | |
7599 | ||
7600 | if (!adapter->vfs_allocated_count) | |
7601 | return -EOPNOTSUPP; | |
7602 | ||
7603 | if (vf >= adapter->vfs_allocated_count) | |
7604 | return -EINVAL; | |
7605 | ||
7606 | reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; | |
7607 | reg_val = rd32(reg_offset); | |
7608 | if (setting) | |
7609 | reg_val |= ((1 << vf) | | |
7610 | (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); | |
7611 | else | |
7612 | reg_val &= ~((1 << vf) | | |
7613 | (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); | |
7614 | wr32(reg_offset, reg_val); | |
7615 | ||
7616 | adapter->vf_data[vf].spoofchk_enabled = setting; | |
7617 | return E1000_SUCCESS; | |
7618 | } | |
7619 | ||
8151d294 WM |
7620 | static int igb_ndo_get_vf_config(struct net_device *netdev, |
7621 | int vf, struct ifla_vf_info *ivi) | |
7622 | { | |
7623 | struct igb_adapter *adapter = netdev_priv(netdev); | |
7624 | if (vf >= adapter->vfs_allocated_count) | |
7625 | return -EINVAL; | |
7626 | ivi->vf = vf; | |
7627 | memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); | |
17dc566c | 7628 | ivi->tx_rate = adapter->vf_data[vf].tx_rate; |
8151d294 WM |
7629 | ivi->vlan = adapter->vf_data[vf].pf_vlan; |
7630 | ivi->qos = adapter->vf_data[vf].pf_qos; | |
70ea4783 | 7631 | ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; |
8151d294 WM |
7632 | return 0; |
7633 | } | |
7634 | ||
4ae196df AD |
7635 | static void igb_vmm_control(struct igb_adapter *adapter) |
7636 | { | |
7637 | struct e1000_hw *hw = &adapter->hw; | |
10d8e907 | 7638 | u32 reg; |
4ae196df | 7639 | |
52a1dd4d AD |
7640 | switch (hw->mac.type) { |
7641 | case e1000_82575: | |
f96a8a0b CW |
7642 | case e1000_i210: |
7643 | case e1000_i211: | |
ceb5f13b | 7644 | case e1000_i354: |
52a1dd4d AD |
7645 | default: |
7646 | /* replication is not supported for 82575 */ | |
4ae196df | 7647 | return; |
52a1dd4d AD |
7648 | case e1000_82576: |
7649 | /* notify HW that the MAC is adding vlan tags */ | |
7650 | reg = rd32(E1000_DTXCTL); | |
7651 | reg |= E1000_DTXCTL_VLAN_ADDED; | |
7652 | wr32(E1000_DTXCTL, reg); | |
7653 | case e1000_82580: | |
7654 | /* enable replication vlan tag stripping */ | |
7655 | reg = rd32(E1000_RPLOLR); | |
7656 | reg |= E1000_RPLOLR_STRVLAN; | |
7657 | wr32(E1000_RPLOLR, reg); | |
d2ba2ed8 AD |
7658 | case e1000_i350: |
7659 | /* none of the above registers are supported by i350 */ | |
52a1dd4d AD |
7660 | break; |
7661 | } | |
10d8e907 | 7662 | |
d4960307 AD |
7663 | if (adapter->vfs_allocated_count) { |
7664 | igb_vmdq_set_loopback_pf(hw, true); | |
7665 | igb_vmdq_set_replication_pf(hw, true); | |
13800469 | 7666 | igb_vmdq_set_anti_spoofing_pf(hw, true, |
b980ac18 | 7667 | adapter->vfs_allocated_count); |
d4960307 AD |
7668 | } else { |
7669 | igb_vmdq_set_loopback_pf(hw, false); | |
7670 | igb_vmdq_set_replication_pf(hw, false); | |
7671 | } | |
4ae196df AD |
7672 | } |
7673 | ||
b6e0c419 CW |
7674 | static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) |
7675 | { | |
7676 | struct e1000_hw *hw = &adapter->hw; | |
7677 | u32 dmac_thr; | |
7678 | u16 hwm; | |
7679 | ||
7680 | if (hw->mac.type > e1000_82580) { | |
7681 | if (adapter->flags & IGB_FLAG_DMAC) { | |
7682 | u32 reg; | |
7683 | ||
7684 | /* force threshold to 0. */ | |
7685 | wr32(E1000_DMCTXTH, 0); | |
7686 | ||
b980ac18 | 7687 | /* DMA Coalescing high water mark needs to be greater |
e8c626e9 MV |
7688 | * than the Rx threshold. Set hwm to PBA - max frame |
7689 | * size in 16B units, capping it at PBA - 6KB. | |
b6e0c419 | 7690 | */ |
e8c626e9 MV |
7691 | hwm = 64 * pba - adapter->max_frame_size / 16; |
7692 | if (hwm < 64 * (pba - 6)) | |
7693 | hwm = 64 * (pba - 6); | |
7694 | reg = rd32(E1000_FCRTC); | |
7695 | reg &= ~E1000_FCRTC_RTH_COAL_MASK; | |
7696 | reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) | |
7697 | & E1000_FCRTC_RTH_COAL_MASK); | |
7698 | wr32(E1000_FCRTC, reg); | |
7699 | ||
b980ac18 | 7700 | /* Set the DMA Coalescing Rx threshold to PBA - 2 * max |
e8c626e9 MV |
7701 | * frame size, capping it at PBA - 10KB. |
7702 | */ | |
7703 | dmac_thr = pba - adapter->max_frame_size / 512; | |
7704 | if (dmac_thr < pba - 10) | |
7705 | dmac_thr = pba - 10; | |
b6e0c419 CW |
7706 | reg = rd32(E1000_DMACR); |
7707 | reg &= ~E1000_DMACR_DMACTHR_MASK; | |
b6e0c419 CW |
7708 | reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) |
7709 | & E1000_DMACR_DMACTHR_MASK); | |
7710 | ||
7711 | /* transition to L0x or L1 if available..*/ | |
7712 | reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); | |
7713 | ||
7714 | /* watchdog timer= +-1000 usec in 32usec intervals */ | |
7715 | reg |= (1000 >> 5); | |
0c02dd98 MV |
7716 | |
7717 | /* Disable BMC-to-OS Watchdog Enable */ | |
ceb5f13b CW |
7718 | if (hw->mac.type != e1000_i354) |
7719 | reg &= ~E1000_DMACR_DC_BMC2OSW_EN; | |
7720 | ||
b6e0c419 CW |
7721 | wr32(E1000_DMACR, reg); |
7722 | ||
b980ac18 | 7723 | /* no lower threshold to disable |
b6e0c419 CW |
7724 | * coalescing(smart fifb)-UTRESH=0 |
7725 | */ | |
7726 | wr32(E1000_DMCRTRH, 0); | |
b6e0c419 CW |
7727 | |
7728 | reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); | |
7729 | ||
7730 | wr32(E1000_DMCTLX, reg); | |
7731 | ||
b980ac18 | 7732 | /* free space in tx packet buffer to wake from |
b6e0c419 CW |
7733 | * DMA coal |
7734 | */ | |
7735 | wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - | |
7736 | (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); | |
7737 | ||
b980ac18 | 7738 | /* make low power state decision controlled |
b6e0c419 CW |
7739 | * by DMA coal |
7740 | */ | |
7741 | reg = rd32(E1000_PCIEMISC); | |
7742 | reg &= ~E1000_PCIEMISC_LX_DECISION; | |
7743 | wr32(E1000_PCIEMISC, reg); | |
7744 | } /* endif adapter->dmac is not disabled */ | |
7745 | } else if (hw->mac.type == e1000_82580) { | |
7746 | u32 reg = rd32(E1000_PCIEMISC); | |
7747 | wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); | |
7748 | wr32(E1000_DMACR, 0); | |
7749 | } | |
7750 | } | |
7751 | ||
b980ac18 JK |
7752 | /** |
7753 | * igb_read_i2c_byte - Reads 8 bit word over I2C | |
441fc6fd CW |
7754 | * @hw: pointer to hardware structure |
7755 | * @byte_offset: byte offset to read | |
7756 | * @dev_addr: device address | |
7757 | * @data: value read | |
7758 | * | |
7759 | * Performs byte read operation over I2C interface at | |
7760 | * a specified device address. | |
b980ac18 | 7761 | **/ |
441fc6fd | 7762 | s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, |
b980ac18 | 7763 | u8 dev_addr, u8 *data) |
441fc6fd CW |
7764 | { |
7765 | struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); | |
603e86fa | 7766 | struct i2c_client *this_client = adapter->i2c_client; |
441fc6fd CW |
7767 | s32 status; |
7768 | u16 swfw_mask = 0; | |
7769 | ||
7770 | if (!this_client) | |
7771 | return E1000_ERR_I2C; | |
7772 | ||
7773 | swfw_mask = E1000_SWFW_PHY0_SM; | |
7774 | ||
7775 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) | |
7776 | != E1000_SUCCESS) | |
7777 | return E1000_ERR_SWFW_SYNC; | |
7778 | ||
7779 | status = i2c_smbus_read_byte_data(this_client, byte_offset); | |
7780 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | |
7781 | ||
7782 | if (status < 0) | |
7783 | return E1000_ERR_I2C; | |
7784 | else { | |
7785 | *data = status; | |
7786 | return E1000_SUCCESS; | |
7787 | } | |
7788 | } | |
7789 | ||
b980ac18 JK |
7790 | /** |
7791 | * igb_write_i2c_byte - Writes 8 bit word over I2C | |
441fc6fd CW |
7792 | * @hw: pointer to hardware structure |
7793 | * @byte_offset: byte offset to write | |
7794 | * @dev_addr: device address | |
7795 | * @data: value to write | |
7796 | * | |
7797 | * Performs byte write operation over I2C interface at | |
7798 | * a specified device address. | |
b980ac18 | 7799 | **/ |
441fc6fd | 7800 | s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, |
b980ac18 | 7801 | u8 dev_addr, u8 data) |
441fc6fd CW |
7802 | { |
7803 | struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); | |
603e86fa | 7804 | struct i2c_client *this_client = adapter->i2c_client; |
441fc6fd CW |
7805 | s32 status; |
7806 | u16 swfw_mask = E1000_SWFW_PHY0_SM; | |
7807 | ||
7808 | if (!this_client) | |
7809 | return E1000_ERR_I2C; | |
7810 | ||
7811 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) | |
7812 | return E1000_ERR_SWFW_SYNC; | |
7813 | status = i2c_smbus_write_byte_data(this_client, byte_offset, data); | |
7814 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); | |
7815 | ||
7816 | if (status) | |
7817 | return E1000_ERR_I2C; | |
7818 | else | |
7819 | return E1000_SUCCESS; | |
7820 | ||
7821 | } | |
9d5c8243 | 7822 | /* igb_main.c */ |