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igb: rename igb define to be more generic
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
6fb46902
TF		 60#define MIN 3
61#define BUILD 0
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
bf456abb 143static void igb_set_uta(struct igb_adapter *adapter, bool set);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
32b3e08f 154static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 184#endif
9d5c8243 185
9d5c8243 186#ifdef CONFIG_PM
d9dd966d 187#ifdef CONFIG_PM_SLEEP
749ab2cd 188static int igb_suspend(struct device *);
d9dd966d 189#endif
749ab2cd 190static int igb_resume(struct device *);
749ab2cd
YZ		 191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
52285b76 949 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 950
047e0030 951 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 952 igb_msix_other, 0, netdev->name, adapter);
047e0030 953 if (err)
52285b76 954 goto err_out;
047e0030
AD		 955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
52285b76
SA		 959 vector++;
960
7b06a690 961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 962
0ba82994 963 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
047e0030 967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
047e0030 970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 971 q_vector->rx.ring->queue_index);
9d5c8243 972 else
047e0030
AD		 973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
9d5c8243 975 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
9d5c8243 978 if (err)
52285b76 979 goto err_free;
9d5c8243
AK		 980 }
981
9d5c8243
AK		 982 igb_configure_msix(adapter);
983 return 0;
52285b76
SA		 984
985err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994err_out:
9d5c8243
AK		 995 return err;
996}
997
5536d210 998/**
b980ac18
JK		 999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
5536d210 1002 *
02ef6e1d 1003 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
02ef6e1d
CW		 1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
17a402a0
CW		 1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
cb06d102
CP		 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
5536d210
AD		 1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
2439fc4d 1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1041
5536d210
AD		 1042 netif_napi_del(&q_vector->napi);
1043
02ef6e1d
CW		 1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
cd14ef54 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1051 pci_disable_msix(adapter->pdev);
cd14ef54 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1053 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1057}
1058
047e0030 1059/**
b980ac18
JK		 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
047e0030 1062 *
b980ac18
JK		 1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
047e0030
AD		 1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
5536d210
AD		 1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
047e0030 1073 adapter->num_q_vectors = 0;
5536d210 1074
02ef6e1d
CW		 1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
5536d210 1077 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1078 }
047e0030
AD		 1079}
1080
1081/**
b980ac18
JK		 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
047e0030 1084 *
b980ac18
JK		 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
047e0030
AD		 1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
047e0030
AD		 1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
9d5c8243
AK		 1093
1094/**
b980ac18
JK		 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
9d5c8243 1098 *
b980ac18
JK		 1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
9d5c8243 1101 **/
53c7d064 1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1103{
1104 int err;
1105 int numvecs, i;
1106
53c7d064
SA		 1107 if (!msix)
1108 goto msi_only;
cd14ef54 1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1110
83b7180d 1111 /* Number of supported queues. */
a99955fc 1112 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1117
b980ac18 1118 /* start with one vector for every Rx queue */
047e0030
AD		 1119 numvecs = adapter->num_rx_queues;
1120
b980ac18 1121 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
047e0030
AD		 1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
9d5c8243
AK		 1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
479d02df
AG		 1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
0c2cc02e 1138 return;
9d5c8243
AK		 1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
b709323d 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1156 wrfl();
2a3abf6d
AD		 1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
4fc82adf 1161 adapter->vfs_allocated_count = 0;
a99955fc 1162 adapter->rss_queues = 1;
4fc82adf 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1164 adapter->num_rx_queues = 1;
661086df 1165 adapter->num_tx_queues = 1;
047e0030 1166 adapter->num_q_vectors = 1;
9d5c8243 1167 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1168 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1169}
1170
5536d210
AD		 1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
047e0030 1178/**
b980ac18
JK		 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
047e0030 1187 *
b980ac18 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1189 **/
5536d210
AD		 1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
047e0030
AD		 1194{
1195 struct igb_q_vector *q_vector;
5536d210
AD		 1196 struct igb_ring *ring;
1197 int ring_count, size;
047e0030 1198
5536d210
AD		 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
02ef6e1d 1208 q_vector = adapter->q_vector[v_idx];
72ddef05 1209 if (!q_vector) {
02ef6e1d 1210 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
c0a06ee1 1215 memset(q_vector, 0, size);
72ddef05 1216 }
5536d210
AD		 1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
7b06a690 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
4e227667
AD		 1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
5536d210
AD		 1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
827da44c
JS		 1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
5536d210
AD		 1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
047e0030 1276 }
81c2fc22 1277
5536d210
AD		 1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
047e0030 1282
5536d210
AD		 1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
047e0030 1285
5536d210
AD		 1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
047e0030 1288
5536d210
AD		 1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1292
e52c0f96 1293 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1294 * have the tag byte-swapped.
b980ac18 1295 */
5536d210
AD		 1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1298
5536d210
AD		 1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
827da44c
JS		 1303 u64_stats_init(&ring->rx_syncp);
1304
5536d210
AD		 1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
047e0030
AD		 1310}
1311
5536d210 1312
047e0030 1313/**
b980ac18
JK		 1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
047e0030 1316 *
b980ac18
JK		 1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
047e0030 1319 **/
5536d210 1320static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1321{
5536d210
AD		 1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
047e0030 1327
5536d210
AD		 1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
047e0030 1332
5536d210
AD		 1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
047e0030 1339 }
047e0030 1340 }
5536d210
AD		 1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1345
5536d210
AD		 1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
047e0030 1359 return 0;
5536d210
AD		 1360
1361err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
047e0030
AD		 1370}
1371
1372/**
b980ac18
JK		 1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
047e0030 1376 *
b980ac18 1377 * This function initializes the interrupts and allocates all of the queues.
047e0030 1378 **/
53c7d064 1379static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1380{
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
53c7d064 1384 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
5536d210 1392 igb_cache_ring_register(adapter);
047e0030
AD		 1393
1394 return 0;
5536d210 1395
047e0030
AD		 1396err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399}
1400
9d5c8243 1401/**
b980ac18
JK		 1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
9d5c8243 1404 *
b980ac18
JK		 1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
9d5c8243
AK		 1407 **/
1408static int igb_request_irq(struct igb_adapter *adapter)
1409{
1410 struct net_device *netdev = adapter->netdev;
047e0030 1411 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1412 int err = 0;
1413
cd14ef54 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1415 err = igb_request_msix(adapter);
844290e5 1416 if (!err)
9d5c8243 1417 goto request_done;
9d5c8243 1418 /* fall back to MSI */
5536d210
AD		 1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
53c7d064 1421
047e0030 1422 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
047e0030 1425 goto request_done;
53c7d064 1426
047e0030
AD		 1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
53c7d064 1429 igb_configure(adapter);
9d5c8243 1430 }
844290e5 1431
c74d588e
AD		 1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
7dfc16fa 1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1436 netdev->name, adapter);
9d5c8243
AK		 1437 if (!err)
1438 goto request_done;
047e0030 1439
9d5c8243
AK		 1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
7dfc16fa 1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1443 }
1444
c74d588e 1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1446 netdev->name, adapter);
9d5c8243 1447
6cb5e577 1448 if (err)
c74d588e 1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1450 err);
9d5c8243
AK		 1451
1452request_done:
1453 return err;
1454}
1455
1456static void igb_free_irq(struct igb_adapter *adapter)
1457{
cd14ef54 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1459 int vector = 0, i;
1460
047e0030 1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1462
0d1ae7f4 1463 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1464 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1465 adapter->q_vector[i]);
047e0030
AD		 1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1468 }
9d5c8243
AK		 1469}
1470
1471/**
b980ac18
JK		 1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
9d5c8243
AK		 1474 **/
1475static void igb_irq_disable(struct igb_adapter *adapter)
1476{
1477 struct e1000_hw *hw = &adapter->hw;
1478
b980ac18 1479 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
cd14ef54 1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1484 u32 regval = rd32(E1000_EIAM);
9005df38 1485
2dfd1212
AD		 1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1490 }
844290e5
PW		 1491
1492 wr32(E1000_IAM, 0);
9d5c8243
AK		 1493 wr32(E1000_IMC, ~0);
1494 wrfl();
cd14ef54 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1496 int i;
9005df38 1497
81a61859
ET		 1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
9d5c8243
AK		 1503}
1504
1505/**
b980ac18
JK		 1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
9d5c8243
AK		 1508 **/
1509static void igb_irq_enable(struct igb_adapter *adapter)
1510{
1511 struct e1000_hw *hw = &adapter->hw;
1512
cd14ef54 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1515 u32 regval = rd32(E1000_EIAC);
9005df38 1516
2dfd1212
AD		 1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1521 if (adapter->vfs_allocated_count) {
4ae196df 1522 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
844290e5 1526 } else {
55cac248
AD		 1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
844290e5 1531 }
9d5c8243
AK		 1532}
1533
1534static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535{
51466239 1536 struct e1000_hw *hw = &adapter->hw;
8b77c6b2 1537 u16 pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
8b77c6b2 1543 igb_vfta_set(hw, vid, pf_id, true, true);
51466239
AD		 1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
b2cb09b1 1551 !test_bit(old_vid, adapter->active_vlans)) {
51466239 1552 /* remove VID from filter table */
8b77c6b2 1553 igb_vfta_set(hw, vid, pf_id, false, true);
9d5c8243
AK		 1554 }
1555}
1556
1557/**
b980ac18
JK		 1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
9d5c8243 1560 *
b980ac18
JK		 1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
9d5c8243
AK		 1564 **/
1565static void igb_release_hw_control(struct igb_adapter *adapter)
1566{
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574}
1575
9d5c8243 1576/**
b980ac18
JK		 1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
9d5c8243 1579 *
b980ac18
JK		 1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
9d5c8243
AK		 1583 **/
1584static void igb_get_hw_control(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593}
1594
9d5c8243 1595/**
b980ac18
JK		 1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
9d5c8243
AK		 1598 **/
1599static void igb_configure(struct igb_adapter *adapter)
1600{
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
ff41f8dc 1605 igb_set_rx_mode(netdev);
9d5c8243
AK		 1606
1607 igb_restore_vlan(adapter);
9d5c8243 1608
85b430b4 1609 igb_setup_tctl(adapter);
06cf2666 1610 igb_setup_mrqc(adapter);
9d5c8243 1611 igb_setup_rctl(adapter);
85b430b4
AD		 1612
1613 igb_configure_tx(adapter);
9d5c8243 1614 igb_configure_rx(adapter);
662d7205
AD		 1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
c493ea45 1618 /* call igb_desc_unused which always leaves
9d5c8243 1619 * at least 1 descriptor unused to make sure
b980ac18
JK		 1620 * next_to_use != next_to_clean
1621 */
9d5c8243 1622 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1623 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1625 }
9d5c8243
AK		 1626}
1627
88a268c1 1628/**
b980ac18
JK		 1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
88a268c1
NN		 1631 **/
1632void igb_power_up_link(struct igb_adapter *adapter)
1633{
76886596
AA		 1634 igb_reset_phy(&adapter->hw);
1635
88a268c1
NN		 1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1640
1641 igb_setup_link(&adapter->hw);
88a268c1
NN		 1642}
1643
1644/**
b980ac18
JK		 1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
88a268c1
NN		 1647 */
1648static void igb_power_down_link(struct igb_adapter *adapter)
1649{
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654}
9d5c8243 1655
56cec249
CW		 1656/**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660static void igb_check_swap_media(struct igb_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721}
1722
9d5c8243 1723/**
b980ac18
JK		 1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
9d5c8243 1726 **/
9d5c8243
AK		 1727int igb_up(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
0d1ae7f4
AD		 1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
cd14ef54 1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1741 igb_configure_msix(adapter);
feeb2721
AD		 1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
d4960307
AD		 1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1752
d4960307
AD		 1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
4cb9be7a
JB		 1757 netif_tx_start_all_queues(adapter->netdev);
1758
25568a53
AD		 1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
f4c01e96
CW		 1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
9d5c8243
AK		 1767 return 0;
1768}
1769
1770void igb_down(struct igb_adapter *adapter)
1771{
9d5c8243 1772 struct net_device *netdev = adapter->netdev;
330a6d6a 1773 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1778 * reschedule our watchdog timer
1779 */
9d5c8243
AK		 1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
f28ea083 1787 netif_carrier_off(netdev);
fd2ea0a7 1788 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
0d451e79 1796 usleep_range(10000, 11000);
9d5c8243 1797
41f149a2
CW		 1798 igb_irq_disable(adapter);
1799
aa9b8cc4
AA		 1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
41f149a2 1802 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
41f149a2 1807 }
9d5c8243 1808
9d5c8243
AK		 1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
04fe6358 1812 /* record the stats before reset*/
12dcd86b
ED		 1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
04fe6358 1816
9d5c8243
AK		 1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
3023682e
JK		 1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
16903caa
AD		 1822
1823 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1824 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1825
9d5c8243
AK		 1826 igb_clean_all_tx_rings(adapter);
1827 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1828#ifdef CONFIG_IGB_DCA
1829
1830 /* since we reset the hardware DCA settings were cleared */
1831 igb_setup_dca(adapter);
1832#endif
9d5c8243
AK		 1833}
1834
1835void igb_reinit_locked(struct igb_adapter *adapter)
1836{
1837 WARN_ON(in_interrupt());
1838 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1839 usleep_range(1000, 2000);
9d5c8243
AK		 1840 igb_down(adapter);
1841 igb_up(adapter);
1842 clear_bit(__IGB_RESETTING, &adapter->state);
1843}
1844
56cec249
CW		 1845/** igb_enable_mas - Media Autosense re-enable after swap
1846 *
1847 * @adapter: adapter struct
1848 **/
8cfb879d 1849static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1850{
1851 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1852 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1853
1854 /* configure for SerDes media detect */
8cfb879d
TF		 1855 if ((hw->phy.media_type == e1000_media_type_copper) &&
1856 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1857 connsw |= E1000_CONNSW_ENRGSRC;
1858 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1859 wr32(E1000_CONNSW, connsw);
1860 wrfl();
56cec249 1861 }
56cec249
CW		 1862}
1863
9d5c8243
AK		 1864void igb_reset(struct igb_adapter *adapter)
1865{
090b1795 1866 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1867 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1868 struct e1000_mac_info *mac = &hw->mac;
1869 struct e1000_fc_info *fc = &hw->fc;
45693bcb 1870 u32 pba, hwm;
9d5c8243
AK		 1871
1872 /* Repartition Pba for greater than 9k mtu
1873 * To take effect CTRL.RST is required.
1874 */
fa4dfae0 1875 switch (mac->type) {
d2ba2ed8 1876 case e1000_i350:
ceb5f13b 1877 case e1000_i354:
55cac248
AD		 1878 case e1000_82580:
1879 pba = rd32(E1000_RXPBS);
1880 pba = igb_rxpbs_adjust_82580(pba);
1881 break;
fa4dfae0 1882 case e1000_82576:
d249be54
AD		 1883 pba = rd32(E1000_RXPBS);
1884 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1885 break;
1886 case e1000_82575:
f96a8a0b
CW		 1887 case e1000_i210:
1888 case e1000_i211:
fa4dfae0
AD		 1889 default:
1890 pba = E1000_PBA_34K;
1891 break;
2d064c06 1892 }
9d5c8243 1893
45693bcb
AD		 1894 if (mac->type == e1000_82575) {
1895 u32 min_rx_space, min_tx_space, needed_tx_space;
1896
1897 /* write Rx PBA so that hardware can report correct Tx PBA */
9d5c8243
AK		 1898 wr32(E1000_PBA, pba);
1899
1900 /* To maintain wire speed transmits, the Tx FIFO should be
1901 * large enough to accommodate two full transmit packets,
1902 * rounded up to the next 1KB and expressed in KB. Likewise,
1903 * the Rx FIFO should be large enough to accommodate at least
1904 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1905 * expressed in KB.
1906 */
45693bcb
AD		 1907 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1908
1909 /* The Tx FIFO also stores 16 bytes of information about the Tx
1910 * but don't include Ethernet FCS because hardware appends it.
1911 * We only need to round down to the nearest 512 byte block
1912 * count since the value we care about is 2 frames, not 1.
b980ac18 1913 */
45693bcb
AD		 1914 min_tx_space = adapter->max_frame_size;
1915 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1916 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1917
1918 /* upper 16 bits has Tx packet buffer allocation size in KB */
1919 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
9d5c8243
AK		 1920
1921 /* If current Tx allocation is less than the min Tx FIFO size,
1922 * and the min Tx FIFO size is less than the current Rx FIFO
45693bcb 1923 * allocation, take space away from current Rx allocation.
b980ac18 1924 */
45693bcb
AD		 1925 if (needed_tx_space < pba) {
1926 pba -= needed_tx_space;
9d5c8243 1927
b980ac18
JK		 1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
9d5c8243
AK		 1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
45693bcb
AD		 1934
1935 /* adjust PBA for jumbo frames */
2d064c06 1936 wr32(E1000_PBA, pba);
9d5c8243 1937 }
9d5c8243 1938
45693bcb
AD		 1939 /* flow control settings
1940 * The high water mark must be low enough to fit one full frame
1941 * after transmitting the pause frame. As such we must have enough
1942 * space to allow for us to complete our current transmit and then
1943 * receive the frame that is in progress from the link partner.
1944 * Set it to:
1945 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
b980ac18 1946 */
45693bcb 1947 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
9d5c8243 1948
d48507fe 1949 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1950 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1951 fc->pause_time = 0xFFFF;
1952 fc->send_xon = 1;
0cce119a 1953 fc->current_mode = fc->requested_mode;
9d5c8243 1954
4ae196df
AD		 1955 /* disable receive for all VFs and wait one second */
1956 if (adapter->vfs_allocated_count) {
1957 int i;
9005df38 1958
4ae196df 1959 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1960 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1961
1962 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1963 igb_ping_all_vfs(adapter);
4ae196df
AD		 1964
1965 /* disable transmits and receives */
1966 wr32(E1000_VFRE, 0);
1967 wr32(E1000_VFTE, 0);
1968 }
1969
9d5c8243 1970 /* Allow time for pending master requests to run */
330a6d6a 1971 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1972 wr32(E1000_WUC, 0);
1973
56cec249
CW		 1974 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1975 /* need to resetup here after media swap */
1976 adapter->ei.get_invariants(hw);
1977 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1978 }
8cfb879d
TF		 1979 if ((mac->type == e1000_82575) &&
1980 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1981 igb_enable_mas(adapter);
56cec249 1982 }
330a6d6a 1983 if (hw->mac.ops.init_hw(hw))
090b1795 1984 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1985
b980ac18 1986 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1987 * control is off when forcing speed.
1988 */
1989 if (!hw->mac.autoneg)
1990 igb_force_mac_fc(hw);
1991
b6e0c419 1992 igb_init_dmac(adapter, pba);
e428893b
CW		 1993#ifdef CONFIG_IGB_HWMON
1994 /* Re-initialize the thermal sensor on i350 devices. */
1995 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1996 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1997 /* If present, re-initialize the external thermal sensor
1998 * interface.
1999 */
2000 if (adapter->ets)
2001 mac->ops.init_thermal_sensor_thresh(hw);
2002 }
2003 }
2004#endif
b936136d 2005 /* Re-establish EEE setting */
f4c01e96
CW		 2006 if (hw->phy.media_type == e1000_media_type_copper) {
2007 switch (mac->type) {
2008 case e1000_i350:
2009 case e1000_i210:
2010 case e1000_i211:
c4c112f1 2011 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2012 break;
2013 case e1000_i354:
c4c112f1 2014 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2015 break;
2016 default:
2017 break;
2018 }
2019 }
88a268c1
NN		 2020 if (!netif_running(adapter->netdev))
2021 igb_power_down_link(adapter);
2022
9d5c8243
AK		 2023 igb_update_mng_vlan(adapter);
2024
2025 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2026 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2027
1f6e8178
MV		 2028 /* Re-enable PTP, where applicable. */
2029 igb_ptp_reset(adapter);
1f6e8178 2030
330a6d6a 2031 igb_get_phy_info(hw);
9d5c8243
AK		 2032}
2033
c8f44aff
MM		 2034static netdev_features_t igb_fix_features(struct net_device *netdev,
2035 netdev_features_t features)
b2cb09b1 2036{
b980ac18
JK		 2037 /* Since there is no support for separate Rx/Tx vlan accel
2038 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2039 */
f646968f
PM		 2040 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2041 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2042 else
f646968f 2043 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2044
2045 return features;
2046}
2047
c8f44aff
MM		 2048static int igb_set_features(struct net_device *netdev,
2049 netdev_features_t features)
ac52caa3 2050{
c8f44aff 2051 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2052 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2053
f646968f 2054 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2055 igb_vlan_mode(netdev, features);
2056
16903caa 2057 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
89eaefb6
BG		 2058 return 0;
2059
2060 netdev->features = features;
2061
2062 if (netif_running(netdev))
2063 igb_reinit_locked(adapter);
2064 else
2065 igb_reset(adapter);
2066
ac52caa3
MM		 2067 return 0;
2068}
2069
268f9d33
AD		 2070static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2071 struct net_device *dev,
2072 const unsigned char *addr, u16 vid,
2073 u16 flags)
2074{
2075 /* guarantee we can provide a unique filter for the unicast address */
2076 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2077 struct igb_adapter *adapter = netdev_priv(dev);
2078 struct e1000_hw *hw = &adapter->hw;
2079 int vfn = adapter->vfs_allocated_count;
2080 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2081
2082 if (netdev_uc_count(dev) >= rar_entries)
2083 return -ENOMEM;
2084 }
2085
2086 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2087}
2088
2e5c6922 2089static const struct net_device_ops igb_netdev_ops = {
559e9c49 2090 .ndo_open = igb_open,
2e5c6922 2091 .ndo_stop = igb_close,
cd392f5c 2092 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2093 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2094 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2095 .ndo_set_mac_address = igb_set_mac,
2096 .ndo_change_mtu = igb_change_mtu,
2097 .ndo_do_ioctl = igb_ioctl,
2098 .ndo_tx_timeout = igb_tx_timeout,
2099 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2100 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2101 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2102 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2103 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2104 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2105 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2106 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2107#ifdef CONFIG_NET_POLL_CONTROLLER
2108 .ndo_poll_controller = igb_netpoll,
2109#endif
b2cb09b1
JP		 2110 .ndo_fix_features = igb_fix_features,
2111 .ndo_set_features = igb_set_features,
268f9d33 2112 .ndo_fdb_add = igb_ndo_fdb_add,
1abbc98a 2113 .ndo_features_check = passthru_features_check,
2e5c6922
SH		 2114};
2115
d67974f0
CW		 2116/**
2117 * igb_set_fw_version - Configure version string for ethtool
2118 * @adapter: adapter struct
d67974f0
CW		 2119 **/
2120void igb_set_fw_version(struct igb_adapter *adapter)
2121{
2122 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2123 struct e1000_fw_version fw;
2124
2125 igb_get_fw_version(hw, &fw);
2126
2127 switch (hw->mac.type) {
7dc98a62 2128 case e1000_i210:
0b1a6f2e 2129 case e1000_i211:
7dc98a62
CW		 2130 if (!(igb_get_flash_presence_i210(hw))) {
2131 snprintf(adapter->fw_version,
2132 sizeof(adapter->fw_version),
2133 "%2d.%2d-%d",
2134 fw.invm_major, fw.invm_minor,
2135 fw.invm_img_type);
2136 break;
2137 }
2138 /* fall through */
0b1a6f2e
CW		 2139 default:
2140 /* if option is rom valid, display its version too */
2141 if (fw.or_valid) {
2142 snprintf(adapter->fw_version,
2143 sizeof(adapter->fw_version),
2144 "%d.%d, 0x%08x, %d.%d.%d",
2145 fw.eep_major, fw.eep_minor, fw.etrack_id,
2146 fw.or_major, fw.or_build, fw.or_patch);
2147 /* no option rom */
7dc98a62 2148 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2149 snprintf(adapter->fw_version,
7dc98a62
CW		 2150 sizeof(adapter->fw_version),
2151 "%d.%d, 0x%08x",
2152 fw.eep_major, fw.eep_minor, fw.etrack_id);
2153 } else {
2154 snprintf(adapter->fw_version,
2155 sizeof(adapter->fw_version),
2156 "%d.%d.%d",
2157 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2158 }
2159 break;
d67974f0 2160 }
d67974f0
CW		 2161}
2162
56cec249
CW		 2163/**
2164 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2165 *
2166 * @adapter: adapter struct
2167 **/
2168static void igb_init_mas(struct igb_adapter *adapter)
2169{
2170 struct e1000_hw *hw = &adapter->hw;
2171 u16 eeprom_data;
2172
2173 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2174 switch (hw->bus.func) {
2175 case E1000_FUNC_0:
2176 if (eeprom_data & IGB_MAS_ENABLE_0) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 case E1000_FUNC_1:
2184 if (eeprom_data & IGB_MAS_ENABLE_1) {
2185 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2186 netdev_info(adapter->netdev,
2187 "MAS: Enabling Media Autosense for port %d\n",
2188 hw->bus.func);
2189 }
2190 break;
2191 case E1000_FUNC_2:
2192 if (eeprom_data & IGB_MAS_ENABLE_2) {
2193 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2194 netdev_info(adapter->netdev,
2195 "MAS: Enabling Media Autosense for port %d\n",
2196 hw->bus.func);
2197 }
2198 break;
2199 case E1000_FUNC_3:
2200 if (eeprom_data & IGB_MAS_ENABLE_3) {
2201 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2202 netdev_info(adapter->netdev,
2203 "MAS: Enabling Media Autosense for port %d\n",
2204 hw->bus.func);
2205 }
2206 break;
2207 default:
2208 /* Shouldn't get here */
2209 netdev_err(adapter->netdev,
2210 "MAS: Invalid port configuration, returning\n");
2211 break;
2212 }
2213}
2214
b980ac18
JK		 2215/**
2216 * igb_init_i2c - Init I2C interface
441fc6fd 2217 * @adapter: pointer to adapter structure
b980ac18 2218 **/
441fc6fd
CW		 2219static s32 igb_init_i2c(struct igb_adapter *adapter)
2220{
23d87824 2221 s32 status = 0;
441fc6fd
CW		 2222
2223 /* I2C interface supported on i350 devices */
2224 if (adapter->hw.mac.type != e1000_i350)
23d87824 2225 return 0;
441fc6fd
CW		 2226
2227 /* Initialize the i2c bus which is controlled by the registers.
2228 * This bus will use the i2c_algo_bit structue that implements
2229 * the protocol through toggling of the 4 bits in the register.
2230 */
2231 adapter->i2c_adap.owner = THIS_MODULE;
2232 adapter->i2c_algo = igb_i2c_algo;
2233 adapter->i2c_algo.data = adapter;
2234 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2235 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2236 strlcpy(adapter->i2c_adap.name, "igb BB",
2237 sizeof(adapter->i2c_adap.name));
2238 status = i2c_bit_add_bus(&adapter->i2c_adap);
2239 return status;
2240}
2241
9d5c8243 2242/**
b980ac18
JK		 2243 * igb_probe - Device Initialization Routine
2244 * @pdev: PCI device information struct
2245 * @ent: entry in igb_pci_tbl
9d5c8243 2246 *
b980ac18 2247 * Returns 0 on success, negative on failure
9d5c8243 2248 *
b980ac18
JK		 2249 * igb_probe initializes an adapter identified by a pci_dev structure.
2250 * The OS initialization, configuring of the adapter private structure,
2251 * and a hardware reset occur.
9d5c8243 2252 **/
1dd06ae8 2253static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2254{
2255 struct net_device *netdev;
2256 struct igb_adapter *adapter;
2257 struct e1000_hw *hw;
4337e993 2258 u16 eeprom_data = 0;
9835fd73 2259 s32 ret_val;
4337e993 2260 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2261 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2262 int err, pci_using_dac;
9835fd73 2263 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2264
bded64a7
AG		 2265 /* Catch broken hardware that put the wrong VF device ID in
2266 * the PCIe SR-IOV capability.
2267 */
2268 if (pdev->is_virtfn) {
2269 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2270 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2271 return -EINVAL;
2272 }
2273
aed5dec3 2274 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2275 if (err)
2276 return err;
2277
2278 pci_using_dac = 0;
dc4ff9bb 2279 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2280 if (!err) {
dc4ff9bb 2281 pci_using_dac = 1;
9d5c8243 2282 } else {
dc4ff9bb 2283 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2284 if (err) {
dc4ff9bb
RK		 2285 dev_err(&pdev->dev,
2286 "No usable DMA configuration, aborting\n");
2287 goto err_dma;
9d5c8243
AK		 2288 }
2289 }
2290
aed5dec3 2291 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2292 IORESOURCE_MEM),
2293 igb_driver_name);
9d5c8243
AK		 2294 if (err)
2295 goto err_pci_reg;
2296
19d5afd4 2297 pci_enable_pcie_error_reporting(pdev);
40a914fa 2298
9d5c8243 2299 pci_set_master(pdev);
c682fc23 2300 pci_save_state(pdev);
9d5c8243
AK		 2301
2302 err = -ENOMEM;
1bfaf07b 2303 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2304 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2305 if (!netdev)
2306 goto err_alloc_etherdev;
2307
2308 SET_NETDEV_DEV(netdev, &pdev->dev);
2309
2310 pci_set_drvdata(pdev, netdev);
2311 adapter = netdev_priv(netdev);
2312 adapter->netdev = netdev;
2313 adapter->pdev = pdev;
2314 hw = &adapter->hw;
2315 hw->back = adapter;
b3f4d599 2316 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2317
9d5c8243 2318 err = -EIO;
73bf8048
JW		 2319 adapter->io_addr = pci_iomap(pdev, 0, 0);
2320 if (!adapter->io_addr)
9d5c8243 2321 goto err_ioremap;
73bf8048
JW		 2322 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2323 hw->hw_addr = adapter->io_addr;
9d5c8243 2324
2e5c6922 2325 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2326 igb_set_ethtool_ops(netdev);
9d5c8243 2327 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2328
2329 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2330
89dbefb2
AS		 2331 netdev->mem_start = pci_resource_start(pdev, 0);
2332 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2333
9d5c8243
AK		 2334 /* PCI config space info */
2335 hw->vendor_id = pdev->vendor;
2336 hw->device_id = pdev->device;
2337 hw->revision_id = pdev->revision;
2338 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2339 hw->subsystem_device_id = pdev->subsystem_device;
2340
9d5c8243
AK		 2341 /* Copy the default MAC, PHY and NVM function pointers */
2342 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2343 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2344 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2345 /* Initialize skew-specific constants */
2346 err = ei->get_invariants(hw);
2347 if (err)
450c87c8 2348 goto err_sw_init;
9d5c8243 2349
450c87c8 2350 /* setup the private structure */
9d5c8243
AK		 2351 err = igb_sw_init(adapter);
2352 if (err)
2353 goto err_sw_init;
2354
2355 igb_get_bus_info_pcie(hw);
2356
2357 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2358
2359 /* Copper options */
2360 if (hw->phy.media_type == e1000_media_type_copper) {
2361 hw->phy.mdix = AUTO_ALL_MODES;
2362 hw->phy.disable_polarity_correction = false;
2363 hw->phy.ms_type = e1000_ms_hw_default;
2364 }
2365
2366 if (igb_check_reset_block(hw))
2367 dev_info(&pdev->dev,
2368 "PHY reset is blocked due to SOL/IDER session.\n");
2369
b980ac18 2370 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2371 * set by igb_sw_init so we should use an or instead of an
2372 * assignment.
2373 */
2374 netdev->features |= NETIF_F_SG |
2375 NETIF_F_IP_CSUM |
2376 NETIF_F_IPV6_CSUM |
2377 NETIF_F_TSO |
2378 NETIF_F_TSO6 |
2379 NETIF_F_RXHASH |
2380 NETIF_F_RXCSUM |
f646968f
PM		 2381 NETIF_F_HW_VLAN_CTAG_RX |
2382 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2383
2384 /* copy netdev features into list of user selectable features */
2385 netdev->hw_features |= netdev->features;
89eaefb6 2386 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2387
2388 /* set this bit last since it cannot be part of hw_features */
f646968f 2389 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2390
2391 netdev->vlan_features |= NETIF_F_TSO |
2392 NETIF_F_TSO6 |
2393 NETIF_F_IP_CSUM |
2394 NETIF_F_IPV6_CSUM |
2395 NETIF_F_SG;
48f29ffc 2396
6b8f0922
BG		 2397 netdev->priv_flags |= IFF_SUPP_NOFCS;
2398
7b872a55 2399 if (pci_using_dac) {
9d5c8243 2400 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2401 netdev->vlan_features |= NETIF_F_HIGHDMA;
2402 }
9d5c8243 2403
ac52caa3 2404 if (hw->mac.type >= e1000_82576) {
53692b1d
TH		 2405 netdev->hw_features |= NETIF_F_SCTP_CRC;
2406 netdev->features |= NETIF_F_SCTP_CRC;
ac52caa3 2407 }
b9473560 2408
01789349
JP		 2409 netdev->priv_flags |= IFF_UNICAST_FLT;
2410
330a6d6a 2411 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2412
2413 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2414 * known good starting state
2415 */
9d5c8243
AK		 2416 hw->mac.ops.reset_hw(hw);
2417
ef3a0092
CW		 2418 /* make sure the NVM is good , i211/i210 parts can have special NVM
2419 * that doesn't contain a checksum
f96a8a0b 2420 */
ef3a0092
CW		 2421 switch (hw->mac.type) {
2422 case e1000_i210:
2423 case e1000_i211:
2424 if (igb_get_flash_presence_i210(hw)) {
2425 if (hw->nvm.ops.validate(hw) < 0) {
2426 dev_err(&pdev->dev,
2427 "The NVM Checksum Is Not Valid\n");
2428 err = -EIO;
2429 goto err_eeprom;
2430 }
2431 }
2432 break;
2433 default:
f96a8a0b
CW		 2434 if (hw->nvm.ops.validate(hw) < 0) {
2435 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2436 err = -EIO;
2437 goto err_eeprom;
2438 }
ef3a0092 2439 break;
9d5c8243
AK		 2440 }
2441
2442 /* copy the MAC address out of the NVM */
2443 if (hw->mac.ops.read_mac_addr(hw))
2444 dev_err(&pdev->dev, "NVM Read Error\n");
2445
2446 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2447
aaeb6cdf 2448 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2449 dev_err(&pdev->dev, "Invalid MAC Address\n");
2450 err = -EIO;
2451 goto err_eeprom;
2452 }
2453
d67974f0
CW		 2454 /* get firmware version for ethtool -i */
2455 igb_set_fw_version(adapter);
2456
27dff8b2
TF		 2457 /* configure RXPBSIZE and TXPBSIZE */
2458 if (hw->mac.type == e1000_i210) {
2459 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2460 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2461 }
2462
c061b18d 2463 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2464 (unsigned long) adapter);
c061b18d 2465 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2466 (unsigned long) adapter);
9d5c8243
AK		 2467
2468 INIT_WORK(&adapter->reset_task, igb_reset_task);
2469 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2470
450c87c8 2471 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2472 adapter->fc_autoneg = true;
2473 hw->mac.autoneg = true;
2474 hw->phy.autoneg_advertised = 0x2f;
2475
0cce119a
AD		 2476 hw->fc.requested_mode = e1000_fc_default;
2477 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2478
9d5c8243
AK		 2479 igb_validate_mdi_setting(hw);
2480
63d4a8f9 2481 /* By default, support wake on port A */
a2cf8b6c 2482 if (hw->bus.func == 0)
63d4a8f9
MV		 2483 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2484
2485 /* Check the NVM for wake support on non-port A ports */
2486 if (hw->mac.type >= e1000_82580)
55cac248 2487 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2488 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2489 &eeprom_data);
a2cf8b6c
AD		 2490 else if (hw->bus.func == 1)
2491 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2492
63d4a8f9
MV		 2493 if (eeprom_data & IGB_EEPROM_APME)
2494 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2495
2496 /* now that we have the eeprom settings, apply the special cases where
2497 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2498 * lan on a particular port
2499 */
9d5c8243
AK		 2500 switch (pdev->device) {
2501 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2502 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2503 break;
2504 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2505 case E1000_DEV_ID_82576_FIBER:
2506 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2507 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2508 * regardless of eeprom setting
2509 */
9d5c8243 2510 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2511 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2512 break;
c8ea5ea9 2513 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2514 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2515 /* if quad port adapter, disable WoL on all but port A */
2516 if (global_quad_port_a != 0)
63d4a8f9 2517 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2518 else
2519 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2520 /* Reset for multiple quad port adapters */
2521 if (++global_quad_port_a == 4)
2522 global_quad_port_a = 0;
2523 break;
63d4a8f9
MV		 2524 default:
2525 /* If the device can't wake, don't set software support */
2526 if (!device_can_wakeup(&adapter->pdev->dev))
2527 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2528 }
2529
2530 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2531 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2532 adapter->wol |= E1000_WUFC_MAG;
2533
2534 /* Some vendors want WoL disabled by default, but still supported */
2535 if ((hw->mac.type == e1000_i350) &&
2536 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2537 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2538 adapter->wol = 0;
2539 }
2540
5e350b92
TF		 2541 /* Some vendors want the ability to Use the EEPROM setting as
2542 * enable/disable only, and not for capability
2543 */
2544 if (((hw->mac.type == e1000_i350) ||
2545 (hw->mac.type == e1000_i354)) &&
2546 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
2547 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2548 adapter->wol = 0;
2549 }
2550 if (hw->mac.type == e1000_i350) {
2551 if (((pdev->subsystem_device == 0x5001) ||
2552 (pdev->subsystem_device == 0x5002)) &&
2553 (hw->bus.func == 0)) {
2554 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2555 adapter->wol = 0;
2556 }
2557 if (pdev->subsystem_device == 0x1F52)
2558 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2559 }
2560
63d4a8f9
MV		 2561 device_set_wakeup_enable(&adapter->pdev->dev,
2562 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2563
2564 /* reset the hardware with the new settings */
2565 igb_reset(adapter);
2566
441fc6fd
CW		 2567 /* Init the I2C interface */
2568 err = igb_init_i2c(adapter);
2569 if (err) {
2570 dev_err(&pdev->dev, "failed to init i2c interface\n");
2571 goto err_eeprom;
2572 }
2573
9d5c8243 2574 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2575 * driver.
2576 */
9d5c8243
AK		 2577 igb_get_hw_control(adapter);
2578
9d5c8243
AK		 2579 strcpy(netdev->name, "eth%d");
2580 err = register_netdev(netdev);
2581 if (err)
2582 goto err_register;
2583
b168dfc5
JB		 2584 /* carrier off reporting is important to ethtool even BEFORE open */
2585 netif_carrier_off(netdev);
2586
421e02f0 2587#ifdef CONFIG_IGB_DCA
bbd98fe4 2588 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2589 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2590 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2591 igb_setup_dca(adapter);
2592 }
fe4506b6 2593
38c845c7 2594#endif
e428893b
CW		 2595#ifdef CONFIG_IGB_HWMON
2596 /* Initialize the thermal sensor on i350 devices. */
2597 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2598 u16 ets_word;
3c89f6d0 2599
b980ac18 2600 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2601 * external thermal sensor.
2602 */
2603 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2604 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2605 adapter->ets = true;
2606 else
2607 adapter->ets = false;
2608 if (igb_sysfs_init(adapter))
2609 dev_err(&pdev->dev,
2610 "failed to allocate sysfs resources\n");
2611 } else {
2612 adapter->ets = false;
2613 }
2614#endif
56cec249
CW		 2615 /* Check if Media Autosense is enabled */
2616 adapter->ei = *ei;
2617 if (hw->dev_spec._82575.mas_capable)
2618 igb_init_mas(adapter);
2619
673b8b70 2620 /* do hw tstamp init after resetting */
7ebae817 2621 igb_ptp_init(adapter);
673b8b70 2622
9d5c8243 2623 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2624 /* print bus type/speed/width info, not applicable to i354 */
2625 if (hw->mac.type != e1000_i354) {
2626 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2627 netdev->name,
2628 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2629 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2630 "unknown"),
2631 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2632 "Width x4" :
2633 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2634 "Width x2" :
2635 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2636 "Width x1" : "unknown"), netdev->dev_addr);
2637 }
9d5c8243 2638
53ea6c7e
TF		 2639 if ((hw->mac.type >= e1000_i210 ||
2640 igb_get_flash_presence_i210(hw))) {
2641 ret_val = igb_read_part_string(hw, part_str,
2642 E1000_PBANUM_LENGTH);
2643 } else {
2644 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2645 }
2646
9835fd73
CW		 2647 if (ret_val)
2648 strcpy(part_str, "Unknown");
2649 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2650 dev_info(&pdev->dev,
2651 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2652 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2653 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2654 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2655 if (hw->phy.media_type == e1000_media_type_copper) {
2656 switch (hw->mac.type) {
2657 case e1000_i350:
2658 case e1000_i210:
2659 case e1000_i211:
2660 /* Enable EEE for internal copper PHY devices */
c4c112f1 2661 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2662 if ((!err) &&
2663 (!hw->dev_spec._82575.eee_disable)) {
2664 adapter->eee_advert =
2665 MDIO_EEE_100TX | MDIO_EEE_1000T;
2666 adapter->flags |= IGB_FLAG_EEE;
2667 }
2668 break;
2669 case e1000_i354:
ceb5f13b 2670 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2671 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2672 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2673 if ((!err) &&
2674 (!hw->dev_spec._82575.eee_disable)) {
2675 adapter->eee_advert =
2676 MDIO_EEE_100TX | MDIO_EEE_1000T;
2677 adapter->flags |= IGB_FLAG_EEE;
2678 }
2679 }
2680 break;
2681 default:
2682 break;
ceb5f13b 2683 }
09b068d4 2684 }
749ab2cd 2685 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2686 return 0;
2687
2688err_register:
2689 igb_release_hw_control(adapter);
441fc6fd 2690 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2691err_eeprom:
2692 if (!igb_check_reset_block(hw))
f5f4cf08 2693 igb_reset_phy(hw);
9d5c8243
AK		 2694
2695 if (hw->flash_address)
2696 iounmap(hw->flash_address);
9d5c8243 2697err_sw_init:
42ad1a03 2698 kfree(adapter->shadow_vfta);
047e0030 2699 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2700#ifdef CONFIG_PCI_IOV
2701 igb_disable_sriov(pdev);
2702#endif
73bf8048 2703 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2704err_ioremap:
2705 free_netdev(netdev);
2706err_alloc_etherdev:
559e9c49 2707 pci_release_selected_regions(pdev,
b980ac18 2708 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2709err_pci_reg:
2710err_dma:
2711 pci_disable_device(pdev);
2712 return err;
2713}
2714
fa44f2f1 2715#ifdef CONFIG_PCI_IOV
781798a1 2716static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2717{
2718 struct net_device *netdev = pci_get_drvdata(pdev);
2719 struct igb_adapter *adapter = netdev_priv(netdev);
2720 struct e1000_hw *hw = &adapter->hw;
2721
2722 /* reclaim resources allocated to VFs */
2723 if (adapter->vf_data) {
2724 /* disable iov and allow time for transactions to clear */
b09186d2 2725 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2726 dev_warn(&pdev->dev,
2727 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2728 return -EPERM;
2729 } else {
2730 pci_disable_sriov(pdev);
2731 msleep(500);
2732 }
2733
2734 kfree(adapter->vf_data);
2735 adapter->vf_data = NULL;
2736 adapter->vfs_allocated_count = 0;
2737 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2738 wrfl();
2739 msleep(100);
2740 dev_info(&pdev->dev, "IOV Disabled\n");
2741
2742 /* Re-enable DMA Coalescing flag since IOV is turned off */
2743 adapter->flags |= IGB_FLAG_DMAC;
2744 }
2745
2746 return 0;
2747}
2748
2749static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2750{
2751 struct net_device *netdev = pci_get_drvdata(pdev);
2752 struct igb_adapter *adapter = netdev_priv(netdev);
2753 int old_vfs = pci_num_vf(pdev);
2754 int err = 0;
2755 int i;
2756
cd14ef54 2757 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2758 err = -EPERM;
2759 goto out;
2760 }
fa44f2f1
GR		 2761 if (!num_vfs)
2762 goto out;
fa44f2f1 2763
781798a1
SA		 2764 if (old_vfs) {
2765 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2766 old_vfs, max_vfs);
2767 adapter->vfs_allocated_count = old_vfs;
2768 } else
2769 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2770
2771 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2772 sizeof(struct vf_data_storage), GFP_KERNEL);
2773
2774 /* if allocation failed then we do not support SR-IOV */
2775 if (!adapter->vf_data) {
2776 adapter->vfs_allocated_count = 0;
2777 dev_err(&pdev->dev,
2778 "Unable to allocate memory for VF Data Storage\n");
2779 err = -ENOMEM;
2780 goto out;
2781 }
2782
781798a1
SA		 2783 /* only call pci_enable_sriov() if no VFs are allocated already */
2784 if (!old_vfs) {
2785 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2786 if (err)
2787 goto err_out;
2788 }
fa44f2f1
GR		 2789 dev_info(&pdev->dev, "%d VFs allocated\n",
2790 adapter->vfs_allocated_count);
2791 for (i = 0; i < adapter->vfs_allocated_count; i++)
2792 igb_vf_configure(adapter, i);
2793
2794 /* DMA Coalescing is not supported in IOV mode. */
2795 adapter->flags &= ~IGB_FLAG_DMAC;
2796 goto out;
2797
2798err_out:
2799 kfree(adapter->vf_data);
2800 adapter->vf_data = NULL;
2801 adapter->vfs_allocated_count = 0;
2802out:
2803 return err;
2804}
2805
2806#endif
b980ac18 2807/**
441fc6fd
CW		 2808 * igb_remove_i2c - Cleanup I2C interface
2809 * @adapter: pointer to adapter structure
b980ac18 2810 **/
441fc6fd
CW		 2811static void igb_remove_i2c(struct igb_adapter *adapter)
2812{
441fc6fd
CW		 2813 /* free the adapter bus structure */
2814 i2c_del_adapter(&adapter->i2c_adap);
2815}
2816
9d5c8243 2817/**
b980ac18
JK		 2818 * igb_remove - Device Removal Routine
2819 * @pdev: PCI device information struct
9d5c8243 2820 *
b980ac18
JK		 2821 * igb_remove is called by the PCI subsystem to alert the driver
2822 * that it should release a PCI device. The could be caused by a
2823 * Hot-Plug event, or because the driver is going to be removed from
2824 * memory.
9d5c8243 2825 **/
9f9a12f8 2826static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2827{
2828 struct net_device *netdev = pci_get_drvdata(pdev);
2829 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2830 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2831
749ab2cd 2832 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2833#ifdef CONFIG_IGB_HWMON
2834 igb_sysfs_exit(adapter);
2835#endif
441fc6fd 2836 igb_remove_i2c(adapter);
a79f4f88 2837 igb_ptp_stop(adapter);
b980ac18 2838 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2839 * disable watchdog from being rescheduled.
2840 */
9d5c8243
AK		 2841 set_bit(__IGB_DOWN, &adapter->state);
2842 del_timer_sync(&adapter->watchdog_timer);
2843 del_timer_sync(&adapter->phy_info_timer);
2844
760141a5
TH		 2845 cancel_work_sync(&adapter->reset_task);
2846 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2847
421e02f0 2848#ifdef CONFIG_IGB_DCA
7dfc16fa 2849 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2850 dev_info(&pdev->dev, "DCA disabled\n");
2851 dca_remove_requester(&pdev->dev);
7dfc16fa 2852 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2853 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2854 }
2855#endif
2856
9d5c8243 2857 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2858 * would have already happened in close and is redundant.
2859 */
9d5c8243
AK		 2860 igb_release_hw_control(adapter);
2861
37680117 2862#ifdef CONFIG_PCI_IOV
fa44f2f1 2863 igb_disable_sriov(pdev);
37680117 2864#endif
559e9c49 2865
c23d92b8
AW		 2866 unregister_netdev(netdev);
2867
2868 igb_clear_interrupt_scheme(adapter);
2869
73bf8048 2870 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2871 if (hw->flash_address)
2872 iounmap(hw->flash_address);
559e9c49 2873 pci_release_selected_regions(pdev,
b980ac18 2874 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2875
1128c756 2876 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2877 free_netdev(netdev);
2878
19d5afd4 2879 pci_disable_pcie_error_reporting(pdev);
40a914fa 2880
9d5c8243
AK		 2881 pci_disable_device(pdev);
2882}
2883
a6b623e0 2884/**
b980ac18
JK		 2885 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2886 * @adapter: board private structure to initialize
a6b623e0 2887 *
b980ac18
JK		 2888 * This function initializes the vf specific data storage and then attempts to
2889 * allocate the VFs. The reason for ordering it this way is because it is much
2890 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2891 * the memory for the VFs.
a6b623e0 2892 **/
9f9a12f8 2893static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2894{
2895#ifdef CONFIG_PCI_IOV
2896 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2897 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2898
f96a8a0b
CW		 2899 /* Virtualization features not supported on i210 family. */
2900 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2901 return;
2902
be06998f
JB		 2903 /* Of the below we really only want the effect of getting
2904 * IGB_FLAG_HAS_MSIX set (if available), without which
2905 * igb_enable_sriov() has no effect.
2906 */
2907 igb_set_interrupt_capability(adapter, true);
2908 igb_reset_interrupt_capability(adapter);
2909
fa44f2f1 2910 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2911 igb_enable_sriov(pdev, max_vfs);
0224d663 2912
a6b623e0
AD		 2913#endif /* CONFIG_PCI_IOV */
2914}
2915
fa44f2f1 2916static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2917{
2918 struct e1000_hw *hw = &adapter->hw;
374a542d 2919 u32 max_rss_queues;
9d5c8243 2920
374a542d 2921 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2922 switch (hw->mac.type) {
374a542d
MV		 2923 case e1000_i211:
2924 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2925 break;
2926 case e1000_82575:
f96a8a0b 2927 case e1000_i210:
374a542d
MV		 2928 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2929 break;
2930 case e1000_i350:
2931 /* I350 cannot do RSS and SR-IOV at the same time */
2932 if (!!adapter->vfs_allocated_count) {
2933 max_rss_queues = 1;
2934 break;
2935 }
2936 /* fall through */
2937 case e1000_82576:
2938 if (!!adapter->vfs_allocated_count) {
2939 max_rss_queues = 2;
2940 break;
2941 }
2942 /* fall through */
2943 case e1000_82580:
ceb5f13b 2944 case e1000_i354:
374a542d
MV		 2945 default:
2946 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2947 break;
374a542d
MV		 2948 }
2949
2950 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2951
72ddef05
SS		 2952 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2953}
2954
2955void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2956 const u32 max_rss_queues)
2957{
2958 struct e1000_hw *hw = &adapter->hw;
2959
374a542d
MV		 2960 /* Determine if we need to pair queues. */
2961 switch (hw->mac.type) {
2962 case e1000_82575:
f96a8a0b 2963 case e1000_i211:
374a542d 2964 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2965 break;
374a542d 2966 case e1000_82576:
374a542d
MV		 2967 case e1000_82580:
2968 case e1000_i350:
ceb5f13b 2969 case e1000_i354:
374a542d 2970 case e1000_i210:
f96a8a0b 2971 default:
b980ac18 2972 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2973 * order to conserve interrupts due to limited supply.
2974 */
2975 if (adapter->rss_queues > (max_rss_queues / 2))
2976 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
37a5d163
SS		 2977 else
2978 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2979 break;
2980 }
fa44f2f1
GR		 2981}
2982
2983/**
b980ac18
JK		 2984 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2985 * @adapter: board private structure to initialize
fa44f2f1 2986 *
b980ac18
JK		 2987 * igb_sw_init initializes the Adapter private data structure.
2988 * Fields are initialized based on PCI device information and
2989 * OS network device settings (MTU size).
fa44f2f1
GR		 2990 **/
2991static int igb_sw_init(struct igb_adapter *adapter)
2992{
2993 struct e1000_hw *hw = &adapter->hw;
2994 struct net_device *netdev = adapter->netdev;
2995 struct pci_dev *pdev = adapter->pdev;
2996
2997 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2998
2999 /* set default ring sizes */
3000 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3001 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3002
3003 /* set default ITR values */
3004 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3005 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3006
3007 /* set default work limits */
3008 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3009
3010 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3011 VLAN_HLEN;
3012 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3013
3014 spin_lock_init(&adapter->stats64_lock);
3015#ifdef CONFIG_PCI_IOV
3016 switch (hw->mac.type) {
3017 case e1000_82576:
3018 case e1000_i350:
3019 if (max_vfs > 7) {
3020 dev_warn(&pdev->dev,
3021 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 3022 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 3023 } else
3024 adapter->vfs_allocated_count = max_vfs;
3025 if (adapter->vfs_allocated_count)
3026 dev_warn(&pdev->dev,
3027 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3028 break;
3029 default:
3030 break;
3031 }
3032#endif /* CONFIG_PCI_IOV */
3033
cbfe360a
SA		 3034 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3035 adapter->flags |= IGB_FLAG_HAS_MSIX;
3036
ceee3450
TF		 3037 igb_probe_vfs(adapter);
3038
fa44f2f1 3039 igb_init_queue_configuration(adapter);
a99955fc 3040
1128c756 3041 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 3042 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3043 GFP_ATOMIC);
1128c756 3044
a6b623e0 3045 /* This call may decrease the number of queues */
53c7d064 3046 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3047 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3048 return -ENOMEM;
3049 }
3050
3051 /* Explicitly disable IRQ since the NIC can be in any state. */
3052 igb_irq_disable(adapter);
3053
f96a8a0b 3054 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3055 adapter->flags &= ~IGB_FLAG_DMAC;
3056
9d5c8243
AK		 3057 set_bit(__IGB_DOWN, &adapter->state);
3058 return 0;
3059}
3060
3061/**
b980ac18
JK		 3062 * igb_open - Called when a network interface is made active
3063 * @netdev: network interface device structure
9d5c8243 3064 *
b980ac18 3065 * Returns 0 on success, negative value on failure
9d5c8243 3066 *
b980ac18
JK		 3067 * The open entry point is called when a network interface is made
3068 * active by the system (IFF_UP). At this point all resources needed
3069 * for transmit and receive operations are allocated, the interrupt
3070 * handler is registered with the OS, the watchdog timer is started,
3071 * and the stack is notified that the interface is ready.
9d5c8243 3072 **/
749ab2cd 3073static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3074{
3075 struct igb_adapter *adapter = netdev_priv(netdev);
3076 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3077 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3078 int err;
3079 int i;
3080
3081 /* disallow open during test */
749ab2cd
YZ		 3082 if (test_bit(__IGB_TESTING, &adapter->state)) {
3083 WARN_ON(resuming);
9d5c8243 3084 return -EBUSY;
749ab2cd
YZ		 3085 }
3086
3087 if (!resuming)
3088 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3089
b168dfc5
JB		 3090 netif_carrier_off(netdev);
3091
9d5c8243
AK		 3092 /* allocate transmit descriptors */
3093 err = igb_setup_all_tx_resources(adapter);
3094 if (err)
3095 goto err_setup_tx;
3096
3097 /* allocate receive descriptors */
3098 err = igb_setup_all_rx_resources(adapter);
3099 if (err)
3100 goto err_setup_rx;
3101
88a268c1 3102 igb_power_up_link(adapter);
9d5c8243 3103
9d5c8243
AK		 3104 /* before we allocate an interrupt, we must be ready to handle it.
3105 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3106 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3107 * clean_rx handler before we do so.
3108 */
9d5c8243
AK		 3109 igb_configure(adapter);
3110
3111 err = igb_request_irq(adapter);
3112 if (err)
3113 goto err_req_irq;
3114
0c2cc02e
AD		 3115 /* Notify the stack of the actual queue counts. */
3116 err = netif_set_real_num_tx_queues(adapter->netdev,
3117 adapter->num_tx_queues);
3118 if (err)
3119 goto err_set_queues;
3120
3121 err = netif_set_real_num_rx_queues(adapter->netdev,
3122 adapter->num_rx_queues);
3123 if (err)
3124 goto err_set_queues;
3125
9d5c8243
AK		 3126 /* From here on the code is the same as igb_up() */
3127 clear_bit(__IGB_DOWN, &adapter->state);
3128
0d1ae7f4
AD		 3129 for (i = 0; i < adapter->num_q_vectors; i++)
3130 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3131
3132 /* Clear any pending interrupts. */
3133 rd32(E1000_ICR);
844290e5
PW		 3134
3135 igb_irq_enable(adapter);
3136
d4960307
AD		 3137 /* notify VFs that reset has been completed */
3138 if (adapter->vfs_allocated_count) {
3139 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3140
d4960307
AD		 3141 reg_data |= E1000_CTRL_EXT_PFRSTD;
3142 wr32(E1000_CTRL_EXT, reg_data);
3143 }
3144
d55b53ff
JK		 3145 netif_tx_start_all_queues(netdev);
3146
749ab2cd
YZ		 3147 if (!resuming)
3148 pm_runtime_put(&pdev->dev);
3149
25568a53
AD		 3150 /* start the watchdog. */
3151 hw->mac.get_link_status = 1;
3152 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3153
3154 return 0;
3155
0c2cc02e
AD		 3156err_set_queues:
3157 igb_free_irq(adapter);
9d5c8243
AK		 3158err_req_irq:
3159 igb_release_hw_control(adapter);
88a268c1 3160 igb_power_down_link(adapter);
9d5c8243
AK		 3161 igb_free_all_rx_resources(adapter);
3162err_setup_rx:
3163 igb_free_all_tx_resources(adapter);
3164err_setup_tx:
3165 igb_reset(adapter);
749ab2cd
YZ		 3166 if (!resuming)
3167 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3168
3169 return err;
3170}
3171
749ab2cd
YZ		 3172static int igb_open(struct net_device *netdev)
3173{
3174 return __igb_open(netdev, false);
3175}
3176
9d5c8243 3177/**
b980ac18
JK		 3178 * igb_close - Disables a network interface
3179 * @netdev: network interface device structure
9d5c8243 3180 *
b980ac18 3181 * Returns 0, this is not allowed to fail
9d5c8243 3182 *
b980ac18
JK		 3183 * The close entry point is called when an interface is de-activated
3184 * by the OS. The hardware is still under the driver's control, but
3185 * needs to be disabled. A global MAC reset is issued to stop the
3186 * hardware, and all transmit and receive resources are freed.
9d5c8243 3187 **/
749ab2cd 3188static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3189{
3190 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3191 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3192
3193 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3194
749ab2cd
YZ		 3195 if (!suspending)
3196 pm_runtime_get_sync(&pdev->dev);
3197
3198 igb_down(adapter);
9d5c8243
AK		 3199 igb_free_irq(adapter);
3200
3201 igb_free_all_tx_resources(adapter);
3202 igb_free_all_rx_resources(adapter);
3203
749ab2cd
YZ		 3204 if (!suspending)
3205 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3206 return 0;
3207}
3208
749ab2cd
YZ		 3209static int igb_close(struct net_device *netdev)
3210{
3211 return __igb_close(netdev, false);
3212}
3213
9d5c8243 3214/**
b980ac18
JK		 3215 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3216 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3217 *
b980ac18 3218 * Return 0 on success, negative on failure
9d5c8243 3219 **/
80785298 3220int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3221{
59d71989 3222 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3223 int size;
3224
06034649 3225 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3226
3227 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3228 if (!tx_ring->tx_buffer_info)
9d5c8243 3229 goto err;
9d5c8243
AK		 3230
3231 /* round up to nearest 4K */
85e8d004 3232 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3233 tx_ring->size = ALIGN(tx_ring->size, 4096);
3234
5536d210
AD		 3235 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3236 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3237 if (!tx_ring->desc)
3238 goto err;
3239
9d5c8243
AK		 3240 tx_ring->next_to_use = 0;
3241 tx_ring->next_to_clean = 0;
81c2fc22 3242
9d5c8243
AK		 3243 return 0;
3244
3245err:
06034649 3246 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3247 tx_ring->tx_buffer_info = NULL;
3248 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3249 return -ENOMEM;
3250}
3251
3252/**
b980ac18
JK		 3253 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3254 * (Descriptors) for all queues
3255 * @adapter: board private structure
9d5c8243 3256 *
b980ac18 3257 * Return 0 on success, negative on failure
9d5c8243
AK		 3258 **/
3259static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3260{
439705e1 3261 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3262 int i, err = 0;
3263
3264 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3265 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3266 if (err) {
439705e1 3267 dev_err(&pdev->dev,
9d5c8243
AK		 3268 "Allocation for Tx Queue %u failed\n", i);
3269 for (i--; i >= 0; i--)
3025a446 3270 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3271 break;
3272 }
3273 }
3274
3275 return err;
3276}
3277
3278/**
b980ac18
JK		 3279 * igb_setup_tctl - configure the transmit control registers
3280 * @adapter: Board private structure
9d5c8243 3281 **/
d7ee5b3a 3282void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3283{
9d5c8243
AK		 3284 struct e1000_hw *hw = &adapter->hw;
3285 u32 tctl;
9d5c8243 3286
85b430b4
AD		 3287 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3288 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3289
3290 /* Program the Transmit Control Register */
9d5c8243
AK		 3291 tctl = rd32(E1000_TCTL);
3292 tctl &= ~E1000_TCTL_CT;
3293 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3294 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3295
3296 igb_config_collision_dist(hw);
3297
9d5c8243
AK		 3298 /* Enable transmits */
3299 tctl |= E1000_TCTL_EN;
3300
3301 wr32(E1000_TCTL, tctl);
3302}
3303
85b430b4 3304/**
b980ac18
JK		 3305 * igb_configure_tx_ring - Configure transmit ring after Reset
3306 * @adapter: board private structure
3307 * @ring: tx ring to configure
85b430b4 3308 *
b980ac18 3309 * Configure a transmit ring after a reset.
85b430b4 3310 **/
d7ee5b3a 3311void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3312 struct igb_ring *ring)
85b430b4
AD		 3313{
3314 struct e1000_hw *hw = &adapter->hw;
a74420e0 3315 u32 txdctl = 0;
85b430b4
AD		 3316 u64 tdba = ring->dma;
3317 int reg_idx = ring->reg_idx;
3318
3319 /* disable the queue */
a74420e0 3320 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3321 wrfl();
3322 mdelay(10);
3323
3324 wr32(E1000_TDLEN(reg_idx),
b980ac18 3325 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3326 wr32(E1000_TDBAL(reg_idx),
b980ac18 3327 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3328 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3329
fce99e34 3330 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3331 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3332 writel(0, ring->tail);
85b430b4
AD		 3333
3334 txdctl |= IGB_TX_PTHRESH;
3335 txdctl |= IGB_TX_HTHRESH << 8;
3336 txdctl |= IGB_TX_WTHRESH << 16;
3337
3338 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3339 wr32(E1000_TXDCTL(reg_idx), txdctl);
3340}
3341
3342/**
b980ac18
JK		 3343 * igb_configure_tx - Configure transmit Unit after Reset
3344 * @adapter: board private structure
85b430b4 3345 *
b980ac18 3346 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3347 **/
3348static void igb_configure_tx(struct igb_adapter *adapter)
3349{
3350 int i;
3351
3352 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3353 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3354}
3355
9d5c8243 3356/**
b980ac18
JK		 3357 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3358 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3359 *
b980ac18 3360 * Returns 0 on success, negative on failure
9d5c8243 3361 **/
80785298 3362int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3363{
59d71989 3364 struct device *dev = rx_ring->dev;
f33005a6 3365 int size;
9d5c8243 3366
06034649 3367 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3368
3369 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3370 if (!rx_ring->rx_buffer_info)
9d5c8243 3371 goto err;
9d5c8243 3372
9d5c8243 3373 /* Round up to nearest 4K */
f33005a6 3374 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3375 rx_ring->size = ALIGN(rx_ring->size, 4096);
3376
5536d210
AD		 3377 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3378 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3379 if (!rx_ring->desc)
3380 goto err;
3381
cbc8e55f 3382 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3383 rx_ring->next_to_clean = 0;
3384 rx_ring->next_to_use = 0;
9d5c8243 3385
9d5c8243
AK		 3386 return 0;
3387
3388err:
06034649
AD		 3389 vfree(rx_ring->rx_buffer_info);
3390 rx_ring->rx_buffer_info = NULL;
f33005a6 3391 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3392 return -ENOMEM;
3393}
3394
3395/**
b980ac18
JK		 3396 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3397 * (Descriptors) for all queues
3398 * @adapter: board private structure
9d5c8243 3399 *
b980ac18 3400 * Return 0 on success, negative on failure
9d5c8243
AK		 3401 **/
3402static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3403{
439705e1 3404 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3405 int i, err = 0;
3406
3407 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3408 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3409 if (err) {
439705e1 3410 dev_err(&pdev->dev,
9d5c8243
AK		 3411 "Allocation for Rx Queue %u failed\n", i);
3412 for (i--; i >= 0; i--)
3025a446 3413 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3414 break;
3415 }
3416 }
3417
3418 return err;
3419}
3420
06cf2666 3421/**
b980ac18
JK		 3422 * igb_setup_mrqc - configure the multiple receive queue control registers
3423 * @adapter: Board private structure
06cf2666
AD		 3424 **/
3425static void igb_setup_mrqc(struct igb_adapter *adapter)
3426{
3427 struct e1000_hw *hw = &adapter->hw;
3428 u32 mrqc, rxcsum;
ed12cc9a 3429 u32 j, num_rx_queues;
eb31f849 3430 u32 rss_key[10];
06cf2666 3431
eb31f849 3432 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3433 for (j = 0; j < 10; j++)
eb31f849 3434 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3435
a99955fc 3436 num_rx_queues = adapter->rss_queues;
06cf2666 3437
797fd4be 3438 switch (hw->mac.type) {
797fd4be
AD		 3439 case e1000_82576:
3440 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3441 if (adapter->vfs_allocated_count)
06cf2666 3442 num_rx_queues = 2;
797fd4be
AD		 3443 break;
3444 default:
3445 break;
06cf2666
AD		 3446 }
3447
ed12cc9a
LMV		 3448 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3449 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3450 adapter->rss_indir_tbl[j] =
3451 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3452 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3453 }
ed12cc9a 3454 igb_write_rss_indir_tbl(adapter);
06cf2666 3455
b980ac18 3456 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3457 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3458 * offloads as they are enabled by default
3459 */
3460 rxcsum = rd32(E1000_RXCSUM);
3461 rxcsum |= E1000_RXCSUM_PCSD;
3462
3463 if (adapter->hw.mac.type >= e1000_82576)
3464 /* Enable Receive Checksum Offload for SCTP */
3465 rxcsum |= E1000_RXCSUM_CRCOFL;
3466
3467 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3468 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3469
039454a8
AA		 3470 /* Generate RSS hash based on packet types, TCP/UDP
3471 * port numbers and/or IPv4/v6 src and dst addresses
3472 */
f96a8a0b
CW		 3473 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3474 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3475 E1000_MRQC_RSS_FIELD_IPV6 |
3476 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3477 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3478
039454a8
AA		 3479 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3480 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3481 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3482 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3483
06cf2666
AD		 3484 /* If VMDq is enabled then we set the appropriate mode for that, else
3485 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3486 * if we are only using one queue
3487 */
06cf2666
AD		 3488 if (adapter->vfs_allocated_count) {
3489 if (hw->mac.type > e1000_82575) {
3490 /* Set the default pool for the PF's first queue */
3491 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3492
06cf2666
AD		 3493 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3494 E1000_VT_CTL_DISABLE_DEF_POOL);
3495 vtctl |= adapter->vfs_allocated_count <<
3496 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3497 wr32(E1000_VT_CTL, vtctl);
3498 }
a99955fc 3499 if (adapter->rss_queues > 1)
c883de9f 3500 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
06cf2666 3501 else
f96a8a0b 3502 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3503 } else {
f96a8a0b 3504 if (hw->mac.type != e1000_i211)
c883de9f 3505 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
06cf2666
AD		 3506 }
3507 igb_vmm_control(adapter);
3508
06cf2666
AD		 3509 wr32(E1000_MRQC, mrqc);
3510}
3511
9d5c8243 3512/**
b980ac18
JK		 3513 * igb_setup_rctl - configure the receive control registers
3514 * @adapter: Board private structure
9d5c8243 3515 **/
d7ee5b3a 3516void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3517{
3518 struct e1000_hw *hw = &adapter->hw;
3519 u32 rctl;
9d5c8243
AK		 3520
3521 rctl = rd32(E1000_RCTL);
3522
3523 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3524 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3525
69d728ba 3526 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3527 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3528
b980ac18 3529 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3530 * redirection as it did with e1000. Newer features require
3531 * that the HW strips the CRC.
73cd78f1 3532 */
87cb7e8c 3533 rctl |= E1000_RCTL_SECRC;
9d5c8243 3534
559e9c49 3535 /* disable store bad packets and clear size bits. */
ec54d7d6 3536 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3537
45693bcb 3538 /* enable LPE to allow for reception of jumbo frames */
6ec43fe6 3539 rctl |= E1000_RCTL_LPE;
9d5c8243 3540
952f72a8
AD		 3541 /* disable queue 0 to prevent tail write w/o re-config */
3542 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3543
e1739522
AD		 3544 /* Attention!!! For SR-IOV PF driver operations you must enable
3545 * queue drop for all VF and PF queues to prevent head of line blocking
3546 * if an un-trusted VF does not provide descriptors to hardware.
3547 */
3548 if (adapter->vfs_allocated_count) {
e1739522
AD		 3549 /* set all queue drop enable bits */
3550 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3551 }
3552
89eaefb6
BG		 3553 /* This is useful for sniffing bad packets. */
3554 if (adapter->netdev->features & NETIF_F_RXALL) {
3555 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3556 * in e1000e_set_rx_mode
3557 */
89eaefb6
BG		 3558 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3559 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3560 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3561
16903caa 3562 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
89eaefb6
BG		 3563 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3564 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3565 * and that breaks VLANs.
3566 */
3567 }
3568
9d5c8243
AK		 3569 wr32(E1000_RCTL, rctl);
3570}
3571
7d5753f0 3572static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3573 int vfn)
7d5753f0
AD		 3574{
3575 struct e1000_hw *hw = &adapter->hw;
3576 u32 vmolr;
3577
d3836f8e
AD		 3578 if (size > MAX_JUMBO_FRAME_SIZE)
3579 size = MAX_JUMBO_FRAME_SIZE;
7d5753f0
AD		 3580
3581 vmolr = rd32(E1000_VMOLR(vfn));
3582 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3583 vmolr |= size | E1000_VMOLR_LPE;
3584 wr32(E1000_VMOLR(vfn), vmolr);
3585
3586 return 0;
3587}
3588
8151d294
WM		 3589static inline void igb_set_vmolr(struct igb_adapter *adapter,
3590 int vfn, bool aupe)
7d5753f0
AD		 3591{
3592 struct e1000_hw *hw = &adapter->hw;
3593 u32 vmolr;
3594
b980ac18 3595 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3596 * we should exit and do nothing
3597 */
3598 if (hw->mac.type < e1000_82576)
3599 return;
3600
3601 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3602 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3603 if (hw->mac.type == e1000_i350) {
3604 u32 dvmolr;
3605
3606 dvmolr = rd32(E1000_DVMOLR(vfn));
3607 dvmolr |= E1000_DVMOLR_STRVLAN;
3608 wr32(E1000_DVMOLR(vfn), dvmolr);
3609 }
8151d294 3610 if (aupe)
b980ac18 3611 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3612 else
3613 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3614
3615 /* clear all bits that might not be set */
3616 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3617
a99955fc 3618 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3619 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3620 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3621 * multicast packets
3622 */
3623 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3624 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3625
3626 wr32(E1000_VMOLR(vfn), vmolr);
3627}
3628
85b430b4 3629/**
b980ac18
JK		 3630 * igb_configure_rx_ring - Configure a receive ring after Reset
3631 * @adapter: board private structure
3632 * @ring: receive ring to be configured
85b430b4 3633 *
b980ac18 3634 * Configure the Rx unit of the MAC after a reset.
85b430b4 3635 **/
d7ee5b3a 3636void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3637 struct igb_ring *ring)
85b430b4
AD		 3638{
3639 struct e1000_hw *hw = &adapter->hw;
3640 u64 rdba = ring->dma;
3641 int reg_idx = ring->reg_idx;
a74420e0 3642 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3643
3644 /* disable the queue */
a74420e0 3645 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3646
3647 /* Set DMA base address registers */
3648 wr32(E1000_RDBAL(reg_idx),
3649 rdba & 0x00000000ffffffffULL);
3650 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3651 wr32(E1000_RDLEN(reg_idx),
b980ac18 3652 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3653
3654 /* initialize head and tail */
fce99e34 3655 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3656 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3657 writel(0, ring->tail);
85b430b4 3658
952f72a8 3659 /* set descriptor configuration */
44390ca6 3660 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3661 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3662 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3663 if (hw->mac.type >= e1000_82580)
757b77e2 3664 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3665 /* Only set Drop Enable if we are supporting multiple queues */
3666 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3667 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3668
3669 wr32(E1000_SRRCTL(reg_idx), srrctl);
3670
7d5753f0 3671 /* set filtering for VMDQ pools */
8151d294 3672 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3673
85b430b4
AD		 3674 rxdctl |= IGB_RX_PTHRESH;
3675 rxdctl |= IGB_RX_HTHRESH << 8;
3676 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3677
3678 /* enable receive descriptor fetching */
3679 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3680 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3681}
3682
9d5c8243 3683/**
b980ac18
JK		 3684 * igb_configure_rx - Configure receive Unit after Reset
3685 * @adapter: board private structure
9d5c8243 3686 *
b980ac18 3687 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3688 **/
3689static void igb_configure_rx(struct igb_adapter *adapter)
3690{
9107584e 3691 int i;
9d5c8243 3692
26ad9178
AD		 3693 /* set the correct pool for the PF default MAC address in entry 0 */
3694 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3695 adapter->vfs_allocated_count);
26ad9178 3696
06cf2666 3697 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3698 * the Base and Length of the Rx Descriptor Ring
3699 */
f9d40f6a
AD		 3700 for (i = 0; i < adapter->num_rx_queues; i++)
3701 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3702}
3703
3704/**
b980ac18
JK		 3705 * igb_free_tx_resources - Free Tx Resources per Queue
3706 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3707 *
b980ac18 3708 * Free all transmit software resources
9d5c8243 3709 **/
68fd9910 3710void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3711{
3b644cf6 3712 igb_clean_tx_ring(tx_ring);
9d5c8243 3713
06034649
AD		 3714 vfree(tx_ring->tx_buffer_info);
3715 tx_ring->tx_buffer_info = NULL;
9d5c8243 3716
439705e1
AD		 3717 /* if not set, then don't free */
3718 if (!tx_ring->desc)
3719 return;
3720
59d71989
AD		 3721 dma_free_coherent(tx_ring->dev, tx_ring->size,
3722 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3723
3724 tx_ring->desc = NULL;
3725}
3726
3727/**
b980ac18
JK		 3728 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3729 * @adapter: board private structure
9d5c8243 3730 *
b980ac18 3731 * Free all transmit software resources
9d5c8243
AK		 3732 **/
3733static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3734{
3735 int i;
3736
3737 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3738 if (adapter->tx_ring[i])
3739 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3740}
3741
ebe42d16
AD		 3742void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3743 struct igb_tx_buffer *tx_buffer)
3744{
3745 if (tx_buffer->skb) {
3746 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3747 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3748 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3749 dma_unmap_addr(tx_buffer, dma),
3750 dma_unmap_len(tx_buffer, len),
ebe42d16 3751 DMA_TO_DEVICE);
c9f14bf3 3752 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3753 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3754 dma_unmap_addr(tx_buffer, dma),
3755 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3756 DMA_TO_DEVICE);
3757 }
3758 tx_buffer->next_to_watch = NULL;
3759 tx_buffer->skb = NULL;
c9f14bf3 3760 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3761 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3762}
3763
3764/**
b980ac18
JK		 3765 * igb_clean_tx_ring - Free Tx Buffers
3766 * @tx_ring: ring to be cleaned
9d5c8243 3767 **/
3b644cf6 3768static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3769{
06034649 3770 struct igb_tx_buffer *buffer_info;
9d5c8243 3771 unsigned long size;
6ad4edfc 3772 u16 i;
9d5c8243 3773
06034649 3774 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3775 return;
3776 /* Free all the Tx ring sk_buffs */
3777
3778 for (i = 0; i < tx_ring->count; i++) {
06034649 3779 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3780 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3781 }
3782
dad8a3b3
JF		 3783 netdev_tx_reset_queue(txring_txq(tx_ring));
3784
06034649
AD		 3785 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3786 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3787
3788 /* Zero out the descriptor ring */
9d5c8243
AK		 3789 memset(tx_ring->desc, 0, tx_ring->size);
3790
3791 tx_ring->next_to_use = 0;
3792 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3793}
3794
3795/**
b980ac18
JK		 3796 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3797 * @adapter: board private structure
9d5c8243
AK		 3798 **/
3799static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3800{
3801 int i;
3802
3803 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3804 if (adapter->tx_ring[i])
3805 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3806}
3807
3808/**
b980ac18
JK		 3809 * igb_free_rx_resources - Free Rx Resources
3810 * @rx_ring: ring to clean the resources from
9d5c8243 3811 *
b980ac18 3812 * Free all receive software resources
9d5c8243 3813 **/
68fd9910 3814void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3815{
3b644cf6 3816 igb_clean_rx_ring(rx_ring);
9d5c8243 3817
06034649
AD		 3818 vfree(rx_ring->rx_buffer_info);
3819 rx_ring->rx_buffer_info = NULL;
9d5c8243 3820
439705e1
AD		 3821 /* if not set, then don't free */
3822 if (!rx_ring->desc)
3823 return;
3824
59d71989
AD		 3825 dma_free_coherent(rx_ring->dev, rx_ring->size,
3826 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3827
3828 rx_ring->desc = NULL;
3829}
3830
3831/**
b980ac18
JK		 3832 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3833 * @adapter: board private structure
9d5c8243 3834 *
b980ac18 3835 * Free all receive software resources
9d5c8243
AK		 3836 **/
3837static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3838{
3839 int i;
3840
3841 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3842 if (adapter->rx_ring[i])
3843 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3844}
3845
3846/**
b980ac18
JK		 3847 * igb_clean_rx_ring - Free Rx Buffers per Queue
3848 * @rx_ring: ring to free buffers from
9d5c8243 3849 **/
3b644cf6 3850static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3851{
9d5c8243 3852 unsigned long size;
c023cd88 3853 u16 i;
9d5c8243 3854
1a1c225b
AD		 3855 if (rx_ring->skb)
3856 dev_kfree_skb(rx_ring->skb);
3857 rx_ring->skb = NULL;
3858
06034649 3859 if (!rx_ring->rx_buffer_info)
9d5c8243 3860 return;
439705e1 3861
9d5c8243
AK		 3862 /* Free all the Rx ring sk_buffs */
3863 for (i = 0; i < rx_ring->count; i++) {
06034649 3864 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3865
cbc8e55f
AD		 3866 if (!buffer_info->page)
3867 continue;
3868
3869 dma_unmap_page(rx_ring->dev,
3870 buffer_info->dma,
3871 PAGE_SIZE,
3872 DMA_FROM_DEVICE);
3873 __free_page(buffer_info->page);
3874
1a1c225b 3875 buffer_info->page = NULL;
9d5c8243
AK		 3876 }
3877
06034649
AD		 3878 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3879 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3880
3881 /* Zero out the descriptor ring */
3882 memset(rx_ring->desc, 0, rx_ring->size);
3883
cbc8e55f 3884 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3885 rx_ring->next_to_clean = 0;
3886 rx_ring->next_to_use = 0;
9d5c8243
AK		 3887}
3888
3889/**
b980ac18
JK		 3890 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3891 * @adapter: board private structure
9d5c8243
AK		 3892 **/
3893static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3894{
3895 int i;
3896
3897 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3898 if (adapter->rx_ring[i])
3899 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3900}
3901
3902/**
b980ac18
JK		 3903 * igb_set_mac - Change the Ethernet Address of the NIC
3904 * @netdev: network interface device structure
3905 * @p: pointer to an address structure
9d5c8243 3906 *
b980ac18 3907 * Returns 0 on success, negative on failure
9d5c8243
AK		 3908 **/
3909static int igb_set_mac(struct net_device *netdev, void *p)
3910{
3911 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3912 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3913 struct sockaddr *addr = p;
3914
3915 if (!is_valid_ether_addr(addr->sa_data))
3916 return -EADDRNOTAVAIL;
3917
3918 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3919 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3920
26ad9178
AD		 3921 /* set the correct pool for the new PF MAC address in entry 0 */
3922 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3923 adapter->vfs_allocated_count);
e1739522 3924
9d5c8243
AK		 3925 return 0;
3926}
3927
3928/**
b980ac18
JK		 3929 * igb_write_mc_addr_list - write multicast addresses to MTA
3930 * @netdev: network interface device structure
9d5c8243 3931 *
b980ac18
JK		 3932 * Writes multicast address list to the MTA hash table.
3933 * Returns: -ENOMEM on failure
3934 * 0 on no addresses written
3935 * X on writing X addresses to MTA
9d5c8243 3936 **/
68d480c4 3937static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3938{
3939 struct igb_adapter *adapter = netdev_priv(netdev);
3940 struct e1000_hw *hw = &adapter->hw;
22bedad3 3941 struct netdev_hw_addr *ha;
68d480c4 3942 u8 *mta_list;
9d5c8243
AK		 3943 int i;
3944
4cd24eaf 3945 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3946 /* nothing to program, so clear mc list */
3947 igb_update_mc_addr_list(hw, NULL, 0);
3948 igb_restore_vf_multicasts(adapter);
3949 return 0;
3950 }
9d5c8243 3951
4cd24eaf 3952 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3953 if (!mta_list)
3954 return -ENOMEM;
ff41f8dc 3955
68d480c4 3956 /* The shared function expects a packed array of only addresses. */
48e2f183 3957 i = 0;
22bedad3
JP		 3958 netdev_for_each_mc_addr(ha, netdev)
3959 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3960
68d480c4
AD		 3961 igb_update_mc_addr_list(hw, mta_list, i);
3962 kfree(mta_list);
3963
4cd24eaf 3964 return netdev_mc_count(netdev);
68d480c4
AD		 3965}
3966
3967/**
b980ac18
JK		 3968 * igb_write_uc_addr_list - write unicast addresses to RAR table
3969 * @netdev: network interface device structure
68d480c4 3970 *
b980ac18
JK		 3971 * Writes unicast address list to the RAR table.
3972 * Returns: -ENOMEM on failure/insufficient address space
3973 * 0 on no addresses written
3974 * X on writing X addresses to the RAR table
68d480c4
AD		 3975 **/
3976static int igb_write_uc_addr_list(struct net_device *netdev)
3977{
3978 struct igb_adapter *adapter = netdev_priv(netdev);
3979 struct e1000_hw *hw = &adapter->hw;
3980 unsigned int vfn = adapter->vfs_allocated_count;
3981 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3982 int count = 0;
3983
3984 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3985 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3986 return -ENOMEM;
9d5c8243 3987
32e7bfc4 3988 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3989 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3990
3991 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3992 if (!rar_entries)
3993 break;
26ad9178 3994 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3995 rar_entries--,
3996 vfn);
68d480c4 3997 count++;
ff41f8dc
AD		 3998 }
3999 }
4000 /* write the addresses in reverse order to avoid write combining */
4001 for (; rar_entries > 0 ; rar_entries--) {
4002 wr32(E1000_RAH(rar_entries), 0);
4003 wr32(E1000_RAL(rar_entries), 0);
4004 }
4005 wrfl();
4006
68d480c4
AD		 4007 return count;
4008}
4009
16903caa
AD		 4010static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4011{
4012 struct e1000_hw *hw = &adapter->hw;
4013 u32 i, pf_id;
4014
4015 switch (hw->mac.type) {
4016 case e1000_i210:
4017 case e1000_i211:
4018 case e1000_i350:
4019 /* VLAN filtering needed for VLAN prio filter */
4020 if (adapter->netdev->features & NETIF_F_NTUPLE)
4021 break;
4022 /* fall through */
4023 case e1000_82576:
4024 case e1000_82580:
4025 case e1000_i354:
4026 /* VLAN filtering needed for pool filtering */
4027 if (adapter->vfs_allocated_count)
4028 break;
4029 /* fall through */
4030 default:
4031 return 1;
4032 }
4033
4034 /* We are already in VLAN promisc, nothing to do */
4035 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4036 return 0;
4037
4038 if (!adapter->vfs_allocated_count)
4039 goto set_vfta;
4040
4041 /* Add PF to all active pools */
4042 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4043
4044 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4045 u32 vlvf = rd32(E1000_VLVF(i));
4046
4047 vlvf |= 1 << pf_id;
4048 wr32(E1000_VLVF(i), vlvf);
4049 }
4050
4051set_vfta:
4052 /* Set all bits in the VLAN filter table array */
4053 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4054 hw->mac.ops.write_vfta(hw, i, ~0U);
4055
4056 /* Set flag so we don't redo unnecessary work */
4057 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4058
4059 return 0;
4060}
4061
4062#define VFTA_BLOCK_SIZE 8
4063static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4064{
4065 struct e1000_hw *hw = &adapter->hw;
4066 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4067 u32 vid_start = vfta_offset * 32;
4068 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4069 u32 i, vid, word, bits, pf_id;
4070
4071 /* guarantee that we don't scrub out management VLAN */
4072 vid = adapter->mng_vlan_id;
4073 if (vid >= vid_start && vid < vid_end)
4074 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4075
4076 if (!adapter->vfs_allocated_count)
4077 goto set_vfta;
4078
4079 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4080
4081 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4082 u32 vlvf = rd32(E1000_VLVF(i));
4083
4084 /* pull VLAN ID from VLVF */
4085 vid = vlvf & VLAN_VID_MASK;
4086
4087 /* only concern ourselves with a certain range */
4088 if (vid < vid_start || vid >= vid_end)
4089 continue;
4090
4091 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4092 /* record VLAN ID in VFTA */
4093 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4094
4095 /* if PF is part of this then continue */
4096 if (test_bit(vid, adapter->active_vlans))
4097 continue;
4098 }
4099
4100 /* remove PF from the pool */
4101 bits = ~(1 << pf_id);
4102 bits &= rd32(E1000_VLVF(i));
4103 wr32(E1000_VLVF(i), bits);
4104 }
4105
4106set_vfta:
4107 /* extract values from active_vlans and write back to VFTA */
4108 for (i = VFTA_BLOCK_SIZE; i--;) {
4109 vid = (vfta_offset + i) * 32;
4110 word = vid / BITS_PER_LONG;
4111 bits = vid % BITS_PER_LONG;
4112
4113 vfta[i] |= adapter->active_vlans[word] >> bits;
4114
4115 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4116 }
4117}
4118
4119static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4120{
4121 u32 i;
4122
4123 /* We are not in VLAN promisc, nothing to do */
4124 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4125 return;
4126
4127 /* Set flag so we don't redo unnecessary work */
4128 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4129
4130 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4131 igb_scrub_vfta(adapter, i);
4132}
4133
68d480c4 4134/**
b980ac18
JK		 4135 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4136 * @netdev: network interface device structure
68d480c4 4137 *
b980ac18
JK		 4138 * The set_rx_mode entry point is called whenever the unicast or multicast
4139 * address lists or the network interface flags are updated. This routine is
4140 * responsible for configuring the hardware for proper unicast, multicast,
4141 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4142 **/
4143static void igb_set_rx_mode(struct net_device *netdev)
4144{
4145 struct igb_adapter *adapter = netdev_priv(netdev);
4146 struct e1000_hw *hw = &adapter->hw;
4147 unsigned int vfn = adapter->vfs_allocated_count;
16903caa 4148 u32 rctl = 0, vmolr = 0;
68d480c4
AD		 4149 int count;
4150
4151 /* Check for Promiscuous and All Multicast modes */
68d480c4 4152 if (netdev->flags & IFF_PROMISC) {
16903caa 4153 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
bf456abb
AD		 4154 vmolr |= E1000_VMOLR_MPME;
4155
4156 /* enable use of UTA filter to force packets to default pool */
4157 if (hw->mac.type == e1000_82576)
4158 vmolr |= E1000_VMOLR_ROPE;
68d480c4
AD		 4159 } else {
4160 if (netdev->flags & IFF_ALLMULTI) {
4161 rctl |= E1000_RCTL_MPE;
4162 vmolr |= E1000_VMOLR_MPME;
4163 } else {
b980ac18 4164 /* Write addresses to the MTA, if the attempt fails
25985edc 4165 * then we should just turn on promiscuous mode so
68d480c4
AD		 4166 * that we can at least receive multicast traffic
4167 */
4168 count = igb_write_mc_addr_list(netdev);
4169 if (count < 0) {
4170 rctl |= E1000_RCTL_MPE;
4171 vmolr |= E1000_VMOLR_MPME;
4172 } else if (count) {
4173 vmolr |= E1000_VMOLR_ROMPE;
4174 }
4175 }
268f9d33
AD		 4176 }
4177
4178 /* Write addresses to available RAR registers, if there is not
4179 * sufficient space to store all the addresses then enable
4180 * unicast promiscuous mode
4181 */
4182 count = igb_write_uc_addr_list(netdev);
4183 if (count < 0) {
4184 rctl |= E1000_RCTL_UPE;
4185 vmolr |= E1000_VMOLR_ROPE;
28fc06f5 4186 }
16903caa
AD		 4187
4188 /* enable VLAN filtering by default */
4189 rctl |= E1000_RCTL_VFE;
4190
4191 /* disable VLAN filtering for modes that require it */
4192 if ((netdev->flags & IFF_PROMISC) ||
4193 (netdev->features & NETIF_F_RXALL)) {
4194 /* if we fail to set all rules then just clear VFE */
4195 if (igb_vlan_promisc_enable(adapter))
4196 rctl &= ~E1000_RCTL_VFE;
4197 } else {
4198 igb_vlan_promisc_disable(adapter);
4199 }
4200
4201 /* update state of unicast, multicast, and VLAN filtering modes */
4202 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4203 E1000_RCTL_VFE);
68d480c4 4204 wr32(E1000_RCTL, rctl);
28fc06f5 4205
b980ac18 4206 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4207 * the VMOLR to enable the appropriate modes. Without this workaround
4208 * we will have issues with VLAN tag stripping not being done for frames
4209 * that are only arriving because we are the default pool
4210 */
f96a8a0b 4211 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4212 return;
9d5c8243 4213
bf456abb
AD		 4214 /* set UTA to appropriate mode */
4215 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4216
68d480c4 4217 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4218 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
45693bcb
AD		 4219
4220 /* enable Rx jumbo frames, no need for restriction */
4221 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4222 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4223
68d480c4 4224 wr32(E1000_VMOLR(vfn), vmolr);
45693bcb
AD		 4225 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4226
28fc06f5 4227 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4228}
4229
13800469
GR		 4230static void igb_check_wvbr(struct igb_adapter *adapter)
4231{
4232 struct e1000_hw *hw = &adapter->hw;
4233 u32 wvbr = 0;
4234
4235 switch (hw->mac.type) {
4236 case e1000_82576:
4237 case e1000_i350:
81ad807b
CW		 4238 wvbr = rd32(E1000_WVBR);
4239 if (!wvbr)
13800469
GR		 4240 return;
4241 break;
4242 default:
4243 break;
4244 }
4245
4246 adapter->wvbr |= wvbr;
4247}
4248
4249#define IGB_STAGGERED_QUEUE_OFFSET 8
4250
4251static void igb_spoof_check(struct igb_adapter *adapter)
4252{
4253 int j;
4254
4255 if (!adapter->wvbr)
4256 return;
4257
9005df38 4258 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4259 if (adapter->wvbr & (1 << j) ||
4260 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4261 dev_warn(&adapter->pdev->dev,
4262 "Spoof event(s) detected on VF %d\n", j);
4263 adapter->wvbr &=
4264 ~((1 << j) |
4265 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4266 }
4267 }
4268}
4269
9d5c8243 4270/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4271 * the phy
4272 */
9d5c8243
AK		 4273static void igb_update_phy_info(unsigned long data)
4274{
4275 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4276 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4277}
4278
4d6b725e 4279/**
b980ac18
JK		 4280 * igb_has_link - check shared code for link and determine up/down
4281 * @adapter: pointer to driver private info
4d6b725e 4282 **/
3145535a 4283bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4284{
4285 struct e1000_hw *hw = &adapter->hw;
4286 bool link_active = false;
4d6b725e
AD		 4287
4288 /* get_link_status is set on LSC (link status) interrupt or
4289 * rx sequence error interrupt. get_link_status will stay
4290 * false until the e1000_check_for_link establishes link
4291 * for copper adapters ONLY
4292 */
4293 switch (hw->phy.media_type) {
4294 case e1000_media_type_copper:
e5c3370f
AA		 4295 if (!hw->mac.get_link_status)
4296 return true;
4d6b725e 4297 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4298 hw->mac.ops.check_for_link(hw);
4299 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4300 break;
4301 default:
4302 case e1000_media_type_unknown:
4303 break;
4304 }
4305
aa9b8cc4
AA		 4306 if (((hw->mac.type == e1000_i210) ||
4307 (hw->mac.type == e1000_i211)) &&
4308 (hw->phy.id == I210_I_PHY_ID)) {
4309 if (!netif_carrier_ok(adapter->netdev)) {
4310 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4311 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4312 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4313 adapter->link_check_timeout = jiffies;
4314 }
4315 }
4316
4d6b725e
AD		 4317 return link_active;
4318}
4319
563988dc
SA		 4320static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4321{
4322 bool ret = false;
4323 u32 ctrl_ext, thstat;
4324
f96a8a0b 4325 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4326 if (hw->mac.type == e1000_i350) {
4327 thstat = rd32(E1000_THSTAT);
4328 ctrl_ext = rd32(E1000_CTRL_EXT);
4329
4330 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4331 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4332 ret = !!(thstat & event);
563988dc
SA		 4333 }
4334
4335 return ret;
4336}
4337
1516f0a6
CW		 4338/**
4339 * igb_check_lvmmc - check for malformed packets received
4340 * and indicated in LVMMC register
4341 * @adapter: pointer to adapter
4342 **/
4343static void igb_check_lvmmc(struct igb_adapter *adapter)
4344{
4345 struct e1000_hw *hw = &adapter->hw;
4346 u32 lvmmc;
4347
4348 lvmmc = rd32(E1000_LVMMC);
4349 if (lvmmc) {
4350 if (unlikely(net_ratelimit())) {
4351 netdev_warn(adapter->netdev,
4352 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4353 lvmmc);
4354 }
4355 }
4356}
4357
9d5c8243 4358/**
b980ac18
JK		 4359 * igb_watchdog - Timer Call-back
4360 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4361 **/
4362static void igb_watchdog(unsigned long data)
4363{
4364 struct igb_adapter *adapter = (struct igb_adapter *)data;
4365 /* Do the rest outside of interrupt context */
4366 schedule_work(&adapter->watchdog_task);
4367}
4368
4369static void igb_watchdog_task(struct work_struct *work)
4370{
4371 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4372 struct igb_adapter,
4373 watchdog_task);
9d5c8243 4374 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4375 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4376 struct net_device *netdev = adapter->netdev;
563988dc 4377 u32 link;
7a6ea550 4378 int i;
56cec249 4379 u32 connsw;
b72f3f72 4380 u16 phy_data, retry_count = 20;
9d5c8243 4381
4d6b725e 4382 link = igb_has_link(adapter);
aa9b8cc4
AA		 4383
4384 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4385 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4386 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4387 else
4388 link = false;
4389 }
4390
56cec249
CW		 4391 /* Force link down if we have fiber to swap to */
4392 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4393 if (hw->phy.media_type == e1000_media_type_copper) {
4394 connsw = rd32(E1000_CONNSW);
4395 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4396 link = 0;
4397 }
4398 }
9d5c8243 4399 if (link) {
2bdfc4e2
CW		 4400 /* Perform a reset if the media type changed. */
4401 if (hw->dev_spec._82575.media_changed) {
4402 hw->dev_spec._82575.media_changed = false;
4403 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4404 igb_reset(adapter);
4405 }
749ab2cd
YZ		 4406 /* Cancel scheduled suspend requests. */
4407 pm_runtime_resume(netdev->dev.parent);
4408
9d5c8243
AK		 4409 if (!netif_carrier_ok(netdev)) {
4410 u32 ctrl;
9005df38 4411
330a6d6a 4412 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4413 &adapter->link_speed,
4414 &adapter->link_duplex);
9d5c8243
AK		 4415
4416 ctrl = rd32(E1000_CTRL);
527d47c1 4417 /* Links status message must follow this format */
c75c4edf
CW		 4418 netdev_info(netdev,
4419 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4420 netdev->name,
4421 adapter->link_speed,
4422 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4423 "Full" : "Half",
4424 (ctrl & E1000_CTRL_TFCE) &&
4425 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4426 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4427 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4428
f4c01e96
CW		 4429 /* disable EEE if enabled */
4430 if ((adapter->flags & IGB_FLAG_EEE) &&
4431 (adapter->link_duplex == HALF_DUPLEX)) {
4432 dev_info(&adapter->pdev->dev,
4433 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4434 adapter->hw.dev_spec._82575.eee_disable = true;
4435 adapter->flags &= ~IGB_FLAG_EEE;
4436 }
4437
c0ba4778
KS		 4438 /* check if SmartSpeed worked */
4439 igb_check_downshift(hw);
4440 if (phy->speed_downgraded)
4441 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4442
563988dc 4443 /* check for thermal sensor event */
876d2d6f 4444 if (igb_thermal_sensor_event(hw,
d34a15ab 4445 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4446 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4447
d07f3e37 4448 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4449 adapter->tx_timeout_factor = 1;
4450 switch (adapter->link_speed) {
4451 case SPEED_10:
9d5c8243
AK		 4452 adapter->tx_timeout_factor = 14;
4453 break;
4454 case SPEED_100:
9d5c8243
AK		 4455 /* maybe add some timeout factor ? */
4456 break;
4457 }
4458
b72f3f72
TU		 4459 if (adapter->link_speed != SPEED_1000)
4460 goto no_wait;
4461
4462 /* wait for Remote receiver status OK */
4463retry_read_status:
4464 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
4465 &phy_data)) {
4466 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4467 retry_count) {
4468 msleep(100);
4469 retry_count--;
4470 goto retry_read_status;
4471 } else if (!retry_count) {
4472 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
4473 }
4474 } else {
4475 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
4476 }
4477no_wait:
9d5c8243 4478 netif_carrier_on(netdev);
9d5c8243 4479
4ae196df 4480 igb_ping_all_vfs(adapter);
17dc566c 4481 igb_check_vf_rate_limit(adapter);
4ae196df 4482
4b1a9877 4483 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4484 if (!test_bit(__IGB_DOWN, &adapter->state))
4485 mod_timer(&adapter->phy_info_timer,
4486 round_jiffies(jiffies + 2 * HZ));
4487 }
4488 } else {
4489 if (netif_carrier_ok(netdev)) {
4490 adapter->link_speed = 0;
4491 adapter->link_duplex = 0;
563988dc
SA		 4492
4493 /* check for thermal sensor event */
876d2d6f
JK		 4494 if (igb_thermal_sensor_event(hw,
4495 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4496 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4497 }
563988dc 4498
527d47c1 4499 /* Links status message must follow this format */
c75c4edf 4500 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4501 netdev->name);
9d5c8243 4502 netif_carrier_off(netdev);
4b1a9877 4503
4ae196df
AD		 4504 igb_ping_all_vfs(adapter);
4505
4b1a9877 4506 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4507 if (!test_bit(__IGB_DOWN, &adapter->state))
4508 mod_timer(&adapter->phy_info_timer,
4509 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4510
56cec249
CW		 4511 /* link is down, time to check for alternate media */
4512 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4513 igb_check_swap_media(adapter);
4514 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4515 schedule_work(&adapter->reset_task);
4516 /* return immediately */
4517 return;
4518 }
4519 }
749ab2cd
YZ		 4520 pm_schedule_suspend(netdev->dev.parent,
4521 MSEC_PER_SEC * 5);
56cec249
CW		 4522
4523 /* also check for alternate media here */
4524 } else if (!netif_carrier_ok(netdev) &&
4525 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4526 igb_check_swap_media(adapter);
4527 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4528 schedule_work(&adapter->reset_task);
4529 /* return immediately */
4530 return;
4531 }
9d5c8243
AK		 4532 }
4533 }
4534
12dcd86b
ED		 4535 spin_lock(&adapter->stats64_lock);
4536 igb_update_stats(adapter, &adapter->stats64);
4537 spin_unlock(&adapter->stats64_lock);
9d5c8243 4538
dbabb065 4539 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4540 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4541 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4542 /* We've lost link, so the controller stops DMA,
4543 * but we've got queued Tx work that's never going
4544 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4545 * (Do the reset outside of interrupt context).
4546 */
dbabb065
AD		 4547 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4548 adapter->tx_timeout_count++;
4549 schedule_work(&adapter->reset_task);
4550 /* return immediately since reset is imminent */
4551 return;
4552 }
9d5c8243 4553 }
9d5c8243 4554
dbabb065 4555 /* Force detection of hung controller every watchdog period */
6d095fa8 4556 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4557 }
f7ba205e 4558
b980ac18 4559 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4560 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4561 u32 eics = 0;
9005df38 4562
0d1ae7f4
AD		 4563 for (i = 0; i < adapter->num_q_vectors; i++)
4564 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4565 wr32(E1000_EICS, eics);
4566 } else {
4567 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4568 }
9d5c8243 4569
13800469 4570 igb_spoof_check(adapter);
fc580751 4571 igb_ptp_rx_hang(adapter);
13800469 4572
1516f0a6
CW		 4573 /* Check LVMMC register on i350/i354 only */
4574 if ((adapter->hw.mac.type == e1000_i350) ||
4575 (adapter->hw.mac.type == e1000_i354))
4576 igb_check_lvmmc(adapter);
4577
9d5c8243 4578 /* Reset the timer */
aa9b8cc4
AA		 4579 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4580 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4581 mod_timer(&adapter->watchdog_timer,
4582 round_jiffies(jiffies + HZ));
4583 else
4584 mod_timer(&adapter->watchdog_timer,
4585 round_jiffies(jiffies + 2 * HZ));
4586 }
9d5c8243
AK		 4587}
4588
4589enum latency_range {
4590 lowest_latency = 0,
4591 low_latency = 1,
4592 bulk_latency = 2,
4593 latency_invalid = 255
4594};
4595
6eb5a7f1 4596/**
b980ac18
JK		 4597 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4598 * @q_vector: pointer to q_vector
6eb5a7f1 4599 *
b980ac18
JK		 4600 * Stores a new ITR value based on strictly on packet size. This
4601 * algorithm is less sophisticated than that used in igb_update_itr,
4602 * due to the difficulty of synchronizing statistics across multiple
4603 * receive rings. The divisors and thresholds used by this function
4604 * were determined based on theoretical maximum wire speed and testing
4605 * data, in order to minimize response time while increasing bulk
4606 * throughput.
406d4965 4607 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4608 * NOTE: This function is called only when operating in a multiqueue
4609 * receive environment.
6eb5a7f1 4610 **/
047e0030 4611static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4612{
047e0030 4613 int new_val = q_vector->itr_val;
6eb5a7f1 4614 int avg_wire_size = 0;
047e0030 4615 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4616 unsigned int packets;
9d5c8243 4617
6eb5a7f1
AD		 4618 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4619 * ints/sec - ITR timer value of 120 ticks.
4620 */
4621 if (adapter->link_speed != SPEED_1000) {
0ba82994 4622 new_val = IGB_4K_ITR;
6eb5a7f1 4623 goto set_itr_val;
9d5c8243 4624 }
047e0030 4625
0ba82994
AD		 4626 packets = q_vector->rx.total_packets;
4627 if (packets)
4628 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4629
0ba82994
AD		 4630 packets = q_vector->tx.total_packets;
4631 if (packets)
4632 avg_wire_size = max_t(u32, avg_wire_size,
4633 q_vector->tx.total_bytes / packets);
047e0030
AD		 4634
4635 /* if avg_wire_size isn't set no work was done */
4636 if (!avg_wire_size)
4637 goto clear_counts;
9d5c8243 4638
6eb5a7f1
AD		 4639 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4640 avg_wire_size += 24;
4641
4642 /* Don't starve jumbo frames */
4643 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4644
6eb5a7f1
AD		 4645 /* Give a little boost to mid-size frames */
4646 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4647 new_val = avg_wire_size / 3;
4648 else
4649 new_val = avg_wire_size / 2;
9d5c8243 4650
0ba82994
AD		 4651 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4652 if (new_val < IGB_20K_ITR &&
4653 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4654 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4655 new_val = IGB_20K_ITR;
abe1c363 4656
6eb5a7f1 4657set_itr_val:
047e0030
AD		 4658 if (new_val != q_vector->itr_val) {
4659 q_vector->itr_val = new_val;
4660 q_vector->set_itr = 1;
9d5c8243 4661 }
6eb5a7f1 4662clear_counts:
0ba82994
AD		 4663 q_vector->rx.total_bytes = 0;
4664 q_vector->rx.total_packets = 0;
4665 q_vector->tx.total_bytes = 0;
4666 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4667}
4668
4669/**
b980ac18
JK		 4670 * igb_update_itr - update the dynamic ITR value based on statistics
4671 * @q_vector: pointer to q_vector
4672 * @ring_container: ring info to update the itr for
4673 *
4674 * Stores a new ITR value based on packets and byte
4675 * counts during the last interrupt. The advantage of per interrupt
4676 * computation is faster updates and more accurate ITR for the current
4677 * traffic pattern. Constants in this function were computed
4678 * based on theoretical maximum wire speed and thresholds were set based
4679 * on testing data as well as attempting to minimize response time
4680 * while increasing bulk throughput.
406d4965 4681 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4682 * NOTE: These calculations are only valid when operating in a single-
4683 * queue environment.
9d5c8243 4684 **/
0ba82994
AD		 4685static void igb_update_itr(struct igb_q_vector *q_vector,
4686 struct igb_ring_container *ring_container)
9d5c8243 4687{
0ba82994
AD		 4688 unsigned int packets = ring_container->total_packets;
4689 unsigned int bytes = ring_container->total_bytes;
4690 u8 itrval = ring_container->itr;
9d5c8243 4691
0ba82994 4692 /* no packets, exit with status unchanged */
9d5c8243 4693 if (packets == 0)
0ba82994 4694 return;
9d5c8243 4695
0ba82994 4696 switch (itrval) {
9d5c8243
AK		 4697 case lowest_latency:
4698 /* handle TSO and jumbo frames */
4699 if (bytes/packets > 8000)
0ba82994 4700 itrval = bulk_latency;
9d5c8243 4701 else if ((packets < 5) && (bytes > 512))
0ba82994 4702 itrval = low_latency;
9d5c8243
AK		 4703 break;
4704 case low_latency: /* 50 usec aka 20000 ints/s */
4705 if (bytes > 10000) {
4706 /* this if handles the TSO accounting */
d34a15ab 4707 if (bytes/packets > 8000)
0ba82994 4708 itrval = bulk_latency;
d34a15ab 4709 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4710 itrval = bulk_latency;
d34a15ab 4711 else if ((packets > 35))
0ba82994 4712 itrval = lowest_latency;
9d5c8243 4713 } else if (bytes/packets > 2000) {
0ba82994 4714 itrval = bulk_latency;
9d5c8243 4715 } else if (packets <= 2 && bytes < 512) {
0ba82994 4716 itrval = lowest_latency;
9d5c8243
AK		 4717 }
4718 break;
4719 case bulk_latency: /* 250 usec aka 4000 ints/s */
4720 if (bytes > 25000) {
4721 if (packets > 35)
0ba82994 4722 itrval = low_latency;
1e5c3d21 4723 } else if (bytes < 1500) {
0ba82994 4724 itrval = low_latency;
9d5c8243
AK		 4725 }
4726 break;
4727 }
4728
0ba82994
AD		 4729 /* clear work counters since we have the values we need */
4730 ring_container->total_bytes = 0;
4731 ring_container->total_packets = 0;
4732
4733 /* write updated itr to ring container */
4734 ring_container->itr = itrval;
9d5c8243
AK		 4735}
4736
0ba82994 4737static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4738{
0ba82994 4739 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4740 u32 new_itr = q_vector->itr_val;
0ba82994 4741 u8 current_itr = 0;
9d5c8243
AK		 4742
4743 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4744 if (adapter->link_speed != SPEED_1000) {
4745 current_itr = 0;
0ba82994 4746 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4747 goto set_itr_now;
4748 }
4749
0ba82994
AD		 4750 igb_update_itr(q_vector, &q_vector->tx);
4751 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4752
0ba82994 4753 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4754
6eb5a7f1 4755 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4756 if (current_itr == lowest_latency &&
4757 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4758 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4759 current_itr = low_latency;
4760
9d5c8243
AK		 4761 switch (current_itr) {
4762 /* counts and packets in update_itr are dependent on these numbers */
4763 case lowest_latency:
0ba82994 4764 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4765 break;
4766 case low_latency:
0ba82994 4767 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4768 break;
4769 case bulk_latency:
0ba82994 4770 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4771 break;
4772 default:
4773 break;
4774 }
4775
4776set_itr_now:
047e0030 4777 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4778 /* this attempts to bias the interrupt rate towards Bulk
4779 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4780 * increasing
4781 */
047e0030 4782 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4783 max((new_itr * q_vector->itr_val) /
4784 (new_itr + (q_vector->itr_val >> 2)),
4785 new_itr) : new_itr;
9d5c8243
AK		 4786 /* Don't write the value here; it resets the adapter's
4787 * internal timer, and causes us to delay far longer than
4788 * we should between interrupts. Instead, we write the ITR
4789 * value at the beginning of the next interrupt so the timing
4790 * ends up being correct.
4791 */
047e0030
AD		 4792 q_vector->itr_val = new_itr;
4793 q_vector->set_itr = 1;
9d5c8243 4794 }
9d5c8243
AK		 4795}
4796
c50b52a0
SH		 4797static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4798 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4799{
4800 struct e1000_adv_tx_context_desc *context_desc;
4801 u16 i = tx_ring->next_to_use;
4802
4803 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4804
4805 i++;
4806 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4807
4808 /* set bits to identify this as an advanced context descriptor */
4809 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4810
4811 /* For 82575, context index must be unique per ring. */
866cff06 4812 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4813 mss_l4len_idx |= tx_ring->reg_idx << 4;
4814
4815 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4816 context_desc->seqnum_seed = 0;
4817 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4818 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4819}
4820
7af40ad9
AD		 4821static int igb_tso(struct igb_ring *tx_ring,
4822 struct igb_tx_buffer *first,
4823 u8 *hdr_len)
9d5c8243 4824{
7af40ad9 4825 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4826 u32 vlan_macip_lens, type_tucmd;
4827 u32 mss_l4len_idx, l4len;
06c14e5a 4828 int err;
7d13a7d0 4829
ed6aa105
AD		 4830 if (skb->ip_summed != CHECKSUM_PARTIAL)
4831 return 0;
4832
7d13a7d0
AD		 4833 if (!skb_is_gso(skb))
4834 return 0;
9d5c8243 4835
06c14e5a
FR		 4836 err = skb_cow_head(skb, 0);
4837 if (err < 0)
4838 return err;
9d5c8243 4839
7d13a7d0
AD		 4840 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4841 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4842
7c4d16ff 4843 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4844 struct iphdr *iph = ip_hdr(skb);
4845 iph->tot_len = 0;
4846 iph->check = 0;
4847 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4848 iph->daddr, 0,
4849 IPPROTO_TCP,
4850 0);
7d13a7d0 4851 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4852 first->tx_flags |= IGB_TX_FLAGS_TSO |
4853 IGB_TX_FLAGS_CSUM |
4854 IGB_TX_FLAGS_IPV4;
8e1e8a47 4855 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4856 ipv6_hdr(skb)->payload_len = 0;
4857 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4858 &ipv6_hdr(skb)->daddr,
4859 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4860 first->tx_flags |= IGB_TX_FLAGS_TSO |
4861 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4862 }
4863
7af40ad9 4864 /* compute header lengths */
7d13a7d0
AD		 4865 l4len = tcp_hdrlen(skb);
4866 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4867
7af40ad9
AD		 4868 /* update gso size and bytecount with header size */
4869 first->gso_segs = skb_shinfo(skb)->gso_segs;
4870 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4871
9d5c8243 4872 /* MSS L4LEN IDX */
7d13a7d0
AD		 4873 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4874 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4875
7d13a7d0
AD		 4876 /* VLAN MACLEN IPLEN */
4877 vlan_macip_lens = skb_network_header_len(skb);
4878 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4879 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4880
7d13a7d0 4881 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4882
7d13a7d0 4883 return 1;
9d5c8243
AK		 4884}
4885
7af40ad9 4886static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4887{
7af40ad9 4888 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4889 u32 vlan_macip_lens = 0;
4890 u32 mss_l4len_idx = 0;
4891 u32 type_tucmd = 0;
9d5c8243 4892
7d13a7d0 4893 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4894 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4895 return;
7d13a7d0
AD		 4896 } else {
4897 u8 l4_hdr = 0;
9005df38 4898
7af40ad9 4899 switch (first->protocol) {
7c4d16ff 4900 case htons(ETH_P_IP):
7d13a7d0
AD		 4901 vlan_macip_lens |= skb_network_header_len(skb);
4902 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4903 l4_hdr = ip_hdr(skb)->protocol;
4904 break;
7c4d16ff 4905 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4906 vlan_macip_lens |= skb_network_header_len(skb);
4907 l4_hdr = ipv6_hdr(skb)->nexthdr;
4908 break;
4909 default:
4910 if (unlikely(net_ratelimit())) {
4911 dev_warn(tx_ring->dev,
b980ac18
JK		 4912 "partial checksum but proto=%x!\n",
4913 first->protocol);
fa4a7ef3 4914 }
7d13a7d0
AD		 4915 break;
4916 }
fa4a7ef3 4917
7d13a7d0
AD		 4918 switch (l4_hdr) {
4919 case IPPROTO_TCP:
4920 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4921 mss_l4len_idx = tcp_hdrlen(skb) <<
4922 E1000_ADVTXD_L4LEN_SHIFT;
4923 break;
4924 case IPPROTO_SCTP:
4925 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4926 mss_l4len_idx = sizeof(struct sctphdr) <<
4927 E1000_ADVTXD_L4LEN_SHIFT;
4928 break;
4929 case IPPROTO_UDP:
4930 mss_l4len_idx = sizeof(struct udphdr) <<
4931 E1000_ADVTXD_L4LEN_SHIFT;
4932 break;
4933 default:
4934 if (unlikely(net_ratelimit())) {
4935 dev_warn(tx_ring->dev,
b980ac18
JK		 4936 "partial checksum but l4 proto=%x!\n",
4937 l4_hdr);
44b0cda3 4938 }
7d13a7d0 4939 break;
9d5c8243 4940 }
7af40ad9
AD		 4941
4942 /* update TX checksum flag */
4943 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4944 }
9d5c8243 4945
7d13a7d0 4946 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4947 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4948
7d13a7d0 4949 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4950}
4951
1d9daf45
AD		 4952#define IGB_SET_FLAG(_input, _flag, _result) \
4953 ((_flag <= _result) ? \
4954 ((u32)(_input & _flag) * (_result / _flag)) : \
4955 ((u32)(_input & _flag) / (_flag / _result)))
4956
4957static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4958{
4959 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4960 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4961 E1000_ADVTXD_DCMD_DEXT |
4962 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4963
4964 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4965 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4966 (E1000_ADVTXD_DCMD_VLE));
4967
4968 /* set segmentation bits for TSO */
4969 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4970 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4971
4972 /* set timestamp bit if present */
1d9daf45
AD		 4973 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4974 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4975
1d9daf45
AD		 4976 /* insert frame checksum */
4977 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4978
4979 return cmd_type;
4980}
4981
7af40ad9
AD		 4982static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4983 union e1000_adv_tx_desc *tx_desc,
4984 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4985{
4986 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4987
1d9daf45
AD		 4988 /* 82575 requires a unique index per ring */
4989 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4990 olinfo_status |= tx_ring->reg_idx << 4;
4991
4992 /* insert L4 checksum */
1d9daf45
AD		 4993 olinfo_status |= IGB_SET_FLAG(tx_flags,
4994 IGB_TX_FLAGS_CSUM,
4995 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4996
1d9daf45
AD		 4997 /* insert IPv4 checksum */
4998 olinfo_status |= IGB_SET_FLAG(tx_flags,
4999 IGB_TX_FLAGS_IPV4,
5000 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 5001
7af40ad9 5002 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 5003}
5004
6f19e12f
DM		 5005static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5006{
5007 struct net_device *netdev = tx_ring->netdev;
5008
5009 netif_stop_subqueue(netdev, tx_ring->queue_index);
5010
5011 /* Herbert's original patch had:
5012 * smp_mb__after_netif_stop_queue();
5013 * but since that doesn't exist yet, just open code it.
5014 */
5015 smp_mb();
5016
5017 /* We need to check again in a case another CPU has just
5018 * made room available.
5019 */
5020 if (igb_desc_unused(tx_ring) < size)
5021 return -EBUSY;
5022
5023 /* A reprieve! */
5024 netif_wake_subqueue(netdev, tx_ring->queue_index);
5025
5026 u64_stats_update_begin(&tx_ring->tx_syncp2);
5027 tx_ring->tx_stats.restart_queue2++;
5028 u64_stats_update_end(&tx_ring->tx_syncp2);
5029
5030 return 0;
5031}
5032
5033static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5034{
5035 if (igb_desc_unused(tx_ring) >= size)
5036 return 0;
5037 return __igb_maybe_stop_tx(tx_ring, size);
5038}
5039
7af40ad9
AD		 5040static void igb_tx_map(struct igb_ring *tx_ring,
5041 struct igb_tx_buffer *first,
ebe42d16 5042 const u8 hdr_len)
9d5c8243 5043{
7af40ad9 5044 struct sk_buff *skb = first->skb;
c9f14bf3 5045 struct igb_tx_buffer *tx_buffer;
ebe42d16 5046 union e1000_adv_tx_desc *tx_desc;
80d0759e 5047 struct skb_frag_struct *frag;
ebe42d16 5048 dma_addr_t dma;
80d0759e 5049 unsigned int data_len, size;
7af40ad9 5050 u32 tx_flags = first->tx_flags;
1d9daf45 5051 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 5052 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 5053
5054 tx_desc = IGB_TX_DESC(tx_ring, i);
5055
80d0759e
AD		 5056 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5057
5058 size = skb_headlen(skb);
5059 data_len = skb->data_len;
ebe42d16
AD		 5060
5061 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 5062
80d0759e
AD		 5063 tx_buffer = first;
5064
5065 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5066 if (dma_mapping_error(tx_ring->dev, dma))
5067 goto dma_error;
5068
5069 /* record length, and DMA address */
5070 dma_unmap_len_set(tx_buffer, len, size);
5071 dma_unmap_addr_set(tx_buffer, dma, dma);
5072
5073 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 5074
ebe42d16
AD		 5075 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5076 tx_desc->read.cmd_type_len =
1d9daf45 5077 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 5078
5079 i++;
5080 tx_desc++;
5081 if (i == tx_ring->count) {
5082 tx_desc = IGB_TX_DESC(tx_ring, 0);
5083 i = 0;
5084 }
80d0759e 5085 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 5086
5087 dma += IGB_MAX_DATA_PER_TXD;
5088 size -= IGB_MAX_DATA_PER_TXD;
5089
ebe42d16
AD		 5090 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5091 }
5092
5093 if (likely(!data_len))
5094 break;
2bbfebe2 5095
1d9daf45 5096 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 5097
65689fef 5098 i++;
ebe42d16
AD		 5099 tx_desc++;
5100 if (i == tx_ring->count) {
5101 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 5102 i = 0;
ebe42d16 5103 }
80d0759e 5104 tx_desc->read.olinfo_status = 0;
65689fef 5105
9e903e08 5106 size = skb_frag_size(frag);
ebe42d16
AD		 5107 data_len -= size;
5108
5109 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 5110 size, DMA_TO_DEVICE);
6366ad33 5111
c9f14bf3 5112 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 5113 }
5114
ebe42d16 5115 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 5116 cmd_type |= size | IGB_TXD_DCMD;
5117 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 5118
80d0759e
AD		 5119 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5120
8542db05
AD		 5121 /* set the timestamp */
5122 first->time_stamp = jiffies;
5123
b980ac18 5124 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 5125 * are new descriptors to fetch. (Only applicable for weak-ordered
5126 * memory model archs, such as IA-64).
5127 *
5128 * We also need this memory barrier to make certain all of the
5129 * status bits have been updated before next_to_watch is written.
5130 */
5131 wmb();
5132
8542db05 5133 /* set next_to_watch value indicating a packet is present */
ebe42d16 5134 first->next_to_watch = tx_desc;
9d5c8243 5135
ebe42d16
AD		 5136 i++;
5137 if (i == tx_ring->count)
5138 i = 0;
6366ad33 5139
ebe42d16 5140 tx_ring->next_to_use = i;
6366ad33 5141
6f19e12f
DM		 5142 /* Make sure there is space in the ring for the next send. */
5143 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5144
5145 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 5146 writel(i, tx_ring->tail);
5147
5148 /* we need this if more than one processor can write to our tail
5149 * at a time, it synchronizes IO on IA64/Altix systems
5150 */
5151 mmiowb();
5152 }
ebe42d16
AD		 5153 return;
5154
5155dma_error:
5156 dev_err(tx_ring->dev, "TX DMA map failed\n");
5157
5158 /* clear dma mappings for failed tx_buffer_info map */
5159 for (;;) {
c9f14bf3
AD		 5160 tx_buffer = &tx_ring->tx_buffer_info[i];
5161 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5162 if (tx_buffer == first)
ebe42d16 5163 break;
a77ff709
NN		 5164 if (i == 0)
5165 i = tx_ring->count;
6366ad33 5166 i--;
6366ad33
AD		 5167 }
5168
9d5c8243 5169 tx_ring->next_to_use = i;
9d5c8243
AK		 5170}
5171
cd392f5c
AD		 5172netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5173 struct igb_ring *tx_ring)
9d5c8243 5174{
8542db05 5175 struct igb_tx_buffer *first;
ebe42d16 5176 int tso;
91d4ee33 5177 u32 tx_flags = 0;
2ee52ad4 5178 unsigned short f;
21ba6fe1 5179 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5180 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5181 u8 hdr_len = 0;
9d5c8243 5182
21ba6fe1
AD		 5183 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5184 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5185 * + 2 desc gap to keep tail from touching head,
9d5c8243 5186 * + 1 desc for context descriptor,
21ba6fe1
AD		 5187 * otherwise try next time
5188 */
2ee52ad4
AD		 5189 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5190 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5191
5192 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5193 /* this is a hard error */
9d5c8243
AK		 5194 return NETDEV_TX_BUSY;
5195 }
33af6bcc 5196
7af40ad9
AD		 5197 /* record the location of the first descriptor for this packet */
5198 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5199 first->skb = skb;
5200 first->bytecount = skb->len;
5201 first->gso_segs = 1;
5202
b646c22e
AD		 5203 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5204 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5205
ed4420a3
JK		 5206 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5207 &adapter->state)) {
b646c22e
AD		 5208 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5209 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5210
5211 adapter->ptp_tx_skb = skb_get(skb);
5212 adapter->ptp_tx_start = jiffies;
5213 if (adapter->hw.mac.type == e1000_82576)
5214 schedule_work(&adapter->ptp_tx_work);
5215 }
33af6bcc 5216 }
9d5c8243 5217
afc835d1
JK		 5218 skb_tx_timestamp(skb);
5219
df8a39de 5220 if (skb_vlan_tag_present(skb)) {
9d5c8243 5221 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5222 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5223 }
5224
7af40ad9
AD		 5225 /* record initial flags and protocol */
5226 first->tx_flags = tx_flags;
5227 first->protocol = protocol;
cdfd01fc 5228
7af40ad9
AD		 5229 tso = igb_tso(tx_ring, first, &hdr_len);
5230 if (tso < 0)
7d13a7d0 5231 goto out_drop;
7af40ad9
AD		 5232 else if (!tso)
5233 igb_tx_csum(tx_ring, first);
9d5c8243 5234
7af40ad9 5235 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5236
9d5c8243 5237 return NETDEV_TX_OK;
7d13a7d0
AD		 5238
5239out_drop:
7af40ad9
AD		 5240 igb_unmap_and_free_tx_resource(tx_ring, first);
5241
7d13a7d0 5242 return NETDEV_TX_OK;
9d5c8243
AK		 5243}
5244
0b725a2c
DM		 5245static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5246 struct sk_buff *skb)
1cc3bd87 5247{
0b725a2c
DM		 5248 unsigned int r_idx = skb->queue_mapping;
5249
1cc3bd87
AD		 5250 if (r_idx >= adapter->num_tx_queues)
5251 r_idx = r_idx % adapter->num_tx_queues;
5252
5253 return adapter->tx_ring[r_idx];
5254}
5255
cd392f5c
AD		 5256static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5257 struct net_device *netdev)
9d5c8243
AK		 5258{
5259 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3 5260
b980ac18 5261 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5262 * in order to meet this minimum size requirement.
5263 */
a94d9e22
AD		 5264 if (skb_put_padto(skb, 17))
5265 return NETDEV_TX_OK;
9d5c8243 5266
1cc3bd87 5267 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5268}
5269
5270/**
b980ac18
JK		 5271 * igb_tx_timeout - Respond to a Tx Hang
5272 * @netdev: network interface device structure
9d5c8243
AK		 5273 **/
5274static void igb_tx_timeout(struct net_device *netdev)
5275{
5276 struct igb_adapter *adapter = netdev_priv(netdev);
5277 struct e1000_hw *hw = &adapter->hw;
5278
5279 /* Do the reset outside of interrupt context */
5280 adapter->tx_timeout_count++;
f7ba205e 5281
06218a8d 5282 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5283 hw->dev_spec._82575.global_device_reset = true;
5284
9d5c8243 5285 schedule_work(&adapter->reset_task);
265de409
AD		 5286 wr32(E1000_EICS,
5287 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5288}
5289
5290static void igb_reset_task(struct work_struct *work)
5291{
5292 struct igb_adapter *adapter;
5293 adapter = container_of(work, struct igb_adapter, reset_task);
5294
c97ec42a
TI		 5295 igb_dump(adapter);
5296 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5297 igb_reinit_locked(adapter);
5298}
5299
5300/**
b980ac18
JK		 5301 * igb_get_stats64 - Get System Network Statistics
5302 * @netdev: network interface device structure
5303 * @stats: rtnl_link_stats64 pointer
9d5c8243 5304 **/
12dcd86b 5305static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5306 struct rtnl_link_stats64 *stats)
9d5c8243 5307{
12dcd86b
ED		 5308 struct igb_adapter *adapter = netdev_priv(netdev);
5309
5310 spin_lock(&adapter->stats64_lock);
5311 igb_update_stats(adapter, &adapter->stats64);
5312 memcpy(stats, &adapter->stats64, sizeof(*stats));
5313 spin_unlock(&adapter->stats64_lock);
5314
5315 return stats;
9d5c8243
AK		 5316}
5317
5318/**
b980ac18
JK		 5319 * igb_change_mtu - Change the Maximum Transfer Unit
5320 * @netdev: network interface device structure
5321 * @new_mtu: new value for maximum frame size
9d5c8243 5322 *
b980ac18 5323 * Returns 0 on success, negative on failure
9d5c8243
AK		 5324 **/
5325static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5326{
5327 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5328 struct pci_dev *pdev = adapter->pdev;
153285f9 5329 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5330
c809d227 5331 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5332 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5333 return -EINVAL;
5334 }
5335
153285f9 5336#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5337 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5338 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5339 return -EINVAL;
5340 }
5341
2ccd994c
AD		 5342 /* adjust max frame to be at least the size of a standard frame */
5343 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5344 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5345
9d5c8243 5346 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5347 usleep_range(1000, 2000);
73cd78f1 5348
9d5c8243
AK		 5349 /* igb_down has a dependency on max_frame_size */
5350 adapter->max_frame_size = max_frame;
559e9c49 5351
4c844851
AD		 5352 if (netif_running(netdev))
5353 igb_down(adapter);
9d5c8243 5354
090b1795 5355 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5356 netdev->mtu, new_mtu);
5357 netdev->mtu = new_mtu;
5358
5359 if (netif_running(netdev))
5360 igb_up(adapter);
5361 else
5362 igb_reset(adapter);
5363
5364 clear_bit(__IGB_RESETTING, &adapter->state);
5365
5366 return 0;
5367}
5368
5369/**
b980ac18
JK		 5370 * igb_update_stats - Update the board statistics counters
5371 * @adapter: board private structure
9d5c8243 5372 **/
12dcd86b
ED		 5373void igb_update_stats(struct igb_adapter *adapter,
5374 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5375{
5376 struct e1000_hw *hw = &adapter->hw;
5377 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5378 u32 reg, mpc;
3f9c0164
AD		 5379 int i;
5380 u64 bytes, packets;
12dcd86b
ED		 5381 unsigned int start;
5382 u64 _bytes, _packets;
9d5c8243 5383
b980ac18 5384 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5385 * connection is down.
5386 */
5387 if (adapter->link_speed == 0)
5388 return;
5389 if (pci_channel_offline(pdev))
5390 return;
5391
3f9c0164
AD		 5392 bytes = 0;
5393 packets = 0;
7f90128e
AA		 5394
5395 rcu_read_lock();
3f9c0164 5396 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5397 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5398 u32 rqdpc = rd32(E1000_RQDPC(i));
5399 if (hw->mac.type >= e1000_i210)
5400 wr32(E1000_RQDPC(i), 0);
12dcd86b 5401
ae1c07a6
AD		 5402 if (rqdpc) {
5403 ring->rx_stats.drops += rqdpc;
5404 net_stats->rx_fifo_errors += rqdpc;
5405 }
12dcd86b
ED		 5406
5407 do {
57a7744e 5408 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5409 _bytes = ring->rx_stats.bytes;
5410 _packets = ring->rx_stats.packets;
57a7744e 5411 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5412 bytes += _bytes;
5413 packets += _packets;
3f9c0164
AD		 5414 }
5415
128e45eb
AD		 5416 net_stats->rx_bytes = bytes;
5417 net_stats->rx_packets = packets;
3f9c0164
AD		 5418
5419 bytes = 0;
5420 packets = 0;
5421 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5422 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5423 do {
57a7744e 5424 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5425 _bytes = ring->tx_stats.bytes;
5426 _packets = ring->tx_stats.packets;
57a7744e 5427 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5428 bytes += _bytes;
5429 packets += _packets;
3f9c0164 5430 }
128e45eb
AD		 5431 net_stats->tx_bytes = bytes;
5432 net_stats->tx_packets = packets;
7f90128e 5433 rcu_read_unlock();
3f9c0164
AD		 5434
5435 /* read stats registers */
9d5c8243
AK		 5436 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5437 adapter->stats.gprc += rd32(E1000_GPRC);
5438 adapter->stats.gorc += rd32(E1000_GORCL);
5439 rd32(E1000_GORCH); /* clear GORCL */
5440 adapter->stats.bprc += rd32(E1000_BPRC);
5441 adapter->stats.mprc += rd32(E1000_MPRC);
5442 adapter->stats.roc += rd32(E1000_ROC);
5443
5444 adapter->stats.prc64 += rd32(E1000_PRC64);
5445 adapter->stats.prc127 += rd32(E1000_PRC127);
5446 adapter->stats.prc255 += rd32(E1000_PRC255);
5447 adapter->stats.prc511 += rd32(E1000_PRC511);
5448 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5449 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5450 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5451 adapter->stats.sec += rd32(E1000_SEC);
5452
fa3d9a6d
MW		 5453 mpc = rd32(E1000_MPC);
5454 adapter->stats.mpc += mpc;
5455 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5456 adapter->stats.scc += rd32(E1000_SCC);
5457 adapter->stats.ecol += rd32(E1000_ECOL);
5458 adapter->stats.mcc += rd32(E1000_MCC);
5459 adapter->stats.latecol += rd32(E1000_LATECOL);
5460 adapter->stats.dc += rd32(E1000_DC);
5461 adapter->stats.rlec += rd32(E1000_RLEC);
5462 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5463 adapter->stats.xontxc += rd32(E1000_XONTXC);
5464 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5465 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5466 adapter->stats.fcruc += rd32(E1000_FCRUC);
5467 adapter->stats.gptc += rd32(E1000_GPTC);
5468 adapter->stats.gotc += rd32(E1000_GOTCL);
5469 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5470 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5471 adapter->stats.ruc += rd32(E1000_RUC);
5472 adapter->stats.rfc += rd32(E1000_RFC);
5473 adapter->stats.rjc += rd32(E1000_RJC);
5474 adapter->stats.tor += rd32(E1000_TORH);
5475 adapter->stats.tot += rd32(E1000_TOTH);
5476 adapter->stats.tpr += rd32(E1000_TPR);
5477
5478 adapter->stats.ptc64 += rd32(E1000_PTC64);
5479 adapter->stats.ptc127 += rd32(E1000_PTC127);
5480 adapter->stats.ptc255 += rd32(E1000_PTC255);
5481 adapter->stats.ptc511 += rd32(E1000_PTC511);
5482 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5483 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5484
5485 adapter->stats.mptc += rd32(E1000_MPTC);
5486 adapter->stats.bptc += rd32(E1000_BPTC);
5487
2d0b0f69
NN		 5488 adapter->stats.tpt += rd32(E1000_TPT);
5489 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5490
5491 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5492 /* read internal phy specific stats */
5493 reg = rd32(E1000_CTRL_EXT);
5494 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5495 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5496
5497 /* this stat has invalid values on i210/i211 */
5498 if ((hw->mac.type != e1000_i210) &&
5499 (hw->mac.type != e1000_i211))
5500 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5501 }
5502
9d5c8243
AK		 5503 adapter->stats.tsctc += rd32(E1000_TSCTC);
5504 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5505
5506 adapter->stats.iac += rd32(E1000_IAC);
5507 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5508 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5509 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5510 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5511 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5512 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5513 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5514 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5515
5516 /* Fill out the OS statistics structure */
128e45eb
AD		 5517 net_stats->multicast = adapter->stats.mprc;
5518 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5519
5520 /* Rx Errors */
5521
5522 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5523 * our own version based on RUC and ROC
5524 */
128e45eb 5525 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5526 adapter->stats.crcerrs + adapter->stats.algnerrc +
5527 adapter->stats.ruc + adapter->stats.roc +
5528 adapter->stats.cexterr;
128e45eb
AD		 5529 net_stats->rx_length_errors = adapter->stats.ruc +
5530 adapter->stats.roc;
5531 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5532 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5533 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5534
5535 /* Tx Errors */
128e45eb
AD		 5536 net_stats->tx_errors = adapter->stats.ecol +
5537 adapter->stats.latecol;
5538 net_stats->tx_aborted_errors = adapter->stats.ecol;
5539 net_stats->tx_window_errors = adapter->stats.latecol;
5540 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5541
5542 /* Tx Dropped needs to be maintained elsewhere */
5543
9d5c8243
AK		 5544 /* Management Stats */
5545 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5546 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5547 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5548
5549 /* OS2BMC Stats */
5550 reg = rd32(E1000_MANC);
5551 if (reg & E1000_MANC_EN_BMC2OS) {
5552 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5553 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5554 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5555 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5556 }
9d5c8243
AK		 5557}
5558
61d7f75f
RC		 5559static void igb_tsync_interrupt(struct igb_adapter *adapter)
5560{
5561 struct e1000_hw *hw = &adapter->hw;
00c65578 5562 struct ptp_clock_event event;
40c9b079 5563 struct timespec64 ts;
720db4ff 5564 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5565
5566 if (tsicr & TSINTR_SYS_WRAP) {
5567 event.type = PTP_CLOCK_PPS;
5568 if (adapter->ptp_caps.pps)
5569 ptp_clock_event(adapter->ptp_clock, &event);
5570 else
5571 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5572 ack |= TSINTR_SYS_WRAP;
5573 }
61d7f75f
RC		 5574
5575 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5576 /* retrieve hardware timestamp */
5577 schedule_work(&adapter->ptp_tx_work);
00c65578 5578 ack |= E1000_TSICR_TXTS;
61d7f75f 5579 }
00c65578 5580
720db4ff
RC		 5581 if (tsicr & TSINTR_TT0) {
5582 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5583 ts = timespec64_add(adapter->perout[0].start,
5584 adapter->perout[0].period);
5585 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5586 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5587 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5588 tsauxc = rd32(E1000_TSAUXC);
5589 tsauxc |= TSAUXC_EN_TT0;
5590 wr32(E1000_TSAUXC, tsauxc);
5591 adapter->perout[0].start = ts;
5592 spin_unlock(&adapter->tmreg_lock);
5593 ack |= TSINTR_TT0;
5594 }
5595
5596 if (tsicr & TSINTR_TT1) {
5597 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5598 ts = timespec64_add(adapter->perout[1].start,
5599 adapter->perout[1].period);
720db4ff 5600 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5601 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5602 tsauxc = rd32(E1000_TSAUXC);
5603 tsauxc |= TSAUXC_EN_TT1;
5604 wr32(E1000_TSAUXC, tsauxc);
5605 adapter->perout[1].start = ts;
5606 spin_unlock(&adapter->tmreg_lock);
5607 ack |= TSINTR_TT1;
5608 }
5609
5610 if (tsicr & TSINTR_AUTT0) {
5611 nsec = rd32(E1000_AUXSTMPL0);
5612 sec = rd32(E1000_AUXSTMPH0);
5613 event.type = PTP_CLOCK_EXTTS;
5614 event.index = 0;
5615 event.timestamp = sec * 1000000000ULL + nsec;
5616 ptp_clock_event(adapter->ptp_clock, &event);
5617 ack |= TSINTR_AUTT0;
5618 }
5619
5620 if (tsicr & TSINTR_AUTT1) {
5621 nsec = rd32(E1000_AUXSTMPL1);
5622 sec = rd32(E1000_AUXSTMPH1);
5623 event.type = PTP_CLOCK_EXTTS;
5624 event.index = 1;
5625 event.timestamp = sec * 1000000000ULL + nsec;
5626 ptp_clock_event(adapter->ptp_clock, &event);
5627 ack |= TSINTR_AUTT1;
5628 }
5629
00c65578
RC		 5630 /* acknowledge the interrupts */
5631 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5632}
5633
9d5c8243
AK		 5634static irqreturn_t igb_msix_other(int irq, void *data)
5635{
047e0030 5636 struct igb_adapter *adapter = data;
9d5c8243 5637 struct e1000_hw *hw = &adapter->hw;
844290e5 5638 u32 icr = rd32(E1000_ICR);
844290e5 5639 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5640
7f081d40
AD		 5641 if (icr & E1000_ICR_DRSTA)
5642 schedule_work(&adapter->reset_task);
5643
047e0030 5644 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5645 /* HW is reporting DMA is out of sync */
5646 adapter->stats.doosync++;
13800469
GR		 5647 /* The DMA Out of Sync is also indication of a spoof event
5648 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5649 * see if it is really a spoof event.
5650 */
13800469 5651 igb_check_wvbr(adapter);
dda0e083 5652 }
eebbbdba 5653
4ae196df
AD		 5654 /* Check for a mailbox event */
5655 if (icr & E1000_ICR_VMMB)
5656 igb_msg_task(adapter);
5657
5658 if (icr & E1000_ICR_LSC) {
5659 hw->mac.get_link_status = 1;
5660 /* guard against interrupt when we're going down */
5661 if (!test_bit(__IGB_DOWN, &adapter->state))
5662 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5663 }
5664
61d7f75f
RC		 5665 if (icr & E1000_ICR_TS)
5666 igb_tsync_interrupt(adapter);
1f6e8178 5667
844290e5 5668 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5669
5670 return IRQ_HANDLED;
5671}
5672
047e0030 5673static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5674{
26b39276 5675 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5676 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5677
047e0030
AD		 5678 if (!q_vector->set_itr)
5679 return;
73cd78f1 5680
047e0030
AD		 5681 if (!itr_val)
5682 itr_val = 0x4;
661086df 5683
26b39276
AD		 5684 if (adapter->hw.mac.type == e1000_82575)
5685 itr_val |= itr_val << 16;
661086df 5686 else
0ba82994 5687 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5688
047e0030
AD		 5689 writel(itr_val, q_vector->itr_register);
5690 q_vector->set_itr = 0;
6eb5a7f1
AD		 5691}
5692
047e0030 5693static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5694{
047e0030 5695 struct igb_q_vector *q_vector = data;
9d5c8243 5696
047e0030
AD		 5697 /* Write the ITR value calculated from the previous interrupt. */
5698 igb_write_itr(q_vector);
9d5c8243 5699
047e0030 5700 napi_schedule(&q_vector->napi);
844290e5 5701
047e0030 5702 return IRQ_HANDLED;
fe4506b6
JC		 5703}
5704
421e02f0 5705#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5706static void igb_update_tx_dca(struct igb_adapter *adapter,
5707 struct igb_ring *tx_ring,
5708 int cpu)
5709{
5710 struct e1000_hw *hw = &adapter->hw;
5711 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5712
5713 if (hw->mac.type != e1000_82575)
5714 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5715
b980ac18 5716 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5717 * DCA is enabled. This is due to a known issue in some chipsets
5718 * which will cause the DCA tag to be cleared.
5719 */
5720 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5721 E1000_DCA_TXCTRL_DATA_RRO_EN |
5722 E1000_DCA_TXCTRL_DESC_DCA_EN;
5723
5724 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5725}
5726
5727static void igb_update_rx_dca(struct igb_adapter *adapter,
5728 struct igb_ring *rx_ring,
5729 int cpu)
5730{
5731 struct e1000_hw *hw = &adapter->hw;
5732 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5733
5734 if (hw->mac.type != e1000_82575)
5735 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5736
b980ac18 5737 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5738 * DCA is enabled. This is due to a known issue in some chipsets
5739 * which will cause the DCA tag to be cleared.
5740 */
5741 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5742 E1000_DCA_RXCTRL_DESC_DCA_EN;
5743
5744 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5745}
5746
047e0030 5747static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5748{
047e0030 5749 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5750 int cpu = get_cpu();
fe4506b6 5751
047e0030
AD		 5752 if (q_vector->cpu == cpu)
5753 goto out_no_update;
5754
6a05004a
AD		 5755 if (q_vector->tx.ring)
5756 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5757
5758 if (q_vector->rx.ring)
5759 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5760
047e0030
AD		 5761 q_vector->cpu = cpu;
5762out_no_update:
fe4506b6
JC		 5763 put_cpu();
5764}
5765
5766static void igb_setup_dca(struct igb_adapter *adapter)
5767{
7e0e99ef 5768 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5769 int i;
5770
7dfc16fa 5771 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5772 return;
5773
7e0e99ef
AD		 5774 /* Always use CB2 mode, difference is masked in the CB driver. */
5775 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5776
047e0030 5777 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5778 adapter->q_vector[i]->cpu = -1;
5779 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5780 }
5781}
5782
5783static int __igb_notify_dca(struct device *dev, void *data)
5784{
5785 struct net_device *netdev = dev_get_drvdata(dev);
5786 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5787 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5788 struct e1000_hw *hw = &adapter->hw;
5789 unsigned long event = *(unsigned long *)data;
5790
5791 switch (event) {
5792 case DCA_PROVIDER_ADD:
5793 /* if already enabled, don't do it again */
7dfc16fa 5794 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5795 break;
fe4506b6 5796 if (dca_add_requester(dev) == 0) {
bbd98fe4 5797 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5798 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5799 igb_setup_dca(adapter);
5800 break;
5801 }
5802 /* Fall Through since DCA is disabled. */
5803 case DCA_PROVIDER_REMOVE:
7dfc16fa 5804 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5805 /* without this a class_device is left
b980ac18
JK		 5806 * hanging around in the sysfs model
5807 */
fe4506b6 5808 dca_remove_requester(dev);
090b1795 5809 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5810 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5811 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5812 }
5813 break;
5814 }
bbd98fe4 5815
fe4506b6 5816 return 0;
9d5c8243
AK		 5817}
5818
fe4506b6 5819static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5820 void *p)
fe4506b6
JC		 5821{
5822 int ret_val;
5823
5824 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5825 __igb_notify_dca);
fe4506b6
JC		 5826
5827 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5828}
421e02f0 5829#endif /* CONFIG_IGB_DCA */
9d5c8243 5830
0224d663
GR		 5831#ifdef CONFIG_PCI_IOV
5832static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5833{
5834 unsigned char mac_addr[ETH_ALEN];
0224d663 5835
5ac6f91d 5836 eth_zero_addr(mac_addr);
0224d663
GR		 5837 igb_set_vf_mac(adapter, vf, mac_addr);
5838
70ea4783
LL		 5839 /* By default spoof check is enabled for all VFs */
5840 adapter->vf_data[vf].spoofchk_enabled = true;
5841
f557147c 5842 return 0;
0224d663
GR		 5843}
5844
0224d663 5845#endif
4ae196df
AD		 5846static void igb_ping_all_vfs(struct igb_adapter *adapter)
5847{
5848 struct e1000_hw *hw = &adapter->hw;
5849 u32 ping;
5850 int i;
5851
5852 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5853 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5854 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5855 ping |= E1000_VT_MSGTYPE_CTS;
5856 igb_write_mbx(hw, &ping, 1, i);
5857 }
5858}
5859
7d5753f0
AD		 5860static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5861{
5862 struct e1000_hw *hw = &adapter->hw;
5863 u32 vmolr = rd32(E1000_VMOLR(vf));
5864 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5865
d85b9004 5866 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5867 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5868 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5869
5870 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5871 vmolr |= E1000_VMOLR_MPME;
d85b9004 5872 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5873 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5874 } else {
b980ac18 5875 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5876 * flag we need to write the hashes to the MTA as this step
5877 * was previously skipped
5878 */
5879 if (vf_data->num_vf_mc_hashes > 30) {
5880 vmolr |= E1000_VMOLR_MPME;
5881 } else if (vf_data->num_vf_mc_hashes) {
5882 int j;
9005df38 5883
7d5753f0
AD		 5884 vmolr |= E1000_VMOLR_ROMPE;
5885 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5886 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5887 }
5888 }
5889
5890 wr32(E1000_VMOLR(vf), vmolr);
5891
5892 /* there are flags left unprocessed, likely not supported */
5893 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5894 return -EINVAL;
5895
5896 return 0;
7d5753f0
AD		 5897}
5898
4ae196df
AD		 5899static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5900 u32 *msgbuf, u32 vf)
5901{
5902 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5903 u16 *hash_list = (u16 *)&msgbuf[1];
5904 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5905 int i;
5906
7d5753f0 5907 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5908 * to this VF for later use to restore when the PF multi cast
5909 * list changes
5910 */
5911 vf_data->num_vf_mc_hashes = n;
5912
7d5753f0
AD		 5913 /* only up to 30 hash values supported */
5914 if (n > 30)
5915 n = 30;
5916
5917 /* store the hashes for later use */
4ae196df 5918 for (i = 0; i < n; i++)
a419aef8 5919 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5920
5921 /* Flush and reset the mta with the new values */
ff41f8dc 5922 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5923
5924 return 0;
5925}
5926
5927static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5928{
5929 struct e1000_hw *hw = &adapter->hw;
5930 struct vf_data_storage *vf_data;
5931 int i, j;
5932
5933 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5934 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5935
7d5753f0
AD		 5936 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5937
4ae196df 5938 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5939
5940 if ((vf_data->num_vf_mc_hashes > 30) ||
5941 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5942 vmolr |= E1000_VMOLR_MPME;
5943 } else if (vf_data->num_vf_mc_hashes) {
5944 vmolr |= E1000_VMOLR_ROMPE;
5945 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5946 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5947 }
5948 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5949 }
5950}
5951
5952static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5953{
5954 struct e1000_hw *hw = &adapter->hw;
16903caa 5955 u32 pool_mask, vlvf_mask, i;
4ae196df 5956
16903caa
AD		 5957 /* create mask for VF and other pools */
5958 pool_mask = E1000_VLVF_POOLSEL_MASK;
5959 vlvf_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5960
5961 /* drop PF from pool bits */
5962 pool_mask &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT +
5963 adapter->vfs_allocated_count));
4ae196df
AD		 5964
5965 /* Find the vlan filter for this id */
16903caa
AD		 5966 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
5967 u32 vlvf = rd32(E1000_VLVF(i));
5968 u32 vfta_mask, vid, vfta;
4ae196df
AD		 5969
5970 /* remove the vf from the pool */
16903caa
AD		 5971 if (!(vlvf & vlvf_mask))
5972 continue;
5973
5974 /* clear out bit from VLVF */
5975 vlvf ^= vlvf_mask;
5976
5977 /* if other pools are present, just remove ourselves */
5978 if (vlvf & pool_mask)
5979 goto update_vlvfb;
5980
5981 /* if PF is present, leave VFTA */
5982 if (vlvf & E1000_VLVF_POOLSEL_MASK)
5983 goto update_vlvf;
4ae196df 5984
16903caa
AD		 5985 vid = vlvf & E1000_VLVF_VLANID_MASK;
5986 vfta_mask = 1 << (vid % 32);
5987
5988 /* clear bit from VFTA */
5989 vfta = adapter->shadow_vfta[vid / 32];
5990 if (vfta & vfta_mask)
5991 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
5992update_vlvf:
5993 /* clear pool selection enable */
5994 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5995 vlvf &= E1000_VLVF_POOLSEL_MASK;
5996 else
5997 vlvf = 0;
5998update_vlvfb:
5999 /* clear pool bits */
6000 wr32(E1000_VLVF(i), vlvf);
4ae196df
AD		 6001 }
6002}
6003
16903caa 6004static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6f3dc319 6005{
16903caa
AD		 6006 u32 vlvf;
6007 int idx;
6f3dc319 6008
16903caa
AD		 6009 /* short cut the special case */
6010 if (vlan == 0)
6011 return 0;
6012
6013 /* Search for the VLAN id in the VLVF entries */
6014 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6015 vlvf = rd32(E1000_VLVF(idx));
6016 if ((vlvf & VLAN_VID_MASK) == vlan)
6f3dc319
GR		 6017 break;
6018 }
6019
16903caa
AD		 6020 return idx;
6021}
6022
6023void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6024{
6025 struct e1000_hw *hw = &adapter->hw;
6026 u32 bits, pf_id;
6027 int idx;
6028
6029 idx = igb_find_vlvf_entry(hw, vid);
6030 if (!idx)
6031 return;
6f3dc319 6032
16903caa
AD		 6033 /* See if any other pools are set for this VLAN filter
6034 * entry other than the PF.
6035 */
6036 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6037 bits = ~(1 << pf_id) & E1000_VLVF_POOLSEL_MASK;
6038 bits &= rd32(E1000_VLVF(idx));
6039
6040 /* Disable the filter so this falls into the default pool. */
6041 if (!bits) {
6042 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6043 wr32(E1000_VLVF(idx), 1 << pf_id);
6044 else
6045 wr32(E1000_VLVF(idx), 0);
6046 }
6f3dc319
GR		 6047}
6048
a15d9259
AD		 6049static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6050 bool add, u32 vf)
4ae196df 6051{
a15d9259 6052 int pf_id = adapter->vfs_allocated_count;
6f3dc319 6053 struct e1000_hw *hw = &adapter->hw;
a15d9259 6054 int err;
4ae196df 6055
a15d9259
AD		 6056 /* If VLAN overlaps with one the PF is currently monitoring make
6057 * sure that we are able to allocate a VLVF entry. This may be
6058 * redundant but it guarantees PF will maintain visibility to
6059 * the VLAN.
6f3dc319 6060 */
16903caa 6061 if (add && test_bit(vid, adapter->active_vlans)) {
a15d9259
AD		 6062 err = igb_vfta_set(hw, vid, pf_id, true, false);
6063 if (err)
6064 return err;
6065 }
6f3dc319 6066
a15d9259 6067 err = igb_vfta_set(hw, vid, vf, add, false);
6f3dc319 6068
16903caa
AD		 6069 if (add && !err)
6070 return err;
6f3dc319 6071
16903caa
AD		 6072 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6073 * we may need to drop the PF pool bit in order to allow us to free
6074 * up the VLVF resources.
6f3dc319 6075 */
16903caa
AD		 6076 if (test_bit(vid, adapter->active_vlans) ||
6077 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6078 igb_update_pf_vlvf(adapter, vid);
6f3dc319 6079
6f3dc319 6080 return err;
4ae196df
AD		 6081}
6082
a15d9259 6083static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4ae196df 6084{
a15d9259
AD		 6085 struct e1000_hw *hw = &adapter->hw;
6086
6087 if (vid)
6088 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6089 else
6090 wr32(E1000_VMVIR(vf), 0);
6091}
6092
6093static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6094 u16 vlan, u8 qos)
6095{
6096 int err;
6097
6098 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6099 if (err)
6100 return err;
6101
6102 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6103 igb_set_vmolr(adapter, vf, !vlan);
6104
6105 /* revoke access to previous VLAN */
6106 if (vlan != adapter->vf_data[vf].pf_vlan)
6107 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6108 false, vf);
6109
6110 adapter->vf_data[vf].pf_vlan = vlan;
6111 adapter->vf_data[vf].pf_qos = qos;
6112 dev_info(&adapter->pdev->dev,
6113 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6114 if (test_bit(__IGB_DOWN, &adapter->state)) {
6115 dev_warn(&adapter->pdev->dev,
6116 "The VF VLAN has been set, but the PF device is not up.\n");
6117 dev_warn(&adapter->pdev->dev,
6118 "Bring the PF device up before attempting to use the VF device.\n");
6119 }
6120
6121 return err;
6122}
4ae196df 6123
a15d9259
AD		 6124static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6125{
6126 /* Restore tagless access via VLAN 0 */
6127 igb_set_vf_vlan(adapter, 0, true, vf);
6128
6129 igb_set_vmvir(adapter, 0, vf);
8151d294 6130 igb_set_vmolr(adapter, vf, true);
4ae196df 6131
a15d9259
AD		 6132 /* Remove any PF assigned VLAN */
6133 if (adapter->vf_data[vf].pf_vlan)
6134 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6135 false, vf);
6136
6137 adapter->vf_data[vf].pf_vlan = 0;
6138 adapter->vf_data[vf].pf_qos = 0;
6139
6140 return 0;
6141}
6142
6143static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6144 int vf, u16 vlan, u8 qos)
6145{
6146 struct igb_adapter *adapter = netdev_priv(netdev);
6147
6148 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6149 return -EINVAL;
6150
6151 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6152 igb_disable_port_vlan(adapter, vf);
6153}
6154
6155static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6156{
6157 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6158 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6159
6160 if (adapter->vf_data[vf].pf_vlan)
6161 return -1;
6162
6163 /* VLAN 0 is a special case, don't allow it to be removed */
6164 if (!vid && !add)
6165 return 0;
6166
6167 return igb_set_vf_vlan(adapter, vid, !!add, vf);
6168}
6169
6170static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6171{
6172 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6173
6174 /* clear flags - except flag that indicates PF has set the MAC */
6175 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6176 vf_data->last_nack = jiffies;
6177
4ae196df
AD		 6178 /* reset vlans for device */
6179 igb_clear_vf_vfta(adapter, vf);
a15d9259
AD		 6180 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6181 igb_set_vmvir(adapter, vf_data->pf_vlan |
6182 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6183 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
4ae196df
AD		 6184
6185 /* reset multicast table array for vf */
6186 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6187
6188 /* Flush and reset the mta with the new values */
ff41f8dc 6189 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6190}
6191
f2ca0dbe
AD		 6192static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6193{
6194 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6195
5ac6f91d 6196 /* clear mac address as we were hotplug removed/added */
8151d294 6197 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6198 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6199
6200 /* process remaining reset events */
6201 igb_vf_reset(adapter, vf);
6202}
6203
6204static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6205{
6206 struct e1000_hw *hw = &adapter->hw;
6207 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6208 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6209 u32 reg, msgbuf[3];
6210 u8 *addr = (u8 *)(&msgbuf[1]);
6211
6212 /* process all the same items cleared in a function level reset */
f2ca0dbe 6213 igb_vf_reset(adapter, vf);
4ae196df
AD		 6214
6215 /* set vf mac address */
26ad9178 6216 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6217
6218 /* enable transmit and receive for vf */
6219 reg = rd32(E1000_VFTE);
6220 wr32(E1000_VFTE, reg | (1 << vf));
6221 reg = rd32(E1000_VFRE);
6222 wr32(E1000_VFRE, reg | (1 << vf));
6223
8fa7e0f7 6224 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6225
6226 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6227 if (!is_zero_ether_addr(vf_mac)) {
6228 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6229 memcpy(addr, vf_mac, ETH_ALEN);
6230 } else {
6231 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6232 }
4ae196df
AD		 6233 igb_write_mbx(hw, msgbuf, 3, vf);
6234}
6235
6236static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6237{
b980ac18 6238 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6239 * starting at the second 32 bit word of the msg array
6240 */
f2ca0dbe
AD		 6241 unsigned char *addr = (char *)&msg[1];
6242 int err = -1;
4ae196df 6243
f2ca0dbe
AD		 6244 if (is_valid_ether_addr(addr))
6245 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6246
f2ca0dbe 6247 return err;
4ae196df
AD		 6248}
6249
6250static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6251{
6252 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6253 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6254 u32 msg = E1000_VT_MSGTYPE_NACK;
6255
6256 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6257 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6258 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6259 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6260 vf_data->last_nack = jiffies;
4ae196df
AD		 6261 }
6262}
6263
f2ca0dbe 6264static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6265{
f2ca0dbe
AD		 6266 struct pci_dev *pdev = adapter->pdev;
6267 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6268 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6269 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6270 s32 retval;
6271
f2ca0dbe 6272 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6273
fef45f4c
AD		 6274 if (retval) {
6275 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6276 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6277 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6278 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6279 return;
6280 goto out;
6281 }
4ae196df
AD		 6282
6283 /* this is a message we already processed, do nothing */
6284 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6285 return;
4ae196df 6286
b980ac18 6287 /* until the vf completes a reset it should not be
4ae196df
AD		 6288 * allowed to start any configuration.
6289 */
4ae196df
AD		 6290 if (msgbuf[0] == E1000_VF_RESET) {
6291 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6292 return;
4ae196df
AD		 6293 }
6294
f2ca0dbe 6295 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6296 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6297 return;
6298 retval = -1;
6299 goto out;
4ae196df
AD		 6300 }
6301
6302 switch ((msgbuf[0] & 0xFFFF)) {
6303 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6304 retval = -EINVAL;
6305 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6306 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6307 else
6308 dev_warn(&pdev->dev,
b980ac18
JK		 6309 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6310 vf);
4ae196df 6311 break;
7d5753f0
AD		 6312 case E1000_VF_SET_PROMISC:
6313 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6314 break;
4ae196df
AD		 6315 case E1000_VF_SET_MULTICAST:
6316 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6317 break;
6318 case E1000_VF_SET_LPE:
6319 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6320 break;
6321 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6322 retval = -1;
6323 if (vf_data->pf_vlan)
6324 dev_warn(&pdev->dev,
b980ac18
JK		 6325 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6326 vf);
8151d294 6327 else
a15d9259 6328 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
4ae196df
AD		 6329 break;
6330 default:
090b1795 6331 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6332 retval = -1;
6333 break;
6334 }
6335
fef45f4c
AD		 6336 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6337out:
4ae196df
AD		 6338 /* notify the VF of the results of what it sent us */
6339 if (retval)
6340 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6341 else
6342 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6343
4ae196df 6344 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6345}
4ae196df 6346
f2ca0dbe
AD		 6347static void igb_msg_task(struct igb_adapter *adapter)
6348{
6349 struct e1000_hw *hw = &adapter->hw;
6350 u32 vf;
6351
6352 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6353 /* process any reset requests */
6354 if (!igb_check_for_rst(hw, vf))
6355 igb_vf_reset_event(adapter, vf);
6356
6357 /* process any messages pending */
6358 if (!igb_check_for_msg(hw, vf))
6359 igb_rcv_msg_from_vf(adapter, vf);
6360
6361 /* process any acks */
6362 if (!igb_check_for_ack(hw, vf))
6363 igb_rcv_ack_from_vf(adapter, vf);
6364 }
4ae196df
AD		 6365}
6366
68d480c4
AD		 6367/**
6368 * igb_set_uta - Set unicast filter table address
6369 * @adapter: board private structure
bf456abb 6370 * @set: boolean indicating if we are setting or clearing bits
68d480c4
AD		 6371 *
6372 * The unicast table address is a register array of 32-bit registers.
6373 * The table is meant to be used in a way similar to how the MTA is used
6374 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6375 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6376 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4 6377 **/
bf456abb 6378static void igb_set_uta(struct igb_adapter *adapter, bool set)
68d480c4
AD		 6379{
6380 struct e1000_hw *hw = &adapter->hw;
bf456abb 6381 u32 uta = set ? ~0 : 0;
68d480c4
AD		 6382 int i;
6383
68d480c4
AD		 6384 /* we only need to do this if VMDq is enabled */
6385 if (!adapter->vfs_allocated_count)
6386 return;
6387
bf456abb
AD		 6388 for (i = hw->mac.uta_reg_count; i--;)
6389 array_wr32(E1000_UTA, i, uta);
68d480c4
AD		 6390}
6391
9d5c8243 6392/**
b980ac18
JK		 6393 * igb_intr_msi - Interrupt Handler
6394 * @irq: interrupt number
6395 * @data: pointer to a network interface device structure
9d5c8243
AK		 6396 **/
6397static irqreturn_t igb_intr_msi(int irq, void *data)
6398{
047e0030
AD		 6399 struct igb_adapter *adapter = data;
6400 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6401 struct e1000_hw *hw = &adapter->hw;
6402 /* read ICR disables interrupts using IAM */
6403 u32 icr = rd32(E1000_ICR);
6404
047e0030 6405 igb_write_itr(q_vector);
9d5c8243 6406
7f081d40
AD		 6407 if (icr & E1000_ICR_DRSTA)
6408 schedule_work(&adapter->reset_task);
6409
047e0030 6410 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6411 /* HW is reporting DMA is out of sync */
6412 adapter->stats.doosync++;
6413 }
6414
9d5c8243
AK		 6415 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6416 hw->mac.get_link_status = 1;
6417 if (!test_bit(__IGB_DOWN, &adapter->state))
6418 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6419 }
6420
61d7f75f
RC		 6421 if (icr & E1000_ICR_TS)
6422 igb_tsync_interrupt(adapter);
1f6e8178 6423
047e0030 6424 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6425
6426 return IRQ_HANDLED;
6427}
6428
6429/**
b980ac18
JK		 6430 * igb_intr - Legacy Interrupt Handler
6431 * @irq: interrupt number
6432 * @data: pointer to a network interface device structure
9d5c8243
AK		 6433 **/
6434static irqreturn_t igb_intr(int irq, void *data)
6435{
047e0030
AD		 6436 struct igb_adapter *adapter = data;
6437 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6438 struct e1000_hw *hw = &adapter->hw;
6439 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6440 * need for the IMC write
6441 */
9d5c8243 6442 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6443
6444 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6445 * not set, then the adapter didn't send an interrupt
6446 */
9d5c8243
AK		 6447 if (!(icr & E1000_ICR_INT_ASSERTED))
6448 return IRQ_NONE;
6449
0ba82994
AD		 6450 igb_write_itr(q_vector);
6451
7f081d40
AD		 6452 if (icr & E1000_ICR_DRSTA)
6453 schedule_work(&adapter->reset_task);
6454
047e0030 6455 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6456 /* HW is reporting DMA is out of sync */
6457 adapter->stats.doosync++;
6458 }
6459
9d5c8243
AK		 6460 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6461 hw->mac.get_link_status = 1;
6462 /* guard against interrupt when we're going down */
6463 if (!test_bit(__IGB_DOWN, &adapter->state))
6464 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6465 }
6466
61d7f75f
RC		 6467 if (icr & E1000_ICR_TS)
6468 igb_tsync_interrupt(adapter);
1f6e8178 6469
047e0030 6470 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6471
6472 return IRQ_HANDLED;
6473}
6474
c50b52a0 6475static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6476{
047e0030 6477 struct igb_adapter *adapter = q_vector->adapter;
46544258 6478 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6479
0ba82994
AD		 6480 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6481 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6482 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6483 igb_set_itr(q_vector);
46544258 6484 else
047e0030 6485 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6486 }
6487
46544258 6488 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6489 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6490 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6491 else
6492 igb_irq_enable(adapter);
6493 }
9d5c8243
AK		 6494}
6495
46544258 6496/**
b980ac18
JK		 6497 * igb_poll - NAPI Rx polling callback
6498 * @napi: napi polling structure
6499 * @budget: count of how many packets we should handle
46544258
AD		 6500 **/
6501static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6502{
047e0030 6503 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6504 struct igb_q_vector,
6505 napi);
16eb8815 6506 bool clean_complete = true;
32b3e08f 6507 int work_done = 0;
9d5c8243 6508
421e02f0 6509#ifdef CONFIG_IGB_DCA
047e0030
AD		 6510 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6511 igb_update_dca(q_vector);
fe4506b6 6512#endif
0ba82994 6513 if (q_vector->tx.ring)
13fde97a 6514 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6515
32b3e08f
JB		 6516 if (q_vector->rx.ring) {
6517 int cleaned = igb_clean_rx_irq(q_vector, budget);
6518
6519 work_done += cleaned;
6520 clean_complete &= (cleaned < budget);
6521 }
047e0030 6522
16eb8815
AD		 6523 /* If all work not completed, return budget and keep polling */
6524 if (!clean_complete)
6525 return budget;
46544258 6526
9d5c8243 6527 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6528 napi_complete_done(napi, work_done);
16eb8815 6529 igb_ring_irq_enable(q_vector);
9d5c8243 6530
16eb8815 6531 return 0;
9d5c8243 6532}
6d8126f9 6533
9d5c8243 6534/**
b980ac18
JK		 6535 * igb_clean_tx_irq - Reclaim resources after transmit completes
6536 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6537 *
b980ac18 6538 * returns true if ring is completely cleaned
9d5c8243 6539 **/
047e0030 6540static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6541{
047e0030 6542 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6543 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6544 struct igb_tx_buffer *tx_buffer;
f4128785 6545 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6546 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6547 unsigned int budget = q_vector->tx.work_limit;
8542db05 6548 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6549
13fde97a
AD		 6550 if (test_bit(__IGB_DOWN, &adapter->state))
6551 return true;
0e014cb1 6552
06034649 6553 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6554 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6555 i -= tx_ring->count;
9d5c8243 6556
f4128785
AD		 6557 do {
6558 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6559
6560 /* if next_to_watch is not set then there is no work pending */
6561 if (!eop_desc)
6562 break;
13fde97a 6563
f4128785 6564 /* prevent any other reads prior to eop_desc */
70d289bc 6565 read_barrier_depends();
f4128785 6566
13fde97a
AD		 6567 /* if DD is not set pending work has not been completed */
6568 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6569 break;
6570
8542db05
AD		 6571 /* clear next_to_watch to prevent false hangs */
6572 tx_buffer->next_to_watch = NULL;
9d5c8243 6573
ebe42d16
AD		 6574 /* update the statistics for this packet */
6575 total_bytes += tx_buffer->bytecount;
6576 total_packets += tx_buffer->gso_segs;
13fde97a 6577
ebe42d16 6578 /* free the skb */
a81fb049 6579 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6580
ebe42d16
AD		 6581 /* unmap skb header data */
6582 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6583 dma_unmap_addr(tx_buffer, dma),
6584 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6585 DMA_TO_DEVICE);
6586
c9f14bf3
AD		 6587 /* clear tx_buffer data */
6588 tx_buffer->skb = NULL;
6589 dma_unmap_len_set(tx_buffer, len, 0);
6590
ebe42d16
AD		 6591 /* clear last DMA location and unmap remaining buffers */
6592 while (tx_desc != eop_desc) {
13fde97a
AD		 6593 tx_buffer++;
6594 tx_desc++;
9d5c8243 6595 i++;
8542db05
AD		 6596 if (unlikely(!i)) {
6597 i -= tx_ring->count;
06034649 6598 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6599 tx_desc = IGB_TX_DESC(tx_ring, 0);
6600 }
ebe42d16
AD		 6601
6602 /* unmap any remaining paged data */
c9f14bf3 6603 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6604 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6605 dma_unmap_addr(tx_buffer, dma),
6606 dma_unmap_len(tx_buffer, len),
ebe42d16 6607 DMA_TO_DEVICE);
c9f14bf3 6608 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6609 }
6610 }
6611
ebe42d16
AD		 6612 /* move us one more past the eop_desc for start of next pkt */
6613 tx_buffer++;
6614 tx_desc++;
6615 i++;
6616 if (unlikely(!i)) {
6617 i -= tx_ring->count;
6618 tx_buffer = tx_ring->tx_buffer_info;
6619 tx_desc = IGB_TX_DESC(tx_ring, 0);
6620 }
f4128785
AD		 6621
6622 /* issue prefetch for next Tx descriptor */
6623 prefetch(tx_desc);
6624
6625 /* update budget accounting */
6626 budget--;
6627 } while (likely(budget));
0e014cb1 6628
bdbc0631
ED		 6629 netdev_tx_completed_queue(txring_txq(tx_ring),
6630 total_packets, total_bytes);
8542db05 6631 i += tx_ring->count;
9d5c8243 6632 tx_ring->next_to_clean = i;
13fde97a
AD		 6633 u64_stats_update_begin(&tx_ring->tx_syncp);
6634 tx_ring->tx_stats.bytes += total_bytes;
6635 tx_ring->tx_stats.packets += total_packets;
6636 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6637 q_vector->tx.total_bytes += total_bytes;
6638 q_vector->tx.total_packets += total_packets;
9d5c8243 6639
6d095fa8 6640 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6641 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6642
9d5c8243 6643 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6644 * check with the clearing of time_stamp and movement of i
6645 */
6d095fa8 6646 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6647 if (tx_buffer->next_to_watch &&
8542db05 6648 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6649 (adapter->tx_timeout_factor * HZ)) &&
6650 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6651
9d5c8243 6652 /* detected Tx unit hang */
59d71989 6653 dev_err(tx_ring->dev,
9d5c8243 6654 "Detected Tx Unit Hang\n"
2d064c06 6655 " Tx Queue <%d>\n"
9d5c8243
AK		 6656 " TDH <%x>\n"
6657 " TDT <%x>\n"
6658 " next_to_use <%x>\n"
6659 " next_to_clean <%x>\n"
9d5c8243
AK		 6660 "buffer_info[next_to_clean]\n"
6661 " time_stamp <%lx>\n"
8542db05 6662 " next_to_watch <%p>\n"
9d5c8243
AK		 6663 " jiffies <%lx>\n"
6664 " desc.status <%x>\n",
2d064c06 6665 tx_ring->queue_index,
238ac817 6666 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6667 readl(tx_ring->tail),
9d5c8243
AK		 6668 tx_ring->next_to_use,
6669 tx_ring->next_to_clean,
8542db05 6670 tx_buffer->time_stamp,
f4128785 6671 tx_buffer->next_to_watch,
9d5c8243 6672 jiffies,
f4128785 6673 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6674 netif_stop_subqueue(tx_ring->netdev,
6675 tx_ring->queue_index);
6676
6677 /* we are about to reset, no point in enabling stuff */
6678 return true;
9d5c8243
AK		 6679 }
6680 }
13fde97a 6681
21ba6fe1 6682#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6683 if (unlikely(total_packets &&
b980ac18
JK		 6684 netif_carrier_ok(tx_ring->netdev) &&
6685 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6686 /* Make sure that anybody stopping the queue after this
6687 * sees the new next_to_clean.
6688 */
6689 smp_mb();
6690 if (__netif_subqueue_stopped(tx_ring->netdev,
6691 tx_ring->queue_index) &&
6692 !(test_bit(__IGB_DOWN, &adapter->state))) {
6693 netif_wake_subqueue(tx_ring->netdev,
6694 tx_ring->queue_index);
6695
6696 u64_stats_update_begin(&tx_ring->tx_syncp);
6697 tx_ring->tx_stats.restart_queue++;
6698 u64_stats_update_end(&tx_ring->tx_syncp);
6699 }
6700 }
6701
6702 return !!budget;
9d5c8243
AK		 6703}
6704
cbc8e55f 6705/**
b980ac18
JK		 6706 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6707 * @rx_ring: rx descriptor ring to store buffers on
6708 * @old_buff: donor buffer to have page reused
cbc8e55f 6709 *
b980ac18 6710 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6711 **/
6712static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6713 struct igb_rx_buffer *old_buff)
6714{
6715 struct igb_rx_buffer *new_buff;
6716 u16 nta = rx_ring->next_to_alloc;
6717
6718 new_buff = &rx_ring->rx_buffer_info[nta];
6719
6720 /* update, and store next to alloc */
6721 nta++;
6722 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6723
6724 /* transfer page from old buffer to new buffer */
a1f63473 6725 *new_buff = *old_buff;
cbc8e55f
AD		 6726
6727 /* sync the buffer for use by the device */
6728 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6729 old_buff->page_offset,
de78d1f9 6730 IGB_RX_BUFSZ,
cbc8e55f
AD		 6731 DMA_FROM_DEVICE);
6732}
6733
95dd44b4
AD		 6734static inline bool igb_page_is_reserved(struct page *page)
6735{
2f064f34 6736 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6737}
6738
74e238ea
AD		 6739static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6740 struct page *page,
6741 unsigned int truesize)
6742{
6743 /* avoid re-using remote pages */
95dd44b4 6744 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6745 return false;
6746
74e238ea
AD		 6747#if (PAGE_SIZE < 8192)
6748 /* if we are only owner of page we can reuse it */
6749 if (unlikely(page_count(page) != 1))
6750 return false;
6751
6752 /* flip page offset to other buffer */
6753 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6754#else
6755 /* move offset up to the next cache line */
6756 rx_buffer->page_offset += truesize;
6757
6758 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6759 return false;
74e238ea
AD		 6760#endif
6761
95dd44b4
AD		 6762 /* Even if we own the page, we are not allowed to use atomic_set()
6763 * This would break get_page_unless_zero() users.
6764 */
6765 atomic_inc(&page->_count);
6766
74e238ea
AD		 6767 return true;
6768}
6769
cbc8e55f 6770/**
b980ac18
JK		 6771 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6772 * @rx_ring: rx descriptor ring to transact packets on
6773 * @rx_buffer: buffer containing page to add
6774 * @rx_desc: descriptor containing length of buffer written by hardware
6775 * @skb: sk_buff to place the data into
cbc8e55f 6776 *
b980ac18
JK		 6777 * This function will add the data contained in rx_buffer->page to the skb.
6778 * This is done either through a direct copy if the data in the buffer is
6779 * less than the skb header size, otherwise it will just attach the page as
6780 * a frag to the skb.
cbc8e55f 6781 *
b980ac18
JK		 6782 * The function will then update the page offset if necessary and return
6783 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6784 **/
6785static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6786 struct igb_rx_buffer *rx_buffer,
6787 union e1000_adv_rx_desc *rx_desc,
6788 struct sk_buff *skb)
6789{
6790 struct page *page = rx_buffer->page;
f56e7bba 6791 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6792 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6793#if (PAGE_SIZE < 8192)
6794 unsigned int truesize = IGB_RX_BUFSZ;
6795#else
f56e7bba 6796 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6797#endif
f56e7bba 6798 unsigned int pull_len;
cbc8e55f 6799
f56e7bba
AD		 6800 if (unlikely(skb_is_nonlinear(skb)))
6801 goto add_tail_frag;
cbc8e55f 6802
f56e7bba
AD		 6803 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6804 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6805 va += IGB_TS_HDR_LEN;
6806 size -= IGB_TS_HDR_LEN;
6807 }
cbc8e55f 6808
f56e7bba 6809 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6810 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6811
95dd44b4
AD		 6812 /* page is not reserved, we can reuse buffer as-is */
6813 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6814 return true;
6815
6816 /* this page cannot be reused so discard it */
95dd44b4 6817 __free_page(page);
cbc8e55f
AD		 6818 return false;
6819 }
6820
f56e7bba
AD		 6821 /* we need the header to contain the greater of either ETH_HLEN or
6822 * 60 bytes if the skb->len is less than 60 for skb_pad.
6823 */
6824 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6825
6826 /* align pull length to size of long to optimize memcpy performance */
6827 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6828
6829 /* update all of the pointers */
6830 va += pull_len;
6831 size -= pull_len;
6832
6833add_tail_frag:
cbc8e55f 6834 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6835 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6836
74e238ea
AD		 6837 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6838}
cbc8e55f 6839
2e334eee
AD		 6840static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6841 union e1000_adv_rx_desc *rx_desc,
6842 struct sk_buff *skb)
6843{
6844 struct igb_rx_buffer *rx_buffer;
6845 struct page *page;
6846
6847 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6848 page = rx_buffer->page;
6849 prefetchw(page);
6850
6851 if (likely(!skb)) {
6852 void *page_addr = page_address(page) +
6853 rx_buffer->page_offset;
6854
6855 /* prefetch first cache line of first page */
6856 prefetch(page_addr);
6857#if L1_CACHE_BYTES < 128
6858 prefetch(page_addr + L1_CACHE_BYTES);
6859#endif
6860
6861 /* allocate a skb to store the frags */
67fd893e 6862 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6863 if (unlikely(!skb)) {
6864 rx_ring->rx_stats.alloc_failed++;
6865 return NULL;
6866 }
6867
b980ac18 6868 /* we will be copying header into skb->data in
2e334eee
AD		 6869 * pskb_may_pull so it is in our interest to prefetch
6870 * it now to avoid a possible cache miss
6871 */
6872 prefetchw(skb->data);
6873 }
6874
6875 /* we are reusing so sync this buffer for CPU use */
6876 dma_sync_single_range_for_cpu(rx_ring->dev,
6877 rx_buffer->dma,
6878 rx_buffer->page_offset,
de78d1f9 6879 IGB_RX_BUFSZ,
2e334eee
AD		 6880 DMA_FROM_DEVICE);
6881
6882 /* pull page into skb */
6883 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6884 /* hand second half of page back to the ring */
6885 igb_reuse_rx_page(rx_ring, rx_buffer);
6886 } else {
6887 /* we are not reusing the buffer so unmap it */
6888 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6889 PAGE_SIZE, DMA_FROM_DEVICE);
6890 }
6891
6892 /* clear contents of rx_buffer */
6893 rx_buffer->page = NULL;
6894
6895 return skb;
6896}
6897
cd392f5c 6898static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6899 union e1000_adv_rx_desc *rx_desc,
6900 struct sk_buff *skb)
9d5c8243 6901{
bc8acf2c 6902 skb_checksum_none_assert(skb);
9d5c8243 6903
294e7d78 6904 /* Ignore Checksum bit is set */
3ceb90fd 6905 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6906 return;
6907
6908 /* Rx checksum disabled via ethtool */
6909 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6910 return;
85ad76b2 6911
9d5c8243 6912 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6913 if (igb_test_staterr(rx_desc,
6914 E1000_RXDEXT_STATERR_TCPE |
6915 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6916 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6917 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6918 * packets, (aka let the stack check the crc32c)
6919 */
866cff06
AD		 6920 if (!((skb->len == 60) &&
6921 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6922 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6923 ring->rx_stats.csum_err++;
12dcd86b
ED		 6924 u64_stats_update_end(&ring->rx_syncp);
6925 }
9d5c8243 6926 /* let the stack verify checksum errors */
9d5c8243
AK		 6927 return;
6928 }
6929 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6930 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6931 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6932 skb->ip_summed = CHECKSUM_UNNECESSARY;
6933
3ceb90fd
AD		 6934 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6935 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6936}
6937
077887c3
AD		 6938static inline void igb_rx_hash(struct igb_ring *ring,
6939 union e1000_adv_rx_desc *rx_desc,
6940 struct sk_buff *skb)
6941{
6942 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6943 skb_set_hash(skb,
6944 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6945 PKT_HASH_TYPE_L3);
077887c3
AD		 6946}
6947
2e334eee 6948/**
b980ac18
JK		 6949 * igb_is_non_eop - process handling of non-EOP buffers
6950 * @rx_ring: Rx ring being processed
6951 * @rx_desc: Rx descriptor for current buffer
6952 * @skb: current socket buffer containing buffer in progress
2e334eee 6953 *
b980ac18
JK		 6954 * This function updates next to clean. If the buffer is an EOP buffer
6955 * this function exits returning false, otherwise it will place the
6956 * sk_buff in the next buffer to be chained and return true indicating
6957 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6958 **/
6959static bool igb_is_non_eop(struct igb_ring *rx_ring,
6960 union e1000_adv_rx_desc *rx_desc)
6961{
6962 u32 ntc = rx_ring->next_to_clean + 1;
6963
6964 /* fetch, update, and store next to clean */
6965 ntc = (ntc < rx_ring->count) ? ntc : 0;
6966 rx_ring->next_to_clean = ntc;
6967
6968 prefetch(IGB_RX_DESC(rx_ring, ntc));
6969
6970 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6971 return false;
6972
6973 return true;
6974}
6975
1a1c225b 6976/**
b980ac18
JK		 6977 * igb_cleanup_headers - Correct corrupted or empty headers
6978 * @rx_ring: rx descriptor ring packet is being transacted on
6979 * @rx_desc: pointer to the EOP Rx descriptor
6980 * @skb: pointer to current skb being fixed
1a1c225b 6981 *
b980ac18
JK		 6982 * Address the case where we are pulling data in on pages only
6983 * and as such no data is present in the skb header.
1a1c225b 6984 *
b980ac18
JK		 6985 * In addition if skb is not at least 60 bytes we need to pad it so that
6986 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6987 *
b980ac18 6988 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6989 **/
6990static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6991 union e1000_adv_rx_desc *rx_desc,
6992 struct sk_buff *skb)
6993{
1a1c225b
AD		 6994 if (unlikely((igb_test_staterr(rx_desc,
6995 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6996 struct net_device *netdev = rx_ring->netdev;
6997 if (!(netdev->features & NETIF_F_RXALL)) {
6998 dev_kfree_skb_any(skb);
6999 return true;
7000 }
7001 }
7002
a94d9e22
AD		 7003 /* if eth_skb_pad returns an error the skb was freed */
7004 if (eth_skb_pad(skb))
7005 return true;
1a1c225b
AD		 7006
7007 return false;
2d94d8ab
AD		 7008}
7009
db2ee5bd 7010/**
b980ac18
JK		 7011 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
7012 * @rx_ring: rx descriptor ring packet is being transacted on
7013 * @rx_desc: pointer to the EOP Rx descriptor
7014 * @skb: pointer to current skb being populated
db2ee5bd 7015 *
b980ac18
JK		 7016 * This function checks the ring, descriptor, and packet information in
7017 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
7018 * other fields within the skb.
db2ee5bd
AD		 7019 **/
7020static void igb_process_skb_fields(struct igb_ring *rx_ring,
7021 union e1000_adv_rx_desc *rx_desc,
7022 struct sk_buff *skb)
7023{
7024 struct net_device *dev = rx_ring->netdev;
7025
7026 igb_rx_hash(rx_ring, rx_desc, skb);
7027
7028 igb_rx_checksum(rx_ring, rx_desc, skb);
7029
5499a968
JK		 7030 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7031 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7032 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 7033
f646968f 7034 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 7035 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7036 u16 vid;
9005df38 7037
db2ee5bd
AD		 7038 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7039 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7040 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7041 else
7042 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7043
86a9bad3 7044 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 7045 }
7046
7047 skb_record_rx_queue(skb, rx_ring->queue_index);
7048
7049 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7050}
7051
32b3e08f 7052static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 7053{
0ba82994 7054 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 7055 struct sk_buff *skb = rx_ring->skb;
9d5c8243 7056 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 7057 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 7058
57ba34c9 7059 while (likely(total_packets < budget)) {
2e334eee 7060 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7061
2e334eee
AD		 7062 /* return some buffers to hardware, one at a time is too slow */
7063 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7064 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7065 cleaned_count = 0;
7066 }
bf36c1a0 7067
2e334eee 7068 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7069
124b74c1 7070 if (!rx_desc->wb.upper.status_error)
2e334eee 7071 break;
9d5c8243 7072
74e238ea
AD		 7073 /* This memory barrier is needed to keep us from reading
7074 * any other fields out of the rx_desc until we know the
124b74c1 7075 * descriptor has been written back
74e238ea 7076 */
124b74c1 7077 dma_rmb();
74e238ea 7078
2e334eee 7079 /* retrieve a buffer from the ring */
f9d40f6a 7080 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7081
2e334eee
AD		 7082 /* exit if we failed to retrieve a buffer */
7083 if (!skb)
7084 break;
1a1c225b 7085
2e334eee 7086 cleaned_count++;
1a1c225b 7087
2e334eee
AD		 7088 /* fetch next buffer in frame if non-eop */
7089 if (igb_is_non_eop(rx_ring, rx_desc))
7090 continue;
1a1c225b
AD		 7091
7092 /* verify the packet layout is correct */
7093 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7094 skb = NULL;
7095 continue;
9d5c8243 7096 }
9d5c8243 7097
db2ee5bd 7098 /* probably a little skewed due to removing CRC */
3ceb90fd 7099 total_bytes += skb->len;
3ceb90fd 7100
db2ee5bd
AD		 7101 /* populate checksum, timestamp, VLAN, and protocol */
7102 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7103
b2cb09b1 7104 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7105
1a1c225b
AD		 7106 /* reset skb pointer */
7107 skb = NULL;
7108
2e334eee
AD		 7109 /* update budget accounting */
7110 total_packets++;
57ba34c9 7111 }
bf36c1a0 7112
1a1c225b
AD		 7113 /* place incomplete frames back on ring for completion */
7114 rx_ring->skb = skb;
7115
12dcd86b 7116 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7117 rx_ring->rx_stats.packets += total_packets;
7118 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7119 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7120 q_vector->rx.total_packets += total_packets;
7121 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7122
7123 if (cleaned_count)
cd392f5c 7124 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7125
32b3e08f 7126 return total_packets;
9d5c8243
AK		 7127}
7128
c023cd88 7129static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7130 struct igb_rx_buffer *bi)
c023cd88
AD		 7131{
7132 struct page *page = bi->page;
cbc8e55f 7133 dma_addr_t dma;
c023cd88 7134
cbc8e55f
AD		 7135 /* since we are recycling buffers we should seldom need to alloc */
7136 if (likely(page))
c023cd88
AD		 7137 return true;
7138
cbc8e55f 7139 /* alloc new page for storage */
42b17f09 7140 page = dev_alloc_page();
cbc8e55f
AD		 7141 if (unlikely(!page)) {
7142 rx_ring->rx_stats.alloc_failed++;
7143 return false;
c023cd88
AD		 7144 }
7145
cbc8e55f
AD		 7146 /* map page for use */
7147 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7148
b980ac18 7149 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7150 * there isn't much point in holding memory we can't use
7151 */
1a1c225b 7152 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7153 __free_page(page);
7154
c023cd88
AD		 7155 rx_ring->rx_stats.alloc_failed++;
7156 return false;
7157 }
7158
1a1c225b 7159 bi->dma = dma;
cbc8e55f
AD		 7160 bi->page = page;
7161 bi->page_offset = 0;
1a1c225b 7162
c023cd88
AD		 7163 return true;
7164}
7165
9d5c8243 7166/**
b980ac18
JK		 7167 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7168 * @adapter: address of board private structure
9d5c8243 7169 **/
cd392f5c 7170void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7171{
9d5c8243 7172 union e1000_adv_rx_desc *rx_desc;
06034649 7173 struct igb_rx_buffer *bi;
c023cd88 7174 u16 i = rx_ring->next_to_use;
9d5c8243 7175
cbc8e55f
AD		 7176 /* nothing to do */
7177 if (!cleaned_count)
7178 return;
7179
60136906 7180 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7181 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7182 i -= rx_ring->count;
9d5c8243 7183
cbc8e55f 7184 do {
1a1c225b 7185 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7186 break;
9d5c8243 7187
b980ac18 7188 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7189 * because each write-back erases this info.
7190 */
f9d40f6a 7191 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7192
c023cd88
AD		 7193 rx_desc++;
7194 bi++;
9d5c8243 7195 i++;
c023cd88 7196 if (unlikely(!i)) {
60136906 7197 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7198 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7199 i -= rx_ring->count;
7200 }
7201
95dd44b4
AD		 7202 /* clear the status bits for the next_to_use descriptor */
7203 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7204
7205 cleaned_count--;
7206 } while (cleaned_count);
9d5c8243 7207
c023cd88
AD		 7208 i += rx_ring->count;
7209
9d5c8243 7210 if (rx_ring->next_to_use != i) {
cbc8e55f 7211 /* record the next descriptor to use */
9d5c8243 7212 rx_ring->next_to_use = i;
9d5c8243 7213
cbc8e55f
AD		 7214 /* update next to alloc since we have filled the ring */
7215 rx_ring->next_to_alloc = i;
7216
b980ac18 7217 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7218 * know there are new descriptors to fetch. (Only
7219 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7220 * such as IA-64).
7221 */
9d5c8243 7222 wmb();
fce99e34 7223 writel(i, rx_ring->tail);
9d5c8243
AK		 7224 }
7225}
7226
7227/**
7228 * igb_mii_ioctl -
7229 * @netdev:
7230 * @ifreq:
7231 * @cmd:
7232 **/
7233static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7234{
7235 struct igb_adapter *adapter = netdev_priv(netdev);
7236 struct mii_ioctl_data *data = if_mii(ifr);
7237
7238 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7239 return -EOPNOTSUPP;
7240
7241 switch (cmd) {
7242 case SIOCGMIIPHY:
7243 data->phy_id = adapter->hw.phy.addr;
7244 break;
7245 case SIOCGMIIREG:
f5f4cf08 7246 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7247 &data->val_out))
9d5c8243
AK		 7248 return -EIO;
7249 break;
7250 case SIOCSMIIREG:
7251 default:
7252 return -EOPNOTSUPP;
7253 }
7254 return 0;
7255}
7256
7257/**
7258 * igb_ioctl -
7259 * @netdev:
7260 * @ifreq:
7261 * @cmd:
7262 **/
7263static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7264{
7265 switch (cmd) {
7266 case SIOCGMIIPHY:
7267 case SIOCGMIIREG:
7268 case SIOCSMIIREG:
7269 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7270 case SIOCGHWTSTAMP:
7271 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7272 case SIOCSHWTSTAMP:
6ab5f7b2 7273 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7274 default:
7275 return -EOPNOTSUPP;
7276 }
7277}
7278
94826487
TF		 7279void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7280{
7281 struct igb_adapter *adapter = hw->back;
7282
7283 pci_read_config_word(adapter->pdev, reg, value);
7284}
7285
7286void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7287{
7288 struct igb_adapter *adapter = hw->back;
7289
7290 pci_write_config_word(adapter->pdev, reg, *value);
7291}
7292
009bc06e
AD		 7293s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7294{
7295 struct igb_adapter *adapter = hw->back;
009bc06e 7296
23d028cc 7297 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7298 return -E1000_ERR_CONFIG;
7299
009bc06e
AD		 7300 return 0;
7301}
7302
7303s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7304{
7305 struct igb_adapter *adapter = hw->back;
009bc06e 7306
23d028cc 7307 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7308 return -E1000_ERR_CONFIG;
7309
009bc06e
AD		 7310 return 0;
7311}
7312
c8f44aff 7313static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7314{
7315 struct igb_adapter *adapter = netdev_priv(netdev);
7316 struct e1000_hw *hw = &adapter->hw;
7317 u32 ctrl, rctl;
f646968f 7318 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7319
5faf030c 7320 if (enable) {
9d5c8243
AK		 7321 /* enable VLAN tag insert/strip */
7322 ctrl = rd32(E1000_CTRL);
7323 ctrl |= E1000_CTRL_VME;
7324 wr32(E1000_CTRL, ctrl);
7325
51466239 7326 /* Disable CFI check */
9d5c8243 7327 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7328 rctl &= ~E1000_RCTL_CFIEN;
7329 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7330 } else {
7331 /* disable VLAN tag insert/strip */
7332 ctrl = rd32(E1000_CTRL);
7333 ctrl &= ~E1000_CTRL_VME;
7334 wr32(E1000_CTRL, ctrl);
9d5c8243 7335 }
9d5c8243
AK		 7336}
7337
80d5c368
PM		 7338static int igb_vlan_rx_add_vid(struct net_device *netdev,
7339 __be16 proto, u16 vid)
9d5c8243
AK		 7340{
7341 struct igb_adapter *adapter = netdev_priv(netdev);
7342 struct e1000_hw *hw = &adapter->hw;
4ae196df 7343 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7344
51466239 7345 /* add the filter since PF can receive vlans w/o entry in vlvf */
16903caa
AD		 7346 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7347 igb_vfta_set(hw, vid, pf_id, true, !!vid);
7348
b2cb09b1 7349 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7350
7351 return 0;
9d5c8243
AK		 7352}
7353
80d5c368
PM		 7354static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7355 __be16 proto, u16 vid)
9d5c8243
AK		 7356{
7357 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 7358 int pf_id = adapter->vfs_allocated_count;
8b77c6b2 7359 struct e1000_hw *hw = &adapter->hw;
9d5c8243 7360
8b77c6b2 7361 /* remove VID from filter table */
16903caa
AD		 7362 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7363 igb_vfta_set(hw, vid, pf_id, false, true);
b2cb09b1
JP		 7364
7365 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7366
7367 return 0;
9d5c8243
AK		 7368}
7369
7370static void igb_restore_vlan(struct igb_adapter *adapter)
7371{
5982a556 7372 u16 vid = 1;
9d5c8243 7373
5faf030c 7374 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
5982a556 7375 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
5faf030c 7376
5982a556 7377 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7378 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7379}
7380
14ad2513 7381int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7382{
090b1795 7383 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7384 struct e1000_mac_info *mac = &adapter->hw.mac;
7385
7386 mac->autoneg = 0;
7387
14ad2513 7388 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7389 * for the switch() below to work
7390 */
14ad2513
DD		 7391 if ((spd & 1) || (dplx & ~1))
7392 goto err_inval;
7393
f502ef7d
AA		 7394 /* Fiber NIC's only allow 1000 gbps Full duplex
7395 * and 100Mbps Full duplex for 100baseFx sfp
7396 */
7397 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7398 switch (spd + dplx) {
7399 case SPEED_10 + DUPLEX_HALF:
7400 case SPEED_10 + DUPLEX_FULL:
7401 case SPEED_100 + DUPLEX_HALF:
7402 goto err_inval;
7403 default:
7404 break;
7405 }
7406 }
cd2638a8 7407
14ad2513 7408 switch (spd + dplx) {
9d5c8243
AK		 7409 case SPEED_10 + DUPLEX_HALF:
7410 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7411 break;
7412 case SPEED_10 + DUPLEX_FULL:
7413 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7414 break;
7415 case SPEED_100 + DUPLEX_HALF:
7416 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7417 break;
7418 case SPEED_100 + DUPLEX_FULL:
7419 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7420 break;
7421 case SPEED_1000 + DUPLEX_FULL:
7422 mac->autoneg = 1;
7423 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7424 break;
7425 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7426 default:
14ad2513 7427 goto err_inval;
9d5c8243 7428 }
8376dad0
JB		 7429
7430 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7431 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7432
9d5c8243 7433 return 0;
14ad2513
DD		 7434
7435err_inval:
7436 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7437 return -EINVAL;
9d5c8243
AK		 7438}
7439
749ab2cd
YZ		 7440static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7441 bool runtime)
9d5c8243
AK		 7442{
7443 struct net_device *netdev = pci_get_drvdata(pdev);
7444 struct igb_adapter *adapter = netdev_priv(netdev);
7445 struct e1000_hw *hw = &adapter->hw;
2d064c06 7446 u32 ctrl, rctl, status;
749ab2cd 7447 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7448#ifdef CONFIG_PM
7449 int retval = 0;
7450#endif
7451
7452 netif_device_detach(netdev);
7453
a88f10ec 7454 if (netif_running(netdev))
749ab2cd 7455 __igb_close(netdev, true);
a88f10ec 7456
047e0030 7457 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7458
7459#ifdef CONFIG_PM
7460 retval = pci_save_state(pdev);
7461 if (retval)
7462 return retval;
7463#endif
7464
7465 status = rd32(E1000_STATUS);
7466 if (status & E1000_STATUS_LU)
7467 wufc &= ~E1000_WUFC_LNKC;
7468
7469 if (wufc) {
7470 igb_setup_rctl(adapter);
ff41f8dc 7471 igb_set_rx_mode(netdev);
9d5c8243
AK		 7472
7473 /* turn on all-multi mode if wake on multicast is enabled */
7474 if (wufc & E1000_WUFC_MC) {
7475 rctl = rd32(E1000_RCTL);
7476 rctl |= E1000_RCTL_MPE;
7477 wr32(E1000_RCTL, rctl);
7478 }
7479
7480 ctrl = rd32(E1000_CTRL);
7481 /* advertise wake from D3Cold */
7482 #define E1000_CTRL_ADVD3WUC 0x00100000
7483 /* phy power management enable */
7484 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7485 ctrl |= E1000_CTRL_ADVD3WUC;
7486 wr32(E1000_CTRL, ctrl);
7487
9d5c8243 7488 /* Allow time for pending master requests to run */
330a6d6a 7489 igb_disable_pcie_master(hw);
9d5c8243
AK		 7490
7491 wr32(E1000_WUC, E1000_WUC_PME_EN);
7492 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7493 } else {
7494 wr32(E1000_WUC, 0);
7495 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7496 }
7497
3fe7c4c9
RW		 7498 *enable_wake = wufc || adapter->en_mng_pt;
7499 if (!*enable_wake)
88a268c1
NN		 7500 igb_power_down_link(adapter);
7501 else
7502 igb_power_up_link(adapter);
9d5c8243
AK		 7503
7504 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7505 * would have already happened in close and is redundant.
7506 */
9d5c8243
AK		 7507 igb_release_hw_control(adapter);
7508
7509 pci_disable_device(pdev);
7510
9d5c8243
AK		 7511 return 0;
7512}
7513
7514#ifdef CONFIG_PM
d9dd966d 7515#ifdef CONFIG_PM_SLEEP
749ab2cd 7516static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7517{
7518 int retval;
7519 bool wake;
749ab2cd 7520 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7521
749ab2cd 7522 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7523 if (retval)
7524 return retval;
7525
7526 if (wake) {
7527 pci_prepare_to_sleep(pdev);
7528 } else {
7529 pci_wake_from_d3(pdev, false);
7530 pci_set_power_state(pdev, PCI_D3hot);
7531 }
7532
7533 return 0;
7534}
d9dd966d 7535#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7536
749ab2cd 7537static int igb_resume(struct device *dev)
9d5c8243 7538{
749ab2cd 7539 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7540 struct net_device *netdev = pci_get_drvdata(pdev);
7541 struct igb_adapter *adapter = netdev_priv(netdev);
7542 struct e1000_hw *hw = &adapter->hw;
7543 u32 err;
7544
7545 pci_set_power_state(pdev, PCI_D0);
7546 pci_restore_state(pdev);
b94f2d77 7547 pci_save_state(pdev);
42bfd33a 7548
17a402a0
CW		 7549 if (!pci_device_is_present(pdev))
7550 return -ENODEV;
aed5dec3 7551 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7552 if (err) {
7553 dev_err(&pdev->dev,
7554 "igb: Cannot enable PCI device from suspend\n");
7555 return err;
7556 }
7557 pci_set_master(pdev);
7558
7559 pci_enable_wake(pdev, PCI_D3hot, 0);
7560 pci_enable_wake(pdev, PCI_D3cold, 0);
7561
53c7d064 7562 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec 7563 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3eb14ea8 7564 rtnl_unlock();
a88f10ec 7565 return -ENOMEM;
9d5c8243
AK		 7566 }
7567
9d5c8243 7568 igb_reset(adapter);
a8564f03
AD		 7569
7570 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7571 * driver.
7572 */
a8564f03
AD		 7573 igb_get_hw_control(adapter);
7574
9d5c8243
AK		 7575 wr32(E1000_WUS, ~0);
7576
749ab2cd 7577 if (netdev->flags & IFF_UP) {
0c2cc02e 7578 rtnl_lock();
749ab2cd 7579 err = __igb_open(netdev, true);
0c2cc02e 7580 rtnl_unlock();
a88f10ec
AD		 7581 if (err)
7582 return err;
7583 }
9d5c8243
AK		 7584
7585 netif_device_attach(netdev);
749ab2cd
YZ		 7586 return 0;
7587}
7588
749ab2cd
YZ		 7589static int igb_runtime_idle(struct device *dev)
7590{
7591 struct pci_dev *pdev = to_pci_dev(dev);
7592 struct net_device *netdev = pci_get_drvdata(pdev);
7593 struct igb_adapter *adapter = netdev_priv(netdev);
7594
7595 if (!igb_has_link(adapter))
7596 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7597
7598 return -EBUSY;
7599}
7600
7601static int igb_runtime_suspend(struct device *dev)
7602{
7603 struct pci_dev *pdev = to_pci_dev(dev);
7604 int retval;
7605 bool wake;
7606
7607 retval = __igb_shutdown(pdev, &wake, 1);
7608 if (retval)
7609 return retval;
7610
7611 if (wake) {
7612 pci_prepare_to_sleep(pdev);
7613 } else {
7614 pci_wake_from_d3(pdev, false);
7615 pci_set_power_state(pdev, PCI_D3hot);
7616 }
9d5c8243 7617
9d5c8243
AK		 7618 return 0;
7619}
749ab2cd
YZ		 7620
7621static int igb_runtime_resume(struct device *dev)
7622{
7623 return igb_resume(dev);
7624}
d61c81cb 7625#endif /* CONFIG_PM */
9d5c8243
AK		 7626
7627static void igb_shutdown(struct pci_dev *pdev)
7628{
3fe7c4c9
RW		 7629 bool wake;
7630
749ab2cd 7631 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7632
7633 if (system_state == SYSTEM_POWER_OFF) {
7634 pci_wake_from_d3(pdev, wake);
7635 pci_set_power_state(pdev, PCI_D3hot);
7636 }
9d5c8243
AK		 7637}
7638
fa44f2f1
GR		 7639#ifdef CONFIG_PCI_IOV
7640static int igb_sriov_reinit(struct pci_dev *dev)
7641{
7642 struct net_device *netdev = pci_get_drvdata(dev);
7643 struct igb_adapter *adapter = netdev_priv(netdev);
7644 struct pci_dev *pdev = adapter->pdev;
7645
7646 rtnl_lock();
7647
7648 if (netif_running(netdev))
7649 igb_close(netdev);
76252723
SA		 7650 else
7651 igb_reset(adapter);
fa44f2f1
GR		 7652
7653 igb_clear_interrupt_scheme(adapter);
7654
7655 igb_init_queue_configuration(adapter);
7656
7657 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7658 rtnl_unlock();
fa44f2f1
GR		 7659 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7660 return -ENOMEM;
7661 }
7662
7663 if (netif_running(netdev))
7664 igb_open(netdev);
7665
7666 rtnl_unlock();
7667
7668 return 0;
7669}
7670
7671static int igb_pci_disable_sriov(struct pci_dev *dev)
7672{
7673 int err = igb_disable_sriov(dev);
7674
7675 if (!err)
7676 err = igb_sriov_reinit(dev);
7677
7678 return err;
7679}
7680
7681static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7682{
7683 int err = igb_enable_sriov(dev, num_vfs);
7684
7685 if (err)
7686 goto out;
7687
7688 err = igb_sriov_reinit(dev);
7689 if (!err)
7690 return num_vfs;
7691
7692out:
7693 return err;
7694}
7695
7696#endif
7697static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7698{
7699#ifdef CONFIG_PCI_IOV
7700 if (num_vfs == 0)
7701 return igb_pci_disable_sriov(dev);
7702 else
7703 return igb_pci_enable_sriov(dev, num_vfs);
7704#endif
7705 return 0;
7706}
7707
9d5c8243 7708#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7709/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7710 * without having to re-enable interrupts. It's not called while
7711 * the interrupt routine is executing.
7712 */
7713static void igb_netpoll(struct net_device *netdev)
7714{
7715 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7716 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7717 struct igb_q_vector *q_vector;
9d5c8243 7718 int i;
9d5c8243 7719
047e0030 7720 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7721 q_vector = adapter->q_vector[i];
cd14ef54 7722 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7723 wr32(E1000_EIMC, q_vector->eims_value);
7724 else
7725 igb_irq_disable(adapter);
047e0030 7726 napi_schedule(&q_vector->napi);
eebbbdba 7727 }
9d5c8243
AK		 7728}
7729#endif /* CONFIG_NET_POLL_CONTROLLER */
7730
7731/**
b980ac18
JK		 7732 * igb_io_error_detected - called when PCI error is detected
7733 * @pdev: Pointer to PCI device
7734 * @state: The current pci connection state
9d5c8243 7735 *
b980ac18
JK		 7736 * This function is called after a PCI bus error affecting
7737 * this device has been detected.
7738 **/
9d5c8243
AK		 7739static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7740 pci_channel_state_t state)
7741{
7742 struct net_device *netdev = pci_get_drvdata(pdev);
7743 struct igb_adapter *adapter = netdev_priv(netdev);
7744
7745 netif_device_detach(netdev);
7746
59ed6eec
AD		 7747 if (state == pci_channel_io_perm_failure)
7748 return PCI_ERS_RESULT_DISCONNECT;
7749
9d5c8243
AK		 7750 if (netif_running(netdev))
7751 igb_down(adapter);
7752 pci_disable_device(pdev);
7753
7754 /* Request a slot slot reset. */
7755 return PCI_ERS_RESULT_NEED_RESET;
7756}
7757
7758/**
b980ac18
JK		 7759 * igb_io_slot_reset - called after the pci bus has been reset.
7760 * @pdev: Pointer to PCI device
9d5c8243 7761 *
b980ac18
JK		 7762 * Restart the card from scratch, as if from a cold-boot. Implementation
7763 * resembles the first-half of the igb_resume routine.
7764 **/
9d5c8243
AK		 7765static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7766{
7767 struct net_device *netdev = pci_get_drvdata(pdev);
7768 struct igb_adapter *adapter = netdev_priv(netdev);
7769 struct e1000_hw *hw = &adapter->hw;
40a914fa 7770 pci_ers_result_t result;
42bfd33a 7771 int err;
9d5c8243 7772
aed5dec3 7773 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7774 dev_err(&pdev->dev,
7775 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7776 result = PCI_ERS_RESULT_DISCONNECT;
7777 } else {
7778 pci_set_master(pdev);
7779 pci_restore_state(pdev);
b94f2d77 7780 pci_save_state(pdev);
9d5c8243 7781
40a914fa
AD		 7782 pci_enable_wake(pdev, PCI_D3hot, 0);
7783 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7784
40a914fa
AD		 7785 igb_reset(adapter);
7786 wr32(E1000_WUS, ~0);
7787 result = PCI_ERS_RESULT_RECOVERED;
7788 }
9d5c8243 7789
ea943d41
JK		 7790 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7791 if (err) {
b980ac18
JK		 7792 dev_err(&pdev->dev,
7793 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7794 err);
ea943d41
JK		 7795 /* non-fatal, continue */
7796 }
40a914fa
AD		 7797
7798 return result;
9d5c8243
AK		 7799}
7800
7801/**
b980ac18
JK		 7802 * igb_io_resume - called when traffic can start flowing again.
7803 * @pdev: Pointer to PCI device
9d5c8243 7804 *
b980ac18
JK		 7805 * This callback is called when the error recovery driver tells us that
7806 * its OK to resume normal operation. Implementation resembles the
7807 * second-half of the igb_resume routine.
9d5c8243
AK		 7808 */
7809static void igb_io_resume(struct pci_dev *pdev)
7810{
7811 struct net_device *netdev = pci_get_drvdata(pdev);
7812 struct igb_adapter *adapter = netdev_priv(netdev);
7813
9d5c8243
AK		 7814 if (netif_running(netdev)) {
7815 if (igb_up(adapter)) {
7816 dev_err(&pdev->dev, "igb_up failed after reset\n");
7817 return;
7818 }
7819 }
7820
7821 netif_device_attach(netdev);
7822
7823 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7824 * driver.
7825 */
9d5c8243 7826 igb_get_hw_control(adapter);
9d5c8243
AK		 7827}
7828
26ad9178 7829static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7830 u8 qsel)
26ad9178 7831{
26ad9178 7832 struct e1000_hw *hw = &adapter->hw;
c3278587 7833 u32 rar_low, rar_high;
26ad9178
AD		 7834
7835 /* HW expects these in little endian so we reverse the byte order
c3278587 7836 * from network order (big endian) to CPU endian
26ad9178 7837 */
c3278587
AD		 7838 rar_low = le32_to_cpup((__be32 *)(addr));
7839 rar_high = le16_to_cpup((__be16 *)(addr + 4));
26ad9178
AD		 7840
7841 /* Indicate to hardware the Address is Valid. */
7842 rar_high |= E1000_RAH_AV;
7843
7844 if (hw->mac.type == e1000_82575)
7845 rar_high |= E1000_RAH_POOL_1 * qsel;
7846 else
7847 rar_high |= E1000_RAH_POOL_1 << qsel;
7848
7849 wr32(E1000_RAL(index), rar_low);
7850 wrfl();
7851 wr32(E1000_RAH(index), rar_high);
7852 wrfl();
7853}
7854
4ae196df 7855static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7856 int vf, unsigned char *mac_addr)
4ae196df
AD		 7857{
7858 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7859 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7860 * towards the first, as a result a collision should not be possible
7861 */
ff41f8dc 7862 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7863
37680117 7864 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7865
26ad9178 7866 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7867
7868 return 0;
7869}
7870
8151d294
WM		 7871static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7872{
7873 struct igb_adapter *adapter = netdev_priv(netdev);
7874 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7875 return -EINVAL;
7876 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7877 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7878 dev_info(&adapter->pdev->dev,
7879 "Reload the VF driver to make this change effective.");
8151d294 7880 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7881 dev_warn(&adapter->pdev->dev,
7882 "The VF MAC address has been set, but the PF device is not up.\n");
7883 dev_warn(&adapter->pdev->dev,
7884 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7885 }
7886 return igb_set_vf_mac(adapter, vf, mac);
7887}
7888
17dc566c
LL		 7889static int igb_link_mbps(int internal_link_speed)
7890{
7891 switch (internal_link_speed) {
7892 case SPEED_100:
7893 return 100;
7894 case SPEED_1000:
7895 return 1000;
7896 default:
7897 return 0;
7898 }
7899}
7900
7901static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7902 int link_speed)
7903{
7904 int rf_dec, rf_int;
7905 u32 bcnrc_val;
7906
7907 if (tx_rate != 0) {
7908 /* Calculate the rate factor values to set */
7909 rf_int = link_speed / tx_rate;
7910 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7911 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7912 tx_rate;
17dc566c
LL		 7913
7914 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7915 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7916 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7917 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7918 } else {
7919 bcnrc_val = 0;
7920 }
7921
7922 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7923 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7924 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7925 */
7926 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7927 wr32(E1000_RTTBCNRC, bcnrc_val);
7928}
7929
7930static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7931{
7932 int actual_link_speed, i;
7933 bool reset_rate = false;
7934
7935 /* VF TX rate limit was not set or not supported */
7936 if ((adapter->vf_rate_link_speed == 0) ||
7937 (adapter->hw.mac.type != e1000_82576))
7938 return;
7939
7940 actual_link_speed = igb_link_mbps(adapter->link_speed);
7941 if (actual_link_speed != adapter->vf_rate_link_speed) {
7942 reset_rate = true;
7943 adapter->vf_rate_link_speed = 0;
7944 dev_info(&adapter->pdev->dev,
b980ac18 7945 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7946 }
7947
7948 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7949 if (reset_rate)
7950 adapter->vf_data[i].tx_rate = 0;
7951
7952 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7953 adapter->vf_data[i].tx_rate,
7954 actual_link_speed);
17dc566c
LL		 7955 }
7956}
7957
ed616689
SC		 7958static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7959 int min_tx_rate, int max_tx_rate)
8151d294 7960{
17dc566c
LL		 7961 struct igb_adapter *adapter = netdev_priv(netdev);
7962 struct e1000_hw *hw = &adapter->hw;
7963 int actual_link_speed;
7964
7965 if (hw->mac.type != e1000_82576)
7966 return -EOPNOTSUPP;
7967
ed616689
SC		 7968 if (min_tx_rate)
7969 return -EINVAL;
7970
17dc566c
LL		 7971 actual_link_speed = igb_link_mbps(adapter->link_speed);
7972 if ((vf >= adapter->vfs_allocated_count) ||
7973 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7974 (max_tx_rate < 0) ||
7975 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7976 return -EINVAL;
7977
7978 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7979 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7980 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7981
7982 return 0;
8151d294
WM		 7983}
7984
70ea4783
LL		 7985static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7986 bool setting)
7987{
7988 struct igb_adapter *adapter = netdev_priv(netdev);
7989 struct e1000_hw *hw = &adapter->hw;
7990 u32 reg_val, reg_offset;
7991
7992 if (!adapter->vfs_allocated_count)
7993 return -EOPNOTSUPP;
7994
7995 if (vf >= adapter->vfs_allocated_count)
7996 return -EINVAL;
7997
7998 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7999 reg_val = rd32(reg_offset);
8000 if (setting)
8001 reg_val |= ((1 << vf) |
8002 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
8003 else
8004 reg_val &= ~((1 << vf) |
8005 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
8006 wr32(reg_offset, reg_val);
8007
8008 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 8009 return 0;
70ea4783
LL		 8010}
8011
8151d294
WM		 8012static int igb_ndo_get_vf_config(struct net_device *netdev,
8013 int vf, struct ifla_vf_info *ivi)
8014{
8015 struct igb_adapter *adapter = netdev_priv(netdev);
8016 if (vf >= adapter->vfs_allocated_count)
8017 return -EINVAL;
8018 ivi->vf = vf;
8019 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 8020 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8021 ivi->min_tx_rate = 0;
8151d294
WM		 8022 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8023 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 8024 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 8025 return 0;
8026}
8027
4ae196df
AD		 8028static void igb_vmm_control(struct igb_adapter *adapter)
8029{
8030 struct e1000_hw *hw = &adapter->hw;
10d8e907 8031 u32 reg;
4ae196df 8032
52a1dd4d
AD		 8033 switch (hw->mac.type) {
8034 case e1000_82575:
f96a8a0b
CW		 8035 case e1000_i210:
8036 case e1000_i211:
ceb5f13b 8037 case e1000_i354:
52a1dd4d
AD		 8038 default:
8039 /* replication is not supported for 82575 */
4ae196df 8040 return;
52a1dd4d
AD		 8041 case e1000_82576:
8042 /* notify HW that the MAC is adding vlan tags */
8043 reg = rd32(E1000_DTXCTL);
8044 reg |= E1000_DTXCTL_VLAN_ADDED;
8045 wr32(E1000_DTXCTL, reg);
b26141d4 8046 /* Fall through */
52a1dd4d
AD		 8047 case e1000_82580:
8048 /* enable replication vlan tag stripping */
8049 reg = rd32(E1000_RPLOLR);
8050 reg |= E1000_RPLOLR_STRVLAN;
8051 wr32(E1000_RPLOLR, reg);
b26141d4 8052 /* Fall through */
d2ba2ed8
AD		 8053 case e1000_i350:
8054 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8055 break;
8056 }
10d8e907 8057
d4960307
AD		 8058 if (adapter->vfs_allocated_count) {
8059 igb_vmdq_set_loopback_pf(hw, true);
8060 igb_vmdq_set_replication_pf(hw, true);
13800469 8061 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8062 adapter->vfs_allocated_count);
d4960307
AD		 8063 } else {
8064 igb_vmdq_set_loopback_pf(hw, false);
8065 igb_vmdq_set_replication_pf(hw, false);
8066 }
4ae196df
AD		 8067}
8068
b6e0c419
CW		 8069static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8070{
8071 struct e1000_hw *hw = &adapter->hw;
8072 u32 dmac_thr;
8073 u16 hwm;
8074
8075 if (hw->mac.type > e1000_82580) {
8076 if (adapter->flags & IGB_FLAG_DMAC) {
8077 u32 reg;
8078
8079 /* force threshold to 0. */
8080 wr32(E1000_DMCTXTH, 0);
8081
b980ac18 8082 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8083 * than the Rx threshold. Set hwm to PBA - max frame
8084 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8085 */
45693bcb 8086 hwm = 64 * (pba - 6);
e8c626e9
MV		 8087 reg = rd32(E1000_FCRTC);
8088 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8089 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8090 & E1000_FCRTC_RTH_COAL_MASK);
8091 wr32(E1000_FCRTC, reg);
8092
b980ac18 8093 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8094 * frame size, capping it at PBA - 10KB.
8095 */
45693bcb 8096 dmac_thr = pba - 10;
b6e0c419
CW		 8097 reg = rd32(E1000_DMACR);
8098 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8099 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8100 & E1000_DMACR_DMACTHR_MASK);
8101
8102 /* transition to L0x or L1 if available..*/
8103 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8104
8105 /* watchdog timer= +-1000 usec in 32usec intervals */
8106 reg |= (1000 >> 5);
0c02dd98
MV		 8107
8108 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8109 if (hw->mac.type != e1000_i354)
8110 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8111
b6e0c419
CW		 8112 wr32(E1000_DMACR, reg);
8113
b980ac18 8114 /* no lower threshold to disable
b6e0c419
CW		 8115 * coalescing(smart fifb)-UTRESH=0
8116 */
8117 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8118
8119 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8120
8121 wr32(E1000_DMCTLX, reg);
8122
b980ac18 8123 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8124 * DMA coal
8125 */
8126 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8127 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8128
b980ac18 8129 /* make low power state decision controlled
b6e0c419
CW		 8130 * by DMA coal
8131 */
8132 reg = rd32(E1000_PCIEMISC);
8133 reg &= ~E1000_PCIEMISC_LX_DECISION;
8134 wr32(E1000_PCIEMISC, reg);
8135 } /* endif adapter->dmac is not disabled */
8136 } else if (hw->mac.type == e1000_82580) {
8137 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8138
b6e0c419
CW		 8139 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8140 wr32(E1000_DMACR, 0);
8141 }
8142}
8143
b980ac18
JK		 8144/**
8145 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8146 * @hw: pointer to hardware structure
8147 * @byte_offset: byte offset to read
8148 * @dev_addr: device address
8149 * @data: value read
8150 *
8151 * Performs byte read operation over I2C interface at
8152 * a specified device address.
b980ac18 8153 **/
441fc6fd 8154s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8155 u8 dev_addr, u8 *data)
441fc6fd
CW		 8156{
8157 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8158 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8159 s32 status;
8160 u16 swfw_mask = 0;
8161
8162 if (!this_client)
8163 return E1000_ERR_I2C;
8164
8165 swfw_mask = E1000_SWFW_PHY0_SM;
8166
23d87824 8167 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8168 return E1000_ERR_SWFW_SYNC;
8169
8170 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8171 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8172
8173 if (status < 0)
8174 return E1000_ERR_I2C;
8175 else {
8176 *data = status;
23d87824 8177 return 0;
441fc6fd
CW		 8178 }
8179}
8180
b980ac18
JK		 8181/**
8182 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8183 * @hw: pointer to hardware structure
8184 * @byte_offset: byte offset to write
8185 * @dev_addr: device address
8186 * @data: value to write
8187 *
8188 * Performs byte write operation over I2C interface at
8189 * a specified device address.
b980ac18 8190 **/
441fc6fd 8191s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8192 u8 dev_addr, u8 data)
441fc6fd
CW		 8193{
8194 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8195 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8196 s32 status;
8197 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8198
8199 if (!this_client)
8200 return E1000_ERR_I2C;
8201
23d87824 8202 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8203 return E1000_ERR_SWFW_SYNC;
8204 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8205 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8206
8207 if (status)
8208 return E1000_ERR_I2C;
8209 else
23d87824 8210 return 0;
441fc6fd
CW		 8211
8212}
907b7835
LMV		 8213
8214int igb_reinit_queues(struct igb_adapter *adapter)
8215{
8216 struct net_device *netdev = adapter->netdev;
8217 struct pci_dev *pdev = adapter->pdev;
8218 int err = 0;
8219
8220 if (netif_running(netdev))
8221 igb_close(netdev);
8222
02ef6e1d 8223 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8224
8225 if (igb_init_interrupt_scheme(adapter, true)) {
8226 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8227 return -ENOMEM;
8228 }
8229
8230 if (netif_running(netdev))
8231 err = igb_open(netdev);
8232
8233 return err;
8234}
9d5c8243 8235/* igb_main.c */
Linux kernel - Deliverables
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