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[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903
CW		 59#define MAJ 5
60#define MIN 0
66f40b8a 61#define BUILD 5
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 182#endif
9d5c8243 183
9d5c8243 184#ifdef CONFIG_PM
d9dd966d 185#ifdef CONFIG_PM_SLEEP
749ab2cd 186static int igb_suspend(struct device *);
d9dd966d 187#endif
749ab2cd
YZ		 188static int igb_resume(struct device *);
189#ifdef CONFIG_PM_RUNTIME
190static int igb_runtime_suspend(struct device *dev);
191static int igb_runtime_resume(struct device *dev);
192static int igb_runtime_idle(struct device *dev);
193#endif
194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
047e0030 949 struct e1000_hw *hw = &adapter->hw;
52285b76 950 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 951
047e0030 952 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 953 igb_msix_other, 0, netdev->name, adapter);
047e0030 954 if (err)
52285b76 955 goto err_out;
047e0030
AD		 956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
52285b76
SA		 960 vector++;
961
047e0030
AD		 962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
963
0ba82994 964 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
047e0030 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
047e0030 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 972 q_vector->rx.ring->queue_index);
9d5c8243 973 else
047e0030
AD		 974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
9d5c8243 976 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
9d5c8243 979 if (err)
52285b76 980 goto err_free;
9d5c8243
AK		 981 }
982
9d5c8243
AK		 983 igb_configure_msix(adapter);
984 return 0;
52285b76
SA		 985
986err_free:
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995err_out:
9d5c8243
AK		 996 return err;
997}
998
5536d210 999/**
b980ac18
JK		 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
5536d210 1003 *
02ef6e1d 1004 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
02ef6e1d
CW		 1010 adapter->q_vector[v_idx] = NULL;
1011
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
1015 kfree_rcu(q_vector, rcu);
1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
cb06d102
CP		 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
5536d210
AD		 1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
1040 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1041
5536d210
AD		 1042 netif_napi_del(&q_vector->napi);
1043
02ef6e1d
CW		 1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
cd14ef54 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1051 pci_disable_msix(adapter->pdev);
cd14ef54 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1053 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1057}
1058
047e0030 1059/**
b980ac18
JK		 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
047e0030 1062 *
b980ac18
JK		 1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
047e0030
AD		 1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
5536d210
AD		 1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
047e0030 1073 adapter->num_q_vectors = 0;
5536d210 1074
02ef6e1d
CW		 1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
5536d210 1077 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1078 }
047e0030
AD		 1079}
1080
1081/**
b980ac18
JK		 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
047e0030 1084 *
b980ac18
JK		 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
047e0030
AD		 1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
047e0030
AD		 1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
9d5c8243
AK		 1093
1094/**
b980ac18
JK		 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
9d5c8243 1098 *
b980ac18
JK		 1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
9d5c8243 1101 **/
53c7d064 1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1103{
1104 int err;
1105 int numvecs, i;
1106
53c7d064
SA		 1107 if (!msix)
1108 goto msi_only;
cd14ef54 1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1110
83b7180d 1111 /* Number of supported queues. */
a99955fc 1112 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1117
b980ac18 1118 /* start with one vector for every Rx queue */
047e0030
AD		 1119 numvecs = adapter->num_rx_queues;
1120
b980ac18 1121 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
047e0030
AD		 1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
9d5c8243
AK		 1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
479d02df
AG		 1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
0c2cc02e 1138 return;
9d5c8243
AK		 1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
b709323d 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1156 wrfl();
2a3abf6d
AD		 1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
4fc82adf 1161 adapter->vfs_allocated_count = 0;
a99955fc 1162 adapter->rss_queues = 1;
4fc82adf 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1164 adapter->num_rx_queues = 1;
661086df 1165 adapter->num_tx_queues = 1;
047e0030 1166 adapter->num_q_vectors = 1;
9d5c8243 1167 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1168 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1169}
1170
5536d210
AD		 1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
047e0030 1178/**
b980ac18
JK		 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
047e0030 1187 *
b980ac18 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1189 **/
5536d210
AD		 1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
047e0030
AD		 1194{
1195 struct igb_q_vector *q_vector;
5536d210
AD		 1196 struct igb_ring *ring;
1197 int ring_count, size;
047e0030 1198
5536d210
AD		 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
02ef6e1d
CW		 1208 q_vector = adapter->q_vector[v_idx];
1209 if (!q_vector)
1210 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1211 if (!q_vector)
1212 return -ENOMEM;
1213
1214 /* initialize NAPI */
1215 netif_napi_add(adapter->netdev, &q_vector->napi,
1216 igb_poll, 64);
1217
1218 /* tie q_vector and adapter together */
1219 adapter->q_vector[v_idx] = q_vector;
1220 q_vector->adapter = adapter;
1221
1222 /* initialize work limits */
1223 q_vector->tx.work_limit = adapter->tx_work_limit;
1224
1225 /* initialize ITR configuration */
1226 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1227 q_vector->itr_val = IGB_START_ITR;
1228
1229 /* initialize pointer to rings */
1230 ring = q_vector->ring;
1231
4e227667
AD		 1232 /* intialize ITR */
1233 if (rxr_count) {
1234 /* rx or rx/tx vector */
1235 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1236 q_vector->itr_val = adapter->rx_itr_setting;
1237 } else {
1238 /* tx only vector */
1239 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1240 q_vector->itr_val = adapter->tx_itr_setting;
1241 }
1242
5536d210
AD		 1243 if (txr_count) {
1244 /* assign generic ring traits */
1245 ring->dev = &adapter->pdev->dev;
1246 ring->netdev = adapter->netdev;
1247
1248 /* configure backlink on ring */
1249 ring->q_vector = q_vector;
1250
1251 /* update q_vector Tx values */
1252 igb_add_ring(ring, &q_vector->tx);
1253
1254 /* For 82575, context index must be unique per ring. */
1255 if (adapter->hw.mac.type == e1000_82575)
1256 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1257
1258 /* apply Tx specific ring traits */
1259 ring->count = adapter->tx_ring_count;
1260 ring->queue_index = txr_idx;
1261
827da44c
JS		 1262 u64_stats_init(&ring->tx_syncp);
1263 u64_stats_init(&ring->tx_syncp2);
1264
5536d210
AD		 1265 /* assign ring to adapter */
1266 adapter->tx_ring[txr_idx] = ring;
1267
1268 /* push pointer to next ring */
1269 ring++;
047e0030 1270 }
81c2fc22 1271
5536d210
AD		 1272 if (rxr_count) {
1273 /* assign generic ring traits */
1274 ring->dev = &adapter->pdev->dev;
1275 ring->netdev = adapter->netdev;
047e0030 1276
5536d210
AD		 1277 /* configure backlink on ring */
1278 ring->q_vector = q_vector;
047e0030 1279
5536d210
AD		 1280 /* update q_vector Rx values */
1281 igb_add_ring(ring, &q_vector->rx);
047e0030 1282
5536d210
AD		 1283 /* set flag indicating ring supports SCTP checksum offload */
1284 if (adapter->hw.mac.type >= e1000_82576)
1285 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1286
e52c0f96 1287 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1288 * have the tag byte-swapped.
b980ac18 1289 */
5536d210
AD		 1290 if (adapter->hw.mac.type >= e1000_i350)
1291 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1292
5536d210
AD		 1293 /* apply Rx specific ring traits */
1294 ring->count = adapter->rx_ring_count;
1295 ring->queue_index = rxr_idx;
1296
827da44c
JS		 1297 u64_stats_init(&ring->rx_syncp);
1298
5536d210
AD		 1299 /* assign ring to adapter */
1300 adapter->rx_ring[rxr_idx] = ring;
1301 }
1302
1303 return 0;
047e0030
AD		 1304}
1305
5536d210 1306
047e0030 1307/**
b980ac18
JK		 1308 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1309 * @adapter: board private structure to initialize
047e0030 1310 *
b980ac18
JK		 1311 * We allocate one q_vector per queue interrupt. If allocation fails we
1312 * return -ENOMEM.
047e0030 1313 **/
5536d210 1314static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1315{
5536d210
AD		 1316 int q_vectors = adapter->num_q_vectors;
1317 int rxr_remaining = adapter->num_rx_queues;
1318 int txr_remaining = adapter->num_tx_queues;
1319 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1320 int err;
047e0030 1321
5536d210
AD		 1322 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1323 for (; rxr_remaining; v_idx++) {
1324 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1325 0, 0, 1, rxr_idx);
047e0030 1326
5536d210
AD		 1327 if (err)
1328 goto err_out;
1329
1330 /* update counts and index */
1331 rxr_remaining--;
1332 rxr_idx++;
047e0030 1333 }
047e0030 1334 }
5536d210
AD		 1335
1336 for (; v_idx < q_vectors; v_idx++) {
1337 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1338 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1339
5536d210
AD		 1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1341 tqpv, txr_idx, rqpv, rxr_idx);
1342
1343 if (err)
1344 goto err_out;
1345
1346 /* update counts and index */
1347 rxr_remaining -= rqpv;
1348 txr_remaining -= tqpv;
1349 rxr_idx++;
1350 txr_idx++;
1351 }
1352
047e0030 1353 return 0;
5536d210
AD		 1354
1355err_out:
1356 adapter->num_tx_queues = 0;
1357 adapter->num_rx_queues = 0;
1358 adapter->num_q_vectors = 0;
1359
1360 while (v_idx--)
1361 igb_free_q_vector(adapter, v_idx);
1362
1363 return -ENOMEM;
047e0030
AD		 1364}
1365
1366/**
b980ac18
JK		 1367 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1368 * @adapter: board private structure to initialize
1369 * @msix: boolean value of MSIX capability
047e0030 1370 *
b980ac18 1371 * This function initializes the interrupts and allocates all of the queues.
047e0030 1372 **/
53c7d064 1373static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1374{
1375 struct pci_dev *pdev = adapter->pdev;
1376 int err;
1377
53c7d064 1378 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1379
1380 err = igb_alloc_q_vectors(adapter);
1381 if (err) {
1382 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1383 goto err_alloc_q_vectors;
1384 }
1385
5536d210 1386 igb_cache_ring_register(adapter);
047e0030
AD		 1387
1388 return 0;
5536d210 1389
047e0030
AD		 1390err_alloc_q_vectors:
1391 igb_reset_interrupt_capability(adapter);
1392 return err;
1393}
1394
9d5c8243 1395/**
b980ac18
JK		 1396 * igb_request_irq - initialize interrupts
1397 * @adapter: board private structure to initialize
9d5c8243 1398 *
b980ac18
JK		 1399 * Attempts to configure interrupts using the best available
1400 * capabilities of the hardware and kernel.
9d5c8243
AK		 1401 **/
1402static int igb_request_irq(struct igb_adapter *adapter)
1403{
1404 struct net_device *netdev = adapter->netdev;
047e0030 1405 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1406 int err = 0;
1407
cd14ef54 1408 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1409 err = igb_request_msix(adapter);
844290e5 1410 if (!err)
9d5c8243 1411 goto request_done;
9d5c8243 1412 /* fall back to MSI */
5536d210
AD		 1413 igb_free_all_tx_resources(adapter);
1414 igb_free_all_rx_resources(adapter);
53c7d064 1415
047e0030 1416 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1417 err = igb_init_interrupt_scheme(adapter, false);
1418 if (err)
047e0030 1419 goto request_done;
53c7d064 1420
047e0030
AD		 1421 igb_setup_all_tx_resources(adapter);
1422 igb_setup_all_rx_resources(adapter);
53c7d064 1423 igb_configure(adapter);
9d5c8243 1424 }
844290e5 1425
c74d588e
AD		 1426 igb_assign_vector(adapter->q_vector[0], 0);
1427
7dfc16fa 1428 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1429 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1430 netdev->name, adapter);
9d5c8243
AK		 1431 if (!err)
1432 goto request_done;
047e0030 1433
9d5c8243
AK		 1434 /* fall back to legacy interrupts */
1435 igb_reset_interrupt_capability(adapter);
7dfc16fa 1436 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1437 }
1438
c74d588e 1439 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1440 netdev->name, adapter);
9d5c8243 1441
6cb5e577 1442 if (err)
c74d588e 1443 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1444 err);
9d5c8243
AK		 1445
1446request_done:
1447 return err;
1448}
1449
1450static void igb_free_irq(struct igb_adapter *adapter)
1451{
cd14ef54 1452 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1453 int vector = 0, i;
1454
047e0030 1455 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1456
0d1ae7f4 1457 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1458 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1459 adapter->q_vector[i]);
047e0030
AD		 1460 } else {
1461 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1462 }
9d5c8243
AK		 1463}
1464
1465/**
b980ac18
JK		 1466 * igb_irq_disable - Mask off interrupt generation on the NIC
1467 * @adapter: board private structure
9d5c8243
AK		 1468 **/
1469static void igb_irq_disable(struct igb_adapter *adapter)
1470{
1471 struct e1000_hw *hw = &adapter->hw;
1472
b980ac18 1473 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1474 * mapped into these registers and so clearing the bits can cause
1475 * issues on the VF drivers so we only need to clear what we set
1476 */
cd14ef54 1477 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1478 u32 regval = rd32(E1000_EIAM);
9005df38 1479
2dfd1212
AD		 1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1481 wr32(E1000_EIMC, adapter->eims_enable_mask);
1482 regval = rd32(E1000_EIAC);
1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1484 }
844290e5
PW		 1485
1486 wr32(E1000_IAM, 0);
9d5c8243
AK		 1487 wr32(E1000_IMC, ~0);
1488 wrfl();
cd14ef54 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1490 int i;
9005df38 1491
81a61859
ET		 1492 for (i = 0; i < adapter->num_q_vectors; i++)
1493 synchronize_irq(adapter->msix_entries[i].vector);
1494 } else {
1495 synchronize_irq(adapter->pdev->irq);
1496 }
9d5c8243
AK		 1497}
1498
1499/**
b980ac18
JK		 1500 * igb_irq_enable - Enable default interrupt generation settings
1501 * @adapter: board private structure
9d5c8243
AK		 1502 **/
1503static void igb_irq_enable(struct igb_adapter *adapter)
1504{
1505 struct e1000_hw *hw = &adapter->hw;
1506
cd14ef54 1507 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1508 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1509 u32 regval = rd32(E1000_EIAC);
9005df38 1510
2dfd1212
AD		 1511 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1512 regval = rd32(E1000_EIAM);
1513 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1514 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1515 if (adapter->vfs_allocated_count) {
4ae196df 1516 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1517 ims |= E1000_IMS_VMMB;
1518 }
1519 wr32(E1000_IMS, ims);
844290e5 1520 } else {
55cac248
AD		 1521 wr32(E1000_IMS, IMS_ENABLE_MASK |
1522 E1000_IMS_DRSTA);
1523 wr32(E1000_IAM, IMS_ENABLE_MASK |
1524 E1000_IMS_DRSTA);
844290e5 1525 }
9d5c8243
AK		 1526}
1527
1528static void igb_update_mng_vlan(struct igb_adapter *adapter)
1529{
51466239 1530 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1531 u16 vid = adapter->hw.mng_cookie.vlan_id;
1532 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1533
1534 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1535 /* add VID to filter table */
1536 igb_vfta_set(hw, vid, true);
1537 adapter->mng_vlan_id = vid;
1538 } else {
1539 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1540 }
1541
1542 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1543 (vid != old_vid) &&
b2cb09b1 1544 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1545 /* remove VID from filter table */
1546 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1547 }
1548}
1549
1550/**
b980ac18
JK		 1551 * igb_release_hw_control - release control of the h/w to f/w
1552 * @adapter: address of board private structure
9d5c8243 1553 *
b980ac18
JK		 1554 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1555 * For ASF and Pass Through versions of f/w this means that the
1556 * driver is no longer loaded.
9d5c8243
AK		 1557 **/
1558static void igb_release_hw_control(struct igb_adapter *adapter)
1559{
1560 struct e1000_hw *hw = &adapter->hw;
1561 u32 ctrl_ext;
1562
1563 /* Let firmware take over control of h/w */
1564 ctrl_ext = rd32(E1000_CTRL_EXT);
1565 wr32(E1000_CTRL_EXT,
1566 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1567}
1568
9d5c8243 1569/**
b980ac18
JK		 1570 * igb_get_hw_control - get control of the h/w from f/w
1571 * @adapter: address of board private structure
9d5c8243 1572 *
b980ac18
JK		 1573 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1574 * For ASF and Pass Through versions of f/w this means that
1575 * the driver is loaded.
9d5c8243
AK		 1576 **/
1577static void igb_get_hw_control(struct igb_adapter *adapter)
1578{
1579 struct e1000_hw *hw = &adapter->hw;
1580 u32 ctrl_ext;
1581
1582 /* Let firmware know the driver has taken over */
1583 ctrl_ext = rd32(E1000_CTRL_EXT);
1584 wr32(E1000_CTRL_EXT,
1585 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1586}
1587
9d5c8243 1588/**
b980ac18
JK		 1589 * igb_configure - configure the hardware for RX and TX
1590 * @adapter: private board structure
9d5c8243
AK		 1591 **/
1592static void igb_configure(struct igb_adapter *adapter)
1593{
1594 struct net_device *netdev = adapter->netdev;
1595 int i;
1596
1597 igb_get_hw_control(adapter);
ff41f8dc 1598 igb_set_rx_mode(netdev);
9d5c8243
AK		 1599
1600 igb_restore_vlan(adapter);
9d5c8243 1601
85b430b4 1602 igb_setup_tctl(adapter);
06cf2666 1603 igb_setup_mrqc(adapter);
9d5c8243 1604 igb_setup_rctl(adapter);
85b430b4
AD		 1605
1606 igb_configure_tx(adapter);
9d5c8243 1607 igb_configure_rx(adapter);
662d7205
AD		 1608
1609 igb_rx_fifo_flush_82575(&adapter->hw);
1610
c493ea45 1611 /* call igb_desc_unused which always leaves
9d5c8243 1612 * at least 1 descriptor unused to make sure
b980ac18
JK		 1613 * next_to_use != next_to_clean
1614 */
9d5c8243 1615 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1616 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1617 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1618 }
9d5c8243
AK		 1619}
1620
88a268c1 1621/**
b980ac18
JK		 1622 * igb_power_up_link - Power up the phy/serdes link
1623 * @adapter: address of board private structure
88a268c1
NN		 1624 **/
1625void igb_power_up_link(struct igb_adapter *adapter)
1626{
76886596
AA		 1627 igb_reset_phy(&adapter->hw);
1628
88a268c1
NN		 1629 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1630 igb_power_up_phy_copper(&adapter->hw);
1631 else
1632 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1633
1634 igb_setup_link(&adapter->hw);
88a268c1
NN		 1635}
1636
1637/**
b980ac18
JK		 1638 * igb_power_down_link - Power down the phy/serdes link
1639 * @adapter: address of board private structure
88a268c1
NN		 1640 */
1641static void igb_power_down_link(struct igb_adapter *adapter)
1642{
1643 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1644 igb_power_down_phy_copper_82575(&adapter->hw);
1645 else
1646 igb_shutdown_serdes_link_82575(&adapter->hw);
1647}
9d5c8243 1648
56cec249
CW		 1649/**
1650 * Detect and switch function for Media Auto Sense
1651 * @adapter: address of the board private structure
1652 **/
1653static void igb_check_swap_media(struct igb_adapter *adapter)
1654{
1655 struct e1000_hw *hw = &adapter->hw;
1656 u32 ctrl_ext, connsw;
1657 bool swap_now = false;
1658
1659 ctrl_ext = rd32(E1000_CTRL_EXT);
1660 connsw = rd32(E1000_CONNSW);
1661
1662 /* need to live swap if current media is copper and we have fiber/serdes
1663 * to go to.
1664 */
1665
1666 if ((hw->phy.media_type == e1000_media_type_copper) &&
1667 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1668 swap_now = true;
1669 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1670 /* copper signal takes time to appear */
1671 if (adapter->copper_tries < 4) {
1672 adapter->copper_tries++;
1673 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1674 wr32(E1000_CONNSW, connsw);
1675 return;
1676 } else {
1677 adapter->copper_tries = 0;
1678 if ((connsw & E1000_CONNSW_PHYSD) &&
1679 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1680 swap_now = true;
1681 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1682 wr32(E1000_CONNSW, connsw);
1683 }
1684 }
1685 }
1686
1687 if (!swap_now)
1688 return;
1689
1690 switch (hw->phy.media_type) {
1691 case e1000_media_type_copper:
1692 netdev_info(adapter->netdev,
1693 "MAS: changing media to fiber/serdes\n");
1694 ctrl_ext |=
1695 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1696 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1697 adapter->copper_tries = 0;
1698 break;
1699 case e1000_media_type_internal_serdes:
1700 case e1000_media_type_fiber:
1701 netdev_info(adapter->netdev,
1702 "MAS: changing media to copper\n");
1703 ctrl_ext &=
1704 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1705 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1706 break;
1707 default:
1708 /* shouldn't get here during regular operation */
1709 netdev_err(adapter->netdev,
1710 "AMS: Invalid media type found, returning\n");
1711 break;
1712 }
1713 wr32(E1000_CTRL_EXT, ctrl_ext);
1714}
1715
9d5c8243 1716/**
b980ac18
JK		 1717 * igb_up - Open the interface and prepare it to handle traffic
1718 * @adapter: board private structure
9d5c8243 1719 **/
9d5c8243
AK		 1720int igb_up(struct igb_adapter *adapter)
1721{
1722 struct e1000_hw *hw = &adapter->hw;
1723 int i;
1724
1725 /* hardware has been reset, we need to reload some things */
1726 igb_configure(adapter);
1727
1728 clear_bit(__IGB_DOWN, &adapter->state);
1729
0d1ae7f4
AD		 1730 for (i = 0; i < adapter->num_q_vectors; i++)
1731 napi_enable(&(adapter->q_vector[i]->napi));
1732
cd14ef54 1733 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1734 igb_configure_msix(adapter);
feeb2721
AD		 1735 else
1736 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1737
1738 /* Clear any pending interrupts. */
1739 rd32(E1000_ICR);
1740 igb_irq_enable(adapter);
1741
d4960307
AD		 1742 /* notify VFs that reset has been completed */
1743 if (adapter->vfs_allocated_count) {
1744 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1745
d4960307
AD		 1746 reg_data |= E1000_CTRL_EXT_PFRSTD;
1747 wr32(E1000_CTRL_EXT, reg_data);
1748 }
1749
4cb9be7a
JB		 1750 netif_tx_start_all_queues(adapter->netdev);
1751
25568a53
AD		 1752 /* start the watchdog. */
1753 hw->mac.get_link_status = 1;
1754 schedule_work(&adapter->watchdog_task);
1755
f4c01e96
CW		 1756 if ((adapter->flags & IGB_FLAG_EEE) &&
1757 (!hw->dev_spec._82575.eee_disable))
1758 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1759
9d5c8243
AK		 1760 return 0;
1761}
1762
1763void igb_down(struct igb_adapter *adapter)
1764{
9d5c8243 1765 struct net_device *netdev = adapter->netdev;
330a6d6a 1766 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1767 u32 tctl, rctl;
1768 int i;
1769
1770 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1771 * reschedule our watchdog timer
1772 */
9d5c8243
AK		 1773 set_bit(__IGB_DOWN, &adapter->state);
1774
1775 /* disable receives in the hardware */
1776 rctl = rd32(E1000_RCTL);
1777 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1778 /* flush and sleep below */
1779
fd2ea0a7 1780 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1781
1782 /* disable transmits in the hardware */
1783 tctl = rd32(E1000_TCTL);
1784 tctl &= ~E1000_TCTL_EN;
1785 wr32(E1000_TCTL, tctl);
1786 /* flush both disables and wait for them to finish */
1787 wrfl();
0d451e79 1788 usleep_range(10000, 11000);
9d5c8243 1789
41f149a2
CW		 1790 igb_irq_disable(adapter);
1791
aa9b8cc4
AA		 1792 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1793
41f149a2
CW		 1794 for (i = 0; i < adapter->num_q_vectors; i++) {
1795 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1796 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1797 }
9d5c8243 1798
9d5c8243
AK		 1799
1800 del_timer_sync(&adapter->watchdog_timer);
1801 del_timer_sync(&adapter->phy_info_timer);
1802
9d5c8243 1803 netif_carrier_off(netdev);
04fe6358
AD		 1804
1805 /* record the stats before reset*/
12dcd86b
ED		 1806 spin_lock(&adapter->stats64_lock);
1807 igb_update_stats(adapter, &adapter->stats64);
1808 spin_unlock(&adapter->stats64_lock);
04fe6358 1809
9d5c8243
AK		 1810 adapter->link_speed = 0;
1811 adapter->link_duplex = 0;
1812
3023682e
JK		 1813 if (!pci_channel_offline(adapter->pdev))
1814 igb_reset(adapter);
9d5c8243
AK		 1815 igb_clean_all_tx_rings(adapter);
1816 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1817#ifdef CONFIG_IGB_DCA
1818
1819 /* since we reset the hardware DCA settings were cleared */
1820 igb_setup_dca(adapter);
1821#endif
9d5c8243
AK		 1822}
1823
1824void igb_reinit_locked(struct igb_adapter *adapter)
1825{
1826 WARN_ON(in_interrupt());
1827 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1828 usleep_range(1000, 2000);
9d5c8243
AK		 1829 igb_down(adapter);
1830 igb_up(adapter);
1831 clear_bit(__IGB_RESETTING, &adapter->state);
1832}
1833
56cec249
CW		 1834/** igb_enable_mas - Media Autosense re-enable after swap
1835 *
1836 * @adapter: adapter struct
1837 **/
1838static s32 igb_enable_mas(struct igb_adapter *adapter)
1839{
1840 struct e1000_hw *hw = &adapter->hw;
1841 u32 connsw;
1842 s32 ret_val = 0;
1843
1844 connsw = rd32(E1000_CONNSW);
1845 if (!(hw->phy.media_type == e1000_media_type_copper))
1846 return ret_val;
1847
1848 /* configure for SerDes media detect */
1849 if (!(connsw & E1000_CONNSW_SERDESD)) {
1850 connsw |= E1000_CONNSW_ENRGSRC;
1851 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1852 wr32(E1000_CONNSW, connsw);
1853 wrfl();
1854 } else if (connsw & E1000_CONNSW_SERDESD) {
1855 /* already SerDes, no need to enable anything */
1856 return ret_val;
1857 } else {
1858 netdev_info(adapter->netdev,
1859 "MAS: Unable to configure feature, disabling..\n");
1860 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1861 }
1862 return ret_val;
1863}
1864
9d5c8243
AK		 1865void igb_reset(struct igb_adapter *adapter)
1866{
090b1795 1867 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1868 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1869 struct e1000_mac_info *mac = &hw->mac;
1870 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1871 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1872
1873 /* Repartition Pba for greater than 9k mtu
1874 * To take effect CTRL.RST is required.
1875 */
fa4dfae0 1876 switch (mac->type) {
d2ba2ed8 1877 case e1000_i350:
ceb5f13b 1878 case e1000_i354:
55cac248
AD		 1879 case e1000_82580:
1880 pba = rd32(E1000_RXPBS);
1881 pba = igb_rxpbs_adjust_82580(pba);
1882 break;
fa4dfae0 1883 case e1000_82576:
d249be54
AD		 1884 pba = rd32(E1000_RXPBS);
1885 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1886 break;
1887 case e1000_82575:
f96a8a0b
CW		 1888 case e1000_i210:
1889 case e1000_i211:
fa4dfae0
AD		 1890 default:
1891 pba = E1000_PBA_34K;
1892 break;
2d064c06 1893 }
9d5c8243 1894
2d064c06
AD		 1895 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1896 (mac->type < e1000_82576)) {
9d5c8243
AK		 1897 /* adjust PBA for jumbo frames */
1898 wr32(E1000_PBA, pba);
1899
1900 /* To maintain wire speed transmits, the Tx FIFO should be
1901 * large enough to accommodate two full transmit packets,
1902 * rounded up to the next 1KB and expressed in KB. Likewise,
1903 * the Rx FIFO should be large enough to accommodate at least
1904 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1905 * expressed in KB.
1906 */
9d5c8243
AK		 1907 pba = rd32(E1000_PBA);
1908 /* upper 16 bits has Tx packet buffer allocation size in KB */
1909 tx_space = pba >> 16;
1910 /* lower 16 bits has Rx packet buffer allocation size in KB */
1911 pba &= 0xffff;
b980ac18
JK		 1912 /* the Tx fifo also stores 16 bytes of information about the Tx
1913 * but don't include ethernet FCS because hardware appends it
1914 */
9d5c8243 1915 min_tx_space = (adapter->max_frame_size +
85e8d004 1916 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1917 ETH_FCS_LEN) * 2;
1918 min_tx_space = ALIGN(min_tx_space, 1024);
1919 min_tx_space >>= 10;
1920 /* software strips receive CRC, so leave room for it */
1921 min_rx_space = adapter->max_frame_size;
1922 min_rx_space = ALIGN(min_rx_space, 1024);
1923 min_rx_space >>= 10;
1924
1925 /* If current Tx allocation is less than the min Tx FIFO size,
1926 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1927 * allocation, take space away from current Rx allocation
1928 */
9d5c8243
AK		 1929 if (tx_space < min_tx_space &&
1930 ((min_tx_space - tx_space) < pba)) {
1931 pba = pba - (min_tx_space - tx_space);
1932
b980ac18
JK		 1933 /* if short on Rx space, Rx wins and must trump Tx
1934 * adjustment
1935 */
9d5c8243
AK		 1936 if (pba < min_rx_space)
1937 pba = min_rx_space;
1938 }
2d064c06 1939 wr32(E1000_PBA, pba);
9d5c8243 1940 }
9d5c8243
AK		 1941
1942 /* flow control settings */
1943 /* The high water mark must be low enough to fit one full frame
1944 * (or the size used for early receive) above it in the Rx FIFO.
1945 * Set it to the lower of:
1946 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1947 * - the full Rx FIFO size minus one full frame
1948 */
9d5c8243 1949 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1950 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1951
d48507fe 1952 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1953 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1954 fc->pause_time = 0xFFFF;
1955 fc->send_xon = 1;
0cce119a 1956 fc->current_mode = fc->requested_mode;
9d5c8243 1957
4ae196df
AD		 1958 /* disable receive for all VFs and wait one second */
1959 if (adapter->vfs_allocated_count) {
1960 int i;
9005df38 1961
4ae196df 1962 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1963 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1964
1965 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1966 igb_ping_all_vfs(adapter);
4ae196df
AD		 1967
1968 /* disable transmits and receives */
1969 wr32(E1000_VFRE, 0);
1970 wr32(E1000_VFTE, 0);
1971 }
1972
9d5c8243 1973 /* Allow time for pending master requests to run */
330a6d6a 1974 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1975 wr32(E1000_WUC, 0);
1976
56cec249
CW		 1977 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1978 /* need to resetup here after media swap */
1979 adapter->ei.get_invariants(hw);
1980 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1981 }
1982 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1983 if (igb_enable_mas(adapter))
1984 dev_err(&pdev->dev,
1985 "Error enabling Media Auto Sense\n");
1986 }
330a6d6a 1987 if (hw->mac.ops.init_hw(hw))
090b1795 1988 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1989
b980ac18 1990 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1991 * control is off when forcing speed.
1992 */
1993 if (!hw->mac.autoneg)
1994 igb_force_mac_fc(hw);
1995
b6e0c419 1996 igb_init_dmac(adapter, pba);
e428893b
CW		 1997#ifdef CONFIG_IGB_HWMON
1998 /* Re-initialize the thermal sensor on i350 devices. */
1999 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2000 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2001 /* If present, re-initialize the external thermal sensor
2002 * interface.
2003 */
2004 if (adapter->ets)
2005 mac->ops.init_thermal_sensor_thresh(hw);
2006 }
2007 }
2008#endif
b936136d 2009 /* Re-establish EEE setting */
f4c01e96
CW		 2010 if (hw->phy.media_type == e1000_media_type_copper) {
2011 switch (mac->type) {
2012 case e1000_i350:
2013 case e1000_i210:
2014 case e1000_i211:
2015 igb_set_eee_i350(hw);
2016 break;
2017 case e1000_i354:
2018 igb_set_eee_i354(hw);
2019 break;
2020 default:
2021 break;
2022 }
2023 }
88a268c1
NN		 2024 if (!netif_running(adapter->netdev))
2025 igb_power_down_link(adapter);
2026
9d5c8243
AK		 2027 igb_update_mng_vlan(adapter);
2028
2029 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2030 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2031
1f6e8178
MV		 2032 /* Re-enable PTP, where applicable. */
2033 igb_ptp_reset(adapter);
1f6e8178 2034
330a6d6a 2035 igb_get_phy_info(hw);
9d5c8243
AK		 2036}
2037
c8f44aff
MM		 2038static netdev_features_t igb_fix_features(struct net_device *netdev,
2039 netdev_features_t features)
b2cb09b1 2040{
b980ac18
JK		 2041 /* Since there is no support for separate Rx/Tx vlan accel
2042 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2043 */
f646968f
PM		 2044 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2045 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2046 else
f646968f 2047 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2048
2049 return features;
2050}
2051
c8f44aff
MM		 2052static int igb_set_features(struct net_device *netdev,
2053 netdev_features_t features)
ac52caa3 2054{
c8f44aff 2055 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2056 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2057
f646968f 2058 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2059 igb_vlan_mode(netdev, features);
2060
89eaefb6
BG		 2061 if (!(changed & NETIF_F_RXALL))
2062 return 0;
2063
2064 netdev->features = features;
2065
2066 if (netif_running(netdev))
2067 igb_reinit_locked(adapter);
2068 else
2069 igb_reset(adapter);
2070
ac52caa3
MM		 2071 return 0;
2072}
2073
2e5c6922 2074static const struct net_device_ops igb_netdev_ops = {
559e9c49 2075 .ndo_open = igb_open,
2e5c6922 2076 .ndo_stop = igb_close,
cd392f5c 2077 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2078 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2079 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2080 .ndo_set_mac_address = igb_set_mac,
2081 .ndo_change_mtu = igb_change_mtu,
2082 .ndo_do_ioctl = igb_ioctl,
2083 .ndo_tx_timeout = igb_tx_timeout,
2084 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2085 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2086 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2087 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2088 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2089 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2090 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2091 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2092#ifdef CONFIG_NET_POLL_CONTROLLER
2093 .ndo_poll_controller = igb_netpoll,
2094#endif
b2cb09b1
JP		 2095 .ndo_fix_features = igb_fix_features,
2096 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2097};
2098
d67974f0
CW		 2099/**
2100 * igb_set_fw_version - Configure version string for ethtool
2101 * @adapter: adapter struct
d67974f0
CW		 2102 **/
2103void igb_set_fw_version(struct igb_adapter *adapter)
2104{
2105 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2106 struct e1000_fw_version fw;
2107
2108 igb_get_fw_version(hw, &fw);
2109
2110 switch (hw->mac.type) {
7dc98a62 2111 case e1000_i210:
0b1a6f2e 2112 case e1000_i211:
7dc98a62
CW		 2113 if (!(igb_get_flash_presence_i210(hw))) {
2114 snprintf(adapter->fw_version,
2115 sizeof(adapter->fw_version),
2116 "%2d.%2d-%d",
2117 fw.invm_major, fw.invm_minor,
2118 fw.invm_img_type);
2119 break;
2120 }
2121 /* fall through */
0b1a6f2e
CW		 2122 default:
2123 /* if option is rom valid, display its version too */
2124 if (fw.or_valid) {
2125 snprintf(adapter->fw_version,
2126 sizeof(adapter->fw_version),
2127 "%d.%d, 0x%08x, %d.%d.%d",
2128 fw.eep_major, fw.eep_minor, fw.etrack_id,
2129 fw.or_major, fw.or_build, fw.or_patch);
2130 /* no option rom */
7dc98a62 2131 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2132 snprintf(adapter->fw_version,
7dc98a62
CW		 2133 sizeof(adapter->fw_version),
2134 "%d.%d, 0x%08x",
2135 fw.eep_major, fw.eep_minor, fw.etrack_id);
2136 } else {
2137 snprintf(adapter->fw_version,
2138 sizeof(adapter->fw_version),
2139 "%d.%d.%d",
2140 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2141 }
2142 break;
d67974f0 2143 }
d67974f0
CW		 2144}
2145
56cec249
CW		 2146/**
2147 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2148 *
2149 * @adapter: adapter struct
2150 **/
2151static void igb_init_mas(struct igb_adapter *adapter)
2152{
2153 struct e1000_hw *hw = &adapter->hw;
2154 u16 eeprom_data;
2155
2156 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2157 switch (hw->bus.func) {
2158 case E1000_FUNC_0:
2159 if (eeprom_data & IGB_MAS_ENABLE_0) {
2160 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2161 netdev_info(adapter->netdev,
2162 "MAS: Enabling Media Autosense for port %d\n",
2163 hw->bus.func);
2164 }
2165 break;
2166 case E1000_FUNC_1:
2167 if (eeprom_data & IGB_MAS_ENABLE_1) {
2168 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2169 netdev_info(adapter->netdev,
2170 "MAS: Enabling Media Autosense for port %d\n",
2171 hw->bus.func);
2172 }
2173 break;
2174 case E1000_FUNC_2:
2175 if (eeprom_data & IGB_MAS_ENABLE_2) {
2176 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2177 netdev_info(adapter->netdev,
2178 "MAS: Enabling Media Autosense for port %d\n",
2179 hw->bus.func);
2180 }
2181 break;
2182 case E1000_FUNC_3:
2183 if (eeprom_data & IGB_MAS_ENABLE_3) {
2184 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2185 netdev_info(adapter->netdev,
2186 "MAS: Enabling Media Autosense for port %d\n",
2187 hw->bus.func);
2188 }
2189 break;
2190 default:
2191 /* Shouldn't get here */
2192 netdev_err(adapter->netdev,
2193 "MAS: Invalid port configuration, returning\n");
2194 break;
2195 }
2196}
2197
b980ac18
JK		 2198/**
2199 * igb_init_i2c - Init I2C interface
441fc6fd 2200 * @adapter: pointer to adapter structure
b980ac18 2201 **/
441fc6fd
CW		 2202static s32 igb_init_i2c(struct igb_adapter *adapter)
2203{
23d87824 2204 s32 status = 0;
441fc6fd
CW		 2205
2206 /* I2C interface supported on i350 devices */
2207 if (adapter->hw.mac.type != e1000_i350)
23d87824 2208 return 0;
441fc6fd
CW		 2209
2210 /* Initialize the i2c bus which is controlled by the registers.
2211 * This bus will use the i2c_algo_bit structue that implements
2212 * the protocol through toggling of the 4 bits in the register.
2213 */
2214 adapter->i2c_adap.owner = THIS_MODULE;
2215 adapter->i2c_algo = igb_i2c_algo;
2216 adapter->i2c_algo.data = adapter;
2217 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2218 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2219 strlcpy(adapter->i2c_adap.name, "igb BB",
2220 sizeof(adapter->i2c_adap.name));
2221 status = i2c_bit_add_bus(&adapter->i2c_adap);
2222 return status;
2223}
2224
9d5c8243 2225/**
b980ac18
JK		 2226 * igb_probe - Device Initialization Routine
2227 * @pdev: PCI device information struct
2228 * @ent: entry in igb_pci_tbl
9d5c8243 2229 *
b980ac18 2230 * Returns 0 on success, negative on failure
9d5c8243 2231 *
b980ac18
JK		 2232 * igb_probe initializes an adapter identified by a pci_dev structure.
2233 * The OS initialization, configuring of the adapter private structure,
2234 * and a hardware reset occur.
9d5c8243 2235 **/
1dd06ae8 2236static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2237{
2238 struct net_device *netdev;
2239 struct igb_adapter *adapter;
2240 struct e1000_hw *hw;
4337e993 2241 u16 eeprom_data = 0;
9835fd73 2242 s32 ret_val;
4337e993 2243 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2244 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2245 int err, pci_using_dac;
9835fd73 2246 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2247
bded64a7
AG		 2248 /* Catch broken hardware that put the wrong VF device ID in
2249 * the PCIe SR-IOV capability.
2250 */
2251 if (pdev->is_virtfn) {
2252 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2253 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2254 return -EINVAL;
2255 }
2256
aed5dec3 2257 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2258 if (err)
2259 return err;
2260
2261 pci_using_dac = 0;
dc4ff9bb 2262 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2263 if (!err) {
dc4ff9bb 2264 pci_using_dac = 1;
9d5c8243 2265 } else {
dc4ff9bb 2266 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2267 if (err) {
dc4ff9bb
RK		 2268 dev_err(&pdev->dev,
2269 "No usable DMA configuration, aborting\n");
2270 goto err_dma;
9d5c8243
AK		 2271 }
2272 }
2273
aed5dec3 2274 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2275 IORESOURCE_MEM),
2276 igb_driver_name);
9d5c8243
AK		 2277 if (err)
2278 goto err_pci_reg;
2279
19d5afd4 2280 pci_enable_pcie_error_reporting(pdev);
40a914fa 2281
9d5c8243 2282 pci_set_master(pdev);
c682fc23 2283 pci_save_state(pdev);
9d5c8243
AK		 2284
2285 err = -ENOMEM;
1bfaf07b 2286 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2287 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2288 if (!netdev)
2289 goto err_alloc_etherdev;
2290
2291 SET_NETDEV_DEV(netdev, &pdev->dev);
2292
2293 pci_set_drvdata(pdev, netdev);
2294 adapter = netdev_priv(netdev);
2295 adapter->netdev = netdev;
2296 adapter->pdev = pdev;
2297 hw = &adapter->hw;
2298 hw->back = adapter;
b3f4d599 2299 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2300
9d5c8243 2301 err = -EIO;
89dbefb2 2302 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2303 if (!hw->hw_addr)
9d5c8243
AK		 2304 goto err_ioremap;
2305
2e5c6922 2306 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2307 igb_set_ethtool_ops(netdev);
9d5c8243 2308 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2309
2310 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2311
89dbefb2
AS		 2312 netdev->mem_start = pci_resource_start(pdev, 0);
2313 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2314
9d5c8243
AK		 2315 /* PCI config space info */
2316 hw->vendor_id = pdev->vendor;
2317 hw->device_id = pdev->device;
2318 hw->revision_id = pdev->revision;
2319 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2320 hw->subsystem_device_id = pdev->subsystem_device;
2321
9d5c8243
AK		 2322 /* Copy the default MAC, PHY and NVM function pointers */
2323 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2324 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2325 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2326 /* Initialize skew-specific constants */
2327 err = ei->get_invariants(hw);
2328 if (err)
450c87c8 2329 goto err_sw_init;
9d5c8243 2330
450c87c8 2331 /* setup the private structure */
9d5c8243
AK		 2332 err = igb_sw_init(adapter);
2333 if (err)
2334 goto err_sw_init;
2335
2336 igb_get_bus_info_pcie(hw);
2337
2338 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2339
2340 /* Copper options */
2341 if (hw->phy.media_type == e1000_media_type_copper) {
2342 hw->phy.mdix = AUTO_ALL_MODES;
2343 hw->phy.disable_polarity_correction = false;
2344 hw->phy.ms_type = e1000_ms_hw_default;
2345 }
2346
2347 if (igb_check_reset_block(hw))
2348 dev_info(&pdev->dev,
2349 "PHY reset is blocked due to SOL/IDER session.\n");
2350
b980ac18 2351 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2352 * set by igb_sw_init so we should use an or instead of an
2353 * assignment.
2354 */
2355 netdev->features |= NETIF_F_SG |
2356 NETIF_F_IP_CSUM |
2357 NETIF_F_IPV6_CSUM |
2358 NETIF_F_TSO |
2359 NETIF_F_TSO6 |
2360 NETIF_F_RXHASH |
2361 NETIF_F_RXCSUM |
f646968f
PM		 2362 NETIF_F_HW_VLAN_CTAG_RX |
2363 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2364
2365 /* copy netdev features into list of user selectable features */
2366 netdev->hw_features |= netdev->features;
89eaefb6 2367 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2368
2369 /* set this bit last since it cannot be part of hw_features */
f646968f 2370 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2371
2372 netdev->vlan_features |= NETIF_F_TSO |
2373 NETIF_F_TSO6 |
2374 NETIF_F_IP_CSUM |
2375 NETIF_F_IPV6_CSUM |
2376 NETIF_F_SG;
48f29ffc 2377
6b8f0922
BG		 2378 netdev->priv_flags |= IFF_SUPP_NOFCS;
2379
7b872a55 2380 if (pci_using_dac) {
9d5c8243 2381 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2382 netdev->vlan_features |= NETIF_F_HIGHDMA;
2383 }
9d5c8243 2384
ac52caa3
MM		 2385 if (hw->mac.type >= e1000_82576) {
2386 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2387 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2388 }
b9473560 2389
01789349
JP		 2390 netdev->priv_flags |= IFF_UNICAST_FLT;
2391
330a6d6a 2392 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2393
2394 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2395 * known good starting state
2396 */
9d5c8243
AK		 2397 hw->mac.ops.reset_hw(hw);
2398
ef3a0092
CW		 2399 /* make sure the NVM is good , i211/i210 parts can have special NVM
2400 * that doesn't contain a checksum
f96a8a0b 2401 */
ef3a0092
CW		 2402 switch (hw->mac.type) {
2403 case e1000_i210:
2404 case e1000_i211:
2405 if (igb_get_flash_presence_i210(hw)) {
2406 if (hw->nvm.ops.validate(hw) < 0) {
2407 dev_err(&pdev->dev,
2408 "The NVM Checksum Is Not Valid\n");
2409 err = -EIO;
2410 goto err_eeprom;
2411 }
2412 }
2413 break;
2414 default:
f96a8a0b
CW		 2415 if (hw->nvm.ops.validate(hw) < 0) {
2416 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2417 err = -EIO;
2418 goto err_eeprom;
2419 }
ef3a0092 2420 break;
9d5c8243
AK		 2421 }
2422
2423 /* copy the MAC address out of the NVM */
2424 if (hw->mac.ops.read_mac_addr(hw))
2425 dev_err(&pdev->dev, "NVM Read Error\n");
2426
2427 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2428
aaeb6cdf 2429 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2430 dev_err(&pdev->dev, "Invalid MAC Address\n");
2431 err = -EIO;
2432 goto err_eeprom;
2433 }
2434
d67974f0
CW		 2435 /* get firmware version for ethtool -i */
2436 igb_set_fw_version(adapter);
2437
27dff8b2
TF		 2438 /* configure RXPBSIZE and TXPBSIZE */
2439 if (hw->mac.type == e1000_i210) {
2440 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2441 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2442 }
2443
c061b18d 2444 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2445 (unsigned long) adapter);
c061b18d 2446 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2447 (unsigned long) adapter);
9d5c8243
AK		 2448
2449 INIT_WORK(&adapter->reset_task, igb_reset_task);
2450 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2451
450c87c8 2452 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2453 adapter->fc_autoneg = true;
2454 hw->mac.autoneg = true;
2455 hw->phy.autoneg_advertised = 0x2f;
2456
0cce119a
AD		 2457 hw->fc.requested_mode = e1000_fc_default;
2458 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2459
9d5c8243
AK		 2460 igb_validate_mdi_setting(hw);
2461
63d4a8f9 2462 /* By default, support wake on port A */
a2cf8b6c 2463 if (hw->bus.func == 0)
63d4a8f9
MV		 2464 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2465
2466 /* Check the NVM for wake support on non-port A ports */
2467 if (hw->mac.type >= e1000_82580)
55cac248 2468 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2469 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2470 &eeprom_data);
a2cf8b6c
AD		 2471 else if (hw->bus.func == 1)
2472 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2473
63d4a8f9
MV		 2474 if (eeprom_data & IGB_EEPROM_APME)
2475 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2476
2477 /* now that we have the eeprom settings, apply the special cases where
2478 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2479 * lan on a particular port
2480 */
9d5c8243
AK		 2481 switch (pdev->device) {
2482 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2483 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2484 break;
2485 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2486 case E1000_DEV_ID_82576_FIBER:
2487 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2488 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2489 * regardless of eeprom setting
2490 */
9d5c8243 2491 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2492 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2493 break;
c8ea5ea9 2494 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2495 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2496 /* if quad port adapter, disable WoL on all but port A */
2497 if (global_quad_port_a != 0)
63d4a8f9 2498 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2499 else
2500 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2501 /* Reset for multiple quad port adapters */
2502 if (++global_quad_port_a == 4)
2503 global_quad_port_a = 0;
2504 break;
63d4a8f9
MV		 2505 default:
2506 /* If the device can't wake, don't set software support */
2507 if (!device_can_wakeup(&adapter->pdev->dev))
2508 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2509 }
2510
2511 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2512 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2513 adapter->wol |= E1000_WUFC_MAG;
2514
2515 /* Some vendors want WoL disabled by default, but still supported */
2516 if ((hw->mac.type == e1000_i350) &&
2517 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2518 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2519 adapter->wol = 0;
2520 }
2521
2522 device_set_wakeup_enable(&adapter->pdev->dev,
2523 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2524
2525 /* reset the hardware with the new settings */
2526 igb_reset(adapter);
2527
441fc6fd
CW		 2528 /* Init the I2C interface */
2529 err = igb_init_i2c(adapter);
2530 if (err) {
2531 dev_err(&pdev->dev, "failed to init i2c interface\n");
2532 goto err_eeprom;
2533 }
2534
9d5c8243 2535 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2536 * driver.
2537 */
9d5c8243
AK		 2538 igb_get_hw_control(adapter);
2539
9d5c8243
AK		 2540 strcpy(netdev->name, "eth%d");
2541 err = register_netdev(netdev);
2542 if (err)
2543 goto err_register;
2544
b168dfc5
JB		 2545 /* carrier off reporting is important to ethtool even BEFORE open */
2546 netif_carrier_off(netdev);
2547
421e02f0 2548#ifdef CONFIG_IGB_DCA
bbd98fe4 2549 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2550 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2551 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2552 igb_setup_dca(adapter);
2553 }
fe4506b6 2554
38c845c7 2555#endif
e428893b
CW		 2556#ifdef CONFIG_IGB_HWMON
2557 /* Initialize the thermal sensor on i350 devices. */
2558 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2559 u16 ets_word;
3c89f6d0 2560
b980ac18 2561 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2562 * external thermal sensor.
2563 */
2564 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2565 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2566 adapter->ets = true;
2567 else
2568 adapter->ets = false;
2569 if (igb_sysfs_init(adapter))
2570 dev_err(&pdev->dev,
2571 "failed to allocate sysfs resources\n");
2572 } else {
2573 adapter->ets = false;
2574 }
2575#endif
56cec249
CW		 2576 /* Check if Media Autosense is enabled */
2577 adapter->ei = *ei;
2578 if (hw->dev_spec._82575.mas_capable)
2579 igb_init_mas(adapter);
2580
673b8b70 2581 /* do hw tstamp init after resetting */
7ebae817 2582 igb_ptp_init(adapter);
673b8b70 2583
9d5c8243 2584 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2585 /* print bus type/speed/width info, not applicable to i354 */
2586 if (hw->mac.type != e1000_i354) {
2587 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2588 netdev->name,
2589 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2590 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2591 "unknown"),
2592 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2593 "Width x4" :
2594 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2595 "Width x2" :
2596 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2597 "Width x1" : "unknown"), netdev->dev_addr);
2598 }
9d5c8243 2599
53ea6c7e
TF		 2600 if ((hw->mac.type >= e1000_i210 ||
2601 igb_get_flash_presence_i210(hw))) {
2602 ret_val = igb_read_part_string(hw, part_str,
2603 E1000_PBANUM_LENGTH);
2604 } else {
2605 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2606 }
2607
9835fd73
CW		 2608 if (ret_val)
2609 strcpy(part_str, "Unknown");
2610 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2611 dev_info(&pdev->dev,
2612 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2613 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2614 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2615 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2616 if (hw->phy.media_type == e1000_media_type_copper) {
2617 switch (hw->mac.type) {
2618 case e1000_i350:
2619 case e1000_i210:
2620 case e1000_i211:
2621 /* Enable EEE for internal copper PHY devices */
2622 err = igb_set_eee_i350(hw);
2623 if ((!err) &&
2624 (!hw->dev_spec._82575.eee_disable)) {
2625 adapter->eee_advert =
2626 MDIO_EEE_100TX | MDIO_EEE_1000T;
2627 adapter->flags |= IGB_FLAG_EEE;
2628 }
2629 break;
2630 case e1000_i354:
ceb5f13b 2631 if ((rd32(E1000_CTRL_EXT) &
f4c01e96
CW		 2632 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2633 err = igb_set_eee_i354(hw);
2634 if ((!err) &&
2635 (!hw->dev_spec._82575.eee_disable)) {
2636 adapter->eee_advert =
2637 MDIO_EEE_100TX | MDIO_EEE_1000T;
2638 adapter->flags |= IGB_FLAG_EEE;
2639 }
2640 }
2641 break;
2642 default:
2643 break;
ceb5f13b 2644 }
09b068d4 2645 }
749ab2cd 2646 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2647 return 0;
2648
2649err_register:
2650 igb_release_hw_control(adapter);
441fc6fd 2651 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2652err_eeprom:
2653 if (!igb_check_reset_block(hw))
f5f4cf08 2654 igb_reset_phy(hw);
9d5c8243
AK		 2655
2656 if (hw->flash_address)
2657 iounmap(hw->flash_address);
9d5c8243 2658err_sw_init:
047e0030 2659 igb_clear_interrupt_scheme(adapter);
75009b3a 2660 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2661err_ioremap:
2662 free_netdev(netdev);
2663err_alloc_etherdev:
559e9c49 2664 pci_release_selected_regions(pdev,
b980ac18 2665 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2666err_pci_reg:
2667err_dma:
2668 pci_disable_device(pdev);
2669 return err;
2670}
2671
fa44f2f1 2672#ifdef CONFIG_PCI_IOV
781798a1 2673static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2674{
2675 struct net_device *netdev = pci_get_drvdata(pdev);
2676 struct igb_adapter *adapter = netdev_priv(netdev);
2677 struct e1000_hw *hw = &adapter->hw;
2678
2679 /* reclaim resources allocated to VFs */
2680 if (adapter->vf_data) {
2681 /* disable iov and allow time for transactions to clear */
b09186d2 2682 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2683 dev_warn(&pdev->dev,
2684 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2685 return -EPERM;
2686 } else {
2687 pci_disable_sriov(pdev);
2688 msleep(500);
2689 }
2690
2691 kfree(adapter->vf_data);
2692 adapter->vf_data = NULL;
2693 adapter->vfs_allocated_count = 0;
2694 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2695 wrfl();
2696 msleep(100);
2697 dev_info(&pdev->dev, "IOV Disabled\n");
2698
2699 /* Re-enable DMA Coalescing flag since IOV is turned off */
2700 adapter->flags |= IGB_FLAG_DMAC;
2701 }
2702
2703 return 0;
2704}
2705
2706static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2707{
2708 struct net_device *netdev = pci_get_drvdata(pdev);
2709 struct igb_adapter *adapter = netdev_priv(netdev);
2710 int old_vfs = pci_num_vf(pdev);
2711 int err = 0;
2712 int i;
2713
cd14ef54 2714 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2715 err = -EPERM;
2716 goto out;
2717 }
fa44f2f1
GR		 2718 if (!num_vfs)
2719 goto out;
fa44f2f1 2720
781798a1
SA		 2721 if (old_vfs) {
2722 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2723 old_vfs, max_vfs);
2724 adapter->vfs_allocated_count = old_vfs;
2725 } else
2726 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2727
2728 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2729 sizeof(struct vf_data_storage), GFP_KERNEL);
2730
2731 /* if allocation failed then we do not support SR-IOV */
2732 if (!adapter->vf_data) {
2733 adapter->vfs_allocated_count = 0;
2734 dev_err(&pdev->dev,
2735 "Unable to allocate memory for VF Data Storage\n");
2736 err = -ENOMEM;
2737 goto out;
2738 }
2739
781798a1
SA		 2740 /* only call pci_enable_sriov() if no VFs are allocated already */
2741 if (!old_vfs) {
2742 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2743 if (err)
2744 goto err_out;
2745 }
fa44f2f1
GR		 2746 dev_info(&pdev->dev, "%d VFs allocated\n",
2747 adapter->vfs_allocated_count);
2748 for (i = 0; i < adapter->vfs_allocated_count; i++)
2749 igb_vf_configure(adapter, i);
2750
2751 /* DMA Coalescing is not supported in IOV mode. */
2752 adapter->flags &= ~IGB_FLAG_DMAC;
2753 goto out;
2754
2755err_out:
2756 kfree(adapter->vf_data);
2757 adapter->vf_data = NULL;
2758 adapter->vfs_allocated_count = 0;
2759out:
2760 return err;
2761}
2762
2763#endif
b980ac18 2764/**
441fc6fd
CW		 2765 * igb_remove_i2c - Cleanup I2C interface
2766 * @adapter: pointer to adapter structure
b980ac18 2767 **/
441fc6fd
CW		 2768static void igb_remove_i2c(struct igb_adapter *adapter)
2769{
441fc6fd
CW		 2770 /* free the adapter bus structure */
2771 i2c_del_adapter(&adapter->i2c_adap);
2772}
2773
9d5c8243 2774/**
b980ac18
JK		 2775 * igb_remove - Device Removal Routine
2776 * @pdev: PCI device information struct
9d5c8243 2777 *
b980ac18
JK		 2778 * igb_remove is called by the PCI subsystem to alert the driver
2779 * that it should release a PCI device. The could be caused by a
2780 * Hot-Plug event, or because the driver is going to be removed from
2781 * memory.
9d5c8243 2782 **/
9f9a12f8 2783static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2784{
2785 struct net_device *netdev = pci_get_drvdata(pdev);
2786 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2787 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2788
749ab2cd 2789 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2790#ifdef CONFIG_IGB_HWMON
2791 igb_sysfs_exit(adapter);
2792#endif
441fc6fd 2793 igb_remove_i2c(adapter);
a79f4f88 2794 igb_ptp_stop(adapter);
b980ac18 2795 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2796 * disable watchdog from being rescheduled.
2797 */
9d5c8243
AK		 2798 set_bit(__IGB_DOWN, &adapter->state);
2799 del_timer_sync(&adapter->watchdog_timer);
2800 del_timer_sync(&adapter->phy_info_timer);
2801
760141a5
TH		 2802 cancel_work_sync(&adapter->reset_task);
2803 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2804
421e02f0 2805#ifdef CONFIG_IGB_DCA
7dfc16fa 2806 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2807 dev_info(&pdev->dev, "DCA disabled\n");
2808 dca_remove_requester(&pdev->dev);
7dfc16fa 2809 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2810 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2811 }
2812#endif
2813
9d5c8243 2814 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2815 * would have already happened in close and is redundant.
2816 */
9d5c8243
AK		 2817 igb_release_hw_control(adapter);
2818
2819 unregister_netdev(netdev);
2820
047e0030 2821 igb_clear_interrupt_scheme(adapter);
9d5c8243 2822
37680117 2823#ifdef CONFIG_PCI_IOV
fa44f2f1 2824 igb_disable_sriov(pdev);
37680117 2825#endif
559e9c49 2826
75009b3a 2827 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2828 if (hw->flash_address)
2829 iounmap(hw->flash_address);
559e9c49 2830 pci_release_selected_regions(pdev,
b980ac18 2831 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2832
1128c756 2833 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2834 free_netdev(netdev);
2835
19d5afd4 2836 pci_disable_pcie_error_reporting(pdev);
40a914fa 2837
9d5c8243
AK		 2838 pci_disable_device(pdev);
2839}
2840
a6b623e0 2841/**
b980ac18
JK		 2842 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2843 * @adapter: board private structure to initialize
a6b623e0 2844 *
b980ac18
JK		 2845 * This function initializes the vf specific data storage and then attempts to
2846 * allocate the VFs. The reason for ordering it this way is because it is much
2847 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2848 * the memory for the VFs.
a6b623e0 2849 **/
9f9a12f8 2850static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2851{
2852#ifdef CONFIG_PCI_IOV
2853 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2854 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2855
f96a8a0b
CW		 2856 /* Virtualization features not supported on i210 family. */
2857 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2858 return;
2859
fa44f2f1 2860 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2861 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2862
a6b623e0
AD		 2863#endif /* CONFIG_PCI_IOV */
2864}
2865
fa44f2f1 2866static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2867{
2868 struct e1000_hw *hw = &adapter->hw;
374a542d 2869 u32 max_rss_queues;
9d5c8243 2870
374a542d 2871 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2872 switch (hw->mac.type) {
374a542d
MV		 2873 case e1000_i211:
2874 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2875 break;
2876 case e1000_82575:
f96a8a0b 2877 case e1000_i210:
374a542d
MV		 2878 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2879 break;
2880 case e1000_i350:
2881 /* I350 cannot do RSS and SR-IOV at the same time */
2882 if (!!adapter->vfs_allocated_count) {
2883 max_rss_queues = 1;
2884 break;
2885 }
2886 /* fall through */
2887 case e1000_82576:
2888 if (!!adapter->vfs_allocated_count) {
2889 max_rss_queues = 2;
2890 break;
2891 }
2892 /* fall through */
2893 case e1000_82580:
ceb5f13b 2894 case e1000_i354:
374a542d
MV		 2895 default:
2896 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2897 break;
374a542d
MV		 2898 }
2899
2900 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2901
2902 /* Determine if we need to pair queues. */
2903 switch (hw->mac.type) {
2904 case e1000_82575:
f96a8a0b 2905 case e1000_i211:
374a542d 2906 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2907 break;
374a542d 2908 case e1000_82576:
b980ac18 2909 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2910 * should pair the queues in order to conserve interrupts due
2911 * to limited supply.
2912 */
2913 if ((adapter->rss_queues > 1) &&
2914 (adapter->vfs_allocated_count > 6))
2915 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2916 /* fall through */
2917 case e1000_82580:
2918 case e1000_i350:
ceb5f13b 2919 case e1000_i354:
374a542d 2920 case e1000_i210:
f96a8a0b 2921 default:
b980ac18 2922 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2923 * order to conserve interrupts due to limited supply.
2924 */
2925 if (adapter->rss_queues > (max_rss_queues / 2))
2926 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2927 break;
2928 }
fa44f2f1
GR		 2929}
2930
2931/**
b980ac18
JK		 2932 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2933 * @adapter: board private structure to initialize
fa44f2f1 2934 *
b980ac18
JK		 2935 * igb_sw_init initializes the Adapter private data structure.
2936 * Fields are initialized based on PCI device information and
2937 * OS network device settings (MTU size).
fa44f2f1
GR		 2938 **/
2939static int igb_sw_init(struct igb_adapter *adapter)
2940{
2941 struct e1000_hw *hw = &adapter->hw;
2942 struct net_device *netdev = adapter->netdev;
2943 struct pci_dev *pdev = adapter->pdev;
2944
2945 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2946
2947 /* set default ring sizes */
2948 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2949 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2950
2951 /* set default ITR values */
2952 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2953 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2954
2955 /* set default work limits */
2956 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2957
2958 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2959 VLAN_HLEN;
2960 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2961
2962 spin_lock_init(&adapter->stats64_lock);
2963#ifdef CONFIG_PCI_IOV
2964 switch (hw->mac.type) {
2965 case e1000_82576:
2966 case e1000_i350:
2967 if (max_vfs > 7) {
2968 dev_warn(&pdev->dev,
2969 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2970 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2971 } else
2972 adapter->vfs_allocated_count = max_vfs;
2973 if (adapter->vfs_allocated_count)
2974 dev_warn(&pdev->dev,
2975 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2976 break;
2977 default:
2978 break;
2979 }
2980#endif /* CONFIG_PCI_IOV */
2981
2982 igb_init_queue_configuration(adapter);
a99955fc 2983
1128c756 2984 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2985 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2986 GFP_ATOMIC);
1128c756 2987
a6b623e0 2988 /* This call may decrease the number of queues */
53c7d064 2989 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2990 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2991 return -ENOMEM;
2992 }
2993
a6b623e0
AD		 2994 igb_probe_vfs(adapter);
2995
9d5c8243
AK		 2996 /* Explicitly disable IRQ since the NIC can be in any state. */
2997 igb_irq_disable(adapter);
2998
f96a8a0b 2999 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3000 adapter->flags &= ~IGB_FLAG_DMAC;
3001
9d5c8243
AK		 3002 set_bit(__IGB_DOWN, &adapter->state);
3003 return 0;
3004}
3005
3006/**
b980ac18
JK		 3007 * igb_open - Called when a network interface is made active
3008 * @netdev: network interface device structure
9d5c8243 3009 *
b980ac18 3010 * Returns 0 on success, negative value on failure
9d5c8243 3011 *
b980ac18
JK		 3012 * The open entry point is called when a network interface is made
3013 * active by the system (IFF_UP). At this point all resources needed
3014 * for transmit and receive operations are allocated, the interrupt
3015 * handler is registered with the OS, the watchdog timer is started,
3016 * and the stack is notified that the interface is ready.
9d5c8243 3017 **/
749ab2cd 3018static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3019{
3020 struct igb_adapter *adapter = netdev_priv(netdev);
3021 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3022 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3023 int err;
3024 int i;
3025
3026 /* disallow open during test */
749ab2cd
YZ		 3027 if (test_bit(__IGB_TESTING, &adapter->state)) {
3028 WARN_ON(resuming);
9d5c8243 3029 return -EBUSY;
749ab2cd
YZ		 3030 }
3031
3032 if (!resuming)
3033 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3034
b168dfc5
JB		 3035 netif_carrier_off(netdev);
3036
9d5c8243
AK		 3037 /* allocate transmit descriptors */
3038 err = igb_setup_all_tx_resources(adapter);
3039 if (err)
3040 goto err_setup_tx;
3041
3042 /* allocate receive descriptors */
3043 err = igb_setup_all_rx_resources(adapter);
3044 if (err)
3045 goto err_setup_rx;
3046
88a268c1 3047 igb_power_up_link(adapter);
9d5c8243 3048
9d5c8243
AK		 3049 /* before we allocate an interrupt, we must be ready to handle it.
3050 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3051 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3052 * clean_rx handler before we do so.
3053 */
9d5c8243
AK		 3054 igb_configure(adapter);
3055
3056 err = igb_request_irq(adapter);
3057 if (err)
3058 goto err_req_irq;
3059
0c2cc02e
AD		 3060 /* Notify the stack of the actual queue counts. */
3061 err = netif_set_real_num_tx_queues(adapter->netdev,
3062 adapter->num_tx_queues);
3063 if (err)
3064 goto err_set_queues;
3065
3066 err = netif_set_real_num_rx_queues(adapter->netdev,
3067 adapter->num_rx_queues);
3068 if (err)
3069 goto err_set_queues;
3070
9d5c8243
AK		 3071 /* From here on the code is the same as igb_up() */
3072 clear_bit(__IGB_DOWN, &adapter->state);
3073
0d1ae7f4
AD		 3074 for (i = 0; i < adapter->num_q_vectors; i++)
3075 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3076
3077 /* Clear any pending interrupts. */
3078 rd32(E1000_ICR);
844290e5
PW		 3079
3080 igb_irq_enable(adapter);
3081
d4960307
AD		 3082 /* notify VFs that reset has been completed */
3083 if (adapter->vfs_allocated_count) {
3084 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3085
d4960307
AD		 3086 reg_data |= E1000_CTRL_EXT_PFRSTD;
3087 wr32(E1000_CTRL_EXT, reg_data);
3088 }
3089
d55b53ff
JK		 3090 netif_tx_start_all_queues(netdev);
3091
749ab2cd
YZ		 3092 if (!resuming)
3093 pm_runtime_put(&pdev->dev);
3094
25568a53
AD		 3095 /* start the watchdog. */
3096 hw->mac.get_link_status = 1;
3097 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3098
3099 return 0;
3100
0c2cc02e
AD		 3101err_set_queues:
3102 igb_free_irq(adapter);
9d5c8243
AK		 3103err_req_irq:
3104 igb_release_hw_control(adapter);
88a268c1 3105 igb_power_down_link(adapter);
9d5c8243
AK		 3106 igb_free_all_rx_resources(adapter);
3107err_setup_rx:
3108 igb_free_all_tx_resources(adapter);
3109err_setup_tx:
3110 igb_reset(adapter);
749ab2cd
YZ		 3111 if (!resuming)
3112 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3113
3114 return err;
3115}
3116
749ab2cd
YZ		 3117static int igb_open(struct net_device *netdev)
3118{
3119 return __igb_open(netdev, false);
3120}
3121
9d5c8243 3122/**
b980ac18
JK		 3123 * igb_close - Disables a network interface
3124 * @netdev: network interface device structure
9d5c8243 3125 *
b980ac18 3126 * Returns 0, this is not allowed to fail
9d5c8243 3127 *
b980ac18
JK		 3128 * The close entry point is called when an interface is de-activated
3129 * by the OS. The hardware is still under the driver's control, but
3130 * needs to be disabled. A global MAC reset is issued to stop the
3131 * hardware, and all transmit and receive resources are freed.
9d5c8243 3132 **/
749ab2cd 3133static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3134{
3135 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3136 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3137
3138 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3139
749ab2cd
YZ		 3140 if (!suspending)
3141 pm_runtime_get_sync(&pdev->dev);
3142
3143 igb_down(adapter);
9d5c8243
AK		 3144 igb_free_irq(adapter);
3145
3146 igb_free_all_tx_resources(adapter);
3147 igb_free_all_rx_resources(adapter);
3148
749ab2cd
YZ		 3149 if (!suspending)
3150 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3151 return 0;
3152}
3153
749ab2cd
YZ		 3154static int igb_close(struct net_device *netdev)
3155{
3156 return __igb_close(netdev, false);
3157}
3158
9d5c8243 3159/**
b980ac18
JK		 3160 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3161 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3162 *
b980ac18 3163 * Return 0 on success, negative on failure
9d5c8243 3164 **/
80785298 3165int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3166{
59d71989 3167 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3168 int size;
3169
06034649 3170 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3171
3172 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3173 if (!tx_ring->tx_buffer_info)
9d5c8243 3174 goto err;
9d5c8243
AK		 3175
3176 /* round up to nearest 4K */
85e8d004 3177 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3178 tx_ring->size = ALIGN(tx_ring->size, 4096);
3179
5536d210
AD		 3180 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3181 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3182 if (!tx_ring->desc)
3183 goto err;
3184
9d5c8243
AK		 3185 tx_ring->next_to_use = 0;
3186 tx_ring->next_to_clean = 0;
81c2fc22 3187
9d5c8243
AK		 3188 return 0;
3189
3190err:
06034649 3191 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3192 tx_ring->tx_buffer_info = NULL;
3193 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3194 return -ENOMEM;
3195}
3196
3197/**
b980ac18
JK		 3198 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3199 * (Descriptors) for all queues
3200 * @adapter: board private structure
9d5c8243 3201 *
b980ac18 3202 * Return 0 on success, negative on failure
9d5c8243
AK		 3203 **/
3204static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3205{
439705e1 3206 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3207 int i, err = 0;
3208
3209 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3210 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3211 if (err) {
439705e1 3212 dev_err(&pdev->dev,
9d5c8243
AK		 3213 "Allocation for Tx Queue %u failed\n", i);
3214 for (i--; i >= 0; i--)
3025a446 3215 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3216 break;
3217 }
3218 }
3219
3220 return err;
3221}
3222
3223/**
b980ac18
JK		 3224 * igb_setup_tctl - configure the transmit control registers
3225 * @adapter: Board private structure
9d5c8243 3226 **/
d7ee5b3a 3227void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3228{
9d5c8243
AK		 3229 struct e1000_hw *hw = &adapter->hw;
3230 u32 tctl;
9d5c8243 3231
85b430b4
AD		 3232 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3233 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3234
3235 /* Program the Transmit Control Register */
9d5c8243
AK		 3236 tctl = rd32(E1000_TCTL);
3237 tctl &= ~E1000_TCTL_CT;
3238 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3239 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3240
3241 igb_config_collision_dist(hw);
3242
9d5c8243
AK		 3243 /* Enable transmits */
3244 tctl |= E1000_TCTL_EN;
3245
3246 wr32(E1000_TCTL, tctl);
3247}
3248
85b430b4 3249/**
b980ac18
JK		 3250 * igb_configure_tx_ring - Configure transmit ring after Reset
3251 * @adapter: board private structure
3252 * @ring: tx ring to configure
85b430b4 3253 *
b980ac18 3254 * Configure a transmit ring after a reset.
85b430b4 3255 **/
d7ee5b3a 3256void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3257 struct igb_ring *ring)
85b430b4
AD		 3258{
3259 struct e1000_hw *hw = &adapter->hw;
a74420e0 3260 u32 txdctl = 0;
85b430b4
AD		 3261 u64 tdba = ring->dma;
3262 int reg_idx = ring->reg_idx;
3263
3264 /* disable the queue */
a74420e0 3265 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3266 wrfl();
3267 mdelay(10);
3268
3269 wr32(E1000_TDLEN(reg_idx),
b980ac18 3270 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3271 wr32(E1000_TDBAL(reg_idx),
b980ac18 3272 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3273 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3274
fce99e34 3275 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3276 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3277 writel(0, ring->tail);
85b430b4
AD		 3278
3279 txdctl |= IGB_TX_PTHRESH;
3280 txdctl |= IGB_TX_HTHRESH << 8;
3281 txdctl |= IGB_TX_WTHRESH << 16;
3282
3283 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3284 wr32(E1000_TXDCTL(reg_idx), txdctl);
3285}
3286
3287/**
b980ac18
JK		 3288 * igb_configure_tx - Configure transmit Unit after Reset
3289 * @adapter: board private structure
85b430b4 3290 *
b980ac18 3291 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3292 **/
3293static void igb_configure_tx(struct igb_adapter *adapter)
3294{
3295 int i;
3296
3297 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3298 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3299}
3300
9d5c8243 3301/**
b980ac18
JK		 3302 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3303 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3304 *
b980ac18 3305 * Returns 0 on success, negative on failure
9d5c8243 3306 **/
80785298 3307int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3308{
59d71989 3309 struct device *dev = rx_ring->dev;
f33005a6 3310 int size;
9d5c8243 3311
06034649 3312 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3313
3314 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3315 if (!rx_ring->rx_buffer_info)
9d5c8243 3316 goto err;
9d5c8243 3317
9d5c8243 3318 /* Round up to nearest 4K */
f33005a6 3319 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3320 rx_ring->size = ALIGN(rx_ring->size, 4096);
3321
5536d210
AD		 3322 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3323 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3324 if (!rx_ring->desc)
3325 goto err;
3326
cbc8e55f 3327 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3328 rx_ring->next_to_clean = 0;
3329 rx_ring->next_to_use = 0;
9d5c8243 3330
9d5c8243
AK		 3331 return 0;
3332
3333err:
06034649
AD		 3334 vfree(rx_ring->rx_buffer_info);
3335 rx_ring->rx_buffer_info = NULL;
f33005a6 3336 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3337 return -ENOMEM;
3338}
3339
3340/**
b980ac18
JK		 3341 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3342 * (Descriptors) for all queues
3343 * @adapter: board private structure
9d5c8243 3344 *
b980ac18 3345 * Return 0 on success, negative on failure
9d5c8243
AK		 3346 **/
3347static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3348{
439705e1 3349 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3350 int i, err = 0;
3351
3352 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3353 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3354 if (err) {
439705e1 3355 dev_err(&pdev->dev,
9d5c8243
AK		 3356 "Allocation for Rx Queue %u failed\n", i);
3357 for (i--; i >= 0; i--)
3025a446 3358 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3359 break;
3360 }
3361 }
3362
3363 return err;
3364}
3365
06cf2666 3366/**
b980ac18
JK		 3367 * igb_setup_mrqc - configure the multiple receive queue control registers
3368 * @adapter: Board private structure
06cf2666
AD		 3369 **/
3370static void igb_setup_mrqc(struct igb_adapter *adapter)
3371{
3372 struct e1000_hw *hw = &adapter->hw;
3373 u32 mrqc, rxcsum;
ed12cc9a 3374 u32 j, num_rx_queues;
a57fe23e
AD		 3375 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3376 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3377 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3378 0xFA01ACBE };
06cf2666
AD		 3379
3380 /* Fill out hash function seeds */
a57fe23e
AD		 3381 for (j = 0; j < 10; j++)
3382 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3383
a99955fc 3384 num_rx_queues = adapter->rss_queues;
06cf2666 3385
797fd4be 3386 switch (hw->mac.type) {
797fd4be
AD		 3387 case e1000_82576:
3388 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3389 if (adapter->vfs_allocated_count)
06cf2666 3390 num_rx_queues = 2;
797fd4be
AD		 3391 break;
3392 default:
3393 break;
06cf2666
AD		 3394 }
3395
ed12cc9a
LMV		 3396 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3397 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3398 adapter->rss_indir_tbl[j] =
3399 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3400 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3401 }
ed12cc9a 3402 igb_write_rss_indir_tbl(adapter);
06cf2666 3403
b980ac18 3404 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3405 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3406 * offloads as they are enabled by default
3407 */
3408 rxcsum = rd32(E1000_RXCSUM);
3409 rxcsum |= E1000_RXCSUM_PCSD;
3410
3411 if (adapter->hw.mac.type >= e1000_82576)
3412 /* Enable Receive Checksum Offload for SCTP */
3413 rxcsum |= E1000_RXCSUM_CRCOFL;
3414
3415 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3416 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3417
039454a8
AA		 3418 /* Generate RSS hash based on packet types, TCP/UDP
3419 * port numbers and/or IPv4/v6 src and dst addresses
3420 */
f96a8a0b
CW		 3421 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3422 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6 |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3425 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3426
039454a8
AA		 3427 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3428 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3429 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3430 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3431
06cf2666
AD		 3432 /* If VMDq is enabled then we set the appropriate mode for that, else
3433 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3434 * if we are only using one queue
3435 */
06cf2666
AD		 3436 if (adapter->vfs_allocated_count) {
3437 if (hw->mac.type > e1000_82575) {
3438 /* Set the default pool for the PF's first queue */
3439 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3440
06cf2666
AD		 3441 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3442 E1000_VT_CTL_DISABLE_DEF_POOL);
3443 vtctl |= adapter->vfs_allocated_count <<
3444 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3445 wr32(E1000_VT_CTL, vtctl);
3446 }
a99955fc 3447 if (adapter->rss_queues > 1)
f96a8a0b 3448 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3449 else
f96a8a0b 3450 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3451 } else {
f96a8a0b
CW		 3452 if (hw->mac.type != e1000_i211)
3453 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3454 }
3455 igb_vmm_control(adapter);
3456
06cf2666
AD		 3457 wr32(E1000_MRQC, mrqc);
3458}
3459
9d5c8243 3460/**
b980ac18
JK		 3461 * igb_setup_rctl - configure the receive control registers
3462 * @adapter: Board private structure
9d5c8243 3463 **/
d7ee5b3a 3464void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3465{
3466 struct e1000_hw *hw = &adapter->hw;
3467 u32 rctl;
9d5c8243
AK		 3468
3469 rctl = rd32(E1000_RCTL);
3470
3471 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3472 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3473
69d728ba 3474 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3475 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3476
b980ac18 3477 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3478 * redirection as it did with e1000. Newer features require
3479 * that the HW strips the CRC.
73cd78f1 3480 */
87cb7e8c 3481 rctl |= E1000_RCTL_SECRC;
9d5c8243 3482
559e9c49 3483 /* disable store bad packets and clear size bits. */
ec54d7d6 3484 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3485
6ec43fe6
AD		 3486 /* enable LPE to prevent packets larger than max_frame_size */
3487 rctl |= E1000_RCTL_LPE;
9d5c8243 3488
952f72a8
AD		 3489 /* disable queue 0 to prevent tail write w/o re-config */
3490 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3491
e1739522
AD		 3492 /* Attention!!! For SR-IOV PF driver operations you must enable
3493 * queue drop for all VF and PF queues to prevent head of line blocking
3494 * if an un-trusted VF does not provide descriptors to hardware.
3495 */
3496 if (adapter->vfs_allocated_count) {
e1739522
AD		 3497 /* set all queue drop enable bits */
3498 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3499 }
3500
89eaefb6
BG		 3501 /* This is useful for sniffing bad packets. */
3502 if (adapter->netdev->features & NETIF_F_RXALL) {
3503 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3504 * in e1000e_set_rx_mode
3505 */
89eaefb6
BG		 3506 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3507 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3508 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3509
3510 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3511 E1000_RCTL_DPF | /* Allow filtered pause */
3512 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3513 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3514 * and that breaks VLANs.
3515 */
3516 }
3517
9d5c8243
AK		 3518 wr32(E1000_RCTL, rctl);
3519}
3520
7d5753f0 3521static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3522 int vfn)
7d5753f0
AD		 3523{
3524 struct e1000_hw *hw = &adapter->hw;
3525 u32 vmolr;
3526
3527 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3528 * increase the size to support vlan tags
3529 */
7d5753f0
AD		 3530 if (vfn < adapter->vfs_allocated_count &&
3531 adapter->vf_data[vfn].vlans_enabled)
3532 size += VLAN_TAG_SIZE;
3533
3534 vmolr = rd32(E1000_VMOLR(vfn));
3535 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3536 vmolr |= size | E1000_VMOLR_LPE;
3537 wr32(E1000_VMOLR(vfn), vmolr);
3538
3539 return 0;
3540}
3541
e1739522 3542/**
b980ac18
JK		 3543 * igb_rlpml_set - set maximum receive packet size
3544 * @adapter: board private structure
e1739522 3545 *
b980ac18 3546 * Configure maximum receivable packet size.
e1739522
AD		 3547 **/
3548static void igb_rlpml_set(struct igb_adapter *adapter)
3549{
153285f9 3550 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3551 struct e1000_hw *hw = &adapter->hw;
3552 u16 pf_id = adapter->vfs_allocated_count;
3553
e1739522
AD		 3554 if (pf_id) {
3555 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3556 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3557 * to our max jumbo frame size, in case we need to enable
3558 * jumbo frames on one of the rings later.
3559 * This will not pass over-length frames into the default
3560 * queue because it's gated by the VMOLR.RLPML.
3561 */
7d5753f0 3562 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3563 }
3564
3565 wr32(E1000_RLPML, max_frame_size);
3566}
3567
8151d294
WM		 3568static inline void igb_set_vmolr(struct igb_adapter *adapter,
3569 int vfn, bool aupe)
7d5753f0
AD		 3570{
3571 struct e1000_hw *hw = &adapter->hw;
3572 u32 vmolr;
3573
b980ac18 3574 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3575 * we should exit and do nothing
3576 */
3577 if (hw->mac.type < e1000_82576)
3578 return;
3579
3580 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3581 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3582 if (hw->mac.type == e1000_i350) {
3583 u32 dvmolr;
3584
3585 dvmolr = rd32(E1000_DVMOLR(vfn));
3586 dvmolr |= E1000_DVMOLR_STRVLAN;
3587 wr32(E1000_DVMOLR(vfn), dvmolr);
3588 }
8151d294 3589 if (aupe)
b980ac18 3590 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3591 else
3592 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3593
3594 /* clear all bits that might not be set */
3595 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3596
a99955fc 3597 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3598 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3599 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3600 * multicast packets
3601 */
3602 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3603 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3604
3605 wr32(E1000_VMOLR(vfn), vmolr);
3606}
3607
85b430b4 3608/**
b980ac18
JK		 3609 * igb_configure_rx_ring - Configure a receive ring after Reset
3610 * @adapter: board private structure
3611 * @ring: receive ring to be configured
85b430b4 3612 *
b980ac18 3613 * Configure the Rx unit of the MAC after a reset.
85b430b4 3614 **/
d7ee5b3a 3615void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3616 struct igb_ring *ring)
85b430b4
AD		 3617{
3618 struct e1000_hw *hw = &adapter->hw;
3619 u64 rdba = ring->dma;
3620 int reg_idx = ring->reg_idx;
a74420e0 3621 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3622
3623 /* disable the queue */
a74420e0 3624 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3625
3626 /* Set DMA base address registers */
3627 wr32(E1000_RDBAL(reg_idx),
3628 rdba & 0x00000000ffffffffULL);
3629 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3630 wr32(E1000_RDLEN(reg_idx),
b980ac18 3631 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3632
3633 /* initialize head and tail */
fce99e34 3634 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3635 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3636 writel(0, ring->tail);
85b430b4 3637
952f72a8 3638 /* set descriptor configuration */
44390ca6 3639 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3640 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3641 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3642 if (hw->mac.type >= e1000_82580)
757b77e2 3643 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3644 /* Only set Drop Enable if we are supporting multiple queues */
3645 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3646 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3647
3648 wr32(E1000_SRRCTL(reg_idx), srrctl);
3649
7d5753f0 3650 /* set filtering for VMDQ pools */
8151d294 3651 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3652
85b430b4
AD		 3653 rxdctl |= IGB_RX_PTHRESH;
3654 rxdctl |= IGB_RX_HTHRESH << 8;
3655 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3656
3657 /* enable receive descriptor fetching */
3658 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3659 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3660}
3661
9d5c8243 3662/**
b980ac18
JK		 3663 * igb_configure_rx - Configure receive Unit after Reset
3664 * @adapter: board private structure
9d5c8243 3665 *
b980ac18 3666 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3667 **/
3668static void igb_configure_rx(struct igb_adapter *adapter)
3669{
9107584e 3670 int i;
9d5c8243 3671
68d480c4
AD		 3672 /* set UTA to appropriate mode */
3673 igb_set_uta(adapter);
3674
26ad9178
AD		 3675 /* set the correct pool for the PF default MAC address in entry 0 */
3676 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3677 adapter->vfs_allocated_count);
26ad9178 3678
06cf2666 3679 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3680 * the Base and Length of the Rx Descriptor Ring
3681 */
f9d40f6a
AD		 3682 for (i = 0; i < adapter->num_rx_queues; i++)
3683 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3684}
3685
3686/**
b980ac18
JK		 3687 * igb_free_tx_resources - Free Tx Resources per Queue
3688 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3689 *
b980ac18 3690 * Free all transmit software resources
9d5c8243 3691 **/
68fd9910 3692void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3693{
3b644cf6 3694 igb_clean_tx_ring(tx_ring);
9d5c8243 3695
06034649
AD		 3696 vfree(tx_ring->tx_buffer_info);
3697 tx_ring->tx_buffer_info = NULL;
9d5c8243 3698
439705e1
AD		 3699 /* if not set, then don't free */
3700 if (!tx_ring->desc)
3701 return;
3702
59d71989
AD		 3703 dma_free_coherent(tx_ring->dev, tx_ring->size,
3704 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3705
3706 tx_ring->desc = NULL;
3707}
3708
3709/**
b980ac18
JK		 3710 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3711 * @adapter: board private structure
9d5c8243 3712 *
b980ac18 3713 * Free all transmit software resources
9d5c8243
AK		 3714 **/
3715static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3716{
3717 int i;
3718
3719 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3720 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3721}
3722
ebe42d16
AD		 3723void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3724 struct igb_tx_buffer *tx_buffer)
3725{
3726 if (tx_buffer->skb) {
3727 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3728 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3729 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3730 dma_unmap_addr(tx_buffer, dma),
3731 dma_unmap_len(tx_buffer, len),
ebe42d16 3732 DMA_TO_DEVICE);
c9f14bf3 3733 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3734 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3735 dma_unmap_addr(tx_buffer, dma),
3736 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3737 DMA_TO_DEVICE);
3738 }
3739 tx_buffer->next_to_watch = NULL;
3740 tx_buffer->skb = NULL;
c9f14bf3 3741 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3742 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3743}
3744
3745/**
b980ac18
JK		 3746 * igb_clean_tx_ring - Free Tx Buffers
3747 * @tx_ring: ring to be cleaned
9d5c8243 3748 **/
3b644cf6 3749static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3750{
06034649 3751 struct igb_tx_buffer *buffer_info;
9d5c8243 3752 unsigned long size;
6ad4edfc 3753 u16 i;
9d5c8243 3754
06034649 3755 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3756 return;
3757 /* Free all the Tx ring sk_buffs */
3758
3759 for (i = 0; i < tx_ring->count; i++) {
06034649 3760 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3761 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3762 }
3763
dad8a3b3
JF		 3764 netdev_tx_reset_queue(txring_txq(tx_ring));
3765
06034649
AD		 3766 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3767 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3768
3769 /* Zero out the descriptor ring */
9d5c8243
AK		 3770 memset(tx_ring->desc, 0, tx_ring->size);
3771
3772 tx_ring->next_to_use = 0;
3773 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3774}
3775
3776/**
b980ac18
JK		 3777 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3778 * @adapter: board private structure
9d5c8243
AK		 3779 **/
3780static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3781{
3782 int i;
3783
3784 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3785 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3786}
3787
3788/**
b980ac18
JK		 3789 * igb_free_rx_resources - Free Rx Resources
3790 * @rx_ring: ring to clean the resources from
9d5c8243 3791 *
b980ac18 3792 * Free all receive software resources
9d5c8243 3793 **/
68fd9910 3794void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3795{
3b644cf6 3796 igb_clean_rx_ring(rx_ring);
9d5c8243 3797
06034649
AD		 3798 vfree(rx_ring->rx_buffer_info);
3799 rx_ring->rx_buffer_info = NULL;
9d5c8243 3800
439705e1
AD		 3801 /* if not set, then don't free */
3802 if (!rx_ring->desc)
3803 return;
3804
59d71989
AD		 3805 dma_free_coherent(rx_ring->dev, rx_ring->size,
3806 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3807
3808 rx_ring->desc = NULL;
3809}
3810
3811/**
b980ac18
JK		 3812 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3813 * @adapter: board private structure
9d5c8243 3814 *
b980ac18 3815 * Free all receive software resources
9d5c8243
AK		 3816 **/
3817static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3818{
3819 int i;
3820
3821 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3822 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3823}
3824
3825/**
b980ac18
JK		 3826 * igb_clean_rx_ring - Free Rx Buffers per Queue
3827 * @rx_ring: ring to free buffers from
9d5c8243 3828 **/
3b644cf6 3829static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3830{
9d5c8243 3831 unsigned long size;
c023cd88 3832 u16 i;
9d5c8243 3833
1a1c225b
AD		 3834 if (rx_ring->skb)
3835 dev_kfree_skb(rx_ring->skb);
3836 rx_ring->skb = NULL;
3837
06034649 3838 if (!rx_ring->rx_buffer_info)
9d5c8243 3839 return;
439705e1 3840
9d5c8243
AK		 3841 /* Free all the Rx ring sk_buffs */
3842 for (i = 0; i < rx_ring->count; i++) {
06034649 3843 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3844
cbc8e55f
AD		 3845 if (!buffer_info->page)
3846 continue;
3847
3848 dma_unmap_page(rx_ring->dev,
3849 buffer_info->dma,
3850 PAGE_SIZE,
3851 DMA_FROM_DEVICE);
3852 __free_page(buffer_info->page);
3853
1a1c225b 3854 buffer_info->page = NULL;
9d5c8243
AK		 3855 }
3856
06034649
AD		 3857 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3858 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3859
3860 /* Zero out the descriptor ring */
3861 memset(rx_ring->desc, 0, rx_ring->size);
3862
cbc8e55f 3863 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3864 rx_ring->next_to_clean = 0;
3865 rx_ring->next_to_use = 0;
9d5c8243
AK		 3866}
3867
3868/**
b980ac18
JK		 3869 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3870 * @adapter: board private structure
9d5c8243
AK		 3871 **/
3872static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3873{
3874 int i;
3875
3876 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3877 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3878}
3879
3880/**
b980ac18
JK		 3881 * igb_set_mac - Change the Ethernet Address of the NIC
3882 * @netdev: network interface device structure
3883 * @p: pointer to an address structure
9d5c8243 3884 *
b980ac18 3885 * Returns 0 on success, negative on failure
9d5c8243
AK		 3886 **/
3887static int igb_set_mac(struct net_device *netdev, void *p)
3888{
3889 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3890 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3891 struct sockaddr *addr = p;
3892
3893 if (!is_valid_ether_addr(addr->sa_data))
3894 return -EADDRNOTAVAIL;
3895
3896 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3897 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3898
26ad9178
AD		 3899 /* set the correct pool for the new PF MAC address in entry 0 */
3900 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3901 adapter->vfs_allocated_count);
e1739522 3902
9d5c8243
AK		 3903 return 0;
3904}
3905
3906/**
b980ac18
JK		 3907 * igb_write_mc_addr_list - write multicast addresses to MTA
3908 * @netdev: network interface device structure
9d5c8243 3909 *
b980ac18
JK		 3910 * Writes multicast address list to the MTA hash table.
3911 * Returns: -ENOMEM on failure
3912 * 0 on no addresses written
3913 * X on writing X addresses to MTA
9d5c8243 3914 **/
68d480c4 3915static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3916{
3917 struct igb_adapter *adapter = netdev_priv(netdev);
3918 struct e1000_hw *hw = &adapter->hw;
22bedad3 3919 struct netdev_hw_addr *ha;
68d480c4 3920 u8 *mta_list;
9d5c8243
AK		 3921 int i;
3922
4cd24eaf 3923 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3924 /* nothing to program, so clear mc list */
3925 igb_update_mc_addr_list(hw, NULL, 0);
3926 igb_restore_vf_multicasts(adapter);
3927 return 0;
3928 }
9d5c8243 3929
4cd24eaf 3930 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3931 if (!mta_list)
3932 return -ENOMEM;
ff41f8dc 3933
68d480c4 3934 /* The shared function expects a packed array of only addresses. */
48e2f183 3935 i = 0;
22bedad3
JP		 3936 netdev_for_each_mc_addr(ha, netdev)
3937 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3938
68d480c4
AD		 3939 igb_update_mc_addr_list(hw, mta_list, i);
3940 kfree(mta_list);
3941
4cd24eaf 3942 return netdev_mc_count(netdev);
68d480c4
AD		 3943}
3944
3945/**
b980ac18
JK		 3946 * igb_write_uc_addr_list - write unicast addresses to RAR table
3947 * @netdev: network interface device structure
68d480c4 3948 *
b980ac18
JK		 3949 * Writes unicast address list to the RAR table.
3950 * Returns: -ENOMEM on failure/insufficient address space
3951 * 0 on no addresses written
3952 * X on writing X addresses to the RAR table
68d480c4
AD		 3953 **/
3954static int igb_write_uc_addr_list(struct net_device *netdev)
3955{
3956 struct igb_adapter *adapter = netdev_priv(netdev);
3957 struct e1000_hw *hw = &adapter->hw;
3958 unsigned int vfn = adapter->vfs_allocated_count;
3959 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3960 int count = 0;
3961
3962 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3963 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3964 return -ENOMEM;
9d5c8243 3965
32e7bfc4 3966 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3967 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3968
3969 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3970 if (!rar_entries)
3971 break;
26ad9178 3972 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3973 rar_entries--,
3974 vfn);
68d480c4 3975 count++;
ff41f8dc
AD		 3976 }
3977 }
3978 /* write the addresses in reverse order to avoid write combining */
3979 for (; rar_entries > 0 ; rar_entries--) {
3980 wr32(E1000_RAH(rar_entries), 0);
3981 wr32(E1000_RAL(rar_entries), 0);
3982 }
3983 wrfl();
3984
68d480c4
AD		 3985 return count;
3986}
3987
3988/**
b980ac18
JK		 3989 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3990 * @netdev: network interface device structure
68d480c4 3991 *
b980ac18
JK		 3992 * The set_rx_mode entry point is called whenever the unicast or multicast
3993 * address lists or the network interface flags are updated. This routine is
3994 * responsible for configuring the hardware for proper unicast, multicast,
3995 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3996 **/
3997static void igb_set_rx_mode(struct net_device *netdev)
3998{
3999 struct igb_adapter *adapter = netdev_priv(netdev);
4000 struct e1000_hw *hw = &adapter->hw;
4001 unsigned int vfn = adapter->vfs_allocated_count;
4002 u32 rctl, vmolr = 0;
4003 int count;
4004
4005 /* Check for Promiscuous and All Multicast modes */
4006 rctl = rd32(E1000_RCTL);
4007
4008 /* clear the effected bits */
4009 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4010
4011 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4012 /* retain VLAN HW filtering if in VT mode */
7e44892c 4013 if (adapter->vfs_allocated_count)
6f3dc319 4014 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4015 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4016 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4017 } else {
4018 if (netdev->flags & IFF_ALLMULTI) {
4019 rctl |= E1000_RCTL_MPE;
4020 vmolr |= E1000_VMOLR_MPME;
4021 } else {
b980ac18 4022 /* Write addresses to the MTA, if the attempt fails
25985edc 4023 * then we should just turn on promiscuous mode so
68d480c4
AD		 4024 * that we can at least receive multicast traffic
4025 */
4026 count = igb_write_mc_addr_list(netdev);
4027 if (count < 0) {
4028 rctl |= E1000_RCTL_MPE;
4029 vmolr |= E1000_VMOLR_MPME;
4030 } else if (count) {
4031 vmolr |= E1000_VMOLR_ROMPE;
4032 }
4033 }
b980ac18 4034 /* Write addresses to available RAR registers, if there is not
68d480c4 4035 * sufficient space to store all the addresses then enable
25985edc 4036 * unicast promiscuous mode
68d480c4
AD		 4037 */
4038 count = igb_write_uc_addr_list(netdev);
4039 if (count < 0) {
4040 rctl |= E1000_RCTL_UPE;
4041 vmolr |= E1000_VMOLR_ROPE;
4042 }
4043 rctl |= E1000_RCTL_VFE;
28fc06f5 4044 }
68d480c4 4045 wr32(E1000_RCTL, rctl);
28fc06f5 4046
b980ac18 4047 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4048 * the VMOLR to enable the appropriate modes. Without this workaround
4049 * we will have issues with VLAN tag stripping not being done for frames
4050 * that are only arriving because we are the default pool
4051 */
f96a8a0b 4052 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4053 return;
9d5c8243 4054
68d480c4 4055 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4056 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4057 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4058 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4059}
4060
13800469
GR		 4061static void igb_check_wvbr(struct igb_adapter *adapter)
4062{
4063 struct e1000_hw *hw = &adapter->hw;
4064 u32 wvbr = 0;
4065
4066 switch (hw->mac.type) {
4067 case e1000_82576:
4068 case e1000_i350:
81ad807b
CW		 4069 wvbr = rd32(E1000_WVBR);
4070 if (!wvbr)
13800469
GR		 4071 return;
4072 break;
4073 default:
4074 break;
4075 }
4076
4077 adapter->wvbr |= wvbr;
4078}
4079
4080#define IGB_STAGGERED_QUEUE_OFFSET 8
4081
4082static void igb_spoof_check(struct igb_adapter *adapter)
4083{
4084 int j;
4085
4086 if (!adapter->wvbr)
4087 return;
4088
9005df38 4089 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4090 if (adapter->wvbr & (1 << j) ||
4091 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4092 dev_warn(&adapter->pdev->dev,
4093 "Spoof event(s) detected on VF %d\n", j);
4094 adapter->wvbr &=
4095 ~((1 << j) |
4096 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4097 }
4098 }
4099}
4100
9d5c8243 4101/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4102 * the phy
4103 */
9d5c8243
AK		 4104static void igb_update_phy_info(unsigned long data)
4105{
4106 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4107 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4108}
4109
4d6b725e 4110/**
b980ac18
JK		 4111 * igb_has_link - check shared code for link and determine up/down
4112 * @adapter: pointer to driver private info
4d6b725e 4113 **/
3145535a 4114bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4115{
4116 struct e1000_hw *hw = &adapter->hw;
4117 bool link_active = false;
4d6b725e
AD		 4118
4119 /* get_link_status is set on LSC (link status) interrupt or
4120 * rx sequence error interrupt. get_link_status will stay
4121 * false until the e1000_check_for_link establishes link
4122 * for copper adapters ONLY
4123 */
4124 switch (hw->phy.media_type) {
4125 case e1000_media_type_copper:
e5c3370f
AA		 4126 if (!hw->mac.get_link_status)
4127 return true;
4d6b725e 4128 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4129 hw->mac.ops.check_for_link(hw);
4130 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4131 break;
4132 default:
4133 case e1000_media_type_unknown:
4134 break;
4135 }
4136
aa9b8cc4
AA		 4137 if (((hw->mac.type == e1000_i210) ||
4138 (hw->mac.type == e1000_i211)) &&
4139 (hw->phy.id == I210_I_PHY_ID)) {
4140 if (!netif_carrier_ok(adapter->netdev)) {
4141 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4142 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4143 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4144 adapter->link_check_timeout = jiffies;
4145 }
4146 }
4147
4d6b725e
AD		 4148 return link_active;
4149}
4150
563988dc
SA		 4151static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4152{
4153 bool ret = false;
4154 u32 ctrl_ext, thstat;
4155
f96a8a0b 4156 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4157 if (hw->mac.type == e1000_i350) {
4158 thstat = rd32(E1000_THSTAT);
4159 ctrl_ext = rd32(E1000_CTRL_EXT);
4160
4161 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4162 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4163 ret = !!(thstat & event);
563988dc
SA		 4164 }
4165
4166 return ret;
4167}
4168
9d5c8243 4169/**
b980ac18
JK		 4170 * igb_watchdog - Timer Call-back
4171 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4172 **/
4173static void igb_watchdog(unsigned long data)
4174{
4175 struct igb_adapter *adapter = (struct igb_adapter *)data;
4176 /* Do the rest outside of interrupt context */
4177 schedule_work(&adapter->watchdog_task);
4178}
4179
4180static void igb_watchdog_task(struct work_struct *work)
4181{
4182 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4183 struct igb_adapter,
4184 watchdog_task);
9d5c8243 4185 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4186 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4187 struct net_device *netdev = adapter->netdev;
563988dc 4188 u32 link;
7a6ea550 4189 int i;
56cec249 4190 u32 connsw;
9d5c8243 4191
4d6b725e 4192 link = igb_has_link(adapter);
aa9b8cc4
AA		 4193
4194 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4195 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4196 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4197 else
4198 link = false;
4199 }
4200
56cec249
CW		 4201 /* Force link down if we have fiber to swap to */
4202 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4203 if (hw->phy.media_type == e1000_media_type_copper) {
4204 connsw = rd32(E1000_CONNSW);
4205 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4206 link = 0;
4207 }
4208 }
9d5c8243 4209 if (link) {
2bdfc4e2
CW		 4210 /* Perform a reset if the media type changed. */
4211 if (hw->dev_spec._82575.media_changed) {
4212 hw->dev_spec._82575.media_changed = false;
4213 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4214 igb_reset(adapter);
4215 }
749ab2cd
YZ		 4216 /* Cancel scheduled suspend requests. */
4217 pm_runtime_resume(netdev->dev.parent);
4218
9d5c8243
AK		 4219 if (!netif_carrier_ok(netdev)) {
4220 u32 ctrl;
9005df38 4221
330a6d6a 4222 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4223 &adapter->link_speed,
4224 &adapter->link_duplex);
9d5c8243
AK		 4225
4226 ctrl = rd32(E1000_CTRL);
527d47c1 4227 /* Links status message must follow this format */
c75c4edf
CW		 4228 netdev_info(netdev,
4229 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4230 netdev->name,
4231 adapter->link_speed,
4232 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4233 "Full" : "Half",
4234 (ctrl & E1000_CTRL_TFCE) &&
4235 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4236 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4237 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4238
f4c01e96
CW		 4239 /* disable EEE if enabled */
4240 if ((adapter->flags & IGB_FLAG_EEE) &&
4241 (adapter->link_duplex == HALF_DUPLEX)) {
4242 dev_info(&adapter->pdev->dev,
4243 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4244 adapter->hw.dev_spec._82575.eee_disable = true;
4245 adapter->flags &= ~IGB_FLAG_EEE;
4246 }
4247
c0ba4778
KS		 4248 /* check if SmartSpeed worked */
4249 igb_check_downshift(hw);
4250 if (phy->speed_downgraded)
4251 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4252
563988dc 4253 /* check for thermal sensor event */
876d2d6f 4254 if (igb_thermal_sensor_event(hw,
d34a15ab 4255 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4256 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4257
d07f3e37 4258 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4259 adapter->tx_timeout_factor = 1;
4260 switch (adapter->link_speed) {
4261 case SPEED_10:
9d5c8243
AK		 4262 adapter->tx_timeout_factor = 14;
4263 break;
4264 case SPEED_100:
9d5c8243
AK		 4265 /* maybe add some timeout factor ? */
4266 break;
4267 }
4268
4269 netif_carrier_on(netdev);
9d5c8243 4270
4ae196df 4271 igb_ping_all_vfs(adapter);
17dc566c 4272 igb_check_vf_rate_limit(adapter);
4ae196df 4273
4b1a9877 4274 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4275 if (!test_bit(__IGB_DOWN, &adapter->state))
4276 mod_timer(&adapter->phy_info_timer,
4277 round_jiffies(jiffies + 2 * HZ));
4278 }
4279 } else {
4280 if (netif_carrier_ok(netdev)) {
4281 adapter->link_speed = 0;
4282 adapter->link_duplex = 0;
563988dc
SA		 4283
4284 /* check for thermal sensor event */
876d2d6f
JK		 4285 if (igb_thermal_sensor_event(hw,
4286 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4287 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4288 }
563988dc 4289
527d47c1 4290 /* Links status message must follow this format */
c75c4edf 4291 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4292 netdev->name);
9d5c8243 4293 netif_carrier_off(netdev);
4b1a9877 4294
4ae196df
AD		 4295 igb_ping_all_vfs(adapter);
4296
4b1a9877 4297 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4298 if (!test_bit(__IGB_DOWN, &adapter->state))
4299 mod_timer(&adapter->phy_info_timer,
4300 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4301
56cec249
CW		 4302 /* link is down, time to check for alternate media */
4303 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4304 igb_check_swap_media(adapter);
4305 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4306 schedule_work(&adapter->reset_task);
4307 /* return immediately */
4308 return;
4309 }
4310 }
749ab2cd
YZ		 4311 pm_schedule_suspend(netdev->dev.parent,
4312 MSEC_PER_SEC * 5);
56cec249
CW		 4313
4314 /* also check for alternate media here */
4315 } else if (!netif_carrier_ok(netdev) &&
4316 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4317 igb_check_swap_media(adapter);
4318 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4319 schedule_work(&adapter->reset_task);
4320 /* return immediately */
4321 return;
4322 }
9d5c8243
AK		 4323 }
4324 }
4325
12dcd86b
ED		 4326 spin_lock(&adapter->stats64_lock);
4327 igb_update_stats(adapter, &adapter->stats64);
4328 spin_unlock(&adapter->stats64_lock);
9d5c8243 4329
dbabb065 4330 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4331 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4332 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4333 /* We've lost link, so the controller stops DMA,
4334 * but we've got queued Tx work that's never going
4335 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4336 * (Do the reset outside of interrupt context).
4337 */
dbabb065
AD		 4338 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4339 adapter->tx_timeout_count++;
4340 schedule_work(&adapter->reset_task);
4341 /* return immediately since reset is imminent */
4342 return;
4343 }
9d5c8243 4344 }
9d5c8243 4345
dbabb065 4346 /* Force detection of hung controller every watchdog period */
6d095fa8 4347 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4348 }
f7ba205e 4349
b980ac18 4350 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4351 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4352 u32 eics = 0;
9005df38 4353
0d1ae7f4
AD		 4354 for (i = 0; i < adapter->num_q_vectors; i++)
4355 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4356 wr32(E1000_EICS, eics);
4357 } else {
4358 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4359 }
9d5c8243 4360
13800469 4361 igb_spoof_check(adapter);
fc580751 4362 igb_ptp_rx_hang(adapter);
13800469 4363
9d5c8243 4364 /* Reset the timer */
aa9b8cc4
AA		 4365 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4366 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4367 mod_timer(&adapter->watchdog_timer,
4368 round_jiffies(jiffies + HZ));
4369 else
4370 mod_timer(&adapter->watchdog_timer,
4371 round_jiffies(jiffies + 2 * HZ));
4372 }
9d5c8243
AK		 4373}
4374
4375enum latency_range {
4376 lowest_latency = 0,
4377 low_latency = 1,
4378 bulk_latency = 2,
4379 latency_invalid = 255
4380};
4381
6eb5a7f1 4382/**
b980ac18
JK		 4383 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4384 * @q_vector: pointer to q_vector
6eb5a7f1 4385 *
b980ac18
JK		 4386 * Stores a new ITR value based on strictly on packet size. This
4387 * algorithm is less sophisticated than that used in igb_update_itr,
4388 * due to the difficulty of synchronizing statistics across multiple
4389 * receive rings. The divisors and thresholds used by this function
4390 * were determined based on theoretical maximum wire speed and testing
4391 * data, in order to minimize response time while increasing bulk
4392 * throughput.
406d4965 4393 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4394 * NOTE: This function is called only when operating in a multiqueue
4395 * receive environment.
6eb5a7f1 4396 **/
047e0030 4397static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4398{
047e0030 4399 int new_val = q_vector->itr_val;
6eb5a7f1 4400 int avg_wire_size = 0;
047e0030 4401 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4402 unsigned int packets;
9d5c8243 4403
6eb5a7f1
AD		 4404 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4405 * ints/sec - ITR timer value of 120 ticks.
4406 */
4407 if (adapter->link_speed != SPEED_1000) {
0ba82994 4408 new_val = IGB_4K_ITR;
6eb5a7f1 4409 goto set_itr_val;
9d5c8243 4410 }
047e0030 4411
0ba82994
AD		 4412 packets = q_vector->rx.total_packets;
4413 if (packets)
4414 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4415
0ba82994
AD		 4416 packets = q_vector->tx.total_packets;
4417 if (packets)
4418 avg_wire_size = max_t(u32, avg_wire_size,
4419 q_vector->tx.total_bytes / packets);
047e0030
AD		 4420
4421 /* if avg_wire_size isn't set no work was done */
4422 if (!avg_wire_size)
4423 goto clear_counts;
9d5c8243 4424
6eb5a7f1
AD		 4425 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4426 avg_wire_size += 24;
4427
4428 /* Don't starve jumbo frames */
4429 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4430
6eb5a7f1
AD		 4431 /* Give a little boost to mid-size frames */
4432 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4433 new_val = avg_wire_size / 3;
4434 else
4435 new_val = avg_wire_size / 2;
9d5c8243 4436
0ba82994
AD		 4437 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4438 if (new_val < IGB_20K_ITR &&
4439 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4440 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4441 new_val = IGB_20K_ITR;
abe1c363 4442
6eb5a7f1 4443set_itr_val:
047e0030
AD		 4444 if (new_val != q_vector->itr_val) {
4445 q_vector->itr_val = new_val;
4446 q_vector->set_itr = 1;
9d5c8243 4447 }
6eb5a7f1 4448clear_counts:
0ba82994
AD		 4449 q_vector->rx.total_bytes = 0;
4450 q_vector->rx.total_packets = 0;
4451 q_vector->tx.total_bytes = 0;
4452 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4453}
4454
4455/**
b980ac18
JK		 4456 * igb_update_itr - update the dynamic ITR value based on statistics
4457 * @q_vector: pointer to q_vector
4458 * @ring_container: ring info to update the itr for
4459 *
4460 * Stores a new ITR value based on packets and byte
4461 * counts during the last interrupt. The advantage of per interrupt
4462 * computation is faster updates and more accurate ITR for the current
4463 * traffic pattern. Constants in this function were computed
4464 * based on theoretical maximum wire speed and thresholds were set based
4465 * on testing data as well as attempting to minimize response time
4466 * while increasing bulk throughput.
406d4965 4467 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4468 * NOTE: These calculations are only valid when operating in a single-
4469 * queue environment.
9d5c8243 4470 **/
0ba82994
AD		 4471static void igb_update_itr(struct igb_q_vector *q_vector,
4472 struct igb_ring_container *ring_container)
9d5c8243 4473{
0ba82994
AD		 4474 unsigned int packets = ring_container->total_packets;
4475 unsigned int bytes = ring_container->total_bytes;
4476 u8 itrval = ring_container->itr;
9d5c8243 4477
0ba82994 4478 /* no packets, exit with status unchanged */
9d5c8243 4479 if (packets == 0)
0ba82994 4480 return;
9d5c8243 4481
0ba82994 4482 switch (itrval) {
9d5c8243
AK		 4483 case lowest_latency:
4484 /* handle TSO and jumbo frames */
4485 if (bytes/packets > 8000)
0ba82994 4486 itrval = bulk_latency;
9d5c8243 4487 else if ((packets < 5) && (bytes > 512))
0ba82994 4488 itrval = low_latency;
9d5c8243
AK		 4489 break;
4490 case low_latency: /* 50 usec aka 20000 ints/s */
4491 if (bytes > 10000) {
4492 /* this if handles the TSO accounting */
d34a15ab 4493 if (bytes/packets > 8000)
0ba82994 4494 itrval = bulk_latency;
d34a15ab 4495 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4496 itrval = bulk_latency;
d34a15ab 4497 else if ((packets > 35))
0ba82994 4498 itrval = lowest_latency;
9d5c8243 4499 } else if (bytes/packets > 2000) {
0ba82994 4500 itrval = bulk_latency;
9d5c8243 4501 } else if (packets <= 2 && bytes < 512) {
0ba82994 4502 itrval = lowest_latency;
9d5c8243
AK		 4503 }
4504 break;
4505 case bulk_latency: /* 250 usec aka 4000 ints/s */
4506 if (bytes > 25000) {
4507 if (packets > 35)
0ba82994 4508 itrval = low_latency;
1e5c3d21 4509 } else if (bytes < 1500) {
0ba82994 4510 itrval = low_latency;
9d5c8243
AK		 4511 }
4512 break;
4513 }
4514
0ba82994
AD		 4515 /* clear work counters since we have the values we need */
4516 ring_container->total_bytes = 0;
4517 ring_container->total_packets = 0;
4518
4519 /* write updated itr to ring container */
4520 ring_container->itr = itrval;
9d5c8243
AK		 4521}
4522
0ba82994 4523static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4524{
0ba82994 4525 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4526 u32 new_itr = q_vector->itr_val;
0ba82994 4527 u8 current_itr = 0;
9d5c8243
AK		 4528
4529 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4530 if (adapter->link_speed != SPEED_1000) {
4531 current_itr = 0;
0ba82994 4532 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4533 goto set_itr_now;
4534 }
4535
0ba82994
AD		 4536 igb_update_itr(q_vector, &q_vector->tx);
4537 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4538
0ba82994 4539 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4540
6eb5a7f1 4541 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4542 if (current_itr == lowest_latency &&
4543 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4544 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4545 current_itr = low_latency;
4546
9d5c8243
AK		 4547 switch (current_itr) {
4548 /* counts and packets in update_itr are dependent on these numbers */
4549 case lowest_latency:
0ba82994 4550 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4551 break;
4552 case low_latency:
0ba82994 4553 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4554 break;
4555 case bulk_latency:
0ba82994 4556 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4557 break;
4558 default:
4559 break;
4560 }
4561
4562set_itr_now:
047e0030 4563 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4564 /* this attempts to bias the interrupt rate towards Bulk
4565 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4566 * increasing
4567 */
047e0030 4568 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4569 max((new_itr * q_vector->itr_val) /
4570 (new_itr + (q_vector->itr_val >> 2)),
4571 new_itr) : new_itr;
9d5c8243
AK		 4572 /* Don't write the value here; it resets the adapter's
4573 * internal timer, and causes us to delay far longer than
4574 * we should between interrupts. Instead, we write the ITR
4575 * value at the beginning of the next interrupt so the timing
4576 * ends up being correct.
4577 */
047e0030
AD		 4578 q_vector->itr_val = new_itr;
4579 q_vector->set_itr = 1;
9d5c8243 4580 }
9d5c8243
AK		 4581}
4582
c50b52a0
SH		 4583static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4584 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4585{
4586 struct e1000_adv_tx_context_desc *context_desc;
4587 u16 i = tx_ring->next_to_use;
4588
4589 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4590
4591 i++;
4592 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4593
4594 /* set bits to identify this as an advanced context descriptor */
4595 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4596
4597 /* For 82575, context index must be unique per ring. */
866cff06 4598 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4599 mss_l4len_idx |= tx_ring->reg_idx << 4;
4600
4601 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4602 context_desc->seqnum_seed = 0;
4603 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4604 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4605}
4606
7af40ad9
AD		 4607static int igb_tso(struct igb_ring *tx_ring,
4608 struct igb_tx_buffer *first,
4609 u8 *hdr_len)
9d5c8243 4610{
7af40ad9 4611 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4612 u32 vlan_macip_lens, type_tucmd;
4613 u32 mss_l4len_idx, l4len;
06c14e5a 4614 int err;
7d13a7d0 4615
ed6aa105
AD		 4616 if (skb->ip_summed != CHECKSUM_PARTIAL)
4617 return 0;
4618
7d13a7d0
AD		 4619 if (!skb_is_gso(skb))
4620 return 0;
9d5c8243 4621
06c14e5a
FR		 4622 err = skb_cow_head(skb, 0);
4623 if (err < 0)
4624 return err;
9d5c8243 4625
7d13a7d0
AD		 4626 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4627 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4628
7c4d16ff 4629 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4630 struct iphdr *iph = ip_hdr(skb);
4631 iph->tot_len = 0;
4632 iph->check = 0;
4633 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4634 iph->daddr, 0,
4635 IPPROTO_TCP,
4636 0);
7d13a7d0 4637 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4638 first->tx_flags |= IGB_TX_FLAGS_TSO |
4639 IGB_TX_FLAGS_CSUM |
4640 IGB_TX_FLAGS_IPV4;
8e1e8a47 4641 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4642 ipv6_hdr(skb)->payload_len = 0;
4643 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4644 &ipv6_hdr(skb)->daddr,
4645 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4646 first->tx_flags |= IGB_TX_FLAGS_TSO |
4647 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4648 }
4649
7af40ad9 4650 /* compute header lengths */
7d13a7d0
AD		 4651 l4len = tcp_hdrlen(skb);
4652 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4653
7af40ad9
AD		 4654 /* update gso size and bytecount with header size */
4655 first->gso_segs = skb_shinfo(skb)->gso_segs;
4656 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4657
9d5c8243 4658 /* MSS L4LEN IDX */
7d13a7d0
AD		 4659 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4660 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4661
7d13a7d0
AD		 4662 /* VLAN MACLEN IPLEN */
4663 vlan_macip_lens = skb_network_header_len(skb);
4664 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4665 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4666
7d13a7d0 4667 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4668
7d13a7d0 4669 return 1;
9d5c8243
AK		 4670}
4671
7af40ad9 4672static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4673{
7af40ad9 4674 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4675 u32 vlan_macip_lens = 0;
4676 u32 mss_l4len_idx = 0;
4677 u32 type_tucmd = 0;
9d5c8243 4678
7d13a7d0 4679 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4680 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4681 return;
7d13a7d0
AD		 4682 } else {
4683 u8 l4_hdr = 0;
9005df38 4684
7af40ad9 4685 switch (first->protocol) {
7c4d16ff 4686 case htons(ETH_P_IP):
7d13a7d0
AD		 4687 vlan_macip_lens |= skb_network_header_len(skb);
4688 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4689 l4_hdr = ip_hdr(skb)->protocol;
4690 break;
7c4d16ff 4691 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4692 vlan_macip_lens |= skb_network_header_len(skb);
4693 l4_hdr = ipv6_hdr(skb)->nexthdr;
4694 break;
4695 default:
4696 if (unlikely(net_ratelimit())) {
4697 dev_warn(tx_ring->dev,
b980ac18
JK		 4698 "partial checksum but proto=%x!\n",
4699 first->protocol);
fa4a7ef3 4700 }
7d13a7d0
AD		 4701 break;
4702 }
fa4a7ef3 4703
7d13a7d0
AD		 4704 switch (l4_hdr) {
4705 case IPPROTO_TCP:
4706 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4707 mss_l4len_idx = tcp_hdrlen(skb) <<
4708 E1000_ADVTXD_L4LEN_SHIFT;
4709 break;
4710 case IPPROTO_SCTP:
4711 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4712 mss_l4len_idx = sizeof(struct sctphdr) <<
4713 E1000_ADVTXD_L4LEN_SHIFT;
4714 break;
4715 case IPPROTO_UDP:
4716 mss_l4len_idx = sizeof(struct udphdr) <<
4717 E1000_ADVTXD_L4LEN_SHIFT;
4718 break;
4719 default:
4720 if (unlikely(net_ratelimit())) {
4721 dev_warn(tx_ring->dev,
b980ac18
JK		 4722 "partial checksum but l4 proto=%x!\n",
4723 l4_hdr);
44b0cda3 4724 }
7d13a7d0 4725 break;
9d5c8243 4726 }
7af40ad9
AD		 4727
4728 /* update TX checksum flag */
4729 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4730 }
9d5c8243 4731
7d13a7d0 4732 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4733 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4734
7d13a7d0 4735 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4736}
4737
1d9daf45
AD		 4738#define IGB_SET_FLAG(_input, _flag, _result) \
4739 ((_flag <= _result) ? \
4740 ((u32)(_input & _flag) * (_result / _flag)) : \
4741 ((u32)(_input & _flag) / (_flag / _result)))
4742
4743static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4744{
4745 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4746 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4747 E1000_ADVTXD_DCMD_DEXT |
4748 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4749
4750 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4751 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4752 (E1000_ADVTXD_DCMD_VLE));
4753
4754 /* set segmentation bits for TSO */
4755 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4756 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4757
4758 /* set timestamp bit if present */
1d9daf45
AD		 4759 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4760 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4761
1d9daf45
AD		 4762 /* insert frame checksum */
4763 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4764
4765 return cmd_type;
4766}
4767
7af40ad9
AD		 4768static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4769 union e1000_adv_tx_desc *tx_desc,
4770 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4771{
4772 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4773
1d9daf45
AD		 4774 /* 82575 requires a unique index per ring */
4775 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4776 olinfo_status |= tx_ring->reg_idx << 4;
4777
4778 /* insert L4 checksum */
1d9daf45
AD		 4779 olinfo_status |= IGB_SET_FLAG(tx_flags,
4780 IGB_TX_FLAGS_CSUM,
4781 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4782
1d9daf45
AD		 4783 /* insert IPv4 checksum */
4784 olinfo_status |= IGB_SET_FLAG(tx_flags,
4785 IGB_TX_FLAGS_IPV4,
4786 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4787
7af40ad9 4788 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4789}
4790
7af40ad9
AD		 4791static void igb_tx_map(struct igb_ring *tx_ring,
4792 struct igb_tx_buffer *first,
ebe42d16 4793 const u8 hdr_len)
9d5c8243 4794{
7af40ad9 4795 struct sk_buff *skb = first->skb;
c9f14bf3 4796 struct igb_tx_buffer *tx_buffer;
ebe42d16 4797 union e1000_adv_tx_desc *tx_desc;
80d0759e 4798 struct skb_frag_struct *frag;
ebe42d16 4799 dma_addr_t dma;
80d0759e 4800 unsigned int data_len, size;
7af40ad9 4801 u32 tx_flags = first->tx_flags;
1d9daf45 4802 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4803 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4804
4805 tx_desc = IGB_TX_DESC(tx_ring, i);
4806
80d0759e
AD		 4807 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4808
4809 size = skb_headlen(skb);
4810 data_len = skb->data_len;
ebe42d16
AD		 4811
4812 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4813
80d0759e
AD		 4814 tx_buffer = first;
4815
4816 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4817 if (dma_mapping_error(tx_ring->dev, dma))
4818 goto dma_error;
4819
4820 /* record length, and DMA address */
4821 dma_unmap_len_set(tx_buffer, len, size);
4822 dma_unmap_addr_set(tx_buffer, dma, dma);
4823
4824 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4825
ebe42d16
AD		 4826 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4827 tx_desc->read.cmd_type_len =
1d9daf45 4828 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4829
4830 i++;
4831 tx_desc++;
4832 if (i == tx_ring->count) {
4833 tx_desc = IGB_TX_DESC(tx_ring, 0);
4834 i = 0;
4835 }
80d0759e 4836 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4837
4838 dma += IGB_MAX_DATA_PER_TXD;
4839 size -= IGB_MAX_DATA_PER_TXD;
4840
ebe42d16
AD		 4841 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4842 }
4843
4844 if (likely(!data_len))
4845 break;
2bbfebe2 4846
1d9daf45 4847 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4848
65689fef 4849 i++;
ebe42d16
AD		 4850 tx_desc++;
4851 if (i == tx_ring->count) {
4852 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4853 i = 0;
ebe42d16 4854 }
80d0759e 4855 tx_desc->read.olinfo_status = 0;
65689fef 4856
9e903e08 4857 size = skb_frag_size(frag);
ebe42d16
AD		 4858 data_len -= size;
4859
4860 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4861 size, DMA_TO_DEVICE);
6366ad33 4862
c9f14bf3 4863 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4864 }
4865
ebe42d16 4866 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4867 cmd_type |= size | IGB_TXD_DCMD;
4868 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4869
80d0759e
AD		 4870 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4871
8542db05
AD		 4872 /* set the timestamp */
4873 first->time_stamp = jiffies;
4874
b980ac18 4875 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4876 * are new descriptors to fetch. (Only applicable for weak-ordered
4877 * memory model archs, such as IA-64).
4878 *
4879 * We also need this memory barrier to make certain all of the
4880 * status bits have been updated before next_to_watch is written.
4881 */
4882 wmb();
4883
8542db05 4884 /* set next_to_watch value indicating a packet is present */
ebe42d16 4885 first->next_to_watch = tx_desc;
9d5c8243 4886
ebe42d16
AD		 4887 i++;
4888 if (i == tx_ring->count)
4889 i = 0;
6366ad33 4890
ebe42d16 4891 tx_ring->next_to_use = i;
6366ad33 4892
ebe42d16 4893 writel(i, tx_ring->tail);
6366ad33 4894
ebe42d16 4895 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4896 * at a time, it synchronizes IO on IA64/Altix systems
4897 */
ebe42d16
AD		 4898 mmiowb();
4899
4900 return;
4901
4902dma_error:
4903 dev_err(tx_ring->dev, "TX DMA map failed\n");
4904
4905 /* clear dma mappings for failed tx_buffer_info map */
4906 for (;;) {
c9f14bf3
AD		 4907 tx_buffer = &tx_ring->tx_buffer_info[i];
4908 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4909 if (tx_buffer == first)
ebe42d16 4910 break;
a77ff709
NN		 4911 if (i == 0)
4912 i = tx_ring->count;
6366ad33 4913 i--;
6366ad33
AD		 4914 }
4915
9d5c8243 4916 tx_ring->next_to_use = i;
9d5c8243
AK		 4917}
4918
6ad4edfc 4919static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4920{
e694e964
AD		 4921 struct net_device *netdev = tx_ring->netdev;
4922
661086df 4923 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4924
9d5c8243
AK		 4925 /* Herbert's original patch had:
4926 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4927 * but since that doesn't exist yet, just open code it.
4928 */
9d5c8243
AK		 4929 smp_mb();
4930
4931 /* We need to check again in a case another CPU has just
b980ac18
JK		 4932 * made room available.
4933 */
c493ea45 4934 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4935 return -EBUSY;
4936
4937 /* A reprieve! */
661086df 4938 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4939
4940 u64_stats_update_begin(&tx_ring->tx_syncp2);
4941 tx_ring->tx_stats.restart_queue2++;
4942 u64_stats_update_end(&tx_ring->tx_syncp2);
4943
9d5c8243
AK		 4944 return 0;
4945}
4946
6ad4edfc 4947static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4948{
c493ea45 4949 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4950 return 0;
e694e964 4951 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4952}
4953
cd392f5c
AD		 4954netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4955 struct igb_ring *tx_ring)
9d5c8243 4956{
8542db05 4957 struct igb_tx_buffer *first;
ebe42d16 4958 int tso;
91d4ee33 4959 u32 tx_flags = 0;
21ba6fe1 4960 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4961 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4962 u8 hdr_len = 0;
9d5c8243 4963
21ba6fe1
AD		 4964 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4965 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4966 * + 2 desc gap to keep tail from touching head,
9d5c8243 4967 * + 1 desc for context descriptor,
21ba6fe1
AD		 4968 * otherwise try next time
4969 */
4970 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4971 unsigned short f;
9005df38 4972
21ba6fe1
AD		 4973 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4974 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4975 } else {
4976 count += skb_shinfo(skb)->nr_frags;
4977 }
4978
4979 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4980 /* this is a hard error */
9d5c8243
AK		 4981 return NETDEV_TX_BUSY;
4982 }
33af6bcc 4983
7af40ad9
AD		 4984 /* record the location of the first descriptor for this packet */
4985 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4986 first->skb = skb;
4987 first->bytecount = skb->len;
4988 first->gso_segs = 1;
4989
b646c22e
AD		 4990 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4991 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4992
ed4420a3
JK		 4993 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
4994 &adapter->state)) {
b646c22e
AD		 4995 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4996 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4997
4998 adapter->ptp_tx_skb = skb_get(skb);
4999 adapter->ptp_tx_start = jiffies;
5000 if (adapter->hw.mac.type == e1000_82576)
5001 schedule_work(&adapter->ptp_tx_work);
5002 }
33af6bcc 5003 }
9d5c8243 5004
afc835d1
JK		 5005 skb_tx_timestamp(skb);
5006
eab6d18d 5007 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 5008 tx_flags |= IGB_TX_FLAGS_VLAN;
5009 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5010 }
5011
7af40ad9
AD		 5012 /* record initial flags and protocol */
5013 first->tx_flags = tx_flags;
5014 first->protocol = protocol;
cdfd01fc 5015
7af40ad9
AD		 5016 tso = igb_tso(tx_ring, first, &hdr_len);
5017 if (tso < 0)
7d13a7d0 5018 goto out_drop;
7af40ad9
AD		 5019 else if (!tso)
5020 igb_tx_csum(tx_ring, first);
9d5c8243 5021
7af40ad9 5022 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 5023
5024 /* Make sure there is space in the ring for the next send. */
21ba6fe1 5025 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 5026
9d5c8243 5027 return NETDEV_TX_OK;
7d13a7d0
AD		 5028
5029out_drop:
7af40ad9
AD		 5030 igb_unmap_and_free_tx_resource(tx_ring, first);
5031
7d13a7d0 5032 return NETDEV_TX_OK;
9d5c8243
AK		 5033}
5034
1cc3bd87
AD		 5035static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5036 struct sk_buff *skb)
5037{
5038 unsigned int r_idx = skb->queue_mapping;
5039
5040 if (r_idx >= adapter->num_tx_queues)
5041 r_idx = r_idx % adapter->num_tx_queues;
5042
5043 return adapter->tx_ring[r_idx];
5044}
5045
cd392f5c
AD		 5046static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5047 struct net_device *netdev)
9d5c8243
AK		 5048{
5049 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5050
5051 if (test_bit(__IGB_DOWN, &adapter->state)) {
5052 dev_kfree_skb_any(skb);
5053 return NETDEV_TX_OK;
5054 }
5055
5056 if (skb->len <= 0) {
5057 dev_kfree_skb_any(skb);
5058 return NETDEV_TX_OK;
5059 }
5060
b980ac18 5061 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5062 * in order to meet this minimum size requirement.
5063 */
ea5ceeab
TD		 5064 if (unlikely(skb->len < 17)) {
5065 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 5066 return NETDEV_TX_OK;
5067 skb->len = 17;
ea5ceeab 5068 skb_set_tail_pointer(skb, 17);
1cc3bd87 5069 }
9d5c8243 5070
1cc3bd87 5071 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5072}
5073
5074/**
b980ac18
JK		 5075 * igb_tx_timeout - Respond to a Tx Hang
5076 * @netdev: network interface device structure
9d5c8243
AK		 5077 **/
5078static void igb_tx_timeout(struct net_device *netdev)
5079{
5080 struct igb_adapter *adapter = netdev_priv(netdev);
5081 struct e1000_hw *hw = &adapter->hw;
5082
5083 /* Do the reset outside of interrupt context */
5084 adapter->tx_timeout_count++;
f7ba205e 5085
06218a8d 5086 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5087 hw->dev_spec._82575.global_device_reset = true;
5088
9d5c8243 5089 schedule_work(&adapter->reset_task);
265de409
AD		 5090 wr32(E1000_EICS,
5091 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5092}
5093
5094static void igb_reset_task(struct work_struct *work)
5095{
5096 struct igb_adapter *adapter;
5097 adapter = container_of(work, struct igb_adapter, reset_task);
5098
c97ec42a
TI		 5099 igb_dump(adapter);
5100 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5101 igb_reinit_locked(adapter);
5102}
5103
5104/**
b980ac18
JK		 5105 * igb_get_stats64 - Get System Network Statistics
5106 * @netdev: network interface device structure
5107 * @stats: rtnl_link_stats64 pointer
9d5c8243 5108 **/
12dcd86b 5109static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5110 struct rtnl_link_stats64 *stats)
9d5c8243 5111{
12dcd86b
ED		 5112 struct igb_adapter *adapter = netdev_priv(netdev);
5113
5114 spin_lock(&adapter->stats64_lock);
5115 igb_update_stats(adapter, &adapter->stats64);
5116 memcpy(stats, &adapter->stats64, sizeof(*stats));
5117 spin_unlock(&adapter->stats64_lock);
5118
5119 return stats;
9d5c8243
AK		 5120}
5121
5122/**
b980ac18
JK		 5123 * igb_change_mtu - Change the Maximum Transfer Unit
5124 * @netdev: network interface device structure
5125 * @new_mtu: new value for maximum frame size
9d5c8243 5126 *
b980ac18 5127 * Returns 0 on success, negative on failure
9d5c8243
AK		 5128 **/
5129static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5130{
5131 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5132 struct pci_dev *pdev = adapter->pdev;
153285f9 5133 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5134
c809d227 5135 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5136 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5137 return -EINVAL;
5138 }
5139
153285f9 5140#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5141 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5142 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5143 return -EINVAL;
5144 }
5145
2ccd994c
AD		 5146 /* adjust max frame to be at least the size of a standard frame */
5147 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5148 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5149
9d5c8243 5150 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5151 usleep_range(1000, 2000);
73cd78f1 5152
9d5c8243
AK		 5153 /* igb_down has a dependency on max_frame_size */
5154 adapter->max_frame_size = max_frame;
559e9c49 5155
4c844851
AD		 5156 if (netif_running(netdev))
5157 igb_down(adapter);
9d5c8243 5158
090b1795 5159 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5160 netdev->mtu, new_mtu);
5161 netdev->mtu = new_mtu;
5162
5163 if (netif_running(netdev))
5164 igb_up(adapter);
5165 else
5166 igb_reset(adapter);
5167
5168 clear_bit(__IGB_RESETTING, &adapter->state);
5169
5170 return 0;
5171}
5172
5173/**
b980ac18
JK		 5174 * igb_update_stats - Update the board statistics counters
5175 * @adapter: board private structure
9d5c8243 5176 **/
12dcd86b
ED		 5177void igb_update_stats(struct igb_adapter *adapter,
5178 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5179{
5180 struct e1000_hw *hw = &adapter->hw;
5181 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5182 u32 reg, mpc;
9d5c8243 5183 u16 phy_tmp;
3f9c0164
AD		 5184 int i;
5185 u64 bytes, packets;
12dcd86b
ED		 5186 unsigned int start;
5187 u64 _bytes, _packets;
9d5c8243
AK		 5188
5189#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
5190
b980ac18 5191 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5192 * connection is down.
5193 */
5194 if (adapter->link_speed == 0)
5195 return;
5196 if (pci_channel_offline(pdev))
5197 return;
5198
3f9c0164
AD		 5199 bytes = 0;
5200 packets = 0;
7f90128e
AA		 5201
5202 rcu_read_lock();
3f9c0164 5203 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5204 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5205 u32 rqdpc = rd32(E1000_RQDPC(i));
5206 if (hw->mac.type >= e1000_i210)
5207 wr32(E1000_RQDPC(i), 0);
12dcd86b 5208
ae1c07a6
AD		 5209 if (rqdpc) {
5210 ring->rx_stats.drops += rqdpc;
5211 net_stats->rx_fifo_errors += rqdpc;
5212 }
12dcd86b
ED		 5213
5214 do {
57a7744e 5215 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5216 _bytes = ring->rx_stats.bytes;
5217 _packets = ring->rx_stats.packets;
57a7744e 5218 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5219 bytes += _bytes;
5220 packets += _packets;
3f9c0164
AD		 5221 }
5222
128e45eb
AD		 5223 net_stats->rx_bytes = bytes;
5224 net_stats->rx_packets = packets;
3f9c0164
AD		 5225
5226 bytes = 0;
5227 packets = 0;
5228 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5229 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5230 do {
57a7744e 5231 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5232 _bytes = ring->tx_stats.bytes;
5233 _packets = ring->tx_stats.packets;
57a7744e 5234 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5235 bytes += _bytes;
5236 packets += _packets;
3f9c0164 5237 }
128e45eb
AD		 5238 net_stats->tx_bytes = bytes;
5239 net_stats->tx_packets = packets;
7f90128e 5240 rcu_read_unlock();
3f9c0164
AD		 5241
5242 /* read stats registers */
9d5c8243
AK		 5243 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5244 adapter->stats.gprc += rd32(E1000_GPRC);
5245 adapter->stats.gorc += rd32(E1000_GORCL);
5246 rd32(E1000_GORCH); /* clear GORCL */
5247 adapter->stats.bprc += rd32(E1000_BPRC);
5248 adapter->stats.mprc += rd32(E1000_MPRC);
5249 adapter->stats.roc += rd32(E1000_ROC);
5250
5251 adapter->stats.prc64 += rd32(E1000_PRC64);
5252 adapter->stats.prc127 += rd32(E1000_PRC127);
5253 adapter->stats.prc255 += rd32(E1000_PRC255);
5254 adapter->stats.prc511 += rd32(E1000_PRC511);
5255 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5256 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5257 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5258 adapter->stats.sec += rd32(E1000_SEC);
5259
fa3d9a6d
MW		 5260 mpc = rd32(E1000_MPC);
5261 adapter->stats.mpc += mpc;
5262 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5263 adapter->stats.scc += rd32(E1000_SCC);
5264 adapter->stats.ecol += rd32(E1000_ECOL);
5265 adapter->stats.mcc += rd32(E1000_MCC);
5266 adapter->stats.latecol += rd32(E1000_LATECOL);
5267 adapter->stats.dc += rd32(E1000_DC);
5268 adapter->stats.rlec += rd32(E1000_RLEC);
5269 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5270 adapter->stats.xontxc += rd32(E1000_XONTXC);
5271 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5272 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5273 adapter->stats.fcruc += rd32(E1000_FCRUC);
5274 adapter->stats.gptc += rd32(E1000_GPTC);
5275 adapter->stats.gotc += rd32(E1000_GOTCL);
5276 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5277 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5278 adapter->stats.ruc += rd32(E1000_RUC);
5279 adapter->stats.rfc += rd32(E1000_RFC);
5280 adapter->stats.rjc += rd32(E1000_RJC);
5281 adapter->stats.tor += rd32(E1000_TORH);
5282 adapter->stats.tot += rd32(E1000_TOTH);
5283 adapter->stats.tpr += rd32(E1000_TPR);
5284
5285 adapter->stats.ptc64 += rd32(E1000_PTC64);
5286 adapter->stats.ptc127 += rd32(E1000_PTC127);
5287 adapter->stats.ptc255 += rd32(E1000_PTC255);
5288 adapter->stats.ptc511 += rd32(E1000_PTC511);
5289 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5290 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5291
5292 adapter->stats.mptc += rd32(E1000_MPTC);
5293 adapter->stats.bptc += rd32(E1000_BPTC);
5294
2d0b0f69
NN		 5295 adapter->stats.tpt += rd32(E1000_TPT);
5296 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5297
5298 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5299 /* read internal phy specific stats */
5300 reg = rd32(E1000_CTRL_EXT);
5301 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5302 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5303
5304 /* this stat has invalid values on i210/i211 */
5305 if ((hw->mac.type != e1000_i210) &&
5306 (hw->mac.type != e1000_i211))
5307 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5308 }
5309
9d5c8243
AK		 5310 adapter->stats.tsctc += rd32(E1000_TSCTC);
5311 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5312
5313 adapter->stats.iac += rd32(E1000_IAC);
5314 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5315 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5316 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5317 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5318 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5319 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5320 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5321 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5322
5323 /* Fill out the OS statistics structure */
128e45eb
AD		 5324 net_stats->multicast = adapter->stats.mprc;
5325 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5326
5327 /* Rx Errors */
5328
5329 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5330 * our own version based on RUC and ROC
5331 */
128e45eb 5332 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5333 adapter->stats.crcerrs + adapter->stats.algnerrc +
5334 adapter->stats.ruc + adapter->stats.roc +
5335 adapter->stats.cexterr;
128e45eb
AD		 5336 net_stats->rx_length_errors = adapter->stats.ruc +
5337 adapter->stats.roc;
5338 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5339 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5340 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5341
5342 /* Tx Errors */
128e45eb
AD		 5343 net_stats->tx_errors = adapter->stats.ecol +
5344 adapter->stats.latecol;
5345 net_stats->tx_aborted_errors = adapter->stats.ecol;
5346 net_stats->tx_window_errors = adapter->stats.latecol;
5347 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5348
5349 /* Tx Dropped needs to be maintained elsewhere */
5350
5351 /* Phy Stats */
5352 if (hw->phy.media_type == e1000_media_type_copper) {
5353 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5354 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5355 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5356 adapter->phy_stats.idle_errors += phy_tmp;
5357 }
5358 }
5359
5360 /* Management Stats */
5361 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5362 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5363 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5364
5365 /* OS2BMC Stats */
5366 reg = rd32(E1000_MANC);
5367 if (reg & E1000_MANC_EN_BMC2OS) {
5368 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5369 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5370 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5371 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5372 }
9d5c8243
AK		 5373}
5374
9d5c8243
AK		 5375static irqreturn_t igb_msix_other(int irq, void *data)
5376{
047e0030 5377 struct igb_adapter *adapter = data;
9d5c8243 5378 struct e1000_hw *hw = &adapter->hw;
844290e5 5379 u32 icr = rd32(E1000_ICR);
844290e5 5380 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5381
7f081d40
AD		 5382 if (icr & E1000_ICR_DRSTA)
5383 schedule_work(&adapter->reset_task);
5384
047e0030 5385 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5386 /* HW is reporting DMA is out of sync */
5387 adapter->stats.doosync++;
13800469
GR		 5388 /* The DMA Out of Sync is also indication of a spoof event
5389 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5390 * see if it is really a spoof event.
5391 */
13800469 5392 igb_check_wvbr(adapter);
dda0e083 5393 }
eebbbdba 5394
4ae196df
AD		 5395 /* Check for a mailbox event */
5396 if (icr & E1000_ICR_VMMB)
5397 igb_msg_task(adapter);
5398
5399 if (icr & E1000_ICR_LSC) {
5400 hw->mac.get_link_status = 1;
5401 /* guard against interrupt when we're going down */
5402 if (!test_bit(__IGB_DOWN, &adapter->state))
5403 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5404 }
5405
1f6e8178
MV		 5406 if (icr & E1000_ICR_TS) {
5407 u32 tsicr = rd32(E1000_TSICR);
5408
5409 if (tsicr & E1000_TSICR_TXTS) {
5410 /* acknowledge the interrupt */
5411 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5412 /* retrieve hardware timestamp */
5413 schedule_work(&adapter->ptp_tx_work);
5414 }
5415 }
1f6e8178 5416
844290e5 5417 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5418
5419 return IRQ_HANDLED;
5420}
5421
047e0030 5422static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5423{
26b39276 5424 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5425 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5426
047e0030
AD		 5427 if (!q_vector->set_itr)
5428 return;
73cd78f1 5429
047e0030
AD		 5430 if (!itr_val)
5431 itr_val = 0x4;
661086df 5432
26b39276
AD		 5433 if (adapter->hw.mac.type == e1000_82575)
5434 itr_val |= itr_val << 16;
661086df 5435 else
0ba82994 5436 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5437
047e0030
AD		 5438 writel(itr_val, q_vector->itr_register);
5439 q_vector->set_itr = 0;
6eb5a7f1
AD		 5440}
5441
047e0030 5442static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5443{
047e0030 5444 struct igb_q_vector *q_vector = data;
9d5c8243 5445
047e0030
AD		 5446 /* Write the ITR value calculated from the previous interrupt. */
5447 igb_write_itr(q_vector);
9d5c8243 5448
047e0030 5449 napi_schedule(&q_vector->napi);
844290e5 5450
047e0030 5451 return IRQ_HANDLED;
fe4506b6
JC		 5452}
5453
421e02f0 5454#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5455static void igb_update_tx_dca(struct igb_adapter *adapter,
5456 struct igb_ring *tx_ring,
5457 int cpu)
5458{
5459 struct e1000_hw *hw = &adapter->hw;
5460 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5461
5462 if (hw->mac.type != e1000_82575)
5463 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5464
b980ac18 5465 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5466 * DCA is enabled. This is due to a known issue in some chipsets
5467 * which will cause the DCA tag to be cleared.
5468 */
5469 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5470 E1000_DCA_TXCTRL_DATA_RRO_EN |
5471 E1000_DCA_TXCTRL_DESC_DCA_EN;
5472
5473 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5474}
5475
5476static void igb_update_rx_dca(struct igb_adapter *adapter,
5477 struct igb_ring *rx_ring,
5478 int cpu)
5479{
5480 struct e1000_hw *hw = &adapter->hw;
5481 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5482
5483 if (hw->mac.type != e1000_82575)
5484 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5485
b980ac18 5486 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5487 * DCA is enabled. This is due to a known issue in some chipsets
5488 * which will cause the DCA tag to be cleared.
5489 */
5490 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5491 E1000_DCA_RXCTRL_DESC_DCA_EN;
5492
5493 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5494}
5495
047e0030 5496static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5497{
047e0030 5498 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5499 int cpu = get_cpu();
fe4506b6 5500
047e0030
AD		 5501 if (q_vector->cpu == cpu)
5502 goto out_no_update;
5503
6a05004a
AD		 5504 if (q_vector->tx.ring)
5505 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5506
5507 if (q_vector->rx.ring)
5508 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5509
047e0030
AD		 5510 q_vector->cpu = cpu;
5511out_no_update:
fe4506b6
JC		 5512 put_cpu();
5513}
5514
5515static void igb_setup_dca(struct igb_adapter *adapter)
5516{
7e0e99ef 5517 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5518 int i;
5519
7dfc16fa 5520 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5521 return;
5522
7e0e99ef
AD		 5523 /* Always use CB2 mode, difference is masked in the CB driver. */
5524 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5525
047e0030 5526 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5527 adapter->q_vector[i]->cpu = -1;
5528 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5529 }
5530}
5531
5532static int __igb_notify_dca(struct device *dev, void *data)
5533{
5534 struct net_device *netdev = dev_get_drvdata(dev);
5535 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5536 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5537 struct e1000_hw *hw = &adapter->hw;
5538 unsigned long event = *(unsigned long *)data;
5539
5540 switch (event) {
5541 case DCA_PROVIDER_ADD:
5542 /* if already enabled, don't do it again */
7dfc16fa 5543 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5544 break;
fe4506b6 5545 if (dca_add_requester(dev) == 0) {
bbd98fe4 5546 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5547 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5548 igb_setup_dca(adapter);
5549 break;
5550 }
5551 /* Fall Through since DCA is disabled. */
5552 case DCA_PROVIDER_REMOVE:
7dfc16fa 5553 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5554 /* without this a class_device is left
b980ac18
JK		 5555 * hanging around in the sysfs model
5556 */
fe4506b6 5557 dca_remove_requester(dev);
090b1795 5558 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5559 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5560 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5561 }
5562 break;
5563 }
bbd98fe4 5564
fe4506b6 5565 return 0;
9d5c8243
AK		 5566}
5567
fe4506b6 5568static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5569 void *p)
fe4506b6
JC		 5570{
5571 int ret_val;
5572
5573 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5574 __igb_notify_dca);
fe4506b6
JC		 5575
5576 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5577}
421e02f0 5578#endif /* CONFIG_IGB_DCA */
9d5c8243 5579
0224d663
GR		 5580#ifdef CONFIG_PCI_IOV
5581static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5582{
5583 unsigned char mac_addr[ETH_ALEN];
0224d663 5584
5ac6f91d 5585 eth_zero_addr(mac_addr);
0224d663
GR		 5586 igb_set_vf_mac(adapter, vf, mac_addr);
5587
70ea4783
LL		 5588 /* By default spoof check is enabled for all VFs */
5589 adapter->vf_data[vf].spoofchk_enabled = true;
5590
f557147c 5591 return 0;
0224d663
GR		 5592}
5593
0224d663 5594#endif
4ae196df
AD		 5595static void igb_ping_all_vfs(struct igb_adapter *adapter)
5596{
5597 struct e1000_hw *hw = &adapter->hw;
5598 u32 ping;
5599 int i;
5600
5601 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5602 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5603 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5604 ping |= E1000_VT_MSGTYPE_CTS;
5605 igb_write_mbx(hw, &ping, 1, i);
5606 }
5607}
5608
7d5753f0
AD		 5609static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5610{
5611 struct e1000_hw *hw = &adapter->hw;
5612 u32 vmolr = rd32(E1000_VMOLR(vf));
5613 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5614
d85b9004 5615 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5616 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5617 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5618
5619 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5620 vmolr |= E1000_VMOLR_MPME;
d85b9004 5621 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5622 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5623 } else {
b980ac18 5624 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5625 * flag we need to write the hashes to the MTA as this step
5626 * was previously skipped
5627 */
5628 if (vf_data->num_vf_mc_hashes > 30) {
5629 vmolr |= E1000_VMOLR_MPME;
5630 } else if (vf_data->num_vf_mc_hashes) {
5631 int j;
9005df38 5632
7d5753f0
AD		 5633 vmolr |= E1000_VMOLR_ROMPE;
5634 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5635 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5636 }
5637 }
5638
5639 wr32(E1000_VMOLR(vf), vmolr);
5640
5641 /* there are flags left unprocessed, likely not supported */
5642 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5643 return -EINVAL;
5644
5645 return 0;
7d5753f0
AD		 5646}
5647
4ae196df
AD		 5648static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5649 u32 *msgbuf, u32 vf)
5650{
5651 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5652 u16 *hash_list = (u16 *)&msgbuf[1];
5653 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5654 int i;
5655
7d5753f0 5656 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5657 * to this VF for later use to restore when the PF multi cast
5658 * list changes
5659 */
5660 vf_data->num_vf_mc_hashes = n;
5661
7d5753f0
AD		 5662 /* only up to 30 hash values supported */
5663 if (n > 30)
5664 n = 30;
5665
5666 /* store the hashes for later use */
4ae196df 5667 for (i = 0; i < n; i++)
a419aef8 5668 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5669
5670 /* Flush and reset the mta with the new values */
ff41f8dc 5671 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5672
5673 return 0;
5674}
5675
5676static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5677{
5678 struct e1000_hw *hw = &adapter->hw;
5679 struct vf_data_storage *vf_data;
5680 int i, j;
5681
5682 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5683 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5684
7d5753f0
AD		 5685 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5686
4ae196df 5687 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5688
5689 if ((vf_data->num_vf_mc_hashes > 30) ||
5690 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5691 vmolr |= E1000_VMOLR_MPME;
5692 } else if (vf_data->num_vf_mc_hashes) {
5693 vmolr |= E1000_VMOLR_ROMPE;
5694 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5695 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5696 }
5697 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5698 }
5699}
5700
5701static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5702{
5703 struct e1000_hw *hw = &adapter->hw;
5704 u32 pool_mask, reg, vid;
5705 int i;
5706
5707 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5708
5709 /* Find the vlan filter for this id */
5710 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5711 reg = rd32(E1000_VLVF(i));
5712
5713 /* remove the vf from the pool */
5714 reg &= ~pool_mask;
5715
5716 /* if pool is empty then remove entry from vfta */
5717 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5718 (reg & E1000_VLVF_VLANID_ENABLE)) {
5719 reg = 0;
5720 vid = reg & E1000_VLVF_VLANID_MASK;
5721 igb_vfta_set(hw, vid, false);
5722 }
5723
5724 wr32(E1000_VLVF(i), reg);
5725 }
ae641bdc
AD		 5726
5727 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5728}
5729
5730static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5731{
5732 struct e1000_hw *hw = &adapter->hw;
5733 u32 reg, i;
5734
51466239
AD		 5735 /* The vlvf table only exists on 82576 hardware and newer */
5736 if (hw->mac.type < e1000_82576)
5737 return -1;
5738
5739 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5740 if (!adapter->vfs_allocated_count)
5741 return -1;
5742
5743 /* Find the vlan filter for this id */
5744 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5745 reg = rd32(E1000_VLVF(i));
5746 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5747 vid == (reg & E1000_VLVF_VLANID_MASK))
5748 break;
5749 }
5750
5751 if (add) {
5752 if (i == E1000_VLVF_ARRAY_SIZE) {
5753 /* Did not find a matching VLAN ID entry that was
5754 * enabled. Search for a free filter entry, i.e.
5755 * one without the enable bit set
5756 */
5757 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5758 reg = rd32(E1000_VLVF(i));
5759 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5760 break;
5761 }
5762 }
5763 if (i < E1000_VLVF_ARRAY_SIZE) {
5764 /* Found an enabled/available entry */
5765 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5766
5767 /* if !enabled we need to set this up in vfta */
5768 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5769 /* add VID to filter table */
5770 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5771 reg |= E1000_VLVF_VLANID_ENABLE;
5772 }
cad6d05f
AD		 5773 reg &= ~E1000_VLVF_VLANID_MASK;
5774 reg |= vid;
4ae196df 5775 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5776
5777 /* do not modify RLPML for PF devices */
5778 if (vf >= adapter->vfs_allocated_count)
5779 return 0;
5780
5781 if (!adapter->vf_data[vf].vlans_enabled) {
5782 u32 size;
9005df38 5783
ae641bdc
AD		 5784 reg = rd32(E1000_VMOLR(vf));
5785 size = reg & E1000_VMOLR_RLPML_MASK;
5786 size += 4;
5787 reg &= ~E1000_VMOLR_RLPML_MASK;
5788 reg |= size;
5789 wr32(E1000_VMOLR(vf), reg);
5790 }
ae641bdc 5791
51466239 5792 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5793 }
5794 } else {
5795 if (i < E1000_VLVF_ARRAY_SIZE) {
5796 /* remove vf from the pool */
5797 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5798 /* if pool is empty then remove entry from vfta */
5799 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5800 reg = 0;
5801 igb_vfta_set(hw, vid, false);
5802 }
5803 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5804
5805 /* do not modify RLPML for PF devices */
5806 if (vf >= adapter->vfs_allocated_count)
5807 return 0;
5808
5809 adapter->vf_data[vf].vlans_enabled--;
5810 if (!adapter->vf_data[vf].vlans_enabled) {
5811 u32 size;
9005df38 5812
ae641bdc
AD		 5813 reg = rd32(E1000_VMOLR(vf));
5814 size = reg & E1000_VMOLR_RLPML_MASK;
5815 size -= 4;
5816 reg &= ~E1000_VMOLR_RLPML_MASK;
5817 reg |= size;
5818 wr32(E1000_VMOLR(vf), reg);
5819 }
4ae196df
AD		 5820 }
5821 }
8151d294
WM		 5822 return 0;
5823}
5824
5825static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5826{
5827 struct e1000_hw *hw = &adapter->hw;
5828
5829 if (vid)
5830 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5831 else
5832 wr32(E1000_VMVIR(vf), 0);
5833}
5834
5835static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5836 int vf, u16 vlan, u8 qos)
5837{
5838 int err = 0;
5839 struct igb_adapter *adapter = netdev_priv(netdev);
5840
5841 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5842 return -EINVAL;
5843 if (vlan || qos) {
5844 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5845 if (err)
5846 goto out;
5847 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5848 igb_set_vmolr(adapter, vf, !vlan);
5849 adapter->vf_data[vf].pf_vlan = vlan;
5850 adapter->vf_data[vf].pf_qos = qos;
5851 dev_info(&adapter->pdev->dev,
5852 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5853 if (test_bit(__IGB_DOWN, &adapter->state)) {
5854 dev_warn(&adapter->pdev->dev,
b980ac18 5855 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5856 dev_warn(&adapter->pdev->dev,
b980ac18 5857 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5858 }
5859 } else {
5860 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5861 false, vf);
8151d294
WM		 5862 igb_set_vmvir(adapter, vlan, vf);
5863 igb_set_vmolr(adapter, vf, true);
5864 adapter->vf_data[vf].pf_vlan = 0;
5865 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5866 }
8151d294 5867out:
b980ac18 5868 return err;
4ae196df
AD		 5869}
5870
6f3dc319
GR		 5871static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5872{
5873 struct e1000_hw *hw = &adapter->hw;
5874 int i;
5875 u32 reg;
5876
5877 /* Find the vlan filter for this id */
5878 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5879 reg = rd32(E1000_VLVF(i));
5880 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5881 vid == (reg & E1000_VLVF_VLANID_MASK))
5882 break;
5883 }
5884
5885 if (i >= E1000_VLVF_ARRAY_SIZE)
5886 i = -1;
5887
5888 return i;
5889}
5890
4ae196df
AD		 5891static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5892{
6f3dc319 5893 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5894 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5895 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5896 int err = 0;
4ae196df 5897
6f3dc319
GR		 5898 /* If in promiscuous mode we need to make sure the PF also has
5899 * the VLAN filter set.
5900 */
5901 if (add && (adapter->netdev->flags & IFF_PROMISC))
5902 err = igb_vlvf_set(adapter, vid, add,
5903 adapter->vfs_allocated_count);
5904 if (err)
5905 goto out;
5906
5907 err = igb_vlvf_set(adapter, vid, add, vf);
5908
5909 if (err)
5910 goto out;
5911
5912 /* Go through all the checks to see if the VLAN filter should
5913 * be wiped completely.
5914 */
5915 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5916 u32 vlvf, bits;
6f3dc319 5917 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 5918
6f3dc319
GR		 5919 if (regndx < 0)
5920 goto out;
5921 /* See if any other pools are set for this VLAN filter
5922 * entry other than the PF.
5923 */
5924 vlvf = bits = rd32(E1000_VLVF(regndx));
5925 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5926 adapter->vfs_allocated_count);
5927 /* If the filter was removed then ensure PF pool bit
5928 * is cleared if the PF only added itself to the pool
5929 * because the PF is in promiscuous mode.
5930 */
5931 if ((vlvf & VLAN_VID_MASK) == vid &&
5932 !test_bit(vid, adapter->active_vlans) &&
5933 !bits)
5934 igb_vlvf_set(adapter, vid, add,
5935 adapter->vfs_allocated_count);
5936 }
5937
5938out:
5939 return err;
4ae196df
AD		 5940}
5941
f2ca0dbe 5942static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5943{
8fa7e0f7
GR		 5944 /* clear flags - except flag that indicates PF has set the MAC */
5945 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5946 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5947
5948 /* reset offloads to defaults */
8151d294 5949 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5950
5951 /* reset vlans for device */
5952 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5953 if (adapter->vf_data[vf].pf_vlan)
5954 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5955 adapter->vf_data[vf].pf_vlan,
5956 adapter->vf_data[vf].pf_qos);
5957 else
5958 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5959
5960 /* reset multicast table array for vf */
5961 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5962
5963 /* Flush and reset the mta with the new values */
ff41f8dc 5964 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5965}
5966
f2ca0dbe
AD		 5967static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5968{
5969 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5970
5ac6f91d 5971 /* clear mac address as we were hotplug removed/added */
8151d294 5972 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5973 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5974
5975 /* process remaining reset events */
5976 igb_vf_reset(adapter, vf);
5977}
5978
5979static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5980{
5981 struct e1000_hw *hw = &adapter->hw;
5982 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5983 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5984 u32 reg, msgbuf[3];
5985 u8 *addr = (u8 *)(&msgbuf[1]);
5986
5987 /* process all the same items cleared in a function level reset */
f2ca0dbe 5988 igb_vf_reset(adapter, vf);
4ae196df
AD		 5989
5990 /* set vf mac address */
26ad9178 5991 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5992
5993 /* enable transmit and receive for vf */
5994 reg = rd32(E1000_VFTE);
5995 wr32(E1000_VFTE, reg | (1 << vf));
5996 reg = rd32(E1000_VFRE);
5997 wr32(E1000_VFRE, reg | (1 << vf));
5998
8fa7e0f7 5999 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6000
6001 /* reply to reset with ack and vf mac address */
6002 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 6003 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 6004 igb_write_mbx(hw, msgbuf, 3, vf);
6005}
6006
6007static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6008{
b980ac18 6009 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6010 * starting at the second 32 bit word of the msg array
6011 */
f2ca0dbe
AD		 6012 unsigned char *addr = (char *)&msg[1];
6013 int err = -1;
4ae196df 6014
f2ca0dbe
AD		 6015 if (is_valid_ether_addr(addr))
6016 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6017
f2ca0dbe 6018 return err;
4ae196df
AD		 6019}
6020
6021static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6022{
6023 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6024 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6025 u32 msg = E1000_VT_MSGTYPE_NACK;
6026
6027 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6028 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6029 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6030 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6031 vf_data->last_nack = jiffies;
4ae196df
AD		 6032 }
6033}
6034
f2ca0dbe 6035static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6036{
f2ca0dbe
AD		 6037 struct pci_dev *pdev = adapter->pdev;
6038 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6039 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6040 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6041 s32 retval;
6042
f2ca0dbe 6043 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6044
fef45f4c
AD		 6045 if (retval) {
6046 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6047 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6048 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6049 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6050 return;
6051 goto out;
6052 }
4ae196df
AD		 6053
6054 /* this is a message we already processed, do nothing */
6055 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6056 return;
4ae196df 6057
b980ac18 6058 /* until the vf completes a reset it should not be
4ae196df
AD		 6059 * allowed to start any configuration.
6060 */
4ae196df
AD		 6061 if (msgbuf[0] == E1000_VF_RESET) {
6062 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6063 return;
4ae196df
AD		 6064 }
6065
f2ca0dbe 6066 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6067 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6068 return;
6069 retval = -1;
6070 goto out;
4ae196df
AD		 6071 }
6072
6073 switch ((msgbuf[0] & 0xFFFF)) {
6074 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6075 retval = -EINVAL;
6076 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6077 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6078 else
6079 dev_warn(&pdev->dev,
b980ac18
JK		 6080 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6081 vf);
4ae196df 6082 break;
7d5753f0
AD		 6083 case E1000_VF_SET_PROMISC:
6084 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6085 break;
4ae196df
AD		 6086 case E1000_VF_SET_MULTICAST:
6087 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6088 break;
6089 case E1000_VF_SET_LPE:
6090 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6091 break;
6092 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6093 retval = -1;
6094 if (vf_data->pf_vlan)
6095 dev_warn(&pdev->dev,
b980ac18
JK		 6096 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6097 vf);
8151d294
WM		 6098 else
6099 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6100 break;
6101 default:
090b1795 6102 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6103 retval = -1;
6104 break;
6105 }
6106
fef45f4c
AD		 6107 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6108out:
4ae196df
AD		 6109 /* notify the VF of the results of what it sent us */
6110 if (retval)
6111 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6112 else
6113 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6114
4ae196df 6115 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6116}
4ae196df 6117
f2ca0dbe
AD		 6118static void igb_msg_task(struct igb_adapter *adapter)
6119{
6120 struct e1000_hw *hw = &adapter->hw;
6121 u32 vf;
6122
6123 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6124 /* process any reset requests */
6125 if (!igb_check_for_rst(hw, vf))
6126 igb_vf_reset_event(adapter, vf);
6127
6128 /* process any messages pending */
6129 if (!igb_check_for_msg(hw, vf))
6130 igb_rcv_msg_from_vf(adapter, vf);
6131
6132 /* process any acks */
6133 if (!igb_check_for_ack(hw, vf))
6134 igb_rcv_ack_from_vf(adapter, vf);
6135 }
4ae196df
AD		 6136}
6137
68d480c4
AD		 6138/**
6139 * igb_set_uta - Set unicast filter table address
6140 * @adapter: board private structure
6141 *
6142 * The unicast table address is a register array of 32-bit registers.
6143 * The table is meant to be used in a way similar to how the MTA is used
6144 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6145 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6146 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6147 **/
6148static void igb_set_uta(struct igb_adapter *adapter)
6149{
6150 struct e1000_hw *hw = &adapter->hw;
6151 int i;
6152
6153 /* The UTA table only exists on 82576 hardware and newer */
6154 if (hw->mac.type < e1000_82576)
6155 return;
6156
6157 /* we only need to do this if VMDq is enabled */
6158 if (!adapter->vfs_allocated_count)
6159 return;
6160
6161 for (i = 0; i < hw->mac.uta_reg_count; i++)
6162 array_wr32(E1000_UTA, i, ~0);
6163}
6164
9d5c8243 6165/**
b980ac18
JK		 6166 * igb_intr_msi - Interrupt Handler
6167 * @irq: interrupt number
6168 * @data: pointer to a network interface device structure
9d5c8243
AK		 6169 **/
6170static irqreturn_t igb_intr_msi(int irq, void *data)
6171{
047e0030
AD		 6172 struct igb_adapter *adapter = data;
6173 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6174 struct e1000_hw *hw = &adapter->hw;
6175 /* read ICR disables interrupts using IAM */
6176 u32 icr = rd32(E1000_ICR);
6177
047e0030 6178 igb_write_itr(q_vector);
9d5c8243 6179
7f081d40
AD		 6180 if (icr & E1000_ICR_DRSTA)
6181 schedule_work(&adapter->reset_task);
6182
047e0030 6183 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6184 /* HW is reporting DMA is out of sync */
6185 adapter->stats.doosync++;
6186 }
6187
9d5c8243
AK		 6188 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6189 hw->mac.get_link_status = 1;
6190 if (!test_bit(__IGB_DOWN, &adapter->state))
6191 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6192 }
6193
1f6e8178
MV		 6194 if (icr & E1000_ICR_TS) {
6195 u32 tsicr = rd32(E1000_TSICR);
6196
6197 if (tsicr & E1000_TSICR_TXTS) {
6198 /* acknowledge the interrupt */
6199 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6200 /* retrieve hardware timestamp */
6201 schedule_work(&adapter->ptp_tx_work);
6202 }
6203 }
1f6e8178 6204
047e0030 6205 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6206
6207 return IRQ_HANDLED;
6208}
6209
6210/**
b980ac18
JK		 6211 * igb_intr - Legacy Interrupt Handler
6212 * @irq: interrupt number
6213 * @data: pointer to a network interface device structure
9d5c8243
AK		 6214 **/
6215static irqreturn_t igb_intr(int irq, void *data)
6216{
047e0030
AD		 6217 struct igb_adapter *adapter = data;
6218 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6219 struct e1000_hw *hw = &adapter->hw;
6220 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6221 * need for the IMC write
6222 */
9d5c8243 6223 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6224
6225 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6226 * not set, then the adapter didn't send an interrupt
6227 */
9d5c8243
AK		 6228 if (!(icr & E1000_ICR_INT_ASSERTED))
6229 return IRQ_NONE;
6230
0ba82994
AD		 6231 igb_write_itr(q_vector);
6232
7f081d40
AD		 6233 if (icr & E1000_ICR_DRSTA)
6234 schedule_work(&adapter->reset_task);
6235
047e0030 6236 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6237 /* HW is reporting DMA is out of sync */
6238 adapter->stats.doosync++;
6239 }
6240
9d5c8243
AK		 6241 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6242 hw->mac.get_link_status = 1;
6243 /* guard against interrupt when we're going down */
6244 if (!test_bit(__IGB_DOWN, &adapter->state))
6245 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6246 }
6247
1f6e8178
MV		 6248 if (icr & E1000_ICR_TS) {
6249 u32 tsicr = rd32(E1000_TSICR);
6250
6251 if (tsicr & E1000_TSICR_TXTS) {
6252 /* acknowledge the interrupt */
6253 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6254 /* retrieve hardware timestamp */
6255 schedule_work(&adapter->ptp_tx_work);
6256 }
6257 }
1f6e8178 6258
047e0030 6259 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6260
6261 return IRQ_HANDLED;
6262}
6263
c50b52a0 6264static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6265{
047e0030 6266 struct igb_adapter *adapter = q_vector->adapter;
46544258 6267 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6268
0ba82994
AD		 6269 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6270 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6271 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6272 igb_set_itr(q_vector);
46544258 6273 else
047e0030 6274 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6275 }
6276
46544258 6277 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6278 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6279 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6280 else
6281 igb_irq_enable(adapter);
6282 }
9d5c8243
AK		 6283}
6284
46544258 6285/**
b980ac18
JK		 6286 * igb_poll - NAPI Rx polling callback
6287 * @napi: napi polling structure
6288 * @budget: count of how many packets we should handle
46544258
AD		 6289 **/
6290static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6291{
047e0030 6292 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6293 struct igb_q_vector,
6294 napi);
16eb8815 6295 bool clean_complete = true;
9d5c8243 6296
421e02f0 6297#ifdef CONFIG_IGB_DCA
047e0030
AD		 6298 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6299 igb_update_dca(q_vector);
fe4506b6 6300#endif
0ba82994 6301 if (q_vector->tx.ring)
13fde97a 6302 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6303
0ba82994 6304 if (q_vector->rx.ring)
cd392f5c 6305 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6306
16eb8815
AD		 6307 /* If all work not completed, return budget and keep polling */
6308 if (!clean_complete)
6309 return budget;
46544258 6310
9d5c8243 6311 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6312 napi_complete(napi);
6313 igb_ring_irq_enable(q_vector);
9d5c8243 6314
16eb8815 6315 return 0;
9d5c8243 6316}
6d8126f9 6317
9d5c8243 6318/**
b980ac18
JK		 6319 * igb_clean_tx_irq - Reclaim resources after transmit completes
6320 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6321 *
b980ac18 6322 * returns true if ring is completely cleaned
9d5c8243 6323 **/
047e0030 6324static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6325{
047e0030 6326 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6327 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6328 struct igb_tx_buffer *tx_buffer;
f4128785 6329 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6330 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6331 unsigned int budget = q_vector->tx.work_limit;
8542db05 6332 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6333
13fde97a
AD		 6334 if (test_bit(__IGB_DOWN, &adapter->state))
6335 return true;
0e014cb1 6336
06034649 6337 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6338 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6339 i -= tx_ring->count;
9d5c8243 6340
f4128785
AD		 6341 do {
6342 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6343
6344 /* if next_to_watch is not set then there is no work pending */
6345 if (!eop_desc)
6346 break;
13fde97a 6347
f4128785 6348 /* prevent any other reads prior to eop_desc */
70d289bc 6349 read_barrier_depends();
f4128785 6350
13fde97a
AD		 6351 /* if DD is not set pending work has not been completed */
6352 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6353 break;
6354
8542db05
AD		 6355 /* clear next_to_watch to prevent false hangs */
6356 tx_buffer->next_to_watch = NULL;
9d5c8243 6357
ebe42d16
AD		 6358 /* update the statistics for this packet */
6359 total_bytes += tx_buffer->bytecount;
6360 total_packets += tx_buffer->gso_segs;
13fde97a 6361
ebe42d16
AD		 6362 /* free the skb */
6363 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6364
ebe42d16
AD		 6365 /* unmap skb header data */
6366 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6367 dma_unmap_addr(tx_buffer, dma),
6368 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6369 DMA_TO_DEVICE);
6370
c9f14bf3
AD		 6371 /* clear tx_buffer data */
6372 tx_buffer->skb = NULL;
6373 dma_unmap_len_set(tx_buffer, len, 0);
6374
ebe42d16
AD		 6375 /* clear last DMA location and unmap remaining buffers */
6376 while (tx_desc != eop_desc) {
13fde97a
AD		 6377 tx_buffer++;
6378 tx_desc++;
9d5c8243 6379 i++;
8542db05
AD		 6380 if (unlikely(!i)) {
6381 i -= tx_ring->count;
06034649 6382 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6383 tx_desc = IGB_TX_DESC(tx_ring, 0);
6384 }
ebe42d16
AD		 6385
6386 /* unmap any remaining paged data */
c9f14bf3 6387 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6388 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6389 dma_unmap_addr(tx_buffer, dma),
6390 dma_unmap_len(tx_buffer, len),
ebe42d16 6391 DMA_TO_DEVICE);
c9f14bf3 6392 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6393 }
6394 }
6395
ebe42d16
AD		 6396 /* move us one more past the eop_desc for start of next pkt */
6397 tx_buffer++;
6398 tx_desc++;
6399 i++;
6400 if (unlikely(!i)) {
6401 i -= tx_ring->count;
6402 tx_buffer = tx_ring->tx_buffer_info;
6403 tx_desc = IGB_TX_DESC(tx_ring, 0);
6404 }
f4128785
AD		 6405
6406 /* issue prefetch for next Tx descriptor */
6407 prefetch(tx_desc);
6408
6409 /* update budget accounting */
6410 budget--;
6411 } while (likely(budget));
0e014cb1 6412
bdbc0631
ED		 6413 netdev_tx_completed_queue(txring_txq(tx_ring),
6414 total_packets, total_bytes);
8542db05 6415 i += tx_ring->count;
9d5c8243 6416 tx_ring->next_to_clean = i;
13fde97a
AD		 6417 u64_stats_update_begin(&tx_ring->tx_syncp);
6418 tx_ring->tx_stats.bytes += total_bytes;
6419 tx_ring->tx_stats.packets += total_packets;
6420 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6421 q_vector->tx.total_bytes += total_bytes;
6422 q_vector->tx.total_packets += total_packets;
9d5c8243 6423
6d095fa8 6424 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6425 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6426
9d5c8243 6427 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6428 * check with the clearing of time_stamp and movement of i
6429 */
6d095fa8 6430 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6431 if (tx_buffer->next_to_watch &&
8542db05 6432 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6433 (adapter->tx_timeout_factor * HZ)) &&
6434 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6435
9d5c8243 6436 /* detected Tx unit hang */
59d71989 6437 dev_err(tx_ring->dev,
9d5c8243 6438 "Detected Tx Unit Hang\n"
2d064c06 6439 " Tx Queue <%d>\n"
9d5c8243
AK		 6440 " TDH <%x>\n"
6441 " TDT <%x>\n"
6442 " next_to_use <%x>\n"
6443 " next_to_clean <%x>\n"
9d5c8243
AK		 6444 "buffer_info[next_to_clean]\n"
6445 " time_stamp <%lx>\n"
8542db05 6446 " next_to_watch <%p>\n"
9d5c8243
AK		 6447 " jiffies <%lx>\n"
6448 " desc.status <%x>\n",
2d064c06 6449 tx_ring->queue_index,
238ac817 6450 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6451 readl(tx_ring->tail),
9d5c8243
AK		 6452 tx_ring->next_to_use,
6453 tx_ring->next_to_clean,
8542db05 6454 tx_buffer->time_stamp,
f4128785 6455 tx_buffer->next_to_watch,
9d5c8243 6456 jiffies,
f4128785 6457 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6458 netif_stop_subqueue(tx_ring->netdev,
6459 tx_ring->queue_index);
6460
6461 /* we are about to reset, no point in enabling stuff */
6462 return true;
9d5c8243
AK		 6463 }
6464 }
13fde97a 6465
21ba6fe1 6466#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6467 if (unlikely(total_packets &&
b980ac18
JK		 6468 netif_carrier_ok(tx_ring->netdev) &&
6469 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6470 /* Make sure that anybody stopping the queue after this
6471 * sees the new next_to_clean.
6472 */
6473 smp_mb();
6474 if (__netif_subqueue_stopped(tx_ring->netdev,
6475 tx_ring->queue_index) &&
6476 !(test_bit(__IGB_DOWN, &adapter->state))) {
6477 netif_wake_subqueue(tx_ring->netdev,
6478 tx_ring->queue_index);
6479
6480 u64_stats_update_begin(&tx_ring->tx_syncp);
6481 tx_ring->tx_stats.restart_queue++;
6482 u64_stats_update_end(&tx_ring->tx_syncp);
6483 }
6484 }
6485
6486 return !!budget;
9d5c8243
AK		 6487}
6488
cbc8e55f 6489/**
b980ac18
JK		 6490 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6491 * @rx_ring: rx descriptor ring to store buffers on
6492 * @old_buff: donor buffer to have page reused
cbc8e55f 6493 *
b980ac18 6494 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6495 **/
6496static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6497 struct igb_rx_buffer *old_buff)
6498{
6499 struct igb_rx_buffer *new_buff;
6500 u16 nta = rx_ring->next_to_alloc;
6501
6502 new_buff = &rx_ring->rx_buffer_info[nta];
6503
6504 /* update, and store next to alloc */
6505 nta++;
6506 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6507
6508 /* transfer page from old buffer to new buffer */
a1f63473 6509 *new_buff = *old_buff;
cbc8e55f
AD		 6510
6511 /* sync the buffer for use by the device */
6512 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6513 old_buff->page_offset,
de78d1f9 6514 IGB_RX_BUFSZ,
cbc8e55f
AD		 6515 DMA_FROM_DEVICE);
6516}
6517
74e238ea
AD		 6518static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6519 struct page *page,
6520 unsigned int truesize)
6521{
6522 /* avoid re-using remote pages */
6523 if (unlikely(page_to_nid(page) != numa_node_id()))
6524 return false;
6525
6526#if (PAGE_SIZE < 8192)
6527 /* if we are only owner of page we can reuse it */
6528 if (unlikely(page_count(page) != 1))
6529 return false;
6530
6531 /* flip page offset to other buffer */
6532 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6533
6534 /* since we are the only owner of the page and we need to
6535 * increment it, just set the value to 2 in order to avoid
6536 * an unnecessary locked operation
6537 */
6538 atomic_set(&page->_count, 2);
6539#else
6540 /* move offset up to the next cache line */
6541 rx_buffer->page_offset += truesize;
6542
6543 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6544 return false;
6545
6546 /* bump ref count on page before it is given to the stack */
6547 get_page(page);
6548#endif
6549
6550 return true;
6551}
6552
cbc8e55f 6553/**
b980ac18
JK		 6554 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6555 * @rx_ring: rx descriptor ring to transact packets on
6556 * @rx_buffer: buffer containing page to add
6557 * @rx_desc: descriptor containing length of buffer written by hardware
6558 * @skb: sk_buff to place the data into
cbc8e55f 6559 *
b980ac18
JK		 6560 * This function will add the data contained in rx_buffer->page to the skb.
6561 * This is done either through a direct copy if the data in the buffer is
6562 * less than the skb header size, otherwise it will just attach the page as
6563 * a frag to the skb.
cbc8e55f 6564 *
b980ac18
JK		 6565 * The function will then update the page offset if necessary and return
6566 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6567 **/
6568static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6569 struct igb_rx_buffer *rx_buffer,
6570 union e1000_adv_rx_desc *rx_desc,
6571 struct sk_buff *skb)
6572{
6573 struct page *page = rx_buffer->page;
6574 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6575#if (PAGE_SIZE < 8192)
6576 unsigned int truesize = IGB_RX_BUFSZ;
6577#else
6578 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6579#endif
cbc8e55f
AD		 6580
6581 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6582 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6583
cbc8e55f
AD		 6584 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6585 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6586 va += IGB_TS_HDR_LEN;
6587 size -= IGB_TS_HDR_LEN;
6588 }
6589
cbc8e55f
AD		 6590 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6591
6592 /* we can reuse buffer as-is, just make sure it is local */
6593 if (likely(page_to_nid(page) == numa_node_id()))
6594 return true;
6595
6596 /* this page cannot be reused so discard it */
6597 put_page(page);
6598 return false;
6599 }
6600
6601 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6602 rx_buffer->page_offset, size, truesize);
cbc8e55f 6603
74e238ea
AD		 6604 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6605}
cbc8e55f 6606
2e334eee
AD		 6607static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6608 union e1000_adv_rx_desc *rx_desc,
6609 struct sk_buff *skb)
6610{
6611 struct igb_rx_buffer *rx_buffer;
6612 struct page *page;
6613
6614 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6615
2e334eee
AD		 6616 page = rx_buffer->page;
6617 prefetchw(page);
6618
6619 if (likely(!skb)) {
6620 void *page_addr = page_address(page) +
6621 rx_buffer->page_offset;
6622
6623 /* prefetch first cache line of first page */
6624 prefetch(page_addr);
6625#if L1_CACHE_BYTES < 128
6626 prefetch(page_addr + L1_CACHE_BYTES);
6627#endif
6628
6629 /* allocate a skb to store the frags */
6630 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6631 IGB_RX_HDR_LEN);
6632 if (unlikely(!skb)) {
6633 rx_ring->rx_stats.alloc_failed++;
6634 return NULL;
6635 }
6636
b980ac18 6637 /* we will be copying header into skb->data in
2e334eee
AD		 6638 * pskb_may_pull so it is in our interest to prefetch
6639 * it now to avoid a possible cache miss
6640 */
6641 prefetchw(skb->data);
6642 }
6643
6644 /* we are reusing so sync this buffer for CPU use */
6645 dma_sync_single_range_for_cpu(rx_ring->dev,
6646 rx_buffer->dma,
6647 rx_buffer->page_offset,
de78d1f9 6648 IGB_RX_BUFSZ,
2e334eee
AD		 6649 DMA_FROM_DEVICE);
6650
6651 /* pull page into skb */
6652 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6653 /* hand second half of page back to the ring */
6654 igb_reuse_rx_page(rx_ring, rx_buffer);
6655 } else {
6656 /* we are not reusing the buffer so unmap it */
6657 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6658 PAGE_SIZE, DMA_FROM_DEVICE);
6659 }
6660
6661 /* clear contents of rx_buffer */
6662 rx_buffer->page = NULL;
6663
6664 return skb;
6665}
6666
cd392f5c 6667static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6668 union e1000_adv_rx_desc *rx_desc,
6669 struct sk_buff *skb)
9d5c8243 6670{
bc8acf2c 6671 skb_checksum_none_assert(skb);
9d5c8243 6672
294e7d78 6673 /* Ignore Checksum bit is set */
3ceb90fd 6674 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6675 return;
6676
6677 /* Rx checksum disabled via ethtool */
6678 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6679 return;
85ad76b2 6680
9d5c8243 6681 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6682 if (igb_test_staterr(rx_desc,
6683 E1000_RXDEXT_STATERR_TCPE |
6684 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6685 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6686 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6687 * packets, (aka let the stack check the crc32c)
6688 */
866cff06
AD		 6689 if (!((skb->len == 60) &&
6690 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6691 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6692 ring->rx_stats.csum_err++;
12dcd86b
ED		 6693 u64_stats_update_end(&ring->rx_syncp);
6694 }
9d5c8243 6695 /* let the stack verify checksum errors */
9d5c8243
AK		 6696 return;
6697 }
6698 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6699 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6700 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6701 skb->ip_summed = CHECKSUM_UNNECESSARY;
6702
3ceb90fd
AD		 6703 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6704 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6705}
6706
077887c3
AD		 6707static inline void igb_rx_hash(struct igb_ring *ring,
6708 union e1000_adv_rx_desc *rx_desc,
6709 struct sk_buff *skb)
6710{
6711 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6712 skb_set_hash(skb,
6713 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6714 PKT_HASH_TYPE_L3);
077887c3
AD		 6715}
6716
2e334eee 6717/**
b980ac18
JK		 6718 * igb_is_non_eop - process handling of non-EOP buffers
6719 * @rx_ring: Rx ring being processed
6720 * @rx_desc: Rx descriptor for current buffer
6721 * @skb: current socket buffer containing buffer in progress
2e334eee 6722 *
b980ac18
JK		 6723 * This function updates next to clean. If the buffer is an EOP buffer
6724 * this function exits returning false, otherwise it will place the
6725 * sk_buff in the next buffer to be chained and return true indicating
6726 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6727 **/
6728static bool igb_is_non_eop(struct igb_ring *rx_ring,
6729 union e1000_adv_rx_desc *rx_desc)
6730{
6731 u32 ntc = rx_ring->next_to_clean + 1;
6732
6733 /* fetch, update, and store next to clean */
6734 ntc = (ntc < rx_ring->count) ? ntc : 0;
6735 rx_ring->next_to_clean = ntc;
6736
6737 prefetch(IGB_RX_DESC(rx_ring, ntc));
6738
6739 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6740 return false;
6741
6742 return true;
6743}
6744
1a1c225b 6745/**
b980ac18
JK		 6746 * igb_get_headlen - determine size of header for LRO/GRO
6747 * @data: pointer to the start of the headers
6748 * @max_len: total length of section to find headers in
1a1c225b 6749 *
b980ac18
JK		 6750 * This function is meant to determine the length of headers that will
6751 * be recognized by hardware for LRO, and GRO offloads. The main
6752 * motivation of doing this is to only perform one pull for IPv4 TCP
6753 * packets so that we can do basic things like calculating the gso_size
6754 * based on the average data per packet.
1a1c225b
AD		 6755 **/
6756static unsigned int igb_get_headlen(unsigned char *data,
6757 unsigned int max_len)
6758{
6759 union {
6760 unsigned char *network;
6761 /* l2 headers */
6762 struct ethhdr *eth;
6763 struct vlan_hdr *vlan;
6764 /* l3 headers */
6765 struct iphdr *ipv4;
6766 struct ipv6hdr *ipv6;
6767 } hdr;
6768 __be16 protocol;
6769 u8 nexthdr = 0; /* default to not TCP */
6770 u8 hlen;
6771
6772 /* this should never happen, but better safe than sorry */
6773 if (max_len < ETH_HLEN)
6774 return max_len;
6775
6776 /* initialize network frame pointer */
6777 hdr.network = data;
6778
6779 /* set first protocol and move network header forward */
6780 protocol = hdr.eth->h_proto;
6781 hdr.network += ETH_HLEN;
6782
6783 /* handle any vlan tag if present */
7c4d16ff 6784 if (protocol == htons(ETH_P_8021Q)) {
1a1c225b
AD		 6785 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6786 return max_len;
6787
6788 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6789 hdr.network += VLAN_HLEN;
6790 }
6791
6792 /* handle L3 protocols */
7c4d16ff 6793 if (protocol == htons(ETH_P_IP)) {
1a1c225b
AD		 6794 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6795 return max_len;
6796
6797 /* access ihl as a u8 to avoid unaligned access on ia64 */
6798 hlen = (hdr.network[0] & 0x0F) << 2;
6799
6800 /* verify hlen meets minimum size requirements */
6801 if (hlen < sizeof(struct iphdr))
6802 return hdr.network - data;
6803
f2fb4ab2 6804 /* record next protocol if header is present */
b9555f66 6805 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6806 nexthdr = hdr.ipv4->protocol;
7c4d16ff 6807 } else if (protocol == htons(ETH_P_IPV6)) {
1a1c225b
AD		 6808 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6809 return max_len;
6810
6811 /* record next protocol */
6812 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6813 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6814 } else {
6815 return hdr.network - data;
6816 }
6817
f2fb4ab2
AD		 6818 /* relocate pointer to start of L4 header */
6819 hdr.network += hlen;
6820
1a1c225b
AD		 6821 /* finally sort out TCP */
6822 if (nexthdr == IPPROTO_TCP) {
6823 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6824 return max_len;
6825
6826 /* access doff as a u8 to avoid unaligned access on ia64 */
6827 hlen = (hdr.network[12] & 0xF0) >> 2;
6828
6829 /* verify hlen meets minimum size requirements */
6830 if (hlen < sizeof(struct tcphdr))
6831 return hdr.network - data;
6832
6833 hdr.network += hlen;
6834 } else if (nexthdr == IPPROTO_UDP) {
6835 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6836 return max_len;
6837
6838 hdr.network += sizeof(struct udphdr);
6839 }
6840
b980ac18 6841 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6842 * data section of the packet and will be the end of the header.
6843 * If not then it probably represents the end of the last recognized
6844 * header.
6845 */
6846 if ((hdr.network - data) < max_len)
6847 return hdr.network - data;
6848 else
6849 return max_len;
6850}
6851
6852/**
b980ac18
JK		 6853 * igb_pull_tail - igb specific version of skb_pull_tail
6854 * @rx_ring: rx descriptor ring packet is being transacted on
6855 * @rx_desc: pointer to the EOP Rx descriptor
6856 * @skb: pointer to current skb being adjusted
1a1c225b 6857 *
b980ac18
JK		 6858 * This function is an igb specific version of __pskb_pull_tail. The
6859 * main difference between this version and the original function is that
6860 * this function can make several assumptions about the state of things
6861 * that allow for significant optimizations versus the standard function.
6862 * As a result we can do things like drop a frag and maintain an accurate
6863 * truesize for the skb.
1a1c225b
AD		 6864 */
6865static void igb_pull_tail(struct igb_ring *rx_ring,
6866 union e1000_adv_rx_desc *rx_desc,
6867 struct sk_buff *skb)
2d94d8ab 6868{
1a1c225b
AD		 6869 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6870 unsigned char *va;
6871 unsigned int pull_len;
6872
b980ac18 6873 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6874 * working with pages allocated out of the lomem pool per
6875 * alloc_page(GFP_ATOMIC)
2d94d8ab 6876 */
1a1c225b
AD		 6877 va = skb_frag_address(frag);
6878
1a1c225b
AD		 6879 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6880 /* retrieve timestamp from buffer */
6881 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6882
6883 /* update pointers to remove timestamp header */
6884 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6885 frag->page_offset += IGB_TS_HDR_LEN;
6886 skb->data_len -= IGB_TS_HDR_LEN;
6887 skb->len -= IGB_TS_HDR_LEN;
6888
6889 /* move va to start of packet data */
6890 va += IGB_TS_HDR_LEN;
6891 }
6892
b980ac18 6893 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6894 * 60 bytes if the skb->len is less than 60 for skb_pad.
6895 */
6896 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6897
6898 /* align pull length to size of long to optimize memcpy performance */
6899 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6900
6901 /* update all of the pointers */
6902 skb_frag_size_sub(frag, pull_len);
6903 frag->page_offset += pull_len;
6904 skb->data_len -= pull_len;
6905 skb->tail += pull_len;
6906}
6907
6908/**
b980ac18
JK		 6909 * igb_cleanup_headers - Correct corrupted or empty headers
6910 * @rx_ring: rx descriptor ring packet is being transacted on
6911 * @rx_desc: pointer to the EOP Rx descriptor
6912 * @skb: pointer to current skb being fixed
1a1c225b 6913 *
b980ac18
JK		 6914 * Address the case where we are pulling data in on pages only
6915 * and as such no data is present in the skb header.
1a1c225b 6916 *
b980ac18
JK		 6917 * In addition if skb is not at least 60 bytes we need to pad it so that
6918 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6919 *
b980ac18 6920 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6921 **/
6922static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6923 union e1000_adv_rx_desc *rx_desc,
6924 struct sk_buff *skb)
6925{
1a1c225b
AD		 6926 if (unlikely((igb_test_staterr(rx_desc,
6927 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6928 struct net_device *netdev = rx_ring->netdev;
6929 if (!(netdev->features & NETIF_F_RXALL)) {
6930 dev_kfree_skb_any(skb);
6931 return true;
6932 }
6933 }
6934
6935 /* place header in linear portion of buffer */
6936 if (skb_is_nonlinear(skb))
6937 igb_pull_tail(rx_ring, rx_desc, skb);
6938
6939 /* if skb_pad returns an error the skb was freed */
6940 if (unlikely(skb->len < 60)) {
6941 int pad_len = 60 - skb->len;
6942
6943 if (skb_pad(skb, pad_len))
6944 return true;
6945 __skb_put(skb, pad_len);
6946 }
6947
6948 return false;
2d94d8ab
AD		 6949}
6950
db2ee5bd 6951/**
b980ac18
JK		 6952 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6953 * @rx_ring: rx descriptor ring packet is being transacted on
6954 * @rx_desc: pointer to the EOP Rx descriptor
6955 * @skb: pointer to current skb being populated
db2ee5bd 6956 *
b980ac18
JK		 6957 * This function checks the ring, descriptor, and packet information in
6958 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6959 * other fields within the skb.
db2ee5bd
AD		 6960 **/
6961static void igb_process_skb_fields(struct igb_ring *rx_ring,
6962 union e1000_adv_rx_desc *rx_desc,
6963 struct sk_buff *skb)
6964{
6965 struct net_device *dev = rx_ring->netdev;
6966
6967 igb_rx_hash(rx_ring, rx_desc, skb);
6968
6969 igb_rx_checksum(rx_ring, rx_desc, skb);
6970
5499a968
JK		 6971 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6972 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6973 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6974
f646968f 6975 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6976 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6977 u16 vid;
9005df38 6978
db2ee5bd
AD		 6979 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6980 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6981 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6982 else
6983 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6984
86a9bad3 6985 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6986 }
6987
6988 skb_record_rx_queue(skb, rx_ring->queue_index);
6989
6990 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6991}
6992
2e334eee 6993static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6994{
0ba82994 6995 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6996 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6997 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6998 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6999
57ba34c9 7000 while (likely(total_packets < budget)) {
2e334eee 7001 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7002
2e334eee
AD		 7003 /* return some buffers to hardware, one at a time is too slow */
7004 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7005 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7006 cleaned_count = 0;
7007 }
bf36c1a0 7008
2e334eee 7009 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7010
2e334eee
AD		 7011 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
7012 break;
9d5c8243 7013
74e238ea
AD		 7014 /* This memory barrier is needed to keep us from reading
7015 * any other fields out of the rx_desc until we know the
7016 * RXD_STAT_DD bit is set
7017 */
7018 rmb();
7019
2e334eee 7020 /* retrieve a buffer from the ring */
f9d40f6a 7021 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7022
2e334eee
AD		 7023 /* exit if we failed to retrieve a buffer */
7024 if (!skb)
7025 break;
1a1c225b 7026
2e334eee 7027 cleaned_count++;
1a1c225b 7028
2e334eee
AD		 7029 /* fetch next buffer in frame if non-eop */
7030 if (igb_is_non_eop(rx_ring, rx_desc))
7031 continue;
1a1c225b
AD		 7032
7033 /* verify the packet layout is correct */
7034 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7035 skb = NULL;
7036 continue;
9d5c8243 7037 }
9d5c8243 7038
db2ee5bd 7039 /* probably a little skewed due to removing CRC */
3ceb90fd 7040 total_bytes += skb->len;
3ceb90fd 7041
db2ee5bd
AD		 7042 /* populate checksum, timestamp, VLAN, and protocol */
7043 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7044
b2cb09b1 7045 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7046
1a1c225b
AD		 7047 /* reset skb pointer */
7048 skb = NULL;
7049
2e334eee
AD		 7050 /* update budget accounting */
7051 total_packets++;
57ba34c9 7052 }
bf36c1a0 7053
1a1c225b
AD		 7054 /* place incomplete frames back on ring for completion */
7055 rx_ring->skb = skb;
7056
12dcd86b 7057 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7058 rx_ring->rx_stats.packets += total_packets;
7059 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7060 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7061 q_vector->rx.total_packets += total_packets;
7062 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7063
7064 if (cleaned_count)
cd392f5c 7065 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7066
da1f1dfe 7067 return total_packets < budget;
9d5c8243
AK		 7068}
7069
c023cd88 7070static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7071 struct igb_rx_buffer *bi)
c023cd88
AD		 7072{
7073 struct page *page = bi->page;
cbc8e55f 7074 dma_addr_t dma;
c023cd88 7075
cbc8e55f
AD		 7076 /* since we are recycling buffers we should seldom need to alloc */
7077 if (likely(page))
c023cd88
AD		 7078 return true;
7079
cbc8e55f
AD		 7080 /* alloc new page for storage */
7081 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
7082 if (unlikely(!page)) {
7083 rx_ring->rx_stats.alloc_failed++;
7084 return false;
c023cd88
AD		 7085 }
7086
cbc8e55f
AD		 7087 /* map page for use */
7088 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7089
b980ac18 7090 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7091 * there isn't much point in holding memory we can't use
7092 */
1a1c225b 7093 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7094 __free_page(page);
7095
c023cd88
AD		 7096 rx_ring->rx_stats.alloc_failed++;
7097 return false;
7098 }
7099
1a1c225b 7100 bi->dma = dma;
cbc8e55f
AD		 7101 bi->page = page;
7102 bi->page_offset = 0;
1a1c225b 7103
c023cd88
AD		 7104 return true;
7105}
7106
9d5c8243 7107/**
b980ac18
JK		 7108 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7109 * @adapter: address of board private structure
9d5c8243 7110 **/
cd392f5c 7111void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7112{
9d5c8243 7113 union e1000_adv_rx_desc *rx_desc;
06034649 7114 struct igb_rx_buffer *bi;
c023cd88 7115 u16 i = rx_ring->next_to_use;
9d5c8243 7116
cbc8e55f
AD		 7117 /* nothing to do */
7118 if (!cleaned_count)
7119 return;
7120
60136906 7121 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7122 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7123 i -= rx_ring->count;
9d5c8243 7124
cbc8e55f 7125 do {
1a1c225b 7126 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7127 break;
9d5c8243 7128
b980ac18 7129 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7130 * because each write-back erases this info.
7131 */
f9d40f6a 7132 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7133
c023cd88
AD		 7134 rx_desc++;
7135 bi++;
9d5c8243 7136 i++;
c023cd88 7137 if (unlikely(!i)) {
60136906 7138 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7139 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7140 i -= rx_ring->count;
7141 }
7142
7143 /* clear the hdr_addr for the next_to_use descriptor */
7144 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7145
7146 cleaned_count--;
7147 } while (cleaned_count);
9d5c8243 7148
c023cd88
AD		 7149 i += rx_ring->count;
7150
9d5c8243 7151 if (rx_ring->next_to_use != i) {
cbc8e55f 7152 /* record the next descriptor to use */
9d5c8243 7153 rx_ring->next_to_use = i;
9d5c8243 7154
cbc8e55f
AD		 7155 /* update next to alloc since we have filled the ring */
7156 rx_ring->next_to_alloc = i;
7157
b980ac18 7158 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7159 * know there are new descriptors to fetch. (Only
7160 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7161 * such as IA-64).
7162 */
9d5c8243 7163 wmb();
fce99e34 7164 writel(i, rx_ring->tail);
9d5c8243
AK		 7165 }
7166}
7167
7168/**
7169 * igb_mii_ioctl -
7170 * @netdev:
7171 * @ifreq:
7172 * @cmd:
7173 **/
7174static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7175{
7176 struct igb_adapter *adapter = netdev_priv(netdev);
7177 struct mii_ioctl_data *data = if_mii(ifr);
7178
7179 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7180 return -EOPNOTSUPP;
7181
7182 switch (cmd) {
7183 case SIOCGMIIPHY:
7184 data->phy_id = adapter->hw.phy.addr;
7185 break;
7186 case SIOCGMIIREG:
f5f4cf08 7187 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7188 &data->val_out))
9d5c8243
AK		 7189 return -EIO;
7190 break;
7191 case SIOCSMIIREG:
7192 default:
7193 return -EOPNOTSUPP;
7194 }
7195 return 0;
7196}
7197
7198/**
7199 * igb_ioctl -
7200 * @netdev:
7201 * @ifreq:
7202 * @cmd:
7203 **/
7204static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7205{
7206 switch (cmd) {
7207 case SIOCGMIIPHY:
7208 case SIOCGMIIREG:
7209 case SIOCSMIIREG:
7210 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7211 case SIOCGHWTSTAMP:
7212 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7213 case SIOCSHWTSTAMP:
6ab5f7b2 7214 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7215 default:
7216 return -EOPNOTSUPP;
7217 }
7218}
7219
94826487
TF		 7220void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7221{
7222 struct igb_adapter *adapter = hw->back;
7223
7224 pci_read_config_word(adapter->pdev, reg, value);
7225}
7226
7227void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7228{
7229 struct igb_adapter *adapter = hw->back;
7230
7231 pci_write_config_word(adapter->pdev, reg, *value);
7232}
7233
009bc06e
AD		 7234s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7235{
7236 struct igb_adapter *adapter = hw->back;
009bc06e 7237
23d028cc 7238 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7239 return -E1000_ERR_CONFIG;
7240
009bc06e
AD		 7241 return 0;
7242}
7243
7244s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7245{
7246 struct igb_adapter *adapter = hw->back;
009bc06e 7247
23d028cc 7248 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7249 return -E1000_ERR_CONFIG;
7250
009bc06e
AD		 7251 return 0;
7252}
7253
c8f44aff 7254static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7255{
7256 struct igb_adapter *adapter = netdev_priv(netdev);
7257 struct e1000_hw *hw = &adapter->hw;
7258 u32 ctrl, rctl;
f646968f 7259 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7260
5faf030c 7261 if (enable) {
9d5c8243
AK		 7262 /* enable VLAN tag insert/strip */
7263 ctrl = rd32(E1000_CTRL);
7264 ctrl |= E1000_CTRL_VME;
7265 wr32(E1000_CTRL, ctrl);
7266
51466239 7267 /* Disable CFI check */
9d5c8243 7268 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7269 rctl &= ~E1000_RCTL_CFIEN;
7270 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7271 } else {
7272 /* disable VLAN tag insert/strip */
7273 ctrl = rd32(E1000_CTRL);
7274 ctrl &= ~E1000_CTRL_VME;
7275 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7276 }
7277
e1739522 7278 igb_rlpml_set(adapter);
9d5c8243
AK		 7279}
7280
80d5c368
PM		 7281static int igb_vlan_rx_add_vid(struct net_device *netdev,
7282 __be16 proto, u16 vid)
9d5c8243
AK		 7283{
7284 struct igb_adapter *adapter = netdev_priv(netdev);
7285 struct e1000_hw *hw = &adapter->hw;
4ae196df 7286 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7287
51466239
AD		 7288 /* attempt to add filter to vlvf array */
7289 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7290
51466239
AD		 7291 /* add the filter since PF can receive vlans w/o entry in vlvf */
7292 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7293
7294 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7295
7296 return 0;
9d5c8243
AK		 7297}
7298
80d5c368
PM		 7299static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7300 __be16 proto, u16 vid)
9d5c8243
AK		 7301{
7302 struct igb_adapter *adapter = netdev_priv(netdev);
7303 struct e1000_hw *hw = &adapter->hw;
4ae196df 7304 int pf_id = adapter->vfs_allocated_count;
51466239 7305 s32 err;
9d5c8243 7306
51466239
AD		 7307 /* remove vlan from VLVF table array */
7308 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7309
51466239
AD		 7310 /* if vid was not present in VLVF just remove it from table */
7311 if (err)
4ae196df 7312 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7313
7314 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7315
7316 return 0;
9d5c8243
AK		 7317}
7318
7319static void igb_restore_vlan(struct igb_adapter *adapter)
7320{
b2cb09b1 7321 u16 vid;
9d5c8243 7322
5faf030c
AD		 7323 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7324
b2cb09b1 7325 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7326 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7327}
7328
14ad2513 7329int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7330{
090b1795 7331 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7332 struct e1000_mac_info *mac = &adapter->hw.mac;
7333
7334 mac->autoneg = 0;
7335
14ad2513 7336 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7337 * for the switch() below to work
7338 */
14ad2513
DD		 7339 if ((spd & 1) || (dplx & ~1))
7340 goto err_inval;
7341
f502ef7d
AA		 7342 /* Fiber NIC's only allow 1000 gbps Full duplex
7343 * and 100Mbps Full duplex for 100baseFx sfp
7344 */
7345 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7346 switch (spd + dplx) {
7347 case SPEED_10 + DUPLEX_HALF:
7348 case SPEED_10 + DUPLEX_FULL:
7349 case SPEED_100 + DUPLEX_HALF:
7350 goto err_inval;
7351 default:
7352 break;
7353 }
7354 }
cd2638a8 7355
14ad2513 7356 switch (spd + dplx) {
9d5c8243
AK		 7357 case SPEED_10 + DUPLEX_HALF:
7358 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7359 break;
7360 case SPEED_10 + DUPLEX_FULL:
7361 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7362 break;
7363 case SPEED_100 + DUPLEX_HALF:
7364 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7365 break;
7366 case SPEED_100 + DUPLEX_FULL:
7367 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7368 break;
7369 case SPEED_1000 + DUPLEX_FULL:
7370 mac->autoneg = 1;
7371 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7372 break;
7373 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7374 default:
14ad2513 7375 goto err_inval;
9d5c8243 7376 }
8376dad0
JB		 7377
7378 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7379 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7380
9d5c8243 7381 return 0;
14ad2513
DD		 7382
7383err_inval:
7384 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7385 return -EINVAL;
9d5c8243
AK		 7386}
7387
749ab2cd
YZ		 7388static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7389 bool runtime)
9d5c8243
AK		 7390{
7391 struct net_device *netdev = pci_get_drvdata(pdev);
7392 struct igb_adapter *adapter = netdev_priv(netdev);
7393 struct e1000_hw *hw = &adapter->hw;
2d064c06 7394 u32 ctrl, rctl, status;
749ab2cd 7395 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7396#ifdef CONFIG_PM
7397 int retval = 0;
7398#endif
7399
7400 netif_device_detach(netdev);
7401
a88f10ec 7402 if (netif_running(netdev))
749ab2cd 7403 __igb_close(netdev, true);
a88f10ec 7404
047e0030 7405 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7406
7407#ifdef CONFIG_PM
7408 retval = pci_save_state(pdev);
7409 if (retval)
7410 return retval;
7411#endif
7412
7413 status = rd32(E1000_STATUS);
7414 if (status & E1000_STATUS_LU)
7415 wufc &= ~E1000_WUFC_LNKC;
7416
7417 if (wufc) {
7418 igb_setup_rctl(adapter);
ff41f8dc 7419 igb_set_rx_mode(netdev);
9d5c8243
AK		 7420
7421 /* turn on all-multi mode if wake on multicast is enabled */
7422 if (wufc & E1000_WUFC_MC) {
7423 rctl = rd32(E1000_RCTL);
7424 rctl |= E1000_RCTL_MPE;
7425 wr32(E1000_RCTL, rctl);
7426 }
7427
7428 ctrl = rd32(E1000_CTRL);
7429 /* advertise wake from D3Cold */
7430 #define E1000_CTRL_ADVD3WUC 0x00100000
7431 /* phy power management enable */
7432 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7433 ctrl |= E1000_CTRL_ADVD3WUC;
7434 wr32(E1000_CTRL, ctrl);
7435
9d5c8243 7436 /* Allow time for pending master requests to run */
330a6d6a 7437 igb_disable_pcie_master(hw);
9d5c8243
AK		 7438
7439 wr32(E1000_WUC, E1000_WUC_PME_EN);
7440 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7441 } else {
7442 wr32(E1000_WUC, 0);
7443 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7444 }
7445
3fe7c4c9
RW		 7446 *enable_wake = wufc || adapter->en_mng_pt;
7447 if (!*enable_wake)
88a268c1
NN		 7448 igb_power_down_link(adapter);
7449 else
7450 igb_power_up_link(adapter);
9d5c8243
AK		 7451
7452 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7453 * would have already happened in close and is redundant.
7454 */
9d5c8243
AK		 7455 igb_release_hw_control(adapter);
7456
7457 pci_disable_device(pdev);
7458
9d5c8243
AK		 7459 return 0;
7460}
7461
7462#ifdef CONFIG_PM
d9dd966d 7463#ifdef CONFIG_PM_SLEEP
749ab2cd 7464static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7465{
7466 int retval;
7467 bool wake;
749ab2cd 7468 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7469
749ab2cd 7470 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7471 if (retval)
7472 return retval;
7473
7474 if (wake) {
7475 pci_prepare_to_sleep(pdev);
7476 } else {
7477 pci_wake_from_d3(pdev, false);
7478 pci_set_power_state(pdev, PCI_D3hot);
7479 }
7480
7481 return 0;
7482}
d9dd966d 7483#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7484
749ab2cd 7485static int igb_resume(struct device *dev)
9d5c8243 7486{
749ab2cd 7487 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7488 struct net_device *netdev = pci_get_drvdata(pdev);
7489 struct igb_adapter *adapter = netdev_priv(netdev);
7490 struct e1000_hw *hw = &adapter->hw;
7491 u32 err;
7492
7493 pci_set_power_state(pdev, PCI_D0);
7494 pci_restore_state(pdev);
b94f2d77 7495 pci_save_state(pdev);
42bfd33a 7496
aed5dec3 7497 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7498 if (err) {
7499 dev_err(&pdev->dev,
7500 "igb: Cannot enable PCI device from suspend\n");
7501 return err;
7502 }
7503 pci_set_master(pdev);
7504
7505 pci_enable_wake(pdev, PCI_D3hot, 0);
7506 pci_enable_wake(pdev, PCI_D3cold, 0);
7507
53c7d064 7508 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7509 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7510 return -ENOMEM;
9d5c8243
AK		 7511 }
7512
9d5c8243 7513 igb_reset(adapter);
a8564f03
AD		 7514
7515 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7516 * driver.
7517 */
a8564f03
AD		 7518 igb_get_hw_control(adapter);
7519
9d5c8243
AK		 7520 wr32(E1000_WUS, ~0);
7521
749ab2cd 7522 if (netdev->flags & IFF_UP) {
0c2cc02e 7523 rtnl_lock();
749ab2cd 7524 err = __igb_open(netdev, true);
0c2cc02e 7525 rtnl_unlock();
a88f10ec
AD		 7526 if (err)
7527 return err;
7528 }
9d5c8243
AK		 7529
7530 netif_device_attach(netdev);
749ab2cd
YZ		 7531 return 0;
7532}
7533
7534#ifdef CONFIG_PM_RUNTIME
7535static int igb_runtime_idle(struct device *dev)
7536{
7537 struct pci_dev *pdev = to_pci_dev(dev);
7538 struct net_device *netdev = pci_get_drvdata(pdev);
7539 struct igb_adapter *adapter = netdev_priv(netdev);
7540
7541 if (!igb_has_link(adapter))
7542 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7543
7544 return -EBUSY;
7545}
7546
7547static int igb_runtime_suspend(struct device *dev)
7548{
7549 struct pci_dev *pdev = to_pci_dev(dev);
7550 int retval;
7551 bool wake;
7552
7553 retval = __igb_shutdown(pdev, &wake, 1);
7554 if (retval)
7555 return retval;
7556
7557 if (wake) {
7558 pci_prepare_to_sleep(pdev);
7559 } else {
7560 pci_wake_from_d3(pdev, false);
7561 pci_set_power_state(pdev, PCI_D3hot);
7562 }
9d5c8243 7563
9d5c8243
AK		 7564 return 0;
7565}
749ab2cd
YZ		 7566
7567static int igb_runtime_resume(struct device *dev)
7568{
7569 return igb_resume(dev);
7570}
7571#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7572#endif
7573
7574static void igb_shutdown(struct pci_dev *pdev)
7575{
3fe7c4c9
RW		 7576 bool wake;
7577
749ab2cd 7578 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7579
7580 if (system_state == SYSTEM_POWER_OFF) {
7581 pci_wake_from_d3(pdev, wake);
7582 pci_set_power_state(pdev, PCI_D3hot);
7583 }
9d5c8243
AK		 7584}
7585
fa44f2f1
GR		 7586#ifdef CONFIG_PCI_IOV
7587static int igb_sriov_reinit(struct pci_dev *dev)
7588{
7589 struct net_device *netdev = pci_get_drvdata(dev);
7590 struct igb_adapter *adapter = netdev_priv(netdev);
7591 struct pci_dev *pdev = adapter->pdev;
7592
7593 rtnl_lock();
7594
7595 if (netif_running(netdev))
7596 igb_close(netdev);
76252723
SA		 7597 else
7598 igb_reset(adapter);
fa44f2f1
GR		 7599
7600 igb_clear_interrupt_scheme(adapter);
7601
7602 igb_init_queue_configuration(adapter);
7603
7604 if (igb_init_interrupt_scheme(adapter, true)) {
7605 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7606 return -ENOMEM;
7607 }
7608
7609 if (netif_running(netdev))
7610 igb_open(netdev);
7611
7612 rtnl_unlock();
7613
7614 return 0;
7615}
7616
7617static int igb_pci_disable_sriov(struct pci_dev *dev)
7618{
7619 int err = igb_disable_sriov(dev);
7620
7621 if (!err)
7622 err = igb_sriov_reinit(dev);
7623
7624 return err;
7625}
7626
7627static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7628{
7629 int err = igb_enable_sriov(dev, num_vfs);
7630
7631 if (err)
7632 goto out;
7633
7634 err = igb_sriov_reinit(dev);
7635 if (!err)
7636 return num_vfs;
7637
7638out:
7639 return err;
7640}
7641
7642#endif
7643static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7644{
7645#ifdef CONFIG_PCI_IOV
7646 if (num_vfs == 0)
7647 return igb_pci_disable_sriov(dev);
7648 else
7649 return igb_pci_enable_sriov(dev, num_vfs);
7650#endif
7651 return 0;
7652}
7653
9d5c8243 7654#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7655/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7656 * without having to re-enable interrupts. It's not called while
7657 * the interrupt routine is executing.
7658 */
7659static void igb_netpoll(struct net_device *netdev)
7660{
7661 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7662 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7663 struct igb_q_vector *q_vector;
9d5c8243 7664 int i;
9d5c8243 7665
047e0030 7666 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7667 q_vector = adapter->q_vector[i];
cd14ef54 7668 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7669 wr32(E1000_EIMC, q_vector->eims_value);
7670 else
7671 igb_irq_disable(adapter);
047e0030 7672 napi_schedule(&q_vector->napi);
eebbbdba 7673 }
9d5c8243
AK		 7674}
7675#endif /* CONFIG_NET_POLL_CONTROLLER */
7676
7677/**
b980ac18
JK		 7678 * igb_io_error_detected - called when PCI error is detected
7679 * @pdev: Pointer to PCI device
7680 * @state: The current pci connection state
9d5c8243 7681 *
b980ac18
JK		 7682 * This function is called after a PCI bus error affecting
7683 * this device has been detected.
7684 **/
9d5c8243
AK		 7685static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7686 pci_channel_state_t state)
7687{
7688 struct net_device *netdev = pci_get_drvdata(pdev);
7689 struct igb_adapter *adapter = netdev_priv(netdev);
7690
7691 netif_device_detach(netdev);
7692
59ed6eec
AD		 7693 if (state == pci_channel_io_perm_failure)
7694 return PCI_ERS_RESULT_DISCONNECT;
7695
9d5c8243
AK		 7696 if (netif_running(netdev))
7697 igb_down(adapter);
7698 pci_disable_device(pdev);
7699
7700 /* Request a slot slot reset. */
7701 return PCI_ERS_RESULT_NEED_RESET;
7702}
7703
7704/**
b980ac18
JK		 7705 * igb_io_slot_reset - called after the pci bus has been reset.
7706 * @pdev: Pointer to PCI device
9d5c8243 7707 *
b980ac18
JK		 7708 * Restart the card from scratch, as if from a cold-boot. Implementation
7709 * resembles the first-half of the igb_resume routine.
7710 **/
9d5c8243
AK		 7711static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7712{
7713 struct net_device *netdev = pci_get_drvdata(pdev);
7714 struct igb_adapter *adapter = netdev_priv(netdev);
7715 struct e1000_hw *hw = &adapter->hw;
40a914fa 7716 pci_ers_result_t result;
42bfd33a 7717 int err;
9d5c8243 7718
aed5dec3 7719 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7720 dev_err(&pdev->dev,
7721 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7722 result = PCI_ERS_RESULT_DISCONNECT;
7723 } else {
7724 pci_set_master(pdev);
7725 pci_restore_state(pdev);
b94f2d77 7726 pci_save_state(pdev);
9d5c8243 7727
40a914fa
AD		 7728 pci_enable_wake(pdev, PCI_D3hot, 0);
7729 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7730
40a914fa
AD		 7731 igb_reset(adapter);
7732 wr32(E1000_WUS, ~0);
7733 result = PCI_ERS_RESULT_RECOVERED;
7734 }
9d5c8243 7735
ea943d41
JK		 7736 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7737 if (err) {
b980ac18
JK		 7738 dev_err(&pdev->dev,
7739 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7740 err);
ea943d41
JK		 7741 /* non-fatal, continue */
7742 }
40a914fa
AD		 7743
7744 return result;
9d5c8243
AK		 7745}
7746
7747/**
b980ac18
JK		 7748 * igb_io_resume - called when traffic can start flowing again.
7749 * @pdev: Pointer to PCI device
9d5c8243 7750 *
b980ac18
JK		 7751 * This callback is called when the error recovery driver tells us that
7752 * its OK to resume normal operation. Implementation resembles the
7753 * second-half of the igb_resume routine.
9d5c8243
AK		 7754 */
7755static void igb_io_resume(struct pci_dev *pdev)
7756{
7757 struct net_device *netdev = pci_get_drvdata(pdev);
7758 struct igb_adapter *adapter = netdev_priv(netdev);
7759
9d5c8243
AK		 7760 if (netif_running(netdev)) {
7761 if (igb_up(adapter)) {
7762 dev_err(&pdev->dev, "igb_up failed after reset\n");
7763 return;
7764 }
7765 }
7766
7767 netif_device_attach(netdev);
7768
7769 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7770 * driver.
7771 */
9d5c8243 7772 igb_get_hw_control(adapter);
9d5c8243
AK		 7773}
7774
26ad9178 7775static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7776 u8 qsel)
26ad9178
AD		 7777{
7778 u32 rar_low, rar_high;
7779 struct e1000_hw *hw = &adapter->hw;
7780
7781 /* HW expects these in little endian so we reverse the byte order
7782 * from network order (big endian) to little endian
7783 */
7784 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7785 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7786 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7787
7788 /* Indicate to hardware the Address is Valid. */
7789 rar_high |= E1000_RAH_AV;
7790
7791 if (hw->mac.type == e1000_82575)
7792 rar_high |= E1000_RAH_POOL_1 * qsel;
7793 else
7794 rar_high |= E1000_RAH_POOL_1 << qsel;
7795
7796 wr32(E1000_RAL(index), rar_low);
7797 wrfl();
7798 wr32(E1000_RAH(index), rar_high);
7799 wrfl();
7800}
7801
4ae196df 7802static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7803 int vf, unsigned char *mac_addr)
4ae196df
AD		 7804{
7805 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7806 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7807 * towards the first, as a result a collision should not be possible
7808 */
ff41f8dc 7809 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7810
37680117 7811 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7812
26ad9178 7813 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7814
7815 return 0;
7816}
7817
8151d294
WM		 7818static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7819{
7820 struct igb_adapter *adapter = netdev_priv(netdev);
7821 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7822 return -EINVAL;
7823 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7824 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7825 dev_info(&adapter->pdev->dev,
7826 "Reload the VF driver to make this change effective.");
8151d294 7827 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7828 dev_warn(&adapter->pdev->dev,
7829 "The VF MAC address has been set, but the PF device is not up.\n");
7830 dev_warn(&adapter->pdev->dev,
7831 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7832 }
7833 return igb_set_vf_mac(adapter, vf, mac);
7834}
7835
17dc566c
LL		 7836static int igb_link_mbps(int internal_link_speed)
7837{
7838 switch (internal_link_speed) {
7839 case SPEED_100:
7840 return 100;
7841 case SPEED_1000:
7842 return 1000;
7843 default:
7844 return 0;
7845 }
7846}
7847
7848static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7849 int link_speed)
7850{
7851 int rf_dec, rf_int;
7852 u32 bcnrc_val;
7853
7854 if (tx_rate != 0) {
7855 /* Calculate the rate factor values to set */
7856 rf_int = link_speed / tx_rate;
7857 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7858 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7859 tx_rate;
17dc566c
LL		 7860
7861 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7862 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7863 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7864 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7865 } else {
7866 bcnrc_val = 0;
7867 }
7868
7869 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7870 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7871 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7872 */
7873 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7874 wr32(E1000_RTTBCNRC, bcnrc_val);
7875}
7876
7877static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7878{
7879 int actual_link_speed, i;
7880 bool reset_rate = false;
7881
7882 /* VF TX rate limit was not set or not supported */
7883 if ((adapter->vf_rate_link_speed == 0) ||
7884 (adapter->hw.mac.type != e1000_82576))
7885 return;
7886
7887 actual_link_speed = igb_link_mbps(adapter->link_speed);
7888 if (actual_link_speed != adapter->vf_rate_link_speed) {
7889 reset_rate = true;
7890 adapter->vf_rate_link_speed = 0;
7891 dev_info(&adapter->pdev->dev,
b980ac18 7892 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7893 }
7894
7895 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7896 if (reset_rate)
7897 adapter->vf_data[i].tx_rate = 0;
7898
7899 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7900 adapter->vf_data[i].tx_rate,
7901 actual_link_speed);
17dc566c
LL		 7902 }
7903}
7904
ed616689
SC		 7905static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7906 int min_tx_rate, int max_tx_rate)
8151d294 7907{
17dc566c
LL		 7908 struct igb_adapter *adapter = netdev_priv(netdev);
7909 struct e1000_hw *hw = &adapter->hw;
7910 int actual_link_speed;
7911
7912 if (hw->mac.type != e1000_82576)
7913 return -EOPNOTSUPP;
7914
ed616689
SC		 7915 if (min_tx_rate)
7916 return -EINVAL;
7917
17dc566c
LL		 7918 actual_link_speed = igb_link_mbps(adapter->link_speed);
7919 if ((vf >= adapter->vfs_allocated_count) ||
7920 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7921 (max_tx_rate < 0) ||
7922 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7923 return -EINVAL;
7924
7925 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7926 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7927 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7928
7929 return 0;
8151d294
WM		 7930}
7931
70ea4783
LL		 7932static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7933 bool setting)
7934{
7935 struct igb_adapter *adapter = netdev_priv(netdev);
7936 struct e1000_hw *hw = &adapter->hw;
7937 u32 reg_val, reg_offset;
7938
7939 if (!adapter->vfs_allocated_count)
7940 return -EOPNOTSUPP;
7941
7942 if (vf >= adapter->vfs_allocated_count)
7943 return -EINVAL;
7944
7945 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7946 reg_val = rd32(reg_offset);
7947 if (setting)
7948 reg_val |= ((1 << vf) |
7949 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7950 else
7951 reg_val &= ~((1 << vf) |
7952 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7953 wr32(reg_offset, reg_val);
7954
7955 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7956 return 0;
70ea4783
LL		 7957}
7958
8151d294
WM		 7959static int igb_ndo_get_vf_config(struct net_device *netdev,
7960 int vf, struct ifla_vf_info *ivi)
7961{
7962 struct igb_adapter *adapter = netdev_priv(netdev);
7963 if (vf >= adapter->vfs_allocated_count)
7964 return -EINVAL;
7965 ivi->vf = vf;
7966 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7967 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7968 ivi->min_tx_rate = 0;
8151d294
WM		 7969 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7970 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7971 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7972 return 0;
7973}
7974
4ae196df
AD		 7975static void igb_vmm_control(struct igb_adapter *adapter)
7976{
7977 struct e1000_hw *hw = &adapter->hw;
10d8e907 7978 u32 reg;
4ae196df 7979
52a1dd4d
AD		 7980 switch (hw->mac.type) {
7981 case e1000_82575:
f96a8a0b
CW		 7982 case e1000_i210:
7983 case e1000_i211:
ceb5f13b 7984 case e1000_i354:
52a1dd4d
AD		 7985 default:
7986 /* replication is not supported for 82575 */
4ae196df 7987 return;
52a1dd4d
AD		 7988 case e1000_82576:
7989 /* notify HW that the MAC is adding vlan tags */
7990 reg = rd32(E1000_DTXCTL);
7991 reg |= E1000_DTXCTL_VLAN_ADDED;
7992 wr32(E1000_DTXCTL, reg);
b26141d4 7993 /* Fall through */
52a1dd4d
AD		 7994 case e1000_82580:
7995 /* enable replication vlan tag stripping */
7996 reg = rd32(E1000_RPLOLR);
7997 reg |= E1000_RPLOLR_STRVLAN;
7998 wr32(E1000_RPLOLR, reg);
b26141d4 7999 /* Fall through */
d2ba2ed8
AD		 8000 case e1000_i350:
8001 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8002 break;
8003 }
10d8e907 8004
d4960307
AD		 8005 if (adapter->vfs_allocated_count) {
8006 igb_vmdq_set_loopback_pf(hw, true);
8007 igb_vmdq_set_replication_pf(hw, true);
13800469 8008 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8009 adapter->vfs_allocated_count);
d4960307
AD		 8010 } else {
8011 igb_vmdq_set_loopback_pf(hw, false);
8012 igb_vmdq_set_replication_pf(hw, false);
8013 }
4ae196df
AD		 8014}
8015
b6e0c419
CW		 8016static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8017{
8018 struct e1000_hw *hw = &adapter->hw;
8019 u32 dmac_thr;
8020 u16 hwm;
8021
8022 if (hw->mac.type > e1000_82580) {
8023 if (adapter->flags & IGB_FLAG_DMAC) {
8024 u32 reg;
8025
8026 /* force threshold to 0. */
8027 wr32(E1000_DMCTXTH, 0);
8028
b980ac18 8029 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8030 * than the Rx threshold. Set hwm to PBA - max frame
8031 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8032 */
e8c626e9
MV		 8033 hwm = 64 * pba - adapter->max_frame_size / 16;
8034 if (hwm < 64 * (pba - 6))
8035 hwm = 64 * (pba - 6);
8036 reg = rd32(E1000_FCRTC);
8037 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8038 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8039 & E1000_FCRTC_RTH_COAL_MASK);
8040 wr32(E1000_FCRTC, reg);
8041
b980ac18 8042 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8043 * frame size, capping it at PBA - 10KB.
8044 */
8045 dmac_thr = pba - adapter->max_frame_size / 512;
8046 if (dmac_thr < pba - 10)
8047 dmac_thr = pba - 10;
b6e0c419
CW		 8048 reg = rd32(E1000_DMACR);
8049 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8050 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8051 & E1000_DMACR_DMACTHR_MASK);
8052
8053 /* transition to L0x or L1 if available..*/
8054 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8055
8056 /* watchdog timer= +-1000 usec in 32usec intervals */
8057 reg |= (1000 >> 5);
0c02dd98
MV		 8058
8059 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8060 if (hw->mac.type != e1000_i354)
8061 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8062
b6e0c419
CW		 8063 wr32(E1000_DMACR, reg);
8064
b980ac18 8065 /* no lower threshold to disable
b6e0c419
CW		 8066 * coalescing(smart fifb)-UTRESH=0
8067 */
8068 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8069
8070 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8071
8072 wr32(E1000_DMCTLX, reg);
8073
b980ac18 8074 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8075 * DMA coal
8076 */
8077 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8078 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8079
b980ac18 8080 /* make low power state decision controlled
b6e0c419
CW		 8081 * by DMA coal
8082 */
8083 reg = rd32(E1000_PCIEMISC);
8084 reg &= ~E1000_PCIEMISC_LX_DECISION;
8085 wr32(E1000_PCIEMISC, reg);
8086 } /* endif adapter->dmac is not disabled */
8087 } else if (hw->mac.type == e1000_82580) {
8088 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8089
b6e0c419
CW		 8090 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8091 wr32(E1000_DMACR, 0);
8092 }
8093}
8094
b980ac18
JK		 8095/**
8096 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8097 * @hw: pointer to hardware structure
8098 * @byte_offset: byte offset to read
8099 * @dev_addr: device address
8100 * @data: value read
8101 *
8102 * Performs byte read operation over I2C interface at
8103 * a specified device address.
b980ac18 8104 **/
441fc6fd 8105s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8106 u8 dev_addr, u8 *data)
441fc6fd
CW		 8107{
8108 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8109 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8110 s32 status;
8111 u16 swfw_mask = 0;
8112
8113 if (!this_client)
8114 return E1000_ERR_I2C;
8115
8116 swfw_mask = E1000_SWFW_PHY0_SM;
8117
23d87824 8118 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8119 return E1000_ERR_SWFW_SYNC;
8120
8121 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8122 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8123
8124 if (status < 0)
8125 return E1000_ERR_I2C;
8126 else {
8127 *data = status;
23d87824 8128 return 0;
441fc6fd
CW		 8129 }
8130}
8131
b980ac18
JK		 8132/**
8133 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8134 * @hw: pointer to hardware structure
8135 * @byte_offset: byte offset to write
8136 * @dev_addr: device address
8137 * @data: value to write
8138 *
8139 * Performs byte write operation over I2C interface at
8140 * a specified device address.
b980ac18 8141 **/
441fc6fd 8142s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8143 u8 dev_addr, u8 data)
441fc6fd
CW		 8144{
8145 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8146 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8147 s32 status;
8148 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8149
8150 if (!this_client)
8151 return E1000_ERR_I2C;
8152
23d87824 8153 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8154 return E1000_ERR_SWFW_SYNC;
8155 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8156 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8157
8158 if (status)
8159 return E1000_ERR_I2C;
8160 else
23d87824 8161 return 0;
441fc6fd
CW		 8162
8163}
907b7835
LMV		 8164
8165int igb_reinit_queues(struct igb_adapter *adapter)
8166{
8167 struct net_device *netdev = adapter->netdev;
8168 struct pci_dev *pdev = adapter->pdev;
8169 int err = 0;
8170
8171 if (netif_running(netdev))
8172 igb_close(netdev);
8173
02ef6e1d 8174 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8175
8176 if (igb_init_interrupt_scheme(adapter, true)) {
8177 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8178 return -ENOMEM;
8179 }
8180
8181 if (netif_running(netdev))
8182 err = igb_open(netdev);
8183
8184 return err;
8185}
9d5c8243 8186/* igb_main.c */
Linux kernel - Deliverables
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