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igb: Fix Null-pointer dereference in igb_reset_q_vector
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
74cfb2e1 4 Copyright(c) 2007-2014 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
74cfb2e1 16 this program; if not, see <http://www.gnu.org/licenses/>.
9d5c8243
AK		 17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
876d2d6f
JK		 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28
9d5c8243
AK		 29#include <linux/module.h>
30#include <linux/types.h>
31#include <linux/init.h>
b2cb09b1 32#include <linux/bitops.h>
9d5c8243
AK		 33#include <linux/vmalloc.h>
34#include <linux/pagemap.h>
35#include <linux/netdevice.h>
9d5c8243 36#include <linux/ipv6.h>
5a0e3ad6 37#include <linux/slab.h>
9d5c8243
AK		 38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
c6cb090b 40#include <linux/net_tstamp.h>
9d5c8243
AK		 41#include <linux/mii.h>
42#include <linux/ethtool.h>
01789349 43#include <linux/if.h>
9d5c8243
AK		 44#include <linux/if_vlan.h>
45#include <linux/pci.h>
c54106bb 46#include <linux/pci-aspm.h>
9d5c8243
AK		 47#include <linux/delay.h>
48#include <linux/interrupt.h>
7d13a7d0
AD		 49#include <linux/ip.h>
50#include <linux/tcp.h>
51#include <linux/sctp.h>
9d5c8243 52#include <linux/if_ether.h>
40a914fa 53#include <linux/aer.h>
70c71606 54#include <linux/prefetch.h>
749ab2cd 55#include <linux/pm_runtime.h>
421e02f0 56#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 57#include <linux/dca.h>
58#endif
441fc6fd 59#include <linux/i2c.h>
9d5c8243
AK		 60#include "igb.h"
61
67b1b903
CW		 62#define MAJ 5
63#define MIN 0
66f40b8a 64#define BUILD 5
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 71static const char igb_copyright[] =
74cfb2e1 72 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 73
9d5c8243
AK		 74static const struct e1000_info *igb_info_tbl[] = {
75 [board_82575] = &e1000_82575_info,
76};
77
a3aa1884 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
114 /* required last entry */
115 {0, }
116};
117
118MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
119
120void igb_reset(struct igb_adapter *);
121static int igb_setup_all_tx_resources(struct igb_adapter *);
122static int igb_setup_all_rx_resources(struct igb_adapter *);
123static void igb_free_all_tx_resources(struct igb_adapter *);
124static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 125static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 126static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 127static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 128static int igb_sw_init(struct igb_adapter *);
129static int igb_open(struct net_device *);
130static int igb_close(struct net_device *);
53c7d064 131static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 132static void igb_configure_tx(struct igb_adapter *);
133static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 134static void igb_clean_all_tx_rings(struct igb_adapter *);
135static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 136static void igb_clean_tx_ring(struct igb_ring *);
137static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 138static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 139static void igb_update_phy_info(unsigned long);
140static void igb_watchdog(unsigned long);
141static void igb_watchdog_task(struct work_struct *);
cd392f5c 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
144 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 145static int igb_change_mtu(struct net_device *, int);
146static int igb_set_mac(struct net_device *, void *);
68d480c4 147static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 148static irqreturn_t igb_intr(int irq, void *);
149static irqreturn_t igb_intr_msi(int irq, void *);
150static irqreturn_t igb_msix_other(int irq, void *);
047e0030 151static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 152#ifdef CONFIG_IGB_DCA
047e0030 153static void igb_update_dca(struct igb_q_vector *);
fe4506b6 154static void igb_setup_dca(struct igb_adapter *);
421e02f0 155#endif /* CONFIG_IGB_DCA */
661086df 156static int igb_poll(struct napi_struct *, int);
13fde97a 157static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 158static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
160static void igb_tx_timeout(struct net_device *);
161static void igb_reset_task(struct work_struct *);
c8f44aff 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 165static void igb_restore_vlan(struct igb_adapter *);
26ad9178 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 167static void igb_ping_all_vfs(struct igb_adapter *);
168static void igb_msg_task(struct igb_adapter *);
4ae196df 169static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
173static int igb_ndo_set_vf_vlan(struct net_device *netdev,
174 int vf, u16 vlan, u8 qos);
175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
177 bool setting);
8151d294
WM		 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
179 struct ifla_vf_info *ivi);
17dc566c 180static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 181
182#ifdef CONFIG_PCI_IOV
0224d663 183static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd
YZ		 191static int igb_resume(struct device *);
192#ifdef CONFIG_PM_RUNTIME
193static int igb_runtime_suspend(struct device *dev);
194static int igb_runtime_resume(struct device *dev);
195static int igb_runtime_idle(struct device *dev);
196#endif
197static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201};
9d5c8243
AK		 202#endif
203static void igb_shutdown(struct pci_dev *);
fa44f2f1 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 205#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211};
212#endif
9d5c8243
AK		 213#ifdef CONFIG_NET_POLL_CONTROLLER
214/* for netdump / net console */
215static void igb_netpoll(struct net_device *);
216#endif
37680117 217#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 218static unsigned int max_vfs = 0;
219module_param(max_vfs, uint, 0);
220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
221 "per physical function");
222#endif /* CONFIG_PCI_IOV */
223
9d5c8243
AK		 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
225 pci_channel_state_t);
226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
227static void igb_io_resume(struct pci_dev *);
228
3646f0e5 229static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 230 .error_detected = igb_io_error_detected,
231 .slot_reset = igb_io_slot_reset,
232 .resume = igb_io_resume,
233};
234
b6e0c419 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 236
237static struct pci_driver igb_driver = {
238 .name = igb_driver_name,
239 .id_table = igb_pci_tbl,
240 .probe = igb_probe,
9f9a12f8 241 .remove = igb_remove,
9d5c8243 242#ifdef CONFIG_PM
749ab2cd 243 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 244#endif
245 .shutdown = igb_shutdown,
fa44f2f1 246 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 247 .err_handler = &igb_err_handler
248};
249
250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
252MODULE_LICENSE("GPL");
253MODULE_VERSION(DRV_VERSION);
254
b3f4d599 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
256static int debug = -1;
257module_param(debug, int, 0);
258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
259
c97ec42a
TI		 260struct igb_reg_info {
261 u32 ofs;
262 char *name;
263};
264
265static const struct igb_reg_info igb_reg_info_tbl[] = {
266
267 /* General Registers */
268 {E1000_CTRL, "CTRL"},
269 {E1000_STATUS, "STATUS"},
270 {E1000_CTRL_EXT, "CTRL_EXT"},
271
272 /* Interrupt Registers */
273 {E1000_ICR, "ICR"},
274
275 /* RX Registers */
276 {E1000_RCTL, "RCTL"},
277 {E1000_RDLEN(0), "RDLEN"},
278 {E1000_RDH(0), "RDH"},
279 {E1000_RDT(0), "RDT"},
280 {E1000_RXDCTL(0), "RXDCTL"},
281 {E1000_RDBAL(0), "RDBAL"},
282 {E1000_RDBAH(0), "RDBAH"},
283
284 /* TX Registers */
285 {E1000_TCTL, "TCTL"},
286 {E1000_TDBAL(0), "TDBAL"},
287 {E1000_TDBAH(0), "TDBAH"},
288 {E1000_TDLEN(0), "TDLEN"},
289 {E1000_TDH(0), "TDH"},
290 {E1000_TDT(0), "TDT"},
291 {E1000_TXDCTL(0), "TXDCTL"},
292 {E1000_TDFH, "TDFH"},
293 {E1000_TDFT, "TDFT"},
294 {E1000_TDFHS, "TDFHS"},
295 {E1000_TDFPC, "TDFPC"},
296
297 /* List Terminator */
298 {}
299};
300
b980ac18 301/* igb_regdump - register printout routine */
c97ec42a
TI		 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
303{
304 int n = 0;
305 char rname[16];
306 u32 regs[8];
307
308 switch (reginfo->ofs) {
309 case E1000_RDLEN(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDLEN(n));
312 break;
313 case E1000_RDH(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDH(n));
316 break;
317 case E1000_RDT(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RDT(n));
320 break;
321 case E1000_RXDCTL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RXDCTL(n));
324 break;
325 case E1000_RDBAL(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAL(n));
328 break;
329 case E1000_RDBAH(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAH(n));
332 break;
333 case E1000_TDBAL(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_RDBAL(n));
336 break;
337 case E1000_TDBAH(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDBAH(n));
340 break;
341 case E1000_TDLEN(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDLEN(n));
344 break;
345 case E1000_TDH(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDH(n));
348 break;
349 case E1000_TDT(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TDT(n));
352 break;
353 case E1000_TXDCTL(0):
354 for (n = 0; n < 4; n++)
355 regs[n] = rd32(E1000_TXDCTL(n));
356 break;
357 default:
876d2d6f 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 359 return;
360 }
361
362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
364 regs[2], regs[3]);
c97ec42a
TI		 365}
366
b980ac18 367/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 368static void igb_dump(struct igb_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 struct e1000_hw *hw = &adapter->hw;
372 struct igb_reg_info *reginfo;
c97ec42a
TI		 373 struct igb_ring *tx_ring;
374 union e1000_adv_tx_desc *tx_desc;
375 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 376 struct igb_ring *rx_ring;
377 union e1000_adv_rx_desc *rx_desc;
378 u32 staterr;
6ad4edfc 379 u16 i, n;
c97ec42a
TI		 380
381 if (!netif_msg_hw(adapter))
382 return;
383
384 /* Print netdevice Info */
385 if (netdev) {
386 dev_info(&adapter->pdev->dev, "Net device Info\n");
876d2d6f
JK		 387 pr_info("Device Name state trans_start "
388 "last_rx\n");
389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
390 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 391 }
392
393 /* Print Registers */
394 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 395 pr_info(" Register Name Value\n");
c97ec42a
TI		 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
397 reginfo->name; reginfo++) {
398 igb_regdump(hw, reginfo);
399 }
400
401 /* Print TX Ring Summary */
402 if (!netdev || !netif_running(netdev))
403 goto exit;
404
405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 407 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 408 struct igb_tx_buffer *buffer_info;
c97ec42a 409 tx_ring = adapter->tx_ring[n];
06034649 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
412 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 413 (u64)dma_unmap_addr(buffer_info, dma),
414 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 415 buffer_info->next_to_watch,
416 (u64)buffer_info->time_stamp);
c97ec42a
TI		 417 }
418
419 /* Print TX Rings */
420 if (!netif_msg_tx_done(adapter))
421 goto rx_ring_summary;
422
423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
424
425 /* Transmit Descriptor Formats
426 *
427 * Advanced Transmit Descriptor
428 * +--------------------------------------------------------------+
429 * 0 | Buffer Address [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
432 * +--------------------------------------------------------------+
433 * 63 46 45 40 39 38 36 35 32 31 24 15 0
434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] "
442 "[bi->dma ] leng ntw timestamp "
443 "bi->skb\n");
c97ec42a
TI		 444
445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 446 const char *next_desc;
06034649 447 struct igb_tx_buffer *buffer_info;
60136906 448 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 449 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 450 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 451 if (i == tx_ring->next_to_use &&
452 i == tx_ring->next_to_clean)
453 next_desc = " NTC/U";
454 else if (i == tx_ring->next_to_use)
455 next_desc = " NTU";
456 else if (i == tx_ring->next_to_clean)
457 next_desc = " NTC";
458 else
459 next_desc = "";
460
461 pr_info("T [0x%03X] %016llX %016llX %016llX"
462 " %04X %p %016llX %p%s\n", i,
c97ec42a
TI		 463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
c9f14bf3
AD		 465 (u64)dma_unmap_addr(buffer_info, dma),
466 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 467 buffer_info->next_to_watch,
468 (u64)buffer_info->time_stamp,
876d2d6f 469 buffer_info->skb, next_desc);
c97ec42a 470
b669588a 471 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS,
b669588a 474 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 475 dma_unmap_len(buffer_info, len),
476 true);
c97ec42a
TI		 477 }
478 }
479
480 /* Print RX Rings Summary */
481rx_ring_summary:
482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 483 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 484 for (n = 0; n < adapter->num_rx_queues; n++) {
485 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 486 pr_info(" %5d %5X %5X\n",
487 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 488 }
489
490 /* Print RX Rings */
491 if (!netif_msg_rx_status(adapter))
492 goto exit;
493
494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
495
496 /* Advanced Receive Descriptor (Read) Format
497 * 63 1 0
498 * +-----------------------------------------------------+
499 * 0 | Packet Buffer Address [63:1] |A0/NSE|
500 * +----------------------------------------------+------+
501 * 8 | Header Buffer Address [63:1] | DD |
502 * +-----------------------------------------------------+
503 *
504 *
505 * Advanced Receive Descriptor (Write-Back) Format
506 *
507 * 63 48 47 32 31 30 21 20 17 16 4 3 0
508 * +------------------------------------------------------+
509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
510 * | Checksum Ident | | | | Type | Type |
511 * +------------------------------------------------------+
512 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
513 * +------------------------------------------------------+
514 * 63 48 47 32 31 20 19 0
515 */
516
517 for (n = 0; n < adapter->num_rx_queues; n++) {
518 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 519 pr_info("------------------------------------\n");
520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
521 pr_info("------------------------------------\n");
522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] "
523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----"
525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 526
527 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 528 const char *next_desc;
06034649
AD		 529 struct igb_rx_buffer *buffer_info;
530 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 531 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 532 u0 = (struct my_u0 *)rx_desc;
533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 534
535 if (i == rx_ring->next_to_use)
536 next_desc = " NTU";
537 else if (i == rx_ring->next_to_clean)
538 next_desc = " NTC";
539 else
540 next_desc = "";
541
c97ec42a
TI		 542 if (staterr & E1000_RXD_STAT_DD) {
543 /* Descriptor Done */
1a1c225b
AD		 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
545 "RWB", i,
c97ec42a
TI		 546 le64_to_cpu(u0->a),
547 le64_to_cpu(u0->b),
1a1c225b 548 next_desc);
c97ec42a 549 } else {
1a1c225b
AD		 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
551 "R ", i,
c97ec42a
TI		 552 le64_to_cpu(u0->a),
553 le64_to_cpu(u0->b),
554 (u64)buffer_info->dma,
1a1c225b 555 next_desc);
c97ec42a 556
b669588a 557 if (netif_msg_pktdata(adapter) &&
1a1c225b 558 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 559 print_hex_dump(KERN_INFO, "",
560 DUMP_PREFIX_ADDRESS,
561 16, 1,
b669588a
ET		 562 page_address(buffer_info->page) +
563 buffer_info->page_offset,
de78d1f9 564 IGB_RX_BUFSZ, true);
c97ec42a
TI		 565 }
566 }
c97ec42a
TI		 567 }
568 }
569
570exit:
571 return;
572}
573
b980ac18
JK		 574/**
575 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 576 * @hw: pointer to hardware structure
577 * @i2cctl: Current value of I2CCTL register
578 *
579 * Returns the I2C data bit value
b980ac18 580 **/
441fc6fd
CW		 581static int igb_get_i2c_data(void *data)
582{
583 struct igb_adapter *adapter = (struct igb_adapter *)data;
584 struct e1000_hw *hw = &adapter->hw;
585 s32 i2cctl = rd32(E1000_I2CPARAMS);
586
587 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
588}
589
b980ac18
JK		 590/**
591 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 592 * @data: pointer to hardware structure
593 * @state: I2C data value (0 or 1) to set
594 *
595 * Sets the I2C data bit
b980ac18 596 **/
441fc6fd
CW		 597static void igb_set_i2c_data(void *data, int state)
598{
599 struct igb_adapter *adapter = (struct igb_adapter *)data;
600 struct e1000_hw *hw = &adapter->hw;
601 s32 i2cctl = rd32(E1000_I2CPARAMS);
602
603 if (state)
604 i2cctl |= E1000_I2C_DATA_OUT;
605 else
606 i2cctl &= ~E1000_I2C_DATA_OUT;
607
608 i2cctl &= ~E1000_I2C_DATA_OE_N;
609 i2cctl |= E1000_I2C_CLK_OE_N;
610 wr32(E1000_I2CPARAMS, i2cctl);
611 wrfl();
612
613}
614
b980ac18
JK		 615/**
616 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 617 * @data: pointer to hardware structure
618 * @state: state to set clock
619 *
620 * Sets the I2C clock line to state
b980ac18 621 **/
441fc6fd
CW		 622static void igb_set_i2c_clk(void *data, int state)
623{
624 struct igb_adapter *adapter = (struct igb_adapter *)data;
625 struct e1000_hw *hw = &adapter->hw;
626 s32 i2cctl = rd32(E1000_I2CPARAMS);
627
628 if (state) {
629 i2cctl |= E1000_I2C_CLK_OUT;
630 i2cctl &= ~E1000_I2C_CLK_OE_N;
631 } else {
632 i2cctl &= ~E1000_I2C_CLK_OUT;
633 i2cctl &= ~E1000_I2C_CLK_OE_N;
634 }
635 wr32(E1000_I2CPARAMS, i2cctl);
636 wrfl();
637}
638
b980ac18
JK		 639/**
640 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 641 * @data: pointer to hardware structure
642 *
643 * Gets the I2C clock state
b980ac18 644 **/
441fc6fd
CW		 645static int igb_get_i2c_clk(void *data)
646{
647 struct igb_adapter *adapter = (struct igb_adapter *)data;
648 struct e1000_hw *hw = &adapter->hw;
649 s32 i2cctl = rd32(E1000_I2CPARAMS);
650
651 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
652}
653
654static const struct i2c_algo_bit_data igb_i2c_algo = {
655 .setsda = igb_set_i2c_data,
656 .setscl = igb_set_i2c_clk,
657 .getsda = igb_get_i2c_data,
658 .getscl = igb_get_i2c_clk,
659 .udelay = 5,
660 .timeout = 20,
661};
662
9d5c8243 663/**
b980ac18
JK		 664 * igb_get_hw_dev - return device
665 * @hw: pointer to hardware structure
666 *
667 * used by hardware layer to print debugging information
9d5c8243 668 **/
c041076a 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 670{
671 struct igb_adapter *adapter = hw->back;
c041076a 672 return adapter->netdev;
9d5c8243 673}
38c845c7 674
9d5c8243 675/**
b980ac18 676 * igb_init_module - Driver Registration Routine
9d5c8243 677 *
b980ac18
JK		 678 * igb_init_module is the first routine called when the driver is
679 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 680 **/
681static int __init igb_init_module(void)
682{
683 int ret;
876d2d6f 684 pr_info("%s - version %s\n",
9d5c8243
AK		 685 igb_driver_string, igb_driver_version);
686
876d2d6f 687 pr_info("%s\n", igb_copyright);
9d5c8243 688
421e02f0 689#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 690 dca_register_notify(&dca_notifier);
691#endif
bbd98fe4 692 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 693 return ret;
694}
695
696module_init(igb_init_module);
697
698/**
b980ac18 699 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 700 *
b980ac18
JK		 701 * igb_exit_module is called just before the driver is removed
702 * from memory.
9d5c8243
AK		 703 **/
704static void __exit igb_exit_module(void)
705{
421e02f0 706#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 707 dca_unregister_notify(&dca_notifier);
708#endif
9d5c8243
AK		 709 pci_unregister_driver(&igb_driver);
710}
711
712module_exit(igb_exit_module);
713
26bc19ec
AD		 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
715/**
b980ac18
JK		 716 * igb_cache_ring_register - Descriptor ring to register mapping
717 * @adapter: board private structure to initialize
26bc19ec 718 *
b980ac18
JK		 719 * Once we know the feature-set enabled for the device, we'll cache
720 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 721 **/
722static void igb_cache_ring_register(struct igb_adapter *adapter)
723{
ee1b9f06 724 int i = 0, j = 0;
047e0030 725 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 726
727 switch (adapter->hw.mac.type) {
728 case e1000_82576:
729 /* The queues are allocated for virtualization such that VF 0
730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
731 * In order to avoid collision we start at the first free queue
732 * and continue consuming queues in the same sequence
733 */
ee1b9f06 734 if (adapter->vfs_allocated_count) {
a99955fc 735 for (; i < adapter->rss_queues; i++)
3025a446 736 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 737 Q_IDX_82576(i);
ee1b9f06 738 }
26bc19ec 739 case e1000_82575:
55cac248 740 case e1000_82580:
d2ba2ed8 741 case e1000_i350:
ceb5f13b 742 case e1000_i354:
f96a8a0b
CW		 743 case e1000_i210:
744 case e1000_i211:
26bc19ec 745 default:
ee1b9f06 746 for (; i < adapter->num_rx_queues; i++)
3025a446 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 748 for (; j < adapter->num_tx_queues; j++)
3025a446 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 750 break;
751 }
752}
753
22a8b291
FT		 754u32 igb_rd32(struct e1000_hw *hw, u32 reg)
755{
756 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
757 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
758 u32 value = 0;
759
760 if (E1000_REMOVED(hw_addr))
761 return ~value;
762
763 value = readl(&hw_addr[reg]);
764
765 /* reads should not return all F's */
766 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
767 struct net_device *netdev = igb->netdev;
768 hw->hw_addr = NULL;
769 netif_device_detach(netdev);
770 netdev_err(netdev, "PCIe link lost, device now detached\n");
771 }
772
773 return value;
774}
775
4be000c8
AD		 776/**
777 * igb_write_ivar - configure ivar for given MSI-X vector
778 * @hw: pointer to the HW structure
779 * @msix_vector: vector number we are allocating to a given ring
780 * @index: row index of IVAR register to write within IVAR table
781 * @offset: column offset of in IVAR, should be multiple of 8
782 *
783 * This function is intended to handle the writing of the IVAR register
784 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
785 * each containing an cause allocation for an Rx and Tx ring, and a
786 * variable number of rows depending on the number of queues supported.
787 **/
788static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
789 int index, int offset)
790{
791 u32 ivar = array_rd32(E1000_IVAR0, index);
792
793 /* clear any bits that are currently set */
794 ivar &= ~((u32)0xFF << offset);
795
796 /* write vector and valid bit */
797 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
798
799 array_wr32(E1000_IVAR0, index, ivar);
800}
801
9d5c8243 802#define IGB_N0_QUEUE -1
047e0030 803static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 804{
047e0030 805 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 806 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 807 int rx_queue = IGB_N0_QUEUE;
808 int tx_queue = IGB_N0_QUEUE;
4be000c8 809 u32 msixbm = 0;
047e0030 810
0ba82994
AD		 811 if (q_vector->rx.ring)
812 rx_queue = q_vector->rx.ring->reg_idx;
813 if (q_vector->tx.ring)
814 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 815
816 switch (hw->mac.type) {
817 case e1000_82575:
9d5c8243 818 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 819 * bitmask for the EICR/EIMS/EIMC registers. To assign one
820 * or more queues to a vector, we write the appropriate bits
821 * into the MSIXBM register for that vector.
822 */
047e0030 823 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 824 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 825 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 826 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 827 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 828 msixbm |= E1000_EIMS_OTHER;
9d5c8243 829 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 830 q_vector->eims_value = msixbm;
2d064c06
AD		 831 break;
832 case e1000_82576:
b980ac18 833 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 834 * with 8 rows. The ordering is column-major so we use the
835 * lower 3 bits as the row index, and the 4th bit as the
836 * column offset.
837 */
838 if (rx_queue > IGB_N0_QUEUE)
839 igb_write_ivar(hw, msix_vector,
840 rx_queue & 0x7,
841 (rx_queue & 0x8) << 1);
842 if (tx_queue > IGB_N0_QUEUE)
843 igb_write_ivar(hw, msix_vector,
844 tx_queue & 0x7,
845 ((tx_queue & 0x8) << 1) + 8);
047e0030 846 q_vector->eims_value = 1 << msix_vector;
2d064c06 847 break;
55cac248 848 case e1000_82580:
d2ba2ed8 849 case e1000_i350:
ceb5f13b 850 case e1000_i354:
f96a8a0b
CW		 851 case e1000_i210:
852 case e1000_i211:
b980ac18 853 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 854 * however instead of ordering column-major we have things
855 * ordered row-major. So we traverse the table by using
856 * bit 0 as the column offset, and the remaining bits as the
857 * row index.
858 */
859 if (rx_queue > IGB_N0_QUEUE)
860 igb_write_ivar(hw, msix_vector,
861 rx_queue >> 1,
862 (rx_queue & 0x1) << 4);
863 if (tx_queue > IGB_N0_QUEUE)
864 igb_write_ivar(hw, msix_vector,
865 tx_queue >> 1,
866 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 867 q_vector->eims_value = 1 << msix_vector;
868 break;
2d064c06
AD		 869 default:
870 BUG();
871 break;
872 }
26b39276
AD		 873
874 /* add q_vector eims value to global eims_enable_mask */
875 adapter->eims_enable_mask |= q_vector->eims_value;
876
877 /* configure q_vector to set itr on first interrupt */
878 q_vector->set_itr = 1;
9d5c8243
AK		 879}
880
881/**
b980ac18
JK		 882 * igb_configure_msix - Configure MSI-X hardware
883 * @adapter: board private structure to initialize
9d5c8243 884 *
b980ac18
JK		 885 * igb_configure_msix sets up the hardware to properly
886 * generate MSI-X interrupts.
9d5c8243
AK		 887 **/
888static void igb_configure_msix(struct igb_adapter *adapter)
889{
890 u32 tmp;
891 int i, vector = 0;
892 struct e1000_hw *hw = &adapter->hw;
893
894 adapter->eims_enable_mask = 0;
9d5c8243
AK		 895
896 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 897 switch (hw->mac.type) {
898 case e1000_82575:
9d5c8243
AK		 899 tmp = rd32(E1000_CTRL_EXT);
900 /* enable MSI-X PBA support*/
901 tmp |= E1000_CTRL_EXT_PBA_CLR;
902
903 /* Auto-Mask interrupts upon ICR read. */
904 tmp |= E1000_CTRL_EXT_EIAME;
905 tmp |= E1000_CTRL_EXT_IRCA;
906
907 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 908
909 /* enable msix_other interrupt */
b980ac18 910 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 911 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 912
2d064c06
AD		 913 break;
914
915 case e1000_82576:
55cac248 916 case e1000_82580:
d2ba2ed8 917 case e1000_i350:
ceb5f13b 918 case e1000_i354:
f96a8a0b
CW		 919 case e1000_i210:
920 case e1000_i211:
047e0030 921 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 922 * won't stick. And it will take days to debug.
923 */
047e0030 924 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 925 E1000_GPIE_PBA | E1000_GPIE_EIAME |
926 E1000_GPIE_NSICR);
047e0030
AD		 927
928 /* enable msix_other interrupt */
929 adapter->eims_other = 1 << vector;
2d064c06 930 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 931
047e0030 932 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 933 break;
934 default:
935 /* do nothing, since nothing else supports MSI-X */
936 break;
937 } /* switch (hw->mac.type) */
047e0030
AD		 938
939 adapter->eims_enable_mask |= adapter->eims_other;
940
26b39276
AD		 941 for (i = 0; i < adapter->num_q_vectors; i++)
942 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 943
9d5c8243
AK		 944 wrfl();
945}
946
947/**
b980ac18
JK		 948 * igb_request_msix - Initialize MSI-X interrupts
949 * @adapter: board private structure to initialize
9d5c8243 950 *
b980ac18
JK		 951 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
952 * kernel.
9d5c8243
AK		 953 **/
954static int igb_request_msix(struct igb_adapter *adapter)
955{
956 struct net_device *netdev = adapter->netdev;
047e0030 957 struct e1000_hw *hw = &adapter->hw;
52285b76 958 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 959
047e0030 960 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 961 igb_msix_other, 0, netdev->name, adapter);
047e0030 962 if (err)
52285b76 963 goto err_out;
047e0030
AD		 964
965 for (i = 0; i < adapter->num_q_vectors; i++) {
966 struct igb_q_vector *q_vector = adapter->q_vector[i];
967
52285b76
SA		 968 vector++;
969
047e0030
AD		 970 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
971
0ba82994 972 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 973 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 974 q_vector->rx.ring->queue_index);
975 else if (q_vector->tx.ring)
047e0030 976 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 977 q_vector->tx.ring->queue_index);
978 else if (q_vector->rx.ring)
047e0030 979 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 980 q_vector->rx.ring->queue_index);
9d5c8243 981 else
047e0030
AD		 982 sprintf(q_vector->name, "%s-unused", netdev->name);
983
9d5c8243 984 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 985 igb_msix_ring, 0, q_vector->name,
986 q_vector);
9d5c8243 987 if (err)
52285b76 988 goto err_free;
9d5c8243
AK		 989 }
990
9d5c8243
AK		 991 igb_configure_msix(adapter);
992 return 0;
52285b76
SA		 993
994err_free:
995 /* free already assigned IRQs */
996 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
997
998 vector--;
999 for (i = 0; i < vector; i++) {
1000 free_irq(adapter->msix_entries[free_vector++].vector,
1001 adapter->q_vector[i]);
1002 }
1003err_out:
9d5c8243
AK		 1004 return err;
1005}
1006
5536d210 1007/**
b980ac18
JK		 1008 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1009 * @adapter: board private structure to initialize
1010 * @v_idx: Index of vector to be freed
5536d210 1011 *
02ef6e1d 1012 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1013 **/
1014static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1015{
1016 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1017
02ef6e1d
CW		 1018 adapter->q_vector[v_idx] = NULL;
1019
1020 /* igb_get_stats64() might access the rings on this vector,
1021 * we must wait a grace period before freeing it.
1022 */
1023 kfree_rcu(q_vector, rcu);
1024}
1025
1026/**
1027 * igb_reset_q_vector - Reset config for interrupt vector
1028 * @adapter: board private structure to initialize
1029 * @v_idx: Index of vector to be reset
1030 *
1031 * If NAPI is enabled it will delete any references to the
1032 * NAPI struct. This is preparation for igb_free_q_vector.
1033 **/
1034static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1035{
1036 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1037
cb06d102
CP		 1038 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1039 * allocated. So, q_vector is NULL so we should stop here.
1040 */
1041 if (!q_vector)
1042 return;
1043
5536d210
AD		 1044 if (q_vector->tx.ring)
1045 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1046
1047 if (q_vector->rx.ring)
1048 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1049
5536d210
AD		 1050 netif_napi_del(&q_vector->napi);
1051
02ef6e1d
CW		 1052}
1053
1054static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1055{
1056 int v_idx = adapter->num_q_vectors;
1057
cd14ef54 1058 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1059 pci_disable_msix(adapter->pdev);
cd14ef54 1060 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1061 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1062
1063 while (v_idx--)
1064 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1065}
1066
047e0030 1067/**
b980ac18
JK		 1068 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1069 * @adapter: board private structure to initialize
047e0030 1070 *
b980ac18
JK		 1071 * This function frees the memory allocated to the q_vectors. In addition if
1072 * NAPI is enabled it will delete any references to the NAPI struct prior
1073 * to freeing the q_vector.
047e0030
AD		 1074 **/
1075static void igb_free_q_vectors(struct igb_adapter *adapter)
1076{
5536d210
AD		 1077 int v_idx = adapter->num_q_vectors;
1078
1079 adapter->num_tx_queues = 0;
1080 adapter->num_rx_queues = 0;
047e0030 1081 adapter->num_q_vectors = 0;
5536d210 1082
02ef6e1d
CW		 1083 while (v_idx--) {
1084 igb_reset_q_vector(adapter, v_idx);
5536d210 1085 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1086 }
047e0030
AD		 1087}
1088
1089/**
b980ac18
JK		 1090 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1091 * @adapter: board private structure to initialize
047e0030 1092 *
b980ac18
JK		 1093 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1094 * MSI-X interrupts allocated.
047e0030
AD		 1095 */
1096static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1097{
047e0030
AD		 1098 igb_free_q_vectors(adapter);
1099 igb_reset_interrupt_capability(adapter);
1100}
9d5c8243
AK		 1101
1102/**
b980ac18
JK		 1103 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1104 * @adapter: board private structure to initialize
1105 * @msix: boolean value of MSIX capability
9d5c8243 1106 *
b980ac18
JK		 1107 * Attempt to configure interrupts using the best available
1108 * capabilities of the hardware and kernel.
9d5c8243 1109 **/
53c7d064 1110static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1111{
1112 int err;
1113 int numvecs, i;
1114
53c7d064
SA		 1115 if (!msix)
1116 goto msi_only;
cd14ef54 1117 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1118
83b7180d 1119 /* Number of supported queues. */
a99955fc 1120 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1121 if (adapter->vfs_allocated_count)
1122 adapter->num_tx_queues = 1;
1123 else
1124 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1125
b980ac18 1126 /* start with one vector for every Rx queue */
047e0030
AD		 1127 numvecs = adapter->num_rx_queues;
1128
b980ac18 1129 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1130 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1131 numvecs += adapter->num_tx_queues;
047e0030
AD		 1132
1133 /* store the number of vectors reserved for queues */
1134 adapter->num_q_vectors = numvecs;
1135
1136 /* add 1 vector for link status interrupts */
1137 numvecs++;
9d5c8243
AK		 1138 for (i = 0; i < numvecs; i++)
1139 adapter->msix_entries[i].entry = i;
1140
479d02df
AG		 1141 err = pci_enable_msix_range(adapter->pdev,
1142 adapter->msix_entries,
1143 numvecs,
1144 numvecs);
1145 if (err > 0)
0c2cc02e 1146 return;
9d5c8243
AK		 1147
1148 igb_reset_interrupt_capability(adapter);
1149
1150 /* If we can't do MSI-X, try MSI */
1151msi_only:
2a3abf6d
AD		 1152#ifdef CONFIG_PCI_IOV
1153 /* disable SR-IOV for non MSI-X configurations */
1154 if (adapter->vf_data) {
1155 struct e1000_hw *hw = &adapter->hw;
1156 /* disable iov and allow time for transactions to clear */
1157 pci_disable_sriov(adapter->pdev);
1158 msleep(500);
1159
1160 kfree(adapter->vf_data);
1161 adapter->vf_data = NULL;
1162 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1163 wrfl();
2a3abf6d
AD		 1164 msleep(100);
1165 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1166 }
1167#endif
4fc82adf 1168 adapter->vfs_allocated_count = 0;
a99955fc 1169 adapter->rss_queues = 1;
4fc82adf 1170 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1171 adapter->num_rx_queues = 1;
661086df 1172 adapter->num_tx_queues = 1;
047e0030 1173 adapter->num_q_vectors = 1;
9d5c8243 1174 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1175 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1176}
1177
5536d210
AD		 1178static void igb_add_ring(struct igb_ring *ring,
1179 struct igb_ring_container *head)
1180{
1181 head->ring = ring;
1182 head->count++;
1183}
1184
047e0030 1185/**
b980ac18
JK		 1186 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1187 * @adapter: board private structure to initialize
1188 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1189 * @v_idx: index of vector in adapter struct
1190 * @txr_count: total number of Tx rings to allocate
1191 * @txr_idx: index of first Tx ring to allocate
1192 * @rxr_count: total number of Rx rings to allocate
1193 * @rxr_idx: index of first Rx ring to allocate
047e0030 1194 *
b980ac18 1195 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1196 **/
5536d210
AD		 1197static int igb_alloc_q_vector(struct igb_adapter *adapter,
1198 int v_count, int v_idx,
1199 int txr_count, int txr_idx,
1200 int rxr_count, int rxr_idx)
047e0030
AD		 1201{
1202 struct igb_q_vector *q_vector;
5536d210
AD		 1203 struct igb_ring *ring;
1204 int ring_count, size;
047e0030 1205
5536d210
AD		 1206 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1207 if (txr_count > 1 || rxr_count > 1)
1208 return -ENOMEM;
1209
1210 ring_count = txr_count + rxr_count;
1211 size = sizeof(struct igb_q_vector) +
1212 (sizeof(struct igb_ring) * ring_count);
1213
1214 /* allocate q_vector and rings */
02ef6e1d
CW		 1215 q_vector = adapter->q_vector[v_idx];
1216 if (!q_vector)
1217 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1218 if (!q_vector)
1219 return -ENOMEM;
1220
1221 /* initialize NAPI */
1222 netif_napi_add(adapter->netdev, &q_vector->napi,
1223 igb_poll, 64);
1224
1225 /* tie q_vector and adapter together */
1226 adapter->q_vector[v_idx] = q_vector;
1227 q_vector->adapter = adapter;
1228
1229 /* initialize work limits */
1230 q_vector->tx.work_limit = adapter->tx_work_limit;
1231
1232 /* initialize ITR configuration */
1233 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1234 q_vector->itr_val = IGB_START_ITR;
1235
1236 /* initialize pointer to rings */
1237 ring = q_vector->ring;
1238
4e227667
AD		 1239 /* intialize ITR */
1240 if (rxr_count) {
1241 /* rx or rx/tx vector */
1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 q_vector->itr_val = adapter->rx_itr_setting;
1244 } else {
1245 /* tx only vector */
1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 q_vector->itr_val = adapter->tx_itr_setting;
1248 }
1249
5536d210
AD		 1250 if (txr_count) {
1251 /* assign generic ring traits */
1252 ring->dev = &adapter->pdev->dev;
1253 ring->netdev = adapter->netdev;
1254
1255 /* configure backlink on ring */
1256 ring->q_vector = q_vector;
1257
1258 /* update q_vector Tx values */
1259 igb_add_ring(ring, &q_vector->tx);
1260
1261 /* For 82575, context index must be unique per ring. */
1262 if (adapter->hw.mac.type == e1000_82575)
1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1264
1265 /* apply Tx specific ring traits */
1266 ring->count = adapter->tx_ring_count;
1267 ring->queue_index = txr_idx;
1268
827da44c
JS		 1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1271
5536d210
AD		 1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1274
1275 /* push pointer to next ring */
1276 ring++;
047e0030 1277 }
81c2fc22 1278
5536d210
AD		 1279 if (rxr_count) {
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
047e0030 1283
5536d210
AD		 1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
047e0030 1286
5536d210
AD		 1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
047e0030 1289
5536d210
AD		 1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1293
ceb5f13b
CW		 1294 /*
1295 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1296 * have the tag byte-swapped.
b980ac18 1297 */
5536d210
AD		 1298 if (adapter->hw.mac.type >= e1000_i350)
1299 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1300
5536d210
AD		 1301 /* apply Rx specific ring traits */
1302 ring->count = adapter->rx_ring_count;
1303 ring->queue_index = rxr_idx;
1304
827da44c
JS		 1305 u64_stats_init(&ring->rx_syncp);
1306
5536d210
AD		 1307 /* assign ring to adapter */
1308 adapter->rx_ring[rxr_idx] = ring;
1309 }
1310
1311 return 0;
047e0030
AD		 1312}
1313
5536d210 1314
047e0030 1315/**
b980ac18
JK		 1316 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1317 * @adapter: board private structure to initialize
047e0030 1318 *
b980ac18
JK		 1319 * We allocate one q_vector per queue interrupt. If allocation fails we
1320 * return -ENOMEM.
047e0030 1321 **/
5536d210 1322static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1323{
5536d210
AD		 1324 int q_vectors = adapter->num_q_vectors;
1325 int rxr_remaining = adapter->num_rx_queues;
1326 int txr_remaining = adapter->num_tx_queues;
1327 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1328 int err;
047e0030 1329
5536d210
AD		 1330 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1331 for (; rxr_remaining; v_idx++) {
1332 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1333 0, 0, 1, rxr_idx);
047e0030 1334
5536d210
AD		 1335 if (err)
1336 goto err_out;
1337
1338 /* update counts and index */
1339 rxr_remaining--;
1340 rxr_idx++;
047e0030 1341 }
047e0030 1342 }
5536d210
AD		 1343
1344 for (; v_idx < q_vectors; v_idx++) {
1345 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1346 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1349
1350 if (err)
1351 goto err_out;
1352
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1356 rxr_idx++;
1357 txr_idx++;
1358 }
1359
047e0030 1360 return 0;
5536d210
AD		 1361
1362err_out:
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1366
1367 while (v_idx--)
1368 igb_free_q_vector(adapter, v_idx);
1369
1370 return -ENOMEM;
047e0030
AD		 1371}
1372
1373/**
b980ac18
JK		 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
047e0030 1377 *
b980ac18 1378 * This function initializes the interrupts and allocates all of the queues.
047e0030 1379 **/
53c7d064 1380static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1381{
1382 struct pci_dev *pdev = adapter->pdev;
1383 int err;
1384
53c7d064 1385 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1386
1387 err = igb_alloc_q_vectors(adapter);
1388 if (err) {
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1391 }
1392
5536d210 1393 igb_cache_ring_register(adapter);
047e0030
AD		 1394
1395 return 0;
5536d210 1396
047e0030
AD		 1397err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1399 return err;
1400}
1401
9d5c8243 1402/**
b980ac18
JK		 1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
9d5c8243 1405 *
b980ac18
JK		 1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
9d5c8243
AK		 1408 **/
1409static int igb_request_irq(struct igb_adapter *adapter)
1410{
1411 struct net_device *netdev = adapter->netdev;
047e0030 1412 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1413 int err = 0;
1414
cd14ef54 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1416 err = igb_request_msix(adapter);
844290e5 1417 if (!err)
9d5c8243 1418 goto request_done;
9d5c8243 1419 /* fall back to MSI */
5536d210
AD		 1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
53c7d064 1422
047e0030 1423 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1424 err = igb_init_interrupt_scheme(adapter, false);
1425 if (err)
047e0030 1426 goto request_done;
53c7d064 1427
047e0030
AD		 1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
53c7d064 1430 igb_configure(adapter);
9d5c8243 1431 }
844290e5 1432
c74d588e
AD		 1433 igb_assign_vector(adapter->q_vector[0], 0);
1434
7dfc16fa 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1437 netdev->name, adapter);
9d5c8243
AK		 1438 if (!err)
1439 goto request_done;
047e0030 1440
9d5c8243
AK		 1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
7dfc16fa 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1444 }
1445
c74d588e 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1447 netdev->name, adapter);
9d5c8243 1448
6cb5e577 1449 if (err)
c74d588e 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1451 err);
9d5c8243
AK		 1452
1453request_done:
1454 return err;
1455}
1456
1457static void igb_free_irq(struct igb_adapter *adapter)
1458{
cd14ef54 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1460 int vector = 0, i;
1461
047e0030 1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1463
0d1ae7f4 1464 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1465 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1466 adapter->q_vector[i]);
047e0030
AD		 1467 } else {
1468 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1469 }
9d5c8243
AK		 1470}
1471
1472/**
b980ac18
JK		 1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
9d5c8243
AK		 1475 **/
1476static void igb_irq_disable(struct igb_adapter *adapter)
1477{
1478 struct e1000_hw *hw = &adapter->hw;
1479
b980ac18 1480 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1483 */
cd14ef54 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212
AD		 1485 u32 regval = rd32(E1000_EIAM);
1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1490 }
844290e5
PW		 1491
1492 wr32(E1000_IAM, 0);
9d5c8243
AK		 1493 wr32(E1000_IMC, ~0);
1494 wrfl();
cd14ef54 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859
ET		 1496 int i;
1497 for (i = 0; i < adapter->num_q_vectors; i++)
1498 synchronize_irq(adapter->msix_entries[i].vector);
1499 } else {
1500 synchronize_irq(adapter->pdev->irq);
1501 }
9d5c8243
AK		 1502}
1503
1504/**
b980ac18
JK		 1505 * igb_irq_enable - Enable default interrupt generation settings
1506 * @adapter: board private structure
9d5c8243
AK		 1507 **/
1508static void igb_irq_enable(struct igb_adapter *adapter)
1509{
1510 struct e1000_hw *hw = &adapter->hw;
1511
cd14ef54 1512 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1513 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1514 u32 regval = rd32(E1000_EIAC);
1515 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1516 regval = rd32(E1000_EIAM);
1517 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1518 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1519 if (adapter->vfs_allocated_count) {
4ae196df 1520 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1521 ims |= E1000_IMS_VMMB;
1522 }
1523 wr32(E1000_IMS, ims);
844290e5 1524 } else {
55cac248
AD		 1525 wr32(E1000_IMS, IMS_ENABLE_MASK |
1526 E1000_IMS_DRSTA);
1527 wr32(E1000_IAM, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
844290e5 1529 }
9d5c8243
AK		 1530}
1531
1532static void igb_update_mng_vlan(struct igb_adapter *adapter)
1533{
51466239 1534 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1535 u16 vid = adapter->hw.mng_cookie.vlan_id;
1536 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1537
1538 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1539 /* add VID to filter table */
1540 igb_vfta_set(hw, vid, true);
1541 adapter->mng_vlan_id = vid;
1542 } else {
1543 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1544 }
1545
1546 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1547 (vid != old_vid) &&
b2cb09b1 1548 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1549 /* remove VID from filter table */
1550 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1551 }
1552}
1553
1554/**
b980ac18
JK		 1555 * igb_release_hw_control - release control of the h/w to f/w
1556 * @adapter: address of board private structure
9d5c8243 1557 *
b980ac18
JK		 1558 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1559 * For ASF and Pass Through versions of f/w this means that the
1560 * driver is no longer loaded.
9d5c8243
AK		 1561 **/
1562static void igb_release_hw_control(struct igb_adapter *adapter)
1563{
1564 struct e1000_hw *hw = &adapter->hw;
1565 u32 ctrl_ext;
1566
1567 /* Let firmware take over control of h/w */
1568 ctrl_ext = rd32(E1000_CTRL_EXT);
1569 wr32(E1000_CTRL_EXT,
1570 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1571}
1572
9d5c8243 1573/**
b980ac18
JK		 1574 * igb_get_hw_control - get control of the h/w from f/w
1575 * @adapter: address of board private structure
9d5c8243 1576 *
b980ac18
JK		 1577 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1578 * For ASF and Pass Through versions of f/w this means that
1579 * the driver is loaded.
9d5c8243
AK		 1580 **/
1581static void igb_get_hw_control(struct igb_adapter *adapter)
1582{
1583 struct e1000_hw *hw = &adapter->hw;
1584 u32 ctrl_ext;
1585
1586 /* Let firmware know the driver has taken over */
1587 ctrl_ext = rd32(E1000_CTRL_EXT);
1588 wr32(E1000_CTRL_EXT,
1589 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1590}
1591
9d5c8243 1592/**
b980ac18
JK		 1593 * igb_configure - configure the hardware for RX and TX
1594 * @adapter: private board structure
9d5c8243
AK		 1595 **/
1596static void igb_configure(struct igb_adapter *adapter)
1597{
1598 struct net_device *netdev = adapter->netdev;
1599 int i;
1600
1601 igb_get_hw_control(adapter);
ff41f8dc 1602 igb_set_rx_mode(netdev);
9d5c8243
AK		 1603
1604 igb_restore_vlan(adapter);
9d5c8243 1605
85b430b4 1606 igb_setup_tctl(adapter);
06cf2666 1607 igb_setup_mrqc(adapter);
9d5c8243 1608 igb_setup_rctl(adapter);
85b430b4
AD		 1609
1610 igb_configure_tx(adapter);
9d5c8243 1611 igb_configure_rx(adapter);
662d7205
AD		 1612
1613 igb_rx_fifo_flush_82575(&adapter->hw);
1614
c493ea45 1615 /* call igb_desc_unused which always leaves
9d5c8243 1616 * at least 1 descriptor unused to make sure
b980ac18
JK		 1617 * next_to_use != next_to_clean
1618 */
9d5c8243 1619 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1620 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1621 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1622 }
9d5c8243
AK		 1623}
1624
88a268c1 1625/**
b980ac18
JK		 1626 * igb_power_up_link - Power up the phy/serdes link
1627 * @adapter: address of board private structure
88a268c1
NN		 1628 **/
1629void igb_power_up_link(struct igb_adapter *adapter)
1630{
76886596
AA		 1631 igb_reset_phy(&adapter->hw);
1632
88a268c1
NN		 1633 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1634 igb_power_up_phy_copper(&adapter->hw);
1635 else
1636 igb_power_up_serdes_link_82575(&adapter->hw);
1637}
1638
1639/**
b980ac18
JK		 1640 * igb_power_down_link - Power down the phy/serdes link
1641 * @adapter: address of board private structure
88a268c1
NN		 1642 */
1643static void igb_power_down_link(struct igb_adapter *adapter)
1644{
1645 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1646 igb_power_down_phy_copper_82575(&adapter->hw);
1647 else
1648 igb_shutdown_serdes_link_82575(&adapter->hw);
1649}
9d5c8243 1650
56cec249
CW		 1651/**
1652 * Detect and switch function for Media Auto Sense
1653 * @adapter: address of the board private structure
1654 **/
1655static void igb_check_swap_media(struct igb_adapter *adapter)
1656{
1657 struct e1000_hw *hw = &adapter->hw;
1658 u32 ctrl_ext, connsw;
1659 bool swap_now = false;
1660
1661 ctrl_ext = rd32(E1000_CTRL_EXT);
1662 connsw = rd32(E1000_CONNSW);
1663
1664 /* need to live swap if current media is copper and we have fiber/serdes
1665 * to go to.
1666 */
1667
1668 if ((hw->phy.media_type == e1000_media_type_copper) &&
1669 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1670 swap_now = true;
1671 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1672 /* copper signal takes time to appear */
1673 if (adapter->copper_tries < 4) {
1674 adapter->copper_tries++;
1675 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1676 wr32(E1000_CONNSW, connsw);
1677 return;
1678 } else {
1679 adapter->copper_tries = 0;
1680 if ((connsw & E1000_CONNSW_PHYSD) &&
1681 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1682 swap_now = true;
1683 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1684 wr32(E1000_CONNSW, connsw);
1685 }
1686 }
1687 }
1688
1689 if (!swap_now)
1690 return;
1691
1692 switch (hw->phy.media_type) {
1693 case e1000_media_type_copper:
1694 netdev_info(adapter->netdev,
1695 "MAS: changing media to fiber/serdes\n");
1696 ctrl_ext |=
1697 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1698 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1699 adapter->copper_tries = 0;
1700 break;
1701 case e1000_media_type_internal_serdes:
1702 case e1000_media_type_fiber:
1703 netdev_info(adapter->netdev,
1704 "MAS: changing media to copper\n");
1705 ctrl_ext &=
1706 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1707 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1708 break;
1709 default:
1710 /* shouldn't get here during regular operation */
1711 netdev_err(adapter->netdev,
1712 "AMS: Invalid media type found, returning\n");
1713 break;
1714 }
1715 wr32(E1000_CTRL_EXT, ctrl_ext);
1716}
1717
9d5c8243 1718/**
b980ac18
JK		 1719 * igb_up - Open the interface and prepare it to handle traffic
1720 * @adapter: board private structure
9d5c8243 1721 **/
9d5c8243
AK		 1722int igb_up(struct igb_adapter *adapter)
1723{
1724 struct e1000_hw *hw = &adapter->hw;
1725 int i;
1726
1727 /* hardware has been reset, we need to reload some things */
1728 igb_configure(adapter);
1729
1730 clear_bit(__IGB_DOWN, &adapter->state);
1731
0d1ae7f4
AD		 1732 for (i = 0; i < adapter->num_q_vectors; i++)
1733 napi_enable(&(adapter->q_vector[i]->napi));
1734
cd14ef54 1735 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1736 igb_configure_msix(adapter);
feeb2721
AD		 1737 else
1738 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1739
1740 /* Clear any pending interrupts. */
1741 rd32(E1000_ICR);
1742 igb_irq_enable(adapter);
1743
d4960307
AD		 1744 /* notify VFs that reset has been completed */
1745 if (adapter->vfs_allocated_count) {
1746 u32 reg_data = rd32(E1000_CTRL_EXT);
1747 reg_data |= E1000_CTRL_EXT_PFRSTD;
1748 wr32(E1000_CTRL_EXT, reg_data);
1749 }
1750
4cb9be7a
JB		 1751 netif_tx_start_all_queues(adapter->netdev);
1752
25568a53
AD		 1753 /* start the watchdog. */
1754 hw->mac.get_link_status = 1;
1755 schedule_work(&adapter->watchdog_task);
1756
f4c01e96
CW		 1757 if ((adapter->flags & IGB_FLAG_EEE) &&
1758 (!hw->dev_spec._82575.eee_disable))
1759 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1760
9d5c8243
AK		 1761 return 0;
1762}
1763
1764void igb_down(struct igb_adapter *adapter)
1765{
9d5c8243 1766 struct net_device *netdev = adapter->netdev;
330a6d6a 1767 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1768 u32 tctl, rctl;
1769 int i;
1770
1771 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1772 * reschedule our watchdog timer
1773 */
9d5c8243
AK		 1774 set_bit(__IGB_DOWN, &adapter->state);
1775
1776 /* disable receives in the hardware */
1777 rctl = rd32(E1000_RCTL);
1778 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1779 /* flush and sleep below */
1780
fd2ea0a7 1781 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1782
1783 /* disable transmits in the hardware */
1784 tctl = rd32(E1000_TCTL);
1785 tctl &= ~E1000_TCTL_EN;
1786 wr32(E1000_TCTL, tctl);
1787 /* flush both disables and wait for them to finish */
1788 wrfl();
1789 msleep(10);
1790
41f149a2
CW		 1791 igb_irq_disable(adapter);
1792
aa9b8cc4
AA		 1793 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1794
41f149a2
CW		 1795 for (i = 0; i < adapter->num_q_vectors; i++) {
1796 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1797 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1798 }
9d5c8243 1799
9d5c8243
AK		 1800
1801 del_timer_sync(&adapter->watchdog_timer);
1802 del_timer_sync(&adapter->phy_info_timer);
1803
9d5c8243 1804 netif_carrier_off(netdev);
04fe6358
AD		 1805
1806 /* record the stats before reset*/
12dcd86b
ED		 1807 spin_lock(&adapter->stats64_lock);
1808 igb_update_stats(adapter, &adapter->stats64);
1809 spin_unlock(&adapter->stats64_lock);
04fe6358 1810
9d5c8243
AK		 1811 adapter->link_speed = 0;
1812 adapter->link_duplex = 0;
1813
3023682e
JK		 1814 if (!pci_channel_offline(adapter->pdev))
1815 igb_reset(adapter);
9d5c8243
AK		 1816 igb_clean_all_tx_rings(adapter);
1817 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1818#ifdef CONFIG_IGB_DCA
1819
1820 /* since we reset the hardware DCA settings were cleared */
1821 igb_setup_dca(adapter);
1822#endif
9d5c8243
AK		 1823}
1824
1825void igb_reinit_locked(struct igb_adapter *adapter)
1826{
1827 WARN_ON(in_interrupt());
1828 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1829 msleep(1);
1830 igb_down(adapter);
1831 igb_up(adapter);
1832 clear_bit(__IGB_RESETTING, &adapter->state);
1833}
1834
56cec249
CW		 1835/** igb_enable_mas - Media Autosense re-enable after swap
1836 *
1837 * @adapter: adapter struct
1838 **/
1839static s32 igb_enable_mas(struct igb_adapter *adapter)
1840{
1841 struct e1000_hw *hw = &adapter->hw;
1842 u32 connsw;
1843 s32 ret_val = 0;
1844
1845 connsw = rd32(E1000_CONNSW);
1846 if (!(hw->phy.media_type == e1000_media_type_copper))
1847 return ret_val;
1848
1849 /* configure for SerDes media detect */
1850 if (!(connsw & E1000_CONNSW_SERDESD)) {
1851 connsw |= E1000_CONNSW_ENRGSRC;
1852 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1853 wr32(E1000_CONNSW, connsw);
1854 wrfl();
1855 } else if (connsw & E1000_CONNSW_SERDESD) {
1856 /* already SerDes, no need to enable anything */
1857 return ret_val;
1858 } else {
1859 netdev_info(adapter->netdev,
1860 "MAS: Unable to configure feature, disabling..\n");
1861 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1862 }
1863 return ret_val;
1864}
1865
9d5c8243
AK		 1866void igb_reset(struct igb_adapter *adapter)
1867{
090b1795 1868 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1869 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1870 struct e1000_mac_info *mac = &hw->mac;
1871 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1872 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1873
1874 /* Repartition Pba for greater than 9k mtu
1875 * To take effect CTRL.RST is required.
1876 */
fa4dfae0 1877 switch (mac->type) {
d2ba2ed8 1878 case e1000_i350:
ceb5f13b 1879 case e1000_i354:
55cac248
AD		 1880 case e1000_82580:
1881 pba = rd32(E1000_RXPBS);
1882 pba = igb_rxpbs_adjust_82580(pba);
1883 break;
fa4dfae0 1884 case e1000_82576:
d249be54
AD		 1885 pba = rd32(E1000_RXPBS);
1886 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1887 break;
1888 case e1000_82575:
f96a8a0b
CW		 1889 case e1000_i210:
1890 case e1000_i211:
fa4dfae0
AD		 1891 default:
1892 pba = E1000_PBA_34K;
1893 break;
2d064c06 1894 }
9d5c8243 1895
2d064c06
AD		 1896 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1897 (mac->type < e1000_82576)) {
9d5c8243
AK		 1898 /* adjust PBA for jumbo frames */
1899 wr32(E1000_PBA, pba);
1900
1901 /* To maintain wire speed transmits, the Tx FIFO should be
1902 * large enough to accommodate two full transmit packets,
1903 * rounded up to the next 1KB and expressed in KB. Likewise,
1904 * the Rx FIFO should be large enough to accommodate at least
1905 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1906 * expressed in KB.
1907 */
9d5c8243
AK		 1908 pba = rd32(E1000_PBA);
1909 /* upper 16 bits has Tx packet buffer allocation size in KB */
1910 tx_space = pba >> 16;
1911 /* lower 16 bits has Rx packet buffer allocation size in KB */
1912 pba &= 0xffff;
b980ac18
JK		 1913 /* the Tx fifo also stores 16 bytes of information about the Tx
1914 * but don't include ethernet FCS because hardware appends it
1915 */
9d5c8243 1916 min_tx_space = (adapter->max_frame_size +
85e8d004 1917 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1918 ETH_FCS_LEN) * 2;
1919 min_tx_space = ALIGN(min_tx_space, 1024);
1920 min_tx_space >>= 10;
1921 /* software strips receive CRC, so leave room for it */
1922 min_rx_space = adapter->max_frame_size;
1923 min_rx_space = ALIGN(min_rx_space, 1024);
1924 min_rx_space >>= 10;
1925
1926 /* If current Tx allocation is less than the min Tx FIFO size,
1927 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1928 * allocation, take space away from current Rx allocation
1929 */
9d5c8243
AK		 1930 if (tx_space < min_tx_space &&
1931 ((min_tx_space - tx_space) < pba)) {
1932 pba = pba - (min_tx_space - tx_space);
1933
b980ac18
JK		 1934 /* if short on Rx space, Rx wins and must trump Tx
1935 * adjustment
1936 */
9d5c8243
AK		 1937 if (pba < min_rx_space)
1938 pba = min_rx_space;
1939 }
2d064c06 1940 wr32(E1000_PBA, pba);
9d5c8243 1941 }
9d5c8243
AK		 1942
1943 /* flow control settings */
1944 /* The high water mark must be low enough to fit one full frame
1945 * (or the size used for early receive) above it in the Rx FIFO.
1946 * Set it to the lower of:
1947 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1948 * - the full Rx FIFO size minus one full frame
1949 */
9d5c8243 1950 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1951 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1952
d48507fe 1953 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1954 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1955 fc->pause_time = 0xFFFF;
1956 fc->send_xon = 1;
0cce119a 1957 fc->current_mode = fc->requested_mode;
9d5c8243 1958
4ae196df
AD		 1959 /* disable receive for all VFs and wait one second */
1960 if (adapter->vfs_allocated_count) {
1961 int i;
1962 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1963 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1964
1965 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1966 igb_ping_all_vfs(adapter);
4ae196df
AD		 1967
1968 /* disable transmits and receives */
1969 wr32(E1000_VFRE, 0);
1970 wr32(E1000_VFTE, 0);
1971 }
1972
9d5c8243 1973 /* Allow time for pending master requests to run */
330a6d6a 1974 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1975 wr32(E1000_WUC, 0);
1976
56cec249
CW		 1977 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1978 /* need to resetup here after media swap */
1979 adapter->ei.get_invariants(hw);
1980 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1981 }
1982 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1983 if (igb_enable_mas(adapter))
1984 dev_err(&pdev->dev,
1985 "Error enabling Media Auto Sense\n");
1986 }
330a6d6a 1987 if (hw->mac.ops.init_hw(hw))
090b1795 1988 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1989
b980ac18 1990 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1991 * control is off when forcing speed.
1992 */
1993 if (!hw->mac.autoneg)
1994 igb_force_mac_fc(hw);
1995
b6e0c419 1996 igb_init_dmac(adapter, pba);
e428893b
CW		 1997#ifdef CONFIG_IGB_HWMON
1998 /* Re-initialize the thermal sensor on i350 devices. */
1999 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2000 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2001 /* If present, re-initialize the external thermal sensor
2002 * interface.
2003 */
2004 if (adapter->ets)
2005 mac->ops.init_thermal_sensor_thresh(hw);
2006 }
2007 }
2008#endif
b936136d 2009 /* Re-establish EEE setting */
f4c01e96
CW		 2010 if (hw->phy.media_type == e1000_media_type_copper) {
2011 switch (mac->type) {
2012 case e1000_i350:
2013 case e1000_i210:
2014 case e1000_i211:
2015 igb_set_eee_i350(hw);
2016 break;
2017 case e1000_i354:
2018 igb_set_eee_i354(hw);
2019 break;
2020 default:
2021 break;
2022 }
2023 }
88a268c1
NN		 2024 if (!netif_running(adapter->netdev))
2025 igb_power_down_link(adapter);
2026
9d5c8243
AK		 2027 igb_update_mng_vlan(adapter);
2028
2029 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2030 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2031
1f6e8178
MV		 2032 /* Re-enable PTP, where applicable. */
2033 igb_ptp_reset(adapter);
1f6e8178 2034
330a6d6a 2035 igb_get_phy_info(hw);
9d5c8243
AK		 2036}
2037
c8f44aff
MM		 2038static netdev_features_t igb_fix_features(struct net_device *netdev,
2039 netdev_features_t features)
b2cb09b1 2040{
b980ac18
JK		 2041 /* Since there is no support for separate Rx/Tx vlan accel
2042 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2043 */
f646968f
PM		 2044 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2045 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2046 else
f646968f 2047 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2048
2049 return features;
2050}
2051
c8f44aff
MM		 2052static int igb_set_features(struct net_device *netdev,
2053 netdev_features_t features)
ac52caa3 2054{
c8f44aff 2055 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2056 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2057
f646968f 2058 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2059 igb_vlan_mode(netdev, features);
2060
89eaefb6
BG		 2061 if (!(changed & NETIF_F_RXALL))
2062 return 0;
2063
2064 netdev->features = features;
2065
2066 if (netif_running(netdev))
2067 igb_reinit_locked(adapter);
2068 else
2069 igb_reset(adapter);
2070
ac52caa3
MM		 2071 return 0;
2072}
2073
2e5c6922 2074static const struct net_device_ops igb_netdev_ops = {
559e9c49 2075 .ndo_open = igb_open,
2e5c6922 2076 .ndo_stop = igb_close,
cd392f5c 2077 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2078 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2079 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2080 .ndo_set_mac_address = igb_set_mac,
2081 .ndo_change_mtu = igb_change_mtu,
2082 .ndo_do_ioctl = igb_ioctl,
2083 .ndo_tx_timeout = igb_tx_timeout,
2084 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2085 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2086 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2087 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2088 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2089 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 2090 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2091 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2092#ifdef CONFIG_NET_POLL_CONTROLLER
2093 .ndo_poll_controller = igb_netpoll,
2094#endif
b2cb09b1
JP		 2095 .ndo_fix_features = igb_fix_features,
2096 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2097};
2098
d67974f0
CW		 2099/**
2100 * igb_set_fw_version - Configure version string for ethtool
2101 * @adapter: adapter struct
d67974f0
CW		 2102 **/
2103void igb_set_fw_version(struct igb_adapter *adapter)
2104{
2105 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2106 struct e1000_fw_version fw;
2107
2108 igb_get_fw_version(hw, &fw);
2109
2110 switch (hw->mac.type) {
7dc98a62 2111 case e1000_i210:
0b1a6f2e 2112 case e1000_i211:
7dc98a62
CW		 2113 if (!(igb_get_flash_presence_i210(hw))) {
2114 snprintf(adapter->fw_version,
2115 sizeof(adapter->fw_version),
2116 "%2d.%2d-%d",
2117 fw.invm_major, fw.invm_minor,
2118 fw.invm_img_type);
2119 break;
2120 }
2121 /* fall through */
0b1a6f2e
CW		 2122 default:
2123 /* if option is rom valid, display its version too */
2124 if (fw.or_valid) {
2125 snprintf(adapter->fw_version,
2126 sizeof(adapter->fw_version),
2127 "%d.%d, 0x%08x, %d.%d.%d",
2128 fw.eep_major, fw.eep_minor, fw.etrack_id,
2129 fw.or_major, fw.or_build, fw.or_patch);
2130 /* no option rom */
7dc98a62 2131 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2132 snprintf(adapter->fw_version,
7dc98a62
CW		 2133 sizeof(adapter->fw_version),
2134 "%d.%d, 0x%08x",
2135 fw.eep_major, fw.eep_minor, fw.etrack_id);
2136 } else {
2137 snprintf(adapter->fw_version,
2138 sizeof(adapter->fw_version),
2139 "%d.%d.%d",
2140 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2141 }
2142 break;
d67974f0 2143 }
d67974f0
CW		 2144 return;
2145}
2146
56cec249
CW		 2147/**
2148 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2149 *
2150 * @adapter: adapter struct
2151 **/
2152static void igb_init_mas(struct igb_adapter *adapter)
2153{
2154 struct e1000_hw *hw = &adapter->hw;
2155 u16 eeprom_data;
2156
2157 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2158 switch (hw->bus.func) {
2159 case E1000_FUNC_0:
2160 if (eeprom_data & IGB_MAS_ENABLE_0) {
2161 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2162 netdev_info(adapter->netdev,
2163 "MAS: Enabling Media Autosense for port %d\n",
2164 hw->bus.func);
2165 }
2166 break;
2167 case E1000_FUNC_1:
2168 if (eeprom_data & IGB_MAS_ENABLE_1) {
2169 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2170 netdev_info(adapter->netdev,
2171 "MAS: Enabling Media Autosense for port %d\n",
2172 hw->bus.func);
2173 }
2174 break;
2175 case E1000_FUNC_2:
2176 if (eeprom_data & IGB_MAS_ENABLE_2) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 case E1000_FUNC_3:
2184 if (eeprom_data & IGB_MAS_ENABLE_3) {
2185 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2186 netdev_info(adapter->netdev,
2187 "MAS: Enabling Media Autosense for port %d\n",
2188 hw->bus.func);
2189 }
2190 break;
2191 default:
2192 /* Shouldn't get here */
2193 netdev_err(adapter->netdev,
2194 "MAS: Invalid port configuration, returning\n");
2195 break;
2196 }
2197}
2198
b980ac18
JK		 2199/**
2200 * igb_init_i2c - Init I2C interface
441fc6fd 2201 * @adapter: pointer to adapter structure
b980ac18 2202 **/
441fc6fd
CW		 2203static s32 igb_init_i2c(struct igb_adapter *adapter)
2204{
2205 s32 status = E1000_SUCCESS;
2206
2207 /* I2C interface supported on i350 devices */
2208 if (adapter->hw.mac.type != e1000_i350)
2209 return E1000_SUCCESS;
2210
2211 /* Initialize the i2c bus which is controlled by the registers.
2212 * This bus will use the i2c_algo_bit structue that implements
2213 * the protocol through toggling of the 4 bits in the register.
2214 */
2215 adapter->i2c_adap.owner = THIS_MODULE;
2216 adapter->i2c_algo = igb_i2c_algo;
2217 adapter->i2c_algo.data = adapter;
2218 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2219 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2220 strlcpy(adapter->i2c_adap.name, "igb BB",
2221 sizeof(adapter->i2c_adap.name));
2222 status = i2c_bit_add_bus(&adapter->i2c_adap);
2223 return status;
2224}
2225
9d5c8243 2226/**
b980ac18
JK		 2227 * igb_probe - Device Initialization Routine
2228 * @pdev: PCI device information struct
2229 * @ent: entry in igb_pci_tbl
9d5c8243 2230 *
b980ac18 2231 * Returns 0 on success, negative on failure
9d5c8243 2232 *
b980ac18
JK		 2233 * igb_probe initializes an adapter identified by a pci_dev structure.
2234 * The OS initialization, configuring of the adapter private structure,
2235 * and a hardware reset occur.
9d5c8243 2236 **/
1dd06ae8 2237static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2238{
2239 struct net_device *netdev;
2240 struct igb_adapter *adapter;
2241 struct e1000_hw *hw;
4337e993 2242 u16 eeprom_data = 0;
9835fd73 2243 s32 ret_val;
4337e993 2244 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2245 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2246 int err, pci_using_dac;
9835fd73 2247 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2248
bded64a7
AG		 2249 /* Catch broken hardware that put the wrong VF device ID in
2250 * the PCIe SR-IOV capability.
2251 */
2252 if (pdev->is_virtfn) {
2253 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2254 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2255 return -EINVAL;
2256 }
2257
aed5dec3 2258 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2259 if (err)
2260 return err;
2261
2262 pci_using_dac = 0;
dc4ff9bb 2263 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2264 if (!err) {
dc4ff9bb 2265 pci_using_dac = 1;
9d5c8243 2266 } else {
dc4ff9bb 2267 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2268 if (err) {
dc4ff9bb
RK		 2269 dev_err(&pdev->dev,
2270 "No usable DMA configuration, aborting\n");
2271 goto err_dma;
9d5c8243
AK		 2272 }
2273 }
2274
aed5dec3 2275 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2276 IORESOURCE_MEM),
2277 igb_driver_name);
9d5c8243
AK		 2278 if (err)
2279 goto err_pci_reg;
2280
19d5afd4 2281 pci_enable_pcie_error_reporting(pdev);
40a914fa 2282
9d5c8243 2283 pci_set_master(pdev);
c682fc23 2284 pci_save_state(pdev);
9d5c8243
AK		 2285
2286 err = -ENOMEM;
1bfaf07b 2287 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2288 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2289 if (!netdev)
2290 goto err_alloc_etherdev;
2291
2292 SET_NETDEV_DEV(netdev, &pdev->dev);
2293
2294 pci_set_drvdata(pdev, netdev);
2295 adapter = netdev_priv(netdev);
2296 adapter->netdev = netdev;
2297 adapter->pdev = pdev;
2298 hw = &adapter->hw;
2299 hw->back = adapter;
b3f4d599 2300 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2301
9d5c8243 2302 err = -EIO;
89dbefb2 2303 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2304 if (!hw->hw_addr)
9d5c8243
AK		 2305 goto err_ioremap;
2306
2e5c6922 2307 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2308 igb_set_ethtool_ops(netdev);
9d5c8243 2309 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2310
2311 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2312
89dbefb2
AS		 2313 netdev->mem_start = pci_resource_start(pdev, 0);
2314 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2315
9d5c8243
AK		 2316 /* PCI config space info */
2317 hw->vendor_id = pdev->vendor;
2318 hw->device_id = pdev->device;
2319 hw->revision_id = pdev->revision;
2320 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2321 hw->subsystem_device_id = pdev->subsystem_device;
2322
9d5c8243
AK		 2323 /* Copy the default MAC, PHY and NVM function pointers */
2324 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2325 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2326 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2327 /* Initialize skew-specific constants */
2328 err = ei->get_invariants(hw);
2329 if (err)
450c87c8 2330 goto err_sw_init;
9d5c8243 2331
450c87c8 2332 /* setup the private structure */
9d5c8243
AK		 2333 err = igb_sw_init(adapter);
2334 if (err)
2335 goto err_sw_init;
2336
2337 igb_get_bus_info_pcie(hw);
2338
2339 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2340
2341 /* Copper options */
2342 if (hw->phy.media_type == e1000_media_type_copper) {
2343 hw->phy.mdix = AUTO_ALL_MODES;
2344 hw->phy.disable_polarity_correction = false;
2345 hw->phy.ms_type = e1000_ms_hw_default;
2346 }
2347
2348 if (igb_check_reset_block(hw))
2349 dev_info(&pdev->dev,
2350 "PHY reset is blocked due to SOL/IDER session.\n");
2351
b980ac18 2352 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2353 * set by igb_sw_init so we should use an or instead of an
2354 * assignment.
2355 */
2356 netdev->features |= NETIF_F_SG |
2357 NETIF_F_IP_CSUM |
2358 NETIF_F_IPV6_CSUM |
2359 NETIF_F_TSO |
2360 NETIF_F_TSO6 |
2361 NETIF_F_RXHASH |
2362 NETIF_F_RXCSUM |
f646968f
PM		 2363 NETIF_F_HW_VLAN_CTAG_RX |
2364 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2365
2366 /* copy netdev features into list of user selectable features */
2367 netdev->hw_features |= netdev->features;
89eaefb6 2368 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2369
2370 /* set this bit last since it cannot be part of hw_features */
f646968f 2371 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2372
2373 netdev->vlan_features |= NETIF_F_TSO |
2374 NETIF_F_TSO6 |
2375 NETIF_F_IP_CSUM |
2376 NETIF_F_IPV6_CSUM |
2377 NETIF_F_SG;
48f29ffc 2378
6b8f0922
BG		 2379 netdev->priv_flags |= IFF_SUPP_NOFCS;
2380
7b872a55 2381 if (pci_using_dac) {
9d5c8243 2382 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2383 netdev->vlan_features |= NETIF_F_HIGHDMA;
2384 }
9d5c8243 2385
ac52caa3
MM		 2386 if (hw->mac.type >= e1000_82576) {
2387 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2388 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2389 }
b9473560 2390
01789349
JP		 2391 netdev->priv_flags |= IFF_UNICAST_FLT;
2392
330a6d6a 2393 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2394
2395 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2396 * known good starting state
2397 */
9d5c8243
AK		 2398 hw->mac.ops.reset_hw(hw);
2399
ef3a0092
CW		 2400 /* make sure the NVM is good , i211/i210 parts can have special NVM
2401 * that doesn't contain a checksum
f96a8a0b 2402 */
ef3a0092
CW		 2403 switch (hw->mac.type) {
2404 case e1000_i210:
2405 case e1000_i211:
2406 if (igb_get_flash_presence_i210(hw)) {
2407 if (hw->nvm.ops.validate(hw) < 0) {
2408 dev_err(&pdev->dev,
2409 "The NVM Checksum Is Not Valid\n");
2410 err = -EIO;
2411 goto err_eeprom;
2412 }
2413 }
2414 break;
2415 default:
f96a8a0b
CW		 2416 if (hw->nvm.ops.validate(hw) < 0) {
2417 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2418 err = -EIO;
2419 goto err_eeprom;
2420 }
ef3a0092 2421 break;
9d5c8243
AK		 2422 }
2423
2424 /* copy the MAC address out of the NVM */
2425 if (hw->mac.ops.read_mac_addr(hw))
2426 dev_err(&pdev->dev, "NVM Read Error\n");
2427
2428 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2429
aaeb6cdf 2430 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2431 dev_err(&pdev->dev, "Invalid MAC Address\n");
2432 err = -EIO;
2433 goto err_eeprom;
2434 }
2435
d67974f0
CW		 2436 /* get firmware version for ethtool -i */
2437 igb_set_fw_version(adapter);
2438
c061b18d 2439 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2440 (unsigned long) adapter);
c061b18d 2441 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2442 (unsigned long) adapter);
9d5c8243
AK		 2443
2444 INIT_WORK(&adapter->reset_task, igb_reset_task);
2445 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2446
450c87c8 2447 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2448 adapter->fc_autoneg = true;
2449 hw->mac.autoneg = true;
2450 hw->phy.autoneg_advertised = 0x2f;
2451
0cce119a
AD		 2452 hw->fc.requested_mode = e1000_fc_default;
2453 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2454
9d5c8243
AK		 2455 igb_validate_mdi_setting(hw);
2456
63d4a8f9 2457 /* By default, support wake on port A */
a2cf8b6c 2458 if (hw->bus.func == 0)
63d4a8f9
MV		 2459 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2460
2461 /* Check the NVM for wake support on non-port A ports */
2462 if (hw->mac.type >= e1000_82580)
55cac248 2463 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2464 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2465 &eeprom_data);
a2cf8b6c
AD		 2466 else if (hw->bus.func == 1)
2467 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2468
63d4a8f9
MV		 2469 if (eeprom_data & IGB_EEPROM_APME)
2470 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2471
2472 /* now that we have the eeprom settings, apply the special cases where
2473 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2474 * lan on a particular port
2475 */
9d5c8243
AK		 2476 switch (pdev->device) {
2477 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2478 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2479 break;
2480 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2481 case E1000_DEV_ID_82576_FIBER:
2482 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2483 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2484 * regardless of eeprom setting
2485 */
9d5c8243 2486 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2488 break;
c8ea5ea9 2489 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2490 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2491 /* if quad port adapter, disable WoL on all but port A */
2492 if (global_quad_port_a != 0)
63d4a8f9 2493 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2494 else
2495 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2496 /* Reset for multiple quad port adapters */
2497 if (++global_quad_port_a == 4)
2498 global_quad_port_a = 0;
2499 break;
63d4a8f9
MV		 2500 default:
2501 /* If the device can't wake, don't set software support */
2502 if (!device_can_wakeup(&adapter->pdev->dev))
2503 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2504 }
2505
2506 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2507 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2508 adapter->wol |= E1000_WUFC_MAG;
2509
2510 /* Some vendors want WoL disabled by default, but still supported */
2511 if ((hw->mac.type == e1000_i350) &&
2512 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2514 adapter->wol = 0;
2515 }
2516
2517 device_set_wakeup_enable(&adapter->pdev->dev,
2518 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2519
2520 /* reset the hardware with the new settings */
2521 igb_reset(adapter);
2522
441fc6fd
CW		 2523 /* Init the I2C interface */
2524 err = igb_init_i2c(adapter);
2525 if (err) {
2526 dev_err(&pdev->dev, "failed to init i2c interface\n");
2527 goto err_eeprom;
2528 }
2529
9d5c8243
AK		 2530 /* let the f/w know that the h/w is now under the control of the
2531 * driver. */
2532 igb_get_hw_control(adapter);
2533
9d5c8243
AK		 2534 strcpy(netdev->name, "eth%d");
2535 err = register_netdev(netdev);
2536 if (err)
2537 goto err_register;
2538
b168dfc5
JB		 2539 /* carrier off reporting is important to ethtool even BEFORE open */
2540 netif_carrier_off(netdev);
2541
421e02f0 2542#ifdef CONFIG_IGB_DCA
bbd98fe4 2543 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2544 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2545 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2546 igb_setup_dca(adapter);
2547 }
fe4506b6 2548
38c845c7 2549#endif
e428893b
CW		 2550#ifdef CONFIG_IGB_HWMON
2551 /* Initialize the thermal sensor on i350 devices. */
2552 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2553 u16 ets_word;
3c89f6d0 2554
b980ac18 2555 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2556 * external thermal sensor.
2557 */
2558 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2559 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2560 adapter->ets = true;
2561 else
2562 adapter->ets = false;
2563 if (igb_sysfs_init(adapter))
2564 dev_err(&pdev->dev,
2565 "failed to allocate sysfs resources\n");
2566 } else {
2567 adapter->ets = false;
2568 }
2569#endif
56cec249
CW		 2570 /* Check if Media Autosense is enabled */
2571 adapter->ei = *ei;
2572 if (hw->dev_spec._82575.mas_capable)
2573 igb_init_mas(adapter);
2574
673b8b70 2575 /* do hw tstamp init after resetting */
7ebae817 2576 igb_ptp_init(adapter);
673b8b70 2577
9d5c8243 2578 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2579 /* print bus type/speed/width info, not applicable to i354 */
2580 if (hw->mac.type != e1000_i354) {
2581 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2582 netdev->name,
2583 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2584 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2585 "unknown"),
2586 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2587 "Width x4" :
2588 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2589 "Width x2" :
2590 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2591 "Width x1" : "unknown"), netdev->dev_addr);
2592 }
9d5c8243 2593
53ea6c7e
TF		 2594 if ((hw->mac.type >= e1000_i210 ||
2595 igb_get_flash_presence_i210(hw))) {
2596 ret_val = igb_read_part_string(hw, part_str,
2597 E1000_PBANUM_LENGTH);
2598 } else {
2599 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2600 }
2601
9835fd73
CW		 2602 if (ret_val)
2603 strcpy(part_str, "Unknown");
2604 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2605 dev_info(&pdev->dev,
2606 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2607 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2608 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2609 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2610 if (hw->phy.media_type == e1000_media_type_copper) {
2611 switch (hw->mac.type) {
2612 case e1000_i350:
2613 case e1000_i210:
2614 case e1000_i211:
2615 /* Enable EEE for internal copper PHY devices */
2616 err = igb_set_eee_i350(hw);
2617 if ((!err) &&
2618 (!hw->dev_spec._82575.eee_disable)) {
2619 adapter->eee_advert =
2620 MDIO_EEE_100TX | MDIO_EEE_1000T;
2621 adapter->flags |= IGB_FLAG_EEE;
2622 }
2623 break;
2624 case e1000_i354:
ceb5f13b 2625 if ((rd32(E1000_CTRL_EXT) &
f4c01e96
CW		 2626 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2627 err = igb_set_eee_i354(hw);
2628 if ((!err) &&
2629 (!hw->dev_spec._82575.eee_disable)) {
2630 adapter->eee_advert =
2631 MDIO_EEE_100TX | MDIO_EEE_1000T;
2632 adapter->flags |= IGB_FLAG_EEE;
2633 }
2634 }
2635 break;
2636 default:
2637 break;
ceb5f13b 2638 }
09b068d4 2639 }
749ab2cd 2640 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2641 return 0;
2642
2643err_register:
2644 igb_release_hw_control(adapter);
441fc6fd 2645 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2646err_eeprom:
2647 if (!igb_check_reset_block(hw))
f5f4cf08 2648 igb_reset_phy(hw);
9d5c8243
AK		 2649
2650 if (hw->flash_address)
2651 iounmap(hw->flash_address);
9d5c8243 2652err_sw_init:
047e0030 2653 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 2654 iounmap(hw->hw_addr);
2655err_ioremap:
2656 free_netdev(netdev);
2657err_alloc_etherdev:
559e9c49 2658 pci_release_selected_regions(pdev,
b980ac18 2659 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2660err_pci_reg:
2661err_dma:
2662 pci_disable_device(pdev);
2663 return err;
2664}
2665
fa44f2f1 2666#ifdef CONFIG_PCI_IOV
781798a1 2667static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2668{
2669 struct net_device *netdev = pci_get_drvdata(pdev);
2670 struct igb_adapter *adapter = netdev_priv(netdev);
2671 struct e1000_hw *hw = &adapter->hw;
2672
2673 /* reclaim resources allocated to VFs */
2674 if (adapter->vf_data) {
2675 /* disable iov and allow time for transactions to clear */
b09186d2 2676 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2677 dev_warn(&pdev->dev,
2678 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2679 return -EPERM;
2680 } else {
2681 pci_disable_sriov(pdev);
2682 msleep(500);
2683 }
2684
2685 kfree(adapter->vf_data);
2686 adapter->vf_data = NULL;
2687 adapter->vfs_allocated_count = 0;
2688 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2689 wrfl();
2690 msleep(100);
2691 dev_info(&pdev->dev, "IOV Disabled\n");
2692
2693 /* Re-enable DMA Coalescing flag since IOV is turned off */
2694 adapter->flags |= IGB_FLAG_DMAC;
2695 }
2696
2697 return 0;
2698}
2699
2700static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2701{
2702 struct net_device *netdev = pci_get_drvdata(pdev);
2703 struct igb_adapter *adapter = netdev_priv(netdev);
2704 int old_vfs = pci_num_vf(pdev);
2705 int err = 0;
2706 int i;
2707
cd14ef54 2708 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2709 err = -EPERM;
2710 goto out;
2711 }
fa44f2f1
GR		 2712 if (!num_vfs)
2713 goto out;
fa44f2f1 2714
781798a1
SA		 2715 if (old_vfs) {
2716 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2717 old_vfs, max_vfs);
2718 adapter->vfs_allocated_count = old_vfs;
2719 } else
2720 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2721
2722 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2723 sizeof(struct vf_data_storage), GFP_KERNEL);
2724
2725 /* if allocation failed then we do not support SR-IOV */
2726 if (!adapter->vf_data) {
2727 adapter->vfs_allocated_count = 0;
2728 dev_err(&pdev->dev,
2729 "Unable to allocate memory for VF Data Storage\n");
2730 err = -ENOMEM;
2731 goto out;
2732 }
2733
781798a1
SA		 2734 /* only call pci_enable_sriov() if no VFs are allocated already */
2735 if (!old_vfs) {
2736 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2737 if (err)
2738 goto err_out;
2739 }
fa44f2f1
GR		 2740 dev_info(&pdev->dev, "%d VFs allocated\n",
2741 adapter->vfs_allocated_count);
2742 for (i = 0; i < adapter->vfs_allocated_count; i++)
2743 igb_vf_configure(adapter, i);
2744
2745 /* DMA Coalescing is not supported in IOV mode. */
2746 adapter->flags &= ~IGB_FLAG_DMAC;
2747 goto out;
2748
2749err_out:
2750 kfree(adapter->vf_data);
2751 adapter->vf_data = NULL;
2752 adapter->vfs_allocated_count = 0;
2753out:
2754 return err;
2755}
2756
2757#endif
b980ac18 2758/**
441fc6fd
CW		 2759 * igb_remove_i2c - Cleanup I2C interface
2760 * @adapter: pointer to adapter structure
b980ac18 2761 **/
441fc6fd
CW		 2762static void igb_remove_i2c(struct igb_adapter *adapter)
2763{
441fc6fd
CW		 2764 /* free the adapter bus structure */
2765 i2c_del_adapter(&adapter->i2c_adap);
2766}
2767
9d5c8243 2768/**
b980ac18
JK		 2769 * igb_remove - Device Removal Routine
2770 * @pdev: PCI device information struct
9d5c8243 2771 *
b980ac18
JK		 2772 * igb_remove is called by the PCI subsystem to alert the driver
2773 * that it should release a PCI device. The could be caused by a
2774 * Hot-Plug event, or because the driver is going to be removed from
2775 * memory.
9d5c8243 2776 **/
9f9a12f8 2777static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2778{
2779 struct net_device *netdev = pci_get_drvdata(pdev);
2780 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2781 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2782
749ab2cd 2783 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2784#ifdef CONFIG_IGB_HWMON
2785 igb_sysfs_exit(adapter);
2786#endif
441fc6fd 2787 igb_remove_i2c(adapter);
a79f4f88 2788 igb_ptp_stop(adapter);
b980ac18 2789 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2790 * disable watchdog from being rescheduled.
2791 */
9d5c8243
AK		 2792 set_bit(__IGB_DOWN, &adapter->state);
2793 del_timer_sync(&adapter->watchdog_timer);
2794 del_timer_sync(&adapter->phy_info_timer);
2795
760141a5
TH		 2796 cancel_work_sync(&adapter->reset_task);
2797 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2798
421e02f0 2799#ifdef CONFIG_IGB_DCA
7dfc16fa 2800 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2801 dev_info(&pdev->dev, "DCA disabled\n");
2802 dca_remove_requester(&pdev->dev);
7dfc16fa 2803 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2804 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2805 }
2806#endif
2807
9d5c8243 2808 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2809 * would have already happened in close and is redundant.
2810 */
9d5c8243
AK		 2811 igb_release_hw_control(adapter);
2812
2813 unregister_netdev(netdev);
2814
047e0030 2815 igb_clear_interrupt_scheme(adapter);
9d5c8243 2816
37680117 2817#ifdef CONFIG_PCI_IOV
fa44f2f1 2818 igb_disable_sriov(pdev);
37680117 2819#endif
559e9c49 2820
28b0759c
AD		 2821 iounmap(hw->hw_addr);
2822 if (hw->flash_address)
2823 iounmap(hw->flash_address);
559e9c49 2824 pci_release_selected_regions(pdev,
b980ac18 2825 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2826
1128c756 2827 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2828 free_netdev(netdev);
2829
19d5afd4 2830 pci_disable_pcie_error_reporting(pdev);
40a914fa 2831
9d5c8243
AK		 2832 pci_disable_device(pdev);
2833}
2834
a6b623e0 2835/**
b980ac18
JK		 2836 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2837 * @adapter: board private structure to initialize
a6b623e0 2838 *
b980ac18
JK		 2839 * This function initializes the vf specific data storage and then attempts to
2840 * allocate the VFs. The reason for ordering it this way is because it is much
2841 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2842 * the memory for the VFs.
a6b623e0 2843 **/
9f9a12f8 2844static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2845{
2846#ifdef CONFIG_PCI_IOV
2847 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2848 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2849
f96a8a0b
CW		 2850 /* Virtualization features not supported on i210 family. */
2851 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2852 return;
2853
fa44f2f1 2854 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2855 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2856
a6b623e0
AD		 2857#endif /* CONFIG_PCI_IOV */
2858}
2859
fa44f2f1 2860static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2861{
2862 struct e1000_hw *hw = &adapter->hw;
374a542d 2863 u32 max_rss_queues;
9d5c8243 2864
374a542d 2865 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2866 switch (hw->mac.type) {
374a542d
MV		 2867 case e1000_i211:
2868 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2869 break;
2870 case e1000_82575:
f96a8a0b 2871 case e1000_i210:
374a542d
MV		 2872 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2873 break;
2874 case e1000_i350:
2875 /* I350 cannot do RSS and SR-IOV at the same time */
2876 if (!!adapter->vfs_allocated_count) {
2877 max_rss_queues = 1;
2878 break;
2879 }
2880 /* fall through */
2881 case e1000_82576:
2882 if (!!adapter->vfs_allocated_count) {
2883 max_rss_queues = 2;
2884 break;
2885 }
2886 /* fall through */
2887 case e1000_82580:
ceb5f13b 2888 case e1000_i354:
374a542d
MV		 2889 default:
2890 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2891 break;
374a542d
MV		 2892 }
2893
2894 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2895
2896 /* Determine if we need to pair queues. */
2897 switch (hw->mac.type) {
2898 case e1000_82575:
f96a8a0b 2899 case e1000_i211:
374a542d 2900 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2901 break;
374a542d 2902 case e1000_82576:
b980ac18 2903 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2904 * should pair the queues in order to conserve interrupts due
2905 * to limited supply.
2906 */
2907 if ((adapter->rss_queues > 1) &&
2908 (adapter->vfs_allocated_count > 6))
2909 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2910 /* fall through */
2911 case e1000_82580:
2912 case e1000_i350:
ceb5f13b 2913 case e1000_i354:
374a542d 2914 case e1000_i210:
f96a8a0b 2915 default:
b980ac18 2916 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2917 * order to conserve interrupts due to limited supply.
2918 */
2919 if (adapter->rss_queues > (max_rss_queues / 2))
2920 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2921 break;
2922 }
fa44f2f1
GR		 2923}
2924
2925/**
b980ac18
JK		 2926 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2927 * @adapter: board private structure to initialize
fa44f2f1 2928 *
b980ac18
JK		 2929 * igb_sw_init initializes the Adapter private data structure.
2930 * Fields are initialized based on PCI device information and
2931 * OS network device settings (MTU size).
fa44f2f1
GR		 2932 **/
2933static int igb_sw_init(struct igb_adapter *adapter)
2934{
2935 struct e1000_hw *hw = &adapter->hw;
2936 struct net_device *netdev = adapter->netdev;
2937 struct pci_dev *pdev = adapter->pdev;
2938
2939 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2940
2941 /* set default ring sizes */
2942 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2943 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2944
2945 /* set default ITR values */
2946 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2947 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2948
2949 /* set default work limits */
2950 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2951
2952 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2953 VLAN_HLEN;
2954 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2955
2956 spin_lock_init(&adapter->stats64_lock);
2957#ifdef CONFIG_PCI_IOV
2958 switch (hw->mac.type) {
2959 case e1000_82576:
2960 case e1000_i350:
2961 if (max_vfs > 7) {
2962 dev_warn(&pdev->dev,
2963 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2964 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2965 } else
2966 adapter->vfs_allocated_count = max_vfs;
2967 if (adapter->vfs_allocated_count)
2968 dev_warn(&pdev->dev,
2969 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2970 break;
2971 default:
2972 break;
2973 }
2974#endif /* CONFIG_PCI_IOV */
2975
2976 igb_init_queue_configuration(adapter);
a99955fc 2977
1128c756 2978 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2979 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2980 GFP_ATOMIC);
1128c756 2981
a6b623e0 2982 /* This call may decrease the number of queues */
53c7d064 2983 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2984 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2985 return -ENOMEM;
2986 }
2987
a6b623e0
AD		 2988 igb_probe_vfs(adapter);
2989
9d5c8243
AK		 2990 /* Explicitly disable IRQ since the NIC can be in any state. */
2991 igb_irq_disable(adapter);
2992
f96a8a0b 2993 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2994 adapter->flags &= ~IGB_FLAG_DMAC;
2995
9d5c8243
AK		 2996 set_bit(__IGB_DOWN, &adapter->state);
2997 return 0;
2998}
2999
3000/**
b980ac18
JK		 3001 * igb_open - Called when a network interface is made active
3002 * @netdev: network interface device structure
9d5c8243 3003 *
b980ac18 3004 * Returns 0 on success, negative value on failure
9d5c8243 3005 *
b980ac18
JK		 3006 * The open entry point is called when a network interface is made
3007 * active by the system (IFF_UP). At this point all resources needed
3008 * for transmit and receive operations are allocated, the interrupt
3009 * handler is registered with the OS, the watchdog timer is started,
3010 * and the stack is notified that the interface is ready.
9d5c8243 3011 **/
749ab2cd 3012static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3013{
3014 struct igb_adapter *adapter = netdev_priv(netdev);
3015 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3016 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3017 int err;
3018 int i;
3019
3020 /* disallow open during test */
749ab2cd
YZ		 3021 if (test_bit(__IGB_TESTING, &adapter->state)) {
3022 WARN_ON(resuming);
9d5c8243 3023 return -EBUSY;
749ab2cd
YZ		 3024 }
3025
3026 if (!resuming)
3027 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3028
b168dfc5
JB		 3029 netif_carrier_off(netdev);
3030
9d5c8243
AK		 3031 /* allocate transmit descriptors */
3032 err = igb_setup_all_tx_resources(adapter);
3033 if (err)
3034 goto err_setup_tx;
3035
3036 /* allocate receive descriptors */
3037 err = igb_setup_all_rx_resources(adapter);
3038 if (err)
3039 goto err_setup_rx;
3040
88a268c1 3041 igb_power_up_link(adapter);
9d5c8243 3042
9d5c8243
AK		 3043 /* before we allocate an interrupt, we must be ready to handle it.
3044 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3045 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3046 * clean_rx handler before we do so.
3047 */
9d5c8243
AK		 3048 igb_configure(adapter);
3049
3050 err = igb_request_irq(adapter);
3051 if (err)
3052 goto err_req_irq;
3053
0c2cc02e
AD		 3054 /* Notify the stack of the actual queue counts. */
3055 err = netif_set_real_num_tx_queues(adapter->netdev,
3056 adapter->num_tx_queues);
3057 if (err)
3058 goto err_set_queues;
3059
3060 err = netif_set_real_num_rx_queues(adapter->netdev,
3061 adapter->num_rx_queues);
3062 if (err)
3063 goto err_set_queues;
3064
9d5c8243
AK		 3065 /* From here on the code is the same as igb_up() */
3066 clear_bit(__IGB_DOWN, &adapter->state);
3067
0d1ae7f4
AD		 3068 for (i = 0; i < adapter->num_q_vectors; i++)
3069 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3070
3071 /* Clear any pending interrupts. */
3072 rd32(E1000_ICR);
844290e5
PW		 3073
3074 igb_irq_enable(adapter);
3075
d4960307
AD		 3076 /* notify VFs that reset has been completed */
3077 if (adapter->vfs_allocated_count) {
3078 u32 reg_data = rd32(E1000_CTRL_EXT);
3079 reg_data |= E1000_CTRL_EXT_PFRSTD;
3080 wr32(E1000_CTRL_EXT, reg_data);
3081 }
3082
d55b53ff
JK		 3083 netif_tx_start_all_queues(netdev);
3084
749ab2cd
YZ		 3085 if (!resuming)
3086 pm_runtime_put(&pdev->dev);
3087
25568a53
AD		 3088 /* start the watchdog. */
3089 hw->mac.get_link_status = 1;
3090 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3091
3092 return 0;
3093
0c2cc02e
AD		 3094err_set_queues:
3095 igb_free_irq(adapter);
9d5c8243
AK		 3096err_req_irq:
3097 igb_release_hw_control(adapter);
88a268c1 3098 igb_power_down_link(adapter);
9d5c8243
AK		 3099 igb_free_all_rx_resources(adapter);
3100err_setup_rx:
3101 igb_free_all_tx_resources(adapter);
3102err_setup_tx:
3103 igb_reset(adapter);
749ab2cd
YZ		 3104 if (!resuming)
3105 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3106
3107 return err;
3108}
3109
749ab2cd
YZ		 3110static int igb_open(struct net_device *netdev)
3111{
3112 return __igb_open(netdev, false);
3113}
3114
9d5c8243 3115/**
b980ac18
JK		 3116 * igb_close - Disables a network interface
3117 * @netdev: network interface device structure
9d5c8243 3118 *
b980ac18 3119 * Returns 0, this is not allowed to fail
9d5c8243 3120 *
b980ac18
JK		 3121 * The close entry point is called when an interface is de-activated
3122 * by the OS. The hardware is still under the driver's control, but
3123 * needs to be disabled. A global MAC reset is issued to stop the
3124 * hardware, and all transmit and receive resources are freed.
9d5c8243 3125 **/
749ab2cd 3126static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3127{
3128 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3129 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3130
3131 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3132
749ab2cd
YZ		 3133 if (!suspending)
3134 pm_runtime_get_sync(&pdev->dev);
3135
3136 igb_down(adapter);
9d5c8243
AK		 3137 igb_free_irq(adapter);
3138
3139 igb_free_all_tx_resources(adapter);
3140 igb_free_all_rx_resources(adapter);
3141
749ab2cd
YZ		 3142 if (!suspending)
3143 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3144 return 0;
3145}
3146
749ab2cd
YZ		 3147static int igb_close(struct net_device *netdev)
3148{
3149 return __igb_close(netdev, false);
3150}
3151
9d5c8243 3152/**
b980ac18
JK		 3153 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3154 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3155 *
b980ac18 3156 * Return 0 on success, negative on failure
9d5c8243 3157 **/
80785298 3158int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3159{
59d71989 3160 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3161 int size;
3162
06034649 3163 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3164
3165 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3166 if (!tx_ring->tx_buffer_info)
9d5c8243 3167 goto err;
9d5c8243
AK		 3168
3169 /* round up to nearest 4K */
85e8d004 3170 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3171 tx_ring->size = ALIGN(tx_ring->size, 4096);
3172
5536d210
AD		 3173 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3174 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3175 if (!tx_ring->desc)
3176 goto err;
3177
9d5c8243
AK		 3178 tx_ring->next_to_use = 0;
3179 tx_ring->next_to_clean = 0;
81c2fc22 3180
9d5c8243
AK		 3181 return 0;
3182
3183err:
06034649 3184 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3185 tx_ring->tx_buffer_info = NULL;
3186 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3187 return -ENOMEM;
3188}
3189
3190/**
b980ac18
JK		 3191 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3192 * (Descriptors) for all queues
3193 * @adapter: board private structure
9d5c8243 3194 *
b980ac18 3195 * Return 0 on success, negative on failure
9d5c8243
AK		 3196 **/
3197static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3198{
439705e1 3199 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3200 int i, err = 0;
3201
3202 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3203 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3204 if (err) {
439705e1 3205 dev_err(&pdev->dev,
9d5c8243
AK		 3206 "Allocation for Tx Queue %u failed\n", i);
3207 for (i--; i >= 0; i--)
3025a446 3208 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3209 break;
3210 }
3211 }
3212
3213 return err;
3214}
3215
3216/**
b980ac18
JK		 3217 * igb_setup_tctl - configure the transmit control registers
3218 * @adapter: Board private structure
9d5c8243 3219 **/
d7ee5b3a 3220void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3221{
9d5c8243
AK		 3222 struct e1000_hw *hw = &adapter->hw;
3223 u32 tctl;
9d5c8243 3224
85b430b4
AD		 3225 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3226 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3227
3228 /* Program the Transmit Control Register */
9d5c8243
AK		 3229 tctl = rd32(E1000_TCTL);
3230 tctl &= ~E1000_TCTL_CT;
3231 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3232 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3233
3234 igb_config_collision_dist(hw);
3235
9d5c8243
AK		 3236 /* Enable transmits */
3237 tctl |= E1000_TCTL_EN;
3238
3239 wr32(E1000_TCTL, tctl);
3240}
3241
85b430b4 3242/**
b980ac18
JK		 3243 * igb_configure_tx_ring - Configure transmit ring after Reset
3244 * @adapter: board private structure
3245 * @ring: tx ring to configure
85b430b4 3246 *
b980ac18 3247 * Configure a transmit ring after a reset.
85b430b4 3248 **/
d7ee5b3a
AD		 3249void igb_configure_tx_ring(struct igb_adapter *adapter,
3250 struct igb_ring *ring)
85b430b4
AD		 3251{
3252 struct e1000_hw *hw = &adapter->hw;
a74420e0 3253 u32 txdctl = 0;
85b430b4
AD		 3254 u64 tdba = ring->dma;
3255 int reg_idx = ring->reg_idx;
3256
3257 /* disable the queue */
a74420e0 3258 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3259 wrfl();
3260 mdelay(10);
3261
3262 wr32(E1000_TDLEN(reg_idx),
b980ac18 3263 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3264 wr32(E1000_TDBAL(reg_idx),
b980ac18 3265 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3266 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3267
fce99e34 3268 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3269 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3270 writel(0, ring->tail);
85b430b4
AD		 3271
3272 txdctl |= IGB_TX_PTHRESH;
3273 txdctl |= IGB_TX_HTHRESH << 8;
3274 txdctl |= IGB_TX_WTHRESH << 16;
3275
3276 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3277 wr32(E1000_TXDCTL(reg_idx), txdctl);
3278}
3279
3280/**
b980ac18
JK		 3281 * igb_configure_tx - Configure transmit Unit after Reset
3282 * @adapter: board private structure
85b430b4 3283 *
b980ac18 3284 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3285 **/
3286static void igb_configure_tx(struct igb_adapter *adapter)
3287{
3288 int i;
3289
3290 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3291 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3292}
3293
9d5c8243 3294/**
b980ac18
JK		 3295 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3296 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3297 *
b980ac18 3298 * Returns 0 on success, negative on failure
9d5c8243 3299 **/
80785298 3300int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3301{
59d71989 3302 struct device *dev = rx_ring->dev;
f33005a6 3303 int size;
9d5c8243 3304
06034649 3305 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3306
3307 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3308 if (!rx_ring->rx_buffer_info)
9d5c8243 3309 goto err;
9d5c8243 3310
9d5c8243 3311 /* Round up to nearest 4K */
f33005a6 3312 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3313 rx_ring->size = ALIGN(rx_ring->size, 4096);
3314
5536d210
AD		 3315 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3316 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3317 if (!rx_ring->desc)
3318 goto err;
3319
cbc8e55f 3320 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3321 rx_ring->next_to_clean = 0;
3322 rx_ring->next_to_use = 0;
9d5c8243 3323
9d5c8243
AK		 3324 return 0;
3325
3326err:
06034649
AD		 3327 vfree(rx_ring->rx_buffer_info);
3328 rx_ring->rx_buffer_info = NULL;
f33005a6 3329 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3330 return -ENOMEM;
3331}
3332
3333/**
b980ac18
JK		 3334 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3335 * (Descriptors) for all queues
3336 * @adapter: board private structure
9d5c8243 3337 *
b980ac18 3338 * Return 0 on success, negative on failure
9d5c8243
AK		 3339 **/
3340static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3341{
439705e1 3342 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3343 int i, err = 0;
3344
3345 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3346 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3347 if (err) {
439705e1 3348 dev_err(&pdev->dev,
9d5c8243
AK		 3349 "Allocation for Rx Queue %u failed\n", i);
3350 for (i--; i >= 0; i--)
3025a446 3351 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3352 break;
3353 }
3354 }
3355
3356 return err;
3357}
3358
06cf2666 3359/**
b980ac18
JK		 3360 * igb_setup_mrqc - configure the multiple receive queue control registers
3361 * @adapter: Board private structure
06cf2666
AD		 3362 **/
3363static void igb_setup_mrqc(struct igb_adapter *adapter)
3364{
3365 struct e1000_hw *hw = &adapter->hw;
3366 u32 mrqc, rxcsum;
ed12cc9a 3367 u32 j, num_rx_queues;
a57fe23e
AD		 3368 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3369 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3370 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3371 0xFA01ACBE };
06cf2666
AD		 3372
3373 /* Fill out hash function seeds */
a57fe23e
AD		 3374 for (j = 0; j < 10; j++)
3375 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3376
a99955fc 3377 num_rx_queues = adapter->rss_queues;
06cf2666 3378
797fd4be 3379 switch (hw->mac.type) {
797fd4be
AD		 3380 case e1000_82576:
3381 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3382 if (adapter->vfs_allocated_count)
06cf2666 3383 num_rx_queues = 2;
797fd4be
AD		 3384 break;
3385 default:
3386 break;
06cf2666
AD		 3387 }
3388
ed12cc9a
LMV		 3389 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3390 for (j = 0; j < IGB_RETA_SIZE; j++)
3391 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3392 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3393 }
ed12cc9a 3394 igb_write_rss_indir_tbl(adapter);
06cf2666 3395
b980ac18 3396 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3397 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3398 * offloads as they are enabled by default
3399 */
3400 rxcsum = rd32(E1000_RXCSUM);
3401 rxcsum |= E1000_RXCSUM_PCSD;
3402
3403 if (adapter->hw.mac.type >= e1000_82576)
3404 /* Enable Receive Checksum Offload for SCTP */
3405 rxcsum |= E1000_RXCSUM_CRCOFL;
3406
3407 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3408 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3409
039454a8
AA		 3410 /* Generate RSS hash based on packet types, TCP/UDP
3411 * port numbers and/or IPv4/v6 src and dst addresses
3412 */
f96a8a0b
CW		 3413 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3414 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3415 E1000_MRQC_RSS_FIELD_IPV6 |
3416 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3417 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3418
039454a8
AA		 3419 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3420 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3421 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3422 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3423
06cf2666
AD		 3424 /* If VMDq is enabled then we set the appropriate mode for that, else
3425 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3426 * if we are only using one queue
3427 */
06cf2666
AD		 3428 if (adapter->vfs_allocated_count) {
3429 if (hw->mac.type > e1000_82575) {
3430 /* Set the default pool for the PF's first queue */
3431 u32 vtctl = rd32(E1000_VT_CTL);
3432 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3433 E1000_VT_CTL_DISABLE_DEF_POOL);
3434 vtctl |= adapter->vfs_allocated_count <<
3435 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3436 wr32(E1000_VT_CTL, vtctl);
3437 }
a99955fc 3438 if (adapter->rss_queues > 1)
f96a8a0b 3439 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3440 else
f96a8a0b 3441 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3442 } else {
f96a8a0b
CW		 3443 if (hw->mac.type != e1000_i211)
3444 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3445 }
3446 igb_vmm_control(adapter);
3447
06cf2666
AD		 3448 wr32(E1000_MRQC, mrqc);
3449}
3450
9d5c8243 3451/**
b980ac18
JK		 3452 * igb_setup_rctl - configure the receive control registers
3453 * @adapter: Board private structure
9d5c8243 3454 **/
d7ee5b3a 3455void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3456{
3457 struct e1000_hw *hw = &adapter->hw;
3458 u32 rctl;
9d5c8243
AK		 3459
3460 rctl = rd32(E1000_RCTL);
3461
3462 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3463 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3464
69d728ba 3465 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3466 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3467
b980ac18 3468 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3469 * redirection as it did with e1000. Newer features require
3470 * that the HW strips the CRC.
73cd78f1 3471 */
87cb7e8c 3472 rctl |= E1000_RCTL_SECRC;
9d5c8243 3473
559e9c49 3474 /* disable store bad packets and clear size bits. */
ec54d7d6 3475 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3476
6ec43fe6
AD		 3477 /* enable LPE to prevent packets larger than max_frame_size */
3478 rctl |= E1000_RCTL_LPE;
9d5c8243 3479
952f72a8
AD		 3480 /* disable queue 0 to prevent tail write w/o re-config */
3481 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3482
e1739522
AD		 3483 /* Attention!!! For SR-IOV PF driver operations you must enable
3484 * queue drop for all VF and PF queues to prevent head of line blocking
3485 * if an un-trusted VF does not provide descriptors to hardware.
3486 */
3487 if (adapter->vfs_allocated_count) {
e1739522
AD		 3488 /* set all queue drop enable bits */
3489 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3490 }
3491
89eaefb6
BG		 3492 /* This is useful for sniffing bad packets. */
3493 if (adapter->netdev->features & NETIF_F_RXALL) {
3494 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3495 * in e1000e_set_rx_mode
3496 */
89eaefb6
BG		 3497 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3498 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3499 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3500
3501 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3502 E1000_RCTL_DPF | /* Allow filtered pause */
3503 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3504 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3505 * and that breaks VLANs.
3506 */
3507 }
3508
9d5c8243
AK		 3509 wr32(E1000_RCTL, rctl);
3510}
3511
7d5753f0
AD		 3512static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3513 int vfn)
3514{
3515 struct e1000_hw *hw = &adapter->hw;
3516 u32 vmolr;
3517
3518 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3519 * increase the size to support vlan tags
3520 */
7d5753f0
AD		 3521 if (vfn < adapter->vfs_allocated_count &&
3522 adapter->vf_data[vfn].vlans_enabled)
3523 size += VLAN_TAG_SIZE;
3524
3525 vmolr = rd32(E1000_VMOLR(vfn));
3526 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3527 vmolr |= size | E1000_VMOLR_LPE;
3528 wr32(E1000_VMOLR(vfn), vmolr);
3529
3530 return 0;
3531}
3532
e1739522 3533/**
b980ac18
JK		 3534 * igb_rlpml_set - set maximum receive packet size
3535 * @adapter: board private structure
e1739522 3536 *
b980ac18 3537 * Configure maximum receivable packet size.
e1739522
AD		 3538 **/
3539static void igb_rlpml_set(struct igb_adapter *adapter)
3540{
153285f9 3541 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3542 struct e1000_hw *hw = &adapter->hw;
3543 u16 pf_id = adapter->vfs_allocated_count;
3544
e1739522
AD		 3545 if (pf_id) {
3546 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3547 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3548 * to our max jumbo frame size, in case we need to enable
3549 * jumbo frames on one of the rings later.
3550 * This will not pass over-length frames into the default
3551 * queue because it's gated by the VMOLR.RLPML.
3552 */
7d5753f0 3553 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3554 }
3555
3556 wr32(E1000_RLPML, max_frame_size);
3557}
3558
8151d294
WM		 3559static inline void igb_set_vmolr(struct igb_adapter *adapter,
3560 int vfn, bool aupe)
7d5753f0
AD		 3561{
3562 struct e1000_hw *hw = &adapter->hw;
3563 u32 vmolr;
3564
b980ac18 3565 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3566 * we should exit and do nothing
3567 */
3568 if (hw->mac.type < e1000_82576)
3569 return;
3570
3571 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3572 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3573 if (hw->mac.type == e1000_i350) {
3574 u32 dvmolr;
3575
3576 dvmolr = rd32(E1000_DVMOLR(vfn));
3577 dvmolr |= E1000_DVMOLR_STRVLAN;
3578 wr32(E1000_DVMOLR(vfn), dvmolr);
3579 }
8151d294 3580 if (aupe)
b980ac18 3581 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3582 else
3583 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3584
3585 /* clear all bits that might not be set */
3586 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3587
a99955fc 3588 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3589 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3590 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3591 * multicast packets
3592 */
3593 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3594 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3595
3596 wr32(E1000_VMOLR(vfn), vmolr);
3597}
3598
85b430b4 3599/**
b980ac18
JK		 3600 * igb_configure_rx_ring - Configure a receive ring after Reset
3601 * @adapter: board private structure
3602 * @ring: receive ring to be configured
85b430b4 3603 *
b980ac18 3604 * Configure the Rx unit of the MAC after a reset.
85b430b4 3605 **/
d7ee5b3a 3606void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3607 struct igb_ring *ring)
85b430b4
AD		 3608{
3609 struct e1000_hw *hw = &adapter->hw;
3610 u64 rdba = ring->dma;
3611 int reg_idx = ring->reg_idx;
a74420e0 3612 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3613
3614 /* disable the queue */
a74420e0 3615 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3616
3617 /* Set DMA base address registers */
3618 wr32(E1000_RDBAL(reg_idx),
3619 rdba & 0x00000000ffffffffULL);
3620 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3621 wr32(E1000_RDLEN(reg_idx),
b980ac18 3622 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3623
3624 /* initialize head and tail */
fce99e34 3625 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3626 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3627 writel(0, ring->tail);
85b430b4 3628
952f72a8 3629 /* set descriptor configuration */
44390ca6 3630 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3631 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3632 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3633 if (hw->mac.type >= e1000_82580)
757b77e2 3634 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3635 /* Only set Drop Enable if we are supporting multiple queues */
3636 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3637 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3638
3639 wr32(E1000_SRRCTL(reg_idx), srrctl);
3640
7d5753f0 3641 /* set filtering for VMDQ pools */
8151d294 3642 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3643
85b430b4
AD		 3644 rxdctl |= IGB_RX_PTHRESH;
3645 rxdctl |= IGB_RX_HTHRESH << 8;
3646 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3647
3648 /* enable receive descriptor fetching */
3649 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3650 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3651}
3652
9d5c8243 3653/**
b980ac18
JK		 3654 * igb_configure_rx - Configure receive Unit after Reset
3655 * @adapter: board private structure
9d5c8243 3656 *
b980ac18 3657 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3658 **/
3659static void igb_configure_rx(struct igb_adapter *adapter)
3660{
9107584e 3661 int i;
9d5c8243 3662
68d480c4
AD		 3663 /* set UTA to appropriate mode */
3664 igb_set_uta(adapter);
3665
26ad9178
AD		 3666 /* set the correct pool for the PF default MAC address in entry 0 */
3667 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3668 adapter->vfs_allocated_count);
26ad9178 3669
06cf2666 3670 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3671 * the Base and Length of the Rx Descriptor Ring
3672 */
f9d40f6a
AD		 3673 for (i = 0; i < adapter->num_rx_queues; i++)
3674 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3675}
3676
3677/**
b980ac18
JK		 3678 * igb_free_tx_resources - Free Tx Resources per Queue
3679 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3680 *
b980ac18 3681 * Free all transmit software resources
9d5c8243 3682 **/
68fd9910 3683void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3684{
3b644cf6 3685 igb_clean_tx_ring(tx_ring);
9d5c8243 3686
06034649
AD		 3687 vfree(tx_ring->tx_buffer_info);
3688 tx_ring->tx_buffer_info = NULL;
9d5c8243 3689
439705e1
AD		 3690 /* if not set, then don't free */
3691 if (!tx_ring->desc)
3692 return;
3693
59d71989
AD		 3694 dma_free_coherent(tx_ring->dev, tx_ring->size,
3695 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3696
3697 tx_ring->desc = NULL;
3698}
3699
3700/**
b980ac18
JK		 3701 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3702 * @adapter: board private structure
9d5c8243 3703 *
b980ac18 3704 * Free all transmit software resources
9d5c8243
AK		 3705 **/
3706static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3707{
3708 int i;
3709
3710 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3711 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3712}
3713
ebe42d16
AD		 3714void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3715 struct igb_tx_buffer *tx_buffer)
3716{
3717 if (tx_buffer->skb) {
3718 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3719 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3720 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3721 dma_unmap_addr(tx_buffer, dma),
3722 dma_unmap_len(tx_buffer, len),
ebe42d16 3723 DMA_TO_DEVICE);
c9f14bf3 3724 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3725 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3726 dma_unmap_addr(tx_buffer, dma),
3727 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3728 DMA_TO_DEVICE);
3729 }
3730 tx_buffer->next_to_watch = NULL;
3731 tx_buffer->skb = NULL;
c9f14bf3 3732 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3733 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3734}
3735
3736/**
b980ac18
JK		 3737 * igb_clean_tx_ring - Free Tx Buffers
3738 * @tx_ring: ring to be cleaned
9d5c8243 3739 **/
3b644cf6 3740static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3741{
06034649 3742 struct igb_tx_buffer *buffer_info;
9d5c8243 3743 unsigned long size;
6ad4edfc 3744 u16 i;
9d5c8243 3745
06034649 3746 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3747 return;
3748 /* Free all the Tx ring sk_buffs */
3749
3750 for (i = 0; i < tx_ring->count; i++) {
06034649 3751 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3752 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3753 }
3754
dad8a3b3
JF		 3755 netdev_tx_reset_queue(txring_txq(tx_ring));
3756
06034649
AD		 3757 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3758 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3759
3760 /* Zero out the descriptor ring */
9d5c8243
AK		 3761 memset(tx_ring->desc, 0, tx_ring->size);
3762
3763 tx_ring->next_to_use = 0;
3764 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3765}
3766
3767/**
b980ac18
JK		 3768 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3769 * @adapter: board private structure
9d5c8243
AK		 3770 **/
3771static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3772{
3773 int i;
3774
3775 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3776 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3777}
3778
3779/**
b980ac18
JK		 3780 * igb_free_rx_resources - Free Rx Resources
3781 * @rx_ring: ring to clean the resources from
9d5c8243 3782 *
b980ac18 3783 * Free all receive software resources
9d5c8243 3784 **/
68fd9910 3785void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3786{
3b644cf6 3787 igb_clean_rx_ring(rx_ring);
9d5c8243 3788
06034649
AD		 3789 vfree(rx_ring->rx_buffer_info);
3790 rx_ring->rx_buffer_info = NULL;
9d5c8243 3791
439705e1
AD		 3792 /* if not set, then don't free */
3793 if (!rx_ring->desc)
3794 return;
3795
59d71989
AD		 3796 dma_free_coherent(rx_ring->dev, rx_ring->size,
3797 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3798
3799 rx_ring->desc = NULL;
3800}
3801
3802/**
b980ac18
JK		 3803 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3804 * @adapter: board private structure
9d5c8243 3805 *
b980ac18 3806 * Free all receive software resources
9d5c8243
AK		 3807 **/
3808static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3809{
3810 int i;
3811
3812 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3813 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3814}
3815
3816/**
b980ac18
JK		 3817 * igb_clean_rx_ring - Free Rx Buffers per Queue
3818 * @rx_ring: ring to free buffers from
9d5c8243 3819 **/
3b644cf6 3820static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3821{
9d5c8243 3822 unsigned long size;
c023cd88 3823 u16 i;
9d5c8243 3824
1a1c225b
AD		 3825 if (rx_ring->skb)
3826 dev_kfree_skb(rx_ring->skb);
3827 rx_ring->skb = NULL;
3828
06034649 3829 if (!rx_ring->rx_buffer_info)
9d5c8243 3830 return;
439705e1 3831
9d5c8243
AK		 3832 /* Free all the Rx ring sk_buffs */
3833 for (i = 0; i < rx_ring->count; i++) {
06034649 3834 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3835
cbc8e55f
AD		 3836 if (!buffer_info->page)
3837 continue;
3838
3839 dma_unmap_page(rx_ring->dev,
3840 buffer_info->dma,
3841 PAGE_SIZE,
3842 DMA_FROM_DEVICE);
3843 __free_page(buffer_info->page);
3844
1a1c225b 3845 buffer_info->page = NULL;
9d5c8243
AK		 3846 }
3847
06034649
AD		 3848 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3849 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3850
3851 /* Zero out the descriptor ring */
3852 memset(rx_ring->desc, 0, rx_ring->size);
3853
cbc8e55f 3854 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3855 rx_ring->next_to_clean = 0;
3856 rx_ring->next_to_use = 0;
9d5c8243
AK		 3857}
3858
3859/**
b980ac18
JK		 3860 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3861 * @adapter: board private structure
9d5c8243
AK		 3862 **/
3863static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3864{
3865 int i;
3866
3867 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3868 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3869}
3870
3871/**
b980ac18
JK		 3872 * igb_set_mac - Change the Ethernet Address of the NIC
3873 * @netdev: network interface device structure
3874 * @p: pointer to an address structure
9d5c8243 3875 *
b980ac18 3876 * Returns 0 on success, negative on failure
9d5c8243
AK		 3877 **/
3878static int igb_set_mac(struct net_device *netdev, void *p)
3879{
3880 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3881 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3882 struct sockaddr *addr = p;
3883
3884 if (!is_valid_ether_addr(addr->sa_data))
3885 return -EADDRNOTAVAIL;
3886
3887 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3888 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3889
26ad9178
AD		 3890 /* set the correct pool for the new PF MAC address in entry 0 */
3891 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3892 adapter->vfs_allocated_count);
e1739522 3893
9d5c8243
AK		 3894 return 0;
3895}
3896
3897/**
b980ac18
JK		 3898 * igb_write_mc_addr_list - write multicast addresses to MTA
3899 * @netdev: network interface device structure
9d5c8243 3900 *
b980ac18
JK		 3901 * Writes multicast address list to the MTA hash table.
3902 * Returns: -ENOMEM on failure
3903 * 0 on no addresses written
3904 * X on writing X addresses to MTA
9d5c8243 3905 **/
68d480c4 3906static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3907{
3908 struct igb_adapter *adapter = netdev_priv(netdev);
3909 struct e1000_hw *hw = &adapter->hw;
22bedad3 3910 struct netdev_hw_addr *ha;
68d480c4 3911 u8 *mta_list;
9d5c8243
AK		 3912 int i;
3913
4cd24eaf 3914 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3915 /* nothing to program, so clear mc list */
3916 igb_update_mc_addr_list(hw, NULL, 0);
3917 igb_restore_vf_multicasts(adapter);
3918 return 0;
3919 }
9d5c8243 3920
4cd24eaf 3921 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3922 if (!mta_list)
3923 return -ENOMEM;
ff41f8dc 3924
68d480c4 3925 /* The shared function expects a packed array of only addresses. */
48e2f183 3926 i = 0;
22bedad3
JP		 3927 netdev_for_each_mc_addr(ha, netdev)
3928 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3929
68d480c4
AD		 3930 igb_update_mc_addr_list(hw, mta_list, i);
3931 kfree(mta_list);
3932
4cd24eaf 3933 return netdev_mc_count(netdev);
68d480c4
AD		 3934}
3935
3936/**
b980ac18
JK		 3937 * igb_write_uc_addr_list - write unicast addresses to RAR table
3938 * @netdev: network interface device structure
68d480c4 3939 *
b980ac18
JK		 3940 * Writes unicast address list to the RAR table.
3941 * Returns: -ENOMEM on failure/insufficient address space
3942 * 0 on no addresses written
3943 * X on writing X addresses to the RAR table
68d480c4
AD		 3944 **/
3945static int igb_write_uc_addr_list(struct net_device *netdev)
3946{
3947 struct igb_adapter *adapter = netdev_priv(netdev);
3948 struct e1000_hw *hw = &adapter->hw;
3949 unsigned int vfn = adapter->vfs_allocated_count;
3950 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3951 int count = 0;
3952
3953 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3954 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3955 return -ENOMEM;
9d5c8243 3956
32e7bfc4 3957 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3958 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3959
3960 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3961 if (!rar_entries)
3962 break;
26ad9178 3963 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3964 rar_entries--,
3965 vfn);
68d480c4 3966 count++;
ff41f8dc
AD		 3967 }
3968 }
3969 /* write the addresses in reverse order to avoid write combining */
3970 for (; rar_entries > 0 ; rar_entries--) {
3971 wr32(E1000_RAH(rar_entries), 0);
3972 wr32(E1000_RAL(rar_entries), 0);
3973 }
3974 wrfl();
3975
68d480c4
AD		 3976 return count;
3977}
3978
3979/**
b980ac18
JK		 3980 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3981 * @netdev: network interface device structure
68d480c4 3982 *
b980ac18
JK		 3983 * The set_rx_mode entry point is called whenever the unicast or multicast
3984 * address lists or the network interface flags are updated. This routine is
3985 * responsible for configuring the hardware for proper unicast, multicast,
3986 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3987 **/
3988static void igb_set_rx_mode(struct net_device *netdev)
3989{
3990 struct igb_adapter *adapter = netdev_priv(netdev);
3991 struct e1000_hw *hw = &adapter->hw;
3992 unsigned int vfn = adapter->vfs_allocated_count;
3993 u32 rctl, vmolr = 0;
3994 int count;
3995
3996 /* Check for Promiscuous and All Multicast modes */
3997 rctl = rd32(E1000_RCTL);
3998
3999 /* clear the effected bits */
4000 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4001
4002 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4003 /* retain VLAN HW filtering if in VT mode */
7e44892c 4004 if (adapter->vfs_allocated_count)
6f3dc319 4005 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4006 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4007 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4008 } else {
4009 if (netdev->flags & IFF_ALLMULTI) {
4010 rctl |= E1000_RCTL_MPE;
4011 vmolr |= E1000_VMOLR_MPME;
4012 } else {
b980ac18 4013 /* Write addresses to the MTA, if the attempt fails
25985edc 4014 * then we should just turn on promiscuous mode so
68d480c4
AD		 4015 * that we can at least receive multicast traffic
4016 */
4017 count = igb_write_mc_addr_list(netdev);
4018 if (count < 0) {
4019 rctl |= E1000_RCTL_MPE;
4020 vmolr |= E1000_VMOLR_MPME;
4021 } else if (count) {
4022 vmolr |= E1000_VMOLR_ROMPE;
4023 }
4024 }
b980ac18 4025 /* Write addresses to available RAR registers, if there is not
68d480c4 4026 * sufficient space to store all the addresses then enable
25985edc 4027 * unicast promiscuous mode
68d480c4
AD		 4028 */
4029 count = igb_write_uc_addr_list(netdev);
4030 if (count < 0) {
4031 rctl |= E1000_RCTL_UPE;
4032 vmolr |= E1000_VMOLR_ROPE;
4033 }
4034 rctl |= E1000_RCTL_VFE;
28fc06f5 4035 }
68d480c4 4036 wr32(E1000_RCTL, rctl);
28fc06f5 4037
b980ac18 4038 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4039 * the VMOLR to enable the appropriate modes. Without this workaround
4040 * we will have issues with VLAN tag stripping not being done for frames
4041 * that are only arriving because we are the default pool
4042 */
f96a8a0b 4043 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4044 return;
9d5c8243 4045
68d480c4 4046 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4047 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4048 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4049 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4050}
4051
13800469
GR		 4052static void igb_check_wvbr(struct igb_adapter *adapter)
4053{
4054 struct e1000_hw *hw = &adapter->hw;
4055 u32 wvbr = 0;
4056
4057 switch (hw->mac.type) {
4058 case e1000_82576:
4059 case e1000_i350:
4060 if (!(wvbr = rd32(E1000_WVBR)))
4061 return;
4062 break;
4063 default:
4064 break;
4065 }
4066
4067 adapter->wvbr |= wvbr;
4068}
4069
4070#define IGB_STAGGERED_QUEUE_OFFSET 8
4071
4072static void igb_spoof_check(struct igb_adapter *adapter)
4073{
4074 int j;
4075
4076 if (!adapter->wvbr)
4077 return;
4078
4079 for(j = 0; j < adapter->vfs_allocated_count; j++) {
4080 if (adapter->wvbr & (1 << j) ||
4081 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4082 dev_warn(&adapter->pdev->dev,
4083 "Spoof event(s) detected on VF %d\n", j);
4084 adapter->wvbr &=
4085 ~((1 << j) |
4086 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4087 }
4088 }
4089}
4090
9d5c8243 4091/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4092 * the phy
4093 */
9d5c8243
AK		 4094static void igb_update_phy_info(unsigned long data)
4095{
4096 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4097 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4098}
4099
4d6b725e 4100/**
b980ac18
JK		 4101 * igb_has_link - check shared code for link and determine up/down
4102 * @adapter: pointer to driver private info
4d6b725e 4103 **/
3145535a 4104bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4105{
4106 struct e1000_hw *hw = &adapter->hw;
4107 bool link_active = false;
4d6b725e
AD		 4108
4109 /* get_link_status is set on LSC (link status) interrupt or
4110 * rx sequence error interrupt. get_link_status will stay
4111 * false until the e1000_check_for_link establishes link
4112 * for copper adapters ONLY
4113 */
4114 switch (hw->phy.media_type) {
4115 case e1000_media_type_copper:
e5c3370f
AA		 4116 if (!hw->mac.get_link_status)
4117 return true;
4d6b725e 4118 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4119 hw->mac.ops.check_for_link(hw);
4120 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4121 break;
4122 default:
4123 case e1000_media_type_unknown:
4124 break;
4125 }
4126
aa9b8cc4
AA		 4127 if (((hw->mac.type == e1000_i210) ||
4128 (hw->mac.type == e1000_i211)) &&
4129 (hw->phy.id == I210_I_PHY_ID)) {
4130 if (!netif_carrier_ok(adapter->netdev)) {
4131 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4132 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4133 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4134 adapter->link_check_timeout = jiffies;
4135 }
4136 }
4137
4d6b725e
AD		 4138 return link_active;
4139}
4140
563988dc
SA		 4141static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4142{
4143 bool ret = false;
4144 u32 ctrl_ext, thstat;
4145
f96a8a0b 4146 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4147 if (hw->mac.type == e1000_i350) {
4148 thstat = rd32(E1000_THSTAT);
4149 ctrl_ext = rd32(E1000_CTRL_EXT);
4150
4151 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4152 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4153 ret = !!(thstat & event);
563988dc
SA		 4154 }
4155
4156 return ret;
4157}
4158
9d5c8243 4159/**
b980ac18
JK		 4160 * igb_watchdog - Timer Call-back
4161 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4162 **/
4163static void igb_watchdog(unsigned long data)
4164{
4165 struct igb_adapter *adapter = (struct igb_adapter *)data;
4166 /* Do the rest outside of interrupt context */
4167 schedule_work(&adapter->watchdog_task);
4168}
4169
4170static void igb_watchdog_task(struct work_struct *work)
4171{
4172 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4173 struct igb_adapter,
4174 watchdog_task);
9d5c8243 4175 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4176 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4177 struct net_device *netdev = adapter->netdev;
563988dc 4178 u32 link;
7a6ea550 4179 int i;
56cec249 4180 u32 connsw;
9d5c8243 4181
4d6b725e 4182 link = igb_has_link(adapter);
aa9b8cc4
AA		 4183
4184 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4185 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4186 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4187 else
4188 link = false;
4189 }
4190
56cec249
CW		 4191 /* Force link down if we have fiber to swap to */
4192 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4193 if (hw->phy.media_type == e1000_media_type_copper) {
4194 connsw = rd32(E1000_CONNSW);
4195 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4196 link = 0;
4197 }
4198 }
9d5c8243 4199 if (link) {
2bdfc4e2
CW		 4200 /* Perform a reset if the media type changed. */
4201 if (hw->dev_spec._82575.media_changed) {
4202 hw->dev_spec._82575.media_changed = false;
4203 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4204 igb_reset(adapter);
4205 }
749ab2cd
YZ		 4206 /* Cancel scheduled suspend requests. */
4207 pm_runtime_resume(netdev->dev.parent);
4208
9d5c8243
AK		 4209 if (!netif_carrier_ok(netdev)) {
4210 u32 ctrl;
330a6d6a 4211 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4212 &adapter->link_speed,
4213 &adapter->link_duplex);
9d5c8243
AK		 4214
4215 ctrl = rd32(E1000_CTRL);
527d47c1 4216 /* Links status message must follow this format */
876d2d6f
JK		 4217 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
4218 "Duplex, Flow Control: %s\n",
559e9c49
AD		 4219 netdev->name,
4220 adapter->link_speed,
4221 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4222 "Full" : "Half",
4223 (ctrl & E1000_CTRL_TFCE) &&
4224 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4225 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4226 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4227
f4c01e96
CW		 4228 /* disable EEE if enabled */
4229 if ((adapter->flags & IGB_FLAG_EEE) &&
4230 (adapter->link_duplex == HALF_DUPLEX)) {
4231 dev_info(&adapter->pdev->dev,
4232 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4233 adapter->hw.dev_spec._82575.eee_disable = true;
4234 adapter->flags &= ~IGB_FLAG_EEE;
4235 }
4236
c0ba4778
KS		 4237 /* check if SmartSpeed worked */
4238 igb_check_downshift(hw);
4239 if (phy->speed_downgraded)
4240 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4241
563988dc 4242 /* check for thermal sensor event */
876d2d6f
JK		 4243 if (igb_thermal_sensor_event(hw,
4244 E1000_THSTAT_LINK_THROTTLE)) {
4245 netdev_info(netdev, "The network adapter link "
4246 "speed was downshifted because it "
4247 "overheated\n");
7ef5ed1c 4248 }
563988dc 4249
d07f3e37 4250 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4251 adapter->tx_timeout_factor = 1;
4252 switch (adapter->link_speed) {
4253 case SPEED_10:
9d5c8243
AK		 4254 adapter->tx_timeout_factor = 14;
4255 break;
4256 case SPEED_100:
9d5c8243
AK		 4257 /* maybe add some timeout factor ? */
4258 break;
4259 }
4260
4261 netif_carrier_on(netdev);
9d5c8243 4262
4ae196df 4263 igb_ping_all_vfs(adapter);
17dc566c 4264 igb_check_vf_rate_limit(adapter);
4ae196df 4265
4b1a9877 4266 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4267 if (!test_bit(__IGB_DOWN, &adapter->state))
4268 mod_timer(&adapter->phy_info_timer,
4269 round_jiffies(jiffies + 2 * HZ));
4270 }
4271 } else {
4272 if (netif_carrier_ok(netdev)) {
4273 adapter->link_speed = 0;
4274 adapter->link_duplex = 0;
563988dc
SA		 4275
4276 /* check for thermal sensor event */
876d2d6f
JK		 4277 if (igb_thermal_sensor_event(hw,
4278 E1000_THSTAT_PWR_DOWN)) {
4279 netdev_err(netdev, "The network adapter was "
4280 "stopped because it overheated\n");
7ef5ed1c 4281 }
563988dc 4282
527d47c1
AD		 4283 /* Links status message must follow this format */
4284 printk(KERN_INFO "igb: %s NIC Link is Down\n",
4285 netdev->name);
9d5c8243 4286 netif_carrier_off(netdev);
4b1a9877 4287
4ae196df
AD		 4288 igb_ping_all_vfs(adapter);
4289
4b1a9877 4290 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4291 if (!test_bit(__IGB_DOWN, &adapter->state))
4292 mod_timer(&adapter->phy_info_timer,
4293 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4294
56cec249
CW		 4295 /* link is down, time to check for alternate media */
4296 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4297 igb_check_swap_media(adapter);
4298 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4299 schedule_work(&adapter->reset_task);
4300 /* return immediately */
4301 return;
4302 }
4303 }
749ab2cd
YZ		 4304 pm_schedule_suspend(netdev->dev.parent,
4305 MSEC_PER_SEC * 5);
56cec249
CW		 4306
4307 /* also check for alternate media here */
4308 } else if (!netif_carrier_ok(netdev) &&
4309 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4310 igb_check_swap_media(adapter);
4311 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4312 schedule_work(&adapter->reset_task);
4313 /* return immediately */
4314 return;
4315 }
9d5c8243
AK		 4316 }
4317 }
4318
12dcd86b
ED		 4319 spin_lock(&adapter->stats64_lock);
4320 igb_update_stats(adapter, &adapter->stats64);
4321 spin_unlock(&adapter->stats64_lock);
9d5c8243 4322
dbabb065 4323 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4324 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4325 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4326 /* We've lost link, so the controller stops DMA,
4327 * but we've got queued Tx work that's never going
4328 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4329 * (Do the reset outside of interrupt context).
4330 */
dbabb065
AD		 4331 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4332 adapter->tx_timeout_count++;
4333 schedule_work(&adapter->reset_task);
4334 /* return immediately since reset is imminent */
4335 return;
4336 }
9d5c8243 4337 }
9d5c8243 4338
dbabb065 4339 /* Force detection of hung controller every watchdog period */
6d095fa8 4340 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4341 }
f7ba205e 4342
b980ac18 4343 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4344 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4345 u32 eics = 0;
0d1ae7f4
AD		 4346 for (i = 0; i < adapter->num_q_vectors; i++)
4347 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4348 wr32(E1000_EICS, eics);
4349 } else {
4350 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4351 }
9d5c8243 4352
13800469 4353 igb_spoof_check(adapter);
fc580751 4354 igb_ptp_rx_hang(adapter);
13800469 4355
9d5c8243 4356 /* Reset the timer */
aa9b8cc4
AA		 4357 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4358 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4359 mod_timer(&adapter->watchdog_timer,
4360 round_jiffies(jiffies + HZ));
4361 else
4362 mod_timer(&adapter->watchdog_timer,
4363 round_jiffies(jiffies + 2 * HZ));
4364 }
9d5c8243
AK		 4365}
4366
4367enum latency_range {
4368 lowest_latency = 0,
4369 low_latency = 1,
4370 bulk_latency = 2,
4371 latency_invalid = 255
4372};
4373
6eb5a7f1 4374/**
b980ac18
JK		 4375 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4376 * @q_vector: pointer to q_vector
6eb5a7f1 4377 *
b980ac18
JK		 4378 * Stores a new ITR value based on strictly on packet size. This
4379 * algorithm is less sophisticated than that used in igb_update_itr,
4380 * due to the difficulty of synchronizing statistics across multiple
4381 * receive rings. The divisors and thresholds used by this function
4382 * were determined based on theoretical maximum wire speed and testing
4383 * data, in order to minimize response time while increasing bulk
4384 * throughput.
406d4965 4385 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4386 * NOTE: This function is called only when operating in a multiqueue
4387 * receive environment.
6eb5a7f1 4388 **/
047e0030 4389static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4390{
047e0030 4391 int new_val = q_vector->itr_val;
6eb5a7f1 4392 int avg_wire_size = 0;
047e0030 4393 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4394 unsigned int packets;
9d5c8243 4395
6eb5a7f1
AD		 4396 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4397 * ints/sec - ITR timer value of 120 ticks.
4398 */
4399 if (adapter->link_speed != SPEED_1000) {
0ba82994 4400 new_val = IGB_4K_ITR;
6eb5a7f1 4401 goto set_itr_val;
9d5c8243 4402 }
047e0030 4403
0ba82994
AD		 4404 packets = q_vector->rx.total_packets;
4405 if (packets)
4406 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4407
0ba82994
AD		 4408 packets = q_vector->tx.total_packets;
4409 if (packets)
4410 avg_wire_size = max_t(u32, avg_wire_size,
4411 q_vector->tx.total_bytes / packets);
047e0030
AD		 4412
4413 /* if avg_wire_size isn't set no work was done */
4414 if (!avg_wire_size)
4415 goto clear_counts;
9d5c8243 4416
6eb5a7f1
AD		 4417 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4418 avg_wire_size += 24;
4419
4420 /* Don't starve jumbo frames */
4421 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4422
6eb5a7f1
AD		 4423 /* Give a little boost to mid-size frames */
4424 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4425 new_val = avg_wire_size / 3;
4426 else
4427 new_val = avg_wire_size / 2;
9d5c8243 4428
0ba82994
AD		 4429 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4430 if (new_val < IGB_20K_ITR &&
4431 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4432 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4433 new_val = IGB_20K_ITR;
abe1c363 4434
6eb5a7f1 4435set_itr_val:
047e0030
AD		 4436 if (new_val != q_vector->itr_val) {
4437 q_vector->itr_val = new_val;
4438 q_vector->set_itr = 1;
9d5c8243 4439 }
6eb5a7f1 4440clear_counts:
0ba82994
AD		 4441 q_vector->rx.total_bytes = 0;
4442 q_vector->rx.total_packets = 0;
4443 q_vector->tx.total_bytes = 0;
4444 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4445}
4446
4447/**
b980ac18
JK		 4448 * igb_update_itr - update the dynamic ITR value based on statistics
4449 * @q_vector: pointer to q_vector
4450 * @ring_container: ring info to update the itr for
4451 *
4452 * Stores a new ITR value based on packets and byte
4453 * counts during the last interrupt. The advantage of per interrupt
4454 * computation is faster updates and more accurate ITR for the current
4455 * traffic pattern. Constants in this function were computed
4456 * based on theoretical maximum wire speed and thresholds were set based
4457 * on testing data as well as attempting to minimize response time
4458 * while increasing bulk throughput.
406d4965 4459 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4460 * NOTE: These calculations are only valid when operating in a single-
4461 * queue environment.
9d5c8243 4462 **/
0ba82994
AD		 4463static void igb_update_itr(struct igb_q_vector *q_vector,
4464 struct igb_ring_container *ring_container)
9d5c8243 4465{
0ba82994
AD		 4466 unsigned int packets = ring_container->total_packets;
4467 unsigned int bytes = ring_container->total_bytes;
4468 u8 itrval = ring_container->itr;
9d5c8243 4469
0ba82994 4470 /* no packets, exit with status unchanged */
9d5c8243 4471 if (packets == 0)
0ba82994 4472 return;
9d5c8243 4473
0ba82994 4474 switch (itrval) {
9d5c8243
AK		 4475 case lowest_latency:
4476 /* handle TSO and jumbo frames */
4477 if (bytes/packets > 8000)
0ba82994 4478 itrval = bulk_latency;
9d5c8243 4479 else if ((packets < 5) && (bytes > 512))
0ba82994 4480 itrval = low_latency;
9d5c8243
AK		 4481 break;
4482 case low_latency: /* 50 usec aka 20000 ints/s */
4483 if (bytes > 10000) {
4484 /* this if handles the TSO accounting */
4485 if (bytes/packets > 8000) {
0ba82994 4486 itrval = bulk_latency;
9d5c8243 4487 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
0ba82994 4488 itrval = bulk_latency;
9d5c8243 4489 } else if ((packets > 35)) {
0ba82994 4490 itrval = lowest_latency;
9d5c8243
AK		 4491 }
4492 } else if (bytes/packets > 2000) {
0ba82994 4493 itrval = bulk_latency;
9d5c8243 4494 } else if (packets <= 2 && bytes < 512) {
0ba82994 4495 itrval = lowest_latency;
9d5c8243
AK		 4496 }
4497 break;
4498 case bulk_latency: /* 250 usec aka 4000 ints/s */
4499 if (bytes > 25000) {
4500 if (packets > 35)
0ba82994 4501 itrval = low_latency;
1e5c3d21 4502 } else if (bytes < 1500) {
0ba82994 4503 itrval = low_latency;
9d5c8243
AK		 4504 }
4505 break;
4506 }
4507
0ba82994
AD		 4508 /* clear work counters since we have the values we need */
4509 ring_container->total_bytes = 0;
4510 ring_container->total_packets = 0;
4511
4512 /* write updated itr to ring container */
4513 ring_container->itr = itrval;
9d5c8243
AK		 4514}
4515
0ba82994 4516static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4517{
0ba82994 4518 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4519 u32 new_itr = q_vector->itr_val;
0ba82994 4520 u8 current_itr = 0;
9d5c8243
AK		 4521
4522 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4523 if (adapter->link_speed != SPEED_1000) {
4524 current_itr = 0;
0ba82994 4525 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4526 goto set_itr_now;
4527 }
4528
0ba82994
AD		 4529 igb_update_itr(q_vector, &q_vector->tx);
4530 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4531
0ba82994 4532 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4533
6eb5a7f1 4534 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4535 if (current_itr == lowest_latency &&
4536 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4537 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4538 current_itr = low_latency;
4539
9d5c8243
AK		 4540 switch (current_itr) {
4541 /* counts and packets in update_itr are dependent on these numbers */
4542 case lowest_latency:
0ba82994 4543 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4544 break;
4545 case low_latency:
0ba82994 4546 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4547 break;
4548 case bulk_latency:
0ba82994 4549 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4550 break;
4551 default:
4552 break;
4553 }
4554
4555set_itr_now:
047e0030 4556 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4557 /* this attempts to bias the interrupt rate towards Bulk
4558 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4559 * increasing
4560 */
047e0030 4561 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4562 max((new_itr * q_vector->itr_val) /
4563 (new_itr + (q_vector->itr_val >> 2)),
4564 new_itr) : new_itr;
9d5c8243
AK		 4565 /* Don't write the value here; it resets the adapter's
4566 * internal timer, and causes us to delay far longer than
4567 * we should between interrupts. Instead, we write the ITR
4568 * value at the beginning of the next interrupt so the timing
4569 * ends up being correct.
4570 */
047e0030
AD		 4571 q_vector->itr_val = new_itr;
4572 q_vector->set_itr = 1;
9d5c8243 4573 }
9d5c8243
AK		 4574}
4575
c50b52a0
SH		 4576static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4577 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4578{
4579 struct e1000_adv_tx_context_desc *context_desc;
4580 u16 i = tx_ring->next_to_use;
4581
4582 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4583
4584 i++;
4585 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4586
4587 /* set bits to identify this as an advanced context descriptor */
4588 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4589
4590 /* For 82575, context index must be unique per ring. */
866cff06 4591 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4592 mss_l4len_idx |= tx_ring->reg_idx << 4;
4593
4594 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4595 context_desc->seqnum_seed = 0;
4596 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4597 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4598}
4599
7af40ad9
AD		 4600static int igb_tso(struct igb_ring *tx_ring,
4601 struct igb_tx_buffer *first,
4602 u8 *hdr_len)
9d5c8243 4603{
7af40ad9 4604 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4605 u32 vlan_macip_lens, type_tucmd;
4606 u32 mss_l4len_idx, l4len;
4607
ed6aa105
AD		 4608 if (skb->ip_summed != CHECKSUM_PARTIAL)
4609 return 0;
4610
7d13a7d0
AD		 4611 if (!skb_is_gso(skb))
4612 return 0;
9d5c8243
AK		 4613
4614 if (skb_header_cloned(skb)) {
7af40ad9 4615 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
9d5c8243
AK		 4616 if (err)
4617 return err;
4618 }
4619
7d13a7d0
AD		 4620 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4621 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4622
7c4d16ff 4623 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4624 struct iphdr *iph = ip_hdr(skb);
4625 iph->tot_len = 0;
4626 iph->check = 0;
4627 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4628 iph->daddr, 0,
4629 IPPROTO_TCP,
4630 0);
7d13a7d0 4631 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4632 first->tx_flags |= IGB_TX_FLAGS_TSO |
4633 IGB_TX_FLAGS_CSUM |
4634 IGB_TX_FLAGS_IPV4;
8e1e8a47 4635 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4636 ipv6_hdr(skb)->payload_len = 0;
4637 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4638 &ipv6_hdr(skb)->daddr,
4639 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4640 first->tx_flags |= IGB_TX_FLAGS_TSO |
4641 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4642 }
4643
7af40ad9 4644 /* compute header lengths */
7d13a7d0
AD		 4645 l4len = tcp_hdrlen(skb);
4646 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4647
7af40ad9
AD		 4648 /* update gso size and bytecount with header size */
4649 first->gso_segs = skb_shinfo(skb)->gso_segs;
4650 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4651
9d5c8243 4652 /* MSS L4LEN IDX */
7d13a7d0
AD		 4653 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4654 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4655
7d13a7d0
AD		 4656 /* VLAN MACLEN IPLEN */
4657 vlan_macip_lens = skb_network_header_len(skb);
4658 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4659 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4660
7d13a7d0 4661 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4662
7d13a7d0 4663 return 1;
9d5c8243
AK		 4664}
4665
7af40ad9 4666static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4667{
7af40ad9 4668 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4669 u32 vlan_macip_lens = 0;
4670 u32 mss_l4len_idx = 0;
4671 u32 type_tucmd = 0;
9d5c8243 4672
7d13a7d0 4673 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4674 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4675 return;
7d13a7d0
AD		 4676 } else {
4677 u8 l4_hdr = 0;
7af40ad9 4678 switch (first->protocol) {
7c4d16ff 4679 case htons(ETH_P_IP):
7d13a7d0
AD		 4680 vlan_macip_lens |= skb_network_header_len(skb);
4681 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4682 l4_hdr = ip_hdr(skb)->protocol;
4683 break;
7c4d16ff 4684 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4685 vlan_macip_lens |= skb_network_header_len(skb);
4686 l4_hdr = ipv6_hdr(skb)->nexthdr;
4687 break;
4688 default:
4689 if (unlikely(net_ratelimit())) {
4690 dev_warn(tx_ring->dev,
b980ac18
JK		 4691 "partial checksum but proto=%x!\n",
4692 first->protocol);
fa4a7ef3 4693 }
7d13a7d0
AD		 4694 break;
4695 }
fa4a7ef3 4696
7d13a7d0
AD		 4697 switch (l4_hdr) {
4698 case IPPROTO_TCP:
4699 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4700 mss_l4len_idx = tcp_hdrlen(skb) <<
4701 E1000_ADVTXD_L4LEN_SHIFT;
4702 break;
4703 case IPPROTO_SCTP:
4704 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4705 mss_l4len_idx = sizeof(struct sctphdr) <<
4706 E1000_ADVTXD_L4LEN_SHIFT;
4707 break;
4708 case IPPROTO_UDP:
4709 mss_l4len_idx = sizeof(struct udphdr) <<
4710 E1000_ADVTXD_L4LEN_SHIFT;
4711 break;
4712 default:
4713 if (unlikely(net_ratelimit())) {
4714 dev_warn(tx_ring->dev,
b980ac18
JK		 4715 "partial checksum but l4 proto=%x!\n",
4716 l4_hdr);
44b0cda3 4717 }
7d13a7d0 4718 break;
9d5c8243 4719 }
7af40ad9
AD		 4720
4721 /* update TX checksum flag */
4722 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4723 }
9d5c8243 4724
7d13a7d0 4725 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4726 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4727
7d13a7d0 4728 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4729}
4730
1d9daf45
AD		 4731#define IGB_SET_FLAG(_input, _flag, _result) \
4732 ((_flag <= _result) ? \
4733 ((u32)(_input & _flag) * (_result / _flag)) : \
4734 ((u32)(_input & _flag) / (_flag / _result)))
4735
4736static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4737{
4738 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4739 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4740 E1000_ADVTXD_DCMD_DEXT |
4741 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4742
4743 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4744 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4745 (E1000_ADVTXD_DCMD_VLE));
4746
4747 /* set segmentation bits for TSO */
4748 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4749 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4750
4751 /* set timestamp bit if present */
1d9daf45
AD		 4752 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4753 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4754
1d9daf45
AD		 4755 /* insert frame checksum */
4756 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4757
4758 return cmd_type;
4759}
4760
7af40ad9
AD		 4761static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4762 union e1000_adv_tx_desc *tx_desc,
4763 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4764{
4765 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4766
1d9daf45
AD		 4767 /* 82575 requires a unique index per ring */
4768 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4769 olinfo_status |= tx_ring->reg_idx << 4;
4770
4771 /* insert L4 checksum */
1d9daf45
AD		 4772 olinfo_status |= IGB_SET_FLAG(tx_flags,
4773 IGB_TX_FLAGS_CSUM,
4774 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4775
1d9daf45
AD		 4776 /* insert IPv4 checksum */
4777 olinfo_status |= IGB_SET_FLAG(tx_flags,
4778 IGB_TX_FLAGS_IPV4,
4779 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4780
7af40ad9 4781 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4782}
4783
7af40ad9
AD		 4784static void igb_tx_map(struct igb_ring *tx_ring,
4785 struct igb_tx_buffer *first,
ebe42d16 4786 const u8 hdr_len)
9d5c8243 4787{
7af40ad9 4788 struct sk_buff *skb = first->skb;
c9f14bf3 4789 struct igb_tx_buffer *tx_buffer;
ebe42d16 4790 union e1000_adv_tx_desc *tx_desc;
80d0759e 4791 struct skb_frag_struct *frag;
ebe42d16 4792 dma_addr_t dma;
80d0759e 4793 unsigned int data_len, size;
7af40ad9 4794 u32 tx_flags = first->tx_flags;
1d9daf45 4795 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4796 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4797
4798 tx_desc = IGB_TX_DESC(tx_ring, i);
4799
80d0759e
AD		 4800 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4801
4802 size = skb_headlen(skb);
4803 data_len = skb->data_len;
ebe42d16
AD		 4804
4805 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4806
80d0759e
AD		 4807 tx_buffer = first;
4808
4809 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4810 if (dma_mapping_error(tx_ring->dev, dma))
4811 goto dma_error;
4812
4813 /* record length, and DMA address */
4814 dma_unmap_len_set(tx_buffer, len, size);
4815 dma_unmap_addr_set(tx_buffer, dma, dma);
4816
4817 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4818
ebe42d16
AD		 4819 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4820 tx_desc->read.cmd_type_len =
1d9daf45 4821 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4822
4823 i++;
4824 tx_desc++;
4825 if (i == tx_ring->count) {
4826 tx_desc = IGB_TX_DESC(tx_ring, 0);
4827 i = 0;
4828 }
80d0759e 4829 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4830
4831 dma += IGB_MAX_DATA_PER_TXD;
4832 size -= IGB_MAX_DATA_PER_TXD;
4833
ebe42d16
AD		 4834 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4835 }
4836
4837 if (likely(!data_len))
4838 break;
2bbfebe2 4839
1d9daf45 4840 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4841
65689fef 4842 i++;
ebe42d16
AD		 4843 tx_desc++;
4844 if (i == tx_ring->count) {
4845 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4846 i = 0;
ebe42d16 4847 }
80d0759e 4848 tx_desc->read.olinfo_status = 0;
65689fef 4849
9e903e08 4850 size = skb_frag_size(frag);
ebe42d16
AD		 4851 data_len -= size;
4852
4853 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4854 size, DMA_TO_DEVICE);
6366ad33 4855
c9f14bf3 4856 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4857 }
4858
ebe42d16 4859 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4860 cmd_type |= size | IGB_TXD_DCMD;
4861 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4862
80d0759e
AD		 4863 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4864
8542db05
AD		 4865 /* set the timestamp */
4866 first->time_stamp = jiffies;
4867
b980ac18 4868 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4869 * are new descriptors to fetch. (Only applicable for weak-ordered
4870 * memory model archs, such as IA-64).
4871 *
4872 * We also need this memory barrier to make certain all of the
4873 * status bits have been updated before next_to_watch is written.
4874 */
4875 wmb();
4876
8542db05 4877 /* set next_to_watch value indicating a packet is present */
ebe42d16 4878 first->next_to_watch = tx_desc;
9d5c8243 4879
ebe42d16
AD		 4880 i++;
4881 if (i == tx_ring->count)
4882 i = 0;
6366ad33 4883
ebe42d16 4884 tx_ring->next_to_use = i;
6366ad33 4885
ebe42d16 4886 writel(i, tx_ring->tail);
6366ad33 4887
ebe42d16 4888 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4889 * at a time, it synchronizes IO on IA64/Altix systems
4890 */
ebe42d16
AD		 4891 mmiowb();
4892
4893 return;
4894
4895dma_error:
4896 dev_err(tx_ring->dev, "TX DMA map failed\n");
4897
4898 /* clear dma mappings for failed tx_buffer_info map */
4899 for (;;) {
c9f14bf3
AD		 4900 tx_buffer = &tx_ring->tx_buffer_info[i];
4901 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4902 if (tx_buffer == first)
ebe42d16 4903 break;
a77ff709
NN		 4904 if (i == 0)
4905 i = tx_ring->count;
6366ad33 4906 i--;
6366ad33
AD		 4907 }
4908
9d5c8243 4909 tx_ring->next_to_use = i;
9d5c8243
AK		 4910}
4911
6ad4edfc 4912static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4913{
e694e964
AD		 4914 struct net_device *netdev = tx_ring->netdev;
4915
661086df 4916 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4917
9d5c8243
AK		 4918 /* Herbert's original patch had:
4919 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4920 * but since that doesn't exist yet, just open code it.
4921 */
9d5c8243
AK		 4922 smp_mb();
4923
4924 /* We need to check again in a case another CPU has just
b980ac18
JK		 4925 * made room available.
4926 */
c493ea45 4927 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4928 return -EBUSY;
4929
4930 /* A reprieve! */
661086df 4931 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4932
4933 u64_stats_update_begin(&tx_ring->tx_syncp2);
4934 tx_ring->tx_stats.restart_queue2++;
4935 u64_stats_update_end(&tx_ring->tx_syncp2);
4936
9d5c8243
AK		 4937 return 0;
4938}
4939
6ad4edfc 4940static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4941{
c493ea45 4942 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4943 return 0;
e694e964 4944 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4945}
4946
cd392f5c
AD		 4947netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4948 struct igb_ring *tx_ring)
9d5c8243 4949{
8542db05 4950 struct igb_tx_buffer *first;
ebe42d16 4951 int tso;
91d4ee33 4952 u32 tx_flags = 0;
21ba6fe1 4953 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4954 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4955 u8 hdr_len = 0;
9d5c8243 4956
21ba6fe1
AD		 4957 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4958 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4959 * + 2 desc gap to keep tail from touching head,
9d5c8243 4960 * + 1 desc for context descriptor,
21ba6fe1
AD		 4961 * otherwise try next time
4962 */
4963 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4964 unsigned short f;
4965 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4966 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4967 } else {
4968 count += skb_shinfo(skb)->nr_frags;
4969 }
4970
4971 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4972 /* this is a hard error */
9d5c8243
AK		 4973 return NETDEV_TX_BUSY;
4974 }
33af6bcc 4975
7af40ad9
AD		 4976 /* record the location of the first descriptor for this packet */
4977 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4978 first->skb = skb;
4979 first->bytecount = skb->len;
4980 first->gso_segs = 1;
4981
b66e2397
MV		 4982 skb_tx_timestamp(skb);
4983
b646c22e
AD		 4984 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4985 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4986
b646c22e
AD		 4987 if (!(adapter->ptp_tx_skb)) {
4988 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4989 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4990
4991 adapter->ptp_tx_skb = skb_get(skb);
4992 adapter->ptp_tx_start = jiffies;
4993 if (adapter->hw.mac.type == e1000_82576)
4994 schedule_work(&adapter->ptp_tx_work);
4995 }
33af6bcc 4996 }
9d5c8243 4997
eab6d18d 4998 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4999 tx_flags |= IGB_TX_FLAGS_VLAN;
5000 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5001 }
5002
7af40ad9
AD		 5003 /* record initial flags and protocol */
5004 first->tx_flags = tx_flags;
5005 first->protocol = protocol;
cdfd01fc 5006
7af40ad9
AD		 5007 tso = igb_tso(tx_ring, first, &hdr_len);
5008 if (tso < 0)
7d13a7d0 5009 goto out_drop;
7af40ad9
AD		 5010 else if (!tso)
5011 igb_tx_csum(tx_ring, first);
9d5c8243 5012
7af40ad9 5013 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 5014
5015 /* Make sure there is space in the ring for the next send. */
21ba6fe1 5016 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 5017
9d5c8243 5018 return NETDEV_TX_OK;
7d13a7d0
AD		 5019
5020out_drop:
7af40ad9
AD		 5021 igb_unmap_and_free_tx_resource(tx_ring, first);
5022
7d13a7d0 5023 return NETDEV_TX_OK;
9d5c8243
AK		 5024}
5025
1cc3bd87
AD		 5026static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5027 struct sk_buff *skb)
5028{
5029 unsigned int r_idx = skb->queue_mapping;
5030
5031 if (r_idx >= adapter->num_tx_queues)
5032 r_idx = r_idx % adapter->num_tx_queues;
5033
5034 return adapter->tx_ring[r_idx];
5035}
5036
cd392f5c
AD		 5037static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5038 struct net_device *netdev)
9d5c8243
AK		 5039{
5040 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5041
5042 if (test_bit(__IGB_DOWN, &adapter->state)) {
5043 dev_kfree_skb_any(skb);
5044 return NETDEV_TX_OK;
5045 }
5046
5047 if (skb->len <= 0) {
5048 dev_kfree_skb_any(skb);
5049 return NETDEV_TX_OK;
5050 }
5051
b980ac18 5052 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5053 * in order to meet this minimum size requirement.
5054 */
ea5ceeab
TD		 5055 if (unlikely(skb->len < 17)) {
5056 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 5057 return NETDEV_TX_OK;
5058 skb->len = 17;
ea5ceeab 5059 skb_set_tail_pointer(skb, 17);
1cc3bd87 5060 }
9d5c8243 5061
1cc3bd87 5062 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5063}
5064
5065/**
b980ac18
JK		 5066 * igb_tx_timeout - Respond to a Tx Hang
5067 * @netdev: network interface device structure
9d5c8243
AK		 5068 **/
5069static void igb_tx_timeout(struct net_device *netdev)
5070{
5071 struct igb_adapter *adapter = netdev_priv(netdev);
5072 struct e1000_hw *hw = &adapter->hw;
5073
5074 /* Do the reset outside of interrupt context */
5075 adapter->tx_timeout_count++;
f7ba205e 5076
06218a8d 5077 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5078 hw->dev_spec._82575.global_device_reset = true;
5079
9d5c8243 5080 schedule_work(&adapter->reset_task);
265de409
AD		 5081 wr32(E1000_EICS,
5082 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5083}
5084
5085static void igb_reset_task(struct work_struct *work)
5086{
5087 struct igb_adapter *adapter;
5088 adapter = container_of(work, struct igb_adapter, reset_task);
5089
c97ec42a
TI		 5090 igb_dump(adapter);
5091 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5092 igb_reinit_locked(adapter);
5093}
5094
5095/**
b980ac18
JK		 5096 * igb_get_stats64 - Get System Network Statistics
5097 * @netdev: network interface device structure
5098 * @stats: rtnl_link_stats64 pointer
9d5c8243 5099 **/
12dcd86b 5100static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5101 struct rtnl_link_stats64 *stats)
9d5c8243 5102{
12dcd86b
ED		 5103 struct igb_adapter *adapter = netdev_priv(netdev);
5104
5105 spin_lock(&adapter->stats64_lock);
5106 igb_update_stats(adapter, &adapter->stats64);
5107 memcpy(stats, &adapter->stats64, sizeof(*stats));
5108 spin_unlock(&adapter->stats64_lock);
5109
5110 return stats;
9d5c8243
AK		 5111}
5112
5113/**
b980ac18
JK		 5114 * igb_change_mtu - Change the Maximum Transfer Unit
5115 * @netdev: network interface device structure
5116 * @new_mtu: new value for maximum frame size
9d5c8243 5117 *
b980ac18 5118 * Returns 0 on success, negative on failure
9d5c8243
AK		 5119 **/
5120static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5121{
5122 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5123 struct pci_dev *pdev = adapter->pdev;
153285f9 5124 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5125
c809d227 5126 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5127 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5128 return -EINVAL;
5129 }
5130
153285f9 5131#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5132 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5133 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5134 return -EINVAL;
5135 }
5136
2ccd994c
AD		 5137 /* adjust max frame to be at least the size of a standard frame */
5138 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5139 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5140
9d5c8243
AK		 5141 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5142 msleep(1);
73cd78f1 5143
9d5c8243
AK		 5144 /* igb_down has a dependency on max_frame_size */
5145 adapter->max_frame_size = max_frame;
559e9c49 5146
4c844851
AD		 5147 if (netif_running(netdev))
5148 igb_down(adapter);
9d5c8243 5149
090b1795 5150 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5151 netdev->mtu, new_mtu);
5152 netdev->mtu = new_mtu;
5153
5154 if (netif_running(netdev))
5155 igb_up(adapter);
5156 else
5157 igb_reset(adapter);
5158
5159 clear_bit(__IGB_RESETTING, &adapter->state);
5160
5161 return 0;
5162}
5163
5164/**
b980ac18
JK		 5165 * igb_update_stats - Update the board statistics counters
5166 * @adapter: board private structure
9d5c8243 5167 **/
12dcd86b
ED		 5168void igb_update_stats(struct igb_adapter *adapter,
5169 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5170{
5171 struct e1000_hw *hw = &adapter->hw;
5172 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5173 u32 reg, mpc;
9d5c8243 5174 u16 phy_tmp;
3f9c0164
AD		 5175 int i;
5176 u64 bytes, packets;
12dcd86b
ED		 5177 unsigned int start;
5178 u64 _bytes, _packets;
9d5c8243
AK		 5179
5180#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
5181
b980ac18 5182 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5183 * connection is down.
5184 */
5185 if (adapter->link_speed == 0)
5186 return;
5187 if (pci_channel_offline(pdev))
5188 return;
5189
3f9c0164
AD		 5190 bytes = 0;
5191 packets = 0;
7f90128e
AA		 5192
5193 rcu_read_lock();
3f9c0164 5194 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 5195 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 5196 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 5197
ae1c07a6
AD		 5198 if (rqdpc) {
5199 ring->rx_stats.drops += rqdpc;
5200 net_stats->rx_fifo_errors += rqdpc;
5201 }
12dcd86b
ED		 5202
5203 do {
57a7744e 5204 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5205 _bytes = ring->rx_stats.bytes;
5206 _packets = ring->rx_stats.packets;
57a7744e 5207 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5208 bytes += _bytes;
5209 packets += _packets;
3f9c0164
AD		 5210 }
5211
128e45eb
AD		 5212 net_stats->rx_bytes = bytes;
5213 net_stats->rx_packets = packets;
3f9c0164
AD		 5214
5215 bytes = 0;
5216 packets = 0;
5217 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5218 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5219 do {
57a7744e 5220 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5221 _bytes = ring->tx_stats.bytes;
5222 _packets = ring->tx_stats.packets;
57a7744e 5223 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5224 bytes += _bytes;
5225 packets += _packets;
3f9c0164 5226 }
128e45eb
AD		 5227 net_stats->tx_bytes = bytes;
5228 net_stats->tx_packets = packets;
7f90128e 5229 rcu_read_unlock();
3f9c0164
AD		 5230
5231 /* read stats registers */
9d5c8243
AK		 5232 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5233 adapter->stats.gprc += rd32(E1000_GPRC);
5234 adapter->stats.gorc += rd32(E1000_GORCL);
5235 rd32(E1000_GORCH); /* clear GORCL */
5236 adapter->stats.bprc += rd32(E1000_BPRC);
5237 adapter->stats.mprc += rd32(E1000_MPRC);
5238 adapter->stats.roc += rd32(E1000_ROC);
5239
5240 adapter->stats.prc64 += rd32(E1000_PRC64);
5241 adapter->stats.prc127 += rd32(E1000_PRC127);
5242 adapter->stats.prc255 += rd32(E1000_PRC255);
5243 adapter->stats.prc511 += rd32(E1000_PRC511);
5244 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5245 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5246 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5247 adapter->stats.sec += rd32(E1000_SEC);
5248
fa3d9a6d
MW		 5249 mpc = rd32(E1000_MPC);
5250 adapter->stats.mpc += mpc;
5251 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5252 adapter->stats.scc += rd32(E1000_SCC);
5253 adapter->stats.ecol += rd32(E1000_ECOL);
5254 adapter->stats.mcc += rd32(E1000_MCC);
5255 adapter->stats.latecol += rd32(E1000_LATECOL);
5256 adapter->stats.dc += rd32(E1000_DC);
5257 adapter->stats.rlec += rd32(E1000_RLEC);
5258 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5259 adapter->stats.xontxc += rd32(E1000_XONTXC);
5260 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5261 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5262 adapter->stats.fcruc += rd32(E1000_FCRUC);
5263 adapter->stats.gptc += rd32(E1000_GPTC);
5264 adapter->stats.gotc += rd32(E1000_GOTCL);
5265 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5266 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5267 adapter->stats.ruc += rd32(E1000_RUC);
5268 adapter->stats.rfc += rd32(E1000_RFC);
5269 adapter->stats.rjc += rd32(E1000_RJC);
5270 adapter->stats.tor += rd32(E1000_TORH);
5271 adapter->stats.tot += rd32(E1000_TOTH);
5272 adapter->stats.tpr += rd32(E1000_TPR);
5273
5274 adapter->stats.ptc64 += rd32(E1000_PTC64);
5275 adapter->stats.ptc127 += rd32(E1000_PTC127);
5276 adapter->stats.ptc255 += rd32(E1000_PTC255);
5277 adapter->stats.ptc511 += rd32(E1000_PTC511);
5278 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5279 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5280
5281 adapter->stats.mptc += rd32(E1000_MPTC);
5282 adapter->stats.bptc += rd32(E1000_BPTC);
5283
2d0b0f69
NN		 5284 adapter->stats.tpt += rd32(E1000_TPT);
5285 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5286
5287 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5288 /* read internal phy specific stats */
5289 reg = rd32(E1000_CTRL_EXT);
5290 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5291 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5292
5293 /* this stat has invalid values on i210/i211 */
5294 if ((hw->mac.type != e1000_i210) &&
5295 (hw->mac.type != e1000_i211))
5296 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5297 }
5298
9d5c8243
AK		 5299 adapter->stats.tsctc += rd32(E1000_TSCTC);
5300 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5301
5302 adapter->stats.iac += rd32(E1000_IAC);
5303 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5304 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5305 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5306 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5307 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5308 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5309 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5310 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5311
5312 /* Fill out the OS statistics structure */
128e45eb
AD		 5313 net_stats->multicast = adapter->stats.mprc;
5314 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5315
5316 /* Rx Errors */
5317
5318 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5319 * our own version based on RUC and ROC
5320 */
128e45eb 5321 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5322 adapter->stats.crcerrs + adapter->stats.algnerrc +
5323 adapter->stats.ruc + adapter->stats.roc +
5324 adapter->stats.cexterr;
128e45eb
AD		 5325 net_stats->rx_length_errors = adapter->stats.ruc +
5326 adapter->stats.roc;
5327 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5328 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5329 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5330
5331 /* Tx Errors */
128e45eb
AD		 5332 net_stats->tx_errors = adapter->stats.ecol +
5333 adapter->stats.latecol;
5334 net_stats->tx_aborted_errors = adapter->stats.ecol;
5335 net_stats->tx_window_errors = adapter->stats.latecol;
5336 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5337
5338 /* Tx Dropped needs to be maintained elsewhere */
5339
5340 /* Phy Stats */
5341 if (hw->phy.media_type == e1000_media_type_copper) {
5342 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5343 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5344 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5345 adapter->phy_stats.idle_errors += phy_tmp;
5346 }
5347 }
5348
5349 /* Management Stats */
5350 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5351 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5352 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5353
5354 /* OS2BMC Stats */
5355 reg = rd32(E1000_MANC);
5356 if (reg & E1000_MANC_EN_BMC2OS) {
5357 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5358 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5359 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5360 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5361 }
9d5c8243
AK		 5362}
5363
9d5c8243
AK		 5364static irqreturn_t igb_msix_other(int irq, void *data)
5365{
047e0030 5366 struct igb_adapter *adapter = data;
9d5c8243 5367 struct e1000_hw *hw = &adapter->hw;
844290e5 5368 u32 icr = rd32(E1000_ICR);
844290e5 5369 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5370
7f081d40
AD		 5371 if (icr & E1000_ICR_DRSTA)
5372 schedule_work(&adapter->reset_task);
5373
047e0030 5374 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5375 /* HW is reporting DMA is out of sync */
5376 adapter->stats.doosync++;
13800469
GR		 5377 /* The DMA Out of Sync is also indication of a spoof event
5378 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5379 * see if it is really a spoof event.
5380 */
13800469 5381 igb_check_wvbr(adapter);
dda0e083 5382 }
eebbbdba 5383
4ae196df
AD		 5384 /* Check for a mailbox event */
5385 if (icr & E1000_ICR_VMMB)
5386 igb_msg_task(adapter);
5387
5388 if (icr & E1000_ICR_LSC) {
5389 hw->mac.get_link_status = 1;
5390 /* guard against interrupt when we're going down */
5391 if (!test_bit(__IGB_DOWN, &adapter->state))
5392 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5393 }
5394
1f6e8178
MV		 5395 if (icr & E1000_ICR_TS) {
5396 u32 tsicr = rd32(E1000_TSICR);
5397
5398 if (tsicr & E1000_TSICR_TXTS) {
5399 /* acknowledge the interrupt */
5400 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5401 /* retrieve hardware timestamp */
5402 schedule_work(&adapter->ptp_tx_work);
5403 }
5404 }
1f6e8178 5405
844290e5 5406 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5407
5408 return IRQ_HANDLED;
5409}
5410
047e0030 5411static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5412{
26b39276 5413 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5414 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5415
047e0030
AD		 5416 if (!q_vector->set_itr)
5417 return;
73cd78f1 5418
047e0030
AD		 5419 if (!itr_val)
5420 itr_val = 0x4;
661086df 5421
26b39276
AD		 5422 if (adapter->hw.mac.type == e1000_82575)
5423 itr_val |= itr_val << 16;
661086df 5424 else
0ba82994 5425 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5426
047e0030
AD		 5427 writel(itr_val, q_vector->itr_register);
5428 q_vector->set_itr = 0;
6eb5a7f1
AD		 5429}
5430
047e0030 5431static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5432{
047e0030 5433 struct igb_q_vector *q_vector = data;
9d5c8243 5434
047e0030
AD		 5435 /* Write the ITR value calculated from the previous interrupt. */
5436 igb_write_itr(q_vector);
9d5c8243 5437
047e0030 5438 napi_schedule(&q_vector->napi);
844290e5 5439
047e0030 5440 return IRQ_HANDLED;
fe4506b6
JC		 5441}
5442
421e02f0 5443#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5444static void igb_update_tx_dca(struct igb_adapter *adapter,
5445 struct igb_ring *tx_ring,
5446 int cpu)
5447{
5448 struct e1000_hw *hw = &adapter->hw;
5449 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5450
5451 if (hw->mac.type != e1000_82575)
5452 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5453
b980ac18 5454 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5455 * DCA is enabled. This is due to a known issue in some chipsets
5456 * which will cause the DCA tag to be cleared.
5457 */
5458 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5459 E1000_DCA_TXCTRL_DATA_RRO_EN |
5460 E1000_DCA_TXCTRL_DESC_DCA_EN;
5461
5462 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5463}
5464
5465static void igb_update_rx_dca(struct igb_adapter *adapter,
5466 struct igb_ring *rx_ring,
5467 int cpu)
5468{
5469 struct e1000_hw *hw = &adapter->hw;
5470 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5471
5472 if (hw->mac.type != e1000_82575)
5473 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5474
b980ac18 5475 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5476 * DCA is enabled. This is due to a known issue in some chipsets
5477 * which will cause the DCA tag to be cleared.
5478 */
5479 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5480 E1000_DCA_RXCTRL_DESC_DCA_EN;
5481
5482 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5483}
5484
047e0030 5485static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5486{
047e0030 5487 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5488 int cpu = get_cpu();
fe4506b6 5489
047e0030
AD		 5490 if (q_vector->cpu == cpu)
5491 goto out_no_update;
5492
6a05004a
AD		 5493 if (q_vector->tx.ring)
5494 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5495
5496 if (q_vector->rx.ring)
5497 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5498
047e0030
AD		 5499 q_vector->cpu = cpu;
5500out_no_update:
fe4506b6
JC		 5501 put_cpu();
5502}
5503
5504static void igb_setup_dca(struct igb_adapter *adapter)
5505{
7e0e99ef 5506 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5507 int i;
5508
7dfc16fa 5509 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5510 return;
5511
7e0e99ef
AD		 5512 /* Always use CB2 mode, difference is masked in the CB driver. */
5513 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5514
047e0030 5515 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5516 adapter->q_vector[i]->cpu = -1;
5517 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5518 }
5519}
5520
5521static int __igb_notify_dca(struct device *dev, void *data)
5522{
5523 struct net_device *netdev = dev_get_drvdata(dev);
5524 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5525 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5526 struct e1000_hw *hw = &adapter->hw;
5527 unsigned long event = *(unsigned long *)data;
5528
5529 switch (event) {
5530 case DCA_PROVIDER_ADD:
5531 /* if already enabled, don't do it again */
7dfc16fa 5532 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5533 break;
fe4506b6 5534 if (dca_add_requester(dev) == 0) {
bbd98fe4 5535 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5536 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5537 igb_setup_dca(adapter);
5538 break;
5539 }
5540 /* Fall Through since DCA is disabled. */
5541 case DCA_PROVIDER_REMOVE:
7dfc16fa 5542 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5543 /* without this a class_device is left
b980ac18
JK		 5544 * hanging around in the sysfs model
5545 */
fe4506b6 5546 dca_remove_requester(dev);
090b1795 5547 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5548 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5549 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5550 }
5551 break;
5552 }
bbd98fe4 5553
fe4506b6 5554 return 0;
9d5c8243
AK		 5555}
5556
fe4506b6 5557static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5558 void *p)
fe4506b6
JC		 5559{
5560 int ret_val;
5561
5562 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5563 __igb_notify_dca);
fe4506b6
JC		 5564
5565 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5566}
421e02f0 5567#endif /* CONFIG_IGB_DCA */
9d5c8243 5568
0224d663
GR		 5569#ifdef CONFIG_PCI_IOV
5570static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5571{
5572 unsigned char mac_addr[ETH_ALEN];
0224d663 5573
5ac6f91d 5574 eth_zero_addr(mac_addr);
0224d663
GR		 5575 igb_set_vf_mac(adapter, vf, mac_addr);
5576
70ea4783
LL		 5577 /* By default spoof check is enabled for all VFs */
5578 adapter->vf_data[vf].spoofchk_enabled = true;
5579
f557147c 5580 return 0;
0224d663
GR		 5581}
5582
0224d663 5583#endif
4ae196df
AD		 5584static void igb_ping_all_vfs(struct igb_adapter *adapter)
5585{
5586 struct e1000_hw *hw = &adapter->hw;
5587 u32 ping;
5588 int i;
5589
5590 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5591 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5592 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5593 ping |= E1000_VT_MSGTYPE_CTS;
5594 igb_write_mbx(hw, &ping, 1, i);
5595 }
5596}
5597
7d5753f0
AD		 5598static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5599{
5600 struct e1000_hw *hw = &adapter->hw;
5601 u32 vmolr = rd32(E1000_VMOLR(vf));
5602 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5603
d85b9004 5604 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5605 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5606 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5607
5608 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5609 vmolr |= E1000_VMOLR_MPME;
d85b9004 5610 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5611 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5612 } else {
b980ac18 5613 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5614 * flag we need to write the hashes to the MTA as this step
5615 * was previously skipped
5616 */
5617 if (vf_data->num_vf_mc_hashes > 30) {
5618 vmolr |= E1000_VMOLR_MPME;
5619 } else if (vf_data->num_vf_mc_hashes) {
5620 int j;
5621 vmolr |= E1000_VMOLR_ROMPE;
5622 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5623 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5624 }
5625 }
5626
5627 wr32(E1000_VMOLR(vf), vmolr);
5628
5629 /* there are flags left unprocessed, likely not supported */
5630 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5631 return -EINVAL;
5632
5633 return 0;
7d5753f0
AD		 5634}
5635
4ae196df
AD		 5636static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5637 u32 *msgbuf, u32 vf)
5638{
5639 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5640 u16 *hash_list = (u16 *)&msgbuf[1];
5641 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5642 int i;
5643
7d5753f0 5644 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5645 * to this VF for later use to restore when the PF multi cast
5646 * list changes
5647 */
5648 vf_data->num_vf_mc_hashes = n;
5649
7d5753f0
AD		 5650 /* only up to 30 hash values supported */
5651 if (n > 30)
5652 n = 30;
5653
5654 /* store the hashes for later use */
4ae196df 5655 for (i = 0; i < n; i++)
a419aef8 5656 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5657
5658 /* Flush and reset the mta with the new values */
ff41f8dc 5659 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5660
5661 return 0;
5662}
5663
5664static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5665{
5666 struct e1000_hw *hw = &adapter->hw;
5667 struct vf_data_storage *vf_data;
5668 int i, j;
5669
5670 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5671 u32 vmolr = rd32(E1000_VMOLR(i));
5672 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5673
4ae196df 5674 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5675
5676 if ((vf_data->num_vf_mc_hashes > 30) ||
5677 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5678 vmolr |= E1000_VMOLR_MPME;
5679 } else if (vf_data->num_vf_mc_hashes) {
5680 vmolr |= E1000_VMOLR_ROMPE;
5681 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5682 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5683 }
5684 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5685 }
5686}
5687
5688static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5689{
5690 struct e1000_hw *hw = &adapter->hw;
5691 u32 pool_mask, reg, vid;
5692 int i;
5693
5694 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5695
5696 /* Find the vlan filter for this id */
5697 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5698 reg = rd32(E1000_VLVF(i));
5699
5700 /* remove the vf from the pool */
5701 reg &= ~pool_mask;
5702
5703 /* if pool is empty then remove entry from vfta */
5704 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5705 (reg & E1000_VLVF_VLANID_ENABLE)) {
5706 reg = 0;
5707 vid = reg & E1000_VLVF_VLANID_MASK;
5708 igb_vfta_set(hw, vid, false);
5709 }
5710
5711 wr32(E1000_VLVF(i), reg);
5712 }
ae641bdc
AD		 5713
5714 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5715}
5716
5717static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5718{
5719 struct e1000_hw *hw = &adapter->hw;
5720 u32 reg, i;
5721
51466239
AD		 5722 /* The vlvf table only exists on 82576 hardware and newer */
5723 if (hw->mac.type < e1000_82576)
5724 return -1;
5725
5726 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5727 if (!adapter->vfs_allocated_count)
5728 return -1;
5729
5730 /* Find the vlan filter for this id */
5731 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5732 reg = rd32(E1000_VLVF(i));
5733 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5734 vid == (reg & E1000_VLVF_VLANID_MASK))
5735 break;
5736 }
5737
5738 if (add) {
5739 if (i == E1000_VLVF_ARRAY_SIZE) {
5740 /* Did not find a matching VLAN ID entry that was
5741 * enabled. Search for a free filter entry, i.e.
5742 * one without the enable bit set
5743 */
5744 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5745 reg = rd32(E1000_VLVF(i));
5746 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5747 break;
5748 }
5749 }
5750 if (i < E1000_VLVF_ARRAY_SIZE) {
5751 /* Found an enabled/available entry */
5752 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5753
5754 /* if !enabled we need to set this up in vfta */
5755 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5756 /* add VID to filter table */
5757 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5758 reg |= E1000_VLVF_VLANID_ENABLE;
5759 }
cad6d05f
AD		 5760 reg &= ~E1000_VLVF_VLANID_MASK;
5761 reg |= vid;
4ae196df 5762 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5763
5764 /* do not modify RLPML for PF devices */
5765 if (vf >= adapter->vfs_allocated_count)
5766 return 0;
5767
5768 if (!adapter->vf_data[vf].vlans_enabled) {
5769 u32 size;
5770 reg = rd32(E1000_VMOLR(vf));
5771 size = reg & E1000_VMOLR_RLPML_MASK;
5772 size += 4;
5773 reg &= ~E1000_VMOLR_RLPML_MASK;
5774 reg |= size;
5775 wr32(E1000_VMOLR(vf), reg);
5776 }
ae641bdc 5777
51466239 5778 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5779 }
5780 } else {
5781 if (i < E1000_VLVF_ARRAY_SIZE) {
5782 /* remove vf from the pool */
5783 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5784 /* if pool is empty then remove entry from vfta */
5785 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5786 reg = 0;
5787 igb_vfta_set(hw, vid, false);
5788 }
5789 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5790
5791 /* do not modify RLPML for PF devices */
5792 if (vf >= adapter->vfs_allocated_count)
5793 return 0;
5794
5795 adapter->vf_data[vf].vlans_enabled--;
5796 if (!adapter->vf_data[vf].vlans_enabled) {
5797 u32 size;
5798 reg = rd32(E1000_VMOLR(vf));
5799 size = reg & E1000_VMOLR_RLPML_MASK;
5800 size -= 4;
5801 reg &= ~E1000_VMOLR_RLPML_MASK;
5802 reg |= size;
5803 wr32(E1000_VMOLR(vf), reg);
5804 }
4ae196df
AD		 5805 }
5806 }
8151d294
WM		 5807 return 0;
5808}
5809
5810static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5811{
5812 struct e1000_hw *hw = &adapter->hw;
5813
5814 if (vid)
5815 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5816 else
5817 wr32(E1000_VMVIR(vf), 0);
5818}
5819
5820static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5821 int vf, u16 vlan, u8 qos)
5822{
5823 int err = 0;
5824 struct igb_adapter *adapter = netdev_priv(netdev);
5825
5826 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5827 return -EINVAL;
5828 if (vlan || qos) {
5829 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5830 if (err)
5831 goto out;
5832 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5833 igb_set_vmolr(adapter, vf, !vlan);
5834 adapter->vf_data[vf].pf_vlan = vlan;
5835 adapter->vf_data[vf].pf_qos = qos;
5836 dev_info(&adapter->pdev->dev,
5837 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5838 if (test_bit(__IGB_DOWN, &adapter->state)) {
5839 dev_warn(&adapter->pdev->dev,
b980ac18 5840 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5841 dev_warn(&adapter->pdev->dev,
b980ac18 5842 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5843 }
5844 } else {
5845 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5846 false, vf);
8151d294
WM		 5847 igb_set_vmvir(adapter, vlan, vf);
5848 igb_set_vmolr(adapter, vf, true);
5849 adapter->vf_data[vf].pf_vlan = 0;
5850 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5851 }
8151d294 5852out:
b980ac18 5853 return err;
4ae196df
AD		 5854}
5855
6f3dc319
GR		 5856static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5857{
5858 struct e1000_hw *hw = &adapter->hw;
5859 int i;
5860 u32 reg;
5861
5862 /* Find the vlan filter for this id */
5863 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5864 reg = rd32(E1000_VLVF(i));
5865 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5866 vid == (reg & E1000_VLVF_VLANID_MASK))
5867 break;
5868 }
5869
5870 if (i >= E1000_VLVF_ARRAY_SIZE)
5871 i = -1;
5872
5873 return i;
5874}
5875
4ae196df
AD		 5876static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5877{
6f3dc319 5878 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5879 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5880 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5881 int err = 0;
4ae196df 5882
6f3dc319
GR		 5883 /* If in promiscuous mode we need to make sure the PF also has
5884 * the VLAN filter set.
5885 */
5886 if (add && (adapter->netdev->flags & IFF_PROMISC))
5887 err = igb_vlvf_set(adapter, vid, add,
5888 adapter->vfs_allocated_count);
5889 if (err)
5890 goto out;
5891
5892 err = igb_vlvf_set(adapter, vid, add, vf);
5893
5894 if (err)
5895 goto out;
5896
5897 /* Go through all the checks to see if the VLAN filter should
5898 * be wiped completely.
5899 */
5900 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5901 u32 vlvf, bits;
5902
5903 int regndx = igb_find_vlvf_entry(adapter, vid);
5904 if (regndx < 0)
5905 goto out;
5906 /* See if any other pools are set for this VLAN filter
5907 * entry other than the PF.
5908 */
5909 vlvf = bits = rd32(E1000_VLVF(regndx));
5910 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5911 adapter->vfs_allocated_count);
5912 /* If the filter was removed then ensure PF pool bit
5913 * is cleared if the PF only added itself to the pool
5914 * because the PF is in promiscuous mode.
5915 */
5916 if ((vlvf & VLAN_VID_MASK) == vid &&
5917 !test_bit(vid, adapter->active_vlans) &&
5918 !bits)
5919 igb_vlvf_set(adapter, vid, add,
5920 adapter->vfs_allocated_count);
5921 }
5922
5923out:
5924 return err;
4ae196df
AD		 5925}
5926
f2ca0dbe 5927static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5928{
8fa7e0f7
GR		 5929 /* clear flags - except flag that indicates PF has set the MAC */
5930 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5931 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5932
5933 /* reset offloads to defaults */
8151d294 5934 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5935
5936 /* reset vlans for device */
5937 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5938 if (adapter->vf_data[vf].pf_vlan)
5939 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5940 adapter->vf_data[vf].pf_vlan,
5941 adapter->vf_data[vf].pf_qos);
5942 else
5943 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5944
5945 /* reset multicast table array for vf */
5946 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5947
5948 /* Flush and reset the mta with the new values */
ff41f8dc 5949 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5950}
5951
f2ca0dbe
AD		 5952static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5953{
5954 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5955
5ac6f91d 5956 /* clear mac address as we were hotplug removed/added */
8151d294 5957 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5958 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5959
5960 /* process remaining reset events */
5961 igb_vf_reset(adapter, vf);
5962}
5963
5964static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5965{
5966 struct e1000_hw *hw = &adapter->hw;
5967 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5968 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5969 u32 reg, msgbuf[3];
5970 u8 *addr = (u8 *)(&msgbuf[1]);
5971
5972 /* process all the same items cleared in a function level reset */
f2ca0dbe 5973 igb_vf_reset(adapter, vf);
4ae196df
AD		 5974
5975 /* set vf mac address */
26ad9178 5976 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5977
5978 /* enable transmit and receive for vf */
5979 reg = rd32(E1000_VFTE);
5980 wr32(E1000_VFTE, reg | (1 << vf));
5981 reg = rd32(E1000_VFRE);
5982 wr32(E1000_VFRE, reg | (1 << vf));
5983
8fa7e0f7 5984 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5985
5986 /* reply to reset with ack and vf mac address */
5987 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5988 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5989 igb_write_mbx(hw, msgbuf, 3, vf);
5990}
5991
5992static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5993{
b980ac18 5994 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5995 * starting at the second 32 bit word of the msg array
5996 */
f2ca0dbe
AD		 5997 unsigned char *addr = (char *)&msg[1];
5998 int err = -1;
4ae196df 5999
f2ca0dbe
AD		 6000 if (is_valid_ether_addr(addr))
6001 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6002
f2ca0dbe 6003 return err;
4ae196df
AD		 6004}
6005
6006static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6007{
6008 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6009 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6010 u32 msg = E1000_VT_MSGTYPE_NACK;
6011
6012 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6013 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6014 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6015 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6016 vf_data->last_nack = jiffies;
4ae196df
AD		 6017 }
6018}
6019
f2ca0dbe 6020static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6021{
f2ca0dbe
AD		 6022 struct pci_dev *pdev = adapter->pdev;
6023 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6024 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6025 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6026 s32 retval;
6027
f2ca0dbe 6028 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6029
fef45f4c
AD		 6030 if (retval) {
6031 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6032 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6033 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6034 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6035 return;
6036 goto out;
6037 }
4ae196df
AD		 6038
6039 /* this is a message we already processed, do nothing */
6040 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6041 return;
4ae196df 6042
b980ac18 6043 /* until the vf completes a reset it should not be
4ae196df
AD		 6044 * allowed to start any configuration.
6045 */
4ae196df
AD		 6046 if (msgbuf[0] == E1000_VF_RESET) {
6047 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6048 return;
4ae196df
AD		 6049 }
6050
f2ca0dbe 6051 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6052 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6053 return;
6054 retval = -1;
6055 goto out;
4ae196df
AD		 6056 }
6057
6058 switch ((msgbuf[0] & 0xFFFF)) {
6059 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6060 retval = -EINVAL;
6061 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6062 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6063 else
6064 dev_warn(&pdev->dev,
b980ac18
JK		 6065 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6066 vf);
4ae196df 6067 break;
7d5753f0
AD		 6068 case E1000_VF_SET_PROMISC:
6069 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6070 break;
4ae196df
AD		 6071 case E1000_VF_SET_MULTICAST:
6072 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6073 break;
6074 case E1000_VF_SET_LPE:
6075 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6076 break;
6077 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6078 retval = -1;
6079 if (vf_data->pf_vlan)
6080 dev_warn(&pdev->dev,
b980ac18
JK		 6081 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6082 vf);
8151d294
WM		 6083 else
6084 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6085 break;
6086 default:
090b1795 6087 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6088 retval = -1;
6089 break;
6090 }
6091
fef45f4c
AD		 6092 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6093out:
4ae196df
AD		 6094 /* notify the VF of the results of what it sent us */
6095 if (retval)
6096 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6097 else
6098 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6099
4ae196df 6100 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6101}
4ae196df 6102
f2ca0dbe
AD		 6103static void igb_msg_task(struct igb_adapter *adapter)
6104{
6105 struct e1000_hw *hw = &adapter->hw;
6106 u32 vf;
6107
6108 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6109 /* process any reset requests */
6110 if (!igb_check_for_rst(hw, vf))
6111 igb_vf_reset_event(adapter, vf);
6112
6113 /* process any messages pending */
6114 if (!igb_check_for_msg(hw, vf))
6115 igb_rcv_msg_from_vf(adapter, vf);
6116
6117 /* process any acks */
6118 if (!igb_check_for_ack(hw, vf))
6119 igb_rcv_ack_from_vf(adapter, vf);
6120 }
4ae196df
AD		 6121}
6122
68d480c4
AD		 6123/**
6124 * igb_set_uta - Set unicast filter table address
6125 * @adapter: board private structure
6126 *
6127 * The unicast table address is a register array of 32-bit registers.
6128 * The table is meant to be used in a way similar to how the MTA is used
6129 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6130 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6131 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6132 **/
6133static void igb_set_uta(struct igb_adapter *adapter)
6134{
6135 struct e1000_hw *hw = &adapter->hw;
6136 int i;
6137
6138 /* The UTA table only exists on 82576 hardware and newer */
6139 if (hw->mac.type < e1000_82576)
6140 return;
6141
6142 /* we only need to do this if VMDq is enabled */
6143 if (!adapter->vfs_allocated_count)
6144 return;
6145
6146 for (i = 0; i < hw->mac.uta_reg_count; i++)
6147 array_wr32(E1000_UTA, i, ~0);
6148}
6149
9d5c8243 6150/**
b980ac18
JK		 6151 * igb_intr_msi - Interrupt Handler
6152 * @irq: interrupt number
6153 * @data: pointer to a network interface device structure
9d5c8243
AK		 6154 **/
6155static irqreturn_t igb_intr_msi(int irq, void *data)
6156{
047e0030
AD		 6157 struct igb_adapter *adapter = data;
6158 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6159 struct e1000_hw *hw = &adapter->hw;
6160 /* read ICR disables interrupts using IAM */
6161 u32 icr = rd32(E1000_ICR);
6162
047e0030 6163 igb_write_itr(q_vector);
9d5c8243 6164
7f081d40
AD		 6165 if (icr & E1000_ICR_DRSTA)
6166 schedule_work(&adapter->reset_task);
6167
047e0030 6168 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6169 /* HW is reporting DMA is out of sync */
6170 adapter->stats.doosync++;
6171 }
6172
9d5c8243
AK		 6173 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6174 hw->mac.get_link_status = 1;
6175 if (!test_bit(__IGB_DOWN, &adapter->state))
6176 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6177 }
6178
1f6e8178
MV		 6179 if (icr & E1000_ICR_TS) {
6180 u32 tsicr = rd32(E1000_TSICR);
6181
6182 if (tsicr & E1000_TSICR_TXTS) {
6183 /* acknowledge the interrupt */
6184 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6185 /* retrieve hardware timestamp */
6186 schedule_work(&adapter->ptp_tx_work);
6187 }
6188 }
1f6e8178 6189
047e0030 6190 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6191
6192 return IRQ_HANDLED;
6193}
6194
6195/**
b980ac18
JK		 6196 * igb_intr - Legacy Interrupt Handler
6197 * @irq: interrupt number
6198 * @data: pointer to a network interface device structure
9d5c8243
AK		 6199 **/
6200static irqreturn_t igb_intr(int irq, void *data)
6201{
047e0030
AD		 6202 struct igb_adapter *adapter = data;
6203 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6204 struct e1000_hw *hw = &adapter->hw;
6205 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6206 * need for the IMC write
6207 */
9d5c8243 6208 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6209
6210 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6211 * not set, then the adapter didn't send an interrupt
6212 */
9d5c8243
AK		 6213 if (!(icr & E1000_ICR_INT_ASSERTED))
6214 return IRQ_NONE;
6215
0ba82994
AD		 6216 igb_write_itr(q_vector);
6217
7f081d40
AD		 6218 if (icr & E1000_ICR_DRSTA)
6219 schedule_work(&adapter->reset_task);
6220
047e0030 6221 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6222 /* HW is reporting DMA is out of sync */
6223 adapter->stats.doosync++;
6224 }
6225
9d5c8243
AK		 6226 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6227 hw->mac.get_link_status = 1;
6228 /* guard against interrupt when we're going down */
6229 if (!test_bit(__IGB_DOWN, &adapter->state))
6230 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6231 }
6232
1f6e8178
MV		 6233 if (icr & E1000_ICR_TS) {
6234 u32 tsicr = rd32(E1000_TSICR);
6235
6236 if (tsicr & E1000_TSICR_TXTS) {
6237 /* acknowledge the interrupt */
6238 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6239 /* retrieve hardware timestamp */
6240 schedule_work(&adapter->ptp_tx_work);
6241 }
6242 }
1f6e8178 6243
047e0030 6244 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6245
6246 return IRQ_HANDLED;
6247}
6248
c50b52a0 6249static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6250{
047e0030 6251 struct igb_adapter *adapter = q_vector->adapter;
46544258 6252 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6253
0ba82994
AD		 6254 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6255 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6256 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6257 igb_set_itr(q_vector);
46544258 6258 else
047e0030 6259 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6260 }
6261
46544258 6262 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6263 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6264 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6265 else
6266 igb_irq_enable(adapter);
6267 }
9d5c8243
AK		 6268}
6269
46544258 6270/**
b980ac18
JK		 6271 * igb_poll - NAPI Rx polling callback
6272 * @napi: napi polling structure
6273 * @budget: count of how many packets we should handle
46544258
AD		 6274 **/
6275static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6276{
047e0030 6277 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6278 struct igb_q_vector,
6279 napi);
16eb8815 6280 bool clean_complete = true;
9d5c8243 6281
421e02f0 6282#ifdef CONFIG_IGB_DCA
047e0030
AD		 6283 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6284 igb_update_dca(q_vector);
fe4506b6 6285#endif
0ba82994 6286 if (q_vector->tx.ring)
13fde97a 6287 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6288
0ba82994 6289 if (q_vector->rx.ring)
cd392f5c 6290 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6291
16eb8815
AD		 6292 /* If all work not completed, return budget and keep polling */
6293 if (!clean_complete)
6294 return budget;
46544258 6295
9d5c8243 6296 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6297 napi_complete(napi);
6298 igb_ring_irq_enable(q_vector);
9d5c8243 6299
16eb8815 6300 return 0;
9d5c8243 6301}
6d8126f9 6302
9d5c8243 6303/**
b980ac18
JK		 6304 * igb_clean_tx_irq - Reclaim resources after transmit completes
6305 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6306 *
b980ac18 6307 * returns true if ring is completely cleaned
9d5c8243 6308 **/
047e0030 6309static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6310{
047e0030 6311 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6312 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6313 struct igb_tx_buffer *tx_buffer;
f4128785 6314 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6315 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6316 unsigned int budget = q_vector->tx.work_limit;
8542db05 6317 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6318
13fde97a
AD		 6319 if (test_bit(__IGB_DOWN, &adapter->state))
6320 return true;
0e014cb1 6321
06034649 6322 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6323 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6324 i -= tx_ring->count;
9d5c8243 6325
f4128785
AD		 6326 do {
6327 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6328
6329 /* if next_to_watch is not set then there is no work pending */
6330 if (!eop_desc)
6331 break;
13fde97a 6332
f4128785 6333 /* prevent any other reads prior to eop_desc */
70d289bc 6334 read_barrier_depends();
f4128785 6335
13fde97a
AD		 6336 /* if DD is not set pending work has not been completed */
6337 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6338 break;
6339
8542db05
AD		 6340 /* clear next_to_watch to prevent false hangs */
6341 tx_buffer->next_to_watch = NULL;
9d5c8243 6342
ebe42d16
AD		 6343 /* update the statistics for this packet */
6344 total_bytes += tx_buffer->bytecount;
6345 total_packets += tx_buffer->gso_segs;
13fde97a 6346
ebe42d16
AD		 6347 /* free the skb */
6348 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6349
ebe42d16
AD		 6350 /* unmap skb header data */
6351 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6352 dma_unmap_addr(tx_buffer, dma),
6353 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6354 DMA_TO_DEVICE);
6355
c9f14bf3
AD		 6356 /* clear tx_buffer data */
6357 tx_buffer->skb = NULL;
6358 dma_unmap_len_set(tx_buffer, len, 0);
6359
ebe42d16
AD		 6360 /* clear last DMA location and unmap remaining buffers */
6361 while (tx_desc != eop_desc) {
13fde97a
AD		 6362 tx_buffer++;
6363 tx_desc++;
9d5c8243 6364 i++;
8542db05
AD		 6365 if (unlikely(!i)) {
6366 i -= tx_ring->count;
06034649 6367 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6368 tx_desc = IGB_TX_DESC(tx_ring, 0);
6369 }
ebe42d16
AD		 6370
6371 /* unmap any remaining paged data */
c9f14bf3 6372 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6373 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6374 dma_unmap_addr(tx_buffer, dma),
6375 dma_unmap_len(tx_buffer, len),
ebe42d16 6376 DMA_TO_DEVICE);
c9f14bf3 6377 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6378 }
6379 }
6380
ebe42d16
AD		 6381 /* move us one more past the eop_desc for start of next pkt */
6382 tx_buffer++;
6383 tx_desc++;
6384 i++;
6385 if (unlikely(!i)) {
6386 i -= tx_ring->count;
6387 tx_buffer = tx_ring->tx_buffer_info;
6388 tx_desc = IGB_TX_DESC(tx_ring, 0);
6389 }
f4128785
AD		 6390
6391 /* issue prefetch for next Tx descriptor */
6392 prefetch(tx_desc);
6393
6394 /* update budget accounting */
6395 budget--;
6396 } while (likely(budget));
0e014cb1 6397
bdbc0631
ED		 6398 netdev_tx_completed_queue(txring_txq(tx_ring),
6399 total_packets, total_bytes);
8542db05 6400 i += tx_ring->count;
9d5c8243 6401 tx_ring->next_to_clean = i;
13fde97a
AD		 6402 u64_stats_update_begin(&tx_ring->tx_syncp);
6403 tx_ring->tx_stats.bytes += total_bytes;
6404 tx_ring->tx_stats.packets += total_packets;
6405 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6406 q_vector->tx.total_bytes += total_bytes;
6407 q_vector->tx.total_packets += total_packets;
9d5c8243 6408
6d095fa8 6409 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6410 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6411
9d5c8243 6412 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6413 * check with the clearing of time_stamp and movement of i
6414 */
6d095fa8 6415 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6416 if (tx_buffer->next_to_watch &&
8542db05 6417 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6418 (adapter->tx_timeout_factor * HZ)) &&
6419 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6420
9d5c8243 6421 /* detected Tx unit hang */
59d71989 6422 dev_err(tx_ring->dev,
9d5c8243 6423 "Detected Tx Unit Hang\n"
2d064c06 6424 " Tx Queue <%d>\n"
9d5c8243
AK		 6425 " TDH <%x>\n"
6426 " TDT <%x>\n"
6427 " next_to_use <%x>\n"
6428 " next_to_clean <%x>\n"
9d5c8243
AK		 6429 "buffer_info[next_to_clean]\n"
6430 " time_stamp <%lx>\n"
8542db05 6431 " next_to_watch <%p>\n"
9d5c8243
AK		 6432 " jiffies <%lx>\n"
6433 " desc.status <%x>\n",
2d064c06 6434 tx_ring->queue_index,
238ac817 6435 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6436 readl(tx_ring->tail),
9d5c8243
AK		 6437 tx_ring->next_to_use,
6438 tx_ring->next_to_clean,
8542db05 6439 tx_buffer->time_stamp,
f4128785 6440 tx_buffer->next_to_watch,
9d5c8243 6441 jiffies,
f4128785 6442 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6443 netif_stop_subqueue(tx_ring->netdev,
6444 tx_ring->queue_index);
6445
6446 /* we are about to reset, no point in enabling stuff */
6447 return true;
9d5c8243
AK		 6448 }
6449 }
13fde97a 6450
21ba6fe1 6451#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6452 if (unlikely(total_packets &&
b980ac18
JK		 6453 netif_carrier_ok(tx_ring->netdev) &&
6454 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6455 /* Make sure that anybody stopping the queue after this
6456 * sees the new next_to_clean.
6457 */
6458 smp_mb();
6459 if (__netif_subqueue_stopped(tx_ring->netdev,
6460 tx_ring->queue_index) &&
6461 !(test_bit(__IGB_DOWN, &adapter->state))) {
6462 netif_wake_subqueue(tx_ring->netdev,
6463 tx_ring->queue_index);
6464
6465 u64_stats_update_begin(&tx_ring->tx_syncp);
6466 tx_ring->tx_stats.restart_queue++;
6467 u64_stats_update_end(&tx_ring->tx_syncp);
6468 }
6469 }
6470
6471 return !!budget;
9d5c8243
AK		 6472}
6473
cbc8e55f 6474/**
b980ac18
JK		 6475 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6476 * @rx_ring: rx descriptor ring to store buffers on
6477 * @old_buff: donor buffer to have page reused
cbc8e55f 6478 *
b980ac18 6479 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6480 **/
6481static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6482 struct igb_rx_buffer *old_buff)
6483{
6484 struct igb_rx_buffer *new_buff;
6485 u16 nta = rx_ring->next_to_alloc;
6486
6487 new_buff = &rx_ring->rx_buffer_info[nta];
6488
6489 /* update, and store next to alloc */
6490 nta++;
6491 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6492
6493 /* transfer page from old buffer to new buffer */
6494 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6495
6496 /* sync the buffer for use by the device */
6497 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6498 old_buff->page_offset,
de78d1f9 6499 IGB_RX_BUFSZ,
cbc8e55f
AD		 6500 DMA_FROM_DEVICE);
6501}
6502
74e238ea
AD		 6503static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6504 struct page *page,
6505 unsigned int truesize)
6506{
6507 /* avoid re-using remote pages */
6508 if (unlikely(page_to_nid(page) != numa_node_id()))
6509 return false;
6510
6511#if (PAGE_SIZE < 8192)
6512 /* if we are only owner of page we can reuse it */
6513 if (unlikely(page_count(page) != 1))
6514 return false;
6515
6516 /* flip page offset to other buffer */
6517 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6518
6519 /* since we are the only owner of the page and we need to
6520 * increment it, just set the value to 2 in order to avoid
6521 * an unnecessary locked operation
6522 */
6523 atomic_set(&page->_count, 2);
6524#else
6525 /* move offset up to the next cache line */
6526 rx_buffer->page_offset += truesize;
6527
6528 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6529 return false;
6530
6531 /* bump ref count on page before it is given to the stack */
6532 get_page(page);
6533#endif
6534
6535 return true;
6536}
6537
cbc8e55f 6538/**
b980ac18
JK		 6539 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6540 * @rx_ring: rx descriptor ring to transact packets on
6541 * @rx_buffer: buffer containing page to add
6542 * @rx_desc: descriptor containing length of buffer written by hardware
6543 * @skb: sk_buff to place the data into
cbc8e55f 6544 *
b980ac18
JK		 6545 * This function will add the data contained in rx_buffer->page to the skb.
6546 * This is done either through a direct copy if the data in the buffer is
6547 * less than the skb header size, otherwise it will just attach the page as
6548 * a frag to the skb.
cbc8e55f 6549 *
b980ac18
JK		 6550 * The function will then update the page offset if necessary and return
6551 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6552 **/
6553static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6554 struct igb_rx_buffer *rx_buffer,
6555 union e1000_adv_rx_desc *rx_desc,
6556 struct sk_buff *skb)
6557{
6558 struct page *page = rx_buffer->page;
6559 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6560#if (PAGE_SIZE < 8192)
6561 unsigned int truesize = IGB_RX_BUFSZ;
6562#else
6563 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6564#endif
cbc8e55f
AD		 6565
6566 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6567 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6568
cbc8e55f
AD		 6569 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6570 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6571 va += IGB_TS_HDR_LEN;
6572 size -= IGB_TS_HDR_LEN;
6573 }
6574
cbc8e55f
AD		 6575 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6576
6577 /* we can reuse buffer as-is, just make sure it is local */
6578 if (likely(page_to_nid(page) == numa_node_id()))
6579 return true;
6580
6581 /* this page cannot be reused so discard it */
6582 put_page(page);
6583 return false;
6584 }
6585
6586 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6587 rx_buffer->page_offset, size, truesize);
cbc8e55f 6588
74e238ea
AD		 6589 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6590}
cbc8e55f 6591
2e334eee
AD		 6592static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6593 union e1000_adv_rx_desc *rx_desc,
6594 struct sk_buff *skb)
6595{
6596 struct igb_rx_buffer *rx_buffer;
6597 struct page *page;
6598
6599 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6600
2e334eee
AD		 6601 page = rx_buffer->page;
6602 prefetchw(page);
6603
6604 if (likely(!skb)) {
6605 void *page_addr = page_address(page) +
6606 rx_buffer->page_offset;
6607
6608 /* prefetch first cache line of first page */
6609 prefetch(page_addr);
6610#if L1_CACHE_BYTES < 128
6611 prefetch(page_addr + L1_CACHE_BYTES);
6612#endif
6613
6614 /* allocate a skb to store the frags */
6615 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6616 IGB_RX_HDR_LEN);
6617 if (unlikely(!skb)) {
6618 rx_ring->rx_stats.alloc_failed++;
6619 return NULL;
6620 }
6621
b980ac18 6622 /* we will be copying header into skb->data in
2e334eee
AD		 6623 * pskb_may_pull so it is in our interest to prefetch
6624 * it now to avoid a possible cache miss
6625 */
6626 prefetchw(skb->data);
6627 }
6628
6629 /* we are reusing so sync this buffer for CPU use */
6630 dma_sync_single_range_for_cpu(rx_ring->dev,
6631 rx_buffer->dma,
6632 rx_buffer->page_offset,
de78d1f9 6633 IGB_RX_BUFSZ,
2e334eee
AD		 6634 DMA_FROM_DEVICE);
6635
6636 /* pull page into skb */
6637 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6638 /* hand second half of page back to the ring */
6639 igb_reuse_rx_page(rx_ring, rx_buffer);
6640 } else {
6641 /* we are not reusing the buffer so unmap it */
6642 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6643 PAGE_SIZE, DMA_FROM_DEVICE);
6644 }
6645
6646 /* clear contents of rx_buffer */
6647 rx_buffer->page = NULL;
6648
6649 return skb;
6650}
6651
cd392f5c 6652static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6653 union e1000_adv_rx_desc *rx_desc,
6654 struct sk_buff *skb)
9d5c8243 6655{
bc8acf2c 6656 skb_checksum_none_assert(skb);
9d5c8243 6657
294e7d78 6658 /* Ignore Checksum bit is set */
3ceb90fd 6659 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6660 return;
6661
6662 /* Rx checksum disabled via ethtool */
6663 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6664 return;
85ad76b2 6665
9d5c8243 6666 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6667 if (igb_test_staterr(rx_desc,
6668 E1000_RXDEXT_STATERR_TCPE |
6669 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6670 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6671 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6672 * packets, (aka let the stack check the crc32c)
6673 */
866cff06
AD		 6674 if (!((skb->len == 60) &&
6675 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6676 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6677 ring->rx_stats.csum_err++;
12dcd86b
ED		 6678 u64_stats_update_end(&ring->rx_syncp);
6679 }
9d5c8243 6680 /* let the stack verify checksum errors */
9d5c8243
AK		 6681 return;
6682 }
6683 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6684 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6685 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6686 skb->ip_summed = CHECKSUM_UNNECESSARY;
6687
3ceb90fd
AD		 6688 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6689 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6690}
6691
077887c3
AD		 6692static inline void igb_rx_hash(struct igb_ring *ring,
6693 union e1000_adv_rx_desc *rx_desc,
6694 struct sk_buff *skb)
6695{
6696 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6697 skb_set_hash(skb,
6698 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6699 PKT_HASH_TYPE_L3);
077887c3
AD		 6700}
6701
2e334eee 6702/**
b980ac18
JK		 6703 * igb_is_non_eop - process handling of non-EOP buffers
6704 * @rx_ring: Rx ring being processed
6705 * @rx_desc: Rx descriptor for current buffer
6706 * @skb: current socket buffer containing buffer in progress
2e334eee 6707 *
b980ac18
JK		 6708 * This function updates next to clean. If the buffer is an EOP buffer
6709 * this function exits returning false, otherwise it will place the
6710 * sk_buff in the next buffer to be chained and return true indicating
6711 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6712 **/
6713static bool igb_is_non_eop(struct igb_ring *rx_ring,
6714 union e1000_adv_rx_desc *rx_desc)
6715{
6716 u32 ntc = rx_ring->next_to_clean + 1;
6717
6718 /* fetch, update, and store next to clean */
6719 ntc = (ntc < rx_ring->count) ? ntc : 0;
6720 rx_ring->next_to_clean = ntc;
6721
6722 prefetch(IGB_RX_DESC(rx_ring, ntc));
6723
6724 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6725 return false;
6726
6727 return true;
6728}
6729
1a1c225b 6730/**
b980ac18
JK		 6731 * igb_get_headlen - determine size of header for LRO/GRO
6732 * @data: pointer to the start of the headers
6733 * @max_len: total length of section to find headers in
1a1c225b 6734 *
b980ac18
JK		 6735 * This function is meant to determine the length of headers that will
6736 * be recognized by hardware for LRO, and GRO offloads. The main
6737 * motivation of doing this is to only perform one pull for IPv4 TCP
6738 * packets so that we can do basic things like calculating the gso_size
6739 * based on the average data per packet.
1a1c225b
AD		 6740 **/
6741static unsigned int igb_get_headlen(unsigned char *data,
6742 unsigned int max_len)
6743{
6744 union {
6745 unsigned char *network;
6746 /* l2 headers */
6747 struct ethhdr *eth;
6748 struct vlan_hdr *vlan;
6749 /* l3 headers */
6750 struct iphdr *ipv4;
6751 struct ipv6hdr *ipv6;
6752 } hdr;
6753 __be16 protocol;
6754 u8 nexthdr = 0; /* default to not TCP */
6755 u8 hlen;
6756
6757 /* this should never happen, but better safe than sorry */
6758 if (max_len < ETH_HLEN)
6759 return max_len;
6760
6761 /* initialize network frame pointer */
6762 hdr.network = data;
6763
6764 /* set first protocol and move network header forward */
6765 protocol = hdr.eth->h_proto;
6766 hdr.network += ETH_HLEN;
6767
6768 /* handle any vlan tag if present */
7c4d16ff 6769 if (protocol == htons(ETH_P_8021Q)) {
1a1c225b
AD		 6770 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6771 return max_len;
6772
6773 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6774 hdr.network += VLAN_HLEN;
6775 }
6776
6777 /* handle L3 protocols */
7c4d16ff 6778 if (protocol == htons(ETH_P_IP)) {
1a1c225b
AD		 6779 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6780 return max_len;
6781
6782 /* access ihl as a u8 to avoid unaligned access on ia64 */
6783 hlen = (hdr.network[0] & 0x0F) << 2;
6784
6785 /* verify hlen meets minimum size requirements */
6786 if (hlen < sizeof(struct iphdr))
6787 return hdr.network - data;
6788
f2fb4ab2 6789 /* record next protocol if header is present */
b9555f66 6790 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6791 nexthdr = hdr.ipv4->protocol;
7c4d16ff 6792 } else if (protocol == htons(ETH_P_IPV6)) {
1a1c225b
AD		 6793 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6794 return max_len;
6795
6796 /* record next protocol */
6797 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6798 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6799 } else {
6800 return hdr.network - data;
6801 }
6802
f2fb4ab2
AD		 6803 /* relocate pointer to start of L4 header */
6804 hdr.network += hlen;
6805
1a1c225b
AD		 6806 /* finally sort out TCP */
6807 if (nexthdr == IPPROTO_TCP) {
6808 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6809 return max_len;
6810
6811 /* access doff as a u8 to avoid unaligned access on ia64 */
6812 hlen = (hdr.network[12] & 0xF0) >> 2;
6813
6814 /* verify hlen meets minimum size requirements */
6815 if (hlen < sizeof(struct tcphdr))
6816 return hdr.network - data;
6817
6818 hdr.network += hlen;
6819 } else if (nexthdr == IPPROTO_UDP) {
6820 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6821 return max_len;
6822
6823 hdr.network += sizeof(struct udphdr);
6824 }
6825
b980ac18 6826 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6827 * data section of the packet and will be the end of the header.
6828 * If not then it probably represents the end of the last recognized
6829 * header.
6830 */
6831 if ((hdr.network - data) < max_len)
6832 return hdr.network - data;
6833 else
6834 return max_len;
6835}
6836
6837/**
b980ac18
JK		 6838 * igb_pull_tail - igb specific version of skb_pull_tail
6839 * @rx_ring: rx descriptor ring packet is being transacted on
6840 * @rx_desc: pointer to the EOP Rx descriptor
6841 * @skb: pointer to current skb being adjusted
1a1c225b 6842 *
b980ac18
JK		 6843 * This function is an igb specific version of __pskb_pull_tail. The
6844 * main difference between this version and the original function is that
6845 * this function can make several assumptions about the state of things
6846 * that allow for significant optimizations versus the standard function.
6847 * As a result we can do things like drop a frag and maintain an accurate
6848 * truesize for the skb.
1a1c225b
AD		 6849 */
6850static void igb_pull_tail(struct igb_ring *rx_ring,
6851 union e1000_adv_rx_desc *rx_desc,
6852 struct sk_buff *skb)
2d94d8ab 6853{
1a1c225b
AD		 6854 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6855 unsigned char *va;
6856 unsigned int pull_len;
6857
b980ac18 6858 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6859 * working with pages allocated out of the lomem pool per
6860 * alloc_page(GFP_ATOMIC)
2d94d8ab 6861 */
1a1c225b
AD		 6862 va = skb_frag_address(frag);
6863
1a1c225b
AD		 6864 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6865 /* retrieve timestamp from buffer */
6866 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6867
6868 /* update pointers to remove timestamp header */
6869 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6870 frag->page_offset += IGB_TS_HDR_LEN;
6871 skb->data_len -= IGB_TS_HDR_LEN;
6872 skb->len -= IGB_TS_HDR_LEN;
6873
6874 /* move va to start of packet data */
6875 va += IGB_TS_HDR_LEN;
6876 }
6877
b980ac18 6878 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6879 * 60 bytes if the skb->len is less than 60 for skb_pad.
6880 */
6881 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6882
6883 /* align pull length to size of long to optimize memcpy performance */
6884 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6885
6886 /* update all of the pointers */
6887 skb_frag_size_sub(frag, pull_len);
6888 frag->page_offset += pull_len;
6889 skb->data_len -= pull_len;
6890 skb->tail += pull_len;
6891}
6892
6893/**
b980ac18
JK		 6894 * igb_cleanup_headers - Correct corrupted or empty headers
6895 * @rx_ring: rx descriptor ring packet is being transacted on
6896 * @rx_desc: pointer to the EOP Rx descriptor
6897 * @skb: pointer to current skb being fixed
1a1c225b 6898 *
b980ac18
JK		 6899 * Address the case where we are pulling data in on pages only
6900 * and as such no data is present in the skb header.
1a1c225b 6901 *
b980ac18
JK		 6902 * In addition if skb is not at least 60 bytes we need to pad it so that
6903 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6904 *
b980ac18 6905 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6906 **/
6907static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6908 union e1000_adv_rx_desc *rx_desc,
6909 struct sk_buff *skb)
6910{
1a1c225b
AD		 6911 if (unlikely((igb_test_staterr(rx_desc,
6912 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6913 struct net_device *netdev = rx_ring->netdev;
6914 if (!(netdev->features & NETIF_F_RXALL)) {
6915 dev_kfree_skb_any(skb);
6916 return true;
6917 }
6918 }
6919
6920 /* place header in linear portion of buffer */
6921 if (skb_is_nonlinear(skb))
6922 igb_pull_tail(rx_ring, rx_desc, skb);
6923
6924 /* if skb_pad returns an error the skb was freed */
6925 if (unlikely(skb->len < 60)) {
6926 int pad_len = 60 - skb->len;
6927
6928 if (skb_pad(skb, pad_len))
6929 return true;
6930 __skb_put(skb, pad_len);
6931 }
6932
6933 return false;
2d94d8ab
AD		 6934}
6935
db2ee5bd 6936/**
b980ac18
JK		 6937 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6938 * @rx_ring: rx descriptor ring packet is being transacted on
6939 * @rx_desc: pointer to the EOP Rx descriptor
6940 * @skb: pointer to current skb being populated
db2ee5bd 6941 *
b980ac18
JK		 6942 * This function checks the ring, descriptor, and packet information in
6943 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6944 * other fields within the skb.
db2ee5bd
AD		 6945 **/
6946static void igb_process_skb_fields(struct igb_ring *rx_ring,
6947 union e1000_adv_rx_desc *rx_desc,
6948 struct sk_buff *skb)
6949{
6950 struct net_device *dev = rx_ring->netdev;
6951
6952 igb_rx_hash(rx_ring, rx_desc, skb);
6953
6954 igb_rx_checksum(rx_ring, rx_desc, skb);
6955
20a48412 6956 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
db2ee5bd 6957
f646968f 6958 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6959 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6960 u16 vid;
6961 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6962 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6963 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6964 else
6965 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6966
86a9bad3 6967 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6968 }
6969
6970 skb_record_rx_queue(skb, rx_ring->queue_index);
6971
6972 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6973}
6974
2e334eee 6975static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6976{
0ba82994 6977 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6978 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6979 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6980 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6981
57ba34c9 6982 while (likely(total_packets < budget)) {
2e334eee 6983 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6984
2e334eee
AD		 6985 /* return some buffers to hardware, one at a time is too slow */
6986 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6987 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6988 cleaned_count = 0;
6989 }
bf36c1a0 6990
2e334eee 6991 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6992
2e334eee
AD		 6993 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6994 break;
9d5c8243 6995
74e238ea
AD		 6996 /* This memory barrier is needed to keep us from reading
6997 * any other fields out of the rx_desc until we know the
6998 * RXD_STAT_DD bit is set
6999 */
7000 rmb();
7001
2e334eee 7002 /* retrieve a buffer from the ring */
f9d40f6a 7003 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7004
2e334eee
AD		 7005 /* exit if we failed to retrieve a buffer */
7006 if (!skb)
7007 break;
1a1c225b 7008
2e334eee 7009 cleaned_count++;
1a1c225b 7010
2e334eee
AD		 7011 /* fetch next buffer in frame if non-eop */
7012 if (igb_is_non_eop(rx_ring, rx_desc))
7013 continue;
1a1c225b
AD		 7014
7015 /* verify the packet layout is correct */
7016 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7017 skb = NULL;
7018 continue;
9d5c8243 7019 }
9d5c8243 7020
db2ee5bd 7021 /* probably a little skewed due to removing CRC */
3ceb90fd 7022 total_bytes += skb->len;
3ceb90fd 7023
db2ee5bd
AD		 7024 /* populate checksum, timestamp, VLAN, and protocol */
7025 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7026
b2cb09b1 7027 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7028
1a1c225b
AD		 7029 /* reset skb pointer */
7030 skb = NULL;
7031
2e334eee
AD		 7032 /* update budget accounting */
7033 total_packets++;
57ba34c9 7034 }
bf36c1a0 7035
1a1c225b
AD		 7036 /* place incomplete frames back on ring for completion */
7037 rx_ring->skb = skb;
7038
12dcd86b 7039 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7040 rx_ring->rx_stats.packets += total_packets;
7041 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7042 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7043 q_vector->rx.total_packets += total_packets;
7044 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7045
7046 if (cleaned_count)
cd392f5c 7047 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7048
2e334eee 7049 return (total_packets < budget);
9d5c8243
AK		 7050}
7051
c023cd88 7052static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7053 struct igb_rx_buffer *bi)
c023cd88
AD		 7054{
7055 struct page *page = bi->page;
cbc8e55f 7056 dma_addr_t dma;
c023cd88 7057
cbc8e55f
AD		 7058 /* since we are recycling buffers we should seldom need to alloc */
7059 if (likely(page))
c023cd88
AD		 7060 return true;
7061
cbc8e55f
AD		 7062 /* alloc new page for storage */
7063 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
7064 if (unlikely(!page)) {
7065 rx_ring->rx_stats.alloc_failed++;
7066 return false;
c023cd88
AD		 7067 }
7068
cbc8e55f
AD		 7069 /* map page for use */
7070 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7071
b980ac18 7072 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7073 * there isn't much point in holding memory we can't use
7074 */
1a1c225b 7075 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7076 __free_page(page);
7077
c023cd88
AD		 7078 rx_ring->rx_stats.alloc_failed++;
7079 return false;
7080 }
7081
1a1c225b 7082 bi->dma = dma;
cbc8e55f
AD		 7083 bi->page = page;
7084 bi->page_offset = 0;
1a1c225b 7085
c023cd88
AD		 7086 return true;
7087}
7088
9d5c8243 7089/**
b980ac18
JK		 7090 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7091 * @adapter: address of board private structure
9d5c8243 7092 **/
cd392f5c 7093void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7094{
9d5c8243 7095 union e1000_adv_rx_desc *rx_desc;
06034649 7096 struct igb_rx_buffer *bi;
c023cd88 7097 u16 i = rx_ring->next_to_use;
9d5c8243 7098
cbc8e55f
AD		 7099 /* nothing to do */
7100 if (!cleaned_count)
7101 return;
7102
60136906 7103 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7104 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7105 i -= rx_ring->count;
9d5c8243 7106
cbc8e55f 7107 do {
1a1c225b 7108 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7109 break;
9d5c8243 7110
b980ac18 7111 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7112 * because each write-back erases this info.
7113 */
f9d40f6a 7114 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7115
c023cd88
AD		 7116 rx_desc++;
7117 bi++;
9d5c8243 7118 i++;
c023cd88 7119 if (unlikely(!i)) {
60136906 7120 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7121 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7122 i -= rx_ring->count;
7123 }
7124
7125 /* clear the hdr_addr for the next_to_use descriptor */
7126 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7127
7128 cleaned_count--;
7129 } while (cleaned_count);
9d5c8243 7130
c023cd88
AD		 7131 i += rx_ring->count;
7132
9d5c8243 7133 if (rx_ring->next_to_use != i) {
cbc8e55f 7134 /* record the next descriptor to use */
9d5c8243 7135 rx_ring->next_to_use = i;
9d5c8243 7136
cbc8e55f
AD		 7137 /* update next to alloc since we have filled the ring */
7138 rx_ring->next_to_alloc = i;
7139
b980ac18 7140 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7141 * know there are new descriptors to fetch. (Only
7142 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7143 * such as IA-64).
7144 */
9d5c8243 7145 wmb();
fce99e34 7146 writel(i, rx_ring->tail);
9d5c8243
AK		 7147 }
7148}
7149
7150/**
7151 * igb_mii_ioctl -
7152 * @netdev:
7153 * @ifreq:
7154 * @cmd:
7155 **/
7156static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7157{
7158 struct igb_adapter *adapter = netdev_priv(netdev);
7159 struct mii_ioctl_data *data = if_mii(ifr);
7160
7161 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7162 return -EOPNOTSUPP;
7163
7164 switch (cmd) {
7165 case SIOCGMIIPHY:
7166 data->phy_id = adapter->hw.phy.addr;
7167 break;
7168 case SIOCGMIIREG:
f5f4cf08
AD		 7169 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7170 &data->val_out))
9d5c8243
AK		 7171 return -EIO;
7172 break;
7173 case SIOCSMIIREG:
7174 default:
7175 return -EOPNOTSUPP;
7176 }
7177 return 0;
7178}
7179
7180/**
7181 * igb_ioctl -
7182 * @netdev:
7183 * @ifreq:
7184 * @cmd:
7185 **/
7186static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7187{
7188 switch (cmd) {
7189 case SIOCGMIIPHY:
7190 case SIOCGMIIREG:
7191 case SIOCSMIIREG:
7192 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7193 case SIOCGHWTSTAMP:
7194 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7195 case SIOCSHWTSTAMP:
6ab5f7b2 7196 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7197 default:
7198 return -EOPNOTSUPP;
7199 }
7200}
7201
009bc06e
AD		 7202s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7203{
7204 struct igb_adapter *adapter = hw->back;
009bc06e 7205
23d028cc 7206 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7207 return -E1000_ERR_CONFIG;
7208
009bc06e
AD		 7209 return 0;
7210}
7211
7212s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7213{
7214 struct igb_adapter *adapter = hw->back;
009bc06e 7215
23d028cc 7216 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7217 return -E1000_ERR_CONFIG;
7218
009bc06e
AD		 7219 return 0;
7220}
7221
c8f44aff 7222static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7223{
7224 struct igb_adapter *adapter = netdev_priv(netdev);
7225 struct e1000_hw *hw = &adapter->hw;
7226 u32 ctrl, rctl;
f646968f 7227 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7228
5faf030c 7229 if (enable) {
9d5c8243
AK		 7230 /* enable VLAN tag insert/strip */
7231 ctrl = rd32(E1000_CTRL);
7232 ctrl |= E1000_CTRL_VME;
7233 wr32(E1000_CTRL, ctrl);
7234
51466239 7235 /* Disable CFI check */
9d5c8243 7236 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7237 rctl &= ~E1000_RCTL_CFIEN;
7238 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7239 } else {
7240 /* disable VLAN tag insert/strip */
7241 ctrl = rd32(E1000_CTRL);
7242 ctrl &= ~E1000_CTRL_VME;
7243 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7244 }
7245
e1739522 7246 igb_rlpml_set(adapter);
9d5c8243
AK		 7247}
7248
80d5c368
PM		 7249static int igb_vlan_rx_add_vid(struct net_device *netdev,
7250 __be16 proto, u16 vid)
9d5c8243
AK		 7251{
7252 struct igb_adapter *adapter = netdev_priv(netdev);
7253 struct e1000_hw *hw = &adapter->hw;
4ae196df 7254 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7255
51466239
AD		 7256 /* attempt to add filter to vlvf array */
7257 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7258
51466239
AD		 7259 /* add the filter since PF can receive vlans w/o entry in vlvf */
7260 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7261
7262 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7263
7264 return 0;
9d5c8243
AK		 7265}
7266
80d5c368
PM		 7267static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7268 __be16 proto, u16 vid)
9d5c8243
AK		 7269{
7270 struct igb_adapter *adapter = netdev_priv(netdev);
7271 struct e1000_hw *hw = &adapter->hw;
4ae196df 7272 int pf_id = adapter->vfs_allocated_count;
51466239 7273 s32 err;
9d5c8243 7274
51466239
AD		 7275 /* remove vlan from VLVF table array */
7276 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7277
51466239
AD		 7278 /* if vid was not present in VLVF just remove it from table */
7279 if (err)
4ae196df 7280 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7281
7282 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7283
7284 return 0;
9d5c8243
AK		 7285}
7286
7287static void igb_restore_vlan(struct igb_adapter *adapter)
7288{
b2cb09b1 7289 u16 vid;
9d5c8243 7290
5faf030c
AD		 7291 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7292
b2cb09b1 7293 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7294 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7295}
7296
14ad2513 7297int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7298{
090b1795 7299 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7300 struct e1000_mac_info *mac = &adapter->hw.mac;
7301
7302 mac->autoneg = 0;
7303
14ad2513 7304 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7305 * for the switch() below to work
7306 */
14ad2513
DD		 7307 if ((spd & 1) || (dplx & ~1))
7308 goto err_inval;
7309
f502ef7d
AA		 7310 /* Fiber NIC's only allow 1000 gbps Full duplex
7311 * and 100Mbps Full duplex for 100baseFx sfp
7312 */
7313 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7314 switch (spd + dplx) {
7315 case SPEED_10 + DUPLEX_HALF:
7316 case SPEED_10 + DUPLEX_FULL:
7317 case SPEED_100 + DUPLEX_HALF:
7318 goto err_inval;
7319 default:
7320 break;
7321 }
7322 }
cd2638a8 7323
14ad2513 7324 switch (spd + dplx) {
9d5c8243
AK		 7325 case SPEED_10 + DUPLEX_HALF:
7326 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7327 break;
7328 case SPEED_10 + DUPLEX_FULL:
7329 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7330 break;
7331 case SPEED_100 + DUPLEX_HALF:
7332 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7333 break;
7334 case SPEED_100 + DUPLEX_FULL:
7335 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7336 break;
7337 case SPEED_1000 + DUPLEX_FULL:
7338 mac->autoneg = 1;
7339 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7340 break;
7341 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7342 default:
14ad2513 7343 goto err_inval;
9d5c8243 7344 }
8376dad0
JB		 7345
7346 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7347 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7348
9d5c8243 7349 return 0;
14ad2513
DD		 7350
7351err_inval:
7352 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7353 return -EINVAL;
9d5c8243
AK		 7354}
7355
749ab2cd
YZ		 7356static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7357 bool runtime)
9d5c8243
AK		 7358{
7359 struct net_device *netdev = pci_get_drvdata(pdev);
7360 struct igb_adapter *adapter = netdev_priv(netdev);
7361 struct e1000_hw *hw = &adapter->hw;
2d064c06 7362 u32 ctrl, rctl, status;
749ab2cd 7363 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7364#ifdef CONFIG_PM
7365 int retval = 0;
7366#endif
7367
7368 netif_device_detach(netdev);
7369
a88f10ec 7370 if (netif_running(netdev))
749ab2cd 7371 __igb_close(netdev, true);
a88f10ec 7372
047e0030 7373 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7374
7375#ifdef CONFIG_PM
7376 retval = pci_save_state(pdev);
7377 if (retval)
7378 return retval;
7379#endif
7380
7381 status = rd32(E1000_STATUS);
7382 if (status & E1000_STATUS_LU)
7383 wufc &= ~E1000_WUFC_LNKC;
7384
7385 if (wufc) {
7386 igb_setup_rctl(adapter);
ff41f8dc 7387 igb_set_rx_mode(netdev);
9d5c8243
AK		 7388
7389 /* turn on all-multi mode if wake on multicast is enabled */
7390 if (wufc & E1000_WUFC_MC) {
7391 rctl = rd32(E1000_RCTL);
7392 rctl |= E1000_RCTL_MPE;
7393 wr32(E1000_RCTL, rctl);
7394 }
7395
7396 ctrl = rd32(E1000_CTRL);
7397 /* advertise wake from D3Cold */
7398 #define E1000_CTRL_ADVD3WUC 0x00100000
7399 /* phy power management enable */
7400 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7401 ctrl |= E1000_CTRL_ADVD3WUC;
7402 wr32(E1000_CTRL, ctrl);
7403
9d5c8243 7404 /* Allow time for pending master requests to run */
330a6d6a 7405 igb_disable_pcie_master(hw);
9d5c8243
AK		 7406
7407 wr32(E1000_WUC, E1000_WUC_PME_EN);
7408 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7409 } else {
7410 wr32(E1000_WUC, 0);
7411 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7412 }
7413
3fe7c4c9
RW		 7414 *enable_wake = wufc || adapter->en_mng_pt;
7415 if (!*enable_wake)
88a268c1
NN		 7416 igb_power_down_link(adapter);
7417 else
7418 igb_power_up_link(adapter);
9d5c8243
AK		 7419
7420 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7421 * would have already happened in close and is redundant.
7422 */
9d5c8243
AK		 7423 igb_release_hw_control(adapter);
7424
7425 pci_disable_device(pdev);
7426
9d5c8243
AK		 7427 return 0;
7428}
7429
7430#ifdef CONFIG_PM
d9dd966d 7431#ifdef CONFIG_PM_SLEEP
749ab2cd 7432static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7433{
7434 int retval;
7435 bool wake;
749ab2cd 7436 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7437
749ab2cd 7438 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7439 if (retval)
7440 return retval;
7441
7442 if (wake) {
7443 pci_prepare_to_sleep(pdev);
7444 } else {
7445 pci_wake_from_d3(pdev, false);
7446 pci_set_power_state(pdev, PCI_D3hot);
7447 }
7448
7449 return 0;
7450}
d9dd966d 7451#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7452
749ab2cd 7453static int igb_resume(struct device *dev)
9d5c8243 7454{
749ab2cd 7455 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7456 struct net_device *netdev = pci_get_drvdata(pdev);
7457 struct igb_adapter *adapter = netdev_priv(netdev);
7458 struct e1000_hw *hw = &adapter->hw;
7459 u32 err;
7460
7461 pci_set_power_state(pdev, PCI_D0);
7462 pci_restore_state(pdev);
b94f2d77 7463 pci_save_state(pdev);
42bfd33a 7464
aed5dec3 7465 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7466 if (err) {
7467 dev_err(&pdev->dev,
7468 "igb: Cannot enable PCI device from suspend\n");
7469 return err;
7470 }
7471 pci_set_master(pdev);
7472
7473 pci_enable_wake(pdev, PCI_D3hot, 0);
7474 pci_enable_wake(pdev, PCI_D3cold, 0);
7475
53c7d064 7476 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7477 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7478 return -ENOMEM;
9d5c8243
AK		 7479 }
7480
9d5c8243 7481 igb_reset(adapter);
a8564f03
AD		 7482
7483 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7484 * driver.
7485 */
a8564f03
AD		 7486 igb_get_hw_control(adapter);
7487
9d5c8243
AK		 7488 wr32(E1000_WUS, ~0);
7489
749ab2cd 7490 if (netdev->flags & IFF_UP) {
0c2cc02e 7491 rtnl_lock();
749ab2cd 7492 err = __igb_open(netdev, true);
0c2cc02e 7493 rtnl_unlock();
a88f10ec
AD		 7494 if (err)
7495 return err;
7496 }
9d5c8243
AK		 7497
7498 netif_device_attach(netdev);
749ab2cd
YZ		 7499 return 0;
7500}
7501
7502#ifdef CONFIG_PM_RUNTIME
7503static int igb_runtime_idle(struct device *dev)
7504{
7505 struct pci_dev *pdev = to_pci_dev(dev);
7506 struct net_device *netdev = pci_get_drvdata(pdev);
7507 struct igb_adapter *adapter = netdev_priv(netdev);
7508
7509 if (!igb_has_link(adapter))
7510 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7511
7512 return -EBUSY;
7513}
7514
7515static int igb_runtime_suspend(struct device *dev)
7516{
7517 struct pci_dev *pdev = to_pci_dev(dev);
7518 int retval;
7519 bool wake;
7520
7521 retval = __igb_shutdown(pdev, &wake, 1);
7522 if (retval)
7523 return retval;
7524
7525 if (wake) {
7526 pci_prepare_to_sleep(pdev);
7527 } else {
7528 pci_wake_from_d3(pdev, false);
7529 pci_set_power_state(pdev, PCI_D3hot);
7530 }
9d5c8243 7531
9d5c8243
AK		 7532 return 0;
7533}
749ab2cd
YZ		 7534
7535static int igb_runtime_resume(struct device *dev)
7536{
7537 return igb_resume(dev);
7538}
7539#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7540#endif
7541
7542static void igb_shutdown(struct pci_dev *pdev)
7543{
3fe7c4c9
RW		 7544 bool wake;
7545
749ab2cd 7546 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7547
7548 if (system_state == SYSTEM_POWER_OFF) {
7549 pci_wake_from_d3(pdev, wake);
7550 pci_set_power_state(pdev, PCI_D3hot);
7551 }
9d5c8243
AK		 7552}
7553
fa44f2f1
GR		 7554#ifdef CONFIG_PCI_IOV
7555static int igb_sriov_reinit(struct pci_dev *dev)
7556{
7557 struct net_device *netdev = pci_get_drvdata(dev);
7558 struct igb_adapter *adapter = netdev_priv(netdev);
7559 struct pci_dev *pdev = adapter->pdev;
7560
7561 rtnl_lock();
7562
7563 if (netif_running(netdev))
7564 igb_close(netdev);
7565
7566 igb_clear_interrupt_scheme(adapter);
7567
7568 igb_init_queue_configuration(adapter);
7569
7570 if (igb_init_interrupt_scheme(adapter, true)) {
7571 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7572 return -ENOMEM;
7573 }
7574
7575 if (netif_running(netdev))
7576 igb_open(netdev);
7577
7578 rtnl_unlock();
7579
7580 return 0;
7581}
7582
7583static int igb_pci_disable_sriov(struct pci_dev *dev)
7584{
7585 int err = igb_disable_sriov(dev);
7586
7587 if (!err)
7588 err = igb_sriov_reinit(dev);
7589
7590 return err;
7591}
7592
7593static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7594{
7595 int err = igb_enable_sriov(dev, num_vfs);
7596
7597 if (err)
7598 goto out;
7599
7600 err = igb_sriov_reinit(dev);
7601 if (!err)
7602 return num_vfs;
7603
7604out:
7605 return err;
7606}
7607
7608#endif
7609static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7610{
7611#ifdef CONFIG_PCI_IOV
7612 if (num_vfs == 0)
7613 return igb_pci_disable_sriov(dev);
7614 else
7615 return igb_pci_enable_sriov(dev, num_vfs);
7616#endif
7617 return 0;
7618}
7619
9d5c8243 7620#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7621/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7622 * without having to re-enable interrupts. It's not called while
7623 * the interrupt routine is executing.
7624 */
7625static void igb_netpoll(struct net_device *netdev)
7626{
7627 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7628 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7629 struct igb_q_vector *q_vector;
9d5c8243 7630 int i;
9d5c8243 7631
047e0030 7632 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7633 q_vector = adapter->q_vector[i];
cd14ef54 7634 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7635 wr32(E1000_EIMC, q_vector->eims_value);
7636 else
7637 igb_irq_disable(adapter);
047e0030 7638 napi_schedule(&q_vector->napi);
eebbbdba 7639 }
9d5c8243
AK		 7640}
7641#endif /* CONFIG_NET_POLL_CONTROLLER */
7642
7643/**
b980ac18
JK		 7644 * igb_io_error_detected - called when PCI error is detected
7645 * @pdev: Pointer to PCI device
7646 * @state: The current pci connection state
9d5c8243 7647 *
b980ac18
JK		 7648 * This function is called after a PCI bus error affecting
7649 * this device has been detected.
7650 **/
9d5c8243
AK		 7651static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7652 pci_channel_state_t state)
7653{
7654 struct net_device *netdev = pci_get_drvdata(pdev);
7655 struct igb_adapter *adapter = netdev_priv(netdev);
7656
7657 netif_device_detach(netdev);
7658
59ed6eec
AD		 7659 if (state == pci_channel_io_perm_failure)
7660 return PCI_ERS_RESULT_DISCONNECT;
7661
9d5c8243
AK		 7662 if (netif_running(netdev))
7663 igb_down(adapter);
7664 pci_disable_device(pdev);
7665
7666 /* Request a slot slot reset. */
7667 return PCI_ERS_RESULT_NEED_RESET;
7668}
7669
7670/**
b980ac18
JK		 7671 * igb_io_slot_reset - called after the pci bus has been reset.
7672 * @pdev: Pointer to PCI device
9d5c8243 7673 *
b980ac18
JK		 7674 * Restart the card from scratch, as if from a cold-boot. Implementation
7675 * resembles the first-half of the igb_resume routine.
7676 **/
9d5c8243
AK		 7677static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7678{
7679 struct net_device *netdev = pci_get_drvdata(pdev);
7680 struct igb_adapter *adapter = netdev_priv(netdev);
7681 struct e1000_hw *hw = &adapter->hw;
40a914fa 7682 pci_ers_result_t result;
42bfd33a 7683 int err;
9d5c8243 7684
aed5dec3 7685 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7686 dev_err(&pdev->dev,
7687 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7688 result = PCI_ERS_RESULT_DISCONNECT;
7689 } else {
7690 pci_set_master(pdev);
7691 pci_restore_state(pdev);
b94f2d77 7692 pci_save_state(pdev);
9d5c8243 7693
40a914fa
AD		 7694 pci_enable_wake(pdev, PCI_D3hot, 0);
7695 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7696
40a914fa
AD		 7697 igb_reset(adapter);
7698 wr32(E1000_WUS, ~0);
7699 result = PCI_ERS_RESULT_RECOVERED;
7700 }
9d5c8243 7701
ea943d41
JK		 7702 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7703 if (err) {
b980ac18
JK		 7704 dev_err(&pdev->dev,
7705 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7706 err);
ea943d41
JK		 7707 /* non-fatal, continue */
7708 }
40a914fa
AD		 7709
7710 return result;
9d5c8243
AK		 7711}
7712
7713/**
b980ac18
JK		 7714 * igb_io_resume - called when traffic can start flowing again.
7715 * @pdev: Pointer to PCI device
9d5c8243 7716 *
b980ac18
JK		 7717 * This callback is called when the error recovery driver tells us that
7718 * its OK to resume normal operation. Implementation resembles the
7719 * second-half of the igb_resume routine.
9d5c8243
AK		 7720 */
7721static void igb_io_resume(struct pci_dev *pdev)
7722{
7723 struct net_device *netdev = pci_get_drvdata(pdev);
7724 struct igb_adapter *adapter = netdev_priv(netdev);
7725
9d5c8243
AK		 7726 if (netif_running(netdev)) {
7727 if (igb_up(adapter)) {
7728 dev_err(&pdev->dev, "igb_up failed after reset\n");
7729 return;
7730 }
7731 }
7732
7733 netif_device_attach(netdev);
7734
7735 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7736 * driver.
7737 */
9d5c8243 7738 igb_get_hw_control(adapter);
9d5c8243
AK		 7739}
7740
26ad9178 7741static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7742 u8 qsel)
26ad9178
AD		 7743{
7744 u32 rar_low, rar_high;
7745 struct e1000_hw *hw = &adapter->hw;
7746
7747 /* HW expects these in little endian so we reverse the byte order
7748 * from network order (big endian) to little endian
7749 */
7750 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7751 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7752 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7753
7754 /* Indicate to hardware the Address is Valid. */
7755 rar_high |= E1000_RAH_AV;
7756
7757 if (hw->mac.type == e1000_82575)
7758 rar_high |= E1000_RAH_POOL_1 * qsel;
7759 else
7760 rar_high |= E1000_RAH_POOL_1 << qsel;
7761
7762 wr32(E1000_RAL(index), rar_low);
7763 wrfl();
7764 wr32(E1000_RAH(index), rar_high);
7765 wrfl();
7766}
7767
4ae196df 7768static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7769 int vf, unsigned char *mac_addr)
4ae196df
AD		 7770{
7771 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7772 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7773 * towards the first, as a result a collision should not be possible
7774 */
ff41f8dc 7775 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7776
37680117 7777 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7778
26ad9178 7779 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7780
7781 return 0;
7782}
7783
8151d294
WM		 7784static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7785{
7786 struct igb_adapter *adapter = netdev_priv(netdev);
7787 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7788 return -EINVAL;
7789 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7790 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7791 dev_info(&adapter->pdev->dev,
7792 "Reload the VF driver to make this change effective.");
8151d294 7793 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7794 dev_warn(&adapter->pdev->dev,
7795 "The VF MAC address has been set, but the PF device is not up.\n");
7796 dev_warn(&adapter->pdev->dev,
7797 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7798 }
7799 return igb_set_vf_mac(adapter, vf, mac);
7800}
7801
17dc566c
LL		 7802static int igb_link_mbps(int internal_link_speed)
7803{
7804 switch (internal_link_speed) {
7805 case SPEED_100:
7806 return 100;
7807 case SPEED_1000:
7808 return 1000;
7809 default:
7810 return 0;
7811 }
7812}
7813
7814static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7815 int link_speed)
7816{
7817 int rf_dec, rf_int;
7818 u32 bcnrc_val;
7819
7820 if (tx_rate != 0) {
7821 /* Calculate the rate factor values to set */
7822 rf_int = link_speed / tx_rate;
7823 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7824 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7825 tx_rate;
17dc566c
LL		 7826
7827 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7828 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7829 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7830 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7831 } else {
7832 bcnrc_val = 0;
7833 }
7834
7835 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7836 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7837 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7838 */
7839 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7840 wr32(E1000_RTTBCNRC, bcnrc_val);
7841}
7842
7843static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7844{
7845 int actual_link_speed, i;
7846 bool reset_rate = false;
7847
7848 /* VF TX rate limit was not set or not supported */
7849 if ((adapter->vf_rate_link_speed == 0) ||
7850 (adapter->hw.mac.type != e1000_82576))
7851 return;
7852
7853 actual_link_speed = igb_link_mbps(adapter->link_speed);
7854 if (actual_link_speed != adapter->vf_rate_link_speed) {
7855 reset_rate = true;
7856 adapter->vf_rate_link_speed = 0;
7857 dev_info(&adapter->pdev->dev,
b980ac18 7858 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7859 }
7860
7861 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7862 if (reset_rate)
7863 adapter->vf_data[i].tx_rate = 0;
7864
7865 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7866 adapter->vf_data[i].tx_rate,
7867 actual_link_speed);
17dc566c
LL		 7868 }
7869}
7870
8151d294
WM		 7871static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7872{
17dc566c
LL		 7873 struct igb_adapter *adapter = netdev_priv(netdev);
7874 struct e1000_hw *hw = &adapter->hw;
7875 int actual_link_speed;
7876
7877 if (hw->mac.type != e1000_82576)
7878 return -EOPNOTSUPP;
7879
7880 actual_link_speed = igb_link_mbps(adapter->link_speed);
7881 if ((vf >= adapter->vfs_allocated_count) ||
7882 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7883 (tx_rate < 0) || (tx_rate > actual_link_speed))
7884 return -EINVAL;
7885
7886 adapter->vf_rate_link_speed = actual_link_speed;
7887 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7888 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7889
7890 return 0;
8151d294
WM		 7891}
7892
70ea4783
LL		 7893static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7894 bool setting)
7895{
7896 struct igb_adapter *adapter = netdev_priv(netdev);
7897 struct e1000_hw *hw = &adapter->hw;
7898 u32 reg_val, reg_offset;
7899
7900 if (!adapter->vfs_allocated_count)
7901 return -EOPNOTSUPP;
7902
7903 if (vf >= adapter->vfs_allocated_count)
7904 return -EINVAL;
7905
7906 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7907 reg_val = rd32(reg_offset);
7908 if (setting)
7909 reg_val |= ((1 << vf) |
7910 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7911 else
7912 reg_val &= ~((1 << vf) |
7913 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7914 wr32(reg_offset, reg_val);
7915
7916 adapter->vf_data[vf].spoofchk_enabled = setting;
7917 return E1000_SUCCESS;
7918}
7919
8151d294
WM		 7920static int igb_ndo_get_vf_config(struct net_device *netdev,
7921 int vf, struct ifla_vf_info *ivi)
7922{
7923 struct igb_adapter *adapter = netdev_priv(netdev);
7924 if (vf >= adapter->vfs_allocated_count)
7925 return -EINVAL;
7926 ivi->vf = vf;
7927 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7928 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7929 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7930 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7931 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7932 return 0;
7933}
7934
4ae196df
AD		 7935static void igb_vmm_control(struct igb_adapter *adapter)
7936{
7937 struct e1000_hw *hw = &adapter->hw;
10d8e907 7938 u32 reg;
4ae196df 7939
52a1dd4d
AD		 7940 switch (hw->mac.type) {
7941 case e1000_82575:
f96a8a0b
CW		 7942 case e1000_i210:
7943 case e1000_i211:
ceb5f13b 7944 case e1000_i354:
52a1dd4d
AD		 7945 default:
7946 /* replication is not supported for 82575 */
4ae196df 7947 return;
52a1dd4d
AD		 7948 case e1000_82576:
7949 /* notify HW that the MAC is adding vlan tags */
7950 reg = rd32(E1000_DTXCTL);
7951 reg |= E1000_DTXCTL_VLAN_ADDED;
7952 wr32(E1000_DTXCTL, reg);
7953 case e1000_82580:
7954 /* enable replication vlan tag stripping */
7955 reg = rd32(E1000_RPLOLR);
7956 reg |= E1000_RPLOLR_STRVLAN;
7957 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7958 case e1000_i350:
7959 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7960 break;
7961 }
10d8e907 7962
d4960307
AD		 7963 if (adapter->vfs_allocated_count) {
7964 igb_vmdq_set_loopback_pf(hw, true);
7965 igb_vmdq_set_replication_pf(hw, true);
13800469 7966 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7967 adapter->vfs_allocated_count);
d4960307
AD		 7968 } else {
7969 igb_vmdq_set_loopback_pf(hw, false);
7970 igb_vmdq_set_replication_pf(hw, false);
7971 }
4ae196df
AD		 7972}
7973
b6e0c419
CW		 7974static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7975{
7976 struct e1000_hw *hw = &adapter->hw;
7977 u32 dmac_thr;
7978 u16 hwm;
7979
7980 if (hw->mac.type > e1000_82580) {
7981 if (adapter->flags & IGB_FLAG_DMAC) {
7982 u32 reg;
7983
7984 /* force threshold to 0. */
7985 wr32(E1000_DMCTXTH, 0);
7986
b980ac18 7987 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7988 * than the Rx threshold. Set hwm to PBA - max frame
7989 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7990 */
e8c626e9
MV		 7991 hwm = 64 * pba - adapter->max_frame_size / 16;
7992 if (hwm < 64 * (pba - 6))
7993 hwm = 64 * (pba - 6);
7994 reg = rd32(E1000_FCRTC);
7995 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7996 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7997 & E1000_FCRTC_RTH_COAL_MASK);
7998 wr32(E1000_FCRTC, reg);
7999
b980ac18 8000 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8001 * frame size, capping it at PBA - 10KB.
8002 */
8003 dmac_thr = pba - adapter->max_frame_size / 512;
8004 if (dmac_thr < pba - 10)
8005 dmac_thr = pba - 10;
b6e0c419
CW		 8006 reg = rd32(E1000_DMACR);
8007 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8008 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8009 & E1000_DMACR_DMACTHR_MASK);
8010
8011 /* transition to L0x or L1 if available..*/
8012 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8013
8014 /* watchdog timer= +-1000 usec in 32usec intervals */
8015 reg |= (1000 >> 5);
0c02dd98
MV		 8016
8017 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8018 if (hw->mac.type != e1000_i354)
8019 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8020
b6e0c419
CW		 8021 wr32(E1000_DMACR, reg);
8022
b980ac18 8023 /* no lower threshold to disable
b6e0c419
CW		 8024 * coalescing(smart fifb)-UTRESH=0
8025 */
8026 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8027
8028 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8029
8030 wr32(E1000_DMCTLX, reg);
8031
b980ac18 8032 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8033 * DMA coal
8034 */
8035 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8036 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8037
b980ac18 8038 /* make low power state decision controlled
b6e0c419
CW		 8039 * by DMA coal
8040 */
8041 reg = rd32(E1000_PCIEMISC);
8042 reg &= ~E1000_PCIEMISC_LX_DECISION;
8043 wr32(E1000_PCIEMISC, reg);
8044 } /* endif adapter->dmac is not disabled */
8045 } else if (hw->mac.type == e1000_82580) {
8046 u32 reg = rd32(E1000_PCIEMISC);
8047 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8048 wr32(E1000_DMACR, 0);
8049 }
8050}
8051
b980ac18
JK		 8052/**
8053 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8054 * @hw: pointer to hardware structure
8055 * @byte_offset: byte offset to read
8056 * @dev_addr: device address
8057 * @data: value read
8058 *
8059 * Performs byte read operation over I2C interface at
8060 * a specified device address.
b980ac18 8061 **/
441fc6fd 8062s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8063 u8 dev_addr, u8 *data)
441fc6fd
CW		 8064{
8065 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8066 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8067 s32 status;
8068 u16 swfw_mask = 0;
8069
8070 if (!this_client)
8071 return E1000_ERR_I2C;
8072
8073 swfw_mask = E1000_SWFW_PHY0_SM;
8074
8075 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
8076 != E1000_SUCCESS)
8077 return E1000_ERR_SWFW_SYNC;
8078
8079 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8080 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8081
8082 if (status < 0)
8083 return E1000_ERR_I2C;
8084 else {
8085 *data = status;
8086 return E1000_SUCCESS;
8087 }
8088}
8089
b980ac18
JK		 8090/**
8091 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8092 * @hw: pointer to hardware structure
8093 * @byte_offset: byte offset to write
8094 * @dev_addr: device address
8095 * @data: value to write
8096 *
8097 * Performs byte write operation over I2C interface at
8098 * a specified device address.
b980ac18 8099 **/
441fc6fd 8100s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8101 u8 dev_addr, u8 data)
441fc6fd
CW		 8102{
8103 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8104 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8105 s32 status;
8106 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8107
8108 if (!this_client)
8109 return E1000_ERR_I2C;
8110
8111 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
8112 return E1000_ERR_SWFW_SYNC;
8113 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8114 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8115
8116 if (status)
8117 return E1000_ERR_I2C;
8118 else
8119 return E1000_SUCCESS;
8120
8121}
907b7835
LMV		 8122
8123int igb_reinit_queues(struct igb_adapter *adapter)
8124{
8125 struct net_device *netdev = adapter->netdev;
8126 struct pci_dev *pdev = adapter->pdev;
8127 int err = 0;
8128
8129 if (netif_running(netdev))
8130 igb_close(netdev);
8131
02ef6e1d 8132 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8133
8134 if (igb_init_interrupt_scheme(adapter, true)) {
8135 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8136 return -ENOMEM;
8137 }
8138
8139 if (netif_running(netdev))
8140 err = igb_open(netdev);
8141
8142 return err;
8143}
9d5c8243 8144/* igb_main.c */
Linux kernel - Deliverables
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