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igbvf: remove "link is Up" message when registering mcast address
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
6fb46902
TF		 60#define MIN 3
61#define BUILD 0
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
bf456abb 143static void igb_set_uta(struct igb_adapter *adapter, bool set);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
32b3e08f 154static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 184#endif
9d5c8243 185
9d5c8243 186#ifdef CONFIG_PM
d9dd966d 187#ifdef CONFIG_PM_SLEEP
749ab2cd 188static int igb_suspend(struct device *);
d9dd966d 189#endif
749ab2cd 190static int igb_resume(struct device *);
749ab2cd
YZ		 191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
52285b76 949 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 950
047e0030 951 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 952 igb_msix_other, 0, netdev->name, adapter);
047e0030 953 if (err)
52285b76 954 goto err_out;
047e0030
AD		 955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
52285b76
SA		 959 vector++;
960
7b06a690 961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 962
0ba82994 963 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
047e0030 967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
047e0030 970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 971 q_vector->rx.ring->queue_index);
9d5c8243 972 else
047e0030
AD		 973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
9d5c8243 975 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
9d5c8243 978 if (err)
52285b76 979 goto err_free;
9d5c8243
AK		 980 }
981
9d5c8243
AK		 982 igb_configure_msix(adapter);
983 return 0;
52285b76
SA		 984
985err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994err_out:
9d5c8243
AK		 995 return err;
996}
997
5536d210 998/**
b980ac18
JK		 999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
5536d210 1002 *
02ef6e1d 1003 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
02ef6e1d
CW		 1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
17a402a0
CW		 1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
cb06d102
CP		 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
5536d210
AD		 1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
2439fc4d 1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1041
5536d210
AD		 1042 netif_napi_del(&q_vector->napi);
1043
02ef6e1d
CW		 1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
cd14ef54 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1051 pci_disable_msix(adapter->pdev);
cd14ef54 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1053 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1057}
1058
047e0030 1059/**
b980ac18
JK		 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
047e0030 1062 *
b980ac18
JK		 1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
047e0030
AD		 1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
5536d210
AD		 1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
047e0030 1073 adapter->num_q_vectors = 0;
5536d210 1074
02ef6e1d
CW		 1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
5536d210 1077 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1078 }
047e0030
AD		 1079}
1080
1081/**
b980ac18
JK		 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
047e0030 1084 *
b980ac18
JK		 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
047e0030
AD		 1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
047e0030
AD		 1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
9d5c8243
AK		 1093
1094/**
b980ac18
JK		 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
9d5c8243 1098 *
b980ac18
JK		 1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
9d5c8243 1101 **/
53c7d064 1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1103{
1104 int err;
1105 int numvecs, i;
1106
53c7d064
SA		 1107 if (!msix)
1108 goto msi_only;
cd14ef54 1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1110
83b7180d 1111 /* Number of supported queues. */
a99955fc 1112 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1117
b980ac18 1118 /* start with one vector for every Rx queue */
047e0030
AD		 1119 numvecs = adapter->num_rx_queues;
1120
b980ac18 1121 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
047e0030
AD		 1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
9d5c8243
AK		 1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
479d02df
AG		 1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
0c2cc02e 1138 return;
9d5c8243
AK		 1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
b709323d 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1156 wrfl();
2a3abf6d
AD		 1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
4fc82adf 1161 adapter->vfs_allocated_count = 0;
a99955fc 1162 adapter->rss_queues = 1;
4fc82adf 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1164 adapter->num_rx_queues = 1;
661086df 1165 adapter->num_tx_queues = 1;
047e0030 1166 adapter->num_q_vectors = 1;
9d5c8243 1167 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1168 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1169}
1170
5536d210
AD		 1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
047e0030 1178/**
b980ac18
JK		 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
047e0030 1187 *
b980ac18 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1189 **/
5536d210
AD		 1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
047e0030
AD		 1194{
1195 struct igb_q_vector *q_vector;
5536d210
AD		 1196 struct igb_ring *ring;
1197 int ring_count, size;
047e0030 1198
5536d210
AD		 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
02ef6e1d 1208 q_vector = adapter->q_vector[v_idx];
72ddef05 1209 if (!q_vector) {
02ef6e1d 1210 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
c0a06ee1 1215 memset(q_vector, 0, size);
72ddef05 1216 }
5536d210
AD		 1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
7b06a690 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
4e227667
AD		 1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
5536d210
AD		 1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
827da44c
JS		 1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
5536d210
AD		 1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
047e0030 1276 }
81c2fc22 1277
5536d210
AD		 1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
047e0030 1282
5536d210
AD		 1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
047e0030 1285
5536d210
AD		 1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
047e0030 1288
5536d210
AD		 1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1292
e52c0f96 1293 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1294 * have the tag byte-swapped.
b980ac18 1295 */
5536d210
AD		 1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1298
5536d210
AD		 1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
827da44c
JS		 1303 u64_stats_init(&ring->rx_syncp);
1304
5536d210
AD		 1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
047e0030
AD		 1310}
1311
5536d210 1312
047e0030 1313/**
b980ac18
JK		 1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
047e0030 1316 *
b980ac18
JK		 1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
047e0030 1319 **/
5536d210 1320static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1321{
5536d210
AD		 1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
047e0030 1327
5536d210
AD		 1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
047e0030 1332
5536d210
AD		 1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
047e0030 1339 }
047e0030 1340 }
5536d210
AD		 1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1345
5536d210
AD		 1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
047e0030 1359 return 0;
5536d210
AD		 1360
1361err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
047e0030
AD		 1370}
1371
1372/**
b980ac18
JK		 1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
047e0030 1376 *
b980ac18 1377 * This function initializes the interrupts and allocates all of the queues.
047e0030 1378 **/
53c7d064 1379static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1380{
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
53c7d064 1384 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
5536d210 1392 igb_cache_ring_register(adapter);
047e0030
AD		 1393
1394 return 0;
5536d210 1395
047e0030
AD		 1396err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399}
1400
9d5c8243 1401/**
b980ac18
JK		 1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
9d5c8243 1404 *
b980ac18
JK		 1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
9d5c8243
AK		 1407 **/
1408static int igb_request_irq(struct igb_adapter *adapter)
1409{
1410 struct net_device *netdev = adapter->netdev;
047e0030 1411 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1412 int err = 0;
1413
cd14ef54 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1415 err = igb_request_msix(adapter);
844290e5 1416 if (!err)
9d5c8243 1417 goto request_done;
9d5c8243 1418 /* fall back to MSI */
5536d210
AD		 1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
53c7d064 1421
047e0030 1422 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
047e0030 1425 goto request_done;
53c7d064 1426
047e0030
AD		 1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
53c7d064 1429 igb_configure(adapter);
9d5c8243 1430 }
844290e5 1431
c74d588e
AD		 1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
7dfc16fa 1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1436 netdev->name, adapter);
9d5c8243
AK		 1437 if (!err)
1438 goto request_done;
047e0030 1439
9d5c8243
AK		 1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
7dfc16fa 1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1443 }
1444
c74d588e 1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1446 netdev->name, adapter);
9d5c8243 1447
6cb5e577 1448 if (err)
c74d588e 1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1450 err);
9d5c8243
AK		 1451
1452request_done:
1453 return err;
1454}
1455
1456static void igb_free_irq(struct igb_adapter *adapter)
1457{
cd14ef54 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1459 int vector = 0, i;
1460
047e0030 1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1462
0d1ae7f4 1463 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1464 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1465 adapter->q_vector[i]);
047e0030
AD		 1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1468 }
9d5c8243
AK		 1469}
1470
1471/**
b980ac18
JK		 1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
9d5c8243
AK		 1474 **/
1475static void igb_irq_disable(struct igb_adapter *adapter)
1476{
1477 struct e1000_hw *hw = &adapter->hw;
1478
b980ac18 1479 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
cd14ef54 1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1484 u32 regval = rd32(E1000_EIAM);
9005df38 1485
2dfd1212
AD		 1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1490 }
844290e5
PW		 1491
1492 wr32(E1000_IAM, 0);
9d5c8243
AK		 1493 wr32(E1000_IMC, ~0);
1494 wrfl();
cd14ef54 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1496 int i;
9005df38 1497
81a61859
ET		 1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
9d5c8243
AK		 1503}
1504
1505/**
b980ac18
JK		 1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
9d5c8243
AK		 1508 **/
1509static void igb_irq_enable(struct igb_adapter *adapter)
1510{
1511 struct e1000_hw *hw = &adapter->hw;
1512
cd14ef54 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1515 u32 regval = rd32(E1000_EIAC);
9005df38 1516
2dfd1212
AD		 1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1521 if (adapter->vfs_allocated_count) {
4ae196df 1522 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
844290e5 1526 } else {
55cac248
AD		 1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
844290e5 1531 }
9d5c8243
AK		 1532}
1533
1534static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535{
51466239 1536 struct e1000_hw *hw = &adapter->hw;
8b77c6b2 1537 u16 pf_id = adapter->vfs_allocated_count;
9d5c8243
AK		 1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
8b77c6b2 1543 igb_vfta_set(hw, vid, pf_id, true, true);
51466239
AD		 1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
b2cb09b1 1551 !test_bit(old_vid, adapter->active_vlans)) {
51466239 1552 /* remove VID from filter table */
8b77c6b2 1553 igb_vfta_set(hw, vid, pf_id, false, true);
9d5c8243
AK		 1554 }
1555}
1556
1557/**
b980ac18
JK		 1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
9d5c8243 1560 *
b980ac18
JK		 1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
9d5c8243
AK		 1564 **/
1565static void igb_release_hw_control(struct igb_adapter *adapter)
1566{
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574}
1575
9d5c8243 1576/**
b980ac18
JK		 1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
9d5c8243 1579 *
b980ac18
JK		 1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
9d5c8243
AK		 1583 **/
1584static void igb_get_hw_control(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593}
1594
9d5c8243 1595/**
b980ac18
JK		 1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
9d5c8243
AK		 1598 **/
1599static void igb_configure(struct igb_adapter *adapter)
1600{
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
ff41f8dc 1605 igb_set_rx_mode(netdev);
9d5c8243
AK		 1606
1607 igb_restore_vlan(adapter);
9d5c8243 1608
85b430b4 1609 igb_setup_tctl(adapter);
06cf2666 1610 igb_setup_mrqc(adapter);
9d5c8243 1611 igb_setup_rctl(adapter);
85b430b4
AD		 1612
1613 igb_configure_tx(adapter);
9d5c8243 1614 igb_configure_rx(adapter);
662d7205
AD		 1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
c493ea45 1618 /* call igb_desc_unused which always leaves
9d5c8243 1619 * at least 1 descriptor unused to make sure
b980ac18
JK		 1620 * next_to_use != next_to_clean
1621 */
9d5c8243 1622 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1623 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1625 }
9d5c8243
AK		 1626}
1627
88a268c1 1628/**
b980ac18
JK		 1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
88a268c1
NN		 1631 **/
1632void igb_power_up_link(struct igb_adapter *adapter)
1633{
76886596
AA		 1634 igb_reset_phy(&adapter->hw);
1635
88a268c1
NN		 1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1640
1641 igb_setup_link(&adapter->hw);
88a268c1
NN		 1642}
1643
1644/**
b980ac18
JK		 1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
88a268c1
NN		 1647 */
1648static void igb_power_down_link(struct igb_adapter *adapter)
1649{
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654}
9d5c8243 1655
56cec249
CW		 1656/**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660static void igb_check_swap_media(struct igb_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721}
1722
9d5c8243 1723/**
b980ac18
JK		 1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
9d5c8243 1726 **/
9d5c8243
AK		 1727int igb_up(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
0d1ae7f4
AD		 1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
cd14ef54 1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1741 igb_configure_msix(adapter);
feeb2721
AD		 1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
d4960307
AD		 1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1752
d4960307
AD		 1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
4cb9be7a
JB		 1757 netif_tx_start_all_queues(adapter->netdev);
1758
25568a53
AD		 1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
f4c01e96
CW		 1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
9d5c8243
AK		 1767 return 0;
1768}
1769
1770void igb_down(struct igb_adapter *adapter)
1771{
9d5c8243 1772 struct net_device *netdev = adapter->netdev;
330a6d6a 1773 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1778 * reschedule our watchdog timer
1779 */
9d5c8243
AK		 1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
f28ea083 1787 netif_carrier_off(netdev);
fd2ea0a7 1788 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
0d451e79 1796 usleep_range(10000, 11000);
9d5c8243 1797
41f149a2
CW		 1798 igb_irq_disable(adapter);
1799
aa9b8cc4
AA		 1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
41f149a2 1802 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
41f149a2 1807 }
9d5c8243 1808
9d5c8243
AK		 1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
04fe6358 1812 /* record the stats before reset*/
12dcd86b
ED		 1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
04fe6358 1816
9d5c8243
AK		 1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
3023682e
JK		 1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
16903caa
AD		 1822
1823 /* clear VLAN promisc flag so VFTA will be updated if necessary */
1824 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
1825
9d5c8243
AK		 1826 igb_clean_all_tx_rings(adapter);
1827 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1828#ifdef CONFIG_IGB_DCA
1829
1830 /* since we reset the hardware DCA settings were cleared */
1831 igb_setup_dca(adapter);
1832#endif
9d5c8243
AK		 1833}
1834
1835void igb_reinit_locked(struct igb_adapter *adapter)
1836{
1837 WARN_ON(in_interrupt());
1838 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1839 usleep_range(1000, 2000);
9d5c8243
AK		 1840 igb_down(adapter);
1841 igb_up(adapter);
1842 clear_bit(__IGB_RESETTING, &adapter->state);
1843}
1844
56cec249
CW		 1845/** igb_enable_mas - Media Autosense re-enable after swap
1846 *
1847 * @adapter: adapter struct
1848 **/
8cfb879d 1849static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1850{
1851 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1852 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1853
1854 /* configure for SerDes media detect */
8cfb879d
TF		 1855 if ((hw->phy.media_type == e1000_media_type_copper) &&
1856 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1857 connsw |= E1000_CONNSW_ENRGSRC;
1858 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1859 wr32(E1000_CONNSW, connsw);
1860 wrfl();
56cec249 1861 }
56cec249
CW		 1862}
1863
9d5c8243
AK		 1864void igb_reset(struct igb_adapter *adapter)
1865{
090b1795 1866 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1867 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1868 struct e1000_mac_info *mac = &hw->mac;
1869 struct e1000_fc_info *fc = &hw->fc;
45693bcb 1870 u32 pba, hwm;
9d5c8243
AK		 1871
1872 /* Repartition Pba for greater than 9k mtu
1873 * To take effect CTRL.RST is required.
1874 */
fa4dfae0 1875 switch (mac->type) {
d2ba2ed8 1876 case e1000_i350:
ceb5f13b 1877 case e1000_i354:
55cac248
AD		 1878 case e1000_82580:
1879 pba = rd32(E1000_RXPBS);
1880 pba = igb_rxpbs_adjust_82580(pba);
1881 break;
fa4dfae0 1882 case e1000_82576:
d249be54
AD		 1883 pba = rd32(E1000_RXPBS);
1884 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1885 break;
1886 case e1000_82575:
f96a8a0b
CW		 1887 case e1000_i210:
1888 case e1000_i211:
fa4dfae0
AD		 1889 default:
1890 pba = E1000_PBA_34K;
1891 break;
2d064c06 1892 }
9d5c8243 1893
45693bcb
AD		 1894 if (mac->type == e1000_82575) {
1895 u32 min_rx_space, min_tx_space, needed_tx_space;
1896
1897 /* write Rx PBA so that hardware can report correct Tx PBA */
9d5c8243
AK		 1898 wr32(E1000_PBA, pba);
1899
1900 /* To maintain wire speed transmits, the Tx FIFO should be
1901 * large enough to accommodate two full transmit packets,
1902 * rounded up to the next 1KB and expressed in KB. Likewise,
1903 * the Rx FIFO should be large enough to accommodate at least
1904 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1905 * expressed in KB.
1906 */
45693bcb
AD		 1907 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
1908
1909 /* The Tx FIFO also stores 16 bytes of information about the Tx
1910 * but don't include Ethernet FCS because hardware appends it.
1911 * We only need to round down to the nearest 512 byte block
1912 * count since the value we care about is 2 frames, not 1.
b980ac18 1913 */
45693bcb
AD		 1914 min_tx_space = adapter->max_frame_size;
1915 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
1916 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
1917
1918 /* upper 16 bits has Tx packet buffer allocation size in KB */
1919 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
9d5c8243
AK		 1920
1921 /* If current Tx allocation is less than the min Tx FIFO size,
1922 * and the min Tx FIFO size is less than the current Rx FIFO
45693bcb 1923 * allocation, take space away from current Rx allocation.
b980ac18 1924 */
45693bcb
AD		 1925 if (needed_tx_space < pba) {
1926 pba -= needed_tx_space;
9d5c8243 1927
b980ac18
JK		 1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
9d5c8243
AK		 1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
45693bcb
AD		 1934
1935 /* adjust PBA for jumbo frames */
2d064c06 1936 wr32(E1000_PBA, pba);
9d5c8243 1937 }
9d5c8243 1938
45693bcb
AD		 1939 /* flow control settings
1940 * The high water mark must be low enough to fit one full frame
1941 * after transmitting the pause frame. As such we must have enough
1942 * space to allow for us to complete our current transmit and then
1943 * receive the frame that is in progress from the link partner.
1944 * Set it to:
1945 * - the full Rx FIFO size minus one full Tx plus one full Rx frame
b980ac18 1946 */
45693bcb 1947 hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
9d5c8243 1948
d48507fe 1949 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1950 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1951 fc->pause_time = 0xFFFF;
1952 fc->send_xon = 1;
0cce119a 1953 fc->current_mode = fc->requested_mode;
9d5c8243 1954
4ae196df
AD		 1955 /* disable receive for all VFs and wait one second */
1956 if (adapter->vfs_allocated_count) {
1957 int i;
9005df38 1958
4ae196df 1959 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1960 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1961
1962 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1963 igb_ping_all_vfs(adapter);
4ae196df
AD		 1964
1965 /* disable transmits and receives */
1966 wr32(E1000_VFRE, 0);
1967 wr32(E1000_VFTE, 0);
1968 }
1969
9d5c8243 1970 /* Allow time for pending master requests to run */
330a6d6a 1971 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1972 wr32(E1000_WUC, 0);
1973
56cec249
CW		 1974 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1975 /* need to resetup here after media swap */
1976 adapter->ei.get_invariants(hw);
1977 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1978 }
8cfb879d
TF		 1979 if ((mac->type == e1000_82575) &&
1980 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1981 igb_enable_mas(adapter);
56cec249 1982 }
330a6d6a 1983 if (hw->mac.ops.init_hw(hw))
090b1795 1984 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1985
b980ac18 1986 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1987 * control is off when forcing speed.
1988 */
1989 if (!hw->mac.autoneg)
1990 igb_force_mac_fc(hw);
1991
b6e0c419 1992 igb_init_dmac(adapter, pba);
e428893b
CW		 1993#ifdef CONFIG_IGB_HWMON
1994 /* Re-initialize the thermal sensor on i350 devices. */
1995 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1996 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1997 /* If present, re-initialize the external thermal sensor
1998 * interface.
1999 */
2000 if (adapter->ets)
2001 mac->ops.init_thermal_sensor_thresh(hw);
2002 }
2003 }
2004#endif
b936136d 2005 /* Re-establish EEE setting */
f4c01e96
CW		 2006 if (hw->phy.media_type == e1000_media_type_copper) {
2007 switch (mac->type) {
2008 case e1000_i350:
2009 case e1000_i210:
2010 case e1000_i211:
c4c112f1 2011 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2012 break;
2013 case e1000_i354:
c4c112f1 2014 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2015 break;
2016 default:
2017 break;
2018 }
2019 }
88a268c1
NN		 2020 if (!netif_running(adapter->netdev))
2021 igb_power_down_link(adapter);
2022
9d5c8243
AK		 2023 igb_update_mng_vlan(adapter);
2024
2025 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2026 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2027
1f6e8178
MV		 2028 /* Re-enable PTP, where applicable. */
2029 igb_ptp_reset(adapter);
1f6e8178 2030
330a6d6a 2031 igb_get_phy_info(hw);
9d5c8243
AK		 2032}
2033
c8f44aff
MM		 2034static netdev_features_t igb_fix_features(struct net_device *netdev,
2035 netdev_features_t features)
b2cb09b1 2036{
b980ac18
JK		 2037 /* Since there is no support for separate Rx/Tx vlan accel
2038 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2039 */
f646968f
PM		 2040 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2041 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2042 else
f646968f 2043 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2044
2045 return features;
2046}
2047
c8f44aff
MM		 2048static int igb_set_features(struct net_device *netdev,
2049 netdev_features_t features)
ac52caa3 2050{
c8f44aff 2051 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2052 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2053
f646968f 2054 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2055 igb_vlan_mode(netdev, features);
2056
16903caa 2057 if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
89eaefb6
BG		 2058 return 0;
2059
2060 netdev->features = features;
2061
2062 if (netif_running(netdev))
2063 igb_reinit_locked(adapter);
2064 else
2065 igb_reset(adapter);
2066
ac52caa3
MM		 2067 return 0;
2068}
2069
268f9d33
AD		 2070static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2071 struct net_device *dev,
2072 const unsigned char *addr, u16 vid,
2073 u16 flags)
2074{
2075 /* guarantee we can provide a unique filter for the unicast address */
2076 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2077 struct igb_adapter *adapter = netdev_priv(dev);
2078 struct e1000_hw *hw = &adapter->hw;
2079 int vfn = adapter->vfs_allocated_count;
2080 int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
2081
2082 if (netdev_uc_count(dev) >= rar_entries)
2083 return -ENOMEM;
2084 }
2085
2086 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2087}
2088
2e5c6922 2089static const struct net_device_ops igb_netdev_ops = {
559e9c49 2090 .ndo_open = igb_open,
2e5c6922 2091 .ndo_stop = igb_close,
cd392f5c 2092 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2093 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2094 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2095 .ndo_set_mac_address = igb_set_mac,
2096 .ndo_change_mtu = igb_change_mtu,
2097 .ndo_do_ioctl = igb_ioctl,
2098 .ndo_tx_timeout = igb_tx_timeout,
2099 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2100 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2101 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2102 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2103 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2104 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2105 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2106 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2107#ifdef CONFIG_NET_POLL_CONTROLLER
2108 .ndo_poll_controller = igb_netpoll,
2109#endif
b2cb09b1
JP		 2110 .ndo_fix_features = igb_fix_features,
2111 .ndo_set_features = igb_set_features,
268f9d33 2112 .ndo_fdb_add = igb_ndo_fdb_add,
1abbc98a 2113 .ndo_features_check = passthru_features_check,
2e5c6922
SH		 2114};
2115
d67974f0
CW		 2116/**
2117 * igb_set_fw_version - Configure version string for ethtool
2118 * @adapter: adapter struct
d67974f0
CW		 2119 **/
2120void igb_set_fw_version(struct igb_adapter *adapter)
2121{
2122 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2123 struct e1000_fw_version fw;
2124
2125 igb_get_fw_version(hw, &fw);
2126
2127 switch (hw->mac.type) {
7dc98a62 2128 case e1000_i210:
0b1a6f2e 2129 case e1000_i211:
7dc98a62
CW		 2130 if (!(igb_get_flash_presence_i210(hw))) {
2131 snprintf(adapter->fw_version,
2132 sizeof(adapter->fw_version),
2133 "%2d.%2d-%d",
2134 fw.invm_major, fw.invm_minor,
2135 fw.invm_img_type);
2136 break;
2137 }
2138 /* fall through */
0b1a6f2e
CW		 2139 default:
2140 /* if option is rom valid, display its version too */
2141 if (fw.or_valid) {
2142 snprintf(adapter->fw_version,
2143 sizeof(adapter->fw_version),
2144 "%d.%d, 0x%08x, %d.%d.%d",
2145 fw.eep_major, fw.eep_minor, fw.etrack_id,
2146 fw.or_major, fw.or_build, fw.or_patch);
2147 /* no option rom */
7dc98a62 2148 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2149 snprintf(adapter->fw_version,
7dc98a62
CW		 2150 sizeof(adapter->fw_version),
2151 "%d.%d, 0x%08x",
2152 fw.eep_major, fw.eep_minor, fw.etrack_id);
2153 } else {
2154 snprintf(adapter->fw_version,
2155 sizeof(adapter->fw_version),
2156 "%d.%d.%d",
2157 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2158 }
2159 break;
d67974f0 2160 }
d67974f0
CW		 2161}
2162
56cec249
CW		 2163/**
2164 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2165 *
2166 * @adapter: adapter struct
2167 **/
2168static void igb_init_mas(struct igb_adapter *adapter)
2169{
2170 struct e1000_hw *hw = &adapter->hw;
2171 u16 eeprom_data;
2172
2173 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2174 switch (hw->bus.func) {
2175 case E1000_FUNC_0:
2176 if (eeprom_data & IGB_MAS_ENABLE_0) {
2177 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2178 netdev_info(adapter->netdev,
2179 "MAS: Enabling Media Autosense for port %d\n",
2180 hw->bus.func);
2181 }
2182 break;
2183 case E1000_FUNC_1:
2184 if (eeprom_data & IGB_MAS_ENABLE_1) {
2185 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2186 netdev_info(adapter->netdev,
2187 "MAS: Enabling Media Autosense for port %d\n",
2188 hw->bus.func);
2189 }
2190 break;
2191 case E1000_FUNC_2:
2192 if (eeprom_data & IGB_MAS_ENABLE_2) {
2193 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2194 netdev_info(adapter->netdev,
2195 "MAS: Enabling Media Autosense for port %d\n",
2196 hw->bus.func);
2197 }
2198 break;
2199 case E1000_FUNC_3:
2200 if (eeprom_data & IGB_MAS_ENABLE_3) {
2201 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2202 netdev_info(adapter->netdev,
2203 "MAS: Enabling Media Autosense for port %d\n",
2204 hw->bus.func);
2205 }
2206 break;
2207 default:
2208 /* Shouldn't get here */
2209 netdev_err(adapter->netdev,
2210 "MAS: Invalid port configuration, returning\n");
2211 break;
2212 }
2213}
2214
b980ac18
JK		 2215/**
2216 * igb_init_i2c - Init I2C interface
441fc6fd 2217 * @adapter: pointer to adapter structure
b980ac18 2218 **/
441fc6fd
CW		 2219static s32 igb_init_i2c(struct igb_adapter *adapter)
2220{
23d87824 2221 s32 status = 0;
441fc6fd
CW		 2222
2223 /* I2C interface supported on i350 devices */
2224 if (adapter->hw.mac.type != e1000_i350)
23d87824 2225 return 0;
441fc6fd
CW		 2226
2227 /* Initialize the i2c bus which is controlled by the registers.
2228 * This bus will use the i2c_algo_bit structue that implements
2229 * the protocol through toggling of the 4 bits in the register.
2230 */
2231 adapter->i2c_adap.owner = THIS_MODULE;
2232 adapter->i2c_algo = igb_i2c_algo;
2233 adapter->i2c_algo.data = adapter;
2234 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2235 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2236 strlcpy(adapter->i2c_adap.name, "igb BB",
2237 sizeof(adapter->i2c_adap.name));
2238 status = i2c_bit_add_bus(&adapter->i2c_adap);
2239 return status;
2240}
2241
9d5c8243 2242/**
b980ac18
JK		 2243 * igb_probe - Device Initialization Routine
2244 * @pdev: PCI device information struct
2245 * @ent: entry in igb_pci_tbl
9d5c8243 2246 *
b980ac18 2247 * Returns 0 on success, negative on failure
9d5c8243 2248 *
b980ac18
JK		 2249 * igb_probe initializes an adapter identified by a pci_dev structure.
2250 * The OS initialization, configuring of the adapter private structure,
2251 * and a hardware reset occur.
9d5c8243 2252 **/
1dd06ae8 2253static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2254{
2255 struct net_device *netdev;
2256 struct igb_adapter *adapter;
2257 struct e1000_hw *hw;
4337e993 2258 u16 eeprom_data = 0;
9835fd73 2259 s32 ret_val;
4337e993 2260 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2261 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2262 int err, pci_using_dac;
9835fd73 2263 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2264
bded64a7
AG		 2265 /* Catch broken hardware that put the wrong VF device ID in
2266 * the PCIe SR-IOV capability.
2267 */
2268 if (pdev->is_virtfn) {
2269 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2270 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2271 return -EINVAL;
2272 }
2273
aed5dec3 2274 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2275 if (err)
2276 return err;
2277
2278 pci_using_dac = 0;
dc4ff9bb 2279 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2280 if (!err) {
dc4ff9bb 2281 pci_using_dac = 1;
9d5c8243 2282 } else {
dc4ff9bb 2283 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2284 if (err) {
dc4ff9bb
RK		 2285 dev_err(&pdev->dev,
2286 "No usable DMA configuration, aborting\n");
2287 goto err_dma;
9d5c8243
AK		 2288 }
2289 }
2290
aed5dec3 2291 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2292 IORESOURCE_MEM),
2293 igb_driver_name);
9d5c8243
AK		 2294 if (err)
2295 goto err_pci_reg;
2296
19d5afd4 2297 pci_enable_pcie_error_reporting(pdev);
40a914fa 2298
9d5c8243 2299 pci_set_master(pdev);
c682fc23 2300 pci_save_state(pdev);
9d5c8243
AK		 2301
2302 err = -ENOMEM;
1bfaf07b 2303 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2304 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2305 if (!netdev)
2306 goto err_alloc_etherdev;
2307
2308 SET_NETDEV_DEV(netdev, &pdev->dev);
2309
2310 pci_set_drvdata(pdev, netdev);
2311 adapter = netdev_priv(netdev);
2312 adapter->netdev = netdev;
2313 adapter->pdev = pdev;
2314 hw = &adapter->hw;
2315 hw->back = adapter;
b3f4d599 2316 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2317
9d5c8243 2318 err = -EIO;
73bf8048
JW		 2319 adapter->io_addr = pci_iomap(pdev, 0, 0);
2320 if (!adapter->io_addr)
9d5c8243 2321 goto err_ioremap;
73bf8048
JW		 2322 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2323 hw->hw_addr = adapter->io_addr;
9d5c8243 2324
2e5c6922 2325 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2326 igb_set_ethtool_ops(netdev);
9d5c8243 2327 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2328
2329 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2330
89dbefb2
AS		 2331 netdev->mem_start = pci_resource_start(pdev, 0);
2332 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2333
9d5c8243
AK		 2334 /* PCI config space info */
2335 hw->vendor_id = pdev->vendor;
2336 hw->device_id = pdev->device;
2337 hw->revision_id = pdev->revision;
2338 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2339 hw->subsystem_device_id = pdev->subsystem_device;
2340
9d5c8243
AK		 2341 /* Copy the default MAC, PHY and NVM function pointers */
2342 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2343 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2344 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2345 /* Initialize skew-specific constants */
2346 err = ei->get_invariants(hw);
2347 if (err)
450c87c8 2348 goto err_sw_init;
9d5c8243 2349
450c87c8 2350 /* setup the private structure */
9d5c8243
AK		 2351 err = igb_sw_init(adapter);
2352 if (err)
2353 goto err_sw_init;
2354
2355 igb_get_bus_info_pcie(hw);
2356
2357 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2358
2359 /* Copper options */
2360 if (hw->phy.media_type == e1000_media_type_copper) {
2361 hw->phy.mdix = AUTO_ALL_MODES;
2362 hw->phy.disable_polarity_correction = false;
2363 hw->phy.ms_type = e1000_ms_hw_default;
2364 }
2365
2366 if (igb_check_reset_block(hw))
2367 dev_info(&pdev->dev,
2368 "PHY reset is blocked due to SOL/IDER session.\n");
2369
b980ac18 2370 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2371 * set by igb_sw_init so we should use an or instead of an
2372 * assignment.
2373 */
2374 netdev->features |= NETIF_F_SG |
077887c3
AD		 2375 NETIF_F_TSO |
2376 NETIF_F_TSO6 |
2377 NETIF_F_RXHASH |
2378 NETIF_F_RXCSUM |
6e033700 2379 NETIF_F_HW_CSUM |
f646968f
PM		 2380 NETIF_F_HW_VLAN_CTAG_RX |
2381 NETIF_F_HW_VLAN_CTAG_TX;
077887c3 2382
6e033700
AD		 2383 if (hw->mac.type >= e1000_82576)
2384 netdev->features |= NETIF_F_SCTP_CRC;
2385
077887c3
AD		 2386 /* copy netdev features into list of user selectable features */
2387 netdev->hw_features |= netdev->features;
89eaefb6 2388 netdev->hw_features |= NETIF_F_RXALL;
077887c3 2389
6e033700
AD		 2390 if (hw->mac.type >= e1000_i350)
2391 netdev->hw_features |= NETIF_F_NTUPLE;
2392
077887c3 2393 /* set this bit last since it cannot be part of hw_features */
f646968f 2394 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3 2395
6e033700
AD		 2396 netdev->vlan_features |= NETIF_F_SG |
2397 NETIF_F_TSO |
077887c3 2398 NETIF_F_TSO6 |
6e033700
AD		 2399 NETIF_F_HW_CSUM |
2400 NETIF_F_SCTP_CRC;
2401
2402 netdev->mpls_features |= NETIF_F_HW_CSUM;
2403 netdev->hw_enc_features |= NETIF_F_HW_CSUM;
48f29ffc 2404
6b8f0922
BG		 2405 netdev->priv_flags |= IFF_SUPP_NOFCS;
2406
7b872a55 2407 if (pci_using_dac) {
9d5c8243 2408 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2409 netdev->vlan_features |= NETIF_F_HIGHDMA;
2410 }
9d5c8243 2411
01789349
JP		 2412 netdev->priv_flags |= IFF_UNICAST_FLT;
2413
330a6d6a 2414 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2415
2416 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2417 * known good starting state
2418 */
9d5c8243
AK		 2419 hw->mac.ops.reset_hw(hw);
2420
ef3a0092
CW		 2421 /* make sure the NVM is good , i211/i210 parts can have special NVM
2422 * that doesn't contain a checksum
f96a8a0b 2423 */
ef3a0092
CW		 2424 switch (hw->mac.type) {
2425 case e1000_i210:
2426 case e1000_i211:
2427 if (igb_get_flash_presence_i210(hw)) {
2428 if (hw->nvm.ops.validate(hw) < 0) {
2429 dev_err(&pdev->dev,
2430 "The NVM Checksum Is Not Valid\n");
2431 err = -EIO;
2432 goto err_eeprom;
2433 }
2434 }
2435 break;
2436 default:
f96a8a0b
CW		 2437 if (hw->nvm.ops.validate(hw) < 0) {
2438 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2439 err = -EIO;
2440 goto err_eeprom;
2441 }
ef3a0092 2442 break;
9d5c8243
AK		 2443 }
2444
2445 /* copy the MAC address out of the NVM */
2446 if (hw->mac.ops.read_mac_addr(hw))
2447 dev_err(&pdev->dev, "NVM Read Error\n");
2448
2449 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2450
aaeb6cdf 2451 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2452 dev_err(&pdev->dev, "Invalid MAC Address\n");
2453 err = -EIO;
2454 goto err_eeprom;
2455 }
2456
d67974f0
CW		 2457 /* get firmware version for ethtool -i */
2458 igb_set_fw_version(adapter);
2459
27dff8b2
TF		 2460 /* configure RXPBSIZE and TXPBSIZE */
2461 if (hw->mac.type == e1000_i210) {
2462 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2463 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2464 }
2465
c061b18d 2466 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2467 (unsigned long) adapter);
c061b18d 2468 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2469 (unsigned long) adapter);
9d5c8243
AK		 2470
2471 INIT_WORK(&adapter->reset_task, igb_reset_task);
2472 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2473
450c87c8 2474 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2475 adapter->fc_autoneg = true;
2476 hw->mac.autoneg = true;
2477 hw->phy.autoneg_advertised = 0x2f;
2478
0cce119a
AD		 2479 hw->fc.requested_mode = e1000_fc_default;
2480 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2481
9d5c8243
AK		 2482 igb_validate_mdi_setting(hw);
2483
63d4a8f9 2484 /* By default, support wake on port A */
a2cf8b6c 2485 if (hw->bus.func == 0)
63d4a8f9
MV		 2486 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2487
2488 /* Check the NVM for wake support on non-port A ports */
2489 if (hw->mac.type >= e1000_82580)
55cac248 2490 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2491 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2492 &eeprom_data);
a2cf8b6c
AD		 2493 else if (hw->bus.func == 1)
2494 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2495
63d4a8f9
MV		 2496 if (eeprom_data & IGB_EEPROM_APME)
2497 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2498
2499 /* now that we have the eeprom settings, apply the special cases where
2500 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2501 * lan on a particular port
2502 */
9d5c8243
AK		 2503 switch (pdev->device) {
2504 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2505 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2506 break;
2507 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2508 case E1000_DEV_ID_82576_FIBER:
2509 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2510 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2511 * regardless of eeprom setting
2512 */
9d5c8243 2513 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2514 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2515 break;
c8ea5ea9 2516 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2517 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2518 /* if quad port adapter, disable WoL on all but port A */
2519 if (global_quad_port_a != 0)
63d4a8f9 2520 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2521 else
2522 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2523 /* Reset for multiple quad port adapters */
2524 if (++global_quad_port_a == 4)
2525 global_quad_port_a = 0;
2526 break;
63d4a8f9
MV		 2527 default:
2528 /* If the device can't wake, don't set software support */
2529 if (!device_can_wakeup(&adapter->pdev->dev))
2530 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2531 }
2532
2533 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2534 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2535 adapter->wol |= E1000_WUFC_MAG;
2536
2537 /* Some vendors want WoL disabled by default, but still supported */
2538 if ((hw->mac.type == e1000_i350) &&
2539 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2540 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2541 adapter->wol = 0;
2542 }
2543
5e350b92
TF		 2544 /* Some vendors want the ability to Use the EEPROM setting as
2545 * enable/disable only, and not for capability
2546 */
2547 if (((hw->mac.type == e1000_i350) ||
2548 (hw->mac.type == e1000_i354)) &&
2549 (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
2550 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2551 adapter->wol = 0;
2552 }
2553 if (hw->mac.type == e1000_i350) {
2554 if (((pdev->subsystem_device == 0x5001) ||
2555 (pdev->subsystem_device == 0x5002)) &&
2556 (hw->bus.func == 0)) {
2557 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2558 adapter->wol = 0;
2559 }
2560 if (pdev->subsystem_device == 0x1F52)
2561 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2562 }
2563
63d4a8f9
MV		 2564 device_set_wakeup_enable(&adapter->pdev->dev,
2565 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2566
2567 /* reset the hardware with the new settings */
2568 igb_reset(adapter);
2569
441fc6fd
CW		 2570 /* Init the I2C interface */
2571 err = igb_init_i2c(adapter);
2572 if (err) {
2573 dev_err(&pdev->dev, "failed to init i2c interface\n");
2574 goto err_eeprom;
2575 }
2576
9d5c8243 2577 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2578 * driver.
2579 */
9d5c8243
AK		 2580 igb_get_hw_control(adapter);
2581
9d5c8243
AK		 2582 strcpy(netdev->name, "eth%d");
2583 err = register_netdev(netdev);
2584 if (err)
2585 goto err_register;
2586
b168dfc5
JB		 2587 /* carrier off reporting is important to ethtool even BEFORE open */
2588 netif_carrier_off(netdev);
2589
421e02f0 2590#ifdef CONFIG_IGB_DCA
bbd98fe4 2591 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2592 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2593 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2594 igb_setup_dca(adapter);
2595 }
fe4506b6 2596
38c845c7 2597#endif
e428893b
CW		 2598#ifdef CONFIG_IGB_HWMON
2599 /* Initialize the thermal sensor on i350 devices. */
2600 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2601 u16 ets_word;
3c89f6d0 2602
b980ac18 2603 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2604 * external thermal sensor.
2605 */
2606 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2607 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2608 adapter->ets = true;
2609 else
2610 adapter->ets = false;
2611 if (igb_sysfs_init(adapter))
2612 dev_err(&pdev->dev,
2613 "failed to allocate sysfs resources\n");
2614 } else {
2615 adapter->ets = false;
2616 }
2617#endif
56cec249
CW		 2618 /* Check if Media Autosense is enabled */
2619 adapter->ei = *ei;
2620 if (hw->dev_spec._82575.mas_capable)
2621 igb_init_mas(adapter);
2622
673b8b70 2623 /* do hw tstamp init after resetting */
7ebae817 2624 igb_ptp_init(adapter);
673b8b70 2625
9d5c8243 2626 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2627 /* print bus type/speed/width info, not applicable to i354 */
2628 if (hw->mac.type != e1000_i354) {
2629 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2630 netdev->name,
2631 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2632 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2633 "unknown"),
2634 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2635 "Width x4" :
2636 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2637 "Width x2" :
2638 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2639 "Width x1" : "unknown"), netdev->dev_addr);
2640 }
9d5c8243 2641
53ea6c7e
TF		 2642 if ((hw->mac.type >= e1000_i210 ||
2643 igb_get_flash_presence_i210(hw))) {
2644 ret_val = igb_read_part_string(hw, part_str,
2645 E1000_PBANUM_LENGTH);
2646 } else {
2647 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2648 }
2649
9835fd73
CW		 2650 if (ret_val)
2651 strcpy(part_str, "Unknown");
2652 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2653 dev_info(&pdev->dev,
2654 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2655 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2656 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2657 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2658 if (hw->phy.media_type == e1000_media_type_copper) {
2659 switch (hw->mac.type) {
2660 case e1000_i350:
2661 case e1000_i210:
2662 case e1000_i211:
2663 /* Enable EEE for internal copper PHY devices */
c4c112f1 2664 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2665 if ((!err) &&
2666 (!hw->dev_spec._82575.eee_disable)) {
2667 adapter->eee_advert =
2668 MDIO_EEE_100TX | MDIO_EEE_1000T;
2669 adapter->flags |= IGB_FLAG_EEE;
2670 }
2671 break;
2672 case e1000_i354:
ceb5f13b 2673 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2674 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2675 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2676 if ((!err) &&
2677 (!hw->dev_spec._82575.eee_disable)) {
2678 adapter->eee_advert =
2679 MDIO_EEE_100TX | MDIO_EEE_1000T;
2680 adapter->flags |= IGB_FLAG_EEE;
2681 }
2682 }
2683 break;
2684 default:
2685 break;
ceb5f13b 2686 }
09b068d4 2687 }
749ab2cd 2688 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2689 return 0;
2690
2691err_register:
2692 igb_release_hw_control(adapter);
441fc6fd 2693 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2694err_eeprom:
2695 if (!igb_check_reset_block(hw))
f5f4cf08 2696 igb_reset_phy(hw);
9d5c8243
AK		 2697
2698 if (hw->flash_address)
2699 iounmap(hw->flash_address);
9d5c8243 2700err_sw_init:
42ad1a03 2701 kfree(adapter->shadow_vfta);
047e0030 2702 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2703#ifdef CONFIG_PCI_IOV
2704 igb_disable_sriov(pdev);
2705#endif
73bf8048 2706 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2707err_ioremap:
2708 free_netdev(netdev);
2709err_alloc_etherdev:
559e9c49 2710 pci_release_selected_regions(pdev,
b980ac18 2711 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2712err_pci_reg:
2713err_dma:
2714 pci_disable_device(pdev);
2715 return err;
2716}
2717
fa44f2f1 2718#ifdef CONFIG_PCI_IOV
781798a1 2719static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2720{
2721 struct net_device *netdev = pci_get_drvdata(pdev);
2722 struct igb_adapter *adapter = netdev_priv(netdev);
2723 struct e1000_hw *hw = &adapter->hw;
2724
2725 /* reclaim resources allocated to VFs */
2726 if (adapter->vf_data) {
2727 /* disable iov and allow time for transactions to clear */
b09186d2 2728 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2729 dev_warn(&pdev->dev,
2730 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2731 return -EPERM;
2732 } else {
2733 pci_disable_sriov(pdev);
2734 msleep(500);
2735 }
2736
2737 kfree(adapter->vf_data);
2738 adapter->vf_data = NULL;
2739 adapter->vfs_allocated_count = 0;
2740 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2741 wrfl();
2742 msleep(100);
2743 dev_info(&pdev->dev, "IOV Disabled\n");
2744
2745 /* Re-enable DMA Coalescing flag since IOV is turned off */
2746 adapter->flags |= IGB_FLAG_DMAC;
2747 }
2748
2749 return 0;
2750}
2751
2752static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2753{
2754 struct net_device *netdev = pci_get_drvdata(pdev);
2755 struct igb_adapter *adapter = netdev_priv(netdev);
2756 int old_vfs = pci_num_vf(pdev);
2757 int err = 0;
2758 int i;
2759
cd14ef54 2760 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2761 err = -EPERM;
2762 goto out;
2763 }
fa44f2f1
GR		 2764 if (!num_vfs)
2765 goto out;
fa44f2f1 2766
781798a1
SA		 2767 if (old_vfs) {
2768 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2769 old_vfs, max_vfs);
2770 adapter->vfs_allocated_count = old_vfs;
2771 } else
2772 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2773
2774 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2775 sizeof(struct vf_data_storage), GFP_KERNEL);
2776
2777 /* if allocation failed then we do not support SR-IOV */
2778 if (!adapter->vf_data) {
2779 adapter->vfs_allocated_count = 0;
2780 dev_err(&pdev->dev,
2781 "Unable to allocate memory for VF Data Storage\n");
2782 err = -ENOMEM;
2783 goto out;
2784 }
2785
781798a1
SA		 2786 /* only call pci_enable_sriov() if no VFs are allocated already */
2787 if (!old_vfs) {
2788 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2789 if (err)
2790 goto err_out;
2791 }
fa44f2f1
GR		 2792 dev_info(&pdev->dev, "%d VFs allocated\n",
2793 adapter->vfs_allocated_count);
2794 for (i = 0; i < adapter->vfs_allocated_count; i++)
2795 igb_vf_configure(adapter, i);
2796
2797 /* DMA Coalescing is not supported in IOV mode. */
2798 adapter->flags &= ~IGB_FLAG_DMAC;
2799 goto out;
2800
2801err_out:
2802 kfree(adapter->vf_data);
2803 adapter->vf_data = NULL;
2804 adapter->vfs_allocated_count = 0;
2805out:
2806 return err;
2807}
2808
2809#endif
b980ac18 2810/**
441fc6fd
CW		 2811 * igb_remove_i2c - Cleanup I2C interface
2812 * @adapter: pointer to adapter structure
b980ac18 2813 **/
441fc6fd
CW		 2814static void igb_remove_i2c(struct igb_adapter *adapter)
2815{
441fc6fd
CW		 2816 /* free the adapter bus structure */
2817 i2c_del_adapter(&adapter->i2c_adap);
2818}
2819
9d5c8243 2820/**
b980ac18
JK		 2821 * igb_remove - Device Removal Routine
2822 * @pdev: PCI device information struct
9d5c8243 2823 *
b980ac18
JK		 2824 * igb_remove is called by the PCI subsystem to alert the driver
2825 * that it should release a PCI device. The could be caused by a
2826 * Hot-Plug event, or because the driver is going to be removed from
2827 * memory.
9d5c8243 2828 **/
9f9a12f8 2829static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2830{
2831 struct net_device *netdev = pci_get_drvdata(pdev);
2832 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2833 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2834
749ab2cd 2835 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2836#ifdef CONFIG_IGB_HWMON
2837 igb_sysfs_exit(adapter);
2838#endif
441fc6fd 2839 igb_remove_i2c(adapter);
a79f4f88 2840 igb_ptp_stop(adapter);
b980ac18 2841 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2842 * disable watchdog from being rescheduled.
2843 */
9d5c8243
AK		 2844 set_bit(__IGB_DOWN, &adapter->state);
2845 del_timer_sync(&adapter->watchdog_timer);
2846 del_timer_sync(&adapter->phy_info_timer);
2847
760141a5
TH		 2848 cancel_work_sync(&adapter->reset_task);
2849 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2850
421e02f0 2851#ifdef CONFIG_IGB_DCA
7dfc16fa 2852 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2853 dev_info(&pdev->dev, "DCA disabled\n");
2854 dca_remove_requester(&pdev->dev);
7dfc16fa 2855 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2856 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2857 }
2858#endif
2859
9d5c8243 2860 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2861 * would have already happened in close and is redundant.
2862 */
9d5c8243
AK		 2863 igb_release_hw_control(adapter);
2864
37680117 2865#ifdef CONFIG_PCI_IOV
fa44f2f1 2866 igb_disable_sriov(pdev);
37680117 2867#endif
559e9c49 2868
c23d92b8
AW		 2869 unregister_netdev(netdev);
2870
2871 igb_clear_interrupt_scheme(adapter);
2872
73bf8048 2873 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2874 if (hw->flash_address)
2875 iounmap(hw->flash_address);
559e9c49 2876 pci_release_selected_regions(pdev,
b980ac18 2877 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2878
1128c756 2879 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2880 free_netdev(netdev);
2881
19d5afd4 2882 pci_disable_pcie_error_reporting(pdev);
40a914fa 2883
9d5c8243
AK		 2884 pci_disable_device(pdev);
2885}
2886
a6b623e0 2887/**
b980ac18
JK		 2888 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2889 * @adapter: board private structure to initialize
a6b623e0 2890 *
b980ac18
JK		 2891 * This function initializes the vf specific data storage and then attempts to
2892 * allocate the VFs. The reason for ordering it this way is because it is much
2893 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2894 * the memory for the VFs.
a6b623e0 2895 **/
9f9a12f8 2896static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2897{
2898#ifdef CONFIG_PCI_IOV
2899 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2900 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2901
f96a8a0b
CW		 2902 /* Virtualization features not supported on i210 family. */
2903 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2904 return;
2905
be06998f
JB		 2906 /* Of the below we really only want the effect of getting
2907 * IGB_FLAG_HAS_MSIX set (if available), without which
2908 * igb_enable_sriov() has no effect.
2909 */
2910 igb_set_interrupt_capability(adapter, true);
2911 igb_reset_interrupt_capability(adapter);
2912
fa44f2f1 2913 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2914 igb_enable_sriov(pdev, max_vfs);
0224d663 2915
a6b623e0
AD		 2916#endif /* CONFIG_PCI_IOV */
2917}
2918
fa44f2f1 2919static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2920{
2921 struct e1000_hw *hw = &adapter->hw;
374a542d 2922 u32 max_rss_queues;
9d5c8243 2923
374a542d 2924 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2925 switch (hw->mac.type) {
374a542d
MV		 2926 case e1000_i211:
2927 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2928 break;
2929 case e1000_82575:
f96a8a0b 2930 case e1000_i210:
374a542d
MV		 2931 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2932 break;
2933 case e1000_i350:
2934 /* I350 cannot do RSS and SR-IOV at the same time */
2935 if (!!adapter->vfs_allocated_count) {
2936 max_rss_queues = 1;
2937 break;
2938 }
2939 /* fall through */
2940 case e1000_82576:
2941 if (!!adapter->vfs_allocated_count) {
2942 max_rss_queues = 2;
2943 break;
2944 }
2945 /* fall through */
2946 case e1000_82580:
ceb5f13b 2947 case e1000_i354:
374a542d
MV		 2948 default:
2949 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2950 break;
374a542d
MV		 2951 }
2952
2953 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2954
72ddef05
SS		 2955 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2956}
2957
2958void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2959 const u32 max_rss_queues)
2960{
2961 struct e1000_hw *hw = &adapter->hw;
2962
374a542d
MV		 2963 /* Determine if we need to pair queues. */
2964 switch (hw->mac.type) {
2965 case e1000_82575:
f96a8a0b 2966 case e1000_i211:
374a542d 2967 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2968 break;
374a542d 2969 case e1000_82576:
374a542d
MV		 2970 case e1000_82580:
2971 case e1000_i350:
ceb5f13b 2972 case e1000_i354:
374a542d 2973 case e1000_i210:
f96a8a0b 2974 default:
b980ac18 2975 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2976 * order to conserve interrupts due to limited supply.
2977 */
2978 if (adapter->rss_queues > (max_rss_queues / 2))
2979 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
37a5d163
SS		 2980 else
2981 adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2982 break;
2983 }
fa44f2f1
GR		 2984}
2985
2986/**
b980ac18
JK		 2987 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2988 * @adapter: board private structure to initialize
fa44f2f1 2989 *
b980ac18
JK		 2990 * igb_sw_init initializes the Adapter private data structure.
2991 * Fields are initialized based on PCI device information and
2992 * OS network device settings (MTU size).
fa44f2f1
GR		 2993 **/
2994static int igb_sw_init(struct igb_adapter *adapter)
2995{
2996 struct e1000_hw *hw = &adapter->hw;
2997 struct net_device *netdev = adapter->netdev;
2998 struct pci_dev *pdev = adapter->pdev;
2999
3000 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3001
3002 /* set default ring sizes */
3003 adapter->tx_ring_count = IGB_DEFAULT_TXD;
3004 adapter->rx_ring_count = IGB_DEFAULT_RXD;
3005
3006 /* set default ITR values */
3007 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3008 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3009
3010 /* set default work limits */
3011 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3012
3013 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3014 VLAN_HLEN;
3015 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3016
3017 spin_lock_init(&adapter->stats64_lock);
3018#ifdef CONFIG_PCI_IOV
3019 switch (hw->mac.type) {
3020 case e1000_82576:
3021 case e1000_i350:
3022 if (max_vfs > 7) {
3023 dev_warn(&pdev->dev,
3024 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 3025 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 3026 } else
3027 adapter->vfs_allocated_count = max_vfs;
3028 if (adapter->vfs_allocated_count)
3029 dev_warn(&pdev->dev,
3030 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3031 break;
3032 default:
3033 break;
3034 }
3035#endif /* CONFIG_PCI_IOV */
3036
cbfe360a
SA		 3037 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3038 adapter->flags |= IGB_FLAG_HAS_MSIX;
3039
ceee3450
TF		 3040 igb_probe_vfs(adapter);
3041
fa44f2f1 3042 igb_init_queue_configuration(adapter);
a99955fc 3043
1128c756 3044 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 3045 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3046 GFP_ATOMIC);
1128c756 3047
a6b623e0 3048 /* This call may decrease the number of queues */
53c7d064 3049 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3050 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3051 return -ENOMEM;
3052 }
3053
3054 /* Explicitly disable IRQ since the NIC can be in any state. */
3055 igb_irq_disable(adapter);
3056
f96a8a0b 3057 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3058 adapter->flags &= ~IGB_FLAG_DMAC;
3059
9d5c8243
AK		 3060 set_bit(__IGB_DOWN, &adapter->state);
3061 return 0;
3062}
3063
3064/**
b980ac18
JK		 3065 * igb_open - Called when a network interface is made active
3066 * @netdev: network interface device structure
9d5c8243 3067 *
b980ac18 3068 * Returns 0 on success, negative value on failure
9d5c8243 3069 *
b980ac18
JK		 3070 * The open entry point is called when a network interface is made
3071 * active by the system (IFF_UP). At this point all resources needed
3072 * for transmit and receive operations are allocated, the interrupt
3073 * handler is registered with the OS, the watchdog timer is started,
3074 * and the stack is notified that the interface is ready.
9d5c8243 3075 **/
749ab2cd 3076static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3077{
3078 struct igb_adapter *adapter = netdev_priv(netdev);
3079 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3080 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3081 int err;
3082 int i;
3083
3084 /* disallow open during test */
749ab2cd
YZ		 3085 if (test_bit(__IGB_TESTING, &adapter->state)) {
3086 WARN_ON(resuming);
9d5c8243 3087 return -EBUSY;
749ab2cd
YZ		 3088 }
3089
3090 if (!resuming)
3091 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3092
b168dfc5
JB		 3093 netif_carrier_off(netdev);
3094
9d5c8243
AK		 3095 /* allocate transmit descriptors */
3096 err = igb_setup_all_tx_resources(adapter);
3097 if (err)
3098 goto err_setup_tx;
3099
3100 /* allocate receive descriptors */
3101 err = igb_setup_all_rx_resources(adapter);
3102 if (err)
3103 goto err_setup_rx;
3104
88a268c1 3105 igb_power_up_link(adapter);
9d5c8243 3106
9d5c8243
AK		 3107 /* before we allocate an interrupt, we must be ready to handle it.
3108 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3109 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3110 * clean_rx handler before we do so.
3111 */
9d5c8243
AK		 3112 igb_configure(adapter);
3113
3114 err = igb_request_irq(adapter);
3115 if (err)
3116 goto err_req_irq;
3117
0c2cc02e
AD		 3118 /* Notify the stack of the actual queue counts. */
3119 err = netif_set_real_num_tx_queues(adapter->netdev,
3120 adapter->num_tx_queues);
3121 if (err)
3122 goto err_set_queues;
3123
3124 err = netif_set_real_num_rx_queues(adapter->netdev,
3125 adapter->num_rx_queues);
3126 if (err)
3127 goto err_set_queues;
3128
9d5c8243
AK		 3129 /* From here on the code is the same as igb_up() */
3130 clear_bit(__IGB_DOWN, &adapter->state);
3131
0d1ae7f4
AD		 3132 for (i = 0; i < adapter->num_q_vectors; i++)
3133 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3134
3135 /* Clear any pending interrupts. */
3136 rd32(E1000_ICR);
844290e5
PW		 3137
3138 igb_irq_enable(adapter);
3139
d4960307
AD		 3140 /* notify VFs that reset has been completed */
3141 if (adapter->vfs_allocated_count) {
3142 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3143
d4960307
AD		 3144 reg_data |= E1000_CTRL_EXT_PFRSTD;
3145 wr32(E1000_CTRL_EXT, reg_data);
3146 }
3147
d55b53ff
JK		 3148 netif_tx_start_all_queues(netdev);
3149
749ab2cd
YZ		 3150 if (!resuming)
3151 pm_runtime_put(&pdev->dev);
3152
25568a53
AD		 3153 /* start the watchdog. */
3154 hw->mac.get_link_status = 1;
3155 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3156
3157 return 0;
3158
0c2cc02e
AD		 3159err_set_queues:
3160 igb_free_irq(adapter);
9d5c8243
AK		 3161err_req_irq:
3162 igb_release_hw_control(adapter);
88a268c1 3163 igb_power_down_link(adapter);
9d5c8243
AK		 3164 igb_free_all_rx_resources(adapter);
3165err_setup_rx:
3166 igb_free_all_tx_resources(adapter);
3167err_setup_tx:
3168 igb_reset(adapter);
749ab2cd
YZ		 3169 if (!resuming)
3170 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3171
3172 return err;
3173}
3174
749ab2cd
YZ		 3175static int igb_open(struct net_device *netdev)
3176{
3177 return __igb_open(netdev, false);
3178}
3179
9d5c8243 3180/**
b980ac18
JK		 3181 * igb_close - Disables a network interface
3182 * @netdev: network interface device structure
9d5c8243 3183 *
b980ac18 3184 * Returns 0, this is not allowed to fail
9d5c8243 3185 *
b980ac18
JK		 3186 * The close entry point is called when an interface is de-activated
3187 * by the OS. The hardware is still under the driver's control, but
3188 * needs to be disabled. A global MAC reset is issued to stop the
3189 * hardware, and all transmit and receive resources are freed.
9d5c8243 3190 **/
749ab2cd 3191static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3192{
3193 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3194 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3195
3196 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3197
749ab2cd
YZ		 3198 if (!suspending)
3199 pm_runtime_get_sync(&pdev->dev);
3200
3201 igb_down(adapter);
9d5c8243
AK		 3202 igb_free_irq(adapter);
3203
3204 igb_free_all_tx_resources(adapter);
3205 igb_free_all_rx_resources(adapter);
3206
749ab2cd
YZ		 3207 if (!suspending)
3208 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3209 return 0;
3210}
3211
749ab2cd
YZ		 3212static int igb_close(struct net_device *netdev)
3213{
3214 return __igb_close(netdev, false);
3215}
3216
9d5c8243 3217/**
b980ac18
JK		 3218 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3219 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3220 *
b980ac18 3221 * Return 0 on success, negative on failure
9d5c8243 3222 **/
80785298 3223int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3224{
59d71989 3225 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3226 int size;
3227
06034649 3228 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3229
3230 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3231 if (!tx_ring->tx_buffer_info)
9d5c8243 3232 goto err;
9d5c8243
AK		 3233
3234 /* round up to nearest 4K */
85e8d004 3235 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3236 tx_ring->size = ALIGN(tx_ring->size, 4096);
3237
5536d210
AD		 3238 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3239 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3240 if (!tx_ring->desc)
3241 goto err;
3242
9d5c8243
AK		 3243 tx_ring->next_to_use = 0;
3244 tx_ring->next_to_clean = 0;
81c2fc22 3245
9d5c8243
AK		 3246 return 0;
3247
3248err:
06034649 3249 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3250 tx_ring->tx_buffer_info = NULL;
3251 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3252 return -ENOMEM;
3253}
3254
3255/**
b980ac18
JK		 3256 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3257 * (Descriptors) for all queues
3258 * @adapter: board private structure
9d5c8243 3259 *
b980ac18 3260 * Return 0 on success, negative on failure
9d5c8243
AK		 3261 **/
3262static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3263{
439705e1 3264 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3265 int i, err = 0;
3266
3267 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3268 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3269 if (err) {
439705e1 3270 dev_err(&pdev->dev,
9d5c8243
AK		 3271 "Allocation for Tx Queue %u failed\n", i);
3272 for (i--; i >= 0; i--)
3025a446 3273 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3274 break;
3275 }
3276 }
3277
3278 return err;
3279}
3280
3281/**
b980ac18
JK		 3282 * igb_setup_tctl - configure the transmit control registers
3283 * @adapter: Board private structure
9d5c8243 3284 **/
d7ee5b3a 3285void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3286{
9d5c8243
AK		 3287 struct e1000_hw *hw = &adapter->hw;
3288 u32 tctl;
9d5c8243 3289
85b430b4
AD		 3290 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3291 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3292
3293 /* Program the Transmit Control Register */
9d5c8243
AK		 3294 tctl = rd32(E1000_TCTL);
3295 tctl &= ~E1000_TCTL_CT;
3296 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3297 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3298
3299 igb_config_collision_dist(hw);
3300
9d5c8243
AK		 3301 /* Enable transmits */
3302 tctl |= E1000_TCTL_EN;
3303
3304 wr32(E1000_TCTL, tctl);
3305}
3306
85b430b4 3307/**
b980ac18
JK		 3308 * igb_configure_tx_ring - Configure transmit ring after Reset
3309 * @adapter: board private structure
3310 * @ring: tx ring to configure
85b430b4 3311 *
b980ac18 3312 * Configure a transmit ring after a reset.
85b430b4 3313 **/
d7ee5b3a 3314void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3315 struct igb_ring *ring)
85b430b4
AD		 3316{
3317 struct e1000_hw *hw = &adapter->hw;
a74420e0 3318 u32 txdctl = 0;
85b430b4
AD		 3319 u64 tdba = ring->dma;
3320 int reg_idx = ring->reg_idx;
3321
3322 /* disable the queue */
a74420e0 3323 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3324 wrfl();
3325 mdelay(10);
3326
3327 wr32(E1000_TDLEN(reg_idx),
b980ac18 3328 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3329 wr32(E1000_TDBAL(reg_idx),
b980ac18 3330 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3331 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3332
fce99e34 3333 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3334 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3335 writel(0, ring->tail);
85b430b4
AD		 3336
3337 txdctl |= IGB_TX_PTHRESH;
3338 txdctl |= IGB_TX_HTHRESH << 8;
3339 txdctl |= IGB_TX_WTHRESH << 16;
3340
3341 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3342 wr32(E1000_TXDCTL(reg_idx), txdctl);
3343}
3344
3345/**
b980ac18
JK		 3346 * igb_configure_tx - Configure transmit Unit after Reset
3347 * @adapter: board private structure
85b430b4 3348 *
b980ac18 3349 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3350 **/
3351static void igb_configure_tx(struct igb_adapter *adapter)
3352{
3353 int i;
3354
3355 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3356 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3357}
3358
9d5c8243 3359/**
b980ac18
JK		 3360 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3361 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3362 *
b980ac18 3363 * Returns 0 on success, negative on failure
9d5c8243 3364 **/
80785298 3365int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3366{
59d71989 3367 struct device *dev = rx_ring->dev;
f33005a6 3368 int size;
9d5c8243 3369
06034649 3370 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3371
3372 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3373 if (!rx_ring->rx_buffer_info)
9d5c8243 3374 goto err;
9d5c8243 3375
9d5c8243 3376 /* Round up to nearest 4K */
f33005a6 3377 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3378 rx_ring->size = ALIGN(rx_ring->size, 4096);
3379
5536d210
AD		 3380 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3381 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3382 if (!rx_ring->desc)
3383 goto err;
3384
cbc8e55f 3385 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3386 rx_ring->next_to_clean = 0;
3387 rx_ring->next_to_use = 0;
9d5c8243 3388
9d5c8243
AK		 3389 return 0;
3390
3391err:
06034649
AD		 3392 vfree(rx_ring->rx_buffer_info);
3393 rx_ring->rx_buffer_info = NULL;
f33005a6 3394 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3395 return -ENOMEM;
3396}
3397
3398/**
b980ac18
JK		 3399 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3400 * (Descriptors) for all queues
3401 * @adapter: board private structure
9d5c8243 3402 *
b980ac18 3403 * Return 0 on success, negative on failure
9d5c8243
AK		 3404 **/
3405static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3406{
439705e1 3407 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3408 int i, err = 0;
3409
3410 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3411 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3412 if (err) {
439705e1 3413 dev_err(&pdev->dev,
9d5c8243
AK		 3414 "Allocation for Rx Queue %u failed\n", i);
3415 for (i--; i >= 0; i--)
3025a446 3416 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3417 break;
3418 }
3419 }
3420
3421 return err;
3422}
3423
06cf2666 3424/**
b980ac18
JK		 3425 * igb_setup_mrqc - configure the multiple receive queue control registers
3426 * @adapter: Board private structure
06cf2666
AD		 3427 **/
3428static void igb_setup_mrqc(struct igb_adapter *adapter)
3429{
3430 struct e1000_hw *hw = &adapter->hw;
3431 u32 mrqc, rxcsum;
ed12cc9a 3432 u32 j, num_rx_queues;
eb31f849 3433 u32 rss_key[10];
06cf2666 3434
eb31f849 3435 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3436 for (j = 0; j < 10; j++)
eb31f849 3437 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3438
a99955fc 3439 num_rx_queues = adapter->rss_queues;
06cf2666 3440
797fd4be 3441 switch (hw->mac.type) {
797fd4be
AD		 3442 case e1000_82576:
3443 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3444 if (adapter->vfs_allocated_count)
06cf2666 3445 num_rx_queues = 2;
797fd4be
AD		 3446 break;
3447 default:
3448 break;
06cf2666
AD		 3449 }
3450
ed12cc9a
LMV		 3451 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3452 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3453 adapter->rss_indir_tbl[j] =
3454 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3455 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3456 }
ed12cc9a 3457 igb_write_rss_indir_tbl(adapter);
06cf2666 3458
b980ac18 3459 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3460 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3461 * offloads as they are enabled by default
3462 */
3463 rxcsum = rd32(E1000_RXCSUM);
3464 rxcsum |= E1000_RXCSUM_PCSD;
3465
3466 if (adapter->hw.mac.type >= e1000_82576)
3467 /* Enable Receive Checksum Offload for SCTP */
3468 rxcsum |= E1000_RXCSUM_CRCOFL;
3469
3470 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3471 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3472
039454a8
AA		 3473 /* Generate RSS hash based on packet types, TCP/UDP
3474 * port numbers and/or IPv4/v6 src and dst addresses
3475 */
f96a8a0b
CW		 3476 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3477 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3478 E1000_MRQC_RSS_FIELD_IPV6 |
3479 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3480 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3481
039454a8
AA		 3482 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3483 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3484 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3485 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3486
06cf2666
AD		 3487 /* If VMDq is enabled then we set the appropriate mode for that, else
3488 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3489 * if we are only using one queue
3490 */
06cf2666
AD		 3491 if (adapter->vfs_allocated_count) {
3492 if (hw->mac.type > e1000_82575) {
3493 /* Set the default pool for the PF's first queue */
3494 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3495
06cf2666
AD		 3496 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3497 E1000_VT_CTL_DISABLE_DEF_POOL);
3498 vtctl |= adapter->vfs_allocated_count <<
3499 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3500 wr32(E1000_VT_CTL, vtctl);
3501 }
a99955fc 3502 if (adapter->rss_queues > 1)
c883de9f 3503 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
06cf2666 3504 else
f96a8a0b 3505 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3506 } else {
f96a8a0b 3507 if (hw->mac.type != e1000_i211)
c883de9f 3508 mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
06cf2666
AD		 3509 }
3510 igb_vmm_control(adapter);
3511
06cf2666
AD		 3512 wr32(E1000_MRQC, mrqc);
3513}
3514
9d5c8243 3515/**
b980ac18
JK		 3516 * igb_setup_rctl - configure the receive control registers
3517 * @adapter: Board private structure
9d5c8243 3518 **/
d7ee5b3a 3519void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3520{
3521 struct e1000_hw *hw = &adapter->hw;
3522 u32 rctl;
9d5c8243
AK		 3523
3524 rctl = rd32(E1000_RCTL);
3525
3526 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3527 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3528
69d728ba 3529 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3530 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3531
b980ac18 3532 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3533 * redirection as it did with e1000. Newer features require
3534 * that the HW strips the CRC.
73cd78f1 3535 */
87cb7e8c 3536 rctl |= E1000_RCTL_SECRC;
9d5c8243 3537
559e9c49 3538 /* disable store bad packets and clear size bits. */
ec54d7d6 3539 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3540
45693bcb 3541 /* enable LPE to allow for reception of jumbo frames */
6ec43fe6 3542 rctl |= E1000_RCTL_LPE;
9d5c8243 3543
952f72a8
AD		 3544 /* disable queue 0 to prevent tail write w/o re-config */
3545 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3546
e1739522
AD		 3547 /* Attention!!! For SR-IOV PF driver operations you must enable
3548 * queue drop for all VF and PF queues to prevent head of line blocking
3549 * if an un-trusted VF does not provide descriptors to hardware.
3550 */
3551 if (adapter->vfs_allocated_count) {
e1739522
AD		 3552 /* set all queue drop enable bits */
3553 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3554 }
3555
89eaefb6
BG		 3556 /* This is useful for sniffing bad packets. */
3557 if (adapter->netdev->features & NETIF_F_RXALL) {
3558 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3559 * in e1000e_set_rx_mode
3560 */
89eaefb6
BG		 3561 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3562 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3563 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3564
16903caa 3565 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
89eaefb6
BG		 3566 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3567 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3568 * and that breaks VLANs.
3569 */
3570 }
3571
9d5c8243
AK		 3572 wr32(E1000_RCTL, rctl);
3573}
3574
7d5753f0 3575static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3576 int vfn)
7d5753f0
AD		 3577{
3578 struct e1000_hw *hw = &adapter->hw;
3579 u32 vmolr;
3580
d3836f8e
AD		 3581 if (size > MAX_JUMBO_FRAME_SIZE)
3582 size = MAX_JUMBO_FRAME_SIZE;
7d5753f0
AD		 3583
3584 vmolr = rd32(E1000_VMOLR(vfn));
3585 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3586 vmolr |= size | E1000_VMOLR_LPE;
3587 wr32(E1000_VMOLR(vfn), vmolr);
3588
3589 return 0;
3590}
3591
8151d294
WM		 3592static inline void igb_set_vmolr(struct igb_adapter *adapter,
3593 int vfn, bool aupe)
7d5753f0
AD		 3594{
3595 struct e1000_hw *hw = &adapter->hw;
3596 u32 vmolr;
3597
b980ac18 3598 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3599 * we should exit and do nothing
3600 */
3601 if (hw->mac.type < e1000_82576)
3602 return;
3603
3604 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3605 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3606 if (hw->mac.type == e1000_i350) {
3607 u32 dvmolr;
3608
3609 dvmolr = rd32(E1000_DVMOLR(vfn));
3610 dvmolr |= E1000_DVMOLR_STRVLAN;
3611 wr32(E1000_DVMOLR(vfn), dvmolr);
3612 }
8151d294 3613 if (aupe)
b980ac18 3614 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3615 else
3616 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3617
3618 /* clear all bits that might not be set */
3619 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3620
a99955fc 3621 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3622 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3623 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3624 * multicast packets
3625 */
3626 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3627 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3628
3629 wr32(E1000_VMOLR(vfn), vmolr);
3630}
3631
85b430b4 3632/**
b980ac18
JK		 3633 * igb_configure_rx_ring - Configure a receive ring after Reset
3634 * @adapter: board private structure
3635 * @ring: receive ring to be configured
85b430b4 3636 *
b980ac18 3637 * Configure the Rx unit of the MAC after a reset.
85b430b4 3638 **/
d7ee5b3a 3639void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3640 struct igb_ring *ring)
85b430b4
AD		 3641{
3642 struct e1000_hw *hw = &adapter->hw;
3643 u64 rdba = ring->dma;
3644 int reg_idx = ring->reg_idx;
a74420e0 3645 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3646
3647 /* disable the queue */
a74420e0 3648 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3649
3650 /* Set DMA base address registers */
3651 wr32(E1000_RDBAL(reg_idx),
3652 rdba & 0x00000000ffffffffULL);
3653 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3654 wr32(E1000_RDLEN(reg_idx),
b980ac18 3655 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3656
3657 /* initialize head and tail */
fce99e34 3658 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3659 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3660 writel(0, ring->tail);
85b430b4 3661
952f72a8 3662 /* set descriptor configuration */
44390ca6 3663 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3664 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3665 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3666 if (hw->mac.type >= e1000_82580)
757b77e2 3667 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3668 /* Only set Drop Enable if we are supporting multiple queues */
3669 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3670 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3671
3672 wr32(E1000_SRRCTL(reg_idx), srrctl);
3673
7d5753f0 3674 /* set filtering for VMDQ pools */
8151d294 3675 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3676
85b430b4
AD		 3677 rxdctl |= IGB_RX_PTHRESH;
3678 rxdctl |= IGB_RX_HTHRESH << 8;
3679 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3680
3681 /* enable receive descriptor fetching */
3682 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3683 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3684}
3685
9d5c8243 3686/**
b980ac18
JK		 3687 * igb_configure_rx - Configure receive Unit after Reset
3688 * @adapter: board private structure
9d5c8243 3689 *
b980ac18 3690 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3691 **/
3692static void igb_configure_rx(struct igb_adapter *adapter)
3693{
9107584e 3694 int i;
9d5c8243 3695
26ad9178
AD		 3696 /* set the correct pool for the PF default MAC address in entry 0 */
3697 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3698 adapter->vfs_allocated_count);
26ad9178 3699
06cf2666 3700 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3701 * the Base and Length of the Rx Descriptor Ring
3702 */
f9d40f6a
AD		 3703 for (i = 0; i < adapter->num_rx_queues; i++)
3704 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3705}
3706
3707/**
b980ac18
JK		 3708 * igb_free_tx_resources - Free Tx Resources per Queue
3709 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3710 *
b980ac18 3711 * Free all transmit software resources
9d5c8243 3712 **/
68fd9910 3713void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3714{
3b644cf6 3715 igb_clean_tx_ring(tx_ring);
9d5c8243 3716
06034649
AD		 3717 vfree(tx_ring->tx_buffer_info);
3718 tx_ring->tx_buffer_info = NULL;
9d5c8243 3719
439705e1
AD		 3720 /* if not set, then don't free */
3721 if (!tx_ring->desc)
3722 return;
3723
59d71989
AD		 3724 dma_free_coherent(tx_ring->dev, tx_ring->size,
3725 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3726
3727 tx_ring->desc = NULL;
3728}
3729
3730/**
b980ac18
JK		 3731 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3732 * @adapter: board private structure
9d5c8243 3733 *
b980ac18 3734 * Free all transmit software resources
9d5c8243
AK		 3735 **/
3736static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3737{
3738 int i;
3739
3740 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3741 if (adapter->tx_ring[i])
3742 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3743}
3744
ebe42d16
AD		 3745void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3746 struct igb_tx_buffer *tx_buffer)
3747{
3748 if (tx_buffer->skb) {
3749 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3750 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3751 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3752 dma_unmap_addr(tx_buffer, dma),
3753 dma_unmap_len(tx_buffer, len),
ebe42d16 3754 DMA_TO_DEVICE);
c9f14bf3 3755 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3756 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3757 dma_unmap_addr(tx_buffer, dma),
3758 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3759 DMA_TO_DEVICE);
3760 }
3761 tx_buffer->next_to_watch = NULL;
3762 tx_buffer->skb = NULL;
c9f14bf3 3763 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3764 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3765}
3766
3767/**
b980ac18
JK		 3768 * igb_clean_tx_ring - Free Tx Buffers
3769 * @tx_ring: ring to be cleaned
9d5c8243 3770 **/
3b644cf6 3771static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3772{
06034649 3773 struct igb_tx_buffer *buffer_info;
9d5c8243 3774 unsigned long size;
6ad4edfc 3775 u16 i;
9d5c8243 3776
06034649 3777 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3778 return;
3779 /* Free all the Tx ring sk_buffs */
3780
3781 for (i = 0; i < tx_ring->count; i++) {
06034649 3782 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3783 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3784 }
3785
dad8a3b3
JF		 3786 netdev_tx_reset_queue(txring_txq(tx_ring));
3787
06034649
AD		 3788 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3789 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3790
3791 /* Zero out the descriptor ring */
9d5c8243
AK		 3792 memset(tx_ring->desc, 0, tx_ring->size);
3793
3794 tx_ring->next_to_use = 0;
3795 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3796}
3797
3798/**
b980ac18
JK		 3799 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3800 * @adapter: board private structure
9d5c8243
AK		 3801 **/
3802static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3803{
3804 int i;
3805
3806 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3807 if (adapter->tx_ring[i])
3808 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3809}
3810
3811/**
b980ac18
JK		 3812 * igb_free_rx_resources - Free Rx Resources
3813 * @rx_ring: ring to clean the resources from
9d5c8243 3814 *
b980ac18 3815 * Free all receive software resources
9d5c8243 3816 **/
68fd9910 3817void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3818{
3b644cf6 3819 igb_clean_rx_ring(rx_ring);
9d5c8243 3820
06034649
AD		 3821 vfree(rx_ring->rx_buffer_info);
3822 rx_ring->rx_buffer_info = NULL;
9d5c8243 3823
439705e1
AD		 3824 /* if not set, then don't free */
3825 if (!rx_ring->desc)
3826 return;
3827
59d71989
AD		 3828 dma_free_coherent(rx_ring->dev, rx_ring->size,
3829 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3830
3831 rx_ring->desc = NULL;
3832}
3833
3834/**
b980ac18
JK		 3835 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3836 * @adapter: board private structure
9d5c8243 3837 *
b980ac18 3838 * Free all receive software resources
9d5c8243
AK		 3839 **/
3840static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3841{
3842 int i;
3843
3844 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3845 if (adapter->rx_ring[i])
3846 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3847}
3848
3849/**
b980ac18
JK		 3850 * igb_clean_rx_ring - Free Rx Buffers per Queue
3851 * @rx_ring: ring to free buffers from
9d5c8243 3852 **/
3b644cf6 3853static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3854{
9d5c8243 3855 unsigned long size;
c023cd88 3856 u16 i;
9d5c8243 3857
1a1c225b
AD		 3858 if (rx_ring->skb)
3859 dev_kfree_skb(rx_ring->skb);
3860 rx_ring->skb = NULL;
3861
06034649 3862 if (!rx_ring->rx_buffer_info)
9d5c8243 3863 return;
439705e1 3864
9d5c8243
AK		 3865 /* Free all the Rx ring sk_buffs */
3866 for (i = 0; i < rx_ring->count; i++) {
06034649 3867 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3868
cbc8e55f
AD		 3869 if (!buffer_info->page)
3870 continue;
3871
3872 dma_unmap_page(rx_ring->dev,
3873 buffer_info->dma,
3874 PAGE_SIZE,
3875 DMA_FROM_DEVICE);
3876 __free_page(buffer_info->page);
3877
1a1c225b 3878 buffer_info->page = NULL;
9d5c8243
AK		 3879 }
3880
06034649
AD		 3881 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3882 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3883
3884 /* Zero out the descriptor ring */
3885 memset(rx_ring->desc, 0, rx_ring->size);
3886
cbc8e55f 3887 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3888 rx_ring->next_to_clean = 0;
3889 rx_ring->next_to_use = 0;
9d5c8243
AK		 3890}
3891
3892/**
b980ac18
JK		 3893 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3894 * @adapter: board private structure
9d5c8243
AK		 3895 **/
3896static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3897{
3898 int i;
3899
3900 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3901 if (adapter->rx_ring[i])
3902 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3903}
3904
3905/**
b980ac18
JK		 3906 * igb_set_mac - Change the Ethernet Address of the NIC
3907 * @netdev: network interface device structure
3908 * @p: pointer to an address structure
9d5c8243 3909 *
b980ac18 3910 * Returns 0 on success, negative on failure
9d5c8243
AK		 3911 **/
3912static int igb_set_mac(struct net_device *netdev, void *p)
3913{
3914 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3915 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3916 struct sockaddr *addr = p;
3917
3918 if (!is_valid_ether_addr(addr->sa_data))
3919 return -EADDRNOTAVAIL;
3920
3921 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3922 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3923
26ad9178
AD		 3924 /* set the correct pool for the new PF MAC address in entry 0 */
3925 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3926 adapter->vfs_allocated_count);
e1739522 3927
9d5c8243
AK		 3928 return 0;
3929}
3930
3931/**
b980ac18
JK		 3932 * igb_write_mc_addr_list - write multicast addresses to MTA
3933 * @netdev: network interface device structure
9d5c8243 3934 *
b980ac18
JK		 3935 * Writes multicast address list to the MTA hash table.
3936 * Returns: -ENOMEM on failure
3937 * 0 on no addresses written
3938 * X on writing X addresses to MTA
9d5c8243 3939 **/
68d480c4 3940static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3941{
3942 struct igb_adapter *adapter = netdev_priv(netdev);
3943 struct e1000_hw *hw = &adapter->hw;
22bedad3 3944 struct netdev_hw_addr *ha;
68d480c4 3945 u8 *mta_list;
9d5c8243
AK		 3946 int i;
3947
4cd24eaf 3948 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3949 /* nothing to program, so clear mc list */
3950 igb_update_mc_addr_list(hw, NULL, 0);
3951 igb_restore_vf_multicasts(adapter);
3952 return 0;
3953 }
9d5c8243 3954
4cd24eaf 3955 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3956 if (!mta_list)
3957 return -ENOMEM;
ff41f8dc 3958
68d480c4 3959 /* The shared function expects a packed array of only addresses. */
48e2f183 3960 i = 0;
22bedad3
JP		 3961 netdev_for_each_mc_addr(ha, netdev)
3962 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3963
68d480c4
AD		 3964 igb_update_mc_addr_list(hw, mta_list, i);
3965 kfree(mta_list);
3966
4cd24eaf 3967 return netdev_mc_count(netdev);
68d480c4
AD		 3968}
3969
3970/**
b980ac18
JK		 3971 * igb_write_uc_addr_list - write unicast addresses to RAR table
3972 * @netdev: network interface device structure
68d480c4 3973 *
b980ac18
JK		 3974 * Writes unicast address list to the RAR table.
3975 * Returns: -ENOMEM on failure/insufficient address space
3976 * 0 on no addresses written
3977 * X on writing X addresses to the RAR table
68d480c4
AD		 3978 **/
3979static int igb_write_uc_addr_list(struct net_device *netdev)
3980{
3981 struct igb_adapter *adapter = netdev_priv(netdev);
3982 struct e1000_hw *hw = &adapter->hw;
3983 unsigned int vfn = adapter->vfs_allocated_count;
3984 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3985 int count = 0;
3986
3987 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3988 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3989 return -ENOMEM;
9d5c8243 3990
32e7bfc4 3991 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3992 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3993
3994 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3995 if (!rar_entries)
3996 break;
26ad9178 3997 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3998 rar_entries--,
3999 vfn);
68d480c4 4000 count++;
ff41f8dc
AD		 4001 }
4002 }
4003 /* write the addresses in reverse order to avoid write combining */
4004 for (; rar_entries > 0 ; rar_entries--) {
4005 wr32(E1000_RAH(rar_entries), 0);
4006 wr32(E1000_RAL(rar_entries), 0);
4007 }
4008 wrfl();
4009
68d480c4
AD		 4010 return count;
4011}
4012
16903caa
AD		 4013static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4014{
4015 struct e1000_hw *hw = &adapter->hw;
4016 u32 i, pf_id;
4017
4018 switch (hw->mac.type) {
4019 case e1000_i210:
4020 case e1000_i211:
4021 case e1000_i350:
4022 /* VLAN filtering needed for VLAN prio filter */
4023 if (adapter->netdev->features & NETIF_F_NTUPLE)
4024 break;
4025 /* fall through */
4026 case e1000_82576:
4027 case e1000_82580:
4028 case e1000_i354:
4029 /* VLAN filtering needed for pool filtering */
4030 if (adapter->vfs_allocated_count)
4031 break;
4032 /* fall through */
4033 default:
4034 return 1;
4035 }
4036
4037 /* We are already in VLAN promisc, nothing to do */
4038 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4039 return 0;
4040
4041 if (!adapter->vfs_allocated_count)
4042 goto set_vfta;
4043
4044 /* Add PF to all active pools */
4045 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4046
4047 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4048 u32 vlvf = rd32(E1000_VLVF(i));
4049
4050 vlvf |= 1 << pf_id;
4051 wr32(E1000_VLVF(i), vlvf);
4052 }
4053
4054set_vfta:
4055 /* Set all bits in the VLAN filter table array */
4056 for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4057 hw->mac.ops.write_vfta(hw, i, ~0U);
4058
4059 /* Set flag so we don't redo unnecessary work */
4060 adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4061
4062 return 0;
4063}
4064
4065#define VFTA_BLOCK_SIZE 8
4066static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4067{
4068 struct e1000_hw *hw = &adapter->hw;
4069 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4070 u32 vid_start = vfta_offset * 32;
4071 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4072 u32 i, vid, word, bits, pf_id;
4073
4074 /* guarantee that we don't scrub out management VLAN */
4075 vid = adapter->mng_vlan_id;
4076 if (vid >= vid_start && vid < vid_end)
4077 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4078
4079 if (!adapter->vfs_allocated_count)
4080 goto set_vfta;
4081
4082 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4083
4084 for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4085 u32 vlvf = rd32(E1000_VLVF(i));
4086
4087 /* pull VLAN ID from VLVF */
4088 vid = vlvf & VLAN_VID_MASK;
4089
4090 /* only concern ourselves with a certain range */
4091 if (vid < vid_start || vid >= vid_end)
4092 continue;
4093
4094 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4095 /* record VLAN ID in VFTA */
4096 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4097
4098 /* if PF is part of this then continue */
4099 if (test_bit(vid, adapter->active_vlans))
4100 continue;
4101 }
4102
4103 /* remove PF from the pool */
4104 bits = ~(1 << pf_id);
4105 bits &= rd32(E1000_VLVF(i));
4106 wr32(E1000_VLVF(i), bits);
4107 }
4108
4109set_vfta:
4110 /* extract values from active_vlans and write back to VFTA */
4111 for (i = VFTA_BLOCK_SIZE; i--;) {
4112 vid = (vfta_offset + i) * 32;
4113 word = vid / BITS_PER_LONG;
4114 bits = vid % BITS_PER_LONG;
4115
4116 vfta[i] |= adapter->active_vlans[word] >> bits;
4117
4118 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4119 }
4120}
4121
4122static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4123{
4124 u32 i;
4125
4126 /* We are not in VLAN promisc, nothing to do */
4127 if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4128 return;
4129
4130 /* Set flag so we don't redo unnecessary work */
4131 adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4132
4133 for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4134 igb_scrub_vfta(adapter, i);
4135}
4136
68d480c4 4137/**
b980ac18
JK		 4138 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4139 * @netdev: network interface device structure
68d480c4 4140 *
b980ac18
JK		 4141 * The set_rx_mode entry point is called whenever the unicast or multicast
4142 * address lists or the network interface flags are updated. This routine is
4143 * responsible for configuring the hardware for proper unicast, multicast,
4144 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4145 **/
4146static void igb_set_rx_mode(struct net_device *netdev)
4147{
4148 struct igb_adapter *adapter = netdev_priv(netdev);
4149 struct e1000_hw *hw = &adapter->hw;
4150 unsigned int vfn = adapter->vfs_allocated_count;
16903caa 4151 u32 rctl = 0, vmolr = 0;
68d480c4
AD		 4152 int count;
4153
4154 /* Check for Promiscuous and All Multicast modes */
68d480c4 4155 if (netdev->flags & IFF_PROMISC) {
16903caa 4156 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
bf456abb
AD		 4157 vmolr |= E1000_VMOLR_MPME;
4158
4159 /* enable use of UTA filter to force packets to default pool */
4160 if (hw->mac.type == e1000_82576)
4161 vmolr |= E1000_VMOLR_ROPE;
68d480c4
AD		 4162 } else {
4163 if (netdev->flags & IFF_ALLMULTI) {
4164 rctl |= E1000_RCTL_MPE;
4165 vmolr |= E1000_VMOLR_MPME;
4166 } else {
b980ac18 4167 /* Write addresses to the MTA, if the attempt fails
25985edc 4168 * then we should just turn on promiscuous mode so
68d480c4
AD		 4169 * that we can at least receive multicast traffic
4170 */
4171 count = igb_write_mc_addr_list(netdev);
4172 if (count < 0) {
4173 rctl |= E1000_RCTL_MPE;
4174 vmolr |= E1000_VMOLR_MPME;
4175 } else if (count) {
4176 vmolr |= E1000_VMOLR_ROMPE;
4177 }
4178 }
268f9d33
AD		 4179 }
4180
4181 /* Write addresses to available RAR registers, if there is not
4182 * sufficient space to store all the addresses then enable
4183 * unicast promiscuous mode
4184 */
4185 count = igb_write_uc_addr_list(netdev);
4186 if (count < 0) {
4187 rctl |= E1000_RCTL_UPE;
4188 vmolr |= E1000_VMOLR_ROPE;
28fc06f5 4189 }
16903caa
AD		 4190
4191 /* enable VLAN filtering by default */
4192 rctl |= E1000_RCTL_VFE;
4193
4194 /* disable VLAN filtering for modes that require it */
4195 if ((netdev->flags & IFF_PROMISC) ||
4196 (netdev->features & NETIF_F_RXALL)) {
4197 /* if we fail to set all rules then just clear VFE */
4198 if (igb_vlan_promisc_enable(adapter))
4199 rctl &= ~E1000_RCTL_VFE;
4200 } else {
4201 igb_vlan_promisc_disable(adapter);
4202 }
4203
4204 /* update state of unicast, multicast, and VLAN filtering modes */
4205 rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
4206 E1000_RCTL_VFE);
68d480c4 4207 wr32(E1000_RCTL, rctl);
28fc06f5 4208
b980ac18 4209 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4210 * the VMOLR to enable the appropriate modes. Without this workaround
4211 * we will have issues with VLAN tag stripping not being done for frames
4212 * that are only arriving because we are the default pool
4213 */
f96a8a0b 4214 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4215 return;
9d5c8243 4216
bf456abb
AD		 4217 /* set UTA to appropriate mode */
4218 igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
4219
68d480c4 4220 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4221 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
45693bcb
AD		 4222
4223 /* enable Rx jumbo frames, no need for restriction */
4224 vmolr &= ~E1000_VMOLR_RLPML_MASK;
4225 vmolr |= MAX_JUMBO_FRAME_SIZE | E1000_VMOLR_LPE;
4226
68d480c4 4227 wr32(E1000_VMOLR(vfn), vmolr);
45693bcb
AD		 4228 wr32(E1000_RLPML, MAX_JUMBO_FRAME_SIZE);
4229
28fc06f5 4230 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4231}
4232
13800469
GR		 4233static void igb_check_wvbr(struct igb_adapter *adapter)
4234{
4235 struct e1000_hw *hw = &adapter->hw;
4236 u32 wvbr = 0;
4237
4238 switch (hw->mac.type) {
4239 case e1000_82576:
4240 case e1000_i350:
81ad807b
CW		 4241 wvbr = rd32(E1000_WVBR);
4242 if (!wvbr)
13800469
GR		 4243 return;
4244 break;
4245 default:
4246 break;
4247 }
4248
4249 adapter->wvbr |= wvbr;
4250}
4251
4252#define IGB_STAGGERED_QUEUE_OFFSET 8
4253
4254static void igb_spoof_check(struct igb_adapter *adapter)
4255{
4256 int j;
4257
4258 if (!adapter->wvbr)
4259 return;
4260
9005df38 4261 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4262 if (adapter->wvbr & (1 << j) ||
4263 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4264 dev_warn(&adapter->pdev->dev,
4265 "Spoof event(s) detected on VF %d\n", j);
4266 adapter->wvbr &=
4267 ~((1 << j) |
4268 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4269 }
4270 }
4271}
4272
9d5c8243 4273/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4274 * the phy
4275 */
9d5c8243
AK		 4276static void igb_update_phy_info(unsigned long data)
4277{
4278 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4279 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4280}
4281
4d6b725e 4282/**
b980ac18
JK		 4283 * igb_has_link - check shared code for link and determine up/down
4284 * @adapter: pointer to driver private info
4d6b725e 4285 **/
3145535a 4286bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4287{
4288 struct e1000_hw *hw = &adapter->hw;
4289 bool link_active = false;
4d6b725e
AD		 4290
4291 /* get_link_status is set on LSC (link status) interrupt or
4292 * rx sequence error interrupt. get_link_status will stay
4293 * false until the e1000_check_for_link establishes link
4294 * for copper adapters ONLY
4295 */
4296 switch (hw->phy.media_type) {
4297 case e1000_media_type_copper:
e5c3370f
AA		 4298 if (!hw->mac.get_link_status)
4299 return true;
4d6b725e 4300 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4301 hw->mac.ops.check_for_link(hw);
4302 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4303 break;
4304 default:
4305 case e1000_media_type_unknown:
4306 break;
4307 }
4308
aa9b8cc4
AA		 4309 if (((hw->mac.type == e1000_i210) ||
4310 (hw->mac.type == e1000_i211)) &&
4311 (hw->phy.id == I210_I_PHY_ID)) {
4312 if (!netif_carrier_ok(adapter->netdev)) {
4313 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4314 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4315 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4316 adapter->link_check_timeout = jiffies;
4317 }
4318 }
4319
4d6b725e
AD		 4320 return link_active;
4321}
4322
563988dc
SA		 4323static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4324{
4325 bool ret = false;
4326 u32 ctrl_ext, thstat;
4327
f96a8a0b 4328 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4329 if (hw->mac.type == e1000_i350) {
4330 thstat = rd32(E1000_THSTAT);
4331 ctrl_ext = rd32(E1000_CTRL_EXT);
4332
4333 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4334 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4335 ret = !!(thstat & event);
563988dc
SA		 4336 }
4337
4338 return ret;
4339}
4340
1516f0a6
CW		 4341/**
4342 * igb_check_lvmmc - check for malformed packets received
4343 * and indicated in LVMMC register
4344 * @adapter: pointer to adapter
4345 **/
4346static void igb_check_lvmmc(struct igb_adapter *adapter)
4347{
4348 struct e1000_hw *hw = &adapter->hw;
4349 u32 lvmmc;
4350
4351 lvmmc = rd32(E1000_LVMMC);
4352 if (lvmmc) {
4353 if (unlikely(net_ratelimit())) {
4354 netdev_warn(adapter->netdev,
4355 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4356 lvmmc);
4357 }
4358 }
4359}
4360
9d5c8243 4361/**
b980ac18
JK		 4362 * igb_watchdog - Timer Call-back
4363 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4364 **/
4365static void igb_watchdog(unsigned long data)
4366{
4367 struct igb_adapter *adapter = (struct igb_adapter *)data;
4368 /* Do the rest outside of interrupt context */
4369 schedule_work(&adapter->watchdog_task);
4370}
4371
4372static void igb_watchdog_task(struct work_struct *work)
4373{
4374 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4375 struct igb_adapter,
4376 watchdog_task);
9d5c8243 4377 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4378 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4379 struct net_device *netdev = adapter->netdev;
563988dc 4380 u32 link;
7a6ea550 4381 int i;
56cec249 4382 u32 connsw;
b72f3f72 4383 u16 phy_data, retry_count = 20;
9d5c8243 4384
4d6b725e 4385 link = igb_has_link(adapter);
aa9b8cc4
AA		 4386
4387 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4388 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4389 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4390 else
4391 link = false;
4392 }
4393
56cec249
CW		 4394 /* Force link down if we have fiber to swap to */
4395 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4396 if (hw->phy.media_type == e1000_media_type_copper) {
4397 connsw = rd32(E1000_CONNSW);
4398 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4399 link = 0;
4400 }
4401 }
9d5c8243 4402 if (link) {
2bdfc4e2
CW		 4403 /* Perform a reset if the media type changed. */
4404 if (hw->dev_spec._82575.media_changed) {
4405 hw->dev_spec._82575.media_changed = false;
4406 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4407 igb_reset(adapter);
4408 }
749ab2cd
YZ		 4409 /* Cancel scheduled suspend requests. */
4410 pm_runtime_resume(netdev->dev.parent);
4411
9d5c8243
AK		 4412 if (!netif_carrier_ok(netdev)) {
4413 u32 ctrl;
9005df38 4414
330a6d6a 4415 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4416 &adapter->link_speed,
4417 &adapter->link_duplex);
9d5c8243
AK		 4418
4419 ctrl = rd32(E1000_CTRL);
527d47c1 4420 /* Links status message must follow this format */
c75c4edf
CW		 4421 netdev_info(netdev,
4422 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4423 netdev->name,
4424 adapter->link_speed,
4425 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4426 "Full" : "Half",
4427 (ctrl & E1000_CTRL_TFCE) &&
4428 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4429 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4430 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4431
f4c01e96
CW		 4432 /* disable EEE if enabled */
4433 if ((adapter->flags & IGB_FLAG_EEE) &&
4434 (adapter->link_duplex == HALF_DUPLEX)) {
4435 dev_info(&adapter->pdev->dev,
4436 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4437 adapter->hw.dev_spec._82575.eee_disable = true;
4438 adapter->flags &= ~IGB_FLAG_EEE;
4439 }
4440
c0ba4778
KS		 4441 /* check if SmartSpeed worked */
4442 igb_check_downshift(hw);
4443 if (phy->speed_downgraded)
4444 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4445
563988dc 4446 /* check for thermal sensor event */
876d2d6f 4447 if (igb_thermal_sensor_event(hw,
d34a15ab 4448 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4449 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4450
d07f3e37 4451 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4452 adapter->tx_timeout_factor = 1;
4453 switch (adapter->link_speed) {
4454 case SPEED_10:
9d5c8243
AK		 4455 adapter->tx_timeout_factor = 14;
4456 break;
4457 case SPEED_100:
9d5c8243
AK		 4458 /* maybe add some timeout factor ? */
4459 break;
4460 }
4461
b72f3f72
TU		 4462 if (adapter->link_speed != SPEED_1000)
4463 goto no_wait;
4464
4465 /* wait for Remote receiver status OK */
4466retry_read_status:
4467 if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
4468 &phy_data)) {
4469 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
4470 retry_count) {
4471 msleep(100);
4472 retry_count--;
4473 goto retry_read_status;
4474 } else if (!retry_count) {
4475 dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
4476 }
4477 } else {
4478 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
4479 }
4480no_wait:
9d5c8243 4481 netif_carrier_on(netdev);
9d5c8243 4482
4ae196df 4483 igb_ping_all_vfs(adapter);
17dc566c 4484 igb_check_vf_rate_limit(adapter);
4ae196df 4485
4b1a9877 4486 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4487 if (!test_bit(__IGB_DOWN, &adapter->state))
4488 mod_timer(&adapter->phy_info_timer,
4489 round_jiffies(jiffies + 2 * HZ));
4490 }
4491 } else {
4492 if (netif_carrier_ok(netdev)) {
4493 adapter->link_speed = 0;
4494 adapter->link_duplex = 0;
563988dc
SA		 4495
4496 /* check for thermal sensor event */
876d2d6f
JK		 4497 if (igb_thermal_sensor_event(hw,
4498 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4499 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4500 }
563988dc 4501
527d47c1 4502 /* Links status message must follow this format */
c75c4edf 4503 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4504 netdev->name);
9d5c8243 4505 netif_carrier_off(netdev);
4b1a9877 4506
4ae196df
AD		 4507 igb_ping_all_vfs(adapter);
4508
4b1a9877 4509 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4510 if (!test_bit(__IGB_DOWN, &adapter->state))
4511 mod_timer(&adapter->phy_info_timer,
4512 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4513
56cec249
CW		 4514 /* link is down, time to check for alternate media */
4515 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4516 igb_check_swap_media(adapter);
4517 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4518 schedule_work(&adapter->reset_task);
4519 /* return immediately */
4520 return;
4521 }
4522 }
749ab2cd
YZ		 4523 pm_schedule_suspend(netdev->dev.parent,
4524 MSEC_PER_SEC * 5);
56cec249
CW		 4525
4526 /* also check for alternate media here */
4527 } else if (!netif_carrier_ok(netdev) &&
4528 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4529 igb_check_swap_media(adapter);
4530 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4531 schedule_work(&adapter->reset_task);
4532 /* return immediately */
4533 return;
4534 }
9d5c8243
AK		 4535 }
4536 }
4537
12dcd86b
ED		 4538 spin_lock(&adapter->stats64_lock);
4539 igb_update_stats(adapter, &adapter->stats64);
4540 spin_unlock(&adapter->stats64_lock);
9d5c8243 4541
dbabb065 4542 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4543 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4544 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4545 /* We've lost link, so the controller stops DMA,
4546 * but we've got queued Tx work that's never going
4547 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4548 * (Do the reset outside of interrupt context).
4549 */
dbabb065
AD		 4550 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4551 adapter->tx_timeout_count++;
4552 schedule_work(&adapter->reset_task);
4553 /* return immediately since reset is imminent */
4554 return;
4555 }
9d5c8243 4556 }
9d5c8243 4557
dbabb065 4558 /* Force detection of hung controller every watchdog period */
6d095fa8 4559 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4560 }
f7ba205e 4561
b980ac18 4562 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4563 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4564 u32 eics = 0;
9005df38 4565
0d1ae7f4
AD		 4566 for (i = 0; i < adapter->num_q_vectors; i++)
4567 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4568 wr32(E1000_EICS, eics);
4569 } else {
4570 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4571 }
9d5c8243 4572
13800469 4573 igb_spoof_check(adapter);
fc580751 4574 igb_ptp_rx_hang(adapter);
13800469 4575
1516f0a6
CW		 4576 /* Check LVMMC register on i350/i354 only */
4577 if ((adapter->hw.mac.type == e1000_i350) ||
4578 (adapter->hw.mac.type == e1000_i354))
4579 igb_check_lvmmc(adapter);
4580
9d5c8243 4581 /* Reset the timer */
aa9b8cc4
AA		 4582 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4583 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4584 mod_timer(&adapter->watchdog_timer,
4585 round_jiffies(jiffies + HZ));
4586 else
4587 mod_timer(&adapter->watchdog_timer,
4588 round_jiffies(jiffies + 2 * HZ));
4589 }
9d5c8243
AK		 4590}
4591
4592enum latency_range {
4593 lowest_latency = 0,
4594 low_latency = 1,
4595 bulk_latency = 2,
4596 latency_invalid = 255
4597};
4598
6eb5a7f1 4599/**
b980ac18
JK		 4600 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4601 * @q_vector: pointer to q_vector
6eb5a7f1 4602 *
b980ac18
JK		 4603 * Stores a new ITR value based on strictly on packet size. This
4604 * algorithm is less sophisticated than that used in igb_update_itr,
4605 * due to the difficulty of synchronizing statistics across multiple
4606 * receive rings. The divisors and thresholds used by this function
4607 * were determined based on theoretical maximum wire speed and testing
4608 * data, in order to minimize response time while increasing bulk
4609 * throughput.
406d4965 4610 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4611 * NOTE: This function is called only when operating in a multiqueue
4612 * receive environment.
6eb5a7f1 4613 **/
047e0030 4614static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4615{
047e0030 4616 int new_val = q_vector->itr_val;
6eb5a7f1 4617 int avg_wire_size = 0;
047e0030 4618 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4619 unsigned int packets;
9d5c8243 4620
6eb5a7f1
AD		 4621 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4622 * ints/sec - ITR timer value of 120 ticks.
4623 */
4624 if (adapter->link_speed != SPEED_1000) {
0ba82994 4625 new_val = IGB_4K_ITR;
6eb5a7f1 4626 goto set_itr_val;
9d5c8243 4627 }
047e0030 4628
0ba82994
AD		 4629 packets = q_vector->rx.total_packets;
4630 if (packets)
4631 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4632
0ba82994
AD		 4633 packets = q_vector->tx.total_packets;
4634 if (packets)
4635 avg_wire_size = max_t(u32, avg_wire_size,
4636 q_vector->tx.total_bytes / packets);
047e0030
AD		 4637
4638 /* if avg_wire_size isn't set no work was done */
4639 if (!avg_wire_size)
4640 goto clear_counts;
9d5c8243 4641
6eb5a7f1
AD		 4642 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4643 avg_wire_size += 24;
4644
4645 /* Don't starve jumbo frames */
4646 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4647
6eb5a7f1
AD		 4648 /* Give a little boost to mid-size frames */
4649 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4650 new_val = avg_wire_size / 3;
4651 else
4652 new_val = avg_wire_size / 2;
9d5c8243 4653
0ba82994
AD		 4654 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4655 if (new_val < IGB_20K_ITR &&
4656 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4657 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4658 new_val = IGB_20K_ITR;
abe1c363 4659
6eb5a7f1 4660set_itr_val:
047e0030
AD		 4661 if (new_val != q_vector->itr_val) {
4662 q_vector->itr_val = new_val;
4663 q_vector->set_itr = 1;
9d5c8243 4664 }
6eb5a7f1 4665clear_counts:
0ba82994
AD		 4666 q_vector->rx.total_bytes = 0;
4667 q_vector->rx.total_packets = 0;
4668 q_vector->tx.total_bytes = 0;
4669 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4670}
4671
4672/**
b980ac18
JK		 4673 * igb_update_itr - update the dynamic ITR value based on statistics
4674 * @q_vector: pointer to q_vector
4675 * @ring_container: ring info to update the itr for
4676 *
4677 * Stores a new ITR value based on packets and byte
4678 * counts during the last interrupt. The advantage of per interrupt
4679 * computation is faster updates and more accurate ITR for the current
4680 * traffic pattern. Constants in this function were computed
4681 * based on theoretical maximum wire speed and thresholds were set based
4682 * on testing data as well as attempting to minimize response time
4683 * while increasing bulk throughput.
406d4965 4684 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4685 * NOTE: These calculations are only valid when operating in a single-
4686 * queue environment.
9d5c8243 4687 **/
0ba82994
AD		 4688static void igb_update_itr(struct igb_q_vector *q_vector,
4689 struct igb_ring_container *ring_container)
9d5c8243 4690{
0ba82994
AD		 4691 unsigned int packets = ring_container->total_packets;
4692 unsigned int bytes = ring_container->total_bytes;
4693 u8 itrval = ring_container->itr;
9d5c8243 4694
0ba82994 4695 /* no packets, exit with status unchanged */
9d5c8243 4696 if (packets == 0)
0ba82994 4697 return;
9d5c8243 4698
0ba82994 4699 switch (itrval) {
9d5c8243
AK		 4700 case lowest_latency:
4701 /* handle TSO and jumbo frames */
4702 if (bytes/packets > 8000)
0ba82994 4703 itrval = bulk_latency;
9d5c8243 4704 else if ((packets < 5) && (bytes > 512))
0ba82994 4705 itrval = low_latency;
9d5c8243
AK		 4706 break;
4707 case low_latency: /* 50 usec aka 20000 ints/s */
4708 if (bytes > 10000) {
4709 /* this if handles the TSO accounting */
d34a15ab 4710 if (bytes/packets > 8000)
0ba82994 4711 itrval = bulk_latency;
d34a15ab 4712 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4713 itrval = bulk_latency;
d34a15ab 4714 else if ((packets > 35))
0ba82994 4715 itrval = lowest_latency;
9d5c8243 4716 } else if (bytes/packets > 2000) {
0ba82994 4717 itrval = bulk_latency;
9d5c8243 4718 } else if (packets <= 2 && bytes < 512) {
0ba82994 4719 itrval = lowest_latency;
9d5c8243
AK		 4720 }
4721 break;
4722 case bulk_latency: /* 250 usec aka 4000 ints/s */
4723 if (bytes > 25000) {
4724 if (packets > 35)
0ba82994 4725 itrval = low_latency;
1e5c3d21 4726 } else if (bytes < 1500) {
0ba82994 4727 itrval = low_latency;
9d5c8243
AK		 4728 }
4729 break;
4730 }
4731
0ba82994
AD		 4732 /* clear work counters since we have the values we need */
4733 ring_container->total_bytes = 0;
4734 ring_container->total_packets = 0;
4735
4736 /* write updated itr to ring container */
4737 ring_container->itr = itrval;
9d5c8243
AK		 4738}
4739
0ba82994 4740static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4741{
0ba82994 4742 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4743 u32 new_itr = q_vector->itr_val;
0ba82994 4744 u8 current_itr = 0;
9d5c8243
AK		 4745
4746 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4747 if (adapter->link_speed != SPEED_1000) {
4748 current_itr = 0;
0ba82994 4749 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4750 goto set_itr_now;
4751 }
4752
0ba82994
AD		 4753 igb_update_itr(q_vector, &q_vector->tx);
4754 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4755
0ba82994 4756 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4757
6eb5a7f1 4758 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4759 if (current_itr == lowest_latency &&
4760 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4761 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4762 current_itr = low_latency;
4763
9d5c8243
AK		 4764 switch (current_itr) {
4765 /* counts and packets in update_itr are dependent on these numbers */
4766 case lowest_latency:
0ba82994 4767 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4768 break;
4769 case low_latency:
0ba82994 4770 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4771 break;
4772 case bulk_latency:
0ba82994 4773 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4774 break;
4775 default:
4776 break;
4777 }
4778
4779set_itr_now:
047e0030 4780 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4781 /* this attempts to bias the interrupt rate towards Bulk
4782 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4783 * increasing
4784 */
047e0030 4785 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4786 max((new_itr * q_vector->itr_val) /
4787 (new_itr + (q_vector->itr_val >> 2)),
4788 new_itr) : new_itr;
9d5c8243
AK		 4789 /* Don't write the value here; it resets the adapter's
4790 * internal timer, and causes us to delay far longer than
4791 * we should between interrupts. Instead, we write the ITR
4792 * value at the beginning of the next interrupt so the timing
4793 * ends up being correct.
4794 */
047e0030
AD		 4795 q_vector->itr_val = new_itr;
4796 q_vector->set_itr = 1;
9d5c8243 4797 }
9d5c8243
AK		 4798}
4799
c50b52a0
SH		 4800static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4801 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4802{
4803 struct e1000_adv_tx_context_desc *context_desc;
4804 u16 i = tx_ring->next_to_use;
4805
4806 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4807
4808 i++;
4809 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4810
4811 /* set bits to identify this as an advanced context descriptor */
4812 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4813
4814 /* For 82575, context index must be unique per ring. */
866cff06 4815 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4816 mss_l4len_idx |= tx_ring->reg_idx << 4;
4817
4818 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4819 context_desc->seqnum_seed = 0;
4820 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4821 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4822}
4823
7af40ad9
AD		 4824static int igb_tso(struct igb_ring *tx_ring,
4825 struct igb_tx_buffer *first,
4826 u8 *hdr_len)
9d5c8243 4827{
7af40ad9 4828 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4829 u32 vlan_macip_lens, type_tucmd;
4830 u32 mss_l4len_idx, l4len;
06c14e5a 4831 int err;
7d13a7d0 4832
ed6aa105
AD		 4833 if (skb->ip_summed != CHECKSUM_PARTIAL)
4834 return 0;
4835
7d13a7d0
AD		 4836 if (!skb_is_gso(skb))
4837 return 0;
9d5c8243 4838
06c14e5a
FR		 4839 err = skb_cow_head(skb, 0);
4840 if (err < 0)
4841 return err;
9d5c8243 4842
7d13a7d0
AD		 4843 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4844 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4845
7c4d16ff 4846 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4847 struct iphdr *iph = ip_hdr(skb);
4848 iph->tot_len = 0;
4849 iph->check = 0;
4850 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4851 iph->daddr, 0,
4852 IPPROTO_TCP,
4853 0);
7d13a7d0 4854 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4855 first->tx_flags |= IGB_TX_FLAGS_TSO |
4856 IGB_TX_FLAGS_CSUM |
4857 IGB_TX_FLAGS_IPV4;
8e1e8a47 4858 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4859 ipv6_hdr(skb)->payload_len = 0;
4860 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4861 &ipv6_hdr(skb)->daddr,
4862 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4863 first->tx_flags |= IGB_TX_FLAGS_TSO |
4864 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4865 }
4866
7af40ad9 4867 /* compute header lengths */
7d13a7d0
AD		 4868 l4len = tcp_hdrlen(skb);
4869 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4870
7af40ad9
AD		 4871 /* update gso size and bytecount with header size */
4872 first->gso_segs = skb_shinfo(skb)->gso_segs;
4873 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4874
9d5c8243 4875 /* MSS L4LEN IDX */
7d13a7d0
AD		 4876 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4877 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4878
7d13a7d0
AD		 4879 /* VLAN MACLEN IPLEN */
4880 vlan_macip_lens = skb_network_header_len(skb);
4881 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4882 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4883
7d13a7d0 4884 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4885
7d13a7d0 4886 return 1;
9d5c8243
AK		 4887}
4888
6e033700
AD		 4889static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
4890{
4891 unsigned int offset = 0;
4892
4893 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
4894
4895 return offset == skb_checksum_start_offset(skb);
4896}
4897
7af40ad9 4898static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4899{
7af40ad9 4900 struct sk_buff *skb = first->skb;
7d13a7d0 4901 u32 vlan_macip_lens = 0;
7d13a7d0 4902 u32 type_tucmd = 0;
9d5c8243 4903
7d13a7d0 4904 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6e033700 4905csum_failed:
7af40ad9
AD		 4906 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4907 return;
6e033700
AD		 4908 goto no_csum;
4909 }
fa4a7ef3 4910
6e033700
AD		 4911 switch (skb->csum_offset) {
4912 case offsetof(struct tcphdr, check):
4913 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4914 /* fall through */
4915 case offsetof(struct udphdr, check):
4916 break;
4917 case offsetof(struct sctphdr, checksum):
4918 /* validate that this is actually an SCTP request */
4919 if (((first->protocol == htons(ETH_P_IP)) &&
4920 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
4921 ((first->protocol == htons(ETH_P_IPV6)) &&
4922 igb_ipv6_csum_is_sctp(skb))) {
4923 type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
7d13a7d0 4924 break;
9d5c8243 4925 }
6e033700
AD		 4926 default:
4927 skb_checksum_help(skb);
4928 goto csum_failed;
7d13a7d0 4929 }
9d5c8243 4930
6e033700
AD		 4931 /* update TX checksum flag */
4932 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4933 vlan_macip_lens = skb_checksum_start_offset(skb) -
4934 skb_network_offset(skb);
4935no_csum:
7d13a7d0 4936 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4937 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4938
6e033700 4939 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, 0);
9d5c8243
AK		 4940}
4941
1d9daf45
AD		 4942#define IGB_SET_FLAG(_input, _flag, _result) \
4943 ((_flag <= _result) ? \
4944 ((u32)(_input & _flag) * (_result / _flag)) : \
4945 ((u32)(_input & _flag) / (_flag / _result)))
4946
4947static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4948{
4949 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4950 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4951 E1000_ADVTXD_DCMD_DEXT |
4952 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4953
4954 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4955 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4956 (E1000_ADVTXD_DCMD_VLE));
4957
4958 /* set segmentation bits for TSO */
4959 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4960 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4961
4962 /* set timestamp bit if present */
1d9daf45
AD		 4963 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4964 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4965
1d9daf45
AD		 4966 /* insert frame checksum */
4967 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4968
4969 return cmd_type;
4970}
4971
7af40ad9
AD		 4972static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4973 union e1000_adv_tx_desc *tx_desc,
4974 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4975{
4976 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4977
1d9daf45
AD		 4978 /* 82575 requires a unique index per ring */
4979 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4980 olinfo_status |= tx_ring->reg_idx << 4;
4981
4982 /* insert L4 checksum */
1d9daf45
AD		 4983 olinfo_status |= IGB_SET_FLAG(tx_flags,
4984 IGB_TX_FLAGS_CSUM,
4985 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4986
1d9daf45
AD		 4987 /* insert IPv4 checksum */
4988 olinfo_status |= IGB_SET_FLAG(tx_flags,
4989 IGB_TX_FLAGS_IPV4,
4990 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4991
7af40ad9 4992 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4993}
4994
6f19e12f
DM		 4995static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4996{
4997 struct net_device *netdev = tx_ring->netdev;
4998
4999 netif_stop_subqueue(netdev, tx_ring->queue_index);
5000
5001 /* Herbert's original patch had:
5002 * smp_mb__after_netif_stop_queue();
5003 * but since that doesn't exist yet, just open code it.
5004 */
5005 smp_mb();
5006
5007 /* We need to check again in a case another CPU has just
5008 * made room available.
5009 */
5010 if (igb_desc_unused(tx_ring) < size)
5011 return -EBUSY;
5012
5013 /* A reprieve! */
5014 netif_wake_subqueue(netdev, tx_ring->queue_index);
5015
5016 u64_stats_update_begin(&tx_ring->tx_syncp2);
5017 tx_ring->tx_stats.restart_queue2++;
5018 u64_stats_update_end(&tx_ring->tx_syncp2);
5019
5020 return 0;
5021}
5022
5023static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5024{
5025 if (igb_desc_unused(tx_ring) >= size)
5026 return 0;
5027 return __igb_maybe_stop_tx(tx_ring, size);
5028}
5029
7af40ad9
AD		 5030static void igb_tx_map(struct igb_ring *tx_ring,
5031 struct igb_tx_buffer *first,
ebe42d16 5032 const u8 hdr_len)
9d5c8243 5033{
7af40ad9 5034 struct sk_buff *skb = first->skb;
c9f14bf3 5035 struct igb_tx_buffer *tx_buffer;
ebe42d16 5036 union e1000_adv_tx_desc *tx_desc;
80d0759e 5037 struct skb_frag_struct *frag;
ebe42d16 5038 dma_addr_t dma;
80d0759e 5039 unsigned int data_len, size;
7af40ad9 5040 u32 tx_flags = first->tx_flags;
1d9daf45 5041 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 5042 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 5043
5044 tx_desc = IGB_TX_DESC(tx_ring, i);
5045
80d0759e
AD		 5046 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5047
5048 size = skb_headlen(skb);
5049 data_len = skb->data_len;
ebe42d16
AD		 5050
5051 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 5052
80d0759e
AD		 5053 tx_buffer = first;
5054
5055 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5056 if (dma_mapping_error(tx_ring->dev, dma))
5057 goto dma_error;
5058
5059 /* record length, and DMA address */
5060 dma_unmap_len_set(tx_buffer, len, size);
5061 dma_unmap_addr_set(tx_buffer, dma, dma);
5062
5063 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 5064
ebe42d16
AD		 5065 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5066 tx_desc->read.cmd_type_len =
1d9daf45 5067 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 5068
5069 i++;
5070 tx_desc++;
5071 if (i == tx_ring->count) {
5072 tx_desc = IGB_TX_DESC(tx_ring, 0);
5073 i = 0;
5074 }
80d0759e 5075 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 5076
5077 dma += IGB_MAX_DATA_PER_TXD;
5078 size -= IGB_MAX_DATA_PER_TXD;
5079
ebe42d16
AD		 5080 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5081 }
5082
5083 if (likely(!data_len))
5084 break;
2bbfebe2 5085
1d9daf45 5086 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 5087
65689fef 5088 i++;
ebe42d16
AD		 5089 tx_desc++;
5090 if (i == tx_ring->count) {
5091 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 5092 i = 0;
ebe42d16 5093 }
80d0759e 5094 tx_desc->read.olinfo_status = 0;
65689fef 5095
9e903e08 5096 size = skb_frag_size(frag);
ebe42d16
AD		 5097 data_len -= size;
5098
5099 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 5100 size, DMA_TO_DEVICE);
6366ad33 5101
c9f14bf3 5102 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 5103 }
5104
ebe42d16 5105 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 5106 cmd_type |= size | IGB_TXD_DCMD;
5107 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 5108
80d0759e
AD		 5109 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5110
8542db05
AD		 5111 /* set the timestamp */
5112 first->time_stamp = jiffies;
5113
b980ac18 5114 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 5115 * are new descriptors to fetch. (Only applicable for weak-ordered
5116 * memory model archs, such as IA-64).
5117 *
5118 * We also need this memory barrier to make certain all of the
5119 * status bits have been updated before next_to_watch is written.
5120 */
5121 wmb();
5122
8542db05 5123 /* set next_to_watch value indicating a packet is present */
ebe42d16 5124 first->next_to_watch = tx_desc;
9d5c8243 5125
ebe42d16
AD		 5126 i++;
5127 if (i == tx_ring->count)
5128 i = 0;
6366ad33 5129
ebe42d16 5130 tx_ring->next_to_use = i;
6366ad33 5131
6f19e12f
DM		 5132 /* Make sure there is space in the ring for the next send. */
5133 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
5134
5135 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 5136 writel(i, tx_ring->tail);
5137
5138 /* we need this if more than one processor can write to our tail
5139 * at a time, it synchronizes IO on IA64/Altix systems
5140 */
5141 mmiowb();
5142 }
ebe42d16
AD		 5143 return;
5144
5145dma_error:
5146 dev_err(tx_ring->dev, "TX DMA map failed\n");
5147
5148 /* clear dma mappings for failed tx_buffer_info map */
5149 for (;;) {
c9f14bf3
AD		 5150 tx_buffer = &tx_ring->tx_buffer_info[i];
5151 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5152 if (tx_buffer == first)
ebe42d16 5153 break;
a77ff709
NN		 5154 if (i == 0)
5155 i = tx_ring->count;
6366ad33 5156 i--;
6366ad33
AD		 5157 }
5158
9d5c8243 5159 tx_ring->next_to_use = i;
9d5c8243
AK		 5160}
5161
cd392f5c
AD		 5162netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
5163 struct igb_ring *tx_ring)
9d5c8243 5164{
8542db05 5165 struct igb_tx_buffer *first;
ebe42d16 5166 int tso;
91d4ee33 5167 u32 tx_flags = 0;
2ee52ad4 5168 unsigned short f;
21ba6fe1 5169 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5170 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5171 u8 hdr_len = 0;
9d5c8243 5172
21ba6fe1
AD		 5173 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5174 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5175 * + 2 desc gap to keep tail from touching head,
9d5c8243 5176 * + 1 desc for context descriptor,
21ba6fe1
AD		 5177 * otherwise try next time
5178 */
2ee52ad4
AD		 5179 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5180 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5181
5182 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5183 /* this is a hard error */
9d5c8243
AK		 5184 return NETDEV_TX_BUSY;
5185 }
33af6bcc 5186
7af40ad9
AD		 5187 /* record the location of the first descriptor for this packet */
5188 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5189 first->skb = skb;
5190 first->bytecount = skb->len;
5191 first->gso_segs = 1;
5192
b646c22e
AD		 5193 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5194 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5195
ed4420a3
JK		 5196 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5197 &adapter->state)) {
b646c22e
AD		 5198 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5199 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5200
5201 adapter->ptp_tx_skb = skb_get(skb);
5202 adapter->ptp_tx_start = jiffies;
5203 if (adapter->hw.mac.type == e1000_82576)
5204 schedule_work(&adapter->ptp_tx_work);
5205 }
33af6bcc 5206 }
9d5c8243 5207
afc835d1
JK		 5208 skb_tx_timestamp(skb);
5209
df8a39de 5210 if (skb_vlan_tag_present(skb)) {
9d5c8243 5211 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5212 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5213 }
5214
7af40ad9
AD		 5215 /* record initial flags and protocol */
5216 first->tx_flags = tx_flags;
5217 first->protocol = protocol;
cdfd01fc 5218
7af40ad9
AD		 5219 tso = igb_tso(tx_ring, first, &hdr_len);
5220 if (tso < 0)
7d13a7d0 5221 goto out_drop;
7af40ad9
AD		 5222 else if (!tso)
5223 igb_tx_csum(tx_ring, first);
9d5c8243 5224
7af40ad9 5225 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5226
9d5c8243 5227 return NETDEV_TX_OK;
7d13a7d0
AD		 5228
5229out_drop:
7af40ad9
AD		 5230 igb_unmap_and_free_tx_resource(tx_ring, first);
5231
7d13a7d0 5232 return NETDEV_TX_OK;
9d5c8243
AK		 5233}
5234
0b725a2c
DM		 5235static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5236 struct sk_buff *skb)
1cc3bd87 5237{
0b725a2c
DM		 5238 unsigned int r_idx = skb->queue_mapping;
5239
1cc3bd87
AD		 5240 if (r_idx >= adapter->num_tx_queues)
5241 r_idx = r_idx % adapter->num_tx_queues;
5242
5243 return adapter->tx_ring[r_idx];
5244}
5245
cd392f5c
AD		 5246static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5247 struct net_device *netdev)
9d5c8243
AK		 5248{
5249 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3 5250
b980ac18 5251 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5252 * in order to meet this minimum size requirement.
5253 */
a94d9e22
AD		 5254 if (skb_put_padto(skb, 17))
5255 return NETDEV_TX_OK;
9d5c8243 5256
1cc3bd87 5257 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5258}
5259
5260/**
b980ac18
JK		 5261 * igb_tx_timeout - Respond to a Tx Hang
5262 * @netdev: network interface device structure
9d5c8243
AK		 5263 **/
5264static void igb_tx_timeout(struct net_device *netdev)
5265{
5266 struct igb_adapter *adapter = netdev_priv(netdev);
5267 struct e1000_hw *hw = &adapter->hw;
5268
5269 /* Do the reset outside of interrupt context */
5270 adapter->tx_timeout_count++;
f7ba205e 5271
06218a8d 5272 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5273 hw->dev_spec._82575.global_device_reset = true;
5274
9d5c8243 5275 schedule_work(&adapter->reset_task);
265de409
AD		 5276 wr32(E1000_EICS,
5277 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5278}
5279
5280static void igb_reset_task(struct work_struct *work)
5281{
5282 struct igb_adapter *adapter;
5283 adapter = container_of(work, struct igb_adapter, reset_task);
5284
c97ec42a
TI		 5285 igb_dump(adapter);
5286 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5287 igb_reinit_locked(adapter);
5288}
5289
5290/**
b980ac18
JK		 5291 * igb_get_stats64 - Get System Network Statistics
5292 * @netdev: network interface device structure
5293 * @stats: rtnl_link_stats64 pointer
9d5c8243 5294 **/
12dcd86b 5295static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5296 struct rtnl_link_stats64 *stats)
9d5c8243 5297{
12dcd86b
ED		 5298 struct igb_adapter *adapter = netdev_priv(netdev);
5299
5300 spin_lock(&adapter->stats64_lock);
5301 igb_update_stats(adapter, &adapter->stats64);
5302 memcpy(stats, &adapter->stats64, sizeof(*stats));
5303 spin_unlock(&adapter->stats64_lock);
5304
5305 return stats;
9d5c8243
AK		 5306}
5307
5308/**
b980ac18
JK		 5309 * igb_change_mtu - Change the Maximum Transfer Unit
5310 * @netdev: network interface device structure
5311 * @new_mtu: new value for maximum frame size
9d5c8243 5312 *
b980ac18 5313 * Returns 0 on success, negative on failure
9d5c8243
AK		 5314 **/
5315static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5316{
5317 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5318 struct pci_dev *pdev = adapter->pdev;
153285f9 5319 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5320
c809d227 5321 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5322 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5323 return -EINVAL;
5324 }
5325
153285f9 5326#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5327 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5328 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5329 return -EINVAL;
5330 }
5331
2ccd994c
AD		 5332 /* adjust max frame to be at least the size of a standard frame */
5333 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5334 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5335
9d5c8243 5336 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5337 usleep_range(1000, 2000);
73cd78f1 5338
9d5c8243
AK		 5339 /* igb_down has a dependency on max_frame_size */
5340 adapter->max_frame_size = max_frame;
559e9c49 5341
4c844851
AD		 5342 if (netif_running(netdev))
5343 igb_down(adapter);
9d5c8243 5344
090b1795 5345 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5346 netdev->mtu, new_mtu);
5347 netdev->mtu = new_mtu;
5348
5349 if (netif_running(netdev))
5350 igb_up(adapter);
5351 else
5352 igb_reset(adapter);
5353
5354 clear_bit(__IGB_RESETTING, &adapter->state);
5355
5356 return 0;
5357}
5358
5359/**
b980ac18
JK		 5360 * igb_update_stats - Update the board statistics counters
5361 * @adapter: board private structure
9d5c8243 5362 **/
12dcd86b
ED		 5363void igb_update_stats(struct igb_adapter *adapter,
5364 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5365{
5366 struct e1000_hw *hw = &adapter->hw;
5367 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5368 u32 reg, mpc;
3f9c0164
AD		 5369 int i;
5370 u64 bytes, packets;
12dcd86b
ED		 5371 unsigned int start;
5372 u64 _bytes, _packets;
9d5c8243 5373
b980ac18 5374 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5375 * connection is down.
5376 */
5377 if (adapter->link_speed == 0)
5378 return;
5379 if (pci_channel_offline(pdev))
5380 return;
5381
3f9c0164
AD		 5382 bytes = 0;
5383 packets = 0;
7f90128e
AA		 5384
5385 rcu_read_lock();
3f9c0164 5386 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5387 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5388 u32 rqdpc = rd32(E1000_RQDPC(i));
5389 if (hw->mac.type >= e1000_i210)
5390 wr32(E1000_RQDPC(i), 0);
12dcd86b 5391
ae1c07a6
AD		 5392 if (rqdpc) {
5393 ring->rx_stats.drops += rqdpc;
5394 net_stats->rx_fifo_errors += rqdpc;
5395 }
12dcd86b
ED		 5396
5397 do {
57a7744e 5398 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5399 _bytes = ring->rx_stats.bytes;
5400 _packets = ring->rx_stats.packets;
57a7744e 5401 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5402 bytes += _bytes;
5403 packets += _packets;
3f9c0164
AD		 5404 }
5405
128e45eb
AD		 5406 net_stats->rx_bytes = bytes;
5407 net_stats->rx_packets = packets;
3f9c0164
AD		 5408
5409 bytes = 0;
5410 packets = 0;
5411 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5412 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5413 do {
57a7744e 5414 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5415 _bytes = ring->tx_stats.bytes;
5416 _packets = ring->tx_stats.packets;
57a7744e 5417 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5418 bytes += _bytes;
5419 packets += _packets;
3f9c0164 5420 }
128e45eb
AD		 5421 net_stats->tx_bytes = bytes;
5422 net_stats->tx_packets = packets;
7f90128e 5423 rcu_read_unlock();
3f9c0164
AD		 5424
5425 /* read stats registers */
9d5c8243
AK		 5426 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5427 adapter->stats.gprc += rd32(E1000_GPRC);
5428 adapter->stats.gorc += rd32(E1000_GORCL);
5429 rd32(E1000_GORCH); /* clear GORCL */
5430 adapter->stats.bprc += rd32(E1000_BPRC);
5431 adapter->stats.mprc += rd32(E1000_MPRC);
5432 adapter->stats.roc += rd32(E1000_ROC);
5433
5434 adapter->stats.prc64 += rd32(E1000_PRC64);
5435 adapter->stats.prc127 += rd32(E1000_PRC127);
5436 adapter->stats.prc255 += rd32(E1000_PRC255);
5437 adapter->stats.prc511 += rd32(E1000_PRC511);
5438 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5439 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5440 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5441 adapter->stats.sec += rd32(E1000_SEC);
5442
fa3d9a6d
MW		 5443 mpc = rd32(E1000_MPC);
5444 adapter->stats.mpc += mpc;
5445 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5446 adapter->stats.scc += rd32(E1000_SCC);
5447 adapter->stats.ecol += rd32(E1000_ECOL);
5448 adapter->stats.mcc += rd32(E1000_MCC);
5449 adapter->stats.latecol += rd32(E1000_LATECOL);
5450 adapter->stats.dc += rd32(E1000_DC);
5451 adapter->stats.rlec += rd32(E1000_RLEC);
5452 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5453 adapter->stats.xontxc += rd32(E1000_XONTXC);
5454 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5455 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5456 adapter->stats.fcruc += rd32(E1000_FCRUC);
5457 adapter->stats.gptc += rd32(E1000_GPTC);
5458 adapter->stats.gotc += rd32(E1000_GOTCL);
5459 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5460 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5461 adapter->stats.ruc += rd32(E1000_RUC);
5462 adapter->stats.rfc += rd32(E1000_RFC);
5463 adapter->stats.rjc += rd32(E1000_RJC);
5464 adapter->stats.tor += rd32(E1000_TORH);
5465 adapter->stats.tot += rd32(E1000_TOTH);
5466 adapter->stats.tpr += rd32(E1000_TPR);
5467
5468 adapter->stats.ptc64 += rd32(E1000_PTC64);
5469 adapter->stats.ptc127 += rd32(E1000_PTC127);
5470 adapter->stats.ptc255 += rd32(E1000_PTC255);
5471 adapter->stats.ptc511 += rd32(E1000_PTC511);
5472 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5473 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5474
5475 adapter->stats.mptc += rd32(E1000_MPTC);
5476 adapter->stats.bptc += rd32(E1000_BPTC);
5477
2d0b0f69
NN		 5478 adapter->stats.tpt += rd32(E1000_TPT);
5479 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5480
5481 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5482 /* read internal phy specific stats */
5483 reg = rd32(E1000_CTRL_EXT);
5484 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5485 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5486
5487 /* this stat has invalid values on i210/i211 */
5488 if ((hw->mac.type != e1000_i210) &&
5489 (hw->mac.type != e1000_i211))
5490 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5491 }
5492
9d5c8243
AK		 5493 adapter->stats.tsctc += rd32(E1000_TSCTC);
5494 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5495
5496 adapter->stats.iac += rd32(E1000_IAC);
5497 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5498 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5499 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5500 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5501 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5502 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5503 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5504 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5505
5506 /* Fill out the OS statistics structure */
128e45eb
AD		 5507 net_stats->multicast = adapter->stats.mprc;
5508 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5509
5510 /* Rx Errors */
5511
5512 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5513 * our own version based on RUC and ROC
5514 */
128e45eb 5515 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5516 adapter->stats.crcerrs + adapter->stats.algnerrc +
5517 adapter->stats.ruc + adapter->stats.roc +
5518 adapter->stats.cexterr;
128e45eb
AD		 5519 net_stats->rx_length_errors = adapter->stats.ruc +
5520 adapter->stats.roc;
5521 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5522 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5523 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5524
5525 /* Tx Errors */
128e45eb
AD		 5526 net_stats->tx_errors = adapter->stats.ecol +
5527 adapter->stats.latecol;
5528 net_stats->tx_aborted_errors = adapter->stats.ecol;
5529 net_stats->tx_window_errors = adapter->stats.latecol;
5530 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5531
5532 /* Tx Dropped needs to be maintained elsewhere */
5533
9d5c8243
AK		 5534 /* Management Stats */
5535 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5536 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5537 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5538
5539 /* OS2BMC Stats */
5540 reg = rd32(E1000_MANC);
5541 if (reg & E1000_MANC_EN_BMC2OS) {
5542 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5543 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5544 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5545 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5546 }
9d5c8243
AK		 5547}
5548
61d7f75f
RC		 5549static void igb_tsync_interrupt(struct igb_adapter *adapter)
5550{
5551 struct e1000_hw *hw = &adapter->hw;
00c65578 5552 struct ptp_clock_event event;
40c9b079 5553 struct timespec64 ts;
720db4ff 5554 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5555
5556 if (tsicr & TSINTR_SYS_WRAP) {
5557 event.type = PTP_CLOCK_PPS;
5558 if (adapter->ptp_caps.pps)
5559 ptp_clock_event(adapter->ptp_clock, &event);
5560 else
5561 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5562 ack |= TSINTR_SYS_WRAP;
5563 }
61d7f75f
RC		 5564
5565 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5566 /* retrieve hardware timestamp */
5567 schedule_work(&adapter->ptp_tx_work);
00c65578 5568 ack |= E1000_TSICR_TXTS;
61d7f75f 5569 }
00c65578 5570
720db4ff
RC		 5571 if (tsicr & TSINTR_TT0) {
5572 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5573 ts = timespec64_add(adapter->perout[0].start,
5574 adapter->perout[0].period);
5575 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5576 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5577 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5578 tsauxc = rd32(E1000_TSAUXC);
5579 tsauxc |= TSAUXC_EN_TT0;
5580 wr32(E1000_TSAUXC, tsauxc);
5581 adapter->perout[0].start = ts;
5582 spin_unlock(&adapter->tmreg_lock);
5583 ack |= TSINTR_TT0;
5584 }
5585
5586 if (tsicr & TSINTR_TT1) {
5587 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5588 ts = timespec64_add(adapter->perout[1].start,
5589 adapter->perout[1].period);
720db4ff 5590 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5591 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5592 tsauxc = rd32(E1000_TSAUXC);
5593 tsauxc |= TSAUXC_EN_TT1;
5594 wr32(E1000_TSAUXC, tsauxc);
5595 adapter->perout[1].start = ts;
5596 spin_unlock(&adapter->tmreg_lock);
5597 ack |= TSINTR_TT1;
5598 }
5599
5600 if (tsicr & TSINTR_AUTT0) {
5601 nsec = rd32(E1000_AUXSTMPL0);
5602 sec = rd32(E1000_AUXSTMPH0);
5603 event.type = PTP_CLOCK_EXTTS;
5604 event.index = 0;
5605 event.timestamp = sec * 1000000000ULL + nsec;
5606 ptp_clock_event(adapter->ptp_clock, &event);
5607 ack |= TSINTR_AUTT0;
5608 }
5609
5610 if (tsicr & TSINTR_AUTT1) {
5611 nsec = rd32(E1000_AUXSTMPL1);
5612 sec = rd32(E1000_AUXSTMPH1);
5613 event.type = PTP_CLOCK_EXTTS;
5614 event.index = 1;
5615 event.timestamp = sec * 1000000000ULL + nsec;
5616 ptp_clock_event(adapter->ptp_clock, &event);
5617 ack |= TSINTR_AUTT1;
5618 }
5619
00c65578
RC		 5620 /* acknowledge the interrupts */
5621 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5622}
5623
9d5c8243
AK		 5624static irqreturn_t igb_msix_other(int irq, void *data)
5625{
047e0030 5626 struct igb_adapter *adapter = data;
9d5c8243 5627 struct e1000_hw *hw = &adapter->hw;
844290e5 5628 u32 icr = rd32(E1000_ICR);
844290e5 5629 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5630
7f081d40
AD		 5631 if (icr & E1000_ICR_DRSTA)
5632 schedule_work(&adapter->reset_task);
5633
047e0030 5634 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5635 /* HW is reporting DMA is out of sync */
5636 adapter->stats.doosync++;
13800469
GR		 5637 /* The DMA Out of Sync is also indication of a spoof event
5638 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5639 * see if it is really a spoof event.
5640 */
13800469 5641 igb_check_wvbr(adapter);
dda0e083 5642 }
eebbbdba 5643
4ae196df
AD		 5644 /* Check for a mailbox event */
5645 if (icr & E1000_ICR_VMMB)
5646 igb_msg_task(adapter);
5647
5648 if (icr & E1000_ICR_LSC) {
5649 hw->mac.get_link_status = 1;
5650 /* guard against interrupt when we're going down */
5651 if (!test_bit(__IGB_DOWN, &adapter->state))
5652 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5653 }
5654
61d7f75f
RC		 5655 if (icr & E1000_ICR_TS)
5656 igb_tsync_interrupt(adapter);
1f6e8178 5657
844290e5 5658 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5659
5660 return IRQ_HANDLED;
5661}
5662
047e0030 5663static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5664{
26b39276 5665 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5666 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5667
047e0030
AD		 5668 if (!q_vector->set_itr)
5669 return;
73cd78f1 5670
047e0030
AD		 5671 if (!itr_val)
5672 itr_val = 0x4;
661086df 5673
26b39276
AD		 5674 if (adapter->hw.mac.type == e1000_82575)
5675 itr_val |= itr_val << 16;
661086df 5676 else
0ba82994 5677 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5678
047e0030
AD		 5679 writel(itr_val, q_vector->itr_register);
5680 q_vector->set_itr = 0;
6eb5a7f1
AD		 5681}
5682
047e0030 5683static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5684{
047e0030 5685 struct igb_q_vector *q_vector = data;
9d5c8243 5686
047e0030
AD		 5687 /* Write the ITR value calculated from the previous interrupt. */
5688 igb_write_itr(q_vector);
9d5c8243 5689
047e0030 5690 napi_schedule(&q_vector->napi);
844290e5 5691
047e0030 5692 return IRQ_HANDLED;
fe4506b6
JC		 5693}
5694
421e02f0 5695#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5696static void igb_update_tx_dca(struct igb_adapter *adapter,
5697 struct igb_ring *tx_ring,
5698 int cpu)
5699{
5700 struct e1000_hw *hw = &adapter->hw;
5701 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5702
5703 if (hw->mac.type != e1000_82575)
5704 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5705
b980ac18 5706 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5707 * DCA is enabled. This is due to a known issue in some chipsets
5708 * which will cause the DCA tag to be cleared.
5709 */
5710 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5711 E1000_DCA_TXCTRL_DATA_RRO_EN |
5712 E1000_DCA_TXCTRL_DESC_DCA_EN;
5713
5714 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5715}
5716
5717static void igb_update_rx_dca(struct igb_adapter *adapter,
5718 struct igb_ring *rx_ring,
5719 int cpu)
5720{
5721 struct e1000_hw *hw = &adapter->hw;
5722 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5723
5724 if (hw->mac.type != e1000_82575)
5725 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5726
b980ac18 5727 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5728 * DCA is enabled. This is due to a known issue in some chipsets
5729 * which will cause the DCA tag to be cleared.
5730 */
5731 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5732 E1000_DCA_RXCTRL_DESC_DCA_EN;
5733
5734 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5735}
5736
047e0030 5737static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5738{
047e0030 5739 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5740 int cpu = get_cpu();
fe4506b6 5741
047e0030
AD		 5742 if (q_vector->cpu == cpu)
5743 goto out_no_update;
5744
6a05004a
AD		 5745 if (q_vector->tx.ring)
5746 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5747
5748 if (q_vector->rx.ring)
5749 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5750
047e0030
AD		 5751 q_vector->cpu = cpu;
5752out_no_update:
fe4506b6
JC		 5753 put_cpu();
5754}
5755
5756static void igb_setup_dca(struct igb_adapter *adapter)
5757{
7e0e99ef 5758 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5759 int i;
5760
7dfc16fa 5761 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5762 return;
5763
7e0e99ef
AD		 5764 /* Always use CB2 mode, difference is masked in the CB driver. */
5765 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5766
047e0030 5767 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5768 adapter->q_vector[i]->cpu = -1;
5769 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5770 }
5771}
5772
5773static int __igb_notify_dca(struct device *dev, void *data)
5774{
5775 struct net_device *netdev = dev_get_drvdata(dev);
5776 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5777 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5778 struct e1000_hw *hw = &adapter->hw;
5779 unsigned long event = *(unsigned long *)data;
5780
5781 switch (event) {
5782 case DCA_PROVIDER_ADD:
5783 /* if already enabled, don't do it again */
7dfc16fa 5784 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5785 break;
fe4506b6 5786 if (dca_add_requester(dev) == 0) {
bbd98fe4 5787 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5788 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5789 igb_setup_dca(adapter);
5790 break;
5791 }
5792 /* Fall Through since DCA is disabled. */
5793 case DCA_PROVIDER_REMOVE:
7dfc16fa 5794 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5795 /* without this a class_device is left
b980ac18
JK		 5796 * hanging around in the sysfs model
5797 */
fe4506b6 5798 dca_remove_requester(dev);
090b1795 5799 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5800 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5801 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5802 }
5803 break;
5804 }
bbd98fe4 5805
fe4506b6 5806 return 0;
9d5c8243
AK		 5807}
5808
fe4506b6 5809static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5810 void *p)
fe4506b6
JC		 5811{
5812 int ret_val;
5813
5814 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5815 __igb_notify_dca);
fe4506b6
JC		 5816
5817 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5818}
421e02f0 5819#endif /* CONFIG_IGB_DCA */
9d5c8243 5820
0224d663
GR		 5821#ifdef CONFIG_PCI_IOV
5822static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5823{
5824 unsigned char mac_addr[ETH_ALEN];
0224d663 5825
5ac6f91d 5826 eth_zero_addr(mac_addr);
0224d663
GR		 5827 igb_set_vf_mac(adapter, vf, mac_addr);
5828
70ea4783
LL		 5829 /* By default spoof check is enabled for all VFs */
5830 adapter->vf_data[vf].spoofchk_enabled = true;
5831
f557147c 5832 return 0;
0224d663
GR		 5833}
5834
0224d663 5835#endif
4ae196df
AD		 5836static void igb_ping_all_vfs(struct igb_adapter *adapter)
5837{
5838 struct e1000_hw *hw = &adapter->hw;
5839 u32 ping;
5840 int i;
5841
5842 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5843 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5844 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5845 ping |= E1000_VT_MSGTYPE_CTS;
5846 igb_write_mbx(hw, &ping, 1, i);
5847 }
5848}
5849
7d5753f0
AD		 5850static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5851{
5852 struct e1000_hw *hw = &adapter->hw;
5853 u32 vmolr = rd32(E1000_VMOLR(vf));
5854 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5855
d85b9004 5856 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5857 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5858 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5859
5860 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5861 vmolr |= E1000_VMOLR_MPME;
d85b9004 5862 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5863 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5864 } else {
b980ac18 5865 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5866 * flag we need to write the hashes to the MTA as this step
5867 * was previously skipped
5868 */
5869 if (vf_data->num_vf_mc_hashes > 30) {
5870 vmolr |= E1000_VMOLR_MPME;
5871 } else if (vf_data->num_vf_mc_hashes) {
5872 int j;
9005df38 5873
7d5753f0
AD		 5874 vmolr |= E1000_VMOLR_ROMPE;
5875 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5876 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5877 }
5878 }
5879
5880 wr32(E1000_VMOLR(vf), vmolr);
5881
5882 /* there are flags left unprocessed, likely not supported */
5883 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5884 return -EINVAL;
5885
5886 return 0;
7d5753f0
AD		 5887}
5888
4ae196df
AD		 5889static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5890 u32 *msgbuf, u32 vf)
5891{
5892 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5893 u16 *hash_list = (u16 *)&msgbuf[1];
5894 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5895 int i;
5896
7d5753f0 5897 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5898 * to this VF for later use to restore when the PF multi cast
5899 * list changes
5900 */
5901 vf_data->num_vf_mc_hashes = n;
5902
7d5753f0
AD		 5903 /* only up to 30 hash values supported */
5904 if (n > 30)
5905 n = 30;
5906
5907 /* store the hashes for later use */
4ae196df 5908 for (i = 0; i < n; i++)
a419aef8 5909 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5910
5911 /* Flush and reset the mta with the new values */
ff41f8dc 5912 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5913
5914 return 0;
5915}
5916
5917static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5918{
5919 struct e1000_hw *hw = &adapter->hw;
5920 struct vf_data_storage *vf_data;
5921 int i, j;
5922
5923 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5924 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5925
7d5753f0
AD		 5926 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5927
4ae196df 5928 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5929
5930 if ((vf_data->num_vf_mc_hashes > 30) ||
5931 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5932 vmolr |= E1000_VMOLR_MPME;
5933 } else if (vf_data->num_vf_mc_hashes) {
5934 vmolr |= E1000_VMOLR_ROMPE;
5935 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5936 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5937 }
5938 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5939 }
5940}
5941
5942static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5943{
5944 struct e1000_hw *hw = &adapter->hw;
16903caa 5945 u32 pool_mask, vlvf_mask, i;
4ae196df 5946
16903caa
AD		 5947 /* create mask for VF and other pools */
5948 pool_mask = E1000_VLVF_POOLSEL_MASK;
5949 vlvf_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5950
5951 /* drop PF from pool bits */
5952 pool_mask &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT +
5953 adapter->vfs_allocated_count));
4ae196df
AD		 5954
5955 /* Find the vlan filter for this id */
16903caa
AD		 5956 for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
5957 u32 vlvf = rd32(E1000_VLVF(i));
5958 u32 vfta_mask, vid, vfta;
4ae196df
AD		 5959
5960 /* remove the vf from the pool */
16903caa
AD		 5961 if (!(vlvf & vlvf_mask))
5962 continue;
5963
5964 /* clear out bit from VLVF */
5965 vlvf ^= vlvf_mask;
5966
5967 /* if other pools are present, just remove ourselves */
5968 if (vlvf & pool_mask)
5969 goto update_vlvfb;
5970
5971 /* if PF is present, leave VFTA */
5972 if (vlvf & E1000_VLVF_POOLSEL_MASK)
5973 goto update_vlvf;
4ae196df 5974
16903caa
AD		 5975 vid = vlvf & E1000_VLVF_VLANID_MASK;
5976 vfta_mask = 1 << (vid % 32);
5977
5978 /* clear bit from VFTA */
5979 vfta = adapter->shadow_vfta[vid / 32];
5980 if (vfta & vfta_mask)
5981 hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
5982update_vlvf:
5983 /* clear pool selection enable */
5984 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
5985 vlvf &= E1000_VLVF_POOLSEL_MASK;
5986 else
5987 vlvf = 0;
5988update_vlvfb:
5989 /* clear pool bits */
5990 wr32(E1000_VLVF(i), vlvf);
4ae196df
AD		 5991 }
5992}
5993
16903caa 5994static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6f3dc319 5995{
16903caa
AD		 5996 u32 vlvf;
5997 int idx;
6f3dc319 5998
16903caa
AD		 5999 /* short cut the special case */
6000 if (vlan == 0)
6001 return 0;
6002
6003 /* Search for the VLAN id in the VLVF entries */
6004 for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6005 vlvf = rd32(E1000_VLVF(idx));
6006 if ((vlvf & VLAN_VID_MASK) == vlan)
6f3dc319
GR		 6007 break;
6008 }
6009
16903caa
AD		 6010 return idx;
6011}
6012
6013void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6014{
6015 struct e1000_hw *hw = &adapter->hw;
6016 u32 bits, pf_id;
6017 int idx;
6018
6019 idx = igb_find_vlvf_entry(hw, vid);
6020 if (!idx)
6021 return;
6f3dc319 6022
16903caa
AD		 6023 /* See if any other pools are set for this VLAN filter
6024 * entry other than the PF.
6025 */
6026 pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6027 bits = ~(1 << pf_id) & E1000_VLVF_POOLSEL_MASK;
6028 bits &= rd32(E1000_VLVF(idx));
6029
6030 /* Disable the filter so this falls into the default pool. */
6031 if (!bits) {
6032 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6033 wr32(E1000_VLVF(idx), 1 << pf_id);
6034 else
6035 wr32(E1000_VLVF(idx), 0);
6036 }
6f3dc319
GR		 6037}
6038
a15d9259
AD		 6039static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6040 bool add, u32 vf)
4ae196df 6041{
a15d9259 6042 int pf_id = adapter->vfs_allocated_count;
6f3dc319 6043 struct e1000_hw *hw = &adapter->hw;
a15d9259 6044 int err;
4ae196df 6045
a15d9259
AD		 6046 /* If VLAN overlaps with one the PF is currently monitoring make
6047 * sure that we are able to allocate a VLVF entry. This may be
6048 * redundant but it guarantees PF will maintain visibility to
6049 * the VLAN.
6f3dc319 6050 */
16903caa 6051 if (add && test_bit(vid, adapter->active_vlans)) {
a15d9259
AD		 6052 err = igb_vfta_set(hw, vid, pf_id, true, false);
6053 if (err)
6054 return err;
6055 }
6f3dc319 6056
a15d9259 6057 err = igb_vfta_set(hw, vid, vf, add, false);
6f3dc319 6058
16903caa
AD		 6059 if (add && !err)
6060 return err;
6f3dc319 6061
16903caa
AD		 6062 /* If we failed to add the VF VLAN or we are removing the VF VLAN
6063 * we may need to drop the PF pool bit in order to allow us to free
6064 * up the VLVF resources.
6f3dc319 6065 */
16903caa
AD		 6066 if (test_bit(vid, adapter->active_vlans) ||
6067 (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6068 igb_update_pf_vlvf(adapter, vid);
6f3dc319 6069
6f3dc319 6070 return err;
4ae196df
AD		 6071}
6072
a15d9259 6073static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
4ae196df 6074{
a15d9259
AD		 6075 struct e1000_hw *hw = &adapter->hw;
6076
6077 if (vid)
6078 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6079 else
6080 wr32(E1000_VMVIR(vf), 0);
6081}
6082
6083static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6084 u16 vlan, u8 qos)
6085{
6086 int err;
6087
6088 err = igb_set_vf_vlan(adapter, vlan, true, vf);
6089 if (err)
6090 return err;
6091
6092 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
6093 igb_set_vmolr(adapter, vf, !vlan);
6094
6095 /* revoke access to previous VLAN */
6096 if (vlan != adapter->vf_data[vf].pf_vlan)
6097 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6098 false, vf);
6099
6100 adapter->vf_data[vf].pf_vlan = vlan;
6101 adapter->vf_data[vf].pf_qos = qos;
6102 dev_info(&adapter->pdev->dev,
6103 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
6104 if (test_bit(__IGB_DOWN, &adapter->state)) {
6105 dev_warn(&adapter->pdev->dev,
6106 "The VF VLAN has been set, but the PF device is not up.\n");
6107 dev_warn(&adapter->pdev->dev,
6108 "Bring the PF device up before attempting to use the VF device.\n");
6109 }
6110
6111 return err;
6112}
4ae196df 6113
a15d9259
AD		 6114static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
6115{
6116 /* Restore tagless access via VLAN 0 */
6117 igb_set_vf_vlan(adapter, 0, true, vf);
6118
6119 igb_set_vmvir(adapter, 0, vf);
8151d294 6120 igb_set_vmolr(adapter, vf, true);
4ae196df 6121
a15d9259
AD		 6122 /* Remove any PF assigned VLAN */
6123 if (adapter->vf_data[vf].pf_vlan)
6124 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
6125 false, vf);
6126
6127 adapter->vf_data[vf].pf_vlan = 0;
6128 adapter->vf_data[vf].pf_qos = 0;
6129
6130 return 0;
6131}
6132
6133static int igb_ndo_set_vf_vlan(struct net_device *netdev,
6134 int vf, u16 vlan, u8 qos)
6135{
6136 struct igb_adapter *adapter = netdev_priv(netdev);
6137
6138 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
6139 return -EINVAL;
6140
6141 return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
6142 igb_disable_port_vlan(adapter, vf);
6143}
6144
6145static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6146{
6147 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6148 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6149
6150 if (adapter->vf_data[vf].pf_vlan)
6151 return -1;
6152
6153 /* VLAN 0 is a special case, don't allow it to be removed */
6154 if (!vid && !add)
6155 return 0;
6156
6157 return igb_set_vf_vlan(adapter, vid, !!add, vf);
6158}
6159
6160static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
6161{
6162 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6163
6164 /* clear flags - except flag that indicates PF has set the MAC */
6165 vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
6166 vf_data->last_nack = jiffies;
6167
4ae196df
AD		 6168 /* reset vlans for device */
6169 igb_clear_vf_vfta(adapter, vf);
a15d9259
AD		 6170 igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
6171 igb_set_vmvir(adapter, vf_data->pf_vlan |
6172 (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
6173 igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
4ae196df
AD		 6174
6175 /* reset multicast table array for vf */
6176 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6177
6178 /* Flush and reset the mta with the new values */
ff41f8dc 6179 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6180}
6181
f2ca0dbe
AD		 6182static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6183{
6184 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6185
5ac6f91d 6186 /* clear mac address as we were hotplug removed/added */
8151d294 6187 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6188 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6189
6190 /* process remaining reset events */
6191 igb_vf_reset(adapter, vf);
6192}
6193
6194static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6195{
6196 struct e1000_hw *hw = &adapter->hw;
6197 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6198 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6199 u32 reg, msgbuf[3];
6200 u8 *addr = (u8 *)(&msgbuf[1]);
6201
6202 /* process all the same items cleared in a function level reset */
f2ca0dbe 6203 igb_vf_reset(adapter, vf);
4ae196df
AD		 6204
6205 /* set vf mac address */
26ad9178 6206 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6207
6208 /* enable transmit and receive for vf */
6209 reg = rd32(E1000_VFTE);
6210 wr32(E1000_VFTE, reg | (1 << vf));
6211 reg = rd32(E1000_VFRE);
6212 wr32(E1000_VFRE, reg | (1 << vf));
6213
8fa7e0f7 6214 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6215
6216 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6217 if (!is_zero_ether_addr(vf_mac)) {
6218 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6219 memcpy(addr, vf_mac, ETH_ALEN);
6220 } else {
6221 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6222 }
4ae196df
AD		 6223 igb_write_mbx(hw, msgbuf, 3, vf);
6224}
6225
6226static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6227{
b980ac18 6228 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6229 * starting at the second 32 bit word of the msg array
6230 */
f2ca0dbe
AD		 6231 unsigned char *addr = (char *)&msg[1];
6232 int err = -1;
4ae196df 6233
f2ca0dbe
AD		 6234 if (is_valid_ether_addr(addr))
6235 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6236
f2ca0dbe 6237 return err;
4ae196df
AD		 6238}
6239
6240static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6241{
6242 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6243 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6244 u32 msg = E1000_VT_MSGTYPE_NACK;
6245
6246 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6247 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6248 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6249 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6250 vf_data->last_nack = jiffies;
4ae196df
AD		 6251 }
6252}
6253
f2ca0dbe 6254static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6255{
f2ca0dbe
AD		 6256 struct pci_dev *pdev = adapter->pdev;
6257 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6258 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6259 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6260 s32 retval;
6261
f2ca0dbe 6262 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6263
fef45f4c
AD		 6264 if (retval) {
6265 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6266 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6267 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6268 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6269 return;
6270 goto out;
6271 }
4ae196df
AD		 6272
6273 /* this is a message we already processed, do nothing */
6274 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6275 return;
4ae196df 6276
b980ac18 6277 /* until the vf completes a reset it should not be
4ae196df
AD		 6278 * allowed to start any configuration.
6279 */
4ae196df
AD		 6280 if (msgbuf[0] == E1000_VF_RESET) {
6281 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6282 return;
4ae196df
AD		 6283 }
6284
f2ca0dbe 6285 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6286 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6287 return;
6288 retval = -1;
6289 goto out;
4ae196df
AD		 6290 }
6291
6292 switch ((msgbuf[0] & 0xFFFF)) {
6293 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6294 retval = -EINVAL;
6295 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6296 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6297 else
6298 dev_warn(&pdev->dev,
b980ac18
JK		 6299 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6300 vf);
4ae196df 6301 break;
7d5753f0
AD		 6302 case E1000_VF_SET_PROMISC:
6303 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6304 break;
4ae196df
AD		 6305 case E1000_VF_SET_MULTICAST:
6306 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6307 break;
6308 case E1000_VF_SET_LPE:
6309 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6310 break;
6311 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6312 retval = -1;
6313 if (vf_data->pf_vlan)
6314 dev_warn(&pdev->dev,
b980ac18
JK		 6315 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6316 vf);
8151d294 6317 else
a15d9259 6318 retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
4ae196df
AD		 6319 break;
6320 default:
090b1795 6321 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6322 retval = -1;
6323 break;
6324 }
6325
fef45f4c
AD		 6326 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6327out:
4ae196df
AD		 6328 /* notify the VF of the results of what it sent us */
6329 if (retval)
6330 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6331 else
6332 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6333
4ae196df 6334 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6335}
4ae196df 6336
f2ca0dbe
AD		 6337static void igb_msg_task(struct igb_adapter *adapter)
6338{
6339 struct e1000_hw *hw = &adapter->hw;
6340 u32 vf;
6341
6342 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6343 /* process any reset requests */
6344 if (!igb_check_for_rst(hw, vf))
6345 igb_vf_reset_event(adapter, vf);
6346
6347 /* process any messages pending */
6348 if (!igb_check_for_msg(hw, vf))
6349 igb_rcv_msg_from_vf(adapter, vf);
6350
6351 /* process any acks */
6352 if (!igb_check_for_ack(hw, vf))
6353 igb_rcv_ack_from_vf(adapter, vf);
6354 }
4ae196df
AD		 6355}
6356
68d480c4
AD		 6357/**
6358 * igb_set_uta - Set unicast filter table address
6359 * @adapter: board private structure
bf456abb 6360 * @set: boolean indicating if we are setting or clearing bits
68d480c4
AD		 6361 *
6362 * The unicast table address is a register array of 32-bit registers.
6363 * The table is meant to be used in a way similar to how the MTA is used
6364 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6365 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6366 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4 6367 **/
bf456abb 6368static void igb_set_uta(struct igb_adapter *adapter, bool set)
68d480c4
AD		 6369{
6370 struct e1000_hw *hw = &adapter->hw;
bf456abb 6371 u32 uta = set ? ~0 : 0;
68d480c4
AD		 6372 int i;
6373
68d480c4
AD		 6374 /* we only need to do this if VMDq is enabled */
6375 if (!adapter->vfs_allocated_count)
6376 return;
6377
bf456abb
AD		 6378 for (i = hw->mac.uta_reg_count; i--;)
6379 array_wr32(E1000_UTA, i, uta);
68d480c4
AD		 6380}
6381
9d5c8243 6382/**
b980ac18
JK		 6383 * igb_intr_msi - Interrupt Handler
6384 * @irq: interrupt number
6385 * @data: pointer to a network interface device structure
9d5c8243
AK		 6386 **/
6387static irqreturn_t igb_intr_msi(int irq, void *data)
6388{
047e0030
AD		 6389 struct igb_adapter *adapter = data;
6390 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6391 struct e1000_hw *hw = &adapter->hw;
6392 /* read ICR disables interrupts using IAM */
6393 u32 icr = rd32(E1000_ICR);
6394
047e0030 6395 igb_write_itr(q_vector);
9d5c8243 6396
7f081d40
AD		 6397 if (icr & E1000_ICR_DRSTA)
6398 schedule_work(&adapter->reset_task);
6399
047e0030 6400 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6401 /* HW is reporting DMA is out of sync */
6402 adapter->stats.doosync++;
6403 }
6404
9d5c8243
AK		 6405 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6406 hw->mac.get_link_status = 1;
6407 if (!test_bit(__IGB_DOWN, &adapter->state))
6408 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6409 }
6410
61d7f75f
RC		 6411 if (icr & E1000_ICR_TS)
6412 igb_tsync_interrupt(adapter);
1f6e8178 6413
047e0030 6414 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6415
6416 return IRQ_HANDLED;
6417}
6418
6419/**
b980ac18
JK		 6420 * igb_intr - Legacy Interrupt Handler
6421 * @irq: interrupt number
6422 * @data: pointer to a network interface device structure
9d5c8243
AK		 6423 **/
6424static irqreturn_t igb_intr(int irq, void *data)
6425{
047e0030
AD		 6426 struct igb_adapter *adapter = data;
6427 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6428 struct e1000_hw *hw = &adapter->hw;
6429 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6430 * need for the IMC write
6431 */
9d5c8243 6432 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6433
6434 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6435 * not set, then the adapter didn't send an interrupt
6436 */
9d5c8243
AK		 6437 if (!(icr & E1000_ICR_INT_ASSERTED))
6438 return IRQ_NONE;
6439
0ba82994
AD		 6440 igb_write_itr(q_vector);
6441
7f081d40
AD		 6442 if (icr & E1000_ICR_DRSTA)
6443 schedule_work(&adapter->reset_task);
6444
047e0030 6445 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6446 /* HW is reporting DMA is out of sync */
6447 adapter->stats.doosync++;
6448 }
6449
9d5c8243
AK		 6450 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6451 hw->mac.get_link_status = 1;
6452 /* guard against interrupt when we're going down */
6453 if (!test_bit(__IGB_DOWN, &adapter->state))
6454 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6455 }
6456
61d7f75f
RC		 6457 if (icr & E1000_ICR_TS)
6458 igb_tsync_interrupt(adapter);
1f6e8178 6459
047e0030 6460 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6461
6462 return IRQ_HANDLED;
6463}
6464
c50b52a0 6465static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6466{
047e0030 6467 struct igb_adapter *adapter = q_vector->adapter;
46544258 6468 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6469
0ba82994
AD		 6470 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6471 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6472 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6473 igb_set_itr(q_vector);
46544258 6474 else
047e0030 6475 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6476 }
6477
46544258 6478 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6479 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6480 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6481 else
6482 igb_irq_enable(adapter);
6483 }
9d5c8243
AK		 6484}
6485
46544258 6486/**
b980ac18
JK		 6487 * igb_poll - NAPI Rx polling callback
6488 * @napi: napi polling structure
6489 * @budget: count of how many packets we should handle
46544258
AD		 6490 **/
6491static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6492{
047e0030 6493 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6494 struct igb_q_vector,
6495 napi);
16eb8815 6496 bool clean_complete = true;
32b3e08f 6497 int work_done = 0;
9d5c8243 6498
421e02f0 6499#ifdef CONFIG_IGB_DCA
047e0030
AD		 6500 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6501 igb_update_dca(q_vector);
fe4506b6 6502#endif
0ba82994 6503 if (q_vector->tx.ring)
13fde97a 6504 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6505
32b3e08f
JB		 6506 if (q_vector->rx.ring) {
6507 int cleaned = igb_clean_rx_irq(q_vector, budget);
6508
6509 work_done += cleaned;
6510 clean_complete &= (cleaned < budget);
6511 }
047e0030 6512
16eb8815
AD		 6513 /* If all work not completed, return budget and keep polling */
6514 if (!clean_complete)
6515 return budget;
46544258 6516
9d5c8243 6517 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6518 napi_complete_done(napi, work_done);
16eb8815 6519 igb_ring_irq_enable(q_vector);
9d5c8243 6520
16eb8815 6521 return 0;
9d5c8243 6522}
6d8126f9 6523
9d5c8243 6524/**
b980ac18
JK		 6525 * igb_clean_tx_irq - Reclaim resources after transmit completes
6526 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6527 *
b980ac18 6528 * returns true if ring is completely cleaned
9d5c8243 6529 **/
047e0030 6530static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6531{
047e0030 6532 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6533 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6534 struct igb_tx_buffer *tx_buffer;
f4128785 6535 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6536 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6537 unsigned int budget = q_vector->tx.work_limit;
8542db05 6538 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6539
13fde97a
AD		 6540 if (test_bit(__IGB_DOWN, &adapter->state))
6541 return true;
0e014cb1 6542
06034649 6543 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6544 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6545 i -= tx_ring->count;
9d5c8243 6546
f4128785
AD		 6547 do {
6548 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6549
6550 /* if next_to_watch is not set then there is no work pending */
6551 if (!eop_desc)
6552 break;
13fde97a 6553
f4128785 6554 /* prevent any other reads prior to eop_desc */
70d289bc 6555 read_barrier_depends();
f4128785 6556
13fde97a
AD		 6557 /* if DD is not set pending work has not been completed */
6558 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6559 break;
6560
8542db05
AD		 6561 /* clear next_to_watch to prevent false hangs */
6562 tx_buffer->next_to_watch = NULL;
9d5c8243 6563
ebe42d16
AD		 6564 /* update the statistics for this packet */
6565 total_bytes += tx_buffer->bytecount;
6566 total_packets += tx_buffer->gso_segs;
13fde97a 6567
ebe42d16 6568 /* free the skb */
a81fb049 6569 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6570
ebe42d16
AD		 6571 /* unmap skb header data */
6572 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6573 dma_unmap_addr(tx_buffer, dma),
6574 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6575 DMA_TO_DEVICE);
6576
c9f14bf3
AD		 6577 /* clear tx_buffer data */
6578 tx_buffer->skb = NULL;
6579 dma_unmap_len_set(tx_buffer, len, 0);
6580
ebe42d16
AD		 6581 /* clear last DMA location and unmap remaining buffers */
6582 while (tx_desc != eop_desc) {
13fde97a
AD		 6583 tx_buffer++;
6584 tx_desc++;
9d5c8243 6585 i++;
8542db05
AD		 6586 if (unlikely(!i)) {
6587 i -= tx_ring->count;
06034649 6588 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6589 tx_desc = IGB_TX_DESC(tx_ring, 0);
6590 }
ebe42d16
AD		 6591
6592 /* unmap any remaining paged data */
c9f14bf3 6593 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6594 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6595 dma_unmap_addr(tx_buffer, dma),
6596 dma_unmap_len(tx_buffer, len),
ebe42d16 6597 DMA_TO_DEVICE);
c9f14bf3 6598 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6599 }
6600 }
6601
ebe42d16
AD		 6602 /* move us one more past the eop_desc for start of next pkt */
6603 tx_buffer++;
6604 tx_desc++;
6605 i++;
6606 if (unlikely(!i)) {
6607 i -= tx_ring->count;
6608 tx_buffer = tx_ring->tx_buffer_info;
6609 tx_desc = IGB_TX_DESC(tx_ring, 0);
6610 }
f4128785
AD		 6611
6612 /* issue prefetch for next Tx descriptor */
6613 prefetch(tx_desc);
6614
6615 /* update budget accounting */
6616 budget--;
6617 } while (likely(budget));
0e014cb1 6618
bdbc0631
ED		 6619 netdev_tx_completed_queue(txring_txq(tx_ring),
6620 total_packets, total_bytes);
8542db05 6621 i += tx_ring->count;
9d5c8243 6622 tx_ring->next_to_clean = i;
13fde97a
AD		 6623 u64_stats_update_begin(&tx_ring->tx_syncp);
6624 tx_ring->tx_stats.bytes += total_bytes;
6625 tx_ring->tx_stats.packets += total_packets;
6626 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6627 q_vector->tx.total_bytes += total_bytes;
6628 q_vector->tx.total_packets += total_packets;
9d5c8243 6629
6d095fa8 6630 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6631 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6632
9d5c8243 6633 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6634 * check with the clearing of time_stamp and movement of i
6635 */
6d095fa8 6636 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6637 if (tx_buffer->next_to_watch &&
8542db05 6638 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6639 (adapter->tx_timeout_factor * HZ)) &&
6640 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6641
9d5c8243 6642 /* detected Tx unit hang */
59d71989 6643 dev_err(tx_ring->dev,
9d5c8243 6644 "Detected Tx Unit Hang\n"
2d064c06 6645 " Tx Queue <%d>\n"
9d5c8243
AK		 6646 " TDH <%x>\n"
6647 " TDT <%x>\n"
6648 " next_to_use <%x>\n"
6649 " next_to_clean <%x>\n"
9d5c8243
AK		 6650 "buffer_info[next_to_clean]\n"
6651 " time_stamp <%lx>\n"
8542db05 6652 " next_to_watch <%p>\n"
9d5c8243
AK		 6653 " jiffies <%lx>\n"
6654 " desc.status <%x>\n",
2d064c06 6655 tx_ring->queue_index,
238ac817 6656 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6657 readl(tx_ring->tail),
9d5c8243
AK		 6658 tx_ring->next_to_use,
6659 tx_ring->next_to_clean,
8542db05 6660 tx_buffer->time_stamp,
f4128785 6661 tx_buffer->next_to_watch,
9d5c8243 6662 jiffies,
f4128785 6663 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6664 netif_stop_subqueue(tx_ring->netdev,
6665 tx_ring->queue_index);
6666
6667 /* we are about to reset, no point in enabling stuff */
6668 return true;
9d5c8243
AK		 6669 }
6670 }
13fde97a 6671
21ba6fe1 6672#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6673 if (unlikely(total_packets &&
b980ac18
JK		 6674 netif_carrier_ok(tx_ring->netdev) &&
6675 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6676 /* Make sure that anybody stopping the queue after this
6677 * sees the new next_to_clean.
6678 */
6679 smp_mb();
6680 if (__netif_subqueue_stopped(tx_ring->netdev,
6681 tx_ring->queue_index) &&
6682 !(test_bit(__IGB_DOWN, &adapter->state))) {
6683 netif_wake_subqueue(tx_ring->netdev,
6684 tx_ring->queue_index);
6685
6686 u64_stats_update_begin(&tx_ring->tx_syncp);
6687 tx_ring->tx_stats.restart_queue++;
6688 u64_stats_update_end(&tx_ring->tx_syncp);
6689 }
6690 }
6691
6692 return !!budget;
9d5c8243
AK		 6693}
6694
cbc8e55f 6695/**
b980ac18
JK		 6696 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6697 * @rx_ring: rx descriptor ring to store buffers on
6698 * @old_buff: donor buffer to have page reused
cbc8e55f 6699 *
b980ac18 6700 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6701 **/
6702static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6703 struct igb_rx_buffer *old_buff)
6704{
6705 struct igb_rx_buffer *new_buff;
6706 u16 nta = rx_ring->next_to_alloc;
6707
6708 new_buff = &rx_ring->rx_buffer_info[nta];
6709
6710 /* update, and store next to alloc */
6711 nta++;
6712 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6713
6714 /* transfer page from old buffer to new buffer */
a1f63473 6715 *new_buff = *old_buff;
cbc8e55f
AD		 6716
6717 /* sync the buffer for use by the device */
6718 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6719 old_buff->page_offset,
de78d1f9 6720 IGB_RX_BUFSZ,
cbc8e55f
AD		 6721 DMA_FROM_DEVICE);
6722}
6723
95dd44b4
AD		 6724static inline bool igb_page_is_reserved(struct page *page)
6725{
2f064f34 6726 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6727}
6728
74e238ea
AD		 6729static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6730 struct page *page,
6731 unsigned int truesize)
6732{
6733 /* avoid re-using remote pages */
95dd44b4 6734 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6735 return false;
6736
74e238ea
AD		 6737#if (PAGE_SIZE < 8192)
6738 /* if we are only owner of page we can reuse it */
6739 if (unlikely(page_count(page) != 1))
6740 return false;
6741
6742 /* flip page offset to other buffer */
6743 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6744#else
6745 /* move offset up to the next cache line */
6746 rx_buffer->page_offset += truesize;
6747
6748 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6749 return false;
74e238ea
AD		 6750#endif
6751
95dd44b4
AD		 6752 /* Even if we own the page, we are not allowed to use atomic_set()
6753 * This would break get_page_unless_zero() users.
6754 */
6755 atomic_inc(&page->_count);
6756
74e238ea
AD		 6757 return true;
6758}
6759
cbc8e55f 6760/**
b980ac18
JK		 6761 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6762 * @rx_ring: rx descriptor ring to transact packets on
6763 * @rx_buffer: buffer containing page to add
6764 * @rx_desc: descriptor containing length of buffer written by hardware
6765 * @skb: sk_buff to place the data into
cbc8e55f 6766 *
b980ac18
JK		 6767 * This function will add the data contained in rx_buffer->page to the skb.
6768 * This is done either through a direct copy if the data in the buffer is
6769 * less than the skb header size, otherwise it will just attach the page as
6770 * a frag to the skb.
cbc8e55f 6771 *
b980ac18
JK		 6772 * The function will then update the page offset if necessary and return
6773 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6774 **/
6775static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6776 struct igb_rx_buffer *rx_buffer,
6777 union e1000_adv_rx_desc *rx_desc,
6778 struct sk_buff *skb)
6779{
6780 struct page *page = rx_buffer->page;
f56e7bba 6781 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6782 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6783#if (PAGE_SIZE < 8192)
6784 unsigned int truesize = IGB_RX_BUFSZ;
6785#else
f56e7bba 6786 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6787#endif
f56e7bba 6788 unsigned int pull_len;
cbc8e55f 6789
f56e7bba
AD		 6790 if (unlikely(skb_is_nonlinear(skb)))
6791 goto add_tail_frag;
cbc8e55f 6792
f56e7bba
AD		 6793 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6794 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6795 va += IGB_TS_HDR_LEN;
6796 size -= IGB_TS_HDR_LEN;
6797 }
cbc8e55f 6798
f56e7bba 6799 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6800 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6801
95dd44b4
AD		 6802 /* page is not reserved, we can reuse buffer as-is */
6803 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6804 return true;
6805
6806 /* this page cannot be reused so discard it */
95dd44b4 6807 __free_page(page);
cbc8e55f
AD		 6808 return false;
6809 }
6810
f56e7bba
AD		 6811 /* we need the header to contain the greater of either ETH_HLEN or
6812 * 60 bytes if the skb->len is less than 60 for skb_pad.
6813 */
6814 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6815
6816 /* align pull length to size of long to optimize memcpy performance */
6817 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6818
6819 /* update all of the pointers */
6820 va += pull_len;
6821 size -= pull_len;
6822
6823add_tail_frag:
cbc8e55f 6824 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6825 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6826
74e238ea
AD		 6827 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6828}
cbc8e55f 6829
2e334eee
AD		 6830static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6831 union e1000_adv_rx_desc *rx_desc,
6832 struct sk_buff *skb)
6833{
6834 struct igb_rx_buffer *rx_buffer;
6835 struct page *page;
6836
6837 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6838 page = rx_buffer->page;
6839 prefetchw(page);
6840
6841 if (likely(!skb)) {
6842 void *page_addr = page_address(page) +
6843 rx_buffer->page_offset;
6844
6845 /* prefetch first cache line of first page */
6846 prefetch(page_addr);
6847#if L1_CACHE_BYTES < 128
6848 prefetch(page_addr + L1_CACHE_BYTES);
6849#endif
6850
6851 /* allocate a skb to store the frags */
67fd893e 6852 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6853 if (unlikely(!skb)) {
6854 rx_ring->rx_stats.alloc_failed++;
6855 return NULL;
6856 }
6857
b980ac18 6858 /* we will be copying header into skb->data in
2e334eee
AD		 6859 * pskb_may_pull so it is in our interest to prefetch
6860 * it now to avoid a possible cache miss
6861 */
6862 prefetchw(skb->data);
6863 }
6864
6865 /* we are reusing so sync this buffer for CPU use */
6866 dma_sync_single_range_for_cpu(rx_ring->dev,
6867 rx_buffer->dma,
6868 rx_buffer->page_offset,
de78d1f9 6869 IGB_RX_BUFSZ,
2e334eee
AD		 6870 DMA_FROM_DEVICE);
6871
6872 /* pull page into skb */
6873 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6874 /* hand second half of page back to the ring */
6875 igb_reuse_rx_page(rx_ring, rx_buffer);
6876 } else {
6877 /* we are not reusing the buffer so unmap it */
6878 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6879 PAGE_SIZE, DMA_FROM_DEVICE);
6880 }
6881
6882 /* clear contents of rx_buffer */
6883 rx_buffer->page = NULL;
6884
6885 return skb;
6886}
6887
cd392f5c 6888static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6889 union e1000_adv_rx_desc *rx_desc,
6890 struct sk_buff *skb)
9d5c8243 6891{
bc8acf2c 6892 skb_checksum_none_assert(skb);
9d5c8243 6893
294e7d78 6894 /* Ignore Checksum bit is set */
3ceb90fd 6895 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6896 return;
6897
6898 /* Rx checksum disabled via ethtool */
6899 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6900 return;
85ad76b2 6901
9d5c8243 6902 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6903 if (igb_test_staterr(rx_desc,
6904 E1000_RXDEXT_STATERR_TCPE |
6905 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6906 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6907 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6908 * packets, (aka let the stack check the crc32c)
6909 */
866cff06
AD		 6910 if (!((skb->len == 60) &&
6911 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6912 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6913 ring->rx_stats.csum_err++;
12dcd86b
ED		 6914 u64_stats_update_end(&ring->rx_syncp);
6915 }
9d5c8243 6916 /* let the stack verify checksum errors */
9d5c8243
AK		 6917 return;
6918 }
6919 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6920 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6921 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6922 skb->ip_summed = CHECKSUM_UNNECESSARY;
6923
3ceb90fd
AD		 6924 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6925 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6926}
6927
077887c3
AD		 6928static inline void igb_rx_hash(struct igb_ring *ring,
6929 union e1000_adv_rx_desc *rx_desc,
6930 struct sk_buff *skb)
6931{
6932 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6933 skb_set_hash(skb,
6934 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6935 PKT_HASH_TYPE_L3);
077887c3
AD		 6936}
6937
2e334eee 6938/**
b980ac18
JK		 6939 * igb_is_non_eop - process handling of non-EOP buffers
6940 * @rx_ring: Rx ring being processed
6941 * @rx_desc: Rx descriptor for current buffer
6942 * @skb: current socket buffer containing buffer in progress
2e334eee 6943 *
b980ac18
JK		 6944 * This function updates next to clean. If the buffer is an EOP buffer
6945 * this function exits returning false, otherwise it will place the
6946 * sk_buff in the next buffer to be chained and return true indicating
6947 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6948 **/
6949static bool igb_is_non_eop(struct igb_ring *rx_ring,
6950 union e1000_adv_rx_desc *rx_desc)
6951{
6952 u32 ntc = rx_ring->next_to_clean + 1;
6953
6954 /* fetch, update, and store next to clean */
6955 ntc = (ntc < rx_ring->count) ? ntc : 0;
6956 rx_ring->next_to_clean = ntc;
6957
6958 prefetch(IGB_RX_DESC(rx_ring, ntc));
6959
6960 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6961 return false;
6962
6963 return true;
6964}
6965
1a1c225b 6966/**
b980ac18
JK		 6967 * igb_cleanup_headers - Correct corrupted or empty headers
6968 * @rx_ring: rx descriptor ring packet is being transacted on
6969 * @rx_desc: pointer to the EOP Rx descriptor
6970 * @skb: pointer to current skb being fixed
1a1c225b 6971 *
b980ac18
JK		 6972 * Address the case where we are pulling data in on pages only
6973 * and as such no data is present in the skb header.
1a1c225b 6974 *
b980ac18
JK		 6975 * In addition if skb is not at least 60 bytes we need to pad it so that
6976 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6977 *
b980ac18 6978 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6979 **/
6980static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6981 union e1000_adv_rx_desc *rx_desc,
6982 struct sk_buff *skb)
6983{
1a1c225b
AD		 6984 if (unlikely((igb_test_staterr(rx_desc,
6985 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6986 struct net_device *netdev = rx_ring->netdev;
6987 if (!(netdev->features & NETIF_F_RXALL)) {
6988 dev_kfree_skb_any(skb);
6989 return true;
6990 }
6991 }
6992
a94d9e22
AD		 6993 /* if eth_skb_pad returns an error the skb was freed */
6994 if (eth_skb_pad(skb))
6995 return true;
1a1c225b
AD		 6996
6997 return false;
2d94d8ab
AD		 6998}
6999
db2ee5bd 7000/**
b980ac18
JK		 7001 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
7002 * @rx_ring: rx descriptor ring packet is being transacted on
7003 * @rx_desc: pointer to the EOP Rx descriptor
7004 * @skb: pointer to current skb being populated
db2ee5bd 7005 *
b980ac18
JK		 7006 * This function checks the ring, descriptor, and packet information in
7007 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
7008 * other fields within the skb.
db2ee5bd
AD		 7009 **/
7010static void igb_process_skb_fields(struct igb_ring *rx_ring,
7011 union e1000_adv_rx_desc *rx_desc,
7012 struct sk_buff *skb)
7013{
7014 struct net_device *dev = rx_ring->netdev;
7015
7016 igb_rx_hash(rx_ring, rx_desc, skb);
7017
7018 igb_rx_checksum(rx_ring, rx_desc, skb);
7019
5499a968
JK		 7020 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
7021 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
7022 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 7023
f646968f 7024 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 7025 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
7026 u16 vid;
9005df38 7027
db2ee5bd
AD		 7028 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
7029 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
7030 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
7031 else
7032 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
7033
86a9bad3 7034 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 7035 }
7036
7037 skb_record_rx_queue(skb, rx_ring->queue_index);
7038
7039 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
7040}
7041
32b3e08f 7042static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 7043{
0ba82994 7044 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 7045 struct sk_buff *skb = rx_ring->skb;
9d5c8243 7046 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 7047 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 7048
57ba34c9 7049 while (likely(total_packets < budget)) {
2e334eee 7050 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 7051
2e334eee
AD		 7052 /* return some buffers to hardware, one at a time is too slow */
7053 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
7054 igb_alloc_rx_buffers(rx_ring, cleaned_count);
7055 cleaned_count = 0;
7056 }
bf36c1a0 7057
2e334eee 7058 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7059
124b74c1 7060 if (!rx_desc->wb.upper.status_error)
2e334eee 7061 break;
9d5c8243 7062
74e238ea
AD		 7063 /* This memory barrier is needed to keep us from reading
7064 * any other fields out of the rx_desc until we know the
124b74c1 7065 * descriptor has been written back
74e238ea 7066 */
124b74c1 7067 dma_rmb();
74e238ea 7068
2e334eee 7069 /* retrieve a buffer from the ring */
f9d40f6a 7070 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7071
2e334eee
AD		 7072 /* exit if we failed to retrieve a buffer */
7073 if (!skb)
7074 break;
1a1c225b 7075
2e334eee 7076 cleaned_count++;
1a1c225b 7077
2e334eee
AD		 7078 /* fetch next buffer in frame if non-eop */
7079 if (igb_is_non_eop(rx_ring, rx_desc))
7080 continue;
1a1c225b
AD		 7081
7082 /* verify the packet layout is correct */
7083 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7084 skb = NULL;
7085 continue;
9d5c8243 7086 }
9d5c8243 7087
db2ee5bd 7088 /* probably a little skewed due to removing CRC */
3ceb90fd 7089 total_bytes += skb->len;
3ceb90fd 7090
db2ee5bd
AD		 7091 /* populate checksum, timestamp, VLAN, and protocol */
7092 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7093
b2cb09b1 7094 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7095
1a1c225b
AD		 7096 /* reset skb pointer */
7097 skb = NULL;
7098
2e334eee
AD		 7099 /* update budget accounting */
7100 total_packets++;
57ba34c9 7101 }
bf36c1a0 7102
1a1c225b
AD		 7103 /* place incomplete frames back on ring for completion */
7104 rx_ring->skb = skb;
7105
12dcd86b 7106 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7107 rx_ring->rx_stats.packets += total_packets;
7108 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7109 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7110 q_vector->rx.total_packets += total_packets;
7111 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7112
7113 if (cleaned_count)
cd392f5c 7114 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7115
32b3e08f 7116 return total_packets;
9d5c8243
AK		 7117}
7118
c023cd88 7119static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7120 struct igb_rx_buffer *bi)
c023cd88
AD		 7121{
7122 struct page *page = bi->page;
cbc8e55f 7123 dma_addr_t dma;
c023cd88 7124
cbc8e55f
AD		 7125 /* since we are recycling buffers we should seldom need to alloc */
7126 if (likely(page))
c023cd88
AD		 7127 return true;
7128
cbc8e55f 7129 /* alloc new page for storage */
42b17f09 7130 page = dev_alloc_page();
cbc8e55f
AD		 7131 if (unlikely(!page)) {
7132 rx_ring->rx_stats.alloc_failed++;
7133 return false;
c023cd88
AD		 7134 }
7135
cbc8e55f
AD		 7136 /* map page for use */
7137 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7138
b980ac18 7139 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7140 * there isn't much point in holding memory we can't use
7141 */
1a1c225b 7142 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7143 __free_page(page);
7144
c023cd88
AD		 7145 rx_ring->rx_stats.alloc_failed++;
7146 return false;
7147 }
7148
1a1c225b 7149 bi->dma = dma;
cbc8e55f
AD		 7150 bi->page = page;
7151 bi->page_offset = 0;
1a1c225b 7152
c023cd88
AD		 7153 return true;
7154}
7155
9d5c8243 7156/**
b980ac18
JK		 7157 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7158 * @adapter: address of board private structure
9d5c8243 7159 **/
cd392f5c 7160void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7161{
9d5c8243 7162 union e1000_adv_rx_desc *rx_desc;
06034649 7163 struct igb_rx_buffer *bi;
c023cd88 7164 u16 i = rx_ring->next_to_use;
9d5c8243 7165
cbc8e55f
AD		 7166 /* nothing to do */
7167 if (!cleaned_count)
7168 return;
7169
60136906 7170 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7171 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7172 i -= rx_ring->count;
9d5c8243 7173
cbc8e55f 7174 do {
1a1c225b 7175 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7176 break;
9d5c8243 7177
b980ac18 7178 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7179 * because each write-back erases this info.
7180 */
f9d40f6a 7181 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7182
c023cd88
AD		 7183 rx_desc++;
7184 bi++;
9d5c8243 7185 i++;
c023cd88 7186 if (unlikely(!i)) {
60136906 7187 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7188 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7189 i -= rx_ring->count;
7190 }
7191
95dd44b4
AD		 7192 /* clear the status bits for the next_to_use descriptor */
7193 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7194
7195 cleaned_count--;
7196 } while (cleaned_count);
9d5c8243 7197
c023cd88
AD		 7198 i += rx_ring->count;
7199
9d5c8243 7200 if (rx_ring->next_to_use != i) {
cbc8e55f 7201 /* record the next descriptor to use */
9d5c8243 7202 rx_ring->next_to_use = i;
9d5c8243 7203
cbc8e55f
AD		 7204 /* update next to alloc since we have filled the ring */
7205 rx_ring->next_to_alloc = i;
7206
b980ac18 7207 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7208 * know there are new descriptors to fetch. (Only
7209 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7210 * such as IA-64).
7211 */
9d5c8243 7212 wmb();
fce99e34 7213 writel(i, rx_ring->tail);
9d5c8243
AK		 7214 }
7215}
7216
7217/**
7218 * igb_mii_ioctl -
7219 * @netdev:
7220 * @ifreq:
7221 * @cmd:
7222 **/
7223static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7224{
7225 struct igb_adapter *adapter = netdev_priv(netdev);
7226 struct mii_ioctl_data *data = if_mii(ifr);
7227
7228 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7229 return -EOPNOTSUPP;
7230
7231 switch (cmd) {
7232 case SIOCGMIIPHY:
7233 data->phy_id = adapter->hw.phy.addr;
7234 break;
7235 case SIOCGMIIREG:
f5f4cf08 7236 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7237 &data->val_out))
9d5c8243
AK		 7238 return -EIO;
7239 break;
7240 case SIOCSMIIREG:
7241 default:
7242 return -EOPNOTSUPP;
7243 }
7244 return 0;
7245}
7246
7247/**
7248 * igb_ioctl -
7249 * @netdev:
7250 * @ifreq:
7251 * @cmd:
7252 **/
7253static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7254{
7255 switch (cmd) {
7256 case SIOCGMIIPHY:
7257 case SIOCGMIIREG:
7258 case SIOCSMIIREG:
7259 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7260 case SIOCGHWTSTAMP:
7261 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7262 case SIOCSHWTSTAMP:
6ab5f7b2 7263 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7264 default:
7265 return -EOPNOTSUPP;
7266 }
7267}
7268
94826487
TF		 7269void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7270{
7271 struct igb_adapter *adapter = hw->back;
7272
7273 pci_read_config_word(adapter->pdev, reg, value);
7274}
7275
7276void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7277{
7278 struct igb_adapter *adapter = hw->back;
7279
7280 pci_write_config_word(adapter->pdev, reg, *value);
7281}
7282
009bc06e
AD		 7283s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7284{
7285 struct igb_adapter *adapter = hw->back;
009bc06e 7286
23d028cc 7287 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7288 return -E1000_ERR_CONFIG;
7289
009bc06e
AD		 7290 return 0;
7291}
7292
7293s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7294{
7295 struct igb_adapter *adapter = hw->back;
009bc06e 7296
23d028cc 7297 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7298 return -E1000_ERR_CONFIG;
7299
009bc06e
AD		 7300 return 0;
7301}
7302
c8f44aff 7303static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7304{
7305 struct igb_adapter *adapter = netdev_priv(netdev);
7306 struct e1000_hw *hw = &adapter->hw;
7307 u32 ctrl, rctl;
f646968f 7308 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7309
5faf030c 7310 if (enable) {
9d5c8243
AK		 7311 /* enable VLAN tag insert/strip */
7312 ctrl = rd32(E1000_CTRL);
7313 ctrl |= E1000_CTRL_VME;
7314 wr32(E1000_CTRL, ctrl);
7315
51466239 7316 /* Disable CFI check */
9d5c8243 7317 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7318 rctl &= ~E1000_RCTL_CFIEN;
7319 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7320 } else {
7321 /* disable VLAN tag insert/strip */
7322 ctrl = rd32(E1000_CTRL);
7323 ctrl &= ~E1000_CTRL_VME;
7324 wr32(E1000_CTRL, ctrl);
9d5c8243 7325 }
9d5c8243
AK		 7326}
7327
80d5c368
PM		 7328static int igb_vlan_rx_add_vid(struct net_device *netdev,
7329 __be16 proto, u16 vid)
9d5c8243
AK		 7330{
7331 struct igb_adapter *adapter = netdev_priv(netdev);
7332 struct e1000_hw *hw = &adapter->hw;
4ae196df 7333 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7334
51466239 7335 /* add the filter since PF can receive vlans w/o entry in vlvf */
16903caa
AD		 7336 if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7337 igb_vfta_set(hw, vid, pf_id, true, !!vid);
7338
b2cb09b1 7339 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7340
7341 return 0;
9d5c8243
AK		 7342}
7343
80d5c368
PM		 7344static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7345 __be16 proto, u16 vid)
9d5c8243
AK		 7346{
7347 struct igb_adapter *adapter = netdev_priv(netdev);
4ae196df 7348 int pf_id = adapter->vfs_allocated_count;
8b77c6b2 7349 struct e1000_hw *hw = &adapter->hw;
9d5c8243 7350
8b77c6b2 7351 /* remove VID from filter table */
16903caa
AD		 7352 if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
7353 igb_vfta_set(hw, vid, pf_id, false, true);
b2cb09b1
JP		 7354
7355 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7356
7357 return 0;
9d5c8243
AK		 7358}
7359
7360static void igb_restore_vlan(struct igb_adapter *adapter)
7361{
5982a556 7362 u16 vid = 1;
9d5c8243 7363
5faf030c 7364 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
5982a556 7365 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
5faf030c 7366
5982a556 7367 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7368 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7369}
7370
14ad2513 7371int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7372{
090b1795 7373 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7374 struct e1000_mac_info *mac = &adapter->hw.mac;
7375
7376 mac->autoneg = 0;
7377
14ad2513 7378 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7379 * for the switch() below to work
7380 */
14ad2513
DD		 7381 if ((spd & 1) || (dplx & ~1))
7382 goto err_inval;
7383
f502ef7d
AA		 7384 /* Fiber NIC's only allow 1000 gbps Full duplex
7385 * and 100Mbps Full duplex for 100baseFx sfp
7386 */
7387 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7388 switch (spd + dplx) {
7389 case SPEED_10 + DUPLEX_HALF:
7390 case SPEED_10 + DUPLEX_FULL:
7391 case SPEED_100 + DUPLEX_HALF:
7392 goto err_inval;
7393 default:
7394 break;
7395 }
7396 }
cd2638a8 7397
14ad2513 7398 switch (spd + dplx) {
9d5c8243
AK		 7399 case SPEED_10 + DUPLEX_HALF:
7400 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7401 break;
7402 case SPEED_10 + DUPLEX_FULL:
7403 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7404 break;
7405 case SPEED_100 + DUPLEX_HALF:
7406 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7407 break;
7408 case SPEED_100 + DUPLEX_FULL:
7409 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7410 break;
7411 case SPEED_1000 + DUPLEX_FULL:
7412 mac->autoneg = 1;
7413 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7414 break;
7415 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7416 default:
14ad2513 7417 goto err_inval;
9d5c8243 7418 }
8376dad0
JB		 7419
7420 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7421 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7422
9d5c8243 7423 return 0;
14ad2513
DD		 7424
7425err_inval:
7426 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7427 return -EINVAL;
9d5c8243
AK		 7428}
7429
749ab2cd
YZ		 7430static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7431 bool runtime)
9d5c8243
AK		 7432{
7433 struct net_device *netdev = pci_get_drvdata(pdev);
7434 struct igb_adapter *adapter = netdev_priv(netdev);
7435 struct e1000_hw *hw = &adapter->hw;
2d064c06 7436 u32 ctrl, rctl, status;
749ab2cd 7437 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7438#ifdef CONFIG_PM
7439 int retval = 0;
7440#endif
7441
7442 netif_device_detach(netdev);
7443
a88f10ec 7444 if (netif_running(netdev))
749ab2cd 7445 __igb_close(netdev, true);
a88f10ec 7446
047e0030 7447 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7448
7449#ifdef CONFIG_PM
7450 retval = pci_save_state(pdev);
7451 if (retval)
7452 return retval;
7453#endif
7454
7455 status = rd32(E1000_STATUS);
7456 if (status & E1000_STATUS_LU)
7457 wufc &= ~E1000_WUFC_LNKC;
7458
7459 if (wufc) {
7460 igb_setup_rctl(adapter);
ff41f8dc 7461 igb_set_rx_mode(netdev);
9d5c8243
AK		 7462
7463 /* turn on all-multi mode if wake on multicast is enabled */
7464 if (wufc & E1000_WUFC_MC) {
7465 rctl = rd32(E1000_RCTL);
7466 rctl |= E1000_RCTL_MPE;
7467 wr32(E1000_RCTL, rctl);
7468 }
7469
7470 ctrl = rd32(E1000_CTRL);
7471 /* advertise wake from D3Cold */
7472 #define E1000_CTRL_ADVD3WUC 0x00100000
7473 /* phy power management enable */
7474 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7475 ctrl |= E1000_CTRL_ADVD3WUC;
7476 wr32(E1000_CTRL, ctrl);
7477
9d5c8243 7478 /* Allow time for pending master requests to run */
330a6d6a 7479 igb_disable_pcie_master(hw);
9d5c8243
AK		 7480
7481 wr32(E1000_WUC, E1000_WUC_PME_EN);
7482 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7483 } else {
7484 wr32(E1000_WUC, 0);
7485 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7486 }
7487
3fe7c4c9
RW		 7488 *enable_wake = wufc || adapter->en_mng_pt;
7489 if (!*enable_wake)
88a268c1
NN		 7490 igb_power_down_link(adapter);
7491 else
7492 igb_power_up_link(adapter);
9d5c8243
AK		 7493
7494 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7495 * would have already happened in close and is redundant.
7496 */
9d5c8243
AK		 7497 igb_release_hw_control(adapter);
7498
7499 pci_disable_device(pdev);
7500
9d5c8243
AK		 7501 return 0;
7502}
7503
7504#ifdef CONFIG_PM
d9dd966d 7505#ifdef CONFIG_PM_SLEEP
749ab2cd 7506static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7507{
7508 int retval;
7509 bool wake;
749ab2cd 7510 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7511
749ab2cd 7512 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7513 if (retval)
7514 return retval;
7515
7516 if (wake) {
7517 pci_prepare_to_sleep(pdev);
7518 } else {
7519 pci_wake_from_d3(pdev, false);
7520 pci_set_power_state(pdev, PCI_D3hot);
7521 }
7522
7523 return 0;
7524}
d9dd966d 7525#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7526
749ab2cd 7527static int igb_resume(struct device *dev)
9d5c8243 7528{
749ab2cd 7529 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7530 struct net_device *netdev = pci_get_drvdata(pdev);
7531 struct igb_adapter *adapter = netdev_priv(netdev);
7532 struct e1000_hw *hw = &adapter->hw;
7533 u32 err;
7534
7535 pci_set_power_state(pdev, PCI_D0);
7536 pci_restore_state(pdev);
b94f2d77 7537 pci_save_state(pdev);
42bfd33a 7538
17a402a0
CW		 7539 if (!pci_device_is_present(pdev))
7540 return -ENODEV;
aed5dec3 7541 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7542 if (err) {
7543 dev_err(&pdev->dev,
7544 "igb: Cannot enable PCI device from suspend\n");
7545 return err;
7546 }
7547 pci_set_master(pdev);
7548
7549 pci_enable_wake(pdev, PCI_D3hot, 0);
7550 pci_enable_wake(pdev, PCI_D3cold, 0);
7551
53c7d064 7552 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec 7553 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3eb14ea8 7554 rtnl_unlock();
a88f10ec 7555 return -ENOMEM;
9d5c8243
AK		 7556 }
7557
9d5c8243 7558 igb_reset(adapter);
a8564f03
AD		 7559
7560 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7561 * driver.
7562 */
a8564f03
AD		 7563 igb_get_hw_control(adapter);
7564
9d5c8243
AK		 7565 wr32(E1000_WUS, ~0);
7566
749ab2cd 7567 if (netdev->flags & IFF_UP) {
0c2cc02e 7568 rtnl_lock();
749ab2cd 7569 err = __igb_open(netdev, true);
0c2cc02e 7570 rtnl_unlock();
a88f10ec
AD		 7571 if (err)
7572 return err;
7573 }
9d5c8243
AK		 7574
7575 netif_device_attach(netdev);
749ab2cd
YZ		 7576 return 0;
7577}
7578
749ab2cd
YZ		 7579static int igb_runtime_idle(struct device *dev)
7580{
7581 struct pci_dev *pdev = to_pci_dev(dev);
7582 struct net_device *netdev = pci_get_drvdata(pdev);
7583 struct igb_adapter *adapter = netdev_priv(netdev);
7584
7585 if (!igb_has_link(adapter))
7586 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7587
7588 return -EBUSY;
7589}
7590
7591static int igb_runtime_suspend(struct device *dev)
7592{
7593 struct pci_dev *pdev = to_pci_dev(dev);
7594 int retval;
7595 bool wake;
7596
7597 retval = __igb_shutdown(pdev, &wake, 1);
7598 if (retval)
7599 return retval;
7600
7601 if (wake) {
7602 pci_prepare_to_sleep(pdev);
7603 } else {
7604 pci_wake_from_d3(pdev, false);
7605 pci_set_power_state(pdev, PCI_D3hot);
7606 }
9d5c8243 7607
9d5c8243
AK		 7608 return 0;
7609}
749ab2cd
YZ		 7610
7611static int igb_runtime_resume(struct device *dev)
7612{
7613 return igb_resume(dev);
7614}
d61c81cb 7615#endif /* CONFIG_PM */
9d5c8243
AK		 7616
7617static void igb_shutdown(struct pci_dev *pdev)
7618{
3fe7c4c9
RW		 7619 bool wake;
7620
749ab2cd 7621 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7622
7623 if (system_state == SYSTEM_POWER_OFF) {
7624 pci_wake_from_d3(pdev, wake);
7625 pci_set_power_state(pdev, PCI_D3hot);
7626 }
9d5c8243
AK		 7627}
7628
fa44f2f1
GR		 7629#ifdef CONFIG_PCI_IOV
7630static int igb_sriov_reinit(struct pci_dev *dev)
7631{
7632 struct net_device *netdev = pci_get_drvdata(dev);
7633 struct igb_adapter *adapter = netdev_priv(netdev);
7634 struct pci_dev *pdev = adapter->pdev;
7635
7636 rtnl_lock();
7637
7638 if (netif_running(netdev))
7639 igb_close(netdev);
76252723
SA		 7640 else
7641 igb_reset(adapter);
fa44f2f1
GR		 7642
7643 igb_clear_interrupt_scheme(adapter);
7644
7645 igb_init_queue_configuration(adapter);
7646
7647 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7648 rtnl_unlock();
fa44f2f1
GR		 7649 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7650 return -ENOMEM;
7651 }
7652
7653 if (netif_running(netdev))
7654 igb_open(netdev);
7655
7656 rtnl_unlock();
7657
7658 return 0;
7659}
7660
7661static int igb_pci_disable_sriov(struct pci_dev *dev)
7662{
7663 int err = igb_disable_sriov(dev);
7664
7665 if (!err)
7666 err = igb_sriov_reinit(dev);
7667
7668 return err;
7669}
7670
7671static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7672{
7673 int err = igb_enable_sriov(dev, num_vfs);
7674
7675 if (err)
7676 goto out;
7677
7678 err = igb_sriov_reinit(dev);
7679 if (!err)
7680 return num_vfs;
7681
7682out:
7683 return err;
7684}
7685
7686#endif
7687static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7688{
7689#ifdef CONFIG_PCI_IOV
7690 if (num_vfs == 0)
7691 return igb_pci_disable_sriov(dev);
7692 else
7693 return igb_pci_enable_sriov(dev, num_vfs);
7694#endif
7695 return 0;
7696}
7697
9d5c8243 7698#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7699/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7700 * without having to re-enable interrupts. It's not called while
7701 * the interrupt routine is executing.
7702 */
7703static void igb_netpoll(struct net_device *netdev)
7704{
7705 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7706 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7707 struct igb_q_vector *q_vector;
9d5c8243 7708 int i;
9d5c8243 7709
047e0030 7710 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7711 q_vector = adapter->q_vector[i];
cd14ef54 7712 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7713 wr32(E1000_EIMC, q_vector->eims_value);
7714 else
7715 igb_irq_disable(adapter);
047e0030 7716 napi_schedule(&q_vector->napi);
eebbbdba 7717 }
9d5c8243
AK		 7718}
7719#endif /* CONFIG_NET_POLL_CONTROLLER */
7720
7721/**
b980ac18
JK		 7722 * igb_io_error_detected - called when PCI error is detected
7723 * @pdev: Pointer to PCI device
7724 * @state: The current pci connection state
9d5c8243 7725 *
b980ac18
JK		 7726 * This function is called after a PCI bus error affecting
7727 * this device has been detected.
7728 **/
9d5c8243
AK		 7729static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7730 pci_channel_state_t state)
7731{
7732 struct net_device *netdev = pci_get_drvdata(pdev);
7733 struct igb_adapter *adapter = netdev_priv(netdev);
7734
7735 netif_device_detach(netdev);
7736
59ed6eec
AD		 7737 if (state == pci_channel_io_perm_failure)
7738 return PCI_ERS_RESULT_DISCONNECT;
7739
9d5c8243
AK		 7740 if (netif_running(netdev))
7741 igb_down(adapter);
7742 pci_disable_device(pdev);
7743
7744 /* Request a slot slot reset. */
7745 return PCI_ERS_RESULT_NEED_RESET;
7746}
7747
7748/**
b980ac18
JK		 7749 * igb_io_slot_reset - called after the pci bus has been reset.
7750 * @pdev: Pointer to PCI device
9d5c8243 7751 *
b980ac18
JK		 7752 * Restart the card from scratch, as if from a cold-boot. Implementation
7753 * resembles the first-half of the igb_resume routine.
7754 **/
9d5c8243
AK		 7755static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7756{
7757 struct net_device *netdev = pci_get_drvdata(pdev);
7758 struct igb_adapter *adapter = netdev_priv(netdev);
7759 struct e1000_hw *hw = &adapter->hw;
40a914fa 7760 pci_ers_result_t result;
42bfd33a 7761 int err;
9d5c8243 7762
aed5dec3 7763 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7764 dev_err(&pdev->dev,
7765 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7766 result = PCI_ERS_RESULT_DISCONNECT;
7767 } else {
7768 pci_set_master(pdev);
7769 pci_restore_state(pdev);
b94f2d77 7770 pci_save_state(pdev);
9d5c8243 7771
40a914fa
AD		 7772 pci_enable_wake(pdev, PCI_D3hot, 0);
7773 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7774
40a914fa
AD		 7775 igb_reset(adapter);
7776 wr32(E1000_WUS, ~0);
7777 result = PCI_ERS_RESULT_RECOVERED;
7778 }
9d5c8243 7779
ea943d41
JK		 7780 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7781 if (err) {
b980ac18
JK		 7782 dev_err(&pdev->dev,
7783 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7784 err);
ea943d41
JK		 7785 /* non-fatal, continue */
7786 }
40a914fa
AD		 7787
7788 return result;
9d5c8243
AK		 7789}
7790
7791/**
b980ac18
JK		 7792 * igb_io_resume - called when traffic can start flowing again.
7793 * @pdev: Pointer to PCI device
9d5c8243 7794 *
b980ac18
JK		 7795 * This callback is called when the error recovery driver tells us that
7796 * its OK to resume normal operation. Implementation resembles the
7797 * second-half of the igb_resume routine.
9d5c8243
AK		 7798 */
7799static void igb_io_resume(struct pci_dev *pdev)
7800{
7801 struct net_device *netdev = pci_get_drvdata(pdev);
7802 struct igb_adapter *adapter = netdev_priv(netdev);
7803
9d5c8243
AK		 7804 if (netif_running(netdev)) {
7805 if (igb_up(adapter)) {
7806 dev_err(&pdev->dev, "igb_up failed after reset\n");
7807 return;
7808 }
7809 }
7810
7811 netif_device_attach(netdev);
7812
7813 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7814 * driver.
7815 */
9d5c8243 7816 igb_get_hw_control(adapter);
9d5c8243
AK		 7817}
7818
26ad9178 7819static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7820 u8 qsel)
26ad9178 7821{
26ad9178 7822 struct e1000_hw *hw = &adapter->hw;
c3278587 7823 u32 rar_low, rar_high;
26ad9178
AD		 7824
7825 /* HW expects these in little endian so we reverse the byte order
c3278587 7826 * from network order (big endian) to CPU endian
26ad9178 7827 */
c3278587
AD		 7828 rar_low = le32_to_cpup((__be32 *)(addr));
7829 rar_high = le16_to_cpup((__be16 *)(addr + 4));
26ad9178
AD		 7830
7831 /* Indicate to hardware the Address is Valid. */
7832 rar_high |= E1000_RAH_AV;
7833
7834 if (hw->mac.type == e1000_82575)
7835 rar_high |= E1000_RAH_POOL_1 * qsel;
7836 else
7837 rar_high |= E1000_RAH_POOL_1 << qsel;
7838
7839 wr32(E1000_RAL(index), rar_low);
7840 wrfl();
7841 wr32(E1000_RAH(index), rar_high);
7842 wrfl();
7843}
7844
4ae196df 7845static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7846 int vf, unsigned char *mac_addr)
4ae196df
AD		 7847{
7848 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7849 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7850 * towards the first, as a result a collision should not be possible
7851 */
ff41f8dc 7852 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7853
37680117 7854 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7855
26ad9178 7856 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7857
7858 return 0;
7859}
7860
8151d294
WM		 7861static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7862{
7863 struct igb_adapter *adapter = netdev_priv(netdev);
7864 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7865 return -EINVAL;
7866 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7867 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7868 dev_info(&adapter->pdev->dev,
7869 "Reload the VF driver to make this change effective.");
8151d294 7870 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7871 dev_warn(&adapter->pdev->dev,
7872 "The VF MAC address has been set, but the PF device is not up.\n");
7873 dev_warn(&adapter->pdev->dev,
7874 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7875 }
7876 return igb_set_vf_mac(adapter, vf, mac);
7877}
7878
17dc566c
LL		 7879static int igb_link_mbps(int internal_link_speed)
7880{
7881 switch (internal_link_speed) {
7882 case SPEED_100:
7883 return 100;
7884 case SPEED_1000:
7885 return 1000;
7886 default:
7887 return 0;
7888 }
7889}
7890
7891static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7892 int link_speed)
7893{
7894 int rf_dec, rf_int;
7895 u32 bcnrc_val;
7896
7897 if (tx_rate != 0) {
7898 /* Calculate the rate factor values to set */
7899 rf_int = link_speed / tx_rate;
7900 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7901 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7902 tx_rate;
17dc566c
LL		 7903
7904 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7905 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7906 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7907 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7908 } else {
7909 bcnrc_val = 0;
7910 }
7911
7912 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7913 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7914 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7915 */
7916 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7917 wr32(E1000_RTTBCNRC, bcnrc_val);
7918}
7919
7920static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7921{
7922 int actual_link_speed, i;
7923 bool reset_rate = false;
7924
7925 /* VF TX rate limit was not set or not supported */
7926 if ((adapter->vf_rate_link_speed == 0) ||
7927 (adapter->hw.mac.type != e1000_82576))
7928 return;
7929
7930 actual_link_speed = igb_link_mbps(adapter->link_speed);
7931 if (actual_link_speed != adapter->vf_rate_link_speed) {
7932 reset_rate = true;
7933 adapter->vf_rate_link_speed = 0;
7934 dev_info(&adapter->pdev->dev,
b980ac18 7935 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7936 }
7937
7938 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7939 if (reset_rate)
7940 adapter->vf_data[i].tx_rate = 0;
7941
7942 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7943 adapter->vf_data[i].tx_rate,
7944 actual_link_speed);
17dc566c
LL		 7945 }
7946}
7947
ed616689
SC		 7948static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7949 int min_tx_rate, int max_tx_rate)
8151d294 7950{
17dc566c
LL		 7951 struct igb_adapter *adapter = netdev_priv(netdev);
7952 struct e1000_hw *hw = &adapter->hw;
7953 int actual_link_speed;
7954
7955 if (hw->mac.type != e1000_82576)
7956 return -EOPNOTSUPP;
7957
ed616689
SC		 7958 if (min_tx_rate)
7959 return -EINVAL;
7960
17dc566c
LL		 7961 actual_link_speed = igb_link_mbps(adapter->link_speed);
7962 if ((vf >= adapter->vfs_allocated_count) ||
7963 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7964 (max_tx_rate < 0) ||
7965 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7966 return -EINVAL;
7967
7968 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7969 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7970 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7971
7972 return 0;
8151d294
WM		 7973}
7974
70ea4783
LL		 7975static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7976 bool setting)
7977{
7978 struct igb_adapter *adapter = netdev_priv(netdev);
7979 struct e1000_hw *hw = &adapter->hw;
7980 u32 reg_val, reg_offset;
7981
7982 if (!adapter->vfs_allocated_count)
7983 return -EOPNOTSUPP;
7984
7985 if (vf >= adapter->vfs_allocated_count)
7986 return -EINVAL;
7987
7988 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7989 reg_val = rd32(reg_offset);
7990 if (setting)
7991 reg_val |= ((1 << vf) |
7992 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7993 else
7994 reg_val &= ~((1 << vf) |
7995 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7996 wr32(reg_offset, reg_val);
7997
7998 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7999 return 0;
70ea4783
LL		 8000}
8001
8151d294
WM		 8002static int igb_ndo_get_vf_config(struct net_device *netdev,
8003 int vf, struct ifla_vf_info *ivi)
8004{
8005 struct igb_adapter *adapter = netdev_priv(netdev);
8006 if (vf >= adapter->vfs_allocated_count)
8007 return -EINVAL;
8008 ivi->vf = vf;
8009 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 8010 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
8011 ivi->min_tx_rate = 0;
8151d294
WM		 8012 ivi->vlan = adapter->vf_data[vf].pf_vlan;
8013 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 8014 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 8015 return 0;
8016}
8017
4ae196df
AD		 8018static void igb_vmm_control(struct igb_adapter *adapter)
8019{
8020 struct e1000_hw *hw = &adapter->hw;
10d8e907 8021 u32 reg;
4ae196df 8022
52a1dd4d
AD		 8023 switch (hw->mac.type) {
8024 case e1000_82575:
f96a8a0b
CW		 8025 case e1000_i210:
8026 case e1000_i211:
ceb5f13b 8027 case e1000_i354:
52a1dd4d
AD		 8028 default:
8029 /* replication is not supported for 82575 */
4ae196df 8030 return;
52a1dd4d
AD		 8031 case e1000_82576:
8032 /* notify HW that the MAC is adding vlan tags */
8033 reg = rd32(E1000_DTXCTL);
8034 reg |= E1000_DTXCTL_VLAN_ADDED;
8035 wr32(E1000_DTXCTL, reg);
b26141d4 8036 /* Fall through */
52a1dd4d
AD		 8037 case e1000_82580:
8038 /* enable replication vlan tag stripping */
8039 reg = rd32(E1000_RPLOLR);
8040 reg |= E1000_RPLOLR_STRVLAN;
8041 wr32(E1000_RPLOLR, reg);
b26141d4 8042 /* Fall through */
d2ba2ed8
AD		 8043 case e1000_i350:
8044 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 8045 break;
8046 }
10d8e907 8047
d4960307
AD		 8048 if (adapter->vfs_allocated_count) {
8049 igb_vmdq_set_loopback_pf(hw, true);
8050 igb_vmdq_set_replication_pf(hw, true);
13800469 8051 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 8052 adapter->vfs_allocated_count);
d4960307
AD		 8053 } else {
8054 igb_vmdq_set_loopback_pf(hw, false);
8055 igb_vmdq_set_replication_pf(hw, false);
8056 }
4ae196df
AD		 8057}
8058
b6e0c419
CW		 8059static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
8060{
8061 struct e1000_hw *hw = &adapter->hw;
8062 u32 dmac_thr;
8063 u16 hwm;
8064
8065 if (hw->mac.type > e1000_82580) {
8066 if (adapter->flags & IGB_FLAG_DMAC) {
8067 u32 reg;
8068
8069 /* force threshold to 0. */
8070 wr32(E1000_DMCTXTH, 0);
8071
b980ac18 8072 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8073 * than the Rx threshold. Set hwm to PBA - max frame
8074 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8075 */
45693bcb 8076 hwm = 64 * (pba - 6);
e8c626e9
MV		 8077 reg = rd32(E1000_FCRTC);
8078 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8079 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8080 & E1000_FCRTC_RTH_COAL_MASK);
8081 wr32(E1000_FCRTC, reg);
8082
b980ac18 8083 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8084 * frame size, capping it at PBA - 10KB.
8085 */
45693bcb 8086 dmac_thr = pba - 10;
b6e0c419
CW		 8087 reg = rd32(E1000_DMACR);
8088 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8089 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8090 & E1000_DMACR_DMACTHR_MASK);
8091
8092 /* transition to L0x or L1 if available..*/
8093 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8094
8095 /* watchdog timer= +-1000 usec in 32usec intervals */
8096 reg |= (1000 >> 5);
0c02dd98
MV		 8097
8098 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8099 if (hw->mac.type != e1000_i354)
8100 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8101
b6e0c419
CW		 8102 wr32(E1000_DMACR, reg);
8103
b980ac18 8104 /* no lower threshold to disable
b6e0c419
CW		 8105 * coalescing(smart fifb)-UTRESH=0
8106 */
8107 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8108
8109 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8110
8111 wr32(E1000_DMCTLX, reg);
8112
b980ac18 8113 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8114 * DMA coal
8115 */
8116 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8117 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8118
b980ac18 8119 /* make low power state decision controlled
b6e0c419
CW		 8120 * by DMA coal
8121 */
8122 reg = rd32(E1000_PCIEMISC);
8123 reg &= ~E1000_PCIEMISC_LX_DECISION;
8124 wr32(E1000_PCIEMISC, reg);
8125 } /* endif adapter->dmac is not disabled */
8126 } else if (hw->mac.type == e1000_82580) {
8127 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8128
b6e0c419
CW		 8129 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8130 wr32(E1000_DMACR, 0);
8131 }
8132}
8133
b980ac18
JK		 8134/**
8135 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8136 * @hw: pointer to hardware structure
8137 * @byte_offset: byte offset to read
8138 * @dev_addr: device address
8139 * @data: value read
8140 *
8141 * Performs byte read operation over I2C interface at
8142 * a specified device address.
b980ac18 8143 **/
441fc6fd 8144s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8145 u8 dev_addr, u8 *data)
441fc6fd
CW		 8146{
8147 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8148 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8149 s32 status;
8150 u16 swfw_mask = 0;
8151
8152 if (!this_client)
8153 return E1000_ERR_I2C;
8154
8155 swfw_mask = E1000_SWFW_PHY0_SM;
8156
23d87824 8157 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8158 return E1000_ERR_SWFW_SYNC;
8159
8160 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8161 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8162
8163 if (status < 0)
8164 return E1000_ERR_I2C;
8165 else {
8166 *data = status;
23d87824 8167 return 0;
441fc6fd
CW		 8168 }
8169}
8170
b980ac18
JK		 8171/**
8172 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8173 * @hw: pointer to hardware structure
8174 * @byte_offset: byte offset to write
8175 * @dev_addr: device address
8176 * @data: value to write
8177 *
8178 * Performs byte write operation over I2C interface at
8179 * a specified device address.
b980ac18 8180 **/
441fc6fd 8181s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8182 u8 dev_addr, u8 data)
441fc6fd
CW		 8183{
8184 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8185 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8186 s32 status;
8187 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8188
8189 if (!this_client)
8190 return E1000_ERR_I2C;
8191
23d87824 8192 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8193 return E1000_ERR_SWFW_SYNC;
8194 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8195 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8196
8197 if (status)
8198 return E1000_ERR_I2C;
8199 else
23d87824 8200 return 0;
441fc6fd
CW		 8201
8202}
907b7835
LMV		 8203
8204int igb_reinit_queues(struct igb_adapter *adapter)
8205{
8206 struct net_device *netdev = adapter->netdev;
8207 struct pci_dev *pdev = adapter->pdev;
8208 int err = 0;
8209
8210 if (netif_running(netdev))
8211 igb_close(netdev);
8212
02ef6e1d 8213 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8214
8215 if (igb_init_interrupt_scheme(adapter, true)) {
8216 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8217 return -ENOMEM;
8218 }
8219
8220 if (netif_running(netdev))
8221 err = igb_open(netdev);
8222
8223 return err;
8224}
9d5c8243 8225/* igb_main.c */
Linux kernel - Deliverables
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