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igb: Remove unnecessary flag setting in igb_set_flag_queue_pairs()
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
6fb46902
TF		 60#define MIN 3
61#define BUILD 0
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
32b3e08f 154static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 184#endif
9d5c8243 185
9d5c8243 186#ifdef CONFIG_PM
d9dd966d 187#ifdef CONFIG_PM_SLEEP
749ab2cd 188static int igb_suspend(struct device *);
d9dd966d 189#endif
749ab2cd 190static int igb_resume(struct device *);
749ab2cd
YZ		 191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
52285b76 949 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 950
047e0030 951 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 952 igb_msix_other, 0, netdev->name, adapter);
047e0030 953 if (err)
52285b76 954 goto err_out;
047e0030
AD		 955
956 for (i = 0; i < adapter->num_q_vectors; i++) {
957 struct igb_q_vector *q_vector = adapter->q_vector[i];
958
52285b76
SA		 959 vector++;
960
7b06a690 961 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
047e0030 962
0ba82994 963 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 964 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 965 q_vector->rx.ring->queue_index);
966 else if (q_vector->tx.ring)
047e0030 967 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 968 q_vector->tx.ring->queue_index);
969 else if (q_vector->rx.ring)
047e0030 970 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 971 q_vector->rx.ring->queue_index);
9d5c8243 972 else
047e0030
AD		 973 sprintf(q_vector->name, "%s-unused", netdev->name);
974
9d5c8243 975 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 976 igb_msix_ring, 0, q_vector->name,
977 q_vector);
9d5c8243 978 if (err)
52285b76 979 goto err_free;
9d5c8243
AK		 980 }
981
9d5c8243
AK		 982 igb_configure_msix(adapter);
983 return 0;
52285b76
SA		 984
985err_free:
986 /* free already assigned IRQs */
987 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
988
989 vector--;
990 for (i = 0; i < vector; i++) {
991 free_irq(adapter->msix_entries[free_vector++].vector,
992 adapter->q_vector[i]);
993 }
994err_out:
9d5c8243
AK		 995 return err;
996}
997
5536d210 998/**
b980ac18
JK		 999 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1000 * @adapter: board private structure to initialize
1001 * @v_idx: Index of vector to be freed
5536d210 1002 *
02ef6e1d 1003 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1004 **/
1005static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1006{
1007 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1008
02ef6e1d
CW		 1009 adapter->q_vector[v_idx] = NULL;
1010
1011 /* igb_get_stats64() might access the rings on this vector,
1012 * we must wait a grace period before freeing it.
1013 */
17a402a0
CW		 1014 if (q_vector)
1015 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
cb06d102
CP		 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
5536d210
AD		 1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
2439fc4d 1040 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1041
5536d210
AD		 1042 netif_napi_del(&q_vector->napi);
1043
02ef6e1d
CW		 1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
cd14ef54 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1051 pci_disable_msix(adapter->pdev);
cd14ef54 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1053 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1057}
1058
047e0030 1059/**
b980ac18
JK		 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
047e0030 1062 *
b980ac18
JK		 1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
047e0030
AD		 1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
5536d210
AD		 1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
047e0030 1073 adapter->num_q_vectors = 0;
5536d210 1074
02ef6e1d
CW		 1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
5536d210 1077 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1078 }
047e0030
AD		 1079}
1080
1081/**
b980ac18
JK		 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
047e0030 1084 *
b980ac18
JK		 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
047e0030
AD		 1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
047e0030
AD		 1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
9d5c8243
AK		 1093
1094/**
b980ac18
JK		 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
9d5c8243 1098 *
b980ac18
JK		 1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
9d5c8243 1101 **/
53c7d064 1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1103{
1104 int err;
1105 int numvecs, i;
1106
53c7d064
SA		 1107 if (!msix)
1108 goto msi_only;
cd14ef54 1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1110
83b7180d 1111 /* Number of supported queues. */
a99955fc 1112 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1117
b980ac18 1118 /* start with one vector for every Rx queue */
047e0030
AD		 1119 numvecs = adapter->num_rx_queues;
1120
b980ac18 1121 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
047e0030
AD		 1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
9d5c8243
AK		 1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
479d02df
AG		 1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
0c2cc02e 1138 return;
9d5c8243
AK		 1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
b709323d 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1156 wrfl();
2a3abf6d
AD		 1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
4fc82adf 1161 adapter->vfs_allocated_count = 0;
a99955fc 1162 adapter->rss_queues = 1;
4fc82adf 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1164 adapter->num_rx_queues = 1;
661086df 1165 adapter->num_tx_queues = 1;
047e0030 1166 adapter->num_q_vectors = 1;
9d5c8243 1167 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1168 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1169}
1170
5536d210
AD		 1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
047e0030 1178/**
b980ac18
JK		 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
047e0030 1187 *
b980ac18 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1189 **/
5536d210
AD		 1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
047e0030
AD		 1194{
1195 struct igb_q_vector *q_vector;
5536d210
AD		 1196 struct igb_ring *ring;
1197 int ring_count, size;
047e0030 1198
5536d210
AD		 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
02ef6e1d 1208 q_vector = adapter->q_vector[v_idx];
72ddef05 1209 if (!q_vector) {
02ef6e1d 1210 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1211 } else if (size > ksize(q_vector)) {
1212 kfree_rcu(q_vector, rcu);
1213 q_vector = kzalloc(size, GFP_KERNEL);
1214 } else {
c0a06ee1 1215 memset(q_vector, 0, size);
72ddef05 1216 }
5536d210
AD		 1217 if (!q_vector)
1218 return -ENOMEM;
1219
1220 /* initialize NAPI */
1221 netif_napi_add(adapter->netdev, &q_vector->napi,
1222 igb_poll, 64);
1223
1224 /* tie q_vector and adapter together */
1225 adapter->q_vector[v_idx] = q_vector;
1226 q_vector->adapter = adapter;
1227
1228 /* initialize work limits */
1229 q_vector->tx.work_limit = adapter->tx_work_limit;
1230
1231 /* initialize ITR configuration */
7b06a690 1232 q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
5536d210
AD		 1233 q_vector->itr_val = IGB_START_ITR;
1234
1235 /* initialize pointer to rings */
1236 ring = q_vector->ring;
1237
4e227667
AD		 1238 /* intialize ITR */
1239 if (rxr_count) {
1240 /* rx or rx/tx vector */
1241 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1242 q_vector->itr_val = adapter->rx_itr_setting;
1243 } else {
1244 /* tx only vector */
1245 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1246 q_vector->itr_val = adapter->tx_itr_setting;
1247 }
1248
5536d210
AD		 1249 if (txr_count) {
1250 /* assign generic ring traits */
1251 ring->dev = &adapter->pdev->dev;
1252 ring->netdev = adapter->netdev;
1253
1254 /* configure backlink on ring */
1255 ring->q_vector = q_vector;
1256
1257 /* update q_vector Tx values */
1258 igb_add_ring(ring, &q_vector->tx);
1259
1260 /* For 82575, context index must be unique per ring. */
1261 if (adapter->hw.mac.type == e1000_82575)
1262 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1263
1264 /* apply Tx specific ring traits */
1265 ring->count = adapter->tx_ring_count;
1266 ring->queue_index = txr_idx;
1267
827da44c
JS		 1268 u64_stats_init(&ring->tx_syncp);
1269 u64_stats_init(&ring->tx_syncp2);
1270
5536d210
AD		 1271 /* assign ring to adapter */
1272 adapter->tx_ring[txr_idx] = ring;
1273
1274 /* push pointer to next ring */
1275 ring++;
047e0030 1276 }
81c2fc22 1277
5536d210
AD		 1278 if (rxr_count) {
1279 /* assign generic ring traits */
1280 ring->dev = &adapter->pdev->dev;
1281 ring->netdev = adapter->netdev;
047e0030 1282
5536d210
AD		 1283 /* configure backlink on ring */
1284 ring->q_vector = q_vector;
047e0030 1285
5536d210
AD		 1286 /* update q_vector Rx values */
1287 igb_add_ring(ring, &q_vector->rx);
047e0030 1288
5536d210
AD		 1289 /* set flag indicating ring supports SCTP checksum offload */
1290 if (adapter->hw.mac.type >= e1000_82576)
1291 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1292
e52c0f96 1293 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1294 * have the tag byte-swapped.
b980ac18 1295 */
5536d210
AD		 1296 if (adapter->hw.mac.type >= e1000_i350)
1297 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1298
5536d210
AD		 1299 /* apply Rx specific ring traits */
1300 ring->count = adapter->rx_ring_count;
1301 ring->queue_index = rxr_idx;
1302
827da44c
JS		 1303 u64_stats_init(&ring->rx_syncp);
1304
5536d210
AD		 1305 /* assign ring to adapter */
1306 adapter->rx_ring[rxr_idx] = ring;
1307 }
1308
1309 return 0;
047e0030
AD		 1310}
1311
5536d210 1312
047e0030 1313/**
b980ac18
JK		 1314 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1315 * @adapter: board private structure to initialize
047e0030 1316 *
b980ac18
JK		 1317 * We allocate one q_vector per queue interrupt. If allocation fails we
1318 * return -ENOMEM.
047e0030 1319 **/
5536d210 1320static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1321{
5536d210
AD		 1322 int q_vectors = adapter->num_q_vectors;
1323 int rxr_remaining = adapter->num_rx_queues;
1324 int txr_remaining = adapter->num_tx_queues;
1325 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1326 int err;
047e0030 1327
5536d210
AD		 1328 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1329 for (; rxr_remaining; v_idx++) {
1330 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1331 0, 0, 1, rxr_idx);
047e0030 1332
5536d210
AD		 1333 if (err)
1334 goto err_out;
1335
1336 /* update counts and index */
1337 rxr_remaining--;
1338 rxr_idx++;
047e0030 1339 }
047e0030 1340 }
5536d210
AD		 1341
1342 for (; v_idx < q_vectors; v_idx++) {
1343 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1344 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1345
5536d210
AD		 1346 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1347 tqpv, txr_idx, rqpv, rxr_idx);
1348
1349 if (err)
1350 goto err_out;
1351
1352 /* update counts and index */
1353 rxr_remaining -= rqpv;
1354 txr_remaining -= tqpv;
1355 rxr_idx++;
1356 txr_idx++;
1357 }
1358
047e0030 1359 return 0;
5536d210
AD		 1360
1361err_out:
1362 adapter->num_tx_queues = 0;
1363 adapter->num_rx_queues = 0;
1364 adapter->num_q_vectors = 0;
1365
1366 while (v_idx--)
1367 igb_free_q_vector(adapter, v_idx);
1368
1369 return -ENOMEM;
047e0030
AD		 1370}
1371
1372/**
b980ac18
JK		 1373 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1374 * @adapter: board private structure to initialize
1375 * @msix: boolean value of MSIX capability
047e0030 1376 *
b980ac18 1377 * This function initializes the interrupts and allocates all of the queues.
047e0030 1378 **/
53c7d064 1379static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1380{
1381 struct pci_dev *pdev = adapter->pdev;
1382 int err;
1383
53c7d064 1384 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1385
1386 err = igb_alloc_q_vectors(adapter);
1387 if (err) {
1388 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1389 goto err_alloc_q_vectors;
1390 }
1391
5536d210 1392 igb_cache_ring_register(adapter);
047e0030
AD		 1393
1394 return 0;
5536d210 1395
047e0030
AD		 1396err_alloc_q_vectors:
1397 igb_reset_interrupt_capability(adapter);
1398 return err;
1399}
1400
9d5c8243 1401/**
b980ac18
JK		 1402 * igb_request_irq - initialize interrupts
1403 * @adapter: board private structure to initialize
9d5c8243 1404 *
b980ac18
JK		 1405 * Attempts to configure interrupts using the best available
1406 * capabilities of the hardware and kernel.
9d5c8243
AK		 1407 **/
1408static int igb_request_irq(struct igb_adapter *adapter)
1409{
1410 struct net_device *netdev = adapter->netdev;
047e0030 1411 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1412 int err = 0;
1413
cd14ef54 1414 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1415 err = igb_request_msix(adapter);
844290e5 1416 if (!err)
9d5c8243 1417 goto request_done;
9d5c8243 1418 /* fall back to MSI */
5536d210
AD		 1419 igb_free_all_tx_resources(adapter);
1420 igb_free_all_rx_resources(adapter);
53c7d064 1421
047e0030 1422 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1423 err = igb_init_interrupt_scheme(adapter, false);
1424 if (err)
047e0030 1425 goto request_done;
53c7d064 1426
047e0030
AD		 1427 igb_setup_all_tx_resources(adapter);
1428 igb_setup_all_rx_resources(adapter);
53c7d064 1429 igb_configure(adapter);
9d5c8243 1430 }
844290e5 1431
c74d588e
AD		 1432 igb_assign_vector(adapter->q_vector[0], 0);
1433
7dfc16fa 1434 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1435 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1436 netdev->name, adapter);
9d5c8243
AK		 1437 if (!err)
1438 goto request_done;
047e0030 1439
9d5c8243
AK		 1440 /* fall back to legacy interrupts */
1441 igb_reset_interrupt_capability(adapter);
7dfc16fa 1442 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1443 }
1444
c74d588e 1445 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1446 netdev->name, adapter);
9d5c8243 1447
6cb5e577 1448 if (err)
c74d588e 1449 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1450 err);
9d5c8243
AK		 1451
1452request_done:
1453 return err;
1454}
1455
1456static void igb_free_irq(struct igb_adapter *adapter)
1457{
cd14ef54 1458 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1459 int vector = 0, i;
1460
047e0030 1461 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1462
0d1ae7f4 1463 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1464 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1465 adapter->q_vector[i]);
047e0030
AD		 1466 } else {
1467 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1468 }
9d5c8243
AK		 1469}
1470
1471/**
b980ac18
JK		 1472 * igb_irq_disable - Mask off interrupt generation on the NIC
1473 * @adapter: board private structure
9d5c8243
AK		 1474 **/
1475static void igb_irq_disable(struct igb_adapter *adapter)
1476{
1477 struct e1000_hw *hw = &adapter->hw;
1478
b980ac18 1479 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1480 * mapped into these registers and so clearing the bits can cause
1481 * issues on the VF drivers so we only need to clear what we set
1482 */
cd14ef54 1483 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1484 u32 regval = rd32(E1000_EIAM);
9005df38 1485
2dfd1212
AD		 1486 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1487 wr32(E1000_EIMC, adapter->eims_enable_mask);
1488 regval = rd32(E1000_EIAC);
1489 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1490 }
844290e5
PW		 1491
1492 wr32(E1000_IAM, 0);
9d5c8243
AK		 1493 wr32(E1000_IMC, ~0);
1494 wrfl();
cd14ef54 1495 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1496 int i;
9005df38 1497
81a61859
ET		 1498 for (i = 0; i < adapter->num_q_vectors; i++)
1499 synchronize_irq(adapter->msix_entries[i].vector);
1500 } else {
1501 synchronize_irq(adapter->pdev->irq);
1502 }
9d5c8243
AK		 1503}
1504
1505/**
b980ac18
JK		 1506 * igb_irq_enable - Enable default interrupt generation settings
1507 * @adapter: board private structure
9d5c8243
AK		 1508 **/
1509static void igb_irq_enable(struct igb_adapter *adapter)
1510{
1511 struct e1000_hw *hw = &adapter->hw;
1512
cd14ef54 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1515 u32 regval = rd32(E1000_EIAC);
9005df38 1516
2dfd1212
AD		 1517 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1518 regval = rd32(E1000_EIAM);
1519 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1520 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1521 if (adapter->vfs_allocated_count) {
4ae196df 1522 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1523 ims |= E1000_IMS_VMMB;
1524 }
1525 wr32(E1000_IMS, ims);
844290e5 1526 } else {
55cac248
AD		 1527 wr32(E1000_IMS, IMS_ENABLE_MASK |
1528 E1000_IMS_DRSTA);
1529 wr32(E1000_IAM, IMS_ENABLE_MASK |
1530 E1000_IMS_DRSTA);
844290e5 1531 }
9d5c8243
AK		 1532}
1533
1534static void igb_update_mng_vlan(struct igb_adapter *adapter)
1535{
51466239 1536 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1537 u16 vid = adapter->hw.mng_cookie.vlan_id;
1538 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1539
1540 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1541 /* add VID to filter table */
1542 igb_vfta_set(hw, vid, true);
1543 adapter->mng_vlan_id = vid;
1544 } else {
1545 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1546 }
1547
1548 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1549 (vid != old_vid) &&
b2cb09b1 1550 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1551 /* remove VID from filter table */
1552 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1553 }
1554}
1555
1556/**
b980ac18
JK		 1557 * igb_release_hw_control - release control of the h/w to f/w
1558 * @adapter: address of board private structure
9d5c8243 1559 *
b980ac18
JK		 1560 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1561 * For ASF and Pass Through versions of f/w this means that the
1562 * driver is no longer loaded.
9d5c8243
AK		 1563 **/
1564static void igb_release_hw_control(struct igb_adapter *adapter)
1565{
1566 struct e1000_hw *hw = &adapter->hw;
1567 u32 ctrl_ext;
1568
1569 /* Let firmware take over control of h/w */
1570 ctrl_ext = rd32(E1000_CTRL_EXT);
1571 wr32(E1000_CTRL_EXT,
1572 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1573}
1574
9d5c8243 1575/**
b980ac18
JK		 1576 * igb_get_hw_control - get control of the h/w from f/w
1577 * @adapter: address of board private structure
9d5c8243 1578 *
b980ac18
JK		 1579 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1580 * For ASF and Pass Through versions of f/w this means that
1581 * the driver is loaded.
9d5c8243
AK		 1582 **/
1583static void igb_get_hw_control(struct igb_adapter *adapter)
1584{
1585 struct e1000_hw *hw = &adapter->hw;
1586 u32 ctrl_ext;
1587
1588 /* Let firmware know the driver has taken over */
1589 ctrl_ext = rd32(E1000_CTRL_EXT);
1590 wr32(E1000_CTRL_EXT,
1591 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1592}
1593
9d5c8243 1594/**
b980ac18
JK		 1595 * igb_configure - configure the hardware for RX and TX
1596 * @adapter: private board structure
9d5c8243
AK		 1597 **/
1598static void igb_configure(struct igb_adapter *adapter)
1599{
1600 struct net_device *netdev = adapter->netdev;
1601 int i;
1602
1603 igb_get_hw_control(adapter);
ff41f8dc 1604 igb_set_rx_mode(netdev);
9d5c8243
AK		 1605
1606 igb_restore_vlan(adapter);
9d5c8243 1607
85b430b4 1608 igb_setup_tctl(adapter);
06cf2666 1609 igb_setup_mrqc(adapter);
9d5c8243 1610 igb_setup_rctl(adapter);
85b430b4
AD		 1611
1612 igb_configure_tx(adapter);
9d5c8243 1613 igb_configure_rx(adapter);
662d7205
AD		 1614
1615 igb_rx_fifo_flush_82575(&adapter->hw);
1616
c493ea45 1617 /* call igb_desc_unused which always leaves
9d5c8243 1618 * at least 1 descriptor unused to make sure
b980ac18
JK		 1619 * next_to_use != next_to_clean
1620 */
9d5c8243 1621 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1622 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1623 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1624 }
9d5c8243
AK		 1625}
1626
88a268c1 1627/**
b980ac18
JK		 1628 * igb_power_up_link - Power up the phy/serdes link
1629 * @adapter: address of board private structure
88a268c1
NN		 1630 **/
1631void igb_power_up_link(struct igb_adapter *adapter)
1632{
76886596
AA		 1633 igb_reset_phy(&adapter->hw);
1634
88a268c1
NN		 1635 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1636 igb_power_up_phy_copper(&adapter->hw);
1637 else
1638 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1639
1640 igb_setup_link(&adapter->hw);
88a268c1
NN		 1641}
1642
1643/**
b980ac18
JK		 1644 * igb_power_down_link - Power down the phy/serdes link
1645 * @adapter: address of board private structure
88a268c1
NN		 1646 */
1647static void igb_power_down_link(struct igb_adapter *adapter)
1648{
1649 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1650 igb_power_down_phy_copper_82575(&adapter->hw);
1651 else
1652 igb_shutdown_serdes_link_82575(&adapter->hw);
1653}
9d5c8243 1654
56cec249
CW		 1655/**
1656 * Detect and switch function for Media Auto Sense
1657 * @adapter: address of the board private structure
1658 **/
1659static void igb_check_swap_media(struct igb_adapter *adapter)
1660{
1661 struct e1000_hw *hw = &adapter->hw;
1662 u32 ctrl_ext, connsw;
1663 bool swap_now = false;
1664
1665 ctrl_ext = rd32(E1000_CTRL_EXT);
1666 connsw = rd32(E1000_CONNSW);
1667
1668 /* need to live swap if current media is copper and we have fiber/serdes
1669 * to go to.
1670 */
1671
1672 if ((hw->phy.media_type == e1000_media_type_copper) &&
1673 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1674 swap_now = true;
1675 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1676 /* copper signal takes time to appear */
1677 if (adapter->copper_tries < 4) {
1678 adapter->copper_tries++;
1679 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1680 wr32(E1000_CONNSW, connsw);
1681 return;
1682 } else {
1683 adapter->copper_tries = 0;
1684 if ((connsw & E1000_CONNSW_PHYSD) &&
1685 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1686 swap_now = true;
1687 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1688 wr32(E1000_CONNSW, connsw);
1689 }
1690 }
1691 }
1692
1693 if (!swap_now)
1694 return;
1695
1696 switch (hw->phy.media_type) {
1697 case e1000_media_type_copper:
1698 netdev_info(adapter->netdev,
1699 "MAS: changing media to fiber/serdes\n");
1700 ctrl_ext |=
1701 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1702 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1703 adapter->copper_tries = 0;
1704 break;
1705 case e1000_media_type_internal_serdes:
1706 case e1000_media_type_fiber:
1707 netdev_info(adapter->netdev,
1708 "MAS: changing media to copper\n");
1709 ctrl_ext &=
1710 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1711 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1712 break;
1713 default:
1714 /* shouldn't get here during regular operation */
1715 netdev_err(adapter->netdev,
1716 "AMS: Invalid media type found, returning\n");
1717 break;
1718 }
1719 wr32(E1000_CTRL_EXT, ctrl_ext);
1720}
1721
9d5c8243 1722/**
b980ac18
JK		 1723 * igb_up - Open the interface and prepare it to handle traffic
1724 * @adapter: board private structure
9d5c8243 1725 **/
9d5c8243
AK		 1726int igb_up(struct igb_adapter *adapter)
1727{
1728 struct e1000_hw *hw = &adapter->hw;
1729 int i;
1730
1731 /* hardware has been reset, we need to reload some things */
1732 igb_configure(adapter);
1733
1734 clear_bit(__IGB_DOWN, &adapter->state);
1735
0d1ae7f4
AD		 1736 for (i = 0; i < adapter->num_q_vectors; i++)
1737 napi_enable(&(adapter->q_vector[i]->napi));
1738
cd14ef54 1739 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1740 igb_configure_msix(adapter);
feeb2721
AD		 1741 else
1742 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1743
1744 /* Clear any pending interrupts. */
1745 rd32(E1000_ICR);
1746 igb_irq_enable(adapter);
1747
d4960307
AD		 1748 /* notify VFs that reset has been completed */
1749 if (adapter->vfs_allocated_count) {
1750 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1751
d4960307
AD		 1752 reg_data |= E1000_CTRL_EXT_PFRSTD;
1753 wr32(E1000_CTRL_EXT, reg_data);
1754 }
1755
4cb9be7a
JB		 1756 netif_tx_start_all_queues(adapter->netdev);
1757
25568a53
AD		 1758 /* start the watchdog. */
1759 hw->mac.get_link_status = 1;
1760 schedule_work(&adapter->watchdog_task);
1761
f4c01e96
CW		 1762 if ((adapter->flags & IGB_FLAG_EEE) &&
1763 (!hw->dev_spec._82575.eee_disable))
1764 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1765
9d5c8243
AK		 1766 return 0;
1767}
1768
1769void igb_down(struct igb_adapter *adapter)
1770{
9d5c8243 1771 struct net_device *netdev = adapter->netdev;
330a6d6a 1772 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1773 u32 tctl, rctl;
1774 int i;
1775
1776 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1777 * reschedule our watchdog timer
1778 */
9d5c8243
AK		 1779 set_bit(__IGB_DOWN, &adapter->state);
1780
1781 /* disable receives in the hardware */
1782 rctl = rd32(E1000_RCTL);
1783 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1784 /* flush and sleep below */
1785
f28ea083 1786 netif_carrier_off(netdev);
fd2ea0a7 1787 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1788
1789 /* disable transmits in the hardware */
1790 tctl = rd32(E1000_TCTL);
1791 tctl &= ~E1000_TCTL_EN;
1792 wr32(E1000_TCTL, tctl);
1793 /* flush both disables and wait for them to finish */
1794 wrfl();
0d451e79 1795 usleep_range(10000, 11000);
9d5c8243 1796
41f149a2
CW		 1797 igb_irq_disable(adapter);
1798
aa9b8cc4
AA		 1799 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1800
41f149a2 1801 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1802 if (adapter->q_vector[i]) {
1803 napi_synchronize(&adapter->q_vector[i]->napi);
1804 napi_disable(&adapter->q_vector[i]->napi);
1805 }
41f149a2 1806 }
9d5c8243 1807
9d5c8243
AK		 1808 del_timer_sync(&adapter->watchdog_timer);
1809 del_timer_sync(&adapter->phy_info_timer);
1810
04fe6358 1811 /* record the stats before reset*/
12dcd86b
ED		 1812 spin_lock(&adapter->stats64_lock);
1813 igb_update_stats(adapter, &adapter->stats64);
1814 spin_unlock(&adapter->stats64_lock);
04fe6358 1815
9d5c8243
AK		 1816 adapter->link_speed = 0;
1817 adapter->link_duplex = 0;
1818
3023682e
JK		 1819 if (!pci_channel_offline(adapter->pdev))
1820 igb_reset(adapter);
9d5c8243
AK		 1821 igb_clean_all_tx_rings(adapter);
1822 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1823#ifdef CONFIG_IGB_DCA
1824
1825 /* since we reset the hardware DCA settings were cleared */
1826 igb_setup_dca(adapter);
1827#endif
9d5c8243
AK		 1828}
1829
1830void igb_reinit_locked(struct igb_adapter *adapter)
1831{
1832 WARN_ON(in_interrupt());
1833 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1834 usleep_range(1000, 2000);
9d5c8243
AK		 1835 igb_down(adapter);
1836 igb_up(adapter);
1837 clear_bit(__IGB_RESETTING, &adapter->state);
1838}
1839
56cec249
CW		 1840/** igb_enable_mas - Media Autosense re-enable after swap
1841 *
1842 * @adapter: adapter struct
1843 **/
8cfb879d 1844static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1845{
1846 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1847 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1848
1849 /* configure for SerDes media detect */
8cfb879d
TF		 1850 if ((hw->phy.media_type == e1000_media_type_copper) &&
1851 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1852 connsw |= E1000_CONNSW_ENRGSRC;
1853 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1854 wr32(E1000_CONNSW, connsw);
1855 wrfl();
56cec249 1856 }
56cec249
CW		 1857}
1858
9d5c8243
AK		 1859void igb_reset(struct igb_adapter *adapter)
1860{
090b1795 1861 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1862 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1863 struct e1000_mac_info *mac = &hw->mac;
1864 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1865 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1866
1867 /* Repartition Pba for greater than 9k mtu
1868 * To take effect CTRL.RST is required.
1869 */
fa4dfae0 1870 switch (mac->type) {
d2ba2ed8 1871 case e1000_i350:
ceb5f13b 1872 case e1000_i354:
55cac248
AD		 1873 case e1000_82580:
1874 pba = rd32(E1000_RXPBS);
1875 pba = igb_rxpbs_adjust_82580(pba);
1876 break;
fa4dfae0 1877 case e1000_82576:
d249be54
AD		 1878 pba = rd32(E1000_RXPBS);
1879 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1880 break;
1881 case e1000_82575:
f96a8a0b
CW		 1882 case e1000_i210:
1883 case e1000_i211:
fa4dfae0
AD		 1884 default:
1885 pba = E1000_PBA_34K;
1886 break;
2d064c06 1887 }
9d5c8243 1888
2d064c06
AD		 1889 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1890 (mac->type < e1000_82576)) {
9d5c8243
AK		 1891 /* adjust PBA for jumbo frames */
1892 wr32(E1000_PBA, pba);
1893
1894 /* To maintain wire speed transmits, the Tx FIFO should be
1895 * large enough to accommodate two full transmit packets,
1896 * rounded up to the next 1KB and expressed in KB. Likewise,
1897 * the Rx FIFO should be large enough to accommodate at least
1898 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1899 * expressed in KB.
1900 */
9d5c8243
AK		 1901 pba = rd32(E1000_PBA);
1902 /* upper 16 bits has Tx packet buffer allocation size in KB */
1903 tx_space = pba >> 16;
1904 /* lower 16 bits has Rx packet buffer allocation size in KB */
1905 pba &= 0xffff;
b980ac18
JK		 1906 /* the Tx fifo also stores 16 bytes of information about the Tx
1907 * but don't include ethernet FCS because hardware appends it
1908 */
9d5c8243 1909 min_tx_space = (adapter->max_frame_size +
85e8d004 1910 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1911 ETH_FCS_LEN) * 2;
1912 min_tx_space = ALIGN(min_tx_space, 1024);
1913 min_tx_space >>= 10;
1914 /* software strips receive CRC, so leave room for it */
1915 min_rx_space = adapter->max_frame_size;
1916 min_rx_space = ALIGN(min_rx_space, 1024);
1917 min_rx_space >>= 10;
1918
1919 /* If current Tx allocation is less than the min Tx FIFO size,
1920 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1921 * allocation, take space away from current Rx allocation
1922 */
9d5c8243
AK		 1923 if (tx_space < min_tx_space &&
1924 ((min_tx_space - tx_space) < pba)) {
1925 pba = pba - (min_tx_space - tx_space);
1926
b980ac18
JK		 1927 /* if short on Rx space, Rx wins and must trump Tx
1928 * adjustment
1929 */
9d5c8243
AK		 1930 if (pba < min_rx_space)
1931 pba = min_rx_space;
1932 }
2d064c06 1933 wr32(E1000_PBA, pba);
9d5c8243 1934 }
9d5c8243
AK		 1935
1936 /* flow control settings */
1937 /* The high water mark must be low enough to fit one full frame
1938 * (or the size used for early receive) above it in the Rx FIFO.
1939 * Set it to the lower of:
1940 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1941 * - the full Rx FIFO size minus one full frame
1942 */
9d5c8243 1943 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1944 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1945
d48507fe 1946 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1947 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1948 fc->pause_time = 0xFFFF;
1949 fc->send_xon = 1;
0cce119a 1950 fc->current_mode = fc->requested_mode;
9d5c8243 1951
4ae196df
AD		 1952 /* disable receive for all VFs and wait one second */
1953 if (adapter->vfs_allocated_count) {
1954 int i;
9005df38 1955
4ae196df 1956 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1957 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1958
1959 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1960 igb_ping_all_vfs(adapter);
4ae196df
AD		 1961
1962 /* disable transmits and receives */
1963 wr32(E1000_VFRE, 0);
1964 wr32(E1000_VFTE, 0);
1965 }
1966
9d5c8243 1967 /* Allow time for pending master requests to run */
330a6d6a 1968 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1969 wr32(E1000_WUC, 0);
1970
56cec249
CW		 1971 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1972 /* need to resetup here after media swap */
1973 adapter->ei.get_invariants(hw);
1974 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1975 }
8cfb879d
TF		 1976 if ((mac->type == e1000_82575) &&
1977 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1978 igb_enable_mas(adapter);
56cec249 1979 }
330a6d6a 1980 if (hw->mac.ops.init_hw(hw))
090b1795 1981 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1982
b980ac18 1983 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1984 * control is off when forcing speed.
1985 */
1986 if (!hw->mac.autoneg)
1987 igb_force_mac_fc(hw);
1988
b6e0c419 1989 igb_init_dmac(adapter, pba);
e428893b
CW		 1990#ifdef CONFIG_IGB_HWMON
1991 /* Re-initialize the thermal sensor on i350 devices. */
1992 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1993 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1994 /* If present, re-initialize the external thermal sensor
1995 * interface.
1996 */
1997 if (adapter->ets)
1998 mac->ops.init_thermal_sensor_thresh(hw);
1999 }
2000 }
2001#endif
b936136d 2002 /* Re-establish EEE setting */
f4c01e96
CW		 2003 if (hw->phy.media_type == e1000_media_type_copper) {
2004 switch (mac->type) {
2005 case e1000_i350:
2006 case e1000_i210:
2007 case e1000_i211:
c4c112f1 2008 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2009 break;
2010 case e1000_i354:
c4c112f1 2011 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2012 break;
2013 default:
2014 break;
2015 }
2016 }
88a268c1
NN		 2017 if (!netif_running(adapter->netdev))
2018 igb_power_down_link(adapter);
2019
9d5c8243
AK		 2020 igb_update_mng_vlan(adapter);
2021
2022 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2023 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2024
1f6e8178
MV		 2025 /* Re-enable PTP, where applicable. */
2026 igb_ptp_reset(adapter);
1f6e8178 2027
330a6d6a 2028 igb_get_phy_info(hw);
9d5c8243
AK		 2029}
2030
c8f44aff
MM		 2031static netdev_features_t igb_fix_features(struct net_device *netdev,
2032 netdev_features_t features)
b2cb09b1 2033{
b980ac18
JK		 2034 /* Since there is no support for separate Rx/Tx vlan accel
2035 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2036 */
f646968f
PM		 2037 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2038 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2039 else
f646968f 2040 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2041
2042 return features;
2043}
2044
c8f44aff
MM		 2045static int igb_set_features(struct net_device *netdev,
2046 netdev_features_t features)
ac52caa3 2047{
c8f44aff 2048 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2049 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2050
f646968f 2051 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2052 igb_vlan_mode(netdev, features);
2053
89eaefb6
BG		 2054 if (!(changed & NETIF_F_RXALL))
2055 return 0;
2056
2057 netdev->features = features;
2058
2059 if (netif_running(netdev))
2060 igb_reinit_locked(adapter);
2061 else
2062 igb_reset(adapter);
2063
ac52caa3
MM		 2064 return 0;
2065}
2066
2e5c6922 2067static const struct net_device_ops igb_netdev_ops = {
559e9c49 2068 .ndo_open = igb_open,
2e5c6922 2069 .ndo_stop = igb_close,
cd392f5c 2070 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2071 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2072 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2073 .ndo_set_mac_address = igb_set_mac,
2074 .ndo_change_mtu = igb_change_mtu,
2075 .ndo_do_ioctl = igb_ioctl,
2076 .ndo_tx_timeout = igb_tx_timeout,
2077 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2078 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2079 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2080 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2081 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2082 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2083 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2084 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2085#ifdef CONFIG_NET_POLL_CONTROLLER
2086 .ndo_poll_controller = igb_netpoll,
2087#endif
b2cb09b1
JP		 2088 .ndo_fix_features = igb_fix_features,
2089 .ndo_set_features = igb_set_features,
1abbc98a 2090 .ndo_features_check = passthru_features_check,
2e5c6922
SH		 2091};
2092
d67974f0
CW		 2093/**
2094 * igb_set_fw_version - Configure version string for ethtool
2095 * @adapter: adapter struct
d67974f0
CW		 2096 **/
2097void igb_set_fw_version(struct igb_adapter *adapter)
2098{
2099 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2100 struct e1000_fw_version fw;
2101
2102 igb_get_fw_version(hw, &fw);
2103
2104 switch (hw->mac.type) {
7dc98a62 2105 case e1000_i210:
0b1a6f2e 2106 case e1000_i211:
7dc98a62
CW		 2107 if (!(igb_get_flash_presence_i210(hw))) {
2108 snprintf(adapter->fw_version,
2109 sizeof(adapter->fw_version),
2110 "%2d.%2d-%d",
2111 fw.invm_major, fw.invm_minor,
2112 fw.invm_img_type);
2113 break;
2114 }
2115 /* fall through */
0b1a6f2e
CW		 2116 default:
2117 /* if option is rom valid, display its version too */
2118 if (fw.or_valid) {
2119 snprintf(adapter->fw_version,
2120 sizeof(adapter->fw_version),
2121 "%d.%d, 0x%08x, %d.%d.%d",
2122 fw.eep_major, fw.eep_minor, fw.etrack_id,
2123 fw.or_major, fw.or_build, fw.or_patch);
2124 /* no option rom */
7dc98a62 2125 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2126 snprintf(adapter->fw_version,
7dc98a62
CW		 2127 sizeof(adapter->fw_version),
2128 "%d.%d, 0x%08x",
2129 fw.eep_major, fw.eep_minor, fw.etrack_id);
2130 } else {
2131 snprintf(adapter->fw_version,
2132 sizeof(adapter->fw_version),
2133 "%d.%d.%d",
2134 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2135 }
2136 break;
d67974f0 2137 }
d67974f0
CW		 2138}
2139
56cec249
CW		 2140/**
2141 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2142 *
2143 * @adapter: adapter struct
2144 **/
2145static void igb_init_mas(struct igb_adapter *adapter)
2146{
2147 struct e1000_hw *hw = &adapter->hw;
2148 u16 eeprom_data;
2149
2150 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2151 switch (hw->bus.func) {
2152 case E1000_FUNC_0:
2153 if (eeprom_data & IGB_MAS_ENABLE_0) {
2154 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2155 netdev_info(adapter->netdev,
2156 "MAS: Enabling Media Autosense for port %d\n",
2157 hw->bus.func);
2158 }
2159 break;
2160 case E1000_FUNC_1:
2161 if (eeprom_data & IGB_MAS_ENABLE_1) {
2162 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2163 netdev_info(adapter->netdev,
2164 "MAS: Enabling Media Autosense for port %d\n",
2165 hw->bus.func);
2166 }
2167 break;
2168 case E1000_FUNC_2:
2169 if (eeprom_data & IGB_MAS_ENABLE_2) {
2170 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2171 netdev_info(adapter->netdev,
2172 "MAS: Enabling Media Autosense for port %d\n",
2173 hw->bus.func);
2174 }
2175 break;
2176 case E1000_FUNC_3:
2177 if (eeprom_data & IGB_MAS_ENABLE_3) {
2178 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2179 netdev_info(adapter->netdev,
2180 "MAS: Enabling Media Autosense for port %d\n",
2181 hw->bus.func);
2182 }
2183 break;
2184 default:
2185 /* Shouldn't get here */
2186 netdev_err(adapter->netdev,
2187 "MAS: Invalid port configuration, returning\n");
2188 break;
2189 }
2190}
2191
b980ac18
JK		 2192/**
2193 * igb_init_i2c - Init I2C interface
441fc6fd 2194 * @adapter: pointer to adapter structure
b980ac18 2195 **/
441fc6fd
CW		 2196static s32 igb_init_i2c(struct igb_adapter *adapter)
2197{
23d87824 2198 s32 status = 0;
441fc6fd
CW		 2199
2200 /* I2C interface supported on i350 devices */
2201 if (adapter->hw.mac.type != e1000_i350)
23d87824 2202 return 0;
441fc6fd
CW		 2203
2204 /* Initialize the i2c bus which is controlled by the registers.
2205 * This bus will use the i2c_algo_bit structue that implements
2206 * the protocol through toggling of the 4 bits in the register.
2207 */
2208 adapter->i2c_adap.owner = THIS_MODULE;
2209 adapter->i2c_algo = igb_i2c_algo;
2210 adapter->i2c_algo.data = adapter;
2211 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2212 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2213 strlcpy(adapter->i2c_adap.name, "igb BB",
2214 sizeof(adapter->i2c_adap.name));
2215 status = i2c_bit_add_bus(&adapter->i2c_adap);
2216 return status;
2217}
2218
9d5c8243 2219/**
b980ac18
JK		 2220 * igb_probe - Device Initialization Routine
2221 * @pdev: PCI device information struct
2222 * @ent: entry in igb_pci_tbl
9d5c8243 2223 *
b980ac18 2224 * Returns 0 on success, negative on failure
9d5c8243 2225 *
b980ac18
JK		 2226 * igb_probe initializes an adapter identified by a pci_dev structure.
2227 * The OS initialization, configuring of the adapter private structure,
2228 * and a hardware reset occur.
9d5c8243 2229 **/
1dd06ae8 2230static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2231{
2232 struct net_device *netdev;
2233 struct igb_adapter *adapter;
2234 struct e1000_hw *hw;
4337e993 2235 u16 eeprom_data = 0;
9835fd73 2236 s32 ret_val;
4337e993 2237 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2238 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2239 int err, pci_using_dac;
9835fd73 2240 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2241
bded64a7
AG		 2242 /* Catch broken hardware that put the wrong VF device ID in
2243 * the PCIe SR-IOV capability.
2244 */
2245 if (pdev->is_virtfn) {
2246 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2247 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2248 return -EINVAL;
2249 }
2250
aed5dec3 2251 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2252 if (err)
2253 return err;
2254
2255 pci_using_dac = 0;
dc4ff9bb 2256 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2257 if (!err) {
dc4ff9bb 2258 pci_using_dac = 1;
9d5c8243 2259 } else {
dc4ff9bb 2260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2261 if (err) {
dc4ff9bb
RK		 2262 dev_err(&pdev->dev,
2263 "No usable DMA configuration, aborting\n");
2264 goto err_dma;
9d5c8243
AK		 2265 }
2266 }
2267
aed5dec3 2268 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2269 IORESOURCE_MEM),
2270 igb_driver_name);
9d5c8243
AK		 2271 if (err)
2272 goto err_pci_reg;
2273
19d5afd4 2274 pci_enable_pcie_error_reporting(pdev);
40a914fa 2275
9d5c8243 2276 pci_set_master(pdev);
c682fc23 2277 pci_save_state(pdev);
9d5c8243
AK		 2278
2279 err = -ENOMEM;
1bfaf07b 2280 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2281 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2282 if (!netdev)
2283 goto err_alloc_etherdev;
2284
2285 SET_NETDEV_DEV(netdev, &pdev->dev);
2286
2287 pci_set_drvdata(pdev, netdev);
2288 adapter = netdev_priv(netdev);
2289 adapter->netdev = netdev;
2290 adapter->pdev = pdev;
2291 hw = &adapter->hw;
2292 hw->back = adapter;
b3f4d599 2293 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2294
9d5c8243 2295 err = -EIO;
73bf8048
JW		 2296 adapter->io_addr = pci_iomap(pdev, 0, 0);
2297 if (!adapter->io_addr)
9d5c8243 2298 goto err_ioremap;
73bf8048
JW		 2299 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2300 hw->hw_addr = adapter->io_addr;
9d5c8243 2301
2e5c6922 2302 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2303 igb_set_ethtool_ops(netdev);
9d5c8243 2304 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2305
2306 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2307
89dbefb2
AS		 2308 netdev->mem_start = pci_resource_start(pdev, 0);
2309 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2310
9d5c8243
AK		 2311 /* PCI config space info */
2312 hw->vendor_id = pdev->vendor;
2313 hw->device_id = pdev->device;
2314 hw->revision_id = pdev->revision;
2315 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2316 hw->subsystem_device_id = pdev->subsystem_device;
2317
9d5c8243
AK		 2318 /* Copy the default MAC, PHY and NVM function pointers */
2319 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2320 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2321 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2322 /* Initialize skew-specific constants */
2323 err = ei->get_invariants(hw);
2324 if (err)
450c87c8 2325 goto err_sw_init;
9d5c8243 2326
450c87c8 2327 /* setup the private structure */
9d5c8243
AK		 2328 err = igb_sw_init(adapter);
2329 if (err)
2330 goto err_sw_init;
2331
2332 igb_get_bus_info_pcie(hw);
2333
2334 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2335
2336 /* Copper options */
2337 if (hw->phy.media_type == e1000_media_type_copper) {
2338 hw->phy.mdix = AUTO_ALL_MODES;
2339 hw->phy.disable_polarity_correction = false;
2340 hw->phy.ms_type = e1000_ms_hw_default;
2341 }
2342
2343 if (igb_check_reset_block(hw))
2344 dev_info(&pdev->dev,
2345 "PHY reset is blocked due to SOL/IDER session.\n");
2346
b980ac18 2347 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2348 * set by igb_sw_init so we should use an or instead of an
2349 * assignment.
2350 */
2351 netdev->features |= NETIF_F_SG |
2352 NETIF_F_IP_CSUM |
2353 NETIF_F_IPV6_CSUM |
2354 NETIF_F_TSO |
2355 NETIF_F_TSO6 |
2356 NETIF_F_RXHASH |
2357 NETIF_F_RXCSUM |
f646968f
PM		 2358 NETIF_F_HW_VLAN_CTAG_RX |
2359 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2360
2361 /* copy netdev features into list of user selectable features */
2362 netdev->hw_features |= netdev->features;
89eaefb6 2363 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2364
2365 /* set this bit last since it cannot be part of hw_features */
f646968f 2366 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2367
2368 netdev->vlan_features |= NETIF_F_TSO |
2369 NETIF_F_TSO6 |
2370 NETIF_F_IP_CSUM |
2371 NETIF_F_IPV6_CSUM |
2372 NETIF_F_SG;
48f29ffc 2373
6b8f0922
BG		 2374 netdev->priv_flags |= IFF_SUPP_NOFCS;
2375
7b872a55 2376 if (pci_using_dac) {
9d5c8243 2377 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2378 netdev->vlan_features |= NETIF_F_HIGHDMA;
2379 }
9d5c8243 2380
ac52caa3 2381 if (hw->mac.type >= e1000_82576) {
53692b1d
TH		 2382 netdev->hw_features |= NETIF_F_SCTP_CRC;
2383 netdev->features |= NETIF_F_SCTP_CRC;
ac52caa3 2384 }
b9473560 2385
01789349
JP		 2386 netdev->priv_flags |= IFF_UNICAST_FLT;
2387
330a6d6a 2388 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2389
2390 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2391 * known good starting state
2392 */
9d5c8243
AK		 2393 hw->mac.ops.reset_hw(hw);
2394
ef3a0092
CW		 2395 /* make sure the NVM is good , i211/i210 parts can have special NVM
2396 * that doesn't contain a checksum
f96a8a0b 2397 */
ef3a0092
CW		 2398 switch (hw->mac.type) {
2399 case e1000_i210:
2400 case e1000_i211:
2401 if (igb_get_flash_presence_i210(hw)) {
2402 if (hw->nvm.ops.validate(hw) < 0) {
2403 dev_err(&pdev->dev,
2404 "The NVM Checksum Is Not Valid\n");
2405 err = -EIO;
2406 goto err_eeprom;
2407 }
2408 }
2409 break;
2410 default:
f96a8a0b
CW		 2411 if (hw->nvm.ops.validate(hw) < 0) {
2412 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2413 err = -EIO;
2414 goto err_eeprom;
2415 }
ef3a0092 2416 break;
9d5c8243
AK		 2417 }
2418
2419 /* copy the MAC address out of the NVM */
2420 if (hw->mac.ops.read_mac_addr(hw))
2421 dev_err(&pdev->dev, "NVM Read Error\n");
2422
2423 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2424
aaeb6cdf 2425 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2426 dev_err(&pdev->dev, "Invalid MAC Address\n");
2427 err = -EIO;
2428 goto err_eeprom;
2429 }
2430
d67974f0
CW		 2431 /* get firmware version for ethtool -i */
2432 igb_set_fw_version(adapter);
2433
27dff8b2
TF		 2434 /* configure RXPBSIZE and TXPBSIZE */
2435 if (hw->mac.type == e1000_i210) {
2436 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2437 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2438 }
2439
c061b18d 2440 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2441 (unsigned long) adapter);
c061b18d 2442 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2443 (unsigned long) adapter);
9d5c8243
AK		 2444
2445 INIT_WORK(&adapter->reset_task, igb_reset_task);
2446 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2447
450c87c8 2448 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2449 adapter->fc_autoneg = true;
2450 hw->mac.autoneg = true;
2451 hw->phy.autoneg_advertised = 0x2f;
2452
0cce119a
AD		 2453 hw->fc.requested_mode = e1000_fc_default;
2454 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2455
9d5c8243
AK		 2456 igb_validate_mdi_setting(hw);
2457
63d4a8f9 2458 /* By default, support wake on port A */
a2cf8b6c 2459 if (hw->bus.func == 0)
63d4a8f9
MV		 2460 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2461
2462 /* Check the NVM for wake support on non-port A ports */
2463 if (hw->mac.type >= e1000_82580)
55cac248 2464 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2465 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2466 &eeprom_data);
a2cf8b6c
AD		 2467 else if (hw->bus.func == 1)
2468 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2469
63d4a8f9
MV		 2470 if (eeprom_data & IGB_EEPROM_APME)
2471 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2472
2473 /* now that we have the eeprom settings, apply the special cases where
2474 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2475 * lan on a particular port
2476 */
9d5c8243
AK		 2477 switch (pdev->device) {
2478 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2479 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2480 break;
2481 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2482 case E1000_DEV_ID_82576_FIBER:
2483 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2484 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2485 * regardless of eeprom setting
2486 */
9d5c8243 2487 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2488 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2489 break;
c8ea5ea9 2490 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2491 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2492 /* if quad port adapter, disable WoL on all but port A */
2493 if (global_quad_port_a != 0)
63d4a8f9 2494 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2495 else
2496 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2497 /* Reset for multiple quad port adapters */
2498 if (++global_quad_port_a == 4)
2499 global_quad_port_a = 0;
2500 break;
63d4a8f9
MV		 2501 default:
2502 /* If the device can't wake, don't set software support */
2503 if (!device_can_wakeup(&adapter->pdev->dev))
2504 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2505 }
2506
2507 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2508 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2509 adapter->wol |= E1000_WUFC_MAG;
2510
2511 /* Some vendors want WoL disabled by default, but still supported */
2512 if ((hw->mac.type == e1000_i350) &&
2513 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2514 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2515 adapter->wol = 0;
2516 }
2517
2518 device_set_wakeup_enable(&adapter->pdev->dev,
2519 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2520
2521 /* reset the hardware with the new settings */
2522 igb_reset(adapter);
2523
441fc6fd
CW		 2524 /* Init the I2C interface */
2525 err = igb_init_i2c(adapter);
2526 if (err) {
2527 dev_err(&pdev->dev, "failed to init i2c interface\n");
2528 goto err_eeprom;
2529 }
2530
9d5c8243 2531 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2532 * driver.
2533 */
9d5c8243
AK		 2534 igb_get_hw_control(adapter);
2535
9d5c8243
AK		 2536 strcpy(netdev->name, "eth%d");
2537 err = register_netdev(netdev);
2538 if (err)
2539 goto err_register;
2540
b168dfc5
JB		 2541 /* carrier off reporting is important to ethtool even BEFORE open */
2542 netif_carrier_off(netdev);
2543
421e02f0 2544#ifdef CONFIG_IGB_DCA
bbd98fe4 2545 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2546 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2547 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2548 igb_setup_dca(adapter);
2549 }
fe4506b6 2550
38c845c7 2551#endif
e428893b
CW		 2552#ifdef CONFIG_IGB_HWMON
2553 /* Initialize the thermal sensor on i350 devices. */
2554 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2555 u16 ets_word;
3c89f6d0 2556
b980ac18 2557 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2558 * external thermal sensor.
2559 */
2560 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2561 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2562 adapter->ets = true;
2563 else
2564 adapter->ets = false;
2565 if (igb_sysfs_init(adapter))
2566 dev_err(&pdev->dev,
2567 "failed to allocate sysfs resources\n");
2568 } else {
2569 adapter->ets = false;
2570 }
2571#endif
56cec249
CW		 2572 /* Check if Media Autosense is enabled */
2573 adapter->ei = *ei;
2574 if (hw->dev_spec._82575.mas_capable)
2575 igb_init_mas(adapter);
2576
673b8b70 2577 /* do hw tstamp init after resetting */
7ebae817 2578 igb_ptp_init(adapter);
673b8b70 2579
9d5c8243 2580 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2581 /* print bus type/speed/width info, not applicable to i354 */
2582 if (hw->mac.type != e1000_i354) {
2583 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2584 netdev->name,
2585 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2586 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2587 "unknown"),
2588 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2589 "Width x4" :
2590 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2591 "Width x2" :
2592 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2593 "Width x1" : "unknown"), netdev->dev_addr);
2594 }
9d5c8243 2595
53ea6c7e
TF		 2596 if ((hw->mac.type >= e1000_i210 ||
2597 igb_get_flash_presence_i210(hw))) {
2598 ret_val = igb_read_part_string(hw, part_str,
2599 E1000_PBANUM_LENGTH);
2600 } else {
2601 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2602 }
2603
9835fd73
CW		 2604 if (ret_val)
2605 strcpy(part_str, "Unknown");
2606 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2607 dev_info(&pdev->dev,
2608 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2609 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2610 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2611 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2612 if (hw->phy.media_type == e1000_media_type_copper) {
2613 switch (hw->mac.type) {
2614 case e1000_i350:
2615 case e1000_i210:
2616 case e1000_i211:
2617 /* Enable EEE for internal copper PHY devices */
c4c112f1 2618 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2619 if ((!err) &&
2620 (!hw->dev_spec._82575.eee_disable)) {
2621 adapter->eee_advert =
2622 MDIO_EEE_100TX | MDIO_EEE_1000T;
2623 adapter->flags |= IGB_FLAG_EEE;
2624 }
2625 break;
2626 case e1000_i354:
ceb5f13b 2627 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2628 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2629 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2630 if ((!err) &&
2631 (!hw->dev_spec._82575.eee_disable)) {
2632 adapter->eee_advert =
2633 MDIO_EEE_100TX | MDIO_EEE_1000T;
2634 adapter->flags |= IGB_FLAG_EEE;
2635 }
2636 }
2637 break;
2638 default:
2639 break;
ceb5f13b 2640 }
09b068d4 2641 }
749ab2cd 2642 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2643 return 0;
2644
2645err_register:
2646 igb_release_hw_control(adapter);
441fc6fd 2647 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2648err_eeprom:
2649 if (!igb_check_reset_block(hw))
f5f4cf08 2650 igb_reset_phy(hw);
9d5c8243
AK		 2651
2652 if (hw->flash_address)
2653 iounmap(hw->flash_address);
9d5c8243 2654err_sw_init:
42ad1a03 2655 kfree(adapter->shadow_vfta);
047e0030 2656 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2657#ifdef CONFIG_PCI_IOV
2658 igb_disable_sriov(pdev);
2659#endif
73bf8048 2660 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2661err_ioremap:
2662 free_netdev(netdev);
2663err_alloc_etherdev:
559e9c49 2664 pci_release_selected_regions(pdev,
b980ac18 2665 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2666err_pci_reg:
2667err_dma:
2668 pci_disable_device(pdev);
2669 return err;
2670}
2671
fa44f2f1 2672#ifdef CONFIG_PCI_IOV
781798a1 2673static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2674{
2675 struct net_device *netdev = pci_get_drvdata(pdev);
2676 struct igb_adapter *adapter = netdev_priv(netdev);
2677 struct e1000_hw *hw = &adapter->hw;
2678
2679 /* reclaim resources allocated to VFs */
2680 if (adapter->vf_data) {
2681 /* disable iov and allow time for transactions to clear */
b09186d2 2682 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2683 dev_warn(&pdev->dev,
2684 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2685 return -EPERM;
2686 } else {
2687 pci_disable_sriov(pdev);
2688 msleep(500);
2689 }
2690
2691 kfree(adapter->vf_data);
2692 adapter->vf_data = NULL;
2693 adapter->vfs_allocated_count = 0;
2694 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2695 wrfl();
2696 msleep(100);
2697 dev_info(&pdev->dev, "IOV Disabled\n");
2698
2699 /* Re-enable DMA Coalescing flag since IOV is turned off */
2700 adapter->flags |= IGB_FLAG_DMAC;
2701 }
2702
2703 return 0;
2704}
2705
2706static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2707{
2708 struct net_device *netdev = pci_get_drvdata(pdev);
2709 struct igb_adapter *adapter = netdev_priv(netdev);
2710 int old_vfs = pci_num_vf(pdev);
2711 int err = 0;
2712 int i;
2713
cd14ef54 2714 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2715 err = -EPERM;
2716 goto out;
2717 }
fa44f2f1
GR		 2718 if (!num_vfs)
2719 goto out;
fa44f2f1 2720
781798a1
SA		 2721 if (old_vfs) {
2722 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2723 old_vfs, max_vfs);
2724 adapter->vfs_allocated_count = old_vfs;
2725 } else
2726 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2727
2728 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2729 sizeof(struct vf_data_storage), GFP_KERNEL);
2730
2731 /* if allocation failed then we do not support SR-IOV */
2732 if (!adapter->vf_data) {
2733 adapter->vfs_allocated_count = 0;
2734 dev_err(&pdev->dev,
2735 "Unable to allocate memory for VF Data Storage\n");
2736 err = -ENOMEM;
2737 goto out;
2738 }
2739
781798a1
SA		 2740 /* only call pci_enable_sriov() if no VFs are allocated already */
2741 if (!old_vfs) {
2742 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2743 if (err)
2744 goto err_out;
2745 }
fa44f2f1
GR		 2746 dev_info(&pdev->dev, "%d VFs allocated\n",
2747 adapter->vfs_allocated_count);
2748 for (i = 0; i < adapter->vfs_allocated_count; i++)
2749 igb_vf_configure(adapter, i);
2750
2751 /* DMA Coalescing is not supported in IOV mode. */
2752 adapter->flags &= ~IGB_FLAG_DMAC;
2753 goto out;
2754
2755err_out:
2756 kfree(adapter->vf_data);
2757 adapter->vf_data = NULL;
2758 adapter->vfs_allocated_count = 0;
2759out:
2760 return err;
2761}
2762
2763#endif
b980ac18 2764/**
441fc6fd
CW		 2765 * igb_remove_i2c - Cleanup I2C interface
2766 * @adapter: pointer to adapter structure
b980ac18 2767 **/
441fc6fd
CW		 2768static void igb_remove_i2c(struct igb_adapter *adapter)
2769{
441fc6fd
CW		 2770 /* free the adapter bus structure */
2771 i2c_del_adapter(&adapter->i2c_adap);
2772}
2773
9d5c8243 2774/**
b980ac18
JK		 2775 * igb_remove - Device Removal Routine
2776 * @pdev: PCI device information struct
9d5c8243 2777 *
b980ac18
JK		 2778 * igb_remove is called by the PCI subsystem to alert the driver
2779 * that it should release a PCI device. The could be caused by a
2780 * Hot-Plug event, or because the driver is going to be removed from
2781 * memory.
9d5c8243 2782 **/
9f9a12f8 2783static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2784{
2785 struct net_device *netdev = pci_get_drvdata(pdev);
2786 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2787 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2788
749ab2cd 2789 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2790#ifdef CONFIG_IGB_HWMON
2791 igb_sysfs_exit(adapter);
2792#endif
441fc6fd 2793 igb_remove_i2c(adapter);
a79f4f88 2794 igb_ptp_stop(adapter);
b980ac18 2795 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2796 * disable watchdog from being rescheduled.
2797 */
9d5c8243
AK		 2798 set_bit(__IGB_DOWN, &adapter->state);
2799 del_timer_sync(&adapter->watchdog_timer);
2800 del_timer_sync(&adapter->phy_info_timer);
2801
760141a5
TH		 2802 cancel_work_sync(&adapter->reset_task);
2803 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2804
421e02f0 2805#ifdef CONFIG_IGB_DCA
7dfc16fa 2806 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2807 dev_info(&pdev->dev, "DCA disabled\n");
2808 dca_remove_requester(&pdev->dev);
7dfc16fa 2809 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2810 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2811 }
2812#endif
2813
9d5c8243 2814 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2815 * would have already happened in close and is redundant.
2816 */
9d5c8243
AK		 2817 igb_release_hw_control(adapter);
2818
37680117 2819#ifdef CONFIG_PCI_IOV
fa44f2f1 2820 igb_disable_sriov(pdev);
37680117 2821#endif
559e9c49 2822
c23d92b8
AW		 2823 unregister_netdev(netdev);
2824
2825 igb_clear_interrupt_scheme(adapter);
2826
73bf8048 2827 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2828 if (hw->flash_address)
2829 iounmap(hw->flash_address);
559e9c49 2830 pci_release_selected_regions(pdev,
b980ac18 2831 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2832
1128c756 2833 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2834 free_netdev(netdev);
2835
19d5afd4 2836 pci_disable_pcie_error_reporting(pdev);
40a914fa 2837
9d5c8243
AK		 2838 pci_disable_device(pdev);
2839}
2840
a6b623e0 2841/**
b980ac18
JK		 2842 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2843 * @adapter: board private structure to initialize
a6b623e0 2844 *
b980ac18
JK		 2845 * This function initializes the vf specific data storage and then attempts to
2846 * allocate the VFs. The reason for ordering it this way is because it is much
2847 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2848 * the memory for the VFs.
a6b623e0 2849 **/
9f9a12f8 2850static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2851{
2852#ifdef CONFIG_PCI_IOV
2853 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2854 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2855
f96a8a0b
CW		 2856 /* Virtualization features not supported on i210 family. */
2857 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2858 return;
2859
be06998f
JB		 2860 /* Of the below we really only want the effect of getting
2861 * IGB_FLAG_HAS_MSIX set (if available), without which
2862 * igb_enable_sriov() has no effect.
2863 */
2864 igb_set_interrupt_capability(adapter, true);
2865 igb_reset_interrupt_capability(adapter);
2866
fa44f2f1 2867 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2868 igb_enable_sriov(pdev, max_vfs);
0224d663 2869
a6b623e0
AD		 2870#endif /* CONFIG_PCI_IOV */
2871}
2872
fa44f2f1 2873static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2874{
2875 struct e1000_hw *hw = &adapter->hw;
374a542d 2876 u32 max_rss_queues;
9d5c8243 2877
374a542d 2878 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2879 switch (hw->mac.type) {
374a542d
MV		 2880 case e1000_i211:
2881 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2882 break;
2883 case e1000_82575:
f96a8a0b 2884 case e1000_i210:
374a542d
MV		 2885 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2886 break;
2887 case e1000_i350:
2888 /* I350 cannot do RSS and SR-IOV at the same time */
2889 if (!!adapter->vfs_allocated_count) {
2890 max_rss_queues = 1;
2891 break;
2892 }
2893 /* fall through */
2894 case e1000_82576:
2895 if (!!adapter->vfs_allocated_count) {
2896 max_rss_queues = 2;
2897 break;
2898 }
2899 /* fall through */
2900 case e1000_82580:
ceb5f13b 2901 case e1000_i354:
374a542d
MV		 2902 default:
2903 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2904 break;
374a542d
MV		 2905 }
2906
2907 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2908
72ddef05
SS		 2909 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2910}
2911
2912void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2913 const u32 max_rss_queues)
2914{
2915 struct e1000_hw *hw = &adapter->hw;
2916
374a542d
MV		 2917 /* Determine if we need to pair queues. */
2918 switch (hw->mac.type) {
2919 case e1000_82575:
f96a8a0b 2920 case e1000_i211:
374a542d 2921 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2922 break;
374a542d 2923 case e1000_82576:
374a542d
MV		 2924 case e1000_82580:
2925 case e1000_i350:
ceb5f13b 2926 case e1000_i354:
374a542d 2927 case e1000_i210:
f96a8a0b 2928 default:
b980ac18 2929 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2930 * order to conserve interrupts due to limited supply.
2931 */
2932 if (adapter->rss_queues > (max_rss_queues / 2))
2933 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2934 break;
2935 }
fa44f2f1
GR		 2936}
2937
2938/**
b980ac18
JK		 2939 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2940 * @adapter: board private structure to initialize
fa44f2f1 2941 *
b980ac18
JK		 2942 * igb_sw_init initializes the Adapter private data structure.
2943 * Fields are initialized based on PCI device information and
2944 * OS network device settings (MTU size).
fa44f2f1
GR		 2945 **/
2946static int igb_sw_init(struct igb_adapter *adapter)
2947{
2948 struct e1000_hw *hw = &adapter->hw;
2949 struct net_device *netdev = adapter->netdev;
2950 struct pci_dev *pdev = adapter->pdev;
2951
2952 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2953
2954 /* set default ring sizes */
2955 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2956 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2957
2958 /* set default ITR values */
2959 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2960 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2961
2962 /* set default work limits */
2963 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2964
2965 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2966 VLAN_HLEN;
2967 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2968
2969 spin_lock_init(&adapter->stats64_lock);
2970#ifdef CONFIG_PCI_IOV
2971 switch (hw->mac.type) {
2972 case e1000_82576:
2973 case e1000_i350:
2974 if (max_vfs > 7) {
2975 dev_warn(&pdev->dev,
2976 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2977 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2978 } else
2979 adapter->vfs_allocated_count = max_vfs;
2980 if (adapter->vfs_allocated_count)
2981 dev_warn(&pdev->dev,
2982 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2983 break;
2984 default:
2985 break;
2986 }
2987#endif /* CONFIG_PCI_IOV */
2988
cbfe360a
SA		 2989 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
2990 adapter->flags |= IGB_FLAG_HAS_MSIX;
2991
ceee3450
TF		 2992 igb_probe_vfs(adapter);
2993
fa44f2f1 2994 igb_init_queue_configuration(adapter);
a99955fc 2995
1128c756 2996 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2997 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2998 GFP_ATOMIC);
1128c756 2999
a6b623e0 3000 /* This call may decrease the number of queues */
53c7d064 3001 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3002 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3003 return -ENOMEM;
3004 }
3005
3006 /* Explicitly disable IRQ since the NIC can be in any state. */
3007 igb_irq_disable(adapter);
3008
f96a8a0b 3009 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3010 adapter->flags &= ~IGB_FLAG_DMAC;
3011
9d5c8243
AK		 3012 set_bit(__IGB_DOWN, &adapter->state);
3013 return 0;
3014}
3015
3016/**
b980ac18
JK		 3017 * igb_open - Called when a network interface is made active
3018 * @netdev: network interface device structure
9d5c8243 3019 *
b980ac18 3020 * Returns 0 on success, negative value on failure
9d5c8243 3021 *
b980ac18
JK		 3022 * The open entry point is called when a network interface is made
3023 * active by the system (IFF_UP). At this point all resources needed
3024 * for transmit and receive operations are allocated, the interrupt
3025 * handler is registered with the OS, the watchdog timer is started,
3026 * and the stack is notified that the interface is ready.
9d5c8243 3027 **/
749ab2cd 3028static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3029{
3030 struct igb_adapter *adapter = netdev_priv(netdev);
3031 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3032 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3033 int err;
3034 int i;
3035
3036 /* disallow open during test */
749ab2cd
YZ		 3037 if (test_bit(__IGB_TESTING, &adapter->state)) {
3038 WARN_ON(resuming);
9d5c8243 3039 return -EBUSY;
749ab2cd
YZ		 3040 }
3041
3042 if (!resuming)
3043 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3044
b168dfc5
JB		 3045 netif_carrier_off(netdev);
3046
9d5c8243
AK		 3047 /* allocate transmit descriptors */
3048 err = igb_setup_all_tx_resources(adapter);
3049 if (err)
3050 goto err_setup_tx;
3051
3052 /* allocate receive descriptors */
3053 err = igb_setup_all_rx_resources(adapter);
3054 if (err)
3055 goto err_setup_rx;
3056
88a268c1 3057 igb_power_up_link(adapter);
9d5c8243 3058
9d5c8243
AK		 3059 /* before we allocate an interrupt, we must be ready to handle it.
3060 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3061 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3062 * clean_rx handler before we do so.
3063 */
9d5c8243
AK		 3064 igb_configure(adapter);
3065
3066 err = igb_request_irq(adapter);
3067 if (err)
3068 goto err_req_irq;
3069
0c2cc02e
AD		 3070 /* Notify the stack of the actual queue counts. */
3071 err = netif_set_real_num_tx_queues(adapter->netdev,
3072 adapter->num_tx_queues);
3073 if (err)
3074 goto err_set_queues;
3075
3076 err = netif_set_real_num_rx_queues(adapter->netdev,
3077 adapter->num_rx_queues);
3078 if (err)
3079 goto err_set_queues;
3080
9d5c8243
AK		 3081 /* From here on the code is the same as igb_up() */
3082 clear_bit(__IGB_DOWN, &adapter->state);
3083
0d1ae7f4
AD		 3084 for (i = 0; i < adapter->num_q_vectors; i++)
3085 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3086
3087 /* Clear any pending interrupts. */
3088 rd32(E1000_ICR);
844290e5
PW		 3089
3090 igb_irq_enable(adapter);
3091
d4960307
AD		 3092 /* notify VFs that reset has been completed */
3093 if (adapter->vfs_allocated_count) {
3094 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3095
d4960307
AD		 3096 reg_data |= E1000_CTRL_EXT_PFRSTD;
3097 wr32(E1000_CTRL_EXT, reg_data);
3098 }
3099
d55b53ff
JK		 3100 netif_tx_start_all_queues(netdev);
3101
749ab2cd
YZ		 3102 if (!resuming)
3103 pm_runtime_put(&pdev->dev);
3104
25568a53
AD		 3105 /* start the watchdog. */
3106 hw->mac.get_link_status = 1;
3107 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3108
3109 return 0;
3110
0c2cc02e
AD		 3111err_set_queues:
3112 igb_free_irq(adapter);
9d5c8243
AK		 3113err_req_irq:
3114 igb_release_hw_control(adapter);
88a268c1 3115 igb_power_down_link(adapter);
9d5c8243
AK		 3116 igb_free_all_rx_resources(adapter);
3117err_setup_rx:
3118 igb_free_all_tx_resources(adapter);
3119err_setup_tx:
3120 igb_reset(adapter);
749ab2cd
YZ		 3121 if (!resuming)
3122 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3123
3124 return err;
3125}
3126
749ab2cd
YZ		 3127static int igb_open(struct net_device *netdev)
3128{
3129 return __igb_open(netdev, false);
3130}
3131
9d5c8243 3132/**
b980ac18
JK		 3133 * igb_close - Disables a network interface
3134 * @netdev: network interface device structure
9d5c8243 3135 *
b980ac18 3136 * Returns 0, this is not allowed to fail
9d5c8243 3137 *
b980ac18
JK		 3138 * The close entry point is called when an interface is de-activated
3139 * by the OS. The hardware is still under the driver's control, but
3140 * needs to be disabled. A global MAC reset is issued to stop the
3141 * hardware, and all transmit and receive resources are freed.
9d5c8243 3142 **/
749ab2cd 3143static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3144{
3145 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3146 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3147
3148 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3149
749ab2cd
YZ		 3150 if (!suspending)
3151 pm_runtime_get_sync(&pdev->dev);
3152
3153 igb_down(adapter);
9d5c8243
AK		 3154 igb_free_irq(adapter);
3155
3156 igb_free_all_tx_resources(adapter);
3157 igb_free_all_rx_resources(adapter);
3158
749ab2cd
YZ		 3159 if (!suspending)
3160 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3161 return 0;
3162}
3163
749ab2cd
YZ		 3164static int igb_close(struct net_device *netdev)
3165{
3166 return __igb_close(netdev, false);
3167}
3168
9d5c8243 3169/**
b980ac18
JK		 3170 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3171 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3172 *
b980ac18 3173 * Return 0 on success, negative on failure
9d5c8243 3174 **/
80785298 3175int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3176{
59d71989 3177 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3178 int size;
3179
06034649 3180 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3181
3182 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3183 if (!tx_ring->tx_buffer_info)
9d5c8243 3184 goto err;
9d5c8243
AK		 3185
3186 /* round up to nearest 4K */
85e8d004 3187 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3188 tx_ring->size = ALIGN(tx_ring->size, 4096);
3189
5536d210
AD		 3190 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3191 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3192 if (!tx_ring->desc)
3193 goto err;
3194
9d5c8243
AK		 3195 tx_ring->next_to_use = 0;
3196 tx_ring->next_to_clean = 0;
81c2fc22 3197
9d5c8243
AK		 3198 return 0;
3199
3200err:
06034649 3201 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3202 tx_ring->tx_buffer_info = NULL;
3203 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3204 return -ENOMEM;
3205}
3206
3207/**
b980ac18
JK		 3208 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3209 * (Descriptors) for all queues
3210 * @adapter: board private structure
9d5c8243 3211 *
b980ac18 3212 * Return 0 on success, negative on failure
9d5c8243
AK		 3213 **/
3214static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3215{
439705e1 3216 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3217 int i, err = 0;
3218
3219 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3220 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3221 if (err) {
439705e1 3222 dev_err(&pdev->dev,
9d5c8243
AK		 3223 "Allocation for Tx Queue %u failed\n", i);
3224 for (i--; i >= 0; i--)
3025a446 3225 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3226 break;
3227 }
3228 }
3229
3230 return err;
3231}
3232
3233/**
b980ac18
JK		 3234 * igb_setup_tctl - configure the transmit control registers
3235 * @adapter: Board private structure
9d5c8243 3236 **/
d7ee5b3a 3237void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3238{
9d5c8243
AK		 3239 struct e1000_hw *hw = &adapter->hw;
3240 u32 tctl;
9d5c8243 3241
85b430b4
AD		 3242 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3243 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3244
3245 /* Program the Transmit Control Register */
9d5c8243
AK		 3246 tctl = rd32(E1000_TCTL);
3247 tctl &= ~E1000_TCTL_CT;
3248 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3249 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3250
3251 igb_config_collision_dist(hw);
3252
9d5c8243
AK		 3253 /* Enable transmits */
3254 tctl |= E1000_TCTL_EN;
3255
3256 wr32(E1000_TCTL, tctl);
3257}
3258
85b430b4 3259/**
b980ac18
JK		 3260 * igb_configure_tx_ring - Configure transmit ring after Reset
3261 * @adapter: board private structure
3262 * @ring: tx ring to configure
85b430b4 3263 *
b980ac18 3264 * Configure a transmit ring after a reset.
85b430b4 3265 **/
d7ee5b3a 3266void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3267 struct igb_ring *ring)
85b430b4
AD		 3268{
3269 struct e1000_hw *hw = &adapter->hw;
a74420e0 3270 u32 txdctl = 0;
85b430b4
AD		 3271 u64 tdba = ring->dma;
3272 int reg_idx = ring->reg_idx;
3273
3274 /* disable the queue */
a74420e0 3275 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3276 wrfl();
3277 mdelay(10);
3278
3279 wr32(E1000_TDLEN(reg_idx),
b980ac18 3280 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3281 wr32(E1000_TDBAL(reg_idx),
b980ac18 3282 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3283 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3284
fce99e34 3285 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3286 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3287 writel(0, ring->tail);
85b430b4
AD		 3288
3289 txdctl |= IGB_TX_PTHRESH;
3290 txdctl |= IGB_TX_HTHRESH << 8;
3291 txdctl |= IGB_TX_WTHRESH << 16;
3292
3293 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3294 wr32(E1000_TXDCTL(reg_idx), txdctl);
3295}
3296
3297/**
b980ac18
JK		 3298 * igb_configure_tx - Configure transmit Unit after Reset
3299 * @adapter: board private structure
85b430b4 3300 *
b980ac18 3301 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3302 **/
3303static void igb_configure_tx(struct igb_adapter *adapter)
3304{
3305 int i;
3306
3307 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3308 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3309}
3310
9d5c8243 3311/**
b980ac18
JK		 3312 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3313 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3314 *
b980ac18 3315 * Returns 0 on success, negative on failure
9d5c8243 3316 **/
80785298 3317int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3318{
59d71989 3319 struct device *dev = rx_ring->dev;
f33005a6 3320 int size;
9d5c8243 3321
06034649 3322 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3323
3324 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3325 if (!rx_ring->rx_buffer_info)
9d5c8243 3326 goto err;
9d5c8243 3327
9d5c8243 3328 /* Round up to nearest 4K */
f33005a6 3329 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3330 rx_ring->size = ALIGN(rx_ring->size, 4096);
3331
5536d210
AD		 3332 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3333 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3334 if (!rx_ring->desc)
3335 goto err;
3336
cbc8e55f 3337 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3338 rx_ring->next_to_clean = 0;
3339 rx_ring->next_to_use = 0;
9d5c8243 3340
9d5c8243
AK		 3341 return 0;
3342
3343err:
06034649
AD		 3344 vfree(rx_ring->rx_buffer_info);
3345 rx_ring->rx_buffer_info = NULL;
f33005a6 3346 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3347 return -ENOMEM;
3348}
3349
3350/**
b980ac18
JK		 3351 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3352 * (Descriptors) for all queues
3353 * @adapter: board private structure
9d5c8243 3354 *
b980ac18 3355 * Return 0 on success, negative on failure
9d5c8243
AK		 3356 **/
3357static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3358{
439705e1 3359 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3360 int i, err = 0;
3361
3362 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3363 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3364 if (err) {
439705e1 3365 dev_err(&pdev->dev,
9d5c8243
AK		 3366 "Allocation for Rx Queue %u failed\n", i);
3367 for (i--; i >= 0; i--)
3025a446 3368 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3369 break;
3370 }
3371 }
3372
3373 return err;
3374}
3375
06cf2666 3376/**
b980ac18
JK		 3377 * igb_setup_mrqc - configure the multiple receive queue control registers
3378 * @adapter: Board private structure
06cf2666
AD		 3379 **/
3380static void igb_setup_mrqc(struct igb_adapter *adapter)
3381{
3382 struct e1000_hw *hw = &adapter->hw;
3383 u32 mrqc, rxcsum;
ed12cc9a 3384 u32 j, num_rx_queues;
eb31f849 3385 u32 rss_key[10];
06cf2666 3386
eb31f849 3387 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3388 for (j = 0; j < 10; j++)
eb31f849 3389 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3390
a99955fc 3391 num_rx_queues = adapter->rss_queues;
06cf2666 3392
797fd4be 3393 switch (hw->mac.type) {
797fd4be
AD		 3394 case e1000_82576:
3395 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3396 if (adapter->vfs_allocated_count)
06cf2666 3397 num_rx_queues = 2;
797fd4be
AD		 3398 break;
3399 default:
3400 break;
06cf2666
AD		 3401 }
3402
ed12cc9a
LMV		 3403 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3404 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3405 adapter->rss_indir_tbl[j] =
3406 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3407 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3408 }
ed12cc9a 3409 igb_write_rss_indir_tbl(adapter);
06cf2666 3410
b980ac18 3411 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3412 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3413 * offloads as they are enabled by default
3414 */
3415 rxcsum = rd32(E1000_RXCSUM);
3416 rxcsum |= E1000_RXCSUM_PCSD;
3417
3418 if (adapter->hw.mac.type >= e1000_82576)
3419 /* Enable Receive Checksum Offload for SCTP */
3420 rxcsum |= E1000_RXCSUM_CRCOFL;
3421
3422 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3423 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3424
039454a8
AA		 3425 /* Generate RSS hash based on packet types, TCP/UDP
3426 * port numbers and/or IPv4/v6 src and dst addresses
3427 */
f96a8a0b
CW		 3428 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3429 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3430 E1000_MRQC_RSS_FIELD_IPV6 |
3431 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3432 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3433
039454a8
AA		 3434 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3435 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3436 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3437 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3438
06cf2666
AD		 3439 /* If VMDq is enabled then we set the appropriate mode for that, else
3440 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3441 * if we are only using one queue
3442 */
06cf2666
AD		 3443 if (adapter->vfs_allocated_count) {
3444 if (hw->mac.type > e1000_82575) {
3445 /* Set the default pool for the PF's first queue */
3446 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3447
06cf2666
AD		 3448 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3449 E1000_VT_CTL_DISABLE_DEF_POOL);
3450 vtctl |= adapter->vfs_allocated_count <<
3451 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3452 wr32(E1000_VT_CTL, vtctl);
3453 }
a99955fc 3454 if (adapter->rss_queues > 1)
f96a8a0b 3455 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3456 else
f96a8a0b 3457 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3458 } else {
f96a8a0b
CW		 3459 if (hw->mac.type != e1000_i211)
3460 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3461 }
3462 igb_vmm_control(adapter);
3463
06cf2666
AD		 3464 wr32(E1000_MRQC, mrqc);
3465}
3466
9d5c8243 3467/**
b980ac18
JK		 3468 * igb_setup_rctl - configure the receive control registers
3469 * @adapter: Board private structure
9d5c8243 3470 **/
d7ee5b3a 3471void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3472{
3473 struct e1000_hw *hw = &adapter->hw;
3474 u32 rctl;
9d5c8243
AK		 3475
3476 rctl = rd32(E1000_RCTL);
3477
3478 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3479 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3480
69d728ba 3481 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3482 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3483
b980ac18 3484 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3485 * redirection as it did with e1000. Newer features require
3486 * that the HW strips the CRC.
73cd78f1 3487 */
87cb7e8c 3488 rctl |= E1000_RCTL_SECRC;
9d5c8243 3489
559e9c49 3490 /* disable store bad packets and clear size bits. */
ec54d7d6 3491 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3492
6ec43fe6
AD		 3493 /* enable LPE to prevent packets larger than max_frame_size */
3494 rctl |= E1000_RCTL_LPE;
9d5c8243 3495
952f72a8
AD		 3496 /* disable queue 0 to prevent tail write w/o re-config */
3497 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3498
e1739522
AD		 3499 /* Attention!!! For SR-IOV PF driver operations you must enable
3500 * queue drop for all VF and PF queues to prevent head of line blocking
3501 * if an un-trusted VF does not provide descriptors to hardware.
3502 */
3503 if (adapter->vfs_allocated_count) {
e1739522
AD		 3504 /* set all queue drop enable bits */
3505 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3506 }
3507
89eaefb6
BG		 3508 /* This is useful for sniffing bad packets. */
3509 if (adapter->netdev->features & NETIF_F_RXALL) {
3510 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3511 * in e1000e_set_rx_mode
3512 */
89eaefb6
BG		 3513 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3514 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3515 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3516
3517 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3518 E1000_RCTL_DPF | /* Allow filtered pause */
3519 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3520 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3521 * and that breaks VLANs.
3522 */
3523 }
3524
9d5c8243
AK		 3525 wr32(E1000_RCTL, rctl);
3526}
3527
7d5753f0 3528static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3529 int vfn)
7d5753f0
AD		 3530{
3531 struct e1000_hw *hw = &adapter->hw;
3532 u32 vmolr;
3533
3534 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3535 * increase the size to support vlan tags
3536 */
7d5753f0
AD		 3537 if (vfn < adapter->vfs_allocated_count &&
3538 adapter->vf_data[vfn].vlans_enabled)
3539 size += VLAN_TAG_SIZE;
3540
3541 vmolr = rd32(E1000_VMOLR(vfn));
3542 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3543 vmolr |= size | E1000_VMOLR_LPE;
3544 wr32(E1000_VMOLR(vfn), vmolr);
3545
3546 return 0;
3547}
3548
e1739522 3549/**
b980ac18
JK		 3550 * igb_rlpml_set - set maximum receive packet size
3551 * @adapter: board private structure
e1739522 3552 *
b980ac18 3553 * Configure maximum receivable packet size.
e1739522
AD		 3554 **/
3555static void igb_rlpml_set(struct igb_adapter *adapter)
3556{
153285f9 3557 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3558 struct e1000_hw *hw = &adapter->hw;
3559 u16 pf_id = adapter->vfs_allocated_count;
3560
e1739522
AD		 3561 if (pf_id) {
3562 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3563 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3564 * to our max jumbo frame size, in case we need to enable
3565 * jumbo frames on one of the rings later.
3566 * This will not pass over-length frames into the default
3567 * queue because it's gated by the VMOLR.RLPML.
3568 */
7d5753f0 3569 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3570 }
3571
3572 wr32(E1000_RLPML, max_frame_size);
3573}
3574
8151d294
WM		 3575static inline void igb_set_vmolr(struct igb_adapter *adapter,
3576 int vfn, bool aupe)
7d5753f0
AD		 3577{
3578 struct e1000_hw *hw = &adapter->hw;
3579 u32 vmolr;
3580
b980ac18 3581 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3582 * we should exit and do nothing
3583 */
3584 if (hw->mac.type < e1000_82576)
3585 return;
3586
3587 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3588 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3589 if (hw->mac.type == e1000_i350) {
3590 u32 dvmolr;
3591
3592 dvmolr = rd32(E1000_DVMOLR(vfn));
3593 dvmolr |= E1000_DVMOLR_STRVLAN;
3594 wr32(E1000_DVMOLR(vfn), dvmolr);
3595 }
8151d294 3596 if (aupe)
b980ac18 3597 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3598 else
3599 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3600
3601 /* clear all bits that might not be set */
3602 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3603
a99955fc 3604 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3605 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3606 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3607 * multicast packets
3608 */
3609 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3610 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3611
3612 wr32(E1000_VMOLR(vfn), vmolr);
3613}
3614
85b430b4 3615/**
b980ac18
JK		 3616 * igb_configure_rx_ring - Configure a receive ring after Reset
3617 * @adapter: board private structure
3618 * @ring: receive ring to be configured
85b430b4 3619 *
b980ac18 3620 * Configure the Rx unit of the MAC after a reset.
85b430b4 3621 **/
d7ee5b3a 3622void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3623 struct igb_ring *ring)
85b430b4
AD		 3624{
3625 struct e1000_hw *hw = &adapter->hw;
3626 u64 rdba = ring->dma;
3627 int reg_idx = ring->reg_idx;
a74420e0 3628 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3629
3630 /* disable the queue */
a74420e0 3631 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3632
3633 /* Set DMA base address registers */
3634 wr32(E1000_RDBAL(reg_idx),
3635 rdba & 0x00000000ffffffffULL);
3636 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3637 wr32(E1000_RDLEN(reg_idx),
b980ac18 3638 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3639
3640 /* initialize head and tail */
fce99e34 3641 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3642 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3643 writel(0, ring->tail);
85b430b4 3644
952f72a8 3645 /* set descriptor configuration */
44390ca6 3646 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3647 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3648 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3649 if (hw->mac.type >= e1000_82580)
757b77e2 3650 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3651 /* Only set Drop Enable if we are supporting multiple queues */
3652 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3653 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3654
3655 wr32(E1000_SRRCTL(reg_idx), srrctl);
3656
7d5753f0 3657 /* set filtering for VMDQ pools */
8151d294 3658 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3659
85b430b4
AD		 3660 rxdctl |= IGB_RX_PTHRESH;
3661 rxdctl |= IGB_RX_HTHRESH << 8;
3662 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3663
3664 /* enable receive descriptor fetching */
3665 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3666 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3667}
3668
9d5c8243 3669/**
b980ac18
JK		 3670 * igb_configure_rx - Configure receive Unit after Reset
3671 * @adapter: board private structure
9d5c8243 3672 *
b980ac18 3673 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3674 **/
3675static void igb_configure_rx(struct igb_adapter *adapter)
3676{
9107584e 3677 int i;
9d5c8243 3678
68d480c4
AD		 3679 /* set UTA to appropriate mode */
3680 igb_set_uta(adapter);
3681
26ad9178
AD		 3682 /* set the correct pool for the PF default MAC address in entry 0 */
3683 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3684 adapter->vfs_allocated_count);
26ad9178 3685
06cf2666 3686 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3687 * the Base and Length of the Rx Descriptor Ring
3688 */
f9d40f6a
AD		 3689 for (i = 0; i < adapter->num_rx_queues; i++)
3690 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3691}
3692
3693/**
b980ac18
JK		 3694 * igb_free_tx_resources - Free Tx Resources per Queue
3695 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3696 *
b980ac18 3697 * Free all transmit software resources
9d5c8243 3698 **/
68fd9910 3699void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3700{
3b644cf6 3701 igb_clean_tx_ring(tx_ring);
9d5c8243 3702
06034649
AD		 3703 vfree(tx_ring->tx_buffer_info);
3704 tx_ring->tx_buffer_info = NULL;
9d5c8243 3705
439705e1
AD		 3706 /* if not set, then don't free */
3707 if (!tx_ring->desc)
3708 return;
3709
59d71989
AD		 3710 dma_free_coherent(tx_ring->dev, tx_ring->size,
3711 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3712
3713 tx_ring->desc = NULL;
3714}
3715
3716/**
b980ac18
JK		 3717 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3718 * @adapter: board private structure
9d5c8243 3719 *
b980ac18 3720 * Free all transmit software resources
9d5c8243
AK		 3721 **/
3722static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3723{
3724 int i;
3725
3726 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3727 if (adapter->tx_ring[i])
3728 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3729}
3730
ebe42d16
AD		 3731void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3732 struct igb_tx_buffer *tx_buffer)
3733{
3734 if (tx_buffer->skb) {
3735 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3736 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3737 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3738 dma_unmap_addr(tx_buffer, dma),
3739 dma_unmap_len(tx_buffer, len),
ebe42d16 3740 DMA_TO_DEVICE);
c9f14bf3 3741 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3742 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3743 dma_unmap_addr(tx_buffer, dma),
3744 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3745 DMA_TO_DEVICE);
3746 }
3747 tx_buffer->next_to_watch = NULL;
3748 tx_buffer->skb = NULL;
c9f14bf3 3749 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3750 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3751}
3752
3753/**
b980ac18
JK		 3754 * igb_clean_tx_ring - Free Tx Buffers
3755 * @tx_ring: ring to be cleaned
9d5c8243 3756 **/
3b644cf6 3757static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3758{
06034649 3759 struct igb_tx_buffer *buffer_info;
9d5c8243 3760 unsigned long size;
6ad4edfc 3761 u16 i;
9d5c8243 3762
06034649 3763 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3764 return;
3765 /* Free all the Tx ring sk_buffs */
3766
3767 for (i = 0; i < tx_ring->count; i++) {
06034649 3768 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3769 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3770 }
3771
dad8a3b3
JF		 3772 netdev_tx_reset_queue(txring_txq(tx_ring));
3773
06034649
AD		 3774 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3775 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3776
3777 /* Zero out the descriptor ring */
9d5c8243
AK		 3778 memset(tx_ring->desc, 0, tx_ring->size);
3779
3780 tx_ring->next_to_use = 0;
3781 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3782}
3783
3784/**
b980ac18
JK		 3785 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3786 * @adapter: board private structure
9d5c8243
AK		 3787 **/
3788static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3789{
3790 int i;
3791
3792 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3793 if (adapter->tx_ring[i])
3794 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3795}
3796
3797/**
b980ac18
JK		 3798 * igb_free_rx_resources - Free Rx Resources
3799 * @rx_ring: ring to clean the resources from
9d5c8243 3800 *
b980ac18 3801 * Free all receive software resources
9d5c8243 3802 **/
68fd9910 3803void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3804{
3b644cf6 3805 igb_clean_rx_ring(rx_ring);
9d5c8243 3806
06034649
AD		 3807 vfree(rx_ring->rx_buffer_info);
3808 rx_ring->rx_buffer_info = NULL;
9d5c8243 3809
439705e1
AD		 3810 /* if not set, then don't free */
3811 if (!rx_ring->desc)
3812 return;
3813
59d71989
AD		 3814 dma_free_coherent(rx_ring->dev, rx_ring->size,
3815 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3816
3817 rx_ring->desc = NULL;
3818}
3819
3820/**
b980ac18
JK		 3821 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3822 * @adapter: board private structure
9d5c8243 3823 *
b980ac18 3824 * Free all receive software resources
9d5c8243
AK		 3825 **/
3826static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3827{
3828 int i;
3829
3830 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3831 if (adapter->rx_ring[i])
3832 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3833}
3834
3835/**
b980ac18
JK		 3836 * igb_clean_rx_ring - Free Rx Buffers per Queue
3837 * @rx_ring: ring to free buffers from
9d5c8243 3838 **/
3b644cf6 3839static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3840{
9d5c8243 3841 unsigned long size;
c023cd88 3842 u16 i;
9d5c8243 3843
1a1c225b
AD		 3844 if (rx_ring->skb)
3845 dev_kfree_skb(rx_ring->skb);
3846 rx_ring->skb = NULL;
3847
06034649 3848 if (!rx_ring->rx_buffer_info)
9d5c8243 3849 return;
439705e1 3850
9d5c8243
AK		 3851 /* Free all the Rx ring sk_buffs */
3852 for (i = 0; i < rx_ring->count; i++) {
06034649 3853 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3854
cbc8e55f
AD		 3855 if (!buffer_info->page)
3856 continue;
3857
3858 dma_unmap_page(rx_ring->dev,
3859 buffer_info->dma,
3860 PAGE_SIZE,
3861 DMA_FROM_DEVICE);
3862 __free_page(buffer_info->page);
3863
1a1c225b 3864 buffer_info->page = NULL;
9d5c8243
AK		 3865 }
3866
06034649
AD		 3867 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3868 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3869
3870 /* Zero out the descriptor ring */
3871 memset(rx_ring->desc, 0, rx_ring->size);
3872
cbc8e55f 3873 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3874 rx_ring->next_to_clean = 0;
3875 rx_ring->next_to_use = 0;
9d5c8243
AK		 3876}
3877
3878/**
b980ac18
JK		 3879 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3880 * @adapter: board private structure
9d5c8243
AK		 3881 **/
3882static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3883{
3884 int i;
3885
3886 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3887 if (adapter->rx_ring[i])
3888 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3889}
3890
3891/**
b980ac18
JK		 3892 * igb_set_mac - Change the Ethernet Address of the NIC
3893 * @netdev: network interface device structure
3894 * @p: pointer to an address structure
9d5c8243 3895 *
b980ac18 3896 * Returns 0 on success, negative on failure
9d5c8243
AK		 3897 **/
3898static int igb_set_mac(struct net_device *netdev, void *p)
3899{
3900 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3901 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3902 struct sockaddr *addr = p;
3903
3904 if (!is_valid_ether_addr(addr->sa_data))
3905 return -EADDRNOTAVAIL;
3906
3907 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3908 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3909
26ad9178
AD		 3910 /* set the correct pool for the new PF MAC address in entry 0 */
3911 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3912 adapter->vfs_allocated_count);
e1739522 3913
9d5c8243
AK		 3914 return 0;
3915}
3916
3917/**
b980ac18
JK		 3918 * igb_write_mc_addr_list - write multicast addresses to MTA
3919 * @netdev: network interface device structure
9d5c8243 3920 *
b980ac18
JK		 3921 * Writes multicast address list to the MTA hash table.
3922 * Returns: -ENOMEM on failure
3923 * 0 on no addresses written
3924 * X on writing X addresses to MTA
9d5c8243 3925 **/
68d480c4 3926static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3927{
3928 struct igb_adapter *adapter = netdev_priv(netdev);
3929 struct e1000_hw *hw = &adapter->hw;
22bedad3 3930 struct netdev_hw_addr *ha;
68d480c4 3931 u8 *mta_list;
9d5c8243
AK		 3932 int i;
3933
4cd24eaf 3934 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3935 /* nothing to program, so clear mc list */
3936 igb_update_mc_addr_list(hw, NULL, 0);
3937 igb_restore_vf_multicasts(adapter);
3938 return 0;
3939 }
9d5c8243 3940
4cd24eaf 3941 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3942 if (!mta_list)
3943 return -ENOMEM;
ff41f8dc 3944
68d480c4 3945 /* The shared function expects a packed array of only addresses. */
48e2f183 3946 i = 0;
22bedad3
JP		 3947 netdev_for_each_mc_addr(ha, netdev)
3948 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3949
68d480c4
AD		 3950 igb_update_mc_addr_list(hw, mta_list, i);
3951 kfree(mta_list);
3952
4cd24eaf 3953 return netdev_mc_count(netdev);
68d480c4
AD		 3954}
3955
3956/**
b980ac18
JK		 3957 * igb_write_uc_addr_list - write unicast addresses to RAR table
3958 * @netdev: network interface device structure
68d480c4 3959 *
b980ac18
JK		 3960 * Writes unicast address list to the RAR table.
3961 * Returns: -ENOMEM on failure/insufficient address space
3962 * 0 on no addresses written
3963 * X on writing X addresses to the RAR table
68d480c4
AD		 3964 **/
3965static int igb_write_uc_addr_list(struct net_device *netdev)
3966{
3967 struct igb_adapter *adapter = netdev_priv(netdev);
3968 struct e1000_hw *hw = &adapter->hw;
3969 unsigned int vfn = adapter->vfs_allocated_count;
3970 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3971 int count = 0;
3972
3973 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3974 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3975 return -ENOMEM;
9d5c8243 3976
32e7bfc4 3977 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3978 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3979
3980 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3981 if (!rar_entries)
3982 break;
26ad9178 3983 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3984 rar_entries--,
3985 vfn);
68d480c4 3986 count++;
ff41f8dc
AD		 3987 }
3988 }
3989 /* write the addresses in reverse order to avoid write combining */
3990 for (; rar_entries > 0 ; rar_entries--) {
3991 wr32(E1000_RAH(rar_entries), 0);
3992 wr32(E1000_RAL(rar_entries), 0);
3993 }
3994 wrfl();
3995
68d480c4
AD		 3996 return count;
3997}
3998
3999/**
b980ac18
JK		 4000 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4001 * @netdev: network interface device structure
68d480c4 4002 *
b980ac18
JK		 4003 * The set_rx_mode entry point is called whenever the unicast or multicast
4004 * address lists or the network interface flags are updated. This routine is
4005 * responsible for configuring the hardware for proper unicast, multicast,
4006 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4007 **/
4008static void igb_set_rx_mode(struct net_device *netdev)
4009{
4010 struct igb_adapter *adapter = netdev_priv(netdev);
4011 struct e1000_hw *hw = &adapter->hw;
4012 unsigned int vfn = adapter->vfs_allocated_count;
4013 u32 rctl, vmolr = 0;
4014 int count;
4015
4016 /* Check for Promiscuous and All Multicast modes */
4017 rctl = rd32(E1000_RCTL);
4018
4019 /* clear the effected bits */
4020 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4021
4022 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4023 /* retain VLAN HW filtering if in VT mode */
7e44892c 4024 if (adapter->vfs_allocated_count)
6f3dc319 4025 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4026 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4027 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4028 } else {
4029 if (netdev->flags & IFF_ALLMULTI) {
4030 rctl |= E1000_RCTL_MPE;
4031 vmolr |= E1000_VMOLR_MPME;
4032 } else {
b980ac18 4033 /* Write addresses to the MTA, if the attempt fails
25985edc 4034 * then we should just turn on promiscuous mode so
68d480c4
AD		 4035 * that we can at least receive multicast traffic
4036 */
4037 count = igb_write_mc_addr_list(netdev);
4038 if (count < 0) {
4039 rctl |= E1000_RCTL_MPE;
4040 vmolr |= E1000_VMOLR_MPME;
4041 } else if (count) {
4042 vmolr |= E1000_VMOLR_ROMPE;
4043 }
4044 }
b980ac18 4045 /* Write addresses to available RAR registers, if there is not
68d480c4 4046 * sufficient space to store all the addresses then enable
25985edc 4047 * unicast promiscuous mode
68d480c4
AD		 4048 */
4049 count = igb_write_uc_addr_list(netdev);
4050 if (count < 0) {
4051 rctl |= E1000_RCTL_UPE;
4052 vmolr |= E1000_VMOLR_ROPE;
4053 }
4054 rctl |= E1000_RCTL_VFE;
28fc06f5 4055 }
68d480c4 4056 wr32(E1000_RCTL, rctl);
28fc06f5 4057
b980ac18 4058 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4059 * the VMOLR to enable the appropriate modes. Without this workaround
4060 * we will have issues with VLAN tag stripping not being done for frames
4061 * that are only arriving because we are the default pool
4062 */
f96a8a0b 4063 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4064 return;
9d5c8243 4065
68d480c4 4066 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4067 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4068 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4069 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4070}
4071
13800469
GR		 4072static void igb_check_wvbr(struct igb_adapter *adapter)
4073{
4074 struct e1000_hw *hw = &adapter->hw;
4075 u32 wvbr = 0;
4076
4077 switch (hw->mac.type) {
4078 case e1000_82576:
4079 case e1000_i350:
81ad807b
CW		 4080 wvbr = rd32(E1000_WVBR);
4081 if (!wvbr)
13800469
GR		 4082 return;
4083 break;
4084 default:
4085 break;
4086 }
4087
4088 adapter->wvbr |= wvbr;
4089}
4090
4091#define IGB_STAGGERED_QUEUE_OFFSET 8
4092
4093static void igb_spoof_check(struct igb_adapter *adapter)
4094{
4095 int j;
4096
4097 if (!adapter->wvbr)
4098 return;
4099
9005df38 4100 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4101 if (adapter->wvbr & (1 << j) ||
4102 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4103 dev_warn(&adapter->pdev->dev,
4104 "Spoof event(s) detected on VF %d\n", j);
4105 adapter->wvbr &=
4106 ~((1 << j) |
4107 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4108 }
4109 }
4110}
4111
9d5c8243 4112/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4113 * the phy
4114 */
9d5c8243
AK		 4115static void igb_update_phy_info(unsigned long data)
4116{
4117 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4118 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4119}
4120
4d6b725e 4121/**
b980ac18
JK		 4122 * igb_has_link - check shared code for link and determine up/down
4123 * @adapter: pointer to driver private info
4d6b725e 4124 **/
3145535a 4125bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4126{
4127 struct e1000_hw *hw = &adapter->hw;
4128 bool link_active = false;
4d6b725e
AD		 4129
4130 /* get_link_status is set on LSC (link status) interrupt or
4131 * rx sequence error interrupt. get_link_status will stay
4132 * false until the e1000_check_for_link establishes link
4133 * for copper adapters ONLY
4134 */
4135 switch (hw->phy.media_type) {
4136 case e1000_media_type_copper:
e5c3370f
AA		 4137 if (!hw->mac.get_link_status)
4138 return true;
4d6b725e 4139 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4140 hw->mac.ops.check_for_link(hw);
4141 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4142 break;
4143 default:
4144 case e1000_media_type_unknown:
4145 break;
4146 }
4147
aa9b8cc4
AA		 4148 if (((hw->mac.type == e1000_i210) ||
4149 (hw->mac.type == e1000_i211)) &&
4150 (hw->phy.id == I210_I_PHY_ID)) {
4151 if (!netif_carrier_ok(adapter->netdev)) {
4152 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4153 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4154 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4155 adapter->link_check_timeout = jiffies;
4156 }
4157 }
4158
4d6b725e
AD		 4159 return link_active;
4160}
4161
563988dc
SA		 4162static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4163{
4164 bool ret = false;
4165 u32 ctrl_ext, thstat;
4166
f96a8a0b 4167 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4168 if (hw->mac.type == e1000_i350) {
4169 thstat = rd32(E1000_THSTAT);
4170 ctrl_ext = rd32(E1000_CTRL_EXT);
4171
4172 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4173 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4174 ret = !!(thstat & event);
563988dc
SA		 4175 }
4176
4177 return ret;
4178}
4179
1516f0a6
CW		 4180/**
4181 * igb_check_lvmmc - check for malformed packets received
4182 * and indicated in LVMMC register
4183 * @adapter: pointer to adapter
4184 **/
4185static void igb_check_lvmmc(struct igb_adapter *adapter)
4186{
4187 struct e1000_hw *hw = &adapter->hw;
4188 u32 lvmmc;
4189
4190 lvmmc = rd32(E1000_LVMMC);
4191 if (lvmmc) {
4192 if (unlikely(net_ratelimit())) {
4193 netdev_warn(adapter->netdev,
4194 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4195 lvmmc);
4196 }
4197 }
4198}
4199
9d5c8243 4200/**
b980ac18
JK		 4201 * igb_watchdog - Timer Call-back
4202 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4203 **/
4204static void igb_watchdog(unsigned long data)
4205{
4206 struct igb_adapter *adapter = (struct igb_adapter *)data;
4207 /* Do the rest outside of interrupt context */
4208 schedule_work(&adapter->watchdog_task);
4209}
4210
4211static void igb_watchdog_task(struct work_struct *work)
4212{
4213 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4214 struct igb_adapter,
4215 watchdog_task);
9d5c8243 4216 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4217 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4218 struct net_device *netdev = adapter->netdev;
563988dc 4219 u32 link;
7a6ea550 4220 int i;
56cec249 4221 u32 connsw;
9d5c8243 4222
4d6b725e 4223 link = igb_has_link(adapter);
aa9b8cc4
AA		 4224
4225 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4226 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4227 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4228 else
4229 link = false;
4230 }
4231
56cec249
CW		 4232 /* Force link down if we have fiber to swap to */
4233 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4234 if (hw->phy.media_type == e1000_media_type_copper) {
4235 connsw = rd32(E1000_CONNSW);
4236 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4237 link = 0;
4238 }
4239 }
9d5c8243 4240 if (link) {
2bdfc4e2
CW		 4241 /* Perform a reset if the media type changed. */
4242 if (hw->dev_spec._82575.media_changed) {
4243 hw->dev_spec._82575.media_changed = false;
4244 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4245 igb_reset(adapter);
4246 }
749ab2cd
YZ		 4247 /* Cancel scheduled suspend requests. */
4248 pm_runtime_resume(netdev->dev.parent);
4249
9d5c8243
AK		 4250 if (!netif_carrier_ok(netdev)) {
4251 u32 ctrl;
9005df38 4252
330a6d6a 4253 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4254 &adapter->link_speed,
4255 &adapter->link_duplex);
9d5c8243
AK		 4256
4257 ctrl = rd32(E1000_CTRL);
527d47c1 4258 /* Links status message must follow this format */
c75c4edf
CW		 4259 netdev_info(netdev,
4260 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4261 netdev->name,
4262 adapter->link_speed,
4263 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4264 "Full" : "Half",
4265 (ctrl & E1000_CTRL_TFCE) &&
4266 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4267 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4268 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4269
f4c01e96
CW		 4270 /* disable EEE if enabled */
4271 if ((adapter->flags & IGB_FLAG_EEE) &&
4272 (adapter->link_duplex == HALF_DUPLEX)) {
4273 dev_info(&adapter->pdev->dev,
4274 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4275 adapter->hw.dev_spec._82575.eee_disable = true;
4276 adapter->flags &= ~IGB_FLAG_EEE;
4277 }
4278
c0ba4778
KS		 4279 /* check if SmartSpeed worked */
4280 igb_check_downshift(hw);
4281 if (phy->speed_downgraded)
4282 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4283
563988dc 4284 /* check for thermal sensor event */
876d2d6f 4285 if (igb_thermal_sensor_event(hw,
d34a15ab 4286 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4287 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4288
d07f3e37 4289 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4290 adapter->tx_timeout_factor = 1;
4291 switch (adapter->link_speed) {
4292 case SPEED_10:
9d5c8243
AK		 4293 adapter->tx_timeout_factor = 14;
4294 break;
4295 case SPEED_100:
9d5c8243
AK		 4296 /* maybe add some timeout factor ? */
4297 break;
4298 }
4299
4300 netif_carrier_on(netdev);
9d5c8243 4301
4ae196df 4302 igb_ping_all_vfs(adapter);
17dc566c 4303 igb_check_vf_rate_limit(adapter);
4ae196df 4304
4b1a9877 4305 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4306 if (!test_bit(__IGB_DOWN, &adapter->state))
4307 mod_timer(&adapter->phy_info_timer,
4308 round_jiffies(jiffies + 2 * HZ));
4309 }
4310 } else {
4311 if (netif_carrier_ok(netdev)) {
4312 adapter->link_speed = 0;
4313 adapter->link_duplex = 0;
563988dc
SA		 4314
4315 /* check for thermal sensor event */
876d2d6f
JK		 4316 if (igb_thermal_sensor_event(hw,
4317 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4318 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4319 }
563988dc 4320
527d47c1 4321 /* Links status message must follow this format */
c75c4edf 4322 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4323 netdev->name);
9d5c8243 4324 netif_carrier_off(netdev);
4b1a9877 4325
4ae196df
AD		 4326 igb_ping_all_vfs(adapter);
4327
4b1a9877 4328 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4329 if (!test_bit(__IGB_DOWN, &adapter->state))
4330 mod_timer(&adapter->phy_info_timer,
4331 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4332
56cec249
CW		 4333 /* link is down, time to check for alternate media */
4334 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4335 igb_check_swap_media(adapter);
4336 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4337 schedule_work(&adapter->reset_task);
4338 /* return immediately */
4339 return;
4340 }
4341 }
749ab2cd
YZ		 4342 pm_schedule_suspend(netdev->dev.parent,
4343 MSEC_PER_SEC * 5);
56cec249
CW		 4344
4345 /* also check for alternate media here */
4346 } else if (!netif_carrier_ok(netdev) &&
4347 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4348 igb_check_swap_media(adapter);
4349 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4350 schedule_work(&adapter->reset_task);
4351 /* return immediately */
4352 return;
4353 }
9d5c8243
AK		 4354 }
4355 }
4356
12dcd86b
ED		 4357 spin_lock(&adapter->stats64_lock);
4358 igb_update_stats(adapter, &adapter->stats64);
4359 spin_unlock(&adapter->stats64_lock);
9d5c8243 4360
dbabb065 4361 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4362 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4363 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4364 /* We've lost link, so the controller stops DMA,
4365 * but we've got queued Tx work that's never going
4366 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4367 * (Do the reset outside of interrupt context).
4368 */
dbabb065
AD		 4369 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4370 adapter->tx_timeout_count++;
4371 schedule_work(&adapter->reset_task);
4372 /* return immediately since reset is imminent */
4373 return;
4374 }
9d5c8243 4375 }
9d5c8243 4376
dbabb065 4377 /* Force detection of hung controller every watchdog period */
6d095fa8 4378 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4379 }
f7ba205e 4380
b980ac18 4381 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4382 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4383 u32 eics = 0;
9005df38 4384
0d1ae7f4
AD		 4385 for (i = 0; i < adapter->num_q_vectors; i++)
4386 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4387 wr32(E1000_EICS, eics);
4388 } else {
4389 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4390 }
9d5c8243 4391
13800469 4392 igb_spoof_check(adapter);
fc580751 4393 igb_ptp_rx_hang(adapter);
13800469 4394
1516f0a6
CW		 4395 /* Check LVMMC register on i350/i354 only */
4396 if ((adapter->hw.mac.type == e1000_i350) ||
4397 (adapter->hw.mac.type == e1000_i354))
4398 igb_check_lvmmc(adapter);
4399
9d5c8243 4400 /* Reset the timer */
aa9b8cc4
AA		 4401 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4402 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4403 mod_timer(&adapter->watchdog_timer,
4404 round_jiffies(jiffies + HZ));
4405 else
4406 mod_timer(&adapter->watchdog_timer,
4407 round_jiffies(jiffies + 2 * HZ));
4408 }
9d5c8243
AK		 4409}
4410
4411enum latency_range {
4412 lowest_latency = 0,
4413 low_latency = 1,
4414 bulk_latency = 2,
4415 latency_invalid = 255
4416};
4417
6eb5a7f1 4418/**
b980ac18
JK		 4419 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4420 * @q_vector: pointer to q_vector
6eb5a7f1 4421 *
b980ac18
JK		 4422 * Stores a new ITR value based on strictly on packet size. This
4423 * algorithm is less sophisticated than that used in igb_update_itr,
4424 * due to the difficulty of synchronizing statistics across multiple
4425 * receive rings. The divisors and thresholds used by this function
4426 * were determined based on theoretical maximum wire speed and testing
4427 * data, in order to minimize response time while increasing bulk
4428 * throughput.
406d4965 4429 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4430 * NOTE: This function is called only when operating in a multiqueue
4431 * receive environment.
6eb5a7f1 4432 **/
047e0030 4433static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4434{
047e0030 4435 int new_val = q_vector->itr_val;
6eb5a7f1 4436 int avg_wire_size = 0;
047e0030 4437 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4438 unsigned int packets;
9d5c8243 4439
6eb5a7f1
AD		 4440 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4441 * ints/sec - ITR timer value of 120 ticks.
4442 */
4443 if (adapter->link_speed != SPEED_1000) {
0ba82994 4444 new_val = IGB_4K_ITR;
6eb5a7f1 4445 goto set_itr_val;
9d5c8243 4446 }
047e0030 4447
0ba82994
AD		 4448 packets = q_vector->rx.total_packets;
4449 if (packets)
4450 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4451
0ba82994
AD		 4452 packets = q_vector->tx.total_packets;
4453 if (packets)
4454 avg_wire_size = max_t(u32, avg_wire_size,
4455 q_vector->tx.total_bytes / packets);
047e0030
AD		 4456
4457 /* if avg_wire_size isn't set no work was done */
4458 if (!avg_wire_size)
4459 goto clear_counts;
9d5c8243 4460
6eb5a7f1
AD		 4461 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4462 avg_wire_size += 24;
4463
4464 /* Don't starve jumbo frames */
4465 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4466
6eb5a7f1
AD		 4467 /* Give a little boost to mid-size frames */
4468 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4469 new_val = avg_wire_size / 3;
4470 else
4471 new_val = avg_wire_size / 2;
9d5c8243 4472
0ba82994
AD		 4473 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4474 if (new_val < IGB_20K_ITR &&
4475 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4476 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4477 new_val = IGB_20K_ITR;
abe1c363 4478
6eb5a7f1 4479set_itr_val:
047e0030
AD		 4480 if (new_val != q_vector->itr_val) {
4481 q_vector->itr_val = new_val;
4482 q_vector->set_itr = 1;
9d5c8243 4483 }
6eb5a7f1 4484clear_counts:
0ba82994
AD		 4485 q_vector->rx.total_bytes = 0;
4486 q_vector->rx.total_packets = 0;
4487 q_vector->tx.total_bytes = 0;
4488 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4489}
4490
4491/**
b980ac18
JK		 4492 * igb_update_itr - update the dynamic ITR value based on statistics
4493 * @q_vector: pointer to q_vector
4494 * @ring_container: ring info to update the itr for
4495 *
4496 * Stores a new ITR value based on packets and byte
4497 * counts during the last interrupt. The advantage of per interrupt
4498 * computation is faster updates and more accurate ITR for the current
4499 * traffic pattern. Constants in this function were computed
4500 * based on theoretical maximum wire speed and thresholds were set based
4501 * on testing data as well as attempting to minimize response time
4502 * while increasing bulk throughput.
406d4965 4503 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4504 * NOTE: These calculations are only valid when operating in a single-
4505 * queue environment.
9d5c8243 4506 **/
0ba82994
AD		 4507static void igb_update_itr(struct igb_q_vector *q_vector,
4508 struct igb_ring_container *ring_container)
9d5c8243 4509{
0ba82994
AD		 4510 unsigned int packets = ring_container->total_packets;
4511 unsigned int bytes = ring_container->total_bytes;
4512 u8 itrval = ring_container->itr;
9d5c8243 4513
0ba82994 4514 /* no packets, exit with status unchanged */
9d5c8243 4515 if (packets == 0)
0ba82994 4516 return;
9d5c8243 4517
0ba82994 4518 switch (itrval) {
9d5c8243
AK		 4519 case lowest_latency:
4520 /* handle TSO and jumbo frames */
4521 if (bytes/packets > 8000)
0ba82994 4522 itrval = bulk_latency;
9d5c8243 4523 else if ((packets < 5) && (bytes > 512))
0ba82994 4524 itrval = low_latency;
9d5c8243
AK		 4525 break;
4526 case low_latency: /* 50 usec aka 20000 ints/s */
4527 if (bytes > 10000) {
4528 /* this if handles the TSO accounting */
d34a15ab 4529 if (bytes/packets > 8000)
0ba82994 4530 itrval = bulk_latency;
d34a15ab 4531 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4532 itrval = bulk_latency;
d34a15ab 4533 else if ((packets > 35))
0ba82994 4534 itrval = lowest_latency;
9d5c8243 4535 } else if (bytes/packets > 2000) {
0ba82994 4536 itrval = bulk_latency;
9d5c8243 4537 } else if (packets <= 2 && bytes < 512) {
0ba82994 4538 itrval = lowest_latency;
9d5c8243
AK		 4539 }
4540 break;
4541 case bulk_latency: /* 250 usec aka 4000 ints/s */
4542 if (bytes > 25000) {
4543 if (packets > 35)
0ba82994 4544 itrval = low_latency;
1e5c3d21 4545 } else if (bytes < 1500) {
0ba82994 4546 itrval = low_latency;
9d5c8243
AK		 4547 }
4548 break;
4549 }
4550
0ba82994
AD		 4551 /* clear work counters since we have the values we need */
4552 ring_container->total_bytes = 0;
4553 ring_container->total_packets = 0;
4554
4555 /* write updated itr to ring container */
4556 ring_container->itr = itrval;
9d5c8243
AK		 4557}
4558
0ba82994 4559static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4560{
0ba82994 4561 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4562 u32 new_itr = q_vector->itr_val;
0ba82994 4563 u8 current_itr = 0;
9d5c8243
AK		 4564
4565 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4566 if (adapter->link_speed != SPEED_1000) {
4567 current_itr = 0;
0ba82994 4568 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4569 goto set_itr_now;
4570 }
4571
0ba82994
AD		 4572 igb_update_itr(q_vector, &q_vector->tx);
4573 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4574
0ba82994 4575 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4576
6eb5a7f1 4577 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4578 if (current_itr == lowest_latency &&
4579 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4580 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4581 current_itr = low_latency;
4582
9d5c8243
AK		 4583 switch (current_itr) {
4584 /* counts and packets in update_itr are dependent on these numbers */
4585 case lowest_latency:
0ba82994 4586 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4587 break;
4588 case low_latency:
0ba82994 4589 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4590 break;
4591 case bulk_latency:
0ba82994 4592 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4593 break;
4594 default:
4595 break;
4596 }
4597
4598set_itr_now:
047e0030 4599 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4600 /* this attempts to bias the interrupt rate towards Bulk
4601 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4602 * increasing
4603 */
047e0030 4604 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4605 max((new_itr * q_vector->itr_val) /
4606 (new_itr + (q_vector->itr_val >> 2)),
4607 new_itr) : new_itr;
9d5c8243
AK		 4608 /* Don't write the value here; it resets the adapter's
4609 * internal timer, and causes us to delay far longer than
4610 * we should between interrupts. Instead, we write the ITR
4611 * value at the beginning of the next interrupt so the timing
4612 * ends up being correct.
4613 */
047e0030
AD		 4614 q_vector->itr_val = new_itr;
4615 q_vector->set_itr = 1;
9d5c8243 4616 }
9d5c8243
AK		 4617}
4618
c50b52a0
SH		 4619static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4620 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4621{
4622 struct e1000_adv_tx_context_desc *context_desc;
4623 u16 i = tx_ring->next_to_use;
4624
4625 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4626
4627 i++;
4628 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4629
4630 /* set bits to identify this as an advanced context descriptor */
4631 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4632
4633 /* For 82575, context index must be unique per ring. */
866cff06 4634 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4635 mss_l4len_idx |= tx_ring->reg_idx << 4;
4636
4637 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4638 context_desc->seqnum_seed = 0;
4639 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4640 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4641}
4642
7af40ad9
AD		 4643static int igb_tso(struct igb_ring *tx_ring,
4644 struct igb_tx_buffer *first,
4645 u8 *hdr_len)
9d5c8243 4646{
7af40ad9 4647 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4648 u32 vlan_macip_lens, type_tucmd;
4649 u32 mss_l4len_idx, l4len;
06c14e5a 4650 int err;
7d13a7d0 4651
ed6aa105
AD		 4652 if (skb->ip_summed != CHECKSUM_PARTIAL)
4653 return 0;
4654
7d13a7d0
AD		 4655 if (!skb_is_gso(skb))
4656 return 0;
9d5c8243 4657
06c14e5a
FR		 4658 err = skb_cow_head(skb, 0);
4659 if (err < 0)
4660 return err;
9d5c8243 4661
7d13a7d0
AD		 4662 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4663 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4664
7c4d16ff 4665 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4666 struct iphdr *iph = ip_hdr(skb);
4667 iph->tot_len = 0;
4668 iph->check = 0;
4669 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4670 iph->daddr, 0,
4671 IPPROTO_TCP,
4672 0);
7d13a7d0 4673 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4674 first->tx_flags |= IGB_TX_FLAGS_TSO |
4675 IGB_TX_FLAGS_CSUM |
4676 IGB_TX_FLAGS_IPV4;
8e1e8a47 4677 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4678 ipv6_hdr(skb)->payload_len = 0;
4679 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4680 &ipv6_hdr(skb)->daddr,
4681 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4682 first->tx_flags |= IGB_TX_FLAGS_TSO |
4683 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4684 }
4685
7af40ad9 4686 /* compute header lengths */
7d13a7d0
AD		 4687 l4len = tcp_hdrlen(skb);
4688 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4689
7af40ad9
AD		 4690 /* update gso size and bytecount with header size */
4691 first->gso_segs = skb_shinfo(skb)->gso_segs;
4692 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4693
9d5c8243 4694 /* MSS L4LEN IDX */
7d13a7d0
AD		 4695 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4696 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4697
7d13a7d0
AD		 4698 /* VLAN MACLEN IPLEN */
4699 vlan_macip_lens = skb_network_header_len(skb);
4700 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4701 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4702
7d13a7d0 4703 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4704
7d13a7d0 4705 return 1;
9d5c8243
AK		 4706}
4707
7af40ad9 4708static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4709{
7af40ad9 4710 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4711 u32 vlan_macip_lens = 0;
4712 u32 mss_l4len_idx = 0;
4713 u32 type_tucmd = 0;
9d5c8243 4714
7d13a7d0 4715 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4716 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4717 return;
7d13a7d0
AD		 4718 } else {
4719 u8 l4_hdr = 0;
9005df38 4720
7af40ad9 4721 switch (first->protocol) {
7c4d16ff 4722 case htons(ETH_P_IP):
7d13a7d0
AD		 4723 vlan_macip_lens |= skb_network_header_len(skb);
4724 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4725 l4_hdr = ip_hdr(skb)->protocol;
4726 break;
7c4d16ff 4727 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4728 vlan_macip_lens |= skb_network_header_len(skb);
4729 l4_hdr = ipv6_hdr(skb)->nexthdr;
4730 break;
4731 default:
4732 if (unlikely(net_ratelimit())) {
4733 dev_warn(tx_ring->dev,
b980ac18
JK		 4734 "partial checksum but proto=%x!\n",
4735 first->protocol);
fa4a7ef3 4736 }
7d13a7d0
AD		 4737 break;
4738 }
fa4a7ef3 4739
7d13a7d0
AD		 4740 switch (l4_hdr) {
4741 case IPPROTO_TCP:
4742 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4743 mss_l4len_idx = tcp_hdrlen(skb) <<
4744 E1000_ADVTXD_L4LEN_SHIFT;
4745 break;
4746 case IPPROTO_SCTP:
4747 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4748 mss_l4len_idx = sizeof(struct sctphdr) <<
4749 E1000_ADVTXD_L4LEN_SHIFT;
4750 break;
4751 case IPPROTO_UDP:
4752 mss_l4len_idx = sizeof(struct udphdr) <<
4753 E1000_ADVTXD_L4LEN_SHIFT;
4754 break;
4755 default:
4756 if (unlikely(net_ratelimit())) {
4757 dev_warn(tx_ring->dev,
b980ac18
JK		 4758 "partial checksum but l4 proto=%x!\n",
4759 l4_hdr);
44b0cda3 4760 }
7d13a7d0 4761 break;
9d5c8243 4762 }
7af40ad9
AD		 4763
4764 /* update TX checksum flag */
4765 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4766 }
9d5c8243 4767
7d13a7d0 4768 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4769 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4770
7d13a7d0 4771 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4772}
4773
1d9daf45
AD		 4774#define IGB_SET_FLAG(_input, _flag, _result) \
4775 ((_flag <= _result) ? \
4776 ((u32)(_input & _flag) * (_result / _flag)) : \
4777 ((u32)(_input & _flag) / (_flag / _result)))
4778
4779static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4780{
4781 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4782 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4783 E1000_ADVTXD_DCMD_DEXT |
4784 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4785
4786 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4787 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4788 (E1000_ADVTXD_DCMD_VLE));
4789
4790 /* set segmentation bits for TSO */
4791 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4792 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4793
4794 /* set timestamp bit if present */
1d9daf45
AD		 4795 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4796 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4797
1d9daf45
AD		 4798 /* insert frame checksum */
4799 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4800
4801 return cmd_type;
4802}
4803
7af40ad9
AD		 4804static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4805 union e1000_adv_tx_desc *tx_desc,
4806 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4807{
4808 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4809
1d9daf45
AD		 4810 /* 82575 requires a unique index per ring */
4811 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4812 olinfo_status |= tx_ring->reg_idx << 4;
4813
4814 /* insert L4 checksum */
1d9daf45
AD		 4815 olinfo_status |= IGB_SET_FLAG(tx_flags,
4816 IGB_TX_FLAGS_CSUM,
4817 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4818
1d9daf45
AD		 4819 /* insert IPv4 checksum */
4820 olinfo_status |= IGB_SET_FLAG(tx_flags,
4821 IGB_TX_FLAGS_IPV4,
4822 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4823
7af40ad9 4824 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4825}
4826
6f19e12f
DM		 4827static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4828{
4829 struct net_device *netdev = tx_ring->netdev;
4830
4831 netif_stop_subqueue(netdev, tx_ring->queue_index);
4832
4833 /* Herbert's original patch had:
4834 * smp_mb__after_netif_stop_queue();
4835 * but since that doesn't exist yet, just open code it.
4836 */
4837 smp_mb();
4838
4839 /* We need to check again in a case another CPU has just
4840 * made room available.
4841 */
4842 if (igb_desc_unused(tx_ring) < size)
4843 return -EBUSY;
4844
4845 /* A reprieve! */
4846 netif_wake_subqueue(netdev, tx_ring->queue_index);
4847
4848 u64_stats_update_begin(&tx_ring->tx_syncp2);
4849 tx_ring->tx_stats.restart_queue2++;
4850 u64_stats_update_end(&tx_ring->tx_syncp2);
4851
4852 return 0;
4853}
4854
4855static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4856{
4857 if (igb_desc_unused(tx_ring) >= size)
4858 return 0;
4859 return __igb_maybe_stop_tx(tx_ring, size);
4860}
4861
7af40ad9
AD		 4862static void igb_tx_map(struct igb_ring *tx_ring,
4863 struct igb_tx_buffer *first,
ebe42d16 4864 const u8 hdr_len)
9d5c8243 4865{
7af40ad9 4866 struct sk_buff *skb = first->skb;
c9f14bf3 4867 struct igb_tx_buffer *tx_buffer;
ebe42d16 4868 union e1000_adv_tx_desc *tx_desc;
80d0759e 4869 struct skb_frag_struct *frag;
ebe42d16 4870 dma_addr_t dma;
80d0759e 4871 unsigned int data_len, size;
7af40ad9 4872 u32 tx_flags = first->tx_flags;
1d9daf45 4873 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4874 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4875
4876 tx_desc = IGB_TX_DESC(tx_ring, i);
4877
80d0759e
AD		 4878 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4879
4880 size = skb_headlen(skb);
4881 data_len = skb->data_len;
ebe42d16
AD		 4882
4883 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4884
80d0759e
AD		 4885 tx_buffer = first;
4886
4887 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4888 if (dma_mapping_error(tx_ring->dev, dma))
4889 goto dma_error;
4890
4891 /* record length, and DMA address */
4892 dma_unmap_len_set(tx_buffer, len, size);
4893 dma_unmap_addr_set(tx_buffer, dma, dma);
4894
4895 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4896
ebe42d16
AD		 4897 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4898 tx_desc->read.cmd_type_len =
1d9daf45 4899 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4900
4901 i++;
4902 tx_desc++;
4903 if (i == tx_ring->count) {
4904 tx_desc = IGB_TX_DESC(tx_ring, 0);
4905 i = 0;
4906 }
80d0759e 4907 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4908
4909 dma += IGB_MAX_DATA_PER_TXD;
4910 size -= IGB_MAX_DATA_PER_TXD;
4911
ebe42d16
AD		 4912 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4913 }
4914
4915 if (likely(!data_len))
4916 break;
2bbfebe2 4917
1d9daf45 4918 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4919
65689fef 4920 i++;
ebe42d16
AD		 4921 tx_desc++;
4922 if (i == tx_ring->count) {
4923 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4924 i = 0;
ebe42d16 4925 }
80d0759e 4926 tx_desc->read.olinfo_status = 0;
65689fef 4927
9e903e08 4928 size = skb_frag_size(frag);
ebe42d16
AD		 4929 data_len -= size;
4930
4931 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4932 size, DMA_TO_DEVICE);
6366ad33 4933
c9f14bf3 4934 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4935 }
4936
ebe42d16 4937 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4938 cmd_type |= size | IGB_TXD_DCMD;
4939 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4940
80d0759e
AD		 4941 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4942
8542db05
AD		 4943 /* set the timestamp */
4944 first->time_stamp = jiffies;
4945
b980ac18 4946 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4947 * are new descriptors to fetch. (Only applicable for weak-ordered
4948 * memory model archs, such as IA-64).
4949 *
4950 * We also need this memory barrier to make certain all of the
4951 * status bits have been updated before next_to_watch is written.
4952 */
4953 wmb();
4954
8542db05 4955 /* set next_to_watch value indicating a packet is present */
ebe42d16 4956 first->next_to_watch = tx_desc;
9d5c8243 4957
ebe42d16
AD		 4958 i++;
4959 if (i == tx_ring->count)
4960 i = 0;
6366ad33 4961
ebe42d16 4962 tx_ring->next_to_use = i;
6366ad33 4963
6f19e12f
DM		 4964 /* Make sure there is space in the ring for the next send. */
4965 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4966
4967 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 4968 writel(i, tx_ring->tail);
4969
4970 /* we need this if more than one processor can write to our tail
4971 * at a time, it synchronizes IO on IA64/Altix systems
4972 */
4973 mmiowb();
4974 }
ebe42d16
AD		 4975 return;
4976
4977dma_error:
4978 dev_err(tx_ring->dev, "TX DMA map failed\n");
4979
4980 /* clear dma mappings for failed tx_buffer_info map */
4981 for (;;) {
c9f14bf3
AD		 4982 tx_buffer = &tx_ring->tx_buffer_info[i];
4983 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4984 if (tx_buffer == first)
ebe42d16 4985 break;
a77ff709
NN		 4986 if (i == 0)
4987 i = tx_ring->count;
6366ad33 4988 i--;
6366ad33
AD		 4989 }
4990
9d5c8243 4991 tx_ring->next_to_use = i;
9d5c8243
AK		 4992}
4993
cd392f5c
AD		 4994netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4995 struct igb_ring *tx_ring)
9d5c8243 4996{
8542db05 4997 struct igb_tx_buffer *first;
ebe42d16 4998 int tso;
91d4ee33 4999 u32 tx_flags = 0;
2ee52ad4 5000 unsigned short f;
21ba6fe1 5001 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5002 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5003 u8 hdr_len = 0;
9d5c8243 5004
21ba6fe1
AD		 5005 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5006 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5007 * + 2 desc gap to keep tail from touching head,
9d5c8243 5008 * + 1 desc for context descriptor,
21ba6fe1
AD		 5009 * otherwise try next time
5010 */
2ee52ad4
AD		 5011 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5012 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5013
5014 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5015 /* this is a hard error */
9d5c8243
AK		 5016 return NETDEV_TX_BUSY;
5017 }
33af6bcc 5018
7af40ad9
AD		 5019 /* record the location of the first descriptor for this packet */
5020 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5021 first->skb = skb;
5022 first->bytecount = skb->len;
5023 first->gso_segs = 1;
5024
b646c22e
AD		 5025 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5026 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5027
ed4420a3
JK		 5028 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5029 &adapter->state)) {
b646c22e
AD		 5030 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5031 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5032
5033 adapter->ptp_tx_skb = skb_get(skb);
5034 adapter->ptp_tx_start = jiffies;
5035 if (adapter->hw.mac.type == e1000_82576)
5036 schedule_work(&adapter->ptp_tx_work);
5037 }
33af6bcc 5038 }
9d5c8243 5039
afc835d1
JK		 5040 skb_tx_timestamp(skb);
5041
df8a39de 5042 if (skb_vlan_tag_present(skb)) {
9d5c8243 5043 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5044 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5045 }
5046
7af40ad9
AD		 5047 /* record initial flags and protocol */
5048 first->tx_flags = tx_flags;
5049 first->protocol = protocol;
cdfd01fc 5050
7af40ad9
AD		 5051 tso = igb_tso(tx_ring, first, &hdr_len);
5052 if (tso < 0)
7d13a7d0 5053 goto out_drop;
7af40ad9
AD		 5054 else if (!tso)
5055 igb_tx_csum(tx_ring, first);
9d5c8243 5056
7af40ad9 5057 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5058
9d5c8243 5059 return NETDEV_TX_OK;
7d13a7d0
AD		 5060
5061out_drop:
7af40ad9
AD		 5062 igb_unmap_and_free_tx_resource(tx_ring, first);
5063
7d13a7d0 5064 return NETDEV_TX_OK;
9d5c8243
AK		 5065}
5066
0b725a2c
DM		 5067static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5068 struct sk_buff *skb)
1cc3bd87 5069{
0b725a2c
DM		 5070 unsigned int r_idx = skb->queue_mapping;
5071
1cc3bd87
AD		 5072 if (r_idx >= adapter->num_tx_queues)
5073 r_idx = r_idx % adapter->num_tx_queues;
5074
5075 return adapter->tx_ring[r_idx];
5076}
5077
cd392f5c
AD		 5078static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5079 struct net_device *netdev)
9d5c8243
AK		 5080{
5081 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5082
5083 if (test_bit(__IGB_DOWN, &adapter->state)) {
5084 dev_kfree_skb_any(skb);
5085 return NETDEV_TX_OK;
5086 }
5087
5088 if (skb->len <= 0) {
5089 dev_kfree_skb_any(skb);
5090 return NETDEV_TX_OK;
5091 }
5092
b980ac18 5093 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5094 * in order to meet this minimum size requirement.
5095 */
a94d9e22
AD		 5096 if (skb_put_padto(skb, 17))
5097 return NETDEV_TX_OK;
9d5c8243 5098
1cc3bd87 5099 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5100}
5101
5102/**
b980ac18
JK		 5103 * igb_tx_timeout - Respond to a Tx Hang
5104 * @netdev: network interface device structure
9d5c8243
AK		 5105 **/
5106static void igb_tx_timeout(struct net_device *netdev)
5107{
5108 struct igb_adapter *adapter = netdev_priv(netdev);
5109 struct e1000_hw *hw = &adapter->hw;
5110
5111 /* Do the reset outside of interrupt context */
5112 adapter->tx_timeout_count++;
f7ba205e 5113
06218a8d 5114 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5115 hw->dev_spec._82575.global_device_reset = true;
5116
9d5c8243 5117 schedule_work(&adapter->reset_task);
265de409
AD		 5118 wr32(E1000_EICS,
5119 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5120}
5121
5122static void igb_reset_task(struct work_struct *work)
5123{
5124 struct igb_adapter *adapter;
5125 adapter = container_of(work, struct igb_adapter, reset_task);
5126
c97ec42a
TI		 5127 igb_dump(adapter);
5128 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5129 igb_reinit_locked(adapter);
5130}
5131
5132/**
b980ac18
JK		 5133 * igb_get_stats64 - Get System Network Statistics
5134 * @netdev: network interface device structure
5135 * @stats: rtnl_link_stats64 pointer
9d5c8243 5136 **/
12dcd86b 5137static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5138 struct rtnl_link_stats64 *stats)
9d5c8243 5139{
12dcd86b
ED		 5140 struct igb_adapter *adapter = netdev_priv(netdev);
5141
5142 spin_lock(&adapter->stats64_lock);
5143 igb_update_stats(adapter, &adapter->stats64);
5144 memcpy(stats, &adapter->stats64, sizeof(*stats));
5145 spin_unlock(&adapter->stats64_lock);
5146
5147 return stats;
9d5c8243
AK		 5148}
5149
5150/**
b980ac18
JK		 5151 * igb_change_mtu - Change the Maximum Transfer Unit
5152 * @netdev: network interface device structure
5153 * @new_mtu: new value for maximum frame size
9d5c8243 5154 *
b980ac18 5155 * Returns 0 on success, negative on failure
9d5c8243
AK		 5156 **/
5157static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5158{
5159 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5160 struct pci_dev *pdev = adapter->pdev;
153285f9 5161 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5162
c809d227 5163 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5164 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5165 return -EINVAL;
5166 }
5167
153285f9 5168#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5169 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5170 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5171 return -EINVAL;
5172 }
5173
2ccd994c
AD		 5174 /* adjust max frame to be at least the size of a standard frame */
5175 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5176 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5177
9d5c8243 5178 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5179 usleep_range(1000, 2000);
73cd78f1 5180
9d5c8243
AK		 5181 /* igb_down has a dependency on max_frame_size */
5182 adapter->max_frame_size = max_frame;
559e9c49 5183
4c844851
AD		 5184 if (netif_running(netdev))
5185 igb_down(adapter);
9d5c8243 5186
090b1795 5187 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5188 netdev->mtu, new_mtu);
5189 netdev->mtu = new_mtu;
5190
5191 if (netif_running(netdev))
5192 igb_up(adapter);
5193 else
5194 igb_reset(adapter);
5195
5196 clear_bit(__IGB_RESETTING, &adapter->state);
5197
5198 return 0;
5199}
5200
5201/**
b980ac18
JK		 5202 * igb_update_stats - Update the board statistics counters
5203 * @adapter: board private structure
9d5c8243 5204 **/
12dcd86b
ED		 5205void igb_update_stats(struct igb_adapter *adapter,
5206 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5207{
5208 struct e1000_hw *hw = &adapter->hw;
5209 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5210 u32 reg, mpc;
3f9c0164
AD		 5211 int i;
5212 u64 bytes, packets;
12dcd86b
ED		 5213 unsigned int start;
5214 u64 _bytes, _packets;
9d5c8243 5215
b980ac18 5216 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5217 * connection is down.
5218 */
5219 if (adapter->link_speed == 0)
5220 return;
5221 if (pci_channel_offline(pdev))
5222 return;
5223
3f9c0164
AD		 5224 bytes = 0;
5225 packets = 0;
7f90128e
AA		 5226
5227 rcu_read_lock();
3f9c0164 5228 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5229 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5230 u32 rqdpc = rd32(E1000_RQDPC(i));
5231 if (hw->mac.type >= e1000_i210)
5232 wr32(E1000_RQDPC(i), 0);
12dcd86b 5233
ae1c07a6
AD		 5234 if (rqdpc) {
5235 ring->rx_stats.drops += rqdpc;
5236 net_stats->rx_fifo_errors += rqdpc;
5237 }
12dcd86b
ED		 5238
5239 do {
57a7744e 5240 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5241 _bytes = ring->rx_stats.bytes;
5242 _packets = ring->rx_stats.packets;
57a7744e 5243 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5244 bytes += _bytes;
5245 packets += _packets;
3f9c0164
AD		 5246 }
5247
128e45eb
AD		 5248 net_stats->rx_bytes = bytes;
5249 net_stats->rx_packets = packets;
3f9c0164
AD		 5250
5251 bytes = 0;
5252 packets = 0;
5253 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5254 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5255 do {
57a7744e 5256 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5257 _bytes = ring->tx_stats.bytes;
5258 _packets = ring->tx_stats.packets;
57a7744e 5259 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5260 bytes += _bytes;
5261 packets += _packets;
3f9c0164 5262 }
128e45eb
AD		 5263 net_stats->tx_bytes = bytes;
5264 net_stats->tx_packets = packets;
7f90128e 5265 rcu_read_unlock();
3f9c0164
AD		 5266
5267 /* read stats registers */
9d5c8243
AK		 5268 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5269 adapter->stats.gprc += rd32(E1000_GPRC);
5270 adapter->stats.gorc += rd32(E1000_GORCL);
5271 rd32(E1000_GORCH); /* clear GORCL */
5272 adapter->stats.bprc += rd32(E1000_BPRC);
5273 adapter->stats.mprc += rd32(E1000_MPRC);
5274 adapter->stats.roc += rd32(E1000_ROC);
5275
5276 adapter->stats.prc64 += rd32(E1000_PRC64);
5277 adapter->stats.prc127 += rd32(E1000_PRC127);
5278 adapter->stats.prc255 += rd32(E1000_PRC255);
5279 adapter->stats.prc511 += rd32(E1000_PRC511);
5280 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5281 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5282 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5283 adapter->stats.sec += rd32(E1000_SEC);
5284
fa3d9a6d
MW		 5285 mpc = rd32(E1000_MPC);
5286 adapter->stats.mpc += mpc;
5287 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5288 adapter->stats.scc += rd32(E1000_SCC);
5289 adapter->stats.ecol += rd32(E1000_ECOL);
5290 adapter->stats.mcc += rd32(E1000_MCC);
5291 adapter->stats.latecol += rd32(E1000_LATECOL);
5292 adapter->stats.dc += rd32(E1000_DC);
5293 adapter->stats.rlec += rd32(E1000_RLEC);
5294 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5295 adapter->stats.xontxc += rd32(E1000_XONTXC);
5296 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5297 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5298 adapter->stats.fcruc += rd32(E1000_FCRUC);
5299 adapter->stats.gptc += rd32(E1000_GPTC);
5300 adapter->stats.gotc += rd32(E1000_GOTCL);
5301 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5302 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5303 adapter->stats.ruc += rd32(E1000_RUC);
5304 adapter->stats.rfc += rd32(E1000_RFC);
5305 adapter->stats.rjc += rd32(E1000_RJC);
5306 adapter->stats.tor += rd32(E1000_TORH);
5307 adapter->stats.tot += rd32(E1000_TOTH);
5308 adapter->stats.tpr += rd32(E1000_TPR);
5309
5310 adapter->stats.ptc64 += rd32(E1000_PTC64);
5311 adapter->stats.ptc127 += rd32(E1000_PTC127);
5312 adapter->stats.ptc255 += rd32(E1000_PTC255);
5313 adapter->stats.ptc511 += rd32(E1000_PTC511);
5314 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5315 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5316
5317 adapter->stats.mptc += rd32(E1000_MPTC);
5318 adapter->stats.bptc += rd32(E1000_BPTC);
5319
2d0b0f69
NN		 5320 adapter->stats.tpt += rd32(E1000_TPT);
5321 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5322
5323 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5324 /* read internal phy specific stats */
5325 reg = rd32(E1000_CTRL_EXT);
5326 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5327 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5328
5329 /* this stat has invalid values on i210/i211 */
5330 if ((hw->mac.type != e1000_i210) &&
5331 (hw->mac.type != e1000_i211))
5332 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5333 }
5334
9d5c8243
AK		 5335 adapter->stats.tsctc += rd32(E1000_TSCTC);
5336 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5337
5338 adapter->stats.iac += rd32(E1000_IAC);
5339 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5340 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5341 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5342 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5343 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5344 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5345 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5346 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5347
5348 /* Fill out the OS statistics structure */
128e45eb
AD		 5349 net_stats->multicast = adapter->stats.mprc;
5350 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5351
5352 /* Rx Errors */
5353
5354 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5355 * our own version based on RUC and ROC
5356 */
128e45eb 5357 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5358 adapter->stats.crcerrs + adapter->stats.algnerrc +
5359 adapter->stats.ruc + adapter->stats.roc +
5360 adapter->stats.cexterr;
128e45eb
AD		 5361 net_stats->rx_length_errors = adapter->stats.ruc +
5362 adapter->stats.roc;
5363 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5364 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5365 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5366
5367 /* Tx Errors */
128e45eb
AD		 5368 net_stats->tx_errors = adapter->stats.ecol +
5369 adapter->stats.latecol;
5370 net_stats->tx_aborted_errors = adapter->stats.ecol;
5371 net_stats->tx_window_errors = adapter->stats.latecol;
5372 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5373
5374 /* Tx Dropped needs to be maintained elsewhere */
5375
9d5c8243
AK		 5376 /* Management Stats */
5377 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5378 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5379 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5380
5381 /* OS2BMC Stats */
5382 reg = rd32(E1000_MANC);
5383 if (reg & E1000_MANC_EN_BMC2OS) {
5384 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5385 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5386 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5387 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5388 }
9d5c8243
AK		 5389}
5390
61d7f75f
RC		 5391static void igb_tsync_interrupt(struct igb_adapter *adapter)
5392{
5393 struct e1000_hw *hw = &adapter->hw;
00c65578 5394 struct ptp_clock_event event;
40c9b079 5395 struct timespec64 ts;
720db4ff 5396 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5397
5398 if (tsicr & TSINTR_SYS_WRAP) {
5399 event.type = PTP_CLOCK_PPS;
5400 if (adapter->ptp_caps.pps)
5401 ptp_clock_event(adapter->ptp_clock, &event);
5402 else
5403 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5404 ack |= TSINTR_SYS_WRAP;
5405 }
61d7f75f
RC		 5406
5407 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5408 /* retrieve hardware timestamp */
5409 schedule_work(&adapter->ptp_tx_work);
00c65578 5410 ack |= E1000_TSICR_TXTS;
61d7f75f 5411 }
00c65578 5412
720db4ff
RC		 5413 if (tsicr & TSINTR_TT0) {
5414 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5415 ts = timespec64_add(adapter->perout[0].start,
5416 adapter->perout[0].period);
5417 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5418 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5419 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5420 tsauxc = rd32(E1000_TSAUXC);
5421 tsauxc |= TSAUXC_EN_TT0;
5422 wr32(E1000_TSAUXC, tsauxc);
5423 adapter->perout[0].start = ts;
5424 spin_unlock(&adapter->tmreg_lock);
5425 ack |= TSINTR_TT0;
5426 }
5427
5428 if (tsicr & TSINTR_TT1) {
5429 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5430 ts = timespec64_add(adapter->perout[1].start,
5431 adapter->perout[1].period);
720db4ff 5432 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5433 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5434 tsauxc = rd32(E1000_TSAUXC);
5435 tsauxc |= TSAUXC_EN_TT1;
5436 wr32(E1000_TSAUXC, tsauxc);
5437 adapter->perout[1].start = ts;
5438 spin_unlock(&adapter->tmreg_lock);
5439 ack |= TSINTR_TT1;
5440 }
5441
5442 if (tsicr & TSINTR_AUTT0) {
5443 nsec = rd32(E1000_AUXSTMPL0);
5444 sec = rd32(E1000_AUXSTMPH0);
5445 event.type = PTP_CLOCK_EXTTS;
5446 event.index = 0;
5447 event.timestamp = sec * 1000000000ULL + nsec;
5448 ptp_clock_event(adapter->ptp_clock, &event);
5449 ack |= TSINTR_AUTT0;
5450 }
5451
5452 if (tsicr & TSINTR_AUTT1) {
5453 nsec = rd32(E1000_AUXSTMPL1);
5454 sec = rd32(E1000_AUXSTMPH1);
5455 event.type = PTP_CLOCK_EXTTS;
5456 event.index = 1;
5457 event.timestamp = sec * 1000000000ULL + nsec;
5458 ptp_clock_event(adapter->ptp_clock, &event);
5459 ack |= TSINTR_AUTT1;
5460 }
5461
00c65578
RC		 5462 /* acknowledge the interrupts */
5463 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5464}
5465
9d5c8243
AK		 5466static irqreturn_t igb_msix_other(int irq, void *data)
5467{
047e0030 5468 struct igb_adapter *adapter = data;
9d5c8243 5469 struct e1000_hw *hw = &adapter->hw;
844290e5 5470 u32 icr = rd32(E1000_ICR);
844290e5 5471 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5472
7f081d40
AD		 5473 if (icr & E1000_ICR_DRSTA)
5474 schedule_work(&adapter->reset_task);
5475
047e0030 5476 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5477 /* HW is reporting DMA is out of sync */
5478 adapter->stats.doosync++;
13800469
GR		 5479 /* The DMA Out of Sync is also indication of a spoof event
5480 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5481 * see if it is really a spoof event.
5482 */
13800469 5483 igb_check_wvbr(adapter);
dda0e083 5484 }
eebbbdba 5485
4ae196df
AD		 5486 /* Check for a mailbox event */
5487 if (icr & E1000_ICR_VMMB)
5488 igb_msg_task(adapter);
5489
5490 if (icr & E1000_ICR_LSC) {
5491 hw->mac.get_link_status = 1;
5492 /* guard against interrupt when we're going down */
5493 if (!test_bit(__IGB_DOWN, &adapter->state))
5494 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5495 }
5496
61d7f75f
RC		 5497 if (icr & E1000_ICR_TS)
5498 igb_tsync_interrupt(adapter);
1f6e8178 5499
844290e5 5500 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5501
5502 return IRQ_HANDLED;
5503}
5504
047e0030 5505static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5506{
26b39276 5507 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5508 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5509
047e0030
AD		 5510 if (!q_vector->set_itr)
5511 return;
73cd78f1 5512
047e0030
AD		 5513 if (!itr_val)
5514 itr_val = 0x4;
661086df 5515
26b39276
AD		 5516 if (adapter->hw.mac.type == e1000_82575)
5517 itr_val |= itr_val << 16;
661086df 5518 else
0ba82994 5519 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5520
047e0030
AD		 5521 writel(itr_val, q_vector->itr_register);
5522 q_vector->set_itr = 0;
6eb5a7f1
AD		 5523}
5524
047e0030 5525static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5526{
047e0030 5527 struct igb_q_vector *q_vector = data;
9d5c8243 5528
047e0030
AD		 5529 /* Write the ITR value calculated from the previous interrupt. */
5530 igb_write_itr(q_vector);
9d5c8243 5531
047e0030 5532 napi_schedule(&q_vector->napi);
844290e5 5533
047e0030 5534 return IRQ_HANDLED;
fe4506b6
JC		 5535}
5536
421e02f0 5537#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5538static void igb_update_tx_dca(struct igb_adapter *adapter,
5539 struct igb_ring *tx_ring,
5540 int cpu)
5541{
5542 struct e1000_hw *hw = &adapter->hw;
5543 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5544
5545 if (hw->mac.type != e1000_82575)
5546 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5547
b980ac18 5548 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5549 * DCA is enabled. This is due to a known issue in some chipsets
5550 * which will cause the DCA tag to be cleared.
5551 */
5552 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5553 E1000_DCA_TXCTRL_DATA_RRO_EN |
5554 E1000_DCA_TXCTRL_DESC_DCA_EN;
5555
5556 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5557}
5558
5559static void igb_update_rx_dca(struct igb_adapter *adapter,
5560 struct igb_ring *rx_ring,
5561 int cpu)
5562{
5563 struct e1000_hw *hw = &adapter->hw;
5564 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5565
5566 if (hw->mac.type != e1000_82575)
5567 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5568
b980ac18 5569 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5570 * DCA is enabled. This is due to a known issue in some chipsets
5571 * which will cause the DCA tag to be cleared.
5572 */
5573 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5574 E1000_DCA_RXCTRL_DESC_DCA_EN;
5575
5576 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5577}
5578
047e0030 5579static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5580{
047e0030 5581 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5582 int cpu = get_cpu();
fe4506b6 5583
047e0030
AD		 5584 if (q_vector->cpu == cpu)
5585 goto out_no_update;
5586
6a05004a
AD		 5587 if (q_vector->tx.ring)
5588 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5589
5590 if (q_vector->rx.ring)
5591 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5592
047e0030
AD		 5593 q_vector->cpu = cpu;
5594out_no_update:
fe4506b6
JC		 5595 put_cpu();
5596}
5597
5598static void igb_setup_dca(struct igb_adapter *adapter)
5599{
7e0e99ef 5600 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5601 int i;
5602
7dfc16fa 5603 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5604 return;
5605
7e0e99ef
AD		 5606 /* Always use CB2 mode, difference is masked in the CB driver. */
5607 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5608
047e0030 5609 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5610 adapter->q_vector[i]->cpu = -1;
5611 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5612 }
5613}
5614
5615static int __igb_notify_dca(struct device *dev, void *data)
5616{
5617 struct net_device *netdev = dev_get_drvdata(dev);
5618 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5619 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5620 struct e1000_hw *hw = &adapter->hw;
5621 unsigned long event = *(unsigned long *)data;
5622
5623 switch (event) {
5624 case DCA_PROVIDER_ADD:
5625 /* if already enabled, don't do it again */
7dfc16fa 5626 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5627 break;
fe4506b6 5628 if (dca_add_requester(dev) == 0) {
bbd98fe4 5629 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5630 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5631 igb_setup_dca(adapter);
5632 break;
5633 }
5634 /* Fall Through since DCA is disabled. */
5635 case DCA_PROVIDER_REMOVE:
7dfc16fa 5636 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5637 /* without this a class_device is left
b980ac18
JK		 5638 * hanging around in the sysfs model
5639 */
fe4506b6 5640 dca_remove_requester(dev);
090b1795 5641 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5642 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5643 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5644 }
5645 break;
5646 }
bbd98fe4 5647
fe4506b6 5648 return 0;
9d5c8243
AK		 5649}
5650
fe4506b6 5651static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5652 void *p)
fe4506b6
JC		 5653{
5654 int ret_val;
5655
5656 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5657 __igb_notify_dca);
fe4506b6
JC		 5658
5659 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5660}
421e02f0 5661#endif /* CONFIG_IGB_DCA */
9d5c8243 5662
0224d663
GR		 5663#ifdef CONFIG_PCI_IOV
5664static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5665{
5666 unsigned char mac_addr[ETH_ALEN];
0224d663 5667
5ac6f91d 5668 eth_zero_addr(mac_addr);
0224d663
GR		 5669 igb_set_vf_mac(adapter, vf, mac_addr);
5670
70ea4783
LL		 5671 /* By default spoof check is enabled for all VFs */
5672 adapter->vf_data[vf].spoofchk_enabled = true;
5673
f557147c 5674 return 0;
0224d663
GR		 5675}
5676
0224d663 5677#endif
4ae196df
AD		 5678static void igb_ping_all_vfs(struct igb_adapter *adapter)
5679{
5680 struct e1000_hw *hw = &adapter->hw;
5681 u32 ping;
5682 int i;
5683
5684 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5685 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5686 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5687 ping |= E1000_VT_MSGTYPE_CTS;
5688 igb_write_mbx(hw, &ping, 1, i);
5689 }
5690}
5691
7d5753f0
AD		 5692static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5693{
5694 struct e1000_hw *hw = &adapter->hw;
5695 u32 vmolr = rd32(E1000_VMOLR(vf));
5696 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5697
d85b9004 5698 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5699 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5700 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5701
5702 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5703 vmolr |= E1000_VMOLR_MPME;
d85b9004 5704 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5705 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5706 } else {
b980ac18 5707 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5708 * flag we need to write the hashes to the MTA as this step
5709 * was previously skipped
5710 */
5711 if (vf_data->num_vf_mc_hashes > 30) {
5712 vmolr |= E1000_VMOLR_MPME;
5713 } else if (vf_data->num_vf_mc_hashes) {
5714 int j;
9005df38 5715
7d5753f0
AD		 5716 vmolr |= E1000_VMOLR_ROMPE;
5717 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5718 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5719 }
5720 }
5721
5722 wr32(E1000_VMOLR(vf), vmolr);
5723
5724 /* there are flags left unprocessed, likely not supported */
5725 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5726 return -EINVAL;
5727
5728 return 0;
7d5753f0
AD		 5729}
5730
4ae196df
AD		 5731static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5732 u32 *msgbuf, u32 vf)
5733{
5734 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5735 u16 *hash_list = (u16 *)&msgbuf[1];
5736 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5737 int i;
5738
7d5753f0 5739 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5740 * to this VF for later use to restore when the PF multi cast
5741 * list changes
5742 */
5743 vf_data->num_vf_mc_hashes = n;
5744
7d5753f0
AD		 5745 /* only up to 30 hash values supported */
5746 if (n > 30)
5747 n = 30;
5748
5749 /* store the hashes for later use */
4ae196df 5750 for (i = 0; i < n; i++)
a419aef8 5751 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5752
5753 /* Flush and reset the mta with the new values */
ff41f8dc 5754 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5755
5756 return 0;
5757}
5758
5759static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5760{
5761 struct e1000_hw *hw = &adapter->hw;
5762 struct vf_data_storage *vf_data;
5763 int i, j;
5764
5765 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5766 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5767
7d5753f0
AD		 5768 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5769
4ae196df 5770 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5771
5772 if ((vf_data->num_vf_mc_hashes > 30) ||
5773 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5774 vmolr |= E1000_VMOLR_MPME;
5775 } else if (vf_data->num_vf_mc_hashes) {
5776 vmolr |= E1000_VMOLR_ROMPE;
5777 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5778 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5779 }
5780 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5781 }
5782}
5783
5784static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5785{
5786 struct e1000_hw *hw = &adapter->hw;
5787 u32 pool_mask, reg, vid;
5788 int i;
5789
5790 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5791
5792 /* Find the vlan filter for this id */
5793 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5794 reg = rd32(E1000_VLVF(i));
5795
5796 /* remove the vf from the pool */
5797 reg &= ~pool_mask;
5798
5799 /* if pool is empty then remove entry from vfta */
5800 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5801 (reg & E1000_VLVF_VLANID_ENABLE)) {
5802 reg = 0;
5803 vid = reg & E1000_VLVF_VLANID_MASK;
5804 igb_vfta_set(hw, vid, false);
5805 }
5806
5807 wr32(E1000_VLVF(i), reg);
5808 }
ae641bdc
AD		 5809
5810 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5811}
5812
5813static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5814{
5815 struct e1000_hw *hw = &adapter->hw;
5816 u32 reg, i;
5817
51466239
AD		 5818 /* The vlvf table only exists on 82576 hardware and newer */
5819 if (hw->mac.type < e1000_82576)
5820 return -1;
5821
5822 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5823 if (!adapter->vfs_allocated_count)
5824 return -1;
5825
5826 /* Find the vlan filter for this id */
5827 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5828 reg = rd32(E1000_VLVF(i));
5829 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5830 vid == (reg & E1000_VLVF_VLANID_MASK))
5831 break;
5832 }
5833
5834 if (add) {
5835 if (i == E1000_VLVF_ARRAY_SIZE) {
5836 /* Did not find a matching VLAN ID entry that was
5837 * enabled. Search for a free filter entry, i.e.
5838 * one without the enable bit set
5839 */
5840 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5841 reg = rd32(E1000_VLVF(i));
5842 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5843 break;
5844 }
5845 }
5846 if (i < E1000_VLVF_ARRAY_SIZE) {
5847 /* Found an enabled/available entry */
5848 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5849
5850 /* if !enabled we need to set this up in vfta */
5851 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5852 /* add VID to filter table */
5853 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5854 reg |= E1000_VLVF_VLANID_ENABLE;
5855 }
cad6d05f
AD		 5856 reg &= ~E1000_VLVF_VLANID_MASK;
5857 reg |= vid;
4ae196df 5858 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5859
5860 /* do not modify RLPML for PF devices */
5861 if (vf >= adapter->vfs_allocated_count)
5862 return 0;
5863
5864 if (!adapter->vf_data[vf].vlans_enabled) {
5865 u32 size;
9005df38 5866
ae641bdc
AD		 5867 reg = rd32(E1000_VMOLR(vf));
5868 size = reg & E1000_VMOLR_RLPML_MASK;
5869 size += 4;
5870 reg &= ~E1000_VMOLR_RLPML_MASK;
5871 reg |= size;
5872 wr32(E1000_VMOLR(vf), reg);
5873 }
ae641bdc 5874
51466239 5875 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5876 }
5877 } else {
5878 if (i < E1000_VLVF_ARRAY_SIZE) {
5879 /* remove vf from the pool */
5880 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5881 /* if pool is empty then remove entry from vfta */
5882 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5883 reg = 0;
5884 igb_vfta_set(hw, vid, false);
5885 }
5886 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5887
5888 /* do not modify RLPML for PF devices */
5889 if (vf >= adapter->vfs_allocated_count)
5890 return 0;
5891
5892 adapter->vf_data[vf].vlans_enabled--;
5893 if (!adapter->vf_data[vf].vlans_enabled) {
5894 u32 size;
9005df38 5895
ae641bdc
AD		 5896 reg = rd32(E1000_VMOLR(vf));
5897 size = reg & E1000_VMOLR_RLPML_MASK;
5898 size -= 4;
5899 reg &= ~E1000_VMOLR_RLPML_MASK;
5900 reg |= size;
5901 wr32(E1000_VMOLR(vf), reg);
5902 }
4ae196df
AD		 5903 }
5904 }
8151d294
WM		 5905 return 0;
5906}
5907
5908static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5909{
5910 struct e1000_hw *hw = &adapter->hw;
5911
5912 if (vid)
5913 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5914 else
5915 wr32(E1000_VMVIR(vf), 0);
5916}
5917
5918static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5919 int vf, u16 vlan, u8 qos)
5920{
5921 int err = 0;
5922 struct igb_adapter *adapter = netdev_priv(netdev);
5923
5924 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5925 return -EINVAL;
5926 if (vlan || qos) {
5927 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5928 if (err)
5929 goto out;
5930 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5931 igb_set_vmolr(adapter, vf, !vlan);
5932 adapter->vf_data[vf].pf_vlan = vlan;
5933 adapter->vf_data[vf].pf_qos = qos;
5934 dev_info(&adapter->pdev->dev,
5935 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5936 if (test_bit(__IGB_DOWN, &adapter->state)) {
5937 dev_warn(&adapter->pdev->dev,
b980ac18 5938 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5939 dev_warn(&adapter->pdev->dev,
b980ac18 5940 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5941 }
5942 } else {
5943 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5944 false, vf);
8151d294
WM		 5945 igb_set_vmvir(adapter, vlan, vf);
5946 igb_set_vmolr(adapter, vf, true);
5947 adapter->vf_data[vf].pf_vlan = 0;
5948 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5949 }
8151d294 5950out:
b980ac18 5951 return err;
4ae196df
AD		 5952}
5953
6f3dc319
GR		 5954static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5955{
5956 struct e1000_hw *hw = &adapter->hw;
5957 int i;
5958 u32 reg;
5959
5960 /* Find the vlan filter for this id */
5961 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5962 reg = rd32(E1000_VLVF(i));
5963 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5964 vid == (reg & E1000_VLVF_VLANID_MASK))
5965 break;
5966 }
5967
5968 if (i >= E1000_VLVF_ARRAY_SIZE)
5969 i = -1;
5970
5971 return i;
5972}
5973
4ae196df
AD		 5974static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5975{
6f3dc319 5976 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5977 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5978 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5979 int err = 0;
4ae196df 5980
6f3dc319
GR		 5981 /* If in promiscuous mode we need to make sure the PF also has
5982 * the VLAN filter set.
5983 */
5984 if (add && (adapter->netdev->flags & IFF_PROMISC))
5985 err = igb_vlvf_set(adapter, vid, add,
5986 adapter->vfs_allocated_count);
5987 if (err)
5988 goto out;
5989
5990 err = igb_vlvf_set(adapter, vid, add, vf);
5991
5992 if (err)
5993 goto out;
5994
5995 /* Go through all the checks to see if the VLAN filter should
5996 * be wiped completely.
5997 */
5998 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5999 u32 vlvf, bits;
6f3dc319 6000 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 6001
6f3dc319
GR		 6002 if (regndx < 0)
6003 goto out;
6004 /* See if any other pools are set for this VLAN filter
6005 * entry other than the PF.
6006 */
6007 vlvf = bits = rd32(E1000_VLVF(regndx));
6008 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6009 adapter->vfs_allocated_count);
6010 /* If the filter was removed then ensure PF pool bit
6011 * is cleared if the PF only added itself to the pool
6012 * because the PF is in promiscuous mode.
6013 */
6014 if ((vlvf & VLAN_VID_MASK) == vid &&
6015 !test_bit(vid, adapter->active_vlans) &&
6016 !bits)
6017 igb_vlvf_set(adapter, vid, add,
6018 adapter->vfs_allocated_count);
6019 }
6020
6021out:
6022 return err;
4ae196df
AD		 6023}
6024
f2ca0dbe 6025static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 6026{
8fa7e0f7
GR		 6027 /* clear flags - except flag that indicates PF has set the MAC */
6028 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 6029 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 6030
6031 /* reset offloads to defaults */
8151d294 6032 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 6033
6034 /* reset vlans for device */
6035 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 6036 if (adapter->vf_data[vf].pf_vlan)
6037 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6038 adapter->vf_data[vf].pf_vlan,
6039 adapter->vf_data[vf].pf_qos);
6040 else
6041 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 6042
6043 /* reset multicast table array for vf */
6044 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6045
6046 /* Flush and reset the mta with the new values */
ff41f8dc 6047 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6048}
6049
f2ca0dbe
AD		 6050static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6051{
6052 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6053
5ac6f91d 6054 /* clear mac address as we were hotplug removed/added */
8151d294 6055 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6056 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6057
6058 /* process remaining reset events */
6059 igb_vf_reset(adapter, vf);
6060}
6061
6062static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6063{
6064 struct e1000_hw *hw = &adapter->hw;
6065 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6066 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6067 u32 reg, msgbuf[3];
6068 u8 *addr = (u8 *)(&msgbuf[1]);
6069
6070 /* process all the same items cleared in a function level reset */
f2ca0dbe 6071 igb_vf_reset(adapter, vf);
4ae196df
AD		 6072
6073 /* set vf mac address */
26ad9178 6074 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6075
6076 /* enable transmit and receive for vf */
6077 reg = rd32(E1000_VFTE);
6078 wr32(E1000_VFTE, reg | (1 << vf));
6079 reg = rd32(E1000_VFRE);
6080 wr32(E1000_VFRE, reg | (1 << vf));
6081
8fa7e0f7 6082 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6083
6084 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6085 if (!is_zero_ether_addr(vf_mac)) {
6086 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6087 memcpy(addr, vf_mac, ETH_ALEN);
6088 } else {
6089 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6090 }
4ae196df
AD		 6091 igb_write_mbx(hw, msgbuf, 3, vf);
6092}
6093
6094static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6095{
b980ac18 6096 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6097 * starting at the second 32 bit word of the msg array
6098 */
f2ca0dbe
AD		 6099 unsigned char *addr = (char *)&msg[1];
6100 int err = -1;
4ae196df 6101
f2ca0dbe
AD		 6102 if (is_valid_ether_addr(addr))
6103 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6104
f2ca0dbe 6105 return err;
4ae196df
AD		 6106}
6107
6108static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6109{
6110 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6111 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6112 u32 msg = E1000_VT_MSGTYPE_NACK;
6113
6114 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6115 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6116 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6117 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6118 vf_data->last_nack = jiffies;
4ae196df
AD		 6119 }
6120}
6121
f2ca0dbe 6122static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6123{
f2ca0dbe
AD		 6124 struct pci_dev *pdev = adapter->pdev;
6125 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6126 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6127 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6128 s32 retval;
6129
f2ca0dbe 6130 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6131
fef45f4c
AD		 6132 if (retval) {
6133 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6134 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6135 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6136 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6137 return;
6138 goto out;
6139 }
4ae196df
AD		 6140
6141 /* this is a message we already processed, do nothing */
6142 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6143 return;
4ae196df 6144
b980ac18 6145 /* until the vf completes a reset it should not be
4ae196df
AD		 6146 * allowed to start any configuration.
6147 */
4ae196df
AD		 6148 if (msgbuf[0] == E1000_VF_RESET) {
6149 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6150 return;
4ae196df
AD		 6151 }
6152
f2ca0dbe 6153 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6154 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6155 return;
6156 retval = -1;
6157 goto out;
4ae196df
AD		 6158 }
6159
6160 switch ((msgbuf[0] & 0xFFFF)) {
6161 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6162 retval = -EINVAL;
6163 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6164 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6165 else
6166 dev_warn(&pdev->dev,
b980ac18
JK		 6167 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6168 vf);
4ae196df 6169 break;
7d5753f0
AD		 6170 case E1000_VF_SET_PROMISC:
6171 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6172 break;
4ae196df
AD		 6173 case E1000_VF_SET_MULTICAST:
6174 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6175 break;
6176 case E1000_VF_SET_LPE:
6177 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6178 break;
6179 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6180 retval = -1;
6181 if (vf_data->pf_vlan)
6182 dev_warn(&pdev->dev,
b980ac18
JK		 6183 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6184 vf);
8151d294
WM		 6185 else
6186 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6187 break;
6188 default:
090b1795 6189 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6190 retval = -1;
6191 break;
6192 }
6193
fef45f4c
AD		 6194 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6195out:
4ae196df
AD		 6196 /* notify the VF of the results of what it sent us */
6197 if (retval)
6198 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6199 else
6200 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6201
4ae196df 6202 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6203}
4ae196df 6204
f2ca0dbe
AD		 6205static void igb_msg_task(struct igb_adapter *adapter)
6206{
6207 struct e1000_hw *hw = &adapter->hw;
6208 u32 vf;
6209
6210 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6211 /* process any reset requests */
6212 if (!igb_check_for_rst(hw, vf))
6213 igb_vf_reset_event(adapter, vf);
6214
6215 /* process any messages pending */
6216 if (!igb_check_for_msg(hw, vf))
6217 igb_rcv_msg_from_vf(adapter, vf);
6218
6219 /* process any acks */
6220 if (!igb_check_for_ack(hw, vf))
6221 igb_rcv_ack_from_vf(adapter, vf);
6222 }
4ae196df
AD		 6223}
6224
68d480c4
AD		 6225/**
6226 * igb_set_uta - Set unicast filter table address
6227 * @adapter: board private structure
6228 *
6229 * The unicast table address is a register array of 32-bit registers.
6230 * The table is meant to be used in a way similar to how the MTA is used
6231 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6232 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6233 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6234 **/
6235static void igb_set_uta(struct igb_adapter *adapter)
6236{
6237 struct e1000_hw *hw = &adapter->hw;
6238 int i;
6239
6240 /* The UTA table only exists on 82576 hardware and newer */
6241 if (hw->mac.type < e1000_82576)
6242 return;
6243
6244 /* we only need to do this if VMDq is enabled */
6245 if (!adapter->vfs_allocated_count)
6246 return;
6247
6248 for (i = 0; i < hw->mac.uta_reg_count; i++)
6249 array_wr32(E1000_UTA, i, ~0);
6250}
6251
9d5c8243 6252/**
b980ac18
JK		 6253 * igb_intr_msi - Interrupt Handler
6254 * @irq: interrupt number
6255 * @data: pointer to a network interface device structure
9d5c8243
AK		 6256 **/
6257static irqreturn_t igb_intr_msi(int irq, void *data)
6258{
047e0030
AD		 6259 struct igb_adapter *adapter = data;
6260 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6261 struct e1000_hw *hw = &adapter->hw;
6262 /* read ICR disables interrupts using IAM */
6263 u32 icr = rd32(E1000_ICR);
6264
047e0030 6265 igb_write_itr(q_vector);
9d5c8243 6266
7f081d40
AD		 6267 if (icr & E1000_ICR_DRSTA)
6268 schedule_work(&adapter->reset_task);
6269
047e0030 6270 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6271 /* HW is reporting DMA is out of sync */
6272 adapter->stats.doosync++;
6273 }
6274
9d5c8243
AK		 6275 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6276 hw->mac.get_link_status = 1;
6277 if (!test_bit(__IGB_DOWN, &adapter->state))
6278 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6279 }
6280
61d7f75f
RC		 6281 if (icr & E1000_ICR_TS)
6282 igb_tsync_interrupt(adapter);
1f6e8178 6283
047e0030 6284 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6285
6286 return IRQ_HANDLED;
6287}
6288
6289/**
b980ac18
JK		 6290 * igb_intr - Legacy Interrupt Handler
6291 * @irq: interrupt number
6292 * @data: pointer to a network interface device structure
9d5c8243
AK		 6293 **/
6294static irqreturn_t igb_intr(int irq, void *data)
6295{
047e0030
AD		 6296 struct igb_adapter *adapter = data;
6297 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6298 struct e1000_hw *hw = &adapter->hw;
6299 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6300 * need for the IMC write
6301 */
9d5c8243 6302 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6303
6304 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6305 * not set, then the adapter didn't send an interrupt
6306 */
9d5c8243
AK		 6307 if (!(icr & E1000_ICR_INT_ASSERTED))
6308 return IRQ_NONE;
6309
0ba82994
AD		 6310 igb_write_itr(q_vector);
6311
7f081d40
AD		 6312 if (icr & E1000_ICR_DRSTA)
6313 schedule_work(&adapter->reset_task);
6314
047e0030 6315 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6316 /* HW is reporting DMA is out of sync */
6317 adapter->stats.doosync++;
6318 }
6319
9d5c8243
AK		 6320 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6321 hw->mac.get_link_status = 1;
6322 /* guard against interrupt when we're going down */
6323 if (!test_bit(__IGB_DOWN, &adapter->state))
6324 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6325 }
6326
61d7f75f
RC		 6327 if (icr & E1000_ICR_TS)
6328 igb_tsync_interrupt(adapter);
1f6e8178 6329
047e0030 6330 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6331
6332 return IRQ_HANDLED;
6333}
6334
c50b52a0 6335static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6336{
047e0030 6337 struct igb_adapter *adapter = q_vector->adapter;
46544258 6338 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6339
0ba82994
AD		 6340 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6341 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6342 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6343 igb_set_itr(q_vector);
46544258 6344 else
047e0030 6345 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6346 }
6347
46544258 6348 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6349 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6350 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6351 else
6352 igb_irq_enable(adapter);
6353 }
9d5c8243
AK		 6354}
6355
46544258 6356/**
b980ac18
JK		 6357 * igb_poll - NAPI Rx polling callback
6358 * @napi: napi polling structure
6359 * @budget: count of how many packets we should handle
46544258
AD		 6360 **/
6361static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6362{
047e0030 6363 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6364 struct igb_q_vector,
6365 napi);
16eb8815 6366 bool clean_complete = true;
32b3e08f 6367 int work_done = 0;
9d5c8243 6368
421e02f0 6369#ifdef CONFIG_IGB_DCA
047e0030
AD		 6370 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6371 igb_update_dca(q_vector);
fe4506b6 6372#endif
0ba82994 6373 if (q_vector->tx.ring)
13fde97a 6374 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6375
32b3e08f
JB		 6376 if (q_vector->rx.ring) {
6377 int cleaned = igb_clean_rx_irq(q_vector, budget);
6378
6379 work_done += cleaned;
6380 clean_complete &= (cleaned < budget);
6381 }
047e0030 6382
16eb8815
AD		 6383 /* If all work not completed, return budget and keep polling */
6384 if (!clean_complete)
6385 return budget;
46544258 6386
9d5c8243 6387 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6388 napi_complete_done(napi, work_done);
16eb8815 6389 igb_ring_irq_enable(q_vector);
9d5c8243 6390
16eb8815 6391 return 0;
9d5c8243 6392}
6d8126f9 6393
9d5c8243 6394/**
b980ac18
JK		 6395 * igb_clean_tx_irq - Reclaim resources after transmit completes
6396 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6397 *
b980ac18 6398 * returns true if ring is completely cleaned
9d5c8243 6399 **/
047e0030 6400static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6401{
047e0030 6402 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6403 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6404 struct igb_tx_buffer *tx_buffer;
f4128785 6405 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6406 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6407 unsigned int budget = q_vector->tx.work_limit;
8542db05 6408 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6409
13fde97a
AD		 6410 if (test_bit(__IGB_DOWN, &adapter->state))
6411 return true;
0e014cb1 6412
06034649 6413 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6414 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6415 i -= tx_ring->count;
9d5c8243 6416
f4128785
AD		 6417 do {
6418 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6419
6420 /* if next_to_watch is not set then there is no work pending */
6421 if (!eop_desc)
6422 break;
13fde97a 6423
f4128785 6424 /* prevent any other reads prior to eop_desc */
70d289bc 6425 read_barrier_depends();
f4128785 6426
13fde97a
AD		 6427 /* if DD is not set pending work has not been completed */
6428 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6429 break;
6430
8542db05
AD		 6431 /* clear next_to_watch to prevent false hangs */
6432 tx_buffer->next_to_watch = NULL;
9d5c8243 6433
ebe42d16
AD		 6434 /* update the statistics for this packet */
6435 total_bytes += tx_buffer->bytecount;
6436 total_packets += tx_buffer->gso_segs;
13fde97a 6437
ebe42d16 6438 /* free the skb */
a81fb049 6439 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6440
ebe42d16
AD		 6441 /* unmap skb header data */
6442 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6443 dma_unmap_addr(tx_buffer, dma),
6444 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6445 DMA_TO_DEVICE);
6446
c9f14bf3
AD		 6447 /* clear tx_buffer data */
6448 tx_buffer->skb = NULL;
6449 dma_unmap_len_set(tx_buffer, len, 0);
6450
ebe42d16
AD		 6451 /* clear last DMA location and unmap remaining buffers */
6452 while (tx_desc != eop_desc) {
13fde97a
AD		 6453 tx_buffer++;
6454 tx_desc++;
9d5c8243 6455 i++;
8542db05
AD		 6456 if (unlikely(!i)) {
6457 i -= tx_ring->count;
06034649 6458 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6459 tx_desc = IGB_TX_DESC(tx_ring, 0);
6460 }
ebe42d16
AD		 6461
6462 /* unmap any remaining paged data */
c9f14bf3 6463 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6464 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6465 dma_unmap_addr(tx_buffer, dma),
6466 dma_unmap_len(tx_buffer, len),
ebe42d16 6467 DMA_TO_DEVICE);
c9f14bf3 6468 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6469 }
6470 }
6471
ebe42d16
AD		 6472 /* move us one more past the eop_desc for start of next pkt */
6473 tx_buffer++;
6474 tx_desc++;
6475 i++;
6476 if (unlikely(!i)) {
6477 i -= tx_ring->count;
6478 tx_buffer = tx_ring->tx_buffer_info;
6479 tx_desc = IGB_TX_DESC(tx_ring, 0);
6480 }
f4128785
AD		 6481
6482 /* issue prefetch for next Tx descriptor */
6483 prefetch(tx_desc);
6484
6485 /* update budget accounting */
6486 budget--;
6487 } while (likely(budget));
0e014cb1 6488
bdbc0631
ED		 6489 netdev_tx_completed_queue(txring_txq(tx_ring),
6490 total_packets, total_bytes);
8542db05 6491 i += tx_ring->count;
9d5c8243 6492 tx_ring->next_to_clean = i;
13fde97a
AD		 6493 u64_stats_update_begin(&tx_ring->tx_syncp);
6494 tx_ring->tx_stats.bytes += total_bytes;
6495 tx_ring->tx_stats.packets += total_packets;
6496 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6497 q_vector->tx.total_bytes += total_bytes;
6498 q_vector->tx.total_packets += total_packets;
9d5c8243 6499
6d095fa8 6500 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6501 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6502
9d5c8243 6503 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6504 * check with the clearing of time_stamp and movement of i
6505 */
6d095fa8 6506 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6507 if (tx_buffer->next_to_watch &&
8542db05 6508 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6509 (adapter->tx_timeout_factor * HZ)) &&
6510 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6511
9d5c8243 6512 /* detected Tx unit hang */
59d71989 6513 dev_err(tx_ring->dev,
9d5c8243 6514 "Detected Tx Unit Hang\n"
2d064c06 6515 " Tx Queue <%d>\n"
9d5c8243
AK		 6516 " TDH <%x>\n"
6517 " TDT <%x>\n"
6518 " next_to_use <%x>\n"
6519 " next_to_clean <%x>\n"
9d5c8243
AK		 6520 "buffer_info[next_to_clean]\n"
6521 " time_stamp <%lx>\n"
8542db05 6522 " next_to_watch <%p>\n"
9d5c8243
AK		 6523 " jiffies <%lx>\n"
6524 " desc.status <%x>\n",
2d064c06 6525 tx_ring->queue_index,
238ac817 6526 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6527 readl(tx_ring->tail),
9d5c8243
AK		 6528 tx_ring->next_to_use,
6529 tx_ring->next_to_clean,
8542db05 6530 tx_buffer->time_stamp,
f4128785 6531 tx_buffer->next_to_watch,
9d5c8243 6532 jiffies,
f4128785 6533 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6534 netif_stop_subqueue(tx_ring->netdev,
6535 tx_ring->queue_index);
6536
6537 /* we are about to reset, no point in enabling stuff */
6538 return true;
9d5c8243
AK		 6539 }
6540 }
13fde97a 6541
21ba6fe1 6542#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6543 if (unlikely(total_packets &&
b980ac18
JK		 6544 netif_carrier_ok(tx_ring->netdev) &&
6545 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6546 /* Make sure that anybody stopping the queue after this
6547 * sees the new next_to_clean.
6548 */
6549 smp_mb();
6550 if (__netif_subqueue_stopped(tx_ring->netdev,
6551 tx_ring->queue_index) &&
6552 !(test_bit(__IGB_DOWN, &adapter->state))) {
6553 netif_wake_subqueue(tx_ring->netdev,
6554 tx_ring->queue_index);
6555
6556 u64_stats_update_begin(&tx_ring->tx_syncp);
6557 tx_ring->tx_stats.restart_queue++;
6558 u64_stats_update_end(&tx_ring->tx_syncp);
6559 }
6560 }
6561
6562 return !!budget;
9d5c8243
AK		 6563}
6564
cbc8e55f 6565/**
b980ac18
JK		 6566 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6567 * @rx_ring: rx descriptor ring to store buffers on
6568 * @old_buff: donor buffer to have page reused
cbc8e55f 6569 *
b980ac18 6570 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6571 **/
6572static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6573 struct igb_rx_buffer *old_buff)
6574{
6575 struct igb_rx_buffer *new_buff;
6576 u16 nta = rx_ring->next_to_alloc;
6577
6578 new_buff = &rx_ring->rx_buffer_info[nta];
6579
6580 /* update, and store next to alloc */
6581 nta++;
6582 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6583
6584 /* transfer page from old buffer to new buffer */
a1f63473 6585 *new_buff = *old_buff;
cbc8e55f
AD		 6586
6587 /* sync the buffer for use by the device */
6588 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6589 old_buff->page_offset,
de78d1f9 6590 IGB_RX_BUFSZ,
cbc8e55f
AD		 6591 DMA_FROM_DEVICE);
6592}
6593
95dd44b4
AD		 6594static inline bool igb_page_is_reserved(struct page *page)
6595{
2f064f34 6596 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6597}
6598
74e238ea
AD		 6599static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6600 struct page *page,
6601 unsigned int truesize)
6602{
6603 /* avoid re-using remote pages */
95dd44b4 6604 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6605 return false;
6606
74e238ea
AD		 6607#if (PAGE_SIZE < 8192)
6608 /* if we are only owner of page we can reuse it */
6609 if (unlikely(page_count(page) != 1))
6610 return false;
6611
6612 /* flip page offset to other buffer */
6613 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6614#else
6615 /* move offset up to the next cache line */
6616 rx_buffer->page_offset += truesize;
6617
6618 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6619 return false;
74e238ea
AD		 6620#endif
6621
95dd44b4
AD		 6622 /* Even if we own the page, we are not allowed to use atomic_set()
6623 * This would break get_page_unless_zero() users.
6624 */
6625 atomic_inc(&page->_count);
6626
74e238ea
AD		 6627 return true;
6628}
6629
cbc8e55f 6630/**
b980ac18
JK		 6631 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6632 * @rx_ring: rx descriptor ring to transact packets on
6633 * @rx_buffer: buffer containing page to add
6634 * @rx_desc: descriptor containing length of buffer written by hardware
6635 * @skb: sk_buff to place the data into
cbc8e55f 6636 *
b980ac18
JK		 6637 * This function will add the data contained in rx_buffer->page to the skb.
6638 * This is done either through a direct copy if the data in the buffer is
6639 * less than the skb header size, otherwise it will just attach the page as
6640 * a frag to the skb.
cbc8e55f 6641 *
b980ac18
JK		 6642 * The function will then update the page offset if necessary and return
6643 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6644 **/
6645static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6646 struct igb_rx_buffer *rx_buffer,
6647 union e1000_adv_rx_desc *rx_desc,
6648 struct sk_buff *skb)
6649{
6650 struct page *page = rx_buffer->page;
f56e7bba 6651 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6652 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6653#if (PAGE_SIZE < 8192)
6654 unsigned int truesize = IGB_RX_BUFSZ;
6655#else
f56e7bba 6656 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6657#endif
f56e7bba 6658 unsigned int pull_len;
cbc8e55f 6659
f56e7bba
AD		 6660 if (unlikely(skb_is_nonlinear(skb)))
6661 goto add_tail_frag;
cbc8e55f 6662
f56e7bba
AD		 6663 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6664 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6665 va += IGB_TS_HDR_LEN;
6666 size -= IGB_TS_HDR_LEN;
6667 }
cbc8e55f 6668
f56e7bba 6669 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6670 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6671
95dd44b4
AD		 6672 /* page is not reserved, we can reuse buffer as-is */
6673 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6674 return true;
6675
6676 /* this page cannot be reused so discard it */
95dd44b4 6677 __free_page(page);
cbc8e55f
AD		 6678 return false;
6679 }
6680
f56e7bba
AD		 6681 /* we need the header to contain the greater of either ETH_HLEN or
6682 * 60 bytes if the skb->len is less than 60 for skb_pad.
6683 */
6684 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6685
6686 /* align pull length to size of long to optimize memcpy performance */
6687 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6688
6689 /* update all of the pointers */
6690 va += pull_len;
6691 size -= pull_len;
6692
6693add_tail_frag:
cbc8e55f 6694 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6695 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6696
74e238ea
AD		 6697 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6698}
cbc8e55f 6699
2e334eee
AD		 6700static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6701 union e1000_adv_rx_desc *rx_desc,
6702 struct sk_buff *skb)
6703{
6704 struct igb_rx_buffer *rx_buffer;
6705 struct page *page;
6706
6707 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6708 page = rx_buffer->page;
6709 prefetchw(page);
6710
6711 if (likely(!skb)) {
6712 void *page_addr = page_address(page) +
6713 rx_buffer->page_offset;
6714
6715 /* prefetch first cache line of first page */
6716 prefetch(page_addr);
6717#if L1_CACHE_BYTES < 128
6718 prefetch(page_addr + L1_CACHE_BYTES);
6719#endif
6720
6721 /* allocate a skb to store the frags */
67fd893e 6722 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6723 if (unlikely(!skb)) {
6724 rx_ring->rx_stats.alloc_failed++;
6725 return NULL;
6726 }
6727
b980ac18 6728 /* we will be copying header into skb->data in
2e334eee
AD		 6729 * pskb_may_pull so it is in our interest to prefetch
6730 * it now to avoid a possible cache miss
6731 */
6732 prefetchw(skb->data);
6733 }
6734
6735 /* we are reusing so sync this buffer for CPU use */
6736 dma_sync_single_range_for_cpu(rx_ring->dev,
6737 rx_buffer->dma,
6738 rx_buffer->page_offset,
de78d1f9 6739 IGB_RX_BUFSZ,
2e334eee
AD		 6740 DMA_FROM_DEVICE);
6741
6742 /* pull page into skb */
6743 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6744 /* hand second half of page back to the ring */
6745 igb_reuse_rx_page(rx_ring, rx_buffer);
6746 } else {
6747 /* we are not reusing the buffer so unmap it */
6748 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6749 PAGE_SIZE, DMA_FROM_DEVICE);
6750 }
6751
6752 /* clear contents of rx_buffer */
6753 rx_buffer->page = NULL;
6754
6755 return skb;
6756}
6757
cd392f5c 6758static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6759 union e1000_adv_rx_desc *rx_desc,
6760 struct sk_buff *skb)
9d5c8243 6761{
bc8acf2c 6762 skb_checksum_none_assert(skb);
9d5c8243 6763
294e7d78 6764 /* Ignore Checksum bit is set */
3ceb90fd 6765 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6766 return;
6767
6768 /* Rx checksum disabled via ethtool */
6769 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6770 return;
85ad76b2 6771
9d5c8243 6772 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6773 if (igb_test_staterr(rx_desc,
6774 E1000_RXDEXT_STATERR_TCPE |
6775 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6776 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6777 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6778 * packets, (aka let the stack check the crc32c)
6779 */
866cff06
AD		 6780 if (!((skb->len == 60) &&
6781 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6782 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6783 ring->rx_stats.csum_err++;
12dcd86b
ED		 6784 u64_stats_update_end(&ring->rx_syncp);
6785 }
9d5c8243 6786 /* let the stack verify checksum errors */
9d5c8243
AK		 6787 return;
6788 }
6789 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6790 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6791 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6792 skb->ip_summed = CHECKSUM_UNNECESSARY;
6793
3ceb90fd
AD		 6794 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6795 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6796}
6797
077887c3
AD		 6798static inline void igb_rx_hash(struct igb_ring *ring,
6799 union e1000_adv_rx_desc *rx_desc,
6800 struct sk_buff *skb)
6801{
6802 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6803 skb_set_hash(skb,
6804 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6805 PKT_HASH_TYPE_L3);
077887c3
AD		 6806}
6807
2e334eee 6808/**
b980ac18
JK		 6809 * igb_is_non_eop - process handling of non-EOP buffers
6810 * @rx_ring: Rx ring being processed
6811 * @rx_desc: Rx descriptor for current buffer
6812 * @skb: current socket buffer containing buffer in progress
2e334eee 6813 *
b980ac18
JK		 6814 * This function updates next to clean. If the buffer is an EOP buffer
6815 * this function exits returning false, otherwise it will place the
6816 * sk_buff in the next buffer to be chained and return true indicating
6817 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6818 **/
6819static bool igb_is_non_eop(struct igb_ring *rx_ring,
6820 union e1000_adv_rx_desc *rx_desc)
6821{
6822 u32 ntc = rx_ring->next_to_clean + 1;
6823
6824 /* fetch, update, and store next to clean */
6825 ntc = (ntc < rx_ring->count) ? ntc : 0;
6826 rx_ring->next_to_clean = ntc;
6827
6828 prefetch(IGB_RX_DESC(rx_ring, ntc));
6829
6830 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6831 return false;
6832
6833 return true;
6834}
6835
1a1c225b 6836/**
b980ac18
JK		 6837 * igb_cleanup_headers - Correct corrupted or empty headers
6838 * @rx_ring: rx descriptor ring packet is being transacted on
6839 * @rx_desc: pointer to the EOP Rx descriptor
6840 * @skb: pointer to current skb being fixed
1a1c225b 6841 *
b980ac18
JK		 6842 * Address the case where we are pulling data in on pages only
6843 * and as such no data is present in the skb header.
1a1c225b 6844 *
b980ac18
JK		 6845 * In addition if skb is not at least 60 bytes we need to pad it so that
6846 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6847 *
b980ac18 6848 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6849 **/
6850static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6851 union e1000_adv_rx_desc *rx_desc,
6852 struct sk_buff *skb)
6853{
1a1c225b
AD		 6854 if (unlikely((igb_test_staterr(rx_desc,
6855 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6856 struct net_device *netdev = rx_ring->netdev;
6857 if (!(netdev->features & NETIF_F_RXALL)) {
6858 dev_kfree_skb_any(skb);
6859 return true;
6860 }
6861 }
6862
a94d9e22
AD		 6863 /* if eth_skb_pad returns an error the skb was freed */
6864 if (eth_skb_pad(skb))
6865 return true;
1a1c225b
AD		 6866
6867 return false;
2d94d8ab
AD		 6868}
6869
db2ee5bd 6870/**
b980ac18
JK		 6871 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6872 * @rx_ring: rx descriptor ring packet is being transacted on
6873 * @rx_desc: pointer to the EOP Rx descriptor
6874 * @skb: pointer to current skb being populated
db2ee5bd 6875 *
b980ac18
JK		 6876 * This function checks the ring, descriptor, and packet information in
6877 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6878 * other fields within the skb.
db2ee5bd
AD		 6879 **/
6880static void igb_process_skb_fields(struct igb_ring *rx_ring,
6881 union e1000_adv_rx_desc *rx_desc,
6882 struct sk_buff *skb)
6883{
6884 struct net_device *dev = rx_ring->netdev;
6885
6886 igb_rx_hash(rx_ring, rx_desc, skb);
6887
6888 igb_rx_checksum(rx_ring, rx_desc, skb);
6889
5499a968
JK		 6890 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6891 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6892 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6893
f646968f 6894 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6895 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6896 u16 vid;
9005df38 6897
db2ee5bd
AD		 6898 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6899 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6900 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6901 else
6902 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6903
86a9bad3 6904 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6905 }
6906
6907 skb_record_rx_queue(skb, rx_ring->queue_index);
6908
6909 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6910}
6911
32b3e08f 6912static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6913{
0ba82994 6914 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6915 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6916 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6917 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6918
57ba34c9 6919 while (likely(total_packets < budget)) {
2e334eee 6920 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6921
2e334eee
AD		 6922 /* return some buffers to hardware, one at a time is too slow */
6923 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6924 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6925 cleaned_count = 0;
6926 }
bf36c1a0 6927
2e334eee 6928 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6929
124b74c1 6930 if (!rx_desc->wb.upper.status_error)
2e334eee 6931 break;
9d5c8243 6932
74e238ea
AD		 6933 /* This memory barrier is needed to keep us from reading
6934 * any other fields out of the rx_desc until we know the
124b74c1 6935 * descriptor has been written back
74e238ea 6936 */
124b74c1 6937 dma_rmb();
74e238ea 6938
2e334eee 6939 /* retrieve a buffer from the ring */
f9d40f6a 6940 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6941
2e334eee
AD		 6942 /* exit if we failed to retrieve a buffer */
6943 if (!skb)
6944 break;
1a1c225b 6945
2e334eee 6946 cleaned_count++;
1a1c225b 6947
2e334eee
AD		 6948 /* fetch next buffer in frame if non-eop */
6949 if (igb_is_non_eop(rx_ring, rx_desc))
6950 continue;
1a1c225b
AD		 6951
6952 /* verify the packet layout is correct */
6953 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6954 skb = NULL;
6955 continue;
9d5c8243 6956 }
9d5c8243 6957
db2ee5bd 6958 /* probably a little skewed due to removing CRC */
3ceb90fd 6959 total_bytes += skb->len;
3ceb90fd 6960
db2ee5bd
AD		 6961 /* populate checksum, timestamp, VLAN, and protocol */
6962 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6963
b2cb09b1 6964 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6965
1a1c225b
AD		 6966 /* reset skb pointer */
6967 skb = NULL;
6968
2e334eee
AD		 6969 /* update budget accounting */
6970 total_packets++;
57ba34c9 6971 }
bf36c1a0 6972
1a1c225b
AD		 6973 /* place incomplete frames back on ring for completion */
6974 rx_ring->skb = skb;
6975
12dcd86b 6976 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6977 rx_ring->rx_stats.packets += total_packets;
6978 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6979 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6980 q_vector->rx.total_packets += total_packets;
6981 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6982
6983 if (cleaned_count)
cd392f5c 6984 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6985
32b3e08f 6986 return total_packets;
9d5c8243
AK		 6987}
6988
c023cd88 6989static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6990 struct igb_rx_buffer *bi)
c023cd88
AD		 6991{
6992 struct page *page = bi->page;
cbc8e55f 6993 dma_addr_t dma;
c023cd88 6994
cbc8e55f
AD		 6995 /* since we are recycling buffers we should seldom need to alloc */
6996 if (likely(page))
c023cd88
AD		 6997 return true;
6998
cbc8e55f 6999 /* alloc new page for storage */
42b17f09 7000 page = dev_alloc_page();
cbc8e55f
AD		 7001 if (unlikely(!page)) {
7002 rx_ring->rx_stats.alloc_failed++;
7003 return false;
c023cd88
AD		 7004 }
7005
cbc8e55f
AD		 7006 /* map page for use */
7007 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7008
b980ac18 7009 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7010 * there isn't much point in holding memory we can't use
7011 */
1a1c225b 7012 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7013 __free_page(page);
7014
c023cd88
AD		 7015 rx_ring->rx_stats.alloc_failed++;
7016 return false;
7017 }
7018
1a1c225b 7019 bi->dma = dma;
cbc8e55f
AD		 7020 bi->page = page;
7021 bi->page_offset = 0;
1a1c225b 7022
c023cd88
AD		 7023 return true;
7024}
7025
9d5c8243 7026/**
b980ac18
JK		 7027 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7028 * @adapter: address of board private structure
9d5c8243 7029 **/
cd392f5c 7030void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7031{
9d5c8243 7032 union e1000_adv_rx_desc *rx_desc;
06034649 7033 struct igb_rx_buffer *bi;
c023cd88 7034 u16 i = rx_ring->next_to_use;
9d5c8243 7035
cbc8e55f
AD		 7036 /* nothing to do */
7037 if (!cleaned_count)
7038 return;
7039
60136906 7040 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7041 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7042 i -= rx_ring->count;
9d5c8243 7043
cbc8e55f 7044 do {
1a1c225b 7045 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7046 break;
9d5c8243 7047
b980ac18 7048 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7049 * because each write-back erases this info.
7050 */
f9d40f6a 7051 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7052
c023cd88
AD		 7053 rx_desc++;
7054 bi++;
9d5c8243 7055 i++;
c023cd88 7056 if (unlikely(!i)) {
60136906 7057 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7058 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7059 i -= rx_ring->count;
7060 }
7061
95dd44b4
AD		 7062 /* clear the status bits for the next_to_use descriptor */
7063 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7064
7065 cleaned_count--;
7066 } while (cleaned_count);
9d5c8243 7067
c023cd88
AD		 7068 i += rx_ring->count;
7069
9d5c8243 7070 if (rx_ring->next_to_use != i) {
cbc8e55f 7071 /* record the next descriptor to use */
9d5c8243 7072 rx_ring->next_to_use = i;
9d5c8243 7073
cbc8e55f
AD		 7074 /* update next to alloc since we have filled the ring */
7075 rx_ring->next_to_alloc = i;
7076
b980ac18 7077 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7078 * know there are new descriptors to fetch. (Only
7079 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7080 * such as IA-64).
7081 */
9d5c8243 7082 wmb();
fce99e34 7083 writel(i, rx_ring->tail);
9d5c8243
AK		 7084 }
7085}
7086
7087/**
7088 * igb_mii_ioctl -
7089 * @netdev:
7090 * @ifreq:
7091 * @cmd:
7092 **/
7093static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7094{
7095 struct igb_adapter *adapter = netdev_priv(netdev);
7096 struct mii_ioctl_data *data = if_mii(ifr);
7097
7098 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7099 return -EOPNOTSUPP;
7100
7101 switch (cmd) {
7102 case SIOCGMIIPHY:
7103 data->phy_id = adapter->hw.phy.addr;
7104 break;
7105 case SIOCGMIIREG:
f5f4cf08 7106 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7107 &data->val_out))
9d5c8243
AK		 7108 return -EIO;
7109 break;
7110 case SIOCSMIIREG:
7111 default:
7112 return -EOPNOTSUPP;
7113 }
7114 return 0;
7115}
7116
7117/**
7118 * igb_ioctl -
7119 * @netdev:
7120 * @ifreq:
7121 * @cmd:
7122 **/
7123static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7124{
7125 switch (cmd) {
7126 case SIOCGMIIPHY:
7127 case SIOCGMIIREG:
7128 case SIOCSMIIREG:
7129 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7130 case SIOCGHWTSTAMP:
7131 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7132 case SIOCSHWTSTAMP:
6ab5f7b2 7133 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7134 default:
7135 return -EOPNOTSUPP;
7136 }
7137}
7138
94826487
TF		 7139void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7140{
7141 struct igb_adapter *adapter = hw->back;
7142
7143 pci_read_config_word(adapter->pdev, reg, value);
7144}
7145
7146void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7147{
7148 struct igb_adapter *adapter = hw->back;
7149
7150 pci_write_config_word(adapter->pdev, reg, *value);
7151}
7152
009bc06e
AD		 7153s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7154{
7155 struct igb_adapter *adapter = hw->back;
009bc06e 7156
23d028cc 7157 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7158 return -E1000_ERR_CONFIG;
7159
009bc06e
AD		 7160 return 0;
7161}
7162
7163s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7164{
7165 struct igb_adapter *adapter = hw->back;
009bc06e 7166
23d028cc 7167 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7168 return -E1000_ERR_CONFIG;
7169
009bc06e
AD		 7170 return 0;
7171}
7172
c8f44aff 7173static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7174{
7175 struct igb_adapter *adapter = netdev_priv(netdev);
7176 struct e1000_hw *hw = &adapter->hw;
7177 u32 ctrl, rctl;
f646968f 7178 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7179
5faf030c 7180 if (enable) {
9d5c8243
AK		 7181 /* enable VLAN tag insert/strip */
7182 ctrl = rd32(E1000_CTRL);
7183 ctrl |= E1000_CTRL_VME;
7184 wr32(E1000_CTRL, ctrl);
7185
51466239 7186 /* Disable CFI check */
9d5c8243 7187 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7188 rctl &= ~E1000_RCTL_CFIEN;
7189 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7190 } else {
7191 /* disable VLAN tag insert/strip */
7192 ctrl = rd32(E1000_CTRL);
7193 ctrl &= ~E1000_CTRL_VME;
7194 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7195 }
7196
e1739522 7197 igb_rlpml_set(adapter);
9d5c8243
AK		 7198}
7199
80d5c368
PM		 7200static int igb_vlan_rx_add_vid(struct net_device *netdev,
7201 __be16 proto, u16 vid)
9d5c8243
AK		 7202{
7203 struct igb_adapter *adapter = netdev_priv(netdev);
7204 struct e1000_hw *hw = &adapter->hw;
4ae196df 7205 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7206
51466239
AD		 7207 /* attempt to add filter to vlvf array */
7208 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7209
51466239
AD		 7210 /* add the filter since PF can receive vlans w/o entry in vlvf */
7211 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7212
7213 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7214
7215 return 0;
9d5c8243
AK		 7216}
7217
80d5c368
PM		 7218static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7219 __be16 proto, u16 vid)
9d5c8243
AK		 7220{
7221 struct igb_adapter *adapter = netdev_priv(netdev);
7222 struct e1000_hw *hw = &adapter->hw;
4ae196df 7223 int pf_id = adapter->vfs_allocated_count;
51466239 7224 s32 err;
9d5c8243 7225
51466239
AD		 7226 /* remove vlan from VLVF table array */
7227 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7228
51466239
AD		 7229 /* if vid was not present in VLVF just remove it from table */
7230 if (err)
4ae196df 7231 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7232
7233 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7234
7235 return 0;
9d5c8243
AK		 7236}
7237
7238static void igb_restore_vlan(struct igb_adapter *adapter)
7239{
b2cb09b1 7240 u16 vid;
9d5c8243 7241
5faf030c
AD		 7242 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7243
b2cb09b1 7244 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7245 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7246}
7247
14ad2513 7248int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7249{
090b1795 7250 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7251 struct e1000_mac_info *mac = &adapter->hw.mac;
7252
7253 mac->autoneg = 0;
7254
14ad2513 7255 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7256 * for the switch() below to work
7257 */
14ad2513
DD		 7258 if ((spd & 1) || (dplx & ~1))
7259 goto err_inval;
7260
f502ef7d
AA		 7261 /* Fiber NIC's only allow 1000 gbps Full duplex
7262 * and 100Mbps Full duplex for 100baseFx sfp
7263 */
7264 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7265 switch (spd + dplx) {
7266 case SPEED_10 + DUPLEX_HALF:
7267 case SPEED_10 + DUPLEX_FULL:
7268 case SPEED_100 + DUPLEX_HALF:
7269 goto err_inval;
7270 default:
7271 break;
7272 }
7273 }
cd2638a8 7274
14ad2513 7275 switch (spd + dplx) {
9d5c8243
AK		 7276 case SPEED_10 + DUPLEX_HALF:
7277 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7278 break;
7279 case SPEED_10 + DUPLEX_FULL:
7280 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7281 break;
7282 case SPEED_100 + DUPLEX_HALF:
7283 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7284 break;
7285 case SPEED_100 + DUPLEX_FULL:
7286 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7287 break;
7288 case SPEED_1000 + DUPLEX_FULL:
7289 mac->autoneg = 1;
7290 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7291 break;
7292 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7293 default:
14ad2513 7294 goto err_inval;
9d5c8243 7295 }
8376dad0
JB		 7296
7297 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7298 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7299
9d5c8243 7300 return 0;
14ad2513
DD		 7301
7302err_inval:
7303 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7304 return -EINVAL;
9d5c8243
AK		 7305}
7306
749ab2cd
YZ		 7307static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7308 bool runtime)
9d5c8243
AK		 7309{
7310 struct net_device *netdev = pci_get_drvdata(pdev);
7311 struct igb_adapter *adapter = netdev_priv(netdev);
7312 struct e1000_hw *hw = &adapter->hw;
2d064c06 7313 u32 ctrl, rctl, status;
749ab2cd 7314 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7315#ifdef CONFIG_PM
7316 int retval = 0;
7317#endif
7318
7319 netif_device_detach(netdev);
7320
a88f10ec 7321 if (netif_running(netdev))
749ab2cd 7322 __igb_close(netdev, true);
a88f10ec 7323
047e0030 7324 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7325
7326#ifdef CONFIG_PM
7327 retval = pci_save_state(pdev);
7328 if (retval)
7329 return retval;
7330#endif
7331
7332 status = rd32(E1000_STATUS);
7333 if (status & E1000_STATUS_LU)
7334 wufc &= ~E1000_WUFC_LNKC;
7335
7336 if (wufc) {
7337 igb_setup_rctl(adapter);
ff41f8dc 7338 igb_set_rx_mode(netdev);
9d5c8243
AK		 7339
7340 /* turn on all-multi mode if wake on multicast is enabled */
7341 if (wufc & E1000_WUFC_MC) {
7342 rctl = rd32(E1000_RCTL);
7343 rctl |= E1000_RCTL_MPE;
7344 wr32(E1000_RCTL, rctl);
7345 }
7346
7347 ctrl = rd32(E1000_CTRL);
7348 /* advertise wake from D3Cold */
7349 #define E1000_CTRL_ADVD3WUC 0x00100000
7350 /* phy power management enable */
7351 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7352 ctrl |= E1000_CTRL_ADVD3WUC;
7353 wr32(E1000_CTRL, ctrl);
7354
9d5c8243 7355 /* Allow time for pending master requests to run */
330a6d6a 7356 igb_disable_pcie_master(hw);
9d5c8243
AK		 7357
7358 wr32(E1000_WUC, E1000_WUC_PME_EN);
7359 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7360 } else {
7361 wr32(E1000_WUC, 0);
7362 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7363 }
7364
3fe7c4c9
RW		 7365 *enable_wake = wufc || adapter->en_mng_pt;
7366 if (!*enable_wake)
88a268c1
NN		 7367 igb_power_down_link(adapter);
7368 else
7369 igb_power_up_link(adapter);
9d5c8243
AK		 7370
7371 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7372 * would have already happened in close and is redundant.
7373 */
9d5c8243
AK		 7374 igb_release_hw_control(adapter);
7375
7376 pci_disable_device(pdev);
7377
9d5c8243
AK		 7378 return 0;
7379}
7380
7381#ifdef CONFIG_PM
d9dd966d 7382#ifdef CONFIG_PM_SLEEP
749ab2cd 7383static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7384{
7385 int retval;
7386 bool wake;
749ab2cd 7387 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7388
749ab2cd 7389 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7390 if (retval)
7391 return retval;
7392
7393 if (wake) {
7394 pci_prepare_to_sleep(pdev);
7395 } else {
7396 pci_wake_from_d3(pdev, false);
7397 pci_set_power_state(pdev, PCI_D3hot);
7398 }
7399
7400 return 0;
7401}
d9dd966d 7402#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7403
749ab2cd 7404static int igb_resume(struct device *dev)
9d5c8243 7405{
749ab2cd 7406 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7407 struct net_device *netdev = pci_get_drvdata(pdev);
7408 struct igb_adapter *adapter = netdev_priv(netdev);
7409 struct e1000_hw *hw = &adapter->hw;
7410 u32 err;
7411
7412 pci_set_power_state(pdev, PCI_D0);
7413 pci_restore_state(pdev);
b94f2d77 7414 pci_save_state(pdev);
42bfd33a 7415
17a402a0
CW		 7416 if (!pci_device_is_present(pdev))
7417 return -ENODEV;
aed5dec3 7418 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7419 if (err) {
7420 dev_err(&pdev->dev,
7421 "igb: Cannot enable PCI device from suspend\n");
7422 return err;
7423 }
7424 pci_set_master(pdev);
7425
7426 pci_enable_wake(pdev, PCI_D3hot, 0);
7427 pci_enable_wake(pdev, PCI_D3cold, 0);
7428
53c7d064 7429 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec 7430 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3eb14ea8 7431 rtnl_unlock();
a88f10ec 7432 return -ENOMEM;
9d5c8243
AK		 7433 }
7434
9d5c8243 7435 igb_reset(adapter);
a8564f03
AD		 7436
7437 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7438 * driver.
7439 */
a8564f03
AD		 7440 igb_get_hw_control(adapter);
7441
9d5c8243
AK		 7442 wr32(E1000_WUS, ~0);
7443
749ab2cd 7444 if (netdev->flags & IFF_UP) {
0c2cc02e 7445 rtnl_lock();
749ab2cd 7446 err = __igb_open(netdev, true);
0c2cc02e 7447 rtnl_unlock();
a88f10ec
AD		 7448 if (err)
7449 return err;
7450 }
9d5c8243
AK		 7451
7452 netif_device_attach(netdev);
749ab2cd
YZ		 7453 return 0;
7454}
7455
749ab2cd
YZ		 7456static int igb_runtime_idle(struct device *dev)
7457{
7458 struct pci_dev *pdev = to_pci_dev(dev);
7459 struct net_device *netdev = pci_get_drvdata(pdev);
7460 struct igb_adapter *adapter = netdev_priv(netdev);
7461
7462 if (!igb_has_link(adapter))
7463 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7464
7465 return -EBUSY;
7466}
7467
7468static int igb_runtime_suspend(struct device *dev)
7469{
7470 struct pci_dev *pdev = to_pci_dev(dev);
7471 int retval;
7472 bool wake;
7473
7474 retval = __igb_shutdown(pdev, &wake, 1);
7475 if (retval)
7476 return retval;
7477
7478 if (wake) {
7479 pci_prepare_to_sleep(pdev);
7480 } else {
7481 pci_wake_from_d3(pdev, false);
7482 pci_set_power_state(pdev, PCI_D3hot);
7483 }
9d5c8243 7484
9d5c8243
AK		 7485 return 0;
7486}
749ab2cd
YZ		 7487
7488static int igb_runtime_resume(struct device *dev)
7489{
7490 return igb_resume(dev);
7491}
d61c81cb 7492#endif /* CONFIG_PM */
9d5c8243
AK		 7493
7494static void igb_shutdown(struct pci_dev *pdev)
7495{
3fe7c4c9
RW		 7496 bool wake;
7497
749ab2cd 7498 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7499
7500 if (system_state == SYSTEM_POWER_OFF) {
7501 pci_wake_from_d3(pdev, wake);
7502 pci_set_power_state(pdev, PCI_D3hot);
7503 }
9d5c8243
AK		 7504}
7505
fa44f2f1
GR		 7506#ifdef CONFIG_PCI_IOV
7507static int igb_sriov_reinit(struct pci_dev *dev)
7508{
7509 struct net_device *netdev = pci_get_drvdata(dev);
7510 struct igb_adapter *adapter = netdev_priv(netdev);
7511 struct pci_dev *pdev = adapter->pdev;
7512
7513 rtnl_lock();
7514
7515 if (netif_running(netdev))
7516 igb_close(netdev);
76252723
SA		 7517 else
7518 igb_reset(adapter);
fa44f2f1
GR		 7519
7520 igb_clear_interrupt_scheme(adapter);
7521
7522 igb_init_queue_configuration(adapter);
7523
7524 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7525 rtnl_unlock();
fa44f2f1
GR		 7526 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7527 return -ENOMEM;
7528 }
7529
7530 if (netif_running(netdev))
7531 igb_open(netdev);
7532
7533 rtnl_unlock();
7534
7535 return 0;
7536}
7537
7538static int igb_pci_disable_sriov(struct pci_dev *dev)
7539{
7540 int err = igb_disable_sriov(dev);
7541
7542 if (!err)
7543 err = igb_sriov_reinit(dev);
7544
7545 return err;
7546}
7547
7548static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7549{
7550 int err = igb_enable_sriov(dev, num_vfs);
7551
7552 if (err)
7553 goto out;
7554
7555 err = igb_sriov_reinit(dev);
7556 if (!err)
7557 return num_vfs;
7558
7559out:
7560 return err;
7561}
7562
7563#endif
7564static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7565{
7566#ifdef CONFIG_PCI_IOV
7567 if (num_vfs == 0)
7568 return igb_pci_disable_sriov(dev);
7569 else
7570 return igb_pci_enable_sriov(dev, num_vfs);
7571#endif
7572 return 0;
7573}
7574
9d5c8243 7575#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7576/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7577 * without having to re-enable interrupts. It's not called while
7578 * the interrupt routine is executing.
7579 */
7580static void igb_netpoll(struct net_device *netdev)
7581{
7582 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7583 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7584 struct igb_q_vector *q_vector;
9d5c8243 7585 int i;
9d5c8243 7586
047e0030 7587 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7588 q_vector = adapter->q_vector[i];
cd14ef54 7589 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7590 wr32(E1000_EIMC, q_vector->eims_value);
7591 else
7592 igb_irq_disable(adapter);
047e0030 7593 napi_schedule(&q_vector->napi);
eebbbdba 7594 }
9d5c8243
AK		 7595}
7596#endif /* CONFIG_NET_POLL_CONTROLLER */
7597
7598/**
b980ac18
JK		 7599 * igb_io_error_detected - called when PCI error is detected
7600 * @pdev: Pointer to PCI device
7601 * @state: The current pci connection state
9d5c8243 7602 *
b980ac18
JK		 7603 * This function is called after a PCI bus error affecting
7604 * this device has been detected.
7605 **/
9d5c8243
AK		 7606static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7607 pci_channel_state_t state)
7608{
7609 struct net_device *netdev = pci_get_drvdata(pdev);
7610 struct igb_adapter *adapter = netdev_priv(netdev);
7611
7612 netif_device_detach(netdev);
7613
59ed6eec
AD		 7614 if (state == pci_channel_io_perm_failure)
7615 return PCI_ERS_RESULT_DISCONNECT;
7616
9d5c8243
AK		 7617 if (netif_running(netdev))
7618 igb_down(adapter);
7619 pci_disable_device(pdev);
7620
7621 /* Request a slot slot reset. */
7622 return PCI_ERS_RESULT_NEED_RESET;
7623}
7624
7625/**
b980ac18
JK		 7626 * igb_io_slot_reset - called after the pci bus has been reset.
7627 * @pdev: Pointer to PCI device
9d5c8243 7628 *
b980ac18
JK		 7629 * Restart the card from scratch, as if from a cold-boot. Implementation
7630 * resembles the first-half of the igb_resume routine.
7631 **/
9d5c8243
AK		 7632static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7633{
7634 struct net_device *netdev = pci_get_drvdata(pdev);
7635 struct igb_adapter *adapter = netdev_priv(netdev);
7636 struct e1000_hw *hw = &adapter->hw;
40a914fa 7637 pci_ers_result_t result;
42bfd33a 7638 int err;
9d5c8243 7639
aed5dec3 7640 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7641 dev_err(&pdev->dev,
7642 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7643 result = PCI_ERS_RESULT_DISCONNECT;
7644 } else {
7645 pci_set_master(pdev);
7646 pci_restore_state(pdev);
b94f2d77 7647 pci_save_state(pdev);
9d5c8243 7648
40a914fa
AD		 7649 pci_enable_wake(pdev, PCI_D3hot, 0);
7650 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7651
40a914fa
AD		 7652 igb_reset(adapter);
7653 wr32(E1000_WUS, ~0);
7654 result = PCI_ERS_RESULT_RECOVERED;
7655 }
9d5c8243 7656
ea943d41
JK		 7657 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7658 if (err) {
b980ac18
JK		 7659 dev_err(&pdev->dev,
7660 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7661 err);
ea943d41
JK		 7662 /* non-fatal, continue */
7663 }
40a914fa
AD		 7664
7665 return result;
9d5c8243
AK		 7666}
7667
7668/**
b980ac18
JK		 7669 * igb_io_resume - called when traffic can start flowing again.
7670 * @pdev: Pointer to PCI device
9d5c8243 7671 *
b980ac18
JK		 7672 * This callback is called when the error recovery driver tells us that
7673 * its OK to resume normal operation. Implementation resembles the
7674 * second-half of the igb_resume routine.
9d5c8243
AK		 7675 */
7676static void igb_io_resume(struct pci_dev *pdev)
7677{
7678 struct net_device *netdev = pci_get_drvdata(pdev);
7679 struct igb_adapter *adapter = netdev_priv(netdev);
7680
9d5c8243
AK		 7681 if (netif_running(netdev)) {
7682 if (igb_up(adapter)) {
7683 dev_err(&pdev->dev, "igb_up failed after reset\n");
7684 return;
7685 }
7686 }
7687
7688 netif_device_attach(netdev);
7689
7690 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7691 * driver.
7692 */
9d5c8243 7693 igb_get_hw_control(adapter);
9d5c8243
AK		 7694}
7695
26ad9178 7696static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7697 u8 qsel)
26ad9178
AD		 7698{
7699 u32 rar_low, rar_high;
7700 struct e1000_hw *hw = &adapter->hw;
7701
7702 /* HW expects these in little endian so we reverse the byte order
7703 * from network order (big endian) to little endian
7704 */
7705 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7706 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7707 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7708
7709 /* Indicate to hardware the Address is Valid. */
7710 rar_high |= E1000_RAH_AV;
7711
7712 if (hw->mac.type == e1000_82575)
7713 rar_high |= E1000_RAH_POOL_1 * qsel;
7714 else
7715 rar_high |= E1000_RAH_POOL_1 << qsel;
7716
7717 wr32(E1000_RAL(index), rar_low);
7718 wrfl();
7719 wr32(E1000_RAH(index), rar_high);
7720 wrfl();
7721}
7722
4ae196df 7723static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7724 int vf, unsigned char *mac_addr)
4ae196df
AD		 7725{
7726 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7727 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7728 * towards the first, as a result a collision should not be possible
7729 */
ff41f8dc 7730 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7731
37680117 7732 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7733
26ad9178 7734 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7735
7736 return 0;
7737}
7738
8151d294
WM		 7739static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7740{
7741 struct igb_adapter *adapter = netdev_priv(netdev);
7742 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7743 return -EINVAL;
7744 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7745 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7746 dev_info(&adapter->pdev->dev,
7747 "Reload the VF driver to make this change effective.");
8151d294 7748 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7749 dev_warn(&adapter->pdev->dev,
7750 "The VF MAC address has been set, but the PF device is not up.\n");
7751 dev_warn(&adapter->pdev->dev,
7752 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7753 }
7754 return igb_set_vf_mac(adapter, vf, mac);
7755}
7756
17dc566c
LL		 7757static int igb_link_mbps(int internal_link_speed)
7758{
7759 switch (internal_link_speed) {
7760 case SPEED_100:
7761 return 100;
7762 case SPEED_1000:
7763 return 1000;
7764 default:
7765 return 0;
7766 }
7767}
7768
7769static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7770 int link_speed)
7771{
7772 int rf_dec, rf_int;
7773 u32 bcnrc_val;
7774
7775 if (tx_rate != 0) {
7776 /* Calculate the rate factor values to set */
7777 rf_int = link_speed / tx_rate;
7778 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7779 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7780 tx_rate;
17dc566c
LL		 7781
7782 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7783 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7784 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7785 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7786 } else {
7787 bcnrc_val = 0;
7788 }
7789
7790 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7791 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7792 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7793 */
7794 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7795 wr32(E1000_RTTBCNRC, bcnrc_val);
7796}
7797
7798static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7799{
7800 int actual_link_speed, i;
7801 bool reset_rate = false;
7802
7803 /* VF TX rate limit was not set or not supported */
7804 if ((adapter->vf_rate_link_speed == 0) ||
7805 (adapter->hw.mac.type != e1000_82576))
7806 return;
7807
7808 actual_link_speed = igb_link_mbps(adapter->link_speed);
7809 if (actual_link_speed != adapter->vf_rate_link_speed) {
7810 reset_rate = true;
7811 adapter->vf_rate_link_speed = 0;
7812 dev_info(&adapter->pdev->dev,
b980ac18 7813 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7814 }
7815
7816 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7817 if (reset_rate)
7818 adapter->vf_data[i].tx_rate = 0;
7819
7820 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7821 adapter->vf_data[i].tx_rate,
7822 actual_link_speed);
17dc566c
LL		 7823 }
7824}
7825
ed616689
SC		 7826static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7827 int min_tx_rate, int max_tx_rate)
8151d294 7828{
17dc566c
LL		 7829 struct igb_adapter *adapter = netdev_priv(netdev);
7830 struct e1000_hw *hw = &adapter->hw;
7831 int actual_link_speed;
7832
7833 if (hw->mac.type != e1000_82576)
7834 return -EOPNOTSUPP;
7835
ed616689
SC		 7836 if (min_tx_rate)
7837 return -EINVAL;
7838
17dc566c
LL		 7839 actual_link_speed = igb_link_mbps(adapter->link_speed);
7840 if ((vf >= adapter->vfs_allocated_count) ||
7841 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7842 (max_tx_rate < 0) ||
7843 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7844 return -EINVAL;
7845
7846 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7847 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7848 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7849
7850 return 0;
8151d294
WM		 7851}
7852
70ea4783
LL		 7853static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7854 bool setting)
7855{
7856 struct igb_adapter *adapter = netdev_priv(netdev);
7857 struct e1000_hw *hw = &adapter->hw;
7858 u32 reg_val, reg_offset;
7859
7860 if (!adapter->vfs_allocated_count)
7861 return -EOPNOTSUPP;
7862
7863 if (vf >= adapter->vfs_allocated_count)
7864 return -EINVAL;
7865
7866 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7867 reg_val = rd32(reg_offset);
7868 if (setting)
7869 reg_val |= ((1 << vf) |
7870 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7871 else
7872 reg_val &= ~((1 << vf) |
7873 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7874 wr32(reg_offset, reg_val);
7875
7876 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7877 return 0;
70ea4783
LL		 7878}
7879
8151d294
WM		 7880static int igb_ndo_get_vf_config(struct net_device *netdev,
7881 int vf, struct ifla_vf_info *ivi)
7882{
7883 struct igb_adapter *adapter = netdev_priv(netdev);
7884 if (vf >= adapter->vfs_allocated_count)
7885 return -EINVAL;
7886 ivi->vf = vf;
7887 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7888 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7889 ivi->min_tx_rate = 0;
8151d294
WM		 7890 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7891 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7892 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7893 return 0;
7894}
7895
4ae196df
AD		 7896static void igb_vmm_control(struct igb_adapter *adapter)
7897{
7898 struct e1000_hw *hw = &adapter->hw;
10d8e907 7899 u32 reg;
4ae196df 7900
52a1dd4d
AD		 7901 switch (hw->mac.type) {
7902 case e1000_82575:
f96a8a0b
CW		 7903 case e1000_i210:
7904 case e1000_i211:
ceb5f13b 7905 case e1000_i354:
52a1dd4d
AD		 7906 default:
7907 /* replication is not supported for 82575 */
4ae196df 7908 return;
52a1dd4d
AD		 7909 case e1000_82576:
7910 /* notify HW that the MAC is adding vlan tags */
7911 reg = rd32(E1000_DTXCTL);
7912 reg |= E1000_DTXCTL_VLAN_ADDED;
7913 wr32(E1000_DTXCTL, reg);
b26141d4 7914 /* Fall through */
52a1dd4d
AD		 7915 case e1000_82580:
7916 /* enable replication vlan tag stripping */
7917 reg = rd32(E1000_RPLOLR);
7918 reg |= E1000_RPLOLR_STRVLAN;
7919 wr32(E1000_RPLOLR, reg);
b26141d4 7920 /* Fall through */
d2ba2ed8
AD		 7921 case e1000_i350:
7922 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7923 break;
7924 }
10d8e907 7925
d4960307
AD		 7926 if (adapter->vfs_allocated_count) {
7927 igb_vmdq_set_loopback_pf(hw, true);
7928 igb_vmdq_set_replication_pf(hw, true);
13800469 7929 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7930 adapter->vfs_allocated_count);
d4960307
AD		 7931 } else {
7932 igb_vmdq_set_loopback_pf(hw, false);
7933 igb_vmdq_set_replication_pf(hw, false);
7934 }
4ae196df
AD		 7935}
7936
b6e0c419
CW		 7937static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7938{
7939 struct e1000_hw *hw = &adapter->hw;
7940 u32 dmac_thr;
7941 u16 hwm;
7942
7943 if (hw->mac.type > e1000_82580) {
7944 if (adapter->flags & IGB_FLAG_DMAC) {
7945 u32 reg;
7946
7947 /* force threshold to 0. */
7948 wr32(E1000_DMCTXTH, 0);
7949
b980ac18 7950 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7951 * than the Rx threshold. Set hwm to PBA - max frame
7952 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7953 */
e8c626e9
MV		 7954 hwm = 64 * pba - adapter->max_frame_size / 16;
7955 if (hwm < 64 * (pba - 6))
7956 hwm = 64 * (pba - 6);
7957 reg = rd32(E1000_FCRTC);
7958 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7959 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7960 & E1000_FCRTC_RTH_COAL_MASK);
7961 wr32(E1000_FCRTC, reg);
7962
b980ac18 7963 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7964 * frame size, capping it at PBA - 10KB.
7965 */
7966 dmac_thr = pba - adapter->max_frame_size / 512;
7967 if (dmac_thr < pba - 10)
7968 dmac_thr = pba - 10;
b6e0c419
CW		 7969 reg = rd32(E1000_DMACR);
7970 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7971 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7972 & E1000_DMACR_DMACTHR_MASK);
7973
7974 /* transition to L0x or L1 if available..*/
7975 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7976
7977 /* watchdog timer= +-1000 usec in 32usec intervals */
7978 reg |= (1000 >> 5);
0c02dd98
MV		 7979
7980 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7981 if (hw->mac.type != e1000_i354)
7982 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7983
b6e0c419
CW		 7984 wr32(E1000_DMACR, reg);
7985
b980ac18 7986 /* no lower threshold to disable
b6e0c419
CW		 7987 * coalescing(smart fifb)-UTRESH=0
7988 */
7989 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7990
7991 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7992
7993 wr32(E1000_DMCTLX, reg);
7994
b980ac18 7995 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7996 * DMA coal
7997 */
7998 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7999 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8000
b980ac18 8001 /* make low power state decision controlled
b6e0c419
CW		 8002 * by DMA coal
8003 */
8004 reg = rd32(E1000_PCIEMISC);
8005 reg &= ~E1000_PCIEMISC_LX_DECISION;
8006 wr32(E1000_PCIEMISC, reg);
8007 } /* endif adapter->dmac is not disabled */
8008 } else if (hw->mac.type == e1000_82580) {
8009 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8010
b6e0c419
CW		 8011 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8012 wr32(E1000_DMACR, 0);
8013 }
8014}
8015
b980ac18
JK		 8016/**
8017 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8018 * @hw: pointer to hardware structure
8019 * @byte_offset: byte offset to read
8020 * @dev_addr: device address
8021 * @data: value read
8022 *
8023 * Performs byte read operation over I2C interface at
8024 * a specified device address.
b980ac18 8025 **/
441fc6fd 8026s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8027 u8 dev_addr, u8 *data)
441fc6fd
CW		 8028{
8029 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8030 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8031 s32 status;
8032 u16 swfw_mask = 0;
8033
8034 if (!this_client)
8035 return E1000_ERR_I2C;
8036
8037 swfw_mask = E1000_SWFW_PHY0_SM;
8038
23d87824 8039 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8040 return E1000_ERR_SWFW_SYNC;
8041
8042 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8043 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8044
8045 if (status < 0)
8046 return E1000_ERR_I2C;
8047 else {
8048 *data = status;
23d87824 8049 return 0;
441fc6fd
CW		 8050 }
8051}
8052
b980ac18
JK		 8053/**
8054 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8055 * @hw: pointer to hardware structure
8056 * @byte_offset: byte offset to write
8057 * @dev_addr: device address
8058 * @data: value to write
8059 *
8060 * Performs byte write operation over I2C interface at
8061 * a specified device address.
b980ac18 8062 **/
441fc6fd 8063s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8064 u8 dev_addr, u8 data)
441fc6fd
CW		 8065{
8066 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8067 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8068 s32 status;
8069 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8070
8071 if (!this_client)
8072 return E1000_ERR_I2C;
8073
23d87824 8074 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8075 return E1000_ERR_SWFW_SYNC;
8076 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8077 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8078
8079 if (status)
8080 return E1000_ERR_I2C;
8081 else
23d87824 8082 return 0;
441fc6fd
CW		 8083
8084}
907b7835
LMV		 8085
8086int igb_reinit_queues(struct igb_adapter *adapter)
8087{
8088 struct net_device *netdev = adapter->netdev;
8089 struct pci_dev *pdev = adapter->pdev;
8090 int err = 0;
8091
8092 if (netif_running(netdev))
8093 igb_close(netdev);
8094
02ef6e1d 8095 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8096
8097 if (igb_init_interrupt_scheme(adapter, true)) {
8098 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8099 return -ENOMEM;
8100 }
8101
8102 if (netif_running(netdev))
8103 err = igb_open(netdev);
8104
8105 return err;
8106}
9d5c8243 8107/* igb_main.c */
Linux kernel - Deliverables
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