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e1000e: Increase timeout of polling bit RSPCIPHY
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
6fb46902
TF		 60#define MIN 3
61#define BUILD 0
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
32b3e08f 154static int igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
ceee3450
TF		 182static int igb_disable_sriov(struct pci_dev *dev);
183static int igb_pci_disable_sriov(struct pci_dev *dev);
46a01698 184#endif
9d5c8243 185
9d5c8243 186#ifdef CONFIG_PM
d9dd966d 187#ifdef CONFIG_PM_SLEEP
749ab2cd 188static int igb_suspend(struct device *);
d9dd966d 189#endif
749ab2cd 190static int igb_resume(struct device *);
749ab2cd
YZ		 191static int igb_runtime_suspend(struct device *dev);
192static int igb_runtime_resume(struct device *dev);
193static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
047e0030 949 struct e1000_hw *hw = &adapter->hw;
52285b76 950 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 951
047e0030 952 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 953 igb_msix_other, 0, netdev->name, adapter);
047e0030 954 if (err)
52285b76 955 goto err_out;
047e0030
AD		 956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
52285b76
SA		 960 vector++;
961
047e0030
AD		 962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
963
0ba82994 964 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
047e0030 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
047e0030 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 972 q_vector->rx.ring->queue_index);
9d5c8243 973 else
047e0030
AD		 974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
9d5c8243 976 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
9d5c8243 979 if (err)
52285b76 980 goto err_free;
9d5c8243
AK		 981 }
982
9d5c8243
AK		 983 igb_configure_msix(adapter);
984 return 0;
52285b76
SA		 985
986err_free:
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995err_out:
9d5c8243
AK		 996 return err;
997}
998
5536d210 999/**
b980ac18
JK		 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
5536d210 1003 *
02ef6e1d 1004 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
02ef6e1d
CW		 1010 adapter->q_vector[v_idx] = NULL;
1011
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
17a402a0
CW		 1015 if (q_vector)
1016 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1017}
1018
1019/**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
cb06d102
CP		 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
5536d210
AD		 1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
2439fc4d 1041 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
5536d210 1042
5536d210
AD		 1043 netif_napi_del(&q_vector->napi);
1044
02ef6e1d
CW		 1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
cd14ef54 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1052 pci_disable_msix(adapter->pdev);
cd14ef54 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1054 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1058}
1059
047e0030 1060/**
b980ac18
JK		 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
047e0030 1063 *
b980ac18
JK		 1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
047e0030
AD		 1067 **/
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
5536d210
AD		 1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
047e0030 1074 adapter->num_q_vectors = 0;
5536d210 1075
02ef6e1d
CW		 1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
5536d210 1078 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1079 }
047e0030
AD		 1080}
1081
1082/**
b980ac18
JK		 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
047e0030 1085 *
b980ac18
JK		 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
047e0030
AD		 1088 */
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
047e0030
AD		 1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
9d5c8243
AK		 1094
1095/**
b980ac18
JK		 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
9d5c8243 1099 *
b980ac18
JK		 1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
9d5c8243 1102 **/
53c7d064 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1104{
1105 int err;
1106 int numvecs, i;
1107
53c7d064
SA		 1108 if (!msix)
1109 goto msi_only;
cd14ef54 1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1111
83b7180d 1112 /* Number of supported queues. */
a99955fc 1113 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1118
b980ac18 1119 /* start with one vector for every Rx queue */
047e0030
AD		 1120 numvecs = adapter->num_rx_queues;
1121
b980ac18 1122 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
047e0030
AD		 1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
9d5c8243
AK		 1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
479d02df
AG		 1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
0c2cc02e 1139 return;
9d5c8243
AK		 1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144msi_only:
b709323d 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1146#ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1157 wrfl();
2a3abf6d
AD		 1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
4fc82adf 1162 adapter->vfs_allocated_count = 0;
a99955fc 1163 adapter->rss_queues = 1;
4fc82adf 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1165 adapter->num_rx_queues = 1;
661086df 1166 adapter->num_tx_queues = 1;
047e0030 1167 adapter->num_q_vectors = 1;
9d5c8243 1168 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1169 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1170}
1171
5536d210
AD		 1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
047e0030 1179/**
b980ac18
JK		 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
047e0030 1188 *
b980ac18 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1190 **/
5536d210
AD		 1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
047e0030
AD		 1195{
1196 struct igb_q_vector *q_vector;
5536d210
AD		 1197 struct igb_ring *ring;
1198 int ring_count, size;
047e0030 1199
5536d210
AD		 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
02ef6e1d 1209 q_vector = adapter->q_vector[v_idx];
72ddef05 1210 if (!q_vector) {
02ef6e1d 1211 q_vector = kzalloc(size, GFP_KERNEL);
72ddef05
SS		 1212 } else if (size > ksize(q_vector)) {
1213 kfree_rcu(q_vector, rcu);
1214 q_vector = kzalloc(size, GFP_KERNEL);
1215 } else {
c0a06ee1 1216 memset(q_vector, 0, size);
72ddef05 1217 }
5536d210
AD		 1218 if (!q_vector)
1219 return -ENOMEM;
1220
1221 /* initialize NAPI */
1222 netif_napi_add(adapter->netdev, &q_vector->napi,
1223 igb_poll, 64);
1224
1225 /* tie q_vector and adapter together */
1226 adapter->q_vector[v_idx] = q_vector;
1227 q_vector->adapter = adapter;
1228
1229 /* initialize work limits */
1230 q_vector->tx.work_limit = adapter->tx_work_limit;
1231
1232 /* initialize ITR configuration */
1233 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1234 q_vector->itr_val = IGB_START_ITR;
1235
1236 /* initialize pointer to rings */
1237 ring = q_vector->ring;
1238
4e227667
AD		 1239 /* intialize ITR */
1240 if (rxr_count) {
1241 /* rx or rx/tx vector */
1242 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1243 q_vector->itr_val = adapter->rx_itr_setting;
1244 } else {
1245 /* tx only vector */
1246 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1247 q_vector->itr_val = adapter->tx_itr_setting;
1248 }
1249
5536d210
AD		 1250 if (txr_count) {
1251 /* assign generic ring traits */
1252 ring->dev = &adapter->pdev->dev;
1253 ring->netdev = adapter->netdev;
1254
1255 /* configure backlink on ring */
1256 ring->q_vector = q_vector;
1257
1258 /* update q_vector Tx values */
1259 igb_add_ring(ring, &q_vector->tx);
1260
1261 /* For 82575, context index must be unique per ring. */
1262 if (adapter->hw.mac.type == e1000_82575)
1263 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1264
1265 /* apply Tx specific ring traits */
1266 ring->count = adapter->tx_ring_count;
1267 ring->queue_index = txr_idx;
1268
827da44c
JS		 1269 u64_stats_init(&ring->tx_syncp);
1270 u64_stats_init(&ring->tx_syncp2);
1271
5536d210
AD		 1272 /* assign ring to adapter */
1273 adapter->tx_ring[txr_idx] = ring;
1274
1275 /* push pointer to next ring */
1276 ring++;
047e0030 1277 }
81c2fc22 1278
5536d210
AD		 1279 if (rxr_count) {
1280 /* assign generic ring traits */
1281 ring->dev = &adapter->pdev->dev;
1282 ring->netdev = adapter->netdev;
047e0030 1283
5536d210
AD		 1284 /* configure backlink on ring */
1285 ring->q_vector = q_vector;
047e0030 1286
5536d210
AD		 1287 /* update q_vector Rx values */
1288 igb_add_ring(ring, &q_vector->rx);
047e0030 1289
5536d210
AD		 1290 /* set flag indicating ring supports SCTP checksum offload */
1291 if (adapter->hw.mac.type >= e1000_82576)
1292 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1293
e52c0f96 1294 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1295 * have the tag byte-swapped.
b980ac18 1296 */
5536d210
AD		 1297 if (adapter->hw.mac.type >= e1000_i350)
1298 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1299
5536d210
AD		 1300 /* apply Rx specific ring traits */
1301 ring->count = adapter->rx_ring_count;
1302 ring->queue_index = rxr_idx;
1303
827da44c
JS		 1304 u64_stats_init(&ring->rx_syncp);
1305
5536d210
AD		 1306 /* assign ring to adapter */
1307 adapter->rx_ring[rxr_idx] = ring;
1308 }
1309
1310 return 0;
047e0030
AD		 1311}
1312
5536d210 1313
047e0030 1314/**
b980ac18
JK		 1315 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316 * @adapter: board private structure to initialize
047e0030 1317 *
b980ac18
JK		 1318 * We allocate one q_vector per queue interrupt. If allocation fails we
1319 * return -ENOMEM.
047e0030 1320 **/
5536d210 1321static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1322{
5536d210
AD		 1323 int q_vectors = adapter->num_q_vectors;
1324 int rxr_remaining = adapter->num_rx_queues;
1325 int txr_remaining = adapter->num_tx_queues;
1326 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327 int err;
047e0030 1328
5536d210
AD		 1329 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330 for (; rxr_remaining; v_idx++) {
1331 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332 0, 0, 1, rxr_idx);
047e0030 1333
5536d210
AD		 1334 if (err)
1335 goto err_out;
1336
1337 /* update counts and index */
1338 rxr_remaining--;
1339 rxr_idx++;
047e0030 1340 }
047e0030 1341 }
5536d210
AD		 1342
1343 for (; v_idx < q_vectors; v_idx++) {
1344 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1346
5536d210
AD		 1347 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348 tqpv, txr_idx, rqpv, rxr_idx);
1349
1350 if (err)
1351 goto err_out;
1352
1353 /* update counts and index */
1354 rxr_remaining -= rqpv;
1355 txr_remaining -= tqpv;
1356 rxr_idx++;
1357 txr_idx++;
1358 }
1359
047e0030 1360 return 0;
5536d210
AD		 1361
1362err_out:
1363 adapter->num_tx_queues = 0;
1364 adapter->num_rx_queues = 0;
1365 adapter->num_q_vectors = 0;
1366
1367 while (v_idx--)
1368 igb_free_q_vector(adapter, v_idx);
1369
1370 return -ENOMEM;
047e0030
AD		 1371}
1372
1373/**
b980ac18
JK		 1374 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375 * @adapter: board private structure to initialize
1376 * @msix: boolean value of MSIX capability
047e0030 1377 *
b980ac18 1378 * This function initializes the interrupts and allocates all of the queues.
047e0030 1379 **/
53c7d064 1380static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1381{
1382 struct pci_dev *pdev = adapter->pdev;
1383 int err;
1384
53c7d064 1385 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1386
1387 err = igb_alloc_q_vectors(adapter);
1388 if (err) {
1389 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390 goto err_alloc_q_vectors;
1391 }
1392
5536d210 1393 igb_cache_ring_register(adapter);
047e0030
AD		 1394
1395 return 0;
5536d210 1396
047e0030
AD		 1397err_alloc_q_vectors:
1398 igb_reset_interrupt_capability(adapter);
1399 return err;
1400}
1401
9d5c8243 1402/**
b980ac18
JK		 1403 * igb_request_irq - initialize interrupts
1404 * @adapter: board private structure to initialize
9d5c8243 1405 *
b980ac18
JK		 1406 * Attempts to configure interrupts using the best available
1407 * capabilities of the hardware and kernel.
9d5c8243
AK		 1408 **/
1409static int igb_request_irq(struct igb_adapter *adapter)
1410{
1411 struct net_device *netdev = adapter->netdev;
047e0030 1412 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1413 int err = 0;
1414
cd14ef54 1415 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1416 err = igb_request_msix(adapter);
844290e5 1417 if (!err)
9d5c8243 1418 goto request_done;
9d5c8243 1419 /* fall back to MSI */
5536d210
AD		 1420 igb_free_all_tx_resources(adapter);
1421 igb_free_all_rx_resources(adapter);
53c7d064 1422
047e0030 1423 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1424 err = igb_init_interrupt_scheme(adapter, false);
1425 if (err)
047e0030 1426 goto request_done;
53c7d064 1427
047e0030
AD		 1428 igb_setup_all_tx_resources(adapter);
1429 igb_setup_all_rx_resources(adapter);
53c7d064 1430 igb_configure(adapter);
9d5c8243 1431 }
844290e5 1432
c74d588e
AD		 1433 igb_assign_vector(adapter->q_vector[0], 0);
1434
7dfc16fa 1435 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1436 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1437 netdev->name, adapter);
9d5c8243
AK		 1438 if (!err)
1439 goto request_done;
047e0030 1440
9d5c8243
AK		 1441 /* fall back to legacy interrupts */
1442 igb_reset_interrupt_capability(adapter);
7dfc16fa 1443 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1444 }
1445
c74d588e 1446 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1447 netdev->name, adapter);
9d5c8243 1448
6cb5e577 1449 if (err)
c74d588e 1450 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1451 err);
9d5c8243
AK		 1452
1453request_done:
1454 return err;
1455}
1456
1457static void igb_free_irq(struct igb_adapter *adapter)
1458{
cd14ef54 1459 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1460 int vector = 0, i;
1461
047e0030 1462 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1463
0d1ae7f4 1464 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1465 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1466 adapter->q_vector[i]);
047e0030
AD		 1467 } else {
1468 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1469 }
9d5c8243
AK		 1470}
1471
1472/**
b980ac18
JK		 1473 * igb_irq_disable - Mask off interrupt generation on the NIC
1474 * @adapter: board private structure
9d5c8243
AK		 1475 **/
1476static void igb_irq_disable(struct igb_adapter *adapter)
1477{
1478 struct e1000_hw *hw = &adapter->hw;
1479
b980ac18 1480 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1481 * mapped into these registers and so clearing the bits can cause
1482 * issues on the VF drivers so we only need to clear what we set
1483 */
cd14ef54 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1485 u32 regval = rd32(E1000_EIAM);
9005df38 1486
2dfd1212
AD		 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489 regval = rd32(E1000_EIAC);
1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1491 }
844290e5
PW		 1492
1493 wr32(E1000_IAM, 0);
9d5c8243
AK		 1494 wr32(E1000_IMC, ~0);
1495 wrfl();
cd14ef54 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1497 int i;
9005df38 1498
81a61859
ET		 1499 for (i = 0; i < adapter->num_q_vectors; i++)
1500 synchronize_irq(adapter->msix_entries[i].vector);
1501 } else {
1502 synchronize_irq(adapter->pdev->irq);
1503 }
9d5c8243
AK		 1504}
1505
1506/**
b980ac18
JK		 1507 * igb_irq_enable - Enable default interrupt generation settings
1508 * @adapter: board private structure
9d5c8243
AK		 1509 **/
1510static void igb_irq_enable(struct igb_adapter *adapter)
1511{
1512 struct e1000_hw *hw = &adapter->hw;
1513
cd14ef54 1514 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1515 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1516 u32 regval = rd32(E1000_EIAC);
9005df38 1517
2dfd1212
AD		 1518 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519 regval = rd32(E1000_EIAM);
1520 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1521 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1522 if (adapter->vfs_allocated_count) {
4ae196df 1523 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1524 ims |= E1000_IMS_VMMB;
1525 }
1526 wr32(E1000_IMS, ims);
844290e5 1527 } else {
55cac248
AD		 1528 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529 E1000_IMS_DRSTA);
1530 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531 E1000_IMS_DRSTA);
844290e5 1532 }
9d5c8243
AK		 1533}
1534
1535static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536{
51466239 1537 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1538 u16 vid = adapter->hw.mng_cookie.vlan_id;
1539 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1540
1541 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1542 /* add VID to filter table */
1543 igb_vfta_set(hw, vid, true);
1544 adapter->mng_vlan_id = vid;
1545 } else {
1546 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1547 }
1548
1549 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1550 (vid != old_vid) &&
b2cb09b1 1551 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1552 /* remove VID from filter table */
1553 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1554 }
1555}
1556
1557/**
b980ac18
JK		 1558 * igb_release_hw_control - release control of the h/w to f/w
1559 * @adapter: address of board private structure
9d5c8243 1560 *
b980ac18
JK		 1561 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1562 * For ASF and Pass Through versions of f/w this means that the
1563 * driver is no longer loaded.
9d5c8243
AK		 1564 **/
1565static void igb_release_hw_control(struct igb_adapter *adapter)
1566{
1567 struct e1000_hw *hw = &adapter->hw;
1568 u32 ctrl_ext;
1569
1570 /* Let firmware take over control of h/w */
1571 ctrl_ext = rd32(E1000_CTRL_EXT);
1572 wr32(E1000_CTRL_EXT,
1573 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1574}
1575
9d5c8243 1576/**
b980ac18
JK		 1577 * igb_get_hw_control - get control of the h/w from f/w
1578 * @adapter: address of board private structure
9d5c8243 1579 *
b980ac18
JK		 1580 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1581 * For ASF and Pass Through versions of f/w this means that
1582 * the driver is loaded.
9d5c8243
AK		 1583 **/
1584static void igb_get_hw_control(struct igb_adapter *adapter)
1585{
1586 struct e1000_hw *hw = &adapter->hw;
1587 u32 ctrl_ext;
1588
1589 /* Let firmware know the driver has taken over */
1590 ctrl_ext = rd32(E1000_CTRL_EXT);
1591 wr32(E1000_CTRL_EXT,
1592 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1593}
1594
9d5c8243 1595/**
b980ac18
JK		 1596 * igb_configure - configure the hardware for RX and TX
1597 * @adapter: private board structure
9d5c8243
AK		 1598 **/
1599static void igb_configure(struct igb_adapter *adapter)
1600{
1601 struct net_device *netdev = adapter->netdev;
1602 int i;
1603
1604 igb_get_hw_control(adapter);
ff41f8dc 1605 igb_set_rx_mode(netdev);
9d5c8243
AK		 1606
1607 igb_restore_vlan(adapter);
9d5c8243 1608
85b430b4 1609 igb_setup_tctl(adapter);
06cf2666 1610 igb_setup_mrqc(adapter);
9d5c8243 1611 igb_setup_rctl(adapter);
85b430b4
AD		 1612
1613 igb_configure_tx(adapter);
9d5c8243 1614 igb_configure_rx(adapter);
662d7205
AD		 1615
1616 igb_rx_fifo_flush_82575(&adapter->hw);
1617
c493ea45 1618 /* call igb_desc_unused which always leaves
9d5c8243 1619 * at least 1 descriptor unused to make sure
b980ac18
JK		 1620 * next_to_use != next_to_clean
1621 */
9d5c8243 1622 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1623 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1624 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1625 }
9d5c8243
AK		 1626}
1627
88a268c1 1628/**
b980ac18
JK		 1629 * igb_power_up_link - Power up the phy/serdes link
1630 * @adapter: address of board private structure
88a268c1
NN		 1631 **/
1632void igb_power_up_link(struct igb_adapter *adapter)
1633{
76886596
AA		 1634 igb_reset_phy(&adapter->hw);
1635
88a268c1
NN		 1636 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1637 igb_power_up_phy_copper(&adapter->hw);
1638 else
1639 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1640
1641 igb_setup_link(&adapter->hw);
88a268c1
NN		 1642}
1643
1644/**
b980ac18
JK		 1645 * igb_power_down_link - Power down the phy/serdes link
1646 * @adapter: address of board private structure
88a268c1
NN		 1647 */
1648static void igb_power_down_link(struct igb_adapter *adapter)
1649{
1650 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1651 igb_power_down_phy_copper_82575(&adapter->hw);
1652 else
1653 igb_shutdown_serdes_link_82575(&adapter->hw);
1654}
9d5c8243 1655
56cec249
CW		 1656/**
1657 * Detect and switch function for Media Auto Sense
1658 * @adapter: address of the board private structure
1659 **/
1660static void igb_check_swap_media(struct igb_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 ctrl_ext, connsw;
1664 bool swap_now = false;
1665
1666 ctrl_ext = rd32(E1000_CTRL_EXT);
1667 connsw = rd32(E1000_CONNSW);
1668
1669 /* need to live swap if current media is copper and we have fiber/serdes
1670 * to go to.
1671 */
1672
1673 if ((hw->phy.media_type == e1000_media_type_copper) &&
1674 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1675 swap_now = true;
1676 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1677 /* copper signal takes time to appear */
1678 if (adapter->copper_tries < 4) {
1679 adapter->copper_tries++;
1680 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1681 wr32(E1000_CONNSW, connsw);
1682 return;
1683 } else {
1684 adapter->copper_tries = 0;
1685 if ((connsw & E1000_CONNSW_PHYSD) &&
1686 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1687 swap_now = true;
1688 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1689 wr32(E1000_CONNSW, connsw);
1690 }
1691 }
1692 }
1693
1694 if (!swap_now)
1695 return;
1696
1697 switch (hw->phy.media_type) {
1698 case e1000_media_type_copper:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to fiber/serdes\n");
1701 ctrl_ext |=
1702 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 adapter->copper_tries = 0;
1705 break;
1706 case e1000_media_type_internal_serdes:
1707 case e1000_media_type_fiber:
1708 netdev_info(adapter->netdev,
1709 "MAS: changing media to copper\n");
1710 ctrl_ext &=
1711 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1712 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1713 break;
1714 default:
1715 /* shouldn't get here during regular operation */
1716 netdev_err(adapter->netdev,
1717 "AMS: Invalid media type found, returning\n");
1718 break;
1719 }
1720 wr32(E1000_CTRL_EXT, ctrl_ext);
1721}
1722
9d5c8243 1723/**
b980ac18
JK		 1724 * igb_up - Open the interface and prepare it to handle traffic
1725 * @adapter: board private structure
9d5c8243 1726 **/
9d5c8243
AK		 1727int igb_up(struct igb_adapter *adapter)
1728{
1729 struct e1000_hw *hw = &adapter->hw;
1730 int i;
1731
1732 /* hardware has been reset, we need to reload some things */
1733 igb_configure(adapter);
1734
1735 clear_bit(__IGB_DOWN, &adapter->state);
1736
0d1ae7f4
AD		 1737 for (i = 0; i < adapter->num_q_vectors; i++)
1738 napi_enable(&(adapter->q_vector[i]->napi));
1739
cd14ef54 1740 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1741 igb_configure_msix(adapter);
feeb2721
AD		 1742 else
1743 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1744
1745 /* Clear any pending interrupts. */
1746 rd32(E1000_ICR);
1747 igb_irq_enable(adapter);
1748
d4960307
AD		 1749 /* notify VFs that reset has been completed */
1750 if (adapter->vfs_allocated_count) {
1751 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1752
d4960307
AD		 1753 reg_data |= E1000_CTRL_EXT_PFRSTD;
1754 wr32(E1000_CTRL_EXT, reg_data);
1755 }
1756
4cb9be7a
JB		 1757 netif_tx_start_all_queues(adapter->netdev);
1758
25568a53
AD		 1759 /* start the watchdog. */
1760 hw->mac.get_link_status = 1;
1761 schedule_work(&adapter->watchdog_task);
1762
f4c01e96
CW		 1763 if ((adapter->flags & IGB_FLAG_EEE) &&
1764 (!hw->dev_spec._82575.eee_disable))
1765 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1766
9d5c8243
AK		 1767 return 0;
1768}
1769
1770void igb_down(struct igb_adapter *adapter)
1771{
9d5c8243 1772 struct net_device *netdev = adapter->netdev;
330a6d6a 1773 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1774 u32 tctl, rctl;
1775 int i;
1776
1777 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1778 * reschedule our watchdog timer
1779 */
9d5c8243
AK		 1780 set_bit(__IGB_DOWN, &adapter->state);
1781
1782 /* disable receives in the hardware */
1783 rctl = rd32(E1000_RCTL);
1784 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1785 /* flush and sleep below */
1786
f28ea083 1787 netif_carrier_off(netdev);
fd2ea0a7 1788 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1789
1790 /* disable transmits in the hardware */
1791 tctl = rd32(E1000_TCTL);
1792 tctl &= ~E1000_TCTL_EN;
1793 wr32(E1000_TCTL, tctl);
1794 /* flush both disables and wait for them to finish */
1795 wrfl();
0d451e79 1796 usleep_range(10000, 11000);
9d5c8243 1797
41f149a2
CW		 1798 igb_irq_disable(adapter);
1799
aa9b8cc4
AA		 1800 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1801
41f149a2 1802 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1803 if (adapter->q_vector[i]) {
1804 napi_synchronize(&adapter->q_vector[i]->napi);
1805 napi_disable(&adapter->q_vector[i]->napi);
1806 }
41f149a2 1807 }
9d5c8243 1808
9d5c8243
AK		 1809 del_timer_sync(&adapter->watchdog_timer);
1810 del_timer_sync(&adapter->phy_info_timer);
1811
04fe6358 1812 /* record the stats before reset*/
12dcd86b
ED		 1813 spin_lock(&adapter->stats64_lock);
1814 igb_update_stats(adapter, &adapter->stats64);
1815 spin_unlock(&adapter->stats64_lock);
04fe6358 1816
9d5c8243
AK		 1817 adapter->link_speed = 0;
1818 adapter->link_duplex = 0;
1819
3023682e
JK		 1820 if (!pci_channel_offline(adapter->pdev))
1821 igb_reset(adapter);
9d5c8243
AK		 1822 igb_clean_all_tx_rings(adapter);
1823 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1824#ifdef CONFIG_IGB_DCA
1825
1826 /* since we reset the hardware DCA settings were cleared */
1827 igb_setup_dca(adapter);
1828#endif
9d5c8243
AK		 1829}
1830
1831void igb_reinit_locked(struct igb_adapter *adapter)
1832{
1833 WARN_ON(in_interrupt());
1834 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1835 usleep_range(1000, 2000);
9d5c8243
AK		 1836 igb_down(adapter);
1837 igb_up(adapter);
1838 clear_bit(__IGB_RESETTING, &adapter->state);
1839}
1840
56cec249
CW		 1841/** igb_enable_mas - Media Autosense re-enable after swap
1842 *
1843 * @adapter: adapter struct
1844 **/
8cfb879d 1845static void igb_enable_mas(struct igb_adapter *adapter)
56cec249
CW		 1846{
1847 struct e1000_hw *hw = &adapter->hw;
8cfb879d 1848 u32 connsw = rd32(E1000_CONNSW);
56cec249
CW		 1849
1850 /* configure for SerDes media detect */
8cfb879d
TF		 1851 if ((hw->phy.media_type == e1000_media_type_copper) &&
1852 (!(connsw & E1000_CONNSW_SERDESD))) {
56cec249
CW		 1853 connsw |= E1000_CONNSW_ENRGSRC;
1854 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1855 wr32(E1000_CONNSW, connsw);
1856 wrfl();
56cec249 1857 }
56cec249
CW		 1858}
1859
9d5c8243
AK		 1860void igb_reset(struct igb_adapter *adapter)
1861{
090b1795 1862 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1863 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1864 struct e1000_mac_info *mac = &hw->mac;
1865 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1866 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1867
1868 /* Repartition Pba for greater than 9k mtu
1869 * To take effect CTRL.RST is required.
1870 */
fa4dfae0 1871 switch (mac->type) {
d2ba2ed8 1872 case e1000_i350:
ceb5f13b 1873 case e1000_i354:
55cac248
AD		 1874 case e1000_82580:
1875 pba = rd32(E1000_RXPBS);
1876 pba = igb_rxpbs_adjust_82580(pba);
1877 break;
fa4dfae0 1878 case e1000_82576:
d249be54
AD		 1879 pba = rd32(E1000_RXPBS);
1880 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1881 break;
1882 case e1000_82575:
f96a8a0b
CW		 1883 case e1000_i210:
1884 case e1000_i211:
fa4dfae0
AD		 1885 default:
1886 pba = E1000_PBA_34K;
1887 break;
2d064c06 1888 }
9d5c8243 1889
2d064c06
AD		 1890 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1891 (mac->type < e1000_82576)) {
9d5c8243
AK		 1892 /* adjust PBA for jumbo frames */
1893 wr32(E1000_PBA, pba);
1894
1895 /* To maintain wire speed transmits, the Tx FIFO should be
1896 * large enough to accommodate two full transmit packets,
1897 * rounded up to the next 1KB and expressed in KB. Likewise,
1898 * the Rx FIFO should be large enough to accommodate at least
1899 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1900 * expressed in KB.
1901 */
9d5c8243
AK		 1902 pba = rd32(E1000_PBA);
1903 /* upper 16 bits has Tx packet buffer allocation size in KB */
1904 tx_space = pba >> 16;
1905 /* lower 16 bits has Rx packet buffer allocation size in KB */
1906 pba &= 0xffff;
b980ac18
JK		 1907 /* the Tx fifo also stores 16 bytes of information about the Tx
1908 * but don't include ethernet FCS because hardware appends it
1909 */
9d5c8243 1910 min_tx_space = (adapter->max_frame_size +
85e8d004 1911 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1912 ETH_FCS_LEN) * 2;
1913 min_tx_space = ALIGN(min_tx_space, 1024);
1914 min_tx_space >>= 10;
1915 /* software strips receive CRC, so leave room for it */
1916 min_rx_space = adapter->max_frame_size;
1917 min_rx_space = ALIGN(min_rx_space, 1024);
1918 min_rx_space >>= 10;
1919
1920 /* If current Tx allocation is less than the min Tx FIFO size,
1921 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1922 * allocation, take space away from current Rx allocation
1923 */
9d5c8243
AK		 1924 if (tx_space < min_tx_space &&
1925 ((min_tx_space - tx_space) < pba)) {
1926 pba = pba - (min_tx_space - tx_space);
1927
b980ac18
JK		 1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
9d5c8243
AK		 1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
2d064c06 1934 wr32(E1000_PBA, pba);
9d5c8243 1935 }
9d5c8243
AK		 1936
1937 /* flow control settings */
1938 /* The high water mark must be low enough to fit one full frame
1939 * (or the size used for early receive) above it in the Rx FIFO.
1940 * Set it to the lower of:
1941 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1942 * - the full Rx FIFO size minus one full frame
1943 */
9d5c8243 1944 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1945 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1946
d48507fe 1947 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1948 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1949 fc->pause_time = 0xFFFF;
1950 fc->send_xon = 1;
0cce119a 1951 fc->current_mode = fc->requested_mode;
9d5c8243 1952
4ae196df
AD		 1953 /* disable receive for all VFs and wait one second */
1954 if (adapter->vfs_allocated_count) {
1955 int i;
9005df38 1956
4ae196df 1957 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1958 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1959
1960 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1961 igb_ping_all_vfs(adapter);
4ae196df
AD		 1962
1963 /* disable transmits and receives */
1964 wr32(E1000_VFRE, 0);
1965 wr32(E1000_VFTE, 0);
1966 }
1967
9d5c8243 1968 /* Allow time for pending master requests to run */
330a6d6a 1969 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1970 wr32(E1000_WUC, 0);
1971
56cec249
CW		 1972 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1973 /* need to resetup here after media swap */
1974 adapter->ei.get_invariants(hw);
1975 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1976 }
8cfb879d
TF		 1977 if ((mac->type == e1000_82575) &&
1978 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
1979 igb_enable_mas(adapter);
56cec249 1980 }
330a6d6a 1981 if (hw->mac.ops.init_hw(hw))
090b1795 1982 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1983
b980ac18 1984 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1985 * control is off when forcing speed.
1986 */
1987 if (!hw->mac.autoneg)
1988 igb_force_mac_fc(hw);
1989
b6e0c419 1990 igb_init_dmac(adapter, pba);
e428893b
CW		 1991#ifdef CONFIG_IGB_HWMON
1992 /* Re-initialize the thermal sensor on i350 devices. */
1993 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1994 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1995 /* If present, re-initialize the external thermal sensor
1996 * interface.
1997 */
1998 if (adapter->ets)
1999 mac->ops.init_thermal_sensor_thresh(hw);
2000 }
2001 }
2002#endif
b936136d 2003 /* Re-establish EEE setting */
f4c01e96
CW		 2004 if (hw->phy.media_type == e1000_media_type_copper) {
2005 switch (mac->type) {
2006 case e1000_i350:
2007 case e1000_i210:
2008 case e1000_i211:
c4c112f1 2009 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2010 break;
2011 case e1000_i354:
c4c112f1 2012 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2013 break;
2014 default:
2015 break;
2016 }
2017 }
88a268c1
NN		 2018 if (!netif_running(adapter->netdev))
2019 igb_power_down_link(adapter);
2020
9d5c8243
AK		 2021 igb_update_mng_vlan(adapter);
2022
2023 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2024 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2025
1f6e8178
MV		 2026 /* Re-enable PTP, where applicable. */
2027 igb_ptp_reset(adapter);
1f6e8178 2028
330a6d6a 2029 igb_get_phy_info(hw);
9d5c8243
AK		 2030}
2031
c8f44aff
MM		 2032static netdev_features_t igb_fix_features(struct net_device *netdev,
2033 netdev_features_t features)
b2cb09b1 2034{
b980ac18
JK		 2035 /* Since there is no support for separate Rx/Tx vlan accel
2036 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2037 */
f646968f
PM		 2038 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2039 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2040 else
f646968f 2041 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2042
2043 return features;
2044}
2045
c8f44aff
MM		 2046static int igb_set_features(struct net_device *netdev,
2047 netdev_features_t features)
ac52caa3 2048{
c8f44aff 2049 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2050 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2051
f646968f 2052 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2053 igb_vlan_mode(netdev, features);
2054
89eaefb6
BG		 2055 if (!(changed & NETIF_F_RXALL))
2056 return 0;
2057
2058 netdev->features = features;
2059
2060 if (netif_running(netdev))
2061 igb_reinit_locked(adapter);
2062 else
2063 igb_reset(adapter);
2064
ac52caa3
MM		 2065 return 0;
2066}
2067
2e5c6922 2068static const struct net_device_ops igb_netdev_ops = {
559e9c49 2069 .ndo_open = igb_open,
2e5c6922 2070 .ndo_stop = igb_close,
cd392f5c 2071 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2072 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2073 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2074 .ndo_set_mac_address = igb_set_mac,
2075 .ndo_change_mtu = igb_change_mtu,
2076 .ndo_do_ioctl = igb_ioctl,
2077 .ndo_tx_timeout = igb_tx_timeout,
2078 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2079 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2080 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2081 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2082 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2083 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2084 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2085 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2086#ifdef CONFIG_NET_POLL_CONTROLLER
2087 .ndo_poll_controller = igb_netpoll,
2088#endif
b2cb09b1
JP		 2089 .ndo_fix_features = igb_fix_features,
2090 .ndo_set_features = igb_set_features,
1abbc98a 2091 .ndo_features_check = passthru_features_check,
2e5c6922
SH		 2092};
2093
d67974f0
CW		 2094/**
2095 * igb_set_fw_version - Configure version string for ethtool
2096 * @adapter: adapter struct
d67974f0
CW		 2097 **/
2098void igb_set_fw_version(struct igb_adapter *adapter)
2099{
2100 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2101 struct e1000_fw_version fw;
2102
2103 igb_get_fw_version(hw, &fw);
2104
2105 switch (hw->mac.type) {
7dc98a62 2106 case e1000_i210:
0b1a6f2e 2107 case e1000_i211:
7dc98a62
CW		 2108 if (!(igb_get_flash_presence_i210(hw))) {
2109 snprintf(adapter->fw_version,
2110 sizeof(adapter->fw_version),
2111 "%2d.%2d-%d",
2112 fw.invm_major, fw.invm_minor,
2113 fw.invm_img_type);
2114 break;
2115 }
2116 /* fall through */
0b1a6f2e
CW		 2117 default:
2118 /* if option is rom valid, display its version too */
2119 if (fw.or_valid) {
2120 snprintf(adapter->fw_version,
2121 sizeof(adapter->fw_version),
2122 "%d.%d, 0x%08x, %d.%d.%d",
2123 fw.eep_major, fw.eep_minor, fw.etrack_id,
2124 fw.or_major, fw.or_build, fw.or_patch);
2125 /* no option rom */
7dc98a62 2126 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2127 snprintf(adapter->fw_version,
7dc98a62
CW		 2128 sizeof(adapter->fw_version),
2129 "%d.%d, 0x%08x",
2130 fw.eep_major, fw.eep_minor, fw.etrack_id);
2131 } else {
2132 snprintf(adapter->fw_version,
2133 sizeof(adapter->fw_version),
2134 "%d.%d.%d",
2135 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2136 }
2137 break;
d67974f0 2138 }
d67974f0
CW		 2139}
2140
56cec249
CW		 2141/**
2142 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2143 *
2144 * @adapter: adapter struct
2145 **/
2146static void igb_init_mas(struct igb_adapter *adapter)
2147{
2148 struct e1000_hw *hw = &adapter->hw;
2149 u16 eeprom_data;
2150
2151 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2152 switch (hw->bus.func) {
2153 case E1000_FUNC_0:
2154 if (eeprom_data & IGB_MAS_ENABLE_0) {
2155 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2156 netdev_info(adapter->netdev,
2157 "MAS: Enabling Media Autosense for port %d\n",
2158 hw->bus.func);
2159 }
2160 break;
2161 case E1000_FUNC_1:
2162 if (eeprom_data & IGB_MAS_ENABLE_1) {
2163 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2164 netdev_info(adapter->netdev,
2165 "MAS: Enabling Media Autosense for port %d\n",
2166 hw->bus.func);
2167 }
2168 break;
2169 case E1000_FUNC_2:
2170 if (eeprom_data & IGB_MAS_ENABLE_2) {
2171 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2172 netdev_info(adapter->netdev,
2173 "MAS: Enabling Media Autosense for port %d\n",
2174 hw->bus.func);
2175 }
2176 break;
2177 case E1000_FUNC_3:
2178 if (eeprom_data & IGB_MAS_ENABLE_3) {
2179 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2180 netdev_info(adapter->netdev,
2181 "MAS: Enabling Media Autosense for port %d\n",
2182 hw->bus.func);
2183 }
2184 break;
2185 default:
2186 /* Shouldn't get here */
2187 netdev_err(adapter->netdev,
2188 "MAS: Invalid port configuration, returning\n");
2189 break;
2190 }
2191}
2192
b980ac18
JK		 2193/**
2194 * igb_init_i2c - Init I2C interface
441fc6fd 2195 * @adapter: pointer to adapter structure
b980ac18 2196 **/
441fc6fd
CW		 2197static s32 igb_init_i2c(struct igb_adapter *adapter)
2198{
23d87824 2199 s32 status = 0;
441fc6fd
CW		 2200
2201 /* I2C interface supported on i350 devices */
2202 if (adapter->hw.mac.type != e1000_i350)
23d87824 2203 return 0;
441fc6fd
CW		 2204
2205 /* Initialize the i2c bus which is controlled by the registers.
2206 * This bus will use the i2c_algo_bit structue that implements
2207 * the protocol through toggling of the 4 bits in the register.
2208 */
2209 adapter->i2c_adap.owner = THIS_MODULE;
2210 adapter->i2c_algo = igb_i2c_algo;
2211 adapter->i2c_algo.data = adapter;
2212 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2213 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2214 strlcpy(adapter->i2c_adap.name, "igb BB",
2215 sizeof(adapter->i2c_adap.name));
2216 status = i2c_bit_add_bus(&adapter->i2c_adap);
2217 return status;
2218}
2219
9d5c8243 2220/**
b980ac18
JK		 2221 * igb_probe - Device Initialization Routine
2222 * @pdev: PCI device information struct
2223 * @ent: entry in igb_pci_tbl
9d5c8243 2224 *
b980ac18 2225 * Returns 0 on success, negative on failure
9d5c8243 2226 *
b980ac18
JK		 2227 * igb_probe initializes an adapter identified by a pci_dev structure.
2228 * The OS initialization, configuring of the adapter private structure,
2229 * and a hardware reset occur.
9d5c8243 2230 **/
1dd06ae8 2231static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2232{
2233 struct net_device *netdev;
2234 struct igb_adapter *adapter;
2235 struct e1000_hw *hw;
4337e993 2236 u16 eeprom_data = 0;
9835fd73 2237 s32 ret_val;
4337e993 2238 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2239 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2240 int err, pci_using_dac;
9835fd73 2241 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2242
bded64a7
AG		 2243 /* Catch broken hardware that put the wrong VF device ID in
2244 * the PCIe SR-IOV capability.
2245 */
2246 if (pdev->is_virtfn) {
2247 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2248 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2249 return -EINVAL;
2250 }
2251
aed5dec3 2252 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2253 if (err)
2254 return err;
2255
2256 pci_using_dac = 0;
dc4ff9bb 2257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2258 if (!err) {
dc4ff9bb 2259 pci_using_dac = 1;
9d5c8243 2260 } else {
dc4ff9bb 2261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2262 if (err) {
dc4ff9bb
RK		 2263 dev_err(&pdev->dev,
2264 "No usable DMA configuration, aborting\n");
2265 goto err_dma;
9d5c8243
AK		 2266 }
2267 }
2268
aed5dec3 2269 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2270 IORESOURCE_MEM),
2271 igb_driver_name);
9d5c8243
AK		 2272 if (err)
2273 goto err_pci_reg;
2274
19d5afd4 2275 pci_enable_pcie_error_reporting(pdev);
40a914fa 2276
9d5c8243 2277 pci_set_master(pdev);
c682fc23 2278 pci_save_state(pdev);
9d5c8243
AK		 2279
2280 err = -ENOMEM;
1bfaf07b 2281 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2282 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2283 if (!netdev)
2284 goto err_alloc_etherdev;
2285
2286 SET_NETDEV_DEV(netdev, &pdev->dev);
2287
2288 pci_set_drvdata(pdev, netdev);
2289 adapter = netdev_priv(netdev);
2290 adapter->netdev = netdev;
2291 adapter->pdev = pdev;
2292 hw = &adapter->hw;
2293 hw->back = adapter;
b3f4d599 2294 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2295
9d5c8243 2296 err = -EIO;
73bf8048
JW		 2297 adapter->io_addr = pci_iomap(pdev, 0, 0);
2298 if (!adapter->io_addr)
9d5c8243 2299 goto err_ioremap;
73bf8048
JW		 2300 /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
2301 hw->hw_addr = adapter->io_addr;
9d5c8243 2302
2e5c6922 2303 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2304 igb_set_ethtool_ops(netdev);
9d5c8243 2305 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2306
2307 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2308
89dbefb2
AS		 2309 netdev->mem_start = pci_resource_start(pdev, 0);
2310 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2311
9d5c8243
AK		 2312 /* PCI config space info */
2313 hw->vendor_id = pdev->vendor;
2314 hw->device_id = pdev->device;
2315 hw->revision_id = pdev->revision;
2316 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2317 hw->subsystem_device_id = pdev->subsystem_device;
2318
9d5c8243
AK		 2319 /* Copy the default MAC, PHY and NVM function pointers */
2320 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2321 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2322 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2323 /* Initialize skew-specific constants */
2324 err = ei->get_invariants(hw);
2325 if (err)
450c87c8 2326 goto err_sw_init;
9d5c8243 2327
450c87c8 2328 /* setup the private structure */
9d5c8243
AK		 2329 err = igb_sw_init(adapter);
2330 if (err)
2331 goto err_sw_init;
2332
2333 igb_get_bus_info_pcie(hw);
2334
2335 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2336
2337 /* Copper options */
2338 if (hw->phy.media_type == e1000_media_type_copper) {
2339 hw->phy.mdix = AUTO_ALL_MODES;
2340 hw->phy.disable_polarity_correction = false;
2341 hw->phy.ms_type = e1000_ms_hw_default;
2342 }
2343
2344 if (igb_check_reset_block(hw))
2345 dev_info(&pdev->dev,
2346 "PHY reset is blocked due to SOL/IDER session.\n");
2347
b980ac18 2348 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2349 * set by igb_sw_init so we should use an or instead of an
2350 * assignment.
2351 */
2352 netdev->features |= NETIF_F_SG |
2353 NETIF_F_IP_CSUM |
2354 NETIF_F_IPV6_CSUM |
2355 NETIF_F_TSO |
2356 NETIF_F_TSO6 |
2357 NETIF_F_RXHASH |
2358 NETIF_F_RXCSUM |
f646968f
PM		 2359 NETIF_F_HW_VLAN_CTAG_RX |
2360 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2361
2362 /* copy netdev features into list of user selectable features */
2363 netdev->hw_features |= netdev->features;
89eaefb6 2364 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2365
2366 /* set this bit last since it cannot be part of hw_features */
f646968f 2367 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2368
2369 netdev->vlan_features |= NETIF_F_TSO |
2370 NETIF_F_TSO6 |
2371 NETIF_F_IP_CSUM |
2372 NETIF_F_IPV6_CSUM |
2373 NETIF_F_SG;
48f29ffc 2374
6b8f0922
BG		 2375 netdev->priv_flags |= IFF_SUPP_NOFCS;
2376
7b872a55 2377 if (pci_using_dac) {
9d5c8243 2378 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2379 netdev->vlan_features |= NETIF_F_HIGHDMA;
2380 }
9d5c8243 2381
ac52caa3
MM		 2382 if (hw->mac.type >= e1000_82576) {
2383 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2384 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2385 }
b9473560 2386
01789349
JP		 2387 netdev->priv_flags |= IFF_UNICAST_FLT;
2388
330a6d6a 2389 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2390
2391 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2392 * known good starting state
2393 */
9d5c8243
AK		 2394 hw->mac.ops.reset_hw(hw);
2395
ef3a0092
CW		 2396 /* make sure the NVM is good , i211/i210 parts can have special NVM
2397 * that doesn't contain a checksum
f96a8a0b 2398 */
ef3a0092
CW		 2399 switch (hw->mac.type) {
2400 case e1000_i210:
2401 case e1000_i211:
2402 if (igb_get_flash_presence_i210(hw)) {
2403 if (hw->nvm.ops.validate(hw) < 0) {
2404 dev_err(&pdev->dev,
2405 "The NVM Checksum Is Not Valid\n");
2406 err = -EIO;
2407 goto err_eeprom;
2408 }
2409 }
2410 break;
2411 default:
f96a8a0b
CW		 2412 if (hw->nvm.ops.validate(hw) < 0) {
2413 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2414 err = -EIO;
2415 goto err_eeprom;
2416 }
ef3a0092 2417 break;
9d5c8243
AK		 2418 }
2419
2420 /* copy the MAC address out of the NVM */
2421 if (hw->mac.ops.read_mac_addr(hw))
2422 dev_err(&pdev->dev, "NVM Read Error\n");
2423
2424 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2425
aaeb6cdf 2426 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2427 dev_err(&pdev->dev, "Invalid MAC Address\n");
2428 err = -EIO;
2429 goto err_eeprom;
2430 }
2431
d67974f0
CW		 2432 /* get firmware version for ethtool -i */
2433 igb_set_fw_version(adapter);
2434
27dff8b2
TF		 2435 /* configure RXPBSIZE and TXPBSIZE */
2436 if (hw->mac.type == e1000_i210) {
2437 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2438 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2439 }
2440
c061b18d 2441 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2442 (unsigned long) adapter);
c061b18d 2443 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2444 (unsigned long) adapter);
9d5c8243
AK		 2445
2446 INIT_WORK(&adapter->reset_task, igb_reset_task);
2447 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2448
450c87c8 2449 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2450 adapter->fc_autoneg = true;
2451 hw->mac.autoneg = true;
2452 hw->phy.autoneg_advertised = 0x2f;
2453
0cce119a
AD		 2454 hw->fc.requested_mode = e1000_fc_default;
2455 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2456
9d5c8243
AK		 2457 igb_validate_mdi_setting(hw);
2458
63d4a8f9 2459 /* By default, support wake on port A */
a2cf8b6c 2460 if (hw->bus.func == 0)
63d4a8f9
MV		 2461 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2462
2463 /* Check the NVM for wake support on non-port A ports */
2464 if (hw->mac.type >= e1000_82580)
55cac248 2465 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2466 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2467 &eeprom_data);
a2cf8b6c
AD		 2468 else if (hw->bus.func == 1)
2469 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2470
63d4a8f9
MV		 2471 if (eeprom_data & IGB_EEPROM_APME)
2472 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2473
2474 /* now that we have the eeprom settings, apply the special cases where
2475 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2476 * lan on a particular port
2477 */
9d5c8243
AK		 2478 switch (pdev->device) {
2479 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2480 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2481 break;
2482 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2483 case E1000_DEV_ID_82576_FIBER:
2484 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2485 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2486 * regardless of eeprom setting
2487 */
9d5c8243 2488 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2489 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2490 break;
c8ea5ea9 2491 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2492 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2493 /* if quad port adapter, disable WoL on all but port A */
2494 if (global_quad_port_a != 0)
63d4a8f9 2495 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2496 else
2497 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2498 /* Reset for multiple quad port adapters */
2499 if (++global_quad_port_a == 4)
2500 global_quad_port_a = 0;
2501 break;
63d4a8f9
MV		 2502 default:
2503 /* If the device can't wake, don't set software support */
2504 if (!device_can_wakeup(&adapter->pdev->dev))
2505 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2506 }
2507
2508 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2509 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2510 adapter->wol |= E1000_WUFC_MAG;
2511
2512 /* Some vendors want WoL disabled by default, but still supported */
2513 if ((hw->mac.type == e1000_i350) &&
2514 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2515 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2516 adapter->wol = 0;
2517 }
2518
2519 device_set_wakeup_enable(&adapter->pdev->dev,
2520 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2521
2522 /* reset the hardware with the new settings */
2523 igb_reset(adapter);
2524
441fc6fd
CW		 2525 /* Init the I2C interface */
2526 err = igb_init_i2c(adapter);
2527 if (err) {
2528 dev_err(&pdev->dev, "failed to init i2c interface\n");
2529 goto err_eeprom;
2530 }
2531
9d5c8243 2532 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2533 * driver.
2534 */
9d5c8243
AK		 2535 igb_get_hw_control(adapter);
2536
9d5c8243
AK		 2537 strcpy(netdev->name, "eth%d");
2538 err = register_netdev(netdev);
2539 if (err)
2540 goto err_register;
2541
b168dfc5
JB		 2542 /* carrier off reporting is important to ethtool even BEFORE open */
2543 netif_carrier_off(netdev);
2544
421e02f0 2545#ifdef CONFIG_IGB_DCA
bbd98fe4 2546 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2547 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2548 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2549 igb_setup_dca(adapter);
2550 }
fe4506b6 2551
38c845c7 2552#endif
e428893b
CW		 2553#ifdef CONFIG_IGB_HWMON
2554 /* Initialize the thermal sensor on i350 devices. */
2555 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2556 u16 ets_word;
3c89f6d0 2557
b980ac18 2558 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2559 * external thermal sensor.
2560 */
2561 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2562 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2563 adapter->ets = true;
2564 else
2565 adapter->ets = false;
2566 if (igb_sysfs_init(adapter))
2567 dev_err(&pdev->dev,
2568 "failed to allocate sysfs resources\n");
2569 } else {
2570 adapter->ets = false;
2571 }
2572#endif
56cec249
CW		 2573 /* Check if Media Autosense is enabled */
2574 adapter->ei = *ei;
2575 if (hw->dev_spec._82575.mas_capable)
2576 igb_init_mas(adapter);
2577
673b8b70 2578 /* do hw tstamp init after resetting */
7ebae817 2579 igb_ptp_init(adapter);
673b8b70 2580
9d5c8243 2581 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2582 /* print bus type/speed/width info, not applicable to i354 */
2583 if (hw->mac.type != e1000_i354) {
2584 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2585 netdev->name,
2586 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2587 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2588 "unknown"),
2589 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2590 "Width x4" :
2591 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2592 "Width x2" :
2593 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2594 "Width x1" : "unknown"), netdev->dev_addr);
2595 }
9d5c8243 2596
53ea6c7e
TF		 2597 if ((hw->mac.type >= e1000_i210 ||
2598 igb_get_flash_presence_i210(hw))) {
2599 ret_val = igb_read_part_string(hw, part_str,
2600 E1000_PBANUM_LENGTH);
2601 } else {
2602 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2603 }
2604
9835fd73
CW		 2605 if (ret_val)
2606 strcpy(part_str, "Unknown");
2607 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2608 dev_info(&pdev->dev,
2609 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2610 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2611 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2612 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2613 if (hw->phy.media_type == e1000_media_type_copper) {
2614 switch (hw->mac.type) {
2615 case e1000_i350:
2616 case e1000_i210:
2617 case e1000_i211:
2618 /* Enable EEE for internal copper PHY devices */
c4c112f1 2619 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2620 if ((!err) &&
2621 (!hw->dev_spec._82575.eee_disable)) {
2622 adapter->eee_advert =
2623 MDIO_EEE_100TX | MDIO_EEE_1000T;
2624 adapter->flags |= IGB_FLAG_EEE;
2625 }
2626 break;
2627 case e1000_i354:
ceb5f13b 2628 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2629 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2630 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2631 if ((!err) &&
2632 (!hw->dev_spec._82575.eee_disable)) {
2633 adapter->eee_advert =
2634 MDIO_EEE_100TX | MDIO_EEE_1000T;
2635 adapter->flags |= IGB_FLAG_EEE;
2636 }
2637 }
2638 break;
2639 default:
2640 break;
ceb5f13b 2641 }
09b068d4 2642 }
749ab2cd 2643 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2644 return 0;
2645
2646err_register:
2647 igb_release_hw_control(adapter);
441fc6fd 2648 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2649err_eeprom:
2650 if (!igb_check_reset_block(hw))
f5f4cf08 2651 igb_reset_phy(hw);
9d5c8243
AK		 2652
2653 if (hw->flash_address)
2654 iounmap(hw->flash_address);
9d5c8243 2655err_sw_init:
42ad1a03 2656 kfree(adapter->shadow_vfta);
047e0030 2657 igb_clear_interrupt_scheme(adapter);
ceee3450
TF		 2658#ifdef CONFIG_PCI_IOV
2659 igb_disable_sriov(pdev);
2660#endif
73bf8048 2661 pci_iounmap(pdev, adapter->io_addr);
9d5c8243
AK		 2662err_ioremap:
2663 free_netdev(netdev);
2664err_alloc_etherdev:
559e9c49 2665 pci_release_selected_regions(pdev,
b980ac18 2666 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2667err_pci_reg:
2668err_dma:
2669 pci_disable_device(pdev);
2670 return err;
2671}
2672
fa44f2f1 2673#ifdef CONFIG_PCI_IOV
781798a1 2674static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2675{
2676 struct net_device *netdev = pci_get_drvdata(pdev);
2677 struct igb_adapter *adapter = netdev_priv(netdev);
2678 struct e1000_hw *hw = &adapter->hw;
2679
2680 /* reclaim resources allocated to VFs */
2681 if (adapter->vf_data) {
2682 /* disable iov and allow time for transactions to clear */
b09186d2 2683 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2684 dev_warn(&pdev->dev,
2685 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2686 return -EPERM;
2687 } else {
2688 pci_disable_sriov(pdev);
2689 msleep(500);
2690 }
2691
2692 kfree(adapter->vf_data);
2693 adapter->vf_data = NULL;
2694 adapter->vfs_allocated_count = 0;
2695 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2696 wrfl();
2697 msleep(100);
2698 dev_info(&pdev->dev, "IOV Disabled\n");
2699
2700 /* Re-enable DMA Coalescing flag since IOV is turned off */
2701 adapter->flags |= IGB_FLAG_DMAC;
2702 }
2703
2704 return 0;
2705}
2706
2707static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2708{
2709 struct net_device *netdev = pci_get_drvdata(pdev);
2710 struct igb_adapter *adapter = netdev_priv(netdev);
2711 int old_vfs = pci_num_vf(pdev);
2712 int err = 0;
2713 int i;
2714
cd14ef54 2715 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2716 err = -EPERM;
2717 goto out;
2718 }
fa44f2f1
GR		 2719 if (!num_vfs)
2720 goto out;
fa44f2f1 2721
781798a1
SA		 2722 if (old_vfs) {
2723 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2724 old_vfs, max_vfs);
2725 adapter->vfs_allocated_count = old_vfs;
2726 } else
2727 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2728
2729 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2730 sizeof(struct vf_data_storage), GFP_KERNEL);
2731
2732 /* if allocation failed then we do not support SR-IOV */
2733 if (!adapter->vf_data) {
2734 adapter->vfs_allocated_count = 0;
2735 dev_err(&pdev->dev,
2736 "Unable to allocate memory for VF Data Storage\n");
2737 err = -ENOMEM;
2738 goto out;
2739 }
2740
781798a1
SA		 2741 /* only call pci_enable_sriov() if no VFs are allocated already */
2742 if (!old_vfs) {
2743 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2744 if (err)
2745 goto err_out;
2746 }
fa44f2f1
GR		 2747 dev_info(&pdev->dev, "%d VFs allocated\n",
2748 adapter->vfs_allocated_count);
2749 for (i = 0; i < adapter->vfs_allocated_count; i++)
2750 igb_vf_configure(adapter, i);
2751
2752 /* DMA Coalescing is not supported in IOV mode. */
2753 adapter->flags &= ~IGB_FLAG_DMAC;
2754 goto out;
2755
2756err_out:
2757 kfree(adapter->vf_data);
2758 adapter->vf_data = NULL;
2759 adapter->vfs_allocated_count = 0;
2760out:
2761 return err;
2762}
2763
2764#endif
b980ac18 2765/**
441fc6fd
CW		 2766 * igb_remove_i2c - Cleanup I2C interface
2767 * @adapter: pointer to adapter structure
b980ac18 2768 **/
441fc6fd
CW		 2769static void igb_remove_i2c(struct igb_adapter *adapter)
2770{
441fc6fd
CW		 2771 /* free the adapter bus structure */
2772 i2c_del_adapter(&adapter->i2c_adap);
2773}
2774
9d5c8243 2775/**
b980ac18
JK		 2776 * igb_remove - Device Removal Routine
2777 * @pdev: PCI device information struct
9d5c8243 2778 *
b980ac18
JK		 2779 * igb_remove is called by the PCI subsystem to alert the driver
2780 * that it should release a PCI device. The could be caused by a
2781 * Hot-Plug event, or because the driver is going to be removed from
2782 * memory.
9d5c8243 2783 **/
9f9a12f8 2784static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2785{
2786 struct net_device *netdev = pci_get_drvdata(pdev);
2787 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2788 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2789
749ab2cd 2790 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2791#ifdef CONFIG_IGB_HWMON
2792 igb_sysfs_exit(adapter);
2793#endif
441fc6fd 2794 igb_remove_i2c(adapter);
a79f4f88 2795 igb_ptp_stop(adapter);
b980ac18 2796 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2797 * disable watchdog from being rescheduled.
2798 */
9d5c8243
AK		 2799 set_bit(__IGB_DOWN, &adapter->state);
2800 del_timer_sync(&adapter->watchdog_timer);
2801 del_timer_sync(&adapter->phy_info_timer);
2802
760141a5
TH		 2803 cancel_work_sync(&adapter->reset_task);
2804 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2805
421e02f0 2806#ifdef CONFIG_IGB_DCA
7dfc16fa 2807 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2808 dev_info(&pdev->dev, "DCA disabled\n");
2809 dca_remove_requester(&pdev->dev);
7dfc16fa 2810 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2811 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2812 }
2813#endif
2814
9d5c8243 2815 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2816 * would have already happened in close and is redundant.
2817 */
9d5c8243
AK		 2818 igb_release_hw_control(adapter);
2819
37680117 2820#ifdef CONFIG_PCI_IOV
fa44f2f1 2821 igb_disable_sriov(pdev);
37680117 2822#endif
559e9c49 2823
c23d92b8
AW		 2824 unregister_netdev(netdev);
2825
2826 igb_clear_interrupt_scheme(adapter);
2827
73bf8048 2828 pci_iounmap(pdev, adapter->io_addr);
28b0759c
AD		 2829 if (hw->flash_address)
2830 iounmap(hw->flash_address);
559e9c49 2831 pci_release_selected_regions(pdev,
b980ac18 2832 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2833
1128c756 2834 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2835 free_netdev(netdev);
2836
19d5afd4 2837 pci_disable_pcie_error_reporting(pdev);
40a914fa 2838
9d5c8243
AK		 2839 pci_disable_device(pdev);
2840}
2841
a6b623e0 2842/**
b980ac18
JK		 2843 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2844 * @adapter: board private structure to initialize
a6b623e0 2845 *
b980ac18
JK		 2846 * This function initializes the vf specific data storage and then attempts to
2847 * allocate the VFs. The reason for ordering it this way is because it is much
2848 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2849 * the memory for the VFs.
a6b623e0 2850 **/
9f9a12f8 2851static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2852{
2853#ifdef CONFIG_PCI_IOV
2854 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2855 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2856
f96a8a0b
CW		 2857 /* Virtualization features not supported on i210 family. */
2858 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2859 return;
2860
fa44f2f1 2861 pci_sriov_set_totalvfs(pdev, 7);
6423fc34 2862 igb_enable_sriov(pdev, max_vfs);
0224d663 2863
a6b623e0
AD		 2864#endif /* CONFIG_PCI_IOV */
2865}
2866
fa44f2f1 2867static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2868{
2869 struct e1000_hw *hw = &adapter->hw;
374a542d 2870 u32 max_rss_queues;
9d5c8243 2871
374a542d 2872 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2873 switch (hw->mac.type) {
374a542d
MV		 2874 case e1000_i211:
2875 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2876 break;
2877 case e1000_82575:
f96a8a0b 2878 case e1000_i210:
374a542d
MV		 2879 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2880 break;
2881 case e1000_i350:
2882 /* I350 cannot do RSS and SR-IOV at the same time */
2883 if (!!adapter->vfs_allocated_count) {
2884 max_rss_queues = 1;
2885 break;
2886 }
2887 /* fall through */
2888 case e1000_82576:
2889 if (!!adapter->vfs_allocated_count) {
2890 max_rss_queues = 2;
2891 break;
2892 }
2893 /* fall through */
2894 case e1000_82580:
ceb5f13b 2895 case e1000_i354:
374a542d
MV		 2896 default:
2897 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2898 break;
374a542d
MV		 2899 }
2900
2901 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2902
72ddef05
SS		 2903 igb_set_flag_queue_pairs(adapter, max_rss_queues);
2904}
2905
2906void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
2907 const u32 max_rss_queues)
2908{
2909 struct e1000_hw *hw = &adapter->hw;
2910
374a542d
MV		 2911 /* Determine if we need to pair queues. */
2912 switch (hw->mac.type) {
2913 case e1000_82575:
f96a8a0b 2914 case e1000_i211:
374a542d 2915 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2916 break;
374a542d 2917 case e1000_82576:
b980ac18 2918 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2919 * should pair the queues in order to conserve interrupts due
2920 * to limited supply.
2921 */
2922 if ((adapter->rss_queues > 1) &&
2923 (adapter->vfs_allocated_count > 6))
2924 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2925 /* fall through */
2926 case e1000_82580:
2927 case e1000_i350:
ceb5f13b 2928 case e1000_i354:
374a542d 2929 case e1000_i210:
f96a8a0b 2930 default:
b980ac18 2931 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2932 * order to conserve interrupts due to limited supply.
2933 */
2934 if (adapter->rss_queues > (max_rss_queues / 2))
2935 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2936 break;
2937 }
fa44f2f1
GR		 2938}
2939
2940/**
b980ac18
JK		 2941 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2942 * @adapter: board private structure to initialize
fa44f2f1 2943 *
b980ac18
JK		 2944 * igb_sw_init initializes the Adapter private data structure.
2945 * Fields are initialized based on PCI device information and
2946 * OS network device settings (MTU size).
fa44f2f1
GR		 2947 **/
2948static int igb_sw_init(struct igb_adapter *adapter)
2949{
2950 struct e1000_hw *hw = &adapter->hw;
2951 struct net_device *netdev = adapter->netdev;
2952 struct pci_dev *pdev = adapter->pdev;
2953
2954 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2955
2956 /* set default ring sizes */
2957 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2958 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2959
2960 /* set default ITR values */
2961 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2962 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2963
2964 /* set default work limits */
2965 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2966
2967 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2968 VLAN_HLEN;
2969 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2970
2971 spin_lock_init(&adapter->stats64_lock);
2972#ifdef CONFIG_PCI_IOV
2973 switch (hw->mac.type) {
2974 case e1000_82576:
2975 case e1000_i350:
2976 if (max_vfs > 7) {
2977 dev_warn(&pdev->dev,
2978 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2979 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2980 } else
2981 adapter->vfs_allocated_count = max_vfs;
2982 if (adapter->vfs_allocated_count)
2983 dev_warn(&pdev->dev,
2984 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2985 break;
2986 default:
2987 break;
2988 }
2989#endif /* CONFIG_PCI_IOV */
2990
cbfe360a
SA		 2991 /* Assume MSI-X interrupts, will be checked during IRQ allocation */
2992 adapter->flags |= IGB_FLAG_HAS_MSIX;
2993
ceee3450
TF		 2994 igb_probe_vfs(adapter);
2995
fa44f2f1 2996 igb_init_queue_configuration(adapter);
a99955fc 2997
1128c756 2998 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2999 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3000 GFP_ATOMIC);
1128c756 3001
a6b623e0 3002 /* This call may decrease the number of queues */
53c7d064 3003 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 3004 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3005 return -ENOMEM;
3006 }
3007
3008 /* Explicitly disable IRQ since the NIC can be in any state. */
3009 igb_irq_disable(adapter);
3010
f96a8a0b 3011 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3012 adapter->flags &= ~IGB_FLAG_DMAC;
3013
9d5c8243
AK		 3014 set_bit(__IGB_DOWN, &adapter->state);
3015 return 0;
3016}
3017
3018/**
b980ac18
JK		 3019 * igb_open - Called when a network interface is made active
3020 * @netdev: network interface device structure
9d5c8243 3021 *
b980ac18 3022 * Returns 0 on success, negative value on failure
9d5c8243 3023 *
b980ac18
JK		 3024 * The open entry point is called when a network interface is made
3025 * active by the system (IFF_UP). At this point all resources needed
3026 * for transmit and receive operations are allocated, the interrupt
3027 * handler is registered with the OS, the watchdog timer is started,
3028 * and the stack is notified that the interface is ready.
9d5c8243 3029 **/
749ab2cd 3030static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3031{
3032 struct igb_adapter *adapter = netdev_priv(netdev);
3033 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3034 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3035 int err;
3036 int i;
3037
3038 /* disallow open during test */
749ab2cd
YZ		 3039 if (test_bit(__IGB_TESTING, &adapter->state)) {
3040 WARN_ON(resuming);
9d5c8243 3041 return -EBUSY;
749ab2cd
YZ		 3042 }
3043
3044 if (!resuming)
3045 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3046
b168dfc5
JB		 3047 netif_carrier_off(netdev);
3048
9d5c8243
AK		 3049 /* allocate transmit descriptors */
3050 err = igb_setup_all_tx_resources(adapter);
3051 if (err)
3052 goto err_setup_tx;
3053
3054 /* allocate receive descriptors */
3055 err = igb_setup_all_rx_resources(adapter);
3056 if (err)
3057 goto err_setup_rx;
3058
88a268c1 3059 igb_power_up_link(adapter);
9d5c8243 3060
9d5c8243
AK		 3061 /* before we allocate an interrupt, we must be ready to handle it.
3062 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3063 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3064 * clean_rx handler before we do so.
3065 */
9d5c8243
AK		 3066 igb_configure(adapter);
3067
3068 err = igb_request_irq(adapter);
3069 if (err)
3070 goto err_req_irq;
3071
0c2cc02e
AD		 3072 /* Notify the stack of the actual queue counts. */
3073 err = netif_set_real_num_tx_queues(adapter->netdev,
3074 adapter->num_tx_queues);
3075 if (err)
3076 goto err_set_queues;
3077
3078 err = netif_set_real_num_rx_queues(adapter->netdev,
3079 adapter->num_rx_queues);
3080 if (err)
3081 goto err_set_queues;
3082
9d5c8243
AK		 3083 /* From here on the code is the same as igb_up() */
3084 clear_bit(__IGB_DOWN, &adapter->state);
3085
0d1ae7f4
AD		 3086 for (i = 0; i < adapter->num_q_vectors; i++)
3087 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3088
3089 /* Clear any pending interrupts. */
3090 rd32(E1000_ICR);
844290e5
PW		 3091
3092 igb_irq_enable(adapter);
3093
d4960307
AD		 3094 /* notify VFs that reset has been completed */
3095 if (adapter->vfs_allocated_count) {
3096 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3097
d4960307
AD		 3098 reg_data |= E1000_CTRL_EXT_PFRSTD;
3099 wr32(E1000_CTRL_EXT, reg_data);
3100 }
3101
d55b53ff
JK		 3102 netif_tx_start_all_queues(netdev);
3103
749ab2cd
YZ		 3104 if (!resuming)
3105 pm_runtime_put(&pdev->dev);
3106
25568a53
AD		 3107 /* start the watchdog. */
3108 hw->mac.get_link_status = 1;
3109 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3110
3111 return 0;
3112
0c2cc02e
AD		 3113err_set_queues:
3114 igb_free_irq(adapter);
9d5c8243
AK		 3115err_req_irq:
3116 igb_release_hw_control(adapter);
88a268c1 3117 igb_power_down_link(adapter);
9d5c8243
AK		 3118 igb_free_all_rx_resources(adapter);
3119err_setup_rx:
3120 igb_free_all_tx_resources(adapter);
3121err_setup_tx:
3122 igb_reset(adapter);
749ab2cd
YZ		 3123 if (!resuming)
3124 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3125
3126 return err;
3127}
3128
749ab2cd
YZ		 3129static int igb_open(struct net_device *netdev)
3130{
3131 return __igb_open(netdev, false);
3132}
3133
9d5c8243 3134/**
b980ac18
JK		 3135 * igb_close - Disables a network interface
3136 * @netdev: network interface device structure
9d5c8243 3137 *
b980ac18 3138 * Returns 0, this is not allowed to fail
9d5c8243 3139 *
b980ac18
JK		 3140 * The close entry point is called when an interface is de-activated
3141 * by the OS. The hardware is still under the driver's control, but
3142 * needs to be disabled. A global MAC reset is issued to stop the
3143 * hardware, and all transmit and receive resources are freed.
9d5c8243 3144 **/
749ab2cd 3145static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3146{
3147 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3148 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3149
3150 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3151
749ab2cd
YZ		 3152 if (!suspending)
3153 pm_runtime_get_sync(&pdev->dev);
3154
3155 igb_down(adapter);
9d5c8243
AK		 3156 igb_free_irq(adapter);
3157
3158 igb_free_all_tx_resources(adapter);
3159 igb_free_all_rx_resources(adapter);
3160
749ab2cd
YZ		 3161 if (!suspending)
3162 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3163 return 0;
3164}
3165
749ab2cd
YZ		 3166static int igb_close(struct net_device *netdev)
3167{
3168 return __igb_close(netdev, false);
3169}
3170
9d5c8243 3171/**
b980ac18
JK		 3172 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3173 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3174 *
b980ac18 3175 * Return 0 on success, negative on failure
9d5c8243 3176 **/
80785298 3177int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3178{
59d71989 3179 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3180 int size;
3181
06034649 3182 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3183
3184 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3185 if (!tx_ring->tx_buffer_info)
9d5c8243 3186 goto err;
9d5c8243
AK		 3187
3188 /* round up to nearest 4K */
85e8d004 3189 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3190 tx_ring->size = ALIGN(tx_ring->size, 4096);
3191
5536d210
AD		 3192 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3193 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3194 if (!tx_ring->desc)
3195 goto err;
3196
9d5c8243
AK		 3197 tx_ring->next_to_use = 0;
3198 tx_ring->next_to_clean = 0;
81c2fc22 3199
9d5c8243
AK		 3200 return 0;
3201
3202err:
06034649 3203 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3204 tx_ring->tx_buffer_info = NULL;
3205 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3206 return -ENOMEM;
3207}
3208
3209/**
b980ac18
JK		 3210 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3211 * (Descriptors) for all queues
3212 * @adapter: board private structure
9d5c8243 3213 *
b980ac18 3214 * Return 0 on success, negative on failure
9d5c8243
AK		 3215 **/
3216static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3217{
439705e1 3218 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3219 int i, err = 0;
3220
3221 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3222 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3223 if (err) {
439705e1 3224 dev_err(&pdev->dev,
9d5c8243
AK		 3225 "Allocation for Tx Queue %u failed\n", i);
3226 for (i--; i >= 0; i--)
3025a446 3227 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3228 break;
3229 }
3230 }
3231
3232 return err;
3233}
3234
3235/**
b980ac18
JK		 3236 * igb_setup_tctl - configure the transmit control registers
3237 * @adapter: Board private structure
9d5c8243 3238 **/
d7ee5b3a 3239void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3240{
9d5c8243
AK		 3241 struct e1000_hw *hw = &adapter->hw;
3242 u32 tctl;
9d5c8243 3243
85b430b4
AD		 3244 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3245 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3246
3247 /* Program the Transmit Control Register */
9d5c8243
AK		 3248 tctl = rd32(E1000_TCTL);
3249 tctl &= ~E1000_TCTL_CT;
3250 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3251 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3252
3253 igb_config_collision_dist(hw);
3254
9d5c8243
AK		 3255 /* Enable transmits */
3256 tctl |= E1000_TCTL_EN;
3257
3258 wr32(E1000_TCTL, tctl);
3259}
3260
85b430b4 3261/**
b980ac18
JK		 3262 * igb_configure_tx_ring - Configure transmit ring after Reset
3263 * @adapter: board private structure
3264 * @ring: tx ring to configure
85b430b4 3265 *
b980ac18 3266 * Configure a transmit ring after a reset.
85b430b4 3267 **/
d7ee5b3a 3268void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3269 struct igb_ring *ring)
85b430b4
AD		 3270{
3271 struct e1000_hw *hw = &adapter->hw;
a74420e0 3272 u32 txdctl = 0;
85b430b4
AD		 3273 u64 tdba = ring->dma;
3274 int reg_idx = ring->reg_idx;
3275
3276 /* disable the queue */
a74420e0 3277 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3278 wrfl();
3279 mdelay(10);
3280
3281 wr32(E1000_TDLEN(reg_idx),
b980ac18 3282 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3283 wr32(E1000_TDBAL(reg_idx),
b980ac18 3284 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3285 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3286
fce99e34 3287 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3288 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3289 writel(0, ring->tail);
85b430b4
AD		 3290
3291 txdctl |= IGB_TX_PTHRESH;
3292 txdctl |= IGB_TX_HTHRESH << 8;
3293 txdctl |= IGB_TX_WTHRESH << 16;
3294
3295 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3296 wr32(E1000_TXDCTL(reg_idx), txdctl);
3297}
3298
3299/**
b980ac18
JK		 3300 * igb_configure_tx - Configure transmit Unit after Reset
3301 * @adapter: board private structure
85b430b4 3302 *
b980ac18 3303 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3304 **/
3305static void igb_configure_tx(struct igb_adapter *adapter)
3306{
3307 int i;
3308
3309 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3310 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3311}
3312
9d5c8243 3313/**
b980ac18
JK		 3314 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3315 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3316 *
b980ac18 3317 * Returns 0 on success, negative on failure
9d5c8243 3318 **/
80785298 3319int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3320{
59d71989 3321 struct device *dev = rx_ring->dev;
f33005a6 3322 int size;
9d5c8243 3323
06034649 3324 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3325
3326 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3327 if (!rx_ring->rx_buffer_info)
9d5c8243 3328 goto err;
9d5c8243 3329
9d5c8243 3330 /* Round up to nearest 4K */
f33005a6 3331 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3332 rx_ring->size = ALIGN(rx_ring->size, 4096);
3333
5536d210
AD		 3334 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3335 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3336 if (!rx_ring->desc)
3337 goto err;
3338
cbc8e55f 3339 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3340 rx_ring->next_to_clean = 0;
3341 rx_ring->next_to_use = 0;
9d5c8243 3342
9d5c8243
AK		 3343 return 0;
3344
3345err:
06034649
AD		 3346 vfree(rx_ring->rx_buffer_info);
3347 rx_ring->rx_buffer_info = NULL;
f33005a6 3348 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3349 return -ENOMEM;
3350}
3351
3352/**
b980ac18
JK		 3353 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3354 * (Descriptors) for all queues
3355 * @adapter: board private structure
9d5c8243 3356 *
b980ac18 3357 * Return 0 on success, negative on failure
9d5c8243
AK		 3358 **/
3359static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3360{
439705e1 3361 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3362 int i, err = 0;
3363
3364 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3365 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3366 if (err) {
439705e1 3367 dev_err(&pdev->dev,
9d5c8243
AK		 3368 "Allocation for Rx Queue %u failed\n", i);
3369 for (i--; i >= 0; i--)
3025a446 3370 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3371 break;
3372 }
3373 }
3374
3375 return err;
3376}
3377
06cf2666 3378/**
b980ac18
JK		 3379 * igb_setup_mrqc - configure the multiple receive queue control registers
3380 * @adapter: Board private structure
06cf2666
AD		 3381 **/
3382static void igb_setup_mrqc(struct igb_adapter *adapter)
3383{
3384 struct e1000_hw *hw = &adapter->hw;
3385 u32 mrqc, rxcsum;
ed12cc9a 3386 u32 j, num_rx_queues;
eb31f849 3387 u32 rss_key[10];
06cf2666 3388
eb31f849 3389 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3390 for (j = 0; j < 10; j++)
eb31f849 3391 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3392
a99955fc 3393 num_rx_queues = adapter->rss_queues;
06cf2666 3394
797fd4be 3395 switch (hw->mac.type) {
797fd4be
AD		 3396 case e1000_82576:
3397 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3398 if (adapter->vfs_allocated_count)
06cf2666 3399 num_rx_queues = 2;
797fd4be
AD		 3400 break;
3401 default:
3402 break;
06cf2666
AD		 3403 }
3404
ed12cc9a
LMV		 3405 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3406 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3407 adapter->rss_indir_tbl[j] =
3408 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3409 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3410 }
ed12cc9a 3411 igb_write_rss_indir_tbl(adapter);
06cf2666 3412
b980ac18 3413 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3414 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3415 * offloads as they are enabled by default
3416 */
3417 rxcsum = rd32(E1000_RXCSUM);
3418 rxcsum |= E1000_RXCSUM_PCSD;
3419
3420 if (adapter->hw.mac.type >= e1000_82576)
3421 /* Enable Receive Checksum Offload for SCTP */
3422 rxcsum |= E1000_RXCSUM_CRCOFL;
3423
3424 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3425 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3426
039454a8
AA		 3427 /* Generate RSS hash based on packet types, TCP/UDP
3428 * port numbers and/or IPv4/v6 src and dst addresses
3429 */
f96a8a0b
CW		 3430 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3431 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3432 E1000_MRQC_RSS_FIELD_IPV6 |
3433 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3434 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3435
039454a8
AA		 3436 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3437 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3438 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3439 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3440
06cf2666
AD		 3441 /* If VMDq is enabled then we set the appropriate mode for that, else
3442 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3443 * if we are only using one queue
3444 */
06cf2666
AD		 3445 if (adapter->vfs_allocated_count) {
3446 if (hw->mac.type > e1000_82575) {
3447 /* Set the default pool for the PF's first queue */
3448 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3449
06cf2666
AD		 3450 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3451 E1000_VT_CTL_DISABLE_DEF_POOL);
3452 vtctl |= adapter->vfs_allocated_count <<
3453 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3454 wr32(E1000_VT_CTL, vtctl);
3455 }
a99955fc 3456 if (adapter->rss_queues > 1)
f96a8a0b 3457 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3458 else
f96a8a0b 3459 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3460 } else {
f96a8a0b
CW		 3461 if (hw->mac.type != e1000_i211)
3462 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3463 }
3464 igb_vmm_control(adapter);
3465
06cf2666
AD		 3466 wr32(E1000_MRQC, mrqc);
3467}
3468
9d5c8243 3469/**
b980ac18
JK		 3470 * igb_setup_rctl - configure the receive control registers
3471 * @adapter: Board private structure
9d5c8243 3472 **/
d7ee5b3a 3473void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3474{
3475 struct e1000_hw *hw = &adapter->hw;
3476 u32 rctl;
9d5c8243
AK		 3477
3478 rctl = rd32(E1000_RCTL);
3479
3480 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3481 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3482
69d728ba 3483 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3484 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3485
b980ac18 3486 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3487 * redirection as it did with e1000. Newer features require
3488 * that the HW strips the CRC.
73cd78f1 3489 */
87cb7e8c 3490 rctl |= E1000_RCTL_SECRC;
9d5c8243 3491
559e9c49 3492 /* disable store bad packets and clear size bits. */
ec54d7d6 3493 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3494
6ec43fe6
AD		 3495 /* enable LPE to prevent packets larger than max_frame_size */
3496 rctl |= E1000_RCTL_LPE;
9d5c8243 3497
952f72a8
AD		 3498 /* disable queue 0 to prevent tail write w/o re-config */
3499 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3500
e1739522
AD		 3501 /* Attention!!! For SR-IOV PF driver operations you must enable
3502 * queue drop for all VF and PF queues to prevent head of line blocking
3503 * if an un-trusted VF does not provide descriptors to hardware.
3504 */
3505 if (adapter->vfs_allocated_count) {
e1739522
AD		 3506 /* set all queue drop enable bits */
3507 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3508 }
3509
89eaefb6
BG		 3510 /* This is useful for sniffing bad packets. */
3511 if (adapter->netdev->features & NETIF_F_RXALL) {
3512 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3513 * in e1000e_set_rx_mode
3514 */
89eaefb6
BG		 3515 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3516 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3517 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3518
3519 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3520 E1000_RCTL_DPF | /* Allow filtered pause */
3521 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3522 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3523 * and that breaks VLANs.
3524 */
3525 }
3526
9d5c8243
AK		 3527 wr32(E1000_RCTL, rctl);
3528}
3529
7d5753f0 3530static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3531 int vfn)
7d5753f0
AD		 3532{
3533 struct e1000_hw *hw = &adapter->hw;
3534 u32 vmolr;
3535
3536 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3537 * increase the size to support vlan tags
3538 */
7d5753f0
AD		 3539 if (vfn < adapter->vfs_allocated_count &&
3540 adapter->vf_data[vfn].vlans_enabled)
3541 size += VLAN_TAG_SIZE;
3542
3543 vmolr = rd32(E1000_VMOLR(vfn));
3544 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3545 vmolr |= size | E1000_VMOLR_LPE;
3546 wr32(E1000_VMOLR(vfn), vmolr);
3547
3548 return 0;
3549}
3550
e1739522 3551/**
b980ac18
JK		 3552 * igb_rlpml_set - set maximum receive packet size
3553 * @adapter: board private structure
e1739522 3554 *
b980ac18 3555 * Configure maximum receivable packet size.
e1739522
AD		 3556 **/
3557static void igb_rlpml_set(struct igb_adapter *adapter)
3558{
153285f9 3559 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3560 struct e1000_hw *hw = &adapter->hw;
3561 u16 pf_id = adapter->vfs_allocated_count;
3562
e1739522
AD		 3563 if (pf_id) {
3564 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3565 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3566 * to our max jumbo frame size, in case we need to enable
3567 * jumbo frames on one of the rings later.
3568 * This will not pass over-length frames into the default
3569 * queue because it's gated by the VMOLR.RLPML.
3570 */
7d5753f0 3571 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3572 }
3573
3574 wr32(E1000_RLPML, max_frame_size);
3575}
3576
8151d294
WM		 3577static inline void igb_set_vmolr(struct igb_adapter *adapter,
3578 int vfn, bool aupe)
7d5753f0
AD		 3579{
3580 struct e1000_hw *hw = &adapter->hw;
3581 u32 vmolr;
3582
b980ac18 3583 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3584 * we should exit and do nothing
3585 */
3586 if (hw->mac.type < e1000_82576)
3587 return;
3588
3589 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3590 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3591 if (hw->mac.type == e1000_i350) {
3592 u32 dvmolr;
3593
3594 dvmolr = rd32(E1000_DVMOLR(vfn));
3595 dvmolr |= E1000_DVMOLR_STRVLAN;
3596 wr32(E1000_DVMOLR(vfn), dvmolr);
3597 }
8151d294 3598 if (aupe)
b980ac18 3599 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3600 else
3601 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3602
3603 /* clear all bits that might not be set */
3604 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3605
a99955fc 3606 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3607 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3608 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3609 * multicast packets
3610 */
3611 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3612 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3613
3614 wr32(E1000_VMOLR(vfn), vmolr);
3615}
3616
85b430b4 3617/**
b980ac18
JK		 3618 * igb_configure_rx_ring - Configure a receive ring after Reset
3619 * @adapter: board private structure
3620 * @ring: receive ring to be configured
85b430b4 3621 *
b980ac18 3622 * Configure the Rx unit of the MAC after a reset.
85b430b4 3623 **/
d7ee5b3a 3624void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3625 struct igb_ring *ring)
85b430b4
AD		 3626{
3627 struct e1000_hw *hw = &adapter->hw;
3628 u64 rdba = ring->dma;
3629 int reg_idx = ring->reg_idx;
a74420e0 3630 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3631
3632 /* disable the queue */
a74420e0 3633 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3634
3635 /* Set DMA base address registers */
3636 wr32(E1000_RDBAL(reg_idx),
3637 rdba & 0x00000000ffffffffULL);
3638 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3639 wr32(E1000_RDLEN(reg_idx),
b980ac18 3640 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3641
3642 /* initialize head and tail */
fce99e34 3643 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3644 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3645 writel(0, ring->tail);
85b430b4 3646
952f72a8 3647 /* set descriptor configuration */
44390ca6 3648 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3649 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3650 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3651 if (hw->mac.type >= e1000_82580)
757b77e2 3652 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3653 /* Only set Drop Enable if we are supporting multiple queues */
3654 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3655 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3656
3657 wr32(E1000_SRRCTL(reg_idx), srrctl);
3658
7d5753f0 3659 /* set filtering for VMDQ pools */
8151d294 3660 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3661
85b430b4
AD		 3662 rxdctl |= IGB_RX_PTHRESH;
3663 rxdctl |= IGB_RX_HTHRESH << 8;
3664 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3665
3666 /* enable receive descriptor fetching */
3667 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3668 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3669}
3670
9d5c8243 3671/**
b980ac18
JK		 3672 * igb_configure_rx - Configure receive Unit after Reset
3673 * @adapter: board private structure
9d5c8243 3674 *
b980ac18 3675 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3676 **/
3677static void igb_configure_rx(struct igb_adapter *adapter)
3678{
9107584e 3679 int i;
9d5c8243 3680
68d480c4
AD		 3681 /* set UTA to appropriate mode */
3682 igb_set_uta(adapter);
3683
26ad9178
AD		 3684 /* set the correct pool for the PF default MAC address in entry 0 */
3685 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3686 adapter->vfs_allocated_count);
26ad9178 3687
06cf2666 3688 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3689 * the Base and Length of the Rx Descriptor Ring
3690 */
f9d40f6a
AD		 3691 for (i = 0; i < adapter->num_rx_queues; i++)
3692 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3693}
3694
3695/**
b980ac18
JK		 3696 * igb_free_tx_resources - Free Tx Resources per Queue
3697 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3698 *
b980ac18 3699 * Free all transmit software resources
9d5c8243 3700 **/
68fd9910 3701void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3702{
3b644cf6 3703 igb_clean_tx_ring(tx_ring);
9d5c8243 3704
06034649
AD		 3705 vfree(tx_ring->tx_buffer_info);
3706 tx_ring->tx_buffer_info = NULL;
9d5c8243 3707
439705e1
AD		 3708 /* if not set, then don't free */
3709 if (!tx_ring->desc)
3710 return;
3711
59d71989
AD		 3712 dma_free_coherent(tx_ring->dev, tx_ring->size,
3713 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3714
3715 tx_ring->desc = NULL;
3716}
3717
3718/**
b980ac18
JK		 3719 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3720 * @adapter: board private structure
9d5c8243 3721 *
b980ac18 3722 * Free all transmit software resources
9d5c8243
AK		 3723 **/
3724static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3725{
3726 int i;
3727
3728 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3729 if (adapter->tx_ring[i])
3730 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3731}
3732
ebe42d16
AD		 3733void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3734 struct igb_tx_buffer *tx_buffer)
3735{
3736 if (tx_buffer->skb) {
3737 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3738 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3739 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3740 dma_unmap_addr(tx_buffer, dma),
3741 dma_unmap_len(tx_buffer, len),
ebe42d16 3742 DMA_TO_DEVICE);
c9f14bf3 3743 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3744 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3745 dma_unmap_addr(tx_buffer, dma),
3746 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3747 DMA_TO_DEVICE);
3748 }
3749 tx_buffer->next_to_watch = NULL;
3750 tx_buffer->skb = NULL;
c9f14bf3 3751 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3752 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3753}
3754
3755/**
b980ac18
JK		 3756 * igb_clean_tx_ring - Free Tx Buffers
3757 * @tx_ring: ring to be cleaned
9d5c8243 3758 **/
3b644cf6 3759static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3760{
06034649 3761 struct igb_tx_buffer *buffer_info;
9d5c8243 3762 unsigned long size;
6ad4edfc 3763 u16 i;
9d5c8243 3764
06034649 3765 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3766 return;
3767 /* Free all the Tx ring sk_buffs */
3768
3769 for (i = 0; i < tx_ring->count; i++) {
06034649 3770 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3771 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3772 }
3773
dad8a3b3
JF		 3774 netdev_tx_reset_queue(txring_txq(tx_ring));
3775
06034649
AD		 3776 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3777 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3778
3779 /* Zero out the descriptor ring */
9d5c8243
AK		 3780 memset(tx_ring->desc, 0, tx_ring->size);
3781
3782 tx_ring->next_to_use = 0;
3783 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3784}
3785
3786/**
b980ac18
JK		 3787 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3788 * @adapter: board private structure
9d5c8243
AK		 3789 **/
3790static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3791{
3792 int i;
3793
3794 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3795 if (adapter->tx_ring[i])
3796 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3797}
3798
3799/**
b980ac18
JK		 3800 * igb_free_rx_resources - Free Rx Resources
3801 * @rx_ring: ring to clean the resources from
9d5c8243 3802 *
b980ac18 3803 * Free all receive software resources
9d5c8243 3804 **/
68fd9910 3805void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3806{
3b644cf6 3807 igb_clean_rx_ring(rx_ring);
9d5c8243 3808
06034649
AD		 3809 vfree(rx_ring->rx_buffer_info);
3810 rx_ring->rx_buffer_info = NULL;
9d5c8243 3811
439705e1
AD		 3812 /* if not set, then don't free */
3813 if (!rx_ring->desc)
3814 return;
3815
59d71989
AD		 3816 dma_free_coherent(rx_ring->dev, rx_ring->size,
3817 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3818
3819 rx_ring->desc = NULL;
3820}
3821
3822/**
b980ac18
JK		 3823 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3824 * @adapter: board private structure
9d5c8243 3825 *
b980ac18 3826 * Free all receive software resources
9d5c8243
AK		 3827 **/
3828static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3829{
3830 int i;
3831
3832 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3833 if (adapter->rx_ring[i])
3834 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3835}
3836
3837/**
b980ac18
JK		 3838 * igb_clean_rx_ring - Free Rx Buffers per Queue
3839 * @rx_ring: ring to free buffers from
9d5c8243 3840 **/
3b644cf6 3841static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3842{
9d5c8243 3843 unsigned long size;
c023cd88 3844 u16 i;
9d5c8243 3845
1a1c225b
AD		 3846 if (rx_ring->skb)
3847 dev_kfree_skb(rx_ring->skb);
3848 rx_ring->skb = NULL;
3849
06034649 3850 if (!rx_ring->rx_buffer_info)
9d5c8243 3851 return;
439705e1 3852
9d5c8243
AK		 3853 /* Free all the Rx ring sk_buffs */
3854 for (i = 0; i < rx_ring->count; i++) {
06034649 3855 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3856
cbc8e55f
AD		 3857 if (!buffer_info->page)
3858 continue;
3859
3860 dma_unmap_page(rx_ring->dev,
3861 buffer_info->dma,
3862 PAGE_SIZE,
3863 DMA_FROM_DEVICE);
3864 __free_page(buffer_info->page);
3865
1a1c225b 3866 buffer_info->page = NULL;
9d5c8243
AK		 3867 }
3868
06034649
AD		 3869 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3870 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3871
3872 /* Zero out the descriptor ring */
3873 memset(rx_ring->desc, 0, rx_ring->size);
3874
cbc8e55f 3875 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3876 rx_ring->next_to_clean = 0;
3877 rx_ring->next_to_use = 0;
9d5c8243
AK		 3878}
3879
3880/**
b980ac18
JK		 3881 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3882 * @adapter: board private structure
9d5c8243
AK		 3883 **/
3884static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3885{
3886 int i;
3887
3888 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3889 if (adapter->rx_ring[i])
3890 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3891}
3892
3893/**
b980ac18
JK		 3894 * igb_set_mac - Change the Ethernet Address of the NIC
3895 * @netdev: network interface device structure
3896 * @p: pointer to an address structure
9d5c8243 3897 *
b980ac18 3898 * Returns 0 on success, negative on failure
9d5c8243
AK		 3899 **/
3900static int igb_set_mac(struct net_device *netdev, void *p)
3901{
3902 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3903 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3904 struct sockaddr *addr = p;
3905
3906 if (!is_valid_ether_addr(addr->sa_data))
3907 return -EADDRNOTAVAIL;
3908
3909 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3910 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3911
26ad9178
AD		 3912 /* set the correct pool for the new PF MAC address in entry 0 */
3913 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3914 adapter->vfs_allocated_count);
e1739522 3915
9d5c8243
AK		 3916 return 0;
3917}
3918
3919/**
b980ac18
JK		 3920 * igb_write_mc_addr_list - write multicast addresses to MTA
3921 * @netdev: network interface device structure
9d5c8243 3922 *
b980ac18
JK		 3923 * Writes multicast address list to the MTA hash table.
3924 * Returns: -ENOMEM on failure
3925 * 0 on no addresses written
3926 * X on writing X addresses to MTA
9d5c8243 3927 **/
68d480c4 3928static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3929{
3930 struct igb_adapter *adapter = netdev_priv(netdev);
3931 struct e1000_hw *hw = &adapter->hw;
22bedad3 3932 struct netdev_hw_addr *ha;
68d480c4 3933 u8 *mta_list;
9d5c8243
AK		 3934 int i;
3935
4cd24eaf 3936 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3937 /* nothing to program, so clear mc list */
3938 igb_update_mc_addr_list(hw, NULL, 0);
3939 igb_restore_vf_multicasts(adapter);
3940 return 0;
3941 }
9d5c8243 3942
4cd24eaf 3943 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3944 if (!mta_list)
3945 return -ENOMEM;
ff41f8dc 3946
68d480c4 3947 /* The shared function expects a packed array of only addresses. */
48e2f183 3948 i = 0;
22bedad3
JP		 3949 netdev_for_each_mc_addr(ha, netdev)
3950 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3951
68d480c4
AD		 3952 igb_update_mc_addr_list(hw, mta_list, i);
3953 kfree(mta_list);
3954
4cd24eaf 3955 return netdev_mc_count(netdev);
68d480c4
AD		 3956}
3957
3958/**
b980ac18
JK		 3959 * igb_write_uc_addr_list - write unicast addresses to RAR table
3960 * @netdev: network interface device structure
68d480c4 3961 *
b980ac18
JK		 3962 * Writes unicast address list to the RAR table.
3963 * Returns: -ENOMEM on failure/insufficient address space
3964 * 0 on no addresses written
3965 * X on writing X addresses to the RAR table
68d480c4
AD		 3966 **/
3967static int igb_write_uc_addr_list(struct net_device *netdev)
3968{
3969 struct igb_adapter *adapter = netdev_priv(netdev);
3970 struct e1000_hw *hw = &adapter->hw;
3971 unsigned int vfn = adapter->vfs_allocated_count;
3972 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3973 int count = 0;
3974
3975 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3976 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3977 return -ENOMEM;
9d5c8243 3978
32e7bfc4 3979 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3980 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3981
3982 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3983 if (!rar_entries)
3984 break;
26ad9178 3985 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3986 rar_entries--,
3987 vfn);
68d480c4 3988 count++;
ff41f8dc
AD		 3989 }
3990 }
3991 /* write the addresses in reverse order to avoid write combining */
3992 for (; rar_entries > 0 ; rar_entries--) {
3993 wr32(E1000_RAH(rar_entries), 0);
3994 wr32(E1000_RAL(rar_entries), 0);
3995 }
3996 wrfl();
3997
68d480c4
AD		 3998 return count;
3999}
4000
4001/**
b980ac18
JK		 4002 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4003 * @netdev: network interface device structure
68d480c4 4004 *
b980ac18
JK		 4005 * The set_rx_mode entry point is called whenever the unicast or multicast
4006 * address lists or the network interface flags are updated. This routine is
4007 * responsible for configuring the hardware for proper unicast, multicast,
4008 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4009 **/
4010static void igb_set_rx_mode(struct net_device *netdev)
4011{
4012 struct igb_adapter *adapter = netdev_priv(netdev);
4013 struct e1000_hw *hw = &adapter->hw;
4014 unsigned int vfn = adapter->vfs_allocated_count;
4015 u32 rctl, vmolr = 0;
4016 int count;
4017
4018 /* Check for Promiscuous and All Multicast modes */
4019 rctl = rd32(E1000_RCTL);
4020
4021 /* clear the effected bits */
4022 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4023
4024 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4025 /* retain VLAN HW filtering if in VT mode */
7e44892c 4026 if (adapter->vfs_allocated_count)
6f3dc319 4027 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4028 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4029 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4030 } else {
4031 if (netdev->flags & IFF_ALLMULTI) {
4032 rctl |= E1000_RCTL_MPE;
4033 vmolr |= E1000_VMOLR_MPME;
4034 } else {
b980ac18 4035 /* Write addresses to the MTA, if the attempt fails
25985edc 4036 * then we should just turn on promiscuous mode so
68d480c4
AD		 4037 * that we can at least receive multicast traffic
4038 */
4039 count = igb_write_mc_addr_list(netdev);
4040 if (count < 0) {
4041 rctl |= E1000_RCTL_MPE;
4042 vmolr |= E1000_VMOLR_MPME;
4043 } else if (count) {
4044 vmolr |= E1000_VMOLR_ROMPE;
4045 }
4046 }
b980ac18 4047 /* Write addresses to available RAR registers, if there is not
68d480c4 4048 * sufficient space to store all the addresses then enable
25985edc 4049 * unicast promiscuous mode
68d480c4
AD		 4050 */
4051 count = igb_write_uc_addr_list(netdev);
4052 if (count < 0) {
4053 rctl |= E1000_RCTL_UPE;
4054 vmolr |= E1000_VMOLR_ROPE;
4055 }
4056 rctl |= E1000_RCTL_VFE;
28fc06f5 4057 }
68d480c4 4058 wr32(E1000_RCTL, rctl);
28fc06f5 4059
b980ac18 4060 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4061 * the VMOLR to enable the appropriate modes. Without this workaround
4062 * we will have issues with VLAN tag stripping not being done for frames
4063 * that are only arriving because we are the default pool
4064 */
f96a8a0b 4065 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4066 return;
9d5c8243 4067
68d480c4 4068 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4069 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4070 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4071 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4072}
4073
13800469
GR		 4074static void igb_check_wvbr(struct igb_adapter *adapter)
4075{
4076 struct e1000_hw *hw = &adapter->hw;
4077 u32 wvbr = 0;
4078
4079 switch (hw->mac.type) {
4080 case e1000_82576:
4081 case e1000_i350:
81ad807b
CW		 4082 wvbr = rd32(E1000_WVBR);
4083 if (!wvbr)
13800469
GR		 4084 return;
4085 break;
4086 default:
4087 break;
4088 }
4089
4090 adapter->wvbr |= wvbr;
4091}
4092
4093#define IGB_STAGGERED_QUEUE_OFFSET 8
4094
4095static void igb_spoof_check(struct igb_adapter *adapter)
4096{
4097 int j;
4098
4099 if (!adapter->wvbr)
4100 return;
4101
9005df38 4102 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4103 if (adapter->wvbr & (1 << j) ||
4104 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4105 dev_warn(&adapter->pdev->dev,
4106 "Spoof event(s) detected on VF %d\n", j);
4107 adapter->wvbr &=
4108 ~((1 << j) |
4109 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4110 }
4111 }
4112}
4113
9d5c8243 4114/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4115 * the phy
4116 */
9d5c8243
AK		 4117static void igb_update_phy_info(unsigned long data)
4118{
4119 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4120 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4121}
4122
4d6b725e 4123/**
b980ac18
JK		 4124 * igb_has_link - check shared code for link and determine up/down
4125 * @adapter: pointer to driver private info
4d6b725e 4126 **/
3145535a 4127bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4128{
4129 struct e1000_hw *hw = &adapter->hw;
4130 bool link_active = false;
4d6b725e
AD		 4131
4132 /* get_link_status is set on LSC (link status) interrupt or
4133 * rx sequence error interrupt. get_link_status will stay
4134 * false until the e1000_check_for_link establishes link
4135 * for copper adapters ONLY
4136 */
4137 switch (hw->phy.media_type) {
4138 case e1000_media_type_copper:
e5c3370f
AA		 4139 if (!hw->mac.get_link_status)
4140 return true;
4d6b725e 4141 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4142 hw->mac.ops.check_for_link(hw);
4143 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4144 break;
4145 default:
4146 case e1000_media_type_unknown:
4147 break;
4148 }
4149
aa9b8cc4
AA		 4150 if (((hw->mac.type == e1000_i210) ||
4151 (hw->mac.type == e1000_i211)) &&
4152 (hw->phy.id == I210_I_PHY_ID)) {
4153 if (!netif_carrier_ok(adapter->netdev)) {
4154 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4155 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4156 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4157 adapter->link_check_timeout = jiffies;
4158 }
4159 }
4160
4d6b725e
AD		 4161 return link_active;
4162}
4163
563988dc
SA		 4164static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4165{
4166 bool ret = false;
4167 u32 ctrl_ext, thstat;
4168
f96a8a0b 4169 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4170 if (hw->mac.type == e1000_i350) {
4171 thstat = rd32(E1000_THSTAT);
4172 ctrl_ext = rd32(E1000_CTRL_EXT);
4173
4174 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4175 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4176 ret = !!(thstat & event);
563988dc
SA		 4177 }
4178
4179 return ret;
4180}
4181
1516f0a6
CW		 4182/**
4183 * igb_check_lvmmc - check for malformed packets received
4184 * and indicated in LVMMC register
4185 * @adapter: pointer to adapter
4186 **/
4187static void igb_check_lvmmc(struct igb_adapter *adapter)
4188{
4189 struct e1000_hw *hw = &adapter->hw;
4190 u32 lvmmc;
4191
4192 lvmmc = rd32(E1000_LVMMC);
4193 if (lvmmc) {
4194 if (unlikely(net_ratelimit())) {
4195 netdev_warn(adapter->netdev,
4196 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4197 lvmmc);
4198 }
4199 }
4200}
4201
9d5c8243 4202/**
b980ac18
JK		 4203 * igb_watchdog - Timer Call-back
4204 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4205 **/
4206static void igb_watchdog(unsigned long data)
4207{
4208 struct igb_adapter *adapter = (struct igb_adapter *)data;
4209 /* Do the rest outside of interrupt context */
4210 schedule_work(&adapter->watchdog_task);
4211}
4212
4213static void igb_watchdog_task(struct work_struct *work)
4214{
4215 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4216 struct igb_adapter,
4217 watchdog_task);
9d5c8243 4218 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4219 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4220 struct net_device *netdev = adapter->netdev;
563988dc 4221 u32 link;
7a6ea550 4222 int i;
56cec249 4223 u32 connsw;
9d5c8243 4224
4d6b725e 4225 link = igb_has_link(adapter);
aa9b8cc4
AA		 4226
4227 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4228 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4229 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4230 else
4231 link = false;
4232 }
4233
56cec249
CW		 4234 /* Force link down if we have fiber to swap to */
4235 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4236 if (hw->phy.media_type == e1000_media_type_copper) {
4237 connsw = rd32(E1000_CONNSW);
4238 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4239 link = 0;
4240 }
4241 }
9d5c8243 4242 if (link) {
2bdfc4e2
CW		 4243 /* Perform a reset if the media type changed. */
4244 if (hw->dev_spec._82575.media_changed) {
4245 hw->dev_spec._82575.media_changed = false;
4246 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4247 igb_reset(adapter);
4248 }
749ab2cd
YZ		 4249 /* Cancel scheduled suspend requests. */
4250 pm_runtime_resume(netdev->dev.parent);
4251
9d5c8243
AK		 4252 if (!netif_carrier_ok(netdev)) {
4253 u32 ctrl;
9005df38 4254
330a6d6a 4255 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4256 &adapter->link_speed,
4257 &adapter->link_duplex);
9d5c8243
AK		 4258
4259 ctrl = rd32(E1000_CTRL);
527d47c1 4260 /* Links status message must follow this format */
c75c4edf
CW		 4261 netdev_info(netdev,
4262 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4263 netdev->name,
4264 adapter->link_speed,
4265 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4266 "Full" : "Half",
4267 (ctrl & E1000_CTRL_TFCE) &&
4268 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4269 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4270 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4271
f4c01e96
CW		 4272 /* disable EEE if enabled */
4273 if ((adapter->flags & IGB_FLAG_EEE) &&
4274 (adapter->link_duplex == HALF_DUPLEX)) {
4275 dev_info(&adapter->pdev->dev,
4276 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4277 adapter->hw.dev_spec._82575.eee_disable = true;
4278 adapter->flags &= ~IGB_FLAG_EEE;
4279 }
4280
c0ba4778
KS		 4281 /* check if SmartSpeed worked */
4282 igb_check_downshift(hw);
4283 if (phy->speed_downgraded)
4284 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4285
563988dc 4286 /* check for thermal sensor event */
876d2d6f 4287 if (igb_thermal_sensor_event(hw,
d34a15ab 4288 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4289 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4290
d07f3e37 4291 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4292 adapter->tx_timeout_factor = 1;
4293 switch (adapter->link_speed) {
4294 case SPEED_10:
9d5c8243
AK		 4295 adapter->tx_timeout_factor = 14;
4296 break;
4297 case SPEED_100:
9d5c8243
AK		 4298 /* maybe add some timeout factor ? */
4299 break;
4300 }
4301
4302 netif_carrier_on(netdev);
9d5c8243 4303
4ae196df 4304 igb_ping_all_vfs(adapter);
17dc566c 4305 igb_check_vf_rate_limit(adapter);
4ae196df 4306
4b1a9877 4307 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4308 if (!test_bit(__IGB_DOWN, &adapter->state))
4309 mod_timer(&adapter->phy_info_timer,
4310 round_jiffies(jiffies + 2 * HZ));
4311 }
4312 } else {
4313 if (netif_carrier_ok(netdev)) {
4314 adapter->link_speed = 0;
4315 adapter->link_duplex = 0;
563988dc
SA		 4316
4317 /* check for thermal sensor event */
876d2d6f
JK		 4318 if (igb_thermal_sensor_event(hw,
4319 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4320 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4321 }
563988dc 4322
527d47c1 4323 /* Links status message must follow this format */
c75c4edf 4324 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4325 netdev->name);
9d5c8243 4326 netif_carrier_off(netdev);
4b1a9877 4327
4ae196df
AD		 4328 igb_ping_all_vfs(adapter);
4329
4b1a9877 4330 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4331 if (!test_bit(__IGB_DOWN, &adapter->state))
4332 mod_timer(&adapter->phy_info_timer,
4333 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4334
56cec249
CW		 4335 /* link is down, time to check for alternate media */
4336 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4337 igb_check_swap_media(adapter);
4338 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4339 schedule_work(&adapter->reset_task);
4340 /* return immediately */
4341 return;
4342 }
4343 }
749ab2cd
YZ		 4344 pm_schedule_suspend(netdev->dev.parent,
4345 MSEC_PER_SEC * 5);
56cec249
CW		 4346
4347 /* also check for alternate media here */
4348 } else if (!netif_carrier_ok(netdev) &&
4349 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4350 igb_check_swap_media(adapter);
4351 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4352 schedule_work(&adapter->reset_task);
4353 /* return immediately */
4354 return;
4355 }
9d5c8243
AK		 4356 }
4357 }
4358
12dcd86b
ED		 4359 spin_lock(&adapter->stats64_lock);
4360 igb_update_stats(adapter, &adapter->stats64);
4361 spin_unlock(&adapter->stats64_lock);
9d5c8243 4362
dbabb065 4363 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4364 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4365 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4366 /* We've lost link, so the controller stops DMA,
4367 * but we've got queued Tx work that's never going
4368 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4369 * (Do the reset outside of interrupt context).
4370 */
dbabb065
AD		 4371 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4372 adapter->tx_timeout_count++;
4373 schedule_work(&adapter->reset_task);
4374 /* return immediately since reset is imminent */
4375 return;
4376 }
9d5c8243 4377 }
9d5c8243 4378
dbabb065 4379 /* Force detection of hung controller every watchdog period */
6d095fa8 4380 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4381 }
f7ba205e 4382
b980ac18 4383 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4384 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4385 u32 eics = 0;
9005df38 4386
0d1ae7f4
AD		 4387 for (i = 0; i < adapter->num_q_vectors; i++)
4388 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4389 wr32(E1000_EICS, eics);
4390 } else {
4391 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4392 }
9d5c8243 4393
13800469 4394 igb_spoof_check(adapter);
fc580751 4395 igb_ptp_rx_hang(adapter);
13800469 4396
1516f0a6
CW		 4397 /* Check LVMMC register on i350/i354 only */
4398 if ((adapter->hw.mac.type == e1000_i350) ||
4399 (adapter->hw.mac.type == e1000_i354))
4400 igb_check_lvmmc(adapter);
4401
9d5c8243 4402 /* Reset the timer */
aa9b8cc4
AA		 4403 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4404 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4405 mod_timer(&adapter->watchdog_timer,
4406 round_jiffies(jiffies + HZ));
4407 else
4408 mod_timer(&adapter->watchdog_timer,
4409 round_jiffies(jiffies + 2 * HZ));
4410 }
9d5c8243
AK		 4411}
4412
4413enum latency_range {
4414 lowest_latency = 0,
4415 low_latency = 1,
4416 bulk_latency = 2,
4417 latency_invalid = 255
4418};
4419
6eb5a7f1 4420/**
b980ac18
JK		 4421 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4422 * @q_vector: pointer to q_vector
6eb5a7f1 4423 *
b980ac18
JK		 4424 * Stores a new ITR value based on strictly on packet size. This
4425 * algorithm is less sophisticated than that used in igb_update_itr,
4426 * due to the difficulty of synchronizing statistics across multiple
4427 * receive rings. The divisors and thresholds used by this function
4428 * were determined based on theoretical maximum wire speed and testing
4429 * data, in order to minimize response time while increasing bulk
4430 * throughput.
406d4965 4431 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4432 * NOTE: This function is called only when operating in a multiqueue
4433 * receive environment.
6eb5a7f1 4434 **/
047e0030 4435static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4436{
047e0030 4437 int new_val = q_vector->itr_val;
6eb5a7f1 4438 int avg_wire_size = 0;
047e0030 4439 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4440 unsigned int packets;
9d5c8243 4441
6eb5a7f1
AD		 4442 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4443 * ints/sec - ITR timer value of 120 ticks.
4444 */
4445 if (adapter->link_speed != SPEED_1000) {
0ba82994 4446 new_val = IGB_4K_ITR;
6eb5a7f1 4447 goto set_itr_val;
9d5c8243 4448 }
047e0030 4449
0ba82994
AD		 4450 packets = q_vector->rx.total_packets;
4451 if (packets)
4452 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4453
0ba82994
AD		 4454 packets = q_vector->tx.total_packets;
4455 if (packets)
4456 avg_wire_size = max_t(u32, avg_wire_size,
4457 q_vector->tx.total_bytes / packets);
047e0030
AD		 4458
4459 /* if avg_wire_size isn't set no work was done */
4460 if (!avg_wire_size)
4461 goto clear_counts;
9d5c8243 4462
6eb5a7f1
AD		 4463 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4464 avg_wire_size += 24;
4465
4466 /* Don't starve jumbo frames */
4467 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4468
6eb5a7f1
AD		 4469 /* Give a little boost to mid-size frames */
4470 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4471 new_val = avg_wire_size / 3;
4472 else
4473 new_val = avg_wire_size / 2;
9d5c8243 4474
0ba82994
AD		 4475 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4476 if (new_val < IGB_20K_ITR &&
4477 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4478 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4479 new_val = IGB_20K_ITR;
abe1c363 4480
6eb5a7f1 4481set_itr_val:
047e0030
AD		 4482 if (new_val != q_vector->itr_val) {
4483 q_vector->itr_val = new_val;
4484 q_vector->set_itr = 1;
9d5c8243 4485 }
6eb5a7f1 4486clear_counts:
0ba82994
AD		 4487 q_vector->rx.total_bytes = 0;
4488 q_vector->rx.total_packets = 0;
4489 q_vector->tx.total_bytes = 0;
4490 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4491}
4492
4493/**
b980ac18
JK		 4494 * igb_update_itr - update the dynamic ITR value based on statistics
4495 * @q_vector: pointer to q_vector
4496 * @ring_container: ring info to update the itr for
4497 *
4498 * Stores a new ITR value based on packets and byte
4499 * counts during the last interrupt. The advantage of per interrupt
4500 * computation is faster updates and more accurate ITR for the current
4501 * traffic pattern. Constants in this function were computed
4502 * based on theoretical maximum wire speed and thresholds were set based
4503 * on testing data as well as attempting to minimize response time
4504 * while increasing bulk throughput.
406d4965 4505 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4506 * NOTE: These calculations are only valid when operating in a single-
4507 * queue environment.
9d5c8243 4508 **/
0ba82994
AD		 4509static void igb_update_itr(struct igb_q_vector *q_vector,
4510 struct igb_ring_container *ring_container)
9d5c8243 4511{
0ba82994
AD		 4512 unsigned int packets = ring_container->total_packets;
4513 unsigned int bytes = ring_container->total_bytes;
4514 u8 itrval = ring_container->itr;
9d5c8243 4515
0ba82994 4516 /* no packets, exit with status unchanged */
9d5c8243 4517 if (packets == 0)
0ba82994 4518 return;
9d5c8243 4519
0ba82994 4520 switch (itrval) {
9d5c8243
AK		 4521 case lowest_latency:
4522 /* handle TSO and jumbo frames */
4523 if (bytes/packets > 8000)
0ba82994 4524 itrval = bulk_latency;
9d5c8243 4525 else if ((packets < 5) && (bytes > 512))
0ba82994 4526 itrval = low_latency;
9d5c8243
AK		 4527 break;
4528 case low_latency: /* 50 usec aka 20000 ints/s */
4529 if (bytes > 10000) {
4530 /* this if handles the TSO accounting */
d34a15ab 4531 if (bytes/packets > 8000)
0ba82994 4532 itrval = bulk_latency;
d34a15ab 4533 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4534 itrval = bulk_latency;
d34a15ab 4535 else if ((packets > 35))
0ba82994 4536 itrval = lowest_latency;
9d5c8243 4537 } else if (bytes/packets > 2000) {
0ba82994 4538 itrval = bulk_latency;
9d5c8243 4539 } else if (packets <= 2 && bytes < 512) {
0ba82994 4540 itrval = lowest_latency;
9d5c8243
AK		 4541 }
4542 break;
4543 case bulk_latency: /* 250 usec aka 4000 ints/s */
4544 if (bytes > 25000) {
4545 if (packets > 35)
0ba82994 4546 itrval = low_latency;
1e5c3d21 4547 } else if (bytes < 1500) {
0ba82994 4548 itrval = low_latency;
9d5c8243
AK		 4549 }
4550 break;
4551 }
4552
0ba82994
AD		 4553 /* clear work counters since we have the values we need */
4554 ring_container->total_bytes = 0;
4555 ring_container->total_packets = 0;
4556
4557 /* write updated itr to ring container */
4558 ring_container->itr = itrval;
9d5c8243
AK		 4559}
4560
0ba82994 4561static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4562{
0ba82994 4563 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4564 u32 new_itr = q_vector->itr_val;
0ba82994 4565 u8 current_itr = 0;
9d5c8243
AK		 4566
4567 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4568 if (adapter->link_speed != SPEED_1000) {
4569 current_itr = 0;
0ba82994 4570 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4571 goto set_itr_now;
4572 }
4573
0ba82994
AD		 4574 igb_update_itr(q_vector, &q_vector->tx);
4575 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4576
0ba82994 4577 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4578
6eb5a7f1 4579 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4580 if (current_itr == lowest_latency &&
4581 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4582 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4583 current_itr = low_latency;
4584
9d5c8243
AK		 4585 switch (current_itr) {
4586 /* counts and packets in update_itr are dependent on these numbers */
4587 case lowest_latency:
0ba82994 4588 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4589 break;
4590 case low_latency:
0ba82994 4591 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4592 break;
4593 case bulk_latency:
0ba82994 4594 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4595 break;
4596 default:
4597 break;
4598 }
4599
4600set_itr_now:
047e0030 4601 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4602 /* this attempts to bias the interrupt rate towards Bulk
4603 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4604 * increasing
4605 */
047e0030 4606 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4607 max((new_itr * q_vector->itr_val) /
4608 (new_itr + (q_vector->itr_val >> 2)),
4609 new_itr) : new_itr;
9d5c8243
AK		 4610 /* Don't write the value here; it resets the adapter's
4611 * internal timer, and causes us to delay far longer than
4612 * we should between interrupts. Instead, we write the ITR
4613 * value at the beginning of the next interrupt so the timing
4614 * ends up being correct.
4615 */
047e0030
AD		 4616 q_vector->itr_val = new_itr;
4617 q_vector->set_itr = 1;
9d5c8243 4618 }
9d5c8243
AK		 4619}
4620
c50b52a0
SH		 4621static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4622 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4623{
4624 struct e1000_adv_tx_context_desc *context_desc;
4625 u16 i = tx_ring->next_to_use;
4626
4627 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4628
4629 i++;
4630 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4631
4632 /* set bits to identify this as an advanced context descriptor */
4633 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4634
4635 /* For 82575, context index must be unique per ring. */
866cff06 4636 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4637 mss_l4len_idx |= tx_ring->reg_idx << 4;
4638
4639 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4640 context_desc->seqnum_seed = 0;
4641 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4642 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4643}
4644
7af40ad9
AD		 4645static int igb_tso(struct igb_ring *tx_ring,
4646 struct igb_tx_buffer *first,
4647 u8 *hdr_len)
9d5c8243 4648{
7af40ad9 4649 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4650 u32 vlan_macip_lens, type_tucmd;
4651 u32 mss_l4len_idx, l4len;
06c14e5a 4652 int err;
7d13a7d0 4653
ed6aa105
AD		 4654 if (skb->ip_summed != CHECKSUM_PARTIAL)
4655 return 0;
4656
7d13a7d0
AD		 4657 if (!skb_is_gso(skb))
4658 return 0;
9d5c8243 4659
06c14e5a
FR		 4660 err = skb_cow_head(skb, 0);
4661 if (err < 0)
4662 return err;
9d5c8243 4663
7d13a7d0
AD		 4664 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4665 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4666
7c4d16ff 4667 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4668 struct iphdr *iph = ip_hdr(skb);
4669 iph->tot_len = 0;
4670 iph->check = 0;
4671 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4672 iph->daddr, 0,
4673 IPPROTO_TCP,
4674 0);
7d13a7d0 4675 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4676 first->tx_flags |= IGB_TX_FLAGS_TSO |
4677 IGB_TX_FLAGS_CSUM |
4678 IGB_TX_FLAGS_IPV4;
8e1e8a47 4679 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4680 ipv6_hdr(skb)->payload_len = 0;
4681 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4682 &ipv6_hdr(skb)->daddr,
4683 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4684 first->tx_flags |= IGB_TX_FLAGS_TSO |
4685 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4686 }
4687
7af40ad9 4688 /* compute header lengths */
7d13a7d0
AD		 4689 l4len = tcp_hdrlen(skb);
4690 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4691
7af40ad9
AD		 4692 /* update gso size and bytecount with header size */
4693 first->gso_segs = skb_shinfo(skb)->gso_segs;
4694 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4695
9d5c8243 4696 /* MSS L4LEN IDX */
7d13a7d0
AD		 4697 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4698 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4699
7d13a7d0
AD		 4700 /* VLAN MACLEN IPLEN */
4701 vlan_macip_lens = skb_network_header_len(skb);
4702 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4703 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4704
7d13a7d0 4705 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4706
7d13a7d0 4707 return 1;
9d5c8243
AK		 4708}
4709
7af40ad9 4710static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4711{
7af40ad9 4712 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4713 u32 vlan_macip_lens = 0;
4714 u32 mss_l4len_idx = 0;
4715 u32 type_tucmd = 0;
9d5c8243 4716
7d13a7d0 4717 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4718 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4719 return;
7d13a7d0
AD		 4720 } else {
4721 u8 l4_hdr = 0;
9005df38 4722
7af40ad9 4723 switch (first->protocol) {
7c4d16ff 4724 case htons(ETH_P_IP):
7d13a7d0
AD		 4725 vlan_macip_lens |= skb_network_header_len(skb);
4726 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4727 l4_hdr = ip_hdr(skb)->protocol;
4728 break;
7c4d16ff 4729 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4730 vlan_macip_lens |= skb_network_header_len(skb);
4731 l4_hdr = ipv6_hdr(skb)->nexthdr;
4732 break;
4733 default:
4734 if (unlikely(net_ratelimit())) {
4735 dev_warn(tx_ring->dev,
b980ac18
JK		 4736 "partial checksum but proto=%x!\n",
4737 first->protocol);
fa4a7ef3 4738 }
7d13a7d0
AD		 4739 break;
4740 }
fa4a7ef3 4741
7d13a7d0
AD		 4742 switch (l4_hdr) {
4743 case IPPROTO_TCP:
4744 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4745 mss_l4len_idx = tcp_hdrlen(skb) <<
4746 E1000_ADVTXD_L4LEN_SHIFT;
4747 break;
4748 case IPPROTO_SCTP:
4749 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4750 mss_l4len_idx = sizeof(struct sctphdr) <<
4751 E1000_ADVTXD_L4LEN_SHIFT;
4752 break;
4753 case IPPROTO_UDP:
4754 mss_l4len_idx = sizeof(struct udphdr) <<
4755 E1000_ADVTXD_L4LEN_SHIFT;
4756 break;
4757 default:
4758 if (unlikely(net_ratelimit())) {
4759 dev_warn(tx_ring->dev,
b980ac18
JK		 4760 "partial checksum but l4 proto=%x!\n",
4761 l4_hdr);
44b0cda3 4762 }
7d13a7d0 4763 break;
9d5c8243 4764 }
7af40ad9
AD		 4765
4766 /* update TX checksum flag */
4767 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4768 }
9d5c8243 4769
7d13a7d0 4770 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4771 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4772
7d13a7d0 4773 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4774}
4775
1d9daf45
AD		 4776#define IGB_SET_FLAG(_input, _flag, _result) \
4777 ((_flag <= _result) ? \
4778 ((u32)(_input & _flag) * (_result / _flag)) : \
4779 ((u32)(_input & _flag) / (_flag / _result)))
4780
4781static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4782{
4783 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4784 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4785 E1000_ADVTXD_DCMD_DEXT |
4786 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4787
4788 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4789 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4790 (E1000_ADVTXD_DCMD_VLE));
4791
4792 /* set segmentation bits for TSO */
4793 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4794 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4795
4796 /* set timestamp bit if present */
1d9daf45
AD		 4797 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4798 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4799
1d9daf45
AD		 4800 /* insert frame checksum */
4801 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4802
4803 return cmd_type;
4804}
4805
7af40ad9
AD		 4806static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4807 union e1000_adv_tx_desc *tx_desc,
4808 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4809{
4810 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4811
1d9daf45
AD		 4812 /* 82575 requires a unique index per ring */
4813 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4814 olinfo_status |= tx_ring->reg_idx << 4;
4815
4816 /* insert L4 checksum */
1d9daf45
AD		 4817 olinfo_status |= IGB_SET_FLAG(tx_flags,
4818 IGB_TX_FLAGS_CSUM,
4819 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4820
1d9daf45
AD		 4821 /* insert IPv4 checksum */
4822 olinfo_status |= IGB_SET_FLAG(tx_flags,
4823 IGB_TX_FLAGS_IPV4,
4824 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4825
7af40ad9 4826 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4827}
4828
6f19e12f
DM		 4829static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4830{
4831 struct net_device *netdev = tx_ring->netdev;
4832
4833 netif_stop_subqueue(netdev, tx_ring->queue_index);
4834
4835 /* Herbert's original patch had:
4836 * smp_mb__after_netif_stop_queue();
4837 * but since that doesn't exist yet, just open code it.
4838 */
4839 smp_mb();
4840
4841 /* We need to check again in a case another CPU has just
4842 * made room available.
4843 */
4844 if (igb_desc_unused(tx_ring) < size)
4845 return -EBUSY;
4846
4847 /* A reprieve! */
4848 netif_wake_subqueue(netdev, tx_ring->queue_index);
4849
4850 u64_stats_update_begin(&tx_ring->tx_syncp2);
4851 tx_ring->tx_stats.restart_queue2++;
4852 u64_stats_update_end(&tx_ring->tx_syncp2);
4853
4854 return 0;
4855}
4856
4857static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4858{
4859 if (igb_desc_unused(tx_ring) >= size)
4860 return 0;
4861 return __igb_maybe_stop_tx(tx_ring, size);
4862}
4863
7af40ad9
AD		 4864static void igb_tx_map(struct igb_ring *tx_ring,
4865 struct igb_tx_buffer *first,
ebe42d16 4866 const u8 hdr_len)
9d5c8243 4867{
7af40ad9 4868 struct sk_buff *skb = first->skb;
c9f14bf3 4869 struct igb_tx_buffer *tx_buffer;
ebe42d16 4870 union e1000_adv_tx_desc *tx_desc;
80d0759e 4871 struct skb_frag_struct *frag;
ebe42d16 4872 dma_addr_t dma;
80d0759e 4873 unsigned int data_len, size;
7af40ad9 4874 u32 tx_flags = first->tx_flags;
1d9daf45 4875 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4876 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4877
4878 tx_desc = IGB_TX_DESC(tx_ring, i);
4879
80d0759e
AD		 4880 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4881
4882 size = skb_headlen(skb);
4883 data_len = skb->data_len;
ebe42d16
AD		 4884
4885 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4886
80d0759e
AD		 4887 tx_buffer = first;
4888
4889 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4890 if (dma_mapping_error(tx_ring->dev, dma))
4891 goto dma_error;
4892
4893 /* record length, and DMA address */
4894 dma_unmap_len_set(tx_buffer, len, size);
4895 dma_unmap_addr_set(tx_buffer, dma, dma);
4896
4897 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4898
ebe42d16
AD		 4899 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4900 tx_desc->read.cmd_type_len =
1d9daf45 4901 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4902
4903 i++;
4904 tx_desc++;
4905 if (i == tx_ring->count) {
4906 tx_desc = IGB_TX_DESC(tx_ring, 0);
4907 i = 0;
4908 }
80d0759e 4909 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4910
4911 dma += IGB_MAX_DATA_PER_TXD;
4912 size -= IGB_MAX_DATA_PER_TXD;
4913
ebe42d16
AD		 4914 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4915 }
4916
4917 if (likely(!data_len))
4918 break;
2bbfebe2 4919
1d9daf45 4920 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4921
65689fef 4922 i++;
ebe42d16
AD		 4923 tx_desc++;
4924 if (i == tx_ring->count) {
4925 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4926 i = 0;
ebe42d16 4927 }
80d0759e 4928 tx_desc->read.olinfo_status = 0;
65689fef 4929
9e903e08 4930 size = skb_frag_size(frag);
ebe42d16
AD		 4931 data_len -= size;
4932
4933 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4934 size, DMA_TO_DEVICE);
6366ad33 4935
c9f14bf3 4936 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4937 }
4938
ebe42d16 4939 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4940 cmd_type |= size | IGB_TXD_DCMD;
4941 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4942
80d0759e
AD		 4943 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4944
8542db05
AD		 4945 /* set the timestamp */
4946 first->time_stamp = jiffies;
4947
b980ac18 4948 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4949 * are new descriptors to fetch. (Only applicable for weak-ordered
4950 * memory model archs, such as IA-64).
4951 *
4952 * We also need this memory barrier to make certain all of the
4953 * status bits have been updated before next_to_watch is written.
4954 */
4955 wmb();
4956
8542db05 4957 /* set next_to_watch value indicating a packet is present */
ebe42d16 4958 first->next_to_watch = tx_desc;
9d5c8243 4959
ebe42d16
AD		 4960 i++;
4961 if (i == tx_ring->count)
4962 i = 0;
6366ad33 4963
ebe42d16 4964 tx_ring->next_to_use = i;
6366ad33 4965
6f19e12f
DM		 4966 /* Make sure there is space in the ring for the next send. */
4967 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4968
4969 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 4970 writel(i, tx_ring->tail);
4971
4972 /* we need this if more than one processor can write to our tail
4973 * at a time, it synchronizes IO on IA64/Altix systems
4974 */
4975 mmiowb();
4976 }
ebe42d16
AD		 4977 return;
4978
4979dma_error:
4980 dev_err(tx_ring->dev, "TX DMA map failed\n");
4981
4982 /* clear dma mappings for failed tx_buffer_info map */
4983 for (;;) {
c9f14bf3
AD		 4984 tx_buffer = &tx_ring->tx_buffer_info[i];
4985 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4986 if (tx_buffer == first)
ebe42d16 4987 break;
a77ff709
NN		 4988 if (i == 0)
4989 i = tx_ring->count;
6366ad33 4990 i--;
6366ad33
AD		 4991 }
4992
9d5c8243 4993 tx_ring->next_to_use = i;
9d5c8243
AK		 4994}
4995
cd392f5c
AD		 4996netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4997 struct igb_ring *tx_ring)
9d5c8243 4998{
8542db05 4999 struct igb_tx_buffer *first;
ebe42d16 5000 int tso;
91d4ee33 5001 u32 tx_flags = 0;
2ee52ad4 5002 unsigned short f;
21ba6fe1 5003 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 5004 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 5005 u8 hdr_len = 0;
9d5c8243 5006
21ba6fe1
AD		 5007 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
5008 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 5009 * + 2 desc gap to keep tail from touching head,
9d5c8243 5010 * + 1 desc for context descriptor,
21ba6fe1
AD		 5011 * otherwise try next time
5012 */
2ee52ad4
AD		 5013 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5014 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
21ba6fe1
AD		 5015
5016 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5017 /* this is a hard error */
9d5c8243
AK		 5018 return NETDEV_TX_BUSY;
5019 }
33af6bcc 5020
7af40ad9
AD		 5021 /* record the location of the first descriptor for this packet */
5022 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5023 first->skb = skb;
5024 first->bytecount = skb->len;
5025 first->gso_segs = 1;
5026
b646c22e
AD		 5027 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5028 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5029
ed4420a3
JK		 5030 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5031 &adapter->state)) {
b646c22e
AD		 5032 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5033 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5034
5035 adapter->ptp_tx_skb = skb_get(skb);
5036 adapter->ptp_tx_start = jiffies;
5037 if (adapter->hw.mac.type == e1000_82576)
5038 schedule_work(&adapter->ptp_tx_work);
5039 }
33af6bcc 5040 }
9d5c8243 5041
afc835d1
JK		 5042 skb_tx_timestamp(skb);
5043
df8a39de 5044 if (skb_vlan_tag_present(skb)) {
9d5c8243 5045 tx_flags |= IGB_TX_FLAGS_VLAN;
df8a39de 5046 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
9d5c8243
AK		 5047 }
5048
7af40ad9
AD		 5049 /* record initial flags and protocol */
5050 first->tx_flags = tx_flags;
5051 first->protocol = protocol;
cdfd01fc 5052
7af40ad9
AD		 5053 tso = igb_tso(tx_ring, first, &hdr_len);
5054 if (tso < 0)
7d13a7d0 5055 goto out_drop;
7af40ad9
AD		 5056 else if (!tso)
5057 igb_tx_csum(tx_ring, first);
9d5c8243 5058
7af40ad9 5059 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5060
9d5c8243 5061 return NETDEV_TX_OK;
7d13a7d0
AD		 5062
5063out_drop:
7af40ad9
AD		 5064 igb_unmap_and_free_tx_resource(tx_ring, first);
5065
7d13a7d0 5066 return NETDEV_TX_OK;
9d5c8243
AK		 5067}
5068
0b725a2c
DM		 5069static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5070 struct sk_buff *skb)
1cc3bd87 5071{
0b725a2c
DM		 5072 unsigned int r_idx = skb->queue_mapping;
5073
1cc3bd87
AD		 5074 if (r_idx >= adapter->num_tx_queues)
5075 r_idx = r_idx % adapter->num_tx_queues;
5076
5077 return adapter->tx_ring[r_idx];
5078}
5079
cd392f5c
AD		 5080static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5081 struct net_device *netdev)
9d5c8243
AK		 5082{
5083 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5084
5085 if (test_bit(__IGB_DOWN, &adapter->state)) {
5086 dev_kfree_skb_any(skb);
5087 return NETDEV_TX_OK;
5088 }
5089
5090 if (skb->len <= 0) {
5091 dev_kfree_skb_any(skb);
5092 return NETDEV_TX_OK;
5093 }
5094
b980ac18 5095 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5096 * in order to meet this minimum size requirement.
5097 */
a94d9e22
AD		 5098 if (skb_put_padto(skb, 17))
5099 return NETDEV_TX_OK;
9d5c8243 5100
1cc3bd87 5101 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5102}
5103
5104/**
b980ac18
JK		 5105 * igb_tx_timeout - Respond to a Tx Hang
5106 * @netdev: network interface device structure
9d5c8243
AK		 5107 **/
5108static void igb_tx_timeout(struct net_device *netdev)
5109{
5110 struct igb_adapter *adapter = netdev_priv(netdev);
5111 struct e1000_hw *hw = &adapter->hw;
5112
5113 /* Do the reset outside of interrupt context */
5114 adapter->tx_timeout_count++;
f7ba205e 5115
06218a8d 5116 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5117 hw->dev_spec._82575.global_device_reset = true;
5118
9d5c8243 5119 schedule_work(&adapter->reset_task);
265de409
AD		 5120 wr32(E1000_EICS,
5121 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5122}
5123
5124static void igb_reset_task(struct work_struct *work)
5125{
5126 struct igb_adapter *adapter;
5127 adapter = container_of(work, struct igb_adapter, reset_task);
5128
c97ec42a
TI		 5129 igb_dump(adapter);
5130 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5131 igb_reinit_locked(adapter);
5132}
5133
5134/**
b980ac18
JK		 5135 * igb_get_stats64 - Get System Network Statistics
5136 * @netdev: network interface device structure
5137 * @stats: rtnl_link_stats64 pointer
9d5c8243 5138 **/
12dcd86b 5139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5140 struct rtnl_link_stats64 *stats)
9d5c8243 5141{
12dcd86b
ED		 5142 struct igb_adapter *adapter = netdev_priv(netdev);
5143
5144 spin_lock(&adapter->stats64_lock);
5145 igb_update_stats(adapter, &adapter->stats64);
5146 memcpy(stats, &adapter->stats64, sizeof(*stats));
5147 spin_unlock(&adapter->stats64_lock);
5148
5149 return stats;
9d5c8243
AK		 5150}
5151
5152/**
b980ac18
JK		 5153 * igb_change_mtu - Change the Maximum Transfer Unit
5154 * @netdev: network interface device structure
5155 * @new_mtu: new value for maximum frame size
9d5c8243 5156 *
b980ac18 5157 * Returns 0 on success, negative on failure
9d5c8243
AK		 5158 **/
5159static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5160{
5161 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5162 struct pci_dev *pdev = adapter->pdev;
153285f9 5163 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5164
c809d227 5165 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5166 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5167 return -EINVAL;
5168 }
5169
153285f9 5170#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5171 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5172 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5173 return -EINVAL;
5174 }
5175
2ccd994c
AD		 5176 /* adjust max frame to be at least the size of a standard frame */
5177 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5178 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5179
9d5c8243 5180 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5181 usleep_range(1000, 2000);
73cd78f1 5182
9d5c8243
AK		 5183 /* igb_down has a dependency on max_frame_size */
5184 adapter->max_frame_size = max_frame;
559e9c49 5185
4c844851
AD		 5186 if (netif_running(netdev))
5187 igb_down(adapter);
9d5c8243 5188
090b1795 5189 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5190 netdev->mtu, new_mtu);
5191 netdev->mtu = new_mtu;
5192
5193 if (netif_running(netdev))
5194 igb_up(adapter);
5195 else
5196 igb_reset(adapter);
5197
5198 clear_bit(__IGB_RESETTING, &adapter->state);
5199
5200 return 0;
5201}
5202
5203/**
b980ac18
JK		 5204 * igb_update_stats - Update the board statistics counters
5205 * @adapter: board private structure
9d5c8243 5206 **/
12dcd86b
ED		 5207void igb_update_stats(struct igb_adapter *adapter,
5208 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5209{
5210 struct e1000_hw *hw = &adapter->hw;
5211 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5212 u32 reg, mpc;
3f9c0164
AD		 5213 int i;
5214 u64 bytes, packets;
12dcd86b
ED		 5215 unsigned int start;
5216 u64 _bytes, _packets;
9d5c8243 5217
b980ac18 5218 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5219 * connection is down.
5220 */
5221 if (adapter->link_speed == 0)
5222 return;
5223 if (pci_channel_offline(pdev))
5224 return;
5225
3f9c0164
AD		 5226 bytes = 0;
5227 packets = 0;
7f90128e
AA		 5228
5229 rcu_read_lock();
3f9c0164 5230 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5231 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5232 u32 rqdpc = rd32(E1000_RQDPC(i));
5233 if (hw->mac.type >= e1000_i210)
5234 wr32(E1000_RQDPC(i), 0);
12dcd86b 5235
ae1c07a6
AD		 5236 if (rqdpc) {
5237 ring->rx_stats.drops += rqdpc;
5238 net_stats->rx_fifo_errors += rqdpc;
5239 }
12dcd86b
ED		 5240
5241 do {
57a7744e 5242 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5243 _bytes = ring->rx_stats.bytes;
5244 _packets = ring->rx_stats.packets;
57a7744e 5245 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5246 bytes += _bytes;
5247 packets += _packets;
3f9c0164
AD		 5248 }
5249
128e45eb
AD		 5250 net_stats->rx_bytes = bytes;
5251 net_stats->rx_packets = packets;
3f9c0164
AD		 5252
5253 bytes = 0;
5254 packets = 0;
5255 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5256 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5257 do {
57a7744e 5258 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5259 _bytes = ring->tx_stats.bytes;
5260 _packets = ring->tx_stats.packets;
57a7744e 5261 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5262 bytes += _bytes;
5263 packets += _packets;
3f9c0164 5264 }
128e45eb
AD		 5265 net_stats->tx_bytes = bytes;
5266 net_stats->tx_packets = packets;
7f90128e 5267 rcu_read_unlock();
3f9c0164
AD		 5268
5269 /* read stats registers */
9d5c8243
AK		 5270 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5271 adapter->stats.gprc += rd32(E1000_GPRC);
5272 adapter->stats.gorc += rd32(E1000_GORCL);
5273 rd32(E1000_GORCH); /* clear GORCL */
5274 adapter->stats.bprc += rd32(E1000_BPRC);
5275 adapter->stats.mprc += rd32(E1000_MPRC);
5276 adapter->stats.roc += rd32(E1000_ROC);
5277
5278 adapter->stats.prc64 += rd32(E1000_PRC64);
5279 adapter->stats.prc127 += rd32(E1000_PRC127);
5280 adapter->stats.prc255 += rd32(E1000_PRC255);
5281 adapter->stats.prc511 += rd32(E1000_PRC511);
5282 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5283 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5284 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5285 adapter->stats.sec += rd32(E1000_SEC);
5286
fa3d9a6d
MW		 5287 mpc = rd32(E1000_MPC);
5288 adapter->stats.mpc += mpc;
5289 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5290 adapter->stats.scc += rd32(E1000_SCC);
5291 adapter->stats.ecol += rd32(E1000_ECOL);
5292 adapter->stats.mcc += rd32(E1000_MCC);
5293 adapter->stats.latecol += rd32(E1000_LATECOL);
5294 adapter->stats.dc += rd32(E1000_DC);
5295 adapter->stats.rlec += rd32(E1000_RLEC);
5296 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5297 adapter->stats.xontxc += rd32(E1000_XONTXC);
5298 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5299 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5300 adapter->stats.fcruc += rd32(E1000_FCRUC);
5301 adapter->stats.gptc += rd32(E1000_GPTC);
5302 adapter->stats.gotc += rd32(E1000_GOTCL);
5303 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5304 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5305 adapter->stats.ruc += rd32(E1000_RUC);
5306 adapter->stats.rfc += rd32(E1000_RFC);
5307 adapter->stats.rjc += rd32(E1000_RJC);
5308 adapter->stats.tor += rd32(E1000_TORH);
5309 adapter->stats.tot += rd32(E1000_TOTH);
5310 adapter->stats.tpr += rd32(E1000_TPR);
5311
5312 adapter->stats.ptc64 += rd32(E1000_PTC64);
5313 adapter->stats.ptc127 += rd32(E1000_PTC127);
5314 adapter->stats.ptc255 += rd32(E1000_PTC255);
5315 adapter->stats.ptc511 += rd32(E1000_PTC511);
5316 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5317 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5318
5319 adapter->stats.mptc += rd32(E1000_MPTC);
5320 adapter->stats.bptc += rd32(E1000_BPTC);
5321
2d0b0f69
NN		 5322 adapter->stats.tpt += rd32(E1000_TPT);
5323 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5324
5325 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5326 /* read internal phy specific stats */
5327 reg = rd32(E1000_CTRL_EXT);
5328 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5329 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5330
5331 /* this stat has invalid values on i210/i211 */
5332 if ((hw->mac.type != e1000_i210) &&
5333 (hw->mac.type != e1000_i211))
5334 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5335 }
5336
9d5c8243
AK		 5337 adapter->stats.tsctc += rd32(E1000_TSCTC);
5338 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5339
5340 adapter->stats.iac += rd32(E1000_IAC);
5341 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5342 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5343 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5344 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5345 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5346 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5347 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5348 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5349
5350 /* Fill out the OS statistics structure */
128e45eb
AD		 5351 net_stats->multicast = adapter->stats.mprc;
5352 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5353
5354 /* Rx Errors */
5355
5356 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5357 * our own version based on RUC and ROC
5358 */
128e45eb 5359 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5360 adapter->stats.crcerrs + adapter->stats.algnerrc +
5361 adapter->stats.ruc + adapter->stats.roc +
5362 adapter->stats.cexterr;
128e45eb
AD		 5363 net_stats->rx_length_errors = adapter->stats.ruc +
5364 adapter->stats.roc;
5365 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5366 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5367 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5368
5369 /* Tx Errors */
128e45eb
AD		 5370 net_stats->tx_errors = adapter->stats.ecol +
5371 adapter->stats.latecol;
5372 net_stats->tx_aborted_errors = adapter->stats.ecol;
5373 net_stats->tx_window_errors = adapter->stats.latecol;
5374 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5375
5376 /* Tx Dropped needs to be maintained elsewhere */
5377
9d5c8243
AK		 5378 /* Management Stats */
5379 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5380 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5381 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5382
5383 /* OS2BMC Stats */
5384 reg = rd32(E1000_MANC);
5385 if (reg & E1000_MANC_EN_BMC2OS) {
5386 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5387 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5388 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5389 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5390 }
9d5c8243
AK		 5391}
5392
61d7f75f
RC		 5393static void igb_tsync_interrupt(struct igb_adapter *adapter)
5394{
5395 struct e1000_hw *hw = &adapter->hw;
00c65578 5396 struct ptp_clock_event event;
40c9b079 5397 struct timespec64 ts;
720db4ff 5398 u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
00c65578
RC		 5399
5400 if (tsicr & TSINTR_SYS_WRAP) {
5401 event.type = PTP_CLOCK_PPS;
5402 if (adapter->ptp_caps.pps)
5403 ptp_clock_event(adapter->ptp_clock, &event);
5404 else
5405 dev_err(&adapter->pdev->dev, "unexpected SYS WRAP");
5406 ack |= TSINTR_SYS_WRAP;
5407 }
61d7f75f
RC		 5408
5409 if (tsicr & E1000_TSICR_TXTS) {
61d7f75f
RC		 5410 /* retrieve hardware timestamp */
5411 schedule_work(&adapter->ptp_tx_work);
00c65578 5412 ack |= E1000_TSICR_TXTS;
61d7f75f 5413 }
00c65578 5414
720db4ff
RC		 5415 if (tsicr & TSINTR_TT0) {
5416 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5417 ts = timespec64_add(adapter->perout[0].start,
5418 adapter->perout[0].period);
5419 /* u32 conversion of tv_sec is safe until y2106 */
720db4ff 5420 wr32(E1000_TRGTTIML0, ts.tv_nsec);
40c9b079 5421 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
720db4ff
RC		 5422 tsauxc = rd32(E1000_TSAUXC);
5423 tsauxc |= TSAUXC_EN_TT0;
5424 wr32(E1000_TSAUXC, tsauxc);
5425 adapter->perout[0].start = ts;
5426 spin_unlock(&adapter->tmreg_lock);
5427 ack |= TSINTR_TT0;
5428 }
5429
5430 if (tsicr & TSINTR_TT1) {
5431 spin_lock(&adapter->tmreg_lock);
40c9b079
AB		 5432 ts = timespec64_add(adapter->perout[1].start,
5433 adapter->perout[1].period);
720db4ff 5434 wr32(E1000_TRGTTIML1, ts.tv_nsec);
40c9b079 5435 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
720db4ff
RC		 5436 tsauxc = rd32(E1000_TSAUXC);
5437 tsauxc |= TSAUXC_EN_TT1;
5438 wr32(E1000_TSAUXC, tsauxc);
5439 adapter->perout[1].start = ts;
5440 spin_unlock(&adapter->tmreg_lock);
5441 ack |= TSINTR_TT1;
5442 }
5443
5444 if (tsicr & TSINTR_AUTT0) {
5445 nsec = rd32(E1000_AUXSTMPL0);
5446 sec = rd32(E1000_AUXSTMPH0);
5447 event.type = PTP_CLOCK_EXTTS;
5448 event.index = 0;
5449 event.timestamp = sec * 1000000000ULL + nsec;
5450 ptp_clock_event(adapter->ptp_clock, &event);
5451 ack |= TSINTR_AUTT0;
5452 }
5453
5454 if (tsicr & TSINTR_AUTT1) {
5455 nsec = rd32(E1000_AUXSTMPL1);
5456 sec = rd32(E1000_AUXSTMPH1);
5457 event.type = PTP_CLOCK_EXTTS;
5458 event.index = 1;
5459 event.timestamp = sec * 1000000000ULL + nsec;
5460 ptp_clock_event(adapter->ptp_clock, &event);
5461 ack |= TSINTR_AUTT1;
5462 }
5463
00c65578
RC		 5464 /* acknowledge the interrupts */
5465 wr32(E1000_TSICR, ack);
61d7f75f
RC		 5466}
5467
9d5c8243
AK		 5468static irqreturn_t igb_msix_other(int irq, void *data)
5469{
047e0030 5470 struct igb_adapter *adapter = data;
9d5c8243 5471 struct e1000_hw *hw = &adapter->hw;
844290e5 5472 u32 icr = rd32(E1000_ICR);
844290e5 5473 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5474
7f081d40
AD		 5475 if (icr & E1000_ICR_DRSTA)
5476 schedule_work(&adapter->reset_task);
5477
047e0030 5478 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5479 /* HW is reporting DMA is out of sync */
5480 adapter->stats.doosync++;
13800469
GR		 5481 /* The DMA Out of Sync is also indication of a spoof event
5482 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5483 * see if it is really a spoof event.
5484 */
13800469 5485 igb_check_wvbr(adapter);
dda0e083 5486 }
eebbbdba 5487
4ae196df
AD		 5488 /* Check for a mailbox event */
5489 if (icr & E1000_ICR_VMMB)
5490 igb_msg_task(adapter);
5491
5492 if (icr & E1000_ICR_LSC) {
5493 hw->mac.get_link_status = 1;
5494 /* guard against interrupt when we're going down */
5495 if (!test_bit(__IGB_DOWN, &adapter->state))
5496 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5497 }
5498
61d7f75f
RC		 5499 if (icr & E1000_ICR_TS)
5500 igb_tsync_interrupt(adapter);
1f6e8178 5501
844290e5 5502 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5503
5504 return IRQ_HANDLED;
5505}
5506
047e0030 5507static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5508{
26b39276 5509 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5510 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5511
047e0030
AD		 5512 if (!q_vector->set_itr)
5513 return;
73cd78f1 5514
047e0030
AD		 5515 if (!itr_val)
5516 itr_val = 0x4;
661086df 5517
26b39276
AD		 5518 if (adapter->hw.mac.type == e1000_82575)
5519 itr_val |= itr_val << 16;
661086df 5520 else
0ba82994 5521 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5522
047e0030
AD		 5523 writel(itr_val, q_vector->itr_register);
5524 q_vector->set_itr = 0;
6eb5a7f1
AD		 5525}
5526
047e0030 5527static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5528{
047e0030 5529 struct igb_q_vector *q_vector = data;
9d5c8243 5530
047e0030
AD		 5531 /* Write the ITR value calculated from the previous interrupt. */
5532 igb_write_itr(q_vector);
9d5c8243 5533
047e0030 5534 napi_schedule(&q_vector->napi);
844290e5 5535
047e0030 5536 return IRQ_HANDLED;
fe4506b6
JC		 5537}
5538
421e02f0 5539#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5540static void igb_update_tx_dca(struct igb_adapter *adapter,
5541 struct igb_ring *tx_ring,
5542 int cpu)
5543{
5544 struct e1000_hw *hw = &adapter->hw;
5545 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5546
5547 if (hw->mac.type != e1000_82575)
5548 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5549
b980ac18 5550 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5551 * DCA is enabled. This is due to a known issue in some chipsets
5552 * which will cause the DCA tag to be cleared.
5553 */
5554 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5555 E1000_DCA_TXCTRL_DATA_RRO_EN |
5556 E1000_DCA_TXCTRL_DESC_DCA_EN;
5557
5558 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5559}
5560
5561static void igb_update_rx_dca(struct igb_adapter *adapter,
5562 struct igb_ring *rx_ring,
5563 int cpu)
5564{
5565 struct e1000_hw *hw = &adapter->hw;
5566 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5567
5568 if (hw->mac.type != e1000_82575)
5569 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5570
b980ac18 5571 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5572 * DCA is enabled. This is due to a known issue in some chipsets
5573 * which will cause the DCA tag to be cleared.
5574 */
5575 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5576 E1000_DCA_RXCTRL_DESC_DCA_EN;
5577
5578 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5579}
5580
047e0030 5581static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5582{
047e0030 5583 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5584 int cpu = get_cpu();
fe4506b6 5585
047e0030
AD		 5586 if (q_vector->cpu == cpu)
5587 goto out_no_update;
5588
6a05004a
AD		 5589 if (q_vector->tx.ring)
5590 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5591
5592 if (q_vector->rx.ring)
5593 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5594
047e0030
AD		 5595 q_vector->cpu = cpu;
5596out_no_update:
fe4506b6
JC		 5597 put_cpu();
5598}
5599
5600static void igb_setup_dca(struct igb_adapter *adapter)
5601{
7e0e99ef 5602 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5603 int i;
5604
7dfc16fa 5605 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5606 return;
5607
7e0e99ef
AD		 5608 /* Always use CB2 mode, difference is masked in the CB driver. */
5609 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5610
047e0030 5611 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5612 adapter->q_vector[i]->cpu = -1;
5613 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5614 }
5615}
5616
5617static int __igb_notify_dca(struct device *dev, void *data)
5618{
5619 struct net_device *netdev = dev_get_drvdata(dev);
5620 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5621 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5622 struct e1000_hw *hw = &adapter->hw;
5623 unsigned long event = *(unsigned long *)data;
5624
5625 switch (event) {
5626 case DCA_PROVIDER_ADD:
5627 /* if already enabled, don't do it again */
7dfc16fa 5628 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5629 break;
fe4506b6 5630 if (dca_add_requester(dev) == 0) {
bbd98fe4 5631 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5632 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5633 igb_setup_dca(adapter);
5634 break;
5635 }
5636 /* Fall Through since DCA is disabled. */
5637 case DCA_PROVIDER_REMOVE:
7dfc16fa 5638 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5639 /* without this a class_device is left
b980ac18
JK		 5640 * hanging around in the sysfs model
5641 */
fe4506b6 5642 dca_remove_requester(dev);
090b1795 5643 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5644 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5645 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5646 }
5647 break;
5648 }
bbd98fe4 5649
fe4506b6 5650 return 0;
9d5c8243
AK		 5651}
5652
fe4506b6 5653static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5654 void *p)
fe4506b6
JC		 5655{
5656 int ret_val;
5657
5658 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5659 __igb_notify_dca);
fe4506b6
JC		 5660
5661 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5662}
421e02f0 5663#endif /* CONFIG_IGB_DCA */
9d5c8243 5664
0224d663
GR		 5665#ifdef CONFIG_PCI_IOV
5666static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5667{
5668 unsigned char mac_addr[ETH_ALEN];
0224d663 5669
5ac6f91d 5670 eth_zero_addr(mac_addr);
0224d663
GR		 5671 igb_set_vf_mac(adapter, vf, mac_addr);
5672
70ea4783
LL		 5673 /* By default spoof check is enabled for all VFs */
5674 adapter->vf_data[vf].spoofchk_enabled = true;
5675
f557147c 5676 return 0;
0224d663
GR		 5677}
5678
0224d663 5679#endif
4ae196df
AD		 5680static void igb_ping_all_vfs(struct igb_adapter *adapter)
5681{
5682 struct e1000_hw *hw = &adapter->hw;
5683 u32 ping;
5684 int i;
5685
5686 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5687 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5688 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5689 ping |= E1000_VT_MSGTYPE_CTS;
5690 igb_write_mbx(hw, &ping, 1, i);
5691 }
5692}
5693
7d5753f0
AD		 5694static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5695{
5696 struct e1000_hw *hw = &adapter->hw;
5697 u32 vmolr = rd32(E1000_VMOLR(vf));
5698 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5699
d85b9004 5700 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5701 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5702 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5703
5704 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5705 vmolr |= E1000_VMOLR_MPME;
d85b9004 5706 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5707 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5708 } else {
b980ac18 5709 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5710 * flag we need to write the hashes to the MTA as this step
5711 * was previously skipped
5712 */
5713 if (vf_data->num_vf_mc_hashes > 30) {
5714 vmolr |= E1000_VMOLR_MPME;
5715 } else if (vf_data->num_vf_mc_hashes) {
5716 int j;
9005df38 5717
7d5753f0
AD		 5718 vmolr |= E1000_VMOLR_ROMPE;
5719 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5720 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5721 }
5722 }
5723
5724 wr32(E1000_VMOLR(vf), vmolr);
5725
5726 /* there are flags left unprocessed, likely not supported */
5727 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5728 return -EINVAL;
5729
5730 return 0;
7d5753f0
AD		 5731}
5732
4ae196df
AD		 5733static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5734 u32 *msgbuf, u32 vf)
5735{
5736 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5737 u16 *hash_list = (u16 *)&msgbuf[1];
5738 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5739 int i;
5740
7d5753f0 5741 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5742 * to this VF for later use to restore when the PF multi cast
5743 * list changes
5744 */
5745 vf_data->num_vf_mc_hashes = n;
5746
7d5753f0
AD		 5747 /* only up to 30 hash values supported */
5748 if (n > 30)
5749 n = 30;
5750
5751 /* store the hashes for later use */
4ae196df 5752 for (i = 0; i < n; i++)
a419aef8 5753 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5754
5755 /* Flush and reset the mta with the new values */
ff41f8dc 5756 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5757
5758 return 0;
5759}
5760
5761static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5762{
5763 struct e1000_hw *hw = &adapter->hw;
5764 struct vf_data_storage *vf_data;
5765 int i, j;
5766
5767 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5768 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5769
7d5753f0
AD		 5770 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5771
4ae196df 5772 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5773
5774 if ((vf_data->num_vf_mc_hashes > 30) ||
5775 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5776 vmolr |= E1000_VMOLR_MPME;
5777 } else if (vf_data->num_vf_mc_hashes) {
5778 vmolr |= E1000_VMOLR_ROMPE;
5779 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5780 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5781 }
5782 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5783 }
5784}
5785
5786static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5787{
5788 struct e1000_hw *hw = &adapter->hw;
5789 u32 pool_mask, reg, vid;
5790 int i;
5791
5792 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5793
5794 /* Find the vlan filter for this id */
5795 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5796 reg = rd32(E1000_VLVF(i));
5797
5798 /* remove the vf from the pool */
5799 reg &= ~pool_mask;
5800
5801 /* if pool is empty then remove entry from vfta */
5802 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5803 (reg & E1000_VLVF_VLANID_ENABLE)) {
5804 reg = 0;
5805 vid = reg & E1000_VLVF_VLANID_MASK;
5806 igb_vfta_set(hw, vid, false);
5807 }
5808
5809 wr32(E1000_VLVF(i), reg);
5810 }
ae641bdc
AD		 5811
5812 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5813}
5814
5815static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5816{
5817 struct e1000_hw *hw = &adapter->hw;
5818 u32 reg, i;
5819
51466239
AD		 5820 /* The vlvf table only exists on 82576 hardware and newer */
5821 if (hw->mac.type < e1000_82576)
5822 return -1;
5823
5824 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5825 if (!adapter->vfs_allocated_count)
5826 return -1;
5827
5828 /* Find the vlan filter for this id */
5829 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5830 reg = rd32(E1000_VLVF(i));
5831 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5832 vid == (reg & E1000_VLVF_VLANID_MASK))
5833 break;
5834 }
5835
5836 if (add) {
5837 if (i == E1000_VLVF_ARRAY_SIZE) {
5838 /* Did not find a matching VLAN ID entry that was
5839 * enabled. Search for a free filter entry, i.e.
5840 * one without the enable bit set
5841 */
5842 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5843 reg = rd32(E1000_VLVF(i));
5844 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5845 break;
5846 }
5847 }
5848 if (i < E1000_VLVF_ARRAY_SIZE) {
5849 /* Found an enabled/available entry */
5850 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5851
5852 /* if !enabled we need to set this up in vfta */
5853 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5854 /* add VID to filter table */
5855 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5856 reg |= E1000_VLVF_VLANID_ENABLE;
5857 }
cad6d05f
AD		 5858 reg &= ~E1000_VLVF_VLANID_MASK;
5859 reg |= vid;
4ae196df 5860 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5861
5862 /* do not modify RLPML for PF devices */
5863 if (vf >= adapter->vfs_allocated_count)
5864 return 0;
5865
5866 if (!adapter->vf_data[vf].vlans_enabled) {
5867 u32 size;
9005df38 5868
ae641bdc
AD		 5869 reg = rd32(E1000_VMOLR(vf));
5870 size = reg & E1000_VMOLR_RLPML_MASK;
5871 size += 4;
5872 reg &= ~E1000_VMOLR_RLPML_MASK;
5873 reg |= size;
5874 wr32(E1000_VMOLR(vf), reg);
5875 }
ae641bdc 5876
51466239 5877 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5878 }
5879 } else {
5880 if (i < E1000_VLVF_ARRAY_SIZE) {
5881 /* remove vf from the pool */
5882 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5883 /* if pool is empty then remove entry from vfta */
5884 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5885 reg = 0;
5886 igb_vfta_set(hw, vid, false);
5887 }
5888 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5889
5890 /* do not modify RLPML for PF devices */
5891 if (vf >= adapter->vfs_allocated_count)
5892 return 0;
5893
5894 adapter->vf_data[vf].vlans_enabled--;
5895 if (!adapter->vf_data[vf].vlans_enabled) {
5896 u32 size;
9005df38 5897
ae641bdc
AD		 5898 reg = rd32(E1000_VMOLR(vf));
5899 size = reg & E1000_VMOLR_RLPML_MASK;
5900 size -= 4;
5901 reg &= ~E1000_VMOLR_RLPML_MASK;
5902 reg |= size;
5903 wr32(E1000_VMOLR(vf), reg);
5904 }
4ae196df
AD		 5905 }
5906 }
8151d294
WM		 5907 return 0;
5908}
5909
5910static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5911{
5912 struct e1000_hw *hw = &adapter->hw;
5913
5914 if (vid)
5915 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5916 else
5917 wr32(E1000_VMVIR(vf), 0);
5918}
5919
5920static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5921 int vf, u16 vlan, u8 qos)
5922{
5923 int err = 0;
5924 struct igb_adapter *adapter = netdev_priv(netdev);
5925
5926 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5927 return -EINVAL;
5928 if (vlan || qos) {
5929 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5930 if (err)
5931 goto out;
5932 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5933 igb_set_vmolr(adapter, vf, !vlan);
5934 adapter->vf_data[vf].pf_vlan = vlan;
5935 adapter->vf_data[vf].pf_qos = qos;
5936 dev_info(&adapter->pdev->dev,
5937 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5938 if (test_bit(__IGB_DOWN, &adapter->state)) {
5939 dev_warn(&adapter->pdev->dev,
b980ac18 5940 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5941 dev_warn(&adapter->pdev->dev,
b980ac18 5942 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5943 }
5944 } else {
5945 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5946 false, vf);
8151d294
WM		 5947 igb_set_vmvir(adapter, vlan, vf);
5948 igb_set_vmolr(adapter, vf, true);
5949 adapter->vf_data[vf].pf_vlan = 0;
5950 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5951 }
8151d294 5952out:
b980ac18 5953 return err;
4ae196df
AD		 5954}
5955
6f3dc319
GR		 5956static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5957{
5958 struct e1000_hw *hw = &adapter->hw;
5959 int i;
5960 u32 reg;
5961
5962 /* Find the vlan filter for this id */
5963 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5964 reg = rd32(E1000_VLVF(i));
5965 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5966 vid == (reg & E1000_VLVF_VLANID_MASK))
5967 break;
5968 }
5969
5970 if (i >= E1000_VLVF_ARRAY_SIZE)
5971 i = -1;
5972
5973 return i;
5974}
5975
4ae196df
AD		 5976static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5977{
6f3dc319 5978 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5979 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5980 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5981 int err = 0;
4ae196df 5982
6f3dc319
GR		 5983 /* If in promiscuous mode we need to make sure the PF also has
5984 * the VLAN filter set.
5985 */
5986 if (add && (adapter->netdev->flags & IFF_PROMISC))
5987 err = igb_vlvf_set(adapter, vid, add,
5988 adapter->vfs_allocated_count);
5989 if (err)
5990 goto out;
5991
5992 err = igb_vlvf_set(adapter, vid, add, vf);
5993
5994 if (err)
5995 goto out;
5996
5997 /* Go through all the checks to see if the VLAN filter should
5998 * be wiped completely.
5999 */
6000 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
6001 u32 vlvf, bits;
6f3dc319 6002 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 6003
6f3dc319
GR		 6004 if (regndx < 0)
6005 goto out;
6006 /* See if any other pools are set for this VLAN filter
6007 * entry other than the PF.
6008 */
6009 vlvf = bits = rd32(E1000_VLVF(regndx));
6010 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
6011 adapter->vfs_allocated_count);
6012 /* If the filter was removed then ensure PF pool bit
6013 * is cleared if the PF only added itself to the pool
6014 * because the PF is in promiscuous mode.
6015 */
6016 if ((vlvf & VLAN_VID_MASK) == vid &&
6017 !test_bit(vid, adapter->active_vlans) &&
6018 !bits)
6019 igb_vlvf_set(adapter, vid, add,
6020 adapter->vfs_allocated_count);
6021 }
6022
6023out:
6024 return err;
4ae196df
AD		 6025}
6026
f2ca0dbe 6027static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 6028{
8fa7e0f7
GR		 6029 /* clear flags - except flag that indicates PF has set the MAC */
6030 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 6031 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 6032
6033 /* reset offloads to defaults */
8151d294 6034 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 6035
6036 /* reset vlans for device */
6037 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 6038 if (adapter->vf_data[vf].pf_vlan)
6039 igb_ndo_set_vf_vlan(adapter->netdev, vf,
6040 adapter->vf_data[vf].pf_vlan,
6041 adapter->vf_data[vf].pf_qos);
6042 else
6043 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 6044
6045 /* reset multicast table array for vf */
6046 adapter->vf_data[vf].num_vf_mc_hashes = 0;
6047
6048 /* Flush and reset the mta with the new values */
ff41f8dc 6049 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 6050}
6051
f2ca0dbe
AD		 6052static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
6053{
6054 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
6055
5ac6f91d 6056 /* clear mac address as we were hotplug removed/added */
8151d294 6057 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 6058 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 6059
6060 /* process remaining reset events */
6061 igb_vf_reset(adapter, vf);
6062}
6063
6064static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 6065{
6066 struct e1000_hw *hw = &adapter->hw;
6067 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 6068 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 6069 u32 reg, msgbuf[3];
6070 u8 *addr = (u8 *)(&msgbuf[1]);
6071
6072 /* process all the same items cleared in a function level reset */
f2ca0dbe 6073 igb_vf_reset(adapter, vf);
4ae196df
AD		 6074
6075 /* set vf mac address */
26ad9178 6076 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6077
6078 /* enable transmit and receive for vf */
6079 reg = rd32(E1000_VFTE);
6080 wr32(E1000_VFTE, reg | (1 << vf));
6081 reg = rd32(E1000_VFRE);
6082 wr32(E1000_VFRE, reg | (1 << vf));
6083
8fa7e0f7 6084 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6085
6086 /* reply to reset with ack and vf mac address */
6ddbc4cf
AG		 6087 if (!is_zero_ether_addr(vf_mac)) {
6088 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
6089 memcpy(addr, vf_mac, ETH_ALEN);
6090 } else {
6091 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
6092 }
4ae196df
AD		 6093 igb_write_mbx(hw, msgbuf, 3, vf);
6094}
6095
6096static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6097{
b980ac18 6098 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6099 * starting at the second 32 bit word of the msg array
6100 */
f2ca0dbe
AD		 6101 unsigned char *addr = (char *)&msg[1];
6102 int err = -1;
4ae196df 6103
f2ca0dbe
AD		 6104 if (is_valid_ether_addr(addr))
6105 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6106
f2ca0dbe 6107 return err;
4ae196df
AD		 6108}
6109
6110static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6111{
6112 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6113 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6114 u32 msg = E1000_VT_MSGTYPE_NACK;
6115
6116 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6117 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6118 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6119 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6120 vf_data->last_nack = jiffies;
4ae196df
AD		 6121 }
6122}
6123
f2ca0dbe 6124static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6125{
f2ca0dbe
AD		 6126 struct pci_dev *pdev = adapter->pdev;
6127 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6128 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6129 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6130 s32 retval;
6131
f2ca0dbe 6132 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6133
fef45f4c
AD		 6134 if (retval) {
6135 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6136 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6137 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6138 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6139 return;
6140 goto out;
6141 }
4ae196df
AD		 6142
6143 /* this is a message we already processed, do nothing */
6144 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6145 return;
4ae196df 6146
b980ac18 6147 /* until the vf completes a reset it should not be
4ae196df
AD		 6148 * allowed to start any configuration.
6149 */
4ae196df
AD		 6150 if (msgbuf[0] == E1000_VF_RESET) {
6151 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6152 return;
4ae196df
AD		 6153 }
6154
f2ca0dbe 6155 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6156 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6157 return;
6158 retval = -1;
6159 goto out;
4ae196df
AD		 6160 }
6161
6162 switch ((msgbuf[0] & 0xFFFF)) {
6163 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6164 retval = -EINVAL;
6165 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6166 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6167 else
6168 dev_warn(&pdev->dev,
b980ac18
JK		 6169 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6170 vf);
4ae196df 6171 break;
7d5753f0
AD		 6172 case E1000_VF_SET_PROMISC:
6173 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6174 break;
4ae196df
AD		 6175 case E1000_VF_SET_MULTICAST:
6176 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6177 break;
6178 case E1000_VF_SET_LPE:
6179 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6180 break;
6181 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6182 retval = -1;
6183 if (vf_data->pf_vlan)
6184 dev_warn(&pdev->dev,
b980ac18
JK		 6185 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6186 vf);
8151d294
WM		 6187 else
6188 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6189 break;
6190 default:
090b1795 6191 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6192 retval = -1;
6193 break;
6194 }
6195
fef45f4c
AD		 6196 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6197out:
4ae196df
AD		 6198 /* notify the VF of the results of what it sent us */
6199 if (retval)
6200 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6201 else
6202 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6203
4ae196df 6204 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6205}
4ae196df 6206
f2ca0dbe
AD		 6207static void igb_msg_task(struct igb_adapter *adapter)
6208{
6209 struct e1000_hw *hw = &adapter->hw;
6210 u32 vf;
6211
6212 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6213 /* process any reset requests */
6214 if (!igb_check_for_rst(hw, vf))
6215 igb_vf_reset_event(adapter, vf);
6216
6217 /* process any messages pending */
6218 if (!igb_check_for_msg(hw, vf))
6219 igb_rcv_msg_from_vf(adapter, vf);
6220
6221 /* process any acks */
6222 if (!igb_check_for_ack(hw, vf))
6223 igb_rcv_ack_from_vf(adapter, vf);
6224 }
4ae196df
AD		 6225}
6226
68d480c4
AD		 6227/**
6228 * igb_set_uta - Set unicast filter table address
6229 * @adapter: board private structure
6230 *
6231 * The unicast table address is a register array of 32-bit registers.
6232 * The table is meant to be used in a way similar to how the MTA is used
6233 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6234 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6235 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6236 **/
6237static void igb_set_uta(struct igb_adapter *adapter)
6238{
6239 struct e1000_hw *hw = &adapter->hw;
6240 int i;
6241
6242 /* The UTA table only exists on 82576 hardware and newer */
6243 if (hw->mac.type < e1000_82576)
6244 return;
6245
6246 /* we only need to do this if VMDq is enabled */
6247 if (!adapter->vfs_allocated_count)
6248 return;
6249
6250 for (i = 0; i < hw->mac.uta_reg_count; i++)
6251 array_wr32(E1000_UTA, i, ~0);
6252}
6253
9d5c8243 6254/**
b980ac18
JK		 6255 * igb_intr_msi - Interrupt Handler
6256 * @irq: interrupt number
6257 * @data: pointer to a network interface device structure
9d5c8243
AK		 6258 **/
6259static irqreturn_t igb_intr_msi(int irq, void *data)
6260{
047e0030
AD		 6261 struct igb_adapter *adapter = data;
6262 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6263 struct e1000_hw *hw = &adapter->hw;
6264 /* read ICR disables interrupts using IAM */
6265 u32 icr = rd32(E1000_ICR);
6266
047e0030 6267 igb_write_itr(q_vector);
9d5c8243 6268
7f081d40
AD		 6269 if (icr & E1000_ICR_DRSTA)
6270 schedule_work(&adapter->reset_task);
6271
047e0030 6272 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6273 /* HW is reporting DMA is out of sync */
6274 adapter->stats.doosync++;
6275 }
6276
9d5c8243
AK		 6277 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6278 hw->mac.get_link_status = 1;
6279 if (!test_bit(__IGB_DOWN, &adapter->state))
6280 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6281 }
6282
61d7f75f
RC		 6283 if (icr & E1000_ICR_TS)
6284 igb_tsync_interrupt(adapter);
1f6e8178 6285
047e0030 6286 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6287
6288 return IRQ_HANDLED;
6289}
6290
6291/**
b980ac18
JK		 6292 * igb_intr - Legacy Interrupt Handler
6293 * @irq: interrupt number
6294 * @data: pointer to a network interface device structure
9d5c8243
AK		 6295 **/
6296static irqreturn_t igb_intr(int irq, void *data)
6297{
047e0030
AD		 6298 struct igb_adapter *adapter = data;
6299 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6300 struct e1000_hw *hw = &adapter->hw;
6301 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6302 * need for the IMC write
6303 */
9d5c8243 6304 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6305
6306 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6307 * not set, then the adapter didn't send an interrupt
6308 */
9d5c8243
AK		 6309 if (!(icr & E1000_ICR_INT_ASSERTED))
6310 return IRQ_NONE;
6311
0ba82994
AD		 6312 igb_write_itr(q_vector);
6313
7f081d40
AD		 6314 if (icr & E1000_ICR_DRSTA)
6315 schedule_work(&adapter->reset_task);
6316
047e0030 6317 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6318 /* HW is reporting DMA is out of sync */
6319 adapter->stats.doosync++;
6320 }
6321
9d5c8243
AK		 6322 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6323 hw->mac.get_link_status = 1;
6324 /* guard against interrupt when we're going down */
6325 if (!test_bit(__IGB_DOWN, &adapter->state))
6326 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6327 }
6328
61d7f75f
RC		 6329 if (icr & E1000_ICR_TS)
6330 igb_tsync_interrupt(adapter);
1f6e8178 6331
047e0030 6332 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6333
6334 return IRQ_HANDLED;
6335}
6336
c50b52a0 6337static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6338{
047e0030 6339 struct igb_adapter *adapter = q_vector->adapter;
46544258 6340 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6341
0ba82994
AD		 6342 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6343 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6344 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6345 igb_set_itr(q_vector);
46544258 6346 else
047e0030 6347 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6348 }
6349
46544258 6350 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6351 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6352 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6353 else
6354 igb_irq_enable(adapter);
6355 }
9d5c8243
AK		 6356}
6357
46544258 6358/**
b980ac18
JK		 6359 * igb_poll - NAPI Rx polling callback
6360 * @napi: napi polling structure
6361 * @budget: count of how many packets we should handle
46544258
AD		 6362 **/
6363static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6364{
047e0030 6365 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6366 struct igb_q_vector,
6367 napi);
16eb8815 6368 bool clean_complete = true;
32b3e08f 6369 int work_done = 0;
9d5c8243 6370
421e02f0 6371#ifdef CONFIG_IGB_DCA
047e0030
AD		 6372 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6373 igb_update_dca(q_vector);
fe4506b6 6374#endif
0ba82994 6375 if (q_vector->tx.ring)
13fde97a 6376 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6377
32b3e08f
JB		 6378 if (q_vector->rx.ring) {
6379 int cleaned = igb_clean_rx_irq(q_vector, budget);
6380
6381 work_done += cleaned;
6382 clean_complete &= (cleaned < budget);
6383 }
047e0030 6384
16eb8815
AD		 6385 /* If all work not completed, return budget and keep polling */
6386 if (!clean_complete)
6387 return budget;
46544258 6388
9d5c8243 6389 /* If not enough Rx work done, exit the polling mode */
32b3e08f 6390 napi_complete_done(napi, work_done);
16eb8815 6391 igb_ring_irq_enable(q_vector);
9d5c8243 6392
16eb8815 6393 return 0;
9d5c8243 6394}
6d8126f9 6395
9d5c8243 6396/**
b980ac18
JK		 6397 * igb_clean_tx_irq - Reclaim resources after transmit completes
6398 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6399 *
b980ac18 6400 * returns true if ring is completely cleaned
9d5c8243 6401 **/
047e0030 6402static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6403{
047e0030 6404 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6405 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6406 struct igb_tx_buffer *tx_buffer;
f4128785 6407 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6408 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6409 unsigned int budget = q_vector->tx.work_limit;
8542db05 6410 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6411
13fde97a
AD		 6412 if (test_bit(__IGB_DOWN, &adapter->state))
6413 return true;
0e014cb1 6414
06034649 6415 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6416 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6417 i -= tx_ring->count;
9d5c8243 6418
f4128785
AD		 6419 do {
6420 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6421
6422 /* if next_to_watch is not set then there is no work pending */
6423 if (!eop_desc)
6424 break;
13fde97a 6425
f4128785 6426 /* prevent any other reads prior to eop_desc */
70d289bc 6427 read_barrier_depends();
f4128785 6428
13fde97a
AD		 6429 /* if DD is not set pending work has not been completed */
6430 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6431 break;
6432
8542db05
AD		 6433 /* clear next_to_watch to prevent false hangs */
6434 tx_buffer->next_to_watch = NULL;
9d5c8243 6435
ebe42d16
AD		 6436 /* update the statistics for this packet */
6437 total_bytes += tx_buffer->bytecount;
6438 total_packets += tx_buffer->gso_segs;
13fde97a 6439
ebe42d16 6440 /* free the skb */
a81fb049 6441 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6442
ebe42d16
AD		 6443 /* unmap skb header data */
6444 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6445 dma_unmap_addr(tx_buffer, dma),
6446 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6447 DMA_TO_DEVICE);
6448
c9f14bf3
AD		 6449 /* clear tx_buffer data */
6450 tx_buffer->skb = NULL;
6451 dma_unmap_len_set(tx_buffer, len, 0);
6452
ebe42d16
AD		 6453 /* clear last DMA location and unmap remaining buffers */
6454 while (tx_desc != eop_desc) {
13fde97a
AD		 6455 tx_buffer++;
6456 tx_desc++;
9d5c8243 6457 i++;
8542db05
AD		 6458 if (unlikely(!i)) {
6459 i -= tx_ring->count;
06034649 6460 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6461 tx_desc = IGB_TX_DESC(tx_ring, 0);
6462 }
ebe42d16
AD		 6463
6464 /* unmap any remaining paged data */
c9f14bf3 6465 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6466 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6467 dma_unmap_addr(tx_buffer, dma),
6468 dma_unmap_len(tx_buffer, len),
ebe42d16 6469 DMA_TO_DEVICE);
c9f14bf3 6470 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6471 }
6472 }
6473
ebe42d16
AD		 6474 /* move us one more past the eop_desc for start of next pkt */
6475 tx_buffer++;
6476 tx_desc++;
6477 i++;
6478 if (unlikely(!i)) {
6479 i -= tx_ring->count;
6480 tx_buffer = tx_ring->tx_buffer_info;
6481 tx_desc = IGB_TX_DESC(tx_ring, 0);
6482 }
f4128785
AD		 6483
6484 /* issue prefetch for next Tx descriptor */
6485 prefetch(tx_desc);
6486
6487 /* update budget accounting */
6488 budget--;
6489 } while (likely(budget));
0e014cb1 6490
bdbc0631
ED		 6491 netdev_tx_completed_queue(txring_txq(tx_ring),
6492 total_packets, total_bytes);
8542db05 6493 i += tx_ring->count;
9d5c8243 6494 tx_ring->next_to_clean = i;
13fde97a
AD		 6495 u64_stats_update_begin(&tx_ring->tx_syncp);
6496 tx_ring->tx_stats.bytes += total_bytes;
6497 tx_ring->tx_stats.packets += total_packets;
6498 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6499 q_vector->tx.total_bytes += total_bytes;
6500 q_vector->tx.total_packets += total_packets;
9d5c8243 6501
6d095fa8 6502 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6503 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6504
9d5c8243 6505 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6506 * check with the clearing of time_stamp and movement of i
6507 */
6d095fa8 6508 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6509 if (tx_buffer->next_to_watch &&
8542db05 6510 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6511 (adapter->tx_timeout_factor * HZ)) &&
6512 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6513
9d5c8243 6514 /* detected Tx unit hang */
59d71989 6515 dev_err(tx_ring->dev,
9d5c8243 6516 "Detected Tx Unit Hang\n"
2d064c06 6517 " Tx Queue <%d>\n"
9d5c8243
AK		 6518 " TDH <%x>\n"
6519 " TDT <%x>\n"
6520 " next_to_use <%x>\n"
6521 " next_to_clean <%x>\n"
9d5c8243
AK		 6522 "buffer_info[next_to_clean]\n"
6523 " time_stamp <%lx>\n"
8542db05 6524 " next_to_watch <%p>\n"
9d5c8243
AK		 6525 " jiffies <%lx>\n"
6526 " desc.status <%x>\n",
2d064c06 6527 tx_ring->queue_index,
238ac817 6528 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6529 readl(tx_ring->tail),
9d5c8243
AK		 6530 tx_ring->next_to_use,
6531 tx_ring->next_to_clean,
8542db05 6532 tx_buffer->time_stamp,
f4128785 6533 tx_buffer->next_to_watch,
9d5c8243 6534 jiffies,
f4128785 6535 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6536 netif_stop_subqueue(tx_ring->netdev,
6537 tx_ring->queue_index);
6538
6539 /* we are about to reset, no point in enabling stuff */
6540 return true;
9d5c8243
AK		 6541 }
6542 }
13fde97a 6543
21ba6fe1 6544#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6545 if (unlikely(total_packets &&
b980ac18
JK		 6546 netif_carrier_ok(tx_ring->netdev) &&
6547 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6548 /* Make sure that anybody stopping the queue after this
6549 * sees the new next_to_clean.
6550 */
6551 smp_mb();
6552 if (__netif_subqueue_stopped(tx_ring->netdev,
6553 tx_ring->queue_index) &&
6554 !(test_bit(__IGB_DOWN, &adapter->state))) {
6555 netif_wake_subqueue(tx_ring->netdev,
6556 tx_ring->queue_index);
6557
6558 u64_stats_update_begin(&tx_ring->tx_syncp);
6559 tx_ring->tx_stats.restart_queue++;
6560 u64_stats_update_end(&tx_ring->tx_syncp);
6561 }
6562 }
6563
6564 return !!budget;
9d5c8243
AK		 6565}
6566
cbc8e55f 6567/**
b980ac18
JK		 6568 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6569 * @rx_ring: rx descriptor ring to store buffers on
6570 * @old_buff: donor buffer to have page reused
cbc8e55f 6571 *
b980ac18 6572 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6573 **/
6574static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6575 struct igb_rx_buffer *old_buff)
6576{
6577 struct igb_rx_buffer *new_buff;
6578 u16 nta = rx_ring->next_to_alloc;
6579
6580 new_buff = &rx_ring->rx_buffer_info[nta];
6581
6582 /* update, and store next to alloc */
6583 nta++;
6584 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6585
6586 /* transfer page from old buffer to new buffer */
a1f63473 6587 *new_buff = *old_buff;
cbc8e55f
AD		 6588
6589 /* sync the buffer for use by the device */
6590 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6591 old_buff->page_offset,
de78d1f9 6592 IGB_RX_BUFSZ,
cbc8e55f
AD		 6593 DMA_FROM_DEVICE);
6594}
6595
95dd44b4
AD		 6596static inline bool igb_page_is_reserved(struct page *page)
6597{
2f064f34 6598 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
95dd44b4
AD		 6599}
6600
74e238ea
AD		 6601static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6602 struct page *page,
6603 unsigned int truesize)
6604{
6605 /* avoid re-using remote pages */
95dd44b4 6606 if (unlikely(igb_page_is_reserved(page)))
bc16e47f
RG		 6607 return false;
6608
74e238ea
AD		 6609#if (PAGE_SIZE < 8192)
6610 /* if we are only owner of page we can reuse it */
6611 if (unlikely(page_count(page) != 1))
6612 return false;
6613
6614 /* flip page offset to other buffer */
6615 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
74e238ea
AD		 6616#else
6617 /* move offset up to the next cache line */
6618 rx_buffer->page_offset += truesize;
6619
6620 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6621 return false;
74e238ea
AD		 6622#endif
6623
95dd44b4
AD		 6624 /* Even if we own the page, we are not allowed to use atomic_set()
6625 * This would break get_page_unless_zero() users.
6626 */
6627 atomic_inc(&page->_count);
6628
74e238ea
AD		 6629 return true;
6630}
6631
cbc8e55f 6632/**
b980ac18
JK		 6633 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6634 * @rx_ring: rx descriptor ring to transact packets on
6635 * @rx_buffer: buffer containing page to add
6636 * @rx_desc: descriptor containing length of buffer written by hardware
6637 * @skb: sk_buff to place the data into
cbc8e55f 6638 *
b980ac18
JK		 6639 * This function will add the data contained in rx_buffer->page to the skb.
6640 * This is done either through a direct copy if the data in the buffer is
6641 * less than the skb header size, otherwise it will just attach the page as
6642 * a frag to the skb.
cbc8e55f 6643 *
b980ac18
JK		 6644 * The function will then update the page offset if necessary and return
6645 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6646 **/
6647static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6648 struct igb_rx_buffer *rx_buffer,
6649 union e1000_adv_rx_desc *rx_desc,
6650 struct sk_buff *skb)
6651{
6652 struct page *page = rx_buffer->page;
f56e7bba 6653 unsigned char *va = page_address(page) + rx_buffer->page_offset;
cbc8e55f 6654 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6655#if (PAGE_SIZE < 8192)
6656 unsigned int truesize = IGB_RX_BUFSZ;
6657#else
f56e7bba 6658 unsigned int truesize = SKB_DATA_ALIGN(size);
74e238ea 6659#endif
f56e7bba 6660 unsigned int pull_len;
cbc8e55f 6661
f56e7bba
AD		 6662 if (unlikely(skb_is_nonlinear(skb)))
6663 goto add_tail_frag;
cbc8e55f 6664
f56e7bba
AD		 6665 if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
6666 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6667 va += IGB_TS_HDR_LEN;
6668 size -= IGB_TS_HDR_LEN;
6669 }
cbc8e55f 6670
f56e7bba 6671 if (likely(size <= IGB_RX_HDR_LEN)) {
cbc8e55f
AD		 6672 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6673
95dd44b4
AD		 6674 /* page is not reserved, we can reuse buffer as-is */
6675 if (likely(!igb_page_is_reserved(page)))
cbc8e55f
AD		 6676 return true;
6677
6678 /* this page cannot be reused so discard it */
95dd44b4 6679 __free_page(page);
cbc8e55f
AD		 6680 return false;
6681 }
6682
f56e7bba
AD		 6683 /* we need the header to contain the greater of either ETH_HLEN or
6684 * 60 bytes if the skb->len is less than 60 for skb_pad.
6685 */
6686 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
6687
6688 /* align pull length to size of long to optimize memcpy performance */
6689 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
6690
6691 /* update all of the pointers */
6692 va += pull_len;
6693 size -= pull_len;
6694
6695add_tail_frag:
cbc8e55f 6696 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
f56e7bba 6697 (unsigned long)va & ~PAGE_MASK, size, truesize);
cbc8e55f 6698
74e238ea
AD		 6699 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6700}
cbc8e55f 6701
2e334eee
AD		 6702static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6703 union e1000_adv_rx_desc *rx_desc,
6704 struct sk_buff *skb)
6705{
6706 struct igb_rx_buffer *rx_buffer;
6707 struct page *page;
6708
6709 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2e334eee
AD		 6710 page = rx_buffer->page;
6711 prefetchw(page);
6712
6713 if (likely(!skb)) {
6714 void *page_addr = page_address(page) +
6715 rx_buffer->page_offset;
6716
6717 /* prefetch first cache line of first page */
6718 prefetch(page_addr);
6719#if L1_CACHE_BYTES < 128
6720 prefetch(page_addr + L1_CACHE_BYTES);
6721#endif
6722
6723 /* allocate a skb to store the frags */
67fd893e 6724 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
2e334eee
AD		 6725 if (unlikely(!skb)) {
6726 rx_ring->rx_stats.alloc_failed++;
6727 return NULL;
6728 }
6729
b980ac18 6730 /* we will be copying header into skb->data in
2e334eee
AD		 6731 * pskb_may_pull so it is in our interest to prefetch
6732 * it now to avoid a possible cache miss
6733 */
6734 prefetchw(skb->data);
6735 }
6736
6737 /* we are reusing so sync this buffer for CPU use */
6738 dma_sync_single_range_for_cpu(rx_ring->dev,
6739 rx_buffer->dma,
6740 rx_buffer->page_offset,
de78d1f9 6741 IGB_RX_BUFSZ,
2e334eee
AD		 6742 DMA_FROM_DEVICE);
6743
6744 /* pull page into skb */
6745 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6746 /* hand second half of page back to the ring */
6747 igb_reuse_rx_page(rx_ring, rx_buffer);
6748 } else {
6749 /* we are not reusing the buffer so unmap it */
6750 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6751 PAGE_SIZE, DMA_FROM_DEVICE);
6752 }
6753
6754 /* clear contents of rx_buffer */
6755 rx_buffer->page = NULL;
6756
6757 return skb;
6758}
6759
cd392f5c 6760static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6761 union e1000_adv_rx_desc *rx_desc,
6762 struct sk_buff *skb)
9d5c8243 6763{
bc8acf2c 6764 skb_checksum_none_assert(skb);
9d5c8243 6765
294e7d78 6766 /* Ignore Checksum bit is set */
3ceb90fd 6767 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6768 return;
6769
6770 /* Rx checksum disabled via ethtool */
6771 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6772 return;
85ad76b2 6773
9d5c8243 6774 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6775 if (igb_test_staterr(rx_desc,
6776 E1000_RXDEXT_STATERR_TCPE |
6777 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6778 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6779 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6780 * packets, (aka let the stack check the crc32c)
6781 */
866cff06
AD		 6782 if (!((skb->len == 60) &&
6783 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6784 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6785 ring->rx_stats.csum_err++;
12dcd86b
ED		 6786 u64_stats_update_end(&ring->rx_syncp);
6787 }
9d5c8243 6788 /* let the stack verify checksum errors */
9d5c8243
AK		 6789 return;
6790 }
6791 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6792 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6793 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6794 skb->ip_summed = CHECKSUM_UNNECESSARY;
6795
3ceb90fd
AD		 6796 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6797 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6798}
6799
077887c3
AD		 6800static inline void igb_rx_hash(struct igb_ring *ring,
6801 union e1000_adv_rx_desc *rx_desc,
6802 struct sk_buff *skb)
6803{
6804 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6805 skb_set_hash(skb,
6806 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6807 PKT_HASH_TYPE_L3);
077887c3
AD		 6808}
6809
2e334eee 6810/**
b980ac18
JK		 6811 * igb_is_non_eop - process handling of non-EOP buffers
6812 * @rx_ring: Rx ring being processed
6813 * @rx_desc: Rx descriptor for current buffer
6814 * @skb: current socket buffer containing buffer in progress
2e334eee 6815 *
b980ac18
JK		 6816 * This function updates next to clean. If the buffer is an EOP buffer
6817 * this function exits returning false, otherwise it will place the
6818 * sk_buff in the next buffer to be chained and return true indicating
6819 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6820 **/
6821static bool igb_is_non_eop(struct igb_ring *rx_ring,
6822 union e1000_adv_rx_desc *rx_desc)
6823{
6824 u32 ntc = rx_ring->next_to_clean + 1;
6825
6826 /* fetch, update, and store next to clean */
6827 ntc = (ntc < rx_ring->count) ? ntc : 0;
6828 rx_ring->next_to_clean = ntc;
6829
6830 prefetch(IGB_RX_DESC(rx_ring, ntc));
6831
6832 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6833 return false;
6834
6835 return true;
6836}
6837
1a1c225b 6838/**
b980ac18
JK		 6839 * igb_cleanup_headers - Correct corrupted or empty headers
6840 * @rx_ring: rx descriptor ring packet is being transacted on
6841 * @rx_desc: pointer to the EOP Rx descriptor
6842 * @skb: pointer to current skb being fixed
1a1c225b 6843 *
b980ac18
JK		 6844 * Address the case where we are pulling data in on pages only
6845 * and as such no data is present in the skb header.
1a1c225b 6846 *
b980ac18
JK		 6847 * In addition if skb is not at least 60 bytes we need to pad it so that
6848 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6849 *
b980ac18 6850 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6851 **/
6852static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6853 union e1000_adv_rx_desc *rx_desc,
6854 struct sk_buff *skb)
6855{
1a1c225b
AD		 6856 if (unlikely((igb_test_staterr(rx_desc,
6857 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6858 struct net_device *netdev = rx_ring->netdev;
6859 if (!(netdev->features & NETIF_F_RXALL)) {
6860 dev_kfree_skb_any(skb);
6861 return true;
6862 }
6863 }
6864
a94d9e22
AD		 6865 /* if eth_skb_pad returns an error the skb was freed */
6866 if (eth_skb_pad(skb))
6867 return true;
1a1c225b
AD		 6868
6869 return false;
2d94d8ab
AD		 6870}
6871
db2ee5bd 6872/**
b980ac18
JK		 6873 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6874 * @rx_ring: rx descriptor ring packet is being transacted on
6875 * @rx_desc: pointer to the EOP Rx descriptor
6876 * @skb: pointer to current skb being populated
db2ee5bd 6877 *
b980ac18
JK		 6878 * This function checks the ring, descriptor, and packet information in
6879 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6880 * other fields within the skb.
db2ee5bd
AD		 6881 **/
6882static void igb_process_skb_fields(struct igb_ring *rx_ring,
6883 union e1000_adv_rx_desc *rx_desc,
6884 struct sk_buff *skb)
6885{
6886 struct net_device *dev = rx_ring->netdev;
6887
6888 igb_rx_hash(rx_ring, rx_desc, skb);
6889
6890 igb_rx_checksum(rx_ring, rx_desc, skb);
6891
5499a968
JK		 6892 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6893 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6894 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6895
f646968f 6896 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6897 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6898 u16 vid;
9005df38 6899
db2ee5bd
AD		 6900 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6901 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6902 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6903 else
6904 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6905
86a9bad3 6906 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6907 }
6908
6909 skb_record_rx_queue(skb, rx_ring->queue_index);
6910
6911 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6912}
6913
32b3e08f 6914static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6915{
0ba82994 6916 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6917 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6918 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6919 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6920
57ba34c9 6921 while (likely(total_packets < budget)) {
2e334eee 6922 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6923
2e334eee
AD		 6924 /* return some buffers to hardware, one at a time is too slow */
6925 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6926 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6927 cleaned_count = 0;
6928 }
bf36c1a0 6929
2e334eee 6930 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6931
124b74c1 6932 if (!rx_desc->wb.upper.status_error)
2e334eee 6933 break;
9d5c8243 6934
74e238ea
AD		 6935 /* This memory barrier is needed to keep us from reading
6936 * any other fields out of the rx_desc until we know the
124b74c1 6937 * descriptor has been written back
74e238ea 6938 */
124b74c1 6939 dma_rmb();
74e238ea 6940
2e334eee 6941 /* retrieve a buffer from the ring */
f9d40f6a 6942 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6943
2e334eee
AD		 6944 /* exit if we failed to retrieve a buffer */
6945 if (!skb)
6946 break;
1a1c225b 6947
2e334eee 6948 cleaned_count++;
1a1c225b 6949
2e334eee
AD		 6950 /* fetch next buffer in frame if non-eop */
6951 if (igb_is_non_eop(rx_ring, rx_desc))
6952 continue;
1a1c225b
AD		 6953
6954 /* verify the packet layout is correct */
6955 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6956 skb = NULL;
6957 continue;
9d5c8243 6958 }
9d5c8243 6959
db2ee5bd 6960 /* probably a little skewed due to removing CRC */
3ceb90fd 6961 total_bytes += skb->len;
3ceb90fd 6962
db2ee5bd
AD		 6963 /* populate checksum, timestamp, VLAN, and protocol */
6964 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6965
b2cb09b1 6966 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6967
1a1c225b
AD		 6968 /* reset skb pointer */
6969 skb = NULL;
6970
2e334eee
AD		 6971 /* update budget accounting */
6972 total_packets++;
57ba34c9 6973 }
bf36c1a0 6974
1a1c225b
AD		 6975 /* place incomplete frames back on ring for completion */
6976 rx_ring->skb = skb;
6977
12dcd86b 6978 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6979 rx_ring->rx_stats.packets += total_packets;
6980 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6981 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6982 q_vector->rx.total_packets += total_packets;
6983 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6984
6985 if (cleaned_count)
cd392f5c 6986 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6987
32b3e08f 6988 return total_packets;
9d5c8243
AK		 6989}
6990
c023cd88 6991static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6992 struct igb_rx_buffer *bi)
c023cd88
AD		 6993{
6994 struct page *page = bi->page;
cbc8e55f 6995 dma_addr_t dma;
c023cd88 6996
cbc8e55f
AD		 6997 /* since we are recycling buffers we should seldom need to alloc */
6998 if (likely(page))
c023cd88
AD		 6999 return true;
7000
cbc8e55f 7001 /* alloc new page for storage */
42b17f09 7002 page = dev_alloc_page();
cbc8e55f
AD		 7003 if (unlikely(!page)) {
7004 rx_ring->rx_stats.alloc_failed++;
7005 return false;
c023cd88
AD		 7006 }
7007
cbc8e55f
AD		 7008 /* map page for use */
7009 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7010
b980ac18 7011 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7012 * there isn't much point in holding memory we can't use
7013 */
1a1c225b 7014 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7015 __free_page(page);
7016
c023cd88
AD		 7017 rx_ring->rx_stats.alloc_failed++;
7018 return false;
7019 }
7020
1a1c225b 7021 bi->dma = dma;
cbc8e55f
AD		 7022 bi->page = page;
7023 bi->page_offset = 0;
1a1c225b 7024
c023cd88
AD		 7025 return true;
7026}
7027
9d5c8243 7028/**
b980ac18
JK		 7029 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7030 * @adapter: address of board private structure
9d5c8243 7031 **/
cd392f5c 7032void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7033{
9d5c8243 7034 union e1000_adv_rx_desc *rx_desc;
06034649 7035 struct igb_rx_buffer *bi;
c023cd88 7036 u16 i = rx_ring->next_to_use;
9d5c8243 7037
cbc8e55f
AD		 7038 /* nothing to do */
7039 if (!cleaned_count)
7040 return;
7041
60136906 7042 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7043 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7044 i -= rx_ring->count;
9d5c8243 7045
cbc8e55f 7046 do {
1a1c225b 7047 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7048 break;
9d5c8243 7049
b980ac18 7050 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7051 * because each write-back erases this info.
7052 */
f9d40f6a 7053 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7054
c023cd88
AD		 7055 rx_desc++;
7056 bi++;
9d5c8243 7057 i++;
c023cd88 7058 if (unlikely(!i)) {
60136906 7059 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7060 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7061 i -= rx_ring->count;
7062 }
7063
95dd44b4
AD		 7064 /* clear the status bits for the next_to_use descriptor */
7065 rx_desc->wb.upper.status_error = 0;
cbc8e55f
AD		 7066
7067 cleaned_count--;
7068 } while (cleaned_count);
9d5c8243 7069
c023cd88
AD		 7070 i += rx_ring->count;
7071
9d5c8243 7072 if (rx_ring->next_to_use != i) {
cbc8e55f 7073 /* record the next descriptor to use */
9d5c8243 7074 rx_ring->next_to_use = i;
9d5c8243 7075
cbc8e55f
AD		 7076 /* update next to alloc since we have filled the ring */
7077 rx_ring->next_to_alloc = i;
7078
b980ac18 7079 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7080 * know there are new descriptors to fetch. (Only
7081 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7082 * such as IA-64).
7083 */
9d5c8243 7084 wmb();
fce99e34 7085 writel(i, rx_ring->tail);
9d5c8243
AK		 7086 }
7087}
7088
7089/**
7090 * igb_mii_ioctl -
7091 * @netdev:
7092 * @ifreq:
7093 * @cmd:
7094 **/
7095static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7096{
7097 struct igb_adapter *adapter = netdev_priv(netdev);
7098 struct mii_ioctl_data *data = if_mii(ifr);
7099
7100 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7101 return -EOPNOTSUPP;
7102
7103 switch (cmd) {
7104 case SIOCGMIIPHY:
7105 data->phy_id = adapter->hw.phy.addr;
7106 break;
7107 case SIOCGMIIREG:
f5f4cf08 7108 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7109 &data->val_out))
9d5c8243
AK		 7110 return -EIO;
7111 break;
7112 case SIOCSMIIREG:
7113 default:
7114 return -EOPNOTSUPP;
7115 }
7116 return 0;
7117}
7118
7119/**
7120 * igb_ioctl -
7121 * @netdev:
7122 * @ifreq:
7123 * @cmd:
7124 **/
7125static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7126{
7127 switch (cmd) {
7128 case SIOCGMIIPHY:
7129 case SIOCGMIIREG:
7130 case SIOCSMIIREG:
7131 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7132 case SIOCGHWTSTAMP:
7133 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7134 case SIOCSHWTSTAMP:
6ab5f7b2 7135 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7136 default:
7137 return -EOPNOTSUPP;
7138 }
7139}
7140
94826487
TF		 7141void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7142{
7143 struct igb_adapter *adapter = hw->back;
7144
7145 pci_read_config_word(adapter->pdev, reg, value);
7146}
7147
7148void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7149{
7150 struct igb_adapter *adapter = hw->back;
7151
7152 pci_write_config_word(adapter->pdev, reg, *value);
7153}
7154
009bc06e
AD		 7155s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7156{
7157 struct igb_adapter *adapter = hw->back;
009bc06e 7158
23d028cc 7159 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7160 return -E1000_ERR_CONFIG;
7161
009bc06e
AD		 7162 return 0;
7163}
7164
7165s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7166{
7167 struct igb_adapter *adapter = hw->back;
009bc06e 7168
23d028cc 7169 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7170 return -E1000_ERR_CONFIG;
7171
009bc06e
AD		 7172 return 0;
7173}
7174
c8f44aff 7175static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7176{
7177 struct igb_adapter *adapter = netdev_priv(netdev);
7178 struct e1000_hw *hw = &adapter->hw;
7179 u32 ctrl, rctl;
f646968f 7180 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7181
5faf030c 7182 if (enable) {
9d5c8243
AK		 7183 /* enable VLAN tag insert/strip */
7184 ctrl = rd32(E1000_CTRL);
7185 ctrl |= E1000_CTRL_VME;
7186 wr32(E1000_CTRL, ctrl);
7187
51466239 7188 /* Disable CFI check */
9d5c8243 7189 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7190 rctl &= ~E1000_RCTL_CFIEN;
7191 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7192 } else {
7193 /* disable VLAN tag insert/strip */
7194 ctrl = rd32(E1000_CTRL);
7195 ctrl &= ~E1000_CTRL_VME;
7196 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7197 }
7198
e1739522 7199 igb_rlpml_set(adapter);
9d5c8243
AK		 7200}
7201
80d5c368
PM		 7202static int igb_vlan_rx_add_vid(struct net_device *netdev,
7203 __be16 proto, u16 vid)
9d5c8243
AK		 7204{
7205 struct igb_adapter *adapter = netdev_priv(netdev);
7206 struct e1000_hw *hw = &adapter->hw;
4ae196df 7207 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7208
51466239
AD		 7209 /* attempt to add filter to vlvf array */
7210 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7211
51466239
AD		 7212 /* add the filter since PF can receive vlans w/o entry in vlvf */
7213 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7214
7215 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7216
7217 return 0;
9d5c8243
AK		 7218}
7219
80d5c368
PM		 7220static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7221 __be16 proto, u16 vid)
9d5c8243
AK		 7222{
7223 struct igb_adapter *adapter = netdev_priv(netdev);
7224 struct e1000_hw *hw = &adapter->hw;
4ae196df 7225 int pf_id = adapter->vfs_allocated_count;
51466239 7226 s32 err;
9d5c8243 7227
51466239
AD		 7228 /* remove vlan from VLVF table array */
7229 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7230
51466239
AD		 7231 /* if vid was not present in VLVF just remove it from table */
7232 if (err)
4ae196df 7233 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7234
7235 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7236
7237 return 0;
9d5c8243
AK		 7238}
7239
7240static void igb_restore_vlan(struct igb_adapter *adapter)
7241{
b2cb09b1 7242 u16 vid;
9d5c8243 7243
5faf030c
AD		 7244 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7245
b2cb09b1 7246 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7247 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7248}
7249
14ad2513 7250int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7251{
090b1795 7252 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7253 struct e1000_mac_info *mac = &adapter->hw.mac;
7254
7255 mac->autoneg = 0;
7256
14ad2513 7257 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7258 * for the switch() below to work
7259 */
14ad2513
DD		 7260 if ((spd & 1) || (dplx & ~1))
7261 goto err_inval;
7262
f502ef7d
AA		 7263 /* Fiber NIC's only allow 1000 gbps Full duplex
7264 * and 100Mbps Full duplex for 100baseFx sfp
7265 */
7266 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7267 switch (spd + dplx) {
7268 case SPEED_10 + DUPLEX_HALF:
7269 case SPEED_10 + DUPLEX_FULL:
7270 case SPEED_100 + DUPLEX_HALF:
7271 goto err_inval;
7272 default:
7273 break;
7274 }
7275 }
cd2638a8 7276
14ad2513 7277 switch (spd + dplx) {
9d5c8243
AK		 7278 case SPEED_10 + DUPLEX_HALF:
7279 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7280 break;
7281 case SPEED_10 + DUPLEX_FULL:
7282 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7283 break;
7284 case SPEED_100 + DUPLEX_HALF:
7285 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7286 break;
7287 case SPEED_100 + DUPLEX_FULL:
7288 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7289 break;
7290 case SPEED_1000 + DUPLEX_FULL:
7291 mac->autoneg = 1;
7292 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7293 break;
7294 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7295 default:
14ad2513 7296 goto err_inval;
9d5c8243 7297 }
8376dad0
JB		 7298
7299 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7300 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7301
9d5c8243 7302 return 0;
14ad2513
DD		 7303
7304err_inval:
7305 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7306 return -EINVAL;
9d5c8243
AK		 7307}
7308
749ab2cd
YZ		 7309static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7310 bool runtime)
9d5c8243
AK		 7311{
7312 struct net_device *netdev = pci_get_drvdata(pdev);
7313 struct igb_adapter *adapter = netdev_priv(netdev);
7314 struct e1000_hw *hw = &adapter->hw;
2d064c06 7315 u32 ctrl, rctl, status;
749ab2cd 7316 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7317#ifdef CONFIG_PM
7318 int retval = 0;
7319#endif
7320
7321 netif_device_detach(netdev);
7322
a88f10ec 7323 if (netif_running(netdev))
749ab2cd 7324 __igb_close(netdev, true);
a88f10ec 7325
047e0030 7326 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7327
7328#ifdef CONFIG_PM
7329 retval = pci_save_state(pdev);
7330 if (retval)
7331 return retval;
7332#endif
7333
7334 status = rd32(E1000_STATUS);
7335 if (status & E1000_STATUS_LU)
7336 wufc &= ~E1000_WUFC_LNKC;
7337
7338 if (wufc) {
7339 igb_setup_rctl(adapter);
ff41f8dc 7340 igb_set_rx_mode(netdev);
9d5c8243
AK		 7341
7342 /* turn on all-multi mode if wake on multicast is enabled */
7343 if (wufc & E1000_WUFC_MC) {
7344 rctl = rd32(E1000_RCTL);
7345 rctl |= E1000_RCTL_MPE;
7346 wr32(E1000_RCTL, rctl);
7347 }
7348
7349 ctrl = rd32(E1000_CTRL);
7350 /* advertise wake from D3Cold */
7351 #define E1000_CTRL_ADVD3WUC 0x00100000
7352 /* phy power management enable */
7353 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7354 ctrl |= E1000_CTRL_ADVD3WUC;
7355 wr32(E1000_CTRL, ctrl);
7356
9d5c8243 7357 /* Allow time for pending master requests to run */
330a6d6a 7358 igb_disable_pcie_master(hw);
9d5c8243
AK		 7359
7360 wr32(E1000_WUC, E1000_WUC_PME_EN);
7361 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7362 } else {
7363 wr32(E1000_WUC, 0);
7364 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7365 }
7366
3fe7c4c9
RW		 7367 *enable_wake = wufc || adapter->en_mng_pt;
7368 if (!*enable_wake)
88a268c1
NN		 7369 igb_power_down_link(adapter);
7370 else
7371 igb_power_up_link(adapter);
9d5c8243
AK		 7372
7373 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7374 * would have already happened in close and is redundant.
7375 */
9d5c8243
AK		 7376 igb_release_hw_control(adapter);
7377
7378 pci_disable_device(pdev);
7379
9d5c8243
AK		 7380 return 0;
7381}
7382
7383#ifdef CONFIG_PM
d9dd966d 7384#ifdef CONFIG_PM_SLEEP
749ab2cd 7385static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7386{
7387 int retval;
7388 bool wake;
749ab2cd 7389 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7390
749ab2cd 7391 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7392 if (retval)
7393 return retval;
7394
7395 if (wake) {
7396 pci_prepare_to_sleep(pdev);
7397 } else {
7398 pci_wake_from_d3(pdev, false);
7399 pci_set_power_state(pdev, PCI_D3hot);
7400 }
7401
7402 return 0;
7403}
d9dd966d 7404#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7405
749ab2cd 7406static int igb_resume(struct device *dev)
9d5c8243 7407{
749ab2cd 7408 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7409 struct net_device *netdev = pci_get_drvdata(pdev);
7410 struct igb_adapter *adapter = netdev_priv(netdev);
7411 struct e1000_hw *hw = &adapter->hw;
7412 u32 err;
7413
7414 pci_set_power_state(pdev, PCI_D0);
7415 pci_restore_state(pdev);
b94f2d77 7416 pci_save_state(pdev);
42bfd33a 7417
17a402a0
CW		 7418 if (!pci_device_is_present(pdev))
7419 return -ENODEV;
aed5dec3 7420 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7421 if (err) {
7422 dev_err(&pdev->dev,
7423 "igb: Cannot enable PCI device from suspend\n");
7424 return err;
7425 }
7426 pci_set_master(pdev);
7427
7428 pci_enable_wake(pdev, PCI_D3hot, 0);
7429 pci_enable_wake(pdev, PCI_D3cold, 0);
7430
53c7d064 7431 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec 7432 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3eb14ea8 7433 rtnl_unlock();
a88f10ec 7434 return -ENOMEM;
9d5c8243
AK		 7435 }
7436
9d5c8243 7437 igb_reset(adapter);
a8564f03
AD		 7438
7439 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7440 * driver.
7441 */
a8564f03
AD		 7442 igb_get_hw_control(adapter);
7443
9d5c8243
AK		 7444 wr32(E1000_WUS, ~0);
7445
749ab2cd 7446 if (netdev->flags & IFF_UP) {
0c2cc02e 7447 rtnl_lock();
749ab2cd 7448 err = __igb_open(netdev, true);
0c2cc02e 7449 rtnl_unlock();
a88f10ec
AD		 7450 if (err)
7451 return err;
7452 }
9d5c8243
AK		 7453
7454 netif_device_attach(netdev);
749ab2cd
YZ		 7455 return 0;
7456}
7457
749ab2cd
YZ		 7458static int igb_runtime_idle(struct device *dev)
7459{
7460 struct pci_dev *pdev = to_pci_dev(dev);
7461 struct net_device *netdev = pci_get_drvdata(pdev);
7462 struct igb_adapter *adapter = netdev_priv(netdev);
7463
7464 if (!igb_has_link(adapter))
7465 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7466
7467 return -EBUSY;
7468}
7469
7470static int igb_runtime_suspend(struct device *dev)
7471{
7472 struct pci_dev *pdev = to_pci_dev(dev);
7473 int retval;
7474 bool wake;
7475
7476 retval = __igb_shutdown(pdev, &wake, 1);
7477 if (retval)
7478 return retval;
7479
7480 if (wake) {
7481 pci_prepare_to_sleep(pdev);
7482 } else {
7483 pci_wake_from_d3(pdev, false);
7484 pci_set_power_state(pdev, PCI_D3hot);
7485 }
9d5c8243 7486
9d5c8243
AK		 7487 return 0;
7488}
749ab2cd
YZ		 7489
7490static int igb_runtime_resume(struct device *dev)
7491{
7492 return igb_resume(dev);
7493}
d61c81cb 7494#endif /* CONFIG_PM */
9d5c8243
AK		 7495
7496static void igb_shutdown(struct pci_dev *pdev)
7497{
3fe7c4c9
RW		 7498 bool wake;
7499
749ab2cd 7500 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7501
7502 if (system_state == SYSTEM_POWER_OFF) {
7503 pci_wake_from_d3(pdev, wake);
7504 pci_set_power_state(pdev, PCI_D3hot);
7505 }
9d5c8243
AK		 7506}
7507
fa44f2f1
GR		 7508#ifdef CONFIG_PCI_IOV
7509static int igb_sriov_reinit(struct pci_dev *dev)
7510{
7511 struct net_device *netdev = pci_get_drvdata(dev);
7512 struct igb_adapter *adapter = netdev_priv(netdev);
7513 struct pci_dev *pdev = adapter->pdev;
7514
7515 rtnl_lock();
7516
7517 if (netif_running(netdev))
7518 igb_close(netdev);
76252723
SA		 7519 else
7520 igb_reset(adapter);
fa44f2f1
GR		 7521
7522 igb_clear_interrupt_scheme(adapter);
7523
7524 igb_init_queue_configuration(adapter);
7525
7526 if (igb_init_interrupt_scheme(adapter, true)) {
f468adc9 7527 rtnl_unlock();
fa44f2f1
GR		 7528 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7529 return -ENOMEM;
7530 }
7531
7532 if (netif_running(netdev))
7533 igb_open(netdev);
7534
7535 rtnl_unlock();
7536
7537 return 0;
7538}
7539
7540static int igb_pci_disable_sriov(struct pci_dev *dev)
7541{
7542 int err = igb_disable_sriov(dev);
7543
7544 if (!err)
7545 err = igb_sriov_reinit(dev);
7546
7547 return err;
7548}
7549
7550static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7551{
7552 int err = igb_enable_sriov(dev, num_vfs);
7553
7554 if (err)
7555 goto out;
7556
7557 err = igb_sriov_reinit(dev);
7558 if (!err)
7559 return num_vfs;
7560
7561out:
7562 return err;
7563}
7564
7565#endif
7566static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7567{
7568#ifdef CONFIG_PCI_IOV
7569 if (num_vfs == 0)
7570 return igb_pci_disable_sriov(dev);
7571 else
7572 return igb_pci_enable_sriov(dev, num_vfs);
7573#endif
7574 return 0;
7575}
7576
9d5c8243 7577#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7578/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7579 * without having to re-enable interrupts. It's not called while
7580 * the interrupt routine is executing.
7581 */
7582static void igb_netpoll(struct net_device *netdev)
7583{
7584 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7585 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7586 struct igb_q_vector *q_vector;
9d5c8243 7587 int i;
9d5c8243 7588
047e0030 7589 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7590 q_vector = adapter->q_vector[i];
cd14ef54 7591 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7592 wr32(E1000_EIMC, q_vector->eims_value);
7593 else
7594 igb_irq_disable(adapter);
047e0030 7595 napi_schedule(&q_vector->napi);
eebbbdba 7596 }
9d5c8243
AK		 7597}
7598#endif /* CONFIG_NET_POLL_CONTROLLER */
7599
7600/**
b980ac18
JK		 7601 * igb_io_error_detected - called when PCI error is detected
7602 * @pdev: Pointer to PCI device
7603 * @state: The current pci connection state
9d5c8243 7604 *
b980ac18
JK		 7605 * This function is called after a PCI bus error affecting
7606 * this device has been detected.
7607 **/
9d5c8243
AK		 7608static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7609 pci_channel_state_t state)
7610{
7611 struct net_device *netdev = pci_get_drvdata(pdev);
7612 struct igb_adapter *adapter = netdev_priv(netdev);
7613
7614 netif_device_detach(netdev);
7615
59ed6eec
AD		 7616 if (state == pci_channel_io_perm_failure)
7617 return PCI_ERS_RESULT_DISCONNECT;
7618
9d5c8243
AK		 7619 if (netif_running(netdev))
7620 igb_down(adapter);
7621 pci_disable_device(pdev);
7622
7623 /* Request a slot slot reset. */
7624 return PCI_ERS_RESULT_NEED_RESET;
7625}
7626
7627/**
b980ac18
JK		 7628 * igb_io_slot_reset - called after the pci bus has been reset.
7629 * @pdev: Pointer to PCI device
9d5c8243 7630 *
b980ac18
JK		 7631 * Restart the card from scratch, as if from a cold-boot. Implementation
7632 * resembles the first-half of the igb_resume routine.
7633 **/
9d5c8243
AK		 7634static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7635{
7636 struct net_device *netdev = pci_get_drvdata(pdev);
7637 struct igb_adapter *adapter = netdev_priv(netdev);
7638 struct e1000_hw *hw = &adapter->hw;
40a914fa 7639 pci_ers_result_t result;
42bfd33a 7640 int err;
9d5c8243 7641
aed5dec3 7642 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7643 dev_err(&pdev->dev,
7644 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7645 result = PCI_ERS_RESULT_DISCONNECT;
7646 } else {
7647 pci_set_master(pdev);
7648 pci_restore_state(pdev);
b94f2d77 7649 pci_save_state(pdev);
9d5c8243 7650
40a914fa
AD		 7651 pci_enable_wake(pdev, PCI_D3hot, 0);
7652 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7653
40a914fa
AD		 7654 igb_reset(adapter);
7655 wr32(E1000_WUS, ~0);
7656 result = PCI_ERS_RESULT_RECOVERED;
7657 }
9d5c8243 7658
ea943d41
JK		 7659 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7660 if (err) {
b980ac18
JK		 7661 dev_err(&pdev->dev,
7662 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7663 err);
ea943d41
JK		 7664 /* non-fatal, continue */
7665 }
40a914fa
AD		 7666
7667 return result;
9d5c8243
AK		 7668}
7669
7670/**
b980ac18
JK		 7671 * igb_io_resume - called when traffic can start flowing again.
7672 * @pdev: Pointer to PCI device
9d5c8243 7673 *
b980ac18
JK		 7674 * This callback is called when the error recovery driver tells us that
7675 * its OK to resume normal operation. Implementation resembles the
7676 * second-half of the igb_resume routine.
9d5c8243
AK		 7677 */
7678static void igb_io_resume(struct pci_dev *pdev)
7679{
7680 struct net_device *netdev = pci_get_drvdata(pdev);
7681 struct igb_adapter *adapter = netdev_priv(netdev);
7682
9d5c8243
AK		 7683 if (netif_running(netdev)) {
7684 if (igb_up(adapter)) {
7685 dev_err(&pdev->dev, "igb_up failed after reset\n");
7686 return;
7687 }
7688 }
7689
7690 netif_device_attach(netdev);
7691
7692 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7693 * driver.
7694 */
9d5c8243 7695 igb_get_hw_control(adapter);
9d5c8243
AK		 7696}
7697
26ad9178 7698static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7699 u8 qsel)
26ad9178
AD		 7700{
7701 u32 rar_low, rar_high;
7702 struct e1000_hw *hw = &adapter->hw;
7703
7704 /* HW expects these in little endian so we reverse the byte order
7705 * from network order (big endian) to little endian
7706 */
7707 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7708 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7709 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7710
7711 /* Indicate to hardware the Address is Valid. */
7712 rar_high |= E1000_RAH_AV;
7713
7714 if (hw->mac.type == e1000_82575)
7715 rar_high |= E1000_RAH_POOL_1 * qsel;
7716 else
7717 rar_high |= E1000_RAH_POOL_1 << qsel;
7718
7719 wr32(E1000_RAL(index), rar_low);
7720 wrfl();
7721 wr32(E1000_RAH(index), rar_high);
7722 wrfl();
7723}
7724
4ae196df 7725static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7726 int vf, unsigned char *mac_addr)
4ae196df
AD		 7727{
7728 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7729 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7730 * towards the first, as a result a collision should not be possible
7731 */
ff41f8dc 7732 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7733
37680117 7734 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7735
26ad9178 7736 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7737
7738 return 0;
7739}
7740
8151d294
WM		 7741static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7742{
7743 struct igb_adapter *adapter = netdev_priv(netdev);
7744 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7745 return -EINVAL;
7746 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7747 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7748 dev_info(&adapter->pdev->dev,
7749 "Reload the VF driver to make this change effective.");
8151d294 7750 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7751 dev_warn(&adapter->pdev->dev,
7752 "The VF MAC address has been set, but the PF device is not up.\n");
7753 dev_warn(&adapter->pdev->dev,
7754 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7755 }
7756 return igb_set_vf_mac(adapter, vf, mac);
7757}
7758
17dc566c
LL		 7759static int igb_link_mbps(int internal_link_speed)
7760{
7761 switch (internal_link_speed) {
7762 case SPEED_100:
7763 return 100;
7764 case SPEED_1000:
7765 return 1000;
7766 default:
7767 return 0;
7768 }
7769}
7770
7771static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7772 int link_speed)
7773{
7774 int rf_dec, rf_int;
7775 u32 bcnrc_val;
7776
7777 if (tx_rate != 0) {
7778 /* Calculate the rate factor values to set */
7779 rf_int = link_speed / tx_rate;
7780 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7781 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7782 tx_rate;
17dc566c
LL		 7783
7784 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7785 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7786 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7787 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7788 } else {
7789 bcnrc_val = 0;
7790 }
7791
7792 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7793 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7794 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7795 */
7796 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7797 wr32(E1000_RTTBCNRC, bcnrc_val);
7798}
7799
7800static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7801{
7802 int actual_link_speed, i;
7803 bool reset_rate = false;
7804
7805 /* VF TX rate limit was not set or not supported */
7806 if ((adapter->vf_rate_link_speed == 0) ||
7807 (adapter->hw.mac.type != e1000_82576))
7808 return;
7809
7810 actual_link_speed = igb_link_mbps(adapter->link_speed);
7811 if (actual_link_speed != adapter->vf_rate_link_speed) {
7812 reset_rate = true;
7813 adapter->vf_rate_link_speed = 0;
7814 dev_info(&adapter->pdev->dev,
b980ac18 7815 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7816 }
7817
7818 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7819 if (reset_rate)
7820 adapter->vf_data[i].tx_rate = 0;
7821
7822 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7823 adapter->vf_data[i].tx_rate,
7824 actual_link_speed);
17dc566c
LL		 7825 }
7826}
7827
ed616689
SC		 7828static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7829 int min_tx_rate, int max_tx_rate)
8151d294 7830{
17dc566c
LL		 7831 struct igb_adapter *adapter = netdev_priv(netdev);
7832 struct e1000_hw *hw = &adapter->hw;
7833 int actual_link_speed;
7834
7835 if (hw->mac.type != e1000_82576)
7836 return -EOPNOTSUPP;
7837
ed616689
SC		 7838 if (min_tx_rate)
7839 return -EINVAL;
7840
17dc566c
LL		 7841 actual_link_speed = igb_link_mbps(adapter->link_speed);
7842 if ((vf >= adapter->vfs_allocated_count) ||
7843 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7844 (max_tx_rate < 0) ||
7845 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7846 return -EINVAL;
7847
7848 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7849 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7850 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7851
7852 return 0;
8151d294
WM		 7853}
7854
70ea4783
LL		 7855static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7856 bool setting)
7857{
7858 struct igb_adapter *adapter = netdev_priv(netdev);
7859 struct e1000_hw *hw = &adapter->hw;
7860 u32 reg_val, reg_offset;
7861
7862 if (!adapter->vfs_allocated_count)
7863 return -EOPNOTSUPP;
7864
7865 if (vf >= adapter->vfs_allocated_count)
7866 return -EINVAL;
7867
7868 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7869 reg_val = rd32(reg_offset);
7870 if (setting)
7871 reg_val |= ((1 << vf) |
7872 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7873 else
7874 reg_val &= ~((1 << vf) |
7875 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7876 wr32(reg_offset, reg_val);
7877
7878 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7879 return 0;
70ea4783
LL		 7880}
7881
8151d294
WM		 7882static int igb_ndo_get_vf_config(struct net_device *netdev,
7883 int vf, struct ifla_vf_info *ivi)
7884{
7885 struct igb_adapter *adapter = netdev_priv(netdev);
7886 if (vf >= adapter->vfs_allocated_count)
7887 return -EINVAL;
7888 ivi->vf = vf;
7889 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7890 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7891 ivi->min_tx_rate = 0;
8151d294
WM		 7892 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7893 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7894 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7895 return 0;
7896}
7897
4ae196df
AD		 7898static void igb_vmm_control(struct igb_adapter *adapter)
7899{
7900 struct e1000_hw *hw = &adapter->hw;
10d8e907 7901 u32 reg;
4ae196df 7902
52a1dd4d
AD		 7903 switch (hw->mac.type) {
7904 case e1000_82575:
f96a8a0b
CW		 7905 case e1000_i210:
7906 case e1000_i211:
ceb5f13b 7907 case e1000_i354:
52a1dd4d
AD		 7908 default:
7909 /* replication is not supported for 82575 */
4ae196df 7910 return;
52a1dd4d
AD		 7911 case e1000_82576:
7912 /* notify HW that the MAC is adding vlan tags */
7913 reg = rd32(E1000_DTXCTL);
7914 reg |= E1000_DTXCTL_VLAN_ADDED;
7915 wr32(E1000_DTXCTL, reg);
b26141d4 7916 /* Fall through */
52a1dd4d
AD		 7917 case e1000_82580:
7918 /* enable replication vlan tag stripping */
7919 reg = rd32(E1000_RPLOLR);
7920 reg |= E1000_RPLOLR_STRVLAN;
7921 wr32(E1000_RPLOLR, reg);
b26141d4 7922 /* Fall through */
d2ba2ed8
AD		 7923 case e1000_i350:
7924 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7925 break;
7926 }
10d8e907 7927
d4960307
AD		 7928 if (adapter->vfs_allocated_count) {
7929 igb_vmdq_set_loopback_pf(hw, true);
7930 igb_vmdq_set_replication_pf(hw, true);
13800469 7931 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7932 adapter->vfs_allocated_count);
d4960307
AD		 7933 } else {
7934 igb_vmdq_set_loopback_pf(hw, false);
7935 igb_vmdq_set_replication_pf(hw, false);
7936 }
4ae196df
AD		 7937}
7938
b6e0c419
CW		 7939static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7940{
7941 struct e1000_hw *hw = &adapter->hw;
7942 u32 dmac_thr;
7943 u16 hwm;
7944
7945 if (hw->mac.type > e1000_82580) {
7946 if (adapter->flags & IGB_FLAG_DMAC) {
7947 u32 reg;
7948
7949 /* force threshold to 0. */
7950 wr32(E1000_DMCTXTH, 0);
7951
b980ac18 7952 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7953 * than the Rx threshold. Set hwm to PBA - max frame
7954 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7955 */
e8c626e9
MV		 7956 hwm = 64 * pba - adapter->max_frame_size / 16;
7957 if (hwm < 64 * (pba - 6))
7958 hwm = 64 * (pba - 6);
7959 reg = rd32(E1000_FCRTC);
7960 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7961 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7962 & E1000_FCRTC_RTH_COAL_MASK);
7963 wr32(E1000_FCRTC, reg);
7964
b980ac18 7965 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7966 * frame size, capping it at PBA - 10KB.
7967 */
7968 dmac_thr = pba - adapter->max_frame_size / 512;
7969 if (dmac_thr < pba - 10)
7970 dmac_thr = pba - 10;
b6e0c419
CW		 7971 reg = rd32(E1000_DMACR);
7972 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7973 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7974 & E1000_DMACR_DMACTHR_MASK);
7975
7976 /* transition to L0x or L1 if available..*/
7977 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7978
7979 /* watchdog timer= +-1000 usec in 32usec intervals */
7980 reg |= (1000 >> 5);
0c02dd98
MV		 7981
7982 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7983 if (hw->mac.type != e1000_i354)
7984 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7985
b6e0c419
CW		 7986 wr32(E1000_DMACR, reg);
7987
b980ac18 7988 /* no lower threshold to disable
b6e0c419
CW		 7989 * coalescing(smart fifb)-UTRESH=0
7990 */
7991 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7992
7993 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7994
7995 wr32(E1000_DMCTLX, reg);
7996
b980ac18 7997 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7998 * DMA coal
7999 */
8000 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8001 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8002
b980ac18 8003 /* make low power state decision controlled
b6e0c419
CW		 8004 * by DMA coal
8005 */
8006 reg = rd32(E1000_PCIEMISC);
8007 reg &= ~E1000_PCIEMISC_LX_DECISION;
8008 wr32(E1000_PCIEMISC, reg);
8009 } /* endif adapter->dmac is not disabled */
8010 } else if (hw->mac.type == e1000_82580) {
8011 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8012
b6e0c419
CW		 8013 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8014 wr32(E1000_DMACR, 0);
8015 }
8016}
8017
b980ac18
JK		 8018/**
8019 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8020 * @hw: pointer to hardware structure
8021 * @byte_offset: byte offset to read
8022 * @dev_addr: device address
8023 * @data: value read
8024 *
8025 * Performs byte read operation over I2C interface at
8026 * a specified device address.
b980ac18 8027 **/
441fc6fd 8028s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8029 u8 dev_addr, u8 *data)
441fc6fd
CW		 8030{
8031 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8032 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8033 s32 status;
8034 u16 swfw_mask = 0;
8035
8036 if (!this_client)
8037 return E1000_ERR_I2C;
8038
8039 swfw_mask = E1000_SWFW_PHY0_SM;
8040
23d87824 8041 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8042 return E1000_ERR_SWFW_SYNC;
8043
8044 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8045 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8046
8047 if (status < 0)
8048 return E1000_ERR_I2C;
8049 else {
8050 *data = status;
23d87824 8051 return 0;
441fc6fd
CW		 8052 }
8053}
8054
b980ac18
JK		 8055/**
8056 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8057 * @hw: pointer to hardware structure
8058 * @byte_offset: byte offset to write
8059 * @dev_addr: device address
8060 * @data: value to write
8061 *
8062 * Performs byte write operation over I2C interface at
8063 * a specified device address.
b980ac18 8064 **/
441fc6fd 8065s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8066 u8 dev_addr, u8 data)
441fc6fd
CW		 8067{
8068 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8069 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8070 s32 status;
8071 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8072
8073 if (!this_client)
8074 return E1000_ERR_I2C;
8075
23d87824 8076 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8077 return E1000_ERR_SWFW_SYNC;
8078 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8079 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8080
8081 if (status)
8082 return E1000_ERR_I2C;
8083 else
23d87824 8084 return 0;
441fc6fd
CW		 8085
8086}
907b7835
LMV		 8087
8088int igb_reinit_queues(struct igb_adapter *adapter)
8089{
8090 struct net_device *netdev = adapter->netdev;
8091 struct pci_dev *pdev = adapter->pdev;
8092 int err = 0;
8093
8094 if (netif_running(netdev))
8095 igb_close(netdev);
8096
02ef6e1d 8097 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8098
8099 if (igb_init_interrupt_scheme(adapter, true)) {
8100 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8101 return -ENOMEM;
8102 }
8103
8104 if (netif_running(netdev))
8105 err = igb_open(netdev);
8106
8107 return err;
8108}
9d5c8243 8109/* igb_main.c */
Linux kernel - Deliverables
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